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prjxray-db
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Updating info based on "Merge pull request #561 from litghost/add_tilegrid_tool". 

See [Info File](Info.md) for details.

Signed-off-by: Tim 'mithro' Ansell <me@mith.ro>
This commit is contained in:
Tim 'mithro' Ansell 2019-01-25 01:08:59 +00:00
parent b4360202a7
commit 4284e2e09f
20 changed files with 1917 additions and 71 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

54
Info.md
View File

@ -37,20 +37,20 @@ These files are released under the very permissive [CC0 1.0 Universal](COPYING).
# Details
Last updated on Wed Jan 30 05:24:00 UTC 2019 (2019-01-30T05:24:00+00:00).
Last updated on Wed Jan 30 05:34:37 UTC 2019 (2019-01-30T05:34:37+00:00).
Created using [Project X-Ray](https://github.com/SymbiFlow/prjxray) version [v0.0-1602-gf61ccd1](https://github.com/SymbiFlow/prjxray/commit/f61ccd1f2ae1fc2bb4f5a47ac5a97ca3c7a06ec6).
Created using [Project X-Ray](https://github.com/SymbiFlow/prjxray) version [v0.0-1623-gd77c6d8](https://github.com/SymbiFlow/prjxray/commit/d77c6d8d6a47fc880ec09872039909b1f1193d20).
Latest commit was;
```
commit f61ccd1f2ae1fc2bb4f5a47ac5a97ca3c7a06ec6
Merge: 4efea26 9e585ef
commit d77c6d8d6a47fc880ec09872039909b1f1193d20
Merge: b767eaf c444e8a
Author: litghost <537074+litghost@users.noreply.github.com>
Date: Fri Jan 18 07:09:59 2019 -0800
Date: Thu Jan 24 10:51:07 2019 -0800
Merge pull request #549 from litghost/accelerate_post_processing
Merge pull request #561 from litghost/add_tilegrid_tool
Refactor 074 post-processing
Add tilegrid tool
```
@ -59,7 +59,7 @@ Date: Fri Jan 18 07:09:59 2019 -0800
### Settings
Created using following [settings/artix7.sh (sha256: 15398c7d0dd8a20e2b3d586ec845e9b1c2292587e308711eacf4fd31508821d5)](https://github.com/SymbiFlow/prjxray/blob/f61ccd1f2ae1fc2bb4f5a47ac5a97ca3c7a06ec6/settings/artix7.sh)
Created using following [settings/artix7.sh (sha256: 15398c7d0dd8a20e2b3d586ec845e9b1c2292587e308711eacf4fd31508821d5)](https://github.com/SymbiFlow/prjxray/blob/d77c6d8d6a47fc880ec09872039909b1f1193d20/settings/artix7.sh)
```shell
export XRAY_DATABASE="artix7"
export XRAY_PART="xc7a50tfgg484-1"
@ -114,20 +114,24 @@ Results have checksums;
* [`bed3ba955aa33b47eb3f4c218d8619e6e3f7c5b7f0d0de700827d666a54956f7 ./artix7/mask_bram_l.db`](./artix7/mask_bram_l.db)
* [`fca753747fb1d583483e22980c4dae3a2de6451a326d46eab3581ea6f50f5b2d ./artix7/mask_bram_r.block_ram.db`](./artix7/mask_bram_r.block_ram.db)
* [`bed3ba955aa33b47eb3f4c218d8619e6e3f7c5b7f0d0de700827d666a54956f7 ./artix7/mask_bram_r.db`](./artix7/mask_bram_r.db)
* [`97501937512bf87b2ed203fc35a1532e4fa96a0ef0693925a7e32c8405d28b67 ./artix7/mask_clbll_l.db`](./artix7/mask_clbll_l.db)
* [`121d2430c14b7170e91bfe974a8a028af667669764eb69a1cfd703ead54e1da4 ./artix7/mask_clbll_r.db`](./artix7/mask_clbll_r.db)
* [`82693076cf011620e3cb609cc5c8781894cc5071b0c371f6931c8086e250c81a ./artix7/mask_clblm_l.db`](./artix7/mask_clblm_l.db)
* [`9c7daaad1ec1ace4d819ad09a761d7d64afc1b617821d3b059dac4268f94cb46 ./artix7/mask_clblm_r.db`](./artix7/mask_clblm_r.db)
* [`4f37a37c925f92956b6fc010034529a4cc37698ecb7dd263a0fe737ad600cde7 ./artix7/mask_clbll_l.db`](./artix7/mask_clbll_l.db)
* [`4f37a37c925f92956b6fc010034529a4cc37698ecb7dd263a0fe737ad600cde7 ./artix7/mask_clbll_r.db`](./artix7/mask_clbll_r.db)
* [`5c274320294201935a3edccb43eca8e347ca1f0acded71ec388c794877d4b55b ./artix7/mask_clblm_l.db`](./artix7/mask_clblm_l.db)
* [`5c274320294201935a3edccb43eca8e347ca1f0acded71ec388c794877d4b55b ./artix7/mask_clblm_r.db`](./artix7/mask_clblm_r.db)
* [`76d1e0bd4b7ad492cf3fe8698b2b5f46f7dcc5fe446984e5dccae373c63edafd ./artix7/mask_hclk_l.db`](./artix7/mask_hclk_l.db)
* [`76d1e0bd4b7ad492cf3fe8698b2b5f46f7dcc5fe446984e5dccae373c63edafd ./artix7/mask_hclk_r.db`](./artix7/mask_hclk_r.db)
* [`d94e4d13df16da498224f0e94deaa310fbf471b6f9ec0ec8b2308fe62fa2eeaf ./artix7/ppips_bram_int_interface_l.db`](./artix7/ppips_bram_int_interface_l.db)
* [`b48d766ac6f9dd0e21280d3a04dd448ea39016143309c0c7867fc00d730a59ae ./artix7/ppips_bram_int_interface_r.db`](./artix7/ppips_bram_int_interface_r.db)
* [`a0c06db8af6ee09419cabb9659ece27cdaf65c73ed30e0282fff4f540f65fdb3 ./artix7/ppips_bram_l.db`](./artix7/ppips_bram_l.db)
* [`634c43a7b667af29893344a71c338b2dedfa595de58c72922df1829e2154a6eb ./artix7/ppips_bram_r.db`](./artix7/ppips_bram_r.db)
* [`b4ffdb01ca695c7d52f34b88508aef6d596377fcffd7fa5e197212acc4b00e9a ./artix7/ppips_clbll_l.db`](./artix7/ppips_clbll_l.db)
* [`bb75573609f56f082544644ecbb39125d023809340f7a30180cb9df823585009 ./artix7/ppips_clbll_r.db`](./artix7/ppips_clbll_r.db)
* [`a5357b0c018ac9c8c1f8cccf3c36b69f66ffd0e29039dfadb5a829caafd71a73 ./artix7/ppips_clblm_l.db`](./artix7/ppips_clblm_l.db)
* [`15424ecbd5816143def2dcb20fc9cfae5ec4e11a1a5cfc1848e71b2904a1a713 ./artix7/ppips_clblm_r.db`](./artix7/ppips_clblm_r.db)
* [`6d35b568a51f9b6761da2470a71738b2477ef72c16068a529ae8eb52b65bf17a ./artix7/ppips_hclk_l.db`](./artix7/ppips_hclk_l.db)
* [`81e0696179a33bdf8d2279a53b406911a403d50224355e9ad29eccee01a70305 ./artix7/ppips_hclk_r.db`](./artix7/ppips_hclk_r.db)
* [`292b55e44a2c49d9a7fc961ba37761ee8a29e50c790ef9da5e8c0d1c6c142b2f ./artix7/ppips_int_l.db`](./artix7/ppips_int_l.db)
* [`60c352d2d6124ad3260ae0c3c151effa29aaad4c32fa2cee7787bfc43ca6aa89 ./artix7/ppips_int_r.db`](./artix7/ppips_int_r.db)
* [`d300ad4128a192e416a958471013b7554f141fd1f816715828b1e5a87838f18d ./artix7/ppips_int_l.db`](./artix7/ppips_int_l.db)
* [`46564e746b8d9e37bf46a68f2915bd1395efb68508d48d336a4dfb9342105285 ./artix7/ppips_int_r.db`](./artix7/ppips_int_r.db)
* [`63cab7c6cb50b9a86cd6de4ec02cfba93b99ac622684a1196b3d70adb1472fc1 ./artix7/segbits_bram_l.block_ram.db`](./artix7/segbits_bram_l.block_ram.db)
* [`231e0e81ed1ad81e2e2f7a91e5eb32505453a8e6df4ab2e109872497f60a7195 ./artix7/segbits_bram_l.db`](./artix7/segbits_bram_l.db)
* [`6daa967b706d7fc5cdf597ed9f142df8f3003ded2fee3d622d484b21ceda2827 ./artix7/segbits_bram_r.block_ram.db`](./artix7/segbits_bram_r.block_ram.db)
@ -140,8 +144,8 @@ Results have checksums;
* [`718d2d615a8b636bdd102c3cf4e36be11f8f4d835c2a3c70fff7e03e9d95a763 ./artix7/segbits_dsp_r.db`](./artix7/segbits_dsp_r.db)
* [`1c2c7229781a4a1d51bbbdeea76238b10497c043aaadf2a76de783041a201878 ./artix7/segbits_hclk_l.db`](./artix7/segbits_hclk_l.db)
* [`51288ec0be63172fcb2a12a92853150c62a21e894c2d42a2586046c462bf57a9 ./artix7/segbits_hclk_r.db`](./artix7/segbits_hclk_r.db)
* [`8458db29d99b66d3171471302c0df0790c7ce96f1424b830dabe1acad26b31e2 ./artix7/segbits_int_l.db`](./artix7/segbits_int_l.db)
* [`21e905d7125a461233406a951f374b8d17da83ddd298810c7602c8666c0bb88a ./artix7/segbits_int_r.db`](./artix7/segbits_int_r.db)
* [`9bb390b2a3c4d568cd268924d21763196ba1f624d9cd287c641258b845f980aa ./artix7/segbits_int_l.db`](./artix7/segbits_int_l.db)
* [`6a7e04b81043f69652511c4e784a8b112dce3d703b4e97d27ceeff3bec792214 ./artix7/segbits_int_r.db`](./artix7/segbits_int_r.db)
* [`2bc07bf06b86af1985fe1c76da7bd6d858768dd6d9e99344a3c52d490b797cdb ./artix7/settings.sh`](./artix7/settings.sh)
* [`ac6ba9ad814503f0fdc1dabb4292aaccd1a2195f5b348276cfee12aed3d96a70 ./artix7/site_type_BSCAN.json`](./artix7/site_type_BSCAN.json)
* [`64724ba2f8af98df5e1d92e5c2da2e6d5a41eec6580f796405e271dadb4e63be ./artix7/site_type_BUFGCTRL.json`](./artix7/site_type_BUFGCTRL.json)
@ -189,8 +193,8 @@ Results have checksums;
* [`f711f285e16aa11d4827ce8504e9413c8ccf87f9f86d108740738ae6cbb4f388 ./artix7/site_type_XADC.json`](./artix7/site_type_XADC.json)
* [`0bfdad62f04128ca4d469aa18b179cbd3bf78e40c6af50450c9ca85bfffd746f ./artix7/tile_type_BRAM_INT_INTERFACE_L.json`](./artix7/tile_type_BRAM_INT_INTERFACE_L.json)
* [`fd0b3b31118249e66193fa06633a58aa5d86820bed16d3f85497b886d2282845 ./artix7/tile_type_BRAM_INT_INTERFACE_R.json`](./artix7/tile_type_BRAM_INT_INTERFACE_R.json)
* [`23af85ab67092eb90d6b05c3bff539499494eaecb07b5063baa2aa494063a1ec ./artix7/tile_type_BRAM_L.json`](./artix7/tile_type_BRAM_L.json)
* [`4ee74c76ea5a5e3125080179eaa2abed0e86835088ae7d2ec38e0ca36f6851bb ./artix7/tile_type_BRAM_R.json`](./artix7/tile_type_BRAM_R.json)
* [`0872dcafbe45716e7f05f85e6f21fdf13b83f1b01ad425194a3beb91ebba9c45 ./artix7/tile_type_BRAM_L.json`](./artix7/tile_type_BRAM_L.json)
* [`1f6fb30b7a5ea1931caad8efebaaef9e4c0f8c7505912418974d3922d9668ed5 ./artix7/tile_type_BRAM_R.json`](./artix7/tile_type_BRAM_R.json)
* [`29e4879a736ff9d43178ba3887ba47b8f1190464dabf4eef7c8fe8d8d23647c2 ./artix7/tile_type_BRKH_BRAM.json`](./artix7/tile_type_BRKH_BRAM.json)
* [`fccd1abee620b9dc48534d82af9c84d7e4fb9f2fbeaa0d8bbef1ddab5d2d91c5 ./artix7/tile_type_BRKH_B_TERM_INT.json`](./artix7/tile_type_BRKH_B_TERM_INT.json)
* [`1adbede824487b01b77eed4443ff5434c9473a067dae3c620df3ccca800951ac ./artix7/tile_type_BRKH_CLB.json`](./artix7/tile_type_BRKH_CLB.json)
@ -227,14 +231,14 @@ Results have checksums;
* [`9207ebd19f94b6a3a9d8ea08f1fe78dcf592d3b5b5f541694a23d5dc1a9163e3 ./artix7/tile_type_CMT_PMV_L.json`](./artix7/tile_type_CMT_PMV_L.json)
* [`63d8187207a325d174e8d509014200531f3e11236e5064c2675871ca42fbbffa ./artix7/tile_type_CMT_TOP_L_LOWER_B.json`](./artix7/tile_type_CMT_TOP_L_LOWER_B.json)
* [`129c5c28dee6d7cc79263d280a391c07b5db326124ad1e973582643d9eadff3a ./artix7/tile_type_CMT_TOP_L_LOWER_T.json`](./artix7/tile_type_CMT_TOP_L_LOWER_T.json)
* [`3196f3226311d6da93de4941e326367c75d2433dcda15df9d1ca9a361f57b297 ./artix7/tile_type_CMT_TOP_L_UPPER_B.json`](./artix7/tile_type_CMT_TOP_L_UPPER_B.json)
* [`74796039811f8938f5ba648cdf6776631345c63a4460e72c6562f457dd176af9 ./artix7/tile_type_CMT_TOP_L_UPPER_B.json`](./artix7/tile_type_CMT_TOP_L_UPPER_B.json)
* [`e008d249e1f1dafa57e4ac276826c60e24b7fd29ec4e5acafd078c0604631afc ./artix7/tile_type_CMT_TOP_L_UPPER_T.json`](./artix7/tile_type_CMT_TOP_L_UPPER_T.json)
* [`5b45ef7b0d9a366440da629a02330f51b6210652842fe723369e88f31df5d732 ./artix7/tile_type_CMT_TOP_R_LOWER_B.json`](./artix7/tile_type_CMT_TOP_R_LOWER_B.json)
* [`6260182cedf2857372997d8b9a9b3d28504931d1c7ff5176d718dd44935354f0 ./artix7/tile_type_CMT_TOP_R_LOWER_T.json`](./artix7/tile_type_CMT_TOP_R_LOWER_T.json)
* [`1e5e97ee35ee5a8af5d7656618b11cdef2a452b9ac8f2257e1a9fb6070898804 ./artix7/tile_type_CMT_TOP_R_UPPER_B.json`](./artix7/tile_type_CMT_TOP_R_UPPER_B.json)
* [`21e908de40301ce5b6d3a2479a5784c74f7227a1493941a5552845e794bdfa2b ./artix7/tile_type_CMT_TOP_R_UPPER_B.json`](./artix7/tile_type_CMT_TOP_R_UPPER_B.json)
* [`816d810709c3f54a33774c6a9acefe472cac1e5748d306e692524007b699ee35 ./artix7/tile_type_CMT_TOP_R_UPPER_T.json`](./artix7/tile_type_CMT_TOP_R_UPPER_T.json)
* [`d4731d3d594d0f941c9e8565caf1d5fc8b2da870dc7b311e988b2216f15f7707 ./artix7/tile_type_DSP_L.json`](./artix7/tile_type_DSP_L.json)
* [`0bc4bf5df264f500c0117a86ba085ffb2b6d6c910f0e677f538fcb79d70478a8 ./artix7/tile_type_DSP_R.json`](./artix7/tile_type_DSP_R.json)
* [`25fd899484af79547af7cf8cdb73d6c12a35dd007c2ce570fe739f8268327d61 ./artix7/tile_type_DSP_R.json`](./artix7/tile_type_DSP_R.json)
* [`01bb373548f7244412efb0a59b85203b18450d357c809b0c36ceaee46a81f3d1 ./artix7/tile_type_GTP_CHANNEL_0.json`](./artix7/tile_type_GTP_CHANNEL_0.json)
* [`e34491f9e8151c172f330dbddd41ee646dbb526772409174810ca8872df4e6a1 ./artix7/tile_type_GTP_CHANNEL_1.json`](./artix7/tile_type_GTP_CHANNEL_1.json)
* [`fcb1a2ac092a41409be635c1d61585f0e9d40d0ce86014e424ab99f2f50342ea ./artix7/tile_type_GTP_CHANNEL_2.json`](./artix7/tile_type_GTP_CHANNEL_2.json)
@ -253,7 +257,7 @@ Results have checksums;
* [`7897a72ad8df7a9561af0cd339d07b78fda2d8978771ca314edb158eb6bf21d5 ./artix7/tile_type_HCLK_GTX.json`](./artix7/tile_type_HCLK_GTX.json)
* [`6a66fa18fdad81ae738e61f650066415a2adc7d15b15ab87b5080faff3edb9e1 ./artix7/tile_type_HCLK_INT_INTERFACE.json`](./artix7/tile_type_HCLK_INT_INTERFACE.json)
* [`51fbaa9613664a08814f372c5791189ceb855720997334f55e52872cc6d4c46f ./artix7/tile_type_HCLK_IOB.json`](./artix7/tile_type_HCLK_IOB.json)
* [`725ed17a96bdb3d91b1e0abd8b9705ac351c64fe1dd7d82e377009c0d9e0a746 ./artix7/tile_type_HCLK_IOI3.json`](./artix7/tile_type_HCLK_IOI3.json)
* [`5e15b63a15fd7864d838d448599718e5f82e8caafa8fd316eb19374e20c0d89c ./artix7/tile_type_HCLK_IOI3.json`](./artix7/tile_type_HCLK_IOI3.json)
* [`2c39172c06f58c30f92d140c6c7c060777b1b3f397a23b9cf82a41a656da82ef ./artix7/tile_type_HCLK_L.json`](./artix7/tile_type_HCLK_L.json)
* [`4270980b733f54a17a34b5259579fd2e42d38efeeb42518967362c599def37c2 ./artix7/tile_type_HCLK_L_BOT_UTURN.json`](./artix7/tile_type_HCLK_L_BOT_UTURN.json)
* [`782d62d7a78ca8282570a945739057b1801795271764120ff4f20696a36e9354 ./artix7/tile_type_HCLK_R.json`](./artix7/tile_type_HCLK_R.json)
@ -300,7 +304,7 @@ Results have checksums;
* [`04409fb1eb974ee5af7e8115bf16aacfd4bda61094c7c4644cc020762a45f6c8 ./artix7/tile_type_VBRK_EXT.json`](./artix7/tile_type_VBRK_EXT.json)
* [`004efcd7f9e172780ca7b8c379ec329bcfc52f86beaa1d997f41dbef7ac4a242 ./artix7/tile_type_VFRAME.json`](./artix7/tile_type_VFRAME.json)
* [`1604d48580815e26069c2b4909fcc50e8e8f974ad0beb349ced2329c302bb06b ./artix7/tileconn.json`](./artix7/tileconn.json)
* [`c4ca9177e8ecef5e3ce98abe3a33ab63d0585c853ab5b92d6d948e8dee2d3ba0 ./artix7/tilegrid.json`](./artix7/tilegrid.json)
* [`294062cc5a981f002f0b4ab868c2d75f46276d413e9f178df7e7af78cc47e911 ./artix7/tilegrid.json`](./artix7/tilegrid.json)
* [`4c20ee41ea32668919b7d91a7fabe38960e0ee4d5b3b83f1d18102d48895bf1c ./artix7/xc7a35tcpg236-1.json`](./artix7/xc7a35tcpg236-1.json)
* [`ef0724733da87455426a0f833642d96e9d206d047f4eb97072c3093f80c40d7d ./artix7/xc7a35tcpg236-1.yaml`](./artix7/xc7a35tcpg236-1.yaml)
* [`4c20ee41ea32668919b7d91a7fabe38960e0ee4d5b3b83f1d18102d48895bf1c ./artix7/xc7a35tcsg324-1.json`](./artix7/xc7a35tcsg324-1.json)
@ -313,7 +317,7 @@ Results have checksums;
### Settings
Created using following [settings/kintex7.sh (sha256: b15d95afeae26cb0236f2a17b411f0242e4af0f3664d49dda936465ad3fa2b25)](https://github.com/SymbiFlow/prjxray/blob/f61ccd1f2ae1fc2bb4f5a47ac5a97ca3c7a06ec6/settings/kintex7.sh)
Created using following [settings/kintex7.sh (sha256: b15d95afeae26cb0236f2a17b411f0242e4af0f3664d49dda936465ad3fa2b25)](https://github.com/SymbiFlow/prjxray/blob/d77c6d8d6a47fc880ec09872039909b1f1193d20/settings/kintex7.sh)
```shell
export XRAY_DATABASE="kintex7"
export XRAY_PART="xc7k70tfbg676-2"
@ -551,7 +555,7 @@ Results have checksums;
### Settings
Created using following [settings/zynq7.sh (sha256: d956938bea24fcf8e8c7f71480116a9a668fb7be744e34a4e627b31a6b553f4b)](https://github.com/SymbiFlow/prjxray/blob/f61ccd1f2ae1fc2bb4f5a47ac5a97ca3c7a06ec6/settings/zynq7.sh)
Created using following [settings/zynq7.sh (sha256: d956938bea24fcf8e8c7f71480116a9a668fb7be744e34a4e627b31a6b553f4b)](https://github.com/SymbiFlow/prjxray/blob/d77c6d8d6a47fc880ec09872039909b1f1193d20/settings/zynq7.sh)
```shell
export XRAY_DATABASE="zynq7"
export XRAY_PART="xc7z010clg400-1"

7
artix7/mask_clbll_l.db
View File

@ -11,7 +11,9 @@ bit 00_09
bit 00_10
bit 00_11
bit 00_12
bit 00_13
bit 00_14
bit 00_15
bit 00_16
bit 00_17
bit 00_18
@ -48,6 +50,7 @@ bit 00_50
bit 00_51
bit 00_52
bit 00_53
bit 00_54
bit 00_55
bit 00_56
bit 00_57
@ -68,10 +71,13 @@ bit 01_08
bit 01_09
bit 01_10
bit 01_11
bit 01_12
bit 01_13
bit 01_14
bit 01_15
bit 01_16
bit 01_17
bit 01_18
bit 01_19
bit 01_20
bit 01_21
@ -100,6 +106,7 @@ bit 01_45
bit 01_46
bit 01_47
bit 01_48
bit 01_49
bit 01_50
bit 01_51
bit 01_52

10
artix7/mask_clbll_r.db
View File

@ -11,7 +11,9 @@ bit 00_09
bit 00_10
bit 00_11
bit 00_12
bit 00_13
bit 00_14
bit 00_15
bit 00_16
bit 00_17
bit 00_18
@ -37,14 +39,18 @@ bit 00_38
bit 00_39
bit 00_41
bit 00_42
bit 00_43
bit 00_44
bit 00_45
bit 00_46
bit 00_47
bit 00_48
bit 00_49
bit 00_50
bit 00_51
bit 00_52
bit 00_53
bit 00_54
bit 00_55
bit 00_56
bit 00_57
@ -65,10 +71,13 @@ bit 01_08
bit 01_09
bit 01_10
bit 01_11
bit 01_12
bit 01_13
bit 01_14
bit 01_15
bit 01_16
bit 01_17
bit 01_18
bit 01_19
bit 01_20
bit 01_21
@ -97,6 +106,7 @@ bit 01_45
bit 01_46
bit 01_47
bit 01_48
bit 01_49
bit 01_50
bit 01_51
bit 01_52

7
artix7/mask_clblm_l.db
View File

@ -11,7 +11,9 @@ bit 00_09
bit 00_10
bit 00_11
bit 00_12
bit 00_13
bit 00_14
bit 00_15
bit 00_16
bit 00_17
bit 00_18
@ -49,6 +51,7 @@ bit 00_50
bit 00_51
bit 00_52
bit 00_53
bit 00_54
bit 00_55
bit 00_56
bit 00_57
@ -69,10 +72,13 @@ bit 01_08
bit 01_09
bit 01_10
bit 01_11
bit 01_12
bit 01_13
bit 01_14
bit 01_15
bit 01_16
bit 01_17
bit 01_18
bit 01_19
bit 01_20
bit 01_21
@ -102,6 +108,7 @@ bit 01_45
bit 01_46
bit 01_47
bit 01_48
bit 01_49
bit 01_50
bit 01_51
bit 01_52

10
artix7/mask_clblm_r.db
View File

@ -11,7 +11,9 @@ bit 00_09
bit 00_10
bit 00_11
bit 00_12
bit 00_13
bit 00_14
bit 00_15
bit 00_16
bit 00_17
bit 00_18
@ -38,14 +40,18 @@ bit 00_39
bit 00_40
bit 00_41
bit 00_42
bit 00_43
bit 00_44
bit 00_45
bit 00_46
bit 00_47
bit 00_48
bit 00_49
bit 00_50
bit 00_51
bit 00_52
bit 00_53
bit 00_54
bit 00_55
bit 00_56
bit 00_57
@ -66,10 +72,13 @@ bit 01_08
bit 01_09
bit 01_10
bit 01_11
bit 01_12
bit 01_13
bit 01_14
bit 01_15
bit 01_16
bit 01_17
bit 01_18
bit 01_19
bit 01_20
bit 01_21
@ -99,6 +108,7 @@ bit 01_45
bit 01_46
bit 01_47
bit 01_48
bit 01_49
bit 01_50
bit 01_51
bit 01_52

24
artix7/ppips_bram_int_interface_l.db Normal file
View File

@ -0,0 +1,24 @@
BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L0.INT_INTERFACE_LOGIC_OUTS_L_B0 always
BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L1.INT_INTERFACE_LOGIC_OUTS_L_B1 always
BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L2.INT_INTERFACE_LOGIC_OUTS_L_B2 always
BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L3.INT_INTERFACE_LOGIC_OUTS_L_B3 always
BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L4.INT_INTERFACE_LOGIC_OUTS_L_B4 always
BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L5.INT_INTERFACE_LOGIC_OUTS_L_B5 always
BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L6.INT_INTERFACE_LOGIC_OUTS_L_B6 always
BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L7.INT_INTERFACE_LOGIC_OUTS_L_B7 always
BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L8.INT_INTERFACE_LOGIC_OUTS_L_B8 always
BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L9.INT_INTERFACE_LOGIC_OUTS_L_B9 always
BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L10.INT_INTERFACE_LOGIC_OUTS_L_B10 always
BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L11.INT_INTERFACE_LOGIC_OUTS_L_B11 always
BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L12.INT_INTERFACE_LOGIC_OUTS_L_B12 always
BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L13.INT_INTERFACE_LOGIC_OUTS_L_B13 always
BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L14.INT_INTERFACE_LOGIC_OUTS_L_B14 always
BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L15.INT_INTERFACE_LOGIC_OUTS_L_B15 always
BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L16.INT_INTERFACE_LOGIC_OUTS_L_B16 always
BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L17.INT_INTERFACE_LOGIC_OUTS_L_B17 always
BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L18.INT_INTERFACE_LOGIC_OUTS_L_B18 always
BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L19.INT_INTERFACE_LOGIC_OUTS_L_B19 always
BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L20.INT_INTERFACE_LOGIC_OUTS_L_B20 always
BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L21.INT_INTERFACE_LOGIC_OUTS_L_B21 always
BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L22.INT_INTERFACE_LOGIC_OUTS_L_B22 always
BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L23.INT_INTERFACE_LOGIC_OUTS_L_B23 always

24
artix7/ppips_bram_int_interface_r.db Normal file
View File

@ -0,0 +1,24 @@
BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS0.INT_INTERFACE_LOGIC_OUTS_B0 always
BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS1.INT_INTERFACE_LOGIC_OUTS_B1 always
BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS2.INT_INTERFACE_LOGIC_OUTS_B2 always
BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS3.INT_INTERFACE_LOGIC_OUTS_B3 always
BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS4.INT_INTERFACE_LOGIC_OUTS_B4 always
BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS5.INT_INTERFACE_LOGIC_OUTS_B5 always
BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS6.INT_INTERFACE_LOGIC_OUTS_B6 always
BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS7.INT_INTERFACE_LOGIC_OUTS_B7 always
BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS8.INT_INTERFACE_LOGIC_OUTS_B8 always
BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS9.INT_INTERFACE_LOGIC_OUTS_B9 always
BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS10.INT_INTERFACE_LOGIC_OUTS_B10 always
BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS11.INT_INTERFACE_LOGIC_OUTS_B11 always
BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS12.INT_INTERFACE_LOGIC_OUTS_B12 always
BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS13.INT_INTERFACE_LOGIC_OUTS_B13 always
BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS14.INT_INTERFACE_LOGIC_OUTS_B14 always
BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS15.INT_INTERFACE_LOGIC_OUTS_B15 always
BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS16.INT_INTERFACE_LOGIC_OUTS_B16 always
BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS17.INT_INTERFACE_LOGIC_OUTS_B17 always
BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS18.INT_INTERFACE_LOGIC_OUTS_B18 always
BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS19.INT_INTERFACE_LOGIC_OUTS_B19 always
BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS20.INT_INTERFACE_LOGIC_OUTS_B20 always
BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS21.INT_INTERFACE_LOGIC_OUTS_B21 always
BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS22.INT_INTERFACE_LOGIC_OUTS_B22 always
BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS23.INT_INTERFACE_LOGIC_OUTS_B23 always

590
artix7/ppips_bram_l.db Normal file
View File

@ -0,0 +1,590 @@
BRAM_L.BRAM_CASCOUT_ADDRARDADDRU0.BRAM_ADDRARDADDRU0 always
BRAM_L.BRAM_CASCOUT_ADDRARDADDRU1.BRAM_ADDRARDADDRU1 always
BRAM_L.BRAM_CASCOUT_ADDRARDADDRU2.BRAM_ADDRARDADDRU2 always
BRAM_L.BRAM_CASCOUT_ADDRARDADDRU3.BRAM_ADDRARDADDRU3 always
BRAM_L.BRAM_CASCOUT_ADDRARDADDRU4.BRAM_ADDRARDADDRU4 always
BRAM_L.BRAM_CASCOUT_ADDRARDADDRU5.BRAM_ADDRARDADDRU5 always
BRAM_L.BRAM_CASCOUT_ADDRARDADDRU6.BRAM_ADDRARDADDRU6 always
BRAM_L.BRAM_CASCOUT_ADDRARDADDRU7.BRAM_ADDRARDADDRU7 always
BRAM_L.BRAM_CASCOUT_ADDRARDADDRU8.BRAM_ADDRARDADDRU8 always
BRAM_L.BRAM_CASCOUT_ADDRARDADDRU9.BRAM_ADDRARDADDRU9 always
BRAM_L.BRAM_CASCOUT_ADDRARDADDRU10.BRAM_ADDRARDADDRU10 always
BRAM_L.BRAM_CASCOUT_ADDRARDADDRU11.BRAM_ADDRARDADDRU11 always
BRAM_L.BRAM_CASCOUT_ADDRARDADDRU12.BRAM_ADDRARDADDRU12 always
BRAM_L.BRAM_CASCOUT_ADDRARDADDRU13.BRAM_ADDRARDADDRU13 always
BRAM_L.BRAM_CASCOUT_ADDRARDADDRU14.BRAM_ADDRARDADDRU14 always
BRAM_L.BRAM_CASCOUT_ADDRBWRADDRU0.BRAM_ADDRBWRADDRU0 always
BRAM_L.BRAM_CASCOUT_ADDRBWRADDRU1.BRAM_ADDRBWRADDRU1 always
BRAM_L.BRAM_CASCOUT_ADDRBWRADDRU2.BRAM_ADDRBWRADDRU2 always
BRAM_L.BRAM_CASCOUT_ADDRBWRADDRU3.BRAM_ADDRBWRADDRU3 always
BRAM_L.BRAM_CASCOUT_ADDRBWRADDRU4.BRAM_ADDRBWRADDRU4 always
BRAM_L.BRAM_CASCOUT_ADDRBWRADDRU5.BRAM_ADDRBWRADDRU5 always
BRAM_L.BRAM_CASCOUT_ADDRBWRADDRU6.BRAM_ADDRBWRADDRU6 always
BRAM_L.BRAM_CASCOUT_ADDRBWRADDRU7.BRAM_ADDRBWRADDRU7 always
BRAM_L.BRAM_CASCOUT_ADDRBWRADDRU8.BRAM_ADDRBWRADDRU8 always
BRAM_L.BRAM_CASCOUT_ADDRBWRADDRU9.BRAM_ADDRBWRADDRU9 always
BRAM_L.BRAM_CASCOUT_ADDRBWRADDRU10.BRAM_ADDRBWRADDRU10 always
BRAM_L.BRAM_CASCOUT_ADDRBWRADDRU11.BRAM_ADDRBWRADDRU11 always
BRAM_L.BRAM_CASCOUT_ADDRBWRADDRU12.BRAM_ADDRBWRADDRU12 always
BRAM_L.BRAM_CASCOUT_ADDRBWRADDRU13.BRAM_ADDRBWRADDRU13 always
BRAM_L.BRAM_CASCOUT_ADDRBWRADDRU14.BRAM_ADDRBWRADDRU14 always
BRAM_L.BRAM_IMUX_ADDRARDADDRL0.BRAM_IMUX17_1 always
BRAM_L.BRAM_IMUX_ADDRARDADDRL1.BRAM_IMUX18_1 always
BRAM_L.BRAM_IMUX_ADDRARDADDRL2.BRAM_IMUX19_1 always
BRAM_L.BRAM_IMUX_ADDRARDADDRL3.BRAM_IMUX18_3 always
BRAM_L.BRAM_IMUX_ADDRARDADDRL4.BRAM_IMUX21_1 always
BRAM_L.BRAM_IMUX_ADDRARDADDRL5.BRAM_IMUX20_3 always
BRAM_L.BRAM_IMUX_ADDRARDADDRL6.BRAM_IMUX16_3 always
BRAM_L.BRAM_IMUX_ADDRARDADDRL7.BRAM_IMUX17_3 always
BRAM_L.BRAM_IMUX_ADDRARDADDRL8.BRAM_IMUX20_1 always
BRAM_L.BRAM_IMUX_ADDRARDADDRL9.BRAM_IMUX19_3 always
BRAM_L.BRAM_IMUX_ADDRARDADDRL10.BRAM_IMUX20_2 always
BRAM_L.BRAM_IMUX_ADDRARDADDRL11.BRAM_IMUX22_1 always
BRAM_L.BRAM_IMUX_ADDRARDADDRL12.BRAM_IMUX21_3 always
BRAM_L.BRAM_IMUX_ADDRARDADDRL13.BRAM_IMUX23_1 always
BRAM_L.BRAM_IMUX_ADDRARDADDRL14.BRAM_IMUX22_3 always
BRAM_L.BRAM_IMUX_ADDRARDADDRL15.BRAM_IMUX31_3 always
BRAM_L.BRAM_IMUX_ADDRARDADDRU0.BRAM_IMUX9_1 always
BRAM_L.BRAM_IMUX_ADDRARDADDRU1.BRAM_IMUX10_1 always
BRAM_L.BRAM_IMUX_ADDRARDADDRU2.BRAM_IMUX11_1 always
BRAM_L.BRAM_IMUX_ADDRARDADDRU3.BRAM_IMUX10_3 always
BRAM_L.BRAM_IMUX_ADDRARDADDRU4.BRAM_IMUX13_1 always
BRAM_L.BRAM_IMUX_ADDRARDADDRU5.BRAM_IMUX12_3 always
BRAM_L.BRAM_IMUX_ADDRARDADDRU6.BRAM_IMUX8_3 always
BRAM_L.BRAM_IMUX_ADDRARDADDRU7.BRAM_IMUX9_3 always
BRAM_L.BRAM_IMUX_ADDRARDADDRU8.BRAM_IMUX12_1 always
BRAM_L.BRAM_IMUX_ADDRARDADDRU9.BRAM_IMUX11_3 always
BRAM_L.BRAM_IMUX_ADDRARDADDRU10.BRAM_IMUX12_2 always
BRAM_L.BRAM_IMUX_ADDRARDADDRU11.BRAM_IMUX14_1 always
BRAM_L.BRAM_IMUX_ADDRARDADDRU12.BRAM_IMUX13_3 always
BRAM_L.BRAM_IMUX_ADDRARDADDRU13.BRAM_IMUX15_1 always
BRAM_L.BRAM_IMUX_ADDRARDADDRU14.BRAM_IMUX14_3 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRL0.BRAM_IMUX33_1 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRL1.BRAM_IMUX34_1 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRL2.BRAM_IMUX35_1 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRL3.BRAM_IMUX34_3 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRL4.BRAM_IMUX37_1 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRL5.BRAM_IMUX36_3 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRL6.BRAM_IMUX32_3 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRL7.BRAM_IMUX33_3 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRL8.BRAM_IMUX36_1 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRL9.BRAM_IMUX35_3 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRL10.BRAM_IMUX36_2 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRL11.BRAM_IMUX38_1 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRL12.BRAM_IMUX37_3 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRL13.BRAM_IMUX39_1 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRL14.BRAM_IMUX38_3 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRL15.BRAM_IMUX39_3 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRU0.BRAM_IMUX25_1 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRU1.BRAM_IMUX26_1 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRU2.BRAM_IMUX27_1 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRU3.BRAM_IMUX26_3 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRU4.BRAM_IMUX29_1 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRU5.BRAM_IMUX28_3 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRU6.BRAM_IMUX24_3 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRU7.BRAM_IMUX25_3 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRU8.BRAM_IMUX28_1 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRU9.BRAM_IMUX27_3 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRU10.BRAM_IMUX28_2 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRU11.BRAM_IMUX30_1 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRU12.BRAM_IMUX29_3 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRU13.BRAM_IMUX31_1 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRU14.BRAM_IMUX30_3 always
BRAM_L.BRAM_LOGIC_OUTS_B9_2.BRAM_FIFO36_SBITERR always
BRAM_L.BRAM_LOGIC_OUTS_B10_2.BRAM_FIFO36_ECCPARITY4 always
BRAM_L.BRAM_LOGIC_OUTS_B11_0.BRAM_FIFO36_TSTOUT4 always
BRAM_L.BRAM_LOGIC_OUTS_B11_1.BRAM_FIFO36_TSTOUT3 always
BRAM_L.BRAM_LOGIC_OUTS_B11_3.BRAM_FIFO36_ECCPARITY7 always
BRAM_L.BRAM_LOGIC_OUTS_B11_4.BRAM_FIFO36_TSTOUT2 always
BRAM_L.BRAM_LOGIC_OUTS_B12_3.BRAM_FIFO36_ECCPARITY1 always
BRAM_L.BRAM_LOGIC_OUTS_B13_2.BRAM_FIFO36_ECCPARITY2 always
BRAM_L.BRAM_LOGIC_OUTS_B16_2.BRAM_FIFO36_DBITERR always
BRAM_L.BRAM_LOGIC_OUTS_B18_0.BRAM_FIFO36_TSTOUT1 always
BRAM_L.BRAM_LOGIC_OUTS_B18_1.BRAM_FIFO36_TSTOUT0 always
BRAM_L.BRAM_LOGIC_OUTS_B18_3.BRAM_FIFO36_ECCPARITY0 always
BRAM_L.BRAM_LOGIC_OUTS_B19_2.BRAM_FIFO36_ECCPARITY3 always
BRAM_L.BRAM_LOGIC_OUTS_B20_2.BRAM_FIFO36_ECCPARITY5 always
BRAM_L.BRAM_LOGIC_OUTS_B21_3.BRAM_FIFO36_ECCPARITY6 always
BRAM_L.BRAM_LOGIC_OUTS_B21_4.BRAM_FIFO36_RDCOUNT12 always
BRAM_L.BRAM_LOGIC_OUTS_B23_4.BRAM_FIFO36_WRCOUNT12 always
BRAM_L.BRAM_UTURN_ADDRARDADDRL0.BRAM_ADDRARDADDRL0 always
BRAM_L.BRAM_UTURN_ADDRARDADDRL1.BRAM_ADDRARDADDRL1 always
BRAM_L.BRAM_UTURN_ADDRARDADDRL2.BRAM_ADDRARDADDRL2 always
BRAM_L.BRAM_UTURN_ADDRARDADDRL3.BRAM_ADDRARDADDRL3 always
BRAM_L.BRAM_UTURN_ADDRARDADDRL4.BRAM_ADDRARDADDRL4 always
BRAM_L.BRAM_UTURN_ADDRARDADDRL5.BRAM_ADDRARDADDRL5 always
BRAM_L.BRAM_UTURN_ADDRARDADDRL6.BRAM_ADDRARDADDRL6 always
BRAM_L.BRAM_UTURN_ADDRARDADDRL7.BRAM_ADDRARDADDRL7 always
BRAM_L.BRAM_UTURN_ADDRARDADDRL8.BRAM_ADDRARDADDRL8 always
BRAM_L.BRAM_UTURN_ADDRARDADDRL9.BRAM_ADDRARDADDRL9 always
BRAM_L.BRAM_UTURN_ADDRARDADDRL10.BRAM_ADDRARDADDRL10 always
BRAM_L.BRAM_UTURN_ADDRARDADDRL11.BRAM_ADDRARDADDRL11 always
BRAM_L.BRAM_UTURN_ADDRARDADDRL12.BRAM_ADDRARDADDRL12 always
BRAM_L.BRAM_UTURN_ADDRARDADDRL13.BRAM_ADDRARDADDRL13 always
BRAM_L.BRAM_UTURN_ADDRARDADDRL14.BRAM_ADDRARDADDRL14 always
BRAM_L.BRAM_UTURN_ADDRARDADDRL15.BRAM_IMUX_ADDRARDADDRL15 always
BRAM_L.BRAM_UTURN_ADDRARDADDRU0.BRAM_ADDRARDADDRU0 always
BRAM_L.BRAM_UTURN_ADDRARDADDRU1.BRAM_ADDRARDADDRU1 always
BRAM_L.BRAM_UTURN_ADDRARDADDRU2.BRAM_ADDRARDADDRU2 always
BRAM_L.BRAM_UTURN_ADDRARDADDRU3.BRAM_ADDRARDADDRU3 always
BRAM_L.BRAM_UTURN_ADDRARDADDRU4.BRAM_ADDRARDADDRU4 always
BRAM_L.BRAM_UTURN_ADDRARDADDRU5.BRAM_ADDRARDADDRU5 always
BRAM_L.BRAM_UTURN_ADDRARDADDRU6.BRAM_ADDRARDADDRU6 always
BRAM_L.BRAM_UTURN_ADDRARDADDRU7.BRAM_ADDRARDADDRU7 always
BRAM_L.BRAM_UTURN_ADDRARDADDRU8.BRAM_ADDRARDADDRU8 always
BRAM_L.BRAM_UTURN_ADDRARDADDRU9.BRAM_ADDRARDADDRU9 always
BRAM_L.BRAM_UTURN_ADDRARDADDRU10.BRAM_ADDRARDADDRU10 always
BRAM_L.BRAM_UTURN_ADDRARDADDRU11.BRAM_ADDRARDADDRU11 always
BRAM_L.BRAM_UTURN_ADDRARDADDRU12.BRAM_ADDRARDADDRU12 always
BRAM_L.BRAM_UTURN_ADDRARDADDRU13.BRAM_ADDRARDADDRU13 always
BRAM_L.BRAM_UTURN_ADDRARDADDRU14.BRAM_ADDRARDADDRU14 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRL0.BRAM_ADDRBWRADDRL0 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRL1.BRAM_ADDRBWRADDRL1 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRL2.BRAM_ADDRBWRADDRL2 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRL3.BRAM_ADDRBWRADDRL3 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRL4.BRAM_ADDRBWRADDRL4 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRL5.BRAM_ADDRBWRADDRL5 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRL6.BRAM_ADDRBWRADDRL6 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRL7.BRAM_ADDRBWRADDRL7 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRL8.BRAM_ADDRBWRADDRL8 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRL9.BRAM_ADDRBWRADDRL9 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRL10.BRAM_ADDRBWRADDRL10 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRL11.BRAM_ADDRBWRADDRL11 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRL12.BRAM_ADDRBWRADDRL12 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRL13.BRAM_ADDRBWRADDRL13 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRL14.BRAM_ADDRBWRADDRL14 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRL15.BRAM_IMUX_ADDRBWRADDRL15 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRU0.BRAM_ADDRBWRADDRU0 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRU1.BRAM_ADDRBWRADDRU1 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRU2.BRAM_ADDRBWRADDRU2 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRU3.BRAM_ADDRBWRADDRU3 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRU4.BRAM_ADDRBWRADDRU4 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRU5.BRAM_ADDRBWRADDRU5 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRU6.BRAM_ADDRBWRADDRU6 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRU7.BRAM_ADDRBWRADDRU7 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRU8.BRAM_ADDRBWRADDRU8 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRU9.BRAM_ADDRBWRADDRU9 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRU10.BRAM_ADDRBWRADDRU10 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRU11.BRAM_ADDRBWRADDRU11 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRU12.BRAM_ADDRBWRADDRU12 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRU13.BRAM_ADDRBWRADDRU13 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRU14.BRAM_ADDRBWRADDRU14 always
BRAM_L.BRAM_FIFO18_CLKARDCLK.BRAM_CLK0_3 always
BRAM_L.BRAM_FIFO18_CLKBWRCLK.BRAM_CLK0_1 always
BRAM_L.BRAM_FIFO18_ENARDEN.BRAM_IMUX18_2 always
BRAM_L.BRAM_FIFO18_ENBWREN.BRAM_IMUX34_2 always
BRAM_L.BRAM_FIFO18_REGCEAREGCE.BRAM_IMUX19_2 always
BRAM_L.BRAM_FIFO18_REGCEB.BRAM_IMUX35_2 always
BRAM_L.BRAM_FIFO18_REGCLKARDRCLK.BRAM_CLK0_4 always
BRAM_L.BRAM_FIFO18_REGCLKB.BRAM_CLK0_0 always
BRAM_L.BRAM_FIFO18_RSTRAMARSTRAM.BRAM_CTRL0_3 always
BRAM_L.BRAM_FIFO18_RSTRAMB.BRAM_CTRL0_1 always
BRAM_L.BRAM_FIFO18_RSTREGARSTREG.BRAM_CTRL0_4 always
BRAM_L.BRAM_FIFO18_RSTREGB.BRAM_CTRL0_0 always
BRAM_L.BRAM_FIFO18_ADDRARDADDR0.BRAM_ADDRARDADDRL1 always
BRAM_L.BRAM_FIFO18_ADDRARDADDR1.BRAM_ADDRARDADDRL2 always
BRAM_L.BRAM_FIFO18_ADDRARDADDR2.BRAM_ADDRARDADDRL3 always
BRAM_L.BRAM_FIFO18_ADDRARDADDR3.BRAM_ADDRARDADDRL4 always
BRAM_L.BRAM_FIFO18_ADDRARDADDR4.BRAM_ADDRARDADDRL5 always
BRAM_L.BRAM_FIFO18_ADDRARDADDR5.BRAM_ADDRARDADDRL6 always
BRAM_L.BRAM_FIFO18_ADDRARDADDR6.BRAM_ADDRARDADDRL7 always
BRAM_L.BRAM_FIFO18_ADDRARDADDR7.BRAM_ADDRARDADDRL8 always
BRAM_L.BRAM_FIFO18_ADDRARDADDR8.BRAM_ADDRARDADDRL9 always
BRAM_L.BRAM_FIFO18_ADDRARDADDR9.BRAM_ADDRARDADDRL10 always
BRAM_L.BRAM_FIFO18_ADDRARDADDR10.BRAM_ADDRARDADDRL11 always
BRAM_L.BRAM_FIFO18_ADDRARDADDR11.BRAM_ADDRARDADDRL12 always
BRAM_L.BRAM_FIFO18_ADDRARDADDR12.BRAM_ADDRARDADDRL13 always
BRAM_L.BRAM_FIFO18_ADDRARDADDR13.BRAM_ADDRARDADDRL14 always
BRAM_L.BRAM_FIFO18_ADDRATIEHIGH0.BRAM_ADDRARDADDRL0 always
BRAM_L.BRAM_FIFO18_ADDRATIEHIGH1.BRAM_IMUX_ADDRARDADDRL15 always
BRAM_L.BRAM_FIFO18_ADDRBTIEHIGH0.BRAM_ADDRBWRADDRL0 always
BRAM_L.BRAM_FIFO18_ADDRBTIEHIGH1.BRAM_IMUX_ADDRBWRADDRL15 always
BRAM_L.BRAM_FIFO18_ADDRBWRADDR0.BRAM_ADDRBWRADDRL1 always
BRAM_L.BRAM_FIFO18_ADDRBWRADDR1.BRAM_ADDRBWRADDRL2 always
BRAM_L.BRAM_FIFO18_ADDRBWRADDR2.BRAM_ADDRBWRADDRL3 always
BRAM_L.BRAM_FIFO18_ADDRBWRADDR3.BRAM_ADDRBWRADDRL4 always
BRAM_L.BRAM_FIFO18_ADDRBWRADDR4.BRAM_ADDRBWRADDRL5 always
BRAM_L.BRAM_FIFO18_ADDRBWRADDR5.BRAM_ADDRBWRADDRL6 always
BRAM_L.BRAM_FIFO18_ADDRBWRADDR6.BRAM_ADDRBWRADDRL7 always
BRAM_L.BRAM_FIFO18_ADDRBWRADDR7.BRAM_ADDRBWRADDRL8 always
BRAM_L.BRAM_FIFO18_ADDRBWRADDR8.BRAM_ADDRBWRADDRL9 always
BRAM_L.BRAM_FIFO18_ADDRBWRADDR9.BRAM_ADDRBWRADDRL10 always
BRAM_L.BRAM_FIFO18_ADDRBWRADDR10.BRAM_ADDRBWRADDRL11 always
BRAM_L.BRAM_FIFO18_ADDRBWRADDR11.BRAM_ADDRBWRADDRL12 always
BRAM_L.BRAM_FIFO18_ADDRBWRADDR12.BRAM_ADDRBWRADDRL13 always
BRAM_L.BRAM_FIFO18_ADDRBWRADDR13.BRAM_ADDRBWRADDRL14 always
BRAM_L.BRAM_FIFO18_DIADI0.BRAM_IMUX16_1 always
BRAM_L.BRAM_FIFO18_DIADI1.BRAM_IMUX26_0 always
BRAM_L.BRAM_FIFO18_DIADI2.BRAM_IMUX28_0 always
BRAM_L.BRAM_FIFO18_DIADI3.BRAM_IMUX30_0 always
BRAM_L.BRAM_FIFO18_DIADI4.BRAM_IMUX41_1 always
BRAM_L.BRAM_FIFO18_DIADI5.BRAM_IMUX43_1 always
BRAM_L.BRAM_FIFO18_DIADI6.BRAM_IMUX45_1 always
BRAM_L.BRAM_FIFO18_DIADI7.BRAM_IMUX40_2 always
BRAM_L.BRAM_FIFO18_DIADI8.BRAM_IMUX25_0 always
BRAM_L.BRAM_FIFO18_DIADI9.BRAM_IMUX27_0 always
BRAM_L.BRAM_FIFO18_DIADI10.BRAM_IMUX29_0 always
BRAM_L.BRAM_FIFO18_DIADI11.BRAM_IMUX31_0 always
BRAM_L.BRAM_FIFO18_DIADI12.BRAM_IMUX42_1 always
BRAM_L.BRAM_FIFO18_DIADI13.BRAM_IMUX44_1 always
BRAM_L.BRAM_FIFO18_DIADI14.BRAM_IMUX46_1 always
BRAM_L.BRAM_FIFO18_DIADI15.BRAM_IMUX41_2 always
BRAM_L.BRAM_FIFO18_DIBDI0.BRAM_IMUX32_1 always
BRAM_L.BRAM_FIFO18_DIBDI1.BRAM_IMUX34_0 always
BRAM_L.BRAM_FIFO18_DIBDI2.BRAM_IMUX36_0 always
BRAM_L.BRAM_FIFO18_DIBDI3.BRAM_IMUX38_0 always
BRAM_L.BRAM_FIFO18_DIBDI4.BRAM_IMUX2_1 always
BRAM_L.BRAM_FIFO18_DIBDI5.BRAM_IMUX4_1 always
BRAM_L.BRAM_FIFO18_DIBDI6.BRAM_IMUX6_1 always
BRAM_L.BRAM_FIFO18_DIBDI7.BRAM_IMUX1_2 always
BRAM_L.BRAM_FIFO18_DIBDI8.BRAM_IMUX33_0 always
BRAM_L.BRAM_FIFO18_DIBDI9.BRAM_IMUX35_0 always
BRAM_L.BRAM_FIFO18_DIBDI10.BRAM_IMUX37_0 always
BRAM_L.BRAM_FIFO18_DIBDI11.BRAM_IMUX39_0 always
BRAM_L.BRAM_FIFO18_DIBDI12.BRAM_IMUX3_1 always
BRAM_L.BRAM_FIFO18_DIBDI13.BRAM_IMUX5_1 always
BRAM_L.BRAM_FIFO18_DIBDI14.BRAM_IMUX7_1 always
BRAM_L.BRAM_FIFO18_DIBDI15.BRAM_IMUX2_2 always
BRAM_L.BRAM_FIFO18_DIPADIP0.BRAM_IMUX3_2 always
BRAM_L.BRAM_FIFO18_DIPADIP1.BRAM_IMUX40_1 always
BRAM_L.BRAM_FIFO18_DIPBDIP0.BRAM_IMUX4_2 always
BRAM_L.BRAM_FIFO18_DIPBDIP1.BRAM_IMUX1_1 always
BRAM_L.BRAM_FIFO18_WEA0.BRAM_IMUX16_2 always
BRAM_L.BRAM_FIFO18_WEA1.BRAM_IMUX32_2 always
BRAM_L.BRAM_FIFO18_WEA2.BRAM_IMUX17_2 always
BRAM_L.BRAM_FIFO18_WEA3.BRAM_IMUX33_2 always
BRAM_L.BRAM_FIFO18_WEBWE0.BRAM_IMUX5_2 always
BRAM_L.BRAM_FIFO18_WEBWE1.BRAM_IMUX21_2 always
BRAM_L.BRAM_FIFO18_WEBWE2.BRAM_IMUX37_2 always
BRAM_L.BRAM_FIFO18_WEBWE3.BRAM_BYP3_2 always
BRAM_L.BRAM_FIFO18_WEBWE4.BRAM_IMUX6_2 always
BRAM_L.BRAM_FIFO18_WEBWE5.BRAM_IMUX22_2 always
BRAM_L.BRAM_FIFO18_WEBWE6.BRAM_IMUX38_2 always
BRAM_L.BRAM_FIFO18_WEBWE7.BRAM_BYP6_2 always
BRAM_L.BRAM_FIFO36_CASCADEOUTA_1.BRAM_FIFO36_CASCADEOUTA always
BRAM_L.BRAM_FIFO36_CASCADEOUTB_1.BRAM_FIFO36_CASCADEOUTB always
BRAM_L.BRAM_FIFO36_CLKARDCLKL.BRAM_CLK0_3 always
BRAM_L.BRAM_FIFO36_CLKARDCLKU.BRAM_CLK1_3 always
BRAM_L.BRAM_FIFO36_CLKBWRCLKL.BRAM_CLK0_1 always
BRAM_L.BRAM_FIFO36_CLKBWRCLKU.BRAM_CLK1_1 always
BRAM_L.BRAM_FIFO36_ENARDENL.BRAM_IMUX18_2 always
BRAM_L.BRAM_FIFO36_ENARDENU.BRAM_IMUX10_2 always
BRAM_L.BRAM_FIFO36_ENBWRENL.BRAM_IMUX34_2 always
BRAM_L.BRAM_FIFO36_ENBWRENU.BRAM_IMUX26_2 always
BRAM_L.BRAM_FIFO36_INJECTDBITERR.BRAM_IMUX31_2 always
BRAM_L.BRAM_FIFO36_INJECTSBITERR.BRAM_IMUX39_2 always
BRAM_L.BRAM_FIFO36_REGCEAREGCEL.BRAM_IMUX19_2 always
BRAM_L.BRAM_FIFO36_REGCEAREGCEU.BRAM_IMUX11_2 always
BRAM_L.BRAM_FIFO36_REGCEBL.BRAM_IMUX35_2 always
BRAM_L.BRAM_FIFO36_REGCEBU.BRAM_IMUX27_2 always
BRAM_L.BRAM_FIFO36_REGCLKARDRCLKL.BRAM_CLK0_4 always
BRAM_L.BRAM_FIFO36_REGCLKARDRCLKU.BRAM_CLK1_4 always
BRAM_L.BRAM_FIFO36_REGCLKBL.BRAM_CLK0_0 always
BRAM_L.BRAM_FIFO36_REGCLKBU.BRAM_CLK1_0 always
BRAM_L.BRAM_FIFO36_RSTRAMARSTRAMLRST.BRAM_CTRL0_3 always
BRAM_L.BRAM_FIFO36_RSTRAMARSTRAMU.BRAM_CTRL1_3 always
BRAM_L.BRAM_FIFO36_RSTRAMBL.BRAM_CTRL0_1 always
BRAM_L.BRAM_FIFO36_RSTRAMBU.BRAM_CTRL1_1 always
BRAM_L.BRAM_FIFO36_RSTREGARSTREGL.BRAM_CTRL0_4 always
BRAM_L.BRAM_FIFO36_RSTREGARSTREGU.BRAM_CTRL1_4 always
BRAM_L.BRAM_FIFO36_RSTREGBL.BRAM_CTRL0_0 always
BRAM_L.BRAM_FIFO36_RSTREGBU.BRAM_CTRL1_0 always
BRAM_L.BRAM_FIFO36_TSTBRAMRST.BRAM_IMUX0_0 always
BRAM_L.BRAM_FIFO36_TSTFLAGIN.BRAM_IMUX5_0 always
BRAM_L.BRAM_FIFO36_TSTOFF.BRAM_IMUX4_0 always
BRAM_L.BRAM_FIFO36_TSTRDCNTOFF.BRAM_IMUX2_0 always
BRAM_L.BRAM_FIFO36_TSTWRCNTOFF.BRAM_IMUX3_0 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRL0.BRAM_ADDRARDADDRL0 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRL1.BRAM_ADDRARDADDRL1 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRL2.BRAM_ADDRARDADDRL2 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRL3.BRAM_ADDRARDADDRL3 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRL4.BRAM_ADDRARDADDRL4 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRL5.BRAM_ADDRARDADDRL5 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRL6.BRAM_ADDRARDADDRL6 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRL7.BRAM_ADDRARDADDRL7 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRL8.BRAM_ADDRARDADDRL8 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRL9.BRAM_ADDRARDADDRL9 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRL10.BRAM_ADDRARDADDRL10 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRL11.BRAM_ADDRARDADDRL11 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRL12.BRAM_ADDRARDADDRL12 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRL13.BRAM_ADDRARDADDRL13 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRL14.BRAM_ADDRARDADDRL14 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRL15.BRAM_IMUX_ADDRARDADDRL15 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRU0.BRAM_ADDRARDADDRU0 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRU1.BRAM_ADDRARDADDRU1 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRU2.BRAM_ADDRARDADDRU2 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRU3.BRAM_ADDRARDADDRU3 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRU4.BRAM_ADDRARDADDRU4 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRU5.BRAM_ADDRARDADDRU5 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRU6.BRAM_ADDRARDADDRU6 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRU7.BRAM_ADDRARDADDRU7 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRU8.BRAM_ADDRARDADDRU8 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRU9.BRAM_ADDRARDADDRU9 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRU10.BRAM_ADDRARDADDRU10 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRU11.BRAM_ADDRARDADDRU11 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRU12.BRAM_ADDRARDADDRU12 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRU13.BRAM_ADDRARDADDRU13 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRU14.BRAM_ADDRARDADDRU14 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRL0.BRAM_ADDRBWRADDRL0 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRL1.BRAM_ADDRBWRADDRL1 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRL2.BRAM_ADDRBWRADDRL2 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRL3.BRAM_ADDRBWRADDRL3 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRL4.BRAM_ADDRBWRADDRL4 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRL5.BRAM_ADDRBWRADDRL5 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRL6.BRAM_ADDRBWRADDRL6 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRL7.BRAM_ADDRBWRADDRL7 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRL8.BRAM_ADDRBWRADDRL8 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRL9.BRAM_ADDRBWRADDRL9 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRL10.BRAM_ADDRBWRADDRL10 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRL11.BRAM_ADDRBWRADDRL11 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRL12.BRAM_ADDRBWRADDRL12 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRL13.BRAM_ADDRBWRADDRL13 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRL14.BRAM_ADDRBWRADDRL14 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRL15.BRAM_IMUX_ADDRBWRADDRL15 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRU0.BRAM_ADDRBWRADDRU0 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRU1.BRAM_ADDRBWRADDRU1 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRU2.BRAM_ADDRBWRADDRU2 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRU3.BRAM_ADDRBWRADDRU3 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRU4.BRAM_ADDRBWRADDRU4 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRU5.BRAM_ADDRBWRADDRU5 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRU6.BRAM_ADDRBWRADDRU6 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRU7.BRAM_ADDRBWRADDRU7 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRU8.BRAM_ADDRBWRADDRU8 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRU9.BRAM_ADDRBWRADDRU9 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRU10.BRAM_ADDRBWRADDRU10 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRU11.BRAM_ADDRBWRADDRU11 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRU12.BRAM_ADDRBWRADDRU12 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRU13.BRAM_ADDRBWRADDRU13 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRU14.BRAM_ADDRBWRADDRU14 always
BRAM_L.BRAM_FIFO36_DIADIL0.BRAM_IMUX16_1 always
BRAM_L.BRAM_FIFO36_DIADIL1.BRAM_IMUX26_0 always
BRAM_L.BRAM_FIFO36_DIADIL2.BRAM_IMUX28_0 always
BRAM_L.BRAM_FIFO36_DIADIL3.BRAM_IMUX30_0 always
BRAM_L.BRAM_FIFO36_DIADIL4.BRAM_IMUX41_1 always
BRAM_L.BRAM_FIFO36_DIADIL5.BRAM_IMUX43_1 always
BRAM_L.BRAM_FIFO36_DIADIL6.BRAM_IMUX45_1 always
BRAM_L.BRAM_FIFO36_DIADIL7.BRAM_IMUX40_2 always
BRAM_L.BRAM_FIFO36_DIADIL8.BRAM_IMUX25_0 always
BRAM_L.BRAM_FIFO36_DIADIL9.BRAM_IMUX27_0 always
BRAM_L.BRAM_FIFO36_DIADIL10.BRAM_IMUX29_0 always
BRAM_L.BRAM_FIFO36_DIADIL11.BRAM_IMUX31_0 always
BRAM_L.BRAM_FIFO36_DIADIL12.BRAM_IMUX42_1 always
BRAM_L.BRAM_FIFO36_DIADIL13.BRAM_IMUX44_1 always
BRAM_L.BRAM_FIFO36_DIADIL14.BRAM_IMUX46_1 always
BRAM_L.BRAM_FIFO36_DIADIL15.BRAM_IMUX41_2 always
BRAM_L.BRAM_FIFO36_DIADIU0.BRAM_IMUX8_1 always
BRAM_L.BRAM_FIFO36_DIADIU1.BRAM_IMUX40_3 always
BRAM_L.BRAM_FIFO36_DIADIU2.BRAM_IMUX42_3 always
BRAM_L.BRAM_FIFO36_DIADIU3.BRAM_IMUX44_3 always
BRAM_L.BRAM_FIFO36_DIADIU4.BRAM_IMUX8_4 always
BRAM_L.BRAM_FIFO36_DIADIU5.BRAM_IMUX10_4 always
BRAM_L.BRAM_FIFO36_DIADIU6.BRAM_IMUX12_4 always
BRAM_L.BRAM_FIFO36_DIADIU7.BRAM_IMUX14_4 always
BRAM_L.BRAM_FIFO36_DIADIU8.BRAM_IMUX15_2 always
BRAM_L.BRAM_FIFO36_DIADIU9.BRAM_IMUX41_3 always
BRAM_L.BRAM_FIFO36_DIADIU10.BRAM_IMUX43_3 always
BRAM_L.BRAM_FIFO36_DIADIU11.BRAM_IMUX45_3 always
BRAM_L.BRAM_FIFO36_DIADIU12.BRAM_IMUX9_4 always
BRAM_L.BRAM_FIFO36_DIADIU13.BRAM_IMUX11_4 always
BRAM_L.BRAM_FIFO36_DIADIU14.BRAM_IMUX13_4 always
BRAM_L.BRAM_FIFO36_DIADIU15.BRAM_IMUX15_4 always
BRAM_L.BRAM_FIFO36_DIBDIL0.BRAM_IMUX32_1 always
BRAM_L.BRAM_FIFO36_DIBDIL1.BRAM_IMUX34_0 always
BRAM_L.BRAM_FIFO36_DIBDIL2.BRAM_IMUX36_0 always
BRAM_L.BRAM_FIFO36_DIBDIL3.BRAM_IMUX38_0 always
BRAM_L.BRAM_FIFO36_DIBDIL4.BRAM_IMUX2_1 always
BRAM_L.BRAM_FIFO36_DIBDIL5.BRAM_IMUX4_1 always
BRAM_L.BRAM_FIFO36_DIBDIL6.BRAM_IMUX6_1 always
BRAM_L.BRAM_FIFO36_DIBDIL7.BRAM_IMUX1_2 always
BRAM_L.BRAM_FIFO36_DIBDIL8.BRAM_IMUX33_0 always
BRAM_L.BRAM_FIFO36_DIBDIL9.BRAM_IMUX35_0 always
BRAM_L.BRAM_FIFO36_DIBDIL10.BRAM_IMUX37_0 always
BRAM_L.BRAM_FIFO36_DIBDIL11.BRAM_IMUX39_0 always
BRAM_L.BRAM_FIFO36_DIBDIL12.BRAM_IMUX3_1 always
BRAM_L.BRAM_FIFO36_DIBDIL13.BRAM_IMUX5_1 always
BRAM_L.BRAM_FIFO36_DIBDIL14.BRAM_IMUX7_1 always
BRAM_L.BRAM_FIFO36_DIBDIL15.BRAM_IMUX2_2 always
BRAM_L.BRAM_FIFO36_DIBDIU0.BRAM_IMUX24_1 always
BRAM_L.BRAM_FIFO36_DIBDIU1.BRAM_IMUX1_3 always
BRAM_L.BRAM_FIFO36_DIBDIU2.BRAM_IMUX3_3 always
BRAM_L.BRAM_FIFO36_DIBDIU3.BRAM_IMUX5_3 always
BRAM_L.BRAM_FIFO36_DIBDIU4.BRAM_IMUX16_4 always
BRAM_L.BRAM_FIFO36_DIBDIU5.BRAM_IMUX18_4 always
BRAM_L.BRAM_FIFO36_DIBDIU6.BRAM_IMUX20_4 always
BRAM_L.BRAM_FIFO36_DIBDIU7.BRAM_IMUX22_4 always
BRAM_L.BRAM_FIFO36_DIBDIU8.BRAM_IMUX23_2 always
BRAM_L.BRAM_FIFO36_DIBDIU9.BRAM_IMUX2_3 always
BRAM_L.BRAM_FIFO36_DIBDIU10.BRAM_IMUX4_3 always
BRAM_L.BRAM_FIFO36_DIBDIU11.BRAM_IMUX6_3 always
BRAM_L.BRAM_FIFO36_DIBDIU12.BRAM_IMUX17_4 always
BRAM_L.BRAM_FIFO36_DIBDIU13.BRAM_IMUX19_4 always
BRAM_L.BRAM_FIFO36_DIBDIU14.BRAM_IMUX21_4 always
BRAM_L.BRAM_FIFO36_DIBDIU15.BRAM_IMUX23_4 always
BRAM_L.BRAM_FIFO36_DIPADIPL0.BRAM_IMUX3_2 always
BRAM_L.BRAM_FIFO36_DIPADIPL1.BRAM_IMUX40_1 always
BRAM_L.BRAM_FIFO36_DIPADIPU0.BRAM_IMUX42_2 always
BRAM_L.BRAM_FIFO36_DIPADIPU1.BRAM_IMUX15_3 always
BRAM_L.BRAM_FIFO36_DIPBDIPL0.BRAM_IMUX4_2 always
BRAM_L.BRAM_FIFO36_DIPBDIPL1.BRAM_IMUX1_1 always
BRAM_L.BRAM_FIFO36_DIPBDIPU0.BRAM_IMUX43_2 always
BRAM_L.BRAM_FIFO36_DIPBDIPU1.BRAM_IMUX23_3 always
BRAM_L.BRAM_FIFO36_TSTCNT0.BRAM_IMUX10_0 always
BRAM_L.BRAM_FIFO36_TSTCNT1.BRAM_IMUX11_0 always
BRAM_L.BRAM_FIFO36_TSTCNT2.BRAM_IMUX12_0 always
BRAM_L.BRAM_FIFO36_TSTCNT3.BRAM_IMUX13_0 always
BRAM_L.BRAM_FIFO36_TSTCNT4.BRAM_IMUX14_0 always
BRAM_L.BRAM_FIFO36_TSTCNT5.BRAM_IMUX15_0 always
BRAM_L.BRAM_FIFO36_TSTCNT6.BRAM_IMUX24_4 always
BRAM_L.BRAM_FIFO36_TSTCNT7.BRAM_IMUX25_4 always
BRAM_L.BRAM_FIFO36_TSTCNT8.BRAM_IMUX26_4 always
BRAM_L.BRAM_FIFO36_TSTCNT9.BRAM_IMUX27_4 always
BRAM_L.BRAM_FIFO36_TSTCNT10.BRAM_IMUX28_4 always
BRAM_L.BRAM_FIFO36_TSTCNT11.BRAM_IMUX29_4 always
BRAM_L.BRAM_FIFO36_TSTCNT12.BRAM_IMUX30_4 always
BRAM_L.BRAM_FIFO36_TSTIN0.BRAM_IMUX5_4 always
BRAM_L.BRAM_FIFO36_TSTIN1.BRAM_IMUX16_0 always
BRAM_L.BRAM_FIFO36_TSTIN2.BRAM_IMUX4_4 always
BRAM_L.BRAM_FIFO36_TSTIN3.BRAM_IMUX8_0 always
BRAM_L.BRAM_FIFO36_TSTIN4.BRAM_IMUX41_0 always
BRAM_L.BRAM_FIFO36_TSTRDOS0.BRAM_IMUX18_0 always
BRAM_L.BRAM_FIFO36_TSTRDOS1.BRAM_IMUX19_0 always
BRAM_L.BRAM_FIFO36_TSTRDOS2.BRAM_IMUX20_0 always
BRAM_L.BRAM_FIFO36_TSTRDOS3.BRAM_IMUX21_0 always
BRAM_L.BRAM_FIFO36_TSTRDOS4.BRAM_IMUX22_0 always
BRAM_L.BRAM_FIFO36_TSTRDOS5.BRAM_IMUX23_0 always
BRAM_L.BRAM_FIFO36_TSTRDOS6.BRAM_IMUX32_4 always
BRAM_L.BRAM_FIFO36_TSTRDOS7.BRAM_IMUX33_4 always
BRAM_L.BRAM_FIFO36_TSTRDOS8.BRAM_IMUX34_4 always
BRAM_L.BRAM_FIFO36_TSTRDOS9.BRAM_IMUX35_4 always
BRAM_L.BRAM_FIFO36_TSTRDOS10.BRAM_IMUX36_4 always
BRAM_L.BRAM_FIFO36_TSTRDOS11.BRAM_IMUX37_4 always
BRAM_L.BRAM_FIFO36_TSTRDOS12.BRAM_IMUX38_4 always
BRAM_L.BRAM_FIFO36_TSTWROS0.BRAM_IMUX42_0 always
BRAM_L.BRAM_FIFO36_TSTWROS1.BRAM_IMUX43_0 always
BRAM_L.BRAM_FIFO36_TSTWROS2.BRAM_IMUX44_0 always
BRAM_L.BRAM_FIFO36_TSTWROS3.BRAM_IMUX45_0 always
BRAM_L.BRAM_FIFO36_TSTWROS4.BRAM_IMUX46_0 always
BRAM_L.BRAM_FIFO36_TSTWROS5.BRAM_IMUX47_0 always
BRAM_L.BRAM_FIFO36_TSTWROS6.BRAM_IMUX40_4 always
BRAM_L.BRAM_FIFO36_TSTWROS7.BRAM_IMUX41_4 always
BRAM_L.BRAM_FIFO36_TSTWROS8.BRAM_IMUX42_4 always
BRAM_L.BRAM_FIFO36_TSTWROS9.BRAM_IMUX43_4 always
BRAM_L.BRAM_FIFO36_TSTWROS10.BRAM_IMUX44_4 always
BRAM_L.BRAM_FIFO36_TSTWROS11.BRAM_IMUX45_4 always
BRAM_L.BRAM_FIFO36_TSTWROS12.BRAM_IMUX46_4 always
BRAM_L.BRAM_FIFO36_WEAL0.BRAM_IMUX16_2 always
BRAM_L.BRAM_FIFO36_WEAL1.BRAM_IMUX32_2 always
BRAM_L.BRAM_FIFO36_WEAL2.BRAM_IMUX17_2 always
BRAM_L.BRAM_FIFO36_WEAL3.BRAM_IMUX33_2 always
BRAM_L.BRAM_FIFO36_WEAU0.BRAM_IMUX8_2 always
BRAM_L.BRAM_FIFO36_WEAU1.BRAM_IMUX24_2 always
BRAM_L.BRAM_FIFO36_WEAU2.BRAM_IMUX9_2 always
BRAM_L.BRAM_FIFO36_WEAU3.BRAM_IMUX25_2 always
BRAM_L.BRAM_FIFO36_WEBWEL0.BRAM_IMUX5_2 always
BRAM_L.BRAM_FIFO36_WEBWEL1.BRAM_IMUX21_2 always
BRAM_L.BRAM_FIFO36_WEBWEL2.BRAM_IMUX37_2 always
BRAM_L.BRAM_FIFO36_WEBWEL3.BRAM_BYP3_2 always
BRAM_L.BRAM_FIFO36_WEBWEL4.BRAM_IMUX6_2 always
BRAM_L.BRAM_FIFO36_WEBWEL5.BRAM_IMUX22_2 always
BRAM_L.BRAM_FIFO36_WEBWEL6.BRAM_IMUX38_2 always
BRAM_L.BRAM_FIFO36_WEBWEL7.BRAM_BYP6_2 always
BRAM_L.BRAM_FIFO36_WEBWEU0.BRAM_FAN5_2 always
BRAM_L.BRAM_FIFO36_WEBWEU1.BRAM_IMUX13_2 always
BRAM_L.BRAM_FIFO36_WEBWEU2.BRAM_IMUX29_2 always
BRAM_L.BRAM_FIFO36_WEBWEU3.BRAM_IMUX45_2 always
BRAM_L.BRAM_FIFO36_WEBWEU4.BRAM_FAN1_2 always
BRAM_L.BRAM_FIFO36_WEBWEU5.BRAM_IMUX14_2 always
BRAM_L.BRAM_FIFO36_WEBWEU6.BRAM_IMUX30_2 always
BRAM_L.BRAM_FIFO36_WEBWEU7.BRAM_IMUX46_2 always
BRAM_L.BRAM_RAMB18_CLKARDCLK.BRAM_CLK1_3 always
BRAM_L.BRAM_RAMB18_CLKBWRCLK.BRAM_CLK1_1 always
BRAM_L.BRAM_RAMB18_ENARDEN.BRAM_IMUX10_2 always
BRAM_L.BRAM_RAMB18_ENBWREN.BRAM_IMUX26_2 always
BRAM_L.BRAM_RAMB18_REGCEAREGCE.BRAM_IMUX11_2 always
BRAM_L.BRAM_RAMB18_REGCEB.BRAM_IMUX27_2 always
BRAM_L.BRAM_RAMB18_REGCLKARDRCLK.BRAM_CLK1_4 always
BRAM_L.BRAM_RAMB18_REGCLKB.BRAM_CLK1_0 always
BRAM_L.BRAM_RAMB18_RSTRAMARSTRAM.BRAM_CTRL1_3 always
BRAM_L.BRAM_RAMB18_RSTRAMB.BRAM_CTRL1_1 always
BRAM_L.BRAM_RAMB18_RSTREGARSTREG.BRAM_CTRL1_4 always
BRAM_L.BRAM_RAMB18_RSTREGB.BRAM_CTRL1_0 always
BRAM_L.BRAM_RAMB18_ADDRARDADDR0.BRAM_ADDRARDADDRU1 always
BRAM_L.BRAM_RAMB18_ADDRARDADDR1.BRAM_ADDRARDADDRU2 always
BRAM_L.BRAM_RAMB18_ADDRARDADDR2.BRAM_ADDRARDADDRU3 always
BRAM_L.BRAM_RAMB18_ADDRARDADDR3.BRAM_ADDRARDADDRU4 always
BRAM_L.BRAM_RAMB18_ADDRARDADDR4.BRAM_ADDRARDADDRU5 always
BRAM_L.BRAM_RAMB18_ADDRARDADDR5.BRAM_ADDRARDADDRU6 always
BRAM_L.BRAM_RAMB18_ADDRARDADDR6.BRAM_ADDRARDADDRU7 always
BRAM_L.BRAM_RAMB18_ADDRARDADDR7.BRAM_ADDRARDADDRU8 always
BRAM_L.BRAM_RAMB18_ADDRARDADDR8.BRAM_ADDRARDADDRU9 always
BRAM_L.BRAM_RAMB18_ADDRARDADDR9.BRAM_ADDRARDADDRU10 always
BRAM_L.BRAM_RAMB18_ADDRARDADDR10.BRAM_ADDRARDADDRU11 always
BRAM_L.BRAM_RAMB18_ADDRARDADDR11.BRAM_ADDRARDADDRU12 always
BRAM_L.BRAM_RAMB18_ADDRARDADDR12.BRAM_ADDRARDADDRU13 always
BRAM_L.BRAM_RAMB18_ADDRARDADDR13.BRAM_ADDRARDADDRU14 always
BRAM_L.BRAM_RAMB18_ADDRATIEHIGH0.BRAM_ADDRARDADDRU0 always
BRAM_L.BRAM_RAMB18_ADDRATIEHIGH1.BRAM_IMUX_ADDRARDADDRL15 always
BRAM_L.BRAM_RAMB18_ADDRBTIEHIGH0.BRAM_ADDRBWRADDRU0 always
BRAM_L.BRAM_RAMB18_ADDRBTIEHIGH1.BRAM_IMUX_ADDRBWRADDRL15 always
BRAM_L.BRAM_RAMB18_ADDRBWRADDR0.BRAM_ADDRBWRADDRU1 always
BRAM_L.BRAM_RAMB18_ADDRBWRADDR1.BRAM_ADDRBWRADDRU2 always
BRAM_L.BRAM_RAMB18_ADDRBWRADDR2.BRAM_ADDRBWRADDRU3 always
BRAM_L.BRAM_RAMB18_ADDRBWRADDR3.BRAM_ADDRBWRADDRU4 always
BRAM_L.BRAM_RAMB18_ADDRBWRADDR4.BRAM_ADDRBWRADDRU5 always
BRAM_L.BRAM_RAMB18_ADDRBWRADDR5.BRAM_ADDRBWRADDRU6 always
BRAM_L.BRAM_RAMB18_ADDRBWRADDR6.BRAM_ADDRBWRADDRU7 always
BRAM_L.BRAM_RAMB18_ADDRBWRADDR7.BRAM_ADDRBWRADDRU8 always
BRAM_L.BRAM_RAMB18_ADDRBWRADDR8.BRAM_ADDRBWRADDRU9 always
BRAM_L.BRAM_RAMB18_ADDRBWRADDR9.BRAM_ADDRBWRADDRU10 always
BRAM_L.BRAM_RAMB18_ADDRBWRADDR10.BRAM_ADDRBWRADDRU11 always
BRAM_L.BRAM_RAMB18_ADDRBWRADDR11.BRAM_ADDRBWRADDRU12 always
BRAM_L.BRAM_RAMB18_ADDRBWRADDR12.BRAM_ADDRBWRADDRU13 always
BRAM_L.BRAM_RAMB18_ADDRBWRADDR13.BRAM_ADDRBWRADDRU14 always
BRAM_L.BRAM_RAMB18_DIADI0.BRAM_IMUX8_1 always
BRAM_L.BRAM_RAMB18_DIADI1.BRAM_IMUX40_3 always
BRAM_L.BRAM_RAMB18_DIADI2.BRAM_IMUX42_3 always
BRAM_L.BRAM_RAMB18_DIADI3.BRAM_IMUX44_3 always
BRAM_L.BRAM_RAMB18_DIADI4.BRAM_IMUX8_4 always
BRAM_L.BRAM_RAMB18_DIADI5.BRAM_IMUX10_4 always
BRAM_L.BRAM_RAMB18_DIADI6.BRAM_IMUX12_4 always
BRAM_L.BRAM_RAMB18_DIADI7.BRAM_IMUX14_4 always
BRAM_L.BRAM_RAMB18_DIADI8.BRAM_IMUX15_2 always
BRAM_L.BRAM_RAMB18_DIADI9.BRAM_IMUX41_3 always
BRAM_L.BRAM_RAMB18_DIADI10.BRAM_IMUX43_3 always
BRAM_L.BRAM_RAMB18_DIADI11.BRAM_IMUX45_3 always
BRAM_L.BRAM_RAMB18_DIADI12.BRAM_IMUX9_4 always
BRAM_L.BRAM_RAMB18_DIADI13.BRAM_IMUX11_4 always
BRAM_L.BRAM_RAMB18_DIADI14.BRAM_IMUX13_4 always
BRAM_L.BRAM_RAMB18_DIADI15.BRAM_IMUX15_4 always
BRAM_L.BRAM_RAMB18_DIBDI0.BRAM_IMUX24_1 always
BRAM_L.BRAM_RAMB18_DIBDI1.BRAM_IMUX1_3 always
BRAM_L.BRAM_RAMB18_DIBDI2.BRAM_IMUX3_3 always
BRAM_L.BRAM_RAMB18_DIBDI3.BRAM_IMUX5_3 always
BRAM_L.BRAM_RAMB18_DIBDI4.BRAM_IMUX16_4 always
BRAM_L.BRAM_RAMB18_DIBDI5.BRAM_IMUX18_4 always
BRAM_L.BRAM_RAMB18_DIBDI6.BRAM_IMUX20_4 always
BRAM_L.BRAM_RAMB18_DIBDI7.BRAM_IMUX22_4 always
BRAM_L.BRAM_RAMB18_DIBDI8.BRAM_IMUX23_2 always
BRAM_L.BRAM_RAMB18_DIBDI9.BRAM_IMUX2_3 always
BRAM_L.BRAM_RAMB18_DIBDI10.BRAM_IMUX4_3 always
BRAM_L.BRAM_RAMB18_DIBDI11.BRAM_IMUX6_3 always
BRAM_L.BRAM_RAMB18_DIBDI12.BRAM_IMUX17_4 always
BRAM_L.BRAM_RAMB18_DIBDI13.BRAM_IMUX19_4 always
BRAM_L.BRAM_RAMB18_DIBDI14.BRAM_IMUX21_4 always
BRAM_L.BRAM_RAMB18_DIBDI15.BRAM_IMUX23_4 always
BRAM_L.BRAM_RAMB18_DIPADIP0.BRAM_IMUX42_2 always
BRAM_L.BRAM_RAMB18_DIPADIP1.BRAM_IMUX15_3 always
BRAM_L.BRAM_RAMB18_DIPBDIP0.BRAM_IMUX43_2 always
BRAM_L.BRAM_RAMB18_DIPBDIP1.BRAM_IMUX23_3 always
BRAM_L.BRAM_RAMB18_WEA0.BRAM_IMUX8_2 always
BRAM_L.BRAM_RAMB18_WEA1.BRAM_IMUX24_2 always
BRAM_L.BRAM_RAMB18_WEA2.BRAM_IMUX9_2 always
BRAM_L.BRAM_RAMB18_WEA3.BRAM_IMUX25_2 always
BRAM_L.BRAM_RAMB18_WEBWE0.BRAM_FAN5_2 always
BRAM_L.BRAM_RAMB18_WEBWE1.BRAM_IMUX13_2 always
BRAM_L.BRAM_RAMB18_WEBWE2.BRAM_IMUX29_2 always
BRAM_L.BRAM_RAMB18_WEBWE3.BRAM_IMUX45_2 always
BRAM_L.BRAM_RAMB18_WEBWE4.BRAM_FAN1_2 always
BRAM_L.BRAM_RAMB18_WEBWE5.BRAM_IMUX14_2 always
BRAM_L.BRAM_RAMB18_WEBWE6.BRAM_IMUX30_2 always
BRAM_L.BRAM_RAMB18_WEBWE7.BRAM_IMUX46_2 always

590
artix7/ppips_bram_r.db Normal file
View File

@ -0,0 +1,590 @@
BRAM_R.BRAM_CASCOUT_ADDRARDADDRU0.BRAM_ADDRARDADDRU0 always
BRAM_R.BRAM_CASCOUT_ADDRARDADDRU1.BRAM_ADDRARDADDRU1 always
BRAM_R.BRAM_CASCOUT_ADDRARDADDRU2.BRAM_ADDRARDADDRU2 always
BRAM_R.BRAM_CASCOUT_ADDRARDADDRU3.BRAM_ADDRARDADDRU3 always
BRAM_R.BRAM_CASCOUT_ADDRARDADDRU4.BRAM_ADDRARDADDRU4 always
BRAM_R.BRAM_CASCOUT_ADDRARDADDRU5.BRAM_ADDRARDADDRU5 always
BRAM_R.BRAM_CASCOUT_ADDRARDADDRU6.BRAM_ADDRARDADDRU6 always
BRAM_R.BRAM_CASCOUT_ADDRARDADDRU7.BRAM_ADDRARDADDRU7 always
BRAM_R.BRAM_CASCOUT_ADDRARDADDRU8.BRAM_ADDRARDADDRU8 always
BRAM_R.BRAM_CASCOUT_ADDRARDADDRU9.BRAM_ADDRARDADDRU9 always
BRAM_R.BRAM_CASCOUT_ADDRARDADDRU10.BRAM_ADDRARDADDRU10 always
BRAM_R.BRAM_CASCOUT_ADDRARDADDRU11.BRAM_ADDRARDADDRU11 always
BRAM_R.BRAM_CASCOUT_ADDRARDADDRU12.BRAM_ADDRARDADDRU12 always
BRAM_R.BRAM_CASCOUT_ADDRARDADDRU13.BRAM_ADDRARDADDRU13 always
BRAM_R.BRAM_CASCOUT_ADDRARDADDRU14.BRAM_ADDRARDADDRU14 always
BRAM_R.BRAM_CASCOUT_ADDRBWRADDRU0.BRAM_ADDRBWRADDRU0 always
BRAM_R.BRAM_CASCOUT_ADDRBWRADDRU1.BRAM_ADDRBWRADDRU1 always
BRAM_R.BRAM_CASCOUT_ADDRBWRADDRU2.BRAM_ADDRBWRADDRU2 always
BRAM_R.BRAM_CASCOUT_ADDRBWRADDRU3.BRAM_ADDRBWRADDRU3 always
BRAM_R.BRAM_CASCOUT_ADDRBWRADDRU4.BRAM_ADDRBWRADDRU4 always
BRAM_R.BRAM_CASCOUT_ADDRBWRADDRU5.BRAM_ADDRBWRADDRU5 always
BRAM_R.BRAM_CASCOUT_ADDRBWRADDRU6.BRAM_ADDRBWRADDRU6 always
BRAM_R.BRAM_CASCOUT_ADDRBWRADDRU7.BRAM_ADDRBWRADDRU7 always
BRAM_R.BRAM_CASCOUT_ADDRBWRADDRU8.BRAM_ADDRBWRADDRU8 always
BRAM_R.BRAM_CASCOUT_ADDRBWRADDRU9.BRAM_ADDRBWRADDRU9 always
BRAM_R.BRAM_CASCOUT_ADDRBWRADDRU10.BRAM_ADDRBWRADDRU10 always
BRAM_R.BRAM_CASCOUT_ADDRBWRADDRU11.BRAM_ADDRBWRADDRU11 always
BRAM_R.BRAM_CASCOUT_ADDRBWRADDRU12.BRAM_ADDRBWRADDRU12 always
BRAM_R.BRAM_CASCOUT_ADDRBWRADDRU13.BRAM_ADDRBWRADDRU13 always
BRAM_R.BRAM_CASCOUT_ADDRBWRADDRU14.BRAM_ADDRBWRADDRU14 always
BRAM_R.BRAM_IMUX_R_ADDRARDADDRL15.BRAM_IMUX31_3 always
BRAM_R.BRAM_IMUX_R_ADDRBWRADDRL15.BRAM_IMUX39_3 always
BRAM_R.BRAM_LOGIC_OUTS_B9_2.BRAM_FIFO36_SBITERR always
BRAM_R.BRAM_LOGIC_OUTS_B10_2.BRAM_FIFO36_ECCPARITY4 always
BRAM_R.BRAM_LOGIC_OUTS_B11_0.BRAM_FIFO36_TSTOUT4 always
BRAM_R.BRAM_LOGIC_OUTS_B11_1.BRAM_FIFO36_TSTOUT3 always
BRAM_R.BRAM_LOGIC_OUTS_B11_3.BRAM_FIFO36_ECCPARITY7 always
BRAM_R.BRAM_LOGIC_OUTS_B11_4.BRAM_FIFO36_TSTOUT2 always
BRAM_R.BRAM_LOGIC_OUTS_B12_3.BRAM_FIFO36_ECCPARITY1 always
BRAM_R.BRAM_LOGIC_OUTS_B13_2.BRAM_FIFO36_ECCPARITY2 always
BRAM_R.BRAM_LOGIC_OUTS_B16_2.BRAM_FIFO36_DBITERR always
BRAM_R.BRAM_LOGIC_OUTS_B18_0.BRAM_FIFO36_TSTOUT1 always
BRAM_R.BRAM_LOGIC_OUTS_B18_1.BRAM_FIFO36_TSTOUT0 always
BRAM_R.BRAM_LOGIC_OUTS_B18_3.BRAM_FIFO36_ECCPARITY0 always
BRAM_R.BRAM_LOGIC_OUTS_B19_2.BRAM_FIFO36_ECCPARITY3 always
BRAM_R.BRAM_LOGIC_OUTS_B20_2.BRAM_FIFO36_ECCPARITY5 always
BRAM_R.BRAM_LOGIC_OUTS_B21_3.BRAM_FIFO36_ECCPARITY6 always
BRAM_R.BRAM_LOGIC_OUTS_B21_4.BRAM_FIFO36_RDCOUNT12 always
BRAM_R.BRAM_LOGIC_OUTS_B23_4.BRAM_FIFO36_WRCOUNT12 always
BRAM_R.BRAM_R_IMUX_ADDRARDADDRL0.BRAM_IMUX17_1 always
BRAM_R.BRAM_R_IMUX_ADDRARDADDRL1.BRAM_IMUX18_1 always
BRAM_R.BRAM_R_IMUX_ADDRARDADDRL2.BRAM_IMUX19_1 always
BRAM_R.BRAM_R_IMUX_ADDRARDADDRL3.BRAM_IMUX18_3 always
BRAM_R.BRAM_R_IMUX_ADDRARDADDRL4.BRAM_IMUX21_1 always
BRAM_R.BRAM_R_IMUX_ADDRARDADDRL5.BRAM_IMUX20_3 always
BRAM_R.BRAM_R_IMUX_ADDRARDADDRL6.BRAM_IMUX16_3 always
BRAM_R.BRAM_R_IMUX_ADDRARDADDRL7.BRAM_IMUX17_3 always
BRAM_R.BRAM_R_IMUX_ADDRARDADDRL8.BRAM_IMUX20_1 always
BRAM_R.BRAM_R_IMUX_ADDRARDADDRL9.BRAM_IMUX19_3 always
BRAM_R.BRAM_R_IMUX_ADDRARDADDRL10.BRAM_IMUX20_2 always
BRAM_R.BRAM_R_IMUX_ADDRARDADDRL11.BRAM_IMUX22_1 always
BRAM_R.BRAM_R_IMUX_ADDRARDADDRL12.BRAM_IMUX21_3 always
BRAM_R.BRAM_R_IMUX_ADDRARDADDRL13.BRAM_IMUX23_1 always
BRAM_R.BRAM_R_IMUX_ADDRARDADDRL14.BRAM_IMUX22_3 always
BRAM_R.BRAM_R_IMUX_ADDRARDADDRU0.BRAM_IMUX9_1 always
BRAM_R.BRAM_R_IMUX_ADDRARDADDRU1.BRAM_IMUX10_1 always
BRAM_R.BRAM_R_IMUX_ADDRARDADDRU2.BRAM_IMUX11_1 always
BRAM_R.BRAM_R_IMUX_ADDRARDADDRU3.BRAM_IMUX10_3 always
BRAM_R.BRAM_R_IMUX_ADDRARDADDRU4.BRAM_IMUX13_1 always
BRAM_R.BRAM_R_IMUX_ADDRARDADDRU5.BRAM_IMUX12_3 always
BRAM_R.BRAM_R_IMUX_ADDRARDADDRU6.BRAM_IMUX8_3 always
BRAM_R.BRAM_R_IMUX_ADDRARDADDRU7.BRAM_IMUX9_3 always
BRAM_R.BRAM_R_IMUX_ADDRARDADDRU8.BRAM_IMUX12_1 always
BRAM_R.BRAM_R_IMUX_ADDRARDADDRU9.BRAM_IMUX11_3 always
BRAM_R.BRAM_R_IMUX_ADDRARDADDRU10.BRAM_IMUX12_2 always
BRAM_R.BRAM_R_IMUX_ADDRARDADDRU11.BRAM_IMUX14_1 always
BRAM_R.BRAM_R_IMUX_ADDRARDADDRU12.BRAM_IMUX13_3 always
BRAM_R.BRAM_R_IMUX_ADDRARDADDRU13.BRAM_IMUX15_1 always
BRAM_R.BRAM_R_IMUX_ADDRARDADDRU14.BRAM_IMUX14_3 always
BRAM_R.BRAM_R_IMUX_ADDRBWRADDRL0.BRAM_IMUX33_1 always
BRAM_R.BRAM_R_IMUX_ADDRBWRADDRL1.BRAM_IMUX34_1 always
BRAM_R.BRAM_R_IMUX_ADDRBWRADDRL2.BRAM_IMUX35_1 always
BRAM_R.BRAM_R_IMUX_ADDRBWRADDRL3.BRAM_IMUX34_3 always
BRAM_R.BRAM_R_IMUX_ADDRBWRADDRL4.BRAM_IMUX37_1 always
BRAM_R.BRAM_R_IMUX_ADDRBWRADDRL5.BRAM_IMUX36_3 always
BRAM_R.BRAM_R_IMUX_ADDRBWRADDRL6.BRAM_IMUX32_3 always
BRAM_R.BRAM_R_IMUX_ADDRBWRADDRL7.BRAM_IMUX33_3 always
BRAM_R.BRAM_R_IMUX_ADDRBWRADDRL8.BRAM_IMUX36_1 always
BRAM_R.BRAM_R_IMUX_ADDRBWRADDRL9.BRAM_IMUX35_3 always
BRAM_R.BRAM_R_IMUX_ADDRBWRADDRL10.BRAM_IMUX36_2 always
BRAM_R.BRAM_R_IMUX_ADDRBWRADDRL11.BRAM_IMUX38_1 always
BRAM_R.BRAM_R_IMUX_ADDRBWRADDRL12.BRAM_IMUX37_3 always
BRAM_R.BRAM_R_IMUX_ADDRBWRADDRL13.BRAM_IMUX39_1 always
BRAM_R.BRAM_R_IMUX_ADDRBWRADDRL14.BRAM_IMUX38_3 always
BRAM_R.BRAM_R_IMUX_ADDRBWRADDRU0.BRAM_IMUX25_1 always
BRAM_R.BRAM_R_IMUX_ADDRBWRADDRU1.BRAM_IMUX26_1 always
BRAM_R.BRAM_R_IMUX_ADDRBWRADDRU2.BRAM_IMUX27_1 always
BRAM_R.BRAM_R_IMUX_ADDRBWRADDRU3.BRAM_IMUX26_3 always
BRAM_R.BRAM_R_IMUX_ADDRBWRADDRU4.BRAM_IMUX29_1 always
BRAM_R.BRAM_R_IMUX_ADDRBWRADDRU5.BRAM_IMUX28_3 always
BRAM_R.BRAM_R_IMUX_ADDRBWRADDRU6.BRAM_IMUX24_3 always
BRAM_R.BRAM_R_IMUX_ADDRBWRADDRU7.BRAM_IMUX25_3 always
BRAM_R.BRAM_R_IMUX_ADDRBWRADDRU8.BRAM_IMUX28_1 always
BRAM_R.BRAM_R_IMUX_ADDRBWRADDRU9.BRAM_IMUX27_3 always
BRAM_R.BRAM_R_IMUX_ADDRBWRADDRU10.BRAM_IMUX28_2 always
BRAM_R.BRAM_R_IMUX_ADDRBWRADDRU11.BRAM_IMUX30_1 always
BRAM_R.BRAM_R_IMUX_ADDRBWRADDRU12.BRAM_IMUX29_3 always
BRAM_R.BRAM_R_IMUX_ADDRBWRADDRU13.BRAM_IMUX31_1 always
BRAM_R.BRAM_R_IMUX_ADDRBWRADDRU14.BRAM_IMUX30_3 always
BRAM_R.BRAM_UTURN_ADDRARDADDRL0.BRAM_ADDRARDADDRL0 always
BRAM_R.BRAM_UTURN_ADDRARDADDRL1.BRAM_ADDRARDADDRL1 always
BRAM_R.BRAM_UTURN_ADDRARDADDRL2.BRAM_ADDRARDADDRL2 always
BRAM_R.BRAM_UTURN_ADDRARDADDRL3.BRAM_ADDRARDADDRL3 always
BRAM_R.BRAM_UTURN_ADDRARDADDRL4.BRAM_ADDRARDADDRL4 always
BRAM_R.BRAM_UTURN_ADDRARDADDRL5.BRAM_ADDRARDADDRL5 always
BRAM_R.BRAM_UTURN_ADDRARDADDRL6.BRAM_ADDRARDADDRL6 always
BRAM_R.BRAM_UTURN_ADDRARDADDRL7.BRAM_ADDRARDADDRL7 always
BRAM_R.BRAM_UTURN_ADDRARDADDRL8.BRAM_ADDRARDADDRL8 always
BRAM_R.BRAM_UTURN_ADDRARDADDRL9.BRAM_ADDRARDADDRL9 always
BRAM_R.BRAM_UTURN_ADDRARDADDRL10.BRAM_ADDRARDADDRL10 always
BRAM_R.BRAM_UTURN_ADDRARDADDRL11.BRAM_ADDRARDADDRL11 always
BRAM_R.BRAM_UTURN_ADDRARDADDRL12.BRAM_ADDRARDADDRL12 always
BRAM_R.BRAM_UTURN_ADDRARDADDRL13.BRAM_ADDRARDADDRL13 always
BRAM_R.BRAM_UTURN_ADDRARDADDRL14.BRAM_ADDRARDADDRL14 always
BRAM_R.BRAM_UTURN_ADDRARDADDRL15.BRAM_IMUX_R_ADDRARDADDRL15 always
BRAM_R.BRAM_UTURN_ADDRARDADDRU0.BRAM_ADDRARDADDRU0 always
BRAM_R.BRAM_UTURN_ADDRARDADDRU1.BRAM_ADDRARDADDRU1 always
BRAM_R.BRAM_UTURN_ADDRARDADDRU2.BRAM_ADDRARDADDRU2 always
BRAM_R.BRAM_UTURN_ADDRARDADDRU3.BRAM_ADDRARDADDRU3 always
BRAM_R.BRAM_UTURN_ADDRARDADDRU4.BRAM_ADDRARDADDRU4 always
BRAM_R.BRAM_UTURN_ADDRARDADDRU5.BRAM_ADDRARDADDRU5 always
BRAM_R.BRAM_UTURN_ADDRARDADDRU6.BRAM_ADDRARDADDRU6 always
BRAM_R.BRAM_UTURN_ADDRARDADDRU7.BRAM_ADDRARDADDRU7 always
BRAM_R.BRAM_UTURN_ADDRARDADDRU8.BRAM_ADDRARDADDRU8 always
BRAM_R.BRAM_UTURN_ADDRARDADDRU9.BRAM_ADDRARDADDRU9 always
BRAM_R.BRAM_UTURN_ADDRARDADDRU10.BRAM_ADDRARDADDRU10 always
BRAM_R.BRAM_UTURN_ADDRARDADDRU11.BRAM_ADDRARDADDRU11 always
BRAM_R.BRAM_UTURN_ADDRARDADDRU12.BRAM_ADDRARDADDRU12 always
BRAM_R.BRAM_UTURN_ADDRARDADDRU13.BRAM_ADDRARDADDRU13 always
BRAM_R.BRAM_UTURN_ADDRARDADDRU14.BRAM_ADDRARDADDRU14 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRL0.BRAM_ADDRBWRADDRL0 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRL1.BRAM_ADDRBWRADDRL1 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRL2.BRAM_ADDRBWRADDRL2 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRL3.BRAM_ADDRBWRADDRL3 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRL4.BRAM_ADDRBWRADDRL4 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRL5.BRAM_ADDRBWRADDRL5 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRL6.BRAM_ADDRBWRADDRL6 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRL7.BRAM_ADDRBWRADDRL7 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRL8.BRAM_ADDRBWRADDRL8 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRL9.BRAM_ADDRBWRADDRL9 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRL10.BRAM_ADDRBWRADDRL10 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRL11.BRAM_ADDRBWRADDRL11 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRL12.BRAM_ADDRBWRADDRL12 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRL13.BRAM_ADDRBWRADDRL13 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRL14.BRAM_ADDRBWRADDRL14 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRL15.BRAM_IMUX_R_ADDRBWRADDRL15 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRU0.BRAM_ADDRBWRADDRU0 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRU1.BRAM_ADDRBWRADDRU1 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRU2.BRAM_ADDRBWRADDRU2 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRU3.BRAM_ADDRBWRADDRU3 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRU4.BRAM_ADDRBWRADDRU4 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRU5.BRAM_ADDRBWRADDRU5 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRU6.BRAM_ADDRBWRADDRU6 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRU7.BRAM_ADDRBWRADDRU7 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRU8.BRAM_ADDRBWRADDRU8 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRU9.BRAM_ADDRBWRADDRU9 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRU10.BRAM_ADDRBWRADDRU10 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRU11.BRAM_ADDRBWRADDRU11 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRU12.BRAM_ADDRBWRADDRU12 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRU13.BRAM_ADDRBWRADDRU13 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRU14.BRAM_ADDRBWRADDRU14 always
BRAM_R.BRAM_FIFO18_CLKARDCLK.BRAM_CLK0_3 always
BRAM_R.BRAM_FIFO18_CLKBWRCLK.BRAM_CLK0_1 always
BRAM_R.BRAM_FIFO18_ENARDEN.BRAM_IMUX18_2 always
BRAM_R.BRAM_FIFO18_ENBWREN.BRAM_IMUX34_2 always
BRAM_R.BRAM_FIFO18_REGCEAREGCE.BRAM_IMUX19_2 always
BRAM_R.BRAM_FIFO18_REGCEB.BRAM_IMUX35_2 always
BRAM_R.BRAM_FIFO18_REGCLKARDRCLK.BRAM_CLK0_4 always
BRAM_R.BRAM_FIFO18_REGCLKB.BRAM_CLK0_0 always
BRAM_R.BRAM_FIFO18_RSTRAMARSTRAM.BRAM_CTRL0_3 always
BRAM_R.BRAM_FIFO18_RSTRAMB.BRAM_CTRL0_1 always
BRAM_R.BRAM_FIFO18_RSTREGARSTREG.BRAM_CTRL0_4 always
BRAM_R.BRAM_FIFO18_RSTREGB.BRAM_CTRL0_0 always
BRAM_R.BRAM_FIFO18_ADDRARDADDR0.BRAM_ADDRARDADDRL1 always
BRAM_R.BRAM_FIFO18_ADDRARDADDR1.BRAM_ADDRARDADDRL2 always
BRAM_R.BRAM_FIFO18_ADDRARDADDR2.BRAM_ADDRARDADDRL3 always
BRAM_R.BRAM_FIFO18_ADDRARDADDR3.BRAM_ADDRARDADDRL4 always
BRAM_R.BRAM_FIFO18_ADDRARDADDR4.BRAM_ADDRARDADDRL5 always
BRAM_R.BRAM_FIFO18_ADDRARDADDR5.BRAM_ADDRARDADDRL6 always
BRAM_R.BRAM_FIFO18_ADDRARDADDR6.BRAM_ADDRARDADDRL7 always
BRAM_R.BRAM_FIFO18_ADDRARDADDR7.BRAM_ADDRARDADDRL8 always
BRAM_R.BRAM_FIFO18_ADDRARDADDR8.BRAM_ADDRARDADDRL9 always
BRAM_R.BRAM_FIFO18_ADDRARDADDR9.BRAM_ADDRARDADDRL10 always
BRAM_R.BRAM_FIFO18_ADDRARDADDR10.BRAM_ADDRARDADDRL11 always
BRAM_R.BRAM_FIFO18_ADDRARDADDR11.BRAM_ADDRARDADDRL12 always
BRAM_R.BRAM_FIFO18_ADDRARDADDR12.BRAM_ADDRARDADDRL13 always
BRAM_R.BRAM_FIFO18_ADDRARDADDR13.BRAM_ADDRARDADDRL14 always
BRAM_R.BRAM_FIFO18_ADDRATIEHIGH0.BRAM_ADDRARDADDRL0 always
BRAM_R.BRAM_FIFO18_ADDRATIEHIGH1.BRAM_IMUX_R_ADDRARDADDRL15 always
BRAM_R.BRAM_FIFO18_ADDRBTIEHIGH0.BRAM_ADDRBWRADDRL0 always
BRAM_R.BRAM_FIFO18_ADDRBTIEHIGH1.BRAM_IMUX_R_ADDRBWRADDRL15 always
BRAM_R.BRAM_FIFO18_ADDRBWRADDR0.BRAM_ADDRBWRADDRL1 always
BRAM_R.BRAM_FIFO18_ADDRBWRADDR1.BRAM_ADDRBWRADDRL2 always
BRAM_R.BRAM_FIFO18_ADDRBWRADDR2.BRAM_ADDRBWRADDRL3 always
BRAM_R.BRAM_FIFO18_ADDRBWRADDR3.BRAM_ADDRBWRADDRL4 always
BRAM_R.BRAM_FIFO18_ADDRBWRADDR4.BRAM_ADDRBWRADDRL5 always
BRAM_R.BRAM_FIFO18_ADDRBWRADDR5.BRAM_ADDRBWRADDRL6 always
BRAM_R.BRAM_FIFO18_ADDRBWRADDR6.BRAM_ADDRBWRADDRL7 always
BRAM_R.BRAM_FIFO18_ADDRBWRADDR7.BRAM_ADDRBWRADDRL8 always
BRAM_R.BRAM_FIFO18_ADDRBWRADDR8.BRAM_ADDRBWRADDRL9 always
BRAM_R.BRAM_FIFO18_ADDRBWRADDR9.BRAM_ADDRBWRADDRL10 always
BRAM_R.BRAM_FIFO18_ADDRBWRADDR10.BRAM_ADDRBWRADDRL11 always
BRAM_R.BRAM_FIFO18_ADDRBWRADDR11.BRAM_ADDRBWRADDRL12 always
BRAM_R.BRAM_FIFO18_ADDRBWRADDR12.BRAM_ADDRBWRADDRL13 always
BRAM_R.BRAM_FIFO18_ADDRBWRADDR13.BRAM_ADDRBWRADDRL14 always
BRAM_R.BRAM_FIFO18_DIADI0.BRAM_IMUX16_1 always
BRAM_R.BRAM_FIFO18_DIADI1.BRAM_IMUX26_0 always
BRAM_R.BRAM_FIFO18_DIADI2.BRAM_IMUX28_0 always
BRAM_R.BRAM_FIFO18_DIADI3.BRAM_IMUX30_0 always
BRAM_R.BRAM_FIFO18_DIADI4.BRAM_IMUX41_1 always
BRAM_R.BRAM_FIFO18_DIADI5.BRAM_IMUX43_1 always
BRAM_R.BRAM_FIFO18_DIADI6.BRAM_IMUX45_1 always
BRAM_R.BRAM_FIFO18_DIADI7.BRAM_IMUX40_2 always
BRAM_R.BRAM_FIFO18_DIADI8.BRAM_IMUX25_0 always
BRAM_R.BRAM_FIFO18_DIADI9.BRAM_IMUX27_0 always
BRAM_R.BRAM_FIFO18_DIADI10.BRAM_IMUX29_0 always
BRAM_R.BRAM_FIFO18_DIADI11.BRAM_IMUX31_0 always
BRAM_R.BRAM_FIFO18_DIADI12.BRAM_IMUX42_1 always
BRAM_R.BRAM_FIFO18_DIADI13.BRAM_IMUX44_1 always
BRAM_R.BRAM_FIFO18_DIADI14.BRAM_IMUX46_1 always
BRAM_R.BRAM_FIFO18_DIADI15.BRAM_IMUX41_2 always
BRAM_R.BRAM_FIFO18_DIBDI0.BRAM_IMUX32_1 always
BRAM_R.BRAM_FIFO18_DIBDI1.BRAM_IMUX34_0 always
BRAM_R.BRAM_FIFO18_DIBDI2.BRAM_IMUX36_0 always
BRAM_R.BRAM_FIFO18_DIBDI3.BRAM_IMUX38_0 always
BRAM_R.BRAM_FIFO18_DIBDI4.BRAM_IMUX2_1 always
BRAM_R.BRAM_FIFO18_DIBDI5.BRAM_IMUX4_1 always
BRAM_R.BRAM_FIFO18_DIBDI6.BRAM_IMUX6_1 always
BRAM_R.BRAM_FIFO18_DIBDI7.BRAM_IMUX1_2 always
BRAM_R.BRAM_FIFO18_DIBDI8.BRAM_IMUX33_0 always
BRAM_R.BRAM_FIFO18_DIBDI9.BRAM_IMUX35_0 always
BRAM_R.BRAM_FIFO18_DIBDI10.BRAM_IMUX37_0 always
BRAM_R.BRAM_FIFO18_DIBDI11.BRAM_IMUX39_0 always
BRAM_R.BRAM_FIFO18_DIBDI12.BRAM_IMUX3_1 always
BRAM_R.BRAM_FIFO18_DIBDI13.BRAM_IMUX5_1 always
BRAM_R.BRAM_FIFO18_DIBDI14.BRAM_IMUX7_1 always
BRAM_R.BRAM_FIFO18_DIBDI15.BRAM_IMUX2_2 always
BRAM_R.BRAM_FIFO18_DIPADIP0.BRAM_IMUX3_2 always
BRAM_R.BRAM_FIFO18_DIPADIP1.BRAM_IMUX40_1 always
BRAM_R.BRAM_FIFO18_DIPBDIP0.BRAM_IMUX4_2 always
BRAM_R.BRAM_FIFO18_DIPBDIP1.BRAM_IMUX1_1 always
BRAM_R.BRAM_FIFO18_WEA0.BRAM_IMUX16_2 always
BRAM_R.BRAM_FIFO18_WEA1.BRAM_IMUX32_2 always
BRAM_R.BRAM_FIFO18_WEA2.BRAM_IMUX17_2 always
BRAM_R.BRAM_FIFO18_WEA3.BRAM_IMUX33_2 always
BRAM_R.BRAM_FIFO18_WEBWE0.BRAM_IMUX5_2 always
BRAM_R.BRAM_FIFO18_WEBWE1.BRAM_IMUX21_2 always
BRAM_R.BRAM_FIFO18_WEBWE2.BRAM_IMUX37_2 always
BRAM_R.BRAM_FIFO18_WEBWE3.BRAM_BYP3_2 always
BRAM_R.BRAM_FIFO18_WEBWE4.BRAM_IMUX6_2 always
BRAM_R.BRAM_FIFO18_WEBWE5.BRAM_IMUX22_2 always
BRAM_R.BRAM_FIFO18_WEBWE6.BRAM_IMUX38_2 always
BRAM_R.BRAM_FIFO18_WEBWE7.BRAM_BYP6_2 always
BRAM_R.BRAM_FIFO36_CASCADEOUTA_1.BRAM_FIFO36_CASCADEOUTA always
BRAM_R.BRAM_FIFO36_CASCADEOUTB_1.BRAM_FIFO36_CASCADEOUTB always
BRAM_R.BRAM_FIFO36_CLKARDCLKL.BRAM_CLK0_3 always
BRAM_R.BRAM_FIFO36_CLKARDCLKU.BRAM_CLK1_3 always
BRAM_R.BRAM_FIFO36_CLKBWRCLKL.BRAM_CLK0_1 always
BRAM_R.BRAM_FIFO36_CLKBWRCLKU.BRAM_CLK1_1 always
BRAM_R.BRAM_FIFO36_ENARDENL.BRAM_IMUX18_2 always
BRAM_R.BRAM_FIFO36_ENARDENU.BRAM_IMUX10_2 always
BRAM_R.BRAM_FIFO36_ENBWRENL.BRAM_IMUX34_2 always
BRAM_R.BRAM_FIFO36_ENBWRENU.BRAM_IMUX26_2 always
BRAM_R.BRAM_FIFO36_INJECTDBITERR.BRAM_IMUX31_2 always
BRAM_R.BRAM_FIFO36_INJECTSBITERR.BRAM_IMUX39_2 always
BRAM_R.BRAM_FIFO36_REGCEAREGCEL.BRAM_IMUX19_2 always
BRAM_R.BRAM_FIFO36_REGCEAREGCEU.BRAM_IMUX11_2 always
BRAM_R.BRAM_FIFO36_REGCEBL.BRAM_IMUX35_2 always
BRAM_R.BRAM_FIFO36_REGCEBU.BRAM_IMUX27_2 always
BRAM_R.BRAM_FIFO36_REGCLKARDRCLKL.BRAM_CLK0_4 always
BRAM_R.BRAM_FIFO36_REGCLKARDRCLKU.BRAM_CLK1_4 always
BRAM_R.BRAM_FIFO36_REGCLKBL.BRAM_CLK0_0 always
BRAM_R.BRAM_FIFO36_REGCLKBU.BRAM_CLK1_0 always
BRAM_R.BRAM_FIFO36_RSTRAMARSTRAMLRST.BRAM_CTRL0_3 always
BRAM_R.BRAM_FIFO36_RSTRAMARSTRAMU.BRAM_CTRL1_3 always
BRAM_R.BRAM_FIFO36_RSTRAMBL.BRAM_CTRL0_1 always
BRAM_R.BRAM_FIFO36_RSTRAMBU.BRAM_CTRL1_1 always
BRAM_R.BRAM_FIFO36_RSTREGARSTREGL.BRAM_CTRL0_4 always
BRAM_R.BRAM_FIFO36_RSTREGARSTREGU.BRAM_CTRL1_4 always
BRAM_R.BRAM_FIFO36_RSTREGBL.BRAM_CTRL0_0 always
BRAM_R.BRAM_FIFO36_RSTREGBU.BRAM_CTRL1_0 always
BRAM_R.BRAM_FIFO36_TSTBRAMRST.BRAM_IMUX0_0 always
BRAM_R.BRAM_FIFO36_TSTFLAGIN.BRAM_IMUX5_0 always
BRAM_R.BRAM_FIFO36_TSTOFF.BRAM_IMUX4_0 always
BRAM_R.BRAM_FIFO36_TSTRDCNTOFF.BRAM_IMUX2_0 always
BRAM_R.BRAM_FIFO36_TSTWRCNTOFF.BRAM_IMUX3_0 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRL0.BRAM_ADDRARDADDRL0 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRL1.BRAM_ADDRARDADDRL1 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRL2.BRAM_ADDRARDADDRL2 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRL3.BRAM_ADDRARDADDRL3 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRL4.BRAM_ADDRARDADDRL4 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRL5.BRAM_ADDRARDADDRL5 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRL6.BRAM_ADDRARDADDRL6 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRL7.BRAM_ADDRARDADDRL7 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRL8.BRAM_ADDRARDADDRL8 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRL9.BRAM_ADDRARDADDRL9 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRL10.BRAM_ADDRARDADDRL10 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRL11.BRAM_ADDRARDADDRL11 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRL12.BRAM_ADDRARDADDRL12 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRL13.BRAM_ADDRARDADDRL13 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRL14.BRAM_ADDRARDADDRL14 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRL15.BRAM_IMUX_R_ADDRARDADDRL15 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRU0.BRAM_ADDRARDADDRU0 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRU1.BRAM_ADDRARDADDRU1 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRU2.BRAM_ADDRARDADDRU2 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRU3.BRAM_ADDRARDADDRU3 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRU4.BRAM_ADDRARDADDRU4 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRU5.BRAM_ADDRARDADDRU5 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRU6.BRAM_ADDRARDADDRU6 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRU7.BRAM_ADDRARDADDRU7 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRU8.BRAM_ADDRARDADDRU8 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRU9.BRAM_ADDRARDADDRU9 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRU10.BRAM_ADDRARDADDRU10 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRU11.BRAM_ADDRARDADDRU11 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRU12.BRAM_ADDRARDADDRU12 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRU13.BRAM_ADDRARDADDRU13 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRU14.BRAM_ADDRARDADDRU14 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRL0.BRAM_ADDRBWRADDRL0 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRL1.BRAM_ADDRBWRADDRL1 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRL2.BRAM_ADDRBWRADDRL2 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRL3.BRAM_ADDRBWRADDRL3 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRL4.BRAM_ADDRBWRADDRL4 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRL5.BRAM_ADDRBWRADDRL5 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRL6.BRAM_ADDRBWRADDRL6 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRL7.BRAM_ADDRBWRADDRL7 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRL8.BRAM_ADDRBWRADDRL8 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRL9.BRAM_ADDRBWRADDRL9 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRL10.BRAM_ADDRBWRADDRL10 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRL11.BRAM_ADDRBWRADDRL11 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRL12.BRAM_ADDRBWRADDRL12 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRL13.BRAM_ADDRBWRADDRL13 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRL14.BRAM_ADDRBWRADDRL14 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRL15.BRAM_IMUX_R_ADDRBWRADDRL15 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRU0.BRAM_ADDRBWRADDRU0 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRU1.BRAM_ADDRBWRADDRU1 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRU2.BRAM_ADDRBWRADDRU2 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRU3.BRAM_ADDRBWRADDRU3 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRU4.BRAM_ADDRBWRADDRU4 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRU5.BRAM_ADDRBWRADDRU5 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRU6.BRAM_ADDRBWRADDRU6 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRU7.BRAM_ADDRBWRADDRU7 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRU8.BRAM_ADDRBWRADDRU8 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRU9.BRAM_ADDRBWRADDRU9 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRU10.BRAM_ADDRBWRADDRU10 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRU11.BRAM_ADDRBWRADDRU11 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRU12.BRAM_ADDRBWRADDRU12 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRU13.BRAM_ADDRBWRADDRU13 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRU14.BRAM_ADDRBWRADDRU14 always
BRAM_R.BRAM_FIFO36_DIADIL0.BRAM_IMUX16_1 always
BRAM_R.BRAM_FIFO36_DIADIL1.BRAM_IMUX26_0 always
BRAM_R.BRAM_FIFO36_DIADIL2.BRAM_IMUX28_0 always
BRAM_R.BRAM_FIFO36_DIADIL3.BRAM_IMUX30_0 always
BRAM_R.BRAM_FIFO36_DIADIL4.BRAM_IMUX41_1 always
BRAM_R.BRAM_FIFO36_DIADIL5.BRAM_IMUX43_1 always
BRAM_R.BRAM_FIFO36_DIADIL6.BRAM_IMUX45_1 always
BRAM_R.BRAM_FIFO36_DIADIL7.BRAM_IMUX40_2 always
BRAM_R.BRAM_FIFO36_DIADIL8.BRAM_IMUX25_0 always
BRAM_R.BRAM_FIFO36_DIADIL9.BRAM_IMUX27_0 always
BRAM_R.BRAM_FIFO36_DIADIL10.BRAM_IMUX29_0 always
BRAM_R.BRAM_FIFO36_DIADIL11.BRAM_IMUX31_0 always
BRAM_R.BRAM_FIFO36_DIADIL12.BRAM_IMUX42_1 always
BRAM_R.BRAM_FIFO36_DIADIL13.BRAM_IMUX44_1 always
BRAM_R.BRAM_FIFO36_DIADIL14.BRAM_IMUX46_1 always
BRAM_R.BRAM_FIFO36_DIADIL15.BRAM_IMUX41_2 always
BRAM_R.BRAM_FIFO36_DIADIU0.BRAM_IMUX8_1 always
BRAM_R.BRAM_FIFO36_DIADIU1.BRAM_IMUX40_3 always
BRAM_R.BRAM_FIFO36_DIADIU2.BRAM_IMUX42_3 always
BRAM_R.BRAM_FIFO36_DIADIU3.BRAM_IMUX44_3 always
BRAM_R.BRAM_FIFO36_DIADIU4.BRAM_IMUX8_4 always
BRAM_R.BRAM_FIFO36_DIADIU5.BRAM_IMUX10_4 always
BRAM_R.BRAM_FIFO36_DIADIU6.BRAM_IMUX12_4 always
BRAM_R.BRAM_FIFO36_DIADIU7.BRAM_IMUX14_4 always
BRAM_R.BRAM_FIFO36_DIADIU8.BRAM_IMUX15_2 always
BRAM_R.BRAM_FIFO36_DIADIU9.BRAM_IMUX41_3 always
BRAM_R.BRAM_FIFO36_DIADIU10.BRAM_IMUX43_3 always
BRAM_R.BRAM_FIFO36_DIADIU11.BRAM_IMUX45_3 always
BRAM_R.BRAM_FIFO36_DIADIU12.BRAM_IMUX9_4 always
BRAM_R.BRAM_FIFO36_DIADIU13.BRAM_IMUX11_4 always
BRAM_R.BRAM_FIFO36_DIADIU14.BRAM_IMUX13_4 always
BRAM_R.BRAM_FIFO36_DIADIU15.BRAM_IMUX15_4 always
BRAM_R.BRAM_FIFO36_DIBDIL0.BRAM_IMUX32_1 always
BRAM_R.BRAM_FIFO36_DIBDIL1.BRAM_IMUX34_0 always
BRAM_R.BRAM_FIFO36_DIBDIL2.BRAM_IMUX36_0 always
BRAM_R.BRAM_FIFO36_DIBDIL3.BRAM_IMUX38_0 always
BRAM_R.BRAM_FIFO36_DIBDIL4.BRAM_IMUX2_1 always
BRAM_R.BRAM_FIFO36_DIBDIL5.BRAM_IMUX4_1 always
BRAM_R.BRAM_FIFO36_DIBDIL6.BRAM_IMUX6_1 always
BRAM_R.BRAM_FIFO36_DIBDIL7.BRAM_IMUX1_2 always
BRAM_R.BRAM_FIFO36_DIBDIL8.BRAM_IMUX33_0 always
BRAM_R.BRAM_FIFO36_DIBDIL9.BRAM_IMUX35_0 always
BRAM_R.BRAM_FIFO36_DIBDIL10.BRAM_IMUX37_0 always
BRAM_R.BRAM_FIFO36_DIBDIL11.BRAM_IMUX39_0 always
BRAM_R.BRAM_FIFO36_DIBDIL12.BRAM_IMUX3_1 always
BRAM_R.BRAM_FIFO36_DIBDIL13.BRAM_IMUX5_1 always
BRAM_R.BRAM_FIFO36_DIBDIL14.BRAM_IMUX7_1 always
BRAM_R.BRAM_FIFO36_DIBDIL15.BRAM_IMUX2_2 always
BRAM_R.BRAM_FIFO36_DIBDIU0.BRAM_IMUX24_1 always
BRAM_R.BRAM_FIFO36_DIBDIU1.BRAM_IMUX1_3 always
BRAM_R.BRAM_FIFO36_DIBDIU2.BRAM_IMUX3_3 always
BRAM_R.BRAM_FIFO36_DIBDIU3.BRAM_IMUX5_3 always
BRAM_R.BRAM_FIFO36_DIBDIU4.BRAM_IMUX16_4 always
BRAM_R.BRAM_FIFO36_DIBDIU5.BRAM_IMUX18_4 always
BRAM_R.BRAM_FIFO36_DIBDIU6.BRAM_IMUX20_4 always
BRAM_R.BRAM_FIFO36_DIBDIU7.BRAM_IMUX22_4 always
BRAM_R.BRAM_FIFO36_DIBDIU8.BRAM_IMUX23_2 always
BRAM_R.BRAM_FIFO36_DIBDIU9.BRAM_IMUX2_3 always
BRAM_R.BRAM_FIFO36_DIBDIU10.BRAM_IMUX4_3 always
BRAM_R.BRAM_FIFO36_DIBDIU11.BRAM_IMUX6_3 always
BRAM_R.BRAM_FIFO36_DIBDIU12.BRAM_IMUX17_4 always
BRAM_R.BRAM_FIFO36_DIBDIU13.BRAM_IMUX19_4 always
BRAM_R.BRAM_FIFO36_DIBDIU14.BRAM_IMUX21_4 always
BRAM_R.BRAM_FIFO36_DIBDIU15.BRAM_IMUX23_4 always
BRAM_R.BRAM_FIFO36_DIPADIPL0.BRAM_IMUX3_2 always
BRAM_R.BRAM_FIFO36_DIPADIPL1.BRAM_IMUX40_1 always
BRAM_R.BRAM_FIFO36_DIPADIPU0.BRAM_IMUX42_2 always
BRAM_R.BRAM_FIFO36_DIPADIPU1.BRAM_IMUX15_3 always
BRAM_R.BRAM_FIFO36_DIPBDIPL0.BRAM_IMUX4_2 always
BRAM_R.BRAM_FIFO36_DIPBDIPL1.BRAM_IMUX1_1 always
BRAM_R.BRAM_FIFO36_DIPBDIPU0.BRAM_IMUX43_2 always
BRAM_R.BRAM_FIFO36_DIPBDIPU1.BRAM_IMUX23_3 always
BRAM_R.BRAM_FIFO36_TSTCNT0.BRAM_IMUX10_0 always
BRAM_R.BRAM_FIFO36_TSTCNT1.BRAM_IMUX11_0 always
BRAM_R.BRAM_FIFO36_TSTCNT2.BRAM_IMUX12_0 always
BRAM_R.BRAM_FIFO36_TSTCNT3.BRAM_IMUX13_0 always
BRAM_R.BRAM_FIFO36_TSTCNT4.BRAM_IMUX14_0 always
BRAM_R.BRAM_FIFO36_TSTCNT5.BRAM_IMUX15_0 always
BRAM_R.BRAM_FIFO36_TSTCNT6.BRAM_IMUX24_4 always
BRAM_R.BRAM_FIFO36_TSTCNT7.BRAM_IMUX25_4 always
BRAM_R.BRAM_FIFO36_TSTCNT8.BRAM_IMUX26_4 always
BRAM_R.BRAM_FIFO36_TSTCNT9.BRAM_IMUX27_4 always
BRAM_R.BRAM_FIFO36_TSTCNT10.BRAM_IMUX28_4 always
BRAM_R.BRAM_FIFO36_TSTCNT11.BRAM_IMUX29_4 always
BRAM_R.BRAM_FIFO36_TSTCNT12.BRAM_IMUX30_4 always
BRAM_R.BRAM_FIFO36_TSTIN0.BRAM_IMUX5_4 always
BRAM_R.BRAM_FIFO36_TSTIN1.BRAM_IMUX16_0 always
BRAM_R.BRAM_FIFO36_TSTIN2.BRAM_IMUX4_4 always
BRAM_R.BRAM_FIFO36_TSTIN3.BRAM_IMUX8_0 always
BRAM_R.BRAM_FIFO36_TSTIN4.BRAM_IMUX41_0 always
BRAM_R.BRAM_FIFO36_TSTRDOS0.BRAM_IMUX18_0 always
BRAM_R.BRAM_FIFO36_TSTRDOS1.BRAM_IMUX19_0 always
BRAM_R.BRAM_FIFO36_TSTRDOS2.BRAM_IMUX20_0 always
BRAM_R.BRAM_FIFO36_TSTRDOS3.BRAM_IMUX21_0 always
BRAM_R.BRAM_FIFO36_TSTRDOS4.BRAM_IMUX22_0 always
BRAM_R.BRAM_FIFO36_TSTRDOS5.BRAM_IMUX23_0 always
BRAM_R.BRAM_FIFO36_TSTRDOS6.BRAM_IMUX32_4 always
BRAM_R.BRAM_FIFO36_TSTRDOS7.BRAM_IMUX33_4 always
BRAM_R.BRAM_FIFO36_TSTRDOS8.BRAM_IMUX34_4 always
BRAM_R.BRAM_FIFO36_TSTRDOS9.BRAM_IMUX35_4 always
BRAM_R.BRAM_FIFO36_TSTRDOS10.BRAM_IMUX36_4 always
BRAM_R.BRAM_FIFO36_TSTRDOS11.BRAM_IMUX37_4 always
BRAM_R.BRAM_FIFO36_TSTRDOS12.BRAM_IMUX38_4 always
BRAM_R.BRAM_FIFO36_TSTWROS0.BRAM_IMUX42_0 always
BRAM_R.BRAM_FIFO36_TSTWROS1.BRAM_IMUX43_0 always
BRAM_R.BRAM_FIFO36_TSTWROS2.BRAM_IMUX44_0 always
BRAM_R.BRAM_FIFO36_TSTWROS3.BRAM_IMUX45_0 always
BRAM_R.BRAM_FIFO36_TSTWROS4.BRAM_IMUX46_0 always
BRAM_R.BRAM_FIFO36_TSTWROS5.BRAM_IMUX47_0 always
BRAM_R.BRAM_FIFO36_TSTWROS6.BRAM_IMUX40_4 always
BRAM_R.BRAM_FIFO36_TSTWROS7.BRAM_IMUX41_4 always
BRAM_R.BRAM_FIFO36_TSTWROS8.BRAM_IMUX42_4 always
BRAM_R.BRAM_FIFO36_TSTWROS9.BRAM_IMUX43_4 always
BRAM_R.BRAM_FIFO36_TSTWROS10.BRAM_IMUX44_4 always
BRAM_R.BRAM_FIFO36_TSTWROS11.BRAM_IMUX45_4 always
BRAM_R.BRAM_FIFO36_TSTWROS12.BRAM_IMUX46_4 always
BRAM_R.BRAM_FIFO36_WEAL0.BRAM_IMUX16_2 always
BRAM_R.BRAM_FIFO36_WEAL1.BRAM_IMUX32_2 always
BRAM_R.BRAM_FIFO36_WEAL2.BRAM_IMUX17_2 always
BRAM_R.BRAM_FIFO36_WEAL3.BRAM_IMUX33_2 always
BRAM_R.BRAM_FIFO36_WEAU0.BRAM_IMUX8_2 always
BRAM_R.BRAM_FIFO36_WEAU1.BRAM_IMUX24_2 always
BRAM_R.BRAM_FIFO36_WEAU2.BRAM_IMUX9_2 always
BRAM_R.BRAM_FIFO36_WEAU3.BRAM_IMUX25_2 always
BRAM_R.BRAM_FIFO36_WEBWEL0.BRAM_IMUX5_2 always
BRAM_R.BRAM_FIFO36_WEBWEL1.BRAM_IMUX21_2 always
BRAM_R.BRAM_FIFO36_WEBWEL2.BRAM_IMUX37_2 always
BRAM_R.BRAM_FIFO36_WEBWEL3.BRAM_BYP3_2 always
BRAM_R.BRAM_FIFO36_WEBWEL4.BRAM_IMUX6_2 always
BRAM_R.BRAM_FIFO36_WEBWEL5.BRAM_IMUX22_2 always
BRAM_R.BRAM_FIFO36_WEBWEL6.BRAM_IMUX38_2 always
BRAM_R.BRAM_FIFO36_WEBWEL7.BRAM_BYP6_2 always
BRAM_R.BRAM_FIFO36_WEBWEU0.BRAM_FAN5_2 always
BRAM_R.BRAM_FIFO36_WEBWEU1.BRAM_IMUX13_2 always
BRAM_R.BRAM_FIFO36_WEBWEU2.BRAM_IMUX29_2 always
BRAM_R.BRAM_FIFO36_WEBWEU3.BRAM_IMUX45_2 always
BRAM_R.BRAM_FIFO36_WEBWEU4.BRAM_FAN1_2 always
BRAM_R.BRAM_FIFO36_WEBWEU5.BRAM_IMUX14_2 always
BRAM_R.BRAM_FIFO36_WEBWEU6.BRAM_IMUX30_2 always
BRAM_R.BRAM_FIFO36_WEBWEU7.BRAM_IMUX46_2 always
BRAM_R.BRAM_RAMB18_CLKARDCLK.BRAM_CLK1_3 always
BRAM_R.BRAM_RAMB18_CLKBWRCLK.BRAM_CLK1_1 always
BRAM_R.BRAM_RAMB18_ENARDEN.BRAM_IMUX10_2 always
BRAM_R.BRAM_RAMB18_ENBWREN.BRAM_IMUX26_2 always
BRAM_R.BRAM_RAMB18_REGCEAREGCE.BRAM_IMUX11_2 always
BRAM_R.BRAM_RAMB18_REGCEB.BRAM_IMUX27_2 always
BRAM_R.BRAM_RAMB18_REGCLKARDRCLK.BRAM_CLK1_4 always
BRAM_R.BRAM_RAMB18_REGCLKB.BRAM_CLK1_0 always
BRAM_R.BRAM_RAMB18_RSTRAMARSTRAM.BRAM_CTRL1_3 always
BRAM_R.BRAM_RAMB18_RSTRAMB.BRAM_CTRL1_1 always
BRAM_R.BRAM_RAMB18_RSTREGARSTREG.BRAM_CTRL1_4 always
BRAM_R.BRAM_RAMB18_RSTREGB.BRAM_CTRL1_0 always
BRAM_R.BRAM_RAMB18_ADDRARDADDR0.BRAM_ADDRARDADDRU1 always
BRAM_R.BRAM_RAMB18_ADDRARDADDR1.BRAM_ADDRARDADDRU2 always
BRAM_R.BRAM_RAMB18_ADDRARDADDR2.BRAM_ADDRARDADDRU3 always
BRAM_R.BRAM_RAMB18_ADDRARDADDR3.BRAM_ADDRARDADDRU4 always
BRAM_R.BRAM_RAMB18_ADDRARDADDR4.BRAM_ADDRARDADDRU5 always
BRAM_R.BRAM_RAMB18_ADDRARDADDR5.BRAM_ADDRARDADDRU6 always
BRAM_R.BRAM_RAMB18_ADDRARDADDR6.BRAM_ADDRARDADDRU7 always
BRAM_R.BRAM_RAMB18_ADDRARDADDR7.BRAM_ADDRARDADDRU8 always
BRAM_R.BRAM_RAMB18_ADDRARDADDR8.BRAM_ADDRARDADDRU9 always
BRAM_R.BRAM_RAMB18_ADDRARDADDR9.BRAM_ADDRARDADDRU10 always
BRAM_R.BRAM_RAMB18_ADDRARDADDR10.BRAM_ADDRARDADDRU11 always
BRAM_R.BRAM_RAMB18_ADDRARDADDR11.BRAM_ADDRARDADDRU12 always
BRAM_R.BRAM_RAMB18_ADDRARDADDR12.BRAM_ADDRARDADDRU13 always
BRAM_R.BRAM_RAMB18_ADDRARDADDR13.BRAM_ADDRARDADDRU14 always
BRAM_R.BRAM_RAMB18_ADDRATIEHIGH0.BRAM_ADDRARDADDRU0 always
BRAM_R.BRAM_RAMB18_ADDRATIEHIGH1.BRAM_IMUX_R_ADDRARDADDRL15 always
BRAM_R.BRAM_RAMB18_ADDRBTIEHIGH0.BRAM_ADDRBWRADDRU0 always
BRAM_R.BRAM_RAMB18_ADDRBTIEHIGH1.BRAM_IMUX_R_ADDRBWRADDRL15 always
BRAM_R.BRAM_RAMB18_ADDRBWRADDR0.BRAM_ADDRBWRADDRU1 always
BRAM_R.BRAM_RAMB18_ADDRBWRADDR1.BRAM_ADDRBWRADDRU2 always
BRAM_R.BRAM_RAMB18_ADDRBWRADDR2.BRAM_ADDRBWRADDRU3 always
BRAM_R.BRAM_RAMB18_ADDRBWRADDR3.BRAM_ADDRBWRADDRU4 always
BRAM_R.BRAM_RAMB18_ADDRBWRADDR4.BRAM_ADDRBWRADDRU5 always
BRAM_R.BRAM_RAMB18_ADDRBWRADDR5.BRAM_ADDRBWRADDRU6 always
BRAM_R.BRAM_RAMB18_ADDRBWRADDR6.BRAM_ADDRBWRADDRU7 always
BRAM_R.BRAM_RAMB18_ADDRBWRADDR7.BRAM_ADDRBWRADDRU8 always
BRAM_R.BRAM_RAMB18_ADDRBWRADDR8.BRAM_ADDRBWRADDRU9 always
BRAM_R.BRAM_RAMB18_ADDRBWRADDR9.BRAM_ADDRBWRADDRU10 always
BRAM_R.BRAM_RAMB18_ADDRBWRADDR10.BRAM_ADDRBWRADDRU11 always
BRAM_R.BRAM_RAMB18_ADDRBWRADDR11.BRAM_ADDRBWRADDRU12 always
BRAM_R.BRAM_RAMB18_ADDRBWRADDR12.BRAM_ADDRBWRADDRU13 always
BRAM_R.BRAM_RAMB18_ADDRBWRADDR13.BRAM_ADDRBWRADDRU14 always
BRAM_R.BRAM_RAMB18_DIADI0.BRAM_IMUX8_1 always
BRAM_R.BRAM_RAMB18_DIADI1.BRAM_IMUX40_3 always
BRAM_R.BRAM_RAMB18_DIADI2.BRAM_IMUX42_3 always
BRAM_R.BRAM_RAMB18_DIADI3.BRAM_IMUX44_3 always
BRAM_R.BRAM_RAMB18_DIADI4.BRAM_IMUX8_4 always
BRAM_R.BRAM_RAMB18_DIADI5.BRAM_IMUX10_4 always
BRAM_R.BRAM_RAMB18_DIADI6.BRAM_IMUX12_4 always
BRAM_R.BRAM_RAMB18_DIADI7.BRAM_IMUX14_4 always
BRAM_R.BRAM_RAMB18_DIADI8.BRAM_IMUX15_2 always
BRAM_R.BRAM_RAMB18_DIADI9.BRAM_IMUX41_3 always
BRAM_R.BRAM_RAMB18_DIADI10.BRAM_IMUX43_3 always
BRAM_R.BRAM_RAMB18_DIADI11.BRAM_IMUX45_3 always
BRAM_R.BRAM_RAMB18_DIADI12.BRAM_IMUX9_4 always
BRAM_R.BRAM_RAMB18_DIADI13.BRAM_IMUX11_4 always
BRAM_R.BRAM_RAMB18_DIADI14.BRAM_IMUX13_4 always
BRAM_R.BRAM_RAMB18_DIADI15.BRAM_IMUX15_4 always
BRAM_R.BRAM_RAMB18_DIBDI0.BRAM_IMUX24_1 always
BRAM_R.BRAM_RAMB18_DIBDI1.BRAM_IMUX1_3 always
BRAM_R.BRAM_RAMB18_DIBDI2.BRAM_IMUX3_3 always
BRAM_R.BRAM_RAMB18_DIBDI3.BRAM_IMUX5_3 always
BRAM_R.BRAM_RAMB18_DIBDI4.BRAM_IMUX16_4 always
BRAM_R.BRAM_RAMB18_DIBDI5.BRAM_IMUX18_4 always
BRAM_R.BRAM_RAMB18_DIBDI6.BRAM_IMUX20_4 always
BRAM_R.BRAM_RAMB18_DIBDI7.BRAM_IMUX22_4 always
BRAM_R.BRAM_RAMB18_DIBDI8.BRAM_IMUX23_2 always
BRAM_R.BRAM_RAMB18_DIBDI9.BRAM_IMUX2_3 always
BRAM_R.BRAM_RAMB18_DIBDI10.BRAM_IMUX4_3 always
BRAM_R.BRAM_RAMB18_DIBDI11.BRAM_IMUX6_3 always
BRAM_R.BRAM_RAMB18_DIBDI12.BRAM_IMUX17_4 always
BRAM_R.BRAM_RAMB18_DIBDI13.BRAM_IMUX19_4 always
BRAM_R.BRAM_RAMB18_DIBDI14.BRAM_IMUX21_4 always
BRAM_R.BRAM_RAMB18_DIBDI15.BRAM_IMUX23_4 always
BRAM_R.BRAM_RAMB18_DIPADIP0.BRAM_IMUX42_2 always
BRAM_R.BRAM_RAMB18_DIPADIP1.BRAM_IMUX15_3 always
BRAM_R.BRAM_RAMB18_DIPBDIP0.BRAM_IMUX43_2 always
BRAM_R.BRAM_RAMB18_DIPBDIP1.BRAM_IMUX23_3 always
BRAM_R.BRAM_RAMB18_WEA0.BRAM_IMUX8_2 always
BRAM_R.BRAM_RAMB18_WEA1.BRAM_IMUX24_2 always
BRAM_R.BRAM_RAMB18_WEA2.BRAM_IMUX9_2 always
BRAM_R.BRAM_RAMB18_WEA3.BRAM_IMUX25_2 always
BRAM_R.BRAM_RAMB18_WEBWE0.BRAM_FAN5_2 always
BRAM_R.BRAM_RAMB18_WEBWE1.BRAM_IMUX13_2 always
BRAM_R.BRAM_RAMB18_WEBWE2.BRAM_IMUX29_2 always
BRAM_R.BRAM_RAMB18_WEBWE3.BRAM_IMUX45_2 always
BRAM_R.BRAM_RAMB18_WEBWE4.BRAM_FAN1_2 always
BRAM_R.BRAM_RAMB18_WEBWE5.BRAM_IMUX14_2 always
BRAM_R.BRAM_RAMB18_WEBWE6.BRAM_IMUX30_2 always
BRAM_R.BRAM_RAMB18_WEBWE7.BRAM_IMUX46_2 always

64
artix7/ppips_int_l.db
View File

@ -1,3 +1,11 @@
INT_L.BYP_ALT0.VCC_WIRE default
INT_L.BYP_ALT1.VCC_WIRE default
INT_L.BYP_ALT2.VCC_WIRE default
INT_L.BYP_ALT3.VCC_WIRE default
INT_L.BYP_ALT4.VCC_WIRE default
INT_L.BYP_ALT5.VCC_WIRE default
INT_L.BYP_ALT6.VCC_WIRE default
INT_L.BYP_ALT7.VCC_WIRE default
INT_L.BYP_BOUNCE0.BYP_ALT0 always
INT_L.BYP_BOUNCE1.BYP_ALT1 always
INT_L.BYP_BOUNCE2.BYP_ALT2 always
@ -14,6 +22,14 @@ INT_L.BYP_L4.BYP_ALT4 always
INT_L.BYP_L5.BYP_ALT5 always
INT_L.BYP_L6.BYP_ALT6 always
INT_L.BYP_L7.BYP_ALT7 always
INT_L.FAN_ALT0.VCC_WIRE default
INT_L.FAN_ALT1.VCC_WIRE default
INT_L.FAN_ALT2.VCC_WIRE default
INT_L.FAN_ALT3.VCC_WIRE default
INT_L.FAN_ALT4.VCC_WIRE default
INT_L.FAN_ALT5.VCC_WIRE default
INT_L.FAN_ALT6.VCC_WIRE default
INT_L.FAN_ALT7.VCC_WIRE default
INT_L.FAN_BOUNCE0.FAN_ALT0 always
INT_L.FAN_BOUNCE1.FAN_ALT1 always
INT_L.FAN_BOUNCE2.FAN_ALT2 always
@ -42,3 +58,51 @@ INT_L.GCLK_L_B10_EAST.GCLK_L_B10 always
INT_L.GCLK_L_B10_WEST.GCLK_L_B10 always
INT_L.GCLK_L_B11_EAST.GCLK_L_B11 always
INT_L.GCLK_L_B11_WEST.GCLK_L_B11 always
INT_L.IMUX_L0.VCC_WIRE default
INT_L.IMUX_L1.VCC_WIRE default
INT_L.IMUX_L2.VCC_WIRE default
INT_L.IMUX_L3.VCC_WIRE default
INT_L.IMUX_L4.VCC_WIRE default
INT_L.IMUX_L5.VCC_WIRE default
INT_L.IMUX_L6.VCC_WIRE default
INT_L.IMUX_L7.VCC_WIRE default
INT_L.IMUX_L8.VCC_WIRE default
INT_L.IMUX_L9.VCC_WIRE default
INT_L.IMUX_L10.VCC_WIRE default
INT_L.IMUX_L11.VCC_WIRE default
INT_L.IMUX_L12.VCC_WIRE default
INT_L.IMUX_L13.VCC_WIRE default
INT_L.IMUX_L14.VCC_WIRE default
INT_L.IMUX_L15.VCC_WIRE default
INT_L.IMUX_L16.VCC_WIRE default
INT_L.IMUX_L17.VCC_WIRE default
INT_L.IMUX_L18.VCC_WIRE default
INT_L.IMUX_L19.VCC_WIRE default
INT_L.IMUX_L20.VCC_WIRE default
INT_L.IMUX_L21.VCC_WIRE default
INT_L.IMUX_L22.VCC_WIRE default
INT_L.IMUX_L23.VCC_WIRE default
INT_L.IMUX_L24.VCC_WIRE default
INT_L.IMUX_L25.VCC_WIRE default
INT_L.IMUX_L26.VCC_WIRE default
INT_L.IMUX_L27.VCC_WIRE default
INT_L.IMUX_L28.VCC_WIRE default
INT_L.IMUX_L29.VCC_WIRE default
INT_L.IMUX_L30.VCC_WIRE default
INT_L.IMUX_L31.VCC_WIRE default
INT_L.IMUX_L32.VCC_WIRE default
INT_L.IMUX_L33.VCC_WIRE default
INT_L.IMUX_L34.VCC_WIRE default
INT_L.IMUX_L35.VCC_WIRE default
INT_L.IMUX_L36.VCC_WIRE default
INT_L.IMUX_L37.VCC_WIRE default
INT_L.IMUX_L38.VCC_WIRE default
INT_L.IMUX_L39.VCC_WIRE default
INT_L.IMUX_L40.VCC_WIRE default
INT_L.IMUX_L41.VCC_WIRE default
INT_L.IMUX_L42.VCC_WIRE default
INT_L.IMUX_L43.VCC_WIRE default
INT_L.IMUX_L44.VCC_WIRE default
INT_L.IMUX_L45.VCC_WIRE default
INT_L.IMUX_L46.VCC_WIRE default
INT_L.IMUX_L47.VCC_WIRE default

64
artix7/ppips_int_r.db
View File

@ -1,3 +1,11 @@
INT_R.BYP_ALT0.VCC_WIRE default
INT_R.BYP_ALT1.VCC_WIRE default
INT_R.BYP_ALT2.VCC_WIRE default
INT_R.BYP_ALT3.VCC_WIRE default
INT_R.BYP_ALT4.VCC_WIRE default
INT_R.BYP_ALT5.VCC_WIRE default
INT_R.BYP_ALT6.VCC_WIRE default
INT_R.BYP_ALT7.VCC_WIRE default
INT_R.BYP_BOUNCE0.BYP_ALT0 always
INT_R.BYP_BOUNCE1.BYP_ALT1 always
INT_R.BYP_BOUNCE2.BYP_ALT2 always
@ -6,6 +14,14 @@ INT_R.BYP_BOUNCE4.BYP_ALT4 always
INT_R.BYP_BOUNCE5.BYP_ALT5 always
INT_R.BYP_BOUNCE6.BYP_ALT6 always
INT_R.BYP_BOUNCE7.BYP_ALT7 always
INT_R.FAN_ALT0.VCC_WIRE default
INT_R.FAN_ALT1.VCC_WIRE default
INT_R.FAN_ALT2.VCC_WIRE default
INT_R.FAN_ALT3.VCC_WIRE default
INT_R.FAN_ALT4.VCC_WIRE default
INT_R.FAN_ALT5.VCC_WIRE default
INT_R.FAN_ALT6.VCC_WIRE default
INT_R.FAN_ALT7.VCC_WIRE default
INT_R.FAN_BOUNCE0.FAN_ALT0 always
INT_R.FAN_BOUNCE1.FAN_ALT1 always
INT_R.FAN_BOUNCE2.FAN_ALT2 always
@ -42,3 +58,51 @@ INT_R.FAN4.FAN_ALT4 always
INT_R.FAN5.FAN_ALT5 always
INT_R.FAN6.FAN_ALT6 always
INT_R.FAN7.FAN_ALT7 always
INT_R.IMUX0.VCC_WIRE default
INT_R.IMUX1.VCC_WIRE default
INT_R.IMUX2.VCC_WIRE default
INT_R.IMUX3.VCC_WIRE default
INT_R.IMUX4.VCC_WIRE default
INT_R.IMUX5.VCC_WIRE default
INT_R.IMUX6.VCC_WIRE default
INT_R.IMUX7.VCC_WIRE default
INT_R.IMUX8.VCC_WIRE default
INT_R.IMUX9.VCC_WIRE default
INT_R.IMUX10.VCC_WIRE default
INT_R.IMUX11.VCC_WIRE default
INT_R.IMUX12.VCC_WIRE default
INT_R.IMUX13.VCC_WIRE default
INT_R.IMUX14.VCC_WIRE default
INT_R.IMUX15.VCC_WIRE default
INT_R.IMUX16.VCC_WIRE default
INT_R.IMUX17.VCC_WIRE default
INT_R.IMUX18.VCC_WIRE default
INT_R.IMUX19.VCC_WIRE default
INT_R.IMUX20.VCC_WIRE default
INT_R.IMUX21.VCC_WIRE default
INT_R.IMUX22.VCC_WIRE default
INT_R.IMUX23.VCC_WIRE default
INT_R.IMUX24.VCC_WIRE default
INT_R.IMUX25.VCC_WIRE default
INT_R.IMUX26.VCC_WIRE default
INT_R.IMUX27.VCC_WIRE default
INT_R.IMUX28.VCC_WIRE default
INT_R.IMUX29.VCC_WIRE default
INT_R.IMUX30.VCC_WIRE default
INT_R.IMUX31.VCC_WIRE default
INT_R.IMUX32.VCC_WIRE default
INT_R.IMUX33.VCC_WIRE default
INT_R.IMUX34.VCC_WIRE default
INT_R.IMUX35.VCC_WIRE default
INT_R.IMUX36.VCC_WIRE default
INT_R.IMUX37.VCC_WIRE default
INT_R.IMUX38.VCC_WIRE default
INT_R.IMUX39.VCC_WIRE default
INT_R.IMUX40.VCC_WIRE default
INT_R.IMUX41.VCC_WIRE default
INT_R.IMUX42.VCC_WIRE default
INT_R.IMUX43.VCC_WIRE default
INT_R.IMUX44.VCC_WIRE default
INT_R.IMUX45.VCC_WIRE default
INT_R.IMUX46.VCC_WIRE default
INT_R.IMUX47.VCC_WIRE default

233
artix7/segbits_int_l.db
View File

@ -222,6 +222,38 @@ INT_L.CLK_L1.GCLK_L_B11_WEST 00_27 !00_29 01_25 01_26 01_29
INT_L.CLK_L1.ER1END1 00_27 00_29 01_25 01_26 !01_29
INT_L.CLK_L1.SR1END1 !00_27 !00_29 01_25 01_26 !01_29
INT_L.CLK_L1.WR1END1 00_27 !00_29 01_25 !01_26 !01_29
INT_L.CTRL_L0.BYP_BOUNCE4 !00_35 !00_39 01_37 01_38 !01_40
INT_L.CTRL_L0.FAN_BOUNCE1 !00_35 00_39 01_37 !01_38 !01_40
INT_L.CTRL_L0.EE4END2 !00_35 00_38 00_39 !01_38 !01_40
INT_L.CTRL_L0.ER1END2 !00_35 !00_39 01_33 01_38 !01_40
INT_L.CTRL_L0.GFAN0 00_35 00_39 01_37 01_38 !01_40
INT_L.CTRL_L0.GFAN1 !00_35 00_39 01_37 01_38 01_40
INT_L.CTRL_L0.NE6END2 !00_35 00_39 01_33 01_38 01_40
INT_L.CTRL_L0.NN6END2 00_35 00_39 01_33 01_38 !01_40
INT_L.CTRL_L0.NR1END2 00_34 !00_35 00_39 01_38 01_40
INT_L.CTRL_L0.NW6END2 00_34 00_35 00_39 01_38 !01_40
INT_L.CTRL_L0.SE6END2 !00_35 00_38 !00_39 01_38 !01_40
INT_L.CTRL_L0.SR1END2 !00_35 00_38 00_39 01_38 01_40
INT_L.CTRL_L0.SS6END2 00_35 00_38 00_39 01_38 !01_40
INT_L.CTRL_L0.SW6END1 00_34 !00_35 !00_39 01_38 !01_40
INT_L.CTRL_L0.WR1END2 00_34 !00_35 00_39 !01_38 !01_40
INT_L.CTRL_L0.WW4END2 !00_35 00_39 01_33 !01_38 !01_40
INT_L.CTRL_L1.BYP_BOUNCE4 !00_37 00_42 01_32 !01_36 !01_41
INT_L.CTRL_L1.FAN_BOUNCE1 !00_37 !00_42 01_32 !01_36 01_41
INT_L.CTRL_L1.EE4END2 !00_37 00_41 !00_42 !01_36 01_41
INT_L.CTRL_L1.ER1END2 00_33 !00_37 00_42 !01_36 !01_41
INT_L.CTRL_L1.GFAN0 !00_37 00_42 01_32 01_36 01_41
INT_L.CTRL_L1.GFAN1 00_37 00_42 01_32 !01_36 01_41
INT_L.CTRL_L1.NE6END2 00_33 00_37 00_42 !01_36 01_41
INT_L.CTRL_L1.NN6END2 00_33 !00_37 00_42 01_36 01_41
INT_L.CTRL_L1.NR1END2 00_37 00_42 01_34 !01_36 01_41
INT_L.CTRL_L1.NW6END2 !00_37 00_42 01_34 01_36 01_41
INT_L.CTRL_L1.SE6END2 !00_37 00_41 00_42 !01_36 !01_41
INT_L.CTRL_L1.SR1END2 00_37 00_41 00_42 !01_36 01_41
INT_L.CTRL_L1.SS6END2 !00_37 00_41 00_42 01_36 01_41
INT_L.CTRL_L1.SW6END1 !00_37 00_42 01_34 !01_36 !01_41
INT_L.CTRL_L1.WR1END2 !00_37 !00_42 01_34 !01_36 01_41
INT_L.CTRL_L1.WW4END2 00_33 !00_37 !00_42 !01_36 01_41
INT_L.EL1BEG_N3.LOGIC_OUTS_L0 11_05 14_05
INT_L.EL1BEG_N3.LOGIC_OUTS_L4 07_04 14_05
INT_L.EL1BEG_N3.LOGIC_OUTS_L8 10_05 14_05
@ -277,6 +309,7 @@ INT_L.FAN_ALT0.WL1END_N1_3 16_00 !22_00 23_00 24_00 25_00
INT_L.FAN_ALT0.WW2END_N0_3 16_00 !22_00 !23_00 !24_00 25_00
INT_L.FAN_ALT0.EE2END0 19_01 !22_00 !23_00 !24_00 25_00
INT_L.FAN_ALT0.EL1END0 17_00 !22_00 23_00 24_00 25_00
INT_L.FAN_ALT0.GFAN0 21_00 !22_00 !23_00 !24_00 25_00
INT_L.FAN_ALT0.NE2END0 18_01 !22_00 !23_00 24_00 !25_00
INT_L.FAN_ALT0.NL1END0 19_01 !22_00 23_00 24_00 25_00
INT_L.FAN_ALT0.NN2END0 18_01 !22_00 !23_00 !24_00 25_00
@ -296,6 +329,7 @@ INT_L.FAN_ALT1.NL1BEG_N3 19_49 !22_48 23_48 24_48 25_48
INT_L.FAN_ALT1.EE2END3 19_49 !22_48 !23_48 !24_48 25_48
INT_L.FAN_ALT1.EL1END3 17_48 !22_48 23_48 24_48 25_48
INT_L.FAN_ALT1.ER1END2 16_48 22_48 !23_48 24_48 25_48
INT_L.FAN_ALT1.GFAN1 21_48 !22_48 !23_48 !24_48 25_48
INT_L.FAN_ALT1.NE2END3 18_49 !22_48 !23_48 24_48 !25_48
INT_L.FAN_ALT1.NN2END3 18_49 !22_48 !23_48 !24_48 25_48
INT_L.FAN_ALT1.NR1END3 18_49 22_48 !23_48 24_48 25_48
@ -319,7 +353,7 @@ INT_L.FAN_ALT2.SR1BEG_S0 19_17 22_16 !23_16 24_16 25_16
INT_L.FAN_ALT2.EE2END1 19_17 !22_16 !23_16 !24_16 25_16
INT_L.FAN_ALT2.EL1END1 17_16 !22_16 23_16 24_16 25_16
INT_L.FAN_ALT2.ER1END0 16_16 22_16 !23_16 24_16 25_16
INT_L.FAN_ALT2.GFAN0 21_16 !22_16 !23_16 !24_16 25_16
INT_L.FAN_ALT2.GFAN0 !00_10 !00_11 !01_09 !01_10 01_14 21_16 !22_16 !23_16 !24_16 25_16
INT_L.FAN_ALT2.NE2END1 18_17 !22_16 !23_16 24_16 !25_16
INT_L.FAN_ALT2.NL1END1 19_17 !22_16 23_16 24_16 25_16
INT_L.FAN_ALT2.NN2END1 18_17 !22_16 !23_16 !24_16 25_16
@ -344,6 +378,7 @@ INT_L.FAN_ALT3.NW2END_S0_0 19_57 !22_56 !23_56 24_56 !25_56
INT_L.FAN_ALT3.EE2END3 16_56 !22_56 !23_56 !24_56 25_56
INT_L.FAN_ALT3.EL1END3 16_56 !22_56 23_56 24_56 25_56
INT_L.FAN_ALT3.ER1END3 17_56 22_56 !23_56 24_56 25_56
INT_L.FAN_ALT3.GFAN1 21_56 !22_56 !23_56 !24_56 25_56
INT_L.FAN_ALT3.NE2END3 17_56 !22_56 !23_56 24_56 !25_56
INT_L.FAN_ALT3.NN2END3 17_56 !22_56 !23_56 !24_56 25_56
INT_L.FAN_ALT3.NR1END3 18_57 22_56 !23_56 24_56 25_56
@ -355,6 +390,8 @@ INT_L.FAN_ALT3.SW2END3 18_57 !22_56 !23_56 24_56 !25_56
INT_L.FAN_ALT3.WL1END3 17_56 !22_56 23_56 24_56 25_56
INT_L.FAN_ALT3.WR1END3 16_56 22_56 !23_56 24_56 25_56
INT_L.FAN_ALT3.WW2END3 19_57 !22_56 !23_56 !24_56 25_56
INT_L.FAN_ALT4.BYP_BOUNCE_N3_3 20_08 !22_08 !23_08 !24_08 25_08
INT_L.FAN_ALT4.BYP_BOUNCE_N3_7 20_08 !22_08 !23_08 24_08 !25_08
INT_L.FAN_ALT4.FAN_BOUNCE2 20_08 22_08 !23_08 24_08 25_08
INT_L.FAN_ALT4.FAN_BOUNCE7 20_08 !22_08 23_08 24_08 25_08
INT_L.FAN_ALT4.LOGIC_OUTS_L4 21_08 22_08 !23_08 24_08 25_08
@ -364,6 +401,7 @@ INT_L.FAN_ALT4.SR1BEG_S0 19_09 22_08 !23_08 24_08 25_08
INT_L.FAN_ALT4.EE2END0 16_08 !22_08 !23_08 !24_08 25_08
INT_L.FAN_ALT4.EL1END0 16_08 !22_08 23_08 24_08 25_08
INT_L.FAN_ALT4.ER1END0 17_08 22_08 !23_08 24_08 25_08
INT_L.FAN_ALT4.GFAN0 21_08 !22_08 !23_08 !24_08 25_08
INT_L.FAN_ALT4.NE2END0 17_08 !22_08 !23_08 24_08 !25_08
INT_L.FAN_ALT4.NL1END1 19_09 !22_08 23_08 24_08 25_08
INT_L.FAN_ALT4.NN2END0 17_08 !22_08 !23_08 !24_08 25_08
@ -376,6 +414,7 @@ INT_L.FAN_ALT4.SW2END0 18_09 !22_08 !23_08 24_08 !25_08
INT_L.FAN_ALT4.WL1END0 17_08 !22_08 23_08 24_08 25_08
INT_L.FAN_ALT4.WR1END0 16_08 22_08 !23_08 24_08 25_08
INT_L.FAN_ALT4.WW2END0 19_09 !22_08 !23_08 !24_08 25_08
INT_L.FAN_ALT5.BYP_BOUNCE1 20_40 !22_40 !23_40 24_40 !25_40
INT_L.FAN_ALT5.BYP_BOUNCE5 20_40 !22_40 !23_40 !24_40 25_40
INT_L.FAN_ALT5.FAN_BOUNCE_S3_0 20_40 22_40 !23_40 24_40 25_40
INT_L.FAN_ALT5.FAN_BOUNCE1 20_40 !22_40 23_40 24_40 25_40
@ -386,6 +425,7 @@ INT_L.FAN_ALT5.NL1BEG_N3 19_41 !22_40 23_40 24_40 25_40
INT_L.FAN_ALT5.EE2END2 16_40 !22_40 !23_40 !24_40 25_40
INT_L.FAN_ALT5.EL1END2 16_40 !22_40 23_40 24_40 25_40
INT_L.FAN_ALT5.ER1END2 17_40 22_40 !23_40 24_40 25_40
INT_L.FAN_ALT5.GFAN1 21_40 !22_40 !23_40 !24_40 25_40
INT_L.FAN_ALT5.NE2END2 17_40 !22_40 !23_40 24_40 !25_40
INT_L.FAN_ALT5.NN2END2 17_40 !22_40 !23_40 !24_40 25_40
INT_L.FAN_ALT5.NR1END2 18_41 22_40 !23_40 24_40 25_40
@ -432,7 +472,7 @@ INT_L.FAN_ALT7.LOGIC_OUTS_L20 21_32 !22_32 !23_32 24_32 !25_32
INT_L.FAN_ALT7.EE2END2 19_33 !22_32 !23_32 !24_32 25_32
INT_L.FAN_ALT7.EL1END2 17_32 !22_32 23_32 24_32 25_32
INT_L.FAN_ALT7.ER1END1 16_32 22_32 !23_32 24_32 25_32
INT_L.FAN_ALT7.GFAN1 01_39 21_32 !22_32 !23_32 !24_32 25_32
INT_L.FAN_ALT7.GFAN1 21_32 !22_32 !23_32 !24_32 25_32
INT_L.FAN_ALT7.NE2END2 18_33 !22_32 !23_32 24_32 !25_32
INT_L.FAN_ALT7.NL1END2 19_33 !22_32 23_32 24_32 25_32
INT_L.FAN_ALT7.NN2END2 18_33 !22_32 !23_32 !24_32 25_32
@ -1598,6 +1638,66 @@ INT_L.IMUX_L47.SS2END3 17_62 !22_62 !23_62 !24_62 25_62
INT_L.IMUX_L47.SW2END3 17_62 !22_62 !23_62 24_62 !25_62
INT_L.IMUX_L47.WL1END3 18_63 !22_62 23_62 24_62 25_62
INT_L.IMUX_L47.WW2END3 16_62 !22_62 !23_62 !24_62 25_62
INT_L.LV_L0.LV_L18 00_09 01_06
INT_L.LV_L0.SR1BEG_S0 00_05 01_05
INT_L.LV_L0.ER1END0 01_04 01_05
INT_L.LV_L0.LH0 00_02 01_06
INT_L.LV_L0.LH6 01_04 01_06
INT_L.LV_L0.LH12 00_05 01_06
INT_L.LV_L0.NN6END0 00_07 00_09
INT_L.LV_L0.NR1END0 00_02 01_05
INT_L.LV_L0.NW6END0 00_07 01_04
INT_L.LV_L0.SW6END0 00_09 01_05
INT_L.LV_L0.WR1END0 00_02 00_07
INT_L.LV_L0.WW4END0 00_05 00_07
INT_L.LV_L18.LV_L0 01_00 01_01
INT_L.LV_L18.SR1BEG_S0 00_03 01_08
INT_L.LV_L18.ER1END0 00_03 00_06
INT_L.LV_L18.LH0 00_01 01_02
INT_L.LV_L18.LH6 00_06 01_02
INT_L.LV_L18.LH12 01_02 01_08
INT_L.LV_L18.NN6END0 00_03 01_00
INT_L.LV_L18.NR1END0 00_01 00_03
INT_L.LV_L18.NW6END0 00_06 01_01
INT_L.LV_L18.SW6END0 01_00 01_02
INT_L.LV_L18.WR1END0 00_01 01_01
INT_L.LV_L18.WW4END0 01_01 01_08
INT_L.LVB_L0.LV_L0 00_47 01_52
INT_L.LVB_L0.LV_L18 01_42 01_52
INT_L.LVB_L0.LVB_L12 00_51 00_54
INT_L.LVB_L0.LH0 00_43 00_51
INT_L.LVB_L0.LH6 00_51 00_53
INT_L.LVB_L0.LH12 00_50 00_51
INT_L.LVB_L0.NE2END2 00_53 01_52
INT_L.LVB_L0.NN6END3 00_50 01_50
INT_L.LVB_L0.NR1END3 00_47 01_50
INT_L.LVB_L0.NW2END2 00_43 01_52
INT_L.LVB_L0.NW6END3 00_43 01_50
INT_L.LVB_L0.SE2END3 00_51 01_42
INT_L.LVB_L0.SE6END3 00_54 01_50
INT_L.LVB_L0.SW2END2 00_50 01_52
INT_L.LVB_L0.SW2END3 00_47 00_51
INT_L.LVB_L0.SW6END2 00_54 01_52
INT_L.LVB_L0.WR1END3 01_42 01_50
INT_L.LVB_L0.WW4END3 00_53 01_50
INT_L.LVB_L12.LV_L0 00_45 01_44
INT_L.LVB_L12.LV_L18 00_45 01_48
INT_L.LVB_L12.LVB_L0 00_45 01_45
INT_L.LVB_L12.LH0 00_46 00_49
INT_L.LVB_L12.LH6 00_46 01_49
INT_L.LVB_L12.LH12 00_46 01_53
INT_L.LVB_L12.NE2END2 00_45 01_49
INT_L.LVB_L12.NN6END3 01_46 01_53
INT_L.LVB_L12.NR1END3 01_44 01_46
INT_L.LVB_L12.NW2END2 00_45 00_49
INT_L.LVB_L12.NW6END3 00_49 01_46
INT_L.LVB_L12.SE2END3 00_46 01_48
INT_L.LVB_L12.SE6END3 00_46 01_45
INT_L.LVB_L12.SW2END2 00_45 01_53
INT_L.LVB_L12.SW2END3 00_46 01_44
INT_L.LVB_L12.SW6END2 01_45 01_46
INT_L.LVB_L12.WR1END3 01_46 01_48
INT_L.LVB_L12.WW4END3 01_46 01_49
INT_L.NL1BEG_N3.LOGIC_OUTS_L0 11_01 14_01
INT_L.NL1BEG_N3.LOGIC_OUTS_L4 07_00 14_01
INT_L.NL1BEG_N3.LOGIC_OUTS_L8 10_01 14_01
@ -1764,8 +1864,10 @@ INT_L.EE4BEG0.LOGIC_OUTS_L8 03_08 07_09
INT_L.EE4BEG0.LOGIC_OUTS_L12 03_08 04_10
INT_L.EE4BEG0.LOGIC_OUTS_L18 06_08 07_09
INT_L.EE4BEG0.LOGIC_OUTS_L22 04_10 06_08
INT_L.EE4BEG0.LV_L0 04_10 05_08
INT_L.EE4BEG0.EE2END0 03_08 03_09
INT_L.EE4BEG0.EE4END0 03_09 05_08
INT_L.EE4BEG0.LH12 05_08 07_09
INT_L.EE4BEG0.NE2END0 02_09 04_09
INT_L.EE4BEG0.NE6END0 04_09 05_08
INT_L.EE4BEG0.NN2END0 03_08 04_09
@ -1782,8 +1884,10 @@ INT_L.EE4BEG1.LOGIC_OUTS_L9 03_24 04_26
INT_L.EE4BEG1.LOGIC_OUTS_L13 03_24 07_25
INT_L.EE4BEG1.LOGIC_OUTS_L19 04_26 06_24
INT_L.EE4BEG1.LOGIC_OUTS_L23 06_24 07_25
INT_L.EE4BEG1.LV_L9 04_26 05_24
INT_L.EE4BEG1.EE2END1 03_24 03_25
INT_L.EE4BEG1.EE4END1 03_25 05_24
INT_L.EE4BEG1.LH6 05_24 07_25
INT_L.EE4BEG1.NE2END1 02_25 04_25
INT_L.EE4BEG1.NE6END1 04_25 05_24
INT_L.EE4BEG1.NN2END1 03_24 04_25
@ -1793,12 +1897,15 @@ INT_L.EE4BEG1.SE6END1 03_25 06_24
INT_L.EE4BEG1.SS2END1 03_24 05_27
INT_L.EE4BEG1.SS6END1 05_27 06_24
INT_L.EE4BEG1.SW2END1 02_25 05_27
INT_L.EE4BEG1.SW6END1 05_24 05_27
INT_L.EE4BEG2.LOGIC_OUTS_L2 02_41 04_42
INT_L.EE4BEG2.LOGIC_OUTS_L6 02_41 07_41
INT_L.EE4BEG2.LOGIC_OUTS_L10 03_40 07_41
INT_L.EE4BEG2.LOGIC_OUTS_L14 03_40 04_42
INT_L.EE4BEG2.LOGIC_OUTS_L16 06_40 07_41
INT_L.EE4BEG2.LOGIC_OUTS_L20 04_42 06_40
INT_L.EE4BEG2.LVB_L0 04_42 05_40
INT_L.EE4BEG2.LVB_L12 05_40 07_41
INT_L.EE4BEG2.EE2END2 03_40 03_41
INT_L.EE4BEG2.EE4END2 03_41 05_40
INT_L.EE4BEG2.NE2END2 02_41 04_41
@ -1810,14 +1917,17 @@ INT_L.EE4BEG2.SE6END2 03_41 06_40
INT_L.EE4BEG2.SS2END2 03_40 05_43
INT_L.EE4BEG2.SS6END2 05_43 06_40
INT_L.EE4BEG2.SW2END2 02_41 05_43
INT_L.EE4BEG2.SW6END2 05_40 05_43
INT_L.EE4BEG3.LOGIC_OUTS_L3 02_57 07_57
INT_L.EE4BEG3.LOGIC_OUTS_L7 02_57 04_58
INT_L.EE4BEG3.LOGIC_OUTS_L11 03_56 04_58
INT_L.EE4BEG3.LOGIC_OUTS_L15 03_56 07_57
INT_L.EE4BEG3.LOGIC_OUTS_L17 04_58 06_56
INT_L.EE4BEG3.LOGIC_OUTS_L21 06_56 07_57
INT_L.EE4BEG3.LV_L18 05_56 07_57
INT_L.EE4BEG3.EE2END3 03_56 03_57
INT_L.EE4BEG3.EE4END3 03_57 05_56
INT_L.EE4BEG3.LH0 04_58 05_56
INT_L.EE4BEG3.NE2END3 02_57 04_57
INT_L.EE4BEG3.NE6END3 04_57 05_56
INT_L.EE4BEG3.NN2END3 03_56 04_57
@ -1827,6 +1937,7 @@ INT_L.EE4BEG3.SE6END3 03_57 06_56
INT_L.EE4BEG3.SS2END3 03_56 05_59
INT_L.EE4BEG3.SS6END3 05_59 06_56
INT_L.EE4BEG3.SW2END3 02_57 05_59
INT_L.EE4BEG3.SW6END3 05_56 05_59
INT_L.EL1BEG0.LOGIC_OUTS_L1 07_20 14_21
INT_L.EL1BEG0.LOGIC_OUTS_L5 11_21 14_21
INT_L.EL1BEG0.LOGIC_OUTS_L9 10_21 13_21
@ -1947,8 +2058,62 @@ INT_L.ER1BEG3.SW2END2 07_42 15_43
INT_L.ER1BEG3.SW6END2 07_42 12_43
INT_L.ER1BEG3.WW2END2 11_43 15_43
INT_L.ER1BEG3.WW4END3 11_43 12_43
INT_L.GFAN0.BYP_BOUNCE1 00_10 00_11 !01_09 01_10 01_14
INT_L.GFAN0.GCLK_L_B0 00_10 00_11 !01_09 01_10 01_12
INT_L.GFAN0.GCLK_L_B1 !00_10 00_11 01_09 01_10 01_12
INT_L.GFAN0.GCLK_L_B2 !00_10 !00_11 !01_09 01_10 01_12
INT_L.GFAN0.GCLK_L_B3 !00_10 00_11 !01_09 !01_10 01_12
INT_L.GFAN0.GCLK_L_B4 00_10 00_11 !01_09 01_10 01_18
INT_L.GFAN0.GCLK_L_B5 !00_10 00_11 01_09 01_10 01_18
INT_L.GFAN0.GCLK_L_B6_WEST !00_10 !00_11 !01_09 01_10 01_18
INT_L.GFAN0.GCLK_L_B7_WEST !00_10 00_11 !01_09 !01_10 01_18
INT_L.GFAN0.GCLK_L_B8_WEST 00_10 00_11 !01_09 01_10 01_16
INT_L.GFAN0.GCLK_L_B9_WEST !00_10 00_11 01_09 01_10 01_16
INT_L.GFAN0.GCLK_L_B10_WEST !00_10 !00_11 !01_09 01_10 01_16
INT_L.GFAN0.GCLK_L_B11_WEST !00_10 00_11 !01_09 !01_10 01_16
INT_L.GFAN0.GND_WIRE !00_10 00_11 !01_09 !01_10 01_14
INT_L.GFAN0.NR1END1 !00_10 00_11 01_09 01_10 01_14
INT_L.GFAN0.WW4END1 !00_10 !00_11 !01_09 01_10 01_14
INT_L.GFAN1.BYP_BOUNCE1 00_14 00_17 00_18 !00_19 01_13
INT_L.GFAN1.GCLK_L_B0 00_13 00_14 00_18 !00_19 01_13
INT_L.GFAN1.GCLK_L_B1 00_13 00_14 !00_18 00_19 01_13
INT_L.GFAN1.GCLK_L_B2 00_13 00_14 !00_18 !00_19 !01_13
INT_L.GFAN1.GCLK_L_B3 00_13 !00_14 !00_18 !00_19 01_13
INT_L.GFAN1.GCLK_L_B4 00_14 00_15 00_18 !00_19 01_13
INT_L.GFAN1.GCLK_L_B5 00_14 00_15 !00_18 00_19 01_13
INT_L.GFAN1.GCLK_L_B6_WEST 00_14 00_15 !00_18 !00_19 !01_13
INT_L.GFAN1.GCLK_L_B7_WEST !00_14 00_15 !00_18 !00_19 01_13
INT_L.GFAN1.GCLK_L_B8_WEST 00_14 00_18 !00_19 01_13 01_17
INT_L.GFAN1.GCLK_L_B9_WEST 00_14 !00_18 00_19 01_13 01_17
INT_L.GFAN1.GCLK_L_B10_WEST 00_14 !00_18 !00_19 !01_13 01_17
INT_L.GFAN1.GCLK_L_B11_WEST !00_14 !00_18 !00_19 01_13 01_17
INT_L.GFAN1.GND_WIRE !00_14 00_17 !00_18 !00_19 01_13
INT_L.GFAN1.NR1END1 00_14 00_17 !00_18 00_19 01_13
INT_L.GFAN1.WW4END1 00_14 00_17 !00_18 !00_19 !01_13
INT_L.LH0.LV_L0 01_56 01_58
INT_L.LH0.LV_L9 00_59 01_56
INT_L.LH0.LV_L18 01_56 01_61
INT_L.LH0.EE4END3 00_58 01_61
INT_L.LH0.ER1END3 00_57 01_54
INT_L.LH0.LH12 01_54 01_56
INT_L.LH0.NE2END3 00_58 00_59
INT_L.LH0.NE6END3 00_58 01_58
INT_L.LH0.NW2END3 00_58 01_54
INT_L.LH0.SR1END3 00_57 00_59
INT_L.LH0.SS6END3 00_57 01_58
INT_L.LH0.SW6END3 00_57 01_61
INT_L.LH12.LV_L0 00_55 00_62
INT_L.LH12.LV_L9 00_62 01_57
INT_L.LH12.LV_L18 00_62 01_62
INT_L.LH12.EE4END3 01_60 01_62
INT_L.LH12.ER1END3 00_63 01_60
INT_L.LH12.LH0 00_61 00_63
INT_L.LH12.NE2END3 01_57 01_60
INT_L.LH12.NE6END3 00_55 01_60
INT_L.LH12.NW2END3 00_62 00_63
INT_L.LH12.SR1END3 00_61 01_57
INT_L.LH12.SS6END3 00_55 00_61
INT_L.LH12.SW6END3 00_61 01_62
INT_L.NE2BEG0.LOGIC_OUTS_L0 09_05 15_04
INT_L.NE2BEG0.LOGIC_OUTS_L4 09_04 15_04
INT_L.NE2BEG0.LOGIC_OUTS_L8 11_04 15_04
@ -2035,9 +2200,11 @@ INT_L.NE6BEG0.LOGIC_OUTS_L8 03_04 04_06
INT_L.NE6BEG0.LOGIC_OUTS_L12 03_04 07_05
INT_L.NE6BEG0.LOGIC_OUTS_L18 04_06 06_04
INT_L.NE6BEG0.LOGIC_OUTS_L22 06_04 07_05
INT_L.NE6BEG0.LV_L0 04_06 05_04
INT_L.NE6BEG0.WW2END_N0_3 03_04 04_05
INT_L.NE6BEG0.EE2END0 03_04 05_07
INT_L.NE6BEG0.EE4END0 05_04 05_07
INT_L.NE6BEG0.LH12 05_04 07_05
INT_L.NE6BEG0.NE2END0 02_05 03_05
INT_L.NE6BEG0.NE6END0 03_05 05_04
INT_L.NE6BEG0.NN2END0 03_04 03_05
@ -2053,8 +2220,10 @@ INT_L.NE6BEG1.LOGIC_OUTS_L9 03_20 07_21
INT_L.NE6BEG1.LOGIC_OUTS_L13 03_20 04_22
INT_L.NE6BEG1.LOGIC_OUTS_L19 06_20 07_21
INT_L.NE6BEG1.LOGIC_OUTS_L23 04_22 06_20
INT_L.NE6BEG1.LV_L9 04_22 05_20
INT_L.NE6BEG1.EE2END1 03_20 05_23
INT_L.NE6BEG1.EE4END1 05_20 05_23
INT_L.NE6BEG1.LH6 05_20 07_21
INT_L.NE6BEG1.NE2END1 02_21 03_21
INT_L.NE6BEG1.NE6END1 03_21 05_20
INT_L.NE6BEG1.NN2END1 03_20 03_21
@ -2071,6 +2240,8 @@ INT_L.NE6BEG2.LOGIC_OUTS_L10 03_36 04_38
INT_L.NE6BEG2.LOGIC_OUTS_L14 03_36 07_37
INT_L.NE6BEG2.LOGIC_OUTS_L16 04_38 06_36
INT_L.NE6BEG2.LOGIC_OUTS_L20 06_36 07_37
INT_L.NE6BEG2.LVB_L0 04_38 05_36
INT_L.NE6BEG2.LVB_L12 05_36 07_37
INT_L.NE6BEG2.EE2END2 03_36 05_39
INT_L.NE6BEG2.EE4END2 05_36 05_39
INT_L.NE6BEG2.NE2END2 02_37 03_37
@ -2082,14 +2253,17 @@ INT_L.NE6BEG2.NW6END2 04_37 06_36
INT_L.NE6BEG2.SE2END2 02_37 05_39
INT_L.NE6BEG2.SE6END2 05_39 06_36
INT_L.NE6BEG2.WW2END1 03_36 04_37
INT_L.NE6BEG2.WW4END2 04_37 05_36
INT_L.NE6BEG3.LOGIC_OUTS_L3 02_53 04_54
INT_L.NE6BEG3.LOGIC_OUTS_L7 02_53 07_53
INT_L.NE6BEG3.LOGIC_OUTS_L11 03_52 07_53
INT_L.NE6BEG3.LOGIC_OUTS_L15 03_52 04_54
INT_L.NE6BEG3.LOGIC_OUTS_L17 06_52 07_53
INT_L.NE6BEG3.LOGIC_OUTS_L21 04_54 06_52
INT_L.NE6BEG3.LV_L18 05_52 07_53
INT_L.NE6BEG3.EE2END3 03_52 05_55
INT_L.NE6BEG3.EE4END3 05_52 05_55
INT_L.NE6BEG3.LH0 04_54 05_52
INT_L.NE6BEG3.NE2END3 02_53 03_53
INT_L.NE6BEG3.NE6END3 03_53 05_52
INT_L.NE6BEG3.NN2END3 03_52 03_53
@ -2099,6 +2273,7 @@ INT_L.NE6BEG3.NW6END3 04_53 06_52
INT_L.NE6BEG3.SE2END3 02_53 05_55
INT_L.NE6BEG3.SE6END3 05_55 06_52
INT_L.NE6BEG3.WW2END2 03_52 04_53
INT_L.NE6BEG3.WW4END3 04_53 05_52
INT_L.NL1BEG0.LOGIC_OUTS_L1 07_16 14_17
INT_L.NL1BEG0.LOGIC_OUTS_L5 11_17 14_17
INT_L.NL1BEG0.LOGIC_OUTS_L9 10_17 13_17
@ -2245,9 +2420,11 @@ INT_L.NN6BEG0.LOGIC_OUTS_L8 02_07 06_06
INT_L.NN6BEG0.LOGIC_OUTS_L12 02_07 05_05
INT_L.NN6BEG0.LOGIC_OUTS_L18 06_06 07_07
INT_L.NN6BEG0.LOGIC_OUTS_L22 05_05 07_07
INT_L.NN6BEG0.LV_L0 04_07 06_06
INT_L.NN6BEG0.WW2END_N0_3 02_07 04_04
INT_L.NN6BEG0.EE2END0 02_07 05_06
INT_L.NN6BEG0.EE4END0 04_07 05_06
INT_L.NN6BEG0.LH12 04_07 05_05
INT_L.NN6BEG0.NE2END0 02_06 03_06
INT_L.NN6BEG0.NE6END0 02_06 04_07
INT_L.NN6BEG0.NN2END0 02_06 02_07
@ -2263,8 +2440,10 @@ INT_L.NN6BEG1.LOGIC_OUTS_L9 02_23 05_21
INT_L.NN6BEG1.LOGIC_OUTS_L13 02_23 06_22
INT_L.NN6BEG1.LOGIC_OUTS_L19 05_21 07_23
INT_L.NN6BEG1.LOGIC_OUTS_L23 06_22 07_23
INT_L.NN6BEG1.LV_L9 04_23 06_22
INT_L.NN6BEG1.EE2END1 02_23 05_22
INT_L.NN6BEG1.EE4END1 04_23 05_22
INT_L.NN6BEG1.LH6 04_23 05_21
INT_L.NN6BEG1.NE2END1 02_22 03_22
INT_L.NN6BEG1.NE6END1 02_22 04_23
INT_L.NN6BEG1.NN2END1 02_22 02_23
@ -2281,6 +2460,8 @@ INT_L.NN6BEG2.LOGIC_OUTS_L10 02_39 06_38
INT_L.NN6BEG2.LOGIC_OUTS_L14 02_39 05_37
INT_L.NN6BEG2.LOGIC_OUTS_L16 06_38 07_39
INT_L.NN6BEG2.LOGIC_OUTS_L20 05_37 07_39
INT_L.NN6BEG2.LVB_L0 04_39 06_38
INT_L.NN6BEG2.LVB_L12 04_39 05_37
INT_L.NN6BEG2.EE2END2 02_39 05_38
INT_L.NN6BEG2.EE4END2 04_39 05_38
INT_L.NN6BEG2.NE2END2 02_38 03_38
@ -2299,8 +2480,10 @@ INT_L.NN6BEG3.LOGIC_OUTS_L11 02_55 05_53
INT_L.NN6BEG3.LOGIC_OUTS_L15 02_55 06_54
INT_L.NN6BEG3.LOGIC_OUTS_L17 05_53 07_55
INT_L.NN6BEG3.LOGIC_OUTS_L21 06_54 07_55
INT_L.NN6BEG3.LV_L18 04_55 05_53
INT_L.NN6BEG3.EE2END3 02_55 05_54
INT_L.NN6BEG3.EE4END3 04_55 05_54
INT_L.NN6BEG3.LH0 04_55 06_54
INT_L.NN6BEG3.NE2END3 02_54 03_54
INT_L.NN6BEG3.NE6END3 02_54 04_55
INT_L.NN6BEG3.NN2END3 02_54 02_55
@ -2308,6 +2491,7 @@ INT_L.NN6BEG3.NN6END3 02_54 07_55
INT_L.NN6BEG3.NW2END3 03_54 04_52
INT_L.NN6BEG3.NW6END3 04_52 07_55
INT_L.NN6BEG3.SE2END3 03_54 05_54
INT_L.NN6BEG3.SE6END3 05_54 07_55
INT_L.NN6BEG3.WW2END2 02_55 04_52
INT_L.NN6BEG3.WW4END3 04_52 04_55
INT_L.NR1BEG0.LOGIC_OUTS_L0 11_07 14_07
@ -2476,11 +2660,13 @@ INT_L.NW6BEG0.LOGIC_OUTS_L8 02_03 05_01
INT_L.NW6BEG0.LOGIC_OUTS_L12 02_03 06_02
INT_L.NW6BEG0.LOGIC_OUTS_L18 05_01 07_03
INT_L.NW6BEG0.LOGIC_OUTS_L22 06_02 07_03
INT_L.NW6BEG0.LV_L0 04_03 06_02
INT_L.NW6BEG0.SS2END_N0_3 02_03 04_00
INT_L.NW6BEG0.SS6END_N0_3 04_00 07_03
INT_L.NW6BEG0.SW2END_N0_3 03_02 04_00
INT_L.NW6BEG0.SW6END_N0_3 04_00 04_03
INT_L.NW6BEG0.WW2END_N0_3 02_02 02_03
INT_L.NW6BEG0.LH12 04_03 05_01
INT_L.NW6BEG0.NE2END0 03_02 05_02
INT_L.NW6BEG0.NE6END0 04_03 05_02
INT_L.NW6BEG0.NN2END0 02_03 05_02
@ -2494,6 +2680,8 @@ INT_L.NW6BEG1.LOGIC_OUTS_L9 02_19 06_18
INT_L.NW6BEG1.LOGIC_OUTS_L13 02_19 05_17
INT_L.NW6BEG1.LOGIC_OUTS_L19 06_18 07_19
INT_L.NW6BEG1.LOGIC_OUTS_L23 05_17 07_19
INT_L.NW6BEG1.LV_L9 04_19 06_18
INT_L.NW6BEG1.LH6 04_19 05_17
INT_L.NW6BEG1.NE2END1 03_18 05_18
INT_L.NW6BEG1.NE6END1 04_19 05_18
INT_L.NW6BEG1.NN2END1 02_19 05_18
@ -2512,6 +2700,8 @@ INT_L.NW6BEG2.LOGIC_OUTS_L10 02_35 05_33
INT_L.NW6BEG2.LOGIC_OUTS_L14 02_35 06_34
INT_L.NW6BEG2.LOGIC_OUTS_L16 05_33 07_35
INT_L.NW6BEG2.LOGIC_OUTS_L20 06_34 07_35
INT_L.NW6BEG2.LVB_L0 04_35 06_34
INT_L.NW6BEG2.LVB_L12 04_35 05_33
INT_L.NW6BEG2.NE2END2 03_34 05_34
INT_L.NW6BEG2.NE6END2 04_35 05_34
INT_L.NW6BEG2.NN2END2 02_35 05_34
@ -2530,6 +2720,8 @@ INT_L.NW6BEG3.LOGIC_OUTS_L11 02_51 06_50
INT_L.NW6BEG3.LOGIC_OUTS_L15 02_51 05_49
INT_L.NW6BEG3.LOGIC_OUTS_L17 06_50 07_51
INT_L.NW6BEG3.LOGIC_OUTS_L21 05_49 07_51
INT_L.NW6BEG3.LV_L18 04_51 05_49
INT_L.NW6BEG3.LH0 04_51 06_50
INT_L.NW6BEG3.NE2END3 03_50 05_50
INT_L.NW6BEG3.NE6END3 04_51 05_50
INT_L.NW6BEG3.NN2END3 02_51 05_50
@ -2628,8 +2820,10 @@ INT_L.SE6BEG0.LOGIC_OUTS_L8 02_11 05_09
INT_L.SE6BEG0.LOGIC_OUTS_L12 02_11 06_10
INT_L.SE6BEG0.LOGIC_OUTS_L18 05_09 07_11
INT_L.SE6BEG0.LOGIC_OUTS_L22 06_10 07_11
INT_L.SE6BEG0.LV_L0 04_11 06_10
INT_L.SE6BEG0.EE2END0 02_10 02_11
INT_L.SE6BEG0.EE4END0 02_10 04_11
INT_L.SE6BEG0.LH12 04_11 05_09
INT_L.SE6BEG0.NE2END0 03_10 04_08
INT_L.SE6BEG0.NE6END0 04_08 04_11
INT_L.SE6BEG0.NN2END0 02_11 04_08
@ -2646,8 +2840,10 @@ INT_L.SE6BEG1.LOGIC_OUTS_L9 02_27 06_26
INT_L.SE6BEG1.LOGIC_OUTS_L13 02_27 05_25
INT_L.SE6BEG1.LOGIC_OUTS_L19 06_26 07_27
INT_L.SE6BEG1.LOGIC_OUTS_L23 05_25 07_27
INT_L.SE6BEG1.LV_L9 04_27 06_26
INT_L.SE6BEG1.EE2END1 02_26 02_27
INT_L.SE6BEG1.EE4END1 02_26 04_27
INT_L.SE6BEG1.LH6 04_27 05_25
INT_L.SE6BEG1.NE2END1 03_26 04_24
INT_L.SE6BEG1.NE6END1 04_24 04_27
INT_L.SE6BEG1.NN2END1 02_27 04_24
@ -2664,6 +2860,8 @@ INT_L.SE6BEG2.LOGIC_OUTS_L10 02_43 05_41
INT_L.SE6BEG2.LOGIC_OUTS_L14 02_43 06_42
INT_L.SE6BEG2.LOGIC_OUTS_L16 05_41 07_43
INT_L.SE6BEG2.LOGIC_OUTS_L20 06_42 07_43
INT_L.SE6BEG2.LVB_L0 04_43 06_42
INT_L.SE6BEG2.LVB_L12 04_43 05_41
INT_L.SE6BEG2.EE2END2 02_42 02_43
INT_L.SE6BEG2.EE4END2 02_42 04_43
INT_L.SE6BEG2.NE2END2 03_42 04_40
@ -2682,8 +2880,10 @@ INT_L.SE6BEG3.LOGIC_OUTS_L11 02_59 06_58
INT_L.SE6BEG3.LOGIC_OUTS_L15 02_59 05_57
INT_L.SE6BEG3.LOGIC_OUTS_L17 06_58 07_59
INT_L.SE6BEG3.LOGIC_OUTS_L21 05_57 07_59
INT_L.SE6BEG3.LV_L18 04_59 05_57
INT_L.SE6BEG3.EE2END3 02_58 02_59
INT_L.SE6BEG3.EE4END3 02_58 04_59
INT_L.SE6BEG3.LH0 04_59 06_58
INT_L.SE6BEG3.NE2END3 03_58 04_56
INT_L.SE6BEG3.NE6END3 04_56 04_59
INT_L.SE6BEG3.NN2END3 02_59 04_56
@ -2920,8 +3120,10 @@ INT_L.SS6BEG0.LOGIC_OUTS_L8 02_15 06_14
INT_L.SS6BEG0.LOGIC_OUTS_L12 02_15 05_13
INT_L.SS6BEG0.LOGIC_OUTS_L18 06_14 07_15
INT_L.SS6BEG0.LOGIC_OUTS_L22 05_13 07_15
INT_L.SS6BEG0.LV_L0 04_15 06_14
INT_L.SS6BEG0.EE2END0 02_15 04_12
INT_L.SS6BEG0.EE4END0 04_12 04_15
INT_L.SS6BEG0.LH12 04_15 05_13
INT_L.SS6BEG0.NW2END1 03_14 05_14
INT_L.SS6BEG0.NW6END1 05_14 07_15
INT_L.SS6BEG0.SE2END0 03_14 04_12
@ -2938,8 +3140,10 @@ INT_L.SS6BEG1.LOGIC_OUTS_L9 02_31 05_29
INT_L.SS6BEG1.LOGIC_OUTS_L13 02_31 06_30
INT_L.SS6BEG1.LOGIC_OUTS_L19 05_29 07_31
INT_L.SS6BEG1.LOGIC_OUTS_L23 06_30 07_31
INT_L.SS6BEG1.LV_L9 04_31 06_30
INT_L.SS6BEG1.EE2END1 02_31 04_28
INT_L.SS6BEG1.EE4END1 04_28 04_31
INT_L.SS6BEG1.LH6 04_31 05_29
INT_L.SS6BEG1.NW2END2 03_30 05_30
INT_L.SS6BEG1.NW6END2 05_30 07_31
INT_L.SS6BEG1.SE2END1 03_30 04_28
@ -2956,6 +3160,8 @@ INT_L.SS6BEG2.LOGIC_OUTS_L10 02_47 06_46
INT_L.SS6BEG2.LOGIC_OUTS_L14 02_47 05_45
INT_L.SS6BEG2.LOGIC_OUTS_L16 06_46 07_47
INT_L.SS6BEG2.LOGIC_OUTS_L20 05_45 07_47
INT_L.SS6BEG2.LVB_L0 04_47 06_46
INT_L.SS6BEG2.LVB_L12 04_47 05_45
INT_L.SS6BEG2.EE2END2 02_47 04_44
INT_L.SS6BEG2.EE4END2 04_44 04_47
INT_L.SS6BEG2.NW2END3 03_46 05_46
@ -2974,11 +3180,13 @@ INT_L.SS6BEG3.LOGIC_OUTS_L11 02_63 05_61
INT_L.SS6BEG3.LOGIC_OUTS_L15 02_63 06_62
INT_L.SS6BEG3.LOGIC_OUTS_L17 05_61 07_63
INT_L.SS6BEG3.LOGIC_OUTS_L21 06_62 07_63
INT_L.SS6BEG3.LV_L18 04_63 05_61
INT_L.SS6BEG3.NW2END_S0_0 03_62 05_62
INT_L.SS6BEG3.NW6END_S0_0 05_62 07_63
INT_L.SS6BEG3.WW4END_S0_0 04_63 05_62
INT_L.SS6BEG3.EE2END3 02_63 04_60
INT_L.SS6BEG3.EE4END3 04_60 04_63
INT_L.SS6BEG3.LH0 04_63 06_62
INT_L.SS6BEG3.SE2END3 03_62 04_60
INT_L.SS6BEG3.SE6END3 04_60 07_63
INT_L.SS6BEG3.SS2END3 02_62 02_63
@ -3072,8 +3280,10 @@ INT_L.SW6BEG0.LOGIC_OUTS_L8 03_12 04_14
INT_L.SW6BEG0.LOGIC_OUTS_L12 03_12 07_13
INT_L.SW6BEG0.LOGIC_OUTS_L18 04_14 06_12
INT_L.SW6BEG0.LOGIC_OUTS_L22 06_12 07_13
INT_L.SW6BEG0.LV_L0 04_14 05_12
INT_L.SW6BEG0.EE2END0 03_12 04_13
INT_L.SW6BEG0.EE4END0 04_13 05_12
INT_L.SW6BEG0.LH12 05_12 07_13
INT_L.SW6BEG0.NW2END1 02_13 05_15
INT_L.SW6BEG0.NW6END1 05_15 06_12
INT_L.SW6BEG0.SE2END0 02_13 04_13
@ -3090,8 +3300,10 @@ INT_L.SW6BEG1.LOGIC_OUTS_L9 03_28 07_29
INT_L.SW6BEG1.LOGIC_OUTS_L13 03_28 04_30
INT_L.SW6BEG1.LOGIC_OUTS_L19 06_28 07_29
INT_L.SW6BEG1.LOGIC_OUTS_L23 04_30 06_28
INT_L.SW6BEG1.LV_L9 04_30 05_28
INT_L.SW6BEG1.EE2END1 03_28 04_29
INT_L.SW6BEG1.EE4END1 04_29 05_28
INT_L.SW6BEG1.LH6 05_28 07_29
INT_L.SW6BEG1.NW2END2 02_29 05_31
INT_L.SW6BEG1.NW6END2 05_31 06_28
INT_L.SW6BEG1.SE2END1 02_29 04_29
@ -3108,7 +3320,10 @@ INT_L.SW6BEG2.LOGIC_OUTS_L10 03_44 04_46
INT_L.SW6BEG2.LOGIC_OUTS_L14 03_44 07_45
INT_L.SW6BEG2.LOGIC_OUTS_L16 04_46 06_44
INT_L.SW6BEG2.LOGIC_OUTS_L20 06_44 07_45
INT_L.SW6BEG2.LVB_L0 04_46 05_44
INT_L.SW6BEG2.LVB_L12 05_44 07_45
INT_L.SW6BEG2.EE2END2 03_44 04_45
INT_L.SW6BEG2.EE4END2 04_45 05_44
INT_L.SW6BEG2.NW2END3 02_45 05_47
INT_L.SW6BEG2.NW6END3 05_47 06_44
INT_L.SW6BEG2.SE2END2 02_45 04_45
@ -3125,10 +3340,13 @@ INT_L.SW6BEG3.LOGIC_OUTS_L11 03_60 07_61
INT_L.SW6BEG3.LOGIC_OUTS_L15 03_60 04_62
INT_L.SW6BEG3.LOGIC_OUTS_L17 06_60 07_61
INT_L.SW6BEG3.LOGIC_OUTS_L21 04_62 06_60
INT_L.SW6BEG3.LV_L18 05_60 07_61
INT_L.SW6BEG3.NW2END_S0_0 02_61 05_63
INT_L.SW6BEG3.NW6END_S0_0 05_63 06_60
INT_L.SW6BEG3.WW4END_S0_0 05_60 05_63
INT_L.SW6BEG3.EE2END3 03_60 04_61
INT_L.SW6BEG3.EE4END3 04_61 05_60
INT_L.SW6BEG3.LH0 04_62 05_60
INT_L.SW6BEG3.SE2END3 02_61 04_61
INT_L.SW6BEG3.SE6END3 04_61 06_60
INT_L.SW6BEG3.SS2END3 03_60 03_61
@ -3342,12 +3560,15 @@ INT_L.WW4BEG0.LOGIC_OUTS_L8 03_00 07_01
INT_L.WW4BEG0.LOGIC_OUTS_L12 03_00 04_02
INT_L.WW4BEG0.LOGIC_OUTS_L18 06_00 07_01
INT_L.WW4BEG0.LOGIC_OUTS_L22 04_02 06_00
INT_L.WW4BEG0.LV_L0 04_02 05_00
INT_L.WW4BEG0.SS2END_N0_3 03_00 04_01
INT_L.WW4BEG0.SS6END_N0_3 04_01 06_00
INT_L.WW4BEG0.SW2END_N0_3 02_01 04_01
INT_L.WW4BEG0.SW6END_N0_3 04_01 05_00
INT_L.WW4BEG0.WW2END_N0_3 03_00 03_01
INT_L.WW4BEG0.LH12 05_00 07_01
INT_L.WW4BEG0.NE2END0 02_01 05_03
INT_L.WW4BEG0.NE6END0 05_00 05_03
INT_L.WW4BEG0.NN2END0 03_00 05_03
INT_L.WW4BEG0.NN6END0 05_03 06_00
INT_L.WW4BEG0.NW2END0 02_01 03_01
@ -3359,6 +3580,8 @@ INT_L.WW4BEG1.LOGIC_OUTS_L9 03_16 04_18
INT_L.WW4BEG1.LOGIC_OUTS_L13 03_16 07_17
INT_L.WW4BEG1.LOGIC_OUTS_L19 04_18 06_16
INT_L.WW4BEG1.LOGIC_OUTS_L23 06_16 07_17
INT_L.WW4BEG1.LV_L9 04_18 05_16
INT_L.WW4BEG1.LH6 05_16 07_17
INT_L.WW4BEG1.NE2END1 02_17 05_19
INT_L.WW4BEG1.NE6END1 05_16 05_19
INT_L.WW4BEG1.NN2END1 03_16 05_19
@ -3377,7 +3600,10 @@ INT_L.WW4BEG2.LOGIC_OUTS_L10 03_32 07_33
INT_L.WW4BEG2.LOGIC_OUTS_L14 03_32 04_34
INT_L.WW4BEG2.LOGIC_OUTS_L16 06_32 07_33
INT_L.WW4BEG2.LOGIC_OUTS_L20 04_34 06_32
INT_L.WW4BEG2.LVB_L0 04_34 05_32
INT_L.WW4BEG2.LVB_L12 05_32 07_33
INT_L.WW4BEG2.NE2END2 02_33 05_35
INT_L.WW4BEG2.NE6END2 05_32 05_35
INT_L.WW4BEG2.NN2END2 03_32 05_35
INT_L.WW4BEG2.NN6END2 05_35 06_32
INT_L.WW4BEG2.NW2END2 02_33 03_33
@ -3394,7 +3620,10 @@ INT_L.WW4BEG3.LOGIC_OUTS_L11 03_48 04_50
INT_L.WW4BEG3.LOGIC_OUTS_L15 03_48 07_49
INT_L.WW4BEG3.LOGIC_OUTS_L17 04_50 06_48
INT_L.WW4BEG3.LOGIC_OUTS_L21 06_48 07_49
INT_L.WW4BEG3.LV_L18 05_48 07_49
INT_L.WW4BEG3.LH0 04_50 05_48
INT_L.WW4BEG3.NE2END3 02_49 05_51
INT_L.WW4BEG3.NE6END3 05_48 05_51
INT_L.WW4BEG3.NN2END3 03_48 05_51
INT_L.WW4BEG3.NN6END3 05_51 06_48
INT_L.WW4BEG3.NW2END3 02_49 03_49

225
artix7/segbits_int_r.db
View File

@ -265,6 +265,7 @@ INT_R.FAN_ALT1.NL1BEG_N3 19_49 !22_48 23_48 24_48 25_48
INT_R.FAN_ALT1.EE2END3 19_49 !22_48 !23_48 !24_48 25_48
INT_R.FAN_ALT1.EL1END3 17_48 !22_48 23_48 24_48 25_48
INT_R.FAN_ALT1.ER1END2 16_48 22_48 !23_48 24_48 25_48
INT_R.FAN_ALT1.GFAN1 21_48 !22_48 !23_48 !24_48 25_48
INT_R.FAN_ALT1.NE2END3 18_49 !22_48 !23_48 24_48 !25_48
INT_R.FAN_ALT1.NN2END3 18_49 !22_48 !23_48 !24_48 25_48
INT_R.FAN_ALT1.NR1END3 18_49 22_48 !23_48 24_48 25_48
@ -277,6 +278,7 @@ INT_R.FAN_ALT1.SW2END2 17_48 !22_48 !23_48 24_48 !25_48
INT_R.FAN_ALT1.WL1END2 16_48 !22_48 23_48 24_48 25_48
INT_R.FAN_ALT1.WR1END3 17_48 22_48 !23_48 24_48 25_48
INT_R.FAN_ALT1.WW2END2 16_48 !22_48 !23_48 !24_48 25_48
INT_R.FAN_ALT2.BYP_BOUNCE_N3_6 20_16 !22_16 !23_16 24_16 !25_16
INT_R.FAN_ALT2.BYP_BOUNCE0 20_16 !22_16 !23_16 !24_16 25_16
INT_R.FAN_ALT2.FAN_BOUNCE5 20_16 !22_16 23_16 24_16 25_16
INT_R.FAN_ALT2.FAN_BOUNCE6 20_16 22_16 !23_16 24_16 25_16
@ -324,7 +326,10 @@ INT_R.FAN_ALT3.SW2END3 18_57 !22_56 !23_56 24_56 !25_56
INT_R.FAN_ALT3.WL1END3 17_56 !22_56 23_56 24_56 25_56
INT_R.FAN_ALT3.WR1END3 16_56 22_56 !23_56 24_56 25_56
INT_R.FAN_ALT3.WW2END3 19_57 !22_56 !23_56 !24_56 25_56
INT_R.FAN_ALT4.BYP_BOUNCE_N3_3 20_08 !22_08 !23_08 !24_08 25_08
INT_R.FAN_ALT4.BYP_BOUNCE_N3_7 20_08 !22_08 !23_08 24_08 !25_08
INT_R.FAN_ALT4.FAN_BOUNCE2 20_08 22_08 !23_08 24_08 25_08
INT_R.FAN_ALT4.FAN_BOUNCE7 20_08 !22_08 23_08 24_08 25_08
INT_R.FAN_ALT4.LOGIC_OUTS4 21_08 22_08 !23_08 24_08 25_08
INT_R.FAN_ALT4.LOGIC_OUTS8 21_08 !22_08 23_08 24_08 25_08
INT_R.FAN_ALT4.LOGIC_OUTS18 21_08 !22_08 !23_08 24_08 !25_08
@ -332,7 +337,7 @@ INT_R.FAN_ALT4.SR1BEG_S0 19_09 22_08 !23_08 24_08 25_08
INT_R.FAN_ALT4.EE2END0 16_08 !22_08 !23_08 !24_08 25_08
INT_R.FAN_ALT4.EL1END0 16_08 !22_08 23_08 24_08 25_08
INT_R.FAN_ALT4.ER1END0 17_08 22_08 !23_08 24_08 25_08
INT_R.FAN_ALT4.GFAN0 21_08 !22_08 !23_08 !24_08 25_08
INT_R.FAN_ALT4.GFAN0 !00_10 !00_11 !01_09 01_10 01_14 21_08 !22_08 !23_08 !24_08 25_08
INT_R.FAN_ALT4.NE2END0 17_08 !22_08 !23_08 24_08 !25_08
INT_R.FAN_ALT4.NL1END1 19_09 !22_08 23_08 24_08 25_08
INT_R.FAN_ALT4.NN2END0 17_08 !22_08 !23_08 !24_08 25_08
@ -345,6 +350,7 @@ INT_R.FAN_ALT4.SW2END0 18_09 !22_08 !23_08 24_08 !25_08
INT_R.FAN_ALT4.WL1END0 17_08 !22_08 23_08 24_08 25_08
INT_R.FAN_ALT4.WR1END0 16_08 22_08 !23_08 24_08 25_08
INT_R.FAN_ALT4.WW2END0 19_09 !22_08 !23_08 !24_08 25_08
INT_R.FAN_ALT5.BYP_BOUNCE1 20_40 !22_40 !23_40 24_40 !25_40
INT_R.FAN_ALT5.BYP_BOUNCE5 20_40 !22_40 !23_40 !24_40 25_40
INT_R.FAN_ALT5.FAN_BOUNCE_S3_0 20_40 22_40 !23_40 24_40 25_40
INT_R.FAN_ALT5.FAN_BOUNCE1 20_40 !22_40 23_40 24_40 25_40
@ -355,6 +361,7 @@ INT_R.FAN_ALT5.NL1BEG_N3 19_41 !22_40 23_40 24_40 25_40
INT_R.FAN_ALT5.EE2END2 16_40 !22_40 !23_40 !24_40 25_40
INT_R.FAN_ALT5.EL1END2 16_40 !22_40 23_40 24_40 25_40
INT_R.FAN_ALT5.ER1END2 17_40 22_40 !23_40 24_40 25_40
INT_R.FAN_ALT5.GFAN1 21_40 !22_40 !23_40 !24_40 25_40
INT_R.FAN_ALT5.NE2END2 17_40 !22_40 !23_40 24_40 !25_40
INT_R.FAN_ALT5.NN2END2 17_40 !22_40 !23_40 !24_40 25_40
INT_R.FAN_ALT5.NR1END2 18_41 22_40 !23_40 24_40 25_40
@ -527,6 +534,38 @@ INT_R.CLK1.GCLK_B11 00_27 !00_29 01_25 01_26 01_29
INT_R.CLK1.ER1END1 00_27 00_29 01_25 01_26 !01_29
INT_R.CLK1.SR1END1 !00_27 !00_29 01_25 01_26 !01_29
INT_R.CLK1.WR1END1 00_27 !00_29 01_25 !01_26 !01_29
INT_R.CTRL0.BYP_BOUNCE4 !00_35 !00_39 01_37 01_38 !01_40
INT_R.CTRL0.FAN_BOUNCE1 !00_35 00_39 01_37 !01_38 !01_40
INT_R.CTRL0.EE4END2 !00_35 00_38 00_39 !01_38 !01_40
INT_R.CTRL0.ER1END2 !00_35 !00_39 01_33 01_38 !01_40
INT_R.CTRL0.GFAN0 00_35 00_39 01_37 01_38 !01_40
INT_R.CTRL0.GFAN1 !00_35 00_39 01_37 01_38 01_40
INT_R.CTRL0.NE6END2 !00_35 00_39 01_33 01_38 01_40
INT_R.CTRL0.NN6END2 00_35 00_39 01_33 01_38 !01_40
INT_R.CTRL0.NR1END2 00_34 !00_35 00_39 01_38 01_40
INT_R.CTRL0.NW6END2 00_34 00_35 00_39 01_38 !01_40
INT_R.CTRL0.SE6END2 !00_35 00_38 !00_39 01_38 !01_40
INT_R.CTRL0.SR1END2 !00_35 00_38 00_39 01_38 01_40
INT_R.CTRL0.SS6END2 00_35 00_38 00_39 01_38 !01_40
INT_R.CTRL0.SW6END1 00_34 !00_35 !00_39 01_38 !01_40
INT_R.CTRL0.WR1END2 00_34 !00_35 00_39 !01_38 !01_40
INT_R.CTRL0.WW4END2 !00_35 00_39 01_33 !01_38 !01_40
INT_R.CTRL1.BYP_BOUNCE4 !00_37 00_42 01_32 !01_36 !01_41
INT_R.CTRL1.FAN_BOUNCE1 !00_37 !00_42 01_32 !01_36 01_41
INT_R.CTRL1.EE4END2 !00_37 00_41 !00_42 !01_36 01_41
INT_R.CTRL1.ER1END2 00_33 !00_37 00_42 !01_36 !01_41
INT_R.CTRL1.GFAN0 !00_37 00_42 01_32 01_36 01_41
INT_R.CTRL1.GFAN1 00_37 00_42 01_32 !01_36 01_41
INT_R.CTRL1.NE6END2 00_33 00_37 00_42 !01_36 01_41
INT_R.CTRL1.NN6END2 00_33 !00_37 00_42 01_36 01_41
INT_R.CTRL1.NR1END2 00_37 00_42 01_34 !01_36 01_41
INT_R.CTRL1.NW6END2 !00_37 00_42 01_34 01_36 01_41
INT_R.CTRL1.SE6END2 !00_37 00_41 00_42 !01_36 !01_41
INT_R.CTRL1.SR1END2 00_37 00_41 00_42 !01_36 01_41
INT_R.CTRL1.SS6END2 !00_37 00_41 00_42 01_36 01_41
INT_R.CTRL1.SW6END1 !00_37 00_42 01_34 !01_36 !01_41
INT_R.CTRL1.WR1END2 !00_37 !00_42 01_34 !01_36 01_41
INT_R.CTRL1.WW4END2 00_33 !00_37 !00_42 !01_36 01_41
INT_R.EE2BEG0.LOGIC_OUTS0 09_07 15_06
INT_R.EE2BEG0.LOGIC_OUTS4 09_06 15_06
INT_R.EE2BEG0.LOGIC_OUTS8 11_06 15_06
@ -615,6 +654,8 @@ INT_R.EE4BEG0.LOGIC_OUTS18 06_08 07_09
INT_R.EE4BEG0.LOGIC_OUTS22 04_10 06_08
INT_R.EE4BEG0.EE2END0 03_08 03_09
INT_R.EE4BEG0.EE4END0 03_09 05_08
INT_R.EE4BEG0.LH12 05_08 07_09
INT_R.EE4BEG0.LV0 04_10 05_08
INT_R.EE4BEG0.NE2END0 02_09 04_09
INT_R.EE4BEG0.NE6END0 04_09 05_08
INT_R.EE4BEG0.NN2END0 03_08 04_09
@ -633,6 +674,8 @@ INT_R.EE4BEG1.LOGIC_OUTS19 04_26 06_24
INT_R.EE4BEG1.LOGIC_OUTS23 06_24 07_25
INT_R.EE4BEG1.EE2END1 03_24 03_25
INT_R.EE4BEG1.EE4END1 03_25 05_24
INT_R.EE4BEG1.LH6 05_24 07_25
INT_R.EE4BEG1.LV9 04_26 05_24
INT_R.EE4BEG1.NE2END1 02_25 04_25
INT_R.EE4BEG1.NE6END1 04_25 05_24
INT_R.EE4BEG1.NN2END1 03_24 04_25
@ -642,6 +685,7 @@ INT_R.EE4BEG1.SE6END1 03_25 06_24
INT_R.EE4BEG1.SS2END1 03_24 05_27
INT_R.EE4BEG1.SS6END1 05_27 06_24
INT_R.EE4BEG1.SW2END1 02_25 05_27
INT_R.EE4BEG1.SW6END1 05_24 05_27
INT_R.EE4BEG2.LOGIC_OUTS2 02_41 04_42
INT_R.EE4BEG2.LOGIC_OUTS6 02_41 07_41
INT_R.EE4BEG2.LOGIC_OUTS10 03_40 07_41
@ -650,6 +694,8 @@ INT_R.EE4BEG2.LOGIC_OUTS16 06_40 07_41
INT_R.EE4BEG2.LOGIC_OUTS20 04_42 06_40
INT_R.EE4BEG2.EE2END2 03_40 03_41
INT_R.EE4BEG2.EE4END2 03_41 05_40
INT_R.EE4BEG2.LVB0 04_42 05_40
INT_R.EE4BEG2.LVB12 05_40 07_41
INT_R.EE4BEG2.NE2END2 02_41 04_41
INT_R.EE4BEG2.NE6END2 04_41 05_40
INT_R.EE4BEG2.NN2END2 03_40 04_41
@ -668,6 +714,8 @@ INT_R.EE4BEG3.LOGIC_OUTS17 04_58 06_56
INT_R.EE4BEG3.LOGIC_OUTS21 06_56 07_57
INT_R.EE4BEG3.EE2END3 03_56 03_57
INT_R.EE4BEG3.EE4END3 03_57 05_56
INT_R.EE4BEG3.LH0 04_58 05_56
INT_R.EE4BEG3.LV18 05_56 07_57
INT_R.EE4BEG3.NE2END3 02_57 04_57
INT_R.EE4BEG3.NE6END3 04_57 05_56
INT_R.EE4BEG3.NN2END3 03_56 04_57
@ -677,6 +725,7 @@ INT_R.EE4BEG3.SE6END3 03_57 06_56
INT_R.EE4BEG3.SS2END3 03_56 05_59
INT_R.EE4BEG3.SS6END3 05_59 06_56
INT_R.EE4BEG3.SW2END3 02_57 05_59
INT_R.EE4BEG3.SW6END3 05_56 05_59
INT_R.EL1BEG0.LOGIC_OUTS1 07_20 14_21
INT_R.EL1BEG0.LOGIC_OUTS5 11_21 14_21
INT_R.EL1BEG0.LOGIC_OUTS9 10_21 13_21
@ -797,8 +846,38 @@ INT_R.ER1BEG3.SW2END2 07_42 15_43
INT_R.ER1BEG3.SW6END2 07_42 12_43
INT_R.ER1BEG3.WW2END2 11_43 15_43
INT_R.ER1BEG3.WW4END3 11_43 12_43
INT_R.GFAN0.BYP_BOUNCE1 00_10 00_11 !01_09 01_10 01_14
INT_R.GFAN0.GCLK_B0_EAST 00_10 00_11 !01_09 01_10 01_12
INT_R.GFAN0.GCLK_B1_EAST !00_10 00_11 01_09 01_10 01_12
INT_R.GFAN0.GCLK_B2_EAST !00_10 !00_11 !01_09 01_10 01_12
INT_R.GFAN0.GCLK_B3_EAST !00_10 00_11 !01_09 !01_10 01_12
INT_R.GFAN0.GCLK_B4_EAST 00_10 00_11 !01_09 01_10 01_18
INT_R.GFAN0.GCLK_B5_EAST !00_10 00_11 01_09 01_10 01_18
INT_R.GFAN0.GCLK_B6 !00_10 !00_11 !01_09 01_10 01_18
INT_R.GFAN0.GCLK_B7 !00_10 00_11 !01_09 !01_10 01_18
INT_R.GFAN0.GCLK_B8 00_10 00_11 !01_09 01_10 01_16
INT_R.GFAN0.GCLK_B9 !00_10 00_11 01_09 01_10 01_16
INT_R.GFAN0.GCLK_B10 !00_10 !00_11 !01_09 01_10 01_16
INT_R.GFAN0.GCLK_B11 !00_10 00_11 !01_09 !01_10 01_16
INT_R.GFAN0.GND_WIRE !00_10 00_11 !01_09 !01_10 01_14
INT_R.GFAN0.NR1END1 !00_10 00_11 01_09 01_10 01_14
INT_R.GFAN0.WW4END1 !00_10 !00_11 !01_09 01_10 01_14
INT_R.GFAN1.BYP_BOUNCE1 00_14 00_17 00_18 !00_19 01_13
INT_R.GFAN1.GCLK_B0_EAST 00_13 00_14 00_18 !00_19 01_13
INT_R.GFAN1.GCLK_B1_EAST 00_13 00_14 !00_18 00_19 01_13
INT_R.GFAN1.GCLK_B2_EAST 00_13 00_14 !00_18 !00_19 !01_13
INT_R.GFAN1.GCLK_B3_EAST 00_13 !00_14 !00_18 !00_19 01_13
INT_R.GFAN1.GCLK_B4_EAST 00_14 00_15 00_18 !00_19 01_13
INT_R.GFAN1.GCLK_B5_EAST 00_14 00_15 !00_18 00_19 01_13
INT_R.GFAN1.GCLK_B6 00_14 00_15 !00_18 !00_19 !01_13
INT_R.GFAN1.GCLK_B7 !00_14 00_15 !00_18 !00_19 01_13
INT_R.GFAN1.GCLK_B8 00_14 00_18 !00_19 01_13 01_17
INT_R.GFAN1.GCLK_B9 00_14 !00_18 00_19 01_13 01_17
INT_R.GFAN1.GCLK_B10 00_14 !00_18 !00_19 !01_13 01_17
INT_R.GFAN1.GCLK_B11 !00_14 !00_18 !00_19 01_13 01_17
INT_R.GFAN1.GND_WIRE !00_14 00_17 !00_18 !00_19 01_13
INT_R.GFAN1.NR1END1 00_14 00_17 !00_18 00_19 01_13
INT_R.GFAN1.WW4END1 00_14 00_17 !00_18 !00_19 !01_13
INT_R.IMUX0.BYP_BOUNCE_N3_2 21_01 !22_01 !23_01 !24_01 25_01
INT_R.IMUX0.BYP_BOUNCE_N3_6 21_01 !22_01 !23_01 24_01 !25_01
INT_R.IMUX0.ER1END_N3_3 18_00 !22_01 23_01 24_01 25_01
@ -1951,6 +2030,90 @@ INT_R.IMUX47.SS2END3 17_62 !22_62 !23_62 !24_62 25_62
INT_R.IMUX47.SW2END3 17_62 !22_62 !23_62 24_62 !25_62
INT_R.IMUX47.WL1END3 18_63 !22_62 23_62 24_62 25_62
INT_R.IMUX47.WW2END3 16_62 !22_62 !23_62 !24_62 25_62
INT_R.LH0.EE4END3 00_58 01_61
INT_R.LH0.ER1END3 00_57 01_54
INT_R.LH0.LH12 01_54 01_56
INT_R.LH0.LV0 01_56 01_58
INT_R.LH0.LV9 00_59 01_56
INT_R.LH0.LV18 01_56 01_61
INT_R.LH0.NE2END3 00_58 00_59
INT_R.LH0.NE6END3 00_58 01_58
INT_R.LH0.NW2END3 00_58 01_54
INT_R.LH0.SR1END3 00_57 00_59
INT_R.LH0.SS6END3 00_57 01_58
INT_R.LH0.SW6END3 00_57 01_61
INT_R.LH12.EE4END3 01_60 01_62
INT_R.LH12.ER1END3 00_63 01_60
INT_R.LH12.LH0 00_61 00_63
INT_R.LH12.LV0 00_55 00_62
INT_R.LH12.LV9 00_62 01_57
INT_R.LH12.LV18 00_62 01_62
INT_R.LH12.NE2END3 01_57 01_60
INT_R.LH12.NE6END3 00_55 01_60
INT_R.LH12.NW2END3 00_62 00_63
INT_R.LH12.SR1END3 00_61 01_57
INT_R.LH12.SS6END3 00_55 00_61
INT_R.LH12.SW6END3 00_61 01_62
INT_R.LV0.SR1BEG_S0 00_05 01_05
INT_R.LV0.ER1END0 01_04 01_05
INT_R.LV0.LH0 00_02 01_06
INT_R.LV0.LH6 01_04 01_06
INT_R.LV0.LH12 00_05 01_06
INT_R.LV0.LV18 00_09 01_06
INT_R.LV0.NN6END0 00_07 00_09
INT_R.LV0.NR1END0 00_02 01_05
INT_R.LV0.NW6END0 00_07 01_04
INT_R.LV0.SW6END0 00_09 01_05
INT_R.LV0.WR1END0 00_02 00_07
INT_R.LV0.WW4END0 00_05 00_07
INT_R.LV18.SR1BEG_S0 00_03 01_08
INT_R.LV18.ER1END0 00_03 00_06
INT_R.LV18.LH0 00_01 01_02
INT_R.LV18.LH6 00_06 01_02
INT_R.LV18.LH12 01_02 01_08
INT_R.LV18.LV0 01_00 01_01
INT_R.LV18.NN6END0 00_03 01_00
INT_R.LV18.NR1END0 00_01 00_03
INT_R.LV18.NW6END0 00_06 01_01
INT_R.LV18.SW6END0 01_00 01_02
INT_R.LV18.WR1END0 00_01 01_01
INT_R.LV18.WW4END0 01_01 01_08
INT_R.LVB0.LH0 00_43 00_51
INT_R.LVB0.LH6 00_51 00_53
INT_R.LVB0.LH12 00_50 00_51
INT_R.LVB0.LV0 00_47 01_52
INT_R.LVB0.LV18 01_42 01_52
INT_R.LVB0.LVB12 00_51 00_54
INT_R.LVB0.NE2END2 00_53 01_52
INT_R.LVB0.NN6END3 00_50 01_50
INT_R.LVB0.NR1END3 00_47 01_50
INT_R.LVB0.NW2END2 00_43 01_52
INT_R.LVB0.NW6END3 00_43 01_50
INT_R.LVB0.SE2END3 00_51 01_42
INT_R.LVB0.SE6END3 00_54 01_50
INT_R.LVB0.SW2END2 00_50 01_52
INT_R.LVB0.SW2END3 00_47 00_51
INT_R.LVB0.SW6END2 00_54 01_52
INT_R.LVB0.WR1END3 01_42 01_50
INT_R.LVB0.WW4END3 00_53 01_50
INT_R.LVB12.LH0 00_46 00_49
INT_R.LVB12.LH6 00_46 01_49
INT_R.LVB12.LH12 00_46 01_53
INT_R.LVB12.LV0 00_45 01_44
INT_R.LVB12.LV18 00_45 01_48
INT_R.LVB12.LVB0 00_45 01_45
INT_R.LVB12.NE2END2 00_45 01_49
INT_R.LVB12.NN6END3 01_46 01_53
INT_R.LVB12.NR1END3 01_44 01_46
INT_R.LVB12.NW2END2 00_45 00_49
INT_R.LVB12.NW6END3 00_49 01_46
INT_R.LVB12.SE2END3 00_46 01_48
INT_R.LVB12.SE6END3 00_46 01_45
INT_R.LVB12.SW2END2 00_45 01_53
INT_R.LVB12.SW2END3 00_46 01_44
INT_R.LVB12.SW6END2 01_45 01_46
INT_R.LVB12.WR1END3 01_46 01_48
INT_R.LVB12.WW4END3 01_46 01_49
INT_R.NE2BEG0.LOGIC_OUTS0 09_05 15_04
INT_R.NE2BEG0.LOGIC_OUTS4 09_04 15_04
INT_R.NE2BEG0.LOGIC_OUTS8 11_04 15_04
@ -2040,6 +2203,8 @@ INT_R.NE6BEG0.LOGIC_OUTS22 06_04 07_05
INT_R.NE6BEG0.WW2END_N0_3 03_04 04_05
INT_R.NE6BEG0.EE2END0 03_04 05_07
INT_R.NE6BEG0.EE4END0 05_04 05_07
INT_R.NE6BEG0.LH12 05_04 07_05
INT_R.NE6BEG0.LV0 04_06 05_04
INT_R.NE6BEG0.NE2END0 02_05 03_05
INT_R.NE6BEG0.NE6END0 03_05 05_04
INT_R.NE6BEG0.NN2END0 03_04 03_05
@ -2057,6 +2222,8 @@ INT_R.NE6BEG1.LOGIC_OUTS19 06_20 07_21
INT_R.NE6BEG1.LOGIC_OUTS23 04_22 06_20
INT_R.NE6BEG1.EE2END1 03_20 05_23
INT_R.NE6BEG1.EE4END1 05_20 05_23
INT_R.NE6BEG1.LH6 05_20 07_21
INT_R.NE6BEG1.LV9 04_22 05_20
INT_R.NE6BEG1.NE2END1 02_21 03_21
INT_R.NE6BEG1.NE6END1 03_21 05_20
INT_R.NE6BEG1.NN2END1 03_20 03_21
@ -2075,6 +2242,8 @@ INT_R.NE6BEG2.LOGIC_OUTS16 04_38 06_36
INT_R.NE6BEG2.LOGIC_OUTS20 06_36 07_37
INT_R.NE6BEG2.EE2END2 03_36 05_39
INT_R.NE6BEG2.EE4END2 05_36 05_39
INT_R.NE6BEG2.LVB0 04_38 05_36
INT_R.NE6BEG2.LVB12 05_36 07_37
INT_R.NE6BEG2.NE2END2 02_37 03_37
INT_R.NE6BEG2.NE6END2 03_37 05_36
INT_R.NE6BEG2.NN2END2 03_36 03_37
@ -2093,6 +2262,8 @@ INT_R.NE6BEG3.LOGIC_OUTS17 06_52 07_53
INT_R.NE6BEG3.LOGIC_OUTS21 04_54 06_52
INT_R.NE6BEG3.EE2END3 03_52 05_55
INT_R.NE6BEG3.EE4END3 05_52 05_55
INT_R.NE6BEG3.LH0 04_54 05_52
INT_R.NE6BEG3.LV18 05_52 07_53
INT_R.NE6BEG3.NE2END3 02_53 03_53
INT_R.NE6BEG3.NE6END3 03_53 05_52
INT_R.NE6BEG3.NN2END3 03_52 03_53
@ -2102,6 +2273,7 @@ INT_R.NE6BEG3.NW6END3 04_53 06_52
INT_R.NE6BEG3.SE2END3 02_53 05_55
INT_R.NE6BEG3.SE6END3 05_55 06_52
INT_R.NE6BEG3.WW2END2 03_52 04_53
INT_R.NE6BEG3.WW4END3 04_53 05_52
INT_R.NL1BEG0.LOGIC_OUTS1 07_16 14_17
INT_R.NL1BEG0.LOGIC_OUTS5 11_17 14_17
INT_R.NL1BEG0.LOGIC_OUTS9 10_17 13_17
@ -2251,6 +2423,8 @@ INT_R.NN6BEG0.LOGIC_OUTS22 05_05 07_07
INT_R.NN6BEG0.WW2END_N0_3 02_07 04_04
INT_R.NN6BEG0.EE2END0 02_07 05_06
INT_R.NN6BEG0.EE4END0 04_07 05_06
INT_R.NN6BEG0.LH12 04_07 05_05
INT_R.NN6BEG0.LV0 04_07 06_06
INT_R.NN6BEG0.NE2END0 02_06 03_06
INT_R.NN6BEG0.NE6END0 02_06 04_07
INT_R.NN6BEG0.NN2END0 02_06 02_07
@ -2268,6 +2442,8 @@ INT_R.NN6BEG1.LOGIC_OUTS19 05_21 07_23
INT_R.NN6BEG1.LOGIC_OUTS23 06_22 07_23
INT_R.NN6BEG1.EE2END1 02_23 05_22
INT_R.NN6BEG1.EE4END1 04_23 05_22
INT_R.NN6BEG1.LH6 04_23 05_21
INT_R.NN6BEG1.LV9 04_23 06_22
INT_R.NN6BEG1.NE2END1 02_22 03_22
INT_R.NN6BEG1.NE6END1 02_22 04_23
INT_R.NN6BEG1.NN2END1 02_22 02_23
@ -2286,6 +2462,8 @@ INT_R.NN6BEG2.LOGIC_OUTS16 06_38 07_39
INT_R.NN6BEG2.LOGIC_OUTS20 05_37 07_39
INT_R.NN6BEG2.EE2END2 02_39 05_38
INT_R.NN6BEG2.EE4END2 04_39 05_38
INT_R.NN6BEG2.LVB0 04_39 06_38
INT_R.NN6BEG2.LVB12 04_39 05_37
INT_R.NN6BEG2.NE2END2 02_38 03_38
INT_R.NN6BEG2.NE6END2 02_38 04_39
INT_R.NN6BEG2.NN2END2 02_38 02_39
@ -2304,6 +2482,8 @@ INT_R.NN6BEG3.LOGIC_OUTS17 05_53 07_55
INT_R.NN6BEG3.LOGIC_OUTS21 06_54 07_55
INT_R.NN6BEG3.EE2END3 02_55 05_54
INT_R.NN6BEG3.EE4END3 04_55 05_54
INT_R.NN6BEG3.LH0 04_55 06_54
INT_R.NN6BEG3.LV18 04_55 05_53
INT_R.NN6BEG3.NE2END3 02_54 03_54
INT_R.NN6BEG3.NE6END3 02_54 04_55
INT_R.NN6BEG3.NN2END3 02_54 02_55
@ -2485,6 +2665,8 @@ INT_R.NW6BEG0.SS6END_N0_3 04_00 07_03
INT_R.NW6BEG0.SW2END_N0_3 03_02 04_00
INT_R.NW6BEG0.SW6END_N0_3 04_00 04_03
INT_R.NW6BEG0.WW2END_N0_3 02_02 02_03
INT_R.NW6BEG0.LH12 04_03 05_01
INT_R.NW6BEG0.LV0 04_03 06_02
INT_R.NW6BEG0.NE2END0 03_02 05_02
INT_R.NW6BEG0.NE6END0 04_03 05_02
INT_R.NW6BEG0.NN2END0 02_03 05_02
@ -2498,6 +2680,8 @@ INT_R.NW6BEG1.LOGIC_OUTS9 02_19 06_18
INT_R.NW6BEG1.LOGIC_OUTS13 02_19 05_17
INT_R.NW6BEG1.LOGIC_OUTS19 06_18 07_19
INT_R.NW6BEG1.LOGIC_OUTS23 05_17 07_19
INT_R.NW6BEG1.LH6 04_19 05_17
INT_R.NW6BEG1.LV9 04_19 06_18
INT_R.NW6BEG1.NE2END1 03_18 05_18
INT_R.NW6BEG1.NE6END1 04_19 05_18
INT_R.NW6BEG1.NN2END1 02_19 05_18
@ -2516,6 +2700,8 @@ INT_R.NW6BEG2.LOGIC_OUTS10 02_35 05_33
INT_R.NW6BEG2.LOGIC_OUTS14 02_35 06_34
INT_R.NW6BEG2.LOGIC_OUTS16 05_33 07_35
INT_R.NW6BEG2.LOGIC_OUTS20 06_34 07_35
INT_R.NW6BEG2.LVB0 04_35 06_34
INT_R.NW6BEG2.LVB12 04_35 05_33
INT_R.NW6BEG2.NE2END2 03_34 05_34
INT_R.NW6BEG2.NE6END2 04_35 05_34
INT_R.NW6BEG2.NN2END2 02_35 05_34
@ -2534,6 +2720,8 @@ INT_R.NW6BEG3.LOGIC_OUTS11 02_51 06_50
INT_R.NW6BEG3.LOGIC_OUTS15 02_51 05_49
INT_R.NW6BEG3.LOGIC_OUTS17 06_50 07_51
INT_R.NW6BEG3.LOGIC_OUTS21 05_49 07_51
INT_R.NW6BEG3.LH0 04_51 06_50
INT_R.NW6BEG3.LV18 04_51 05_49
INT_R.NW6BEG3.NE2END3 03_50 05_50
INT_R.NW6BEG3.NE6END3 04_51 05_50
INT_R.NW6BEG3.NN2END3 02_51 05_50
@ -2634,6 +2822,8 @@ INT_R.SE6BEG0.LOGIC_OUTS18 05_09 07_11
INT_R.SE6BEG0.LOGIC_OUTS22 06_10 07_11
INT_R.SE6BEG0.EE2END0 02_10 02_11
INT_R.SE6BEG0.EE4END0 02_10 04_11
INT_R.SE6BEG0.LH12 04_11 05_09
INT_R.SE6BEG0.LV0 04_11 06_10
INT_R.SE6BEG0.NE2END0 03_10 04_08
INT_R.SE6BEG0.NE6END0 04_08 04_11
INT_R.SE6BEG0.NN2END0 02_11 04_08
@ -2652,6 +2842,8 @@ INT_R.SE6BEG1.LOGIC_OUTS19 06_26 07_27
INT_R.SE6BEG1.LOGIC_OUTS23 05_25 07_27
INT_R.SE6BEG1.EE2END1 02_26 02_27
INT_R.SE6BEG1.EE4END1 02_26 04_27
INT_R.SE6BEG1.LH6 04_27 05_25
INT_R.SE6BEG1.LV9 04_27 06_26
INT_R.SE6BEG1.NE2END1 03_26 04_24
INT_R.SE6BEG1.NE6END1 04_24 04_27
INT_R.SE6BEG1.NN2END1 02_27 04_24
@ -2670,6 +2862,8 @@ INT_R.SE6BEG2.LOGIC_OUTS16 05_41 07_43
INT_R.SE6BEG2.LOGIC_OUTS20 06_42 07_43
INT_R.SE6BEG2.EE2END2 02_42 02_43
INT_R.SE6BEG2.EE4END2 02_42 04_43
INT_R.SE6BEG2.LVB0 04_43 06_42
INT_R.SE6BEG2.LVB12 04_43 05_41
INT_R.SE6BEG2.NE2END2 03_42 04_40
INT_R.SE6BEG2.NE6END2 04_40 04_43
INT_R.SE6BEG2.NN2END2 02_43 04_40
@ -2688,6 +2882,8 @@ INT_R.SE6BEG3.LOGIC_OUTS17 06_58 07_59
INT_R.SE6BEG3.LOGIC_OUTS21 05_57 07_59
INT_R.SE6BEG3.EE2END3 02_58 02_59
INT_R.SE6BEG3.EE4END3 02_58 04_59
INT_R.SE6BEG3.LH0 04_59 06_58
INT_R.SE6BEG3.LV18 04_59 05_57
INT_R.SE6BEG3.NE2END3 03_58 04_56
INT_R.SE6BEG3.NE6END3 04_56 04_59
INT_R.SE6BEG3.NN2END3 02_59 04_56
@ -2926,6 +3122,8 @@ INT_R.SS6BEG0.LOGIC_OUTS18 06_14 07_15
INT_R.SS6BEG0.LOGIC_OUTS22 05_13 07_15
INT_R.SS6BEG0.EE2END0 02_15 04_12
INT_R.SS6BEG0.EE4END0 04_12 04_15
INT_R.SS6BEG0.LH12 04_15 05_13
INT_R.SS6BEG0.LV0 04_15 06_14
INT_R.SS6BEG0.NW2END1 03_14 05_14
INT_R.SS6BEG0.NW6END1 05_14 07_15
INT_R.SS6BEG0.SE2END0 03_14 04_12
@ -2944,6 +3142,8 @@ INT_R.SS6BEG1.LOGIC_OUTS19 05_29 07_31
INT_R.SS6BEG1.LOGIC_OUTS23 06_30 07_31
INT_R.SS6BEG1.EE2END1 02_31 04_28
INT_R.SS6BEG1.EE4END1 04_28 04_31
INT_R.SS6BEG1.LH6 04_31 05_29
INT_R.SS6BEG1.LV9 04_31 06_30
INT_R.SS6BEG1.NW2END2 03_30 05_30
INT_R.SS6BEG1.NW6END2 05_30 07_31
INT_R.SS6BEG1.SE2END1 03_30 04_28
@ -2962,6 +3162,8 @@ INT_R.SS6BEG2.LOGIC_OUTS16 06_46 07_47
INT_R.SS6BEG2.LOGIC_OUTS20 05_45 07_47
INT_R.SS6BEG2.EE2END2 02_47 04_44
INT_R.SS6BEG2.EE4END2 04_44 04_47
INT_R.SS6BEG2.LVB0 04_47 06_46
INT_R.SS6BEG2.LVB12 04_47 05_45
INT_R.SS6BEG2.NW2END3 03_46 05_46
INT_R.SS6BEG2.NW6END3 05_46 07_47
INT_R.SS6BEG2.SE2END2 03_46 04_44
@ -2983,6 +3185,8 @@ INT_R.SS6BEG3.NW6END_S0_0 05_62 07_63
INT_R.SS6BEG3.WW4END_S0_0 04_63 05_62
INT_R.SS6BEG3.EE2END3 02_63 04_60
INT_R.SS6BEG3.EE4END3 04_60 04_63
INT_R.SS6BEG3.LH0 04_63 06_62
INT_R.SS6BEG3.LV18 04_63 05_61
INT_R.SS6BEG3.SE2END3 03_62 04_60
INT_R.SS6BEG3.SE6END3 04_60 07_63
INT_R.SS6BEG3.SS2END3 02_62 02_63
@ -3078,6 +3282,8 @@ INT_R.SW6BEG0.LOGIC_OUTS18 04_14 06_12
INT_R.SW6BEG0.LOGIC_OUTS22 06_12 07_13
INT_R.SW6BEG0.EE2END0 03_12 04_13
INT_R.SW6BEG0.EE4END0 04_13 05_12
INT_R.SW6BEG0.LH12 05_12 07_13
INT_R.SW6BEG0.LV0 04_14 05_12
INT_R.SW6BEG0.NW2END1 02_13 05_15
INT_R.SW6BEG0.NW6END1 05_15 06_12
INT_R.SW6BEG0.SE2END0 02_13 04_13
@ -3096,6 +3302,8 @@ INT_R.SW6BEG1.LOGIC_OUTS19 06_28 07_29
INT_R.SW6BEG1.LOGIC_OUTS23 04_30 06_28
INT_R.SW6BEG1.EE2END1 03_28 04_29
INT_R.SW6BEG1.EE4END1 04_29 05_28
INT_R.SW6BEG1.LH6 05_28 07_29
INT_R.SW6BEG1.LV9 04_30 05_28
INT_R.SW6BEG1.NW2END2 02_29 05_31
INT_R.SW6BEG1.NW6END2 05_31 06_28
INT_R.SW6BEG1.SE2END1 02_29 04_29
@ -3114,6 +3322,8 @@ INT_R.SW6BEG2.LOGIC_OUTS16 04_46 06_44
INT_R.SW6BEG2.LOGIC_OUTS20 06_44 07_45
INT_R.SW6BEG2.EE2END2 03_44 04_45
INT_R.SW6BEG2.EE4END2 04_45 05_44
INT_R.SW6BEG2.LVB0 04_46 05_44
INT_R.SW6BEG2.LVB12 05_44 07_45
INT_R.SW6BEG2.NW2END3 02_45 05_47
INT_R.SW6BEG2.NW6END3 05_47 06_44
INT_R.SW6BEG2.SE2END2 02_45 04_45
@ -3134,6 +3344,9 @@ INT_R.SW6BEG3.NW2END_S0_0 02_61 05_63
INT_R.SW6BEG3.NW6END_S0_0 05_63 06_60
INT_R.SW6BEG3.WW4END_S0_0 05_60 05_63
INT_R.SW6BEG3.EE2END3 03_60 04_61
INT_R.SW6BEG3.EE4END3 04_61 05_60
INT_R.SW6BEG3.LH0 04_62 05_60
INT_R.SW6BEG3.LV18 05_60 07_61
INT_R.SW6BEG3.SE2END3 02_61 04_61
INT_R.SW6BEG3.SE6END3 04_61 06_60
INT_R.SW6BEG3.SS2END3 03_60 03_61
@ -3352,6 +3565,8 @@ INT_R.WW4BEG0.SS6END_N0_3 04_01 06_00
INT_R.WW4BEG0.SW2END_N0_3 02_01 04_01
INT_R.WW4BEG0.SW6END_N0_3 04_01 05_00
INT_R.WW4BEG0.WW2END_N0_3 03_00 03_01
INT_R.WW4BEG0.LH12 05_00 07_01
INT_R.WW4BEG0.LV0 04_02 05_00
INT_R.WW4BEG0.NE2END0 02_01 05_03
INT_R.WW4BEG0.NE6END0 05_00 05_03
INT_R.WW4BEG0.NN2END0 03_00 05_03
@ -3365,6 +3580,8 @@ INT_R.WW4BEG1.LOGIC_OUTS9 03_16 04_18
INT_R.WW4BEG1.LOGIC_OUTS13 03_16 07_17
INT_R.WW4BEG1.LOGIC_OUTS19 04_18 06_16
INT_R.WW4BEG1.LOGIC_OUTS23 06_16 07_17
INT_R.WW4BEG1.LH6 05_16 07_17
INT_R.WW4BEG1.LV9 04_18 05_16
INT_R.WW4BEG1.NE2END1 02_17 05_19
INT_R.WW4BEG1.NE6END1 05_16 05_19
INT_R.WW4BEG1.NN2END1 03_16 05_19
@ -3383,7 +3600,10 @@ INT_R.WW4BEG2.LOGIC_OUTS10 03_32 07_33
INT_R.WW4BEG2.LOGIC_OUTS14 03_32 04_34
INT_R.WW4BEG2.LOGIC_OUTS16 06_32 07_33
INT_R.WW4BEG2.LOGIC_OUTS20 04_34 06_32
INT_R.WW4BEG2.LVB0 04_34 05_32
INT_R.WW4BEG2.LVB12 05_32 07_33
INT_R.WW4BEG2.NE2END2 02_33 05_35
INT_R.WW4BEG2.NE6END2 05_32 05_35
INT_R.WW4BEG2.NN2END2 03_32 05_35
INT_R.WW4BEG2.NN6END2 05_35 06_32
INT_R.WW4BEG2.NW2END2 02_33 03_33
@ -3400,7 +3620,10 @@ INT_R.WW4BEG3.LOGIC_OUTS11 03_48 04_50
INT_R.WW4BEG3.LOGIC_OUTS15 03_48 07_49
INT_R.WW4BEG3.LOGIC_OUTS17 04_50 06_48
INT_R.WW4BEG3.LOGIC_OUTS21 06_48 07_49
INT_R.WW4BEG3.LH0 04_50 05_48
INT_R.WW4BEG3.LV18 05_48 07_49
INT_R.WW4BEG3.NE2END3 02_49 05_51
INT_R.WW4BEG3.NE6END3 05_48 05_51
INT_R.WW4BEG3.NN2END3 03_48 05_51
INT_R.WW4BEG3.NN6END3 05_51 06_48
INT_R.WW4BEG3.NW2END3 02_49 03_49

8
artix7/tile_type_BRAM_L.json
View File

@ -7186,7 +7186,7 @@
"y_coord": 0
},
{
"name": "X0Y0",
"name": "X0Y29",
"prefix": "RAMB18",
"site_pins": {
"ADDRARDADDR0": "BRAM_FIFO18_ADDRARDADDR0",
@ -7350,10 +7350,10 @@
},
"type": "FIFO18E1",
"x_coord": 0,
"y_coord": 0
"y_coord": 29
},
{
"name": "X0Y1",
"name": "X0Y30",
"prefix": "RAMB18",
"site_pins": {
"ADDRARDADDR0": "BRAM_RAMB18_ADDRARDADDR0",
@ -7517,7 +7517,7 @@
},
"type": "RAMB18E1",
"x_coord": 0,
"y_coord": 1
"y_coord": 30
}
],
"tile_type": "BRAM_L",

8
artix7/tile_type_BRAM_R.json
View File

@ -6821,7 +6821,7 @@
},
"sites": [
{
"name": "X0Y17",
"name": "X0Y19",
"prefix": "RAMB18",
"site_pins": {
"ADDRARDADDR0": "BRAM_FIFO18_ADDRARDADDR0",
@ -6985,10 +6985,10 @@
},
"type": "FIFO18E1",
"x_coord": 0,
"y_coord": 17
"y_coord": 19
},
{
"name": "X0Y18",
"name": "X0Y20",
"prefix": "RAMB18",
"site_pins": {
"ADDRARDADDR0": "BRAM_RAMB18_ADDRARDADDR0",
@ -7152,7 +7152,7 @@
},
"type": "RAMB18E1",
"x_coord": 0,
"y_coord": 18
"y_coord": 20
},
{
"name": "X0Y0",

16
artix7/tile_type_CMT_TOP_L_UPPER_B.json
View File

@ -2856,7 +2856,7 @@
"y_coord": 0
},
{
"name": "X0Y5",
"name": "X0Y2",
"prefix": "PHASER_OUT_PHY",
"site_pins": {
"BURSTPENDING": "CMT_PHASER_OUT_CA_BURSTPENDING",
@ -2939,10 +2939,10 @@
},
"type": "PHASER_OUT_PHY",
"x_coord": 0,
"y_coord": 5
"y_coord": 2
},
{
"name": "X0Y5",
"name": "X0Y2",
"prefix": "PHASER_IN_PHY",
"site_pins": {
"BURSTPENDING": "CMT_PHASER_IN_CA_BURSTPENDING",
@ -3040,10 +3040,10 @@
},
"type": "PHASER_IN_PHY",
"x_coord": 0,
"y_coord": 5
"y_coord": 2
},
{
"name": "X0Y6",
"name": "X0Y3",
"prefix": "PHASER_OUT_PHY",
"site_pins": {
"BURSTPENDING": "CMT_PHASER_OUT_DB_BURSTPENDING",
@ -3126,10 +3126,10 @@
},
"type": "PHASER_OUT_PHY",
"x_coord": 0,
"y_coord": 6
"y_coord": 3
},
{
"name": "X0Y6",
"name": "X0Y3",
"prefix": "PHASER_IN_PHY",
"site_pins": {
"BURSTPENDING": "CMT_PHASER_IN_DB_BURSTPENDING",
@ -3227,7 +3227,7 @@
},
"type": "PHASER_IN_PHY",
"x_coord": 0,
"y_coord": 6
"y_coord": 3
}
],
"tile_type": "CMT_TOP_L_UPPER_B",

16
artix7/tile_type_CMT_TOP_R_UPPER_B.json
View File

@ -2856,7 +2856,7 @@
"y_coord": 0
},
{
"name": "X0Y5",
"name": "X0Y8",
"prefix": "PHASER_OUT_PHY",
"site_pins": {
"BURSTPENDING": "CMT_PHASER_OUT_CA_BURSTPENDING",
@ -2939,10 +2939,10 @@
},
"type": "PHASER_OUT_PHY",
"x_coord": 0,
"y_coord": 5
"y_coord": 8
},
{
"name": "X0Y5",
"name": "X0Y8",
"prefix": "PHASER_IN_PHY",
"site_pins": {
"BURSTPENDING": "CMT_PHASER_IN_CA_BURSTPENDING",
@ -3040,10 +3040,10 @@
},
"type": "PHASER_IN_PHY",
"x_coord": 0,
"y_coord": 5
"y_coord": 8
},
{
"name": "X0Y6",
"name": "X0Y9",
"prefix": "PHASER_OUT_PHY",
"site_pins": {
"BURSTPENDING": "CMT_PHASER_OUT_DB_BURSTPENDING",
@ -3126,10 +3126,10 @@
},
"type": "PHASER_OUT_PHY",
"x_coord": 0,
"y_coord": 6
"y_coord": 9
},
{
"name": "X0Y6",
"name": "X0Y9",
"prefix": "PHASER_IN_PHY",
"site_pins": {
"BURSTPENDING": "CMT_PHASER_IN_DB_BURSTPENDING",
@ -3227,7 +3227,7 @@
},
"type": "PHASER_IN_PHY",
"x_coord": 0,
"y_coord": 6
"y_coord": 9
}
],
"tile_type": "CMT_TOP_R_UPPER_B",

4
artix7/tile_type_DSP_R.json
View File

@ -6413,7 +6413,7 @@
"y_coord": 1
},
{
"name": "X10Y39",
"name": "X10Y0",
"prefix": "TIEOFF",
"site_pins": {
"HARD0": "DSP_GND_R",
@ -6421,7 +6421,7 @@
},
"type": "TIEOFF",
"x_coord": 10,
"y_coord": 39
"y_coord": 0
}
],
"tile_type": "DSP_R",

32
artix7/tile_type_HCLK_IOI3.json
View File

@ -1711,7 +1711,7 @@
},
"sites": [
{
"name": "X0Y7",
"name": "X0Y1",
"prefix": "BUFIO",
"site_pins": {
"I": "HCLK_IOI_IO_PLL_CLK3",
@ -1719,10 +1719,10 @@
},
"type": "BUFIO",
"x_coord": 0,
"y_coord": 7
"y_coord": 1
},
{
"name": "X0Y6",
"name": "X0Y0",
"prefix": "BUFIO",
"site_pins": {
"I": "HCLK_IOI_IO_PLL_CLK2",
@ -1730,10 +1730,10 @@
},
"type": "BUFIO",
"x_coord": 0,
"y_coord": 6
"y_coord": 0
},
{
"name": "X0Y9",
"name": "X0Y3",
"prefix": "BUFIO",
"site_pins": {
"I": "HCLK_IOI_IO_PLL_CLK1",
@ -1741,10 +1741,10 @@
},
"type": "BUFIO",
"x_coord": 0,
"y_coord": 9
"y_coord": 3
},
{
"name": "X0Y8",
"name": "X0Y2",
"prefix": "BUFIO",
"site_pins": {
"I": "HCLK_IOI_IO_PLL_CLK0",
@ -1752,10 +1752,10 @@
},
"type": "BUFIO",
"x_coord": 0,
"y_coord": 8
"y_coord": 2
},
{
"name": "X0Y7",
"name": "X0Y1",
"prefix": "BUFR",
"site_pins": {
"CE": "HCLK_IOI_BUFR3_CE",
@ -1765,10 +1765,10 @@
},
"type": "BUFR",
"x_coord": 0,
"y_coord": 7
"y_coord": 1
},
{
"name": "X0Y6",
"name": "X0Y0",
"prefix": "BUFR",
"site_pins": {
"CE": "HCLK_IOI_BUFR2_CE",
@ -1778,10 +1778,10 @@
},
"type": "BUFR",
"x_coord": 0,
"y_coord": 6
"y_coord": 0
},
{
"name": "X0Y9",
"name": "X0Y3",
"prefix": "BUFR",
"site_pins": {
"CE": "HCLK_IOI_BUFR1_CE",
@ -1791,10 +1791,10 @@
},
"type": "BUFR",
"x_coord": 0,
"y_coord": 9
"y_coord": 3
},
{
"name": "X0Y8",
"name": "X0Y2",
"prefix": "BUFR",
"site_pins": {
"CE": "HCLK_IOI_BUFR0_CE",
@ -1804,7 +1804,7 @@
},
"type": "BUFR",
"x_coord": 0,
"y_coord": 8
"y_coord": 2
},
{
"name": "X0Y0",

2
artix7/tilegrid.json
View File

@ -152936,7 +152936,7 @@
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}
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