Updating info based on "Merge pull request #549 from litghost/accelerate_post_processing".
See [Info File](Info.md) for details. Signed-off-by: Tim 'mithro' Ansell <me@mith.ro>
This commit is contained in:
Tim 'mithro' Ansell
parent
a111007f61
commit
b4360202a7
64
Info.md
64
Info.md
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@ -37,20 +37,20 @@ These files are released under the very permissive [CC0 1.0 Universal](COPYING).
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# Details
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Last updated on Wed Jan 30 04:31:46 UTC 2019 (2019-01-30T04:31:46+00:00).
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Last updated on Wed Jan 30 05:24:00 UTC 2019 (2019-01-30T05:24:00+00:00).
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Created using [Project X-Ray](https://github.com/SymbiFlow/prjxray) version [v0.0-1084-gafe50c6](https://github.com/SymbiFlow/prjxray/commit/afe50c68c464c0cd4a3fa92b6a07c9abbe41682f).
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Created using [Project X-Ray](https://github.com/SymbiFlow/prjxray) version [v0.0-1602-gf61ccd1](https://github.com/SymbiFlow/prjxray/commit/f61ccd1f2ae1fc2bb4f5a47ac5a97ca3c7a06ec6).
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Latest commit was;
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```
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commit afe50c68c464c0cd4a3fa92b6a07c9abbe41682f
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Merge: 8385636 5c82555
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Author: John McMaster <18452276+mcmasterg@users.noreply.github.com>
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Date: Wed Nov 28 14:28:03 2018 -0800
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commit f61ccd1f2ae1fc2bb4f5a47ac5a97ca3c7a06ec6
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Merge: 4efea26 9e585ef
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Author: litghost <537074+litghost@users.noreply.github.com>
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Date: Fri Jan 18 07:09:59 2019 -0800
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Merge pull request #275 from mcmasterg/rempips
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Merge pull request #549 from litghost/accelerate_post_processing
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Rempips
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Refactor 074 post-processing
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```
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@ -59,7 +59,7 @@ Date: Wed Nov 28 14:28:03 2018 -0800
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### Settings
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Created using following [settings/artix7.sh (sha256: 15398c7d0dd8a20e2b3d586ec845e9b1c2292587e308711eacf4fd31508821d5)](https://github.com/SymbiFlow/prjxray/blob/afe50c68c464c0cd4a3fa92b6a07c9abbe41682f/settings/artix7.sh)
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Created using following [settings/artix7.sh (sha256: 15398c7d0dd8a20e2b3d586ec845e9b1c2292587e308711eacf4fd31508821d5)](https://github.com/SymbiFlow/prjxray/blob/f61ccd1f2ae1fc2bb4f5a47ac5a97ca3c7a06ec6/settings/artix7.sh)
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```shell
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export XRAY_DATABASE="artix7"
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export XRAY_PART="xc7a50tfgg484-1"
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@ -110,10 +110,14 @@ Results have checksums;
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* [`8cac3f210fcc33e78fe576841c286a19138be26004dee70397f93a0b3019e451 ./artix7/harness/basys3/swbut/design.dcp`](./artix7/harness/basys3/swbut/design.dcp)
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* [`11d15eb449e9f42409e7187c26635d3facb6974cc0172819b4387ada2ff2532c ./artix7/harness/basys3/swbut/design.json`](./artix7/harness/basys3/swbut/design.json)
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* [`9df8eac3c11e57d81b4bf4a927ade787f881f0ef46c8ab610ca529f35e887689 ./artix7/harness/basys3/swbut/design.txt`](./artix7/harness/basys3/swbut/design.txt)
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* [`5acfc8680a96dfe832cbcf70e55d98617323e8f37405d3dca7bcfda9b31aef17 ./artix7/mask_clbll_l.db`](./artix7/mask_clbll_l.db)
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* [`615472574699aeeb8471224558ce13e18f14c3e65e3b5a2ecc862ee6d3e89211 ./artix7/mask_clbll_r.db`](./artix7/mask_clbll_r.db)
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* [`5acfc8680a96dfe832cbcf70e55d98617323e8f37405d3dca7bcfda9b31aef17 ./artix7/mask_clblm_l.db`](./artix7/mask_clblm_l.db)
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* [`615472574699aeeb8471224558ce13e18f14c3e65e3b5a2ecc862ee6d3e89211 ./artix7/mask_clblm_r.db`](./artix7/mask_clblm_r.db)
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* [`fca753747fb1d583483e22980c4dae3a2de6451a326d46eab3581ea6f50f5b2d ./artix7/mask_bram_l.block_ram.db`](./artix7/mask_bram_l.block_ram.db)
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* [`bed3ba955aa33b47eb3f4c218d8619e6e3f7c5b7f0d0de700827d666a54956f7 ./artix7/mask_bram_l.db`](./artix7/mask_bram_l.db)
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* [`fca753747fb1d583483e22980c4dae3a2de6451a326d46eab3581ea6f50f5b2d ./artix7/mask_bram_r.block_ram.db`](./artix7/mask_bram_r.block_ram.db)
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* [`bed3ba955aa33b47eb3f4c218d8619e6e3f7c5b7f0d0de700827d666a54956f7 ./artix7/mask_bram_r.db`](./artix7/mask_bram_r.db)
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* [`97501937512bf87b2ed203fc35a1532e4fa96a0ef0693925a7e32c8405d28b67 ./artix7/mask_clbll_l.db`](./artix7/mask_clbll_l.db)
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* [`121d2430c14b7170e91bfe974a8a028af667669764eb69a1cfd703ead54e1da4 ./artix7/mask_clbll_r.db`](./artix7/mask_clbll_r.db)
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* [`82693076cf011620e3cb609cc5c8781894cc5071b0c371f6931c8086e250c81a ./artix7/mask_clblm_l.db`](./artix7/mask_clblm_l.db)
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* [`9c7daaad1ec1ace4d819ad09a761d7d64afc1b617821d3b059dac4268f94cb46 ./artix7/mask_clblm_r.db`](./artix7/mask_clblm_r.db)
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* [`76d1e0bd4b7ad492cf3fe8698b2b5f46f7dcc5fe446984e5dccae373c63edafd ./artix7/mask_hclk_l.db`](./artix7/mask_hclk_l.db)
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* [`76d1e0bd4b7ad492cf3fe8698b2b5f46f7dcc5fe446984e5dccae373c63edafd ./artix7/mask_hclk_r.db`](./artix7/mask_hclk_r.db)
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* [`b4ffdb01ca695c7d52f34b88508aef6d596377fcffd7fa5e197212acc4b00e9a ./artix7/ppips_clbll_l.db`](./artix7/ppips_clbll_l.db)
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@ -125,17 +129,19 @@ Results have checksums;
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* [`292b55e44a2c49d9a7fc961ba37761ee8a29e50c790ef9da5e8c0d1c6c142b2f ./artix7/ppips_int_l.db`](./artix7/ppips_int_l.db)
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* [`60c352d2d6124ad3260ae0c3c151effa29aaad4c32fa2cee7787bfc43ca6aa89 ./artix7/ppips_int_r.db`](./artix7/ppips_int_r.db)
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* [`63cab7c6cb50b9a86cd6de4ec02cfba93b99ac622684a1196b3d70adb1472fc1 ./artix7/segbits_bram_l.block_ram.db`](./artix7/segbits_bram_l.block_ram.db)
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* [`4b616026c8d3cb1e4e61e5e5e5abdfa381e66ac6583cacc5262c69273ff813f0 ./artix7/segbits_bram_l.db`](./artix7/segbits_bram_l.db)
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* [`231e0e81ed1ad81e2e2f7a91e5eb32505453a8e6df4ab2e109872497f60a7195 ./artix7/segbits_bram_l.db`](./artix7/segbits_bram_l.db)
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* [`6daa967b706d7fc5cdf597ed9f142df8f3003ded2fee3d622d484b21ceda2827 ./artix7/segbits_bram_r.block_ram.db`](./artix7/segbits_bram_r.block_ram.db)
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* [`fb840f2f70f9203652d00f3b1dd5ea57e1b30d6ef49cb8c940b0f197b03ee5fe ./artix7/segbits_bram_r.db`](./artix7/segbits_bram_r.db)
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* [`47ecf9e30df92e809b0b9fc20a5b4048a46647a73cc1feec967a439bedb4045b ./artix7/segbits_clbll_l.db`](./artix7/segbits_clbll_l.db)
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* [`df25b39b33a981b1d20af7e4e04e1f39f9eb5b1d4b5afbaaf1e430525bf631b2 ./artix7/segbits_clbll_r.db`](./artix7/segbits_clbll_r.db)
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* [`631b4a3dc78241a6032b1c435097e26124023394f0ad16b50f5c9c841dd55407 ./artix7/segbits_clblm_l.db`](./artix7/segbits_clblm_l.db)
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* [`fda5c70c0a236d268af8821af66e452f82b69865cc51936e0130ab932560bb2b ./artix7/segbits_clblm_r.db`](./artix7/segbits_clblm_r.db)
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* [`41b85caddb170c03fc5a7ba588fcf509bb4fdd8baf9c2c3ca83c0063c89028ff ./artix7/segbits_bram_r.db`](./artix7/segbits_bram_r.db)
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* [`ef6706ef033396c75469738223e66d1b5f38b832e27b5bb80f07efd571e28fb7 ./artix7/segbits_clbll_l.db`](./artix7/segbits_clbll_l.db)
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* [`53c0ea2b05a2c4ddf2b6cce38073534d0c21b893fc5783dc777d97de2f2d6a9e ./artix7/segbits_clbll_r.db`](./artix7/segbits_clbll_r.db)
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* [`e6459c01d0c1c7724fa02716103fd02a3e2a75d6b7326f4c937f158a264ffe85 ./artix7/segbits_clblm_l.db`](./artix7/segbits_clblm_l.db)
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* [`5862b402a5e0a95be5f140112678fd39e1dc039bc339fda0e58111ca1ee9cb6e ./artix7/segbits_clblm_r.db`](./artix7/segbits_clblm_r.db)
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* [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./artix7/segbits_dsp_l.db`](./artix7/segbits_dsp_l.db)
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* [`718d2d615a8b636bdd102c3cf4e36be11f8f4d835c2a3c70fff7e03e9d95a763 ./artix7/segbits_dsp_r.db`](./artix7/segbits_dsp_r.db)
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* [`1c2c7229781a4a1d51bbbdeea76238b10497c043aaadf2a76de783041a201878 ./artix7/segbits_hclk_l.db`](./artix7/segbits_hclk_l.db)
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* [`51288ec0be63172fcb2a12a92853150c62a21e894c2d42a2586046c462bf57a9 ./artix7/segbits_hclk_r.db`](./artix7/segbits_hclk_r.db)
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* [`90a351d97c49ae04fc83b67bb71292b369dea648e75384276eb3655229cc02e0 ./artix7/segbits_int_l.db`](./artix7/segbits_int_l.db)
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* [`212fee423056293a26b17003c19ab8bb0931cf45c5d4bdb839df5af3bf0cdee9 ./artix7/segbits_int_r.db`](./artix7/segbits_int_r.db)
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* [`8458db29d99b66d3171471302c0df0790c7ce96f1424b830dabe1acad26b31e2 ./artix7/segbits_int_l.db`](./artix7/segbits_int_l.db)
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* [`21e905d7125a461233406a951f374b8d17da83ddd298810c7602c8666c0bb88a ./artix7/segbits_int_r.db`](./artix7/segbits_int_r.db)
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* [`2bc07bf06b86af1985fe1c76da7bd6d858768dd6d9e99344a3c52d490b797cdb ./artix7/settings.sh`](./artix7/settings.sh)
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* [`ac6ba9ad814503f0fdc1dabb4292aaccd1a2195f5b348276cfee12aed3d96a70 ./artix7/site_type_BSCAN.json`](./artix7/site_type_BSCAN.json)
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* [`64724ba2f8af98df5e1d92e5c2da2e6d5a41eec6580f796405e271dadb4e63be ./artix7/site_type_BUFGCTRL.json`](./artix7/site_type_BUFGCTRL.json)
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@ -183,8 +189,8 @@ Results have checksums;
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* [`f711f285e16aa11d4827ce8504e9413c8ccf87f9f86d108740738ae6cbb4f388 ./artix7/site_type_XADC.json`](./artix7/site_type_XADC.json)
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* [`0bfdad62f04128ca4d469aa18b179cbd3bf78e40c6af50450c9ca85bfffd746f ./artix7/tile_type_BRAM_INT_INTERFACE_L.json`](./artix7/tile_type_BRAM_INT_INTERFACE_L.json)
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* [`fd0b3b31118249e66193fa06633a58aa5d86820bed16d3f85497b886d2282845 ./artix7/tile_type_BRAM_INT_INTERFACE_R.json`](./artix7/tile_type_BRAM_INT_INTERFACE_R.json)
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* [`0872dcafbe45716e7f05f85e6f21fdf13b83f1b01ad425194a3beb91ebba9c45 ./artix7/tile_type_BRAM_L.json`](./artix7/tile_type_BRAM_L.json)
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* [`1f6fb30b7a5ea1931caad8efebaaef9e4c0f8c7505912418974d3922d9668ed5 ./artix7/tile_type_BRAM_R.json`](./artix7/tile_type_BRAM_R.json)
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* [`23af85ab67092eb90d6b05c3bff539499494eaecb07b5063baa2aa494063a1ec ./artix7/tile_type_BRAM_L.json`](./artix7/tile_type_BRAM_L.json)
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* [`4ee74c76ea5a5e3125080179eaa2abed0e86835088ae7d2ec38e0ca36f6851bb ./artix7/tile_type_BRAM_R.json`](./artix7/tile_type_BRAM_R.json)
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* [`29e4879a736ff9d43178ba3887ba47b8f1190464dabf4eef7c8fe8d8d23647c2 ./artix7/tile_type_BRKH_BRAM.json`](./artix7/tile_type_BRKH_BRAM.json)
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* [`fccd1abee620b9dc48534d82af9c84d7e4fb9f2fbeaa0d8bbef1ddab5d2d91c5 ./artix7/tile_type_BRKH_B_TERM_INT.json`](./artix7/tile_type_BRKH_B_TERM_INT.json)
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* [`1adbede824487b01b77eed4443ff5434c9473a067dae3c620df3ccca800951ac ./artix7/tile_type_BRKH_CLB.json`](./artix7/tile_type_BRKH_CLB.json)
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@ -225,10 +231,10 @@ Results have checksums;
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* [`e008d249e1f1dafa57e4ac276826c60e24b7fd29ec4e5acafd078c0604631afc ./artix7/tile_type_CMT_TOP_L_UPPER_T.json`](./artix7/tile_type_CMT_TOP_L_UPPER_T.json)
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* [`5b45ef7b0d9a366440da629a02330f51b6210652842fe723369e88f31df5d732 ./artix7/tile_type_CMT_TOP_R_LOWER_B.json`](./artix7/tile_type_CMT_TOP_R_LOWER_B.json)
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* [`6260182cedf2857372997d8b9a9b3d28504931d1c7ff5176d718dd44935354f0 ./artix7/tile_type_CMT_TOP_R_LOWER_T.json`](./artix7/tile_type_CMT_TOP_R_LOWER_T.json)
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* [`21e908de40301ce5b6d3a2479a5784c74f7227a1493941a5552845e794bdfa2b ./artix7/tile_type_CMT_TOP_R_UPPER_B.json`](./artix7/tile_type_CMT_TOP_R_UPPER_B.json)
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* [`1e5e97ee35ee5a8af5d7656618b11cdef2a452b9ac8f2257e1a9fb6070898804 ./artix7/tile_type_CMT_TOP_R_UPPER_B.json`](./artix7/tile_type_CMT_TOP_R_UPPER_B.json)
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* [`816d810709c3f54a33774c6a9acefe472cac1e5748d306e692524007b699ee35 ./artix7/tile_type_CMT_TOP_R_UPPER_T.json`](./artix7/tile_type_CMT_TOP_R_UPPER_T.json)
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* [`acd1f4d85f068809d6b1aa29426168b9418923631cc514a9159e95bfff599350 ./artix7/tile_type_DSP_L.json`](./artix7/tile_type_DSP_L.json)
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* [`bc2866210b36ed258d392e54b68d08171dd254eb1c976187259ce5bf403f920a ./artix7/tile_type_DSP_R.json`](./artix7/tile_type_DSP_R.json)
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* [`d4731d3d594d0f941c9e8565caf1d5fc8b2da870dc7b311e988b2216f15f7707 ./artix7/tile_type_DSP_L.json`](./artix7/tile_type_DSP_L.json)
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* [`0bc4bf5df264f500c0117a86ba085ffb2b6d6c910f0e677f538fcb79d70478a8 ./artix7/tile_type_DSP_R.json`](./artix7/tile_type_DSP_R.json)
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* [`01bb373548f7244412efb0a59b85203b18450d357c809b0c36ceaee46a81f3d1 ./artix7/tile_type_GTP_CHANNEL_0.json`](./artix7/tile_type_GTP_CHANNEL_0.json)
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* [`e34491f9e8151c172f330dbddd41ee646dbb526772409174810ca8872df4e6a1 ./artix7/tile_type_GTP_CHANNEL_1.json`](./artix7/tile_type_GTP_CHANNEL_1.json)
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* [`fcb1a2ac092a41409be635c1d61585f0e9d40d0ce86014e424ab99f2f50342ea ./artix7/tile_type_GTP_CHANNEL_2.json`](./artix7/tile_type_GTP_CHANNEL_2.json)
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@ -294,7 +300,7 @@ Results have checksums;
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* [`04409fb1eb974ee5af7e8115bf16aacfd4bda61094c7c4644cc020762a45f6c8 ./artix7/tile_type_VBRK_EXT.json`](./artix7/tile_type_VBRK_EXT.json)
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* [`004efcd7f9e172780ca7b8c379ec329bcfc52f86beaa1d997f41dbef7ac4a242 ./artix7/tile_type_VFRAME.json`](./artix7/tile_type_VFRAME.json)
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* [`1604d48580815e26069c2b4909fcc50e8e8f974ad0beb349ced2329c302bb06b ./artix7/tileconn.json`](./artix7/tileconn.json)
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* [`70fc6a01f6485a7229011d894a4e1832ab3ff01d39e319f9093d58b3dc94f226 ./artix7/tilegrid.json`](./artix7/tilegrid.json)
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* [`c4ca9177e8ecef5e3ce98abe3a33ab63d0585c853ab5b92d6d948e8dee2d3ba0 ./artix7/tilegrid.json`](./artix7/tilegrid.json)
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* [`4c20ee41ea32668919b7d91a7fabe38960e0ee4d5b3b83f1d18102d48895bf1c ./artix7/xc7a35tcpg236-1.json`](./artix7/xc7a35tcpg236-1.json)
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* [`ef0724733da87455426a0f833642d96e9d206d047f4eb97072c3093f80c40d7d ./artix7/xc7a35tcpg236-1.yaml`](./artix7/xc7a35tcpg236-1.yaml)
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* [`4c20ee41ea32668919b7d91a7fabe38960e0ee4d5b3b83f1d18102d48895bf1c ./artix7/xc7a35tcsg324-1.json`](./artix7/xc7a35tcsg324-1.json)
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@ -307,7 +313,7 @@ Results have checksums;
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### Settings
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Created using following [settings/kintex7.sh (sha256: b15d95afeae26cb0236f2a17b411f0242e4af0f3664d49dda936465ad3fa2b25)](https://github.com/SymbiFlow/prjxray/blob/afe50c68c464c0cd4a3fa92b6a07c9abbe41682f/settings/kintex7.sh)
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Created using following [settings/kintex7.sh (sha256: b15d95afeae26cb0236f2a17b411f0242e4af0f3664d49dda936465ad3fa2b25)](https://github.com/SymbiFlow/prjxray/blob/f61ccd1f2ae1fc2bb4f5a47ac5a97ca3c7a06ec6/settings/kintex7.sh)
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```shell
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export XRAY_DATABASE="kintex7"
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export XRAY_PART="xc7k70tfbg676-2"
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|
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@ -545,7 +551,7 @@ Results have checksums;
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### Settings
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|
||||
Created using following [settings/zynq7.sh (sha256: d956938bea24fcf8e8c7f71480116a9a668fb7be744e34a4e627b31a6b553f4b)](https://github.com/SymbiFlow/prjxray/blob/afe50c68c464c0cd4a3fa92b6a07c9abbe41682f/settings/zynq7.sh)
|
||||
Created using following [settings/zynq7.sh (sha256: d956938bea24fcf8e8c7f71480116a9a668fb7be744e34a4e627b31a6b553f4b)](https://github.com/SymbiFlow/prjxray/blob/f61ccd1f2ae1fc2bb4f5a47ac5a97ca3c7a06ec6/settings/zynq7.sh)
|
||||
```shell
|
||||
export XRAY_DATABASE="zynq7"
|
||||
export XRAY_PART="xc7z010clg400-1"
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -17,11 +17,16 @@ bit 00_17
|
|||
bit 00_18
|
||||
bit 00_19
|
||||
bit 00_20
|
||||
bit 00_21
|
||||
bit 00_22
|
||||
bit 00_23
|
||||
bit 00_24
|
||||
bit 00_25
|
||||
bit 00_26
|
||||
bit 00_27
|
||||
bit 00_28
|
||||
bit 00_29
|
||||
bit 00_30
|
||||
bit 00_32
|
||||
bit 00_33
|
||||
bit 00_34
|
||||
|
|
@ -38,7 +43,10 @@ bit 00_45
|
|||
bit 00_46
|
||||
bit 00_47
|
||||
bit 00_48
|
||||
bit 00_49
|
||||
bit 00_50
|
||||
bit 00_51
|
||||
bit 00_52
|
||||
bit 00_53
|
||||
bit 00_55
|
||||
bit 00_56
|
||||
|
|
@ -63,12 +71,16 @@ bit 01_11
|
|||
bit 01_13
|
||||
bit 01_14
|
||||
bit 01_15
|
||||
bit 01_16
|
||||
bit 01_19
|
||||
bit 01_20
|
||||
bit 01_21
|
||||
bit 01_22
|
||||
bit 01_23
|
||||
bit 01_24
|
||||
bit 01_25
|
||||
bit 01_26
|
||||
bit 01_28
|
||||
bit 01_29
|
||||
bit 01_31
|
||||
bit 01_32
|
||||
|
|
@ -89,6 +101,7 @@ bit 01_46
|
|||
bit 01_47
|
||||
bit 01_48
|
||||
bit 01_50
|
||||
bit 01_51
|
||||
bit 01_52
|
||||
bit 01_53
|
||||
bit 01_54
|
||||
|
|
@ -1889,6 +1902,7 @@ bit 30_27
|
|||
bit 30_28
|
||||
bit 30_29
|
||||
bit 30_30
|
||||
bit 30_32
|
||||
bit 30_33
|
||||
bit 30_34
|
||||
bit 30_35
|
||||
|
|
@ -1933,8 +1947,6 @@ bit 31_12
|
|||
bit 31_13
|
||||
bit 31_14
|
||||
bit 31_15
|
||||
bit 31_16
|
||||
bit 31_17
|
||||
bit 31_18
|
||||
bit 31_19
|
||||
bit 31_20
|
||||
|
|
@ -1948,6 +1960,7 @@ bit 31_27
|
|||
bit 31_28
|
||||
bit 31_29
|
||||
bit 31_30
|
||||
bit 31_32
|
||||
bit 31_33
|
||||
bit 31_34
|
||||
bit 31_35
|
||||
|
|
@ -1961,8 +1974,6 @@ bit 31_42
|
|||
bit 31_43
|
||||
bit 31_44
|
||||
bit 31_45
|
||||
bit 31_46
|
||||
bit 31_47
|
||||
bit 31_48
|
||||
bit 31_49
|
||||
bit 31_50
|
||||
|
|
|
|||
|
|
@ -17,11 +17,16 @@ bit 00_17
|
|||
bit 00_18
|
||||
bit 00_19
|
||||
bit 00_20
|
||||
bit 00_21
|
||||
bit 00_22
|
||||
bit 00_23
|
||||
bit 00_24
|
||||
bit 00_25
|
||||
bit 00_26
|
||||
bit 00_27
|
||||
bit 00_28
|
||||
bit 00_29
|
||||
bit 00_30
|
||||
bit 00_32
|
||||
bit 00_33
|
||||
bit 00_34
|
||||
|
|
@ -32,15 +37,14 @@ bit 00_38
|
|||
bit 00_39
|
||||
bit 00_41
|
||||
bit 00_42
|
||||
bit 00_43
|
||||
bit 00_44
|
||||
bit 00_45
|
||||
bit 00_46
|
||||
bit 00_47
|
||||
bit 00_48
|
||||
bit 00_49
|
||||
bit 00_50
|
||||
bit 00_53
|
||||
bit 00_51
|
||||
bit 00_52
|
||||
bit 00_55
|
||||
bit 00_56
|
||||
bit 00_57
|
||||
|
|
@ -64,12 +68,16 @@ bit 01_11
|
|||
bit 01_13
|
||||
bit 01_14
|
||||
bit 01_15
|
||||
bit 01_16
|
||||
bit 01_19
|
||||
bit 01_20
|
||||
bit 01_21
|
||||
bit 01_22
|
||||
bit 01_23
|
||||
bit 01_24
|
||||
bit 01_25
|
||||
bit 01_26
|
||||
bit 01_28
|
||||
bit 01_29
|
||||
bit 01_31
|
||||
bit 01_32
|
||||
|
|
@ -90,6 +98,7 @@ bit 01_46
|
|||
bit 01_47
|
||||
bit 01_48
|
||||
bit 01_50
|
||||
bit 01_51
|
||||
bit 01_52
|
||||
bit 01_53
|
||||
bit 01_54
|
||||
|
|
@ -1890,6 +1899,7 @@ bit 30_27
|
|||
bit 30_28
|
||||
bit 30_29
|
||||
bit 30_30
|
||||
bit 30_32
|
||||
bit 30_33
|
||||
bit 30_34
|
||||
bit 30_35
|
||||
|
|
@ -1934,8 +1944,6 @@ bit 31_12
|
|||
bit 31_13
|
||||
bit 31_14
|
||||
bit 31_15
|
||||
bit 31_16
|
||||
bit 31_17
|
||||
bit 31_18
|
||||
bit 31_19
|
||||
bit 31_20
|
||||
|
|
@ -1949,6 +1957,7 @@ bit 31_27
|
|||
bit 31_28
|
||||
bit 31_29
|
||||
bit 31_30
|
||||
bit 31_32
|
||||
bit 31_33
|
||||
bit 31_34
|
||||
bit 31_35
|
||||
|
|
@ -1962,8 +1971,6 @@ bit 31_42
|
|||
bit 31_43
|
||||
bit 31_44
|
||||
bit 31_45
|
||||
bit 31_46
|
||||
bit 31_47
|
||||
bit 31_48
|
||||
bit 31_49
|
||||
bit 31_50
|
||||
|
|
|
|||
|
|
@ -17,11 +17,16 @@ bit 00_17
|
|||
bit 00_18
|
||||
bit 00_19
|
||||
bit 00_20
|
||||
bit 00_21
|
||||
bit 00_22
|
||||
bit 00_23
|
||||
bit 00_24
|
||||
bit 00_25
|
||||
bit 00_26
|
||||
bit 00_27
|
||||
bit 00_28
|
||||
bit 00_29
|
||||
bit 00_30
|
||||
bit 00_32
|
||||
bit 00_33
|
||||
bit 00_34
|
||||
|
|
@ -30,6 +35,7 @@ bit 00_36
|
|||
bit 00_37
|
||||
bit 00_38
|
||||
bit 00_39
|
||||
bit 00_40
|
||||
bit 00_41
|
||||
bit 00_42
|
||||
bit 00_43
|
||||
|
|
@ -38,7 +44,10 @@ bit 00_45
|
|||
bit 00_46
|
||||
bit 00_47
|
||||
bit 00_48
|
||||
bit 00_49
|
||||
bit 00_50
|
||||
bit 00_51
|
||||
bit 00_52
|
||||
bit 00_53
|
||||
bit 00_55
|
||||
bit 00_56
|
||||
|
|
@ -63,12 +72,17 @@ bit 01_11
|
|||
bit 01_13
|
||||
bit 01_14
|
||||
bit 01_15
|
||||
bit 01_16
|
||||
bit 01_19
|
||||
bit 01_20
|
||||
bit 01_21
|
||||
bit 01_22
|
||||
bit 01_23
|
||||
bit 01_24
|
||||
bit 01_25
|
||||
bit 01_26
|
||||
bit 01_27
|
||||
bit 01_28
|
||||
bit 01_29
|
||||
bit 01_31
|
||||
bit 01_32
|
||||
|
|
@ -89,6 +103,7 @@ bit 01_46
|
|||
bit 01_47
|
||||
bit 01_48
|
||||
bit 01_50
|
||||
bit 01_51
|
||||
bit 01_52
|
||||
bit 01_53
|
||||
bit 01_54
|
||||
|
|
@ -1876,6 +1891,8 @@ bit 30_12
|
|||
bit 30_13
|
||||
bit 30_14
|
||||
bit 30_15
|
||||
bit 30_16
|
||||
bit 30_17
|
||||
bit 30_18
|
||||
bit 30_19
|
||||
bit 30_20
|
||||
|
|
@ -1889,6 +1906,7 @@ bit 30_27
|
|||
bit 30_28
|
||||
bit 30_29
|
||||
bit 30_30
|
||||
bit 30_32
|
||||
bit 30_33
|
||||
bit 30_34
|
||||
bit 30_35
|
||||
|
|
@ -1902,6 +1920,8 @@ bit 30_42
|
|||
bit 30_43
|
||||
bit 30_44
|
||||
bit 30_45
|
||||
bit 30_46
|
||||
bit 30_47
|
||||
bit 30_48
|
||||
bit 30_49
|
||||
bit 30_50
|
||||
|
|
@ -1948,6 +1968,7 @@ bit 31_27
|
|||
bit 31_28
|
||||
bit 31_29
|
||||
bit 31_30
|
||||
bit 31_32
|
||||
bit 31_33
|
||||
bit 31_34
|
||||
bit 31_35
|
||||
|
|
|
|||
|
|
@ -17,11 +17,16 @@ bit 00_17
|
|||
bit 00_18
|
||||
bit 00_19
|
||||
bit 00_20
|
||||
bit 00_21
|
||||
bit 00_22
|
||||
bit 00_23
|
||||
bit 00_24
|
||||
bit 00_25
|
||||
bit 00_26
|
||||
bit 00_27
|
||||
bit 00_28
|
||||
bit 00_29
|
||||
bit 00_30
|
||||
bit 00_32
|
||||
bit 00_33
|
||||
bit 00_34
|
||||
|
|
@ -30,17 +35,17 @@ bit 00_36
|
|||
bit 00_37
|
||||
bit 00_38
|
||||
bit 00_39
|
||||
bit 00_40
|
||||
bit 00_41
|
||||
bit 00_42
|
||||
bit 00_43
|
||||
bit 00_44
|
||||
bit 00_45
|
||||
bit 00_46
|
||||
bit 00_47
|
||||
bit 00_48
|
||||
bit 00_49
|
||||
bit 00_50
|
||||
bit 00_53
|
||||
bit 00_51
|
||||
bit 00_52
|
||||
bit 00_55
|
||||
bit 00_56
|
||||
bit 00_57
|
||||
|
|
@ -64,12 +69,17 @@ bit 01_11
|
|||
bit 01_13
|
||||
bit 01_14
|
||||
bit 01_15
|
||||
bit 01_16
|
||||
bit 01_19
|
||||
bit 01_20
|
||||
bit 01_21
|
||||
bit 01_22
|
||||
bit 01_23
|
||||
bit 01_24
|
||||
bit 01_25
|
||||
bit 01_26
|
||||
bit 01_27
|
||||
bit 01_28
|
||||
bit 01_29
|
||||
bit 01_31
|
||||
bit 01_32
|
||||
|
|
@ -90,6 +100,7 @@ bit 01_46
|
|||
bit 01_47
|
||||
bit 01_48
|
||||
bit 01_50
|
||||
bit 01_51
|
||||
bit 01_52
|
||||
bit 01_53
|
||||
bit 01_54
|
||||
|
|
@ -1877,6 +1888,8 @@ bit 30_12
|
|||
bit 30_13
|
||||
bit 30_14
|
||||
bit 30_15
|
||||
bit 30_16
|
||||
bit 30_17
|
||||
bit 30_18
|
||||
bit 30_19
|
||||
bit 30_20
|
||||
|
|
@ -1890,6 +1903,7 @@ bit 30_27
|
|||
bit 30_28
|
||||
bit 30_29
|
||||
bit 30_30
|
||||
bit 30_32
|
||||
bit 30_33
|
||||
bit 30_34
|
||||
bit 30_35
|
||||
|
|
@ -1903,6 +1917,8 @@ bit 30_42
|
|||
bit 30_43
|
||||
bit 30_44
|
||||
bit 30_45
|
||||
bit 30_46
|
||||
bit 30_47
|
||||
bit 30_48
|
||||
bit 30_49
|
||||
bit 30_50
|
||||
|
|
@ -1949,6 +1965,7 @@ bit 31_27
|
|||
bit 31_28
|
||||
bit 31_29
|
||||
bit 31_30
|
||||
bit 31_32
|
||||
bit 31_33
|
||||
bit 31_34
|
||||
bit 31_35
|
||||
|
|
|
|||
|
|
@ -1,3 +1,5 @@
|
|||
BRAM_L.RAMB18_Y0.DOA_REG 27_69
|
||||
BRAM_L.RAMB18_Y0.DOB_REG 27_72
|
||||
BRAM_L.RAMB18_Y0.INIT_A[0] 27_73
|
||||
BRAM_L.RAMB18_Y0.INIT_A[1] 27_65
|
||||
BRAM_L.RAMB18_Y0.INIT_A[2] 27_137
|
||||
|
|
@ -34,10 +36,12 @@ BRAM_L.RAMB18_Y0.INIT_B[14] 27_55
|
|||
BRAM_L.RAMB18_Y0.INIT_B[15] 27_39
|
||||
BRAM_L.RAMB18_Y0.INIT_B[16] 27_23
|
||||
BRAM_L.RAMB18_Y0.INIT_B[17] 27_07
|
||||
BRAM_L.RAMB18_Y0.READ_WIDTH_A_1 !27_35 !27_36 !27_37
|
||||
BRAM_L.RAMB18_Y0.READ_WIDTH_A_2 27_35 !27_36 !27_37
|
||||
BRAM_L.RAMB18_Y0.READ_WIDTH_A_4 !27_35 27_36 !27_37
|
||||
BRAM_L.RAMB18_Y0.READ_WIDTH_A_9 27_35 27_36 !27_37
|
||||
BRAM_L.RAMB18_Y0.READ_WIDTH_A_18 !27_35 !27_36 27_37
|
||||
BRAM_L.RAMB18_Y0.READ_WIDTH_B_1 !27_43 !27_44 !27_45
|
||||
BRAM_L.RAMB18_Y0.READ_WIDTH_B_2 27_43 !27_44 !27_45
|
||||
BRAM_L.RAMB18_Y0.READ_WIDTH_B_4 !27_43 27_44 !27_45
|
||||
BRAM_L.RAMB18_Y0.READ_WIDTH_B_9 27_43 27_44 !27_45
|
||||
|
|
@ -82,10 +86,12 @@ BRAM_L.RAMB18_Y0.WRITE_MODE_A_NO_CHANGE 27_64
|
|||
BRAM_L.RAMB18_Y0.WRITE_MODE_A_READ_FIRST 27_56
|
||||
BRAM_L.RAMB18_Y0.WRITE_MODE_B_NO_CHANGE 27_68
|
||||
BRAM_L.RAMB18_Y0.WRITE_MODE_B_READ_FIRST 27_67
|
||||
BRAM_L.RAMB18_Y0.WRITE_WIDTH_A_1 !27_51 !27_52 !27_53
|
||||
BRAM_L.RAMB18_Y0.WRITE_WIDTH_A_2 27_51 !27_52 !27_53
|
||||
BRAM_L.RAMB18_Y0.WRITE_WIDTH_A_4 !27_51 27_52 !27_53
|
||||
BRAM_L.RAMB18_Y0.WRITE_WIDTH_A_9 27_51 27_52 !27_53
|
||||
BRAM_L.RAMB18_Y0.WRITE_WIDTH_A_18 !27_51 !27_52 27_53
|
||||
BRAM_L.RAMB18_Y0.WRITE_WIDTH_B_1 !27_59 !27_60 !27_61
|
||||
BRAM_L.RAMB18_Y0.WRITE_WIDTH_B_2 27_59 !27_60 !27_61
|
||||
BRAM_L.RAMB18_Y0.WRITE_WIDTH_B_4 !27_59 27_60 !27_61
|
||||
BRAM_L.RAMB18_Y0.WRITE_WIDTH_B_9 27_59 27_60 !27_61
|
||||
|
|
@ -98,6 +104,8 @@ BRAM_L.RAMB18_Y0.ZINV_RSTRAMARSTRAM 27_116
|
|||
BRAM_L.RAMB18_Y0.ZINV_RSTRAMB 27_117
|
||||
BRAM_L.RAMB18_Y0.ZINV_RSTREGARSTREG 27_120
|
||||
BRAM_L.RAMB18_Y0.ZINV_RSTREGB 27_123
|
||||
BRAM_L.RAMB18_Y1.DOA_REG 27_251
|
||||
BRAM_L.RAMB18_Y1.DOB_REG 27_248
|
||||
BRAM_L.RAMB18_Y1.INIT_A[0] 27_249
|
||||
BRAM_L.RAMB18_Y1.INIT_A[1] 27_241
|
||||
BRAM_L.RAMB18_Y1.INIT_A[2] 27_313
|
||||
|
|
@ -134,10 +142,12 @@ BRAM_L.RAMB18_Y1.INIT_B[14] 27_231
|
|||
BRAM_L.RAMB18_Y1.INIT_B[15] 27_215
|
||||
BRAM_L.RAMB18_Y1.INIT_B[16] 27_199
|
||||
BRAM_L.RAMB18_Y1.INIT_B[17] 27_183
|
||||
BRAM_L.RAMB18_Y1.READ_WIDTH_A_1 !27_283 !27_284 !27_285
|
||||
BRAM_L.RAMB18_Y1.READ_WIDTH_A_2 !27_283 !27_284 27_285
|
||||
BRAM_L.RAMB18_Y1.READ_WIDTH_A_4 !27_283 27_284 !27_285
|
||||
BRAM_L.RAMB18_Y1.READ_WIDTH_A_9 !27_283 27_284 27_285
|
||||
BRAM_L.RAMB18_Y1.READ_WIDTH_A_18 27_283 !27_284 !27_285
|
||||
BRAM_L.RAMB18_Y1.READ_WIDTH_B_1 !27_275 !27_276 !27_277
|
||||
BRAM_L.RAMB18_Y1.READ_WIDTH_B_2 !27_275 !27_276 27_277
|
||||
BRAM_L.RAMB18_Y1.READ_WIDTH_B_4 !27_275 27_276 !27_277
|
||||
BRAM_L.RAMB18_Y1.READ_WIDTH_B_9 !27_275 27_276 27_277
|
||||
|
|
@ -182,10 +192,12 @@ BRAM_L.RAMB18_Y1.WRITE_MODE_A_NO_CHANGE 27_256
|
|||
BRAM_L.RAMB18_Y1.WRITE_MODE_A_READ_FIRST 27_264
|
||||
BRAM_L.RAMB18_Y1.WRITE_MODE_B_NO_CHANGE 27_252
|
||||
BRAM_L.RAMB18_Y1.WRITE_MODE_B_READ_FIRST 27_253
|
||||
BRAM_L.RAMB18_Y1.WRITE_WIDTH_A_1 !27_267 !27_268 !27_269
|
||||
BRAM_L.RAMB18_Y1.WRITE_WIDTH_A_2 !27_267 !27_268 27_269
|
||||
BRAM_L.RAMB18_Y1.WRITE_WIDTH_A_4 !27_267 27_268 !27_269
|
||||
BRAM_L.RAMB18_Y1.WRITE_WIDTH_A_9 !27_267 27_268 27_269
|
||||
BRAM_L.RAMB18_Y1.WRITE_WIDTH_A_18 27_267 !27_268 !27_269
|
||||
BRAM_L.RAMB18_Y1.WRITE_WIDTH_B_1 !27_259 !27_260 !27_261
|
||||
BRAM_L.RAMB18_Y1.WRITE_WIDTH_B_2 !27_259 !27_260 27_261
|
||||
BRAM_L.RAMB18_Y1.WRITE_WIDTH_B_4 !27_259 27_260 !27_261
|
||||
BRAM_L.RAMB18_Y1.WRITE_WIDTH_B_9 !27_259 27_260 27_261
|
||||
|
|
|
|||
|
|
@ -1,3 +1,5 @@
|
|||
BRAM_R.RAMB18_Y0.DOA_REG 27_69
|
||||
BRAM_R.RAMB18_Y0.DOB_REG 27_72
|
||||
BRAM_R.RAMB18_Y0.INIT_A[0] 27_73
|
||||
BRAM_R.RAMB18_Y0.INIT_A[1] 27_65
|
||||
BRAM_R.RAMB18_Y0.INIT_A[2] 27_137
|
||||
|
|
@ -34,10 +36,12 @@ BRAM_R.RAMB18_Y0.INIT_B[14] 27_55
|
|||
BRAM_R.RAMB18_Y0.INIT_B[15] 27_39
|
||||
BRAM_R.RAMB18_Y0.INIT_B[16] 27_23
|
||||
BRAM_R.RAMB18_Y0.INIT_B[17] 27_07
|
||||
BRAM_R.RAMB18_Y0.READ_WIDTH_A_1 !27_35 !27_36 !27_37
|
||||
BRAM_R.RAMB18_Y0.READ_WIDTH_A_2 27_35 !27_36 !27_37
|
||||
BRAM_R.RAMB18_Y0.READ_WIDTH_A_4 !27_35 27_36 !27_37
|
||||
BRAM_R.RAMB18_Y0.READ_WIDTH_A_9 27_35 27_36 !27_37
|
||||
BRAM_R.RAMB18_Y0.READ_WIDTH_A_18 !27_35 !27_36 27_37
|
||||
BRAM_R.RAMB18_Y0.READ_WIDTH_B_1 !27_43 !27_44 !27_45
|
||||
BRAM_R.RAMB18_Y0.READ_WIDTH_B_2 27_43 !27_44 !27_45
|
||||
BRAM_R.RAMB18_Y0.READ_WIDTH_B_4 !27_43 27_44 !27_45
|
||||
BRAM_R.RAMB18_Y0.READ_WIDTH_B_9 27_43 27_44 !27_45
|
||||
|
|
@ -82,10 +86,12 @@ BRAM_R.RAMB18_Y0.WRITE_MODE_A_NO_CHANGE 27_64
|
|||
BRAM_R.RAMB18_Y0.WRITE_MODE_A_READ_FIRST 27_56
|
||||
BRAM_R.RAMB18_Y0.WRITE_MODE_B_NO_CHANGE 27_68
|
||||
BRAM_R.RAMB18_Y0.WRITE_MODE_B_READ_FIRST 27_67
|
||||
BRAM_R.RAMB18_Y0.WRITE_WIDTH_A_1 !27_51 !27_52 !27_53
|
||||
BRAM_R.RAMB18_Y0.WRITE_WIDTH_A_2 27_51 !27_52 !27_53
|
||||
BRAM_R.RAMB18_Y0.WRITE_WIDTH_A_4 !27_51 27_52 !27_53
|
||||
BRAM_R.RAMB18_Y0.WRITE_WIDTH_A_9 27_51 27_52 !27_53
|
||||
BRAM_R.RAMB18_Y0.WRITE_WIDTH_A_18 !27_51 !27_52 27_53
|
||||
BRAM_R.RAMB18_Y0.WRITE_WIDTH_B_1 !27_59 !27_60 !27_61
|
||||
BRAM_R.RAMB18_Y0.WRITE_WIDTH_B_2 27_59 !27_60 !27_61
|
||||
BRAM_R.RAMB18_Y0.WRITE_WIDTH_B_4 !27_59 27_60 !27_61
|
||||
BRAM_R.RAMB18_Y0.WRITE_WIDTH_B_9 27_59 27_60 !27_61
|
||||
|
|
@ -98,6 +104,8 @@ BRAM_R.RAMB18_Y0.ZINV_RSTRAMARSTRAM 27_116
|
|||
BRAM_R.RAMB18_Y0.ZINV_RSTRAMB 27_117
|
||||
BRAM_R.RAMB18_Y0.ZINV_RSTREGARSTREG 27_120
|
||||
BRAM_R.RAMB18_Y0.ZINV_RSTREGB 27_123
|
||||
BRAM_R.RAMB18_Y1.DOA_REG 27_251
|
||||
BRAM_R.RAMB18_Y1.DOB_REG 27_248
|
||||
BRAM_R.RAMB18_Y1.INIT_A[0] 27_249
|
||||
BRAM_R.RAMB18_Y1.INIT_A[1] 27_241
|
||||
BRAM_R.RAMB18_Y1.INIT_A[2] 27_313
|
||||
|
|
@ -134,10 +142,12 @@ BRAM_R.RAMB18_Y1.INIT_B[14] 27_231
|
|||
BRAM_R.RAMB18_Y1.INIT_B[15] 27_215
|
||||
BRAM_R.RAMB18_Y1.INIT_B[16] 27_199
|
||||
BRAM_R.RAMB18_Y1.INIT_B[17] 27_183
|
||||
BRAM_R.RAMB18_Y1.READ_WIDTH_A_1 !27_283 !27_284 !27_285
|
||||
BRAM_R.RAMB18_Y1.READ_WIDTH_A_2 !27_283 !27_284 27_285
|
||||
BRAM_R.RAMB18_Y1.READ_WIDTH_A_4 !27_283 27_284 !27_285
|
||||
BRAM_R.RAMB18_Y1.READ_WIDTH_A_9 !27_283 27_284 27_285
|
||||
BRAM_R.RAMB18_Y1.READ_WIDTH_A_18 27_283 !27_284 !27_285
|
||||
BRAM_R.RAMB18_Y1.READ_WIDTH_B_1 !27_275 !27_276 !27_277
|
||||
BRAM_R.RAMB18_Y1.READ_WIDTH_B_2 !27_275 !27_276 27_277
|
||||
BRAM_R.RAMB18_Y1.READ_WIDTH_B_4 !27_275 27_276 !27_277
|
||||
BRAM_R.RAMB18_Y1.READ_WIDTH_B_9 !27_275 27_276 27_277
|
||||
|
|
@ -182,10 +192,12 @@ BRAM_R.RAMB18_Y1.WRITE_MODE_A_NO_CHANGE 27_256
|
|||
BRAM_R.RAMB18_Y1.WRITE_MODE_A_READ_FIRST 27_264
|
||||
BRAM_R.RAMB18_Y1.WRITE_MODE_B_NO_CHANGE 27_252
|
||||
BRAM_R.RAMB18_Y1.WRITE_MODE_B_READ_FIRST 27_253
|
||||
BRAM_R.RAMB18_Y1.WRITE_WIDTH_A_1 !27_267 !27_268 !27_269
|
||||
BRAM_R.RAMB18_Y1.WRITE_WIDTH_A_2 !27_267 !27_268 27_269
|
||||
BRAM_R.RAMB18_Y1.WRITE_WIDTH_A_4 !27_267 27_268 !27_269
|
||||
BRAM_R.RAMB18_Y1.WRITE_WIDTH_A_9 !27_267 27_268 27_269
|
||||
BRAM_R.RAMB18_Y1.WRITE_WIDTH_A_18 27_267 !27_268 !27_269
|
||||
BRAM_R.RAMB18_Y1.WRITE_WIDTH_B_1 !27_259 !27_260 !27_261
|
||||
BRAM_R.RAMB18_Y1.WRITE_WIDTH_B_2 !27_259 !27_260 27_261
|
||||
BRAM_R.RAMB18_Y1.WRITE_WIDTH_B_4 !27_259 27_260 !27_261
|
||||
BRAM_R.RAMB18_Y1.WRITE_WIDTH_B_9 !27_259 27_260 27_261
|
||||
|
|
|
|||
|
|
@ -74,7 +74,6 @@ CLBLL_L.SLICEL_X0.ALUT.INIT[60] 35_01
|
|||
CLBLL_L.SLICEL_X0.ALUT.INIT[61] 34_01
|
||||
CLBLL_L.SLICEL_X0.ALUT.INIT[62] 35_00
|
||||
CLBLL_L.SLICEL_X0.ALUT.INIT[63] 34_00
|
||||
CLBLL_L.SLICEL_X0.ALUT.RAM 31_16
|
||||
CLBLL_L.SLICEL_X0.AOUTMUX.A5Q !30_06 30_07 !30_08 !30_11
|
||||
CLBLL_L.SLICEL_X0.AOUTMUX.CY 30_06 !30_07 30_08 !30_11
|
||||
CLBLL_L.SLICEL_X0.AOUTMUX.XOR !30_06 !30_07 30_08 !30_11
|
||||
|
|
@ -157,7 +156,6 @@ CLBLL_L.SLICEL_X0.BLUT.INIT[60] 35_17
|
|||
CLBLL_L.SLICEL_X0.BLUT.INIT[61] 34_17
|
||||
CLBLL_L.SLICEL_X0.BLUT.INIT[62] 35_16
|
||||
CLBLL_L.SLICEL_X0.BLUT.INIT[63] 34_16
|
||||
CLBLL_L.SLICEL_X0.BLUT.RAM 31_17
|
||||
CLBLL_L.SLICEL_X0.BOUTMUX.B5Q !30_20 !30_21 !30_22 30_23
|
||||
CLBLL_L.SLICEL_X0.BOUTMUX.CY !30_20 30_21 30_22 !30_23
|
||||
CLBLL_L.SLICEL_X0.BOUTMUX.XOR !30_20 30_21 !30_22 !30_23
|
||||
|
|
@ -242,7 +240,6 @@ CLBLL_L.SLICEL_X0.CLUT.INIT[60] 35_33
|
|||
CLBLL_L.SLICEL_X0.CLUT.INIT[61] 34_33
|
||||
CLBLL_L.SLICEL_X0.CLUT.INIT[62] 35_32
|
||||
CLBLL_L.SLICEL_X0.CLUT.INIT[63] 34_32
|
||||
CLBLL_L.SLICEL_X0.CLUT.RAM 31_46
|
||||
CLBLL_L.SLICEL_X0.COUTMUX.C5Q !30_40 30_43 !30_44 !30_45
|
||||
CLBLL_L.SLICEL_X0.COUTMUX.CY 30_40 !30_43 30_44 !30_45
|
||||
CLBLL_L.SLICEL_X0.COUTMUX.XOR !30_40 !30_43 30_44 !30_45
|
||||
|
|
@ -324,9 +321,6 @@ CLBLL_L.SLICEL_X0.DLUT.INIT[60] 35_49
|
|||
CLBLL_L.SLICEL_X0.DLUT.INIT[61] 34_49
|
||||
CLBLL_L.SLICEL_X0.DLUT.INIT[62] 35_48
|
||||
CLBLL_L.SLICEL_X0.DLUT.INIT[63] 34_48
|
||||
CLBLL_L.SLICEL_X0.DLUT.RAM 31_47
|
||||
CLBLL_L.SLICEL_X0.DLUT.SMALL 01_59
|
||||
CLBLL_L.SLICEL_X0.DLUT.SRL 30_47
|
||||
CLBLL_L.SLICEL_X0.DOUTMUX.CY 30_51 30_52 !30_56 !30_57
|
||||
CLBLL_L.SLICEL_X0.DOUTMUX.D5Q !30_51 !30_52 !30_56 30_57
|
||||
CLBLL_L.SLICEL_X0.DOUTMUX.XOR 30_51 !30_52 !30_56 !30_57
|
||||
|
|
@ -334,9 +328,10 @@ CLBLL_L.SLICEL_X0.DOUTMUX.O5 !30_51 30_52 30_56 !30_57
|
|||
CLBLL_L.SLICEL_X0.DOUTMUX.O6 !30_51 !30_52 30_56 !30_57
|
||||
CLBLL_L.SLICEL_X0.FFSYNC 00_48
|
||||
CLBLL_L.SLICEL_X0.LATCH 30_32
|
||||
CLBLL_L.SLICEL_X0.PRECYINIT.1 00_12 !30_13 !30_14
|
||||
CLBLL_L.SLICEL_X0.PRECYINIT.AX !00_12 !30_13 30_14
|
||||
CLBLL_L.SLICEL_X0.PRECYINIT.CIN !00_12 30_13 !30_14
|
||||
CLBLL_L.SLICEL_X0.PRECYINIT.C0 !00_12 !30_13 !30_14
|
||||
CLBLL_L.SLICEL_X0.PRECYINIT.C1 00_12 !30_13 !30_14
|
||||
CLBLL_L.SLICEL_X0.SRUSEDMUX 01_35
|
||||
CLBLL_L.SLICEL_X0.CARRY4.ACY0 30_15
|
||||
CLBLL_L.SLICEL_X0.CARRY4.BCY0 01_15
|
||||
|
|
@ -672,9 +667,10 @@ CLBLL_L.SLICEL_X1.DOUTMUX.O5 !30_53 !31_53 31_56 31_57
|
|||
CLBLL_L.SLICEL_X1.DOUTMUX.O6 !30_53 !31_53 31_56 !31_57
|
||||
CLBLL_L.SLICEL_X1.FFSYNC 01_31
|
||||
CLBLL_L.SLICEL_X1.LATCH 31_32
|
||||
CLBLL_L.SLICEL_X1.PRECYINIT.1 01_11 !31_12 !31_13
|
||||
CLBLL_L.SLICEL_X1.PRECYINIT.AX !01_11 !31_12 31_13
|
||||
CLBLL_L.SLICEL_X1.PRECYINIT.CIN !01_11 31_12 !31_13
|
||||
CLBLL_L.SLICEL_X1.PRECYINIT.C0 !01_11 !31_12 !31_13
|
||||
CLBLL_L.SLICEL_X1.PRECYINIT.C1 01_11 !31_12 !31_13
|
||||
CLBLL_L.SLICEL_X1.SRUSEDMUX 00_32
|
||||
CLBLL_L.SLICEL_X1.CARRY4.ACY0 31_14
|
||||
CLBLL_L.SLICEL_X1.CARRY4.BCY0 00_08
|
||||
|
|
|
|||
|
|
@ -74,7 +74,6 @@ CLBLL_R.SLICEL_X0.ALUT.INIT[60] 35_01
|
|||
CLBLL_R.SLICEL_X0.ALUT.INIT[61] 34_01
|
||||
CLBLL_R.SLICEL_X0.ALUT.INIT[62] 35_00
|
||||
CLBLL_R.SLICEL_X0.ALUT.INIT[63] 34_00
|
||||
CLBLL_R.SLICEL_X0.ALUT.RAM 31_16
|
||||
CLBLL_R.SLICEL_X0.AOUTMUX.A5Q !30_06 30_07 !30_08 !30_11
|
||||
CLBLL_R.SLICEL_X0.AOUTMUX.CY 30_06 !30_07 30_08 !30_11
|
||||
CLBLL_R.SLICEL_X0.AOUTMUX.XOR !30_06 !30_07 30_08 !30_11
|
||||
|
|
@ -157,7 +156,6 @@ CLBLL_R.SLICEL_X0.BLUT.INIT[60] 35_17
|
|||
CLBLL_R.SLICEL_X0.BLUT.INIT[61] 34_17
|
||||
CLBLL_R.SLICEL_X0.BLUT.INIT[62] 35_16
|
||||
CLBLL_R.SLICEL_X0.BLUT.INIT[63] 34_16
|
||||
CLBLL_R.SLICEL_X0.BLUT.RAM 31_17
|
||||
CLBLL_R.SLICEL_X0.BOUTMUX.B5Q !30_20 !30_21 !30_22 30_23
|
||||
CLBLL_R.SLICEL_X0.BOUTMUX.CY !30_20 30_21 30_22 !30_23
|
||||
CLBLL_R.SLICEL_X0.BOUTMUX.XOR !30_20 30_21 !30_22 !30_23
|
||||
|
|
@ -242,7 +240,6 @@ CLBLL_R.SLICEL_X0.CLUT.INIT[60] 35_33
|
|||
CLBLL_R.SLICEL_X0.CLUT.INIT[61] 34_33
|
||||
CLBLL_R.SLICEL_X0.CLUT.INIT[62] 35_32
|
||||
CLBLL_R.SLICEL_X0.CLUT.INIT[63] 34_32
|
||||
CLBLL_R.SLICEL_X0.CLUT.RAM 31_46
|
||||
CLBLL_R.SLICEL_X0.COUTMUX.C5Q !30_40 30_43 !30_44 !30_45
|
||||
CLBLL_R.SLICEL_X0.COUTMUX.CY 30_40 !30_43 30_44 !30_45
|
||||
CLBLL_R.SLICEL_X0.COUTMUX.XOR !30_40 !30_43 30_44 !30_45
|
||||
|
|
@ -324,9 +321,6 @@ CLBLL_R.SLICEL_X0.DLUT.INIT[60] 35_49
|
|||
CLBLL_R.SLICEL_X0.DLUT.INIT[61] 34_49
|
||||
CLBLL_R.SLICEL_X0.DLUT.INIT[62] 35_48
|
||||
CLBLL_R.SLICEL_X0.DLUT.INIT[63] 34_48
|
||||
CLBLL_R.SLICEL_X0.DLUT.RAM 31_47
|
||||
CLBLL_R.SLICEL_X0.DLUT.SMALL 01_59
|
||||
CLBLL_R.SLICEL_X0.DLUT.SRL 30_47
|
||||
CLBLL_R.SLICEL_X0.DOUTMUX.CY 30_51 30_52 !30_56 !30_57
|
||||
CLBLL_R.SLICEL_X0.DOUTMUX.D5Q !30_51 !30_52 !30_56 30_57
|
||||
CLBLL_R.SLICEL_X0.DOUTMUX.XOR 30_51 !30_52 !30_56 !30_57
|
||||
|
|
@ -334,9 +328,10 @@ CLBLL_R.SLICEL_X0.DOUTMUX.O5 !30_51 30_52 30_56 !30_57
|
|||
CLBLL_R.SLICEL_X0.DOUTMUX.O6 !30_51 !30_52 30_56 !30_57
|
||||
CLBLL_R.SLICEL_X0.FFSYNC 00_48
|
||||
CLBLL_R.SLICEL_X0.LATCH 30_32
|
||||
CLBLL_R.SLICEL_X0.PRECYINIT.1 00_12 !30_13 !30_14
|
||||
CLBLL_R.SLICEL_X0.PRECYINIT.AX !00_12 !30_13 30_14
|
||||
CLBLL_R.SLICEL_X0.PRECYINIT.CIN !00_12 30_13 !30_14
|
||||
CLBLL_R.SLICEL_X0.PRECYINIT.C0 !00_12 !30_13 !30_14
|
||||
CLBLL_R.SLICEL_X0.PRECYINIT.C1 00_12 !30_13 !30_14
|
||||
CLBLL_R.SLICEL_X0.SRUSEDMUX 01_35
|
||||
CLBLL_R.SLICEL_X0.CARRY4.ACY0 30_15
|
||||
CLBLL_R.SLICEL_X0.CARRY4.BCY0 01_15
|
||||
|
|
@ -672,9 +667,10 @@ CLBLL_R.SLICEL_X1.DOUTMUX.O5 !30_53 !31_53 31_56 31_57
|
|||
CLBLL_R.SLICEL_X1.DOUTMUX.O6 !30_53 !31_53 31_56 !31_57
|
||||
CLBLL_R.SLICEL_X1.FFSYNC 01_31
|
||||
CLBLL_R.SLICEL_X1.LATCH 31_32
|
||||
CLBLL_R.SLICEL_X1.PRECYINIT.1 01_11 !31_12 !31_13
|
||||
CLBLL_R.SLICEL_X1.PRECYINIT.AX !01_11 !31_12 31_13
|
||||
CLBLL_R.SLICEL_X1.PRECYINIT.CIN !01_11 31_12 !31_13
|
||||
CLBLL_R.SLICEL_X1.PRECYINIT.C0 !01_11 !31_12 !31_13
|
||||
CLBLL_R.SLICEL_X1.PRECYINIT.C1 01_11 !31_12 !31_13
|
||||
CLBLL_R.SLICEL_X1.SRUSEDMUX 00_32
|
||||
CLBLL_R.SLICEL_X1.CARRY4.ACY0 31_14
|
||||
CLBLL_R.SLICEL_X1.CARRY4.BCY0 00_08
|
||||
|
|
|
|||
|
|
@ -328,9 +328,10 @@ CLBLM_L.SLICEL_X1.DOUTMUX.O5 !30_53 !31_53 31_56 31_57
|
|||
CLBLM_L.SLICEL_X1.DOUTMUX.O6 !30_53 !31_53 31_56 !31_57
|
||||
CLBLM_L.SLICEL_X1.FFSYNC 01_31
|
||||
CLBLM_L.SLICEL_X1.LATCH 31_32
|
||||
CLBLM_L.SLICEL_X1.PRECYINIT.1 01_11 !31_12 !31_13
|
||||
CLBLM_L.SLICEL_X1.PRECYINIT.AX !01_11 !31_12 31_13
|
||||
CLBLM_L.SLICEL_X1.PRECYINIT.CIN !01_11 31_12 !31_13
|
||||
CLBLM_L.SLICEL_X1.PRECYINIT.C0 !01_11 !31_12 !31_13
|
||||
CLBLM_L.SLICEL_X1.PRECYINIT.C1 01_11 !31_12 !31_13
|
||||
CLBLM_L.SLICEL_X1.SRUSEDMUX 00_32
|
||||
CLBLM_L.SLICEL_X1.CARRY4.ACY0 31_14
|
||||
CLBLM_L.SLICEL_X1.CARRY4.BCY0 00_08
|
||||
|
|
@ -681,9 +682,10 @@ CLBLM_L.SLICEM_X0.DOUTMUX.O5 !30_51 30_52 30_56 !30_57
|
|||
CLBLM_L.SLICEM_X0.DOUTMUX.O6 !30_51 !30_52 30_56 !30_57
|
||||
CLBLM_L.SLICEM_X0.FFSYNC 00_48
|
||||
CLBLM_L.SLICEM_X0.LATCH 30_32
|
||||
CLBLM_L.SLICEM_X0.PRECYINIT.1 00_12 !30_13 !30_14
|
||||
CLBLM_L.SLICEM_X0.PRECYINIT.AX !00_12 !30_13 30_14
|
||||
CLBLM_L.SLICEM_X0.PRECYINIT.CIN !00_12 30_13 !30_14
|
||||
CLBLM_L.SLICEM_X0.PRECYINIT.C0 !00_12 !30_13 !30_14
|
||||
CLBLM_L.SLICEM_X0.PRECYINIT.C1 00_12 !30_13 !30_14
|
||||
CLBLM_L.SLICEM_X0.SRUSEDMUX 01_35
|
||||
CLBLM_L.SLICEM_X0.WA7USED 00_40
|
||||
CLBLM_L.SLICEM_X0.WA8USED 01_27
|
||||
|
|
|
|||
|
|
@ -328,9 +328,10 @@ CLBLM_R.SLICEL_X1.DOUTMUX.O5 !30_53 !31_53 31_56 31_57
|
|||
CLBLM_R.SLICEL_X1.DOUTMUX.O6 !30_53 !31_53 31_56 !31_57
|
||||
CLBLM_R.SLICEL_X1.FFSYNC 01_31
|
||||
CLBLM_R.SLICEL_X1.LATCH 31_32
|
||||
CLBLM_R.SLICEL_X1.PRECYINIT.1 01_11 !31_12 !31_13
|
||||
CLBLM_R.SLICEL_X1.PRECYINIT.AX !01_11 !31_12 31_13
|
||||
CLBLM_R.SLICEL_X1.PRECYINIT.CIN !01_11 31_12 !31_13
|
||||
CLBLM_R.SLICEL_X1.PRECYINIT.C0 !01_11 !31_12 !31_13
|
||||
CLBLM_R.SLICEL_X1.PRECYINIT.C1 01_11 !31_12 !31_13
|
||||
CLBLM_R.SLICEL_X1.SRUSEDMUX 00_32
|
||||
CLBLM_R.SLICEL_X1.CARRY4.ACY0 31_14
|
||||
CLBLM_R.SLICEL_X1.CARRY4.BCY0 00_08
|
||||
|
|
@ -681,9 +682,10 @@ CLBLM_R.SLICEM_X0.DOUTMUX.O5 !30_51 30_52 30_56 !30_57
|
|||
CLBLM_R.SLICEM_X0.DOUTMUX.O6 !30_51 !30_52 30_56 !30_57
|
||||
CLBLM_R.SLICEM_X0.FFSYNC 00_48
|
||||
CLBLM_R.SLICEM_X0.LATCH 30_32
|
||||
CLBLM_R.SLICEM_X0.PRECYINIT.1 00_12 !30_13 !30_14
|
||||
CLBLM_R.SLICEM_X0.PRECYINIT.AX !00_12 !30_13 30_14
|
||||
CLBLM_R.SLICEM_X0.PRECYINIT.CIN !00_12 30_13 !30_14
|
||||
CLBLM_R.SLICEM_X0.PRECYINIT.C0 !00_12 !30_13 !30_14
|
||||
CLBLM_R.SLICEM_X0.PRECYINIT.C1 00_12 !30_13 !30_14
|
||||
CLBLM_R.SLICEM_X0.SRUSEDMUX 01_35
|
||||
CLBLM_R.SLICEM_X0.WA7USED 00_40
|
||||
CLBLM_R.SLICEM_X0.WA8USED 01_27
|
||||
|
|
|
|||
|
|
@ -0,0 +1,192 @@
|
|||
DSP_R.DSP_0.MASK[0] 27_01
|
||||
DSP_R.DSP_0.MASK[1] 26_03
|
||||
DSP_R.DSP_0.MASK[2] 27_06
|
||||
DSP_R.DSP_0.MASK[3] 26_07
|
||||
DSP_R.DSP_0.MASK[4] 26_10
|
||||
DSP_R.DSP_0.MASK[5] 27_11
|
||||
DSP_R.DSP_0.MASK[6] 26_18
|
||||
DSP_R.DSP_0.MASK[7] 27_19
|
||||
DSP_R.DSP_0.MASK[8] 26_22
|
||||
DSP_R.DSP_0.MASK[9] 27_23
|
||||
DSP_R.DSP_0.MASK[10] 27_26
|
||||
DSP_R.DSP_0.MASK[11] 26_28
|
||||
DSP_R.DSP_0.MASK[12] 26_41
|
||||
DSP_R.DSP_0.MASK[13] 27_42
|
||||
DSP_R.DSP_0.MASK[14] 26_45
|
||||
DSP_R.DSP_0.MASK[15] 27_46
|
||||
DSP_R.DSP_0.MASK[16] 26_49
|
||||
DSP_R.DSP_0.MASK[17] 27_50
|
||||
DSP_R.DSP_0.MASK[18] 27_57
|
||||
DSP_R.DSP_0.MASK[19] 26_59
|
||||
DSP_R.DSP_0.MASK[20] 26_62
|
||||
DSP_R.DSP_0.MASK[21] 27_63
|
||||
DSP_R.DSP_0.MASK[22] 26_66
|
||||
DSP_R.DSP_0.MASK[23] 27_67
|
||||
DSP_R.DSP_0.MASK[24] 27_86
|
||||
DSP_R.DSP_0.MASK[25] 26_88
|
||||
DSP_R.DSP_0.MASK[26] 27_90
|
||||
DSP_R.DSP_0.MASK[27] 26_92
|
||||
DSP_R.DSP_0.MASK[28] 27_94
|
||||
DSP_R.DSP_0.MASK[29] 26_96
|
||||
DSP_R.DSP_0.MASK[30] 27_102
|
||||
DSP_R.DSP_0.MASK[31] 26_104
|
||||
DSP_R.DSP_0.MASK[32] 27_106
|
||||
DSP_R.DSP_0.MASK[33] 26_108
|
||||
DSP_R.DSP_0.MASK[34] 27_110
|
||||
DSP_R.DSP_0.MASK[35] 26_112
|
||||
DSP_R.DSP_0.MASK[36] 27_127
|
||||
DSP_R.DSP_0.MASK[37] 26_129
|
||||
DSP_R.DSP_0.MASK[38] 26_132
|
||||
DSP_R.DSP_0.MASK[39] 27_133
|
||||
DSP_R.DSP_0.MASK[40] 26_136
|
||||
DSP_R.DSP_0.MASK[41] 27_137
|
||||
DSP_R.DSP_0.MASK[42] 27_144
|
||||
DSP_R.DSP_0.MASK[43] 26_146
|
||||
DSP_R.DSP_0.MASK[44] 26_149
|
||||
DSP_R.DSP_0.MASK[45] 27_150
|
||||
DSP_R.DSP_0.MASK[46] 26_153
|
||||
DSP_R.DSP_0.MASK[47] 26_154
|
||||
DSP_R.DSP_0.PATTERN[0] 26_01
|
||||
DSP_R.DSP_0.PATTERN[1] 26_04
|
||||
DSP_R.DSP_0.PATTERN[2] 26_05
|
||||
DSP_R.DSP_0.PATTERN[3] 27_08
|
||||
DSP_R.DSP_0.PATTERN[4] 26_09
|
||||
DSP_R.DSP_0.PATTERN[5] 26_12
|
||||
DSP_R.DSP_0.PATTERN[6] 27_17
|
||||
DSP_R.DSP_0.PATTERN[7] 26_20
|
||||
DSP_R.DSP_0.PATTERN[8] 27_21
|
||||
DSP_R.DSP_0.PATTERN[9] 27_24
|
||||
DSP_R.DSP_0.PATTERN[10] 26_26
|
||||
DSP_R.DSP_0.PATTERN[11] 26_29
|
||||
DSP_R.DSP_0.PATTERN[12] 27_40
|
||||
DSP_R.DSP_0.PATTERN[13] 26_43
|
||||
DSP_R.DSP_0.PATTERN[14] 27_44
|
||||
DSP_R.DSP_0.PATTERN[15] 26_47
|
||||
DSP_R.DSP_0.PATTERN[16] 27_48
|
||||
DSP_R.DSP_0.PATTERN[17] 26_51
|
||||
DSP_R.DSP_0.PATTERN[18] 26_57
|
||||
DSP_R.DSP_0.PATTERN[19] 26_60
|
||||
DSP_R.DSP_0.PATTERN[20] 27_61
|
||||
DSP_R.DSP_0.PATTERN[21] 26_64
|
||||
DSP_R.DSP_0.PATTERN[22] 27_65
|
||||
DSP_R.DSP_0.PATTERN[23] 26_68
|
||||
DSP_R.DSP_0.PATTERN[24] 26_86
|
||||
DSP_R.DSP_0.PATTERN[25] 27_88
|
||||
DSP_R.DSP_0.PATTERN[26] 26_90
|
||||
DSP_R.DSP_0.PATTERN[27] 27_92
|
||||
DSP_R.DSP_0.PATTERN[28] 26_94
|
||||
DSP_R.DSP_0.PATTERN[29] 26_97
|
||||
DSP_R.DSP_0.PATTERN[30] 27_101
|
||||
DSP_R.DSP_0.PATTERN[31] 27_104
|
||||
DSP_R.DSP_0.PATTERN[32] 26_106
|
||||
DSP_R.DSP_0.PATTERN[33] 27_108
|
||||
DSP_R.DSP_0.PATTERN[34] 26_110
|
||||
DSP_R.DSP_0.PATTERN[35] 27_112
|
||||
DSP_R.DSP_0.PATTERN[36] 26_127
|
||||
DSP_R.DSP_0.PATTERN[37] 26_130
|
||||
DSP_R.DSP_0.PATTERN[38] 27_131
|
||||
DSP_R.DSP_0.PATTERN[39] 26_134
|
||||
DSP_R.DSP_0.PATTERN[40] 27_135
|
||||
DSP_R.DSP_0.PATTERN[41] 26_138
|
||||
DSP_R.DSP_0.PATTERN[42] 26_144
|
||||
DSP_R.DSP_0.PATTERN[43] 27_146
|
||||
DSP_R.DSP_0.PATTERN[44] 26_148
|
||||
DSP_R.DSP_0.PATTERN[45] 26_151
|
||||
DSP_R.DSP_0.PATTERN[46] 27_152
|
||||
DSP_R.DSP_0.PATTERN[47] 26_155
|
||||
DSP_R.DSP_1.MASK[0] 27_161
|
||||
DSP_R.DSP_1.MASK[1] 26_163
|
||||
DSP_R.DSP_1.MASK[2] 27_166
|
||||
DSP_R.DSP_1.MASK[3] 26_167
|
||||
DSP_R.DSP_1.MASK[4] 26_170
|
||||
DSP_R.DSP_1.MASK[5] 27_171
|
||||
DSP_R.DSP_1.MASK[6] 26_178
|
||||
DSP_R.DSP_1.MASK[7] 27_179
|
||||
DSP_R.DSP_1.MASK[8] 26_182
|
||||
DSP_R.DSP_1.MASK[9] 27_183
|
||||
DSP_R.DSP_1.MASK[10] 27_186
|
||||
DSP_R.DSP_1.MASK[11] 26_188
|
||||
DSP_R.DSP_1.MASK[12] 26_201
|
||||
DSP_R.DSP_1.MASK[13] 27_202
|
||||
DSP_R.DSP_1.MASK[14] 26_205
|
||||
DSP_R.DSP_1.MASK[15] 27_206
|
||||
DSP_R.DSP_1.MASK[16] 26_209
|
||||
DSP_R.DSP_1.MASK[17] 27_210
|
||||
DSP_R.DSP_1.MASK[18] 27_217
|
||||
DSP_R.DSP_1.MASK[19] 26_219
|
||||
DSP_R.DSP_1.MASK[20] 26_222
|
||||
DSP_R.DSP_1.MASK[21] 27_223
|
||||
DSP_R.DSP_1.MASK[22] 26_226
|
||||
DSP_R.DSP_1.MASK[23] 27_227
|
||||
DSP_R.DSP_1.MASK[24] 27_246
|
||||
DSP_R.DSP_1.MASK[25] 26_248
|
||||
DSP_R.DSP_1.MASK[26] 27_250
|
||||
DSP_R.DSP_1.MASK[27] 26_252
|
||||
DSP_R.DSP_1.MASK[28] 27_254
|
||||
DSP_R.DSP_1.MASK[29] 26_256
|
||||
DSP_R.DSP_1.MASK[30] 27_262
|
||||
DSP_R.DSP_1.MASK[31] 26_264
|
||||
DSP_R.DSP_1.MASK[32] 27_266
|
||||
DSP_R.DSP_1.MASK[33] 26_268
|
||||
DSP_R.DSP_1.MASK[34] 27_270
|
||||
DSP_R.DSP_1.MASK[35] 26_272
|
||||
DSP_R.DSP_1.MASK[36] 27_287
|
||||
DSP_R.DSP_1.MASK[37] 26_289
|
||||
DSP_R.DSP_1.MASK[38] 26_292
|
||||
DSP_R.DSP_1.MASK[39] 27_293
|
||||
DSP_R.DSP_1.MASK[40] 26_296
|
||||
DSP_R.DSP_1.MASK[41] 27_297
|
||||
DSP_R.DSP_1.MASK[42] 27_304
|
||||
DSP_R.DSP_1.MASK[43] 26_306
|
||||
DSP_R.DSP_1.MASK[44] 26_309
|
||||
DSP_R.DSP_1.MASK[45] 27_310
|
||||
DSP_R.DSP_1.MASK[46] 26_313
|
||||
DSP_R.DSP_1.MASK[47] 26_314
|
||||
DSP_R.DSP_1.PATTERN[0] 26_161
|
||||
DSP_R.DSP_1.PATTERN[1] 26_164
|
||||
DSP_R.DSP_1.PATTERN[2] 26_165
|
||||
DSP_R.DSP_1.PATTERN[3] 27_168
|
||||
DSP_R.DSP_1.PATTERN[4] 26_169
|
||||
DSP_R.DSP_1.PATTERN[5] 26_172
|
||||
DSP_R.DSP_1.PATTERN[6] 27_177
|
||||
DSP_R.DSP_1.PATTERN[7] 26_180
|
||||
DSP_R.DSP_1.PATTERN[8] 27_181
|
||||
DSP_R.DSP_1.PATTERN[9] 27_184
|
||||
DSP_R.DSP_1.PATTERN[10] 26_186
|
||||
DSP_R.DSP_1.PATTERN[11] 26_189
|
||||
DSP_R.DSP_1.PATTERN[12] 27_200
|
||||
DSP_R.DSP_1.PATTERN[13] 26_203
|
||||
DSP_R.DSP_1.PATTERN[14] 27_204
|
||||
DSP_R.DSP_1.PATTERN[15] 26_207
|
||||
DSP_R.DSP_1.PATTERN[16] 27_208
|
||||
DSP_R.DSP_1.PATTERN[17] 26_211
|
||||
DSP_R.DSP_1.PATTERN[18] 26_217
|
||||
DSP_R.DSP_1.PATTERN[19] 26_220
|
||||
DSP_R.DSP_1.PATTERN[20] 27_221
|
||||
DSP_R.DSP_1.PATTERN[21] 26_224
|
||||
DSP_R.DSP_1.PATTERN[22] 27_225
|
||||
DSP_R.DSP_1.PATTERN[23] 26_228
|
||||
DSP_R.DSP_1.PATTERN[24] 26_246
|
||||
DSP_R.DSP_1.PATTERN[25] 27_248
|
||||
DSP_R.DSP_1.PATTERN[26] 26_250
|
||||
DSP_R.DSP_1.PATTERN[27] 27_252
|
||||
DSP_R.DSP_1.PATTERN[28] 26_254
|
||||
DSP_R.DSP_1.PATTERN[29] 26_257
|
||||
DSP_R.DSP_1.PATTERN[30] 27_261
|
||||
DSP_R.DSP_1.PATTERN[31] 27_264
|
||||
DSP_R.DSP_1.PATTERN[32] 26_266
|
||||
DSP_R.DSP_1.PATTERN[33] 27_268
|
||||
DSP_R.DSP_1.PATTERN[34] 26_270
|
||||
DSP_R.DSP_1.PATTERN[35] 27_272
|
||||
DSP_R.DSP_1.PATTERN[36] 26_287
|
||||
DSP_R.DSP_1.PATTERN[37] 26_290
|
||||
DSP_R.DSP_1.PATTERN[38] 27_291
|
||||
DSP_R.DSP_1.PATTERN[39] 26_294
|
||||
DSP_R.DSP_1.PATTERN[40] 27_295
|
||||
DSP_R.DSP_1.PATTERN[41] 26_298
|
||||
DSP_R.DSP_1.PATTERN[42] 26_304
|
||||
DSP_R.DSP_1.PATTERN[43] 27_306
|
||||
DSP_R.DSP_1.PATTERN[44] 26_308
|
||||
DSP_R.DSP_1.PATTERN[45] 26_311
|
||||
DSP_R.DSP_1.PATTERN[46] 27_312
|
||||
DSP_R.DSP_1.PATTERN[47] 26_315
|
||||
|
|
@ -222,38 +222,6 @@ INT_L.CLK_L1.GCLK_L_B11_WEST 00_27 !00_29 01_25 01_26 01_29
|
|||
INT_L.CLK_L1.ER1END1 00_27 00_29 01_25 01_26 !01_29
|
||||
INT_L.CLK_L1.SR1END1 !00_27 !00_29 01_25 01_26 !01_29
|
||||
INT_L.CLK_L1.WR1END1 00_27 !00_29 01_25 !01_26 !01_29
|
||||
INT_L.CTRL_L0.BYP_BOUNCE4 !00_35 !00_39 01_37 01_38 !01_40
|
||||
INT_L.CTRL_L0.FAN_BOUNCE1 !00_35 00_39 01_37 !01_38 !01_40
|
||||
INT_L.CTRL_L0.EE4END2 !00_35 00_38 00_39 !01_38 !01_40
|
||||
INT_L.CTRL_L0.ER1END2 !00_35 !00_39 01_33 01_38 !01_40
|
||||
INT_L.CTRL_L0.GFAN0 00_35 00_39 01_37 01_38 !01_40
|
||||
INT_L.CTRL_L0.GFAN1 !00_35 00_39 01_37 01_38 01_40
|
||||
INT_L.CTRL_L0.NE6END2 !00_35 00_39 01_33 01_38 01_40
|
||||
INT_L.CTRL_L0.NN6END2 00_35 00_39 01_33 01_38 !01_40
|
||||
INT_L.CTRL_L0.NR1END2 00_34 !00_35 00_39 01_38 01_40
|
||||
INT_L.CTRL_L0.NW6END2 00_34 00_35 00_39 01_38 !01_40
|
||||
INT_L.CTRL_L0.SE6END2 !00_35 00_38 !00_39 01_38 !01_40
|
||||
INT_L.CTRL_L0.SR1END2 !00_35 00_38 00_39 01_38 01_40
|
||||
INT_L.CTRL_L0.SS6END2 00_35 00_38 00_39 01_38 !01_40
|
||||
INT_L.CTRL_L0.SW6END1 00_34 !00_35 !00_39 01_38 !01_40
|
||||
INT_L.CTRL_L0.WR1END2 00_34 !00_35 00_39 !01_38 !01_40
|
||||
INT_L.CTRL_L0.WW4END2 !00_35 00_39 01_33 !01_38 !01_40
|
||||
INT_L.CTRL_L1.BYP_BOUNCE4 !00_37 00_42 01_32 !01_36 !01_41
|
||||
INT_L.CTRL_L1.FAN_BOUNCE1 !00_37 !00_42 01_32 !01_36 01_41
|
||||
INT_L.CTRL_L1.EE4END2 !00_37 00_41 !00_42 !01_36 01_41
|
||||
INT_L.CTRL_L1.ER1END2 00_33 !00_37 00_42 !01_36 !01_41
|
||||
INT_L.CTRL_L1.GFAN0 !00_37 00_42 01_32 01_36 01_41
|
||||
INT_L.CTRL_L1.GFAN1 00_37 00_42 01_32 !01_36 01_41
|
||||
INT_L.CTRL_L1.NE6END2 00_33 00_37 00_42 !01_36 01_41
|
||||
INT_L.CTRL_L1.NN6END2 00_33 !00_37 00_42 01_36 01_41
|
||||
INT_L.CTRL_L1.NR1END2 00_37 00_42 01_34 !01_36 01_41
|
||||
INT_L.CTRL_L1.NW6END2 !00_37 00_42 01_34 01_36 01_41
|
||||
INT_L.CTRL_L1.SE6END2 !00_37 00_41 00_42 !01_36 !01_41
|
||||
INT_L.CTRL_L1.SR1END2 00_37 00_41 00_42 !01_36 01_41
|
||||
INT_L.CTRL_L1.SS6END2 !00_37 00_41 00_42 01_36 01_41
|
||||
INT_L.CTRL_L1.SW6END1 !00_37 00_42 01_34 !01_36 !01_41
|
||||
INT_L.CTRL_L1.WR1END2 !00_37 !00_42 01_34 !01_36 01_41
|
||||
INT_L.CTRL_L1.WW4END2 00_33 !00_37 !00_42 !01_36 01_41
|
||||
INT_L.EL1BEG_N3.LOGIC_OUTS_L0 11_05 14_05
|
||||
INT_L.EL1BEG_N3.LOGIC_OUTS_L4 07_04 14_05
|
||||
INT_L.EL1BEG_N3.LOGIC_OUTS_L8 10_05 14_05
|
||||
|
|
@ -309,7 +277,6 @@ INT_L.FAN_ALT0.WL1END_N1_3 16_00 !22_00 23_00 24_00 25_00
|
|||
INT_L.FAN_ALT0.WW2END_N0_3 16_00 !22_00 !23_00 !24_00 25_00
|
||||
INT_L.FAN_ALT0.EE2END0 19_01 !22_00 !23_00 !24_00 25_00
|
||||
INT_L.FAN_ALT0.EL1END0 17_00 !22_00 23_00 24_00 25_00
|
||||
INT_L.FAN_ALT0.GFAN0 21_00 !22_00 !23_00 !24_00 25_00
|
||||
INT_L.FAN_ALT0.NE2END0 18_01 !22_00 !23_00 24_00 !25_00
|
||||
INT_L.FAN_ALT0.NL1END0 19_01 !22_00 23_00 24_00 25_00
|
||||
INT_L.FAN_ALT0.NN2END0 18_01 !22_00 !23_00 !24_00 25_00
|
||||
|
|
@ -329,7 +296,6 @@ INT_L.FAN_ALT1.NL1BEG_N3 19_49 !22_48 23_48 24_48 25_48
|
|||
INT_L.FAN_ALT1.EE2END3 19_49 !22_48 !23_48 !24_48 25_48
|
||||
INT_L.FAN_ALT1.EL1END3 17_48 !22_48 23_48 24_48 25_48
|
||||
INT_L.FAN_ALT1.ER1END2 16_48 22_48 !23_48 24_48 25_48
|
||||
INT_L.FAN_ALT1.GFAN1 00_14 00_17 21_48 25_48
|
||||
INT_L.FAN_ALT1.NE2END3 18_49 !22_48 !23_48 24_48 !25_48
|
||||
INT_L.FAN_ALT1.NN2END3 18_49 !22_48 !23_48 !24_48 25_48
|
||||
INT_L.FAN_ALT1.NR1END3 18_49 22_48 !23_48 24_48 25_48
|
||||
|
|
@ -378,7 +344,6 @@ INT_L.FAN_ALT3.NW2END_S0_0 19_57 !22_56 !23_56 24_56 !25_56
|
|||
INT_L.FAN_ALT3.EE2END3 16_56 !22_56 !23_56 !24_56 25_56
|
||||
INT_L.FAN_ALT3.EL1END3 16_56 !22_56 23_56 24_56 25_56
|
||||
INT_L.FAN_ALT3.ER1END3 17_56 22_56 !23_56 24_56 25_56
|
||||
INT_L.FAN_ALT3.GFAN1 21_56 !22_56 !23_56 !24_56 25_56
|
||||
INT_L.FAN_ALT3.NE2END3 17_56 !22_56 !23_56 24_56 !25_56
|
||||
INT_L.FAN_ALT3.NN2END3 17_56 !22_56 !23_56 !24_56 25_56
|
||||
INT_L.FAN_ALT3.NR1END3 18_57 22_56 !23_56 24_56 25_56
|
||||
|
|
@ -390,8 +355,6 @@ INT_L.FAN_ALT3.SW2END3 18_57 !22_56 !23_56 24_56 !25_56
|
|||
INT_L.FAN_ALT3.WL1END3 17_56 !22_56 23_56 24_56 25_56
|
||||
INT_L.FAN_ALT3.WR1END3 16_56 22_56 !23_56 24_56 25_56
|
||||
INT_L.FAN_ALT3.WW2END3 19_57 !22_56 !23_56 !24_56 25_56
|
||||
INT_L.FAN_ALT4.BYP_BOUNCE_N3_3 20_08 25_08
|
||||
INT_L.FAN_ALT4.BYP_BOUNCE_N3_7 20_08 !22_08 !23_08 24_08 !25_08
|
||||
INT_L.FAN_ALT4.FAN_BOUNCE2 20_08 22_08 !23_08 24_08 25_08
|
||||
INT_L.FAN_ALT4.FAN_BOUNCE7 20_08 !22_08 23_08 24_08 25_08
|
||||
INT_L.FAN_ALT4.LOGIC_OUTS_L4 21_08 22_08 !23_08 24_08 25_08
|
||||
|
|
@ -401,7 +364,6 @@ INT_L.FAN_ALT4.SR1BEG_S0 19_09 22_08 !23_08 24_08 25_08
|
|||
INT_L.FAN_ALT4.EE2END0 16_08 !22_08 !23_08 !24_08 25_08
|
||||
INT_L.FAN_ALT4.EL1END0 16_08 !22_08 23_08 24_08 25_08
|
||||
INT_L.FAN_ALT4.ER1END0 17_08 22_08 !23_08 24_08 25_08
|
||||
INT_L.FAN_ALT4.GFAN0 21_08 !22_08 !23_08 !24_08 25_08
|
||||
INT_L.FAN_ALT4.NE2END0 17_08 !22_08 !23_08 24_08 !25_08
|
||||
INT_L.FAN_ALT4.NL1END1 19_09 !22_08 23_08 24_08 25_08
|
||||
INT_L.FAN_ALT4.NN2END0 17_08 !22_08 !23_08 !24_08 25_08
|
||||
|
|
@ -414,7 +376,6 @@ INT_L.FAN_ALT4.SW2END0 18_09 !22_08 !23_08 24_08 !25_08
|
|||
INT_L.FAN_ALT4.WL1END0 17_08 !22_08 23_08 24_08 25_08
|
||||
INT_L.FAN_ALT4.WR1END0 16_08 22_08 !23_08 24_08 25_08
|
||||
INT_L.FAN_ALT4.WW2END0 19_09 !22_08 !23_08 !24_08 25_08
|
||||
INT_L.FAN_ALT5.BYP_BOUNCE1 20_40 24_40
|
||||
INT_L.FAN_ALT5.BYP_BOUNCE5 20_40 !22_40 !23_40 !24_40 25_40
|
||||
INT_L.FAN_ALT5.FAN_BOUNCE_S3_0 20_40 22_40 !23_40 24_40 25_40
|
||||
INT_L.FAN_ALT5.FAN_BOUNCE1 20_40 !22_40 23_40 24_40 25_40
|
||||
|
|
@ -425,7 +386,6 @@ INT_L.FAN_ALT5.NL1BEG_N3 19_41 !22_40 23_40 24_40 25_40
|
|||
INT_L.FAN_ALT5.EE2END2 16_40 !22_40 !23_40 !24_40 25_40
|
||||
INT_L.FAN_ALT5.EL1END2 16_40 !22_40 23_40 24_40 25_40
|
||||
INT_L.FAN_ALT5.ER1END2 17_40 22_40 !23_40 24_40 25_40
|
||||
INT_L.FAN_ALT5.GFAN1 00_14 00_17 21_40 25_40
|
||||
INT_L.FAN_ALT5.NE2END2 17_40 !22_40 !23_40 24_40 !25_40
|
||||
INT_L.FAN_ALT5.NN2END2 17_40 !22_40 !23_40 !24_40 25_40
|
||||
INT_L.FAN_ALT5.NR1END2 18_41 22_40 !23_40 24_40 25_40
|
||||
|
|
@ -472,7 +432,7 @@ INT_L.FAN_ALT7.LOGIC_OUTS_L20 21_32 !22_32 !23_32 24_32 !25_32
|
|||
INT_L.FAN_ALT7.EE2END2 19_33 !22_32 !23_32 !24_32 25_32
|
||||
INT_L.FAN_ALT7.EL1END2 17_32 !22_32 23_32 24_32 25_32
|
||||
INT_L.FAN_ALT7.ER1END1 16_32 22_32 !23_32 24_32 25_32
|
||||
INT_L.FAN_ALT7.GFAN1 21_32 !22_32 !23_32 !24_32 25_32
|
||||
INT_L.FAN_ALT7.GFAN1 01_39 21_32 !22_32 !23_32 !24_32 25_32
|
||||
INT_L.FAN_ALT7.NE2END2 18_33 !22_32 !23_32 24_32 !25_32
|
||||
INT_L.FAN_ALT7.NL1END2 19_33 !22_32 23_32 24_32 25_32
|
||||
INT_L.FAN_ALT7.NN2END2 18_33 !22_32 !23_32 !24_32 25_32
|
||||
|
|
@ -1638,66 +1598,6 @@ INT_L.IMUX_L47.SS2END3 17_62 !22_62 !23_62 !24_62 25_62
|
|||
INT_L.IMUX_L47.SW2END3 17_62 !22_62 !23_62 24_62 !25_62
|
||||
INT_L.IMUX_L47.WL1END3 18_63 !22_62 23_62 24_62 25_62
|
||||
INT_L.IMUX_L47.WW2END3 16_62 !22_62 !23_62 !24_62 25_62
|
||||
INT_L.LV_L0.LV_L18 00_09 01_06
|
||||
INT_L.LV_L0.SR1BEG_S0 00_05 01_05
|
||||
INT_L.LV_L0.ER1END0 01_04 01_05
|
||||
INT_L.LV_L0.LH0 00_02 01_06
|
||||
INT_L.LV_L0.LH6 01_04 01_06
|
||||
INT_L.LV_L0.LH12 00_05 01_06
|
||||
INT_L.LV_L0.NN6END0 00_07 00_09
|
||||
INT_L.LV_L0.NR1END0 00_02 01_05
|
||||
INT_L.LV_L0.NW6END0 00_07 01_04
|
||||
INT_L.LV_L0.SW6END0 00_09 01_05
|
||||
INT_L.LV_L0.WR1END0 00_02 00_07
|
||||
INT_L.LV_L0.WW4END0 00_05 00_07
|
||||
INT_L.LV_L18.LV_L0 01_00 01_01
|
||||
INT_L.LV_L18.SR1BEG_S0 00_03 01_08
|
||||
INT_L.LV_L18.ER1END0 00_03 00_06
|
||||
INT_L.LV_L18.LH0 00_01 01_02
|
||||
INT_L.LV_L18.LH6 00_06 01_02
|
||||
INT_L.LV_L18.LH12 01_08
|
||||
INT_L.LV_L18.NN6END0 00_03 01_00
|
||||
INT_L.LV_L18.NR1END0 00_01 00_03
|
||||
INT_L.LV_L18.NW6END0 00_06 01_01
|
||||
INT_L.LV_L18.SW6END0 01_00 01_02
|
||||
INT_L.LV_L18.WR1END0 00_01 01_01
|
||||
INT_L.LV_L18.WW4END0 01_01 01_08
|
||||
INT_L.LVB_L0.LV_L0 00_47 01_52
|
||||
INT_L.LVB_L0.LV_L18 01_42 01_52
|
||||
INT_L.LVB_L0.LVB_L12 00_51 00_54
|
||||
INT_L.LVB_L0.LH0 00_43 00_51
|
||||
INT_L.LVB_L0.LH6 00_51 00_53
|
||||
INT_L.LVB_L0.LH12 00_50 00_51
|
||||
INT_L.LVB_L0.NE2END2 00_53 01_52
|
||||
INT_L.LVB_L0.NN6END3 00_50 01_50
|
||||
INT_L.LVB_L0.NR1END3 00_47 01_50
|
||||
INT_L.LVB_L0.NW2END2 00_43 01_52
|
||||
INT_L.LVB_L0.NW6END3 00_43 01_50
|
||||
INT_L.LVB_L0.SE2END3 00_51 01_42
|
||||
INT_L.LVB_L0.SE6END3 00_54 01_50
|
||||
INT_L.LVB_L0.SW2END2 00_50 01_52
|
||||
INT_L.LVB_L0.SW2END3 00_47 00_51
|
||||
INT_L.LVB_L0.SW6END2 00_54 01_52
|
||||
INT_L.LVB_L0.WR1END3 01_42 01_50
|
||||
INT_L.LVB_L0.WW4END3 00_53 01_50
|
||||
INT_L.LVB_L12.LV_L0 00_45 01_44
|
||||
INT_L.LVB_L12.LV_L18 00_45 01_48
|
||||
INT_L.LVB_L12.LVB_L0 00_45 01_45
|
||||
INT_L.LVB_L12.LH0 00_46 00_49
|
||||
INT_L.LVB_L12.LH6 00_46 01_49
|
||||
INT_L.LVB_L12.LH12 00_46 01_53
|
||||
INT_L.LVB_L12.NE2END2 00_45 01_49
|
||||
INT_L.LVB_L12.NN6END3 01_46 01_53
|
||||
INT_L.LVB_L12.NR1END3 01_44 01_46
|
||||
INT_L.LVB_L12.NW2END2 00_45 00_49
|
||||
INT_L.LVB_L12.NW6END3 00_49 01_46
|
||||
INT_L.LVB_L12.SE2END3 00_46 01_48
|
||||
INT_L.LVB_L12.SE6END3 00_46 01_45
|
||||
INT_L.LVB_L12.SW2END2 00_45 01_53
|
||||
INT_L.LVB_L12.SW2END3 00_46 01_44
|
||||
INT_L.LVB_L12.SW6END2 01_45 01_46
|
||||
INT_L.LVB_L12.WR1END3 01_46 01_48
|
||||
INT_L.LVB_L12.WW4END3 01_46 01_49
|
||||
INT_L.NL1BEG_N3.LOGIC_OUTS_L0 11_01 14_01
|
||||
INT_L.NL1BEG_N3.LOGIC_OUTS_L4 07_00 14_01
|
||||
INT_L.NL1BEG_N3.LOGIC_OUTS_L8 10_01 14_01
|
||||
|
|
@ -1864,10 +1764,8 @@ INT_L.EE4BEG0.LOGIC_OUTS_L8 03_08 07_09
|
|||
INT_L.EE4BEG0.LOGIC_OUTS_L12 03_08 04_10
|
||||
INT_L.EE4BEG0.LOGIC_OUTS_L18 06_08 07_09
|
||||
INT_L.EE4BEG0.LOGIC_OUTS_L22 04_10 06_08
|
||||
INT_L.EE4BEG0.LV_L0 04_10 05_08
|
||||
INT_L.EE4BEG0.EE2END0 03_08 03_09
|
||||
INT_L.EE4BEG0.EE4END0 03_09 05_08
|
||||
INT_L.EE4BEG0.LH12 05_08 07_09
|
||||
INT_L.EE4BEG0.NE2END0 02_09 04_09
|
||||
INT_L.EE4BEG0.NE6END0 04_09 05_08
|
||||
INT_L.EE4BEG0.NN2END0 03_08 04_09
|
||||
|
|
@ -1884,10 +1782,8 @@ INT_L.EE4BEG1.LOGIC_OUTS_L9 03_24 04_26
|
|||
INT_L.EE4BEG1.LOGIC_OUTS_L13 03_24 07_25
|
||||
INT_L.EE4BEG1.LOGIC_OUTS_L19 04_26 06_24
|
||||
INT_L.EE4BEG1.LOGIC_OUTS_L23 06_24 07_25
|
||||
INT_L.EE4BEG1.LV_L9 04_26 05_24
|
||||
INT_L.EE4BEG1.EE2END1 03_24 03_25
|
||||
INT_L.EE4BEG1.EE4END1 03_25 05_24
|
||||
INT_L.EE4BEG1.LH6 05_24 07_25
|
||||
INT_L.EE4BEG1.NE2END1 02_25 04_25
|
||||
INT_L.EE4BEG1.NE6END1 04_25 05_24
|
||||
INT_L.EE4BEG1.NN2END1 03_24 04_25
|
||||
|
|
@ -1897,15 +1793,12 @@ INT_L.EE4BEG1.SE6END1 03_25 06_24
|
|||
INT_L.EE4BEG1.SS2END1 03_24 05_27
|
||||
INT_L.EE4BEG1.SS6END1 05_27 06_24
|
||||
INT_L.EE4BEG1.SW2END1 02_25 05_27
|
||||
INT_L.EE4BEG1.SW6END1 05_24 05_27
|
||||
INT_L.EE4BEG2.LOGIC_OUTS_L2 02_41 04_42
|
||||
INT_L.EE4BEG2.LOGIC_OUTS_L6 02_41 07_41
|
||||
INT_L.EE4BEG2.LOGIC_OUTS_L10 03_40 07_41
|
||||
INT_L.EE4BEG2.LOGIC_OUTS_L14 03_40 04_42
|
||||
INT_L.EE4BEG2.LOGIC_OUTS_L16 06_40 07_41
|
||||
INT_L.EE4BEG2.LOGIC_OUTS_L20 04_42 06_40
|
||||
INT_L.EE4BEG2.LVB_L0 04_42 05_40
|
||||
INT_L.EE4BEG2.LVB_L12 05_40 07_41
|
||||
INT_L.EE4BEG2.EE2END2 03_40 03_41
|
||||
INT_L.EE4BEG2.EE4END2 03_41 05_40
|
||||
INT_L.EE4BEG2.NE2END2 02_41 04_41
|
||||
|
|
@ -1917,17 +1810,14 @@ INT_L.EE4BEG2.SE6END2 03_41 06_40
|
|||
INT_L.EE4BEG2.SS2END2 03_40 05_43
|
||||
INT_L.EE4BEG2.SS6END2 05_43 06_40
|
||||
INT_L.EE4BEG2.SW2END2 02_41 05_43
|
||||
INT_L.EE4BEG2.SW6END2 05_40 05_43
|
||||
INT_L.EE4BEG3.LOGIC_OUTS_L3 02_57 07_57
|
||||
INT_L.EE4BEG3.LOGIC_OUTS_L7 02_57 04_58
|
||||
INT_L.EE4BEG3.LOGIC_OUTS_L11 03_56 04_58
|
||||
INT_L.EE4BEG3.LOGIC_OUTS_L15 03_56 07_57
|
||||
INT_L.EE4BEG3.LOGIC_OUTS_L17 04_58 06_56
|
||||
INT_L.EE4BEG3.LOGIC_OUTS_L21 06_56 07_57
|
||||
INT_L.EE4BEG3.LV_L18 05_56 07_57
|
||||
INT_L.EE4BEG3.EE2END3 03_56 03_57
|
||||
INT_L.EE4BEG3.EE4END3 03_57 05_56
|
||||
INT_L.EE4BEG3.LH0 04_58 05_56
|
||||
INT_L.EE4BEG3.NE2END3 02_57 04_57
|
||||
INT_L.EE4BEG3.NE6END3 04_57 05_56
|
||||
INT_L.EE4BEG3.NN2END3 03_56 04_57
|
||||
|
|
@ -1937,7 +1827,6 @@ INT_L.EE4BEG3.SE6END3 03_57 06_56
|
|||
INT_L.EE4BEG3.SS2END3 03_56 05_59
|
||||
INT_L.EE4BEG3.SS6END3 05_59 06_56
|
||||
INT_L.EE4BEG3.SW2END3 02_57 05_59
|
||||
INT_L.EE4BEG3.SW6END3 05_56 05_59
|
||||
INT_L.EL1BEG0.LOGIC_OUTS_L1 07_20 14_21
|
||||
INT_L.EL1BEG0.LOGIC_OUTS_L5 11_21 14_21
|
||||
INT_L.EL1BEG0.LOGIC_OUTS_L9 10_21 13_21
|
||||
|
|
@ -2058,62 +1947,8 @@ INT_L.ER1BEG3.SW2END2 07_42 15_43
|
|||
INT_L.ER1BEG3.SW6END2 07_42 12_43
|
||||
INT_L.ER1BEG3.WW2END2 11_43 15_43
|
||||
INT_L.ER1BEG3.WW4END3 11_43 12_43
|
||||
INT_L.GFAN0.BYP_BOUNCE1 00_10 00_11 !01_09 01_10 01_14
|
||||
INT_L.GFAN0.GCLK_L_B0 00_10 00_11 !01_09 01_10 01_12
|
||||
INT_L.GFAN0.GCLK_L_B1 !00_10 00_11 01_09 01_10 01_12
|
||||
INT_L.GFAN0.GCLK_L_B2 !00_10 !00_11 !01_09 01_10 01_12
|
||||
INT_L.GFAN0.GCLK_L_B3 !00_10 00_11 !01_09 !01_10 01_12
|
||||
INT_L.GFAN0.GCLK_L_B4 00_10 00_11 !01_09 01_10 01_18
|
||||
INT_L.GFAN0.GCLK_L_B5 !00_10 00_11 01_09 01_10 01_18
|
||||
INT_L.GFAN0.GCLK_L_B6_WEST !00_10 !00_11 !01_09 01_10 01_18
|
||||
INT_L.GFAN0.GCLK_L_B7_WEST !00_10 00_11 !01_09 !01_10 01_18
|
||||
INT_L.GFAN0.GCLK_L_B8_WEST 00_10 00_11 !01_09 01_10 01_16
|
||||
INT_L.GFAN0.GCLK_L_B9_WEST !00_10 00_11 01_09 01_10 01_16
|
||||
INT_L.GFAN0.GCLK_L_B10_WEST !00_10 !00_11 !01_09 01_10 01_16
|
||||
INT_L.GFAN0.GCLK_L_B11_WEST !00_10 00_11 !01_09 !01_10 01_16
|
||||
INT_L.GFAN0.GND_WIRE !00_10 00_11 !01_09 !01_10 01_14
|
||||
INT_L.GFAN0.NR1END1 !00_10 00_11 01_09 01_10 01_14
|
||||
INT_L.GFAN0.WW4END1 !00_10 !00_11 !01_09 01_10 01_14
|
||||
INT_L.GFAN1.BYP_BOUNCE1 00_14 00_17 00_18 !00_19 01_13
|
||||
INT_L.GFAN1.GCLK_L_B0 00_13 00_14 00_18 !00_19 01_13
|
||||
INT_L.GFAN1.GCLK_L_B1 00_13 00_14 !00_18 00_19 01_13
|
||||
INT_L.GFAN1.GCLK_L_B2 00_13 00_14 !00_18 !00_19 !01_13
|
||||
INT_L.GFAN1.GCLK_L_B3 00_13 !00_14 !00_18 !00_19 01_13
|
||||
INT_L.GFAN1.GCLK_L_B4 00_14 00_15 00_18 !00_19 01_13
|
||||
INT_L.GFAN1.GCLK_L_B5 00_14 00_15 !00_18 00_19 01_13
|
||||
INT_L.GFAN1.GCLK_L_B6_WEST 00_14 00_15 !00_18 !00_19 !01_13
|
||||
INT_L.GFAN1.GCLK_L_B7_WEST !00_14 00_15 !00_18 !00_19 01_13
|
||||
INT_L.GFAN1.GCLK_L_B8_WEST 00_14 00_18 !00_19 01_13 01_17
|
||||
INT_L.GFAN1.GCLK_L_B9_WEST 00_14 !00_18 00_19 01_13 01_17
|
||||
INT_L.GFAN1.GCLK_L_B10_WEST 00_14 !00_18 !00_19 !01_13 01_17
|
||||
INT_L.GFAN1.GCLK_L_B11_WEST !00_14 !00_18 !00_19 01_13 01_17
|
||||
INT_L.GFAN1.GND_WIRE !00_14 00_17 !00_18 !00_19 01_13
|
||||
INT_L.GFAN1.NR1END1 00_14 00_17 !00_18 00_19 01_13
|
||||
INT_L.GFAN1.WW4END1 00_14 00_17 !00_18 !00_19 !01_13
|
||||
INT_L.LH0.LV_L0 01_56 01_58
|
||||
INT_L.LH0.LV_L9 00_59 01_56
|
||||
INT_L.LH0.LV_L18 01_56 01_61
|
||||
INT_L.LH0.EE4END3 00_58 01_61
|
||||
INT_L.LH0.ER1END3 00_57 01_54
|
||||
INT_L.LH0.LH12 01_54 01_56
|
||||
INT_L.LH0.NE2END3 00_58 00_59
|
||||
INT_L.LH0.NE6END3 00_58 01_58
|
||||
INT_L.LH0.NW2END3 00_58 01_54
|
||||
INT_L.LH0.SR1END3 00_57 00_59
|
||||
INT_L.LH0.SS6END3 00_57 01_58
|
||||
INT_L.LH0.SW6END3 00_57 01_61
|
||||
INT_L.LH12.LV_L0 00_55 00_62
|
||||
INT_L.LH12.LV_L9 00_62 01_57
|
||||
INT_L.LH12.LV_L18 00_62 01_62
|
||||
INT_L.LH12.EE4END3 01_60 01_62
|
||||
INT_L.LH12.ER1END3 00_63 01_60
|
||||
INT_L.LH12.LH0 00_61 00_63
|
||||
INT_L.LH12.NE2END3 01_57 01_60
|
||||
INT_L.LH12.NE6END3 00_55 01_60
|
||||
INT_L.LH12.NW2END3 00_62 00_63
|
||||
INT_L.LH12.SR1END3 00_61 01_57
|
||||
INT_L.LH12.SS6END3 00_55 00_61
|
||||
INT_L.LH12.SW6END3 00_61 01_62
|
||||
INT_L.NE2BEG0.LOGIC_OUTS_L0 09_05 15_04
|
||||
INT_L.NE2BEG0.LOGIC_OUTS_L4 09_04 15_04
|
||||
INT_L.NE2BEG0.LOGIC_OUTS_L8 11_04 15_04
|
||||
|
|
@ -2200,11 +2035,9 @@ INT_L.NE6BEG0.LOGIC_OUTS_L8 03_04 04_06
|
|||
INT_L.NE6BEG0.LOGIC_OUTS_L12 03_04 07_05
|
||||
INT_L.NE6BEG0.LOGIC_OUTS_L18 04_06 06_04
|
||||
INT_L.NE6BEG0.LOGIC_OUTS_L22 06_04 07_05
|
||||
INT_L.NE6BEG0.LV_L0 04_06 05_04
|
||||
INT_L.NE6BEG0.WW2END_N0_3 03_04 04_05
|
||||
INT_L.NE6BEG0.EE2END0 03_04 05_07
|
||||
INT_L.NE6BEG0.EE4END0 05_04 05_07
|
||||
INT_L.NE6BEG0.LH12 05_04 07_05
|
||||
INT_L.NE6BEG0.NE2END0 02_05 03_05
|
||||
INT_L.NE6BEG0.NE6END0 03_05 05_04
|
||||
INT_L.NE6BEG0.NN2END0 03_04 03_05
|
||||
|
|
@ -2220,10 +2053,8 @@ INT_L.NE6BEG1.LOGIC_OUTS_L9 03_20 07_21
|
|||
INT_L.NE6BEG1.LOGIC_OUTS_L13 03_20 04_22
|
||||
INT_L.NE6BEG1.LOGIC_OUTS_L19 06_20 07_21
|
||||
INT_L.NE6BEG1.LOGIC_OUTS_L23 04_22 06_20
|
||||
INT_L.NE6BEG1.LV_L9 04_22 05_20
|
||||
INT_L.NE6BEG1.EE2END1 03_20 05_23
|
||||
INT_L.NE6BEG1.EE4END1 05_20 05_23
|
||||
INT_L.NE6BEG1.LH6 05_20 07_21
|
||||
INT_L.NE6BEG1.NE2END1 02_21 03_21
|
||||
INT_L.NE6BEG1.NE6END1 03_21 05_20
|
||||
INT_L.NE6BEG1.NN2END1 03_20 03_21
|
||||
|
|
@ -2240,8 +2071,6 @@ INT_L.NE6BEG2.LOGIC_OUTS_L10 03_36 04_38
|
|||
INT_L.NE6BEG2.LOGIC_OUTS_L14 03_36 07_37
|
||||
INT_L.NE6BEG2.LOGIC_OUTS_L16 04_38 06_36
|
||||
INT_L.NE6BEG2.LOGIC_OUTS_L20 06_36 07_37
|
||||
INT_L.NE6BEG2.LVB_L0 04_38 05_36
|
||||
INT_L.NE6BEG2.LVB_L12 05_36 07_37
|
||||
INT_L.NE6BEG2.EE2END2 03_36 05_39
|
||||
INT_L.NE6BEG2.EE4END2 05_36 05_39
|
||||
INT_L.NE6BEG2.NE2END2 02_37 03_37
|
||||
|
|
@ -2253,17 +2082,14 @@ INT_L.NE6BEG2.NW6END2 04_37 06_36
|
|||
INT_L.NE6BEG2.SE2END2 02_37 05_39
|
||||
INT_L.NE6BEG2.SE6END2 05_39 06_36
|
||||
INT_L.NE6BEG2.WW2END1 03_36 04_37
|
||||
INT_L.NE6BEG2.WW4END2 04_37 05_36
|
||||
INT_L.NE6BEG3.LOGIC_OUTS_L3 02_53 04_54
|
||||
INT_L.NE6BEG3.LOGIC_OUTS_L7 02_53 07_53
|
||||
INT_L.NE6BEG3.LOGIC_OUTS_L11 03_52 07_53
|
||||
INT_L.NE6BEG3.LOGIC_OUTS_L15 03_52 04_54
|
||||
INT_L.NE6BEG3.LOGIC_OUTS_L17 06_52 07_53
|
||||
INT_L.NE6BEG3.LOGIC_OUTS_L21 04_54 06_52
|
||||
INT_L.NE6BEG3.LV_L18 05_52 07_53
|
||||
INT_L.NE6BEG3.EE2END3 03_52 05_55
|
||||
INT_L.NE6BEG3.EE4END3 05_52 05_55
|
||||
INT_L.NE6BEG3.LH0 04_54 05_52
|
||||
INT_L.NE6BEG3.NE2END3 02_53 03_53
|
||||
INT_L.NE6BEG3.NE6END3 03_53 05_52
|
||||
INT_L.NE6BEG3.NN2END3 03_52 03_53
|
||||
|
|
@ -2273,7 +2099,6 @@ INT_L.NE6BEG3.NW6END3 04_53 06_52
|
|||
INT_L.NE6BEG3.SE2END3 02_53 05_55
|
||||
INT_L.NE6BEG3.SE6END3 05_55 06_52
|
||||
INT_L.NE6BEG3.WW2END2 03_52 04_53
|
||||
INT_L.NE6BEG3.WW4END3 04_53 05_52
|
||||
INT_L.NL1BEG0.LOGIC_OUTS_L1 07_16 14_17
|
||||
INT_L.NL1BEG0.LOGIC_OUTS_L5 11_17 14_17
|
||||
INT_L.NL1BEG0.LOGIC_OUTS_L9 10_17 13_17
|
||||
|
|
@ -2420,11 +2245,9 @@ INT_L.NN6BEG0.LOGIC_OUTS_L8 02_07 06_06
|
|||
INT_L.NN6BEG0.LOGIC_OUTS_L12 02_07 05_05
|
||||
INT_L.NN6BEG0.LOGIC_OUTS_L18 06_06 07_07
|
||||
INT_L.NN6BEG0.LOGIC_OUTS_L22 05_05 07_07
|
||||
INT_L.NN6BEG0.LV_L0 04_07 06_06
|
||||
INT_L.NN6BEG0.WW2END_N0_3 02_07 04_04
|
||||
INT_L.NN6BEG0.EE2END0 02_07 05_06
|
||||
INT_L.NN6BEG0.EE4END0 04_07 05_06
|
||||
INT_L.NN6BEG0.LH12 04_07 05_05
|
||||
INT_L.NN6BEG0.NE2END0 02_06 03_06
|
||||
INT_L.NN6BEG0.NE6END0 02_06 04_07
|
||||
INT_L.NN6BEG0.NN2END0 02_06 02_07
|
||||
|
|
@ -2440,10 +2263,8 @@ INT_L.NN6BEG1.LOGIC_OUTS_L9 02_23 05_21
|
|||
INT_L.NN6BEG1.LOGIC_OUTS_L13 02_23 06_22
|
||||
INT_L.NN6BEG1.LOGIC_OUTS_L19 05_21 07_23
|
||||
INT_L.NN6BEG1.LOGIC_OUTS_L23 06_22 07_23
|
||||
INT_L.NN6BEG1.LV_L9 04_23 06_22
|
||||
INT_L.NN6BEG1.EE2END1 02_23 05_22
|
||||
INT_L.NN6BEG1.EE4END1 04_23 05_22
|
||||
INT_L.NN6BEG1.LH6 04_23 05_21
|
||||
INT_L.NN6BEG1.NE2END1 02_22 03_22
|
||||
INT_L.NN6BEG1.NE6END1 02_22 04_23
|
||||
INT_L.NN6BEG1.NN2END1 02_22 02_23
|
||||
|
|
@ -2460,8 +2281,6 @@ INT_L.NN6BEG2.LOGIC_OUTS_L10 02_39 06_38
|
|||
INT_L.NN6BEG2.LOGIC_OUTS_L14 02_39 05_37
|
||||
INT_L.NN6BEG2.LOGIC_OUTS_L16 06_38 07_39
|
||||
INT_L.NN6BEG2.LOGIC_OUTS_L20 05_37 07_39
|
||||
INT_L.NN6BEG2.LVB_L0 04_39 06_38
|
||||
INT_L.NN6BEG2.LVB_L12 04_39 05_37
|
||||
INT_L.NN6BEG2.EE2END2 02_39 05_38
|
||||
INT_L.NN6BEG2.EE4END2 04_39 05_38
|
||||
INT_L.NN6BEG2.NE2END2 02_38 03_38
|
||||
|
|
@ -2480,10 +2299,8 @@ INT_L.NN6BEG3.LOGIC_OUTS_L11 02_55 05_53
|
|||
INT_L.NN6BEG3.LOGIC_OUTS_L15 02_55 06_54
|
||||
INT_L.NN6BEG3.LOGIC_OUTS_L17 05_53 07_55
|
||||
INT_L.NN6BEG3.LOGIC_OUTS_L21 06_54 07_55
|
||||
INT_L.NN6BEG3.LV_L18 04_55 05_53
|
||||
INT_L.NN6BEG3.EE2END3 02_55 05_54
|
||||
INT_L.NN6BEG3.EE4END3 04_55 05_54
|
||||
INT_L.NN6BEG3.LH0 04_55 06_54
|
||||
INT_L.NN6BEG3.NE2END3 02_54 03_54
|
||||
INT_L.NN6BEG3.NE6END3 02_54 04_55
|
||||
INT_L.NN6BEG3.NN2END3 02_54 02_55
|
||||
|
|
@ -2491,7 +2308,6 @@ INT_L.NN6BEG3.NN6END3 02_54 07_55
|
|||
INT_L.NN6BEG3.NW2END3 03_54 04_52
|
||||
INT_L.NN6BEG3.NW6END3 04_52 07_55
|
||||
INT_L.NN6BEG3.SE2END3 03_54 05_54
|
||||
INT_L.NN6BEG3.SE6END3 05_54 07_55
|
||||
INT_L.NN6BEG3.WW2END2 02_55 04_52
|
||||
INT_L.NN6BEG3.WW4END3 04_52 04_55
|
||||
INT_L.NR1BEG0.LOGIC_OUTS_L0 11_07 14_07
|
||||
|
|
@ -2660,13 +2476,11 @@ INT_L.NW6BEG0.LOGIC_OUTS_L8 02_03 05_01
|
|||
INT_L.NW6BEG0.LOGIC_OUTS_L12 02_03 06_02
|
||||
INT_L.NW6BEG0.LOGIC_OUTS_L18 05_01 07_03
|
||||
INT_L.NW6BEG0.LOGIC_OUTS_L22 06_02 07_03
|
||||
INT_L.NW6BEG0.LV_L0 04_03 06_02
|
||||
INT_L.NW6BEG0.SS2END_N0_3 02_03 04_00
|
||||
INT_L.NW6BEG0.SS6END_N0_3 04_00 07_03
|
||||
INT_L.NW6BEG0.SW2END_N0_3 03_02 04_00
|
||||
INT_L.NW6BEG0.SW6END_N0_3 04_00 04_03
|
||||
INT_L.NW6BEG0.WW2END_N0_3 02_02 02_03
|
||||
INT_L.NW6BEG0.LH12 04_03 05_01
|
||||
INT_L.NW6BEG0.NE2END0 03_02 05_02
|
||||
INT_L.NW6BEG0.NE6END0 04_03 05_02
|
||||
INT_L.NW6BEG0.NN2END0 02_03 05_02
|
||||
|
|
@ -2680,8 +2494,6 @@ INT_L.NW6BEG1.LOGIC_OUTS_L9 02_19 06_18
|
|||
INT_L.NW6BEG1.LOGIC_OUTS_L13 02_19 05_17
|
||||
INT_L.NW6BEG1.LOGIC_OUTS_L19 06_18 07_19
|
||||
INT_L.NW6BEG1.LOGIC_OUTS_L23 05_17 07_19
|
||||
INT_L.NW6BEG1.LV_L9 04_19 06_18
|
||||
INT_L.NW6BEG1.LH6 04_19 05_17
|
||||
INT_L.NW6BEG1.NE2END1 03_18 05_18
|
||||
INT_L.NW6BEG1.NE6END1 04_19 05_18
|
||||
INT_L.NW6BEG1.NN2END1 02_19 05_18
|
||||
|
|
@ -2700,8 +2512,6 @@ INT_L.NW6BEG2.LOGIC_OUTS_L10 02_35 05_33
|
|||
INT_L.NW6BEG2.LOGIC_OUTS_L14 02_35 06_34
|
||||
INT_L.NW6BEG2.LOGIC_OUTS_L16 05_33 07_35
|
||||
INT_L.NW6BEG2.LOGIC_OUTS_L20 06_34 07_35
|
||||
INT_L.NW6BEG2.LVB_L0 04_35 06_34
|
||||
INT_L.NW6BEG2.LVB_L12 04_35 05_33
|
||||
INT_L.NW6BEG2.NE2END2 03_34 05_34
|
||||
INT_L.NW6BEG2.NE6END2 04_35 05_34
|
||||
INT_L.NW6BEG2.NN2END2 02_35 05_34
|
||||
|
|
@ -2720,8 +2530,6 @@ INT_L.NW6BEG3.LOGIC_OUTS_L11 02_51 06_50
|
|||
INT_L.NW6BEG3.LOGIC_OUTS_L15 02_51 05_49
|
||||
INT_L.NW6BEG3.LOGIC_OUTS_L17 06_50 07_51
|
||||
INT_L.NW6BEG3.LOGIC_OUTS_L21 05_49 07_51
|
||||
INT_L.NW6BEG3.LV_L18 04_51 05_49
|
||||
INT_L.NW6BEG3.LH0 04_51 06_50
|
||||
INT_L.NW6BEG3.NE2END3 03_50 05_50
|
||||
INT_L.NW6BEG3.NE6END3 04_51 05_50
|
||||
INT_L.NW6BEG3.NN2END3 02_51 05_50
|
||||
|
|
@ -2820,10 +2628,8 @@ INT_L.SE6BEG0.LOGIC_OUTS_L8 02_11 05_09
|
|||
INT_L.SE6BEG0.LOGIC_OUTS_L12 02_11 06_10
|
||||
INT_L.SE6BEG0.LOGIC_OUTS_L18 05_09 07_11
|
||||
INT_L.SE6BEG0.LOGIC_OUTS_L22 06_10 07_11
|
||||
INT_L.SE6BEG0.LV_L0 04_11 06_10
|
||||
INT_L.SE6BEG0.EE2END0 02_10 02_11
|
||||
INT_L.SE6BEG0.EE4END0 02_10 04_11
|
||||
INT_L.SE6BEG0.LH12 04_11 05_09
|
||||
INT_L.SE6BEG0.NE2END0 03_10 04_08
|
||||
INT_L.SE6BEG0.NE6END0 04_08 04_11
|
||||
INT_L.SE6BEG0.NN2END0 02_11 04_08
|
||||
|
|
@ -2840,10 +2646,8 @@ INT_L.SE6BEG1.LOGIC_OUTS_L9 02_27 06_26
|
|||
INT_L.SE6BEG1.LOGIC_OUTS_L13 02_27 05_25
|
||||
INT_L.SE6BEG1.LOGIC_OUTS_L19 06_26 07_27
|
||||
INT_L.SE6BEG1.LOGIC_OUTS_L23 05_25 07_27
|
||||
INT_L.SE6BEG1.LV_L9 04_27 06_26
|
||||
INT_L.SE6BEG1.EE2END1 02_26 02_27
|
||||
INT_L.SE6BEG1.EE4END1 02_26 04_27
|
||||
INT_L.SE6BEG1.LH6 04_27 05_25
|
||||
INT_L.SE6BEG1.NE2END1 03_26 04_24
|
||||
INT_L.SE6BEG1.NE6END1 04_24 04_27
|
||||
INT_L.SE6BEG1.NN2END1 02_27 04_24
|
||||
|
|
@ -2860,8 +2664,6 @@ INT_L.SE6BEG2.LOGIC_OUTS_L10 02_43 05_41
|
|||
INT_L.SE6BEG2.LOGIC_OUTS_L14 02_43 06_42
|
||||
INT_L.SE6BEG2.LOGIC_OUTS_L16 05_41 07_43
|
||||
INT_L.SE6BEG2.LOGIC_OUTS_L20 06_42 07_43
|
||||
INT_L.SE6BEG2.LVB_L0 04_43 06_42
|
||||
INT_L.SE6BEG2.LVB_L12 04_43 05_41
|
||||
INT_L.SE6BEG2.EE2END2 02_42 02_43
|
||||
INT_L.SE6BEG2.EE4END2 02_42 04_43
|
||||
INT_L.SE6BEG2.NE2END2 03_42 04_40
|
||||
|
|
@ -2880,10 +2682,8 @@ INT_L.SE6BEG3.LOGIC_OUTS_L11 02_59 06_58
|
|||
INT_L.SE6BEG3.LOGIC_OUTS_L15 02_59 05_57
|
||||
INT_L.SE6BEG3.LOGIC_OUTS_L17 06_58 07_59
|
||||
INT_L.SE6BEG3.LOGIC_OUTS_L21 05_57 07_59
|
||||
INT_L.SE6BEG3.LV_L18 04_59 05_57
|
||||
INT_L.SE6BEG3.EE2END3 02_58 02_59
|
||||
INT_L.SE6BEG3.EE4END3 02_58 04_59
|
||||
INT_L.SE6BEG3.LH0 04_59 06_58
|
||||
INT_L.SE6BEG3.NE2END3 03_58 04_56
|
||||
INT_L.SE6BEG3.NE6END3 04_56 04_59
|
||||
INT_L.SE6BEG3.NN2END3 02_59 04_56
|
||||
|
|
@ -3120,10 +2920,8 @@ INT_L.SS6BEG0.LOGIC_OUTS_L8 02_15 06_14
|
|||
INT_L.SS6BEG0.LOGIC_OUTS_L12 02_15 05_13
|
||||
INT_L.SS6BEG0.LOGIC_OUTS_L18 06_14 07_15
|
||||
INT_L.SS6BEG0.LOGIC_OUTS_L22 05_13 07_15
|
||||
INT_L.SS6BEG0.LV_L0 04_15 06_14
|
||||
INT_L.SS6BEG0.EE2END0 02_15 04_12
|
||||
INT_L.SS6BEG0.EE4END0 04_12 04_15
|
||||
INT_L.SS6BEG0.LH12 04_15 05_13
|
||||
INT_L.SS6BEG0.NW2END1 03_14 05_14
|
||||
INT_L.SS6BEG0.NW6END1 05_14 07_15
|
||||
INT_L.SS6BEG0.SE2END0 03_14 04_12
|
||||
|
|
@ -3140,10 +2938,8 @@ INT_L.SS6BEG1.LOGIC_OUTS_L9 02_31 05_29
|
|||
INT_L.SS6BEG1.LOGIC_OUTS_L13 02_31 06_30
|
||||
INT_L.SS6BEG1.LOGIC_OUTS_L19 05_29 07_31
|
||||
INT_L.SS6BEG1.LOGIC_OUTS_L23 06_30 07_31
|
||||
INT_L.SS6BEG1.LV_L9 04_31 06_30
|
||||
INT_L.SS6BEG1.EE2END1 02_31 04_28
|
||||
INT_L.SS6BEG1.EE4END1 04_28 04_31
|
||||
INT_L.SS6BEG1.LH6 04_31 05_29
|
||||
INT_L.SS6BEG1.NW2END2 03_30 05_30
|
||||
INT_L.SS6BEG1.NW6END2 05_30 07_31
|
||||
INT_L.SS6BEG1.SE2END1 03_30 04_28
|
||||
|
|
@ -3160,8 +2956,6 @@ INT_L.SS6BEG2.LOGIC_OUTS_L10 02_47 06_46
|
|||
INT_L.SS6BEG2.LOGIC_OUTS_L14 02_47 05_45
|
||||
INT_L.SS6BEG2.LOGIC_OUTS_L16 06_46 07_47
|
||||
INT_L.SS6BEG2.LOGIC_OUTS_L20 05_45 07_47
|
||||
INT_L.SS6BEG2.LVB_L0 04_47 06_46
|
||||
INT_L.SS6BEG2.LVB_L12 04_47 05_45
|
||||
INT_L.SS6BEG2.EE2END2 02_47 04_44
|
||||
INT_L.SS6BEG2.EE4END2 04_44 04_47
|
||||
INT_L.SS6BEG2.NW2END3 03_46 05_46
|
||||
|
|
@ -3180,13 +2974,11 @@ INT_L.SS6BEG3.LOGIC_OUTS_L11 02_63 05_61
|
|||
INT_L.SS6BEG3.LOGIC_OUTS_L15 02_63 06_62
|
||||
INT_L.SS6BEG3.LOGIC_OUTS_L17 05_61 07_63
|
||||
INT_L.SS6BEG3.LOGIC_OUTS_L21 06_62 07_63
|
||||
INT_L.SS6BEG3.LV_L18 04_63 05_61
|
||||
INT_L.SS6BEG3.NW2END_S0_0 03_62 05_62
|
||||
INT_L.SS6BEG3.NW6END_S0_0 05_62 07_63
|
||||
INT_L.SS6BEG3.WW4END_S0_0 04_63 05_62
|
||||
INT_L.SS6BEG3.EE2END3 02_63 04_60
|
||||
INT_L.SS6BEG3.EE4END3 04_60 04_63
|
||||
INT_L.SS6BEG3.LH0 04_63 06_62
|
||||
INT_L.SS6BEG3.SE2END3 03_62 04_60
|
||||
INT_L.SS6BEG3.SE6END3 04_60 07_63
|
||||
INT_L.SS6BEG3.SS2END3 02_62 02_63
|
||||
|
|
@ -3280,10 +3072,8 @@ INT_L.SW6BEG0.LOGIC_OUTS_L8 03_12 04_14
|
|||
INT_L.SW6BEG0.LOGIC_OUTS_L12 03_12 07_13
|
||||
INT_L.SW6BEG0.LOGIC_OUTS_L18 04_14 06_12
|
||||
INT_L.SW6BEG0.LOGIC_OUTS_L22 06_12 07_13
|
||||
INT_L.SW6BEG0.LV_L0 04_14 05_12
|
||||
INT_L.SW6BEG0.EE2END0 03_12 04_13
|
||||
INT_L.SW6BEG0.EE4END0 04_13 05_12
|
||||
INT_L.SW6BEG0.LH12 05_12 07_13
|
||||
INT_L.SW6BEG0.NW2END1 02_13 05_15
|
||||
INT_L.SW6BEG0.NW6END1 05_15 06_12
|
||||
INT_L.SW6BEG0.SE2END0 02_13 04_13
|
||||
|
|
@ -3300,10 +3090,8 @@ INT_L.SW6BEG1.LOGIC_OUTS_L9 03_28 07_29
|
|||
INT_L.SW6BEG1.LOGIC_OUTS_L13 03_28 04_30
|
||||
INT_L.SW6BEG1.LOGIC_OUTS_L19 06_28 07_29
|
||||
INT_L.SW6BEG1.LOGIC_OUTS_L23 04_30 06_28
|
||||
INT_L.SW6BEG1.LV_L9 04_30 05_28
|
||||
INT_L.SW6BEG1.EE2END1 03_28 04_29
|
||||
INT_L.SW6BEG1.EE4END1 04_29 05_28
|
||||
INT_L.SW6BEG1.LH6 05_28 07_29
|
||||
INT_L.SW6BEG1.NW2END2 02_29 05_31
|
||||
INT_L.SW6BEG1.NW6END2 05_31 06_28
|
||||
INT_L.SW6BEG1.SE2END1 02_29 04_29
|
||||
|
|
@ -3320,10 +3108,7 @@ INT_L.SW6BEG2.LOGIC_OUTS_L10 03_44 04_46
|
|||
INT_L.SW6BEG2.LOGIC_OUTS_L14 03_44 07_45
|
||||
INT_L.SW6BEG2.LOGIC_OUTS_L16 04_46 06_44
|
||||
INT_L.SW6BEG2.LOGIC_OUTS_L20 06_44 07_45
|
||||
INT_L.SW6BEG2.LVB_L0 04_46 05_44
|
||||
INT_L.SW6BEG2.LVB_L12 05_44 07_45
|
||||
INT_L.SW6BEG2.EE2END2 03_44 04_45
|
||||
INT_L.SW6BEG2.EE4END2 04_45 05_44
|
||||
INT_L.SW6BEG2.NW2END3 02_45 05_47
|
||||
INT_L.SW6BEG2.NW6END3 05_47 06_44
|
||||
INT_L.SW6BEG2.SE2END2 02_45 04_45
|
||||
|
|
@ -3340,13 +3125,10 @@ INT_L.SW6BEG3.LOGIC_OUTS_L11 03_60 07_61
|
|||
INT_L.SW6BEG3.LOGIC_OUTS_L15 03_60 04_62
|
||||
INT_L.SW6BEG3.LOGIC_OUTS_L17 06_60 07_61
|
||||
INT_L.SW6BEG3.LOGIC_OUTS_L21 04_62 06_60
|
||||
INT_L.SW6BEG3.LV_L18 05_60 07_61
|
||||
INT_L.SW6BEG3.NW2END_S0_0 02_61 05_63
|
||||
INT_L.SW6BEG3.NW6END_S0_0 05_63 06_60
|
||||
INT_L.SW6BEG3.WW4END_S0_0 05_60 05_63
|
||||
INT_L.SW6BEG3.EE2END3 03_60 04_61
|
||||
INT_L.SW6BEG3.EE4END3 04_61 05_60
|
||||
INT_L.SW6BEG3.LH0 04_62 05_60
|
||||
INT_L.SW6BEG3.SE2END3 02_61 04_61
|
||||
INT_L.SW6BEG3.SE6END3 04_61 06_60
|
||||
INT_L.SW6BEG3.SS2END3 03_60 03_61
|
||||
|
|
@ -3560,15 +3342,12 @@ INT_L.WW4BEG0.LOGIC_OUTS_L8 03_00 07_01
|
|||
INT_L.WW4BEG0.LOGIC_OUTS_L12 03_00 04_02
|
||||
INT_L.WW4BEG0.LOGIC_OUTS_L18 06_00 07_01
|
||||
INT_L.WW4BEG0.LOGIC_OUTS_L22 04_02 06_00
|
||||
INT_L.WW4BEG0.LV_L0 04_02 05_00
|
||||
INT_L.WW4BEG0.SS2END_N0_3 03_00 04_01
|
||||
INT_L.WW4BEG0.SS6END_N0_3 04_01 06_00
|
||||
INT_L.WW4BEG0.SW2END_N0_3 02_01 04_01
|
||||
INT_L.WW4BEG0.SW6END_N0_3 04_01 05_00
|
||||
INT_L.WW4BEG0.WW2END_N0_3 03_00 03_01
|
||||
INT_L.WW4BEG0.LH12 05_00 07_01
|
||||
INT_L.WW4BEG0.NE2END0 02_01 05_03
|
||||
INT_L.WW4BEG0.NE6END0 05_00 05_03
|
||||
INT_L.WW4BEG0.NN2END0 03_00 05_03
|
||||
INT_L.WW4BEG0.NN6END0 05_03 06_00
|
||||
INT_L.WW4BEG0.NW2END0 02_01 03_01
|
||||
|
|
@ -3580,8 +3359,6 @@ INT_L.WW4BEG1.LOGIC_OUTS_L9 03_16 04_18
|
|||
INT_L.WW4BEG1.LOGIC_OUTS_L13 03_16 07_17
|
||||
INT_L.WW4BEG1.LOGIC_OUTS_L19 04_18 06_16
|
||||
INT_L.WW4BEG1.LOGIC_OUTS_L23 06_16 07_17
|
||||
INT_L.WW4BEG1.LV_L9 04_18 05_16
|
||||
INT_L.WW4BEG1.LH6 05_16 07_17
|
||||
INT_L.WW4BEG1.NE2END1 02_17 05_19
|
||||
INT_L.WW4BEG1.NE6END1 05_16 05_19
|
||||
INT_L.WW4BEG1.NN2END1 03_16 05_19
|
||||
|
|
@ -3600,10 +3377,7 @@ INT_L.WW4BEG2.LOGIC_OUTS_L10 03_32 07_33
|
|||
INT_L.WW4BEG2.LOGIC_OUTS_L14 03_32 04_34
|
||||
INT_L.WW4BEG2.LOGIC_OUTS_L16 06_32 07_33
|
||||
INT_L.WW4BEG2.LOGIC_OUTS_L20 04_34 06_32
|
||||
INT_L.WW4BEG2.LVB_L0 04_34 05_32
|
||||
INT_L.WW4BEG2.LVB_L12 05_32 07_33
|
||||
INT_L.WW4BEG2.NE2END2 02_33 05_35
|
||||
INT_L.WW4BEG2.NE6END2 05_32 05_35
|
||||
INT_L.WW4BEG2.NN2END2 03_32 05_35
|
||||
INT_L.WW4BEG2.NN6END2 05_35 06_32
|
||||
INT_L.WW4BEG2.NW2END2 02_33 03_33
|
||||
|
|
@ -3620,10 +3394,7 @@ INT_L.WW4BEG3.LOGIC_OUTS_L11 03_48 04_50
|
|||
INT_L.WW4BEG3.LOGIC_OUTS_L15 03_48 07_49
|
||||
INT_L.WW4BEG3.LOGIC_OUTS_L17 04_50 06_48
|
||||
INT_L.WW4BEG3.LOGIC_OUTS_L21 06_48 07_49
|
||||
INT_L.WW4BEG3.LV_L18 05_48 07_49
|
||||
INT_L.WW4BEG3.LH0 04_50 05_48
|
||||
INT_L.WW4BEG3.NE2END3 02_49 05_51
|
||||
INT_L.WW4BEG3.NE6END3 05_48 05_51
|
||||
INT_L.WW4BEG3.NN2END3 03_48 05_51
|
||||
INT_L.WW4BEG3.NN6END3 05_51 06_48
|
||||
INT_L.WW4BEG3.NW2END3 02_49 03_49
|
||||
|
|
|
|||
|
|
@ -245,7 +245,7 @@ INT_R.FAN_ALT0.WL1END_N1_3 16_00 !22_00 23_00 24_00 25_00
|
|||
INT_R.FAN_ALT0.WW2END_N0_3 16_00 !22_00 !23_00 !24_00 25_00
|
||||
INT_R.FAN_ALT0.EE2END0 19_01 !22_00 !23_00 !24_00 25_00
|
||||
INT_R.FAN_ALT0.EL1END0 17_00 !22_00 23_00 24_00 25_00
|
||||
INT_R.FAN_ALT0.GFAN0 01_10 01_14 21_00 25_00
|
||||
INT_R.FAN_ALT0.GFAN0 21_00 !22_00 !23_00 !24_00 25_00
|
||||
INT_R.FAN_ALT0.NE2END0 18_01 !22_00 !23_00 24_00 !25_00
|
||||
INT_R.FAN_ALT0.NL1END0 19_01 !22_00 23_00 24_00 25_00
|
||||
INT_R.FAN_ALT0.NN2END0 18_01 !22_00 !23_00 !24_00 25_00
|
||||
|
|
@ -265,7 +265,6 @@ INT_R.FAN_ALT1.NL1BEG_N3 19_49 !22_48 23_48 24_48 25_48
|
|||
INT_R.FAN_ALT1.EE2END3 19_49 !22_48 !23_48 !24_48 25_48
|
||||
INT_R.FAN_ALT1.EL1END3 17_48 !22_48 23_48 24_48 25_48
|
||||
INT_R.FAN_ALT1.ER1END2 16_48 22_48 !23_48 24_48 25_48
|
||||
INT_R.FAN_ALT1.GFAN1 00_14 00_17 21_48 25_48
|
||||
INT_R.FAN_ALT1.NE2END3 18_49 !22_48 !23_48 24_48 !25_48
|
||||
INT_R.FAN_ALT1.NN2END3 18_49 !22_48 !23_48 !24_48 25_48
|
||||
INT_R.FAN_ALT1.NR1END3 18_49 22_48 !23_48 24_48 25_48
|
||||
|
|
@ -278,7 +277,6 @@ INT_R.FAN_ALT1.SW2END2 17_48 !22_48 !23_48 24_48 !25_48
|
|||
INT_R.FAN_ALT1.WL1END2 16_48 !22_48 23_48 24_48 25_48
|
||||
INT_R.FAN_ALT1.WR1END3 17_48 22_48 !23_48 24_48 25_48
|
||||
INT_R.FAN_ALT1.WW2END2 16_48 !22_48 !23_48 !24_48 25_48
|
||||
INT_R.FAN_ALT2.BYP_BOUNCE_N3_6 20_16 !22_16 !23_16 24_16 !25_16
|
||||
INT_R.FAN_ALT2.BYP_BOUNCE0 20_16 !22_16 !23_16 !24_16 25_16
|
||||
INT_R.FAN_ALT2.FAN_BOUNCE5 20_16 !22_16 23_16 24_16 25_16
|
||||
INT_R.FAN_ALT2.FAN_BOUNCE6 20_16 22_16 !23_16 24_16 25_16
|
||||
|
|
@ -314,7 +312,7 @@ INT_R.FAN_ALT3.NW2END_S0_0 19_57 !22_56 !23_56 24_56 !25_56
|
|||
INT_R.FAN_ALT3.EE2END3 16_56 !22_56 !23_56 !24_56 25_56
|
||||
INT_R.FAN_ALT3.EL1END3 16_56 !22_56 23_56 24_56 25_56
|
||||
INT_R.FAN_ALT3.ER1END3 17_56 22_56 !23_56 24_56 25_56
|
||||
INT_R.FAN_ALT3.GFAN1 00_14 00_17 21_56 25_56
|
||||
INT_R.FAN_ALT3.GFAN1 21_56 !22_56 !23_56 !24_56 25_56
|
||||
INT_R.FAN_ALT3.NE2END3 17_56 !22_56 !23_56 24_56 !25_56
|
||||
INT_R.FAN_ALT3.NN2END3 17_56 !22_56 !23_56 !24_56 25_56
|
||||
INT_R.FAN_ALT3.NR1END3 18_57 22_56 !23_56 24_56 25_56
|
||||
|
|
@ -326,10 +324,7 @@ INT_R.FAN_ALT3.SW2END3 18_57 !22_56 !23_56 24_56 !25_56
|
|||
INT_R.FAN_ALT3.WL1END3 17_56 !22_56 23_56 24_56 25_56
|
||||
INT_R.FAN_ALT3.WR1END3 16_56 22_56 !23_56 24_56 25_56
|
||||
INT_R.FAN_ALT3.WW2END3 19_57 !22_56 !23_56 !24_56 25_56
|
||||
INT_R.FAN_ALT4.BYP_BOUNCE_N3_3 20_08 !22_08 !23_08 !24_08 25_08
|
||||
INT_R.FAN_ALT4.BYP_BOUNCE_N3_7 20_08 !22_08 !23_08 24_08 !25_08
|
||||
INT_R.FAN_ALT4.FAN_BOUNCE2 20_08 22_08 !23_08 24_08 25_08
|
||||
INT_R.FAN_ALT4.FAN_BOUNCE7 20_08 !22_08 23_08 24_08 25_08
|
||||
INT_R.FAN_ALT4.LOGIC_OUTS4 21_08 22_08 !23_08 24_08 25_08
|
||||
INT_R.FAN_ALT4.LOGIC_OUTS8 21_08 !22_08 23_08 24_08 25_08
|
||||
INT_R.FAN_ALT4.LOGIC_OUTS18 21_08 !22_08 !23_08 24_08 !25_08
|
||||
|
|
@ -350,7 +345,6 @@ INT_R.FAN_ALT4.SW2END0 18_09 !22_08 !23_08 24_08 !25_08
|
|||
INT_R.FAN_ALT4.WL1END0 17_08 !22_08 23_08 24_08 25_08
|
||||
INT_R.FAN_ALT4.WR1END0 16_08 22_08 !23_08 24_08 25_08
|
||||
INT_R.FAN_ALT4.WW2END0 19_09 !22_08 !23_08 !24_08 25_08
|
||||
INT_R.FAN_ALT5.BYP_BOUNCE1 20_40 24_40 25_15
|
||||
INT_R.FAN_ALT5.BYP_BOUNCE5 20_40 !22_40 !23_40 !24_40 25_40
|
||||
INT_R.FAN_ALT5.FAN_BOUNCE_S3_0 20_40 22_40 !23_40 24_40 25_40
|
||||
INT_R.FAN_ALT5.FAN_BOUNCE1 20_40 !22_40 23_40 24_40 25_40
|
||||
|
|
@ -361,7 +355,6 @@ INT_R.FAN_ALT5.NL1BEG_N3 19_41 !22_40 23_40 24_40 25_40
|
|||
INT_R.FAN_ALT5.EE2END2 16_40 !22_40 !23_40 !24_40 25_40
|
||||
INT_R.FAN_ALT5.EL1END2 16_40 !22_40 23_40 24_40 25_40
|
||||
INT_R.FAN_ALT5.ER1END2 17_40 22_40 !23_40 24_40 25_40
|
||||
INT_R.FAN_ALT5.GFAN1 00_20 01_43 21_40 !22_40 !23_40 !24_40 25_40
|
||||
INT_R.FAN_ALT5.NE2END2 17_40 !22_40 !23_40 24_40 !25_40
|
||||
INT_R.FAN_ALT5.NN2END2 17_40 !22_40 !23_40 !24_40 25_40
|
||||
INT_R.FAN_ALT5.NR1END2 18_41 22_40 !23_40 24_40 25_40
|
||||
|
|
@ -534,38 +527,6 @@ INT_R.CLK1.GCLK_B11 00_27 !00_29 01_25 01_26 01_29
|
|||
INT_R.CLK1.ER1END1 00_27 00_29 01_25 01_26 !01_29
|
||||
INT_R.CLK1.SR1END1 !00_27 !00_29 01_25 01_26 !01_29
|
||||
INT_R.CLK1.WR1END1 00_27 !00_29 01_25 !01_26 !01_29
|
||||
INT_R.CTRL0.BYP_BOUNCE4 !00_35 !00_39 01_37 01_38 !01_40
|
||||
INT_R.CTRL0.FAN_BOUNCE1 !00_35 00_39 01_37 !01_38 !01_40
|
||||
INT_R.CTRL0.EE4END2 !00_35 00_38 00_39 !01_38 !01_40
|
||||
INT_R.CTRL0.ER1END2 !00_35 !00_39 01_33 01_38 !01_40
|
||||
INT_R.CTRL0.GFAN0 00_35 00_39 01_37 01_38 !01_40
|
||||
INT_R.CTRL0.GFAN1 !00_35 00_39 01_37 01_38 01_40
|
||||
INT_R.CTRL0.NE6END2 !00_35 00_39 01_33 01_38 01_40
|
||||
INT_R.CTRL0.NN6END2 00_35 00_39 01_33 01_38 !01_40
|
||||
INT_R.CTRL0.NR1END2 00_34 !00_35 00_39 01_38 01_40
|
||||
INT_R.CTRL0.NW6END2 00_34 00_35 00_39 01_38 !01_40
|
||||
INT_R.CTRL0.SE6END2 !00_35 00_38 !00_39 01_38 !01_40
|
||||
INT_R.CTRL0.SR1END2 !00_35 00_38 00_39 01_38 01_40
|
||||
INT_R.CTRL0.SS6END2 00_35 00_38 00_39 01_38 !01_40
|
||||
INT_R.CTRL0.SW6END1 00_34 !00_35 !00_39 01_38 !01_40
|
||||
INT_R.CTRL0.WR1END2 00_34 !00_35 00_39 !01_38 !01_40
|
||||
INT_R.CTRL0.WW4END2 !00_35 00_39 01_33 !01_38 !01_40
|
||||
INT_R.CTRL1.BYP_BOUNCE4 !00_37 00_42 01_32 !01_36 !01_41
|
||||
INT_R.CTRL1.FAN_BOUNCE1 !00_37 !00_42 01_32 !01_36 01_41
|
||||
INT_R.CTRL1.EE4END2 !00_37 00_41 !00_42 !01_36 01_41
|
||||
INT_R.CTRL1.ER1END2 00_33 !00_37 00_42 !01_36 !01_41
|
||||
INT_R.CTRL1.GFAN0 !00_37 00_42 01_32 01_36 01_41
|
||||
INT_R.CTRL1.GFAN1 00_37 00_42 01_32 !01_36 01_41
|
||||
INT_R.CTRL1.NE6END2 00_33 00_37 00_42 !01_36 01_41
|
||||
INT_R.CTRL1.NN6END2 00_33 !00_37 00_42 01_36 01_41
|
||||
INT_R.CTRL1.NR1END2 00_37 00_42 01_34 !01_36 01_41
|
||||
INT_R.CTRL1.NW6END2 !00_37 00_42 01_34 01_36 01_41
|
||||
INT_R.CTRL1.SE6END2 !00_37 00_41 00_42 !01_36 !01_41
|
||||
INT_R.CTRL1.SR1END2 00_37 00_41 00_42 !01_36 01_41
|
||||
INT_R.CTRL1.SS6END2 !00_37 00_41 00_42 01_36 01_41
|
||||
INT_R.CTRL1.SW6END1 !00_37 00_42 01_34 !01_36 !01_41
|
||||
INT_R.CTRL1.WR1END2 !00_37 !00_42 01_34 !01_36 01_41
|
||||
INT_R.CTRL1.WW4END2 00_33 !00_37 !00_42 !01_36 01_41
|
||||
INT_R.EE2BEG0.LOGIC_OUTS0 09_07 15_06
|
||||
INT_R.EE2BEG0.LOGIC_OUTS4 09_06 15_06
|
||||
INT_R.EE2BEG0.LOGIC_OUTS8 11_06 15_06
|
||||
|
|
@ -654,8 +615,6 @@ INT_R.EE4BEG0.LOGIC_OUTS18 06_08 07_09
|
|||
INT_R.EE4BEG0.LOGIC_OUTS22 04_10 06_08
|
||||
INT_R.EE4BEG0.EE2END0 03_08 03_09
|
||||
INT_R.EE4BEG0.EE4END0 03_09 05_08
|
||||
INT_R.EE4BEG0.LH12 05_08 07_09
|
||||
INT_R.EE4BEG0.LV0 04_10 05_08
|
||||
INT_R.EE4BEG0.NE2END0 02_09 04_09
|
||||
INT_R.EE4BEG0.NE6END0 04_09 05_08
|
||||
INT_R.EE4BEG0.NN2END0 03_08 04_09
|
||||
|
|
@ -674,8 +633,6 @@ INT_R.EE4BEG1.LOGIC_OUTS19 04_26 06_24
|
|||
INT_R.EE4BEG1.LOGIC_OUTS23 06_24 07_25
|
||||
INT_R.EE4BEG1.EE2END1 03_24 03_25
|
||||
INT_R.EE4BEG1.EE4END1 03_25 05_24
|
||||
INT_R.EE4BEG1.LH6 05_24 07_25
|
||||
INT_R.EE4BEG1.LV9 04_26 05_24
|
||||
INT_R.EE4BEG1.NE2END1 02_25 04_25
|
||||
INT_R.EE4BEG1.NE6END1 04_25 05_24
|
||||
INT_R.EE4BEG1.NN2END1 03_24 04_25
|
||||
|
|
@ -685,7 +642,6 @@ INT_R.EE4BEG1.SE6END1 03_25 06_24
|
|||
INT_R.EE4BEG1.SS2END1 03_24 05_27
|
||||
INT_R.EE4BEG1.SS6END1 05_27 06_24
|
||||
INT_R.EE4BEG1.SW2END1 02_25 05_27
|
||||
INT_R.EE4BEG1.SW6END1 05_24 05_27
|
||||
INT_R.EE4BEG2.LOGIC_OUTS2 02_41 04_42
|
||||
INT_R.EE4BEG2.LOGIC_OUTS6 02_41 07_41
|
||||
INT_R.EE4BEG2.LOGIC_OUTS10 03_40 07_41
|
||||
|
|
@ -694,8 +650,6 @@ INT_R.EE4BEG2.LOGIC_OUTS16 06_40 07_41
|
|||
INT_R.EE4BEG2.LOGIC_OUTS20 04_42 06_40
|
||||
INT_R.EE4BEG2.EE2END2 03_40 03_41
|
||||
INT_R.EE4BEG2.EE4END2 03_41 05_40
|
||||
INT_R.EE4BEG2.LVB0 04_42 05_40
|
||||
INT_R.EE4BEG2.LVB12 05_40 07_41
|
||||
INT_R.EE4BEG2.NE2END2 02_41 04_41
|
||||
INT_R.EE4BEG2.NE6END2 04_41 05_40
|
||||
INT_R.EE4BEG2.NN2END2 03_40 04_41
|
||||
|
|
@ -714,8 +668,6 @@ INT_R.EE4BEG3.LOGIC_OUTS17 04_58 06_56
|
|||
INT_R.EE4BEG3.LOGIC_OUTS21 06_56 07_57
|
||||
INT_R.EE4BEG3.EE2END3 03_56 03_57
|
||||
INT_R.EE4BEG3.EE4END3 03_57 05_56
|
||||
INT_R.EE4BEG3.LH0 04_58 05_56
|
||||
INT_R.EE4BEG3.LV18 05_56 07_57
|
||||
INT_R.EE4BEG3.NE2END3 02_57 04_57
|
||||
INT_R.EE4BEG3.NE6END3 04_57 05_56
|
||||
INT_R.EE4BEG3.NN2END3 03_56 04_57
|
||||
|
|
@ -725,7 +677,6 @@ INT_R.EE4BEG3.SE6END3 03_57 06_56
|
|||
INT_R.EE4BEG3.SS2END3 03_56 05_59
|
||||
INT_R.EE4BEG3.SS6END3 05_59 06_56
|
||||
INT_R.EE4BEG3.SW2END3 02_57 05_59
|
||||
INT_R.EE4BEG3.SW6END3 05_56 05_59
|
||||
INT_R.EL1BEG0.LOGIC_OUTS1 07_20 14_21
|
||||
INT_R.EL1BEG0.LOGIC_OUTS5 11_21 14_21
|
||||
INT_R.EL1BEG0.LOGIC_OUTS9 10_21 13_21
|
||||
|
|
@ -846,38 +797,8 @@ INT_R.ER1BEG3.SW2END2 07_42 15_43
|
|||
INT_R.ER1BEG3.SW6END2 07_42 12_43
|
||||
INT_R.ER1BEG3.WW2END2 11_43 15_43
|
||||
INT_R.ER1BEG3.WW4END3 11_43 12_43
|
||||
INT_R.GFAN0.BYP_BOUNCE1 00_10 00_11 !01_09 01_10 01_14
|
||||
INT_R.GFAN0.GCLK_B0_EAST 00_10 00_11 !01_09 01_10 01_12
|
||||
INT_R.GFAN0.GCLK_B1_EAST !00_10 00_11 01_09 01_10 01_12
|
||||
INT_R.GFAN0.GCLK_B2_EAST !00_10 !00_11 !01_09 01_10 01_12
|
||||
INT_R.GFAN0.GCLK_B3_EAST !00_10 00_11 !01_09 !01_10 01_12
|
||||
INT_R.GFAN0.GCLK_B4_EAST 00_10 00_11 !01_09 01_10 01_18
|
||||
INT_R.GFAN0.GCLK_B5_EAST !00_10 00_11 01_09 01_10 01_18
|
||||
INT_R.GFAN0.GCLK_B6 !00_10 !00_11 !01_09 01_10 01_18
|
||||
INT_R.GFAN0.GCLK_B7 !00_10 00_11 !01_09 !01_10 01_18
|
||||
INT_R.GFAN0.GCLK_B8 00_10 00_11 !01_09 01_10 01_16
|
||||
INT_R.GFAN0.GCLK_B9 !00_10 00_11 01_09 01_10 01_16
|
||||
INT_R.GFAN0.GCLK_B10 !00_10 !00_11 !01_09 01_10 01_16
|
||||
INT_R.GFAN0.GCLK_B11 !00_10 00_11 !01_09 !01_10 01_16
|
||||
INT_R.GFAN0.GND_WIRE !00_10 00_11 !01_09 !01_10 01_14
|
||||
INT_R.GFAN0.NR1END1 !00_10 00_11 01_09 01_10 01_14
|
||||
INT_R.GFAN0.WW4END1 !00_10 !00_11 !01_09 01_10 01_14
|
||||
INT_R.GFAN1.BYP_BOUNCE1 00_14 00_17 00_18 !00_19 01_13
|
||||
INT_R.GFAN1.GCLK_B0_EAST 00_13 00_14 00_18 !00_19 01_13
|
||||
INT_R.GFAN1.GCLK_B1_EAST 00_13 00_14 !00_18 00_19 01_13
|
||||
INT_R.GFAN1.GCLK_B2_EAST 00_13 00_14 !00_18 !00_19 !01_13
|
||||
INT_R.GFAN1.GCLK_B3_EAST 00_13 !00_14 !00_18 !00_19 01_13
|
||||
INT_R.GFAN1.GCLK_B4_EAST 00_14 00_15 00_18 !00_19 01_13
|
||||
INT_R.GFAN1.GCLK_B5_EAST 00_14 00_15 !00_18 00_19 01_13
|
||||
INT_R.GFAN1.GCLK_B6 00_14 00_15 !00_18 !00_19 !01_13
|
||||
INT_R.GFAN1.GCLK_B7 !00_14 00_15 !00_18 !00_19 01_13
|
||||
INT_R.GFAN1.GCLK_B8 00_14 00_18 !00_19 01_13 01_17
|
||||
INT_R.GFAN1.GCLK_B9 00_14 !00_18 00_19 01_13 01_17
|
||||
INT_R.GFAN1.GCLK_B10 00_14 !00_18 !00_19 !01_13 01_17
|
||||
INT_R.GFAN1.GCLK_B11 !00_14 !00_18 !00_19 01_13 01_17
|
||||
INT_R.GFAN1.GND_WIRE !00_14 00_17 !00_18 !00_19 01_13
|
||||
INT_R.GFAN1.NR1END1 00_14 00_17 !00_18 00_19 01_13
|
||||
INT_R.GFAN1.WW4END1 00_14 00_17 !00_18 !00_19 !01_13
|
||||
INT_R.IMUX0.BYP_BOUNCE_N3_2 21_01 !22_01 !23_01 !24_01 25_01
|
||||
INT_R.IMUX0.BYP_BOUNCE_N3_6 21_01 !22_01 !23_01 24_01 !25_01
|
||||
INT_R.IMUX0.ER1END_N3_3 18_00 !22_01 23_01 24_01 25_01
|
||||
|
|
@ -2030,90 +1951,6 @@ INT_R.IMUX47.SS2END3 17_62 !22_62 !23_62 !24_62 25_62
|
|||
INT_R.IMUX47.SW2END3 17_62 !22_62 !23_62 24_62 !25_62
|
||||
INT_R.IMUX47.WL1END3 18_63 !22_62 23_62 24_62 25_62
|
||||
INT_R.IMUX47.WW2END3 16_62 !22_62 !23_62 !24_62 25_62
|
||||
INT_R.LH0.EE4END3 00_58 01_61
|
||||
INT_R.LH0.ER1END3 00_57 01_54
|
||||
INT_R.LH0.LH12 01_54 01_56
|
||||
INT_R.LH0.LV0 01_56 01_58
|
||||
INT_R.LH0.LV9 00_59 01_56
|
||||
INT_R.LH0.LV18 01_56 01_61
|
||||
INT_R.LH0.NE2END3 00_58 00_59
|
||||
INT_R.LH0.NE6END3 00_58 01_58
|
||||
INT_R.LH0.NW2END3 00_58 01_54
|
||||
INT_R.LH0.SR1END3 00_57 00_59
|
||||
INT_R.LH0.SS6END3 00_57 01_58
|
||||
INT_R.LH0.SW6END3 00_57 01_61
|
||||
INT_R.LH12.EE4END3 01_60 01_62
|
||||
INT_R.LH12.ER1END3 00_63 01_60
|
||||
INT_R.LH12.LH0 00_61 00_63
|
||||
INT_R.LH12.LV0 00_55 00_62
|
||||
INT_R.LH12.LV9 00_62 01_57
|
||||
INT_R.LH12.LV18 00_62 01_62
|
||||
INT_R.LH12.NE2END3 01_57 01_60
|
||||
INT_R.LH12.NE6END3 00_55 01_60
|
||||
INT_R.LH12.NW2END3 00_62 00_63
|
||||
INT_R.LH12.SR1END3 00_61 01_57
|
||||
INT_R.LH12.SS6END3 00_55 00_61
|
||||
INT_R.LH12.SW6END3 00_61 01_62
|
||||
INT_R.LV0.SR1BEG_S0 00_05 01_05
|
||||
INT_R.LV0.ER1END0 01_04 01_05
|
||||
INT_R.LV0.LH0 00_02 01_06
|
||||
INT_R.LV0.LH6 01_04 01_06
|
||||
INT_R.LV0.LH12 00_05 01_06
|
||||
INT_R.LV0.LV18 00_09 01_06
|
||||
INT_R.LV0.NN6END0 00_07 00_09
|
||||
INT_R.LV0.NR1END0 00_02 01_05
|
||||
INT_R.LV0.NW6END0 00_07 01_04
|
||||
INT_R.LV0.SW6END0 00_09 01_05
|
||||
INT_R.LV0.WR1END0 00_02 00_07
|
||||
INT_R.LV0.WW4END0 00_05 00_07
|
||||
INT_R.LV18.SR1BEG_S0 00_03 01_08
|
||||
INT_R.LV18.ER1END0 00_03 00_06
|
||||
INT_R.LV18.LH0 00_01 01_02
|
||||
INT_R.LV18.LH6 00_06 01_02
|
||||
INT_R.LV18.LH12 01_08
|
||||
INT_R.LV18.LV0 01_00 01_01
|
||||
INT_R.LV18.NN6END0 00_03 01_00
|
||||
INT_R.LV18.NR1END0 00_01 00_03
|
||||
INT_R.LV18.NW6END0 00_06 01_01
|
||||
INT_R.LV18.SW6END0 01_00 01_02
|
||||
INT_R.LV18.WR1END0 00_01 01_01
|
||||
INT_R.LV18.WW4END0 01_01 01_08
|
||||
INT_R.LVB0.LH0 00_43 00_51
|
||||
INT_R.LVB0.LH6 00_51 00_53
|
||||
INT_R.LVB0.LH12 00_50 00_51
|
||||
INT_R.LVB0.LV0 00_47 01_52
|
||||
INT_R.LVB0.LV18 01_42 01_52
|
||||
INT_R.LVB0.LVB12 00_51 00_54
|
||||
INT_R.LVB0.NE2END2 00_53 01_52
|
||||
INT_R.LVB0.NN6END3 00_50 01_50
|
||||
INT_R.LVB0.NR1END3 00_47 01_50
|
||||
INT_R.LVB0.NW2END2 00_43 01_52
|
||||
INT_R.LVB0.NW6END3 00_43 01_50
|
||||
INT_R.LVB0.SE2END3 00_51 01_42
|
||||
INT_R.LVB0.SE6END3 00_54 01_50
|
||||
INT_R.LVB0.SW2END2 00_50 01_52
|
||||
INT_R.LVB0.SW2END3 00_47 00_51
|
||||
INT_R.LVB0.SW6END2 00_54 01_52
|
||||
INT_R.LVB0.WR1END3 01_42 01_50
|
||||
INT_R.LVB0.WW4END3 00_53 01_50
|
||||
INT_R.LVB12.LH0 00_46 00_49
|
||||
INT_R.LVB12.LH6 00_46 01_49
|
||||
INT_R.LVB12.LH12 00_46 01_53
|
||||
INT_R.LVB12.LV0 00_45 01_44
|
||||
INT_R.LVB12.LV18 00_45 01_48
|
||||
INT_R.LVB12.LVB0 00_45 01_45
|
||||
INT_R.LVB12.NE2END2 00_45 01_49
|
||||
INT_R.LVB12.NN6END3 01_46 01_53
|
||||
INT_R.LVB12.NR1END3 01_44 01_46
|
||||
INT_R.LVB12.NW2END2 00_45 00_49
|
||||
INT_R.LVB12.NW6END3 00_49 01_46
|
||||
INT_R.LVB12.SE2END3 00_46 01_48
|
||||
INT_R.LVB12.SE6END3 00_46 01_45
|
||||
INT_R.LVB12.SW2END2 00_45 01_53
|
||||
INT_R.LVB12.SW2END3 00_46 01_44
|
||||
INT_R.LVB12.SW6END2 01_45 01_46
|
||||
INT_R.LVB12.WR1END3 01_46 01_48
|
||||
INT_R.LVB12.WW4END3 01_46 01_49
|
||||
INT_R.NE2BEG0.LOGIC_OUTS0 09_05 15_04
|
||||
INT_R.NE2BEG0.LOGIC_OUTS4 09_04 15_04
|
||||
INT_R.NE2BEG0.LOGIC_OUTS8 11_04 15_04
|
||||
|
|
@ -2203,8 +2040,6 @@ INT_R.NE6BEG0.LOGIC_OUTS22 06_04 07_05
|
|||
INT_R.NE6BEG0.WW2END_N0_3 03_04 04_05
|
||||
INT_R.NE6BEG0.EE2END0 03_04 05_07
|
||||
INT_R.NE6BEG0.EE4END0 05_04 05_07
|
||||
INT_R.NE6BEG0.LH12 05_04 07_05
|
||||
INT_R.NE6BEG0.LV0 04_06 05_04
|
||||
INT_R.NE6BEG0.NE2END0 02_05 03_05
|
||||
INT_R.NE6BEG0.NE6END0 03_05 05_04
|
||||
INT_R.NE6BEG0.NN2END0 03_04 03_05
|
||||
|
|
@ -2222,8 +2057,6 @@ INT_R.NE6BEG1.LOGIC_OUTS19 06_20 07_21
|
|||
INT_R.NE6BEG1.LOGIC_OUTS23 04_22 06_20
|
||||
INT_R.NE6BEG1.EE2END1 03_20 05_23
|
||||
INT_R.NE6BEG1.EE4END1 05_20 05_23
|
||||
INT_R.NE6BEG1.LH6 05_20 07_21
|
||||
INT_R.NE6BEG1.LV9 04_22 05_20
|
||||
INT_R.NE6BEG1.NE2END1 02_21 03_21
|
||||
INT_R.NE6BEG1.NE6END1 03_21 05_20
|
||||
INT_R.NE6BEG1.NN2END1 03_20 03_21
|
||||
|
|
@ -2242,8 +2075,6 @@ INT_R.NE6BEG2.LOGIC_OUTS16 04_38 06_36
|
|||
INT_R.NE6BEG2.LOGIC_OUTS20 06_36 07_37
|
||||
INT_R.NE6BEG2.EE2END2 03_36 05_39
|
||||
INT_R.NE6BEG2.EE4END2 05_36 05_39
|
||||
INT_R.NE6BEG2.LVB0 04_38 05_36
|
||||
INT_R.NE6BEG2.LVB12 05_36 07_37
|
||||
INT_R.NE6BEG2.NE2END2 02_37 03_37
|
||||
INT_R.NE6BEG2.NE6END2 03_37 05_36
|
||||
INT_R.NE6BEG2.NN2END2 03_36 03_37
|
||||
|
|
@ -2262,8 +2093,6 @@ INT_R.NE6BEG3.LOGIC_OUTS17 06_52 07_53
|
|||
INT_R.NE6BEG3.LOGIC_OUTS21 04_54 06_52
|
||||
INT_R.NE6BEG3.EE2END3 03_52 05_55
|
||||
INT_R.NE6BEG3.EE4END3 05_52 05_55
|
||||
INT_R.NE6BEG3.LH0 04_54 05_52
|
||||
INT_R.NE6BEG3.LV18 05_52 07_53
|
||||
INT_R.NE6BEG3.NE2END3 02_53 03_53
|
||||
INT_R.NE6BEG3.NE6END3 03_53 05_52
|
||||
INT_R.NE6BEG3.NN2END3 03_52 03_53
|
||||
|
|
@ -2273,7 +2102,6 @@ INT_R.NE6BEG3.NW6END3 04_53 06_52
|
|||
INT_R.NE6BEG3.SE2END3 02_53 05_55
|
||||
INT_R.NE6BEG3.SE6END3 05_55 06_52
|
||||
INT_R.NE6BEG3.WW2END2 03_52 04_53
|
||||
INT_R.NE6BEG3.WW4END3 04_53 05_52
|
||||
INT_R.NL1BEG0.LOGIC_OUTS1 07_16 14_17
|
||||
INT_R.NL1BEG0.LOGIC_OUTS5 11_17 14_17
|
||||
INT_R.NL1BEG0.LOGIC_OUTS9 10_17 13_17
|
||||
|
|
@ -2423,8 +2251,6 @@ INT_R.NN6BEG0.LOGIC_OUTS22 05_05 07_07
|
|||
INT_R.NN6BEG0.WW2END_N0_3 02_07 04_04
|
||||
INT_R.NN6BEG0.EE2END0 02_07 05_06
|
||||
INT_R.NN6BEG0.EE4END0 04_07 05_06
|
||||
INT_R.NN6BEG0.LH12 04_07 05_05
|
||||
INT_R.NN6BEG0.LV0 04_07 06_06
|
||||
INT_R.NN6BEG0.NE2END0 02_06 03_06
|
||||
INT_R.NN6BEG0.NE6END0 02_06 04_07
|
||||
INT_R.NN6BEG0.NN2END0 02_06 02_07
|
||||
|
|
@ -2442,8 +2268,6 @@ INT_R.NN6BEG1.LOGIC_OUTS19 05_21 07_23
|
|||
INT_R.NN6BEG1.LOGIC_OUTS23 06_22 07_23
|
||||
INT_R.NN6BEG1.EE2END1 02_23 05_22
|
||||
INT_R.NN6BEG1.EE4END1 04_23 05_22
|
||||
INT_R.NN6BEG1.LH6 04_23 05_21
|
||||
INT_R.NN6BEG1.LV9 04_23 06_22
|
||||
INT_R.NN6BEG1.NE2END1 02_22 03_22
|
||||
INT_R.NN6BEG1.NE6END1 02_22 04_23
|
||||
INT_R.NN6BEG1.NN2END1 02_22 02_23
|
||||
|
|
@ -2462,8 +2286,6 @@ INT_R.NN6BEG2.LOGIC_OUTS16 06_38 07_39
|
|||
INT_R.NN6BEG2.LOGIC_OUTS20 05_37 07_39
|
||||
INT_R.NN6BEG2.EE2END2 02_39 05_38
|
||||
INT_R.NN6BEG2.EE4END2 04_39 05_38
|
||||
INT_R.NN6BEG2.LVB0 04_39 06_38
|
||||
INT_R.NN6BEG2.LVB12 04_39 05_37
|
||||
INT_R.NN6BEG2.NE2END2 02_38 03_38
|
||||
INT_R.NN6BEG2.NE6END2 02_38 04_39
|
||||
INT_R.NN6BEG2.NN2END2 02_38 02_39
|
||||
|
|
@ -2482,8 +2304,6 @@ INT_R.NN6BEG3.LOGIC_OUTS17 05_53 07_55
|
|||
INT_R.NN6BEG3.LOGIC_OUTS21 06_54 07_55
|
||||
INT_R.NN6BEG3.EE2END3 02_55 05_54
|
||||
INT_R.NN6BEG3.EE4END3 04_55 05_54
|
||||
INT_R.NN6BEG3.LH0 04_55 06_54
|
||||
INT_R.NN6BEG3.LV18 04_55 05_53
|
||||
INT_R.NN6BEG3.NE2END3 02_54 03_54
|
||||
INT_R.NN6BEG3.NE6END3 02_54 04_55
|
||||
INT_R.NN6BEG3.NN2END3 02_54 02_55
|
||||
|
|
@ -2665,8 +2485,6 @@ INT_R.NW6BEG0.SS6END_N0_3 04_00 07_03
|
|||
INT_R.NW6BEG0.SW2END_N0_3 03_02 04_00
|
||||
INT_R.NW6BEG0.SW6END_N0_3 04_00 04_03
|
||||
INT_R.NW6BEG0.WW2END_N0_3 02_02 02_03
|
||||
INT_R.NW6BEG0.LH12 04_03 05_01
|
||||
INT_R.NW6BEG0.LV0 04_03 06_02
|
||||
INT_R.NW6BEG0.NE2END0 03_02 05_02
|
||||
INT_R.NW6BEG0.NE6END0 04_03 05_02
|
||||
INT_R.NW6BEG0.NN2END0 02_03 05_02
|
||||
|
|
@ -2680,8 +2498,6 @@ INT_R.NW6BEG1.LOGIC_OUTS9 02_19 06_18
|
|||
INT_R.NW6BEG1.LOGIC_OUTS13 02_19 05_17
|
||||
INT_R.NW6BEG1.LOGIC_OUTS19 06_18 07_19
|
||||
INT_R.NW6BEG1.LOGIC_OUTS23 05_17 07_19
|
||||
INT_R.NW6BEG1.LH6 04_19 05_17
|
||||
INT_R.NW6BEG1.LV9 04_19 06_18
|
||||
INT_R.NW6BEG1.NE2END1 03_18 05_18
|
||||
INT_R.NW6BEG1.NE6END1 04_19 05_18
|
||||
INT_R.NW6BEG1.NN2END1 02_19 05_18
|
||||
|
|
@ -2700,8 +2516,6 @@ INT_R.NW6BEG2.LOGIC_OUTS10 02_35 05_33
|
|||
INT_R.NW6BEG2.LOGIC_OUTS14 02_35 06_34
|
||||
INT_R.NW6BEG2.LOGIC_OUTS16 05_33 07_35
|
||||
INT_R.NW6BEG2.LOGIC_OUTS20 06_34 07_35
|
||||
INT_R.NW6BEG2.LVB0 04_35 06_34
|
||||
INT_R.NW6BEG2.LVB12 04_35 05_33
|
||||
INT_R.NW6BEG2.NE2END2 03_34 05_34
|
||||
INT_R.NW6BEG2.NE6END2 04_35 05_34
|
||||
INT_R.NW6BEG2.NN2END2 02_35 05_34
|
||||
|
|
@ -2720,8 +2534,6 @@ INT_R.NW6BEG3.LOGIC_OUTS11 02_51 06_50
|
|||
INT_R.NW6BEG3.LOGIC_OUTS15 02_51 05_49
|
||||
INT_R.NW6BEG3.LOGIC_OUTS17 06_50 07_51
|
||||
INT_R.NW6BEG3.LOGIC_OUTS21 05_49 07_51
|
||||
INT_R.NW6BEG3.LH0 04_51 06_50
|
||||
INT_R.NW6BEG3.LV18 04_51 05_49
|
||||
INT_R.NW6BEG3.NE2END3 03_50 05_50
|
||||
INT_R.NW6BEG3.NE6END3 04_51 05_50
|
||||
INT_R.NW6BEG3.NN2END3 02_51 05_50
|
||||
|
|
@ -2822,8 +2634,6 @@ INT_R.SE6BEG0.LOGIC_OUTS18 05_09 07_11
|
|||
INT_R.SE6BEG0.LOGIC_OUTS22 06_10 07_11
|
||||
INT_R.SE6BEG0.EE2END0 02_10 02_11
|
||||
INT_R.SE6BEG0.EE4END0 02_10 04_11
|
||||
INT_R.SE6BEG0.LH12 04_11 05_09
|
||||
INT_R.SE6BEG0.LV0 04_11 06_10
|
||||
INT_R.SE6BEG0.NE2END0 03_10 04_08
|
||||
INT_R.SE6BEG0.NE6END0 04_08 04_11
|
||||
INT_R.SE6BEG0.NN2END0 02_11 04_08
|
||||
|
|
@ -2842,8 +2652,6 @@ INT_R.SE6BEG1.LOGIC_OUTS19 06_26 07_27
|
|||
INT_R.SE6BEG1.LOGIC_OUTS23 05_25 07_27
|
||||
INT_R.SE6BEG1.EE2END1 02_26 02_27
|
||||
INT_R.SE6BEG1.EE4END1 02_26 04_27
|
||||
INT_R.SE6BEG1.LH6 04_27 05_25
|
||||
INT_R.SE6BEG1.LV9 04_27 06_26
|
||||
INT_R.SE6BEG1.NE2END1 03_26 04_24
|
||||
INT_R.SE6BEG1.NE6END1 04_24 04_27
|
||||
INT_R.SE6BEG1.NN2END1 02_27 04_24
|
||||
|
|
@ -2862,8 +2670,6 @@ INT_R.SE6BEG2.LOGIC_OUTS16 05_41 07_43
|
|||
INT_R.SE6BEG2.LOGIC_OUTS20 06_42 07_43
|
||||
INT_R.SE6BEG2.EE2END2 02_42 02_43
|
||||
INT_R.SE6BEG2.EE4END2 02_42 04_43
|
||||
INT_R.SE6BEG2.LVB0 04_43 06_42
|
||||
INT_R.SE6BEG2.LVB12 04_43 05_41
|
||||
INT_R.SE6BEG2.NE2END2 03_42 04_40
|
||||
INT_R.SE6BEG2.NE6END2 04_40 04_43
|
||||
INT_R.SE6BEG2.NN2END2 02_43 04_40
|
||||
|
|
@ -2882,8 +2688,6 @@ INT_R.SE6BEG3.LOGIC_OUTS17 06_58 07_59
|
|||
INT_R.SE6BEG3.LOGIC_OUTS21 05_57 07_59
|
||||
INT_R.SE6BEG3.EE2END3 02_58 02_59
|
||||
INT_R.SE6BEG3.EE4END3 02_58 04_59
|
||||
INT_R.SE6BEG3.LH0 04_59 06_58
|
||||
INT_R.SE6BEG3.LV18 04_59 05_57
|
||||
INT_R.SE6BEG3.NE2END3 03_58 04_56
|
||||
INT_R.SE6BEG3.NE6END3 04_56 04_59
|
||||
INT_R.SE6BEG3.NN2END3 02_59 04_56
|
||||
|
|
@ -3122,8 +2926,6 @@ INT_R.SS6BEG0.LOGIC_OUTS18 06_14 07_15
|
|||
INT_R.SS6BEG0.LOGIC_OUTS22 05_13 07_15
|
||||
INT_R.SS6BEG0.EE2END0 02_15 04_12
|
||||
INT_R.SS6BEG0.EE4END0 04_12 04_15
|
||||
INT_R.SS6BEG0.LH12 04_15 05_13
|
||||
INT_R.SS6BEG0.LV0 04_15 06_14
|
||||
INT_R.SS6BEG0.NW2END1 03_14 05_14
|
||||
INT_R.SS6BEG0.NW6END1 05_14 07_15
|
||||
INT_R.SS6BEG0.SE2END0 03_14 04_12
|
||||
|
|
@ -3142,8 +2944,6 @@ INT_R.SS6BEG1.LOGIC_OUTS19 05_29 07_31
|
|||
INT_R.SS6BEG1.LOGIC_OUTS23 06_30 07_31
|
||||
INT_R.SS6BEG1.EE2END1 02_31 04_28
|
||||
INT_R.SS6BEG1.EE4END1 04_28 04_31
|
||||
INT_R.SS6BEG1.LH6 04_31 05_29
|
||||
INT_R.SS6BEG1.LV9 04_31 06_30
|
||||
INT_R.SS6BEG1.NW2END2 03_30 05_30
|
||||
INT_R.SS6BEG1.NW6END2 05_30 07_31
|
||||
INT_R.SS6BEG1.SE2END1 03_30 04_28
|
||||
|
|
@ -3162,8 +2962,6 @@ INT_R.SS6BEG2.LOGIC_OUTS16 06_46 07_47
|
|||
INT_R.SS6BEG2.LOGIC_OUTS20 05_45 07_47
|
||||
INT_R.SS6BEG2.EE2END2 02_47 04_44
|
||||
INT_R.SS6BEG2.EE4END2 04_44 04_47
|
||||
INT_R.SS6BEG2.LVB0 04_47 06_46
|
||||
INT_R.SS6BEG2.LVB12 04_47 05_45
|
||||
INT_R.SS6BEG2.NW2END3 03_46 05_46
|
||||
INT_R.SS6BEG2.NW6END3 05_46 07_47
|
||||
INT_R.SS6BEG2.SE2END2 03_46 04_44
|
||||
|
|
@ -3185,8 +2983,6 @@ INT_R.SS6BEG3.NW6END_S0_0 05_62 07_63
|
|||
INT_R.SS6BEG3.WW4END_S0_0 04_63 05_62
|
||||
INT_R.SS6BEG3.EE2END3 02_63 04_60
|
||||
INT_R.SS6BEG3.EE4END3 04_60 04_63
|
||||
INT_R.SS6BEG3.LH0 04_63 06_62
|
||||
INT_R.SS6BEG3.LV18 04_63 05_61
|
||||
INT_R.SS6BEG3.SE2END3 03_62 04_60
|
||||
INT_R.SS6BEG3.SE6END3 04_60 07_63
|
||||
INT_R.SS6BEG3.SS2END3 02_62 02_63
|
||||
|
|
@ -3282,8 +3078,6 @@ INT_R.SW6BEG0.LOGIC_OUTS18 04_14 06_12
|
|||
INT_R.SW6BEG0.LOGIC_OUTS22 06_12 07_13
|
||||
INT_R.SW6BEG0.EE2END0 03_12 04_13
|
||||
INT_R.SW6BEG0.EE4END0 04_13 05_12
|
||||
INT_R.SW6BEG0.LH12 05_12 07_13
|
||||
INT_R.SW6BEG0.LV0 04_14 05_12
|
||||
INT_R.SW6BEG0.NW2END1 02_13 05_15
|
||||
INT_R.SW6BEG0.NW6END1 05_15 06_12
|
||||
INT_R.SW6BEG0.SE2END0 02_13 04_13
|
||||
|
|
@ -3302,8 +3096,6 @@ INT_R.SW6BEG1.LOGIC_OUTS19 06_28 07_29
|
|||
INT_R.SW6BEG1.LOGIC_OUTS23 04_30 06_28
|
||||
INT_R.SW6BEG1.EE2END1 03_28 04_29
|
||||
INT_R.SW6BEG1.EE4END1 04_29 05_28
|
||||
INT_R.SW6BEG1.LH6 05_28 07_29
|
||||
INT_R.SW6BEG1.LV9 04_30 05_28
|
||||
INT_R.SW6BEG1.NW2END2 02_29 05_31
|
||||
INT_R.SW6BEG1.NW6END2 05_31 06_28
|
||||
INT_R.SW6BEG1.SE2END1 02_29 04_29
|
||||
|
|
@ -3322,8 +3114,6 @@ INT_R.SW6BEG2.LOGIC_OUTS16 04_46 06_44
|
|||
INT_R.SW6BEG2.LOGIC_OUTS20 06_44 07_45
|
||||
INT_R.SW6BEG2.EE2END2 03_44 04_45
|
||||
INT_R.SW6BEG2.EE4END2 04_45 05_44
|
||||
INT_R.SW6BEG2.LVB0 04_46 05_44
|
||||
INT_R.SW6BEG2.LVB12 05_44 07_45
|
||||
INT_R.SW6BEG2.NW2END3 02_45 05_47
|
||||
INT_R.SW6BEG2.NW6END3 05_47 06_44
|
||||
INT_R.SW6BEG2.SE2END2 02_45 04_45
|
||||
|
|
@ -3344,9 +3134,6 @@ INT_R.SW6BEG3.NW2END_S0_0 02_61 05_63
|
|||
INT_R.SW6BEG3.NW6END_S0_0 05_63 06_60
|
||||
INT_R.SW6BEG3.WW4END_S0_0 05_60 05_63
|
||||
INT_R.SW6BEG3.EE2END3 03_60 04_61
|
||||
INT_R.SW6BEG3.EE4END3 04_61 05_60
|
||||
INT_R.SW6BEG3.LH0 04_62 05_60
|
||||
INT_R.SW6BEG3.LV18 05_60 07_61
|
||||
INT_R.SW6BEG3.SE2END3 02_61 04_61
|
||||
INT_R.SW6BEG3.SE6END3 04_61 06_60
|
||||
INT_R.SW6BEG3.SS2END3 03_60 03_61
|
||||
|
|
@ -3565,8 +3352,6 @@ INT_R.WW4BEG0.SS6END_N0_3 04_01 06_00
|
|||
INT_R.WW4BEG0.SW2END_N0_3 02_01 04_01
|
||||
INT_R.WW4BEG0.SW6END_N0_3 04_01 05_00
|
||||
INT_R.WW4BEG0.WW2END_N0_3 03_00 03_01
|
||||
INT_R.WW4BEG0.LH12 05_00 07_01
|
||||
INT_R.WW4BEG0.LV0 04_02 05_00
|
||||
INT_R.WW4BEG0.NE2END0 02_01 05_03
|
||||
INT_R.WW4BEG0.NE6END0 05_00 05_03
|
||||
INT_R.WW4BEG0.NN2END0 03_00 05_03
|
||||
|
|
@ -3580,8 +3365,6 @@ INT_R.WW4BEG1.LOGIC_OUTS9 03_16 04_18
|
|||
INT_R.WW4BEG1.LOGIC_OUTS13 03_16 07_17
|
||||
INT_R.WW4BEG1.LOGIC_OUTS19 04_18 06_16
|
||||
INT_R.WW4BEG1.LOGIC_OUTS23 06_16 07_17
|
||||
INT_R.WW4BEG1.LH6 05_16 07_17
|
||||
INT_R.WW4BEG1.LV9 04_18 05_16
|
||||
INT_R.WW4BEG1.NE2END1 02_17 05_19
|
||||
INT_R.WW4BEG1.NE6END1 05_16 05_19
|
||||
INT_R.WW4BEG1.NN2END1 03_16 05_19
|
||||
|
|
@ -3600,10 +3383,7 @@ INT_R.WW4BEG2.LOGIC_OUTS10 03_32 07_33
|
|||
INT_R.WW4BEG2.LOGIC_OUTS14 03_32 04_34
|
||||
INT_R.WW4BEG2.LOGIC_OUTS16 06_32 07_33
|
||||
INT_R.WW4BEG2.LOGIC_OUTS20 04_34 06_32
|
||||
INT_R.WW4BEG2.LVB0 04_34 05_32
|
||||
INT_R.WW4BEG2.LVB12 05_32 07_33
|
||||
INT_R.WW4BEG2.NE2END2 02_33 05_35
|
||||
INT_R.WW4BEG2.NE6END2 05_32 05_35
|
||||
INT_R.WW4BEG2.NN2END2 03_32 05_35
|
||||
INT_R.WW4BEG2.NN6END2 05_35 06_32
|
||||
INT_R.WW4BEG2.NW2END2 02_33 03_33
|
||||
|
|
@ -3620,10 +3400,7 @@ INT_R.WW4BEG3.LOGIC_OUTS11 03_48 04_50
|
|||
INT_R.WW4BEG3.LOGIC_OUTS15 03_48 07_49
|
||||
INT_R.WW4BEG3.LOGIC_OUTS17 04_50 06_48
|
||||
INT_R.WW4BEG3.LOGIC_OUTS21 06_48 07_49
|
||||
INT_R.WW4BEG3.LH0 04_50 05_48
|
||||
INT_R.WW4BEG3.LV18 05_48 07_49
|
||||
INT_R.WW4BEG3.NE2END3 02_49 05_51
|
||||
INT_R.WW4BEG3.NE6END3 05_48 05_51
|
||||
INT_R.WW4BEG3.NN2END3 03_48 05_51
|
||||
INT_R.WW4BEG3.NN6END3 05_51 06_48
|
||||
INT_R.WW4BEG3.NW2END3 02_49 03_49
|
||||
|
|
|
|||
|
|
@ -7186,7 +7186,7 @@
|
|||
"y_coord": 0
|
||||
},
|
||||
{
|
||||
"name": "X0Y29",
|
||||
"name": "X0Y0",
|
||||
"prefix": "RAMB18",
|
||||
"site_pins": {
|
||||
"ADDRARDADDR0": "BRAM_FIFO18_ADDRARDADDR0",
|
||||
|
|
@ -7350,10 +7350,10 @@
|
|||
},
|
||||
"type": "FIFO18E1",
|
||||
"x_coord": 0,
|
||||
"y_coord": 29
|
||||
"y_coord": 0
|
||||
},
|
||||
{
|
||||
"name": "X0Y30",
|
||||
"name": "X0Y1",
|
||||
"prefix": "RAMB18",
|
||||
"site_pins": {
|
||||
"ADDRARDADDR0": "BRAM_RAMB18_ADDRARDADDR0",
|
||||
|
|
@ -7517,7 +7517,7 @@
|
|||
},
|
||||
"type": "RAMB18E1",
|
||||
"x_coord": 0,
|
||||
"y_coord": 30
|
||||
"y_coord": 1
|
||||
}
|
||||
],
|
||||
"tile_type": "BRAM_L",
|
||||
|
|
|
|||
|
|
@ -6821,7 +6821,7 @@
|
|||
},
|
||||
"sites": [
|
||||
{
|
||||
"name": "X0Y19",
|
||||
"name": "X0Y17",
|
||||
"prefix": "RAMB18",
|
||||
"site_pins": {
|
||||
"ADDRARDADDR0": "BRAM_FIFO18_ADDRARDADDR0",
|
||||
|
|
@ -6985,10 +6985,10 @@
|
|||
},
|
||||
"type": "FIFO18E1",
|
||||
"x_coord": 0,
|
||||
"y_coord": 19
|
||||
"y_coord": 17
|
||||
},
|
||||
{
|
||||
"name": "X0Y20",
|
||||
"name": "X0Y18",
|
||||
"prefix": "RAMB18",
|
||||
"site_pins": {
|
||||
"ADDRARDADDR0": "BRAM_RAMB18_ADDRARDADDR0",
|
||||
|
|
@ -7152,7 +7152,7 @@
|
|||
},
|
||||
"type": "RAMB18E1",
|
||||
"x_coord": 0,
|
||||
"y_coord": 20
|
||||
"y_coord": 18
|
||||
},
|
||||
{
|
||||
"name": "X0Y0",
|
||||
|
|
|
|||
|
|
@ -2856,7 +2856,7 @@
|
|||
"y_coord": 0
|
||||
},
|
||||
{
|
||||
"name": "X0Y8",
|
||||
"name": "X0Y5",
|
||||
"prefix": "PHASER_OUT_PHY",
|
||||
"site_pins": {
|
||||
"BURSTPENDING": "CMT_PHASER_OUT_CA_BURSTPENDING",
|
||||
|
|
@ -2939,10 +2939,10 @@
|
|||
},
|
||||
"type": "PHASER_OUT_PHY",
|
||||
"x_coord": 0,
|
||||
"y_coord": 8
|
||||
"y_coord": 5
|
||||
},
|
||||
{
|
||||
"name": "X0Y8",
|
||||
"name": "X0Y5",
|
||||
"prefix": "PHASER_IN_PHY",
|
||||
"site_pins": {
|
||||
"BURSTPENDING": "CMT_PHASER_IN_CA_BURSTPENDING",
|
||||
|
|
@ -3040,10 +3040,10 @@
|
|||
},
|
||||
"type": "PHASER_IN_PHY",
|
||||
"x_coord": 0,
|
||||
"y_coord": 8
|
||||
"y_coord": 5
|
||||
},
|
||||
{
|
||||
"name": "X0Y9",
|
||||
"name": "X0Y6",
|
||||
"prefix": "PHASER_OUT_PHY",
|
||||
"site_pins": {
|
||||
"BURSTPENDING": "CMT_PHASER_OUT_DB_BURSTPENDING",
|
||||
|
|
@ -3126,10 +3126,10 @@
|
|||
},
|
||||
"type": "PHASER_OUT_PHY",
|
||||
"x_coord": 0,
|
||||
"y_coord": 9
|
||||
"y_coord": 6
|
||||
},
|
||||
{
|
||||
"name": "X0Y9",
|
||||
"name": "X0Y6",
|
||||
"prefix": "PHASER_IN_PHY",
|
||||
"site_pins": {
|
||||
"BURSTPENDING": "CMT_PHASER_IN_DB_BURSTPENDING",
|
||||
|
|
@ -3227,7 +3227,7 @@
|
|||
},
|
||||
"type": "PHASER_IN_PHY",
|
||||
"x_coord": 0,
|
||||
"y_coord": 9
|
||||
"y_coord": 6
|
||||
}
|
||||
],
|
||||
"tile_type": "CMT_TOP_R_UPPER_B",
|
||||
|
|
|
|||
|
|
@ -6413,7 +6413,7 @@
|
|||
"y_coord": 1
|
||||
},
|
||||
{
|
||||
"name": "X34Y87",
|
||||
"name": "X34Y0",
|
||||
"prefix": "TIEOFF",
|
||||
"site_pins": {
|
||||
"HARD0": "DSP_GND_L",
|
||||
|
|
@ -6421,7 +6421,7 @@
|
|||
},
|
||||
"type": "TIEOFF",
|
||||
"x_coord": 34,
|
||||
"y_coord": 87
|
||||
"y_coord": 0
|
||||
}
|
||||
],
|
||||
"tile_type": "DSP_L",
|
||||
|
|
|
|||
|
|
@ -6413,7 +6413,7 @@
|
|||
"y_coord": 1
|
||||
},
|
||||
{
|
||||
"name": "X10Y87",
|
||||
"name": "X10Y39",
|
||||
"prefix": "TIEOFF",
|
||||
"site_pins": {
|
||||
"HARD0": "DSP_GND_R",
|
||||
|
|
@ -6421,7 +6421,7 @@
|
|||
},
|
||||
"type": "TIEOFF",
|
||||
"x_coord": 10,
|
||||
"y_coord": 87
|
||||
"y_coord": 39
|
||||
}
|
||||
],
|
||||
"tile_type": "DSP_R",
|
||||
|
|
|
|||
82485
artix7/tilegrid.json
82485
artix7/tilegrid.json
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue