diff --git a/Info.md b/Info.md index fff47f0..222d9bd 100644 --- a/Info.md +++ b/Info.md @@ -37,20 +37,20 @@ These files are released under the very permissive [CC0 1.0 Universal](COPYING). # Details -Last updated on Thu 25 Feb 2021 06:48:02 PM UTC (2021-02-25T18:48:02+00:00). +Last updated on Thu 11 Mar 2021 07:29:56 PM UTC (2021-03-11T19:29:56+00:00). -Created using [Project X-Ray](https://github.com/SymbiFlow/prjxray) version [6867429c](https://github.com/SymbiFlow/prjxray/commit/6867429cc3a4ce422b06ceda100b868a0a7f8b23). +Created using [Project X-Ray](https://github.com/SymbiFlow/prjxray) version [0d9418a9](https://github.com/SymbiFlow/prjxray/commit/0d9418a908dafecae1d38418d3a0e2d2b2416ea0). Latest commit was; ``` -commit 6867429cc3a4ce422b06ceda100b868a0a7f8b23 -Merge: 45abab75 9b4f4551 +commit 0d9418a908dafecae1d38418d3a0e2d2b2416ea0 +Merge: 0ddf03b8 2ccada20 Author: litghost <537074+litghost@users.noreply.github.com> -Date: Wed Feb 24 08:23:12 2021 -0800 +Date: Wed Mar 10 09:07:49 2021 -0800 - Merge pull request #1592 from antmicro/fix-iob-lvds-tmds + Merge pull request #1614 from antmicro/add-gtp-ports-attrs-file - 030-iob: improve rdb processing for LVDS and TMDS + gtp: generate attributes and ports files to add to the db ``` @@ -59,7 +59,7 @@ Date: Wed Feb 24 08:23:12 2021 -0800 ### Settings -Created using following [settings/artix7.sh (sha256: 00d45bf1672d3460e8d452cda8e747fa713eed629aa086b219162886452013e4)](https://github.com/SymbiFlow/prjxray/blob/6867429cc3a4ce422b06ceda100b868a0a7f8b23/settings/artix7.sh) +Created using following [settings/artix7.sh (sha256: 00d45bf1672d3460e8d452cda8e747fa713eed629aa086b219162886452013e4)](https://github.com/SymbiFlow/prjxray/blob/0d9418a908dafecae1d38418d3a0e2d2b2416ea0/settings/artix7.sh) ```shell #!/bin/bash # Copyright (C) 2017-2020 The Project X-Ray Authors. @@ -104,24 +104,28 @@ eval $(python3 ${XRAY_UTILS_DIR}/create_environment.py) Results have checksums; + * [`efcb8d5580edebfd8a6aa1d742c65cfd96f5544a855e4956e790fcee2568d30a ./artix7/cells_data/gtpe2_channel_attrs.json`](./artix7/cells_data/gtpe2_channel_attrs.json) + * [`962b9db76b9e6333b72880fc196a492756f4f5d37dae2fe727c7f6fb6db8e834 ./artix7/cells_data/gtpe2_channel_ports.json`](./artix7/cells_data/gtpe2_channel_ports.json) + * [`0928d105dc294cedc1f19bf61790f81f5adee62f03fcfe4a4d220546d99a2b40 ./artix7/cells_data/gtpe2_common_attrs.json`](./artix7/cells_data/gtpe2_common_attrs.json) + * [`b6c8fbd663d4c7410909f3b7cb0a473d82343e3240810a27e4323ac6220abeb5 ./artix7/cells_data/gtpe2_common_ports.json`](./artix7/cells_data/gtpe2_common_ports.json) * [`d7c598657e5d66095a732b74bfa559253fba959bf53706cfd464635f07ae6b9b ./artix7/element_counts.csv`](./artix7/element_counts.csv) * [`b5a8a5e4aa788f9a8b17a0b0879814d9e8f38f6cbb65740fb537935fb028296a ./artix7/gridinfo/grid-xc7a50tfgg484-1-db.txt`](./artix7/gridinfo/grid-xc7a50tfgg484-1-db.txt) * [`2b18b3806f0e58024469eac1fe11749d04c6b035d2c2eafa7d2f30bf57173fa9 ./artix7/harness/README.md`](./artix7/harness/README.md) * [`560f255b569fd4798989f45104d4a511b51380418d4ca6fc53201141b36b20aa ./artix7/harness/arty-a7/pmod/design.bit`](./artix7/harness/arty-a7/pmod/design.bit) * [`1d8a121c3aa3bca7893429cfb08a8748206134271432daa52cdc9d3f5593bda0 ./artix7/harness/arty-a7/pmod/design.dcp`](./artix7/harness/arty-a7/pmod/design.dcp) - * [`b57ed4b48e47f3bc75e9a95dd15bc40082d3bbb35883a646d98c1ed60402713c ./artix7/harness/arty-a7/pmod/design.json`](./artix7/harness/arty-a7/pmod/design.json) + * [`f1f528bdfd394f9d11a8fe98e42e4ad67b5b11f96cd49f31f8b61b1de8c585c0 ./artix7/harness/arty-a7/pmod/design.json`](./artix7/harness/arty-a7/pmod/design.json) * [`fb90ad5fe10750f33d5802e1409ebc2406f7b0adab4bf6ef12b53c0e100b43ea ./artix7/harness/arty-a7/pmod/design.txt`](./artix7/harness/arty-a7/pmod/design.txt) * [`931c1598b75005a8a8e5b2225cc7454c2c7be451cb907bc4c047cb04db99772d ./artix7/harness/arty-a7/swbut/design.bit`](./artix7/harness/arty-a7/swbut/design.bit) * [`5d06132c788097344a9bca7040a08dd0e1632e177ed8def1d7445132020cc768 ./artix7/harness/arty-a7/swbut/design.dcp`](./artix7/harness/arty-a7/swbut/design.dcp) - * [`ff29541f33458d2912cc630f03df7ee959246bb783c5840cddea32b42746b52f ./artix7/harness/arty-a7/swbut/design.json`](./artix7/harness/arty-a7/swbut/design.json) + * [`83549af508a4004ebd53f71249c7e11db7af9c2d603f91bbaafcffe9dd824b9a ./artix7/harness/arty-a7/swbut/design.json`](./artix7/harness/arty-a7/swbut/design.json) * [`884af447661ff1cb653cd8280602c2348435366b35bf2627e2221af34899d191 ./artix7/harness/arty-a7/swbut/design.txt`](./artix7/harness/arty-a7/swbut/design.txt) * [`128e73ee026cf2238a35c7e993b845e3551919c90fc77b277635bc5098d59741 ./artix7/harness/arty-a7/uart/design.bit`](./artix7/harness/arty-a7/uart/design.bit) * [`955daed70c5728c13865eddc9bd7001d93183a50c560559a7b6628aa85b1fbbe ./artix7/harness/arty-a7/uart/design.dcp`](./artix7/harness/arty-a7/uart/design.dcp) - * [`b902e72932a9039258a0e469a0499e5621adc1e797e6b201290d05a9313ac3cd ./artix7/harness/arty-a7/uart/design.json`](./artix7/harness/arty-a7/uart/design.json) + * [`a0e37fee3200d72d04ff92c60a840a406f053de4c3d1c779d4ffbcd1823bf47f ./artix7/harness/arty-a7/uart/design.json`](./artix7/harness/arty-a7/uart/design.json) * [`0583aa7502ee7a0303510c524f5500d8e1b9598aa26016d3d0e4e9623bf8ab8d ./artix7/harness/arty-a7/uart/design.txt`](./artix7/harness/arty-a7/uart/design.txt) * [`d3109010f8fced3be08e720741a157d08b7042359e84d04bbe677f50cbf10a04 ./artix7/harness/basys3/swbut/design.bit`](./artix7/harness/basys3/swbut/design.bit) * [`abedfa7f2ee5a4dbc51b582ebae62dd20489f745a4a239e49b18ba3e02be019f ./artix7/harness/basys3/swbut/design.dcp`](./artix7/harness/basys3/swbut/design.dcp) - * [`a63c62d553aa5811bf3d98c82d998733bf27e28c57328c08e7329f5dd980b9c2 ./artix7/harness/basys3/swbut/design.json`](./artix7/harness/basys3/swbut/design.json) + * [`ada2b826fc1b0c687ab4194f95b025460db0fbad8fe24a69ed600b1983b51ea8 ./artix7/harness/basys3/swbut/design.json`](./artix7/harness/basys3/swbut/design.json) * [`9df8eac3c11e57d81b4bf4a927ade787f881f0ef46c8ab610ca529f35e887689 ./artix7/harness/basys3/swbut/design.txt`](./artix7/harness/basys3/swbut/design.txt) * [`e5ebd51966bcfddb9b04078203231810df64f5afd3e3a608a5fb8fdc7d3c3304 ./artix7/mapping/devices.yaml`](./artix7/mapping/devices.yaml) * [`9a63d519dcfee4016602553490a53c00a2fbc8cd0355ed201cfa3545650f6ce4 ./artix7/mapping/parts.yaml`](./artix7/mapping/parts.yaml) @@ -213,22 +217,24 @@ Results have checksums; * [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./artix7/ppips_dsp_l.origin_info.db`](./artix7/ppips_dsp_l.origin_info.db) * [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./artix7/ppips_dsp_r.db`](./artix7/ppips_dsp_r.db) * [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./artix7/ppips_dsp_r.origin_info.db`](./artix7/ppips_dsp_r.origin_info.db) - * [`9a41911dfa0be59fced626ba228abf9ef7cf020affbd2743a26ed16b6856dfd5 ./artix7/ppips_gtp_channel_0.db`](./artix7/ppips_gtp_channel_0.db) - * [`4179cf95c0e079b2bf699e944e3059470147c60de6cfcdda9bd70c907f6851df ./artix7/ppips_gtp_channel_0_mid_left.db`](./artix7/ppips_gtp_channel_0_mid_left.db) - * [`3550a2e77580e0f8385418efd0beea4d6fe2f7e21544da921116459589e58a9a ./artix7/ppips_gtp_channel_0_mid_right.db`](./artix7/ppips_gtp_channel_0_mid_right.db) - * [`42449df4353f2fc1764ee337f0e18afb0d4b419e611eda5ea7282180587c118b ./artix7/ppips_gtp_channel_1.db`](./artix7/ppips_gtp_channel_1.db) - * [`663a27fa99c2e337e961d6636bf41d57e4bbade7ba31af82623280f40ecc54f7 ./artix7/ppips_gtp_channel_1_mid_left.db`](./artix7/ppips_gtp_channel_1_mid_left.db) - * [`5502dc8909a39565bb584df2e702c9d5aada1ab7b520fa01366eb1e07e9521ca ./artix7/ppips_gtp_channel_1_mid_right.db`](./artix7/ppips_gtp_channel_1_mid_right.db) - * [`b14787fc826a3c64160af864346775ca1e387a08f23679a72c9e4fa11a436b40 ./artix7/ppips_gtp_channel_2.db`](./artix7/ppips_gtp_channel_2.db) - * [`21df745b5828962164f7d7b54df58bb308a2083f8863d5be10e870367f34a1f4 ./artix7/ppips_gtp_channel_2_mid_left.db`](./artix7/ppips_gtp_channel_2_mid_left.db) - * [`993c198a976dd0ffe90592296923210480aec35a3f259295c3486a783390d892 ./artix7/ppips_gtp_channel_2_mid_right.db`](./artix7/ppips_gtp_channel_2_mid_right.db) - * [`229584a094cadcf181cc7c9b04a0c151ad9fc0b230cccc761b33beb7109156ed ./artix7/ppips_gtp_channel_3.db`](./artix7/ppips_gtp_channel_3.db) - * [`df7fe61346d9a21e1b69ba2a045b8da6f6efa4a0d1dfab29f86577475d7b7cc3 ./artix7/ppips_gtp_channel_3_mid_left.db`](./artix7/ppips_gtp_channel_3_mid_left.db) - * [`565286894f6c314d07809888b3c17279f8784bc38dfe59ee16d3b7874ba770f8 ./artix7/ppips_gtp_channel_3_mid_right.db`](./artix7/ppips_gtp_channel_3_mid_right.db) - * [`e5b17573f36b84838c40a76bdf9015fd89bd860bb2dde3a0da80061248bcd17a ./artix7/ppips_gtp_common.db`](./artix7/ppips_gtp_common.db) - * [`afe293d42525ca4fb85e4fc795d841f9d71ac0d3be85b3d5b1c6011834492348 ./artix7/ppips_gtp_common_mid_left.db`](./artix7/ppips_gtp_common_mid_left.db) - * [`6bb1ed0b882bd46476fdc425721b67096282828cc9a7adc22176a634e1253820 ./artix7/ppips_gtp_common_mid_right.db`](./artix7/ppips_gtp_common_mid_right.db) - * [`35dd7280544b90f1de8b8d02b952a2e3180e734653c5a9889dbac3854d887cd3 ./artix7/ppips_gtp_int_interface.db`](./artix7/ppips_gtp_int_interface.db) + * [`cec8e43d2eb67f3eb1d45e1393b8c9809a46e9b82d619e0fa8d421acf65bbd85 ./artix7/ppips_gtp_channel_0.db`](./artix7/ppips_gtp_channel_0.db) + * [`9502d2635bb01f9823a7ff473acce052f97903abefc87230ed29dacb22a93537 ./artix7/ppips_gtp_channel_0_mid_left.db`](./artix7/ppips_gtp_channel_0_mid_left.db) + * [`bd881f11a46fe69af9ab4a84c14c4670c4c274098c2e3d77407639f4e4e8e1eb ./artix7/ppips_gtp_channel_0_mid_right.db`](./artix7/ppips_gtp_channel_0_mid_right.db) + * [`c2ecc077a70e4a077e2b25c1fcc9e4459c635806f378f21f52e20411c90ac04e ./artix7/ppips_gtp_channel_1.db`](./artix7/ppips_gtp_channel_1.db) + * [`653cb2b169ba9abfdc9b74723b67fc9170fd7efea8b7cd5579688f43abeca166 ./artix7/ppips_gtp_channel_1_mid_left.db`](./artix7/ppips_gtp_channel_1_mid_left.db) + * [`518b48f277454295222baba2f7bc46e321630cd2923ad0f25a7de7a2ce0cd8f5 ./artix7/ppips_gtp_channel_1_mid_right.db`](./artix7/ppips_gtp_channel_1_mid_right.db) + * [`793af5ec6f50d440dd5df9739cdad49967adcf0b8f6db656143b703663b0cb4c ./artix7/ppips_gtp_channel_2.db`](./artix7/ppips_gtp_channel_2.db) + * [`e283c878a932cbf9f0af41fa7f220572393cddccaa7a4bfcd098b4e1e8729043 ./artix7/ppips_gtp_channel_2_mid_left.db`](./artix7/ppips_gtp_channel_2_mid_left.db) + * [`450fec8a8618320e905433639af7d55571e557bba586d8ecf5bed611f5876bd4 ./artix7/ppips_gtp_channel_2_mid_right.db`](./artix7/ppips_gtp_channel_2_mid_right.db) + * [`8760eedb9df37a5b1c9116830426af90ca3eb7b1b57b88bafe5462d4feea55b4 ./artix7/ppips_gtp_channel_3.db`](./artix7/ppips_gtp_channel_3.db) + * [`aac1994d80f9d596b442f6c12f0274e36af75dea23c150fd894d4119201df6ee ./artix7/ppips_gtp_channel_3_mid_left.db`](./artix7/ppips_gtp_channel_3_mid_left.db) + * [`3cfedd95d7c8892abfb4e00004f96019494755de7880b47a13053c3978285af5 ./artix7/ppips_gtp_channel_3_mid_right.db`](./artix7/ppips_gtp_channel_3_mid_right.db) + * [`8fed1b3aea95f60e6f03c8f59aed1e0b57b55f8ae03c725cd4c2cf6dbe627332 ./artix7/ppips_gtp_common.db`](./artix7/ppips_gtp_common.db) + * [`875523212b092efe2cb4dcf2a8113bee0612b1a90346b288cac7f350ca7ba976 ./artix7/ppips_gtp_common_mid_left.db`](./artix7/ppips_gtp_common_mid_left.db) + * [`53e657437795033a555a247c3011fecaef3f54e369a106df276d80d383394f1e ./artix7/ppips_gtp_common_mid_right.db`](./artix7/ppips_gtp_common_mid_right.db) + * [`40aa7466e006edc7e2b4265c74455ea6bcc8ddcabeb25535865962a360d0d9e9 ./artix7/ppips_gtp_int_interface.db`](./artix7/ppips_gtp_int_interface.db) + * [`25b73299c2c7ef8e4edc6bece4530b5c550a90db1e46892dad942ffec05b019e ./artix7/ppips_gtp_int_interface_l.db`](./artix7/ppips_gtp_int_interface_l.db) + * [`7066eaf79cfebffff26f86e85c2fb759c991f1440c5e786d1bf97148a977c58a ./artix7/ppips_gtp_int_interface_r.db`](./artix7/ppips_gtp_int_interface_r.db) * [`edeccdbee739f85558baee09f68ebee6cca1f2121b1ef7e38839e8a9f0797641 ./artix7/ppips_hclk_cmt.db`](./artix7/ppips_hclk_cmt.db) * [`633e6ad608c7b7fc6b5d863812fea75fd0162bf6d58dd6794e6d3f32100ec2a3 ./artix7/ppips_hclk_ioi3.db`](./artix7/ppips_hclk_ioi3.db) * [`b61bbc9db6d0de1141a87d787f5d118be0a244802eed712612ff2aa0b6aeb73a ./artix7/ppips_hclk_l.db`](./artix7/ppips_hclk_l.db) @@ -247,6 +253,10 @@ Results have checksums; * [`f87e449ccf9c605acad950269bfe104bc3a45daf79c5b7fe21042169feb7a428 ./artix7/ppips_lioi3_sing.db`](./artix7/ppips_lioi3_sing.db) * [`1046256199fd3c54a5f3ee7e5ec7fd72863882e01cc8da326e487c763159e2f8 ./artix7/ppips_lioi3_tbytesrc.db`](./artix7/ppips_lioi3_tbytesrc.db) * [`b6255a5ec971695a0aadd4901f2021d839c20b9cff781b2fccc8f5e779295319 ./artix7/ppips_lioi3_tbyteterm.db`](./artix7/ppips_lioi3_tbyteterm.db) + * [`48ad9ebcaa48a039f5bcc9f6d5b4736be64976434ad79bc317e88c4f40b980aa ./artix7/ppips_pcie_bot.db`](./artix7/ppips_pcie_bot.db) + * [`38b7dd3cf1ef560f06933b501059b4d029e1625193038eba112424f9bff630c5 ./artix7/ppips_pcie_int_interface_l.db`](./artix7/ppips_pcie_int_interface_l.db) + * [`e998a9cc7b3ea7f185485133a97510a9ec73dfec574f3b8583eb968073f6a7d5 ./artix7/ppips_pcie_int_interface_r.db`](./artix7/ppips_pcie_int_interface_r.db) + * [`5684a64e33378f61f7b92cee7011c2fc4f85be16762919a86103dc8652c73d63 ./artix7/ppips_pcie_top.db`](./artix7/ppips_pcie_top.db) * [`5c818ae170303c8f215cb08e33f6682eb18e4c1b142da8c86e209d80199f6512 ./artix7/ppips_rioi3.db`](./artix7/ppips_rioi3.db) * [`bb65252c9f425d9b6eee636057f458b5b7548ee47228127f29afe0e7e5878682 ./artix7/ppips_rioi3_sing.db`](./artix7/ppips_rioi3_sing.db) * [`fe8fe52b167f239f3d28ffc0c1f4dd35de5ad2572526ad79500ac2cf89a5dfb2 ./artix7/ppips_rioi3_tbytesrc.db`](./artix7/ppips_rioi3_tbytesrc.db) @@ -279,48 +289,48 @@ Results have checksums; * [`cf71a4438ae35cb2493b614e895e3d5cf577613a8d9c10cf1c566872a2ea9b4f ./artix7/segbits_clk_hrow_bot_r.origin_info.db`](./artix7/segbits_clk_hrow_bot_r.origin_info.db) * [`8ab24467b7f56fa8ff0dd334c0588cb196a4d875895abb48afcd33e1e2ba1deb ./artix7/segbits_clk_hrow_top_r.db`](./artix7/segbits_clk_hrow_top_r.db) * [`cf14bb07343da1aede131d701579bcda71a147da4d8cbefa85e8017f2c54225d ./artix7/segbits_clk_hrow_top_r.origin_info.db`](./artix7/segbits_clk_hrow_top_r.origin_info.db) - * [`311bd38ca939dc8643afb130f77c3642f3a89c902634cfa5a06f29c3fb26e9f3 ./artix7/segbits_cmt_top_l_lower_b.db`](./artix7/segbits_cmt_top_l_lower_b.db) - * [`5e5166ef8643919dac09df0f904d212ff72b5c633152e16f7c89c2e650b3ac2b ./artix7/segbits_cmt_top_l_lower_b.origin_info.db`](./artix7/segbits_cmt_top_l_lower_b.origin_info.db) - * [`8c385232c1123d062d161054aca2c0089c9f3d89dac37f2fe35cbf18a2bc10a3 ./artix7/segbits_cmt_top_l_upper_t.db`](./artix7/segbits_cmt_top_l_upper_t.db) - * [`79e0d3fbf25cee9b675e356ad190b75e7063ded499a0a6155cc6bded3a36046a ./artix7/segbits_cmt_top_l_upper_t.origin_info.db`](./artix7/segbits_cmt_top_l_upper_t.origin_info.db) - * [`8cd75b06942f3fefe474eb10ab4522043d5a52a2ee79c4555a7c89d1d6d11ecb ./artix7/segbits_cmt_top_r_lower_b.db`](./artix7/segbits_cmt_top_r_lower_b.db) - * [`0a36013e20bc01d66d1a73eb2594e67d57898efddeb8de046ebcf65eed259c27 ./artix7/segbits_cmt_top_r_lower_b.origin_info.db`](./artix7/segbits_cmt_top_r_lower_b.origin_info.db) - * [`05dd5d01374a8b40883444d33ea467e5e4363fc329e89402ee9618bde4d6752b ./artix7/segbits_cmt_top_r_upper_t.db`](./artix7/segbits_cmt_top_r_upper_t.db) - * [`1117a583fc1c9265aa6dcea7d32f363dd2c5ebe0e657f3a242c5fb0ceb8555fc ./artix7/segbits_cmt_top_r_upper_t.origin_info.db`](./artix7/segbits_cmt_top_r_upper_t.origin_info.db) + * [`f67fcf1a6891fbc8a81f8c26403fe901e055b24e070277c5512a344635285bc2 ./artix7/segbits_cmt_top_l_lower_b.db`](./artix7/segbits_cmt_top_l_lower_b.db) + * [`dde4d2632c4fbf25cbab1891bbbc4355b63bde78c3f3646949238ffe60df11bb ./artix7/segbits_cmt_top_l_lower_b.origin_info.db`](./artix7/segbits_cmt_top_l_lower_b.origin_info.db) + * [`310d60fbc6081e27d8a6e06d659870acf9480ca28884813d804b5a2db26037ac ./artix7/segbits_cmt_top_l_upper_t.db`](./artix7/segbits_cmt_top_l_upper_t.db) + * [`eb47f86d4be61c185bb3f390d742a99ea9e4577d6ffa225c2c0f4835b4f8a920 ./artix7/segbits_cmt_top_l_upper_t.origin_info.db`](./artix7/segbits_cmt_top_l_upper_t.origin_info.db) + * [`4a350d31eb78785fbd6b65044c02d623d6f787606c31a2f01a2efaf9cc2daad7 ./artix7/segbits_cmt_top_r_lower_b.db`](./artix7/segbits_cmt_top_r_lower_b.db) + * [`e712f48558e63ca7b078df3c357344b7977797a47b560f6b65bc953cfc93b815 ./artix7/segbits_cmt_top_r_lower_b.origin_info.db`](./artix7/segbits_cmt_top_r_lower_b.origin_info.db) + * [`6be3a84f654fa195720e2bde7e227711f9798afc48ec680cca57dd0810871cb9 ./artix7/segbits_cmt_top_r_upper_t.db`](./artix7/segbits_cmt_top_r_upper_t.db) + * [`882c5ed49538c83baed0003b8e3108e3c69d5324866c0566ce9f9160b5293f3f ./artix7/segbits_cmt_top_r_upper_t.origin_info.db`](./artix7/segbits_cmt_top_r_upper_t.origin_info.db) * [`81e0623ff13a253e3f9303de3d5dfbcf2fc92cf5cba277bd7de69e70c3c527e3 ./artix7/segbits_dsp_l.db`](./artix7/segbits_dsp_l.db) * [`18cfd5dd8f59ca704cabeeddb2365486c755185b16a41714cc18ad08818c4f62 ./artix7/segbits_dsp_l.origin_info.db`](./artix7/segbits_dsp_l.origin_info.db) * [`5297906aaafefd3be356682dc03cc4f8c85d0ec238a7d66bafc8b1b50a6c0c96 ./artix7/segbits_dsp_r.db`](./artix7/segbits_dsp_r.db) * [`1f6d942f652416b24c7cdae7188144cc9a0778fc439d6e9f22ecec5d7833a391 ./artix7/segbits_dsp_r.origin_info.db`](./artix7/segbits_dsp_r.origin_info.db) - * [`43e958853f10cd658ae0af26f78469bdac9b2bd1abb5dbee83f4e9dfad40eaeb ./artix7/segbits_gtp_channel_0.db`](./artix7/segbits_gtp_channel_0.db) - * [`23f87065aec5f4f22dd0c3c0b5e73a50e13e28b3c494f07becf435f219030b30 ./artix7/segbits_gtp_channel_0.origin_info.db`](./artix7/segbits_gtp_channel_0.origin_info.db) - * [`fffd49cbef2952247233e2128b2752bf28f91f05e194495c6b044d125902191e ./artix7/segbits_gtp_channel_0_mid_left.db`](./artix7/segbits_gtp_channel_0_mid_left.db) - * [`3c51cce7195efee2655f0d8bdddbcebd9f7424fc531958a503ce700a209833f4 ./artix7/segbits_gtp_channel_0_mid_left.origin_info.db`](./artix7/segbits_gtp_channel_0_mid_left.origin_info.db) - * [`cf590acfaf96e259c464dd05b6d9728724941aff4926bf8bd57794c07c6931b7 ./artix7/segbits_gtp_channel_0_mid_right.db`](./artix7/segbits_gtp_channel_0_mid_right.db) - * [`a9c772ded5981040e503509abde4e9dc48619655c4dc75eb6950ca7641a70af3 ./artix7/segbits_gtp_channel_0_mid_right.origin_info.db`](./artix7/segbits_gtp_channel_0_mid_right.origin_info.db) - * [`ed22f29d7ea7180e50160b86da8c10e081ed9c3c399b7ff5b11f5e3c272d11a3 ./artix7/segbits_gtp_channel_1.db`](./artix7/segbits_gtp_channel_1.db) - * [`4c212e5ad3ac869e0b8e9927a97f32b75d5f5b166eb4a37af83738cb4ea2e95d ./artix7/segbits_gtp_channel_1.origin_info.db`](./artix7/segbits_gtp_channel_1.origin_info.db) - * [`efc28e01454541111a2517802814f6afd6c8d6f44d9ed9bbd79923e547cd2668 ./artix7/segbits_gtp_channel_1_mid_left.db`](./artix7/segbits_gtp_channel_1_mid_left.db) - * [`e3ff98c549a159a928e34d7bccca8a5c513401019d0f2c3f476f56322db4bd3e ./artix7/segbits_gtp_channel_1_mid_left.origin_info.db`](./artix7/segbits_gtp_channel_1_mid_left.origin_info.db) - * [`0d004b9755465b0d0c937f06d8ee3cfe83b6651810f766e8d2e63fbbccb6cab3 ./artix7/segbits_gtp_channel_1_mid_right.db`](./artix7/segbits_gtp_channel_1_mid_right.db) - * [`f15d88b953d32c73fbebe87a72bbae9a89b7e9f1e8fb53c45898a08f8c390dbc ./artix7/segbits_gtp_channel_1_mid_right.origin_info.db`](./artix7/segbits_gtp_channel_1_mid_right.origin_info.db) - * [`9a689135198dfacb307687415b086aef5a49e69eb39e331b6238e802907e3088 ./artix7/segbits_gtp_channel_2.db`](./artix7/segbits_gtp_channel_2.db) - * [`f5801a6809eb80627a630a988bc319d65e6b2fa2e56b2d612f07d98060cf6105 ./artix7/segbits_gtp_channel_2.origin_info.db`](./artix7/segbits_gtp_channel_2.origin_info.db) - * [`697dda8e24472fdfc92a94a31f9b6abac78e41b25fcb46303db9cef0016778f5 ./artix7/segbits_gtp_channel_2_mid_left.db`](./artix7/segbits_gtp_channel_2_mid_left.db) - * [`2fa375cc1c9b59a885e4c42764ac7fe816ec550df1dd694dbe55550e9ac495f5 ./artix7/segbits_gtp_channel_2_mid_left.origin_info.db`](./artix7/segbits_gtp_channel_2_mid_left.origin_info.db) - * [`e4eaec32de51c26916143be6fb83d005652b2dbdc82083f6dbfd6837dd8e6a46 ./artix7/segbits_gtp_channel_2_mid_right.db`](./artix7/segbits_gtp_channel_2_mid_right.db) - * [`d5bcd83a26fcc62bda3d7dffc5e54813fca2098c1a6c2294300f94c5f20b86ee ./artix7/segbits_gtp_channel_2_mid_right.origin_info.db`](./artix7/segbits_gtp_channel_2_mid_right.origin_info.db) - * [`7e13681d1a2435db935e800c9e8db3e17e1922c167cf470dc2172af733bc95ef ./artix7/segbits_gtp_channel_3.db`](./artix7/segbits_gtp_channel_3.db) - * [`2b7728a26ab3a151e08f27cfa88582d661fc96900c227d5ab6ab6a4ff362e358 ./artix7/segbits_gtp_channel_3.origin_info.db`](./artix7/segbits_gtp_channel_3.origin_info.db) - * [`2d8634163b632d2030104a8c090e0dd935cdd5afd78b7491d3bfd83e1e81887d ./artix7/segbits_gtp_channel_3_mid_left.db`](./artix7/segbits_gtp_channel_3_mid_left.db) - * [`290ca89106b61311978f9b7a9650fddb4dd5fb2b249612f66abdbe5a0a102f75 ./artix7/segbits_gtp_channel_3_mid_left.origin_info.db`](./artix7/segbits_gtp_channel_3_mid_left.origin_info.db) - * [`4cda734eeec2bfdcd7eab62628b5577277f820aae7ba01c85fa7dbe2389ada1d ./artix7/segbits_gtp_channel_3_mid_right.db`](./artix7/segbits_gtp_channel_3_mid_right.db) - * [`e8357be2f52886f7160aafa6495791ab890808f99a1e396077e17c30e49e6700 ./artix7/segbits_gtp_channel_3_mid_right.origin_info.db`](./artix7/segbits_gtp_channel_3_mid_right.origin_info.db) - * [`ea2df8227b92dbceb1073077f6453b6eb22eb6add9f330b93490915afd74ac2b ./artix7/segbits_gtp_common.db`](./artix7/segbits_gtp_common.db) - * [`1d1399b298c426c6e15ffb7c75ee1fa9887d3de1210e17a046022ffff4d45287 ./artix7/segbits_gtp_common.origin_info.db`](./artix7/segbits_gtp_common.origin_info.db) - * [`37afc4aaffef82bc42052353e4a68a483be81cc4b08e0847b4627a395fad6a24 ./artix7/segbits_gtp_common_mid_left.db`](./artix7/segbits_gtp_common_mid_left.db) - * [`c792735501a19ea5ffb9808844d8875c21f234e653ed51a33e8fb9c777b4f9ef ./artix7/segbits_gtp_common_mid_left.origin_info.db`](./artix7/segbits_gtp_common_mid_left.origin_info.db) - * [`1207c6985578749fe921840fe35187fd9043733059b463616ca9f8c189c6f81b ./artix7/segbits_gtp_common_mid_right.db`](./artix7/segbits_gtp_common_mid_right.db) - * [`2f4d78754b65f558fb7ec8c89641312ba45e68d434529885be26696204de066b ./artix7/segbits_gtp_common_mid_right.origin_info.db`](./artix7/segbits_gtp_common_mid_right.origin_info.db) + * [`a7a14326fcc4070e63a7586fc841eb8526c8eb4dc8d186cd9e8037f23350d546 ./artix7/segbits_gtp_channel_0.db`](./artix7/segbits_gtp_channel_0.db) + * [`91bafb14948c2a35dc049b415bd16c8cbc88fe7985538984f401f42d5d708970 ./artix7/segbits_gtp_channel_0.origin_info.db`](./artix7/segbits_gtp_channel_0.origin_info.db) + * [`e411594c01c7b33b332a9fd223cd7eceb4ef4e1473edede5cb6969609c0ff7f7 ./artix7/segbits_gtp_channel_0_mid_left.db`](./artix7/segbits_gtp_channel_0_mid_left.db) + * [`834de3b40c70aad66d37510e63e4f5a8a7ec50b89eb690333608dc56586986a3 ./artix7/segbits_gtp_channel_0_mid_left.origin_info.db`](./artix7/segbits_gtp_channel_0_mid_left.origin_info.db) + * [`aff9007b8c44a3a3549d7862057795f61f09be525befc258266343cdae056eb4 ./artix7/segbits_gtp_channel_0_mid_right.db`](./artix7/segbits_gtp_channel_0_mid_right.db) + * [`b1b96476b53065cdbff088078a6aa4b7818f02eeb797933fba4a028a8caeda06 ./artix7/segbits_gtp_channel_0_mid_right.origin_info.db`](./artix7/segbits_gtp_channel_0_mid_right.origin_info.db) + * [`226fea8aff6e578e4fc1295bb5cb4e223d80a8ef12730dbda743a449a15cdbe9 ./artix7/segbits_gtp_channel_1.db`](./artix7/segbits_gtp_channel_1.db) + * [`f273392d7d1d8628f5a627fa8373bfec2c8b24726b91a5185e5df00f22afff35 ./artix7/segbits_gtp_channel_1.origin_info.db`](./artix7/segbits_gtp_channel_1.origin_info.db) + * [`4e48837b97ca5240646cf2c5e1d0f680f6a3f0d23937645486d7e908e02bf28f ./artix7/segbits_gtp_channel_1_mid_left.db`](./artix7/segbits_gtp_channel_1_mid_left.db) + * [`2e7b8fe029b4422697b50d0703cbe55cdf1a7c4b398807e2c5999c01b41d88fb ./artix7/segbits_gtp_channel_1_mid_left.origin_info.db`](./artix7/segbits_gtp_channel_1_mid_left.origin_info.db) + * [`13b281ee07001a36cb7136b8570114c4e5cd5c4a40d18a2252418b0c7f92fa69 ./artix7/segbits_gtp_channel_1_mid_right.db`](./artix7/segbits_gtp_channel_1_mid_right.db) + * [`27df1513b6d254c558d1af092480833812a629f94859e9a9c42a137bc960e797 ./artix7/segbits_gtp_channel_1_mid_right.origin_info.db`](./artix7/segbits_gtp_channel_1_mid_right.origin_info.db) + * [`74f0502840985582c2b2b8d652cf2ecb28ab4dcf2bc52ccd10c1089e308a59f2 ./artix7/segbits_gtp_channel_2.db`](./artix7/segbits_gtp_channel_2.db) + * [`37a6bfebbb8e200208bb6bbc9510fc03b473b715826b3b9c65a56434e6fb491a ./artix7/segbits_gtp_channel_2.origin_info.db`](./artix7/segbits_gtp_channel_2.origin_info.db) + * [`9f3a29973fe4cc8f71c135a7ec304717c40b855a737cd1bba786e15b20c27184 ./artix7/segbits_gtp_channel_2_mid_left.db`](./artix7/segbits_gtp_channel_2_mid_left.db) + * [`6ca00c289c74f00acdc4a805035d24e6829d592c6ac27e96e66082874d16fab4 ./artix7/segbits_gtp_channel_2_mid_left.origin_info.db`](./artix7/segbits_gtp_channel_2_mid_left.origin_info.db) + * [`a9117aa88b0531d41dde96012eaf67309f705cc40927afcca92eefde3de9559f ./artix7/segbits_gtp_channel_2_mid_right.db`](./artix7/segbits_gtp_channel_2_mid_right.db) + * [`05e2e7b310ec7e0f08c4d48385ae5fcd26e05f348605705315562ccdb5ba062b ./artix7/segbits_gtp_channel_2_mid_right.origin_info.db`](./artix7/segbits_gtp_channel_2_mid_right.origin_info.db) + * [`9556bb97435b7f0ab59474677a047a549695248c83a83eccb0dcd35991bd737f ./artix7/segbits_gtp_channel_3.db`](./artix7/segbits_gtp_channel_3.db) + * [`0f4611c5c4b9ed91e29b139818296f3f64ac348b89c709dbc0ceea80d7ede844 ./artix7/segbits_gtp_channel_3.origin_info.db`](./artix7/segbits_gtp_channel_3.origin_info.db) + * [`d3c855bcf82086aa16d6eea3b7aeab7c19fa11c5916d64b8d82026627f934b7d ./artix7/segbits_gtp_channel_3_mid_left.db`](./artix7/segbits_gtp_channel_3_mid_left.db) + * [`f15bbdb97fb3018f3f53e96e9884672c97cf7496923b8075f02cede42e684bd3 ./artix7/segbits_gtp_channel_3_mid_left.origin_info.db`](./artix7/segbits_gtp_channel_3_mid_left.origin_info.db) + * [`e4f594f168b79d795c7aed60b92cc488d55c23df866d2eb3bf8f51e6d08704d8 ./artix7/segbits_gtp_channel_3_mid_right.db`](./artix7/segbits_gtp_channel_3_mid_right.db) + * [`db62bb5589de46e222495bc7689669686dc88d6e9aa51dbe78005f11578e2d24 ./artix7/segbits_gtp_channel_3_mid_right.origin_info.db`](./artix7/segbits_gtp_channel_3_mid_right.origin_info.db) + * [`9ec90c0988fcc69eb2a318038610778acab3a28391f968241850f9b59cf8365d ./artix7/segbits_gtp_common.db`](./artix7/segbits_gtp_common.db) + * [`db3370950e12398bfa641ccdf9c9f1522cdded52ee92e423ed9ae11244696819 ./artix7/segbits_gtp_common.origin_info.db`](./artix7/segbits_gtp_common.origin_info.db) + * [`4ed6df3458c728f66719885ceeded8deb1a0106c1157287cae44c9b97467ec4b ./artix7/segbits_gtp_common_mid_left.db`](./artix7/segbits_gtp_common_mid_left.db) + * [`5bb96a2ca569432f210d0a493953706bd945f8f1b39ee78d16eb0ade2efa80f2 ./artix7/segbits_gtp_common_mid_left.origin_info.db`](./artix7/segbits_gtp_common_mid_left.origin_info.db) + * [`f8dddd100f08cd5c801564666d875331c97d133319dfabad8285d94bd6de0e20 ./artix7/segbits_gtp_common_mid_right.db`](./artix7/segbits_gtp_common_mid_right.db) + * [`4cf9dd94cff081643450b89cdbf34d9c95370eeaedb7c9bc89172f9a3c4e229c ./artix7/segbits_gtp_common_mid_right.origin_info.db`](./artix7/segbits_gtp_common_mid_right.origin_info.db) * [`0716b02a4d15baf2ae6ad06fd828e5e5d14bb6ca6ec4ed73da297863b66d9855 ./artix7/segbits_gtp_int_interface.db`](./artix7/segbits_gtp_int_interface.db) * [`78df9b3f2977dddf280f5d0586d708bd635aa539d1e784fbc66cfde597670086 ./artix7/segbits_gtp_int_interface.origin_info.db`](./artix7/segbits_gtp_int_interface.origin_info.db) * [`0cbdfb2e0e68dd296429972a70391d785011b7db5c720b605379d9812a45756c ./artix7/segbits_gtp_int_interface_l.db`](./artix7/segbits_gtp_int_interface_l.db) @@ -338,11 +348,11 @@ Results have checksums; * [`51288ec0be63172fcb2a12a92853150c62a21e894c2d42a2586046c462bf57a9 ./artix7/segbits_hclk_r.db`](./artix7/segbits_hclk_r.db) * [`61d05145f3613042e8f0c1d97d63f6c185cfb66df609b621b44422ebb27c77a0 ./artix7/segbits_hclk_r.origin_info.db`](./artix7/segbits_hclk_r.origin_info.db) * [`0ea44e8dfaf97ed200f30b2afe117e94e1a68bdb26af2e09e69e855414779520 ./artix7/segbits_int_l.db`](./artix7/segbits_int_l.db) - * [`53f0117e2838f3d7b71a9132f35aec36950a59186cfcd4cb9c39d86149ee28a0 ./artix7/segbits_int_l.origin_info.db`](./artix7/segbits_int_l.origin_info.db) + * [`c5e7dd396db511c4e0e8bf8b45e7632ae70a1589c028405f1e08e855314ffe53 ./artix7/segbits_int_l.origin_info.db`](./artix7/segbits_int_l.origin_info.db) * [`1541c7832dd161c5b3b5745d08fe0ee6f92bfbd372b76c12f54afc032c888556 ./artix7/segbits_int_r.db`](./artix7/segbits_int_r.db) - * [`ac84ef8991ce42d55bd72b28e4b26d7ec00f37c94a3d2fb0c77fa4e76ea28194 ./artix7/segbits_int_r.origin_info.db`](./artix7/segbits_int_r.origin_info.db) - * [`72a187998817e8fb0bb4922f02821a0d31051fb7ff7c5139549e601fe68b082b ./artix7/segbits_liob33.db`](./artix7/segbits_liob33.db) - * [`39de3860980e187c9d7911a18adf6536c0218f21284ef287f63bd9932f78ed5b ./artix7/segbits_liob33.origin_info.db`](./artix7/segbits_liob33.origin_info.db) + * [`dc42429ae7563134fe7874b0aad2a563363496ff16a8423aa104321559fd82e0 ./artix7/segbits_int_r.origin_info.db`](./artix7/segbits_int_r.origin_info.db) + * [`432e956da48016ba647631ff91975eb501f98e3961330bdaa35c686d780300d9 ./artix7/segbits_liob33.db`](./artix7/segbits_liob33.db) + * [`606867ace72307cf773d819f40696862301419fda3d6d748746d2bfc58579731 ./artix7/segbits_liob33.origin_info.db`](./artix7/segbits_liob33.origin_info.db) * [`d369c1e614ef6ab1a464c0ab01d07456f73e88ca5a0c3c0dc524bb3b4f4364ff ./artix7/segbits_lioi3.db`](./artix7/segbits_lioi3.db) * [`4b1dd698dba50fdf44426b05641189c2faaff29a99d387543d1874983fd68a50 ./artix7/segbits_lioi3.origin_info.db`](./artix7/segbits_lioi3.origin_info.db) * [`0fb3e4c3427cb3fe2426445f9e6ebd1a33a3a5900904f28c7aea339a5f71530e ./artix7/segbits_lioi3_tbytesrc.db`](./artix7/segbits_lioi3_tbytesrc.db) @@ -355,8 +365,8 @@ Results have checksums; * [`ed58243250118f8cb3e7378e04b9861aa580db4991b7026b3edc439e0cfe0a77 ./artix7/segbits_pcie_int_interface_l.origin_info.db`](./artix7/segbits_pcie_int_interface_l.origin_info.db) * [`0bc32fce572935289e5ac7b10c95fb96b78418270016546d42ab11276285343e ./artix7/segbits_pcie_int_interface_r.db`](./artix7/segbits_pcie_int_interface_r.db) * [`ad36811e5e38c911473f2c3a6b805e7bb1f6186408bb6740c0dd906754762e3b ./artix7/segbits_pcie_int_interface_r.origin_info.db`](./artix7/segbits_pcie_int_interface_r.origin_info.db) - * [`f3d531a299bfa96ec116cb97070592a2ae75776bf9738f0b192b0015b2eb74e0 ./artix7/segbits_riob33.db`](./artix7/segbits_riob33.db) - * [`7b42c4babeef6857ac0e9ef248b0ba2279a3f95fd46dcf86f8f3660e2495bb74 ./artix7/segbits_riob33.origin_info.db`](./artix7/segbits_riob33.origin_info.db) + * [`327992e6b38faaeb0ddf948e8b42b8ce082a662f83f0dac14ebac901b3aeb909 ./artix7/segbits_riob33.db`](./artix7/segbits_riob33.db) + * [`f5b3e67f5a0afcd5351a35efd5c3a9e74254347c4268259de6ef4fa9c7bbfaeb ./artix7/segbits_riob33.origin_info.db`](./artix7/segbits_riob33.origin_info.db) * [`712cc4b66ff35ea6033cb76e41d8dde1225857836f4b799834925ab5c3e8575a ./artix7/segbits_rioi3.db`](./artix7/segbits_rioi3.db) * [`4d0e9719c7016a0dece266060eabf4db7218b6cc982449cb93b87e7b2d0c755b ./artix7/segbits_rioi3.origin_info.db`](./artix7/segbits_rioi3.origin_info.db) * [`6823106be1cdccae2cf0c1332c7a36ee11a1a86c31376100f16921b6b579ea19 ./artix7/segbits_rioi3_tbytesrc.db`](./artix7/segbits_rioi3_tbytesrc.db) @@ -588,7 +598,7 @@ Results have checksums; * [`3d2da5714d8c81165fa51403fb719b3ddd9e7ea7ab79280ae4e157d11a29172e ./artix7/timings/slicem.sdf`](./artix7/timings/slicem.sdf) * [`9aaa711d29833f53f765caa74f1e43ac288803d9af8030ce1694b3e3137c4078 ./artix7/xc7a100t/node_wires.json`](./artix7/xc7a100t/node_wires.json) * [`9cf701615e6f9ed6e89d86738f10ebb9d5bf1a233f1e3251315b2f9159f73391 ./artix7/xc7a100t/tileconn.json`](./artix7/xc7a100t/tileconn.json) - * [`40b95df1b59fd6cd9eb9c1be30ea756fc855c6fd960f9ce402485f44d154d782 ./artix7/xc7a100t/tilegrid.json`](./artix7/xc7a100t/tilegrid.json) + * [`1a06a603d9ffa72000924f1f97f32e6a24e5b4823945db479a0a84ed16a16480 ./artix7/xc7a100t/tilegrid.json`](./artix7/xc7a100t/tilegrid.json) * [`3f202fefbd0f36761f08eb58737a42754c65c965968174421df0374198e31daa ./artix7/xc7a100tcsg324-1/package_pins.csv`](./artix7/xc7a100tcsg324-1/package_pins.csv) * [`277906907e43846ac8a52115983cd0ece673b2310d8d10c9b2253d6537bf1a02 ./artix7/xc7a100tcsg324-1/part.json`](./artix7/xc7a100tcsg324-1/part.json) * [`4e1f153303270ed3727ca40af3179020f74271ff63c4d771556020b1d3037b92 ./artix7/xc7a100tcsg324-1/part.yaml`](./artix7/xc7a100tcsg324-1/part.yaml) @@ -600,7 +610,7 @@ Results have checksums; * [`4e1f153303270ed3727ca40af3179020f74271ff63c4d771556020b1d3037b92 ./artix7/xc7a100tfgg676-1/part.yaml`](./artix7/xc7a100tfgg676-1/part.yaml) * [`f25057c3f5f1273ab0e21bddafcb4499e219d84f7b5a00764b48bcb64dcd4bd2 ./artix7/xc7a200t/node_wires.json`](./artix7/xc7a200t/node_wires.json) * [`bed4bf8553b0faa4a63964100e6b4a8b5f9ac77dbcac474a2d2cbe7240aa4617 ./artix7/xc7a200t/tileconn.json`](./artix7/xc7a200t/tileconn.json) - * [`95c95a4f20601c927854c0e7e56a5fcd9d90ae00df7d4ef9c7a273f65e15c9a2 ./artix7/xc7a200t/tilegrid.json`](./artix7/xc7a200t/tilegrid.json) + * [`9908f8b3411195a24249a79e4e060f5d34f45f22111cf2139a3ec06d683511a0 ./artix7/xc7a200t/tilegrid.json`](./artix7/xc7a200t/tilegrid.json) * [`72dd638f5c8f6c36e74765915c01b2fa28e3c28b2c0afd91871ab7b0490a14f3 ./artix7/xc7a200tffg1156-1/package_pins.csv`](./artix7/xc7a200tffg1156-1/package_pins.csv) * [`fe44ca57c10c7b804357ded2cdea392c008b7b4d5a82ad917fa3148a756e4e42 ./artix7/xc7a200tffg1156-1/part.json`](./artix7/xc7a200tffg1156-1/part.json) * [`a3d493aef436b9978b2ed1c98c4e1364ab9eb096f824e19acd7cce3f7d920e97 ./artix7/xc7a200tffg1156-1/part.yaml`](./artix7/xc7a200tffg1156-1/part.yaml) @@ -618,7 +628,7 @@ Results have checksums; * [`ef0724733da87455426a0f833642d96e9d206d047f4eb97072c3093f80c40d7d ./artix7/xc7a35tftg256-1/part.yaml`](./artix7/xc7a35tftg256-1/part.yaml) * [`b60e01fef4c8c8d47fc646190d2d17fc63210cd0e82613624761e7463a7c35a6 ./artix7/xc7a50t/node_wires.json`](./artix7/xc7a50t/node_wires.json) * [`1604d48580815e26069c2b4909fcc50e8e8f974ad0beb349ced2329c302bb06b ./artix7/xc7a50t/tileconn.json`](./artix7/xc7a50t/tileconn.json) - * [`930c3c75e7ecc929c0baaf13249e346092b78a474b54201271d107ed74d5b6ff ./artix7/xc7a50t/tilegrid.json`](./artix7/xc7a50t/tilegrid.json) + * [`84d4da13bc1bbe8da3f18ef4f514473de576c46e2d7e49ca89a58e9cab3cca3e ./artix7/xc7a50t/tilegrid.json`](./artix7/xc7a50t/tilegrid.json) * [`1b01a06e9bae479981698cdb89fff971c825c75266b3b529cd69cd54815ce805 ./artix7/xc7a50tfgg484-1/package_pins.csv`](./artix7/xc7a50tfgg484-1/package_pins.csv) * [`6f58dc1e7f454bb28592ecfc9b343541283593d596dba555d0088d0bff9ca1ae ./artix7/xc7a50tfgg484-1/part.json`](./artix7/xc7a50tfgg484-1/part.json) * [`41c360b1e2f7e08b9051f1160a34954ce4c05a445a07f226f1f4059caf1fa1d3 ./artix7/xc7a50tfgg484-1/part.yaml`](./artix7/xc7a50tfgg484-1/part.yaml) @@ -628,7 +638,7 @@ Results have checksums; ### Settings -Created using following [settings/kintex7.sh (sha256: f04c23dee2bff14bf48a04f60034d3f3d674bb3e40182cc88201265679ac42fb)](https://github.com/SymbiFlow/prjxray/blob/6867429cc3a4ce422b06ceda100b868a0a7f8b23/settings/kintex7.sh) +Created using following [settings/kintex7.sh (sha256: f04c23dee2bff14bf48a04f60034d3f3d674bb3e40182cc88201265679ac42fb)](https://github.com/SymbiFlow/prjxray/blob/0d9418a908dafecae1d38418d3a0e2d2b2416ea0/settings/kintex7.sh) ```shell # Copyright (C) 2017-2020 The Project X-Ray Authors. # @@ -760,6 +770,10 @@ Results have checksums; * [`f87e449ccf9c605acad950269bfe104bc3a45daf79c5b7fe21042169feb7a428 ./kintex7/ppips_lioi3_sing.db`](./kintex7/ppips_lioi3_sing.db) * [`1046256199fd3c54a5f3ee7e5ec7fd72863882e01cc8da326e487c763159e2f8 ./kintex7/ppips_lioi3_tbytesrc.db`](./kintex7/ppips_lioi3_tbytesrc.db) * [`b6255a5ec971695a0aadd4901f2021d839c20b9cff781b2fccc8f5e779295319 ./kintex7/ppips_lioi3_tbyteterm.db`](./kintex7/ppips_lioi3_tbyteterm.db) + * [`48ad9ebcaa48a039f5bcc9f6d5b4736be64976434ad79bc317e88c4f40b980aa ./kintex7/ppips_pcie_bot.db`](./kintex7/ppips_pcie_bot.db) + * [`38b7dd3cf1ef560f06933b501059b4d029e1625193038eba112424f9bff630c5 ./kintex7/ppips_pcie_int_interface_l.db`](./kintex7/ppips_pcie_int_interface_l.db) + * [`e998a9cc7b3ea7f185485133a97510a9ec73dfec574f3b8583eb968073f6a7d5 ./kintex7/ppips_pcie_int_interface_r.db`](./kintex7/ppips_pcie_int_interface_r.db) + * [`5684a64e33378f61f7b92cee7011c2fc4f85be16762919a86103dc8652c73d63 ./kintex7/ppips_pcie_top.db`](./kintex7/ppips_pcie_top.db) * [`8a2136e564ac92c06b226ef8715a122050fcabbb063f69eeaf46cfee5c89670f ./kintex7/segbits_bram_l.block_ram.db`](./kintex7/segbits_bram_l.block_ram.db) * [`0cb9b3fb3c7627b1c16330f28fc212188441e087c30b0aefd506883676cde42f ./kintex7/segbits_bram_l.block_ram.origin_info.db`](./kintex7/segbits_bram_l.block_ram.origin_info.db) * [`3957476dee60377d1050b3c2ad7c2fcdfc8319e3b8243f3ab61646c3596e02de ./kintex7/segbits_bram_l.db`](./kintex7/segbits_bram_l.db) @@ -788,14 +802,14 @@ Results have checksums; * [`cf71a4438ae35cb2493b614e895e3d5cf577613a8d9c10cf1c566872a2ea9b4f ./kintex7/segbits_clk_hrow_bot_r.origin_info.db`](./kintex7/segbits_clk_hrow_bot_r.origin_info.db) * [`89ca5e5d4e9bc222815bd81e6d94cbff6950b99e3d2e80ac677334dcde40e4c2 ./kintex7/segbits_clk_hrow_top_r.db`](./kintex7/segbits_clk_hrow_top_r.db) * [`b9a1e70499c2597a6ae2381d3ab47780f2a69430073c87f2b639901d1f563e65 ./kintex7/segbits_clk_hrow_top_r.origin_info.db`](./kintex7/segbits_clk_hrow_top_r.origin_info.db) - * [`311bd38ca939dc8643afb130f77c3642f3a89c902634cfa5a06f29c3fb26e9f3 ./kintex7/segbits_cmt_top_l_lower_b.db`](./kintex7/segbits_cmt_top_l_lower_b.db) - * [`5e5166ef8643919dac09df0f904d212ff72b5c633152e16f7c89c2e650b3ac2b ./kintex7/segbits_cmt_top_l_lower_b.origin_info.db`](./kintex7/segbits_cmt_top_l_lower_b.origin_info.db) - * [`3e33276e75c69bf622e1019c4bf4b8cf3f7bb8bebcdd500f16e160b49e5a6811 ./kintex7/segbits_cmt_top_l_upper_t.db`](./kintex7/segbits_cmt_top_l_upper_t.db) - * [`a8ba9d40de847f2175429ab3328c585242372124e499a520af2a2d8fb97d1550 ./kintex7/segbits_cmt_top_l_upper_t.origin_info.db`](./kintex7/segbits_cmt_top_l_upper_t.origin_info.db) - * [`8cd75b06942f3fefe474eb10ab4522043d5a52a2ee79c4555a7c89d1d6d11ecb ./kintex7/segbits_cmt_top_r_lower_b.db`](./kintex7/segbits_cmt_top_r_lower_b.db) - * [`0a36013e20bc01d66d1a73eb2594e67d57898efddeb8de046ebcf65eed259c27 ./kintex7/segbits_cmt_top_r_lower_b.origin_info.db`](./kintex7/segbits_cmt_top_r_lower_b.origin_info.db) - * [`ff3f5ed631016fb97d2e949d02b6a4eda93b5291a14b43cda962a93eeed88894 ./kintex7/segbits_cmt_top_r_upper_t.db`](./kintex7/segbits_cmt_top_r_upper_t.db) - * [`a6ea0f1abacda03e873459b43b5fda477a027904533d9bff94c0763bc2e30cef ./kintex7/segbits_cmt_top_r_upper_t.origin_info.db`](./kintex7/segbits_cmt_top_r_upper_t.origin_info.db) + * [`f67fcf1a6891fbc8a81f8c26403fe901e055b24e070277c5512a344635285bc2 ./kintex7/segbits_cmt_top_l_lower_b.db`](./kintex7/segbits_cmt_top_l_lower_b.db) + * [`dde4d2632c4fbf25cbab1891bbbc4355b63bde78c3f3646949238ffe60df11bb ./kintex7/segbits_cmt_top_l_lower_b.origin_info.db`](./kintex7/segbits_cmt_top_l_lower_b.origin_info.db) + * [`84747f20186b10b07c4d0e1ec18f2753a0d6c7d8cb71d55373b0b306e81721d9 ./kintex7/segbits_cmt_top_l_upper_t.db`](./kintex7/segbits_cmt_top_l_upper_t.db) + * [`7e121848ca4a34942ed87fa352db9b9ec41ddf4f420de235633367e6c0494962 ./kintex7/segbits_cmt_top_l_upper_t.origin_info.db`](./kintex7/segbits_cmt_top_l_upper_t.origin_info.db) + * [`4a350d31eb78785fbd6b65044c02d623d6f787606c31a2f01a2efaf9cc2daad7 ./kintex7/segbits_cmt_top_r_lower_b.db`](./kintex7/segbits_cmt_top_r_lower_b.db) + * [`e712f48558e63ca7b078df3c357344b7977797a47b560f6b65bc953cfc93b815 ./kintex7/segbits_cmt_top_r_lower_b.origin_info.db`](./kintex7/segbits_cmt_top_r_lower_b.origin_info.db) + * [`8f938e8163274dc2b39298c571bc6f35bc65ae6e1b6314803ccfc3bb1eb6cf4e ./kintex7/segbits_cmt_top_r_upper_t.db`](./kintex7/segbits_cmt_top_r_upper_t.db) + * [`cca311d41050776907fd73cf41d1933287b65dfd291f3072a6923ad0fc222067 ./kintex7/segbits_cmt_top_r_upper_t.origin_info.db`](./kintex7/segbits_cmt_top_r_upper_t.origin_info.db) * [`81e0623ff13a253e3f9303de3d5dfbcf2fc92cf5cba277bd7de69e70c3c527e3 ./kintex7/segbits_dsp_l.db`](./kintex7/segbits_dsp_l.db) * [`18cfd5dd8f59ca704cabeeddb2365486c755185b16a41714cc18ad08818c4f62 ./kintex7/segbits_dsp_l.origin_info.db`](./kintex7/segbits_dsp_l.origin_info.db) * [`5297906aaafefd3be356682dc03cc4f8c85d0ec238a7d66bafc8b1b50a6c0c96 ./kintex7/segbits_dsp_r.db`](./kintex7/segbits_dsp_r.db) @@ -811,19 +825,19 @@ Results have checksums; * [`51288ec0be63172fcb2a12a92853150c62a21e894c2d42a2586046c462bf57a9 ./kintex7/segbits_hclk_r.db`](./kintex7/segbits_hclk_r.db) * [`61d05145f3613042e8f0c1d97d63f6c185cfb66df609b621b44422ebb27c77a0 ./kintex7/segbits_hclk_r.origin_info.db`](./kintex7/segbits_hclk_r.origin_info.db) * [`0ea44e8dfaf97ed200f30b2afe117e94e1a68bdb26af2e09e69e855414779520 ./kintex7/segbits_int_l.db`](./kintex7/segbits_int_l.db) - * [`e1439b1e1f115bff678208fc65c78f4eb104aa59d2599adb5f5c9bda1c554e47 ./kintex7/segbits_int_l.origin_info.db`](./kintex7/segbits_int_l.origin_info.db) + * [`a8e4e0a62a4c109423a18d94aaf5a963f187c58ffe17e321088395dad6300b32 ./kintex7/segbits_int_l.origin_info.db`](./kintex7/segbits_int_l.origin_info.db) * [`1541c7832dd161c5b3b5745d08fe0ee6f92bfbd372b76c12f54afc032c888556 ./kintex7/segbits_int_r.db`](./kintex7/segbits_int_r.db) - * [`fdcb761e2a4274a34fb6cf5b9029c5c1d48fca331038366ac2fe0eedb0f635f5 ./kintex7/segbits_int_r.origin_info.db`](./kintex7/segbits_int_r.origin_info.db) - * [`72a187998817e8fb0bb4922f02821a0d31051fb7ff7c5139549e601fe68b082b ./kintex7/segbits_liob33.db`](./kintex7/segbits_liob33.db) - * [`39de3860980e187c9d7911a18adf6536c0218f21284ef287f63bd9932f78ed5b ./kintex7/segbits_liob33.origin_info.db`](./kintex7/segbits_liob33.origin_info.db) + * [`be03541f8c9a9fce4375588fc0747427c1bbbe3ca4fc27a5ae5e594435401d3d ./kintex7/segbits_int_r.origin_info.db`](./kintex7/segbits_int_r.origin_info.db) + * [`432e956da48016ba647631ff91975eb501f98e3961330bdaa35c686d780300d9 ./kintex7/segbits_liob33.db`](./kintex7/segbits_liob33.db) + * [`606867ace72307cf773d819f40696862301419fda3d6d748746d2bfc58579731 ./kintex7/segbits_liob33.origin_info.db`](./kintex7/segbits_liob33.origin_info.db) * [`d369c1e614ef6ab1a464c0ab01d07456f73e88ca5a0c3c0dc524bb3b4f4364ff ./kintex7/segbits_lioi3.db`](./kintex7/segbits_lioi3.db) * [`4b1dd698dba50fdf44426b05641189c2faaff29a99d387543d1874983fd68a50 ./kintex7/segbits_lioi3.origin_info.db`](./kintex7/segbits_lioi3.origin_info.db) * [`0fb3e4c3427cb3fe2426445f9e6ebd1a33a3a5900904f28c7aea339a5f71530e ./kintex7/segbits_lioi3_tbytesrc.db`](./kintex7/segbits_lioi3_tbytesrc.db) * [`cbc24997471fa0a4cc59db46589a3daea9f59b4d599ca802a1f62b730090c89c ./kintex7/segbits_lioi3_tbytesrc.origin_info.db`](./kintex7/segbits_lioi3_tbytesrc.origin_info.db) * [`e81ad6e17e179647d06b9dc193588c8297af448e8eb7bd6c4b807a832631e07b ./kintex7/segbits_lioi3_tbyteterm.db`](./kintex7/segbits_lioi3_tbyteterm.db) * [`bf79280a339e566244220050232020c5d3b8dceed7bd80bcf23da7b4a53cb250 ./kintex7/segbits_lioi3_tbyteterm.origin_info.db`](./kintex7/segbits_lioi3_tbyteterm.origin_info.db) - * [`f3d531a299bfa96ec116cb97070592a2ae75776bf9738f0b192b0015b2eb74e0 ./kintex7/segbits_riob33.db`](./kintex7/segbits_riob33.db) - * [`7b42c4babeef6857ac0e9ef248b0ba2279a3f95fd46dcf86f8f3660e2495bb74 ./kintex7/segbits_riob33.origin_info.db`](./kintex7/segbits_riob33.origin_info.db) + * [`327992e6b38faaeb0ddf948e8b42b8ce082a662f83f0dac14ebac901b3aeb909 ./kintex7/segbits_riob33.db`](./kintex7/segbits_riob33.db) + * [`f5b3e67f5a0afcd5351a35efd5c3a9e74254347c4268259de6ef4fa9c7bbfaeb ./kintex7/segbits_riob33.origin_info.db`](./kintex7/segbits_riob33.origin_info.db) * [`712cc4b66ff35ea6033cb76e41d8dde1225857836f4b799834925ab5c3e8575a ./kintex7/segbits_rioi3.db`](./kintex7/segbits_rioi3.db) * [`4d0e9719c7016a0dece266060eabf4db7218b6cc982449cb93b87e7b2d0c755b ./kintex7/segbits_rioi3.origin_info.db`](./kintex7/segbits_rioi3.origin_info.db) * [`6823106be1cdccae2cf0c1332c7a36ee11a1a86c31376100f16921b6b579ea19 ./kintex7/segbits_rioi3_tbytesrc.db`](./kintex7/segbits_rioi3_tbytesrc.db) @@ -1007,7 +1021,7 @@ Results have checksums; ### Settings -Created using following [settings/zynq7.sh (sha256: 241ebc54a73b6a3cb3eacea09b798fe9887d955ccdfe7b48994a9a10928837c2)](https://github.com/SymbiFlow/prjxray/blob/6867429cc3a4ce422b06ceda100b868a0a7f8b23/settings/zynq7.sh) +Created using following [settings/zynq7.sh (sha256: 241ebc54a73b6a3cb3eacea09b798fe9887d955ccdfe7b48994a9a10928837c2)](https://github.com/SymbiFlow/prjxray/blob/0d9418a908dafecae1d38418d3a0e2d2b2416ea0/settings/zynq7.sh) ```shell # Copyright (C) 2017-2020 The Project X-Ray Authors. # @@ -1180,14 +1194,14 @@ Results have checksums; * [`c913b6c8399b21d515063a9eba05749e06fcdb24fc40d7a4e1e009e91d7b9c02 ./zynq7/segbits_clk_hrow_bot_r.origin_info.db`](./zynq7/segbits_clk_hrow_bot_r.origin_info.db) * [`4c9c9effdaa6039eaa0df3c44056be0ceeaa1a34eab9134821f9f3e85f46738c ./zynq7/segbits_clk_hrow_top_r.db`](./zynq7/segbits_clk_hrow_top_r.db) * [`dce4badb8750dc9ddf3db28e818df81abf4f2258c189891c35a427616c0cfc71 ./zynq7/segbits_clk_hrow_top_r.origin_info.db`](./zynq7/segbits_clk_hrow_top_r.origin_info.db) - * [`a4f42d6098b3aff51585f5ed58c0d13fb62019287172d98d73a5e0d8884134da ./zynq7/segbits_cmt_top_l_lower_b.db`](./zynq7/segbits_cmt_top_l_lower_b.db) - * [`fe4b0310db36eb87fef9901c790193b7077fbe216b1ba789ef65446c1e3b0b19 ./zynq7/segbits_cmt_top_l_lower_b.origin_info.db`](./zynq7/segbits_cmt_top_l_lower_b.origin_info.db) - * [`3e33276e75c69bf622e1019c4bf4b8cf3f7bb8bebcdd500f16e160b49e5a6811 ./zynq7/segbits_cmt_top_l_upper_t.db`](./zynq7/segbits_cmt_top_l_upper_t.db) - * [`a8ba9d40de847f2175429ab3328c585242372124e499a520af2a2d8fb97d1550 ./zynq7/segbits_cmt_top_l_upper_t.origin_info.db`](./zynq7/segbits_cmt_top_l_upper_t.origin_info.db) - * [`32cc74ba971e07fea70818fb15cd9b0e66e2cbd3f971ac68ca0e0f69337c11ca ./zynq7/segbits_cmt_top_r_lower_b.db`](./zynq7/segbits_cmt_top_r_lower_b.db) - * [`a526b7838198cdd3d9733b59aa41fc07ae55b1b3f7dfb1d6f9c3193c6384573a ./zynq7/segbits_cmt_top_r_lower_b.origin_info.db`](./zynq7/segbits_cmt_top_r_lower_b.origin_info.db) - * [`ff3f5ed631016fb97d2e949d02b6a4eda93b5291a14b43cda962a93eeed88894 ./zynq7/segbits_cmt_top_r_upper_t.db`](./zynq7/segbits_cmt_top_r_upper_t.db) - * [`a6ea0f1abacda03e873459b43b5fda477a027904533d9bff94c0763bc2e30cef ./zynq7/segbits_cmt_top_r_upper_t.origin_info.db`](./zynq7/segbits_cmt_top_r_upper_t.origin_info.db) + * [`a27bb7c254f63ac3cb9498e070d31f81b5763a31c395e94ad83f669692d18fa3 ./zynq7/segbits_cmt_top_l_lower_b.db`](./zynq7/segbits_cmt_top_l_lower_b.db) + * [`72ac477ff993341126a717a2bbfa2466e774119f3c145e6579f65b77ddba130f ./zynq7/segbits_cmt_top_l_lower_b.origin_info.db`](./zynq7/segbits_cmt_top_l_lower_b.origin_info.db) + * [`84747f20186b10b07c4d0e1ec18f2753a0d6c7d8cb71d55373b0b306e81721d9 ./zynq7/segbits_cmt_top_l_upper_t.db`](./zynq7/segbits_cmt_top_l_upper_t.db) + * [`7e121848ca4a34942ed87fa352db9b9ec41ddf4f420de235633367e6c0494962 ./zynq7/segbits_cmt_top_l_upper_t.origin_info.db`](./zynq7/segbits_cmt_top_l_upper_t.origin_info.db) + * [`316ec3a054a9bb371a9315aaf7e7ee2a351ef43098fc4510880e332d6286c90e ./zynq7/segbits_cmt_top_r_lower_b.db`](./zynq7/segbits_cmt_top_r_lower_b.db) + * [`db6e283a3f418b2e9c5c1946bdb7145183ed70b783018b0013ff04f676d37a47 ./zynq7/segbits_cmt_top_r_lower_b.origin_info.db`](./zynq7/segbits_cmt_top_r_lower_b.origin_info.db) + * [`8f938e8163274dc2b39298c571bc6f35bc65ae6e1b6314803ccfc3bb1eb6cf4e ./zynq7/segbits_cmt_top_r_upper_t.db`](./zynq7/segbits_cmt_top_r_upper_t.db) + * [`cca311d41050776907fd73cf41d1933287b65dfd291f3072a6923ad0fc222067 ./zynq7/segbits_cmt_top_r_upper_t.origin_info.db`](./zynq7/segbits_cmt_top_r_upper_t.origin_info.db) * [`81e0623ff13a253e3f9303de3d5dfbcf2fc92cf5cba277bd7de69e70c3c527e3 ./zynq7/segbits_dsp_l.db`](./zynq7/segbits_dsp_l.db) * [`18cfd5dd8f59ca704cabeeddb2365486c755185b16a41714cc18ad08818c4f62 ./zynq7/segbits_dsp_l.origin_info.db`](./zynq7/segbits_dsp_l.origin_info.db) * [`5297906aaafefd3be356682dc03cc4f8c85d0ec238a7d66bafc8b1b50a6c0c96 ./zynq7/segbits_dsp_r.db`](./zynq7/segbits_dsp_r.db) @@ -1203,19 +1217,19 @@ Results have checksums; * [`51288ec0be63172fcb2a12a92853150c62a21e894c2d42a2586046c462bf57a9 ./zynq7/segbits_hclk_r.db`](./zynq7/segbits_hclk_r.db) * [`61d05145f3613042e8f0c1d97d63f6c185cfb66df609b621b44422ebb27c77a0 ./zynq7/segbits_hclk_r.origin_info.db`](./zynq7/segbits_hclk_r.origin_info.db) * [`0ea44e8dfaf97ed200f30b2afe117e94e1a68bdb26af2e09e69e855414779520 ./zynq7/segbits_int_l.db`](./zynq7/segbits_int_l.db) - * [`621e9074a0f82f119ee9746ff098e92505920351aa885f6106952abef368858b ./zynq7/segbits_int_l.origin_info.db`](./zynq7/segbits_int_l.origin_info.db) + * [`66c9451631fbcde9a417fa19168a60a8bae3a991823d6773ffa1543396dde30e ./zynq7/segbits_int_l.origin_info.db`](./zynq7/segbits_int_l.origin_info.db) * [`1541c7832dd161c5b3b5745d08fe0ee6f92bfbd372b76c12f54afc032c888556 ./zynq7/segbits_int_r.db`](./zynq7/segbits_int_r.db) - * [`a55eef9788528b90c6433681387fd48064d4af45fe820d76e3016978e962f9d2 ./zynq7/segbits_int_r.origin_info.db`](./zynq7/segbits_int_r.origin_info.db) - * [`72a187998817e8fb0bb4922f02821a0d31051fb7ff7c5139549e601fe68b082b ./zynq7/segbits_liob33.db`](./zynq7/segbits_liob33.db) - * [`39de3860980e187c9d7911a18adf6536c0218f21284ef287f63bd9932f78ed5b ./zynq7/segbits_liob33.origin_info.db`](./zynq7/segbits_liob33.origin_info.db) + * [`578bb187f19d5a0dff2e5dccda6fde721e03b25abbe4287fb48d563f484e0866 ./zynq7/segbits_int_r.origin_info.db`](./zynq7/segbits_int_r.origin_info.db) + * [`432e956da48016ba647631ff91975eb501f98e3961330bdaa35c686d780300d9 ./zynq7/segbits_liob33.db`](./zynq7/segbits_liob33.db) + * [`606867ace72307cf773d819f40696862301419fda3d6d748746d2bfc58579731 ./zynq7/segbits_liob33.origin_info.db`](./zynq7/segbits_liob33.origin_info.db) * [`d369c1e614ef6ab1a464c0ab01d07456f73e88ca5a0c3c0dc524bb3b4f4364ff ./zynq7/segbits_lioi3.db`](./zynq7/segbits_lioi3.db) * [`4b1dd698dba50fdf44426b05641189c2faaff29a99d387543d1874983fd68a50 ./zynq7/segbits_lioi3.origin_info.db`](./zynq7/segbits_lioi3.origin_info.db) * [`0fb3e4c3427cb3fe2426445f9e6ebd1a33a3a5900904f28c7aea339a5f71530e ./zynq7/segbits_lioi3_tbytesrc.db`](./zynq7/segbits_lioi3_tbytesrc.db) * [`cbc24997471fa0a4cc59db46589a3daea9f59b4d599ca802a1f62b730090c89c ./zynq7/segbits_lioi3_tbytesrc.origin_info.db`](./zynq7/segbits_lioi3_tbytesrc.origin_info.db) * [`e81ad6e17e179647d06b9dc193588c8297af448e8eb7bd6c4b807a832631e07b ./zynq7/segbits_lioi3_tbyteterm.db`](./zynq7/segbits_lioi3_tbyteterm.db) * [`bf79280a339e566244220050232020c5d3b8dceed7bd80bcf23da7b4a53cb250 ./zynq7/segbits_lioi3_tbyteterm.origin_info.db`](./zynq7/segbits_lioi3_tbyteterm.origin_info.db) - * [`f3d531a299bfa96ec116cb97070592a2ae75776bf9738f0b192b0015b2eb74e0 ./zynq7/segbits_riob33.db`](./zynq7/segbits_riob33.db) - * [`7b42c4babeef6857ac0e9ef248b0ba2279a3f95fd46dcf86f8f3660e2495bb74 ./zynq7/segbits_riob33.origin_info.db`](./zynq7/segbits_riob33.origin_info.db) + * [`327992e6b38faaeb0ddf948e8b42b8ce082a662f83f0dac14ebac901b3aeb909 ./zynq7/segbits_riob33.db`](./zynq7/segbits_riob33.db) + * [`f5b3e67f5a0afcd5351a35efd5c3a9e74254347c4268259de6ef4fa9c7bbfaeb ./zynq7/segbits_riob33.origin_info.db`](./zynq7/segbits_riob33.origin_info.db) * [`712cc4b66ff35ea6033cb76e41d8dde1225857836f4b799834925ab5c3e8575a ./zynq7/segbits_rioi3.db`](./zynq7/segbits_rioi3.db) * [`4d0e9719c7016a0dece266060eabf4db7218b6cc982449cb93b87e7b2d0c755b ./zynq7/segbits_rioi3.origin_info.db`](./zynq7/segbits_rioi3.origin_info.db) * [`6823106be1cdccae2cf0c1332c7a36ee11a1a86c31376100f16921b6b579ea19 ./zynq7/segbits_rioi3_tbytesrc.db`](./zynq7/segbits_rioi3_tbytesrc.db) diff --git a/artix7/cells_data/gtpe2_channel_attrs.json b/artix7/cells_data/gtpe2_channel_attrs.json new file mode 100644 index 0000000..02641ef --- /dev/null +++ b/artix7/cells_data/gtpe2_channel_attrs.json @@ -0,0 +1,3645 @@ +{ + "ACJTAG_DEBUG_MODE": { + "digits": 1, + "type": "BIN", + "values": [ + 1 + ] + }, + "ACJTAG_MODE": { + "digits": 1, + "type": "BIN", + "values": [ + 1 + ] + }, + "ACJTAG_RESET": { + "digits": 1, + "type": "BIN", + "values": [ + 1 + ] + }, + "ADAPT_CFG0": { + "digits": 20, + "type": "BIN", + "values": [ + 983025 + ] + }, + "ALIGN_COMMA_DOUBLE": { + "digits": 1, + "type": "BOOL", + "values": [ + "FALSE", + "TRUE" + ] + }, + "ALIGN_COMMA_ENABLE": { + "digits": 10, + "type": "BIN", + "values": [ + 1023 + ] + }, + "ALIGN_COMMA_WORD": { + "digits": 2, + "encoding": [ + 1, + 2 + ], + "type": "INT", + "values": [ + 1, + 2 + ] + }, + "ALIGN_MCOMMA_DET": { + "digits": 1, + "type": "BOOL", + "values": [ + "FALSE", + "TRUE" + ] + }, + "ALIGN_MCOMMA_VALUE": { + "digits": 10, + "type": "BIN", + "values": [ + 1023 + ] + }, + "ALIGN_PCOMMA_DET": { + "digits": 1, + "type": "BOOL", + "values": [ + "FALSE", + "TRUE" + ] + }, + "ALIGN_PCOMMA_VALUE": { + "digits": 10, + "type": "BIN", + "values": [ + 1023 + ] + }, + "CBCC_DATA_SOURCE_SEL": { + "digits": 1, + "type": "STR", + "values": [ + "ENCODED", + "DECODED" + ] + }, + "CFOK_CFG": { + "digits": 43, + "type": "BIN", + "values": [ + 8791529752575 + ] + }, + "CFOK_CFG2": { + "digits": 7, + "type": "BIN", + "values": [ + 127 + ] + }, + "CFOK_CFG3": { + "digits": 7, + "type": "BIN", + "values": [ + 127 + ] + }, + "CFOK_CFG4": { + "digits": 1, + "type": "BIN", + "values": [ + 1 + ] + }, + "CFOK_CFG5": { + "digits": 2, + "type": "BIN", + "values": [ + 3 + ] + }, + "CFOK_CFG6": { + "digits": 4, + "type": "BIN", + "values": [ + 15 + ] + }, + "CHAN_BOND_KEEP_ALIGN": { + "digits": 1, + "type": "BOOL", + "values": [ + "FALSE", + "TRUE" + ] + }, + "CHAN_BOND_MAX_SKEW": { + "digits": 4, + "encoding": [ + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14 + ], + "type": "INT", + "values": [ + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14 + ] + }, + "CHAN_BOND_SEQ_1_1": { + "digits": 10, + "type": "BIN", + "values": [ + 1023 + ] + }, + "CHAN_BOND_SEQ_1_2": { + "digits": 10, + "type": "BIN", + "values": [ + 1023 + ] + }, + "CHAN_BOND_SEQ_1_3": { + "digits": 10, + "type": "BIN", + "values": [ + 1023 + ] + }, + "CHAN_BOND_SEQ_1_4": { + "digits": 10, + "type": "BIN", + "values": [ + 1023 + ] + }, + "CHAN_BOND_SEQ_1_ENABLE": { + "digits": 4, + "type": "BIN", + "values": [ + 15 + ] + }, + "CHAN_BOND_SEQ_2_1": { + "digits": 10, + "type": "BIN", + "values": [ + 1023 + ] + }, + "CHAN_BOND_SEQ_2_2": { + "digits": 10, + "type": "BIN", + "values": [ + 1023 + ] + }, + "CHAN_BOND_SEQ_2_3": { + "digits": 10, + "type": "BIN", + "values": [ + 1023 + ] + }, + "CHAN_BOND_SEQ_2_4": { + "digits": 10, + "type": "BIN", + "values": [ + 1023 + ] + }, + "CHAN_BOND_SEQ_2_ENABLE": { + "digits": 4, + "type": "BIN", + "values": [ + 15 + ] + }, + "CHAN_BOND_SEQ_2_USE": { + "digits": 1, + "type": "BOOL", + "values": [ + "FALSE", + "TRUE" + ] + }, + "CHAN_BOND_SEQ_LEN": { + "digits": 2, + "encoding": [ + 0, + 1, + 2, + 3 + ], + "type": "INT", + "values": [ + 1, + 2, + 3, + 4 + ] + }, + "CLK_COMMON_SWING": { + "digits": 1, + "type": "BIN", + "values": [ + 1 + ] + }, + "CLK_CORRECT_USE": { + "digits": 1, + "type": "BOOL", + "values": [ + "FALSE", + "TRUE" + ] + }, + "CLK_COR_KEEP_IDLE": { + "digits": 1, + "type": "BOOL", + "values": [ + "FALSE", + "TRUE" + ] + }, + "CLK_COR_MAX_LAT": { + "digits": 6, + "encoding": [ + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15, + 16, + 17, + 18, + 19, + 20, + 21, + 22, + 23, + 24, + 25, + 26, + 27, + 28, + 29, + 30, + 31, + 32, + 33, + 34, + 35, + 36, + 37, + 38, + 39, + 40, + 41, + 42, + 43, + 44, + 45, + 46, + 47, + 48, + 49, + 50, + 51, + 52, + 53, + 54, + 55, + 56, + 57, + 58, + 59, + 60 + ], + "type": "INT", + "values": [ + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15, + 16, + 17, + 18, + 19, + 20, + 21, + 22, + 23, + 24, + 25, + 26, + 27, + 28, + 29, + 30, + 31, + 32, + 33, + 34, + 35, + 36, + 37, + 38, + 39, + 40, + 41, + 42, + 43, + 44, + 45, + 46, + 47, + 48, + 49, + 50, + 51, + 52, + 53, + 54, + 55, + 56, + 57, + 58, + 59, + 60 + ] + }, + "CLK_COR_MIN_LAT": { + "digits": 6, + "encoding": [ + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15, + 16, + 17, + 18, + 19, + 20, + 21, + 22, + 23, + 24, + 25, + 26, + 27, + 28, + 29, + 30, + 31, + 32, + 33, + 34, + 35, + 36, + 37, + 38, + 39, + 40, + 41, + 42, + 43, + 44, + 45, + 46, + 47, + 48, + 49, + 50, + 51, + 52, + 53, + 54, + 55, + 56, + 57, + 58, + 59, + 60 + ], + "type": "INT", + "values": [ + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15, + 16, + 17, + 18, + 19, + 20, + 21, + 22, + 23, + 24, + 25, + 26, + 27, + 28, + 29, + 30, + 31, + 32, + 33, + 34, + 35, + 36, + 37, + 38, + 39, + 40, + 41, + 42, + 43, + 44, + 45, + 46, + 47, + 48, + 49, + 50, + 51, + 52, + 53, + 54, + 55, + 56, + 57, + 58, + 59, + 60 + ] + }, + "CLK_COR_PRECEDENCE": { + "digits": 1, + "type": "BOOL", + "values": [ + "FALSE", + "TRUE" + ] + }, + "CLK_COR_REPEAT_WAIT": { + "digits": 5, + "encoding": [ + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15, + 16, + 17, + 18, + 19, + 20, + 21, + 22, + 23, + 24, + 25, + 26, + 27, + 28, + 29, + 30, + 31 + ], + "type": "INT", + "values": [ + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15, + 16, + 17, + 18, + 19, + 20, + 21, + 22, + 23, + 24, + 25, + 26, + 27, + 28, + 29, + 30, + 31 + ] + }, + "CLK_COR_SEQ_1_1": { + "digits": 10, + "type": "BIN", + "values": [ + 1023 + ] + }, + "CLK_COR_SEQ_1_2": { + "digits": 10, + "type": "BIN", + "values": [ + 1023 + ] + }, + "CLK_COR_SEQ_1_3": { + "digits": 10, + "type": "BIN", + "values": [ + 1023 + ] + }, + "CLK_COR_SEQ_1_4": { + "digits": 10, + "type": "BIN", + "values": [ + 1023 + ] + }, + "CLK_COR_SEQ_1_ENABLE": { + "digits": 4, + "type": "BIN", + "values": [ + 15 + ] + }, + "CLK_COR_SEQ_2_1": { + "digits": 10, + "type": "BIN", + "values": [ + 1023 + ] + }, + "CLK_COR_SEQ_2_2": { + "digits": 10, + "type": "BIN", + "values": [ + 1023 + ] + }, + "CLK_COR_SEQ_2_3": { + "digits": 10, + "type": "BIN", + "values": [ + 1023 + ] + }, + "CLK_COR_SEQ_2_4": { + "digits": 10, + "type": "BIN", + "values": [ + 1023 + ] + }, + "CLK_COR_SEQ_2_ENABLE": { + "digits": 4, + "type": "BIN", + "values": [ + 15 + ] + }, + "CLK_COR_SEQ_2_USE": { + "digits": 1, + "type": "BOOL", + "values": [ + "FALSE", + "TRUE" + ] + }, + "CLK_COR_SEQ_LEN": { + "digits": 2, + "encoding": [ + 0, + 1, + 2, + 3 + ], + "type": "INT", + "values": [ + 1, + 2, + 3, + 4 + ] + }, + "DEC_MCOMMA_DETECT": { + "digits": 1, + "type": "BOOL", + "values": [ + "FALSE", + "TRUE" + ] + }, + "DEC_PCOMMA_DETECT": { + "digits": 1, + "type": "BOOL", + "values": [ + "FALSE", + "TRUE" + ] + }, + "DEC_VALID_COMMA_ONLY": { + "digits": 1, + "type": "BOOL", + "values": [ + "FALSE", + "TRUE" + ] + }, + "DMONITOR_CFG": { + "digits": 24, + "type": "BIN", + "values": [ + 16711425 + ] + }, + "ES_CLK_PHASE_SEL": { + "digits": 1, + "type": "BIN", + "values": [ + 1 + ] + }, + "ES_CONTROL": { + "digits": 6, + "type": "BIN", + "values": [ + 63 + ] + }, + "ES_ERRDET_EN": { + "digits": 1, + "type": "BOOL", + "values": [ + "FALSE", + "TRUE" + ] + }, + "ES_EYE_SCAN_EN": { + "digits": 1, + "type": "BOOL", + "values": [ + "FALSE", + "TRUE" + ] + }, + "ES_HORZ_OFFSET": { + "digits": 12, + "type": "BIN", + "values": [ + 4095 + ] + }, + "ES_PMA_CFG": { + "digits": 10, + "type": "BIN", + "values": [ + 1023 + ] + }, + "ES_PRESCALE": { + "digits": 5, + "type": "BIN", + "values": [ + 31 + ] + }, + "ES_QUALIFIER": { + "digits": 80, + "type": "BIN", + "values": [ + 1208833588708967444709375 + ] + }, + "ES_QUAL_MASK": { + "digits": 80, + "type": "BIN", + "values": [ + 1208833588708967444709375 + ] + }, + "ES_SDATA_MASK": { + "digits": 80, + "type": "BIN", + "values": [ + 1208833588708967444709375 + ] + }, + "ES_VERT_OFFSET": { + "digits": 9, + "type": "BIN", + "values": [ + 511 + ] + }, + "FTS_DESKEW_SEQ_ENABLE": { + "digits": 4, + "type": "BIN", + "values": [ + 15 + ] + }, + "FTS_LANE_DESKEW_CFG": { + "digits": 4, + "type": "BIN", + "values": [ + 15 + ] + }, + "FTS_LANE_DESKEW_EN": { + "digits": 1, + "type": "BOOL", + "values": [ + "FALSE", + "TRUE" + ] + }, + "GEARBOX_MODE": { + "digits": 3, + "type": "BIN", + "values": [ + 7 + ] + }, + "LOOPBACK_CFG": { + "digits": 1, + "type": "BIN", + "values": [ + 1 + ] + }, + "OUTREFCLK_SEL_INV": { + "digits": 2, + "type": "BIN", + "values": [ + 3 + ] + }, + "PCS_PCIE_EN": { + "digits": 1, + "type": "BOOL", + "values": [ + "FALSE", + "TRUE" + ] + }, + "PCS_RSVD_ATTR": { + "digits": 48, + "type": "BIN", + "values": [ + 281462092005375 + ] + }, + "PD_TRANS_TIME_FROM_P2": { + "digits": 12, + "type": "BIN", + "values": [ + 4095 + ] + }, + "PD_TRANS_TIME_NONE_P2": { + "digits": 8, + "type": "BIN", + "values": [ + 255 + ] + }, + "PD_TRANS_TIME_TO_P2": { + "digits": 8, + "type": "BIN", + "values": [ + 255 + ] + }, + "PMA_LOOPBACK_CFG": { + "digits": 1, + "type": "BIN", + "values": [ + 1 + ] + }, + "PMA_RSV": { + "digits": 32, + "type": "BIN", + "values": [ + 4294836225 + ] + }, + "PMA_RSV2": { + "digits": 32, + "type": "BIN", + "values": [ + 4294836225 + ] + }, + "PMA_RSV3": { + "digits": 2, + "type": "BIN", + "values": [ + 3 + ] + }, + "PMA_RSV4": { + "digits": 4, + "type": "BIN", + "values": [ + 15 + ] + }, + "PMA_RSV5": { + "digits": 1, + "type": "BIN", + "values": [ + 1 + ] + }, + "PMA_RSV6": { + "digits": 1, + "type": "BIN", + "values": [ + 1 + ] + }, + "PMA_RSV7": { + "digits": 1, + "type": "BIN", + "values": [ + 1 + ] + }, + "RXBUFRESET_TIME": { + "digits": 5, + "type": "BIN", + "values": [ + 31 + ] + }, + "RXBUF_ADDR_MODE": { + "digits": 1, + "type": "STR", + "values": [ + "FULL", + "FAST" + ] + }, + "RXBUF_EIDLE_HI_CNT": { + "digits": 4, + "type": "BIN", + "values": [ + 15 + ] + }, + "RXBUF_EIDLE_LO_CNT": { + "digits": 4, + "type": "BIN", + "values": [ + 15 + ] + }, + "RXBUF_EN": { + "digits": 1, + "type": "BOOL", + "values": [ + "FALSE", + "TRUE" + ] + }, + "RXBUF_RESET_ON_CB_CHANGE": { + "digits": 1, + "type": "BOOL", + "values": [ + "FALSE", + "TRUE" + ] + }, + "RXBUF_RESET_ON_COMMAALIGN": { + "digits": 1, + "type": "BOOL", + "values": [ + "FALSE", + "TRUE" + ] + }, + "RXBUF_RESET_ON_EIDLE": { + "digits": 1, + "type": "BOOL", + "values": [ + "FALSE", + "TRUE" + ] + }, + "RXBUF_RESET_ON_RATE_CHANGE": { + "digits": 1, + "type": "BOOL", + "values": [ + "FALSE", + "TRUE" + ] + }, + "RXBUF_THRESH_OVFLW": { + "digits": 6, + "encoding": [ + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15, + 16, + 17, + 18, + 19, + 20, + 21, + 22, + 23, + 24, + 25, + 26, + 27, + 28, + 29, + 30, + 31, + 32, + 33, + 34, + 35, + 36, + 37, + 38, + 39, + 40, + 41, + 42, + 43, + 44, + 45, + 46, + 47, + 48, + 49, + 50, + 51, + 52, + 53, + 54, + 55, + 56, + 57, + 58, + 59, + 60, + 61, + 62, + 63 + ], + "type": "INT", + "values": [ + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15, + 16, + 17, + 18, + 19, + 20, + 21, + 22, + 23, + 24, + 25, + 26, + 27, + 28, + 29, + 30, + 31, + 32, + 33, + 34, + 35, + 36, + 37, + 38, + 39, + 40, + 41, + 42, + 43, + 44, + 45, + 46, + 47, + 48, + 49, + 50, + 51, + 52, + 53, + 54, + 55, + 56, + 57, + 58, + 59, + 60, + 61, + 62, + 63 + ] + }, + "RXBUF_THRESH_OVRD": { + "digits": 1, + "type": "BOOL", + "values": [ + "FALSE", + "TRUE" + ] + }, + "RXBUF_THRESH_UNDFLW": { + "digits": 6, + "encoding": [ + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15, + 16, + 17, + 18, + 19, + 20, + 21, + 22, + 23, + 24, + 25, + 26, + 27, + 28, + 29, + 30, + 31, + 32, + 33, + 34, + 35, + 36, + 37, + 38, + 39, + 40, + 41, + 42, + 43, + 44, + 45, + 46, + 47, + 48, + 49, + 50, + 51, + 52, + 53, + 54, + 55, + 56, + 57, + 58, + 59, + 60, + 61, + 62, + 63 + ], + "type": "INT", + "values": [ + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15, + 16, + 17, + 18, + 19, + 20, + 21, + 22, + 23, + 24, + 25, + 26, + 27, + 28, + 29, + 30, + 31, + 32, + 33, + 34, + 35, + 36, + 37, + 38, + 39, + 40, + 41, + 42, + 43, + 44, + 45, + 46, + 47, + 48, + 49, + 50, + 51, + 52, + 53, + 54, + 55, + 56, + 57, + 58, + 59, + 60, + 61, + 62, + 63 + ] + }, + "RXCDRFREQRESET_TIME": { + "digits": 5, + "type": "BIN", + "values": [ + 31 + ] + }, + "RXCDRPHRESET_TIME": { + "digits": 5, + "type": "BIN", + "values": [ + 31 + ] + }, + "RXCDR_CFG": { + "digits": 83, + "type": "BIN", + "values": [ + 8461835120962772112965625 + ] + }, + "RXCDR_FR_RESET_ON_EIDLE": { + "digits": 1, + "type": "BIN", + "values": [ + 1 + ] + }, + "RXCDR_HOLD_DURING_EIDLE": { + "digits": 1, + "type": "BIN", + "values": [ + 1 + ] + }, + "RXCDR_LOCK_CFG": { + "digits": 6, + "type": "BIN", + "values": [ + 63 + ] + }, + "RXCDR_PH_RESET_ON_EIDLE": { + "digits": 1, + "type": "BIN", + "values": [ + 1 + ] + }, + "RXDLY_CFG": { + "digits": 16, + "type": "BIN", + "values": [ + 65535 + ] + }, + "RXDLY_LCFG": { + "digits": 9, + "type": "BIN", + "values": [ + 511 + ] + }, + "RXDLY_TAP_CFG": { + "digits": 16, + "type": "BIN", + "values": [ + 65535 + ] + }, + "RXGEARBOX_EN": { + "digits": 1, + "type": "BOOL", + "values": [ + "FALSE", + "TRUE" + ] + }, + "RXISCANRESET_TIME": { + "digits": 5, + "type": "BIN", + "values": [ + 31 + ] + }, + "RXLPMRESET_TIME": { + "digits": 7, + "type": "BIN", + "values": [ + 127 + ] + }, + "RXLPM_BIAS_STARTUP_DISABLE": { + "digits": 1, + "type": "BIN", + "values": [ + 1 + ] + }, + "RXLPM_CFG": { + "digits": 4, + "type": "BIN", + "values": [ + 15 + ] + }, + "RXLPM_CFG1": { + "digits": 1, + "type": "BIN", + "values": [ + 1 + ] + }, + "RXLPM_CM_CFG": { + "digits": 1, + "type": "BIN", + "values": [ + 1 + ] + }, + "RXLPM_GC_CFG": { + "digits": 9, + "type": "BIN", + "values": [ + 511 + ] + }, + "RXLPM_GC_CFG2": { + "digits": 3, + "type": "BIN", + "values": [ + 7 + ] + }, + "RXLPM_HF_CFG": { + "digits": 14, + "type": "BIN", + "values": [ + 16383 + ] + }, + "RXLPM_HF_CFG2": { + "digits": 5, + "type": "BIN", + "values": [ + 31 + ] + }, + "RXLPM_HF_CFG3": { + "digits": 4, + "type": "BIN", + "values": [ + 15 + ] + }, + "RXLPM_HOLD_DURING_EIDLE": { + "digits": 1, + "type": "BIN", + "values": [ + 1 + ] + }, + "RXLPM_INCM_CFG": { + "digits": 1, + "type": "BIN", + "values": [ + 1 + ] + }, + "RXLPM_IPCM_CFG": { + "digits": 1, + "type": "BIN", + "values": [ + 1 + ] + }, + "RXLPM_LF_CFG": { + "digits": 18, + "type": "BIN", + "values": [ + 262144 + ] + }, + "RXLPM_LF_CFG2": { + "digits": 5, + "type": "BIN", + "values": [ + 31 + ] + }, + "RXLPM_OSINT_CFG": { + "digits": 3, + "type": "BIN", + "values": [ + 7 + ] + }, + "RXOOB_CFG": { + "digits": 7, + "type": "BIN", + "values": [ + 127 + ] + }, + "RXOOB_CLK_CFG": { + "digits": 1, + "type": "STR", + "values": [ + "PMA", + "FABRIC" + ] + }, + "RXOSCALRESET_TIME": { + "digits": 5, + "type": "BIN", + "values": [ + 31 + ] + }, + "RXOSCALRESET_TIMEOUT": { + "digits": 5, + "type": "BIN", + "values": [ + 31 + ] + }, + "RXOUT_DIV": { + "digits": 3, + "encoding": [ + 0, + 1, + 2, + 3 + ], + "type": "INT", + "values": [ + 1, + 2, + 4, + 8 + ] + }, + "RXPCSRESET_TIME": { + "digits": 5, + "type": "BIN", + "values": [ + 31 + ] + }, + "RXPHDLY_CFG": { + "digits": 24, + "type": "BIN", + "values": [ + 16711425 + ] + }, + "RXPH_CFG": { + "digits": 24, + "type": "BIN", + "values": [ + 16711425 + ] + }, + "RXPH_MONITOR_SEL": { + "digits": 5, + "type": "BIN", + "values": [ + 31 + ] + }, + "RXPI_CFG0": { + "digits": 3, + "type": "BIN", + "values": [ + 7 + ] + }, + "RXPI_CFG1": { + "digits": 1, + "type": "BIN", + "values": [ + 1 + ] + }, + "RXPI_CFG2": { + "digits": 1, + "type": "BIN", + "values": [ + 1 + ] + }, + "RXPMARESET_TIME": { + "digits": 5, + "type": "BIN", + "values": [ + 31 + ] + }, + "RXPRBS_ERR_LOOPBACK": { + "digits": 1, + "type": "BIN", + "values": [ + 1 + ] + }, + "RXSLIDE_AUTO_WAIT": { + "digits": 4, + "encoding": [ + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15 + ], + "type": "INT", + "values": [ + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15 + ] + }, + "RXSLIDE_MODE": { + "digits": 2, + "type": "STR", + "values": [ + "OFF", + "AUTO", + "PCS", + "PMA" + ] + }, + "RXSYNC_MULTILANE": { + "digits": 1, + "type": "BIN", + "values": [ + 1 + ] + }, + "RXSYNC_OVRD": { + "digits": 1, + "type": "BIN", + "values": [ + 1 + ] + }, + "RXSYNC_SKIP_DA": { + "digits": 1, + "type": "BIN", + "values": [ + 1 + ] + }, + "RX_BIAS_CFG": { + "digits": 16, + "type": "BIN", + "values": [ + 65535 + ] + }, + "RX_BUFFER_CFG": { + "digits": 6, + "type": "BIN", + "values": [ + 63 + ] + }, + "RX_CLK25_DIV": { + "digits": 5, + "encoding": [ + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15, + 16, + 17, + 18, + 19, + 20, + 21, + 22, + 23, + 24, + 25, + 26, + 27, + 28, + 29, + 30, + 31 + ], + "type": "INT", + "values": [ + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15, + 16, + 17, + 18, + 19, + 20, + 21, + 22, + 23, + 24, + 25, + 26, + 27, + 28, + 29, + 30, + 31, + 32 + ] + }, + "RX_CLKMUX_EN": { + "digits": 1, + "type": "BIN", + "values": [ + 1 + ] + }, + "RX_CM_SEL": { + "digits": 2, + "type": "BIN", + "values": [ + 3 + ] + }, + "RX_CM_TRIM": { + "digits": 4, + "type": "BIN", + "values": [ + 15 + ] + }, + "RX_DATA_WIDTH": { + "digits": 3, + "encoding": [ + 2, + 3, + 4, + 5 + ], + "type": "INT", + "values": [ + 16, + 20, + 32, + 40 + ] + }, + "RX_DDI_SEL": { + "digits": 6, + "type": "BIN", + "values": [ + 63 + ] + }, + "RX_DEBUG_CFG": { + "digits": 14, + "type": "BIN", + "values": [ + 16383 + ] + }, + "RX_DEFER_RESET_BUF_EN": { + "digits": 1, + "type": "BOOL", + "values": [ + "FALSE", + "TRUE" + ] + }, + "RX_DISPERR_SEQ_MATCH": { + "digits": 1, + "type": "BOOL", + "values": [ + "FALSE", + "TRUE" + ] + }, + "RX_OS_CFG": { + "digits": 13, + "type": "BIN", + "values": [ + 8191 + ] + }, + "RX_SIG_VALID_DLY": { + "digits": 5, + "encoding": [ + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15, + 16, + 17, + 18, + 19, + 20, + 21, + 22, + 23, + 24, + 25, + 26, + 27, + 28, + 29, + 30, + 31 + ], + "type": "INT", + "values": [ + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15, + 16, + 17, + 18, + 19, + 20, + 21, + 22, + 23, + 24, + 25, + 26, + 27, + 28, + 29, + 30, + 31, + 32 + ] + }, + "RX_XCLK_SEL": { + "digits": 1, + "type": "STR", + "values": [ + "RXREC", + "RXUSR" + ] + }, + "SAS_MAX_COM": { + "digits": 7, + "encoding": [ + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15, + 16, + 17, + 18, + 19, + 20, + 21, + 22, + 23, + 24, + 25, + 26, + 27, + 28, + 29, + 30, + 31, + 32, + 33, + 34, + 35, + 36, + 37, + 38, + 39, + 40, + 41, + 42, + 43, + 44, + 45, + 46, + 47, + 48, + 49, + 50, + 51, + 52, + 53, + 54, + 55, + 56, + 57, + 58, + 59, + 60, + 61, + 62, + 63, + 64, + 65, + 66, + 67, + 68, + 69, + 70, + 71, + 71, + 73, + 74, + 75, + 76, + 77, + 78, + 79, + 80, + 81, + 82, + 83, + 84, + 85, + 86, + 87, + 88, + 89, + 90, + 91, + 92, + 93, + 94, + 95, + 96, + 97, + 98, + 99, + 100, + 101, + 102, + 103, + 104, + 105, + 106, + 107, + 108, + 109, + 110, + 111, + 112, + 113, + 114, + 115, + 116, + 117, + 118, + 119, + 120, + 121, + 122, + 123, + 124, + 125, + 126, + 127 + ], + "type": "INT", + "values": [ + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15, + 16, + 17, + 18, + 19, + 20, + 21, + 22, + 23, + 24, + 25, + 26, + 27, + 28, + 29, + 30, + 31, + 32, + 33, + 34, + 35, + 36, + 37, + 38, + 39, + 40, + 41, + 42, + 43, + 44, + 45, + 46, + 47, + 48, + 49, + 50, + 51, + 52, + 53, + 54, + 55, + 56, + 57, + 58, + 59, + 60, + 61, + 62, + 63, + 64, + 65, + 66, + 67, + 68, + 69, + 70, + 71, + 71, + 73, + 74, + 75, + 76, + 77, + 78, + 79, + 80, + 81, + 82, + 83, + 84, + 85, + 86, + 87, + 88, + 89, + 90, + 91, + 92, + 93, + 94, + 95, + 96, + 97, + 98, + 99, + 100, + 101, + 102, + 103, + 104, + 105, + 106, + 107, + 108, + 109, + 110, + 111, + 112, + 113, + 114, + 115, + 116, + 117, + 118, + 119, + 120, + 121, + 122, + 123, + 124, + 125, + 126, + 127 + ] + }, + "SAS_MIN_COM": { + "digits": 6, + "encoding": [ + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15, + 16, + 17, + 18, + 19, + 20, + 21, + 22, + 23, + 24, + 25, + 26, + 27, + 28, + 29, + 30, + 31, + 32, + 33, + 34, + 35, + 36, + 37, + 38, + 39, + 40, + 41, + 42, + 43, + 44, + 45, + 46, + 47, + 48, + 49, + 50, + 51, + 52, + 53, + 54, + 55, + 56, + 57, + 58, + 59, + 60, + 61, + 62, + 63 + ], + "type": "INT", + "values": [ + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15, + 16, + 17, + 18, + 19, + 20, + 21, + 22, + 23, + 24, + 25, + 26, + 27, + 28, + 29, + 30, + 31, + 32, + 33, + 34, + 35, + 36, + 37, + 38, + 39, + 40, + 41, + 42, + 43, + 44, + 45, + 46, + 47, + 48, + 49, + 50, + 51, + 52, + 53, + 54, + 55, + 56, + 57, + 58, + 59, + 60, + 61, + 62, + 63 + ] + }, + "SATA_BURST_SEQ_LEN": { + "digits": 4, + "type": "BIN", + "values": [ + 15 + ] + }, + "SATA_BURST_VAL": { + "digits": 3, + "type": "BIN", + "values": [ + 7 + ] + }, + "SATA_EIDLE_VAL": { + "digits": 3, + "type": "BIN", + "values": [ + 7 + ] + }, + "SATA_MAX_BURST": { + "digits": 6, + "encoding": [ + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15, + 16, + 17, + 18, + 19, + 20, + 21, + 22, + 23, + 24, + 25, + 26, + 27, + 28, + 29, + 30, + 31, + 32, + 33, + 34, + 35, + 36, + 37, + 38, + 39, + 40, + 41, + 42, + 43, + 44, + 45, + 46, + 47, + 48, + 49, + 50, + 51, + 52, + 53, + 54, + 55, + 56, + 57, + 58, + 59, + 60, + 61, + 62, + 63 + ], + "type": "INT", + "values": [ + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15, + 16, + 17, + 18, + 19, + 20, + 21, + 22, + 23, + 24, + 25, + 26, + 27, + 28, + 29, + 30, + 31, + 32, + 33, + 34, + 35, + 36, + 37, + 38, + 39, + 40, + 41, + 42, + 43, + 44, + 45, + 46, + 47, + 48, + 49, + 50, + 51, + 52, + 53, + 54, + 55, + 56, + 57, + 58, + 59, + 60, + 61, + 62, + 63 + ] + }, + "SATA_MAX_INIT": { + "digits": 6, + "encoding": [ + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15, + 16, + 17, + 18, + 19, + 20, + 21, + 22, + 23, + 24, + 25, + 26, + 27, + 28, + 29, + 30, + 31, + 32, + 33, + 34, + 35, + 36, + 37, + 38, + 39, + 40, + 41, + 42, + 43, + 44, + 45, + 46, + 47, + 48, + 49, + 50, + 51, + 52, + 53, + 54, + 55, + 56, + 57, + 58, + 59, + 60, + 61, + 62, + 63 + ], + "type": "INT", + "values": [ + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15, + 16, + 17, + 18, + 19, + 20, + 21, + 22, + 23, + 24, + 25, + 26, + 27, + 28, + 29, + 30, + 31, + 32, + 33, + 34, + 35, + 36, + 37, + 38, + 39, + 40, + 41, + 42, + 43, + 44, + 45, + 46, + 47, + 48, + 49, + 50, + 51, + 52, + 53, + 54, + 55, + 56, + 57, + 58, + 59, + 60, + 61, + 62, + 63 + ] + }, + "SATA_MAX_WAKE": { + "digits": 6, + "encoding": [ + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15, + 16, + 17, + 18, + 19, + 20, + 21, + 22, + 23, + 24, + 25, + 26, + 27, + 28, + 29, + 30, + 31, + 32, + 33, + 34, + 35, + 36, + 37, + 38, + 39, + 40, + 41, + 42, + 43, + 44, + 45, + 46, + 47, + 48, + 49, + 50, + 51, + 52, + 53, + 54, + 55, + 56, + 57, + 58, + 59, + 60, + 61, + 62, + 63 + ], + "type": "INT", + "values": [ + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15, + 16, + 17, + 18, + 19, + 20, + 21, + 22, + 23, + 24, + 25, + 26, + 27, + 28, + 29, + 30, + 31, + 32, + 33, + 34, + 35, + 36, + 37, + 38, + 39, + 40, + 41, + 42, + 43, + 44, + 45, + 46, + 47, + 48, + 49, + 50, + 51, + 52, + 53, + 54, + 55, + 56, + 57, + 58, + 59, + 60, + 61, + 62, + 63 + ] + }, + "SATA_MIN_BURST": { + "digits": 6, + "encoding": [ + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15, + 16, + 17, + 18, + 19, + 20, + 21, + 22, + 23, + 24, + 25, + 26, + 27, + 28, + 29, + 30, + 31, + 32, + 33, + 34, + 35, + 36, + 37, + 38, + 39, + 40, + 41, + 42, + 43, + 44, + 45, + 46, + 47, + 48, + 49, + 50, + 51, + 52, + 53, + 54, + 55, + 56, + 57, + 58, + 59, + 60, + 61 + ], + "type": "INT", + "values": [ + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15, + 16, + 17, + 18, + 19, + 20, + 21, + 22, + 23, + 24, + 25, + 26, + 27, + 28, + 29, + 30, + 31, + 32, + 33, + 34, + 35, + 36, + 37, + 38, + 39, + 40, + 41, + 42, + 43, + 44, + 45, + 46, + 47, + 48, + 49, + 50, + 51, + 52, + 53, + 54, + 55, + 56, + 57, + 58, + 59, + 60, + 61 + ] + }, + "SATA_MIN_INIT": { + "digits": 6, + "encoding": [ + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15, + 16, + 17, + 18, + 19, + 20, + 21, + 22, + 23, + 24, + 25, + 26, + 27, + 28, + 29, + 30, + 31, + 32, + 33, + 34, + 35, + 36, + 37, + 38, + 39, + 40, + 41, + 42, + 43, + 44, + 45, + 46, + 47, + 48, + 49, + 50, + 51, + 52, + 53, + 54, + 55, + 56, + 57, + 58, + 59, + 60, + 61, + 62, + 63 + ], + "type": "INT", + "values": [ + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15, + 16, + 17, + 18, + 19, + 20, + 21, + 22, + 23, + 24, + 25, + 26, + 27, + 28, + 29, + 30, + 31, + 32, + 33, + 34, + 35, + 36, + 37, + 38, + 39, + 40, + 41, + 42, + 43, + 44, + 45, + 46, + 47, + 48, + 49, + 50, + 51, + 52, + 53, + 54, + 55, + 56, + 57, + 58, + 59, + 60, + 61, + 62, + 63 + ] + }, + "SATA_MIN_WAKE": { + "digits": 6, + "encoding": [ + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15, + 16, + 17, + 18, + 19, + 20, + 21, + 22, + 23, + 24, + 25, + 26, + 27, + 28, + 29, + 30, + 31, + 32, + 33, + 34, + 35, + 36, + 37, + 38, + 39, + 40, + 41, + 42, + 43, + 44, + 45, + 46, + 47, + 48, + 49, + 50, + 51, + 52, + 53, + 54, + 55, + 56, + 57, + 58, + 59, + 60, + 61, + 62, + 63 + ], + "type": "INT", + "values": [ + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15, + 16, + 17, + 18, + 19, + 20, + 21, + 22, + 23, + 24, + 25, + 26, + 27, + 28, + 29, + 30, + 31, + 32, + 33, + 34, + 35, + 36, + 37, + 38, + 39, + 40, + 41, + 42, + 43, + 44, + 45, + 46, + 47, + 48, + 49, + 50, + 51, + 52, + 53, + 54, + 55, + 56, + 57, + 58, + 59, + 60, + 61, + 62, + 63 + ] + }, + "SATA_PLL_CFG": { + "digits": 2, + "type": "STR", + "values": [ + "VCO_3000MHZ", + "VCO_1500MHZ", + "VCO_750MHZ" + ] + }, + "SHOW_REALIGN_COMMA": { + "digits": 1, + "type": "BOOL", + "values": [ + "FALSE", + "TRUE" + ] + }, + "TERM_RCAL_CFG": { + "digits": 15, + "type": "BIN", + "values": [ + 32767 + ] + }, + "TERM_RCAL_OVRD": { + "digits": 3, + "type": "BIN", + "values": [ + 7 + ] + }, + "TRANS_TIME_RATE": { + "digits": 8, + "type": "BIN", + "values": [ + 255 + ] + }, + "TST_RSV": { + "digits": 32, + "type": "BIN", + "values": [ + 4294836225 + ] + }, + "TXBUF_EN": { + "digits": 1, + "type": "BOOL", + "values": [ + "FALSE", + "TRUE" + ] + }, + "TXBUF_RESET_ON_RATE_CHANGE": { + "digits": 1, + "type": "BOOL", + "values": [ + "FALSE", + "TRUE" + ] + }, + "TXDLY_CFG": { + "digits": 16, + "type": "BIN", + "values": [ + 65535 + ] + }, + "TXDLY_LCFG": { + "digits": 9, + "type": "BIN", + "values": [ + 511 + ] + }, + "TXDLY_TAP_CFG": { + "digits": 16, + "type": "BIN", + "values": [ + 65535 + ] + }, + "TXGEARBOX_EN": { + "digits": 1, + "type": "BOOL", + "values": [ + "FALSE", + "TRUE" + ] + }, + "TXOOB_CFG": { + "digits": 1, + "type": "BIN", + "values": [ + 1 + ] + }, + "TXOUT_DIV": { + "digits": 3, + "encoding": [ + 0, + 1, + 2, + 3 + ], + "type": "INT", + "values": [ + 1, + 2, + 4, + 8 + ] + }, + "TXPCSRESET_TIME": { + "digits": 5, + "type": "BIN", + "values": [ + 31 + ] + }, + "TXPHDLY_CFG": { + "digits": 24, + "type": "BIN", + "values": [ + 16711425 + ] + }, + "TXPH_CFG": { + "digits": 16, + "type": "BIN", + "values": [ + 65535 + ] + }, + "TXPH_MONITOR_SEL": { + "digits": 5, + "type": "BIN", + "values": [ + 31 + ] + }, + "TXPI_CFG0": { + "digits": 2, + "type": "BIN", + "values": [ + 3 + ] + }, + "TXPI_CFG1": { + "digits": 2, + "type": "BIN", + "values": [ + 3 + ] + }, + "TXPI_CFG2": { + "digits": 2, + "type": "BIN", + "values": [ + 3 + ] + }, + "TXPI_CFG3": { + "digits": 1, + "type": "BIN", + "values": [ + 1 + ] + }, + "TXPI_CFG4": { + "digits": 1, + "type": "BIN", + "values": [ + 1 + ] + }, + "TXPI_CFG5": { + "digits": 3, + "type": "BIN", + "values": [ + 7 + ] + }, + "TXPI_GREY_SEL": { + "digits": 1, + "type": "BIN", + "values": [ + 1 + ] + }, + "TXPI_INVSTROBE_SEL": { + "digits": 1, + "type": "BIN", + "values": [ + 1 + ] + }, + "TXPI_PPMCLK_SEL": { + "digits": 1, + "type": "STR", + "values": [ + "TXUSRCLK", + "TXUSRCLK2" + ] + }, + "TXPI_PPM_CFG": { + "digits": 8, + "type": "BIN", + "values": [ + 255 + ] + }, + "TXPI_SYNFREQ_PPM": { + "digits": 3, + "type": "BIN", + "values": [ + 7 + ] + }, + "TXPMARESET_TIME": { + "digits": 5, + "type": "BIN", + "values": [ + 31 + ] + }, + "TXSYNC_MULTILANE": { + "digits": 1, + "type": "BIN", + "values": [ + 1 + ] + }, + "TXSYNC_OVRD": { + "digits": 1, + "type": "BIN", + "values": [ + 1 + ] + }, + "TXSYNC_SKIP_DA": { + "digits": 1, + "type": "BIN", + "values": [ + 1 + ] + }, + "TX_CLK25_DIV": { + "digits": 5, + "encoding": [ + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15, + 16, + 17, + 18, + 19, + 20, + 21, + 22, + 23, + 24, + 25, + 26, + 27, + 28, + 29, + 30, + 31 + ], + "type": "INT", + "values": [ + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15, + 16, + 17, + 18, + 19, + 20, + 21, + 22, + 23, + 24, + 25, + 26, + 27, + 28, + 29, + 30, + 31, + 32 + ] + }, + "TX_CLKMUX_EN": { + "digits": 1, + "type": "BIN", + "values": [ + 1 + ] + }, + "TX_DATA_WIDTH": { + "digits": 3, + "encoding": [ + 2, + 3, + 4, + 5 + ], + "type": "INT", + "values": [ + 16, + 20, + 32, + 40 + ] + }, + "TX_DEEMPH0": { + "digits": 6, + "type": "BIN", + "values": [ + 63 + ] + }, + "TX_DEEMPH1": { + "digits": 6, + "type": "BIN", + "values": [ + 63 + ] + }, + "TX_DRIVE_MODE": { + "digits": 1, + "type": "STR", + "values": [ + "DIRECT", + "PIPE" + ] + }, + "TX_EIDLE_ASSERT_DELAY": { + "digits": 3, + "type": "BIN", + "values": [ + 7 + ] + }, + "TX_EIDLE_DEASSERT_DELAY": { + "digits": 3, + "type": "BIN", + "values": [ + 7 + ] + }, + "TX_LOOPBACK_DRIVE_HIZ": { + "digits": 1, + "type": "BOOL", + "values": [ + "FALSE", + "TRUE" + ] + }, + "TX_MAINCURSOR_SEL": { + "digits": 1, + "type": "BIN", + "values": [ + 1 + ] + }, + "TX_MARGIN_FULL_0": { + "digits": 7, + "type": "BIN", + "values": [ + 127 + ] + }, + "TX_MARGIN_FULL_1": { + "digits": 7, + "type": "BIN", + "values": [ + 127 + ] + }, + "TX_MARGIN_FULL_2": { + "digits": 7, + "type": "BIN", + "values": [ + 127 + ] + }, + "TX_MARGIN_FULL_3": { + "digits": 7, + "type": "BIN", + "values": [ + 127 + ] + }, + "TX_MARGIN_FULL_4": { + "digits": 7, + "type": "BIN", + "values": [ + 127 + ] + }, + "TX_MARGIN_LOW_0": { + "digits": 7, + "type": "BIN", + "values": [ + 127 + ] + }, + "TX_MARGIN_LOW_1": { + "digits": 7, + "type": "BIN", + "values": [ + 127 + ] + }, + "TX_MARGIN_LOW_2": { + "digits": 7, + "type": "BIN", + "values": [ + 127 + ] + }, + "TX_MARGIN_LOW_3": { + "digits": 7, + "type": "BIN", + "values": [ + 127 + ] + }, + "TX_MARGIN_LOW_4": { + "digits": 7, + "type": "BIN", + "values": [ + 127 + ] + }, + "TX_PREDRIVER_MODE": { + "digits": 1, + "type": "BIN", + "values": [ + 1 + ] + }, + "TX_RXDETECT_CFG": { + "digits": 14, + "type": "BIN", + "values": [ + 16383 + ] + }, + "TX_RXDETECT_REF": { + "digits": 3, + "type": "BIN", + "values": [ + 7 + ] + }, + "TX_XCLK_SEL": { + "digits": 1, + "type": "STR", + "values": [ + "TXOUT", + "TXUSR" + ] + }, + "UCODEER_CLR": { + "digits": 1, + "type": "BIN", + "values": [ + 1 + ] + }, + "USE_PCS_CLK_PHASE_SEL": { + "digits": 1, + "type": "BIN", + "values": [ + 1 + ] + } +} diff --git a/artix7/cells_data/gtpe2_channel_ports.json b/artix7/cells_data/gtpe2_channel_ports.json new file mode 100644 index 0000000..063f572 --- /dev/null +++ b/artix7/cells_data/gtpe2_channel_ports.json @@ -0,0 +1,910 @@ +{ + "CFGRESET": { + "direction": "input", + "width": 1 + }, + "CLKRSVD0": { + "direction": "input", + "width": 1 + }, + "CLKRSVD1": { + "direction": "input", + "width": 1 + }, + "DMONFIFORESET": { + "direction": "input", + "width": 1 + }, + "DMONITORCLK": { + "direction": "input", + "width": 1 + }, + "DMONITOROUT": { + "direction": "output", + "width": 15 + }, + "DRPADDR": { + "direction": "input", + "width": 9 + }, + "DRPCLK": { + "direction": "input", + "width": 1 + }, + "DRPDI": { + "direction": "input", + "width": 16 + }, + "DRPDO": { + "direction": "output", + "width": 16 + }, + "DRPEN": { + "direction": "input", + "width": 1 + }, + "DRPRDY": { + "direction": "output", + "width": 1 + }, + "DRPWE": { + "direction": "input", + "width": 1 + }, + "EYESCANDATAERROR": { + "direction": "output", + "width": 1 + }, + "EYESCANMODE": { + "direction": "input", + "width": 1 + }, + "EYESCANRESET": { + "direction": "input", + "width": 1 + }, + "EYESCANTRIGGER": { + "direction": "input", + "width": 1 + }, + "GTPRXN": { + "direction": "input", + "width": 1 + }, + "GTPRXP": { + "direction": "input", + "width": 1 + }, + "GTPTXN": { + "direction": "output", + "width": 1 + }, + "GTPTXP": { + "direction": "output", + "width": 1 + }, + "GTRESETSEL": { + "direction": "input", + "width": 1 + }, + "GTRSVD": { + "direction": "input", + "width": 16 + }, + "GTRXRESET": { + "direction": "input", + "width": 1 + }, + "GTTXRESET": { + "direction": "input", + "width": 1 + }, + "LOOPBACK": { + "direction": "input", + "width": 3 + }, + "PCSRSVDIN": { + "direction": "input", + "width": 16 + }, + "PCSRSVDOUT": { + "direction": "output", + "width": 16 + }, + "PHYSTATUS": { + "direction": "output", + "width": 1 + }, + "PLL0CLK": { + "direction": "input", + "width": 1 + }, + "PLL0REFCLK": { + "direction": "input", + "width": 1 + }, + "PLL1CLK": { + "direction": "input", + "width": 1 + }, + "PLL1REFCLK": { + "direction": "input", + "width": 1 + }, + "PMARSVDIN0": { + "direction": "input", + "width": 1 + }, + "PMARSVDIN1": { + "direction": "input", + "width": 1 + }, + "PMARSVDIN2": { + "direction": "input", + "width": 1 + }, + "PMARSVDIN3": { + "direction": "input", + "width": 1 + }, + "PMARSVDIN4": { + "direction": "input", + "width": 1 + }, + "PMARSVDOUT0": { + "direction": "output", + "width": 1 + }, + "PMARSVDOUT1": { + "direction": "output", + "width": 1 + }, + "RESETOVRD": { + "direction": "input", + "width": 1 + }, + "RX8B10BEN": { + "direction": "input", + "width": 1 + }, + "RXADAPTSELTEST": { + "direction": "input", + "width": 14 + }, + "RXBUFRESET": { + "direction": "input", + "width": 1 + }, + "RXBUFSTATUS": { + "direction": "output", + "width": 3 + }, + "RXBYTEISALIGNED": { + "direction": "output", + "width": 1 + }, + "RXBYTEREALIGN": { + "direction": "output", + "width": 1 + }, + "RXCDRFREQRESET": { + "direction": "input", + "width": 1 + }, + "RXCDRHOLD": { + "direction": "input", + "width": 1 + }, + "RXCDRLOCK": { + "direction": "output", + "width": 1 + }, + "RXCDROVRDEN": { + "direction": "input", + "width": 1 + }, + "RXCDRRESET": { + "direction": "input", + "width": 1 + }, + "RXCDRRESETRSV": { + "direction": "input", + "width": 1 + }, + "RXCHANBONDSEQ": { + "direction": "output", + "width": 1 + }, + "RXCHANISALIGNED": { + "direction": "output", + "width": 1 + }, + "RXCHANREALIGN": { + "direction": "output", + "width": 1 + }, + "RXCHARISCOMMA": { + "direction": "output", + "width": 4 + }, + "RXCHARISK": { + "direction": "output", + "width": 4 + }, + "RXCHBONDEN": { + "direction": "input", + "width": 1 + }, + "RXCHBONDI": { + "direction": "input", + "width": 4 + }, + "RXCHBONDLEVEL": { + "direction": "input", + "width": 3 + }, + "RXCHBONDMASTER": { + "direction": "input", + "width": 1 + }, + "RXCHBONDO": { + "direction": "output", + "width": 4 + }, + "RXCHBONDSLAVE": { + "direction": "input", + "width": 1 + }, + "RXCLKCORCNT": { + "direction": "output", + "width": 2 + }, + "RXCOMINITDET": { + "direction": "output", + "width": 1 + }, + "RXCOMMADET": { + "direction": "output", + "width": 1 + }, + "RXCOMMADETEN": { + "direction": "input", + "width": 1 + }, + "RXCOMSASDET": { + "direction": "output", + "width": 1 + }, + "RXCOMWAKEDET": { + "direction": "output", + "width": 1 + }, + "RXDATA": { + "direction": "output", + "width": 32 + }, + "RXDATAVALID": { + "direction": "output", + "width": 2 + }, + "RXDDIEN": { + "direction": "input", + "width": 1 + }, + "RXDFEXYDEN": { + "direction": "input", + "width": 1 + }, + "RXDISPERR": { + "direction": "output", + "width": 4 + }, + "RXDLYBYPASS": { + "direction": "input", + "width": 1 + }, + "RXDLYEN": { + "direction": "input", + "width": 1 + }, + "RXDLYOVRDEN": { + "direction": "input", + "width": 1 + }, + "RXDLYSRESET": { + "direction": "input", + "width": 1 + }, + "RXDLYSRESETDONE": { + "direction": "output", + "width": 1 + }, + "RXELECIDLE": { + "direction": "output", + "width": 1 + }, + "RXELECIDLEMODE": { + "direction": "input", + "width": 2 + }, + "RXGEARBOXSLIP": { + "direction": "input", + "width": 1 + }, + "RXHEADER": { + "direction": "output", + "width": 3 + }, + "RXHEADERVALID": { + "direction": "output", + "width": 1 + }, + "RXLPMHFHOLD": { + "direction": "input", + "width": 1 + }, + "RXLPMHFOVRDEN": { + "direction": "input", + "width": 1 + }, + "RXLPMLFHOLD": { + "direction": "input", + "width": 1 + }, + "RXLPMLFOVRDEN": { + "direction": "input", + "width": 1 + }, + "RXLPMOSINTNTRLEN": { + "direction": "input", + "width": 1 + }, + "RXLPMRESET": { + "direction": "input", + "width": 1 + }, + "RXMCOMMAALIGNEN": { + "direction": "input", + "width": 1 + }, + "RXNOTINTABLE": { + "direction": "output", + "width": 4 + }, + "RXOOBRESET": { + "direction": "input", + "width": 1 + }, + "RXOSCALRESET": { + "direction": "input", + "width": 1 + }, + "RXOSHOLD": { + "direction": "input", + "width": 1 + }, + "RXOSINTCFG": { + "direction": "input", + "width": 4 + }, + "RXOSINTDONE": { + "direction": "output", + "width": 1 + }, + "RXOSINTEN": { + "direction": "input", + "width": 1 + }, + "RXOSINTHOLD": { + "direction": "input", + "width": 1 + }, + "RXOSINTID0": { + "direction": "input", + "width": 4 + }, + "RXOSINTNTRLEN": { + "direction": "input", + "width": 1 + }, + "RXOSINTOVRDEN": { + "direction": "input", + "width": 1 + }, + "RXOSINTPD": { + "direction": "input", + "width": 1 + }, + "RXOSINTSTARTED": { + "direction": "output", + "width": 1 + }, + "RXOSINTSTROBE": { + "direction": "input", + "width": 1 + }, + "RXOSINTSTROBEDONE": { + "direction": "output", + "width": 1 + }, + "RXOSINTSTROBESTARTED": { + "direction": "output", + "width": 1 + }, + "RXOSINTTESTOVRDEN": { + "direction": "input", + "width": 1 + }, + "RXOSOVRDEN": { + "direction": "input", + "width": 1 + }, + "RXOUTCLK": { + "direction": "output", + "width": 1 + }, + "RXOUTCLKFABRIC": { + "direction": "output", + "width": 1 + }, + "RXOUTCLKPCS": { + "direction": "output", + "width": 1 + }, + "RXOUTCLKSEL": { + "direction": "input", + "width": 3 + }, + "RXPCOMMAALIGNEN": { + "direction": "input", + "width": 1 + }, + "RXPCSRESET": { + "direction": "input", + "width": 1 + }, + "RXPD": { + "direction": "input", + "width": 2 + }, + "RXPHALIGN": { + "direction": "input", + "width": 1 + }, + "RXPHALIGNDONE": { + "direction": "output", + "width": 1 + }, + "RXPHALIGNEN": { + "direction": "input", + "width": 1 + }, + "RXPHDLYPD": { + "direction": "input", + "width": 1 + }, + "RXPHDLYRESET": { + "direction": "input", + "width": 1 + }, + "RXPHMONITOR": { + "direction": "output", + "width": 5 + }, + "RXPHOVRDEN": { + "direction": "input", + "width": 1 + }, + "RXPHSLIPMONITOR": { + "direction": "output", + "width": 5 + }, + "RXPMARESET": { + "direction": "input", + "width": 1 + }, + "RXPMARESETDONE": { + "direction": "output", + "width": 1 + }, + "RXPOLARITY": { + "direction": "input", + "width": 1 + }, + "RXPRBSCNTRESET": { + "direction": "input", + "width": 1 + }, + "RXPRBSERR": { + "direction": "output", + "width": 1 + }, + "RXPRBSSEL": { + "direction": "input", + "width": 3 + }, + "RXRATE": { + "direction": "input", + "width": 3 + }, + "RXRATEDONE": { + "direction": "output", + "width": 1 + }, + "RXRATEMODE": { + "direction": "input", + "width": 1 + }, + "RXRESETDONE": { + "direction": "output", + "width": 1 + }, + "RXSLIDE": { + "direction": "input", + "width": 1 + }, + "RXSTARTOFSEQ": { + "direction": "output", + "width": 2 + }, + "RXSTATUS": { + "direction": "output", + "width": 3 + }, + "RXSYNCALLIN": { + "direction": "input", + "width": 1 + }, + "RXSYNCDONE": { + "direction": "output", + "width": 1 + }, + "RXSYNCIN": { + "direction": "input", + "width": 1 + }, + "RXSYNCMODE": { + "direction": "input", + "width": 1 + }, + "RXSYNCOUT": { + "direction": "output", + "width": 1 + }, + "RXSYSCLKSEL": { + "direction": "input", + "width": 2 + }, + "RXUSERRDY": { + "direction": "input", + "width": 1 + }, + "RXUSRCLK": { + "direction": "input", + "width": 1 + }, + "RXUSRCLK2": { + "direction": "input", + "width": 1 + }, + "RXVALID": { + "direction": "output", + "width": 1 + }, + "SETERRSTATUS": { + "direction": "input", + "width": 1 + }, + "SIGVALIDCLK": { + "direction": "input", + "width": 1 + }, + "TSTIN": { + "direction": "input", + "width": 20 + }, + "TX8B10BBYPASS": { + "direction": "input", + "width": 4 + }, + "TX8B10BEN": { + "direction": "input", + "width": 1 + }, + "TXBUFDIFFCTRL": { + "direction": "input", + "width": 3 + }, + "TXBUFSTATUS": { + "direction": "output", + "width": 2 + }, + "TXCHARDISPMODE": { + "direction": "input", + "width": 4 + }, + "TXCHARDISPVAL": { + "direction": "input", + "width": 4 + }, + "TXCHARISK": { + "direction": "input", + "width": 4 + }, + "TXCOMFINISH": { + "direction": "output", + "width": 1 + }, + "TXCOMINIT": { + "direction": "input", + "width": 1 + }, + "TXCOMSAS": { + "direction": "input", + "width": 1 + }, + "TXCOMWAKE": { + "direction": "input", + "width": 1 + }, + "TXDATA": { + "direction": "input", + "width": 32 + }, + "TXDEEMPH": { + "direction": "input", + "width": 1 + }, + "TXDETECTRX": { + "direction": "input", + "width": 1 + }, + "TXDIFFCTRL": { + "direction": "input", + "width": 4 + }, + "TXDIFFPD": { + "direction": "input", + "width": 1 + }, + "TXDLYBYPASS": { + "direction": "input", + "width": 1 + }, + "TXDLYEN": { + "direction": "input", + "width": 1 + }, + "TXDLYHOLD": { + "direction": "input", + "width": 1 + }, + "TXDLYOVRDEN": { + "direction": "input", + "width": 1 + }, + "TXDLYSRESET": { + "direction": "input", + "width": 1 + }, + "TXDLYSRESETDONE": { + "direction": "output", + "width": 1 + }, + "TXDLYUPDOWN": { + "direction": "input", + "width": 1 + }, + "TXELECIDLE": { + "direction": "input", + "width": 1 + }, + "TXGEARBOXREADY": { + "direction": "output", + "width": 1 + }, + "TXHEADER": { + "direction": "input", + "width": 3 + }, + "TXINHIBIT": { + "direction": "input", + "width": 1 + }, + "TXMAINCURSOR": { + "direction": "input", + "width": 7 + }, + "TXMARGIN": { + "direction": "input", + "width": 3 + }, + "TXOUTCLK": { + "direction": "output", + "width": 1 + }, + "TXOUTCLKFABRIC": { + "direction": "output", + "width": 1 + }, + "TXOUTCLKPCS": { + "direction": "output", + "width": 1 + }, + "TXOUTCLKSEL": { + "direction": "input", + "width": 3 + }, + "TXPCSRESET": { + "direction": "input", + "width": 1 + }, + "TXPD": { + "direction": "input", + "width": 2 + }, + "TXPDELECIDLEMODE": { + "direction": "input", + "width": 1 + }, + "TXPHALIGN": { + "direction": "input", + "width": 1 + }, + "TXPHALIGNDONE": { + "direction": "output", + "width": 1 + }, + "TXPHALIGNEN": { + "direction": "input", + "width": 1 + }, + "TXPHDLYPD": { + "direction": "input", + "width": 1 + }, + "TXPHDLYRESET": { + "direction": "input", + "width": 1 + }, + "TXPHDLYTSTCLK": { + "direction": "input", + "width": 1 + }, + "TXPHINIT": { + "direction": "input", + "width": 1 + }, + "TXPHINITDONE": { + "direction": "output", + "width": 1 + }, + "TXPHOVRDEN": { + "direction": "input", + "width": 1 + }, + "TXPIPPMEN": { + "direction": "input", + "width": 1 + }, + "TXPIPPMOVRDEN": { + "direction": "input", + "width": 1 + }, + "TXPIPPMPD": { + "direction": "input", + "width": 1 + }, + "TXPIPPMSEL": { + "direction": "input", + "width": 1 + }, + "TXPIPPMSTEPSIZE": { + "direction": "input", + "width": 5 + }, + "TXPISOPD": { + "direction": "input", + "width": 1 + }, + "TXPMARESET": { + "direction": "input", + "width": 1 + }, + "TXPMARESETDONE": { + "direction": "output", + "width": 1 + }, + "TXPOLARITY": { + "direction": "input", + "width": 1 + }, + "TXPOSTCURSOR": { + "direction": "input", + "width": 5 + }, + "TXPOSTCURSORINV": { + "direction": "input", + "width": 1 + }, + "TXPRBSFORCEERR": { + "direction": "input", + "width": 1 + }, + "TXPRBSSEL": { + "direction": "input", + "width": 3 + }, + "TXPRECURSOR": { + "direction": "input", + "width": 5 + }, + "TXPRECURSORINV": { + "direction": "input", + "width": 1 + }, + "TXRATE": { + "direction": "input", + "width": 3 + }, + "TXRATEDONE": { + "direction": "output", + "width": 1 + }, + "TXRATEMODE": { + "direction": "input", + "width": 1 + }, + "TXRESETDONE": { + "direction": "output", + "width": 1 + }, + "TXSEQUENCE": { + "direction": "input", + "width": 7 + }, + "TXSTARTSEQ": { + "direction": "input", + "width": 1 + }, + "TXSWING": { + "direction": "input", + "width": 1 + }, + "TXSYNCALLIN": { + "direction": "input", + "width": 1 + }, + "TXSYNCDONE": { + "direction": "output", + "width": 1 + }, + "TXSYNCIN": { + "direction": "input", + "width": 1 + }, + "TXSYNCMODE": { + "direction": "input", + "width": 1 + }, + "TXSYNCOUT": { + "direction": "output", + "width": 1 + }, + "TXSYSCLKSEL": { + "direction": "input", + "width": 2 + }, + "TXUSERRDY": { + "direction": "input", + "width": 1 + }, + "TXUSRCLK": { + "direction": "input", + "width": 1 + }, + "TXUSRCLK2": { + "direction": "input", + "width": 1 + } +} diff --git a/artix7/cells_data/gtpe2_common_attrs.json b/artix7/cells_data/gtpe2_common_attrs.json new file mode 100644 index 0000000..73df480 --- /dev/null +++ b/artix7/cells_data/gtpe2_common_attrs.json @@ -0,0 +1,177 @@ +{ + "BIAS_CFG": { + "digits": 64, + "type": "BIN", + "values": [ + 18445618199572250625 + ] + }, + "COMMON_CFG": { + "digits": 32, + "type": "BIN", + "values": [ + 4294836225 + ] + }, + "PLL0_CFG": { + "digits": 27, + "type": "BIN", + "values": [ + 134150145 + ] + }, + "PLL0_DMON_CFG": { + "digits": 1, + "type": "BIN", + "values": [ + 1 + ] + }, + "PLL0_FBDIV": { + "digits": 6, + "encoding": [ + 16, + 0, + 1, + 2, + 3 + ], + "type": "INT", + "values": [ + 1, + 2, + 3, + 4, + 5 + ] + }, + "PLL0_FBDIV_45": { + "digits": 1, + "encoding": [ + 0, + 1 + ], + "type": "INT", + "values": [ + 4, + 5 + ] + }, + "PLL0_INIT_CFG": { + "digits": 24, + "type": "BIN", + "values": [ + 16711425 + ] + }, + "PLL0_LOCK_CFG": { + "digits": 9, + "type": "BIN", + "values": [ + 511 + ] + }, + "PLL0_REFCLK_DIV": { + "digits": 5, + "encoding": [ + 16, + 0 + ], + "type": "INT", + "values": [ + 1, + 2 + ] + }, + "PLL1_CFG": { + "digits": 27, + "type": "BIN", + "values": [ + 134150145 + ] + }, + "PLL1_DMON_CFG": { + "digits": 1, + "type": "BIN", + "values": [ + 1 + ] + }, + "PLL1_FBDIV": { + "digits": 6, + "encoding": [ + 16, + 0, + 1, + 2, + 3 + ], + "type": "INT", + "values": [ + 1, + 2, + 3, + 4, + 5 + ] + }, + "PLL1_FBDIV_45": { + "digits": 1, + "encoding": [ + 0, + 1 + ], + "type": "INT", + "values": [ + 4, + 5 + ] + }, + "PLL1_INIT_CFG": { + "digits": 24, + "type": "BIN", + "values": [ + 16711425 + ] + }, + "PLL1_LOCK_CFG": { + "digits": 9, + "type": "BIN", + "values": [ + 511 + ] + }, + "PLL1_REFCLK_DIV": { + "digits": 5, + "encoding": [ + 16, + 0 + ], + "type": "INT", + "values": [ + 1, + 2 + ] + }, + "PLL_CLKOUT_CFG": { + "digits": 8, + "type": "BIN", + "values": [ + 255 + ] + }, + "RSVD_ATTR0": { + "digits": 16, + "type": "BIN", + "values": [ + 65535 + ] + }, + "RSVD_ATTR1": { + "digits": 16, + "type": "BIN", + "values": [ + 65535 + ] + } +} diff --git a/artix7/cells_data/gtpe2_common_ports.json b/artix7/cells_data/gtpe2_common_ports.json new file mode 100644 index 0000000..eebd685 --- /dev/null +++ b/artix7/cells_data/gtpe2_common_ports.json @@ -0,0 +1,186 @@ +{ + "BGBYPASSB": { + "direction": "input", + "width": 1 + }, + "BGMONITORENB": { + "direction": "input", + "width": 1 + }, + "BGPDB": { + "direction": "input", + "width": 1 + }, + "BGRCALOVRD": { + "direction": "input", + "width": 5 + }, + "BGRCALOVRDENB": { + "direction": "input", + "width": 1 + }, + "DMONITOROUT": { + "direction": "output", + "width": 8 + }, + "DRPADDR": { + "direction": "input", + "width": 8 + }, + "DRPCLK": { + "direction": "input", + "width": 1 + }, + "DRPDI": { + "direction": "input", + "width": 16 + }, + "DRPDO": { + "direction": "output", + "width": 16 + }, + "DRPEN": { + "direction": "input", + "width": 1 + }, + "DRPRDY": { + "direction": "output", + "width": 1 + }, + "DRPWE": { + "direction": "input", + "width": 1 + }, + "GTGREFCLK0": { + "direction": "input", + "width": 1 + }, + "GTGREFCLK1": { + "direction": "input", + "width": 1 + }, + "GTREFCLK0": { + "direction": "input", + "width": 1 + }, + "GTREFCLK1": { + "direction": "input", + "width": 1 + }, + "GTWESTREFCLK0": { + "direction": "input", + "width": 1 + }, + "GTWESTREFCLK1": { + "direction": "input", + "width": 1 + }, + "PLL0FBCLKLOST": { + "direction": "output", + "width": 1 + }, + "PLL0LOCK": { + "direction": "output", + "width": 1 + }, + "PLL0LOCKDETCLK": { + "direction": "input", + "width": 1 + }, + "PLL0LOCKEN": { + "direction": "input", + "width": 1 + }, + "PLL0OUTCLK": { + "direction": "output", + "width": 1 + }, + "PLL0OUTREFCLK": { + "direction": "output", + "width": 1 + }, + "PLL0PD": { + "direction": "input", + "width": 1 + }, + "PLL0REFCLKLOST": { + "direction": "output", + "width": 1 + }, + "PLL0REFCLKSEL": { + "direction": "input", + "width": 3 + }, + "PLL0RESET": { + "direction": "input", + "width": 1 + }, + "PLL1FBCLKLOST": { + "direction": "output", + "width": 1 + }, + "PLL1LOCK": { + "direction": "output", + "width": 1 + }, + "PLL1LOCKDETCLK": { + "direction": "input", + "width": 1 + }, + "PLL1LOCKEN": { + "direction": "input", + "width": 1 + }, + "PLL1OUTCLK": { + "direction": "output", + "width": 1 + }, + "PLL1OUTREFCLK": { + "direction": "output", + "width": 1 + }, + "PLL1PD": { + "direction": "input", + "width": 1 + }, + "PLL1REFCLKLOST": { + "direction": "output", + "width": 1 + }, + "PLL1REFCLKSEL": { + "direction": "input", + "width": 3 + }, + "PLL1RESET": { + "direction": "input", + "width": 1 + }, + "PLLRSVD1": { + "direction": "input", + "width": 16 + }, + "PLLRSVD2": { + "direction": "input", + "width": 5 + }, + "PMARSVD": { + "direction": "input", + "width": 8 + }, + "PMARSVDOUT": { + "direction": "output", + "width": 16 + }, + "RCALENB": { + "direction": "input", + "width": 1 + }, + "REFCLKOUTMONITOR0": { + "direction": "output", + "width": 1 + }, + "REFCLKOUTMONITOR1": { + "direction": "output", + "width": 1 + } +} diff --git a/artix7/harness/arty-a7/pmod/design.json b/artix7/harness/arty-a7/pmod/design.json index d75cda6..5286435 100644 --- a/artix7/harness/arty-a7/pmod/design.json +++ b/artix7/harness/arty-a7/pmod/design.json @@ -1078,8 +1078,8 @@ "INT_R_X1Y116.WW2BEG2.NN6END3", "INT_R_X23Y46.IMUX24.SE2END0", "LIOB33_SING_X0Y99.IOB_Y1.IN_TERM.NONE", + "LIOB33_SING_X0Y99.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVDS_25_LVTTL_SSTL135_SSTL15_TMDS_33.IN_ONLY", "LIOB33_SING_X0Y99.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST", - "LIOB33_SING_X0Y99.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.IN_ONLY", "LIOB33_SING_X0Y99.IOB_Y1.LVCMOS25_LVCMOS33_LVTTL.IN", "LIOB33_SING_X0Y99.IOB_Y1.PULLTYPE.NONE", "LIOB33_X0Y3.IOB_Y0.IN_TERM.NONE", @@ -1128,8 +1128,8 @@ "LIOB33_X0Y51.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN", "LIOB33_X0Y51.IOB_Y0.PULLTYPE.NONE", "LIOB33_X0Y51.IOB_Y1.IN_TERM.NONE", + "LIOB33_X0Y51.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVDS_25_LVTTL_SSTL135_SSTL15_TMDS_33.IN_ONLY", "LIOB33_X0Y51.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST", - "LIOB33_X0Y51.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.IN_ONLY", "LIOB33_X0Y51.IOB_Y1.LVCMOS25_LVCMOS33_LVTTL.IN", "LIOB33_X0Y51.IOB_Y1.PULLTYPE.NONE", "LIOB33_X0Y53.IOB_Y0.IN_TERM.NONE", @@ -1138,8 +1138,8 @@ "LIOB33_X0Y53.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN", "LIOB33_X0Y53.IOB_Y0.PULLTYPE.NONE", "LIOB33_X0Y53.IOB_Y1.IN_TERM.NONE", + "LIOB33_X0Y53.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVDS_25_LVTTL_SSTL135_SSTL15_TMDS_33.IN_ONLY", "LIOB33_X0Y53.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST", - "LIOB33_X0Y53.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.IN_ONLY", "LIOB33_X0Y53.IOB_Y1.LVCMOS25_LVCMOS33_LVTTL.IN", "LIOB33_X0Y53.IOB_Y1.PULLTYPE.NONE", "LIOB33_X0Y75.IOB_Y0.IN_TERM.NONE", @@ -1148,8 +1148,8 @@ "LIOB33_X0Y75.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN", "LIOB33_X0Y75.IOB_Y0.PULLTYPE.NONE", "LIOB33_X0Y75.IOB_Y1.IN_TERM.NONE", + "LIOB33_X0Y75.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVDS_25_LVTTL_SSTL135_SSTL15_TMDS_33.IN_ONLY", "LIOB33_X0Y75.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST", - "LIOB33_X0Y75.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.IN_ONLY", "LIOB33_X0Y75.IOB_Y1.LVCMOS25_LVCMOS33_LVTTL.IN", "LIOB33_X0Y75.IOB_Y1.PULLTYPE.NONE", "LIOB33_X0Y77.IOB_Y0.IN_TERM.NONE", @@ -1158,8 +1158,8 @@ "LIOB33_X0Y77.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN", "LIOB33_X0Y77.IOB_Y0.PULLTYPE.NONE", "LIOB33_X0Y77.IOB_Y1.IN_TERM.NONE", + "LIOB33_X0Y77.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVDS_25_LVTTL_SSTL135_SSTL15_TMDS_33.IN_ONLY", "LIOB33_X0Y77.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST", - "LIOB33_X0Y77.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.IN_ONLY", "LIOB33_X0Y77.IOB_Y1.LVCMOS25_LVCMOS33_LVTTL.IN", "LIOB33_X0Y77.IOB_Y1.PULLTYPE.NONE", "LIOI3_SING_X0Y99.IDELAY_Y1.IDELAY_TYPE_FIXED", diff --git a/artix7/harness/arty-a7/swbut/design.json b/artix7/harness/arty-a7/swbut/design.json index a9ea557..1476496 100644 --- a/artix7/harness/arty-a7/swbut/design.json +++ b/artix7/harness/arty-a7/swbut/design.json @@ -892,8 +892,8 @@ "LIOB33_X0Y123.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN", "LIOB33_X0Y123.IOB_Y0.PULLTYPE.NONE", "LIOB33_X0Y123.IOB_Y1.IN_TERM.NONE", + "LIOB33_X0Y123.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVDS_25_LVTTL_SSTL135_SSTL15_TMDS_33.IN_ONLY", "LIOB33_X0Y123.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST", - "LIOB33_X0Y123.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.IN_ONLY", "LIOB33_X0Y123.IOB_Y1.LVCMOS25_LVCMOS33_LVTTL.IN", "LIOB33_X0Y123.IOB_Y1.PULLTYPE.NONE", "LIOB33_X0Y125.IOB_Y0.IN_TERM.NONE", @@ -902,8 +902,8 @@ "LIOB33_X0Y125.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN", "LIOB33_X0Y125.IOB_Y0.PULLTYPE.NONE", "LIOB33_X0Y125.IOB_Y1.IN_TERM.NONE", + "LIOB33_X0Y125.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVDS_25_LVTTL_SSTL135_SSTL15_TMDS_33.IN_ONLY", "LIOB33_X0Y125.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST", - "LIOB33_X0Y125.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.IN_ONLY", "LIOB33_X0Y125.IOB_Y1.LVCMOS25_LVCMOS33_LVTTL.IN", "LIOB33_X0Y125.IOB_Y1.PULLTYPE.NONE", "LIOB33_X0Y127.IOB_Y0.IN_TERM.NONE", @@ -912,16 +912,16 @@ "LIOB33_X0Y127.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN", "LIOB33_X0Y127.IOB_Y0.PULLTYPE.NONE", "LIOB33_X0Y127.IOB_Y1.IN_TERM.NONE", + "LIOB33_X0Y127.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVDS_25_LVTTL_SSTL135_SSTL15_TMDS_33.IN_ONLY", "LIOB33_X0Y127.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST", - "LIOB33_X0Y127.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.IN_ONLY", "LIOB33_X0Y127.IOB_Y1.LVCMOS25_LVCMOS33_LVTTL.IN", "LIOB33_X0Y127.IOB_Y1.PULLTYPE.NONE", "LIOB33_X0Y137.IOB_Y0.IN_TERM.NONE", "LIOB33_X0Y137.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST", "LIOB33_X0Y137.IOB_Y0.PULLTYPE.PULLDOWN", "LIOB33_X0Y137.IOB_Y1.IN_TERM.NONE", + "LIOB33_X0Y137.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVDS_25_LVTTL_SSTL135_SSTL15_TMDS_33.IN_ONLY", "LIOB33_X0Y137.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST", - "LIOB33_X0Y137.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.IN_ONLY", "LIOB33_X0Y137.IOB_Y1.LVCMOS25_LVCMOS33_LVTTL.IN", "LIOB33_X0Y137.IOB_Y1.PULLTYPE.NONE", "LIOI3_TBYTETERM_X0Y137.IDELAY_Y0.IDELAY_TYPE_FIXED", diff --git a/artix7/harness/arty-a7/uart/design.json b/artix7/harness/arty-a7/uart/design.json index 62abf2c..e05c7bc 100644 --- a/artix7/harness/arty-a7/uart/design.json +++ b/artix7/harness/arty-a7/uart/design.json @@ -371,8 +371,8 @@ "LIOB33_X0Y121.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST", "LIOB33_X0Y121.IOB_Y0.PULLTYPE.PULLDOWN", "LIOB33_X0Y121.IOB_Y1.IN_TERM.NONE", + "LIOB33_X0Y121.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVDS_25_LVTTL_SSTL135_SSTL15_TMDS_33.IN_ONLY", "LIOB33_X0Y121.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST", - "LIOB33_X0Y121.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.IN_ONLY", "LIOB33_X0Y121.IOB_Y1.LVCMOS25_LVCMOS33_LVTTL.IN", "LIOB33_X0Y121.IOB_Y1.PULLTYPE.NONE", "LIOI3_X0Y1.IDELAY_Y0.IDELAY_TYPE_FIXED", diff --git a/artix7/harness/basys3/swbut/design.json b/artix7/harness/basys3/swbut/design.json index 057c992..6c5869c 100644 --- a/artix7/harness/basys3/swbut/design.json +++ b/artix7/harness/basys3/swbut/design.json @@ -3532,8 +3532,8 @@ "LIOB33_X0Y5.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN", "LIOB33_X0Y5.IOB_Y0.PULLTYPE.NONE", "LIOB33_X0Y5.IOB_Y1.IN_TERM.NONE", + "LIOB33_X0Y5.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVDS_25_LVTTL_SSTL135_SSTL15_TMDS_33.IN_ONLY", "LIOB33_X0Y5.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST", - "LIOB33_X0Y5.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.IN_ONLY", "LIOB33_X0Y5.IOB_Y1.LVCMOS25_LVCMOS33_LVTTL.IN", "LIOB33_X0Y5.IOB_Y1.PULLTYPE.NONE", "LIOB33_X0Y7.IOB_Y0.IN_TERM.NONE", @@ -3542,8 +3542,8 @@ "LIOB33_X0Y7.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN", "LIOB33_X0Y7.IOB_Y0.PULLTYPE.NONE", "LIOB33_X0Y7.IOB_Y1.IN_TERM.NONE", + "LIOB33_X0Y7.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVDS_25_LVTTL_SSTL135_SSTL15_TMDS_33.IN_ONLY", "LIOB33_X0Y7.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST", - "LIOB33_X0Y7.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.IN_ONLY", "LIOB33_X0Y7.IOB_Y1.LVCMOS25_LVCMOS33_LVTTL.IN", "LIOB33_X0Y7.IOB_Y1.PULLTYPE.NONE", "LIOB33_X0Y9.IOB_Y0.IN_TERM.NONE", @@ -3552,8 +3552,8 @@ "LIOB33_X0Y9.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN", "LIOB33_X0Y9.IOB_Y0.PULLTYPE.NONE", "LIOB33_X0Y9.IOB_Y1.IN_TERM.NONE", + "LIOB33_X0Y9.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVDS_25_LVTTL_SSTL135_SSTL15_TMDS_33.IN_ONLY", "LIOB33_X0Y9.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST", - "LIOB33_X0Y9.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.IN_ONLY", "LIOB33_X0Y9.IOB_Y1.LVCMOS25_LVCMOS33_LVTTL.IN", "LIOB33_X0Y9.IOB_Y1.PULLTYPE.NONE", "LIOB33_X0Y11.IOB_Y0.IN_TERM.NONE", @@ -3562,8 +3562,8 @@ "LIOB33_X0Y11.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN", "LIOB33_X0Y11.IOB_Y0.PULLTYPE.NONE", "LIOB33_X0Y11.IOB_Y1.IN_TERM.NONE", + "LIOB33_X0Y11.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVDS_25_LVTTL_SSTL135_SSTL15_TMDS_33.IN_ONLY", "LIOB33_X0Y11.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST", - "LIOB33_X0Y11.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.IN_ONLY", "LIOB33_X0Y11.IOB_Y1.LVCMOS25_LVCMOS33_LVTTL.IN", "LIOB33_X0Y11.IOB_Y1.PULLTYPE.NONE", "LIOB33_X0Y17.IOB_Y0.IN_TERM.NONE", @@ -3772,8 +3772,8 @@ "RIOB33_X43Y39.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN", "RIOB33_X43Y39.IOB_Y0.PULLTYPE.NONE", "RIOB33_X43Y39.IOB_Y1.IN_TERM.NONE", + "RIOB33_X43Y39.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVDS_25_LVTTL_SSTL135_SSTL15_TMDS_33.IN_ONLY", "RIOB33_X43Y39.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST", - "RIOB33_X43Y39.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.IN_ONLY", "RIOB33_X43Y39.IOB_Y1.LVCMOS25_LVCMOS33_LVTTL.IN", "RIOB33_X43Y39.IOB_Y1.PULLTYPE.NONE", "RIOB33_X43Y43.IOB_Y0.IN_TERM.NONE", @@ -3782,8 +3782,8 @@ "RIOB33_X43Y43.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN", "RIOB33_X43Y43.IOB_Y0.PULLTYPE.NONE", "RIOB33_X43Y43.IOB_Y1.IN_TERM.NONE", + "RIOB33_X43Y43.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVDS_25_LVTTL_SSTL135_SSTL15_TMDS_33.IN_ONLY", "RIOB33_X43Y43.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST", - "RIOB33_X43Y43.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.IN_ONLY", "RIOB33_X43Y43.IOB_Y1.LVCMOS25_LVCMOS33_LVTTL.IN", "RIOB33_X43Y43.IOB_Y1.PULLTYPE.NONE", "RIOB33_X43Y45.IOB_Y0.IN_TERM.NONE", @@ -3792,8 +3792,8 @@ "RIOB33_X43Y45.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN", "RIOB33_X43Y45.IOB_Y0.PULLTYPE.NONE", "RIOB33_X43Y45.IOB_Y1.IN_TERM.NONE", + "RIOB33_X43Y45.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVDS_25_LVTTL_SSTL135_SSTL15_TMDS_33.IN_ONLY", "RIOB33_X43Y45.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST", - "RIOB33_X43Y45.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.IN_ONLY", "RIOB33_X43Y45.IOB_Y1.LVCMOS25_LVCMOS33_LVTTL.IN", "RIOB33_X43Y45.IOB_Y1.PULLTYPE.NONE", "RIOB33_X43Y47.IOB_Y0.IN_TERM.NONE", @@ -3802,8 +3802,8 @@ "RIOB33_X43Y47.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN", "RIOB33_X43Y47.IOB_Y0.PULLTYPE.NONE", "RIOB33_X43Y47.IOB_Y1.IN_TERM.NONE", + "RIOB33_X43Y47.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVDS_25_LVTTL_SSTL135_SSTL15_TMDS_33.IN_ONLY", "RIOB33_X43Y47.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST", - "RIOB33_X43Y47.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.IN_ONLY", "RIOB33_X43Y47.IOB_Y1.LVCMOS25_LVCMOS33_LVTTL.IN", "RIOB33_X43Y47.IOB_Y1.PULLTYPE.NONE", "RIOB33_X43Y61.IOB_Y0.IN_TERM.NONE", diff --git a/artix7/ppips_gtp_channel_0.db b/artix7/ppips_gtp_channel_0.db index b334f0b..c67f32a 100644 --- a/artix7/ppips_gtp_channel_0.db +++ b/artix7/ppips_gtp_channel_0.db @@ -10,6 +10,10 @@ GTP_CHANNEL_0.GTPE2_CHANNEL_EYESCANTRIGGER.GTPE2_IMUX31_8 always GTP_CHANNEL_0.GTPE2_CHANNEL_GTRESETSEL.GTPE2_CTRL0_10 always GTP_CHANNEL_0.GTPE2_CHANNEL_GTRXRESET.GTPE2_CTRL0_8 always GTP_CHANNEL_0.GTPE2_CHANNEL_GTTXRESET.GTPE2_CTRL0_5 always +GTP_CHANNEL_0.GTPE2_CHANNEL_PLL0CLK.GTPE2_CHANNEL_PLLCLK0 always +GTP_CHANNEL_0.GTPE2_CHANNEL_PLL0REFCLK.GTPE2_CHANNEL_PLLREFCLK0 always +GTP_CHANNEL_0.GTPE2_CHANNEL_PLL1CLK.GTPE2_CHANNEL_PLLCLK1 always +GTP_CHANNEL_0.GTPE2_CHANNEL_PLL1REFCLK.GTPE2_CHANNEL_PLLREFCLK1 always GTP_CHANNEL_0.GTPE2_CHANNEL_RESETOVRD.GTPE2_IMUX41_5 always GTP_CHANNEL_0.GTPE2_CHANNEL_RX8B10BEN.GTPE2_IMUX45_1 always GTP_CHANNEL_0.GTPE2_CHANNEL_RXBUFRESET.GTPE2_CTRL1_6 always @@ -36,6 +40,7 @@ GTP_CHANNEL_0.GTPE2_CHANNEL_RXLPMLFOVRDEN.GTPE2_IMUX3_10 always GTP_CHANNEL_0.GTPE2_CHANNEL_RXLPMOSINTNTRLEN.GTPE2_IMUX7_2 always GTP_CHANNEL_0.GTPE2_CHANNEL_RXLPMRESET.GTPE2_CTRL0_9 always GTP_CHANNEL_0.GTPE2_CHANNEL_RXMCOMMAALIGNEN.GTPE2_IMUX41_1 always +GTP_CHANNEL_0.GTPE2_CHANNEL_RXN.GTPE2_CHANNEL_RXN_PAD always GTP_CHANNEL_0.GTPE2_CHANNEL_RXOOBRESET.GTPE2_CTRL1_10 always GTP_CHANNEL_0.GTPE2_CHANNEL_RXOSCALRESET.GTPE2_IMUX46_2 always GTP_CHANNEL_0.GTPE2_CHANNEL_RXOSHOLD.GTPE2_IMUX29_8 always @@ -47,6 +52,8 @@ GTP_CHANNEL_0.GTPE2_CHANNEL_RXOSINTPD.GTPE2_IMUX3_0 always GTP_CHANNEL_0.GTPE2_CHANNEL_RXOSINTSTROBE.GTPE2_IMUX32_9 always GTP_CHANNEL_0.GTPE2_CHANNEL_RXOSINTTESTOVRDEN.GTPE2_IMUX5_9 always GTP_CHANNEL_0.GTPE2_CHANNEL_RXOSOVRDEN.GTPE2_IMUX13_8 always +GTP_CHANNEL_0.GTPE2_CHANNEL_RXOUTCLK_0.GTPE2_CHANNEL_GTRXOUTCLK_0 always +GTP_CHANNEL_0.GTPE2_CHANNEL_RXP.GTPE2_CHANNEL_RXP_PAD always GTP_CHANNEL_0.GTPE2_CHANNEL_RXPCOMMAALIGNEN.GTPE2_IMUX40_1 always GTP_CHANNEL_0.GTPE2_CHANNEL_RXPCSRESET.GTPE2_IMUX46_1 always GTP_CHANNEL_0.GTPE2_CHANNEL_RXPHALIGN.GTPE2_IMUX14_9 always @@ -81,6 +88,9 @@ GTP_CHANNEL_0.GTPE2_CHANNEL_TXDLYSRESET.GTPE2_IMUX45_3 always GTP_CHANNEL_0.GTPE2_CHANNEL_TXDLYUPDOWN.GTPE2_IMUX43_5 always GTP_CHANNEL_0.GTPE2_CHANNEL_TXELECIDLE.GTPE2_IMUX39_6 always GTP_CHANNEL_0.GTPE2_CHANNEL_TXINHIBIT.GTPE2_IMUX32_2 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TXN_PAD.GTPE2_CHANNEL_TXN always +GTP_CHANNEL_0.GTPE2_CHANNEL_TXOUTCLK_0.GTPE2_CHANNEL_GTTXOUTCLK_0 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TXP_PAD.GTPE2_CHANNEL_TXP always GTP_CHANNEL_0.GTPE2_CHANNEL_TXPCSRESET.GTPE2_IMUX46_0 always GTP_CHANNEL_0.GTPE2_CHANNEL_TXPDELECIDLEMODE.GTPE2_IMUX14_0 always GTP_CHANNEL_0.GTPE2_CHANNEL_TXPHALIGN.GTPE2_IMUX25_2 always @@ -344,3 +354,173 @@ GTP_CHANNEL_0.GTPE2_CHANNEL_TXSEQUENCE6.GTPE2_IMUX8_0 always GTP_CHANNEL_0.GTPE2_CHANNEL_TXSYSCLKSEL0.GTPE2_IMUX28_5 always GTP_CHANNEL_0.GTPE2_CHANNEL_TXSYSCLKSEL1.GTPE2_IMUX28_4 always GTP_CHANNEL_0.GTPE2_CHANNEL_TXUSRCLK2.GTPE2_CLK0_5 always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B0_3.GTPE2_CHANNEL_RXOSINTSTROBEDONE always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B0_4.GTPE2_CHANNEL_RXDATA27 always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B0_5.GTPE2_CHANNEL_PCSRSVDOUT1 always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B0_6.GTPE2_CHANNEL_RXDATA19 always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B0_7.GTPE2_CHANNEL_RXOSINTSTROBESTARTED always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B0_8.GTPE2_CHANNEL_RXDATA11 always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B0_10.GTPE2_CHANNEL_RXDATA3 always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B1_3.GTPE2_CHANNEL_RXDATA30 always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B1_5.GTPE2_CHANNEL_RXDATA22 always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B1_6.GTPE2_CHANNEL_DMONITOROUT13 always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B1_7.GTPE2_CHANNEL_RXDATA14 always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B1_8.GTPE2_CHANNEL_DRPDO11 always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B1_9.GTPE2_CHANNEL_RXDATA6 always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B1_10.GTPE2_CHANNEL_TXPHINITDONE always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B2_4.GTPE2_CHANNEL_RXDATA25 always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B2_6.GTPE2_CHANNEL_RXDATA17 always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B2_8.GTPE2_CHANNEL_RXDATA9 always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B2_9.GTPE2_CHANNEL_DRPDO10 always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B2_10.GTPE2_CHANNEL_RXDATA1 always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B3_2.GTPE2_CHANNEL_RXPHMONITOR3 always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B3_3.GTPE2_CHANNEL_RXDATA28 always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B3_5.GTPE2_CHANNEL_RXDATA20 always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B3_6.GTPE2_CHANNEL_RXOSINTDONE always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B3_7.GTPE2_CHANNEL_RXDATA12 always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B3_9.GTPE2_CHANNEL_RXDATA4 always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B4_3.GTPE2_CHANNEL_DRPDO2 always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B4_4.GTPE2_CHANNEL_RXDATA26 always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B4_5.GTPE2_CHANNEL_DRPDO7 always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B4_6.GTPE2_CHANNEL_RXDATA18 always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B4_7.GTPE2_CHANNEL_DRPDO15 always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B4_8.GTPE2_CHANNEL_RXDATA10 always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B4_9.GTPE2_CHANNEL_DRPDO9 always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B4_10.GTPE2_CHANNEL_RXDATA2 always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B5_1.GTPE2_CHANNEL_RXDATAVALID1 always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B5_3.GTPE2_CHANNEL_RXDATA31 always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B5_5.GTPE2_CHANNEL_RXDATA23 always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B5_6.GTPE2_CHANNEL_PCSRSVDOUT14 always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B5_7.GTPE2_CHANNEL_RXDATA15 always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B5_8.GTPE2_CHANNEL_PCSRSVDOUT11 always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B5_9.GTPE2_CHANNEL_RXDATA7 always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B5_10.GTPE2_CHANNEL_PCSRSVDOUT0 always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B6_2.GTPE2_CHANNEL_RXPHSLIPMONITOR3 always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B6_4.GTPE2_CHANNEL_RXDATA24 always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B6_6.GTPE2_CHANNEL_RXDATA16 always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B6_7.GTPE2_CHANNEL_RXOSINTSTARTED always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B6_8.GTPE2_CHANNEL_RXDATA8 always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B6_10.GTPE2_CHANNEL_RXDATA0 always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B7_2.GTPE2_CHANNEL_RXPHMONITOR2 always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B7_3.GTPE2_CHANNEL_RXDATA29 always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B7_4.GTPE2_CHANNEL_PCSRSVDOUT12 always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B7_5.GTPE2_CHANNEL_RXDATA21 always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B7_6.GTPE2_CHANNEL_PMARSVDOUT1 always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B7_7.GTPE2_CHANNEL_RXDATA13 always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B7_8.GTPE2_CHANNEL_DRPDO12 always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B7_9.GTPE2_CHANNEL_RXDATA5 always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B8_0.GTPE2_CHANNEL_RXBYTEISALIGNED always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B8_1.GTPE2_CHANNEL_RXCHANBONDSEQ always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B9_0.GTPE2_CHANNEL_RXPHSLIPMONITOR2 always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B9_2.GTPE2_CHANNEL_PCSRSVDOUT13 always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B9_3.GTPE2_CHANNEL_DMONITOROUT7 always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B9_4.GTPE2_CHANNEL_DMONITOROUT6 always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B9_5.GTPE2_CHANNEL_DMONITOROUT5 always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B9_6.GTPE2_CHANNEL_DMONITOROUT4 always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B9_7.GTPE2_CHANNEL_DMONITOROUT3 always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B9_8.GTPE2_CHANNEL_DMONITOROUT2 always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B9_9.GTPE2_CHANNEL_DMONITOROUT1 always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B9_10.GTPE2_CHANNEL_DMONITOROUT0 always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B10_0.GTPE2_CHANNEL_RXPHMONITOR1 always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B10_1.GTPE2_CHANNEL_RXSYNCOUT always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B10_3.GTPE2_CHANNEL_DRPDO4 always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B10_5.GTPE2_CHANNEL_DMONITOROUT14 always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B10_9.GTPE2_CHANNEL_PHYSTATUS always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B11_0.GTPE2_CHANNEL_RXCLKCORCNT0 always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B11_10.GTPE2_CHANNEL_RXSTARTOFSEQ1 always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B12_0.GTPE2_CHANNEL_RXDLYSRESETDONE always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B12_1.GTPE2_CHANNEL_RXCOMWAKEDET always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B12_2.GTPE2_CHANNEL_RXPMARESETDONE always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B12_3.GTPE2_CHANNEL_DRPDO0 always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B12_4.GTPE2_CHANNEL_RXCHARISK3 always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B12_5.GTPE2_CHANNEL_DRPDO5 always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B12_6.GTPE2_CHANNEL_RXCHARISK2 always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B12_7.GTPE2_CHANNEL_DRPDO14 always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B12_8.GTPE2_CHANNEL_RXCHARISK1 always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B12_9.GTPE2_CHANNEL_DRPDO8 always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B12_10.GTPE2_CHANNEL_RXCHARISK0 always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B13_0.GTPE2_CHANNEL_RXPHSLIPMONITOR0 always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B13_1.GTPE2_CHANNEL_RXDATAVALID0 always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B13_2.GTPE2_CHANNEL_PCSRSVDOUT2 always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B13_3.GTPE2_CHANNEL_PCSRSVDOUT3 always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B13_4.GTPE2_CHANNEL_PCSRSVDOUT4 always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B13_5.GTPE2_CHANNEL_PCSRSVDOUT5 always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B13_6.GTPE2_CHANNEL_PCSRSVDOUT6 always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B13_7.GTPE2_CHANNEL_PCSRSVDOUT7 always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B13_8.GTPE2_CHANNEL_PCSRSVDOUT8 always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B13_9.GTPE2_CHANNEL_PCSRSVDOUT9 always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B13_10.GTPE2_CHANNEL_PCSRSVDOUT10 always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B14_0.GTPE2_CHANNEL_RXBYTEREALIGN always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B14_1.GTPE2_CHANNEL_RXHEADERVALID always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B14_2.GTPE2_CHANNEL_TXPMARESETDONE always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B14_3.GTPE2_CHANNEL_DRPDO3 always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B14_4.GTPE2_CHANNEL_RXNOTINTABLE3 always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B14_5.GTPE2_CHANNEL_DRPRDY always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B14_6.GTPE2_CHANNEL_RXNOTINTABLE2 always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B14_7.GTPE2_CHANNEL_TXSYNCOUT always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B14_8.GTPE2_CHANNEL_RXNOTINTABLE1 always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B14_9.GTPE2_CHANNEL_RXSYNCDONE always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B14_10.GTPE2_CHANNEL_RXNOTINTABLE0 always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B15_0.GTPE2_CHANNEL_RXCLKCORCNT1 always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B15_1.GTPE2_CHANNEL_TXOUTCLKFABRIC always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B15_2.GTPE2_CHANNEL_DMONITOROUT12 always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B15_3.GTPE2_CHANNEL_RXCHARISCOMMA3 always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B15_4.GTPE2_CHANNEL_PCSRSVDOUT15 always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B15_5.GTPE2_CHANNEL_RXCHARISCOMMA2 always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B15_6.GTPE2_CHANNEL_PMARSVDOUT0 always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B15_7.GTPE2_CHANNEL_RXCHARISCOMMA1 always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B15_8.GTPE2_CHANNEL_DRPDO13 always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B15_9.GTPE2_CHANNEL_RXCHARISCOMMA0 always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B16_0.GTPE2_CHANNEL_RXPHMONITOR0 always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B16_1.GTPE2_CHANNEL_RXPRBSERR always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B16_3.GTPE2_CHANNEL_RXPHSLIPMONITOR4 always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B16_4.GTPE2_CHANNEL_TXRESETDONE always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B16_7.GTPE2_CHANNEL_RXCHBONDO3 always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B16_8.GTPE2_CHANNEL_RXCHBONDO2 always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B16_9.GTPE2_CHANNEL_RXCHBONDO1 always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B16_10.GTPE2_CHANNEL_RXCHBONDO0 always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B17_1.GTPE2_CHANNEL_RXPHMONITOR4 always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B17_2.GTPE2_CHANNEL_TXBUFSTATUS0 always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B17_3.GTPE2_CHANNEL_TXDLYSRESETDONE always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B17_4.GTPE2_CHANNEL_TXOUTCLKPCS always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B17_5.GTPE2_CHANNEL_RXCDRLOCK always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B17_6.GTPE2_CHANNEL_RXHEADER2 always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B17_8.GTPE2_CHANNEL_RXSTATUS1 always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B17_10.GTPE2_CHANNEL_RXBUFSTATUS2 always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B18_0.GTPE2_CHANNEL_EYESCANDATAERROR always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B18_1.GTPE2_CHANNEL_RXRESETDONE always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B18_3.GTPE2_CHANNEL_TXPHALIGNDONE always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B18_4.GTPE2_CHANNEL_RXPHALIGNDONE always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B18_7.GTPE2_CHANNEL_RXCOMSASDET always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B18_8.GTPE2_CHANNEL_RXSTARTOFSEQ0 always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B18_9.GTPE2_CHANNEL_RXCHANISALIGNED always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B19_0.GTPE2_CHANNEL_RXPHSLIPMONITOR1 always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B19_6.GTPE2_CHANNEL_RXHEADER0 always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B19_7.GTPE2_CHANNEL_RXCOMMADET always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B19_8.GTPE2_CHANNEL_RXELECIDLE always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B19_10.GTPE2_CHANNEL_RXBUFSTATUS1 always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B20_0.GTPE2_CHANNEL_TXBUFSTATUS1 always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B20_1.GTPE2_CHANNEL_RXCOMINITDET always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B20_4.GTPE2_CHANNEL_TXRATEDONE always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B20_9.GTPE2_CHANNEL_RXVALID always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B21_4.GTPE2_CHANNEL_DMONITOROUT11 always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B21_5.GTPE2_CHANNEL_DMONITOROUT10 always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B21_6.GTPE2_CHANNEL_DMONITOROUT9 always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B21_7.GTPE2_CHANNEL_DMONITOROUT8 always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B21_8.GTPE2_CHANNEL_RXSTATUS0 always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B22_0.GTPE2_CHANNEL_RXOUTCLKFABRIC always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B22_1.GTPE2_CHANNEL_RXOUTCLKPCS always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B22_3.GTPE2_CHANNEL_DRPDO1 always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B22_4.GTPE2_CHANNEL_RXDISPERR3 always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B22_5.GTPE2_CHANNEL_DRPDO6 always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B22_6.GTPE2_CHANNEL_RXDISPERR2 always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B22_8.GTPE2_CHANNEL_RXDISPERR1 always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B22_9.GTPE2_CHANNEL_TXSYNCDONE always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B22_10.GTPE2_CHANNEL_RXDISPERR0 always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B23_1.GTPE2_CHANNEL_TXCOMFINISH always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B23_4.GTPE2_CHANNEL_TXGEARBOXREADY always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B23_5.GTPE2_CHANNEL_RXRATEDONE always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B23_6.GTPE2_CHANNEL_RXHEADER1 always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B23_8.GTPE2_CHANNEL_RXSTATUS2 always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B23_9.GTPE2_CHANNEL_RXCHANREALIGN always +GTP_CHANNEL_0.GTPE2_LOGIC_OUTS_B23_10.GTPE2_CHANNEL_RXBUFSTATUS0 always diff --git a/artix7/ppips_gtp_channel_0_mid_left.db b/artix7/ppips_gtp_channel_0_mid_left.db index f17dbd8..388022f 100644 --- a/artix7/ppips_gtp_channel_0_mid_left.db +++ b/artix7/ppips_gtp_channel_0_mid_left.db @@ -10,6 +10,10 @@ GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_EYESCANTRIGGER.GTPE2_IMUX31_8 always GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_GTRESETSEL.GTPE2_CTRL0_10 always GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_GTRXRESET.GTPE2_CTRL0_8 always GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_GTTXRESET.GTPE2_CTRL0_5 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_PLL0CLK.GTPE2_CHANNEL_PLLCLK0 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_PLL0REFCLK.GTPE2_CHANNEL_PLLREFCLK0 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_PLL1CLK.GTPE2_CHANNEL_PLLCLK1 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_PLL1REFCLK.GTPE2_CHANNEL_PLLREFCLK1 always GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RESETOVRD.GTPE2_IMUX41_5 always GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RX8B10BEN.GTPE2_IMUX45_1 always GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXBUFRESET.GTPE2_CTRL1_6 always @@ -36,6 +40,7 @@ GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXLPMLFOVRDEN.GTPE2_IMUX3_10 always GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXLPMOSINTNTRLEN.GTPE2_IMUX7_2 always GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXLPMRESET.GTPE2_CTRL0_9 always GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXMCOMMAALIGNEN.GTPE2_IMUX41_1 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXN.GTPE2_CHANNEL_RXN_PAD always GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXOOBRESET.GTPE2_CTRL1_10 always GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXOSCALRESET.GTPE2_IMUX46_2 always GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXOSHOLD.GTPE2_IMUX29_8 always @@ -47,6 +52,8 @@ GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXOSINTPD.GTPE2_IMUX3_0 always GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXOSINTSTROBE.GTPE2_IMUX32_9 always GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXOSINTTESTOVRDEN.GTPE2_IMUX5_9 always GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXOSOVRDEN.GTPE2_IMUX13_8 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXOUTCLK_0.GTPE2_CHANNEL_GTRXOUTCLK_0 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXP.GTPE2_CHANNEL_RXP_PAD always GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXPCOMMAALIGNEN.GTPE2_IMUX40_1 always GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXPCSRESET.GTPE2_IMUX46_1 always GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXPHALIGN.GTPE2_IMUX14_9 always @@ -81,6 +88,9 @@ GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXDLYSRESET.GTPE2_IMUX45_3 always GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXDLYUPDOWN.GTPE2_IMUX43_5 always GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXELECIDLE.GTPE2_IMUX39_6 always GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXINHIBIT.GTPE2_IMUX32_2 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXN_PAD.GTPE2_CHANNEL_TXN always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXOUTCLK_0.GTPE2_CHANNEL_GTTXOUTCLK_0 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXP_PAD.GTPE2_CHANNEL_TXP always GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXPCSRESET.GTPE2_IMUX46_0 always GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXPDELECIDLEMODE.GTPE2_IMUX14_0 always GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXPHALIGN.GTPE2_IMUX25_2 always @@ -344,3 +354,173 @@ GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXSEQUENCE6.GTPE2_IMUX8_0 always GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXSYSCLKSEL0.GTPE2_IMUX28_5 always GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXSYSCLKSEL1.GTPE2_IMUX28_4 always GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXUSRCLK2.GTPE2_CLK0_5 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B0_3.GTPE2_CHANNEL_RXOSINTSTROBEDONE always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B0_4.GTPE2_CHANNEL_RXDATA27 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B0_5.GTPE2_CHANNEL_PCSRSVDOUT1 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B0_6.GTPE2_CHANNEL_RXDATA19 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B0_7.GTPE2_CHANNEL_RXOSINTSTROBESTARTED always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B0_8.GTPE2_CHANNEL_RXDATA11 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B0_10.GTPE2_CHANNEL_RXDATA3 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B1_3.GTPE2_CHANNEL_RXDATA30 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B1_5.GTPE2_CHANNEL_RXDATA22 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B1_6.GTPE2_CHANNEL_DMONITOROUT13 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B1_7.GTPE2_CHANNEL_RXDATA14 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B1_8.GTPE2_CHANNEL_DRPDO11 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B1_9.GTPE2_CHANNEL_RXDATA6 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B1_10.GTPE2_CHANNEL_TXPHINITDONE always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B2_4.GTPE2_CHANNEL_RXDATA25 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B2_6.GTPE2_CHANNEL_RXDATA17 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B2_8.GTPE2_CHANNEL_RXDATA9 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B2_9.GTPE2_CHANNEL_DRPDO10 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B2_10.GTPE2_CHANNEL_RXDATA1 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B3_2.GTPE2_CHANNEL_RXPHMONITOR3 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B3_3.GTPE2_CHANNEL_RXDATA28 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B3_5.GTPE2_CHANNEL_RXDATA20 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B3_6.GTPE2_CHANNEL_RXOSINTDONE always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B3_7.GTPE2_CHANNEL_RXDATA12 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B3_9.GTPE2_CHANNEL_RXDATA4 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B4_3.GTPE2_CHANNEL_DRPDO2 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B4_4.GTPE2_CHANNEL_RXDATA26 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B4_5.GTPE2_CHANNEL_DRPDO7 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B4_6.GTPE2_CHANNEL_RXDATA18 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B4_7.GTPE2_CHANNEL_DRPDO15 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B4_8.GTPE2_CHANNEL_RXDATA10 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B4_9.GTPE2_CHANNEL_DRPDO9 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B4_10.GTPE2_CHANNEL_RXDATA2 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B5_1.GTPE2_CHANNEL_RXDATAVALID1 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B5_3.GTPE2_CHANNEL_RXDATA31 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B5_5.GTPE2_CHANNEL_RXDATA23 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B5_6.GTPE2_CHANNEL_PCSRSVDOUT14 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B5_7.GTPE2_CHANNEL_RXDATA15 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B5_8.GTPE2_CHANNEL_PCSRSVDOUT11 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B5_9.GTPE2_CHANNEL_RXDATA7 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B5_10.GTPE2_CHANNEL_PCSRSVDOUT0 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B6_2.GTPE2_CHANNEL_RXPHSLIPMONITOR3 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B6_4.GTPE2_CHANNEL_RXDATA24 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B6_6.GTPE2_CHANNEL_RXDATA16 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B6_7.GTPE2_CHANNEL_RXOSINTSTARTED always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B6_8.GTPE2_CHANNEL_RXDATA8 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B6_10.GTPE2_CHANNEL_RXDATA0 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B7_2.GTPE2_CHANNEL_RXPHMONITOR2 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B7_3.GTPE2_CHANNEL_RXDATA29 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B7_4.GTPE2_CHANNEL_PCSRSVDOUT12 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B7_5.GTPE2_CHANNEL_RXDATA21 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B7_6.GTPE2_CHANNEL_PMARSVDOUT1 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B7_7.GTPE2_CHANNEL_RXDATA13 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B7_8.GTPE2_CHANNEL_DRPDO12 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B7_9.GTPE2_CHANNEL_RXDATA5 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B8_0.GTPE2_CHANNEL_RXBYTEISALIGNED always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B8_1.GTPE2_CHANNEL_RXCHANBONDSEQ always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B9_0.GTPE2_CHANNEL_RXPHSLIPMONITOR2 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B9_2.GTPE2_CHANNEL_PCSRSVDOUT13 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B9_3.GTPE2_CHANNEL_DMONITOROUT7 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B9_4.GTPE2_CHANNEL_DMONITOROUT6 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B9_5.GTPE2_CHANNEL_DMONITOROUT5 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B9_6.GTPE2_CHANNEL_DMONITOROUT4 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B9_7.GTPE2_CHANNEL_DMONITOROUT3 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B9_8.GTPE2_CHANNEL_DMONITOROUT2 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B9_9.GTPE2_CHANNEL_DMONITOROUT1 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B9_10.GTPE2_CHANNEL_DMONITOROUT0 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B10_0.GTPE2_CHANNEL_RXPHMONITOR1 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B10_1.GTPE2_CHANNEL_RXSYNCOUT always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B10_3.GTPE2_CHANNEL_DRPDO4 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B10_5.GTPE2_CHANNEL_DMONITOROUT14 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B10_9.GTPE2_CHANNEL_PHYSTATUS always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B11_0.GTPE2_CHANNEL_RXCLKCORCNT0 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B11_10.GTPE2_CHANNEL_RXSTARTOFSEQ1 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B12_0.GTPE2_CHANNEL_RXDLYSRESETDONE always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B12_1.GTPE2_CHANNEL_RXCOMWAKEDET always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B12_2.GTPE2_CHANNEL_RXPMARESETDONE always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B12_3.GTPE2_CHANNEL_DRPDO0 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B12_4.GTPE2_CHANNEL_RXCHARISK3 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B12_5.GTPE2_CHANNEL_DRPDO5 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B12_6.GTPE2_CHANNEL_RXCHARISK2 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B12_7.GTPE2_CHANNEL_DRPDO14 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B12_8.GTPE2_CHANNEL_RXCHARISK1 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B12_9.GTPE2_CHANNEL_DRPDO8 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B12_10.GTPE2_CHANNEL_RXCHARISK0 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B13_0.GTPE2_CHANNEL_RXPHSLIPMONITOR0 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B13_1.GTPE2_CHANNEL_RXDATAVALID0 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B13_2.GTPE2_CHANNEL_PCSRSVDOUT2 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B13_3.GTPE2_CHANNEL_PCSRSVDOUT3 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B13_4.GTPE2_CHANNEL_PCSRSVDOUT4 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B13_5.GTPE2_CHANNEL_PCSRSVDOUT5 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B13_6.GTPE2_CHANNEL_PCSRSVDOUT6 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B13_7.GTPE2_CHANNEL_PCSRSVDOUT7 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B13_8.GTPE2_CHANNEL_PCSRSVDOUT8 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B13_9.GTPE2_CHANNEL_PCSRSVDOUT9 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B13_10.GTPE2_CHANNEL_PCSRSVDOUT10 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B14_0.GTPE2_CHANNEL_RXBYTEREALIGN always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B14_1.GTPE2_CHANNEL_RXHEADERVALID always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B14_2.GTPE2_CHANNEL_TXPMARESETDONE always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B14_3.GTPE2_CHANNEL_DRPDO3 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B14_4.GTPE2_CHANNEL_RXNOTINTABLE3 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B14_5.GTPE2_CHANNEL_DRPRDY always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B14_6.GTPE2_CHANNEL_RXNOTINTABLE2 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B14_7.GTPE2_CHANNEL_TXSYNCOUT always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B14_8.GTPE2_CHANNEL_RXNOTINTABLE1 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B14_9.GTPE2_CHANNEL_RXSYNCDONE always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B14_10.GTPE2_CHANNEL_RXNOTINTABLE0 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B15_0.GTPE2_CHANNEL_RXCLKCORCNT1 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B15_1.GTPE2_CHANNEL_TXOUTCLKFABRIC always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B15_2.GTPE2_CHANNEL_DMONITOROUT12 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B15_3.GTPE2_CHANNEL_RXCHARISCOMMA3 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B15_4.GTPE2_CHANNEL_PCSRSVDOUT15 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B15_5.GTPE2_CHANNEL_RXCHARISCOMMA2 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B15_6.GTPE2_CHANNEL_PMARSVDOUT0 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B15_7.GTPE2_CHANNEL_RXCHARISCOMMA1 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B15_8.GTPE2_CHANNEL_DRPDO13 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B15_9.GTPE2_CHANNEL_RXCHARISCOMMA0 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B16_0.GTPE2_CHANNEL_RXPHMONITOR0 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B16_1.GTPE2_CHANNEL_RXPRBSERR always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B16_3.GTPE2_CHANNEL_RXPHSLIPMONITOR4 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B16_4.GTPE2_CHANNEL_TXRESETDONE always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B16_7.GTPE2_CHANNEL_RXCHBONDO3 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B16_8.GTPE2_CHANNEL_RXCHBONDO2 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B16_9.GTPE2_CHANNEL_RXCHBONDO1 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B16_10.GTPE2_CHANNEL_RXCHBONDO0 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B17_1.GTPE2_CHANNEL_RXPHMONITOR4 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B17_2.GTPE2_CHANNEL_TXBUFSTATUS0 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B17_3.GTPE2_CHANNEL_TXDLYSRESETDONE always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B17_4.GTPE2_CHANNEL_TXOUTCLKPCS always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B17_5.GTPE2_CHANNEL_RXCDRLOCK always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B17_6.GTPE2_CHANNEL_RXHEADER2 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B17_8.GTPE2_CHANNEL_RXSTATUS1 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B17_10.GTPE2_CHANNEL_RXBUFSTATUS2 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B18_0.GTPE2_CHANNEL_EYESCANDATAERROR always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B18_1.GTPE2_CHANNEL_RXRESETDONE always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B18_3.GTPE2_CHANNEL_TXPHALIGNDONE always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B18_4.GTPE2_CHANNEL_RXPHALIGNDONE always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B18_7.GTPE2_CHANNEL_RXCOMSASDET always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B18_8.GTPE2_CHANNEL_RXSTARTOFSEQ0 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B18_9.GTPE2_CHANNEL_RXCHANISALIGNED always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B19_0.GTPE2_CHANNEL_RXPHSLIPMONITOR1 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B19_6.GTPE2_CHANNEL_RXHEADER0 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B19_7.GTPE2_CHANNEL_RXCOMMADET always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B19_8.GTPE2_CHANNEL_RXELECIDLE always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B19_10.GTPE2_CHANNEL_RXBUFSTATUS1 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B20_0.GTPE2_CHANNEL_TXBUFSTATUS1 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B20_1.GTPE2_CHANNEL_RXCOMINITDET always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B20_4.GTPE2_CHANNEL_TXRATEDONE always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B20_9.GTPE2_CHANNEL_RXVALID always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B21_4.GTPE2_CHANNEL_DMONITOROUT11 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B21_5.GTPE2_CHANNEL_DMONITOROUT10 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B21_6.GTPE2_CHANNEL_DMONITOROUT9 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B21_7.GTPE2_CHANNEL_DMONITOROUT8 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B21_8.GTPE2_CHANNEL_RXSTATUS0 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B22_0.GTPE2_CHANNEL_RXOUTCLKFABRIC always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B22_1.GTPE2_CHANNEL_RXOUTCLKPCS always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B22_3.GTPE2_CHANNEL_DRPDO1 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B22_4.GTPE2_CHANNEL_RXDISPERR3 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B22_5.GTPE2_CHANNEL_DRPDO6 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B22_6.GTPE2_CHANNEL_RXDISPERR2 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B22_8.GTPE2_CHANNEL_RXDISPERR1 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B22_9.GTPE2_CHANNEL_TXSYNCDONE always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B22_10.GTPE2_CHANNEL_RXDISPERR0 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B23_1.GTPE2_CHANNEL_TXCOMFINISH always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B23_4.GTPE2_CHANNEL_TXGEARBOXREADY always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B23_5.GTPE2_CHANNEL_RXRATEDONE always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B23_6.GTPE2_CHANNEL_RXHEADER1 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B23_8.GTPE2_CHANNEL_RXSTATUS2 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B23_9.GTPE2_CHANNEL_RXCHANREALIGN always +GTP_CHANNEL_0_MID_LEFT.GTPE2_LOGIC_OUTS_B23_10.GTPE2_CHANNEL_RXBUFSTATUS0 always diff --git a/artix7/ppips_gtp_channel_0_mid_right.db b/artix7/ppips_gtp_channel_0_mid_right.db index ab4b943..42e25b9 100644 --- a/artix7/ppips_gtp_channel_0_mid_right.db +++ b/artix7/ppips_gtp_channel_0_mid_right.db @@ -10,6 +10,10 @@ GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_EYESCANTRIGGER.GTPE2_IMUX31_8 always GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_GTRESETSEL.GTPE2_CTRL0_10 always GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_GTRXRESET.GTPE2_CTRL0_8 always GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_GTTXRESET.GTPE2_CTRL0_5 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_PLL0CLK.GTPE2_CHANNEL_PLLCLK0 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_PLL0REFCLK.GTPE2_CHANNEL_PLLREFCLK0 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_PLL1CLK.GTPE2_CHANNEL_PLLCLK1 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_PLL1REFCLK.GTPE2_CHANNEL_PLLREFCLK1 always GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RESETOVRD.GTPE2_IMUX41_5 always GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RX8B10BEN.GTPE2_IMUX45_1 always GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXBUFRESET.GTPE2_CTRL1_6 always @@ -36,6 +40,7 @@ GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXLPMLFOVRDEN.GTPE2_IMUX3_10 always GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXLPMOSINTNTRLEN.GTPE2_IMUX7_2 always GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXLPMRESET.GTPE2_CTRL0_9 always GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXMCOMMAALIGNEN.GTPE2_IMUX41_1 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXN.GTPE2_CHANNEL_RXN_PAD always GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXOOBRESET.GTPE2_CTRL1_10 always GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXOSCALRESET.GTPE2_IMUX46_2 always GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXOSHOLD.GTPE2_IMUX29_8 always @@ -47,6 +52,8 @@ GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXOSINTPD.GTPE2_IMUX3_0 always GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXOSINTSTROBE.GTPE2_IMUX32_9 always GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXOSINTTESTOVRDEN.GTPE2_IMUX5_9 always GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXOSOVRDEN.GTPE2_IMUX13_8 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXOUTCLK_0.GTPE2_CHANNEL_GTRXOUTCLK_0 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXP.GTPE2_CHANNEL_RXP_PAD always GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXPCOMMAALIGNEN.GTPE2_IMUX40_1 always GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXPCSRESET.GTPE2_IMUX46_1 always GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXPHALIGN.GTPE2_IMUX14_9 always @@ -81,6 +88,9 @@ GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXDLYSRESET.GTPE2_IMUX45_3 always GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXDLYUPDOWN.GTPE2_IMUX43_5 always GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXELECIDLE.GTPE2_IMUX39_6 always GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXINHIBIT.GTPE2_IMUX32_2 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXN_PAD.GTPE2_CHANNEL_TXN always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXOUTCLK_0.GTPE2_CHANNEL_GTTXOUTCLK_0 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXP_PAD.GTPE2_CHANNEL_TXP always GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXPCSRESET.GTPE2_IMUX46_0 always GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXPDELECIDLEMODE.GTPE2_IMUX14_0 always GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXPHALIGN.GTPE2_IMUX25_2 always @@ -344,3 +354,173 @@ GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXSEQUENCE6.GTPE2_IMUX8_0 always GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXSYSCLKSEL0.GTPE2_IMUX28_5 always GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXSYSCLKSEL1.GTPE2_IMUX28_4 always GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXUSRCLK2.GTPE2_CLK0_5 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B0_3.GTPE2_CHANNEL_RXOSINTSTROBEDONE always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B0_4.GTPE2_CHANNEL_RXDATA27 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B0_5.GTPE2_CHANNEL_PCSRSVDOUT1 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B0_6.GTPE2_CHANNEL_RXDATA19 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B0_7.GTPE2_CHANNEL_RXOSINTSTROBESTARTED always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B0_8.GTPE2_CHANNEL_RXDATA11 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B0_10.GTPE2_CHANNEL_RXDATA3 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B1_3.GTPE2_CHANNEL_RXDATA30 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B1_5.GTPE2_CHANNEL_RXDATA22 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B1_6.GTPE2_CHANNEL_DMONITOROUT13 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B1_7.GTPE2_CHANNEL_RXDATA14 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B1_8.GTPE2_CHANNEL_DRPDO11 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B1_9.GTPE2_CHANNEL_RXDATA6 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B1_10.GTPE2_CHANNEL_TXPHINITDONE always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B2_4.GTPE2_CHANNEL_RXDATA25 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B2_6.GTPE2_CHANNEL_RXDATA17 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B2_8.GTPE2_CHANNEL_RXDATA9 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B2_9.GTPE2_CHANNEL_DRPDO10 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B2_10.GTPE2_CHANNEL_RXDATA1 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B3_2.GTPE2_CHANNEL_RXPHMONITOR3 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B3_3.GTPE2_CHANNEL_RXDATA28 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B3_5.GTPE2_CHANNEL_RXDATA20 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B3_6.GTPE2_CHANNEL_RXOSINTDONE always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B3_7.GTPE2_CHANNEL_RXDATA12 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B3_9.GTPE2_CHANNEL_RXDATA4 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B4_3.GTPE2_CHANNEL_DRPDO2 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B4_4.GTPE2_CHANNEL_RXDATA26 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B4_5.GTPE2_CHANNEL_DRPDO7 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B4_6.GTPE2_CHANNEL_RXDATA18 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B4_7.GTPE2_CHANNEL_DRPDO15 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B4_8.GTPE2_CHANNEL_RXDATA10 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B4_9.GTPE2_CHANNEL_DRPDO9 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B4_10.GTPE2_CHANNEL_RXDATA2 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B5_1.GTPE2_CHANNEL_RXDATAVALID1 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B5_3.GTPE2_CHANNEL_RXDATA31 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B5_5.GTPE2_CHANNEL_RXDATA23 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B5_6.GTPE2_CHANNEL_PCSRSVDOUT14 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B5_7.GTPE2_CHANNEL_RXDATA15 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B5_8.GTPE2_CHANNEL_PCSRSVDOUT11 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B5_9.GTPE2_CHANNEL_RXDATA7 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B5_10.GTPE2_CHANNEL_PCSRSVDOUT0 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B6_2.GTPE2_CHANNEL_RXPHSLIPMONITOR3 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B6_4.GTPE2_CHANNEL_RXDATA24 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B6_6.GTPE2_CHANNEL_RXDATA16 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B6_7.GTPE2_CHANNEL_RXOSINTSTARTED always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B6_8.GTPE2_CHANNEL_RXDATA8 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B6_10.GTPE2_CHANNEL_RXDATA0 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B7_2.GTPE2_CHANNEL_RXPHMONITOR2 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B7_3.GTPE2_CHANNEL_RXDATA29 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B7_4.GTPE2_CHANNEL_PCSRSVDOUT12 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B7_5.GTPE2_CHANNEL_RXDATA21 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B7_6.GTPE2_CHANNEL_PMARSVDOUT1 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B7_7.GTPE2_CHANNEL_RXDATA13 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B7_8.GTPE2_CHANNEL_DRPDO12 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B7_9.GTPE2_CHANNEL_RXDATA5 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B8_0.GTPE2_CHANNEL_RXBYTEISALIGNED always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B8_1.GTPE2_CHANNEL_RXCHANBONDSEQ always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B9_0.GTPE2_CHANNEL_RXPHSLIPMONITOR2 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B9_2.GTPE2_CHANNEL_PCSRSVDOUT13 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B9_3.GTPE2_CHANNEL_DMONITOROUT7 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B9_4.GTPE2_CHANNEL_DMONITOROUT6 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B9_5.GTPE2_CHANNEL_DMONITOROUT5 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B9_6.GTPE2_CHANNEL_DMONITOROUT4 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B9_7.GTPE2_CHANNEL_DMONITOROUT3 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B9_8.GTPE2_CHANNEL_DMONITOROUT2 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B9_9.GTPE2_CHANNEL_DMONITOROUT1 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B9_10.GTPE2_CHANNEL_DMONITOROUT0 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B10_0.GTPE2_CHANNEL_RXPHMONITOR1 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B10_1.GTPE2_CHANNEL_RXSYNCOUT always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B10_3.GTPE2_CHANNEL_DRPDO4 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B10_5.GTPE2_CHANNEL_DMONITOROUT14 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B10_9.GTPE2_CHANNEL_PHYSTATUS always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B11_0.GTPE2_CHANNEL_RXCLKCORCNT0 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B11_10.GTPE2_CHANNEL_RXSTARTOFSEQ1 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B12_0.GTPE2_CHANNEL_RXDLYSRESETDONE always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B12_1.GTPE2_CHANNEL_RXCOMWAKEDET always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B12_2.GTPE2_CHANNEL_RXPMARESETDONE always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B12_3.GTPE2_CHANNEL_DRPDO0 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B12_4.GTPE2_CHANNEL_RXCHARISK3 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B12_5.GTPE2_CHANNEL_DRPDO5 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B12_6.GTPE2_CHANNEL_RXCHARISK2 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B12_7.GTPE2_CHANNEL_DRPDO14 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B12_8.GTPE2_CHANNEL_RXCHARISK1 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B12_9.GTPE2_CHANNEL_DRPDO8 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B12_10.GTPE2_CHANNEL_RXCHARISK0 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B13_0.GTPE2_CHANNEL_RXPHSLIPMONITOR0 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B13_1.GTPE2_CHANNEL_RXDATAVALID0 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B13_2.GTPE2_CHANNEL_PCSRSVDOUT2 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B13_3.GTPE2_CHANNEL_PCSRSVDOUT3 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B13_4.GTPE2_CHANNEL_PCSRSVDOUT4 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B13_5.GTPE2_CHANNEL_PCSRSVDOUT5 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B13_6.GTPE2_CHANNEL_PCSRSVDOUT6 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B13_7.GTPE2_CHANNEL_PCSRSVDOUT7 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B13_8.GTPE2_CHANNEL_PCSRSVDOUT8 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B13_9.GTPE2_CHANNEL_PCSRSVDOUT9 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B13_10.GTPE2_CHANNEL_PCSRSVDOUT10 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B14_0.GTPE2_CHANNEL_RXBYTEREALIGN always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B14_1.GTPE2_CHANNEL_RXHEADERVALID always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B14_2.GTPE2_CHANNEL_TXPMARESETDONE always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B14_3.GTPE2_CHANNEL_DRPDO3 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B14_4.GTPE2_CHANNEL_RXNOTINTABLE3 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B14_5.GTPE2_CHANNEL_DRPRDY always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B14_6.GTPE2_CHANNEL_RXNOTINTABLE2 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B14_7.GTPE2_CHANNEL_TXSYNCOUT always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B14_8.GTPE2_CHANNEL_RXNOTINTABLE1 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B14_9.GTPE2_CHANNEL_RXSYNCDONE always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B14_10.GTPE2_CHANNEL_RXNOTINTABLE0 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B15_0.GTPE2_CHANNEL_RXCLKCORCNT1 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B15_1.GTPE2_CHANNEL_TXOUTCLKFABRIC always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B15_2.GTPE2_CHANNEL_DMONITOROUT12 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B15_3.GTPE2_CHANNEL_RXCHARISCOMMA3 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B15_4.GTPE2_CHANNEL_PCSRSVDOUT15 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B15_5.GTPE2_CHANNEL_RXCHARISCOMMA2 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B15_6.GTPE2_CHANNEL_PMARSVDOUT0 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B15_7.GTPE2_CHANNEL_RXCHARISCOMMA1 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B15_8.GTPE2_CHANNEL_DRPDO13 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B15_9.GTPE2_CHANNEL_RXCHARISCOMMA0 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B16_0.GTPE2_CHANNEL_RXPHMONITOR0 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B16_1.GTPE2_CHANNEL_RXPRBSERR always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B16_3.GTPE2_CHANNEL_RXPHSLIPMONITOR4 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B16_4.GTPE2_CHANNEL_TXRESETDONE always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B16_7.GTPE2_CHANNEL_RXCHBONDO3 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B16_8.GTPE2_CHANNEL_RXCHBONDO2 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B16_9.GTPE2_CHANNEL_RXCHBONDO1 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B16_10.GTPE2_CHANNEL_RXCHBONDO0 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B17_1.GTPE2_CHANNEL_RXPHMONITOR4 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B17_2.GTPE2_CHANNEL_TXBUFSTATUS0 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B17_3.GTPE2_CHANNEL_TXDLYSRESETDONE always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B17_4.GTPE2_CHANNEL_TXOUTCLKPCS always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B17_5.GTPE2_CHANNEL_RXCDRLOCK always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B17_6.GTPE2_CHANNEL_RXHEADER2 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B17_8.GTPE2_CHANNEL_RXSTATUS1 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B17_10.GTPE2_CHANNEL_RXBUFSTATUS2 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B18_0.GTPE2_CHANNEL_EYESCANDATAERROR always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B18_1.GTPE2_CHANNEL_RXRESETDONE always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B18_3.GTPE2_CHANNEL_TXPHALIGNDONE always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B18_4.GTPE2_CHANNEL_RXPHALIGNDONE always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B18_7.GTPE2_CHANNEL_RXCOMSASDET always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B18_8.GTPE2_CHANNEL_RXSTARTOFSEQ0 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B18_9.GTPE2_CHANNEL_RXCHANISALIGNED always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B19_0.GTPE2_CHANNEL_RXPHSLIPMONITOR1 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B19_6.GTPE2_CHANNEL_RXHEADER0 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B19_7.GTPE2_CHANNEL_RXCOMMADET always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B19_8.GTPE2_CHANNEL_RXELECIDLE always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B19_10.GTPE2_CHANNEL_RXBUFSTATUS1 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B20_0.GTPE2_CHANNEL_TXBUFSTATUS1 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B20_1.GTPE2_CHANNEL_RXCOMINITDET always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B20_4.GTPE2_CHANNEL_TXRATEDONE always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B20_9.GTPE2_CHANNEL_RXVALID always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B21_4.GTPE2_CHANNEL_DMONITOROUT11 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B21_5.GTPE2_CHANNEL_DMONITOROUT10 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B21_6.GTPE2_CHANNEL_DMONITOROUT9 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B21_7.GTPE2_CHANNEL_DMONITOROUT8 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B21_8.GTPE2_CHANNEL_RXSTATUS0 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B22_0.GTPE2_CHANNEL_RXOUTCLKFABRIC always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B22_1.GTPE2_CHANNEL_RXOUTCLKPCS always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B22_3.GTPE2_CHANNEL_DRPDO1 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B22_4.GTPE2_CHANNEL_RXDISPERR3 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B22_5.GTPE2_CHANNEL_DRPDO6 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B22_6.GTPE2_CHANNEL_RXDISPERR2 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B22_8.GTPE2_CHANNEL_RXDISPERR1 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B22_9.GTPE2_CHANNEL_TXSYNCDONE always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B22_10.GTPE2_CHANNEL_RXDISPERR0 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B23_1.GTPE2_CHANNEL_TXCOMFINISH always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B23_4.GTPE2_CHANNEL_TXGEARBOXREADY always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B23_5.GTPE2_CHANNEL_RXRATEDONE always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B23_6.GTPE2_CHANNEL_RXHEADER1 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B23_8.GTPE2_CHANNEL_RXSTATUS2 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B23_9.GTPE2_CHANNEL_RXCHANREALIGN always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_LOGIC_OUTS_B23_10.GTPE2_CHANNEL_RXBUFSTATUS0 always diff --git a/artix7/ppips_gtp_channel_1.db b/artix7/ppips_gtp_channel_1.db index 07a0ab1..7c3ee00 100644 --- a/artix7/ppips_gtp_channel_1.db +++ b/artix7/ppips_gtp_channel_1.db @@ -10,6 +10,10 @@ GTP_CHANNEL_1.GTPE2_CHANNEL_EYESCANTRIGGER.GTPE2_IMUX31_8 always GTP_CHANNEL_1.GTPE2_CHANNEL_GTRESETSEL.GTPE2_CTRL0_10 always GTP_CHANNEL_1.GTPE2_CHANNEL_GTRXRESET.GTPE2_CTRL0_8 always GTP_CHANNEL_1.GTPE2_CHANNEL_GTTXRESET.GTPE2_CTRL0_5 always +GTP_CHANNEL_1.GTPE2_CHANNEL_PLL0CLK.GTPE2_CHANNEL_PLLCLK0 always +GTP_CHANNEL_1.GTPE2_CHANNEL_PLL0REFCLK.GTPE2_CHANNEL_PLLREFCLK0 always +GTP_CHANNEL_1.GTPE2_CHANNEL_PLL1CLK.GTPE2_CHANNEL_PLLCLK1 always +GTP_CHANNEL_1.GTPE2_CHANNEL_PLL1REFCLK.GTPE2_CHANNEL_PLLREFCLK1 always GTP_CHANNEL_1.GTPE2_CHANNEL_RESETOVRD.GTPE2_IMUX41_5 always GTP_CHANNEL_1.GTPE2_CHANNEL_RX8B10BEN.GTPE2_IMUX45_1 always GTP_CHANNEL_1.GTPE2_CHANNEL_RXBUFRESET.GTPE2_CTRL1_6 always @@ -36,6 +40,7 @@ GTP_CHANNEL_1.GTPE2_CHANNEL_RXLPMLFOVRDEN.GTPE2_IMUX3_10 always GTP_CHANNEL_1.GTPE2_CHANNEL_RXLPMOSINTNTRLEN.GTPE2_IMUX7_2 always GTP_CHANNEL_1.GTPE2_CHANNEL_RXLPMRESET.GTPE2_CTRL0_9 always GTP_CHANNEL_1.GTPE2_CHANNEL_RXMCOMMAALIGNEN.GTPE2_IMUX41_1 always +GTP_CHANNEL_1.GTPE2_CHANNEL_RXN.GTPE2_CHANNEL_RXN_PAD always GTP_CHANNEL_1.GTPE2_CHANNEL_RXOOBRESET.GTPE2_CTRL1_10 always GTP_CHANNEL_1.GTPE2_CHANNEL_RXOSCALRESET.GTPE2_IMUX46_2 always GTP_CHANNEL_1.GTPE2_CHANNEL_RXOSHOLD.GTPE2_IMUX29_8 always @@ -47,6 +52,8 @@ GTP_CHANNEL_1.GTPE2_CHANNEL_RXOSINTPD.GTPE2_IMUX3_0 always GTP_CHANNEL_1.GTPE2_CHANNEL_RXOSINTSTROBE.GTPE2_IMUX32_9 always GTP_CHANNEL_1.GTPE2_CHANNEL_RXOSINTTESTOVRDEN.GTPE2_IMUX5_9 always GTP_CHANNEL_1.GTPE2_CHANNEL_RXOSOVRDEN.GTPE2_IMUX13_8 always +GTP_CHANNEL_1.GTPE2_CHANNEL_RXOUTCLK_1.GTPE2_CHANNEL_GTRXOUTCLK_1 always +GTP_CHANNEL_1.GTPE2_CHANNEL_RXP.GTPE2_CHANNEL_RXP_PAD always GTP_CHANNEL_1.GTPE2_CHANNEL_RXPCOMMAALIGNEN.GTPE2_IMUX40_1 always GTP_CHANNEL_1.GTPE2_CHANNEL_RXPCSRESET.GTPE2_IMUX46_1 always GTP_CHANNEL_1.GTPE2_CHANNEL_RXPHALIGN.GTPE2_IMUX14_9 always @@ -81,6 +88,9 @@ GTP_CHANNEL_1.GTPE2_CHANNEL_TXDLYSRESET.GTPE2_IMUX45_3 always GTP_CHANNEL_1.GTPE2_CHANNEL_TXDLYUPDOWN.GTPE2_IMUX43_5 always GTP_CHANNEL_1.GTPE2_CHANNEL_TXELECIDLE.GTPE2_IMUX39_6 always GTP_CHANNEL_1.GTPE2_CHANNEL_TXINHIBIT.GTPE2_IMUX32_2 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TXN_PAD.GTPE2_CHANNEL_TXN always +GTP_CHANNEL_1.GTPE2_CHANNEL_TXOUTCLK_1.GTPE2_CHANNEL_GTTXOUTCLK_1 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TXP_PAD.GTPE2_CHANNEL_TXP always GTP_CHANNEL_1.GTPE2_CHANNEL_TXPCSRESET.GTPE2_IMUX46_0 always GTP_CHANNEL_1.GTPE2_CHANNEL_TXPDELECIDLEMODE.GTPE2_IMUX14_0 always GTP_CHANNEL_1.GTPE2_CHANNEL_TXPHALIGN.GTPE2_IMUX25_2 always @@ -344,3 +354,173 @@ GTP_CHANNEL_1.GTPE2_CHANNEL_TXSEQUENCE6.GTPE2_IMUX8_0 always GTP_CHANNEL_1.GTPE2_CHANNEL_TXSYSCLKSEL0.GTPE2_IMUX28_5 always GTP_CHANNEL_1.GTPE2_CHANNEL_TXSYSCLKSEL1.GTPE2_IMUX28_4 always GTP_CHANNEL_1.GTPE2_CHANNEL_TXUSRCLK2.GTPE2_CLK0_5 always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B0_3.GTPE2_CHANNEL_RXOSINTSTROBEDONE always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B0_4.GTPE2_CHANNEL_RXDATA27 always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B0_5.GTPE2_CHANNEL_PCSRSVDOUT1 always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B0_6.GTPE2_CHANNEL_RXDATA19 always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B0_7.GTPE2_CHANNEL_RXOSINTSTROBESTARTED always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B0_8.GTPE2_CHANNEL_RXDATA11 always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B0_10.GTPE2_CHANNEL_RXDATA3 always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B1_3.GTPE2_CHANNEL_RXDATA30 always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B1_5.GTPE2_CHANNEL_RXDATA22 always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B1_6.GTPE2_CHANNEL_DMONITOROUT13 always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B1_7.GTPE2_CHANNEL_RXDATA14 always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B1_8.GTPE2_CHANNEL_DRPDO11 always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B1_9.GTPE2_CHANNEL_RXDATA6 always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B1_10.GTPE2_CHANNEL_TXPHINITDONE always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B2_4.GTPE2_CHANNEL_RXDATA25 always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B2_6.GTPE2_CHANNEL_RXDATA17 always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B2_8.GTPE2_CHANNEL_RXDATA9 always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B2_9.GTPE2_CHANNEL_DRPDO10 always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B2_10.GTPE2_CHANNEL_RXDATA1 always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B3_2.GTPE2_CHANNEL_RXPHMONITOR3 always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B3_3.GTPE2_CHANNEL_RXDATA28 always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B3_5.GTPE2_CHANNEL_RXDATA20 always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B3_6.GTPE2_CHANNEL_RXOSINTDONE always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B3_7.GTPE2_CHANNEL_RXDATA12 always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B3_9.GTPE2_CHANNEL_RXDATA4 always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B4_3.GTPE2_CHANNEL_DRPDO2 always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B4_4.GTPE2_CHANNEL_RXDATA26 always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B4_5.GTPE2_CHANNEL_DRPDO7 always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B4_6.GTPE2_CHANNEL_RXDATA18 always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B4_7.GTPE2_CHANNEL_DRPDO15 always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B4_8.GTPE2_CHANNEL_RXDATA10 always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B4_9.GTPE2_CHANNEL_DRPDO9 always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B4_10.GTPE2_CHANNEL_RXDATA2 always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B5_1.GTPE2_CHANNEL_RXDATAVALID1 always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B5_3.GTPE2_CHANNEL_RXDATA31 always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B5_5.GTPE2_CHANNEL_RXDATA23 always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B5_6.GTPE2_CHANNEL_PCSRSVDOUT14 always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B5_7.GTPE2_CHANNEL_RXDATA15 always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B5_8.GTPE2_CHANNEL_PCSRSVDOUT11 always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B5_9.GTPE2_CHANNEL_RXDATA7 always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B5_10.GTPE2_CHANNEL_PCSRSVDOUT0 always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B6_2.GTPE2_CHANNEL_RXPHSLIPMONITOR3 always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B6_4.GTPE2_CHANNEL_RXDATA24 always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B6_6.GTPE2_CHANNEL_RXDATA16 always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B6_7.GTPE2_CHANNEL_RXOSINTSTARTED always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B6_8.GTPE2_CHANNEL_RXDATA8 always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B6_10.GTPE2_CHANNEL_RXDATA0 always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B7_2.GTPE2_CHANNEL_RXPHMONITOR2 always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B7_3.GTPE2_CHANNEL_RXDATA29 always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B7_4.GTPE2_CHANNEL_PCSRSVDOUT12 always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B7_5.GTPE2_CHANNEL_RXDATA21 always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B7_6.GTPE2_CHANNEL_PMARSVDOUT1 always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B7_7.GTPE2_CHANNEL_RXDATA13 always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B7_8.GTPE2_CHANNEL_DRPDO12 always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B7_9.GTPE2_CHANNEL_RXDATA5 always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B8_0.GTPE2_CHANNEL_RXBYTEISALIGNED always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B8_1.GTPE2_CHANNEL_RXCHANBONDSEQ always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B9_0.GTPE2_CHANNEL_RXPHSLIPMONITOR2 always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B9_2.GTPE2_CHANNEL_PCSRSVDOUT13 always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B9_3.GTPE2_CHANNEL_DMONITOROUT7 always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B9_4.GTPE2_CHANNEL_DMONITOROUT6 always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B9_5.GTPE2_CHANNEL_DMONITOROUT5 always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B9_6.GTPE2_CHANNEL_DMONITOROUT4 always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B9_7.GTPE2_CHANNEL_DMONITOROUT3 always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B9_8.GTPE2_CHANNEL_DMONITOROUT2 always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B9_9.GTPE2_CHANNEL_DMONITOROUT1 always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B9_10.GTPE2_CHANNEL_DMONITOROUT0 always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B10_0.GTPE2_CHANNEL_RXPHMONITOR1 always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B10_1.GTPE2_CHANNEL_RXSYNCOUT always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B10_3.GTPE2_CHANNEL_DRPDO4 always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B10_5.GTPE2_CHANNEL_DMONITOROUT14 always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B10_9.GTPE2_CHANNEL_PHYSTATUS always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B11_0.GTPE2_CHANNEL_RXCLKCORCNT0 always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B11_10.GTPE2_CHANNEL_RXSTARTOFSEQ1 always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B12_0.GTPE2_CHANNEL_RXDLYSRESETDONE always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B12_1.GTPE2_CHANNEL_RXCOMWAKEDET always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B12_2.GTPE2_CHANNEL_RXPMARESETDONE always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B12_3.GTPE2_CHANNEL_DRPDO0 always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B12_4.GTPE2_CHANNEL_RXCHARISK3 always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B12_5.GTPE2_CHANNEL_DRPDO5 always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B12_6.GTPE2_CHANNEL_RXCHARISK2 always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B12_7.GTPE2_CHANNEL_DRPDO14 always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B12_8.GTPE2_CHANNEL_RXCHARISK1 always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B12_9.GTPE2_CHANNEL_DRPDO8 always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B12_10.GTPE2_CHANNEL_RXCHARISK0 always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B13_0.GTPE2_CHANNEL_RXPHSLIPMONITOR0 always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B13_1.GTPE2_CHANNEL_RXDATAVALID0 always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B13_2.GTPE2_CHANNEL_PCSRSVDOUT2 always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B13_3.GTPE2_CHANNEL_PCSRSVDOUT3 always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B13_4.GTPE2_CHANNEL_PCSRSVDOUT4 always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B13_5.GTPE2_CHANNEL_PCSRSVDOUT5 always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B13_6.GTPE2_CHANNEL_PCSRSVDOUT6 always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B13_7.GTPE2_CHANNEL_PCSRSVDOUT7 always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B13_8.GTPE2_CHANNEL_PCSRSVDOUT8 always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B13_9.GTPE2_CHANNEL_PCSRSVDOUT9 always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B13_10.GTPE2_CHANNEL_PCSRSVDOUT10 always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B14_0.GTPE2_CHANNEL_RXBYTEREALIGN always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B14_1.GTPE2_CHANNEL_RXHEADERVALID always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B14_2.GTPE2_CHANNEL_TXPMARESETDONE always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B14_3.GTPE2_CHANNEL_DRPDO3 always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B14_4.GTPE2_CHANNEL_RXNOTINTABLE3 always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B14_5.GTPE2_CHANNEL_DRPRDY always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B14_6.GTPE2_CHANNEL_RXNOTINTABLE2 always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B14_7.GTPE2_CHANNEL_TXSYNCOUT always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B14_8.GTPE2_CHANNEL_RXNOTINTABLE1 always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B14_9.GTPE2_CHANNEL_RXSYNCDONE always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B14_10.GTPE2_CHANNEL_RXNOTINTABLE0 always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B15_0.GTPE2_CHANNEL_RXCLKCORCNT1 always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B15_1.GTPE2_CHANNEL_TXOUTCLKFABRIC always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B15_2.GTPE2_CHANNEL_DMONITOROUT12 always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B15_3.GTPE2_CHANNEL_RXCHARISCOMMA3 always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B15_4.GTPE2_CHANNEL_PCSRSVDOUT15 always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B15_5.GTPE2_CHANNEL_RXCHARISCOMMA2 always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B15_6.GTPE2_CHANNEL_PMARSVDOUT0 always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B15_7.GTPE2_CHANNEL_RXCHARISCOMMA1 always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B15_8.GTPE2_CHANNEL_DRPDO13 always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B15_9.GTPE2_CHANNEL_RXCHARISCOMMA0 always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B16_0.GTPE2_CHANNEL_RXPHMONITOR0 always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B16_1.GTPE2_CHANNEL_RXPRBSERR always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B16_3.GTPE2_CHANNEL_RXPHSLIPMONITOR4 always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B16_4.GTPE2_CHANNEL_TXRESETDONE always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B16_7.GTPE2_CHANNEL_RXCHBONDO3 always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B16_8.GTPE2_CHANNEL_RXCHBONDO2 always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B16_9.GTPE2_CHANNEL_RXCHBONDO1 always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B16_10.GTPE2_CHANNEL_RXCHBONDO0 always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B17_1.GTPE2_CHANNEL_RXPHMONITOR4 always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B17_2.GTPE2_CHANNEL_TXBUFSTATUS0 always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B17_3.GTPE2_CHANNEL_TXDLYSRESETDONE always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B17_4.GTPE2_CHANNEL_TXOUTCLKPCS always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B17_5.GTPE2_CHANNEL_RXCDRLOCK always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B17_6.GTPE2_CHANNEL_RXHEADER2 always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B17_8.GTPE2_CHANNEL_RXSTATUS1 always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B17_10.GTPE2_CHANNEL_RXBUFSTATUS2 always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B18_0.GTPE2_CHANNEL_EYESCANDATAERROR always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B18_1.GTPE2_CHANNEL_RXRESETDONE always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B18_3.GTPE2_CHANNEL_TXPHALIGNDONE always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B18_4.GTPE2_CHANNEL_RXPHALIGNDONE always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B18_7.GTPE2_CHANNEL_RXCOMSASDET always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B18_8.GTPE2_CHANNEL_RXSTARTOFSEQ0 always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B18_9.GTPE2_CHANNEL_RXCHANISALIGNED always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B19_0.GTPE2_CHANNEL_RXPHSLIPMONITOR1 always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B19_6.GTPE2_CHANNEL_RXHEADER0 always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B19_7.GTPE2_CHANNEL_RXCOMMADET always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B19_8.GTPE2_CHANNEL_RXELECIDLE always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B19_10.GTPE2_CHANNEL_RXBUFSTATUS1 always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B20_0.GTPE2_CHANNEL_TXBUFSTATUS1 always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B20_1.GTPE2_CHANNEL_RXCOMINITDET always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B20_4.GTPE2_CHANNEL_TXRATEDONE always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B20_9.GTPE2_CHANNEL_RXVALID always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B21_4.GTPE2_CHANNEL_DMONITOROUT11 always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B21_5.GTPE2_CHANNEL_DMONITOROUT10 always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B21_6.GTPE2_CHANNEL_DMONITOROUT9 always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B21_7.GTPE2_CHANNEL_DMONITOROUT8 always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B21_8.GTPE2_CHANNEL_RXSTATUS0 always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B22_0.GTPE2_CHANNEL_RXOUTCLKFABRIC always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B22_1.GTPE2_CHANNEL_RXOUTCLKPCS always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B22_3.GTPE2_CHANNEL_DRPDO1 always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B22_4.GTPE2_CHANNEL_RXDISPERR3 always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B22_5.GTPE2_CHANNEL_DRPDO6 always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B22_6.GTPE2_CHANNEL_RXDISPERR2 always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B22_8.GTPE2_CHANNEL_RXDISPERR1 always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B22_9.GTPE2_CHANNEL_TXSYNCDONE always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B22_10.GTPE2_CHANNEL_RXDISPERR0 always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B23_1.GTPE2_CHANNEL_TXCOMFINISH always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B23_4.GTPE2_CHANNEL_TXGEARBOXREADY always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B23_5.GTPE2_CHANNEL_RXRATEDONE always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B23_6.GTPE2_CHANNEL_RXHEADER1 always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B23_8.GTPE2_CHANNEL_RXSTATUS2 always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B23_9.GTPE2_CHANNEL_RXCHANREALIGN always +GTP_CHANNEL_1.GTPE2_LOGIC_OUTS_B23_10.GTPE2_CHANNEL_RXBUFSTATUS0 always diff --git a/artix7/ppips_gtp_channel_1_mid_left.db b/artix7/ppips_gtp_channel_1_mid_left.db index 1ca3707..e9a840c 100644 --- a/artix7/ppips_gtp_channel_1_mid_left.db +++ b/artix7/ppips_gtp_channel_1_mid_left.db @@ -10,6 +10,10 @@ GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_EYESCANTRIGGER.GTPE2_IMUX31_8 always GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_GTRESETSEL.GTPE2_CTRL0_10 always GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_GTRXRESET.GTPE2_CTRL0_8 always GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_GTTXRESET.GTPE2_CTRL0_5 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_PLL0CLK.GTPE2_CHANNEL_PLLCLK0 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_PLL0REFCLK.GTPE2_CHANNEL_PLLREFCLK0 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_PLL1CLK.GTPE2_CHANNEL_PLLCLK1 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_PLL1REFCLK.GTPE2_CHANNEL_PLLREFCLK1 always GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RESETOVRD.GTPE2_IMUX41_5 always GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RX8B10BEN.GTPE2_IMUX45_1 always GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXBUFRESET.GTPE2_CTRL1_6 always @@ -36,6 +40,7 @@ GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXLPMLFOVRDEN.GTPE2_IMUX3_10 always GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXLPMOSINTNTRLEN.GTPE2_IMUX7_2 always GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXLPMRESET.GTPE2_CTRL0_9 always GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXMCOMMAALIGNEN.GTPE2_IMUX41_1 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXN.GTPE2_CHANNEL_RXN_PAD always GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXOOBRESET.GTPE2_CTRL1_10 always GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXOSCALRESET.GTPE2_IMUX46_2 always GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXOSHOLD.GTPE2_IMUX29_8 always @@ -47,6 +52,8 @@ GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXOSINTPD.GTPE2_IMUX3_0 always GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXOSINTSTROBE.GTPE2_IMUX32_9 always GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXOSINTTESTOVRDEN.GTPE2_IMUX5_9 always GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXOSOVRDEN.GTPE2_IMUX13_8 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXOUTCLK_1.GTPE2_CHANNEL_GTRXOUTCLK_1 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXP.GTPE2_CHANNEL_RXP_PAD always GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXPCOMMAALIGNEN.GTPE2_IMUX40_1 always GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXPCSRESET.GTPE2_IMUX46_1 always GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXPHALIGN.GTPE2_IMUX14_9 always @@ -81,6 +88,9 @@ GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXDLYSRESET.GTPE2_IMUX45_3 always GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXDLYUPDOWN.GTPE2_IMUX43_5 always GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXELECIDLE.GTPE2_IMUX39_6 always GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXINHIBIT.GTPE2_IMUX32_2 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXN_PAD.GTPE2_CHANNEL_TXN always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXOUTCLK_1.GTPE2_CHANNEL_GTTXOUTCLK_1 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXP_PAD.GTPE2_CHANNEL_TXP always GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXPCSRESET.GTPE2_IMUX46_0 always GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXPDELECIDLEMODE.GTPE2_IMUX14_0 always GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXPHALIGN.GTPE2_IMUX25_2 always @@ -344,3 +354,173 @@ GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXSEQUENCE6.GTPE2_IMUX8_0 always GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXSYSCLKSEL0.GTPE2_IMUX28_5 always GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXSYSCLKSEL1.GTPE2_IMUX28_4 always GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXUSRCLK2.GTPE2_CLK0_5 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B0_3.GTPE2_CHANNEL_RXOSINTSTROBEDONE always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B0_4.GTPE2_CHANNEL_RXDATA27 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B0_5.GTPE2_CHANNEL_PCSRSVDOUT1 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B0_6.GTPE2_CHANNEL_RXDATA19 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B0_7.GTPE2_CHANNEL_RXOSINTSTROBESTARTED always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B0_8.GTPE2_CHANNEL_RXDATA11 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B0_10.GTPE2_CHANNEL_RXDATA3 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B1_3.GTPE2_CHANNEL_RXDATA30 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B1_5.GTPE2_CHANNEL_RXDATA22 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B1_6.GTPE2_CHANNEL_DMONITOROUT13 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B1_7.GTPE2_CHANNEL_RXDATA14 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B1_8.GTPE2_CHANNEL_DRPDO11 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B1_9.GTPE2_CHANNEL_RXDATA6 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B1_10.GTPE2_CHANNEL_TXPHINITDONE always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B2_4.GTPE2_CHANNEL_RXDATA25 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B2_6.GTPE2_CHANNEL_RXDATA17 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B2_8.GTPE2_CHANNEL_RXDATA9 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B2_9.GTPE2_CHANNEL_DRPDO10 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B2_10.GTPE2_CHANNEL_RXDATA1 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B3_2.GTPE2_CHANNEL_RXPHMONITOR3 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B3_3.GTPE2_CHANNEL_RXDATA28 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B3_5.GTPE2_CHANNEL_RXDATA20 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B3_6.GTPE2_CHANNEL_RXOSINTDONE always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B3_7.GTPE2_CHANNEL_RXDATA12 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B3_9.GTPE2_CHANNEL_RXDATA4 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B4_3.GTPE2_CHANNEL_DRPDO2 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B4_4.GTPE2_CHANNEL_RXDATA26 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B4_5.GTPE2_CHANNEL_DRPDO7 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B4_6.GTPE2_CHANNEL_RXDATA18 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B4_7.GTPE2_CHANNEL_DRPDO15 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B4_8.GTPE2_CHANNEL_RXDATA10 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B4_9.GTPE2_CHANNEL_DRPDO9 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B4_10.GTPE2_CHANNEL_RXDATA2 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B5_1.GTPE2_CHANNEL_RXDATAVALID1 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B5_3.GTPE2_CHANNEL_RXDATA31 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B5_5.GTPE2_CHANNEL_RXDATA23 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B5_6.GTPE2_CHANNEL_PCSRSVDOUT14 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B5_7.GTPE2_CHANNEL_RXDATA15 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B5_8.GTPE2_CHANNEL_PCSRSVDOUT11 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B5_9.GTPE2_CHANNEL_RXDATA7 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B5_10.GTPE2_CHANNEL_PCSRSVDOUT0 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B6_2.GTPE2_CHANNEL_RXPHSLIPMONITOR3 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B6_4.GTPE2_CHANNEL_RXDATA24 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B6_6.GTPE2_CHANNEL_RXDATA16 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B6_7.GTPE2_CHANNEL_RXOSINTSTARTED always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B6_8.GTPE2_CHANNEL_RXDATA8 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B6_10.GTPE2_CHANNEL_RXDATA0 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B7_2.GTPE2_CHANNEL_RXPHMONITOR2 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B7_3.GTPE2_CHANNEL_RXDATA29 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B7_4.GTPE2_CHANNEL_PCSRSVDOUT12 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B7_5.GTPE2_CHANNEL_RXDATA21 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B7_6.GTPE2_CHANNEL_PMARSVDOUT1 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B7_7.GTPE2_CHANNEL_RXDATA13 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B7_8.GTPE2_CHANNEL_DRPDO12 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B7_9.GTPE2_CHANNEL_RXDATA5 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B8_0.GTPE2_CHANNEL_RXBYTEISALIGNED always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B8_1.GTPE2_CHANNEL_RXCHANBONDSEQ always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B9_0.GTPE2_CHANNEL_RXPHSLIPMONITOR2 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B9_2.GTPE2_CHANNEL_PCSRSVDOUT13 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B9_3.GTPE2_CHANNEL_DMONITOROUT7 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B9_4.GTPE2_CHANNEL_DMONITOROUT6 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B9_5.GTPE2_CHANNEL_DMONITOROUT5 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B9_6.GTPE2_CHANNEL_DMONITOROUT4 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B9_7.GTPE2_CHANNEL_DMONITOROUT3 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B9_8.GTPE2_CHANNEL_DMONITOROUT2 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B9_9.GTPE2_CHANNEL_DMONITOROUT1 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B9_10.GTPE2_CHANNEL_DMONITOROUT0 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B10_0.GTPE2_CHANNEL_RXPHMONITOR1 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B10_1.GTPE2_CHANNEL_RXSYNCOUT always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B10_3.GTPE2_CHANNEL_DRPDO4 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B10_5.GTPE2_CHANNEL_DMONITOROUT14 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B10_9.GTPE2_CHANNEL_PHYSTATUS always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B11_0.GTPE2_CHANNEL_RXCLKCORCNT0 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B11_10.GTPE2_CHANNEL_RXSTARTOFSEQ1 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B12_0.GTPE2_CHANNEL_RXDLYSRESETDONE always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B12_1.GTPE2_CHANNEL_RXCOMWAKEDET always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B12_2.GTPE2_CHANNEL_RXPMARESETDONE always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B12_3.GTPE2_CHANNEL_DRPDO0 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B12_4.GTPE2_CHANNEL_RXCHARISK3 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B12_5.GTPE2_CHANNEL_DRPDO5 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B12_6.GTPE2_CHANNEL_RXCHARISK2 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B12_7.GTPE2_CHANNEL_DRPDO14 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B12_8.GTPE2_CHANNEL_RXCHARISK1 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B12_9.GTPE2_CHANNEL_DRPDO8 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B12_10.GTPE2_CHANNEL_RXCHARISK0 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B13_0.GTPE2_CHANNEL_RXPHSLIPMONITOR0 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B13_1.GTPE2_CHANNEL_RXDATAVALID0 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B13_2.GTPE2_CHANNEL_PCSRSVDOUT2 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B13_3.GTPE2_CHANNEL_PCSRSVDOUT3 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B13_4.GTPE2_CHANNEL_PCSRSVDOUT4 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B13_5.GTPE2_CHANNEL_PCSRSVDOUT5 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B13_6.GTPE2_CHANNEL_PCSRSVDOUT6 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B13_7.GTPE2_CHANNEL_PCSRSVDOUT7 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B13_8.GTPE2_CHANNEL_PCSRSVDOUT8 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B13_9.GTPE2_CHANNEL_PCSRSVDOUT9 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B13_10.GTPE2_CHANNEL_PCSRSVDOUT10 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B14_0.GTPE2_CHANNEL_RXBYTEREALIGN always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B14_1.GTPE2_CHANNEL_RXHEADERVALID always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B14_2.GTPE2_CHANNEL_TXPMARESETDONE always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B14_3.GTPE2_CHANNEL_DRPDO3 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B14_4.GTPE2_CHANNEL_RXNOTINTABLE3 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B14_5.GTPE2_CHANNEL_DRPRDY always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B14_6.GTPE2_CHANNEL_RXNOTINTABLE2 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B14_7.GTPE2_CHANNEL_TXSYNCOUT always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B14_8.GTPE2_CHANNEL_RXNOTINTABLE1 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B14_9.GTPE2_CHANNEL_RXSYNCDONE always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B14_10.GTPE2_CHANNEL_RXNOTINTABLE0 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B15_0.GTPE2_CHANNEL_RXCLKCORCNT1 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B15_1.GTPE2_CHANNEL_TXOUTCLKFABRIC always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B15_2.GTPE2_CHANNEL_DMONITOROUT12 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B15_3.GTPE2_CHANNEL_RXCHARISCOMMA3 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B15_4.GTPE2_CHANNEL_PCSRSVDOUT15 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B15_5.GTPE2_CHANNEL_RXCHARISCOMMA2 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B15_6.GTPE2_CHANNEL_PMARSVDOUT0 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B15_7.GTPE2_CHANNEL_RXCHARISCOMMA1 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B15_8.GTPE2_CHANNEL_DRPDO13 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B15_9.GTPE2_CHANNEL_RXCHARISCOMMA0 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B16_0.GTPE2_CHANNEL_RXPHMONITOR0 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B16_1.GTPE2_CHANNEL_RXPRBSERR always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B16_3.GTPE2_CHANNEL_RXPHSLIPMONITOR4 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B16_4.GTPE2_CHANNEL_TXRESETDONE always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B16_7.GTPE2_CHANNEL_RXCHBONDO3 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B16_8.GTPE2_CHANNEL_RXCHBONDO2 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B16_9.GTPE2_CHANNEL_RXCHBONDO1 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B16_10.GTPE2_CHANNEL_RXCHBONDO0 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B17_1.GTPE2_CHANNEL_RXPHMONITOR4 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B17_2.GTPE2_CHANNEL_TXBUFSTATUS0 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B17_3.GTPE2_CHANNEL_TXDLYSRESETDONE always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B17_4.GTPE2_CHANNEL_TXOUTCLKPCS always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B17_5.GTPE2_CHANNEL_RXCDRLOCK always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B17_6.GTPE2_CHANNEL_RXHEADER2 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B17_8.GTPE2_CHANNEL_RXSTATUS1 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B17_10.GTPE2_CHANNEL_RXBUFSTATUS2 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B18_0.GTPE2_CHANNEL_EYESCANDATAERROR always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B18_1.GTPE2_CHANNEL_RXRESETDONE always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B18_3.GTPE2_CHANNEL_TXPHALIGNDONE always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B18_4.GTPE2_CHANNEL_RXPHALIGNDONE always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B18_7.GTPE2_CHANNEL_RXCOMSASDET always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B18_8.GTPE2_CHANNEL_RXSTARTOFSEQ0 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B18_9.GTPE2_CHANNEL_RXCHANISALIGNED always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B19_0.GTPE2_CHANNEL_RXPHSLIPMONITOR1 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B19_6.GTPE2_CHANNEL_RXHEADER0 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B19_7.GTPE2_CHANNEL_RXCOMMADET always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B19_8.GTPE2_CHANNEL_RXELECIDLE always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B19_10.GTPE2_CHANNEL_RXBUFSTATUS1 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B20_0.GTPE2_CHANNEL_TXBUFSTATUS1 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B20_1.GTPE2_CHANNEL_RXCOMINITDET always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B20_4.GTPE2_CHANNEL_TXRATEDONE always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B20_9.GTPE2_CHANNEL_RXVALID always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B21_4.GTPE2_CHANNEL_DMONITOROUT11 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B21_5.GTPE2_CHANNEL_DMONITOROUT10 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B21_6.GTPE2_CHANNEL_DMONITOROUT9 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B21_7.GTPE2_CHANNEL_DMONITOROUT8 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B21_8.GTPE2_CHANNEL_RXSTATUS0 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B22_0.GTPE2_CHANNEL_RXOUTCLKFABRIC always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B22_1.GTPE2_CHANNEL_RXOUTCLKPCS always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B22_3.GTPE2_CHANNEL_DRPDO1 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B22_4.GTPE2_CHANNEL_RXDISPERR3 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B22_5.GTPE2_CHANNEL_DRPDO6 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B22_6.GTPE2_CHANNEL_RXDISPERR2 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B22_8.GTPE2_CHANNEL_RXDISPERR1 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B22_9.GTPE2_CHANNEL_TXSYNCDONE always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B22_10.GTPE2_CHANNEL_RXDISPERR0 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B23_1.GTPE2_CHANNEL_TXCOMFINISH always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B23_4.GTPE2_CHANNEL_TXGEARBOXREADY always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B23_5.GTPE2_CHANNEL_RXRATEDONE always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B23_6.GTPE2_CHANNEL_RXHEADER1 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B23_8.GTPE2_CHANNEL_RXSTATUS2 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B23_9.GTPE2_CHANNEL_RXCHANREALIGN always +GTP_CHANNEL_1_MID_LEFT.GTPE2_LOGIC_OUTS_B23_10.GTPE2_CHANNEL_RXBUFSTATUS0 always diff --git a/artix7/ppips_gtp_channel_1_mid_right.db b/artix7/ppips_gtp_channel_1_mid_right.db index d809506..0052723 100644 --- a/artix7/ppips_gtp_channel_1_mid_right.db +++ b/artix7/ppips_gtp_channel_1_mid_right.db @@ -10,6 +10,10 @@ GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_EYESCANTRIGGER.GTPE2_IMUX31_8 always GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_GTRESETSEL.GTPE2_CTRL0_10 always GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_GTRXRESET.GTPE2_CTRL0_8 always GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_GTTXRESET.GTPE2_CTRL0_5 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_PLL0CLK.GTPE2_CHANNEL_PLLCLK0 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_PLL0REFCLK.GTPE2_CHANNEL_PLLREFCLK0 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_PLL1CLK.GTPE2_CHANNEL_PLLCLK1 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_PLL1REFCLK.GTPE2_CHANNEL_PLLREFCLK1 always GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RESETOVRD.GTPE2_IMUX41_5 always GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RX8B10BEN.GTPE2_IMUX45_1 always GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXBUFRESET.GTPE2_CTRL1_6 always @@ -36,6 +40,7 @@ GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXLPMLFOVRDEN.GTPE2_IMUX3_10 always GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXLPMOSINTNTRLEN.GTPE2_IMUX7_2 always GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXLPMRESET.GTPE2_CTRL0_9 always GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXMCOMMAALIGNEN.GTPE2_IMUX41_1 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXN.GTPE2_CHANNEL_RXN_PAD always GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXOOBRESET.GTPE2_CTRL1_10 always GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXOSCALRESET.GTPE2_IMUX46_2 always GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXOSHOLD.GTPE2_IMUX29_8 always @@ -47,6 +52,8 @@ GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXOSINTPD.GTPE2_IMUX3_0 always GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXOSINTSTROBE.GTPE2_IMUX32_9 always GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXOSINTTESTOVRDEN.GTPE2_IMUX5_9 always GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXOSOVRDEN.GTPE2_IMUX13_8 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXOUTCLK_1.GTPE2_CHANNEL_GTRXOUTCLK_1 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXP.GTPE2_CHANNEL_RXP_PAD always GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXPCOMMAALIGNEN.GTPE2_IMUX40_1 always GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXPCSRESET.GTPE2_IMUX46_1 always GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXPHALIGN.GTPE2_IMUX14_9 always @@ -81,6 +88,9 @@ GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXDLYSRESET.GTPE2_IMUX45_3 always GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXDLYUPDOWN.GTPE2_IMUX43_5 always GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXELECIDLE.GTPE2_IMUX39_6 always GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXINHIBIT.GTPE2_IMUX32_2 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXN_PAD.GTPE2_CHANNEL_TXN always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXOUTCLK_1.GTPE2_CHANNEL_GTTXOUTCLK_1 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXP_PAD.GTPE2_CHANNEL_TXP always GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXPCSRESET.GTPE2_IMUX46_0 always GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXPDELECIDLEMODE.GTPE2_IMUX14_0 always GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXPHALIGN.GTPE2_IMUX25_2 always @@ -344,3 +354,173 @@ GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXSEQUENCE6.GTPE2_IMUX8_0 always GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXSYSCLKSEL0.GTPE2_IMUX28_5 always GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXSYSCLKSEL1.GTPE2_IMUX28_4 always GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXUSRCLK2.GTPE2_CLK0_5 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B0_3.GTPE2_CHANNEL_RXOSINTSTROBEDONE always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B0_4.GTPE2_CHANNEL_RXDATA27 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B0_5.GTPE2_CHANNEL_PCSRSVDOUT1 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B0_6.GTPE2_CHANNEL_RXDATA19 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B0_7.GTPE2_CHANNEL_RXOSINTSTROBESTARTED always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B0_8.GTPE2_CHANNEL_RXDATA11 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B0_10.GTPE2_CHANNEL_RXDATA3 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B1_3.GTPE2_CHANNEL_RXDATA30 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B1_5.GTPE2_CHANNEL_RXDATA22 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B1_6.GTPE2_CHANNEL_DMONITOROUT13 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B1_7.GTPE2_CHANNEL_RXDATA14 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B1_8.GTPE2_CHANNEL_DRPDO11 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B1_9.GTPE2_CHANNEL_RXDATA6 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B1_10.GTPE2_CHANNEL_TXPHINITDONE always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B2_4.GTPE2_CHANNEL_RXDATA25 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B2_6.GTPE2_CHANNEL_RXDATA17 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B2_8.GTPE2_CHANNEL_RXDATA9 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B2_9.GTPE2_CHANNEL_DRPDO10 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B2_10.GTPE2_CHANNEL_RXDATA1 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B3_2.GTPE2_CHANNEL_RXPHMONITOR3 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B3_3.GTPE2_CHANNEL_RXDATA28 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B3_5.GTPE2_CHANNEL_RXDATA20 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B3_6.GTPE2_CHANNEL_RXOSINTDONE always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B3_7.GTPE2_CHANNEL_RXDATA12 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B3_9.GTPE2_CHANNEL_RXDATA4 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B4_3.GTPE2_CHANNEL_DRPDO2 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B4_4.GTPE2_CHANNEL_RXDATA26 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B4_5.GTPE2_CHANNEL_DRPDO7 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B4_6.GTPE2_CHANNEL_RXDATA18 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B4_7.GTPE2_CHANNEL_DRPDO15 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B4_8.GTPE2_CHANNEL_RXDATA10 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B4_9.GTPE2_CHANNEL_DRPDO9 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B4_10.GTPE2_CHANNEL_RXDATA2 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B5_1.GTPE2_CHANNEL_RXDATAVALID1 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B5_3.GTPE2_CHANNEL_RXDATA31 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B5_5.GTPE2_CHANNEL_RXDATA23 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B5_6.GTPE2_CHANNEL_PCSRSVDOUT14 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B5_7.GTPE2_CHANNEL_RXDATA15 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B5_8.GTPE2_CHANNEL_PCSRSVDOUT11 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B5_9.GTPE2_CHANNEL_RXDATA7 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B5_10.GTPE2_CHANNEL_PCSRSVDOUT0 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B6_2.GTPE2_CHANNEL_RXPHSLIPMONITOR3 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B6_4.GTPE2_CHANNEL_RXDATA24 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B6_6.GTPE2_CHANNEL_RXDATA16 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B6_7.GTPE2_CHANNEL_RXOSINTSTARTED always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B6_8.GTPE2_CHANNEL_RXDATA8 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B6_10.GTPE2_CHANNEL_RXDATA0 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B7_2.GTPE2_CHANNEL_RXPHMONITOR2 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B7_3.GTPE2_CHANNEL_RXDATA29 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B7_4.GTPE2_CHANNEL_PCSRSVDOUT12 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B7_5.GTPE2_CHANNEL_RXDATA21 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B7_6.GTPE2_CHANNEL_PMARSVDOUT1 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B7_7.GTPE2_CHANNEL_RXDATA13 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B7_8.GTPE2_CHANNEL_DRPDO12 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B7_9.GTPE2_CHANNEL_RXDATA5 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B8_0.GTPE2_CHANNEL_RXBYTEISALIGNED always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B8_1.GTPE2_CHANNEL_RXCHANBONDSEQ always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B9_0.GTPE2_CHANNEL_RXPHSLIPMONITOR2 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B9_2.GTPE2_CHANNEL_PCSRSVDOUT13 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B9_3.GTPE2_CHANNEL_DMONITOROUT7 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B9_4.GTPE2_CHANNEL_DMONITOROUT6 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B9_5.GTPE2_CHANNEL_DMONITOROUT5 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B9_6.GTPE2_CHANNEL_DMONITOROUT4 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B9_7.GTPE2_CHANNEL_DMONITOROUT3 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B9_8.GTPE2_CHANNEL_DMONITOROUT2 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B9_9.GTPE2_CHANNEL_DMONITOROUT1 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B9_10.GTPE2_CHANNEL_DMONITOROUT0 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B10_0.GTPE2_CHANNEL_RXPHMONITOR1 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B10_1.GTPE2_CHANNEL_RXSYNCOUT always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B10_3.GTPE2_CHANNEL_DRPDO4 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B10_5.GTPE2_CHANNEL_DMONITOROUT14 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B10_9.GTPE2_CHANNEL_PHYSTATUS always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B11_0.GTPE2_CHANNEL_RXCLKCORCNT0 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B11_10.GTPE2_CHANNEL_RXSTARTOFSEQ1 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B12_0.GTPE2_CHANNEL_RXDLYSRESETDONE always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B12_1.GTPE2_CHANNEL_RXCOMWAKEDET always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B12_2.GTPE2_CHANNEL_RXPMARESETDONE always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B12_3.GTPE2_CHANNEL_DRPDO0 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B12_4.GTPE2_CHANNEL_RXCHARISK3 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B12_5.GTPE2_CHANNEL_DRPDO5 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B12_6.GTPE2_CHANNEL_RXCHARISK2 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B12_7.GTPE2_CHANNEL_DRPDO14 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B12_8.GTPE2_CHANNEL_RXCHARISK1 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B12_9.GTPE2_CHANNEL_DRPDO8 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B12_10.GTPE2_CHANNEL_RXCHARISK0 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B13_0.GTPE2_CHANNEL_RXPHSLIPMONITOR0 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B13_1.GTPE2_CHANNEL_RXDATAVALID0 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B13_2.GTPE2_CHANNEL_PCSRSVDOUT2 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B13_3.GTPE2_CHANNEL_PCSRSVDOUT3 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B13_4.GTPE2_CHANNEL_PCSRSVDOUT4 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B13_5.GTPE2_CHANNEL_PCSRSVDOUT5 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B13_6.GTPE2_CHANNEL_PCSRSVDOUT6 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B13_7.GTPE2_CHANNEL_PCSRSVDOUT7 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B13_8.GTPE2_CHANNEL_PCSRSVDOUT8 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B13_9.GTPE2_CHANNEL_PCSRSVDOUT9 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B13_10.GTPE2_CHANNEL_PCSRSVDOUT10 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B14_0.GTPE2_CHANNEL_RXBYTEREALIGN always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B14_1.GTPE2_CHANNEL_RXHEADERVALID always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B14_2.GTPE2_CHANNEL_TXPMARESETDONE always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B14_3.GTPE2_CHANNEL_DRPDO3 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B14_4.GTPE2_CHANNEL_RXNOTINTABLE3 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B14_5.GTPE2_CHANNEL_DRPRDY always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B14_6.GTPE2_CHANNEL_RXNOTINTABLE2 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B14_7.GTPE2_CHANNEL_TXSYNCOUT always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B14_8.GTPE2_CHANNEL_RXNOTINTABLE1 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B14_9.GTPE2_CHANNEL_RXSYNCDONE always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B14_10.GTPE2_CHANNEL_RXNOTINTABLE0 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B15_0.GTPE2_CHANNEL_RXCLKCORCNT1 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B15_1.GTPE2_CHANNEL_TXOUTCLKFABRIC always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B15_2.GTPE2_CHANNEL_DMONITOROUT12 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B15_3.GTPE2_CHANNEL_RXCHARISCOMMA3 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B15_4.GTPE2_CHANNEL_PCSRSVDOUT15 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B15_5.GTPE2_CHANNEL_RXCHARISCOMMA2 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B15_6.GTPE2_CHANNEL_PMARSVDOUT0 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B15_7.GTPE2_CHANNEL_RXCHARISCOMMA1 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B15_8.GTPE2_CHANNEL_DRPDO13 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B15_9.GTPE2_CHANNEL_RXCHARISCOMMA0 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B16_0.GTPE2_CHANNEL_RXPHMONITOR0 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B16_1.GTPE2_CHANNEL_RXPRBSERR always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B16_3.GTPE2_CHANNEL_RXPHSLIPMONITOR4 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B16_4.GTPE2_CHANNEL_TXRESETDONE always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B16_7.GTPE2_CHANNEL_RXCHBONDO3 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B16_8.GTPE2_CHANNEL_RXCHBONDO2 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B16_9.GTPE2_CHANNEL_RXCHBONDO1 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B16_10.GTPE2_CHANNEL_RXCHBONDO0 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B17_1.GTPE2_CHANNEL_RXPHMONITOR4 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B17_2.GTPE2_CHANNEL_TXBUFSTATUS0 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B17_3.GTPE2_CHANNEL_TXDLYSRESETDONE always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B17_4.GTPE2_CHANNEL_TXOUTCLKPCS always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B17_5.GTPE2_CHANNEL_RXCDRLOCK always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B17_6.GTPE2_CHANNEL_RXHEADER2 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B17_8.GTPE2_CHANNEL_RXSTATUS1 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B17_10.GTPE2_CHANNEL_RXBUFSTATUS2 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B18_0.GTPE2_CHANNEL_EYESCANDATAERROR always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B18_1.GTPE2_CHANNEL_RXRESETDONE always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B18_3.GTPE2_CHANNEL_TXPHALIGNDONE always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B18_4.GTPE2_CHANNEL_RXPHALIGNDONE always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B18_7.GTPE2_CHANNEL_RXCOMSASDET always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B18_8.GTPE2_CHANNEL_RXSTARTOFSEQ0 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B18_9.GTPE2_CHANNEL_RXCHANISALIGNED always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B19_0.GTPE2_CHANNEL_RXPHSLIPMONITOR1 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B19_6.GTPE2_CHANNEL_RXHEADER0 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B19_7.GTPE2_CHANNEL_RXCOMMADET always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B19_8.GTPE2_CHANNEL_RXELECIDLE always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B19_10.GTPE2_CHANNEL_RXBUFSTATUS1 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B20_0.GTPE2_CHANNEL_TXBUFSTATUS1 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B20_1.GTPE2_CHANNEL_RXCOMINITDET always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B20_4.GTPE2_CHANNEL_TXRATEDONE always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B20_9.GTPE2_CHANNEL_RXVALID always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B21_4.GTPE2_CHANNEL_DMONITOROUT11 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B21_5.GTPE2_CHANNEL_DMONITOROUT10 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B21_6.GTPE2_CHANNEL_DMONITOROUT9 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B21_7.GTPE2_CHANNEL_DMONITOROUT8 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B21_8.GTPE2_CHANNEL_RXSTATUS0 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B22_0.GTPE2_CHANNEL_RXOUTCLKFABRIC always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B22_1.GTPE2_CHANNEL_RXOUTCLKPCS always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B22_3.GTPE2_CHANNEL_DRPDO1 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B22_4.GTPE2_CHANNEL_RXDISPERR3 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B22_5.GTPE2_CHANNEL_DRPDO6 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B22_6.GTPE2_CHANNEL_RXDISPERR2 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B22_8.GTPE2_CHANNEL_RXDISPERR1 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B22_9.GTPE2_CHANNEL_TXSYNCDONE always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B22_10.GTPE2_CHANNEL_RXDISPERR0 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B23_1.GTPE2_CHANNEL_TXCOMFINISH always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B23_4.GTPE2_CHANNEL_TXGEARBOXREADY always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B23_5.GTPE2_CHANNEL_RXRATEDONE always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B23_6.GTPE2_CHANNEL_RXHEADER1 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B23_8.GTPE2_CHANNEL_RXSTATUS2 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B23_9.GTPE2_CHANNEL_RXCHANREALIGN always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_LOGIC_OUTS_B23_10.GTPE2_CHANNEL_RXBUFSTATUS0 always diff --git a/artix7/ppips_gtp_channel_2.db b/artix7/ppips_gtp_channel_2.db index 0c384ed..707e6d9 100644 --- a/artix7/ppips_gtp_channel_2.db +++ b/artix7/ppips_gtp_channel_2.db @@ -10,6 +10,10 @@ GTP_CHANNEL_2.GTPE2_CHANNEL_EYESCANTRIGGER.GTPE2_IMUX31_8 always GTP_CHANNEL_2.GTPE2_CHANNEL_GTRESETSEL.GTPE2_CTRL0_10 always GTP_CHANNEL_2.GTPE2_CHANNEL_GTRXRESET.GTPE2_CTRL0_8 always GTP_CHANNEL_2.GTPE2_CHANNEL_GTTXRESET.GTPE2_CTRL0_5 always +GTP_CHANNEL_2.GTPE2_CHANNEL_PLL0CLK.GTPE2_CHANNEL_PLLCLK0 always +GTP_CHANNEL_2.GTPE2_CHANNEL_PLL0REFCLK.GTPE2_CHANNEL_PLLREFCLK0 always +GTP_CHANNEL_2.GTPE2_CHANNEL_PLL1CLK.GTPE2_CHANNEL_PLLCLK1 always +GTP_CHANNEL_2.GTPE2_CHANNEL_PLL1REFCLK.GTPE2_CHANNEL_PLLREFCLK1 always GTP_CHANNEL_2.GTPE2_CHANNEL_RESETOVRD.GTPE2_IMUX41_5 always GTP_CHANNEL_2.GTPE2_CHANNEL_RX8B10BEN.GTPE2_IMUX45_1 always GTP_CHANNEL_2.GTPE2_CHANNEL_RXBUFRESET.GTPE2_CTRL1_6 always @@ -36,6 +40,7 @@ GTP_CHANNEL_2.GTPE2_CHANNEL_RXLPMLFOVRDEN.GTPE2_IMUX3_10 always GTP_CHANNEL_2.GTPE2_CHANNEL_RXLPMOSINTNTRLEN.GTPE2_IMUX7_2 always GTP_CHANNEL_2.GTPE2_CHANNEL_RXLPMRESET.GTPE2_CTRL0_9 always GTP_CHANNEL_2.GTPE2_CHANNEL_RXMCOMMAALIGNEN.GTPE2_IMUX41_1 always +GTP_CHANNEL_2.GTPE2_CHANNEL_RXN.GTPE2_CHANNEL_RXN_PAD always GTP_CHANNEL_2.GTPE2_CHANNEL_RXOOBRESET.GTPE2_CTRL1_10 always GTP_CHANNEL_2.GTPE2_CHANNEL_RXOSCALRESET.GTPE2_IMUX46_2 always GTP_CHANNEL_2.GTPE2_CHANNEL_RXOSHOLD.GTPE2_IMUX29_8 always @@ -47,6 +52,8 @@ GTP_CHANNEL_2.GTPE2_CHANNEL_RXOSINTPD.GTPE2_IMUX3_0 always GTP_CHANNEL_2.GTPE2_CHANNEL_RXOSINTSTROBE.GTPE2_IMUX32_9 always GTP_CHANNEL_2.GTPE2_CHANNEL_RXOSINTTESTOVRDEN.GTPE2_IMUX5_9 always GTP_CHANNEL_2.GTPE2_CHANNEL_RXOSOVRDEN.GTPE2_IMUX13_8 always +GTP_CHANNEL_2.GTPE2_CHANNEL_RXOUTCLK_2.GTPE2_CHANNEL_GTRXOUTCLK_2 always +GTP_CHANNEL_2.GTPE2_CHANNEL_RXP.GTPE2_CHANNEL_RXP_PAD always GTP_CHANNEL_2.GTPE2_CHANNEL_RXPCOMMAALIGNEN.GTPE2_IMUX40_1 always GTP_CHANNEL_2.GTPE2_CHANNEL_RXPCSRESET.GTPE2_IMUX46_1 always GTP_CHANNEL_2.GTPE2_CHANNEL_RXPHALIGN.GTPE2_IMUX14_9 always @@ -81,6 +88,9 @@ GTP_CHANNEL_2.GTPE2_CHANNEL_TXDLYSRESET.GTPE2_IMUX45_3 always GTP_CHANNEL_2.GTPE2_CHANNEL_TXDLYUPDOWN.GTPE2_IMUX43_5 always GTP_CHANNEL_2.GTPE2_CHANNEL_TXELECIDLE.GTPE2_IMUX39_6 always GTP_CHANNEL_2.GTPE2_CHANNEL_TXINHIBIT.GTPE2_IMUX32_2 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TXN_PAD.GTPE2_CHANNEL_TXN always +GTP_CHANNEL_2.GTPE2_CHANNEL_TXOUTCLK_2.GTPE2_CHANNEL_GTTXOUTCLK_2 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TXP_PAD.GTPE2_CHANNEL_TXP always GTP_CHANNEL_2.GTPE2_CHANNEL_TXPCSRESET.GTPE2_IMUX46_0 always GTP_CHANNEL_2.GTPE2_CHANNEL_TXPDELECIDLEMODE.GTPE2_IMUX14_0 always GTP_CHANNEL_2.GTPE2_CHANNEL_TXPHALIGN.GTPE2_IMUX25_2 always @@ -344,3 +354,173 @@ GTP_CHANNEL_2.GTPE2_CHANNEL_TXSEQUENCE6.GTPE2_IMUX8_0 always GTP_CHANNEL_2.GTPE2_CHANNEL_TXSYSCLKSEL0.GTPE2_IMUX28_5 always GTP_CHANNEL_2.GTPE2_CHANNEL_TXSYSCLKSEL1.GTPE2_IMUX28_4 always GTP_CHANNEL_2.GTPE2_CHANNEL_TXUSRCLK2.GTPE2_CLK0_5 always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B0_3.GTPE2_CHANNEL_RXOSINTSTROBEDONE always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B0_4.GTPE2_CHANNEL_RXDATA27 always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B0_5.GTPE2_CHANNEL_PCSRSVDOUT1 always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B0_6.GTPE2_CHANNEL_RXDATA19 always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B0_7.GTPE2_CHANNEL_RXOSINTSTROBESTARTED always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B0_8.GTPE2_CHANNEL_RXDATA11 always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B0_10.GTPE2_CHANNEL_RXDATA3 always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B1_3.GTPE2_CHANNEL_RXDATA30 always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B1_5.GTPE2_CHANNEL_RXDATA22 always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B1_6.GTPE2_CHANNEL_DMONITOROUT13 always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B1_7.GTPE2_CHANNEL_RXDATA14 always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B1_8.GTPE2_CHANNEL_DRPDO11 always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B1_9.GTPE2_CHANNEL_RXDATA6 always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B1_10.GTPE2_CHANNEL_TXPHINITDONE always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B2_4.GTPE2_CHANNEL_RXDATA25 always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B2_6.GTPE2_CHANNEL_RXDATA17 always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B2_8.GTPE2_CHANNEL_RXDATA9 always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B2_9.GTPE2_CHANNEL_DRPDO10 always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B2_10.GTPE2_CHANNEL_RXDATA1 always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B3_2.GTPE2_CHANNEL_RXPHMONITOR3 always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B3_3.GTPE2_CHANNEL_RXDATA28 always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B3_5.GTPE2_CHANNEL_RXDATA20 always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B3_6.GTPE2_CHANNEL_RXOSINTDONE always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B3_7.GTPE2_CHANNEL_RXDATA12 always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B3_9.GTPE2_CHANNEL_RXDATA4 always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B4_3.GTPE2_CHANNEL_DRPDO2 always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B4_4.GTPE2_CHANNEL_RXDATA26 always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B4_5.GTPE2_CHANNEL_DRPDO7 always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B4_6.GTPE2_CHANNEL_RXDATA18 always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B4_7.GTPE2_CHANNEL_DRPDO15 always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B4_8.GTPE2_CHANNEL_RXDATA10 always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B4_9.GTPE2_CHANNEL_DRPDO9 always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B4_10.GTPE2_CHANNEL_RXDATA2 always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B5_1.GTPE2_CHANNEL_RXDATAVALID1 always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B5_3.GTPE2_CHANNEL_RXDATA31 always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B5_5.GTPE2_CHANNEL_RXDATA23 always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B5_6.GTPE2_CHANNEL_PCSRSVDOUT14 always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B5_7.GTPE2_CHANNEL_RXDATA15 always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B5_8.GTPE2_CHANNEL_PCSRSVDOUT11 always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B5_9.GTPE2_CHANNEL_RXDATA7 always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B5_10.GTPE2_CHANNEL_PCSRSVDOUT0 always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B6_2.GTPE2_CHANNEL_RXPHSLIPMONITOR3 always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B6_4.GTPE2_CHANNEL_RXDATA24 always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B6_6.GTPE2_CHANNEL_RXDATA16 always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B6_7.GTPE2_CHANNEL_RXOSINTSTARTED always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B6_8.GTPE2_CHANNEL_RXDATA8 always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B6_10.GTPE2_CHANNEL_RXDATA0 always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B7_2.GTPE2_CHANNEL_RXPHMONITOR2 always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B7_3.GTPE2_CHANNEL_RXDATA29 always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B7_4.GTPE2_CHANNEL_PCSRSVDOUT12 always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B7_5.GTPE2_CHANNEL_RXDATA21 always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B7_6.GTPE2_CHANNEL_PMARSVDOUT1 always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B7_7.GTPE2_CHANNEL_RXDATA13 always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B7_8.GTPE2_CHANNEL_DRPDO12 always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B7_9.GTPE2_CHANNEL_RXDATA5 always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B8_0.GTPE2_CHANNEL_RXBYTEISALIGNED always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B8_1.GTPE2_CHANNEL_RXCHANBONDSEQ always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B9_0.GTPE2_CHANNEL_RXPHSLIPMONITOR2 always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B9_2.GTPE2_CHANNEL_PCSRSVDOUT13 always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B9_3.GTPE2_CHANNEL_DMONITOROUT7 always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B9_4.GTPE2_CHANNEL_DMONITOROUT6 always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B9_5.GTPE2_CHANNEL_DMONITOROUT5 always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B9_6.GTPE2_CHANNEL_DMONITOROUT4 always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B9_7.GTPE2_CHANNEL_DMONITOROUT3 always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B9_8.GTPE2_CHANNEL_DMONITOROUT2 always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B9_9.GTPE2_CHANNEL_DMONITOROUT1 always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B9_10.GTPE2_CHANNEL_DMONITOROUT0 always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B10_0.GTPE2_CHANNEL_RXPHMONITOR1 always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B10_1.GTPE2_CHANNEL_RXSYNCOUT always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B10_3.GTPE2_CHANNEL_DRPDO4 always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B10_5.GTPE2_CHANNEL_DMONITOROUT14 always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B10_9.GTPE2_CHANNEL_PHYSTATUS always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B11_0.GTPE2_CHANNEL_RXCLKCORCNT0 always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B11_10.GTPE2_CHANNEL_RXSTARTOFSEQ1 always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B12_0.GTPE2_CHANNEL_RXDLYSRESETDONE always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B12_1.GTPE2_CHANNEL_RXCOMWAKEDET always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B12_2.GTPE2_CHANNEL_RXPMARESETDONE always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B12_3.GTPE2_CHANNEL_DRPDO0 always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B12_4.GTPE2_CHANNEL_RXCHARISK3 always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B12_5.GTPE2_CHANNEL_DRPDO5 always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B12_6.GTPE2_CHANNEL_RXCHARISK2 always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B12_7.GTPE2_CHANNEL_DRPDO14 always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B12_8.GTPE2_CHANNEL_RXCHARISK1 always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B12_9.GTPE2_CHANNEL_DRPDO8 always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B12_10.GTPE2_CHANNEL_RXCHARISK0 always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B13_0.GTPE2_CHANNEL_RXPHSLIPMONITOR0 always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B13_1.GTPE2_CHANNEL_RXDATAVALID0 always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B13_2.GTPE2_CHANNEL_PCSRSVDOUT2 always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B13_3.GTPE2_CHANNEL_PCSRSVDOUT3 always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B13_4.GTPE2_CHANNEL_PCSRSVDOUT4 always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B13_5.GTPE2_CHANNEL_PCSRSVDOUT5 always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B13_6.GTPE2_CHANNEL_PCSRSVDOUT6 always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B13_7.GTPE2_CHANNEL_PCSRSVDOUT7 always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B13_8.GTPE2_CHANNEL_PCSRSVDOUT8 always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B13_9.GTPE2_CHANNEL_PCSRSVDOUT9 always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B13_10.GTPE2_CHANNEL_PCSRSVDOUT10 always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B14_0.GTPE2_CHANNEL_RXBYTEREALIGN always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B14_1.GTPE2_CHANNEL_RXHEADERVALID always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B14_2.GTPE2_CHANNEL_TXPMARESETDONE always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B14_3.GTPE2_CHANNEL_DRPDO3 always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B14_4.GTPE2_CHANNEL_RXNOTINTABLE3 always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B14_5.GTPE2_CHANNEL_DRPRDY always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B14_6.GTPE2_CHANNEL_RXNOTINTABLE2 always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B14_7.GTPE2_CHANNEL_TXSYNCOUT always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B14_8.GTPE2_CHANNEL_RXNOTINTABLE1 always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B14_9.GTPE2_CHANNEL_RXSYNCDONE always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B14_10.GTPE2_CHANNEL_RXNOTINTABLE0 always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B15_0.GTPE2_CHANNEL_RXCLKCORCNT1 always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B15_1.GTPE2_CHANNEL_TXOUTCLKFABRIC always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B15_2.GTPE2_CHANNEL_DMONITOROUT12 always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B15_3.GTPE2_CHANNEL_RXCHARISCOMMA3 always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B15_4.GTPE2_CHANNEL_PCSRSVDOUT15 always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B15_5.GTPE2_CHANNEL_RXCHARISCOMMA2 always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B15_6.GTPE2_CHANNEL_PMARSVDOUT0 always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B15_7.GTPE2_CHANNEL_RXCHARISCOMMA1 always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B15_8.GTPE2_CHANNEL_DRPDO13 always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B15_9.GTPE2_CHANNEL_RXCHARISCOMMA0 always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B16_0.GTPE2_CHANNEL_RXPHMONITOR0 always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B16_1.GTPE2_CHANNEL_RXPRBSERR always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B16_3.GTPE2_CHANNEL_RXPHSLIPMONITOR4 always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B16_4.GTPE2_CHANNEL_TXRESETDONE always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B16_7.GTPE2_CHANNEL_RXCHBONDO3 always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B16_8.GTPE2_CHANNEL_RXCHBONDO2 always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B16_9.GTPE2_CHANNEL_RXCHBONDO1 always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B16_10.GTPE2_CHANNEL_RXCHBONDO0 always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B17_1.GTPE2_CHANNEL_RXPHMONITOR4 always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B17_2.GTPE2_CHANNEL_TXBUFSTATUS0 always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B17_3.GTPE2_CHANNEL_TXDLYSRESETDONE always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B17_4.GTPE2_CHANNEL_TXOUTCLKPCS always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B17_5.GTPE2_CHANNEL_RXCDRLOCK always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B17_6.GTPE2_CHANNEL_RXHEADER2 always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B17_8.GTPE2_CHANNEL_RXSTATUS1 always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B17_10.GTPE2_CHANNEL_RXBUFSTATUS2 always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B18_0.GTPE2_CHANNEL_EYESCANDATAERROR always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B18_1.GTPE2_CHANNEL_RXRESETDONE always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B18_3.GTPE2_CHANNEL_TXPHALIGNDONE always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B18_4.GTPE2_CHANNEL_RXPHALIGNDONE always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B18_7.GTPE2_CHANNEL_RXCOMSASDET always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B18_8.GTPE2_CHANNEL_RXSTARTOFSEQ0 always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B18_9.GTPE2_CHANNEL_RXCHANISALIGNED always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B19_0.GTPE2_CHANNEL_RXPHSLIPMONITOR1 always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B19_6.GTPE2_CHANNEL_RXHEADER0 always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B19_7.GTPE2_CHANNEL_RXCOMMADET always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B19_8.GTPE2_CHANNEL_RXELECIDLE always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B19_10.GTPE2_CHANNEL_RXBUFSTATUS1 always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B20_0.GTPE2_CHANNEL_TXBUFSTATUS1 always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B20_1.GTPE2_CHANNEL_RXCOMINITDET always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B20_4.GTPE2_CHANNEL_TXRATEDONE always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B20_9.GTPE2_CHANNEL_RXVALID always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B21_4.GTPE2_CHANNEL_DMONITOROUT11 always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B21_5.GTPE2_CHANNEL_DMONITOROUT10 always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B21_6.GTPE2_CHANNEL_DMONITOROUT9 always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B21_7.GTPE2_CHANNEL_DMONITOROUT8 always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B21_8.GTPE2_CHANNEL_RXSTATUS0 always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B22_0.GTPE2_CHANNEL_RXOUTCLKFABRIC always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B22_1.GTPE2_CHANNEL_RXOUTCLKPCS always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B22_3.GTPE2_CHANNEL_DRPDO1 always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B22_4.GTPE2_CHANNEL_RXDISPERR3 always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B22_5.GTPE2_CHANNEL_DRPDO6 always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B22_6.GTPE2_CHANNEL_RXDISPERR2 always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B22_8.GTPE2_CHANNEL_RXDISPERR1 always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B22_9.GTPE2_CHANNEL_TXSYNCDONE always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B22_10.GTPE2_CHANNEL_RXDISPERR0 always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B23_1.GTPE2_CHANNEL_TXCOMFINISH always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B23_4.GTPE2_CHANNEL_TXGEARBOXREADY always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B23_5.GTPE2_CHANNEL_RXRATEDONE always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B23_6.GTPE2_CHANNEL_RXHEADER1 always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B23_8.GTPE2_CHANNEL_RXSTATUS2 always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B23_9.GTPE2_CHANNEL_RXCHANREALIGN always +GTP_CHANNEL_2.GTPE2_LOGIC_OUTS_B23_10.GTPE2_CHANNEL_RXBUFSTATUS0 always diff --git a/artix7/ppips_gtp_channel_2_mid_left.db b/artix7/ppips_gtp_channel_2_mid_left.db index 1403e8c..3e3f1ed 100644 --- a/artix7/ppips_gtp_channel_2_mid_left.db +++ b/artix7/ppips_gtp_channel_2_mid_left.db @@ -10,6 +10,10 @@ GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_EYESCANTRIGGER.GTPE2_IMUX31_8 always GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_GTRESETSEL.GTPE2_CTRL0_10 always GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_GTRXRESET.GTPE2_CTRL0_8 always GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_GTTXRESET.GTPE2_CTRL0_5 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_PLL0CLK.GTPE2_CHANNEL_PLLCLK0 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_PLL0REFCLK.GTPE2_CHANNEL_PLLREFCLK0 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_PLL1CLK.GTPE2_CHANNEL_PLLCLK1 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_PLL1REFCLK.GTPE2_CHANNEL_PLLREFCLK1 always GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RESETOVRD.GTPE2_IMUX41_5 always GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RX8B10BEN.GTPE2_IMUX45_1 always GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXBUFRESET.GTPE2_CTRL1_6 always @@ -36,6 +40,7 @@ GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXLPMLFOVRDEN.GTPE2_IMUX3_10 always GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXLPMOSINTNTRLEN.GTPE2_IMUX7_2 always GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXLPMRESET.GTPE2_CTRL0_9 always GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXMCOMMAALIGNEN.GTPE2_IMUX41_1 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXN.GTPE2_CHANNEL_RXN_PAD always GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXOOBRESET.GTPE2_CTRL1_10 always GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXOSCALRESET.GTPE2_IMUX46_2 always GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXOSHOLD.GTPE2_IMUX29_8 always @@ -47,6 +52,8 @@ GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXOSINTPD.GTPE2_IMUX3_0 always GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXOSINTSTROBE.GTPE2_IMUX32_9 always GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXOSINTTESTOVRDEN.GTPE2_IMUX5_9 always GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXOSOVRDEN.GTPE2_IMUX13_8 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXOUTCLK_2.GTPE2_CHANNEL_GTRXOUTCLK_2 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXP.GTPE2_CHANNEL_RXP_PAD always GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXPCOMMAALIGNEN.GTPE2_IMUX40_1 always GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXPCSRESET.GTPE2_IMUX46_1 always GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXPHALIGN.GTPE2_IMUX14_9 always @@ -81,6 +88,9 @@ GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXDLYSRESET.GTPE2_IMUX45_3 always GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXDLYUPDOWN.GTPE2_IMUX43_5 always GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXELECIDLE.GTPE2_IMUX39_6 always GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXINHIBIT.GTPE2_IMUX32_2 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXN_PAD.GTPE2_CHANNEL_TXN always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXOUTCLK_2.GTPE2_CHANNEL_GTTXOUTCLK_2 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXP_PAD.GTPE2_CHANNEL_TXP always GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXPCSRESET.GTPE2_IMUX46_0 always GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXPDELECIDLEMODE.GTPE2_IMUX14_0 always GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXPHALIGN.GTPE2_IMUX25_2 always @@ -344,3 +354,173 @@ GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXSEQUENCE6.GTPE2_IMUX8_0 always GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXSYSCLKSEL0.GTPE2_IMUX28_5 always GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXSYSCLKSEL1.GTPE2_IMUX28_4 always GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXUSRCLK2.GTPE2_CLK0_5 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B0_3.GTPE2_CHANNEL_RXOSINTSTROBEDONE always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B0_4.GTPE2_CHANNEL_RXDATA27 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B0_5.GTPE2_CHANNEL_PCSRSVDOUT1 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B0_6.GTPE2_CHANNEL_RXDATA19 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B0_7.GTPE2_CHANNEL_RXOSINTSTROBESTARTED always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B0_8.GTPE2_CHANNEL_RXDATA11 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B0_10.GTPE2_CHANNEL_RXDATA3 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B1_3.GTPE2_CHANNEL_RXDATA30 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B1_5.GTPE2_CHANNEL_RXDATA22 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B1_6.GTPE2_CHANNEL_DMONITOROUT13 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B1_7.GTPE2_CHANNEL_RXDATA14 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B1_8.GTPE2_CHANNEL_DRPDO11 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B1_9.GTPE2_CHANNEL_RXDATA6 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B1_10.GTPE2_CHANNEL_TXPHINITDONE always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B2_4.GTPE2_CHANNEL_RXDATA25 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B2_6.GTPE2_CHANNEL_RXDATA17 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B2_8.GTPE2_CHANNEL_RXDATA9 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B2_9.GTPE2_CHANNEL_DRPDO10 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B2_10.GTPE2_CHANNEL_RXDATA1 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B3_2.GTPE2_CHANNEL_RXPHMONITOR3 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B3_3.GTPE2_CHANNEL_RXDATA28 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B3_5.GTPE2_CHANNEL_RXDATA20 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B3_6.GTPE2_CHANNEL_RXOSINTDONE always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B3_7.GTPE2_CHANNEL_RXDATA12 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B3_9.GTPE2_CHANNEL_RXDATA4 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B4_3.GTPE2_CHANNEL_DRPDO2 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B4_4.GTPE2_CHANNEL_RXDATA26 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B4_5.GTPE2_CHANNEL_DRPDO7 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B4_6.GTPE2_CHANNEL_RXDATA18 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B4_7.GTPE2_CHANNEL_DRPDO15 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B4_8.GTPE2_CHANNEL_RXDATA10 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B4_9.GTPE2_CHANNEL_DRPDO9 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B4_10.GTPE2_CHANNEL_RXDATA2 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B5_1.GTPE2_CHANNEL_RXDATAVALID1 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B5_3.GTPE2_CHANNEL_RXDATA31 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B5_5.GTPE2_CHANNEL_RXDATA23 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B5_6.GTPE2_CHANNEL_PCSRSVDOUT14 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B5_7.GTPE2_CHANNEL_RXDATA15 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B5_8.GTPE2_CHANNEL_PCSRSVDOUT11 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B5_9.GTPE2_CHANNEL_RXDATA7 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B5_10.GTPE2_CHANNEL_PCSRSVDOUT0 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B6_2.GTPE2_CHANNEL_RXPHSLIPMONITOR3 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B6_4.GTPE2_CHANNEL_RXDATA24 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B6_6.GTPE2_CHANNEL_RXDATA16 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B6_7.GTPE2_CHANNEL_RXOSINTSTARTED always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B6_8.GTPE2_CHANNEL_RXDATA8 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B6_10.GTPE2_CHANNEL_RXDATA0 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B7_2.GTPE2_CHANNEL_RXPHMONITOR2 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B7_3.GTPE2_CHANNEL_RXDATA29 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B7_4.GTPE2_CHANNEL_PCSRSVDOUT12 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B7_5.GTPE2_CHANNEL_RXDATA21 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B7_6.GTPE2_CHANNEL_PMARSVDOUT1 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B7_7.GTPE2_CHANNEL_RXDATA13 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B7_8.GTPE2_CHANNEL_DRPDO12 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B7_9.GTPE2_CHANNEL_RXDATA5 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B8_0.GTPE2_CHANNEL_RXBYTEISALIGNED always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B8_1.GTPE2_CHANNEL_RXCHANBONDSEQ always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B9_0.GTPE2_CHANNEL_RXPHSLIPMONITOR2 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B9_2.GTPE2_CHANNEL_PCSRSVDOUT13 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B9_3.GTPE2_CHANNEL_DMONITOROUT7 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B9_4.GTPE2_CHANNEL_DMONITOROUT6 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B9_5.GTPE2_CHANNEL_DMONITOROUT5 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B9_6.GTPE2_CHANNEL_DMONITOROUT4 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B9_7.GTPE2_CHANNEL_DMONITOROUT3 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B9_8.GTPE2_CHANNEL_DMONITOROUT2 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B9_9.GTPE2_CHANNEL_DMONITOROUT1 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B9_10.GTPE2_CHANNEL_DMONITOROUT0 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B10_0.GTPE2_CHANNEL_RXPHMONITOR1 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B10_1.GTPE2_CHANNEL_RXSYNCOUT always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B10_3.GTPE2_CHANNEL_DRPDO4 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B10_5.GTPE2_CHANNEL_DMONITOROUT14 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B10_9.GTPE2_CHANNEL_PHYSTATUS always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B11_0.GTPE2_CHANNEL_RXCLKCORCNT0 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B11_10.GTPE2_CHANNEL_RXSTARTOFSEQ1 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B12_0.GTPE2_CHANNEL_RXDLYSRESETDONE always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B12_1.GTPE2_CHANNEL_RXCOMWAKEDET always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B12_2.GTPE2_CHANNEL_RXPMARESETDONE always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B12_3.GTPE2_CHANNEL_DRPDO0 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B12_4.GTPE2_CHANNEL_RXCHARISK3 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B12_5.GTPE2_CHANNEL_DRPDO5 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B12_6.GTPE2_CHANNEL_RXCHARISK2 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B12_7.GTPE2_CHANNEL_DRPDO14 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B12_8.GTPE2_CHANNEL_RXCHARISK1 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B12_9.GTPE2_CHANNEL_DRPDO8 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B12_10.GTPE2_CHANNEL_RXCHARISK0 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B13_0.GTPE2_CHANNEL_RXPHSLIPMONITOR0 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B13_1.GTPE2_CHANNEL_RXDATAVALID0 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B13_2.GTPE2_CHANNEL_PCSRSVDOUT2 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B13_3.GTPE2_CHANNEL_PCSRSVDOUT3 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B13_4.GTPE2_CHANNEL_PCSRSVDOUT4 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B13_5.GTPE2_CHANNEL_PCSRSVDOUT5 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B13_6.GTPE2_CHANNEL_PCSRSVDOUT6 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B13_7.GTPE2_CHANNEL_PCSRSVDOUT7 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B13_8.GTPE2_CHANNEL_PCSRSVDOUT8 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B13_9.GTPE2_CHANNEL_PCSRSVDOUT9 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B13_10.GTPE2_CHANNEL_PCSRSVDOUT10 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B14_0.GTPE2_CHANNEL_RXBYTEREALIGN always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B14_1.GTPE2_CHANNEL_RXHEADERVALID always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B14_2.GTPE2_CHANNEL_TXPMARESETDONE always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B14_3.GTPE2_CHANNEL_DRPDO3 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B14_4.GTPE2_CHANNEL_RXNOTINTABLE3 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B14_5.GTPE2_CHANNEL_DRPRDY always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B14_6.GTPE2_CHANNEL_RXNOTINTABLE2 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B14_7.GTPE2_CHANNEL_TXSYNCOUT always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B14_8.GTPE2_CHANNEL_RXNOTINTABLE1 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B14_9.GTPE2_CHANNEL_RXSYNCDONE always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B14_10.GTPE2_CHANNEL_RXNOTINTABLE0 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B15_0.GTPE2_CHANNEL_RXCLKCORCNT1 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B15_1.GTPE2_CHANNEL_TXOUTCLKFABRIC always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B15_2.GTPE2_CHANNEL_DMONITOROUT12 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B15_3.GTPE2_CHANNEL_RXCHARISCOMMA3 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B15_4.GTPE2_CHANNEL_PCSRSVDOUT15 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B15_5.GTPE2_CHANNEL_RXCHARISCOMMA2 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B15_6.GTPE2_CHANNEL_PMARSVDOUT0 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B15_7.GTPE2_CHANNEL_RXCHARISCOMMA1 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B15_8.GTPE2_CHANNEL_DRPDO13 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B15_9.GTPE2_CHANNEL_RXCHARISCOMMA0 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B16_0.GTPE2_CHANNEL_RXPHMONITOR0 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B16_1.GTPE2_CHANNEL_RXPRBSERR always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B16_3.GTPE2_CHANNEL_RXPHSLIPMONITOR4 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B16_4.GTPE2_CHANNEL_TXRESETDONE always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B16_7.GTPE2_CHANNEL_RXCHBONDO3 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B16_8.GTPE2_CHANNEL_RXCHBONDO2 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B16_9.GTPE2_CHANNEL_RXCHBONDO1 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B16_10.GTPE2_CHANNEL_RXCHBONDO0 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B17_1.GTPE2_CHANNEL_RXPHMONITOR4 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B17_2.GTPE2_CHANNEL_TXBUFSTATUS0 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B17_3.GTPE2_CHANNEL_TXDLYSRESETDONE always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B17_4.GTPE2_CHANNEL_TXOUTCLKPCS always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B17_5.GTPE2_CHANNEL_RXCDRLOCK always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B17_6.GTPE2_CHANNEL_RXHEADER2 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B17_8.GTPE2_CHANNEL_RXSTATUS1 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B17_10.GTPE2_CHANNEL_RXBUFSTATUS2 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B18_0.GTPE2_CHANNEL_EYESCANDATAERROR always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B18_1.GTPE2_CHANNEL_RXRESETDONE always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B18_3.GTPE2_CHANNEL_TXPHALIGNDONE always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B18_4.GTPE2_CHANNEL_RXPHALIGNDONE always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B18_7.GTPE2_CHANNEL_RXCOMSASDET always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B18_8.GTPE2_CHANNEL_RXSTARTOFSEQ0 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B18_9.GTPE2_CHANNEL_RXCHANISALIGNED always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B19_0.GTPE2_CHANNEL_RXPHSLIPMONITOR1 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B19_6.GTPE2_CHANNEL_RXHEADER0 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B19_7.GTPE2_CHANNEL_RXCOMMADET always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B19_8.GTPE2_CHANNEL_RXELECIDLE always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B19_10.GTPE2_CHANNEL_RXBUFSTATUS1 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B20_0.GTPE2_CHANNEL_TXBUFSTATUS1 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B20_1.GTPE2_CHANNEL_RXCOMINITDET always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B20_4.GTPE2_CHANNEL_TXRATEDONE always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B20_9.GTPE2_CHANNEL_RXVALID always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B21_4.GTPE2_CHANNEL_DMONITOROUT11 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B21_5.GTPE2_CHANNEL_DMONITOROUT10 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B21_6.GTPE2_CHANNEL_DMONITOROUT9 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B21_7.GTPE2_CHANNEL_DMONITOROUT8 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B21_8.GTPE2_CHANNEL_RXSTATUS0 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B22_0.GTPE2_CHANNEL_RXOUTCLKFABRIC always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B22_1.GTPE2_CHANNEL_RXOUTCLKPCS always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B22_3.GTPE2_CHANNEL_DRPDO1 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B22_4.GTPE2_CHANNEL_RXDISPERR3 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B22_5.GTPE2_CHANNEL_DRPDO6 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B22_6.GTPE2_CHANNEL_RXDISPERR2 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B22_8.GTPE2_CHANNEL_RXDISPERR1 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B22_9.GTPE2_CHANNEL_TXSYNCDONE always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B22_10.GTPE2_CHANNEL_RXDISPERR0 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B23_1.GTPE2_CHANNEL_TXCOMFINISH always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B23_4.GTPE2_CHANNEL_TXGEARBOXREADY always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B23_5.GTPE2_CHANNEL_RXRATEDONE always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B23_6.GTPE2_CHANNEL_RXHEADER1 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B23_8.GTPE2_CHANNEL_RXSTATUS2 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B23_9.GTPE2_CHANNEL_RXCHANREALIGN always +GTP_CHANNEL_2_MID_LEFT.GTPE2_LOGIC_OUTS_B23_10.GTPE2_CHANNEL_RXBUFSTATUS0 always diff --git a/artix7/ppips_gtp_channel_2_mid_right.db b/artix7/ppips_gtp_channel_2_mid_right.db index abdc6e7..bae7cc3 100644 --- a/artix7/ppips_gtp_channel_2_mid_right.db +++ b/artix7/ppips_gtp_channel_2_mid_right.db @@ -10,6 +10,10 @@ GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_EYESCANTRIGGER.GTPE2_IMUX31_8 always GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_GTRESETSEL.GTPE2_CTRL0_10 always GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_GTRXRESET.GTPE2_CTRL0_8 always GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_GTTXRESET.GTPE2_CTRL0_5 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_PLL0CLK.GTPE2_CHANNEL_PLLCLK0 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_PLL0REFCLK.GTPE2_CHANNEL_PLLREFCLK0 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_PLL1CLK.GTPE2_CHANNEL_PLLCLK1 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_PLL1REFCLK.GTPE2_CHANNEL_PLLREFCLK1 always GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RESETOVRD.GTPE2_IMUX41_5 always GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RX8B10BEN.GTPE2_IMUX45_1 always GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXBUFRESET.GTPE2_CTRL1_6 always @@ -36,6 +40,7 @@ GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXLPMLFOVRDEN.GTPE2_IMUX3_10 always GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXLPMOSINTNTRLEN.GTPE2_IMUX7_2 always GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXLPMRESET.GTPE2_CTRL0_9 always GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXMCOMMAALIGNEN.GTPE2_IMUX41_1 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXN.GTPE2_CHANNEL_RXN_PAD always GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXOOBRESET.GTPE2_CTRL1_10 always GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXOSCALRESET.GTPE2_IMUX46_2 always GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXOSHOLD.GTPE2_IMUX29_8 always @@ -47,6 +52,8 @@ GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXOSINTPD.GTPE2_IMUX3_0 always GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXOSINTSTROBE.GTPE2_IMUX32_9 always GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXOSINTTESTOVRDEN.GTPE2_IMUX5_9 always GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXOSOVRDEN.GTPE2_IMUX13_8 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXOUTCLK_2.GTPE2_CHANNEL_GTRXOUTCLK_2 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXP.GTPE2_CHANNEL_RXP_PAD always GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXPCOMMAALIGNEN.GTPE2_IMUX40_1 always GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXPCSRESET.GTPE2_IMUX46_1 always GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXPHALIGN.GTPE2_IMUX14_9 always @@ -81,6 +88,9 @@ GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXDLYSRESET.GTPE2_IMUX45_3 always GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXDLYUPDOWN.GTPE2_IMUX43_5 always GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXELECIDLE.GTPE2_IMUX39_6 always GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXINHIBIT.GTPE2_IMUX32_2 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXN_PAD.GTPE2_CHANNEL_TXN always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXOUTCLK_2.GTPE2_CHANNEL_GTTXOUTCLK_2 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXP_PAD.GTPE2_CHANNEL_TXP always GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXPCSRESET.GTPE2_IMUX46_0 always GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXPDELECIDLEMODE.GTPE2_IMUX14_0 always GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXPHALIGN.GTPE2_IMUX25_2 always @@ -344,3 +354,173 @@ GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXSEQUENCE6.GTPE2_IMUX8_0 always GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXSYSCLKSEL0.GTPE2_IMUX28_5 always GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXSYSCLKSEL1.GTPE2_IMUX28_4 always GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXUSRCLK2.GTPE2_CLK0_5 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B0_3.GTPE2_CHANNEL_RXOSINTSTROBEDONE always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B0_4.GTPE2_CHANNEL_RXDATA27 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B0_5.GTPE2_CHANNEL_PCSRSVDOUT1 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B0_6.GTPE2_CHANNEL_RXDATA19 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B0_7.GTPE2_CHANNEL_RXOSINTSTROBESTARTED always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B0_8.GTPE2_CHANNEL_RXDATA11 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B0_10.GTPE2_CHANNEL_RXDATA3 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B1_3.GTPE2_CHANNEL_RXDATA30 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B1_5.GTPE2_CHANNEL_RXDATA22 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B1_6.GTPE2_CHANNEL_DMONITOROUT13 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B1_7.GTPE2_CHANNEL_RXDATA14 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B1_8.GTPE2_CHANNEL_DRPDO11 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B1_9.GTPE2_CHANNEL_RXDATA6 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B1_10.GTPE2_CHANNEL_TXPHINITDONE always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B2_4.GTPE2_CHANNEL_RXDATA25 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B2_6.GTPE2_CHANNEL_RXDATA17 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B2_8.GTPE2_CHANNEL_RXDATA9 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B2_9.GTPE2_CHANNEL_DRPDO10 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B2_10.GTPE2_CHANNEL_RXDATA1 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B3_2.GTPE2_CHANNEL_RXPHMONITOR3 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B3_3.GTPE2_CHANNEL_RXDATA28 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B3_5.GTPE2_CHANNEL_RXDATA20 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B3_6.GTPE2_CHANNEL_RXOSINTDONE always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B3_7.GTPE2_CHANNEL_RXDATA12 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B3_9.GTPE2_CHANNEL_RXDATA4 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B4_3.GTPE2_CHANNEL_DRPDO2 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B4_4.GTPE2_CHANNEL_RXDATA26 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B4_5.GTPE2_CHANNEL_DRPDO7 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B4_6.GTPE2_CHANNEL_RXDATA18 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B4_7.GTPE2_CHANNEL_DRPDO15 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B4_8.GTPE2_CHANNEL_RXDATA10 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B4_9.GTPE2_CHANNEL_DRPDO9 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B4_10.GTPE2_CHANNEL_RXDATA2 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B5_1.GTPE2_CHANNEL_RXDATAVALID1 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B5_3.GTPE2_CHANNEL_RXDATA31 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B5_5.GTPE2_CHANNEL_RXDATA23 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B5_6.GTPE2_CHANNEL_PCSRSVDOUT14 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B5_7.GTPE2_CHANNEL_RXDATA15 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B5_8.GTPE2_CHANNEL_PCSRSVDOUT11 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B5_9.GTPE2_CHANNEL_RXDATA7 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B5_10.GTPE2_CHANNEL_PCSRSVDOUT0 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B6_2.GTPE2_CHANNEL_RXPHSLIPMONITOR3 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B6_4.GTPE2_CHANNEL_RXDATA24 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B6_6.GTPE2_CHANNEL_RXDATA16 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B6_7.GTPE2_CHANNEL_RXOSINTSTARTED always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B6_8.GTPE2_CHANNEL_RXDATA8 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B6_10.GTPE2_CHANNEL_RXDATA0 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B7_2.GTPE2_CHANNEL_RXPHMONITOR2 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B7_3.GTPE2_CHANNEL_RXDATA29 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B7_4.GTPE2_CHANNEL_PCSRSVDOUT12 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B7_5.GTPE2_CHANNEL_RXDATA21 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B7_6.GTPE2_CHANNEL_PMARSVDOUT1 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B7_7.GTPE2_CHANNEL_RXDATA13 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B7_8.GTPE2_CHANNEL_DRPDO12 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B7_9.GTPE2_CHANNEL_RXDATA5 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B8_0.GTPE2_CHANNEL_RXBYTEISALIGNED always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B8_1.GTPE2_CHANNEL_RXCHANBONDSEQ always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B9_0.GTPE2_CHANNEL_RXPHSLIPMONITOR2 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B9_2.GTPE2_CHANNEL_PCSRSVDOUT13 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B9_3.GTPE2_CHANNEL_DMONITOROUT7 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B9_4.GTPE2_CHANNEL_DMONITOROUT6 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B9_5.GTPE2_CHANNEL_DMONITOROUT5 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B9_6.GTPE2_CHANNEL_DMONITOROUT4 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B9_7.GTPE2_CHANNEL_DMONITOROUT3 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B9_8.GTPE2_CHANNEL_DMONITOROUT2 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B9_9.GTPE2_CHANNEL_DMONITOROUT1 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B9_10.GTPE2_CHANNEL_DMONITOROUT0 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B10_0.GTPE2_CHANNEL_RXPHMONITOR1 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B10_1.GTPE2_CHANNEL_RXSYNCOUT always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B10_3.GTPE2_CHANNEL_DRPDO4 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B10_5.GTPE2_CHANNEL_DMONITOROUT14 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B10_9.GTPE2_CHANNEL_PHYSTATUS always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B11_0.GTPE2_CHANNEL_RXCLKCORCNT0 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B11_10.GTPE2_CHANNEL_RXSTARTOFSEQ1 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B12_0.GTPE2_CHANNEL_RXDLYSRESETDONE always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B12_1.GTPE2_CHANNEL_RXCOMWAKEDET always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B12_2.GTPE2_CHANNEL_RXPMARESETDONE always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B12_3.GTPE2_CHANNEL_DRPDO0 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B12_4.GTPE2_CHANNEL_RXCHARISK3 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B12_5.GTPE2_CHANNEL_DRPDO5 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B12_6.GTPE2_CHANNEL_RXCHARISK2 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B12_7.GTPE2_CHANNEL_DRPDO14 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B12_8.GTPE2_CHANNEL_RXCHARISK1 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B12_9.GTPE2_CHANNEL_DRPDO8 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B12_10.GTPE2_CHANNEL_RXCHARISK0 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B13_0.GTPE2_CHANNEL_RXPHSLIPMONITOR0 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B13_1.GTPE2_CHANNEL_RXDATAVALID0 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B13_2.GTPE2_CHANNEL_PCSRSVDOUT2 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B13_3.GTPE2_CHANNEL_PCSRSVDOUT3 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B13_4.GTPE2_CHANNEL_PCSRSVDOUT4 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B13_5.GTPE2_CHANNEL_PCSRSVDOUT5 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B13_6.GTPE2_CHANNEL_PCSRSVDOUT6 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B13_7.GTPE2_CHANNEL_PCSRSVDOUT7 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B13_8.GTPE2_CHANNEL_PCSRSVDOUT8 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B13_9.GTPE2_CHANNEL_PCSRSVDOUT9 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B13_10.GTPE2_CHANNEL_PCSRSVDOUT10 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B14_0.GTPE2_CHANNEL_RXBYTEREALIGN always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B14_1.GTPE2_CHANNEL_RXHEADERVALID always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B14_2.GTPE2_CHANNEL_TXPMARESETDONE always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B14_3.GTPE2_CHANNEL_DRPDO3 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B14_4.GTPE2_CHANNEL_RXNOTINTABLE3 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B14_5.GTPE2_CHANNEL_DRPRDY always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B14_6.GTPE2_CHANNEL_RXNOTINTABLE2 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B14_7.GTPE2_CHANNEL_TXSYNCOUT always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B14_8.GTPE2_CHANNEL_RXNOTINTABLE1 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B14_9.GTPE2_CHANNEL_RXSYNCDONE always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B14_10.GTPE2_CHANNEL_RXNOTINTABLE0 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B15_0.GTPE2_CHANNEL_RXCLKCORCNT1 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B15_1.GTPE2_CHANNEL_TXOUTCLKFABRIC always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B15_2.GTPE2_CHANNEL_DMONITOROUT12 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B15_3.GTPE2_CHANNEL_RXCHARISCOMMA3 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B15_4.GTPE2_CHANNEL_PCSRSVDOUT15 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B15_5.GTPE2_CHANNEL_RXCHARISCOMMA2 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B15_6.GTPE2_CHANNEL_PMARSVDOUT0 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B15_7.GTPE2_CHANNEL_RXCHARISCOMMA1 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B15_8.GTPE2_CHANNEL_DRPDO13 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B15_9.GTPE2_CHANNEL_RXCHARISCOMMA0 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B16_0.GTPE2_CHANNEL_RXPHMONITOR0 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B16_1.GTPE2_CHANNEL_RXPRBSERR always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B16_3.GTPE2_CHANNEL_RXPHSLIPMONITOR4 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B16_4.GTPE2_CHANNEL_TXRESETDONE always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B16_7.GTPE2_CHANNEL_RXCHBONDO3 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B16_8.GTPE2_CHANNEL_RXCHBONDO2 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B16_9.GTPE2_CHANNEL_RXCHBONDO1 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B16_10.GTPE2_CHANNEL_RXCHBONDO0 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B17_1.GTPE2_CHANNEL_RXPHMONITOR4 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B17_2.GTPE2_CHANNEL_TXBUFSTATUS0 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B17_3.GTPE2_CHANNEL_TXDLYSRESETDONE always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B17_4.GTPE2_CHANNEL_TXOUTCLKPCS always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B17_5.GTPE2_CHANNEL_RXCDRLOCK always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B17_6.GTPE2_CHANNEL_RXHEADER2 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B17_8.GTPE2_CHANNEL_RXSTATUS1 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B17_10.GTPE2_CHANNEL_RXBUFSTATUS2 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B18_0.GTPE2_CHANNEL_EYESCANDATAERROR always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B18_1.GTPE2_CHANNEL_RXRESETDONE always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B18_3.GTPE2_CHANNEL_TXPHALIGNDONE always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B18_4.GTPE2_CHANNEL_RXPHALIGNDONE always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B18_7.GTPE2_CHANNEL_RXCOMSASDET always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B18_8.GTPE2_CHANNEL_RXSTARTOFSEQ0 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B18_9.GTPE2_CHANNEL_RXCHANISALIGNED always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B19_0.GTPE2_CHANNEL_RXPHSLIPMONITOR1 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B19_6.GTPE2_CHANNEL_RXHEADER0 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B19_7.GTPE2_CHANNEL_RXCOMMADET always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B19_8.GTPE2_CHANNEL_RXELECIDLE always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B19_10.GTPE2_CHANNEL_RXBUFSTATUS1 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B20_0.GTPE2_CHANNEL_TXBUFSTATUS1 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B20_1.GTPE2_CHANNEL_RXCOMINITDET always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B20_4.GTPE2_CHANNEL_TXRATEDONE always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B20_9.GTPE2_CHANNEL_RXVALID always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B21_4.GTPE2_CHANNEL_DMONITOROUT11 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B21_5.GTPE2_CHANNEL_DMONITOROUT10 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B21_6.GTPE2_CHANNEL_DMONITOROUT9 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B21_7.GTPE2_CHANNEL_DMONITOROUT8 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B21_8.GTPE2_CHANNEL_RXSTATUS0 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B22_0.GTPE2_CHANNEL_RXOUTCLKFABRIC always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B22_1.GTPE2_CHANNEL_RXOUTCLKPCS always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B22_3.GTPE2_CHANNEL_DRPDO1 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B22_4.GTPE2_CHANNEL_RXDISPERR3 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B22_5.GTPE2_CHANNEL_DRPDO6 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B22_6.GTPE2_CHANNEL_RXDISPERR2 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B22_8.GTPE2_CHANNEL_RXDISPERR1 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B22_9.GTPE2_CHANNEL_TXSYNCDONE always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B22_10.GTPE2_CHANNEL_RXDISPERR0 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B23_1.GTPE2_CHANNEL_TXCOMFINISH always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B23_4.GTPE2_CHANNEL_TXGEARBOXREADY always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B23_5.GTPE2_CHANNEL_RXRATEDONE always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B23_6.GTPE2_CHANNEL_RXHEADER1 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B23_8.GTPE2_CHANNEL_RXSTATUS2 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B23_9.GTPE2_CHANNEL_RXCHANREALIGN always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_LOGIC_OUTS_B23_10.GTPE2_CHANNEL_RXBUFSTATUS0 always diff --git a/artix7/ppips_gtp_channel_3.db b/artix7/ppips_gtp_channel_3.db index d544403..19d9df5 100644 --- a/artix7/ppips_gtp_channel_3.db +++ b/artix7/ppips_gtp_channel_3.db @@ -10,6 +10,10 @@ GTP_CHANNEL_3.GTPE2_CHANNEL_EYESCANTRIGGER.GTPE2_IMUX31_8 always GTP_CHANNEL_3.GTPE2_CHANNEL_GTRESETSEL.GTPE2_CTRL0_10 always GTP_CHANNEL_3.GTPE2_CHANNEL_GTRXRESET.GTPE2_CTRL0_8 always GTP_CHANNEL_3.GTPE2_CHANNEL_GTTXRESET.GTPE2_CTRL0_5 always +GTP_CHANNEL_3.GTPE2_CHANNEL_PLL0CLK.GTPE2_CHANNEL_PLLCLK0 always +GTP_CHANNEL_3.GTPE2_CHANNEL_PLL0REFCLK.GTPE2_CHANNEL_PLLREFCLK0 always +GTP_CHANNEL_3.GTPE2_CHANNEL_PLL1CLK.GTPE2_CHANNEL_PLLCLK1 always +GTP_CHANNEL_3.GTPE2_CHANNEL_PLL1REFCLK.GTPE2_CHANNEL_PLLREFCLK1 always GTP_CHANNEL_3.GTPE2_CHANNEL_RESETOVRD.GTPE2_IMUX41_5 always GTP_CHANNEL_3.GTPE2_CHANNEL_RX8B10BEN.GTPE2_IMUX45_1 always GTP_CHANNEL_3.GTPE2_CHANNEL_RXBUFRESET.GTPE2_CTRL1_6 always @@ -36,6 +40,7 @@ GTP_CHANNEL_3.GTPE2_CHANNEL_RXLPMLFOVRDEN.GTPE2_IMUX3_10 always GTP_CHANNEL_3.GTPE2_CHANNEL_RXLPMOSINTNTRLEN.GTPE2_IMUX7_2 always GTP_CHANNEL_3.GTPE2_CHANNEL_RXLPMRESET.GTPE2_CTRL0_9 always GTP_CHANNEL_3.GTPE2_CHANNEL_RXMCOMMAALIGNEN.GTPE2_IMUX41_1 always +GTP_CHANNEL_3.GTPE2_CHANNEL_RXN.GTPE2_CHANNEL_RXN_PAD always GTP_CHANNEL_3.GTPE2_CHANNEL_RXOOBRESET.GTPE2_CTRL1_10 always GTP_CHANNEL_3.GTPE2_CHANNEL_RXOSCALRESET.GTPE2_IMUX46_2 always GTP_CHANNEL_3.GTPE2_CHANNEL_RXOSHOLD.GTPE2_IMUX29_8 always @@ -47,6 +52,8 @@ GTP_CHANNEL_3.GTPE2_CHANNEL_RXOSINTPD.GTPE2_IMUX3_0 always GTP_CHANNEL_3.GTPE2_CHANNEL_RXOSINTSTROBE.GTPE2_IMUX32_9 always GTP_CHANNEL_3.GTPE2_CHANNEL_RXOSINTTESTOVRDEN.GTPE2_IMUX5_9 always GTP_CHANNEL_3.GTPE2_CHANNEL_RXOSOVRDEN.GTPE2_IMUX13_8 always +GTP_CHANNEL_3.GTPE2_CHANNEL_RXOUTCLK_3.GTPE2_CHANNEL_GTRXOUTCLK_3 always +GTP_CHANNEL_3.GTPE2_CHANNEL_RXP.GTPE2_CHANNEL_RXP_PAD always GTP_CHANNEL_3.GTPE2_CHANNEL_RXPCOMMAALIGNEN.GTPE2_IMUX40_1 always GTP_CHANNEL_3.GTPE2_CHANNEL_RXPCSRESET.GTPE2_IMUX46_1 always GTP_CHANNEL_3.GTPE2_CHANNEL_RXPHALIGN.GTPE2_IMUX14_9 always @@ -81,6 +88,9 @@ GTP_CHANNEL_3.GTPE2_CHANNEL_TXDLYSRESET.GTPE2_IMUX45_3 always GTP_CHANNEL_3.GTPE2_CHANNEL_TXDLYUPDOWN.GTPE2_IMUX43_5 always GTP_CHANNEL_3.GTPE2_CHANNEL_TXELECIDLE.GTPE2_IMUX39_6 always GTP_CHANNEL_3.GTPE2_CHANNEL_TXINHIBIT.GTPE2_IMUX32_2 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TXN_PAD.GTPE2_CHANNEL_TXN always +GTP_CHANNEL_3.GTPE2_CHANNEL_TXOUTCLK_3.GTPE2_CHANNEL_GTTXOUTCLK_3 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TXP_PAD.GTPE2_CHANNEL_TXP always GTP_CHANNEL_3.GTPE2_CHANNEL_TXPCSRESET.GTPE2_IMUX46_0 always GTP_CHANNEL_3.GTPE2_CHANNEL_TXPDELECIDLEMODE.GTPE2_IMUX14_0 always GTP_CHANNEL_3.GTPE2_CHANNEL_TXPHALIGN.GTPE2_IMUX25_2 always @@ -344,3 +354,173 @@ GTP_CHANNEL_3.GTPE2_CHANNEL_TXSEQUENCE6.GTPE2_IMUX8_0 always GTP_CHANNEL_3.GTPE2_CHANNEL_TXSYSCLKSEL0.GTPE2_IMUX28_5 always GTP_CHANNEL_3.GTPE2_CHANNEL_TXSYSCLKSEL1.GTPE2_IMUX28_4 always GTP_CHANNEL_3.GTPE2_CHANNEL_TXUSRCLK2.GTPE2_CLK0_5 always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B0_3.GTPE2_CHANNEL_RXOSINTSTROBEDONE always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B0_4.GTPE2_CHANNEL_RXDATA27 always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B0_5.GTPE2_CHANNEL_PCSRSVDOUT1 always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B0_6.GTPE2_CHANNEL_RXDATA19 always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B0_7.GTPE2_CHANNEL_RXOSINTSTROBESTARTED always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B0_8.GTPE2_CHANNEL_RXDATA11 always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B0_10.GTPE2_CHANNEL_RXDATA3 always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B1_3.GTPE2_CHANNEL_RXDATA30 always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B1_5.GTPE2_CHANNEL_RXDATA22 always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B1_6.GTPE2_CHANNEL_DMONITOROUT13 always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B1_7.GTPE2_CHANNEL_RXDATA14 always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B1_8.GTPE2_CHANNEL_DRPDO11 always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B1_9.GTPE2_CHANNEL_RXDATA6 always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B1_10.GTPE2_CHANNEL_TXPHINITDONE always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B2_4.GTPE2_CHANNEL_RXDATA25 always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B2_6.GTPE2_CHANNEL_RXDATA17 always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B2_8.GTPE2_CHANNEL_RXDATA9 always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B2_9.GTPE2_CHANNEL_DRPDO10 always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B2_10.GTPE2_CHANNEL_RXDATA1 always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B3_2.GTPE2_CHANNEL_RXPHMONITOR3 always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B3_3.GTPE2_CHANNEL_RXDATA28 always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B3_5.GTPE2_CHANNEL_RXDATA20 always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B3_6.GTPE2_CHANNEL_RXOSINTDONE always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B3_7.GTPE2_CHANNEL_RXDATA12 always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B3_9.GTPE2_CHANNEL_RXDATA4 always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B4_3.GTPE2_CHANNEL_DRPDO2 always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B4_4.GTPE2_CHANNEL_RXDATA26 always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B4_5.GTPE2_CHANNEL_DRPDO7 always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B4_6.GTPE2_CHANNEL_RXDATA18 always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B4_7.GTPE2_CHANNEL_DRPDO15 always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B4_8.GTPE2_CHANNEL_RXDATA10 always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B4_9.GTPE2_CHANNEL_DRPDO9 always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B4_10.GTPE2_CHANNEL_RXDATA2 always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B5_1.GTPE2_CHANNEL_RXDATAVALID1 always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B5_3.GTPE2_CHANNEL_RXDATA31 always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B5_5.GTPE2_CHANNEL_RXDATA23 always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B5_6.GTPE2_CHANNEL_PCSRSVDOUT14 always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B5_7.GTPE2_CHANNEL_RXDATA15 always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B5_8.GTPE2_CHANNEL_PCSRSVDOUT11 always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B5_9.GTPE2_CHANNEL_RXDATA7 always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B5_10.GTPE2_CHANNEL_PCSRSVDOUT0 always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B6_2.GTPE2_CHANNEL_RXPHSLIPMONITOR3 always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B6_4.GTPE2_CHANNEL_RXDATA24 always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B6_6.GTPE2_CHANNEL_RXDATA16 always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B6_7.GTPE2_CHANNEL_RXOSINTSTARTED always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B6_8.GTPE2_CHANNEL_RXDATA8 always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B6_10.GTPE2_CHANNEL_RXDATA0 always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B7_2.GTPE2_CHANNEL_RXPHMONITOR2 always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B7_3.GTPE2_CHANNEL_RXDATA29 always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B7_4.GTPE2_CHANNEL_PCSRSVDOUT12 always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B7_5.GTPE2_CHANNEL_RXDATA21 always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B7_6.GTPE2_CHANNEL_PMARSVDOUT1 always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B7_7.GTPE2_CHANNEL_RXDATA13 always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B7_8.GTPE2_CHANNEL_DRPDO12 always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B7_9.GTPE2_CHANNEL_RXDATA5 always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B8_0.GTPE2_CHANNEL_RXBYTEISALIGNED always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B8_1.GTPE2_CHANNEL_RXCHANBONDSEQ always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B9_0.GTPE2_CHANNEL_RXPHSLIPMONITOR2 always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B9_2.GTPE2_CHANNEL_PCSRSVDOUT13 always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B9_3.GTPE2_CHANNEL_DMONITOROUT7 always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B9_4.GTPE2_CHANNEL_DMONITOROUT6 always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B9_5.GTPE2_CHANNEL_DMONITOROUT5 always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B9_6.GTPE2_CHANNEL_DMONITOROUT4 always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B9_7.GTPE2_CHANNEL_DMONITOROUT3 always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B9_8.GTPE2_CHANNEL_DMONITOROUT2 always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B9_9.GTPE2_CHANNEL_DMONITOROUT1 always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B9_10.GTPE2_CHANNEL_DMONITOROUT0 always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B10_0.GTPE2_CHANNEL_RXPHMONITOR1 always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B10_1.GTPE2_CHANNEL_RXSYNCOUT always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B10_3.GTPE2_CHANNEL_DRPDO4 always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B10_5.GTPE2_CHANNEL_DMONITOROUT14 always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B10_9.GTPE2_CHANNEL_PHYSTATUS always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B11_0.GTPE2_CHANNEL_RXCLKCORCNT0 always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B11_10.GTPE2_CHANNEL_RXSTARTOFSEQ1 always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B12_0.GTPE2_CHANNEL_RXDLYSRESETDONE always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B12_1.GTPE2_CHANNEL_RXCOMWAKEDET always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B12_2.GTPE2_CHANNEL_RXPMARESETDONE always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B12_3.GTPE2_CHANNEL_DRPDO0 always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B12_4.GTPE2_CHANNEL_RXCHARISK3 always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B12_5.GTPE2_CHANNEL_DRPDO5 always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B12_6.GTPE2_CHANNEL_RXCHARISK2 always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B12_7.GTPE2_CHANNEL_DRPDO14 always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B12_8.GTPE2_CHANNEL_RXCHARISK1 always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B12_9.GTPE2_CHANNEL_DRPDO8 always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B12_10.GTPE2_CHANNEL_RXCHARISK0 always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B13_0.GTPE2_CHANNEL_RXPHSLIPMONITOR0 always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B13_1.GTPE2_CHANNEL_RXDATAVALID0 always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B13_2.GTPE2_CHANNEL_PCSRSVDOUT2 always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B13_3.GTPE2_CHANNEL_PCSRSVDOUT3 always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B13_4.GTPE2_CHANNEL_PCSRSVDOUT4 always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B13_5.GTPE2_CHANNEL_PCSRSVDOUT5 always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B13_6.GTPE2_CHANNEL_PCSRSVDOUT6 always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B13_7.GTPE2_CHANNEL_PCSRSVDOUT7 always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B13_8.GTPE2_CHANNEL_PCSRSVDOUT8 always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B13_9.GTPE2_CHANNEL_PCSRSVDOUT9 always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B13_10.GTPE2_CHANNEL_PCSRSVDOUT10 always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B14_0.GTPE2_CHANNEL_RXBYTEREALIGN always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B14_1.GTPE2_CHANNEL_RXHEADERVALID always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B14_2.GTPE2_CHANNEL_TXPMARESETDONE always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B14_3.GTPE2_CHANNEL_DRPDO3 always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B14_4.GTPE2_CHANNEL_RXNOTINTABLE3 always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B14_5.GTPE2_CHANNEL_DRPRDY always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B14_6.GTPE2_CHANNEL_RXNOTINTABLE2 always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B14_7.GTPE2_CHANNEL_TXSYNCOUT always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B14_8.GTPE2_CHANNEL_RXNOTINTABLE1 always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B14_9.GTPE2_CHANNEL_RXSYNCDONE always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B14_10.GTPE2_CHANNEL_RXNOTINTABLE0 always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B15_0.GTPE2_CHANNEL_RXCLKCORCNT1 always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B15_1.GTPE2_CHANNEL_TXOUTCLKFABRIC always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B15_2.GTPE2_CHANNEL_DMONITOROUT12 always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B15_3.GTPE2_CHANNEL_RXCHARISCOMMA3 always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B15_4.GTPE2_CHANNEL_PCSRSVDOUT15 always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B15_5.GTPE2_CHANNEL_RXCHARISCOMMA2 always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B15_6.GTPE2_CHANNEL_PMARSVDOUT0 always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B15_7.GTPE2_CHANNEL_RXCHARISCOMMA1 always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B15_8.GTPE2_CHANNEL_DRPDO13 always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B15_9.GTPE2_CHANNEL_RXCHARISCOMMA0 always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B16_0.GTPE2_CHANNEL_RXPHMONITOR0 always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B16_1.GTPE2_CHANNEL_RXPRBSERR always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B16_3.GTPE2_CHANNEL_RXPHSLIPMONITOR4 always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B16_4.GTPE2_CHANNEL_TXRESETDONE always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B16_7.GTPE2_CHANNEL_RXCHBONDO3 always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B16_8.GTPE2_CHANNEL_RXCHBONDO2 always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B16_9.GTPE2_CHANNEL_RXCHBONDO1 always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B16_10.GTPE2_CHANNEL_RXCHBONDO0 always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B17_1.GTPE2_CHANNEL_RXPHMONITOR4 always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B17_2.GTPE2_CHANNEL_TXBUFSTATUS0 always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B17_3.GTPE2_CHANNEL_TXDLYSRESETDONE always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B17_4.GTPE2_CHANNEL_TXOUTCLKPCS always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B17_5.GTPE2_CHANNEL_RXCDRLOCK always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B17_6.GTPE2_CHANNEL_RXHEADER2 always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B17_8.GTPE2_CHANNEL_RXSTATUS1 always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B17_10.GTPE2_CHANNEL_RXBUFSTATUS2 always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B18_0.GTPE2_CHANNEL_EYESCANDATAERROR always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B18_1.GTPE2_CHANNEL_RXRESETDONE always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B18_3.GTPE2_CHANNEL_TXPHALIGNDONE always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B18_4.GTPE2_CHANNEL_RXPHALIGNDONE always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B18_7.GTPE2_CHANNEL_RXCOMSASDET always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B18_8.GTPE2_CHANNEL_RXSTARTOFSEQ0 always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B18_9.GTPE2_CHANNEL_RXCHANISALIGNED always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B19_0.GTPE2_CHANNEL_RXPHSLIPMONITOR1 always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B19_6.GTPE2_CHANNEL_RXHEADER0 always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B19_7.GTPE2_CHANNEL_RXCOMMADET always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B19_8.GTPE2_CHANNEL_RXELECIDLE always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B19_10.GTPE2_CHANNEL_RXBUFSTATUS1 always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B20_0.GTPE2_CHANNEL_TXBUFSTATUS1 always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B20_1.GTPE2_CHANNEL_RXCOMINITDET always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B20_4.GTPE2_CHANNEL_TXRATEDONE always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B20_9.GTPE2_CHANNEL_RXVALID always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B21_4.GTPE2_CHANNEL_DMONITOROUT11 always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B21_5.GTPE2_CHANNEL_DMONITOROUT10 always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B21_6.GTPE2_CHANNEL_DMONITOROUT9 always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B21_7.GTPE2_CHANNEL_DMONITOROUT8 always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B21_8.GTPE2_CHANNEL_RXSTATUS0 always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B22_0.GTPE2_CHANNEL_RXOUTCLKFABRIC always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B22_1.GTPE2_CHANNEL_RXOUTCLKPCS always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B22_3.GTPE2_CHANNEL_DRPDO1 always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B22_4.GTPE2_CHANNEL_RXDISPERR3 always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B22_5.GTPE2_CHANNEL_DRPDO6 always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B22_6.GTPE2_CHANNEL_RXDISPERR2 always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B22_8.GTPE2_CHANNEL_RXDISPERR1 always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B22_9.GTPE2_CHANNEL_TXSYNCDONE always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B22_10.GTPE2_CHANNEL_RXDISPERR0 always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B23_1.GTPE2_CHANNEL_TXCOMFINISH always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B23_4.GTPE2_CHANNEL_TXGEARBOXREADY always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B23_5.GTPE2_CHANNEL_RXRATEDONE always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B23_6.GTPE2_CHANNEL_RXHEADER1 always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B23_8.GTPE2_CHANNEL_RXSTATUS2 always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B23_9.GTPE2_CHANNEL_RXCHANREALIGN always +GTP_CHANNEL_3.GTPE2_LOGIC_OUTS_B23_10.GTPE2_CHANNEL_RXBUFSTATUS0 always diff --git a/artix7/ppips_gtp_channel_3_mid_left.db b/artix7/ppips_gtp_channel_3_mid_left.db index f1da2cc..c0127f4 100644 --- a/artix7/ppips_gtp_channel_3_mid_left.db +++ b/artix7/ppips_gtp_channel_3_mid_left.db @@ -10,6 +10,10 @@ GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_EYESCANTRIGGER.GTPE2_IMUX31_8 always GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_GTRESETSEL.GTPE2_CTRL0_10 always GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_GTRXRESET.GTPE2_CTRL0_8 always GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_GTTXRESET.GTPE2_CTRL0_5 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_PLL0CLK.GTPE2_CHANNEL_PLLCLK0 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_PLL0REFCLK.GTPE2_CHANNEL_PLLREFCLK0 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_PLL1CLK.GTPE2_CHANNEL_PLLCLK1 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_PLL1REFCLK.GTPE2_CHANNEL_PLLREFCLK1 always GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RESETOVRD.GTPE2_IMUX41_5 always GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RX8B10BEN.GTPE2_IMUX45_1 always GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXBUFRESET.GTPE2_CTRL1_6 always @@ -36,6 +40,7 @@ GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXLPMLFOVRDEN.GTPE2_IMUX3_10 always GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXLPMOSINTNTRLEN.GTPE2_IMUX7_2 always GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXLPMRESET.GTPE2_CTRL0_9 always GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXMCOMMAALIGNEN.GTPE2_IMUX41_1 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXN.GTPE2_CHANNEL_RXN_PAD always GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXOOBRESET.GTPE2_CTRL1_10 always GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXOSCALRESET.GTPE2_IMUX46_2 always GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXOSHOLD.GTPE2_IMUX29_8 always @@ -47,6 +52,8 @@ GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXOSINTPD.GTPE2_IMUX3_0 always GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXOSINTSTROBE.GTPE2_IMUX32_9 always GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXOSINTTESTOVRDEN.GTPE2_IMUX5_9 always GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXOSOVRDEN.GTPE2_IMUX13_8 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXOUTCLK_3.GTPE2_CHANNEL_GTRXOUTCLK_3 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXP.GTPE2_CHANNEL_RXP_PAD always GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXPCOMMAALIGNEN.GTPE2_IMUX40_1 always GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXPCSRESET.GTPE2_IMUX46_1 always GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXPHALIGN.GTPE2_IMUX14_9 always @@ -81,6 +88,9 @@ GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXDLYSRESET.GTPE2_IMUX45_3 always GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXDLYUPDOWN.GTPE2_IMUX43_5 always GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXELECIDLE.GTPE2_IMUX39_6 always GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXINHIBIT.GTPE2_IMUX32_2 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXN_PAD.GTPE2_CHANNEL_TXN always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXOUTCLK_3.GTPE2_CHANNEL_GTTXOUTCLK_3 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXP_PAD.GTPE2_CHANNEL_TXP always GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXPCSRESET.GTPE2_IMUX46_0 always GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXPDELECIDLEMODE.GTPE2_IMUX14_0 always GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXPHALIGN.GTPE2_IMUX25_2 always @@ -344,3 +354,173 @@ GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXSEQUENCE6.GTPE2_IMUX8_0 always GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXSYSCLKSEL0.GTPE2_IMUX28_5 always GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXSYSCLKSEL1.GTPE2_IMUX28_4 always GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXUSRCLK2.GTPE2_CLK0_5 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B0_3.GTPE2_CHANNEL_RXOSINTSTROBEDONE always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B0_4.GTPE2_CHANNEL_RXDATA27 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B0_5.GTPE2_CHANNEL_PCSRSVDOUT1 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B0_6.GTPE2_CHANNEL_RXDATA19 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B0_7.GTPE2_CHANNEL_RXOSINTSTROBESTARTED always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B0_8.GTPE2_CHANNEL_RXDATA11 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B0_10.GTPE2_CHANNEL_RXDATA3 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B1_3.GTPE2_CHANNEL_RXDATA30 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B1_5.GTPE2_CHANNEL_RXDATA22 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B1_6.GTPE2_CHANNEL_DMONITOROUT13 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B1_7.GTPE2_CHANNEL_RXDATA14 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B1_8.GTPE2_CHANNEL_DRPDO11 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B1_9.GTPE2_CHANNEL_RXDATA6 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B1_10.GTPE2_CHANNEL_TXPHINITDONE always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B2_4.GTPE2_CHANNEL_RXDATA25 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B2_6.GTPE2_CHANNEL_RXDATA17 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B2_8.GTPE2_CHANNEL_RXDATA9 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B2_9.GTPE2_CHANNEL_DRPDO10 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B2_10.GTPE2_CHANNEL_RXDATA1 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B3_2.GTPE2_CHANNEL_RXPHMONITOR3 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B3_3.GTPE2_CHANNEL_RXDATA28 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B3_5.GTPE2_CHANNEL_RXDATA20 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B3_6.GTPE2_CHANNEL_RXOSINTDONE always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B3_7.GTPE2_CHANNEL_RXDATA12 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B3_9.GTPE2_CHANNEL_RXDATA4 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B4_3.GTPE2_CHANNEL_DRPDO2 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B4_4.GTPE2_CHANNEL_RXDATA26 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B4_5.GTPE2_CHANNEL_DRPDO7 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B4_6.GTPE2_CHANNEL_RXDATA18 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B4_7.GTPE2_CHANNEL_DRPDO15 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B4_8.GTPE2_CHANNEL_RXDATA10 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B4_9.GTPE2_CHANNEL_DRPDO9 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B4_10.GTPE2_CHANNEL_RXDATA2 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B5_1.GTPE2_CHANNEL_RXDATAVALID1 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B5_3.GTPE2_CHANNEL_RXDATA31 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B5_5.GTPE2_CHANNEL_RXDATA23 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B5_6.GTPE2_CHANNEL_PCSRSVDOUT14 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B5_7.GTPE2_CHANNEL_RXDATA15 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B5_8.GTPE2_CHANNEL_PCSRSVDOUT11 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B5_9.GTPE2_CHANNEL_RXDATA7 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B5_10.GTPE2_CHANNEL_PCSRSVDOUT0 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B6_2.GTPE2_CHANNEL_RXPHSLIPMONITOR3 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B6_4.GTPE2_CHANNEL_RXDATA24 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B6_6.GTPE2_CHANNEL_RXDATA16 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B6_7.GTPE2_CHANNEL_RXOSINTSTARTED always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B6_8.GTPE2_CHANNEL_RXDATA8 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B6_10.GTPE2_CHANNEL_RXDATA0 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B7_2.GTPE2_CHANNEL_RXPHMONITOR2 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B7_3.GTPE2_CHANNEL_RXDATA29 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B7_4.GTPE2_CHANNEL_PCSRSVDOUT12 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B7_5.GTPE2_CHANNEL_RXDATA21 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B7_6.GTPE2_CHANNEL_PMARSVDOUT1 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B7_7.GTPE2_CHANNEL_RXDATA13 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B7_8.GTPE2_CHANNEL_DRPDO12 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B7_9.GTPE2_CHANNEL_RXDATA5 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B8_0.GTPE2_CHANNEL_RXBYTEISALIGNED always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B8_1.GTPE2_CHANNEL_RXCHANBONDSEQ always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B9_0.GTPE2_CHANNEL_RXPHSLIPMONITOR2 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B9_2.GTPE2_CHANNEL_PCSRSVDOUT13 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B9_3.GTPE2_CHANNEL_DMONITOROUT7 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B9_4.GTPE2_CHANNEL_DMONITOROUT6 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B9_5.GTPE2_CHANNEL_DMONITOROUT5 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B9_6.GTPE2_CHANNEL_DMONITOROUT4 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B9_7.GTPE2_CHANNEL_DMONITOROUT3 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B9_8.GTPE2_CHANNEL_DMONITOROUT2 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B9_9.GTPE2_CHANNEL_DMONITOROUT1 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B9_10.GTPE2_CHANNEL_DMONITOROUT0 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B10_0.GTPE2_CHANNEL_RXPHMONITOR1 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B10_1.GTPE2_CHANNEL_RXSYNCOUT always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B10_3.GTPE2_CHANNEL_DRPDO4 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B10_5.GTPE2_CHANNEL_DMONITOROUT14 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B10_9.GTPE2_CHANNEL_PHYSTATUS always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B11_0.GTPE2_CHANNEL_RXCLKCORCNT0 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B11_10.GTPE2_CHANNEL_RXSTARTOFSEQ1 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B12_0.GTPE2_CHANNEL_RXDLYSRESETDONE always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B12_1.GTPE2_CHANNEL_RXCOMWAKEDET always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B12_2.GTPE2_CHANNEL_RXPMARESETDONE always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B12_3.GTPE2_CHANNEL_DRPDO0 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B12_4.GTPE2_CHANNEL_RXCHARISK3 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B12_5.GTPE2_CHANNEL_DRPDO5 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B12_6.GTPE2_CHANNEL_RXCHARISK2 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B12_7.GTPE2_CHANNEL_DRPDO14 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B12_8.GTPE2_CHANNEL_RXCHARISK1 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B12_9.GTPE2_CHANNEL_DRPDO8 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B12_10.GTPE2_CHANNEL_RXCHARISK0 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B13_0.GTPE2_CHANNEL_RXPHSLIPMONITOR0 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B13_1.GTPE2_CHANNEL_RXDATAVALID0 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B13_2.GTPE2_CHANNEL_PCSRSVDOUT2 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B13_3.GTPE2_CHANNEL_PCSRSVDOUT3 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B13_4.GTPE2_CHANNEL_PCSRSVDOUT4 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B13_5.GTPE2_CHANNEL_PCSRSVDOUT5 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B13_6.GTPE2_CHANNEL_PCSRSVDOUT6 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B13_7.GTPE2_CHANNEL_PCSRSVDOUT7 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B13_8.GTPE2_CHANNEL_PCSRSVDOUT8 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B13_9.GTPE2_CHANNEL_PCSRSVDOUT9 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B13_10.GTPE2_CHANNEL_PCSRSVDOUT10 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B14_0.GTPE2_CHANNEL_RXBYTEREALIGN always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B14_1.GTPE2_CHANNEL_RXHEADERVALID always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B14_2.GTPE2_CHANNEL_TXPMARESETDONE always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B14_3.GTPE2_CHANNEL_DRPDO3 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B14_4.GTPE2_CHANNEL_RXNOTINTABLE3 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B14_5.GTPE2_CHANNEL_DRPRDY always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B14_6.GTPE2_CHANNEL_RXNOTINTABLE2 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B14_7.GTPE2_CHANNEL_TXSYNCOUT always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B14_8.GTPE2_CHANNEL_RXNOTINTABLE1 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B14_9.GTPE2_CHANNEL_RXSYNCDONE always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B14_10.GTPE2_CHANNEL_RXNOTINTABLE0 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B15_0.GTPE2_CHANNEL_RXCLKCORCNT1 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B15_1.GTPE2_CHANNEL_TXOUTCLKFABRIC always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B15_2.GTPE2_CHANNEL_DMONITOROUT12 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B15_3.GTPE2_CHANNEL_RXCHARISCOMMA3 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B15_4.GTPE2_CHANNEL_PCSRSVDOUT15 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B15_5.GTPE2_CHANNEL_RXCHARISCOMMA2 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B15_6.GTPE2_CHANNEL_PMARSVDOUT0 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B15_7.GTPE2_CHANNEL_RXCHARISCOMMA1 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B15_8.GTPE2_CHANNEL_DRPDO13 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B15_9.GTPE2_CHANNEL_RXCHARISCOMMA0 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B16_0.GTPE2_CHANNEL_RXPHMONITOR0 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B16_1.GTPE2_CHANNEL_RXPRBSERR always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B16_3.GTPE2_CHANNEL_RXPHSLIPMONITOR4 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B16_4.GTPE2_CHANNEL_TXRESETDONE always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B16_7.GTPE2_CHANNEL_RXCHBONDO3 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B16_8.GTPE2_CHANNEL_RXCHBONDO2 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B16_9.GTPE2_CHANNEL_RXCHBONDO1 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B16_10.GTPE2_CHANNEL_RXCHBONDO0 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B17_1.GTPE2_CHANNEL_RXPHMONITOR4 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B17_2.GTPE2_CHANNEL_TXBUFSTATUS0 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B17_3.GTPE2_CHANNEL_TXDLYSRESETDONE always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B17_4.GTPE2_CHANNEL_TXOUTCLKPCS always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B17_5.GTPE2_CHANNEL_RXCDRLOCK always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B17_6.GTPE2_CHANNEL_RXHEADER2 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B17_8.GTPE2_CHANNEL_RXSTATUS1 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B17_10.GTPE2_CHANNEL_RXBUFSTATUS2 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B18_0.GTPE2_CHANNEL_EYESCANDATAERROR always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B18_1.GTPE2_CHANNEL_RXRESETDONE always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B18_3.GTPE2_CHANNEL_TXPHALIGNDONE always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B18_4.GTPE2_CHANNEL_RXPHALIGNDONE always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B18_7.GTPE2_CHANNEL_RXCOMSASDET always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B18_8.GTPE2_CHANNEL_RXSTARTOFSEQ0 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B18_9.GTPE2_CHANNEL_RXCHANISALIGNED always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B19_0.GTPE2_CHANNEL_RXPHSLIPMONITOR1 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B19_6.GTPE2_CHANNEL_RXHEADER0 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B19_7.GTPE2_CHANNEL_RXCOMMADET always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B19_8.GTPE2_CHANNEL_RXELECIDLE always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B19_10.GTPE2_CHANNEL_RXBUFSTATUS1 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B20_0.GTPE2_CHANNEL_TXBUFSTATUS1 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B20_1.GTPE2_CHANNEL_RXCOMINITDET always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B20_4.GTPE2_CHANNEL_TXRATEDONE always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B20_9.GTPE2_CHANNEL_RXVALID always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B21_4.GTPE2_CHANNEL_DMONITOROUT11 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B21_5.GTPE2_CHANNEL_DMONITOROUT10 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B21_6.GTPE2_CHANNEL_DMONITOROUT9 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B21_7.GTPE2_CHANNEL_DMONITOROUT8 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B21_8.GTPE2_CHANNEL_RXSTATUS0 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B22_0.GTPE2_CHANNEL_RXOUTCLKFABRIC always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B22_1.GTPE2_CHANNEL_RXOUTCLKPCS always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B22_3.GTPE2_CHANNEL_DRPDO1 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B22_4.GTPE2_CHANNEL_RXDISPERR3 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B22_5.GTPE2_CHANNEL_DRPDO6 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B22_6.GTPE2_CHANNEL_RXDISPERR2 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B22_8.GTPE2_CHANNEL_RXDISPERR1 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B22_9.GTPE2_CHANNEL_TXSYNCDONE always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B22_10.GTPE2_CHANNEL_RXDISPERR0 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B23_1.GTPE2_CHANNEL_TXCOMFINISH always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B23_4.GTPE2_CHANNEL_TXGEARBOXREADY always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B23_5.GTPE2_CHANNEL_RXRATEDONE always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B23_6.GTPE2_CHANNEL_RXHEADER1 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B23_8.GTPE2_CHANNEL_RXSTATUS2 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B23_9.GTPE2_CHANNEL_RXCHANREALIGN always +GTP_CHANNEL_3_MID_LEFT.GTPE2_LOGIC_OUTS_B23_10.GTPE2_CHANNEL_RXBUFSTATUS0 always diff --git a/artix7/ppips_gtp_channel_3_mid_right.db b/artix7/ppips_gtp_channel_3_mid_right.db index 38fc343..4a1190e 100644 --- a/artix7/ppips_gtp_channel_3_mid_right.db +++ b/artix7/ppips_gtp_channel_3_mid_right.db @@ -10,6 +10,10 @@ GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_EYESCANTRIGGER.GTPE2_IMUX31_8 always GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_GTRESETSEL.GTPE2_CTRL0_10 always GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_GTRXRESET.GTPE2_CTRL0_8 always GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_GTTXRESET.GTPE2_CTRL0_5 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_PLL0CLK.GTPE2_CHANNEL_PLLCLK0 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_PLL0REFCLK.GTPE2_CHANNEL_PLLREFCLK0 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_PLL1CLK.GTPE2_CHANNEL_PLLCLK1 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_PLL1REFCLK.GTPE2_CHANNEL_PLLREFCLK1 always GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RESETOVRD.GTPE2_IMUX41_5 always GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RX8B10BEN.GTPE2_IMUX45_1 always GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXBUFRESET.GTPE2_CTRL1_6 always @@ -36,6 +40,7 @@ GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXLPMLFOVRDEN.GTPE2_IMUX3_10 always GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXLPMOSINTNTRLEN.GTPE2_IMUX7_2 always GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXLPMRESET.GTPE2_CTRL0_9 always GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXMCOMMAALIGNEN.GTPE2_IMUX41_1 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXN.GTPE2_CHANNEL_RXN_PAD always GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXOOBRESET.GTPE2_CTRL1_10 always GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXOSCALRESET.GTPE2_IMUX46_2 always GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXOSHOLD.GTPE2_IMUX29_8 always @@ -47,6 +52,8 @@ GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXOSINTPD.GTPE2_IMUX3_0 always GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXOSINTSTROBE.GTPE2_IMUX32_9 always GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXOSINTTESTOVRDEN.GTPE2_IMUX5_9 always GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXOSOVRDEN.GTPE2_IMUX13_8 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXOUTCLK_3.GTPE2_CHANNEL_GTRXOUTCLK_3 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXP.GTPE2_CHANNEL_RXP_PAD always GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXPCOMMAALIGNEN.GTPE2_IMUX40_1 always GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXPCSRESET.GTPE2_IMUX46_1 always GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXPHALIGN.GTPE2_IMUX14_9 always @@ -81,6 +88,9 @@ GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXDLYSRESET.GTPE2_IMUX45_3 always GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXDLYUPDOWN.GTPE2_IMUX43_5 always GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXELECIDLE.GTPE2_IMUX39_6 always GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXINHIBIT.GTPE2_IMUX32_2 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXN_PAD.GTPE2_CHANNEL_TXN always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXOUTCLK_3.GTPE2_CHANNEL_GTTXOUTCLK_3 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXP_PAD.GTPE2_CHANNEL_TXP always GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXPCSRESET.GTPE2_IMUX46_0 always GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXPDELECIDLEMODE.GTPE2_IMUX14_0 always GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXPHALIGN.GTPE2_IMUX25_2 always @@ -344,3 +354,173 @@ GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXSEQUENCE6.GTPE2_IMUX8_0 always GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXSYSCLKSEL0.GTPE2_IMUX28_5 always GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXSYSCLKSEL1.GTPE2_IMUX28_4 always GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXUSRCLK2.GTPE2_CLK0_5 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B0_3.GTPE2_CHANNEL_RXOSINTSTROBEDONE always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B0_4.GTPE2_CHANNEL_RXDATA27 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B0_5.GTPE2_CHANNEL_PCSRSVDOUT1 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B0_6.GTPE2_CHANNEL_RXDATA19 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B0_7.GTPE2_CHANNEL_RXOSINTSTROBESTARTED always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B0_8.GTPE2_CHANNEL_RXDATA11 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B0_10.GTPE2_CHANNEL_RXDATA3 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B1_3.GTPE2_CHANNEL_RXDATA30 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B1_5.GTPE2_CHANNEL_RXDATA22 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B1_6.GTPE2_CHANNEL_DMONITOROUT13 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B1_7.GTPE2_CHANNEL_RXDATA14 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B1_8.GTPE2_CHANNEL_DRPDO11 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B1_9.GTPE2_CHANNEL_RXDATA6 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B1_10.GTPE2_CHANNEL_TXPHINITDONE always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B2_4.GTPE2_CHANNEL_RXDATA25 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B2_6.GTPE2_CHANNEL_RXDATA17 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B2_8.GTPE2_CHANNEL_RXDATA9 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B2_9.GTPE2_CHANNEL_DRPDO10 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B2_10.GTPE2_CHANNEL_RXDATA1 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B3_2.GTPE2_CHANNEL_RXPHMONITOR3 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B3_3.GTPE2_CHANNEL_RXDATA28 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B3_5.GTPE2_CHANNEL_RXDATA20 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B3_6.GTPE2_CHANNEL_RXOSINTDONE always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B3_7.GTPE2_CHANNEL_RXDATA12 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B3_9.GTPE2_CHANNEL_RXDATA4 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B4_3.GTPE2_CHANNEL_DRPDO2 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B4_4.GTPE2_CHANNEL_RXDATA26 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B4_5.GTPE2_CHANNEL_DRPDO7 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B4_6.GTPE2_CHANNEL_RXDATA18 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B4_7.GTPE2_CHANNEL_DRPDO15 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B4_8.GTPE2_CHANNEL_RXDATA10 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B4_9.GTPE2_CHANNEL_DRPDO9 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B4_10.GTPE2_CHANNEL_RXDATA2 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B5_1.GTPE2_CHANNEL_RXDATAVALID1 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B5_3.GTPE2_CHANNEL_RXDATA31 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B5_5.GTPE2_CHANNEL_RXDATA23 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B5_6.GTPE2_CHANNEL_PCSRSVDOUT14 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B5_7.GTPE2_CHANNEL_RXDATA15 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B5_8.GTPE2_CHANNEL_PCSRSVDOUT11 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B5_9.GTPE2_CHANNEL_RXDATA7 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B5_10.GTPE2_CHANNEL_PCSRSVDOUT0 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B6_2.GTPE2_CHANNEL_RXPHSLIPMONITOR3 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B6_4.GTPE2_CHANNEL_RXDATA24 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B6_6.GTPE2_CHANNEL_RXDATA16 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B6_7.GTPE2_CHANNEL_RXOSINTSTARTED always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B6_8.GTPE2_CHANNEL_RXDATA8 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B6_10.GTPE2_CHANNEL_RXDATA0 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B7_2.GTPE2_CHANNEL_RXPHMONITOR2 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B7_3.GTPE2_CHANNEL_RXDATA29 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B7_4.GTPE2_CHANNEL_PCSRSVDOUT12 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B7_5.GTPE2_CHANNEL_RXDATA21 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B7_6.GTPE2_CHANNEL_PMARSVDOUT1 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B7_7.GTPE2_CHANNEL_RXDATA13 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B7_8.GTPE2_CHANNEL_DRPDO12 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B7_9.GTPE2_CHANNEL_RXDATA5 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B8_0.GTPE2_CHANNEL_RXBYTEISALIGNED always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B8_1.GTPE2_CHANNEL_RXCHANBONDSEQ always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B9_0.GTPE2_CHANNEL_RXPHSLIPMONITOR2 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B9_2.GTPE2_CHANNEL_PCSRSVDOUT13 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B9_3.GTPE2_CHANNEL_DMONITOROUT7 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B9_4.GTPE2_CHANNEL_DMONITOROUT6 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B9_5.GTPE2_CHANNEL_DMONITOROUT5 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B9_6.GTPE2_CHANNEL_DMONITOROUT4 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B9_7.GTPE2_CHANNEL_DMONITOROUT3 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B9_8.GTPE2_CHANNEL_DMONITOROUT2 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B9_9.GTPE2_CHANNEL_DMONITOROUT1 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B9_10.GTPE2_CHANNEL_DMONITOROUT0 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B10_0.GTPE2_CHANNEL_RXPHMONITOR1 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B10_1.GTPE2_CHANNEL_RXSYNCOUT always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B10_3.GTPE2_CHANNEL_DRPDO4 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B10_5.GTPE2_CHANNEL_DMONITOROUT14 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B10_9.GTPE2_CHANNEL_PHYSTATUS always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B11_0.GTPE2_CHANNEL_RXCLKCORCNT0 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B11_10.GTPE2_CHANNEL_RXSTARTOFSEQ1 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B12_0.GTPE2_CHANNEL_RXDLYSRESETDONE always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B12_1.GTPE2_CHANNEL_RXCOMWAKEDET always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B12_2.GTPE2_CHANNEL_RXPMARESETDONE always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B12_3.GTPE2_CHANNEL_DRPDO0 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B12_4.GTPE2_CHANNEL_RXCHARISK3 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B12_5.GTPE2_CHANNEL_DRPDO5 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B12_6.GTPE2_CHANNEL_RXCHARISK2 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B12_7.GTPE2_CHANNEL_DRPDO14 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B12_8.GTPE2_CHANNEL_RXCHARISK1 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B12_9.GTPE2_CHANNEL_DRPDO8 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B12_10.GTPE2_CHANNEL_RXCHARISK0 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B13_0.GTPE2_CHANNEL_RXPHSLIPMONITOR0 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B13_1.GTPE2_CHANNEL_RXDATAVALID0 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B13_2.GTPE2_CHANNEL_PCSRSVDOUT2 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B13_3.GTPE2_CHANNEL_PCSRSVDOUT3 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B13_4.GTPE2_CHANNEL_PCSRSVDOUT4 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B13_5.GTPE2_CHANNEL_PCSRSVDOUT5 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B13_6.GTPE2_CHANNEL_PCSRSVDOUT6 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B13_7.GTPE2_CHANNEL_PCSRSVDOUT7 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B13_8.GTPE2_CHANNEL_PCSRSVDOUT8 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B13_9.GTPE2_CHANNEL_PCSRSVDOUT9 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B13_10.GTPE2_CHANNEL_PCSRSVDOUT10 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B14_0.GTPE2_CHANNEL_RXBYTEREALIGN always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B14_1.GTPE2_CHANNEL_RXHEADERVALID always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B14_2.GTPE2_CHANNEL_TXPMARESETDONE always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B14_3.GTPE2_CHANNEL_DRPDO3 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B14_4.GTPE2_CHANNEL_RXNOTINTABLE3 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B14_5.GTPE2_CHANNEL_DRPRDY always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B14_6.GTPE2_CHANNEL_RXNOTINTABLE2 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B14_7.GTPE2_CHANNEL_TXSYNCOUT always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B14_8.GTPE2_CHANNEL_RXNOTINTABLE1 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B14_9.GTPE2_CHANNEL_RXSYNCDONE always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B14_10.GTPE2_CHANNEL_RXNOTINTABLE0 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B15_0.GTPE2_CHANNEL_RXCLKCORCNT1 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B15_1.GTPE2_CHANNEL_TXOUTCLKFABRIC always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B15_2.GTPE2_CHANNEL_DMONITOROUT12 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B15_3.GTPE2_CHANNEL_RXCHARISCOMMA3 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B15_4.GTPE2_CHANNEL_PCSRSVDOUT15 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B15_5.GTPE2_CHANNEL_RXCHARISCOMMA2 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B15_6.GTPE2_CHANNEL_PMARSVDOUT0 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B15_7.GTPE2_CHANNEL_RXCHARISCOMMA1 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B15_8.GTPE2_CHANNEL_DRPDO13 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B15_9.GTPE2_CHANNEL_RXCHARISCOMMA0 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B16_0.GTPE2_CHANNEL_RXPHMONITOR0 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B16_1.GTPE2_CHANNEL_RXPRBSERR always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B16_3.GTPE2_CHANNEL_RXPHSLIPMONITOR4 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B16_4.GTPE2_CHANNEL_TXRESETDONE always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B16_7.GTPE2_CHANNEL_RXCHBONDO3 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B16_8.GTPE2_CHANNEL_RXCHBONDO2 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B16_9.GTPE2_CHANNEL_RXCHBONDO1 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B16_10.GTPE2_CHANNEL_RXCHBONDO0 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B17_1.GTPE2_CHANNEL_RXPHMONITOR4 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B17_2.GTPE2_CHANNEL_TXBUFSTATUS0 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B17_3.GTPE2_CHANNEL_TXDLYSRESETDONE always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B17_4.GTPE2_CHANNEL_TXOUTCLKPCS always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B17_5.GTPE2_CHANNEL_RXCDRLOCK always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B17_6.GTPE2_CHANNEL_RXHEADER2 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B17_8.GTPE2_CHANNEL_RXSTATUS1 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B17_10.GTPE2_CHANNEL_RXBUFSTATUS2 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B18_0.GTPE2_CHANNEL_EYESCANDATAERROR always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B18_1.GTPE2_CHANNEL_RXRESETDONE always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B18_3.GTPE2_CHANNEL_TXPHALIGNDONE always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B18_4.GTPE2_CHANNEL_RXPHALIGNDONE always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B18_7.GTPE2_CHANNEL_RXCOMSASDET always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B18_8.GTPE2_CHANNEL_RXSTARTOFSEQ0 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B18_9.GTPE2_CHANNEL_RXCHANISALIGNED always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B19_0.GTPE2_CHANNEL_RXPHSLIPMONITOR1 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B19_6.GTPE2_CHANNEL_RXHEADER0 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B19_7.GTPE2_CHANNEL_RXCOMMADET always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B19_8.GTPE2_CHANNEL_RXELECIDLE always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B19_10.GTPE2_CHANNEL_RXBUFSTATUS1 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B20_0.GTPE2_CHANNEL_TXBUFSTATUS1 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B20_1.GTPE2_CHANNEL_RXCOMINITDET always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B20_4.GTPE2_CHANNEL_TXRATEDONE always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B20_9.GTPE2_CHANNEL_RXVALID always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B21_4.GTPE2_CHANNEL_DMONITOROUT11 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B21_5.GTPE2_CHANNEL_DMONITOROUT10 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B21_6.GTPE2_CHANNEL_DMONITOROUT9 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B21_7.GTPE2_CHANNEL_DMONITOROUT8 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B21_8.GTPE2_CHANNEL_RXSTATUS0 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B22_0.GTPE2_CHANNEL_RXOUTCLKFABRIC always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B22_1.GTPE2_CHANNEL_RXOUTCLKPCS always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B22_3.GTPE2_CHANNEL_DRPDO1 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B22_4.GTPE2_CHANNEL_RXDISPERR3 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B22_5.GTPE2_CHANNEL_DRPDO6 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B22_6.GTPE2_CHANNEL_RXDISPERR2 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B22_8.GTPE2_CHANNEL_RXDISPERR1 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B22_9.GTPE2_CHANNEL_TXSYNCDONE always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B22_10.GTPE2_CHANNEL_RXDISPERR0 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B23_1.GTPE2_CHANNEL_TXCOMFINISH always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B23_4.GTPE2_CHANNEL_TXGEARBOXREADY always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B23_5.GTPE2_CHANNEL_RXRATEDONE always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B23_6.GTPE2_CHANNEL_RXHEADER1 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B23_8.GTPE2_CHANNEL_RXSTATUS2 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B23_9.GTPE2_CHANNEL_RXCHANREALIGN always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_LOGIC_OUTS_B23_10.GTPE2_CHANNEL_RXBUFSTATUS0 always diff --git a/artix7/ppips_gtp_common.db b/artix7/ppips_gtp_common.db index 6d7b59e..ccd1b1d 100644 --- a/artix7/ppips_gtp_common.db +++ b/artix7/ppips_gtp_common.db @@ -1,5 +1,15 @@ GTP_COMMON.IBUFDS_GTPE2_0_CEB.GTPE2_IMUX3_1 always +GTP_COMMON.IBUFDS_GTPE2_0_CLKTESTSIG.IBUFDS_GTPE2_0_CLKTESTSIG_SEG always +GTP_COMMON.IBUFDS_GTPE2_0_I_SEG.IBUFDS_GTPE2_0_I always +GTP_COMMON.IBUFDS_GTPE2_0_IB_SEG.IBUFDS_GTPE2_0_IB always +GTP_COMMON.IBUFDS_GTPE2_0_MGTCLKOUT.IBUFDS_GTPE2_0_O always +GTP_COMMON.IBUFDS_GTPE2_0_MGTCLKOUT.IBUFDS_GTPE2_0_ODIV2 always GTP_COMMON.IBUFDS_GTPE2_1_CEB.GTPE2_IMUX0_1 always +GTP_COMMON.IBUFDS_GTPE2_1_CLKTESTSIG.IBUFDS_GTPE2_1_CLKTESTSIG_SEG always +GTP_COMMON.IBUFDS_GTPE2_1_I_SEG.IBUFDS_GTPE2_1_I always +GTP_COMMON.IBUFDS_GTPE2_1_IB_SEG.IBUFDS_GTPE2_1_IB always +GTP_COMMON.IBUFDS_GTPE2_1_MGTCLKOUT.IBUFDS_GTPE2_1_O always +GTP_COMMON.IBUFDS_GTPE2_1_MGTCLKOUT.IBUFDS_GTPE2_1_ODIV2 always GTP_COMMON.GTPE2_COMMON_BGBYPASSB.GTPE2_IMUX27_1 always GTP_COMMON.GTPE2_COMMON_BGMONITORENB.GTPE2_IMUX22_1 always GTP_COMMON.GTPE2_COMMON_BGPDB.GTPE2_IMUX3_3 always @@ -7,6 +17,16 @@ GTP_COMMON.GTPE2_COMMON_BGRCALOVRDENB.GTPE2_IMUX42_5 always GTP_COMMON.GTPE2_COMMON_DRPCLK.GTPE2_CLK1_5 always GTP_COMMON.GTPE2_COMMON_DRPEN.GTPE2_IMUX22_3 always GTP_COMMON.GTPE2_COMMON_DRPWE.GTPE2_IMUX35_1 always +GTP_COMMON.GTPE2_COMMON_MGT_CLK0.GTPE2_COMMON_RXOUTCLK_0 always +GTP_COMMON.GTPE2_COMMON_MGT_CLK1.GTPE2_COMMON_RXOUTCLK_1 always +GTP_COMMON.GTPE2_COMMON_MGT_CLK2.GTPE2_COMMON_TXOUTCLK_0 always +GTP_COMMON.GTPE2_COMMON_MGT_CLK3.GTPE2_COMMON_TXOUTCLK_1 always +GTP_COMMON.GTPE2_COMMON_MGT_CLK4.IBUFDS_GTPE2_0_MGTCLKOUT always +GTP_COMMON.GTPE2_COMMON_MGT_CLK5.IBUFDS_GTPE2_1_MGTCLKOUT always +GTP_COMMON.GTPE2_COMMON_MGT_CLK6.GTPE2_COMMON_RXOUTCLK_2 always +GTP_COMMON.GTPE2_COMMON_MGT_CLK7.GTPE2_COMMON_RXOUTCLK_3 always +GTP_COMMON.GTPE2_COMMON_MGT_CLK8.GTPE2_COMMON_TXOUTCLK_2 always +GTP_COMMON.GTPE2_COMMON_MGT_CLK9.GTPE2_COMMON_TXOUTCLK_3 always GTP_COMMON.GTPE2_COMMON_PLL0LOCKDETCLK.GTPE2_CLK0_1 always GTP_COMMON.GTPE2_COMMON_PLL0LOCKEN.GTPE2_IMUX42_4 always GTP_COMMON.GTPE2_COMMON_PLL0PD.GTPE2_IMUX42_3 always @@ -47,12 +67,18 @@ GTP_COMMON.GTPE2_COMMON_DRPDI14.GTPE2_IMUX22_4 always GTP_COMMON.GTPE2_COMMON_DRPDI15.GTPE2_IMUX14_4 always GTP_COMMON.GTPE2_COMMON_GTGREFCLK0.GTPE2_CLK0_5 always GTP_COMMON.GTPE2_COMMON_GTGREFCLK1.GTPE2_CLK1_4 always +GTP_COMMON.GTPE2_COMMON_GTREFCLK0.GTPE2_COMMON_REFCLK0 always +GTP_COMMON.GTPE2_COMMON_GTREFCLK1.GTPE2_COMMON_REFCLK1 always GTP_COMMON.GTPE2_COMMON_PLL0REFCLKSEL0.GTPE2_IMUX2_5 always GTP_COMMON.GTPE2_COMMON_PLL0REFCLKSEL1.GTPE2_IMUX2_4 always GTP_COMMON.GTPE2_COMMON_PLL0REFCLKSEL2.GTPE2_IMUX2_3 always GTP_COMMON.GTPE2_COMMON_PLL1REFCLKSEL0.GTPE2_IMUX2_2 always GTP_COMMON.GTPE2_COMMON_PLL1REFCLKSEL1.GTPE2_IMUX2_1 always GTP_COMMON.GTPE2_COMMON_PLL1REFCLKSEL2.GTPE2_IMUX41_3 always +GTP_COMMON.GTPE2_COMMON_PLLOUTCLK0.GTPE2_COMMON_PLL0OUTCLK always +GTP_COMMON.GTPE2_COMMON_PLLOUTCLK1.GTPE2_COMMON_PLL1OUTCLK always +GTP_COMMON.GTPE2_COMMON_PLLREFCLK0.GTPE2_COMMON_PLL0REFCLK always +GTP_COMMON.GTPE2_COMMON_PLLREFCLK1.GTPE2_COMMON_PLL1REFCLK always GTP_COMMON.GTPE2_COMMON_PLLRSVD10.GTPE2_IMUX32_5 always GTP_COMMON.GTPE2_COMMON_PLLRSVD11.GTPE2_IMUX24_5 always GTP_COMMON.GTPE2_COMMON_PLLRSVD12.GTPE2_IMUX32_4 always @@ -82,3 +108,54 @@ GTP_COMMON.GTPE2_COMMON_PMARSVD4.GTPE2_IMUX20_1 always GTP_COMMON.GTPE2_COMMON_PMARSVD5.GTPE2_IMUX41_5 always GTP_COMMON.GTPE2_COMMON_PMARSVD6.GTPE2_IMUX41_4 always GTP_COMMON.GTPE2_COMMON_PMARSVD7.GTPE2_IMUX41_2 always +GTP_COMMON.GTPE2_COMMON_REFCLK0.IBUFDS_GTPE2_0_O always +GTP_COMMON.GTPE2_COMMON_REFCLK1.IBUFDS_GTPE2_1_O always +GTP_COMMON.GTPE2_LOGIC_OUTS_B8_1.GTPE2_COMMON_DMONITOROUT4 always +GTP_COMMON.GTPE2_LOGIC_OUTS_B8_2.GTPE2_COMMON_DMONITOROUT3 always +GTP_COMMON.GTPE2_LOGIC_OUTS_B8_3.GTPE2_COMMON_DMONITOROUT2 always +GTP_COMMON.GTPE2_LOGIC_OUTS_B8_4.GTPE2_COMMON_DMONITOROUT1 always +GTP_COMMON.GTPE2_LOGIC_OUTS_B8_5.GTPE2_COMMON_DMONITOROUT0 always +GTP_COMMON.GTPE2_LOGIC_OUTS_B9_1.GTPE2_COMMON_DRPDO4 always +GTP_COMMON.GTPE2_LOGIC_OUTS_B9_2.GTPE2_COMMON_DRPDO3 always +GTP_COMMON.GTPE2_LOGIC_OUTS_B9_3.GTPE2_COMMON_DRPDO2 always +GTP_COMMON.GTPE2_LOGIC_OUTS_B9_4.GTPE2_COMMON_DRPDO1 always +GTP_COMMON.GTPE2_LOGIC_OUTS_B9_5.GTPE2_COMMON_DRPDO0 always +GTP_COMMON.GTPE2_LOGIC_OUTS_B10_1.GTPE2_COMMON_DRPDO14 always +GTP_COMMON.GTPE2_LOGIC_OUTS_B10_2.GTPE2_COMMON_DRPDO13 always +GTP_COMMON.GTPE2_LOGIC_OUTS_B10_3.GTPE2_COMMON_DRPDO12 always +GTP_COMMON.GTPE2_LOGIC_OUTS_B10_4.GTPE2_COMMON_DRPDO11 always +GTP_COMMON.GTPE2_LOGIC_OUTS_B10_5.GTPE2_COMMON_DRPDO10 always +GTP_COMMON.GTPE2_LOGIC_OUTS_B11_4.GTPE2_COMMON_PLL1REFCLKLOST always +GTP_COMMON.GTPE2_LOGIC_OUTS_B11_5.GTPE2_COMMON_PLL1LOCK always +GTP_COMMON.GTPE2_LOGIC_OUTS_B13_1.GTPE2_COMMON_PMARSVDOUT4 always +GTP_COMMON.GTPE2_LOGIC_OUTS_B13_2.GTPE2_COMMON_PMARSVDOUT3 always +GTP_COMMON.GTPE2_LOGIC_OUTS_B13_3.GTPE2_COMMON_PMARSVDOUT2 always +GTP_COMMON.GTPE2_LOGIC_OUTS_B13_4.GTPE2_COMMON_PMARSVDOUT1 always +GTP_COMMON.GTPE2_LOGIC_OUTS_B13_5.GTPE2_COMMON_PMARSVDOUT0 always +GTP_COMMON.GTPE2_LOGIC_OUTS_B14_3.GTPE2_COMMON_DMONITOROUT7 always +GTP_COMMON.GTPE2_LOGIC_OUTS_B14_4.GTPE2_COMMON_DMONITOROUT6 always +GTP_COMMON.GTPE2_LOGIC_OUTS_B14_5.GTPE2_COMMON_DMONITOROUT5 always +GTP_COMMON.GTPE2_LOGIC_OUTS_B16_1.GTPE2_COMMON_DRPDO9 always +GTP_COMMON.GTPE2_LOGIC_OUTS_B16_2.GTPE2_COMMON_DRPDO8 always +GTP_COMMON.GTPE2_LOGIC_OUTS_B16_3.GTPE2_COMMON_DRPDO7 always +GTP_COMMON.GTPE2_LOGIC_OUTS_B16_4.GTPE2_COMMON_DRPDO6 always +GTP_COMMON.GTPE2_LOGIC_OUTS_B16_5.GTPE2_COMMON_DRPDO5 always +GTP_COMMON.GTPE2_LOGIC_OUTS_B17_1.GTPE2_COMMON_PLL0REFCLKLOST always +GTP_COMMON.GTPE2_LOGIC_OUTS_B17_2.GTPE2_COMMON_PLL0LOCK always +GTP_COMMON.GTPE2_LOGIC_OUTS_B17_3.GTPE2_COMMON_PLL0FBCLKLOST always +GTP_COMMON.GTPE2_LOGIC_OUTS_B17_4.GTPE2_COMMON_REFCLKOUTMONITOR0 always +GTP_COMMON.GTPE2_LOGIC_OUTS_B17_5.GTPE2_COMMON_DRPRDY always +GTP_COMMON.GTPE2_LOGIC_OUTS_B18_2.GTPE2_COMMON_REFCLKOUTMONITOR1 always +GTP_COMMON.GTPE2_LOGIC_OUTS_B18_3.GTPE2_COMMON_DRPDO15 always +GTP_COMMON.GTPE2_LOGIC_OUTS_B18_4.GTPE2_COMMON_PMARSVDOUT15 always +GTP_COMMON.GTPE2_LOGIC_OUTS_B18_5.GTPE2_COMMON_PLL1FBCLKLOST always +GTP_COMMON.GTPE2_LOGIC_OUTS_B19_1.GTPE2_COMMON_PMARSVDOUT9 always +GTP_COMMON.GTPE2_LOGIC_OUTS_B19_2.GTPE2_COMMON_PMARSVDOUT8 always +GTP_COMMON.GTPE2_LOGIC_OUTS_B19_3.GTPE2_COMMON_PMARSVDOUT7 always +GTP_COMMON.GTPE2_LOGIC_OUTS_B19_4.GTPE2_COMMON_PMARSVDOUT6 always +GTP_COMMON.GTPE2_LOGIC_OUTS_B19_5.GTPE2_COMMON_PMARSVDOUT5 always +GTP_COMMON.GTPE2_LOGIC_OUTS_B20_1.GTPE2_COMMON_PMARSVDOUT14 always +GTP_COMMON.GTPE2_LOGIC_OUTS_B20_2.GTPE2_COMMON_PMARSVDOUT13 always +GTP_COMMON.GTPE2_LOGIC_OUTS_B20_3.GTPE2_COMMON_PMARSVDOUT12 always +GTP_COMMON.GTPE2_LOGIC_OUTS_B20_4.GTPE2_COMMON_PMARSVDOUT11 always +GTP_COMMON.GTPE2_LOGIC_OUTS_B20_5.GTPE2_COMMON_PMARSVDOUT10 always diff --git a/artix7/ppips_gtp_common_mid_left.db b/artix7/ppips_gtp_common_mid_left.db index 36acb7c..0c76a54 100644 --- a/artix7/ppips_gtp_common_mid_left.db +++ b/artix7/ppips_gtp_common_mid_left.db @@ -1,5 +1,15 @@ GTP_COMMON_MID_LEFT.IBUFDS_GTPE2_0_CEB.GTPE2_IMUX3_1 always +GTP_COMMON_MID_LEFT.IBUFDS_GTPE2_0_CLKTESTSIG.IBUFDS_GTPE2_0_CLKTESTSIG_SEG always +GTP_COMMON_MID_LEFT.IBUFDS_GTPE2_0_I_SEG.IBUFDS_GTPE2_0_I always +GTP_COMMON_MID_LEFT.IBUFDS_GTPE2_0_IB_SEG.IBUFDS_GTPE2_0_IB always +GTP_COMMON_MID_LEFT.IBUFDS_GTPE2_0_MGTCLKOUT.IBUFDS_GTPE2_0_O always +GTP_COMMON_MID_LEFT.IBUFDS_GTPE2_0_MGTCLKOUT.IBUFDS_GTPE2_0_ODIV2 always GTP_COMMON_MID_LEFT.IBUFDS_GTPE2_1_CEB.GTPE2_IMUX0_1 always +GTP_COMMON_MID_LEFT.IBUFDS_GTPE2_1_CLKTESTSIG.IBUFDS_GTPE2_1_CLKTESTSIG_SEG always +GTP_COMMON_MID_LEFT.IBUFDS_GTPE2_1_I_SEG.IBUFDS_GTPE2_1_I always +GTP_COMMON_MID_LEFT.IBUFDS_GTPE2_1_IB_SEG.IBUFDS_GTPE2_1_IB always +GTP_COMMON_MID_LEFT.IBUFDS_GTPE2_1_MGTCLKOUT.IBUFDS_GTPE2_1_O always +GTP_COMMON_MID_LEFT.IBUFDS_GTPE2_1_MGTCLKOUT.IBUFDS_GTPE2_1_ODIV2 always GTP_COMMON_MID_LEFT.GTPE2_COMMON_BGBYPASSB.GTPE2_IMUX27_1 always GTP_COMMON_MID_LEFT.GTPE2_COMMON_BGMONITORENB.GTPE2_IMUX22_1 always GTP_COMMON_MID_LEFT.GTPE2_COMMON_BGPDB.GTPE2_IMUX3_3 always @@ -47,12 +57,18 @@ GTP_COMMON_MID_LEFT.GTPE2_COMMON_DRPDI14.GTPE2_IMUX22_4 always GTP_COMMON_MID_LEFT.GTPE2_COMMON_DRPDI15.GTPE2_IMUX14_4 always GTP_COMMON_MID_LEFT.GTPE2_COMMON_GTGREFCLK0.GTPE2_CLK0_5 always GTP_COMMON_MID_LEFT.GTPE2_COMMON_GTGREFCLK1.GTPE2_CLK1_4 always +GTP_COMMON_MID_LEFT.GTPE2_COMMON_GTREFCLK0.GTPE2_COMMON_REFCLK0 always +GTP_COMMON_MID_LEFT.GTPE2_COMMON_GTREFCLK1.GTPE2_COMMON_REFCLK1 always GTP_COMMON_MID_LEFT.GTPE2_COMMON_PLL0REFCLKSEL0.GTPE2_IMUX2_5 always GTP_COMMON_MID_LEFT.GTPE2_COMMON_PLL0REFCLKSEL1.GTPE2_IMUX2_4 always GTP_COMMON_MID_LEFT.GTPE2_COMMON_PLL0REFCLKSEL2.GTPE2_IMUX2_3 always GTP_COMMON_MID_LEFT.GTPE2_COMMON_PLL1REFCLKSEL0.GTPE2_IMUX2_2 always GTP_COMMON_MID_LEFT.GTPE2_COMMON_PLL1REFCLKSEL1.GTPE2_IMUX2_1 always GTP_COMMON_MID_LEFT.GTPE2_COMMON_PLL1REFCLKSEL2.GTPE2_IMUX41_3 always +GTP_COMMON_MID_LEFT.GTPE2_COMMON_PLLOUTCLK0.GTPE2_COMMON_PLL0OUTCLK always +GTP_COMMON_MID_LEFT.GTPE2_COMMON_PLLOUTCLK1.GTPE2_COMMON_PLL1OUTCLK always +GTP_COMMON_MID_LEFT.GTPE2_COMMON_PLLREFCLK0.GTPE2_COMMON_PLL0REFCLK always +GTP_COMMON_MID_LEFT.GTPE2_COMMON_PLLREFCLK1.GTPE2_COMMON_PLL1REFCLK always GTP_COMMON_MID_LEFT.GTPE2_COMMON_PLLRSVD10.GTPE2_IMUX32_5 always GTP_COMMON_MID_LEFT.GTPE2_COMMON_PLLRSVD11.GTPE2_IMUX24_5 always GTP_COMMON_MID_LEFT.GTPE2_COMMON_PLLRSVD12.GTPE2_IMUX32_4 always @@ -82,3 +98,54 @@ GTP_COMMON_MID_LEFT.GTPE2_COMMON_PMARSVD4.GTPE2_IMUX20_1 always GTP_COMMON_MID_LEFT.GTPE2_COMMON_PMARSVD5.GTPE2_IMUX41_5 always GTP_COMMON_MID_LEFT.GTPE2_COMMON_PMARSVD6.GTPE2_IMUX41_4 always GTP_COMMON_MID_LEFT.GTPE2_COMMON_PMARSVD7.GTPE2_IMUX41_2 always +GTP_COMMON_MID_LEFT.GTPE2_COMMON_REFCLK0.IBUFDS_GTPE2_0_O always +GTP_COMMON_MID_LEFT.GTPE2_COMMON_REFCLK1.IBUFDS_GTPE2_1_O always +GTP_COMMON_MID_LEFT.GTPE2_LOGIC_OUTS_B8_1.GTPE2_COMMON_DMONITOROUT4 always +GTP_COMMON_MID_LEFT.GTPE2_LOGIC_OUTS_B8_2.GTPE2_COMMON_DMONITOROUT3 always +GTP_COMMON_MID_LEFT.GTPE2_LOGIC_OUTS_B8_3.GTPE2_COMMON_DMONITOROUT2 always +GTP_COMMON_MID_LEFT.GTPE2_LOGIC_OUTS_B8_4.GTPE2_COMMON_DMONITOROUT1 always +GTP_COMMON_MID_LEFT.GTPE2_LOGIC_OUTS_B8_5.GTPE2_COMMON_DMONITOROUT0 always +GTP_COMMON_MID_LEFT.GTPE2_LOGIC_OUTS_B9_1.GTPE2_COMMON_DRPDO4 always +GTP_COMMON_MID_LEFT.GTPE2_LOGIC_OUTS_B9_2.GTPE2_COMMON_DRPDO3 always +GTP_COMMON_MID_LEFT.GTPE2_LOGIC_OUTS_B9_3.GTPE2_COMMON_DRPDO2 always +GTP_COMMON_MID_LEFT.GTPE2_LOGIC_OUTS_B9_4.GTPE2_COMMON_DRPDO1 always +GTP_COMMON_MID_LEFT.GTPE2_LOGIC_OUTS_B9_5.GTPE2_COMMON_DRPDO0 always +GTP_COMMON_MID_LEFT.GTPE2_LOGIC_OUTS_B10_1.GTPE2_COMMON_DRPDO14 always +GTP_COMMON_MID_LEFT.GTPE2_LOGIC_OUTS_B10_2.GTPE2_COMMON_DRPDO13 always +GTP_COMMON_MID_LEFT.GTPE2_LOGIC_OUTS_B10_3.GTPE2_COMMON_DRPDO12 always +GTP_COMMON_MID_LEFT.GTPE2_LOGIC_OUTS_B10_4.GTPE2_COMMON_DRPDO11 always +GTP_COMMON_MID_LEFT.GTPE2_LOGIC_OUTS_B10_5.GTPE2_COMMON_DRPDO10 always +GTP_COMMON_MID_LEFT.GTPE2_LOGIC_OUTS_B11_4.GTPE2_COMMON_PLL1REFCLKLOST always +GTP_COMMON_MID_LEFT.GTPE2_LOGIC_OUTS_B11_5.GTPE2_COMMON_PLL1LOCK always +GTP_COMMON_MID_LEFT.GTPE2_LOGIC_OUTS_B13_1.GTPE2_COMMON_PMARSVDOUT4 always +GTP_COMMON_MID_LEFT.GTPE2_LOGIC_OUTS_B13_2.GTPE2_COMMON_PMARSVDOUT3 always +GTP_COMMON_MID_LEFT.GTPE2_LOGIC_OUTS_B13_3.GTPE2_COMMON_PMARSVDOUT2 always +GTP_COMMON_MID_LEFT.GTPE2_LOGIC_OUTS_B13_4.GTPE2_COMMON_PMARSVDOUT1 always +GTP_COMMON_MID_LEFT.GTPE2_LOGIC_OUTS_B13_5.GTPE2_COMMON_PMARSVDOUT0 always +GTP_COMMON_MID_LEFT.GTPE2_LOGIC_OUTS_B14_3.GTPE2_COMMON_DMONITOROUT7 always +GTP_COMMON_MID_LEFT.GTPE2_LOGIC_OUTS_B14_4.GTPE2_COMMON_DMONITOROUT6 always +GTP_COMMON_MID_LEFT.GTPE2_LOGIC_OUTS_B14_5.GTPE2_COMMON_DMONITOROUT5 always +GTP_COMMON_MID_LEFT.GTPE2_LOGIC_OUTS_B16_1.GTPE2_COMMON_DRPDO9 always +GTP_COMMON_MID_LEFT.GTPE2_LOGIC_OUTS_B16_2.GTPE2_COMMON_DRPDO8 always +GTP_COMMON_MID_LEFT.GTPE2_LOGIC_OUTS_B16_3.GTPE2_COMMON_DRPDO7 always +GTP_COMMON_MID_LEFT.GTPE2_LOGIC_OUTS_B16_4.GTPE2_COMMON_DRPDO6 always +GTP_COMMON_MID_LEFT.GTPE2_LOGIC_OUTS_B16_5.GTPE2_COMMON_DRPDO5 always +GTP_COMMON_MID_LEFT.GTPE2_LOGIC_OUTS_B17_1.GTPE2_COMMON_PLL0REFCLKLOST always +GTP_COMMON_MID_LEFT.GTPE2_LOGIC_OUTS_B17_2.GTPE2_COMMON_PLL0LOCK always +GTP_COMMON_MID_LEFT.GTPE2_LOGIC_OUTS_B17_3.GTPE2_COMMON_PLL0FBCLKLOST always +GTP_COMMON_MID_LEFT.GTPE2_LOGIC_OUTS_B17_4.GTPE2_COMMON_REFCLKOUTMONITOR0 always +GTP_COMMON_MID_LEFT.GTPE2_LOGIC_OUTS_B17_5.GTPE2_COMMON_DRPRDY always +GTP_COMMON_MID_LEFT.GTPE2_LOGIC_OUTS_B18_2.GTPE2_COMMON_REFCLKOUTMONITOR1 always +GTP_COMMON_MID_LEFT.GTPE2_LOGIC_OUTS_B18_3.GTPE2_COMMON_DRPDO15 always +GTP_COMMON_MID_LEFT.GTPE2_LOGIC_OUTS_B18_4.GTPE2_COMMON_PMARSVDOUT15 always +GTP_COMMON_MID_LEFT.GTPE2_LOGIC_OUTS_B18_5.GTPE2_COMMON_PLL1FBCLKLOST always +GTP_COMMON_MID_LEFT.GTPE2_LOGIC_OUTS_B19_1.GTPE2_COMMON_PMARSVDOUT9 always +GTP_COMMON_MID_LEFT.GTPE2_LOGIC_OUTS_B19_2.GTPE2_COMMON_PMARSVDOUT8 always +GTP_COMMON_MID_LEFT.GTPE2_LOGIC_OUTS_B19_3.GTPE2_COMMON_PMARSVDOUT7 always +GTP_COMMON_MID_LEFT.GTPE2_LOGIC_OUTS_B19_4.GTPE2_COMMON_PMARSVDOUT6 always +GTP_COMMON_MID_LEFT.GTPE2_LOGIC_OUTS_B19_5.GTPE2_COMMON_PMARSVDOUT5 always +GTP_COMMON_MID_LEFT.GTPE2_LOGIC_OUTS_B20_1.GTPE2_COMMON_PMARSVDOUT14 always +GTP_COMMON_MID_LEFT.GTPE2_LOGIC_OUTS_B20_2.GTPE2_COMMON_PMARSVDOUT13 always +GTP_COMMON_MID_LEFT.GTPE2_LOGIC_OUTS_B20_3.GTPE2_COMMON_PMARSVDOUT12 always +GTP_COMMON_MID_LEFT.GTPE2_LOGIC_OUTS_B20_4.GTPE2_COMMON_PMARSVDOUT11 always +GTP_COMMON_MID_LEFT.GTPE2_LOGIC_OUTS_B20_5.GTPE2_COMMON_PMARSVDOUT10 always diff --git a/artix7/ppips_gtp_common_mid_right.db b/artix7/ppips_gtp_common_mid_right.db index 3fb4779..1a5e718 100644 --- a/artix7/ppips_gtp_common_mid_right.db +++ b/artix7/ppips_gtp_common_mid_right.db @@ -1,5 +1,15 @@ GTP_COMMON_MID_RIGHT.IBUFDS_GTPE2_0_CEB.GTPE2_IMUX3_1 always +GTP_COMMON_MID_RIGHT.IBUFDS_GTPE2_0_CLKTESTSIG.IBUFDS_GTPE2_0_CLKTESTSIG_SEG always +GTP_COMMON_MID_RIGHT.IBUFDS_GTPE2_0_I_SEG.IBUFDS_GTPE2_0_I always +GTP_COMMON_MID_RIGHT.IBUFDS_GTPE2_0_IB_SEG.IBUFDS_GTPE2_0_IB always +GTP_COMMON_MID_RIGHT.IBUFDS_GTPE2_0_MGTCLKOUT.IBUFDS_GTPE2_0_O always +GTP_COMMON_MID_RIGHT.IBUFDS_GTPE2_0_MGTCLKOUT.IBUFDS_GTPE2_0_ODIV2 always GTP_COMMON_MID_RIGHT.IBUFDS_GTPE2_1_CEB.GTPE2_IMUX0_1 always +GTP_COMMON_MID_RIGHT.IBUFDS_GTPE2_1_CLKTESTSIG.IBUFDS_GTPE2_1_CLKTESTSIG_SEG always +GTP_COMMON_MID_RIGHT.IBUFDS_GTPE2_1_I_SEG.IBUFDS_GTPE2_1_I always +GTP_COMMON_MID_RIGHT.IBUFDS_GTPE2_1_IB_SEG.IBUFDS_GTPE2_1_IB always +GTP_COMMON_MID_RIGHT.IBUFDS_GTPE2_1_MGTCLKOUT.IBUFDS_GTPE2_1_O always +GTP_COMMON_MID_RIGHT.IBUFDS_GTPE2_1_MGTCLKOUT.IBUFDS_GTPE2_1_ODIV2 always GTP_COMMON_MID_RIGHT.GTPE2_COMMON_BGBYPASSB.GTPE2_IMUX27_1 always GTP_COMMON_MID_RIGHT.GTPE2_COMMON_BGMONITORENB.GTPE2_IMUX22_1 always GTP_COMMON_MID_RIGHT.GTPE2_COMMON_BGPDB.GTPE2_IMUX3_3 always @@ -47,12 +57,18 @@ GTP_COMMON_MID_RIGHT.GTPE2_COMMON_DRPDI14.GTPE2_IMUX22_4 always GTP_COMMON_MID_RIGHT.GTPE2_COMMON_DRPDI15.GTPE2_IMUX14_4 always GTP_COMMON_MID_RIGHT.GTPE2_COMMON_GTGREFCLK0.GTPE2_CLK0_5 always GTP_COMMON_MID_RIGHT.GTPE2_COMMON_GTGREFCLK1.GTPE2_CLK1_4 always +GTP_COMMON_MID_RIGHT.GTPE2_COMMON_GTREFCLK0.GTPE2_COMMON_REFCLK0 always +GTP_COMMON_MID_RIGHT.GTPE2_COMMON_GTREFCLK1.GTPE2_COMMON_REFCLK1 always GTP_COMMON_MID_RIGHT.GTPE2_COMMON_PLL0REFCLKSEL0.GTPE2_IMUX2_5 always GTP_COMMON_MID_RIGHT.GTPE2_COMMON_PLL0REFCLKSEL1.GTPE2_IMUX2_4 always GTP_COMMON_MID_RIGHT.GTPE2_COMMON_PLL0REFCLKSEL2.GTPE2_IMUX2_3 always GTP_COMMON_MID_RIGHT.GTPE2_COMMON_PLL1REFCLKSEL0.GTPE2_IMUX2_2 always GTP_COMMON_MID_RIGHT.GTPE2_COMMON_PLL1REFCLKSEL1.GTPE2_IMUX2_1 always GTP_COMMON_MID_RIGHT.GTPE2_COMMON_PLL1REFCLKSEL2.GTPE2_IMUX41_3 always +GTP_COMMON_MID_RIGHT.GTPE2_COMMON_PLLOUTCLK0.GTPE2_COMMON_PLL0OUTCLK always +GTP_COMMON_MID_RIGHT.GTPE2_COMMON_PLLOUTCLK1.GTPE2_COMMON_PLL1OUTCLK always +GTP_COMMON_MID_RIGHT.GTPE2_COMMON_PLLREFCLK0.GTPE2_COMMON_PLL0REFCLK always +GTP_COMMON_MID_RIGHT.GTPE2_COMMON_PLLREFCLK1.GTPE2_COMMON_PLL1REFCLK always GTP_COMMON_MID_RIGHT.GTPE2_COMMON_PLLRSVD10.GTPE2_IMUX32_5 always GTP_COMMON_MID_RIGHT.GTPE2_COMMON_PLLRSVD11.GTPE2_IMUX24_5 always GTP_COMMON_MID_RIGHT.GTPE2_COMMON_PLLRSVD12.GTPE2_IMUX32_4 always @@ -82,3 +98,54 @@ GTP_COMMON_MID_RIGHT.GTPE2_COMMON_PMARSVD4.GTPE2_IMUX20_1 always GTP_COMMON_MID_RIGHT.GTPE2_COMMON_PMARSVD5.GTPE2_IMUX41_5 always GTP_COMMON_MID_RIGHT.GTPE2_COMMON_PMARSVD6.GTPE2_IMUX41_4 always GTP_COMMON_MID_RIGHT.GTPE2_COMMON_PMARSVD7.GTPE2_IMUX41_2 always +GTP_COMMON_MID_RIGHT.GTPE2_COMMON_REFCLK0.IBUFDS_GTPE2_0_O always +GTP_COMMON_MID_RIGHT.GTPE2_COMMON_REFCLK1.IBUFDS_GTPE2_1_O always +GTP_COMMON_MID_RIGHT.GTPE2_LOGIC_OUTS_B8_1.GTPE2_COMMON_DMONITOROUT4 always +GTP_COMMON_MID_RIGHT.GTPE2_LOGIC_OUTS_B8_2.GTPE2_COMMON_DMONITOROUT3 always +GTP_COMMON_MID_RIGHT.GTPE2_LOGIC_OUTS_B8_3.GTPE2_COMMON_DMONITOROUT2 always +GTP_COMMON_MID_RIGHT.GTPE2_LOGIC_OUTS_B8_4.GTPE2_COMMON_DMONITOROUT1 always +GTP_COMMON_MID_RIGHT.GTPE2_LOGIC_OUTS_B8_5.GTPE2_COMMON_DMONITOROUT0 always +GTP_COMMON_MID_RIGHT.GTPE2_LOGIC_OUTS_B9_1.GTPE2_COMMON_DRPDO4 always +GTP_COMMON_MID_RIGHT.GTPE2_LOGIC_OUTS_B9_2.GTPE2_COMMON_DRPDO3 always +GTP_COMMON_MID_RIGHT.GTPE2_LOGIC_OUTS_B9_3.GTPE2_COMMON_DRPDO2 always +GTP_COMMON_MID_RIGHT.GTPE2_LOGIC_OUTS_B9_4.GTPE2_COMMON_DRPDO1 always +GTP_COMMON_MID_RIGHT.GTPE2_LOGIC_OUTS_B9_5.GTPE2_COMMON_DRPDO0 always +GTP_COMMON_MID_RIGHT.GTPE2_LOGIC_OUTS_B10_1.GTPE2_COMMON_DRPDO14 always +GTP_COMMON_MID_RIGHT.GTPE2_LOGIC_OUTS_B10_2.GTPE2_COMMON_DRPDO13 always +GTP_COMMON_MID_RIGHT.GTPE2_LOGIC_OUTS_B10_3.GTPE2_COMMON_DRPDO12 always +GTP_COMMON_MID_RIGHT.GTPE2_LOGIC_OUTS_B10_4.GTPE2_COMMON_DRPDO11 always +GTP_COMMON_MID_RIGHT.GTPE2_LOGIC_OUTS_B10_5.GTPE2_COMMON_DRPDO10 always +GTP_COMMON_MID_RIGHT.GTPE2_LOGIC_OUTS_B11_4.GTPE2_COMMON_PLL1REFCLKLOST always +GTP_COMMON_MID_RIGHT.GTPE2_LOGIC_OUTS_B11_5.GTPE2_COMMON_PLL1LOCK always +GTP_COMMON_MID_RIGHT.GTPE2_LOGIC_OUTS_B13_1.GTPE2_COMMON_PMARSVDOUT4 always +GTP_COMMON_MID_RIGHT.GTPE2_LOGIC_OUTS_B13_2.GTPE2_COMMON_PMARSVDOUT3 always +GTP_COMMON_MID_RIGHT.GTPE2_LOGIC_OUTS_B13_3.GTPE2_COMMON_PMARSVDOUT2 always +GTP_COMMON_MID_RIGHT.GTPE2_LOGIC_OUTS_B13_4.GTPE2_COMMON_PMARSVDOUT1 always +GTP_COMMON_MID_RIGHT.GTPE2_LOGIC_OUTS_B13_5.GTPE2_COMMON_PMARSVDOUT0 always +GTP_COMMON_MID_RIGHT.GTPE2_LOGIC_OUTS_B14_3.GTPE2_COMMON_DMONITOROUT7 always +GTP_COMMON_MID_RIGHT.GTPE2_LOGIC_OUTS_B14_4.GTPE2_COMMON_DMONITOROUT6 always +GTP_COMMON_MID_RIGHT.GTPE2_LOGIC_OUTS_B14_5.GTPE2_COMMON_DMONITOROUT5 always +GTP_COMMON_MID_RIGHT.GTPE2_LOGIC_OUTS_B16_1.GTPE2_COMMON_DRPDO9 always +GTP_COMMON_MID_RIGHT.GTPE2_LOGIC_OUTS_B16_2.GTPE2_COMMON_DRPDO8 always +GTP_COMMON_MID_RIGHT.GTPE2_LOGIC_OUTS_B16_3.GTPE2_COMMON_DRPDO7 always +GTP_COMMON_MID_RIGHT.GTPE2_LOGIC_OUTS_B16_4.GTPE2_COMMON_DRPDO6 always +GTP_COMMON_MID_RIGHT.GTPE2_LOGIC_OUTS_B16_5.GTPE2_COMMON_DRPDO5 always +GTP_COMMON_MID_RIGHT.GTPE2_LOGIC_OUTS_B17_1.GTPE2_COMMON_PLL0REFCLKLOST always +GTP_COMMON_MID_RIGHT.GTPE2_LOGIC_OUTS_B17_2.GTPE2_COMMON_PLL0LOCK always +GTP_COMMON_MID_RIGHT.GTPE2_LOGIC_OUTS_B17_3.GTPE2_COMMON_PLL0FBCLKLOST always +GTP_COMMON_MID_RIGHT.GTPE2_LOGIC_OUTS_B17_4.GTPE2_COMMON_REFCLKOUTMONITOR0 always +GTP_COMMON_MID_RIGHT.GTPE2_LOGIC_OUTS_B17_5.GTPE2_COMMON_DRPRDY always +GTP_COMMON_MID_RIGHT.GTPE2_LOGIC_OUTS_B18_2.GTPE2_COMMON_REFCLKOUTMONITOR1 always +GTP_COMMON_MID_RIGHT.GTPE2_LOGIC_OUTS_B18_3.GTPE2_COMMON_DRPDO15 always +GTP_COMMON_MID_RIGHT.GTPE2_LOGIC_OUTS_B18_4.GTPE2_COMMON_PMARSVDOUT15 always +GTP_COMMON_MID_RIGHT.GTPE2_LOGIC_OUTS_B18_5.GTPE2_COMMON_PLL1FBCLKLOST always +GTP_COMMON_MID_RIGHT.GTPE2_LOGIC_OUTS_B19_1.GTPE2_COMMON_PMARSVDOUT9 always +GTP_COMMON_MID_RIGHT.GTPE2_LOGIC_OUTS_B19_2.GTPE2_COMMON_PMARSVDOUT8 always +GTP_COMMON_MID_RIGHT.GTPE2_LOGIC_OUTS_B19_3.GTPE2_COMMON_PMARSVDOUT7 always +GTP_COMMON_MID_RIGHT.GTPE2_LOGIC_OUTS_B19_4.GTPE2_COMMON_PMARSVDOUT6 always +GTP_COMMON_MID_RIGHT.GTPE2_LOGIC_OUTS_B19_5.GTPE2_COMMON_PMARSVDOUT5 always +GTP_COMMON_MID_RIGHT.GTPE2_LOGIC_OUTS_B20_1.GTPE2_COMMON_PMARSVDOUT14 always +GTP_COMMON_MID_RIGHT.GTPE2_LOGIC_OUTS_B20_2.GTPE2_COMMON_PMARSVDOUT13 always +GTP_COMMON_MID_RIGHT.GTPE2_LOGIC_OUTS_B20_3.GTPE2_COMMON_PMARSVDOUT12 always +GTP_COMMON_MID_RIGHT.GTPE2_LOGIC_OUTS_B20_4.GTPE2_COMMON_PMARSVDOUT11 always +GTP_COMMON_MID_RIGHT.GTPE2_LOGIC_OUTS_B20_5.GTPE2_COMMON_PMARSVDOUT10 always diff --git a/artix7/ppips_gtp_int_interface.db b/artix7/ppips_gtp_int_interface.db index 0f88d75..e50f60c 100644 --- a/artix7/ppips_gtp_int_interface.db +++ b/artix7/ppips_gtp_int_interface.db @@ -1,3 +1,75 @@ +GTP_INT_INTERFACE.INT_INTERFACE_LOGIC_OUTS0.INT_INTERFACE_LOGIC_OUTS_B0 always +GTP_INT_INTERFACE.INT_INTERFACE_LOGIC_OUTS1.INT_INTERFACE_LOGIC_OUTS_B1 always +GTP_INT_INTERFACE.INT_INTERFACE_LOGIC_OUTS2.INT_INTERFACE_LOGIC_OUTS_B2 always +GTP_INT_INTERFACE.INT_INTERFACE_LOGIC_OUTS3.INT_INTERFACE_LOGIC_OUTS_B3 always +GTP_INT_INTERFACE.INT_INTERFACE_LOGIC_OUTS4.INT_INTERFACE_LOGIC_OUTS_B4 always +GTP_INT_INTERFACE.INT_INTERFACE_LOGIC_OUTS5.INT_INTERFACE_LOGIC_OUTS_B5 always +GTP_INT_INTERFACE.INT_INTERFACE_LOGIC_OUTS6.INT_INTERFACE_LOGIC_OUTS_B6 always +GTP_INT_INTERFACE.INT_INTERFACE_LOGIC_OUTS7.INT_INTERFACE_LOGIC_OUTS_B7 always +GTP_INT_INTERFACE.INT_INTERFACE_LOGIC_OUTS8.INT_INTERFACE_LOGIC_OUTS_B8 always +GTP_INT_INTERFACE.INT_INTERFACE_LOGIC_OUTS9.INT_INTERFACE_LOGIC_OUTS_B9 always +GTP_INT_INTERFACE.INT_INTERFACE_LOGIC_OUTS10.INT_INTERFACE_LOGIC_OUTS_B10 always +GTP_INT_INTERFACE.INT_INTERFACE_LOGIC_OUTS11.INT_INTERFACE_LOGIC_OUTS_B11 always +GTP_INT_INTERFACE.INT_INTERFACE_LOGIC_OUTS12.INT_INTERFACE_LOGIC_OUTS_B12 always +GTP_INT_INTERFACE.INT_INTERFACE_LOGIC_OUTS13.INT_INTERFACE_LOGIC_OUTS_B13 always +GTP_INT_INTERFACE.INT_INTERFACE_LOGIC_OUTS14.INT_INTERFACE_LOGIC_OUTS_B14 always +GTP_INT_INTERFACE.INT_INTERFACE_LOGIC_OUTS15.INT_INTERFACE_LOGIC_OUTS_B15 always +GTP_INT_INTERFACE.INT_INTERFACE_LOGIC_OUTS16.INT_INTERFACE_LOGIC_OUTS_B16 always +GTP_INT_INTERFACE.INT_INTERFACE_LOGIC_OUTS17.INT_INTERFACE_LOGIC_OUTS_B17 always +GTP_INT_INTERFACE.INT_INTERFACE_LOGIC_OUTS18.INT_INTERFACE_LOGIC_OUTS_B18 always +GTP_INT_INTERFACE.INT_INTERFACE_LOGIC_OUTS19.INT_INTERFACE_LOGIC_OUTS_B19 always +GTP_INT_INTERFACE.INT_INTERFACE_LOGIC_OUTS20.INT_INTERFACE_LOGIC_OUTS_B20 always +GTP_INT_INTERFACE.INT_INTERFACE_LOGIC_OUTS21.INT_INTERFACE_LOGIC_OUTS_B21 always +GTP_INT_INTERFACE.INT_INTERFACE_LOGIC_OUTS22.INT_INTERFACE_LOGIC_OUTS_B22 always +GTP_INT_INTERFACE.INT_INTERFACE_LOGIC_OUTS23.INT_INTERFACE_LOGIC_OUTS_B23 always +GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY0.GTPE2_INT_INTERFACE_IMUX0 always +GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY1.GTPE2_INT_INTERFACE_IMUX1 always +GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY2.GTPE2_INT_INTERFACE_IMUX2 always +GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY3.GTPE2_INT_INTERFACE_IMUX3 always +GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY4.GTPE2_INT_INTERFACE_IMUX4 always +GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY5.GTPE2_INT_INTERFACE_IMUX5 always +GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY6.GTPE2_INT_INTERFACE_IMUX6 always +GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY7.GTPE2_INT_INTERFACE_IMUX7 always +GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY8.GTPE2_INT_INTERFACE_IMUX8 always +GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY9.GTPE2_INT_INTERFACE_IMUX9 always +GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY10.GTPE2_INT_INTERFACE_IMUX10 always +GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY11.GTPE2_INT_INTERFACE_IMUX11 always +GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY12.GTPE2_INT_INTERFACE_IMUX12 always +GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY13.GTPE2_INT_INTERFACE_IMUX13 always +GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY14.GTPE2_INT_INTERFACE_IMUX14 always +GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY15.GTPE2_INT_INTERFACE_IMUX15 always +GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY16.GTPE2_INT_INTERFACE_IMUX16 always +GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY17.GTPE2_INT_INTERFACE_IMUX17 always +GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY18.GTPE2_INT_INTERFACE_IMUX18 always +GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY19.GTPE2_INT_INTERFACE_IMUX19 always +GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY20.GTPE2_INT_INTERFACE_IMUX20 always +GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY21.GTPE2_INT_INTERFACE_IMUX21 always +GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY22.GTPE2_INT_INTERFACE_IMUX22 always +GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY23.GTPE2_INT_INTERFACE_IMUX23 always +GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY24.GTPE2_INT_INTERFACE_IMUX24 always +GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY25.GTPE2_INT_INTERFACE_IMUX25 always +GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY26.GTPE2_INT_INTERFACE_IMUX26 always +GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY27.GTPE2_INT_INTERFACE_IMUX27 always +GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY28.GTPE2_INT_INTERFACE_IMUX28 always +GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY29.GTPE2_INT_INTERFACE_IMUX29 always +GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY30.GTPE2_INT_INTERFACE_IMUX30 always +GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY31.GTPE2_INT_INTERFACE_IMUX31 always +GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY32.GTPE2_INT_INTERFACE_IMUX32 always +GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY33.GTPE2_INT_INTERFACE_IMUX33 always +GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY34.GTPE2_INT_INTERFACE_IMUX34 always +GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY35.GTPE2_INT_INTERFACE_IMUX35 always +GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY36.GTPE2_INT_INTERFACE_IMUX36 always +GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY37.GTPE2_INT_INTERFACE_IMUX37 always +GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY38.GTPE2_INT_INTERFACE_IMUX38 always +GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY39.GTPE2_INT_INTERFACE_IMUX39 always +GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY40.GTPE2_INT_INTERFACE_IMUX40 always +GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY41.GTPE2_INT_INTERFACE_IMUX41 always +GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY42.GTPE2_INT_INTERFACE_IMUX42 always +GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY43.GTPE2_INT_INTERFACE_IMUX43 always +GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY44.GTPE2_INT_INTERFACE_IMUX44 always +GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY45.GTPE2_INT_INTERFACE_IMUX45 always +GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY46.GTPE2_INT_INTERFACE_IMUX46 always +GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY47.GTPE2_INT_INTERFACE_IMUX47 always GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_OUT0.GTPE2_INT_INTERFACE_IMUX0 always GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_OUT1.GTPE2_INT_INTERFACE_IMUX1 always GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_OUT2.GTPE2_INT_INTERFACE_IMUX2 always diff --git a/artix7/ppips_gtp_int_interface_l.db b/artix7/ppips_gtp_int_interface_l.db new file mode 100644 index 0000000..423d413 --- /dev/null +++ b/artix7/ppips_gtp_int_interface_l.db @@ -0,0 +1,120 @@ +GTP_INT_INTERFACE_L.GTPE2_INT_INTERFACE_LOGIC_OUTS0.GTPE2_INT_INTERFACE_LOGIC_OUTS_B0 always +GTP_INT_INTERFACE_L.GTPE2_INT_INTERFACE_LOGIC_OUTS1.GTPE2_INT_INTERFACE_LOGIC_OUTS_B1 always +GTP_INT_INTERFACE_L.GTPE2_INT_INTERFACE_LOGIC_OUTS2.GTPE2_INT_INTERFACE_LOGIC_OUTS_B2 always +GTP_INT_INTERFACE_L.GTPE2_INT_INTERFACE_LOGIC_OUTS3.GTPE2_INT_INTERFACE_LOGIC_OUTS_B3 always +GTP_INT_INTERFACE_L.GTPE2_INT_INTERFACE_LOGIC_OUTS4.GTPE2_INT_INTERFACE_LOGIC_OUTS_B4 always +GTP_INT_INTERFACE_L.GTPE2_INT_INTERFACE_LOGIC_OUTS5.GTPE2_INT_INTERFACE_LOGIC_OUTS_B5 always +GTP_INT_INTERFACE_L.GTPE2_INT_INTERFACE_LOGIC_OUTS6.GTPE2_INT_INTERFACE_LOGIC_OUTS_B6 always +GTP_INT_INTERFACE_L.GTPE2_INT_INTERFACE_LOGIC_OUTS7.GTPE2_INT_INTERFACE_LOGIC_OUTS_B7 always +GTP_INT_INTERFACE_L.GTPE2_INT_INTERFACE_LOGIC_OUTS8.GTPE2_INT_INTERFACE_LOGIC_OUTS_B8 always +GTP_INT_INTERFACE_L.GTPE2_INT_INTERFACE_LOGIC_OUTS9.GTPE2_INT_INTERFACE_LOGIC_OUTS_B9 always +GTP_INT_INTERFACE_L.GTPE2_INT_INTERFACE_LOGIC_OUTS10.GTPE2_INT_INTERFACE_LOGIC_OUTS_B10 always +GTP_INT_INTERFACE_L.GTPE2_INT_INTERFACE_LOGIC_OUTS11.GTPE2_INT_INTERFACE_LOGIC_OUTS_B11 always +GTP_INT_INTERFACE_L.GTPE2_INT_INTERFACE_LOGIC_OUTS12.GTPE2_INT_INTERFACE_LOGIC_OUTS_B12 always +GTP_INT_INTERFACE_L.GTPE2_INT_INTERFACE_LOGIC_OUTS13.GTPE2_INT_INTERFACE_LOGIC_OUTS_B13 always +GTP_INT_INTERFACE_L.GTPE2_INT_INTERFACE_LOGIC_OUTS14.GTPE2_INT_INTERFACE_LOGIC_OUTS_B14 always +GTP_INT_INTERFACE_L.GTPE2_INT_INTERFACE_LOGIC_OUTS15.GTPE2_INT_INTERFACE_LOGIC_OUTS_B15 always +GTP_INT_INTERFACE_L.GTPE2_INT_INTERFACE_LOGIC_OUTS16.GTPE2_INT_INTERFACE_LOGIC_OUTS_B16 always +GTP_INT_INTERFACE_L.GTPE2_INT_INTERFACE_LOGIC_OUTS17.GTPE2_INT_INTERFACE_LOGIC_OUTS_B17 always +GTP_INT_INTERFACE_L.GTPE2_INT_INTERFACE_LOGIC_OUTS18.GTPE2_INT_INTERFACE_LOGIC_OUTS_B18 always +GTP_INT_INTERFACE_L.GTPE2_INT_INTERFACE_LOGIC_OUTS19.GTPE2_INT_INTERFACE_LOGIC_OUTS_B19 always +GTP_INT_INTERFACE_L.GTPE2_INT_INTERFACE_LOGIC_OUTS20.GTPE2_INT_INTERFACE_LOGIC_OUTS_B20 always +GTP_INT_INTERFACE_L.GTPE2_INT_INTERFACE_LOGIC_OUTS21.GTPE2_INT_INTERFACE_LOGIC_OUTS_B21 always +GTP_INT_INTERFACE_L.GTPE2_INT_INTERFACE_LOGIC_OUTS22.GTPE2_INT_INTERFACE_LOGIC_OUTS_B22 always +GTP_INT_INTERFACE_L.GTPE2_INT_INTERFACE_LOGIC_OUTS23.GTPE2_INT_INTERFACE_LOGIC_OUTS_B23 always +GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_DELAY0.GTPE2_LEFT_INT_INTERFACE_IMUX0 always +GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_DELAY1.GTPE2_LEFT_INT_INTERFACE_IMUX1 always +GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_DELAY2.GTPE2_LEFT_INT_INTERFACE_IMUX2 always +GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_DELAY3.GTPE2_LEFT_INT_INTERFACE_IMUX3 always +GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_DELAY4.GTPE2_LEFT_INT_INTERFACE_IMUX4 always +GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_DELAY5.GTPE2_LEFT_INT_INTERFACE_IMUX5 always +GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_DELAY6.GTPE2_LEFT_INT_INTERFACE_IMUX6 always +GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_DELAY7.GTPE2_LEFT_INT_INTERFACE_IMUX7 always +GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_DELAY8.GTPE2_LEFT_INT_INTERFACE_IMUX8 always +GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_DELAY9.GTPE2_LEFT_INT_INTERFACE_IMUX9 always +GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_DELAY10.GTPE2_LEFT_INT_INTERFACE_IMUX10 always +GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_DELAY11.GTPE2_LEFT_INT_INTERFACE_IMUX11 always +GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_DELAY12.GTPE2_LEFT_INT_INTERFACE_IMUX12 always +GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_DELAY13.GTPE2_LEFT_INT_INTERFACE_IMUX13 always +GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_DELAY14.GTPE2_LEFT_INT_INTERFACE_IMUX14 always +GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_DELAY15.GTPE2_LEFT_INT_INTERFACE_IMUX15 always +GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_DELAY16.GTPE2_LEFT_INT_INTERFACE_IMUX16 always +GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_DELAY17.GTPE2_LEFT_INT_INTERFACE_IMUX17 always +GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_DELAY18.GTPE2_LEFT_INT_INTERFACE_IMUX18 always +GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_DELAY19.GTPE2_LEFT_INT_INTERFACE_IMUX19 always +GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_DELAY20.GTPE2_LEFT_INT_INTERFACE_IMUX20 always +GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_DELAY21.GTPE2_LEFT_INT_INTERFACE_IMUX21 always +GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_DELAY22.GTPE2_LEFT_INT_INTERFACE_IMUX22 always +GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_DELAY23.GTPE2_LEFT_INT_INTERFACE_IMUX23 always +GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_DELAY24.GTPE2_LEFT_INT_INTERFACE_IMUX24 always +GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_DELAY25.GTPE2_LEFT_INT_INTERFACE_IMUX25 always +GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_DELAY26.GTPE2_LEFT_INT_INTERFACE_IMUX26 always +GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_DELAY27.GTPE2_LEFT_INT_INTERFACE_IMUX27 always +GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_DELAY28.GTPE2_LEFT_INT_INTERFACE_IMUX28 always +GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_DELAY29.GTPE2_LEFT_INT_INTERFACE_IMUX29 always +GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_DELAY30.GTPE2_LEFT_INT_INTERFACE_IMUX30 always +GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_DELAY31.GTPE2_LEFT_INT_INTERFACE_IMUX31 always +GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_DELAY32.GTPE2_LEFT_INT_INTERFACE_IMUX32 always +GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_DELAY33.GTPE2_LEFT_INT_INTERFACE_IMUX33 always +GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_DELAY34.GTPE2_LEFT_INT_INTERFACE_IMUX34 always +GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_DELAY35.GTPE2_LEFT_INT_INTERFACE_IMUX35 always +GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_DELAY36.GTPE2_LEFT_INT_INTERFACE_IMUX36 always +GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_DELAY37.GTPE2_LEFT_INT_INTERFACE_IMUX37 always +GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_DELAY38.GTPE2_LEFT_INT_INTERFACE_IMUX38 always +GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_DELAY39.GTPE2_LEFT_INT_INTERFACE_IMUX39 always +GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_DELAY40.GTPE2_LEFT_INT_INTERFACE_IMUX40 always +GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_DELAY41.GTPE2_LEFT_INT_INTERFACE_IMUX41 always +GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_DELAY42.GTPE2_LEFT_INT_INTERFACE_IMUX42 always +GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_DELAY43.GTPE2_LEFT_INT_INTERFACE_IMUX43 always +GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_DELAY44.GTPE2_LEFT_INT_INTERFACE_IMUX44 always +GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_DELAY45.GTPE2_LEFT_INT_INTERFACE_IMUX45 always +GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_DELAY46.GTPE2_LEFT_INT_INTERFACE_IMUX46 always +GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_DELAY47.GTPE2_LEFT_INT_INTERFACE_IMUX47 always +GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_OUT0.GTPE2_LEFT_INT_INTERFACE_IMUX0 always +GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_OUT1.GTPE2_LEFT_INT_INTERFACE_IMUX1 always +GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_OUT2.GTPE2_LEFT_INT_INTERFACE_IMUX2 always +GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_OUT3.GTPE2_LEFT_INT_INTERFACE_IMUX3 always +GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_OUT4.GTPE2_LEFT_INT_INTERFACE_IMUX4 always +GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_OUT5.GTPE2_LEFT_INT_INTERFACE_IMUX5 always +GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_OUT6.GTPE2_LEFT_INT_INTERFACE_IMUX6 always +GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_OUT7.GTPE2_LEFT_INT_INTERFACE_IMUX7 always +GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_OUT8.GTPE2_LEFT_INT_INTERFACE_IMUX8 always +GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_OUT9.GTPE2_LEFT_INT_INTERFACE_IMUX9 always +GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_OUT10.GTPE2_LEFT_INT_INTERFACE_IMUX10 always +GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_OUT11.GTPE2_LEFT_INT_INTERFACE_IMUX11 always +GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_OUT12.GTPE2_LEFT_INT_INTERFACE_IMUX12 always +GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_OUT13.GTPE2_LEFT_INT_INTERFACE_IMUX13 always +GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_OUT14.GTPE2_LEFT_INT_INTERFACE_IMUX14 always +GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_OUT15.GTPE2_LEFT_INT_INTERFACE_IMUX15 always +GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_OUT16.GTPE2_LEFT_INT_INTERFACE_IMUX16 always +GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_OUT17.GTPE2_LEFT_INT_INTERFACE_IMUX17 always +GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_OUT18.GTPE2_LEFT_INT_INTERFACE_IMUX18 always +GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_OUT19.GTPE2_LEFT_INT_INTERFACE_IMUX19 always +GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_OUT20.GTPE2_LEFT_INT_INTERFACE_IMUX20 always +GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_OUT21.GTPE2_LEFT_INT_INTERFACE_IMUX21 always +GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_OUT22.GTPE2_LEFT_INT_INTERFACE_IMUX22 always +GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_OUT23.GTPE2_LEFT_INT_INTERFACE_IMUX23 always +GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_OUT24.GTPE2_LEFT_INT_INTERFACE_IMUX24 always +GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_OUT25.GTPE2_LEFT_INT_INTERFACE_IMUX25 always +GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_OUT26.GTPE2_LEFT_INT_INTERFACE_IMUX26 always +GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_OUT27.GTPE2_LEFT_INT_INTERFACE_IMUX27 always +GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_OUT28.GTPE2_LEFT_INT_INTERFACE_IMUX28 always +GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_OUT29.GTPE2_LEFT_INT_INTERFACE_IMUX29 always +GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_OUT30.GTPE2_LEFT_INT_INTERFACE_IMUX30 always +GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_OUT31.GTPE2_LEFT_INT_INTERFACE_IMUX31 always +GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_OUT32.GTPE2_LEFT_INT_INTERFACE_IMUX32 always +GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_OUT33.GTPE2_LEFT_INT_INTERFACE_IMUX33 always +GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_OUT34.GTPE2_LEFT_INT_INTERFACE_IMUX34 always +GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_OUT35.GTPE2_LEFT_INT_INTERFACE_IMUX35 always +GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_OUT36.GTPE2_LEFT_INT_INTERFACE_IMUX36 always +GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_OUT37.GTPE2_LEFT_INT_INTERFACE_IMUX37 always +GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_OUT38.GTPE2_LEFT_INT_INTERFACE_IMUX38 always +GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_OUT39.GTPE2_LEFT_INT_INTERFACE_IMUX39 always +GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_OUT40.GTPE2_LEFT_INT_INTERFACE_IMUX40 always +GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_OUT41.GTPE2_LEFT_INT_INTERFACE_IMUX41 always +GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_OUT42.GTPE2_LEFT_INT_INTERFACE_IMUX42 always +GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_OUT43.GTPE2_LEFT_INT_INTERFACE_IMUX43 always +GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_OUT44.GTPE2_LEFT_INT_INTERFACE_IMUX44 always +GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_OUT45.GTPE2_LEFT_INT_INTERFACE_IMUX45 always +GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_OUT46.GTPE2_LEFT_INT_INTERFACE_IMUX46 always +GTP_INT_INTERFACE_L.GTPE2_LEFT_INT_INTERFACE_IMUX_OUT47.GTPE2_LEFT_INT_INTERFACE_IMUX47 always diff --git a/artix7/ppips_gtp_int_interface_r.db b/artix7/ppips_gtp_int_interface_r.db new file mode 100644 index 0000000..49e1c84 --- /dev/null +++ b/artix7/ppips_gtp_int_interface_r.db @@ -0,0 +1,120 @@ +GTP_INT_INTERFACE_R.GTPE2_INT_INTERFACE_LOGIC_OUTS0.GTPE2_INT_INTERFACE_LOGIC_OUTS_B0 always +GTP_INT_INTERFACE_R.GTPE2_INT_INTERFACE_LOGIC_OUTS1.GTPE2_INT_INTERFACE_LOGIC_OUTS_B1 always +GTP_INT_INTERFACE_R.GTPE2_INT_INTERFACE_LOGIC_OUTS2.GTPE2_INT_INTERFACE_LOGIC_OUTS_B2 always +GTP_INT_INTERFACE_R.GTPE2_INT_INTERFACE_LOGIC_OUTS3.GTPE2_INT_INTERFACE_LOGIC_OUTS_B3 always +GTP_INT_INTERFACE_R.GTPE2_INT_INTERFACE_LOGIC_OUTS4.GTPE2_INT_INTERFACE_LOGIC_OUTS_B4 always +GTP_INT_INTERFACE_R.GTPE2_INT_INTERFACE_LOGIC_OUTS5.GTPE2_INT_INTERFACE_LOGIC_OUTS_B5 always +GTP_INT_INTERFACE_R.GTPE2_INT_INTERFACE_LOGIC_OUTS6.GTPE2_INT_INTERFACE_LOGIC_OUTS_B6 always +GTP_INT_INTERFACE_R.GTPE2_INT_INTERFACE_LOGIC_OUTS7.GTPE2_INT_INTERFACE_LOGIC_OUTS_B7 always +GTP_INT_INTERFACE_R.GTPE2_INT_INTERFACE_LOGIC_OUTS8.GTPE2_INT_INTERFACE_LOGIC_OUTS_B8 always +GTP_INT_INTERFACE_R.GTPE2_INT_INTERFACE_LOGIC_OUTS9.GTPE2_INT_INTERFACE_LOGIC_OUTS_B9 always +GTP_INT_INTERFACE_R.GTPE2_INT_INTERFACE_LOGIC_OUTS10.GTPE2_INT_INTERFACE_LOGIC_OUTS_B10 always +GTP_INT_INTERFACE_R.GTPE2_INT_INTERFACE_LOGIC_OUTS11.GTPE2_INT_INTERFACE_LOGIC_OUTS_B11 always +GTP_INT_INTERFACE_R.GTPE2_INT_INTERFACE_LOGIC_OUTS12.GTPE2_INT_INTERFACE_LOGIC_OUTS_B12 always +GTP_INT_INTERFACE_R.GTPE2_INT_INTERFACE_LOGIC_OUTS13.GTPE2_INT_INTERFACE_LOGIC_OUTS_B13 always +GTP_INT_INTERFACE_R.GTPE2_INT_INTERFACE_LOGIC_OUTS14.GTPE2_INT_INTERFACE_LOGIC_OUTS_B14 always +GTP_INT_INTERFACE_R.GTPE2_INT_INTERFACE_LOGIC_OUTS15.GTPE2_INT_INTERFACE_LOGIC_OUTS_B15 always +GTP_INT_INTERFACE_R.GTPE2_INT_INTERFACE_LOGIC_OUTS16.GTPE2_INT_INTERFACE_LOGIC_OUTS_B16 always +GTP_INT_INTERFACE_R.GTPE2_INT_INTERFACE_LOGIC_OUTS17.GTPE2_INT_INTERFACE_LOGIC_OUTS_B17 always +GTP_INT_INTERFACE_R.GTPE2_INT_INTERFACE_LOGIC_OUTS18.GTPE2_INT_INTERFACE_LOGIC_OUTS_B18 always +GTP_INT_INTERFACE_R.GTPE2_INT_INTERFACE_LOGIC_OUTS19.GTPE2_INT_INTERFACE_LOGIC_OUTS_B19 always +GTP_INT_INTERFACE_R.GTPE2_INT_INTERFACE_LOGIC_OUTS20.GTPE2_INT_INTERFACE_LOGIC_OUTS_B20 always +GTP_INT_INTERFACE_R.GTPE2_INT_INTERFACE_LOGIC_OUTS21.GTPE2_INT_INTERFACE_LOGIC_OUTS_B21 always +GTP_INT_INTERFACE_R.GTPE2_INT_INTERFACE_LOGIC_OUTS22.GTPE2_INT_INTERFACE_LOGIC_OUTS_B22 always +GTP_INT_INTERFACE_R.GTPE2_INT_INTERFACE_LOGIC_OUTS23.GTPE2_INT_INTERFACE_LOGIC_OUTS_B23 always +GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_DELAY0.GTPE2_R_INT_INTERFACE_IMUX0 always +GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_DELAY1.GTPE2_R_INT_INTERFACE_IMUX1 always +GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_DELAY2.GTPE2_R_INT_INTERFACE_IMUX2 always +GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_DELAY3.GTPE2_R_INT_INTERFACE_IMUX3 always +GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_DELAY4.GTPE2_R_INT_INTERFACE_IMUX4 always +GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_DELAY5.GTPE2_R_INT_INTERFACE_IMUX5 always +GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_DELAY6.GTPE2_R_INT_INTERFACE_IMUX6 always +GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_DELAY7.GTPE2_R_INT_INTERFACE_IMUX7 always +GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_DELAY8.GTPE2_R_INT_INTERFACE_IMUX8 always +GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_DELAY9.GTPE2_R_INT_INTERFACE_IMUX9 always +GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_DELAY10.GTPE2_R_INT_INTERFACE_IMUX10 always +GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_DELAY11.GTPE2_R_INT_INTERFACE_IMUX11 always +GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_DELAY12.GTPE2_R_INT_INTERFACE_IMUX12 always +GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_DELAY13.GTPE2_R_INT_INTERFACE_IMUX13 always +GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_DELAY14.GTPE2_R_INT_INTERFACE_IMUX14 always +GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_DELAY15.GTPE2_R_INT_INTERFACE_IMUX15 always +GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_DELAY16.GTPE2_R_INT_INTERFACE_IMUX16 always +GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_DELAY17.GTPE2_R_INT_INTERFACE_IMUX17 always +GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_DELAY18.GTPE2_R_INT_INTERFACE_IMUX18 always +GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_DELAY19.GTPE2_R_INT_INTERFACE_IMUX19 always +GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_DELAY20.GTPE2_R_INT_INTERFACE_IMUX20 always +GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_DELAY21.GTPE2_R_INT_INTERFACE_IMUX21 always +GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_DELAY22.GTPE2_R_INT_INTERFACE_IMUX22 always +GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_DELAY23.GTPE2_R_INT_INTERFACE_IMUX23 always +GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_DELAY24.GTPE2_R_INT_INTERFACE_IMUX24 always +GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_DELAY25.GTPE2_R_INT_INTERFACE_IMUX25 always +GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_DELAY26.GTPE2_R_INT_INTERFACE_IMUX26 always +GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_DELAY27.GTPE2_R_INT_INTERFACE_IMUX27 always +GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_DELAY28.GTPE2_R_INT_INTERFACE_IMUX28 always +GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_DELAY29.GTPE2_R_INT_INTERFACE_IMUX29 always +GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_DELAY30.GTPE2_R_INT_INTERFACE_IMUX30 always +GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_DELAY31.GTPE2_R_INT_INTERFACE_IMUX31 always +GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_DELAY32.GTPE2_R_INT_INTERFACE_IMUX32 always +GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_DELAY33.GTPE2_R_INT_INTERFACE_IMUX33 always +GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_DELAY34.GTPE2_R_INT_INTERFACE_IMUX34 always +GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_DELAY35.GTPE2_R_INT_INTERFACE_IMUX35 always +GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_DELAY36.GTPE2_R_INT_INTERFACE_IMUX36 always +GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_DELAY37.GTPE2_R_INT_INTERFACE_IMUX37 always +GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_DELAY38.GTPE2_R_INT_INTERFACE_IMUX38 always +GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_DELAY39.GTPE2_R_INT_INTERFACE_IMUX39 always +GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_DELAY40.GTPE2_R_INT_INTERFACE_IMUX40 always +GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_DELAY41.GTPE2_R_INT_INTERFACE_IMUX41 always +GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_DELAY42.GTPE2_R_INT_INTERFACE_IMUX42 always +GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_DELAY43.GTPE2_R_INT_INTERFACE_IMUX43 always +GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_DELAY44.GTPE2_R_INT_INTERFACE_IMUX44 always +GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_DELAY45.GTPE2_R_INT_INTERFACE_IMUX45 always +GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_DELAY46.GTPE2_R_INT_INTERFACE_IMUX46 always +GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_DELAY47.GTPE2_R_INT_INTERFACE_IMUX47 always +GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_OUT0.GTPE2_R_INT_INTERFACE_IMUX0 always +GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_OUT1.GTPE2_R_INT_INTERFACE_IMUX1 always +GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_OUT2.GTPE2_R_INT_INTERFACE_IMUX2 always +GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_OUT3.GTPE2_R_INT_INTERFACE_IMUX3 always +GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_OUT4.GTPE2_R_INT_INTERFACE_IMUX4 always +GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_OUT5.GTPE2_R_INT_INTERFACE_IMUX5 always +GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_OUT6.GTPE2_R_INT_INTERFACE_IMUX6 always +GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_OUT7.GTPE2_R_INT_INTERFACE_IMUX7 always +GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_OUT8.GTPE2_R_INT_INTERFACE_IMUX8 always +GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_OUT9.GTPE2_R_INT_INTERFACE_IMUX9 always +GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_OUT10.GTPE2_R_INT_INTERFACE_IMUX10 always +GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_OUT11.GTPE2_R_INT_INTERFACE_IMUX11 always +GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_OUT12.GTPE2_R_INT_INTERFACE_IMUX12 always +GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_OUT13.GTPE2_R_INT_INTERFACE_IMUX13 always +GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_OUT14.GTPE2_R_INT_INTERFACE_IMUX14 always +GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_OUT15.GTPE2_R_INT_INTERFACE_IMUX15 always +GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_OUT16.GTPE2_R_INT_INTERFACE_IMUX16 always +GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_OUT17.GTPE2_R_INT_INTERFACE_IMUX17 always +GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_OUT18.GTPE2_R_INT_INTERFACE_IMUX18 always +GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_OUT19.GTPE2_R_INT_INTERFACE_IMUX19 always +GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_OUT20.GTPE2_R_INT_INTERFACE_IMUX20 always +GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_OUT21.GTPE2_R_INT_INTERFACE_IMUX21 always +GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_OUT22.GTPE2_R_INT_INTERFACE_IMUX22 always +GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_OUT23.GTPE2_R_INT_INTERFACE_IMUX23 always +GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_OUT24.GTPE2_R_INT_INTERFACE_IMUX24 always +GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_OUT25.GTPE2_R_INT_INTERFACE_IMUX25 always +GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_OUT26.GTPE2_R_INT_INTERFACE_IMUX26 always +GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_OUT27.GTPE2_R_INT_INTERFACE_IMUX27 always +GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_OUT28.GTPE2_R_INT_INTERFACE_IMUX28 always +GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_OUT29.GTPE2_R_INT_INTERFACE_IMUX29 always +GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_OUT30.GTPE2_R_INT_INTERFACE_IMUX30 always +GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_OUT31.GTPE2_R_INT_INTERFACE_IMUX31 always +GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_OUT32.GTPE2_R_INT_INTERFACE_IMUX32 always +GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_OUT33.GTPE2_R_INT_INTERFACE_IMUX33 always +GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_OUT34.GTPE2_R_INT_INTERFACE_IMUX34 always +GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_OUT35.GTPE2_R_INT_INTERFACE_IMUX35 always +GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_OUT36.GTPE2_R_INT_INTERFACE_IMUX36 always +GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_OUT37.GTPE2_R_INT_INTERFACE_IMUX37 always +GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_OUT38.GTPE2_R_INT_INTERFACE_IMUX38 always +GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_OUT39.GTPE2_R_INT_INTERFACE_IMUX39 always +GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_OUT40.GTPE2_R_INT_INTERFACE_IMUX40 always +GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_OUT41.GTPE2_R_INT_INTERFACE_IMUX41 always +GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_OUT42.GTPE2_R_INT_INTERFACE_IMUX42 always +GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_OUT43.GTPE2_R_INT_INTERFACE_IMUX43 always +GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_OUT44.GTPE2_R_INT_INTERFACE_IMUX44 always +GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_OUT45.GTPE2_R_INT_INTERFACE_IMUX45 always +GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_OUT46.GTPE2_R_INT_INTERFACE_IMUX46 always +GTP_INT_INTERFACE_R.GTPE2_R_INT_INTERFACE_IMUX_OUT47.GTPE2_R_INT_INTERFACE_IMUX47 always diff --git a/artix7/ppips_pcie_bot.db b/artix7/ppips_pcie_bot.db new file mode 100644 index 0000000..f2a0989 --- /dev/null +++ b/artix7/ppips_pcie_bot.db @@ -0,0 +1,1736 @@ +PCIE_BOT.PCIE_CFGERRACSN.PCIE_IMUX12_R_16 always +PCIE_BOT.PCIE_CFGERRATOMICEGRESSBLOCKEDN.PCIE_IMUX13_R_17 always +PCIE_BOT.PCIE_CFGERRCORN.PCIE_IMUX9_R_15 always +PCIE_BOT.PCIE_CFGERRCPLABORTN.PCIE_IMUX9_R_16 always +PCIE_BOT.PCIE_CFGERRCPLTIMEOUTN.PCIE_IMUX12_R_15 always +PCIE_BOT.PCIE_CFGERRCPLUNEXPECTN.PCIE_IMUX10_R_16 always +PCIE_BOT.PCIE_CFGERRECRCN.PCIE_IMUX11_R_15 always +PCIE_BOT.PCIE_CFGERRINTERNALCORN.PCIE_IMUX17_R_17 always +PCIE_BOT.PCIE_CFGERRINTERNALUNCORN.PCIE_IMUX15_R_17 always +PCIE_BOT.PCIE_CFGERRMALFORMEDN.PCIE_IMUX8_R_14 always +PCIE_BOT.PCIE_CFGERRMCBLOCKEDN.PCIE_IMUX14_R_17 always +PCIE_BOT.PCIE_CFGERRPOISONEDN.PCIE_IMUX11_R_16 always +PCIE_BOT.PCIE_CFGERRPOSTEDN.PCIE_IMUX17_R_18 always +PCIE_BOT.PCIE_CFGERRURN.PCIE_IMUX10_R_15 always +PCIE_BOT.PCIE_CFGFORCECOMMONCLOCKOFF.PCIE_IMUX9_L_5 always +PCIE_BOT.PCIE_CFGFORCEEXTENDEDSYNCON.PCIE_IMUX10_L_5 always +PCIE_BOT.PCIE_CFGINTERRUPTASSERTN.PCIE_IMUX16_R_13 always +PCIE_BOT.PCIE_CFGINTERRUPTSTATN.PCIE_IMUX13_R_12 always +PCIE_BOT.PCIE_CFGMGMTRDENN.PCIE_IMUX7_R_14 always +PCIE_BOT.PCIE_CFGMGMTWRENN.PCIE_IMUX6_R_14 always +PCIE_BOT.PCIE_CFGMGMTWRREADONLYN.PCIE_IMUX5_R_14 always +PCIE_BOT.PCIE_CFGMGMTWRRW1CASRWN.PCIE_IMUX8_R_13 always +PCIE_BOT.PCIE_CFGPMFORCESTATEENN.PCIE_IMUX10_L_1 always +PCIE_BOT.PCIE_CFGPMHALTASPML0SN.PCIE_IMUX8_L_1 always +PCIE_BOT.PCIE_CFGPMHALTASPML1N.PCIE_IMUX9_L_1 always +PCIE_BOT.PCIE_CFGPMSENDPMETON.PCIE_IMUX11_L_2 always +PCIE_BOT.PCIE_CFGPMTURNOFFOKN.PCIE_IMUX10_L_2 always +PCIE_BOT.PCIE_CFGPMWAKEN.PCIE_IMUX9_L_2 always +PCIE_BOT.PCIE_CFGTRNPENDINGN.PCIE_IMUX9_L_4 always +PCIE_BOT.PCIE_CMRSTN.PCIE_CTRL1_R_0 always +PCIE_BOT.PCIE_CMSTICKYRSTN.PCIE_CTRL0_R_1 always +PCIE_BOT.PCIE_DBGSUBMODE.PCIE_IMUX21_R_12 always +PCIE_BOT.PCIE_DLRSTN.PCIE_CTRL1_R_2 always +PCIE_BOT.PCIE_DRPCLK.PCIE_CLK1_R_11 always +PCIE_BOT.PCIE_DRPEN.PCIE_IMUX13_L_16 always +PCIE_BOT.PCIE_DRPWE.PCIE_IMUX12_L_17 always +PCIE_BOT.PCIE_FUNCLVLRSTN.PCIE_CTRL1_R_1 always +PCIE_BOT.PCIE_LOGIC_OUTS_B0_L_0.PCIE_PIPETX3DATA12 always +PCIE_BOT.PCIE_LOGIC_OUTS_B0_L_1.PCIE_PLRXPMSTATE0 always +PCIE_BOT.PCIE_LOGIC_OUTS_B0_L_2.PCIE_PIPETX3DATA4 always +PCIE_BOT.PCIE_LOGIC_OUTS_B0_L_3.PCIE_PLDIRECTEDCHANGEDONE always +PCIE_BOT.PCIE_LOGIC_OUTS_B0_L_4.PCIE_PIPETX1DATA12 always +PCIE_BOT.PCIE_LOGIC_OUTS_B0_L_5.PCIE_TRNTCFGREQ always +PCIE_BOT.PCIE_LOGIC_OUTS_B0_L_6.PCIE_PIPETX1DATA4 always +PCIE_BOT.PCIE_LOGIC_OUTS_B0_L_7.PCIE_TRNRD7 always +PCIE_BOT.PCIE_LOGIC_OUTS_B0_L_8.PCIE_TRNRD11 always +PCIE_BOT.PCIE_LOGIC_OUTS_B0_L_9.PCIE_TRNRD15 always +PCIE_BOT.PCIE_LOGIC_OUTS_B0_L_10.PCIE_TRNRD19 always +PCIE_BOT.PCIE_LOGIC_OUTS_B0_L_11.PCIE_PIPETX2DATA12 always +PCIE_BOT.PCIE_LOGIC_OUTS_B0_L_12.PCIE_TRNRD27 always +PCIE_BOT.PCIE_LOGIC_OUTS_B0_L_13.PCIE_PIPETX2DATA4 always +PCIE_BOT.PCIE_LOGIC_OUTS_B0_L_14.PCIE_TRNRD35 always +PCIE_BOT.PCIE_LOGIC_OUTS_B0_L_15.PCIE_PIPETX0DATA12 always +PCIE_BOT.PCIE_LOGIC_OUTS_B0_L_16.PCIE_TRNRD43 always +PCIE_BOT.PCIE_LOGIC_OUTS_B0_L_17.PCIE_PIPETX0DATA4 always +PCIE_BOT.PCIE_LOGIC_OUTS_B0_L_18.PCIE_TRNRD51 always +PCIE_BOT.PCIE_LOGIC_OUTS_B0_L_19.PCIE_TRNRD55 always +PCIE_BOT.PCIE_LOGIC_OUTS_B0_R_0.PCIE_PIPETX7DATA12 always +PCIE_BOT.PCIE_LOGIC_OUTS_B0_R_1.PCIE_TRNFCPD2 always +PCIE_BOT.PCIE_LOGIC_OUTS_B0_R_2.PCIE_PIPETX7DATA4 always +PCIE_BOT.PCIE_LOGIC_OUTS_B0_R_3.PCIE_TRNFCPH6 always +PCIE_BOT.PCIE_LOGIC_OUTS_B0_R_4.PCIE_PIPETX5DATA12 always +PCIE_BOT.PCIE_LOGIC_OUTS_B0_R_5.PCIE_MIMTXWDATA20 always +PCIE_BOT.PCIE_LOGIC_OUTS_B0_R_6.PCIE_PIPETX5DATA4 always +PCIE_BOT.PCIE_LOGIC_OUTS_B0_R_7.PCIE_TRNLNKUP always +PCIE_BOT.PCIE_LOGIC_OUTS_B0_R_8.PCIE_PIPETXDEEMPH always +PCIE_BOT.PCIE_LOGIC_OUTS_B0_R_9.PCIE_TRNRBARHIT0 always +PCIE_BOT.PCIE_LOGIC_OUTS_B0_R_10.PCIE_TRNRSRCRDY always +PCIE_BOT.PCIE_LOGIC_OUTS_B0_R_11.PCIE_PIPETX6DATA12 always +PCIE_BOT.PCIE_LOGIC_OUTS_B0_R_12.PCIE_TRNRD124 always +PCIE_BOT.PCIE_LOGIC_OUTS_B0_R_13.PCIE_PIPETX6DATA4 always +PCIE_BOT.PCIE_LOGIC_OUTS_B0_R_14.PCIE_TRNRD116 always +PCIE_BOT.PCIE_LOGIC_OUTS_B0_R_15.PCIE_PIPETX4DATA12 always +PCIE_BOT.PCIE_LOGIC_OUTS_B0_R_16.PCIE_TRNRD110 always +PCIE_BOT.PCIE_LOGIC_OUTS_B0_R_17.PCIE_PIPETX4DATA4 always +PCIE_BOT.PCIE_LOGIC_OUTS_B0_R_18.PCIE_TRNRD103 always +PCIE_BOT.PCIE_LOGIC_OUTS_B0_R_19.PCIE_MIMRXWDATA16 always +PCIE_BOT.PCIE_LOGIC_OUTS_B1_L_0.PCIE_PLSELLNKRATE always +PCIE_BOT.PCIE_LOGIC_OUTS_B1_L_1.PCIE_PLRXPMSTATE1 always +PCIE_BOT.PCIE_LOGIC_OUTS_B1_L_2.PCIE_PIPETX3POWERDOWN0 always +PCIE_BOT.PCIE_LOGIC_OUTS_B1_L_3.PCIE_PIPERX3POLARITY always +PCIE_BOT.PCIE_LOGIC_OUTS_B1_L_4.PCIE_TRNTBUFAV2 always +PCIE_BOT.PCIE_LOGIC_OUTS_B1_L_5.PCIE_TRNRD0 always +PCIE_BOT.PCIE_LOGIC_OUTS_B1_L_6.PCIE_PIPETX1POWERDOWN0 always +PCIE_BOT.PCIE_LOGIC_OUTS_B1_L_7.PCIE_PIPERX1POLARITY always +PCIE_BOT.PCIE_LOGIC_OUTS_B1_L_8.PCIE_TRNRD12 always +PCIE_BOT.PCIE_LOGIC_OUTS_B1_L_9.PCIE_TRNRD16 always +PCIE_BOT.PCIE_LOGIC_OUTS_B1_L_10.PCIE_TRNRD20 always +PCIE_BOT.PCIE_LOGIC_OUTS_B1_L_11.PCIE_TRNRD23 always +PCIE_BOT.PCIE_LOGIC_OUTS_B1_L_12.PCIE_TRNRD28 always +PCIE_BOT.PCIE_LOGIC_OUTS_B1_L_13.PCIE_PIPETX2POWERDOWN0 always +PCIE_BOT.PCIE_LOGIC_OUTS_B1_L_14.PCIE_PIPERX2POLARITY always +PCIE_BOT.PCIE_LOGIC_OUTS_B1_L_15.PCIE_TRNRD39 always +PCIE_BOT.PCIE_LOGIC_OUTS_B1_L_16.PCIE_TRNRD44 always +PCIE_BOT.PCIE_LOGIC_OUTS_B1_L_17.PCIE_PIPETX0POWERDOWN0 always +PCIE_BOT.PCIE_LOGIC_OUTS_B1_L_18.PCIE_PIPERX0POLARITY always +PCIE_BOT.PCIE_LOGIC_OUTS_B1_L_19.PCIE_TRNRD56 always +PCIE_BOT.PCIE_LOGIC_OUTS_B1_R_0.PCIE_MIMTXWDATA40 always +PCIE_BOT.PCIE_LOGIC_OUTS_B1_R_1.PCIE_TRNFCPD3 always +PCIE_BOT.PCIE_LOGIC_OUTS_B1_R_2.PCIE_PIPETX7POWERDOWN0 always +PCIE_BOT.PCIE_LOGIC_OUTS_B1_R_3.PCIE_PIPERX7POLARITY always +PCIE_BOT.PCIE_LOGIC_OUTS_B1_R_4.PCIE_MIMTXWDATA16 always +PCIE_BOT.PCIE_LOGIC_OUTS_B1_R_5.PCIE_MIMTXWDATA18 always +PCIE_BOT.PCIE_LOGIC_OUTS_B1_R_6.PCIE_PIPETX5POWERDOWN0 always +PCIE_BOT.PCIE_LOGIC_OUTS_B1_R_7.PCIE_PIPERX5POLARITY always +PCIE_BOT.PCIE_LOGIC_OUTS_B1_R_8.PCIE_TRNRBARHIT4 always +PCIE_BOT.PCIE_LOGIC_OUTS_B1_R_9.PCIE_TRNRBARHIT1 always +PCIE_BOT.PCIE_LOGIC_OUTS_B1_R_10.PCIE_TRNTDSTRDY0 always +PCIE_BOT.PCIE_LOGIC_OUTS_B1_R_11.PCIE_TRNRREM0 always +PCIE_BOT.PCIE_LOGIC_OUTS_B1_R_12.PCIE_TRNRD125 always +PCIE_BOT.PCIE_LOGIC_OUTS_B1_R_13.PCIE_PIPETX6POWERDOWN0 always +PCIE_BOT.PCIE_LOGIC_OUTS_B1_R_14.PCIE_PIPERX6POLARITY always +PCIE_BOT.PCIE_LOGIC_OUTS_B1_R_15.PCIE_TRNTDSTRDY1 always +PCIE_BOT.PCIE_LOGIC_OUTS_B1_R_16.PCIE_TRNRD111 always +PCIE_BOT.PCIE_LOGIC_OUTS_B1_R_17.PCIE_PIPETX4POWERDOWN0 always +PCIE_BOT.PCIE_LOGIC_OUTS_B1_R_18.PCIE_PIPERX4POLARITY always +PCIE_BOT.PCIE_LOGIC_OUTS_B1_R_19.PCIE_TRNRD99 always +PCIE_BOT.PCIE_LOGIC_OUTS_B2_L_0.PCIE_PIPETX3DATA14 always +PCIE_BOT.PCIE_LOGIC_OUTS_B2_L_1.PCIE_PLLINKUPCFGCAP always +PCIE_BOT.PCIE_LOGIC_OUTS_B2_L_2.PCIE_PIPETX3DATA6 always +PCIE_BOT.PCIE_LOGIC_OUTS_B2_L_3.PCIE_TRNTERRDROP always +PCIE_BOT.PCIE_LOGIC_OUTS_B2_L_4.PCIE_PIPETX1DATA14 always +PCIE_BOT.PCIE_LOGIC_OUTS_B2_L_5.PCIE_TRNRD1 always +PCIE_BOT.PCIE_LOGIC_OUTS_B2_L_6.PCIE_PIPETX1DATA6 always +PCIE_BOT.PCIE_LOGIC_OUTS_B2_L_7.PCIE_TRNRD8 always +PCIE_BOT.PCIE_LOGIC_OUTS_B2_L_8.PCIE_TRNRD13 always +PCIE_BOT.PCIE_LOGIC_OUTS_B2_L_9.PCIE_TRNRD17 always +PCIE_BOT.PCIE_LOGIC_OUTS_B2_L_10.PCIE_TRNRD21 always +PCIE_BOT.PCIE_LOGIC_OUTS_B2_L_11.PCIE_PIPETX2DATA14 always +PCIE_BOT.PCIE_LOGIC_OUTS_B2_L_12.PCIE_TRNRD29 always +PCIE_BOT.PCIE_LOGIC_OUTS_B2_L_13.PCIE_PIPETX2DATA6 always +PCIE_BOT.PCIE_LOGIC_OUTS_B2_L_14.PCIE_TRNRD36 always +PCIE_BOT.PCIE_LOGIC_OUTS_B2_L_15.PCIE_PIPETX0DATA14 always +PCIE_BOT.PCIE_LOGIC_OUTS_B2_L_16.PCIE_TRNRD45 always +PCIE_BOT.PCIE_LOGIC_OUTS_B2_L_17.PCIE_PIPETX0DATA6 always +PCIE_BOT.PCIE_LOGIC_OUTS_B2_L_18.PCIE_TRNRD52 always +PCIE_BOT.PCIE_LOGIC_OUTS_B2_L_19.PCIE_TRNRD57 always +PCIE_BOT.PCIE_LOGIC_OUTS_B2_R_0.PCIE_PIPETX7DATA14 always +PCIE_BOT.PCIE_LOGIC_OUTS_B2_R_1.PCIE_TRNFCPD4 always +PCIE_BOT.PCIE_LOGIC_OUTS_B2_R_2.PCIE_PIPETX7DATA6 always +PCIE_BOT.PCIE_LOGIC_OUTS_B2_R_3.PCIE_MIMTXWADDR11 always +PCIE_BOT.PCIE_LOGIC_OUTS_B2_R_4.PCIE_PIPETX5DATA14 always +PCIE_BOT.PCIE_LOGIC_OUTS_B2_R_5.PCIE_TRNFCPH2 always +PCIE_BOT.PCIE_LOGIC_OUTS_B2_R_6.PCIE_PIPETX5DATA6 always +PCIE_BOT.PCIE_LOGIC_OUTS_B2_R_7.PCIE_TRNFCPH0 always +PCIE_BOT.PCIE_LOGIC_OUTS_B2_R_8.PCIE_TRNRBARHIT5 always +PCIE_BOT.PCIE_LOGIC_OUTS_B2_R_9.PCIE_TRNRBARHIT2 always +PCIE_BOT.PCIE_LOGIC_OUTS_B2_R_10.PCIE_MIMTXWDATA29 always +PCIE_BOT.PCIE_LOGIC_OUTS_B2_R_11.PCIE_PIPETX6DATA14 always +PCIE_BOT.PCIE_LOGIC_OUTS_B2_R_12.PCIE_TRNRD126 always +PCIE_BOT.PCIE_LOGIC_OUTS_B2_R_13.PCIE_PIPETX6DATA6 always +PCIE_BOT.PCIE_LOGIC_OUTS_B2_R_14.PCIE_TRNRD117 always +PCIE_BOT.PCIE_LOGIC_OUTS_B2_R_15.PCIE_PIPETX4DATA14 always +PCIE_BOT.PCIE_LOGIC_OUTS_B2_R_16.PCIE_DBGVECA32 always +PCIE_BOT.PCIE_LOGIC_OUTS_B2_R_17.PCIE_PIPETX4DATA6 always +PCIE_BOT.PCIE_LOGIC_OUTS_B2_R_18.PCIE_TRNRD104 always +PCIE_BOT.PCIE_LOGIC_OUTS_B2_R_19.PCIE_MIMRXWDATA18 always +PCIE_BOT.PCIE_LOGIC_OUTS_B3_L_0.PCIE_PLSELLNKWIDTH0 always +PCIE_BOT.PCIE_LOGIC_OUTS_B3_L_1.PCIE_PLLINKGEN2CAP always +PCIE_BOT.PCIE_LOGIC_OUTS_B3_L_2.PCIE_PIPETX3ELECIDLE always +PCIE_BOT.PCIE_LOGIC_OUTS_B3_L_3.PCIE_PIPETX3COMPLIANCE always +PCIE_BOT.PCIE_LOGIC_OUTS_B3_L_4.PCIE_TRNTBUFAV3 always +PCIE_BOT.PCIE_LOGIC_OUTS_B3_L_5.PCIE_TRNRD2 always +PCIE_BOT.PCIE_LOGIC_OUTS_B3_L_6.PCIE_PIPETX1ELECIDLE always +PCIE_BOT.PCIE_LOGIC_OUTS_B3_L_7.PCIE_PIPETX1COMPLIANCE always +PCIE_BOT.PCIE_LOGIC_OUTS_B3_L_8.PCIE_TRNRD14 always +PCIE_BOT.PCIE_LOGIC_OUTS_B3_L_9.PCIE_TRNRD18 always +PCIE_BOT.PCIE_LOGIC_OUTS_B3_L_10.PCIE_TRNRD22 always +PCIE_BOT.PCIE_LOGIC_OUTS_B3_L_11.PCIE_TRNRD24 always +PCIE_BOT.PCIE_LOGIC_OUTS_B3_L_12.PCIE_TRNRD30 always +PCIE_BOT.PCIE_LOGIC_OUTS_B3_L_13.PCIE_PIPETX2ELECIDLE always +PCIE_BOT.PCIE_LOGIC_OUTS_B3_L_14.PCIE_PIPETX2COMPLIANCE always +PCIE_BOT.PCIE_LOGIC_OUTS_B3_L_15.PCIE_TRNRD40 always +PCIE_BOT.PCIE_LOGIC_OUTS_B3_L_16.PCIE_TRNRD46 always +PCIE_BOT.PCIE_LOGIC_OUTS_B3_L_17.PCIE_PIPETX0ELECIDLE always +PCIE_BOT.PCIE_LOGIC_OUTS_B3_L_18.PCIE_PIPETX0COMPLIANCE always +PCIE_BOT.PCIE_LOGIC_OUTS_B3_L_19.PCIE_TRNRD58 always +PCIE_BOT.PCIE_LOGIC_OUTS_B3_R_0.PCIE_TRNTDSTRDY2 always +PCIE_BOT.PCIE_LOGIC_OUTS_B3_R_1.PCIE_TRNFCPD5 always +PCIE_BOT.PCIE_LOGIC_OUTS_B3_R_2.PCIE_PIPETX7ELECIDLE always +PCIE_BOT.PCIE_LOGIC_OUTS_B3_R_3.PCIE_PIPETX7COMPLIANCE always +PCIE_BOT.PCIE_LOGIC_OUTS_B3_R_4.PCIE_MIMTXRADDR9 always +PCIE_BOT.PCIE_LOGIC_OUTS_B3_R_5.PCIE_TRNFCPH3 always +PCIE_BOT.PCIE_LOGIC_OUTS_B3_R_6.PCIE_PIPETX5ELECIDLE always +PCIE_BOT.PCIE_LOGIC_OUTS_B3_R_7.PCIE_PIPETX5COMPLIANCE always +PCIE_BOT.PCIE_LOGIC_OUTS_B3_R_8.PCIE_TRNRBARHIT6 always +PCIE_BOT.PCIE_LOGIC_OUTS_B3_R_9.PCIE_TRNRBARHIT3 always +PCIE_BOT.PCIE_LOGIC_OUTS_B3_R_10.PCIE_TRNRSRCDSC always +PCIE_BOT.PCIE_LOGIC_OUTS_B3_R_11.PCIE_TRNRREM1 always +PCIE_BOT.PCIE_LOGIC_OUTS_B3_R_12.PCIE_TRNRD127 always +PCIE_BOT.PCIE_LOGIC_OUTS_B3_R_13.PCIE_PIPETX6ELECIDLE always +PCIE_BOT.PCIE_LOGIC_OUTS_B3_R_14.PCIE_PIPETX6COMPLIANCE always +PCIE_BOT.PCIE_LOGIC_OUTS_B3_R_15.PCIE_TRNRD112 always +PCIE_BOT.PCIE_LOGIC_OUTS_B3_R_16.PCIE_LL2LINKSTATUS2 always +PCIE_BOT.PCIE_LOGIC_OUTS_B3_R_17.PCIE_PIPETX4ELECIDLE always +PCIE_BOT.PCIE_LOGIC_OUTS_B3_R_18.PCIE_PIPETX4COMPLIANCE always +PCIE_BOT.PCIE_LOGIC_OUTS_B3_R_19.PCIE_TRNRD100 always +PCIE_BOT.PCIE_LOGIC_OUTS_B4_L_0.PCIE_PIPETX3DATA13 always +PCIE_BOT.PCIE_LOGIC_OUTS_B4_L_1.PCIE_TRNFCPD9 always +PCIE_BOT.PCIE_LOGIC_OUTS_B4_L_2.PCIE_PIPETX3DATA5 always +PCIE_BOT.PCIE_LOGIC_OUTS_B4_L_3.PCIE_TRNTBUFAV0 always +PCIE_BOT.PCIE_LOGIC_OUTS_B4_L_4.PCIE_PIPETX1DATA13 always +PCIE_BOT.PCIE_LOGIC_OUTS_B4_L_5.PCIE_TRNFCNPD5 always +PCIE_BOT.PCIE_LOGIC_OUTS_B4_L_6.PCIE_PIPETX1DATA5 always +PCIE_BOT.PCIE_LOGIC_OUTS_B4_L_7.PCIE_TRNRD9 always +PCIE_BOT.PCIE_LOGIC_OUTS_B4_L_8.PCIE_TRNFCCPLH5 always +PCIE_BOT.PCIE_LOGIC_OUTS_B4_L_9.PCIE_TRNFCCPLD1 always +PCIE_BOT.PCIE_LOGIC_OUTS_B4_L_10.PCIE_TRNFCCPLD5 always +PCIE_BOT.PCIE_LOGIC_OUTS_B4_L_11.PCIE_PIPETX2DATA13 always +PCIE_BOT.PCIE_LOGIC_OUTS_B4_L_12.PCIE_TRNRDLLPDATA0 always +PCIE_BOT.PCIE_LOGIC_OUTS_B4_L_13.PCIE_PIPETX2DATA5 always +PCIE_BOT.PCIE_LOGIC_OUTS_B4_L_14.PCIE_TRNRD37 always +PCIE_BOT.PCIE_LOGIC_OUTS_B4_L_15.PCIE_PIPETX0DATA13 always +PCIE_BOT.PCIE_LOGIC_OUTS_B4_L_16.PCIE_TRNRDLLPDATA16 always +PCIE_BOT.PCIE_LOGIC_OUTS_B4_L_17.PCIE_PIPETX0DATA5 always +PCIE_BOT.PCIE_LOGIC_OUTS_B4_L_18.PCIE_TRNRD53 always +PCIE_BOT.PCIE_LOGIC_OUTS_B4_L_19.PCIE_TRNRDLLPDATA28 always +PCIE_BOT.PCIE_LOGIC_OUTS_B4_R_0.PCIE_PIPETX7DATA13 always +PCIE_BOT.PCIE_LOGIC_OUTS_B4_R_1.PCIE_TL2ERRHDR18 always +PCIE_BOT.PCIE_LOGIC_OUTS_B4_R_2.PCIE_PIPETX7DATA5 always +PCIE_BOT.PCIE_LOGIC_OUTS_B4_R_3.PCIE_TRNFCPH7 always +PCIE_BOT.PCIE_LOGIC_OUTS_B4_R_4.PCIE_PIPETX5DATA13 always +PCIE_BOT.PCIE_LOGIC_OUTS_B4_R_5.PCIE_TRNFCPH4 always +PCIE_BOT.PCIE_LOGIC_OUTS_B4_R_6.PCIE_PIPETX5DATA5 always +PCIE_BOT.PCIE_LOGIC_OUTS_B4_R_7.PCIE_MIMTXWDATA33 always +PCIE_BOT.PCIE_LOGIC_OUTS_B4_R_8.PCIE_MIMTXWDATA19 always +PCIE_BOT.PCIE_LOGIC_OUTS_B4_R_9.PCIE_MIMTXWDATA5 always +PCIE_BOT.PCIE_LOGIC_OUTS_B4_R_10.PCIE_TRNRECRCERR always +PCIE_BOT.PCIE_LOGIC_OUTS_B4_R_11.PCIE_PIPETX6DATA13 always +PCIE_BOT.PCIE_LOGIC_OUTS_B4_R_12.PCIE_LL2REPLAYROERR always +PCIE_BOT.PCIE_LOGIC_OUTS_B4_R_13.PCIE_PIPETX6DATA5 always +PCIE_BOT.PCIE_LOGIC_OUTS_B4_R_14.PCIE_TRNRD118 always +PCIE_BOT.PCIE_LOGIC_OUTS_B4_R_15.PCIE_PIPETX4DATA13 always +PCIE_BOT.PCIE_LOGIC_OUTS_B4_R_16.PCIE_LL2LINKSTATUS3 always +PCIE_BOT.PCIE_LOGIC_OUTS_B4_R_17.PCIE_PIPETX4DATA5 always +PCIE_BOT.PCIE_LOGIC_OUTS_B4_R_18.PCIE_MIMRXWDATA14 always +PCIE_BOT.PCIE_LOGIC_OUTS_B4_R_19.PCIE_TRNRD101 always +PCIE_BOT.PCIE_LOGIC_OUTS_B5_L_0.PCIE_PLSELLNKWIDTH1 always +PCIE_BOT.PCIE_LOGIC_OUTS_B5_L_1.PCIE_TRNFCPD10 always +PCIE_BOT.PCIE_LOGIC_OUTS_B5_L_2.PCIE_PLLINKPARTNERGEN2SUPPORTED always +PCIE_BOT.PCIE_LOGIC_OUTS_B5_L_3.PCIE_TRNTBUFAV1 always +PCIE_BOT.PCIE_LOGIC_OUTS_B5_L_4.PCIE_TRNTBUFAV4 always +PCIE_BOT.PCIE_LOGIC_OUTS_B5_L_5.PCIE_TRNFCNPD6 always +PCIE_BOT.PCIE_LOGIC_OUTS_B5_L_6.PCIE_TRNRD3 always +PCIE_BOT.PCIE_LOGIC_OUTS_B5_L_7.PCIE_TRNRD10 always +PCIE_BOT.PCIE_LOGIC_OUTS_B5_L_8.PCIE_TRNFCCPLH6 always +PCIE_BOT.PCIE_LOGIC_OUTS_B5_L_9.PCIE_TRNFCCPLD2 always +PCIE_BOT.PCIE_LOGIC_OUTS_B5_L_10.PCIE_TRNFCCPLD6 always +PCIE_BOT.PCIE_LOGIC_OUTS_B5_L_11.PCIE_TRNRD25 always +PCIE_BOT.PCIE_LOGIC_OUTS_B5_L_12.PCIE_TRNRDLLPDATA1 always +PCIE_BOT.PCIE_LOGIC_OUTS_B5_L_13.PCIE_TRNRD31 always +PCIE_BOT.PCIE_LOGIC_OUTS_B5_L_14.PCIE_TRNRD38 always +PCIE_BOT.PCIE_LOGIC_OUTS_B5_L_15.PCIE_TRNRD41 always +PCIE_BOT.PCIE_LOGIC_OUTS_B5_L_16.PCIE_TRNRDLLPDATA17 always +PCIE_BOT.PCIE_LOGIC_OUTS_B5_L_17.PCIE_TRNRD47 always +PCIE_BOT.PCIE_LOGIC_OUTS_B5_L_18.PCIE_TRNRD54 always +PCIE_BOT.PCIE_LOGIC_OUTS_B5_L_19.PCIE_TRNRDLLPDATA29 always +PCIE_BOT.PCIE_LOGIC_OUTS_B5_R_0.PCIE_TRNFCPD6 always +PCIE_BOT.PCIE_LOGIC_OUTS_B5_R_1.PCIE_MIMTXWDATA62 always +PCIE_BOT.PCIE_LOGIC_OUTS_B5_R_2.PCIE_MIMTXWDATA68 always +PCIE_BOT.PCIE_LOGIC_OUTS_B5_R_3.PCIE_TRNFCPD0 always +PCIE_BOT.PCIE_LOGIC_OUTS_B5_R_4.PCIE_TRNFCPH5 always +PCIE_BOT.PCIE_LOGIC_OUTS_B5_R_5.PCIE_MIMTXWDATA4 always +PCIE_BOT.PCIE_LOGIC_OUTS_B5_R_6.PCIE_MIMTXWDATA26 always +PCIE_BOT.PCIE_LOGIC_OUTS_B5_R_7.PCIE_MIMTXWDATA17 always +PCIE_BOT.PCIE_LOGIC_OUTS_B5_R_8.PCIE_MIMTXWDATA21 always +PCIE_BOT.PCIE_LOGIC_OUTS_B5_R_9.PCIE_MIMTXWDATA13 always +PCIE_BOT.PCIE_LOGIC_OUTS_B5_R_10.PCIE_TRNRERRFWD always +PCIE_BOT.PCIE_LOGIC_OUTS_B5_R_11.PCIE_TRNRSOF always +PCIE_BOT.PCIE_LOGIC_OUTS_B5_R_12.PCIE_LL2REPLAYTOERR always +PCIE_BOT.PCIE_LOGIC_OUTS_B5_R_13.PCIE_TRNRD120 always +PCIE_BOT.PCIE_LOGIC_OUTS_B5_R_14.PCIE_TRNRD119 always +PCIE_BOT.PCIE_LOGIC_OUTS_B5_R_15.PCIE_TRNRD113 always +PCIE_BOT.PCIE_LOGIC_OUTS_B5_R_16.PCIE_MIMRXWDATA54 always +PCIE_BOT.PCIE_LOGIC_OUTS_B5_R_17.PCIE_TRNRD106 always +PCIE_BOT.PCIE_LOGIC_OUTS_B5_R_18.PCIE_TRNRD105 always +PCIE_BOT.PCIE_LOGIC_OUTS_B5_R_19.PCIE_MIMRXWDATA57 always +PCIE_BOT.PCIE_LOGIC_OUTS_B6_L_0.PCIE_PIPETX3DATA15 always +PCIE_BOT.PCIE_LOGIC_OUTS_B6_L_1.PCIE_TRNFCPD11 always +PCIE_BOT.PCIE_LOGIC_OUTS_B6_L_2.PCIE_PIPETX3DATA7 always +PCIE_BOT.PCIE_LOGIC_OUTS_B6_L_3.PCIE_TRNFCNPH5 always +PCIE_BOT.PCIE_LOGIC_OUTS_B6_L_4.PCIE_PIPETX1DATA15 always +PCIE_BOT.PCIE_LOGIC_OUTS_B6_L_5.PCIE_TRNFCNPD7 always +PCIE_BOT.PCIE_LOGIC_OUTS_B6_L_6.PCIE_PIPETX1DATA7 always +PCIE_BOT.PCIE_LOGIC_OUTS_B6_L_7.PCIE_TRNFCCPLH1 always +PCIE_BOT.PCIE_LOGIC_OUTS_B6_L_8.PCIE_TRNFCCPLH7 always +PCIE_BOT.PCIE_LOGIC_OUTS_B6_L_9.PCIE_TRNFCCPLD3 always +PCIE_BOT.PCIE_LOGIC_OUTS_B6_L_10.PCIE_TRNFCCPLD7 always +PCIE_BOT.PCIE_LOGIC_OUTS_B6_L_11.PCIE_PIPETX2DATA15 always +PCIE_BOT.PCIE_LOGIC_OUTS_B6_L_12.PCIE_TRNRDLLPDATA2 always +PCIE_BOT.PCIE_LOGIC_OUTS_B6_L_13.PCIE_PIPETX2DATA7 always +PCIE_BOT.PCIE_LOGIC_OUTS_B6_L_14.PCIE_TRNRDLLPDATA8 always +PCIE_BOT.PCIE_LOGIC_OUTS_B6_L_15.PCIE_PIPETX0DATA15 always +PCIE_BOT.PCIE_LOGIC_OUTS_B6_L_16.PCIE_TRNRDLLPDATA18 always +PCIE_BOT.PCIE_LOGIC_OUTS_B6_L_17.PCIE_PIPETX0DATA7 always +PCIE_BOT.PCIE_LOGIC_OUTS_B6_L_18.PCIE_TRNRDLLPDATA24 always +PCIE_BOT.PCIE_LOGIC_OUTS_B6_L_19.PCIE_TRNRDLLPDATA30 always +PCIE_BOT.PCIE_LOGIC_OUTS_B6_R_0.PCIE_PIPETX7DATA15 always +PCIE_BOT.PCIE_LOGIC_OUTS_B6_R_1.PCIE_MIMTXWADDR1 always +PCIE_BOT.PCIE_LOGIC_OUTS_B6_R_2.PCIE_PIPETX7DATA7 always +PCIE_BOT.PCIE_LOGIC_OUTS_B6_R_3.PCIE_MIMTXWDATA61 always +PCIE_BOT.PCIE_LOGIC_OUTS_B6_R_4.PCIE_PIPETX5DATA15 always +PCIE_BOT.PCIE_LOGIC_OUTS_B6_R_5.PCIE_DBGVECB18 always +PCIE_BOT.PCIE_LOGIC_OUTS_B6_R_6.PCIE_PIPETX5DATA7 always +PCIE_BOT.PCIE_LOGIC_OUTS_B6_R_7.PCIE_TRNFCPH1 always +PCIE_BOT.PCIE_LOGIC_OUTS_B6_R_8.PCIE_TRNRBARHIT7 always +PCIE_BOT.PCIE_LOGIC_OUTS_B6_R_9.PCIE_TL2ERRHDR10 always +PCIE_BOT.PCIE_LOGIC_OUTS_B6_R_10.PCIE_TL2ERRHDR6 always +PCIE_BOT.PCIE_LOGIC_OUTS_B6_R_11.PCIE_PIPETX6DATA15 always +PCIE_BOT.PCIE_LOGIC_OUTS_B6_R_12.PCIE_TL2ERRHDR0 always +PCIE_BOT.PCIE_LOGIC_OUTS_B6_R_13.PCIE_PIPETX6DATA7 always +PCIE_BOT.PCIE_LOGIC_OUTS_B6_R_14.PCIE_TL2ASPMSUSPENDREQ always +PCIE_BOT.PCIE_LOGIC_OUTS_B6_R_15.PCIE_PIPETX4DATA15 always +PCIE_BOT.PCIE_LOGIC_OUTS_B6_R_16.PCIE_MIMRXWDATA56 always +PCIE_BOT.PCIE_LOGIC_OUTS_B6_R_17.PCIE_PIPETX4DATA7 always +PCIE_BOT.PCIE_LOGIC_OUTS_B6_R_18.PCIE_MIMRXWDATA60 always +PCIE_BOT.PCIE_LOGIC_OUTS_B6_R_19.PCIE_TRNRD102 always +PCIE_BOT.PCIE_LOGIC_OUTS_B7_L_0.PCIE_PLLTSSMSTATE0 always +PCIE_BOT.PCIE_LOGIC_OUTS_B7_L_1.PCIE_TRNFCNPH0 always +PCIE_BOT.PCIE_LOGIC_OUTS_B7_L_2.PCIE_PIPETX3POWERDOWN1 always +PCIE_BOT.PCIE_LOGIC_OUTS_B7_L_3.PCIE_TRNFCNPH6 always +PCIE_BOT.PCIE_LOGIC_OUTS_B7_L_4.PCIE_TRNTBUFAV5 always +PCIE_BOT.PCIE_LOGIC_OUTS_B7_L_5.PCIE_TRNFCNPD8 always +PCIE_BOT.PCIE_LOGIC_OUTS_B7_L_6.PCIE_PIPETX1POWERDOWN1 always +PCIE_BOT.PCIE_LOGIC_OUTS_B7_L_7.PCIE_TRNFCCPLH2 always +PCIE_BOT.PCIE_LOGIC_OUTS_B7_L_8.PCIE_TRNFCCPLD0 always +PCIE_BOT.PCIE_LOGIC_OUTS_B7_L_9.PCIE_TRNFCCPLD4 always +PCIE_BOT.PCIE_LOGIC_OUTS_B7_L_10.PCIE_TRNFCCPLD8 always +PCIE_BOT.PCIE_LOGIC_OUTS_B7_L_11.PCIE_TRNRD26 always +PCIE_BOT.PCIE_LOGIC_OUTS_B7_L_12.PCIE_TRNRDLLPDATA3 always +PCIE_BOT.PCIE_LOGIC_OUTS_B7_L_13.PCIE_PIPETX2POWERDOWN1 always +PCIE_BOT.PCIE_LOGIC_OUTS_B7_L_14.PCIE_TRNRDLLPDATA9 always +PCIE_BOT.PCIE_LOGIC_OUTS_B7_L_15.PCIE_TRNRD42 always +PCIE_BOT.PCIE_LOGIC_OUTS_B7_L_16.PCIE_TRNRDLLPDATA19 always +PCIE_BOT.PCIE_LOGIC_OUTS_B7_L_17.PCIE_PIPETX0POWERDOWN1 always +PCIE_BOT.PCIE_LOGIC_OUTS_B7_L_18.PCIE_TRNRDLLPDATA25 always +PCIE_BOT.PCIE_LOGIC_OUTS_B7_L_19.PCIE_TRNRDLLPDATA31 always +PCIE_BOT.PCIE_LOGIC_OUTS_B7_R_0.PCIE_TRNFCPD7 always +PCIE_BOT.PCIE_LOGIC_OUTS_B7_R_1.PCIE_MIMTXWDATA50 always +PCIE_BOT.PCIE_LOGIC_OUTS_B7_R_2.PCIE_PIPETX7POWERDOWN1 always +PCIE_BOT.PCIE_LOGIC_OUTS_B7_R_3.PCIE_DBGVECB26 always +PCIE_BOT.PCIE_LOGIC_OUTS_B7_R_4.PCIE_DBGVECB22 always +PCIE_BOT.PCIE_LOGIC_OUTS_B7_R_5.PCIE_DBGVECB19 always +PCIE_BOT.PCIE_LOGIC_OUTS_B7_R_6.PCIE_PIPETX5POWERDOWN1 always +PCIE_BOT.PCIE_LOGIC_OUTS_B7_R_7.PCIE_MIMTXWDATA3 always +PCIE_BOT.PCIE_LOGIC_OUTS_B7_R_8.PCIE_TL2ERRHDR14 always +PCIE_BOT.PCIE_LOGIC_OUTS_B7_R_9.PCIE_MIMTXWDATA31 always +PCIE_BOT.PCIE_LOGIC_OUTS_B7_R_10.PCIE_TL2ERRHDR7 always +PCIE_BOT.PCIE_LOGIC_OUTS_B7_R_11.PCIE_TRNREOF always +PCIE_BOT.PCIE_LOGIC_OUTS_B7_R_12.PCIE_TL2ERRHDR1 always +PCIE_BOT.PCIE_LOGIC_OUTS_B7_R_13.PCIE_PIPETX6POWERDOWN1 always +PCIE_BOT.PCIE_LOGIC_OUTS_B7_R_14.PCIE_TL2ASPMSUSPENDCREDITCHECKOK always +PCIE_BOT.PCIE_LOGIC_OUTS_B7_R_15.PCIE_TRNRD114 always +PCIE_BOT.PCIE_LOGIC_OUTS_B7_R_16.PCIE_MIMRXWADDR3 always +PCIE_BOT.PCIE_LOGIC_OUTS_B7_R_17.PCIE_PIPETX4POWERDOWN1 always +PCIE_BOT.PCIE_LOGIC_OUTS_B7_R_18.PCIE_DBGVECA25 always +PCIE_BOT.PCIE_LOGIC_OUTS_B7_R_19.PCIE_PL2RXELECIDLE always +PCIE_BOT.PCIE_LOGIC_OUTS_B8_L_0.PCIE_PLLTSSMSTATE1 always +PCIE_BOT.PCIE_LOGIC_OUTS_B8_L_1.PCIE_TL2ERRHDR19 always +PCIE_BOT.PCIE_LOGIC_OUTS_B8_L_2.PCIE_PLINITIALLINKWIDTH0 always +PCIE_BOT.PCIE_LOGIC_OUTS_B8_L_3.PCIE_TRNFCNPH7 always +PCIE_BOT.PCIE_LOGIC_OUTS_B8_L_4.PCIE_TRNFCNPD1 always +PCIE_BOT.PCIE_LOGIC_OUTS_B8_L_5.PCIE_TL2ERRHDR33 always +PCIE_BOT.PCIE_LOGIC_OUTS_B8_L_6.PCIE_TRNRD4 always +PCIE_BOT.PCIE_LOGIC_OUTS_B8_L_7.PCIE_TRNFCCPLH3 always +PCIE_BOT.PCIE_LOGIC_OUTS_B8_L_8.PCIE_TL2ERRHDR43 always +PCIE_BOT.PCIE_LOGIC_OUTS_B8_L_9.PCIE_TL2ERRHDR47 always +PCIE_BOT.PCIE_LOGIC_OUTS_B8_L_10.PCIE_TL2ERRHDR51 always +PCIE_BOT.PCIE_LOGIC_OUTS_B8_L_11.PCIE_TRNFCCPLD9 always +PCIE_BOT.PCIE_LOGIC_OUTS_B8_L_12.PCIE_TL2ERRHDR59 always +PCIE_BOT.PCIE_LOGIC_OUTS_B8_L_13.PCIE_TRNRD32 always +PCIE_BOT.PCIE_LOGIC_OUTS_B8_L_14.PCIE_TRNRDLLPDATA10 always +PCIE_BOT.PCIE_LOGIC_OUTS_B8_L_15.PCIE_TRNRDLLPDATA12 always +PCIE_BOT.PCIE_LOGIC_OUTS_B8_L_16.PCIE_CFGMSGRECEIVEDERRFATAL always +PCIE_BOT.PCIE_LOGIC_OUTS_B8_L_17.PCIE_TRNRD48 always +PCIE_BOT.PCIE_LOGIC_OUTS_B8_L_18.PCIE_TRNRDLLPDATA26 always +PCIE_BOT.PCIE_LOGIC_OUTS_B8_L_19.PCIE_CFGMSGRECEIVEDSETSLOTPOWERLIMIT always +PCIE_BOT.PCIE_LOGIC_OUTS_B8_R_0.PCIE_TRNFCPD8 always +PCIE_BOT.PCIE_LOGIC_OUTS_B8_R_1.PCIE_MIMTXWDATA44 always +PCIE_BOT.PCIE_LOGIC_OUTS_B8_R_2.PCIE_TRNFCPD1 always +PCIE_BOT.PCIE_LOGIC_OUTS_B8_R_3.PCIE_DBGVECB27 always +PCIE_BOT.PCIE_LOGIC_OUTS_B8_R_4.PCIE_DBGVECB23 always +PCIE_BOT.PCIE_LOGIC_OUTS_B8_R_5.PCIE_MIMTXRADDR11 always +PCIE_BOT.PCIE_LOGIC_OUTS_B8_R_6.PCIE_MIMTXREN always +PCIE_BOT.PCIE_LOGIC_OUTS_B8_R_7.PCIE_MIMTXRADDR12 always +PCIE_BOT.PCIE_LOGIC_OUTS_B8_R_8.PCIE_TL2ERRHDR15 always +PCIE_BOT.PCIE_LOGIC_OUTS_B8_R_9.PCIE_MIMTXRADDR10 always +PCIE_BOT.PCIE_LOGIC_OUTS_B8_R_10.PCIE_TL2ERRHDR8 always +PCIE_BOT.PCIE_LOGIC_OUTS_B8_R_11.PCIE_TL2ERRHDR2 always +PCIE_BOT.PCIE_LOGIC_OUTS_B8_R_12.PCIE_CFGMGMTDO6 always +PCIE_BOT.PCIE_LOGIC_OUTS_B8_R_13.PCIE_TRNRD121 always +PCIE_BOT.PCIE_LOGIC_OUTS_B8_R_14.PCIE_PL2LINKUP always +PCIE_BOT.PCIE_LOGIC_OUTS_B8_R_15.PCIE_TRNRD115 always +PCIE_BOT.PCIE_LOGIC_OUTS_B8_R_16.PCIE_MIMRXWADDR8 always +PCIE_BOT.PCIE_LOGIC_OUTS_B8_R_17.PCIE_TRNRD107 always +PCIE_BOT.PCIE_LOGIC_OUTS_B8_R_18.PCIE_DBGVECA26 always +PCIE_BOT.PCIE_LOGIC_OUTS_B8_R_19.PCIE_MIMRXRADDR5 always +PCIE_BOT.PCIE_LOGIC_OUTS_B9_L_0.PCIE_PLLTSSMSTATE2 always +PCIE_BOT.PCIE_LOGIC_OUTS_B9_L_1.PCIE_PIPETX3DATA8 always +PCIE_BOT.PCIE_LOGIC_OUTS_B9_L_2.PCIE_PLINITIALLINKWIDTH1 always +PCIE_BOT.PCIE_LOGIC_OUTS_B9_L_3.PCIE_PIPETX3DATA0 always +PCIE_BOT.PCIE_LOGIC_OUTS_B9_L_4.PCIE_TRNFCNPD2 always +PCIE_BOT.PCIE_LOGIC_OUTS_B9_L_5.PCIE_PIPETX1DATA8 always +PCIE_BOT.PCIE_LOGIC_OUTS_B9_L_6.PCIE_TRNRD5 always +PCIE_BOT.PCIE_LOGIC_OUTS_B9_L_7.PCIE_PIPETX1DATA0 always +PCIE_BOT.PCIE_LOGIC_OUTS_B9_L_8.PCIE_TL2ERRHDR44 always +PCIE_BOT.PCIE_LOGIC_OUTS_B9_L_9.PCIE_TL2ERRHDR48 always +PCIE_BOT.PCIE_LOGIC_OUTS_B9_L_10.PCIE_TL2ERRHDR52 always +PCIE_BOT.PCIE_LOGIC_OUTS_B9_L_11.PCIE_TRNFCCPLD10 always +PCIE_BOT.PCIE_LOGIC_OUTS_B9_L_12.PCIE_PIPETX2DATA8 always +PCIE_BOT.PCIE_LOGIC_OUTS_B9_L_13.PCIE_TRNRD33 always +PCIE_BOT.PCIE_LOGIC_OUTS_B9_L_14.PCIE_PIPETX2DATA0 always +PCIE_BOT.PCIE_LOGIC_OUTS_B9_L_15.PCIE_TRNRDLLPDATA13 always +PCIE_BOT.PCIE_LOGIC_OUTS_B9_L_16.PCIE_PIPETX0DATA8 always +PCIE_BOT.PCIE_LOGIC_OUTS_B9_L_17.PCIE_TRNRD49 always +PCIE_BOT.PCIE_LOGIC_OUTS_B9_L_18.PCIE_PIPETX0DATA0 always +PCIE_BOT.PCIE_LOGIC_OUTS_B9_L_19.PCIE_CFGMSGRECEIVEDUNLOCK always +PCIE_BOT.PCIE_LOGIC_OUTS_B9_R_0.PCIE_MIMTXWDATA37 always +PCIE_BOT.PCIE_LOGIC_OUTS_B9_R_1.PCIE_PIPETX7DATA8 always +PCIE_BOT.PCIE_LOGIC_OUTS_B9_R_3.PCIE_PIPETX7DATA0 always +PCIE_BOT.PCIE_LOGIC_OUTS_B9_R_4.PCIE_MIMTXWDATA57 always +PCIE_BOT.PCIE_LOGIC_OUTS_B9_R_5.PCIE_PIPETX5DATA8 always +PCIE_BOT.PCIE_LOGIC_OUTS_B9_R_6.PCIE_DBGVECB16 always +PCIE_BOT.PCIE_LOGIC_OUTS_B9_R_7.PCIE_PIPETX5DATA0 always +PCIE_BOT.PCIE_LOGIC_OUTS_B9_R_8.PCIE_TL2ERRHDR16 always +PCIE_BOT.PCIE_LOGIC_OUTS_B9_R_9.PCIE_TL2ERRHDR11 always +PCIE_BOT.PCIE_LOGIC_OUTS_B9_R_10.PCIE_TL2ERRHDR9 always +PCIE_BOT.PCIE_LOGIC_OUTS_B9_R_11.PCIE_PIPETXRESET always +PCIE_BOT.PCIE_LOGIC_OUTS_B9_R_12.PCIE_PIPETX6DATA8 always +PCIE_BOT.PCIE_LOGIC_OUTS_B9_R_13.PCIE_TRNRD122 always +PCIE_BOT.PCIE_LOGIC_OUTS_B9_R_14.PCIE_PIPETX6DATA0 always +PCIE_BOT.PCIE_LOGIC_OUTS_B9_R_15.PCIE_MIMRXWDATA37 always +PCIE_BOT.PCIE_LOGIC_OUTS_B9_R_16.PCIE_PIPETX4DATA8 always +PCIE_BOT.PCIE_LOGIC_OUTS_B9_R_17.PCIE_TRNRD108 always +PCIE_BOT.PCIE_LOGIC_OUTS_B9_R_18.PCIE_PIPETX4DATA0 always +PCIE_BOT.PCIE_LOGIC_OUTS_B9_R_19.PCIE_MIMRXRADDR6 always +PCIE_BOT.PCIE_LOGIC_OUTS_B10_L_0.PCIE_PLLTSSMSTATE3 always +PCIE_BOT.PCIE_LOGIC_OUTS_B10_L_1.PCIE_TL2ERRHDR20 always +PCIE_BOT.PCIE_LOGIC_OUTS_B10_L_2.PCIE_PLINITIALLINKWIDTH2 always +PCIE_BOT.PCIE_LOGIC_OUTS_B10_L_3.PCIE_TRNFCNPD0 always +PCIE_BOT.PCIE_LOGIC_OUTS_B10_L_4.PCIE_TRNFCNPD3 always +PCIE_BOT.PCIE_LOGIC_OUTS_B10_L_5.PCIE_TL2ERRHDR34 always +PCIE_BOT.PCIE_LOGIC_OUTS_B10_L_6.PCIE_TRNRD6 always +PCIE_BOT.PCIE_LOGIC_OUTS_B10_L_7.PCIE_TRNFCCPLH4 always +PCIE_BOT.PCIE_LOGIC_OUTS_B10_L_8.PCIE_TL2ERRHDR45 always +PCIE_BOT.PCIE_LOGIC_OUTS_B10_L_9.PCIE_TL2ERRHDR49 always +PCIE_BOT.PCIE_LOGIC_OUTS_B10_L_10.PCIE_TL2ERRHDR53 always +PCIE_BOT.PCIE_LOGIC_OUTS_B10_L_11.PCIE_TRNFCCPLD11 always +PCIE_BOT.PCIE_LOGIC_OUTS_B10_L_12.PCIE_TL2ERRHDR60 always +PCIE_BOT.PCIE_LOGIC_OUTS_B10_L_13.PCIE_TRNRD34 always +PCIE_BOT.PCIE_LOGIC_OUTS_B10_L_14.PCIE_TRNRDLLPDATA11 always +PCIE_BOT.PCIE_LOGIC_OUTS_B10_L_15.PCIE_TRNRDLLPDATA14 always +PCIE_BOT.PCIE_LOGIC_OUTS_B10_L_16.PCIE_CFGMSGRECEIVEDASSERTINTA always +PCIE_BOT.PCIE_LOGIC_OUTS_B10_L_17.PCIE_TRNRD50 always +PCIE_BOT.PCIE_LOGIC_OUTS_B10_L_18.PCIE_TRNRDLLPDATA27 always +PCIE_BOT.PCIE_LOGIC_OUTS_B10_L_19.PCIE_CFGMSGRECEIVEDPMASNAK always +PCIE_BOT.PCIE_LOGIC_OUTS_B10_R_0.PCIE_MIMTXWDATA56 always +PCIE_BOT.PCIE_LOGIC_OUTS_B10_R_1.PCIE_MIMTXWADDR12 always +PCIE_BOT.PCIE_LOGIC_OUTS_B10_R_2.PCIE_MIMTXRADDR3 always +PCIE_BOT.PCIE_LOGIC_OUTS_B10_R_3.PCIE_MIMTXWDATA63 always +PCIE_BOT.PCIE_LOGIC_OUTS_B10_R_4.PCIE_MIMTXWADDR4 always +PCIE_BOT.PCIE_LOGIC_OUTS_B10_R_5.PCIE_MIMTXWDATA65 always +PCIE_BOT.PCIE_LOGIC_OUTS_B10_R_6.PCIE_MIMTXWDATA12 always +PCIE_BOT.PCIE_LOGIC_OUTS_B10_R_7.PCIE_DBGVECB12 always +PCIE_BOT.PCIE_LOGIC_OUTS_B10_R_8.PCIE_MIMTXWDATA25 always +PCIE_BOT.PCIE_LOGIC_OUTS_B10_R_9.PCIE_TL2ERRHDR12 always +PCIE_BOT.PCIE_LOGIC_OUTS_B10_R_10.PCIE_LNKCLKEN always +PCIE_BOT.PCIE_LOGIC_OUTS_B10_R_11.PCIE_TL2ERRHDR3 always +PCIE_BOT.PCIE_LOGIC_OUTS_B10_R_12.PCIE_CFGMGMTDO7 always +PCIE_BOT.PCIE_LOGIC_OUTS_B10_R_13.PCIE_TRNRD123 always +PCIE_BOT.PCIE_LOGIC_OUTS_B10_R_14.PCIE_PL2RECEIVERERR always +PCIE_BOT.PCIE_LOGIC_OUTS_B10_R_15.PCIE_DBGVECA34 always +PCIE_BOT.PCIE_LOGIC_OUTS_B10_R_16.PCIE_MIMRXWDATA64 always +PCIE_BOT.PCIE_LOGIC_OUTS_B10_R_17.PCIE_TRNRD109 always +PCIE_BOT.PCIE_LOGIC_OUTS_B10_R_18.PCIE_MIMRXWDATA63 always +PCIE_BOT.PCIE_LOGIC_OUTS_B10_R_19.PCIE_MIMRXWDATA65 always +PCIE_BOT.PCIE_LOGIC_OUTS_B11_L_0.PCIE_PLLTSSMSTATE4 always +PCIE_BOT.PCIE_LOGIC_OUTS_B11_L_1.PCIE_PIPETX3DATA10 always +PCIE_BOT.PCIE_LOGIC_OUTS_B11_L_2.PCIE_TRNFCNPH1 always +PCIE_BOT.PCIE_LOGIC_OUTS_B11_L_3.PCIE_PIPETX3DATA2 always +PCIE_BOT.PCIE_LOGIC_OUTS_B11_L_4.PCIE_TRNFCNPD4 always +PCIE_BOT.PCIE_LOGIC_OUTS_B11_L_5.PCIE_PIPETX1DATA10 always +PCIE_BOT.PCIE_LOGIC_OUTS_B11_L_6.PCIE_TRNFCNPD9 always +PCIE_BOT.PCIE_LOGIC_OUTS_B11_L_7.PCIE_PIPETX1DATA2 always +PCIE_BOT.PCIE_LOGIC_OUTS_B11_L_8.PCIE_TL2ERRHDR46 always +PCIE_BOT.PCIE_LOGIC_OUTS_B11_L_9.PCIE_TL2ERRHDR50 always +PCIE_BOT.PCIE_LOGIC_OUTS_B11_L_10.PCIE_TL2ERRHDR54 always +PCIE_BOT.PCIE_LOGIC_OUTS_B11_L_11.PCIE_TRNTDLLPDSTRDY always +PCIE_BOT.PCIE_LOGIC_OUTS_B11_L_12.PCIE_PIPETX2DATA10 always +PCIE_BOT.PCIE_LOGIC_OUTS_B11_L_13.PCIE_TRNRDLLPDATA4 always +PCIE_BOT.PCIE_LOGIC_OUTS_B11_L_14.PCIE_PIPETX2DATA2 always +PCIE_BOT.PCIE_LOGIC_OUTS_B11_L_15.PCIE_TRNRDLLPDATA15 always +PCIE_BOT.PCIE_LOGIC_OUTS_B11_L_16.PCIE_PIPETX0DATA10 always +PCIE_BOT.PCIE_LOGIC_OUTS_B11_L_17.PCIE_TRNRDLLPDATA20 always +PCIE_BOT.PCIE_LOGIC_OUTS_B11_L_18.PCIE_PIPETX0DATA2 always +PCIE_BOT.PCIE_LOGIC_OUTS_B11_L_19.PCIE_CFGPCIELINKSTATE0 always +PCIE_BOT.PCIE_LOGIC_OUTS_B11_R_0.PCIE_MIMTXWDATA36 always +PCIE_BOT.PCIE_LOGIC_OUTS_B11_R_1.PCIE_PIPETX7DATA10 always +PCIE_BOT.PCIE_LOGIC_OUTS_B11_R_2.PCIE_MIMTXWADDR6 always +PCIE_BOT.PCIE_LOGIC_OUTS_B11_R_3.PCIE_PIPETX7DATA2 always +PCIE_BOT.PCIE_LOGIC_OUTS_B11_R_4.PCIE_MIMTXWDATA59 always +PCIE_BOT.PCIE_LOGIC_OUTS_B11_R_5.PCIE_PIPETX5DATA10 always +PCIE_BOT.PCIE_LOGIC_OUTS_B11_R_6.PCIE_MIMTXRADDR1 always +PCIE_BOT.PCIE_LOGIC_OUTS_B11_R_7.PCIE_PIPETX5DATA2 always +PCIE_BOT.PCIE_LOGIC_OUTS_B11_R_8.PCIE_TL2ERRHDR17 always +PCIE_BOT.PCIE_LOGIC_OUTS_B11_R_9.PCIE_TL2ERRHDR13 always +PCIE_BOT.PCIE_LOGIC_OUTS_B11_R_10.PCIE_CFGMGMTDO0 always +PCIE_BOT.PCIE_LOGIC_OUTS_B11_R_11.PCIE_TL2ERRHDR4 always +PCIE_BOT.PCIE_LOGIC_OUTS_B11_R_12.PCIE_PIPETX6DATA10 always +PCIE_BOT.PCIE_LOGIC_OUTS_B11_R_13.PCIE_LL2RECEIVERERR always +PCIE_BOT.PCIE_LOGIC_OUTS_B11_R_14.PCIE_PIPETX6DATA2 always +PCIE_BOT.PCIE_LOGIC_OUTS_B11_R_15.PCIE_DBGVECA35 always +PCIE_BOT.PCIE_LOGIC_OUTS_B11_R_16.PCIE_PIPETX4DATA10 always +PCIE_BOT.PCIE_LOGIC_OUTS_B11_R_17.PCIE_MIMRXWDATA53 always +PCIE_BOT.PCIE_LOGIC_OUTS_B11_R_18.PCIE_PIPETX4DATA2 always +PCIE_BOT.PCIE_LOGIC_OUTS_B11_R_19.PCIE_MIMRXWADDR7 always +PCIE_BOT.PCIE_LOGIC_OUTS_B12_L_0.PCIE_PLLTSSMSTATE5 always +PCIE_BOT.PCIE_LOGIC_OUTS_B12_L_1.PCIE_TL2ERRHDR21 always +PCIE_BOT.PCIE_LOGIC_OUTS_B12_L_2.PCIE_TRNFCNPH2 always +PCIE_BOT.PCIE_LOGIC_OUTS_B12_L_3.PCIE_TL2ERRHDR25 always +PCIE_BOT.PCIE_LOGIC_OUTS_B12_L_4.PCIE_TL2ERRHDR29 always +PCIE_BOT.PCIE_LOGIC_OUTS_B12_L_5.PCIE_TL2ERRHDR35 always +PCIE_BOT.PCIE_LOGIC_OUTS_B12_L_6.PCIE_TRNFCNPD10 always +PCIE_BOT.PCIE_LOGIC_OUTS_B12_L_7.PCIE_TL2ERRHDR39 always +PCIE_BOT.PCIE_LOGIC_OUTS_B12_L_8.PCIE_CFGINTERRUPTDO1 always +PCIE_BOT.PCIE_LOGIC_OUTS_B12_L_9.PCIE_CFGINTERRUPTDO5 always +PCIE_BOT.PCIE_LOGIC_OUTS_B12_L_10.PCIE_CFGMSGDATA0 always +PCIE_BOT.PCIE_LOGIC_OUTS_B12_L_11.PCIE_TL2ERRHDR55 always +PCIE_BOT.PCIE_LOGIC_OUTS_B12_L_12.PCIE_TL2ERRHDR61 always +PCIE_BOT.PCIE_LOGIC_OUTS_B12_L_13.PCIE_TRNRDLLPDATA5 always +PCIE_BOT.PCIE_LOGIC_OUTS_B12_L_14.PCIE_CFGMSGDATA10 always +PCIE_BOT.PCIE_LOGIC_OUTS_B12_L_15.PCIE_CFGMSGDATA14 always +PCIE_BOT.PCIE_LOGIC_OUTS_B12_L_16.PCIE_CFGMSGRECEIVEDDEASSERTINTA always +PCIE_BOT.PCIE_LOGIC_OUTS_B12_L_17.PCIE_TRNRDLLPDATA21 always +PCIE_BOT.PCIE_LOGIC_OUTS_B12_L_18.PCIE_CFGMSGRECEIVEDDEASSERTINTD always +PCIE_BOT.PCIE_LOGIC_OUTS_B12_L_19.PCIE_CFGLINKSTATUSDLLACTIVE always +PCIE_BOT.PCIE_LOGIC_OUTS_B12_R_0.PCIE_MIMTXWDATA52 always +PCIE_BOT.PCIE_LOGIC_OUTS_B12_R_1.PCIE_MIMTXWDATA60 always +PCIE_BOT.PCIE_LOGIC_OUTS_B12_R_2.PCIE_DBGVECB30 always +PCIE_BOT.PCIE_LOGIC_OUTS_B12_R_3.PCIE_MIMTXWADDR8 always +PCIE_BOT.PCIE_LOGIC_OUTS_B12_R_4.PCIE_DBGVECB24 always +PCIE_BOT.PCIE_LOGIC_OUTS_B12_R_5.PCIE_MIMTXWDATA2 always +PCIE_BOT.PCIE_LOGIC_OUTS_B12_R_6.PCIE_MIMTXWEN always +PCIE_BOT.PCIE_LOGIC_OUTS_B12_R_7.PCIE_MIMTXWADDR2 always +PCIE_BOT.PCIE_LOGIC_OUTS_B12_R_8.PCIE_USERRSTN always +PCIE_BOT.PCIE_LOGIC_OUTS_B12_R_9.PCIE_RECEIVEDFUNCLVLRSTN always +PCIE_BOT.PCIE_LOGIC_OUTS_B12_R_10.PCIE_CFGMGMTDO1 always +PCIE_BOT.PCIE_LOGIC_OUTS_B12_R_11.PCIE_TL2ERRHDR5 always +PCIE_BOT.PCIE_LOGIC_OUTS_B12_R_12.PCIE_CFGMGMTDO8 always +PCIE_BOT.PCIE_LOGIC_OUTS_B12_R_13.PCIE_LL2PROTOCOLERR always +PCIE_BOT.PCIE_LOGIC_OUTS_B12_R_14.PCIE_CFGMGMTDO12 always +PCIE_BOT.PCIE_LOGIC_OUTS_B12_R_15.PCIE_MIMRXWDATA38 always +PCIE_BOT.PCIE_LOGIC_OUTS_B12_R_16.PCIE_MIMRXWADDR10 always +PCIE_BOT.PCIE_LOGIC_OUTS_B12_R_17.PCIE_LL2SUSPENDOK always +PCIE_BOT.PCIE_LOGIC_OUTS_B12_R_18.PCIE_MIMRXWDATA55 always +PCIE_BOT.PCIE_LOGIC_OUTS_B12_R_19.PCIE_MIMRXWDATA61 always +PCIE_BOT.PCIE_LOGIC_OUTS_B13_L_0.PCIE_PLLANEREVERSALMODE0 always +PCIE_BOT.PCIE_LOGIC_OUTS_B13_L_1.PCIE_PIPETX3DATA9 always +PCIE_BOT.PCIE_LOGIC_OUTS_B13_L_2.PCIE_TRNFCNPH3 always +PCIE_BOT.PCIE_LOGIC_OUTS_B13_L_3.PCIE_PIPETX3DATA1 always +PCIE_BOT.PCIE_LOGIC_OUTS_B13_L_4.PCIE_TL2ERRHDR30 always +PCIE_BOT.PCIE_LOGIC_OUTS_B13_L_5.PCIE_PIPETX1DATA9 always +PCIE_BOT.PCIE_LOGIC_OUTS_B13_L_6.PCIE_TRNFCNPD11 always +PCIE_BOT.PCIE_LOGIC_OUTS_B13_L_7.PCIE_PIPETX1DATA1 always +PCIE_BOT.PCIE_LOGIC_OUTS_B13_L_8.PCIE_CFGINTERRUPTDO2 always +PCIE_BOT.PCIE_LOGIC_OUTS_B13_L_9.PCIE_CFGINTERRUPTDO6 always +PCIE_BOT.PCIE_LOGIC_OUTS_B13_L_10.PCIE_CFGMSGDATA1 always +PCIE_BOT.PCIE_LOGIC_OUTS_B13_L_11.PCIE_TL2ERRHDR56 always +PCIE_BOT.PCIE_LOGIC_OUTS_B13_L_12.PCIE_PIPETX2DATA9 always +PCIE_BOT.PCIE_LOGIC_OUTS_B13_L_13.PCIE_TRNRDLLPDATA6 always +PCIE_BOT.PCIE_LOGIC_OUTS_B13_L_14.PCIE_PIPETX2DATA1 always +PCIE_BOT.PCIE_LOGIC_OUTS_B13_L_15.PCIE_CFGMSGDATA15 always +PCIE_BOT.PCIE_LOGIC_OUTS_B13_L_16.PCIE_PIPETX0DATA9 always +PCIE_BOT.PCIE_LOGIC_OUTS_B13_L_17.PCIE_TRNRDLLPDATA22 always +PCIE_BOT.PCIE_LOGIC_OUTS_B13_L_18.PCIE_PIPETX0DATA1 always +PCIE_BOT.PCIE_LOGIC_OUTS_B13_L_19.PCIE_CFGLINKSTATUSBANDWIDTHSTATUS always +PCIE_BOT.PCIE_LOGIC_OUTS_B13_R_0.PCIE_MIMTXWDATA54 always +PCIE_BOT.PCIE_LOGIC_OUTS_B13_R_1.PCIE_PIPETX7DATA9 always +PCIE_BOT.PCIE_LOGIC_OUTS_B13_R_2.PCIE_DBGVECB31 always +PCIE_BOT.PCIE_LOGIC_OUTS_B13_R_3.PCIE_PIPETX7DATA1 always +PCIE_BOT.PCIE_LOGIC_OUTS_B13_R_4.PCIE_MIMTXWDATA49 always +PCIE_BOT.PCIE_LOGIC_OUTS_B13_R_5.PCIE_PIPETX5DATA9 always +PCIE_BOT.PCIE_LOGIC_OUTS_B13_R_6.PCIE_DBGVECB17 always +PCIE_BOT.PCIE_LOGIC_OUTS_B13_R_7.PCIE_PIPETX5DATA1 always +PCIE_BOT.PCIE_LOGIC_OUTS_B13_R_8.PCIE_PLRECEIVEDHOTRST always +PCIE_BOT.PCIE_LOGIC_OUTS_B13_R_9.PCIE_MIMTXWDATA27 always +PCIE_BOT.PCIE_LOGIC_OUTS_B13_R_10.PCIE_CFGMGMTDO2 always +PCIE_BOT.PCIE_LOGIC_OUTS_B13_R_11.PCIE_CFGMGMTDO3 always +PCIE_BOT.PCIE_LOGIC_OUTS_B13_R_12.PCIE_PIPETX6DATA9 always +PCIE_BOT.PCIE_LOGIC_OUTS_B13_R_13.PCIE_LL2BADTLPERR always +PCIE_BOT.PCIE_LOGIC_OUTS_B13_R_14.PCIE_PIPETX6DATA1 always +PCIE_BOT.PCIE_LOGIC_OUTS_B13_R_15.PCIE_MIMRXWDATA40 always +PCIE_BOT.PCIE_LOGIC_OUTS_B13_R_16.PCIE_PIPETX4DATA9 always +PCIE_BOT.PCIE_LOGIC_OUTS_B13_R_17.PCIE_LL2TXIDLE always +PCIE_BOT.PCIE_LOGIC_OUTS_B13_R_18.PCIE_PIPETX4DATA1 always +PCIE_BOT.PCIE_LOGIC_OUTS_B13_R_19.PCIE_PL2RXPMSTATE0 always +PCIE_BOT.PCIE_LOGIC_OUTS_B14_L_0.PCIE_PLLANEREVERSALMODE1 always +PCIE_BOT.PCIE_LOGIC_OUTS_B14_L_1.PCIE_TL2ERRHDR22 always +PCIE_BOT.PCIE_LOGIC_OUTS_B14_L_2.PCIE_TRNFCNPH4 always +PCIE_BOT.PCIE_LOGIC_OUTS_B14_L_3.PCIE_TL2ERRHDR26 always +PCIE_BOT.PCIE_LOGIC_OUTS_B14_L_4.PCIE_TL2ERRHDR31 always +PCIE_BOT.PCIE_LOGIC_OUTS_B14_L_5.PCIE_TL2ERRHDR36 always +PCIE_BOT.PCIE_LOGIC_OUTS_B14_L_6.PCIE_TRNFCCPLH0 always +PCIE_BOT.PCIE_LOGIC_OUTS_B14_L_7.PCIE_TL2ERRHDR40 always +PCIE_BOT.PCIE_LOGIC_OUTS_B14_L_8.PCIE_CFGINTERRUPTDO3 always +PCIE_BOT.PCIE_LOGIC_OUTS_B14_L_9.PCIE_CFGINTERRUPTDO7 always +PCIE_BOT.PCIE_LOGIC_OUTS_B14_L_10.PCIE_CFGMSGDATA2 always +PCIE_BOT.PCIE_LOGIC_OUTS_B14_L_11.PCIE_TL2ERRHDR57 always +PCIE_BOT.PCIE_LOGIC_OUTS_B14_L_12.PCIE_TL2ERRHDR62 always +PCIE_BOT.PCIE_LOGIC_OUTS_B14_L_13.PCIE_TRNRDLLPDATA7 always +PCIE_BOT.PCIE_LOGIC_OUTS_B14_L_14.PCIE_CFGMSGDATA11 always +PCIE_BOT.PCIE_LOGIC_OUTS_B14_L_15.PCIE_CFGMSGRECEIVEDERRCOR always +PCIE_BOT.PCIE_LOGIC_OUTS_B14_L_16.PCIE_CFGMSGRECEIVEDASSERTINTB always +PCIE_BOT.PCIE_LOGIC_OUTS_B14_L_17.PCIE_TRNRDLLPDATA23 always +PCIE_BOT.PCIE_LOGIC_OUTS_B14_L_18.PCIE_CFGMSGRECEIVEDPMPME always +PCIE_BOT.PCIE_LOGIC_OUTS_B14_L_19.PCIE_CFGLINKSTATUSAUTOBANDWIDTHSTATUS always +PCIE_BOT.PCIE_LOGIC_OUTS_B14_R_0.PCIE_MIMTXWDATA42 always +PCIE_BOT.PCIE_LOGIC_OUTS_B14_R_1.PCIE_MIMTXWDATA48 always +PCIE_BOT.PCIE_LOGIC_OUTS_B14_R_2.PCIE_MIMTXWDATA67 always +PCIE_BOT.PCIE_LOGIC_OUTS_B14_R_3.PCIE_MIMTXWADDR5 always +PCIE_BOT.PCIE_LOGIC_OUTS_B14_R_4.PCIE_MIMTXRADDR4 always +PCIE_BOT.PCIE_LOGIC_OUTS_B14_R_5.PCIE_MIMTXWDATA51 always +PCIE_BOT.PCIE_LOGIC_OUTS_B14_R_7.PCIE_DBGVECB13 always +PCIE_BOT.PCIE_LOGIC_OUTS_B14_R_8.PCIE_DBGVECA62 always +PCIE_BOT.PCIE_LOGIC_OUTS_B14_R_9.PCIE_DBGVECA58 always +PCIE_BOT.PCIE_LOGIC_OUTS_B14_R_10.PCIE_CFGERRCPLRDYN always +PCIE_BOT.PCIE_LOGIC_OUTS_B14_R_11.PCIE_CFGMGMTDO4 always +PCIE_BOT.PCIE_LOGIC_OUTS_B14_R_12.PCIE_CFGMGMTDO9 always +PCIE_BOT.PCIE_LOGIC_OUTS_B14_R_13.PCIE_LL2BADDLLPERR always +PCIE_BOT.PCIE_LOGIC_OUTS_B14_R_14.PCIE_CFGMGMTDO13 always +PCIE_BOT.PCIE_LOGIC_OUTS_B14_R_15.PCIE_MIMRXWDATA42 always +PCIE_BOT.PCIE_LOGIC_OUTS_B14_R_16.PCIE_MIMRXWADDR11 always +PCIE_BOT.PCIE_LOGIC_OUTS_B14_R_17.PCIE_MIMRXWDATA67 always +PCIE_BOT.PCIE_LOGIC_OUTS_B14_R_18.PCIE_MIMRXWDATA59 always +PCIE_BOT.PCIE_LOGIC_OUTS_B14_R_19.PCIE_MIMRXWADDR0 always +PCIE_BOT.PCIE_LOGIC_OUTS_B15_L_0.PCIE_PLPHYLNKUPN always +PCIE_BOT.PCIE_LOGIC_OUTS_B15_L_1.PCIE_PIPETX3DATA11 always +PCIE_BOT.PCIE_LOGIC_OUTS_B15_L_2.PCIE_TL2ERRHDR23 always +PCIE_BOT.PCIE_LOGIC_OUTS_B15_L_3.PCIE_PIPETX3DATA3 always +PCIE_BOT.PCIE_LOGIC_OUTS_B15_L_4.PCIE_TL2ERRHDR32 always +PCIE_BOT.PCIE_LOGIC_OUTS_B15_L_5.PCIE_PIPETX1DATA11 always +PCIE_BOT.PCIE_LOGIC_OUTS_B15_L_6.PCIE_TL2ERRHDR37 always +PCIE_BOT.PCIE_LOGIC_OUTS_B15_L_7.PCIE_PIPETX1DATA3 always +PCIE_BOT.PCIE_LOGIC_OUTS_B15_L_8.PCIE_CFGINTERRUPTDO4 always +PCIE_BOT.PCIE_LOGIC_OUTS_B15_L_9.PCIE_CFGMSGRECEIVED always +PCIE_BOT.PCIE_LOGIC_OUTS_B15_L_10.PCIE_CFGMSGDATA3 always +PCIE_BOT.PCIE_LOGIC_OUTS_B15_L_11.PCIE_TL2ERRHDR58 always +PCIE_BOT.PCIE_LOGIC_OUTS_B15_L_12.PCIE_PIPETX2DATA11 always +PCIE_BOT.PCIE_LOGIC_OUTS_B15_L_13.PCIE_TL2ERRHDR63 always +PCIE_BOT.PCIE_LOGIC_OUTS_B15_L_14.PCIE_PIPETX2DATA3 always +PCIE_BOT.PCIE_LOGIC_OUTS_B15_L_15.PCIE_CFGMSGRECEIVEDERRNONFATAL always +PCIE_BOT.PCIE_LOGIC_OUTS_B15_L_16.PCIE_PIPETX0DATA11 always +PCIE_BOT.PCIE_LOGIC_OUTS_B15_L_17.PCIE_CFGMSGRECEIVEDDEASSERTINTB always +PCIE_BOT.PCIE_LOGIC_OUTS_B15_L_18.PCIE_PIPETX0DATA3 always +PCIE_BOT.PCIE_LOGIC_OUTS_B15_L_19.PCIE_CFGLINKCONTROLASPMCONTROL0 always +PCIE_BOT.PCIE_LOGIC_OUTS_B15_R_1.PCIE_PIPETX7DATA11 always +PCIE_BOT.PCIE_LOGIC_OUTS_B15_R_2.PCIE_DBGVECB32 always +PCIE_BOT.PCIE_LOGIC_OUTS_B15_R_3.PCIE_PIPETX7DATA3 always +PCIE_BOT.PCIE_LOGIC_OUTS_B15_R_4.PCIE_MIMTXWADDR7 always +PCIE_BOT.PCIE_LOGIC_OUTS_B15_R_5.PCIE_PIPETX5DATA11 always +PCIE_BOT.PCIE_LOGIC_OUTS_B15_R_6.PCIE_MIMTXWDATA34 always +PCIE_BOT.PCIE_LOGIC_OUTS_B15_R_7.PCIE_PIPETX5DATA3 always +PCIE_BOT.PCIE_LOGIC_OUTS_B15_R_8.PCIE_DBGVECA63 always +PCIE_BOT.PCIE_LOGIC_OUTS_B15_R_9.PCIE_PIPETXRCVRDET always +PCIE_BOT.PCIE_LOGIC_OUTS_B15_R_10.PCIE_CFGINTERRUPTRDYN always +PCIE_BOT.PCIE_LOGIC_OUTS_B15_R_11.PCIE_CFGMGMTDO5 always +PCIE_BOT.PCIE_LOGIC_OUTS_B15_R_12.PCIE_PIPETX6DATA11 always +PCIE_BOT.PCIE_LOGIC_OUTS_B15_R_13.PCIE_CFGMGMTDO10 always +PCIE_BOT.PCIE_LOGIC_OUTS_B15_R_14.PCIE_PIPETX6DATA3 always +PCIE_BOT.PCIE_LOGIC_OUTS_B15_R_15.PCIE_MIMRXWDATA58 always +PCIE_BOT.PCIE_LOGIC_OUTS_B15_R_16.PCIE_PIPETX4DATA11 always +PCIE_BOT.PCIE_LOGIC_OUTS_B15_R_17.PCIE_LL2LINKSTATUS0 always +PCIE_BOT.PCIE_LOGIC_OUTS_B15_R_18.PCIE_PIPETX4DATA3 always +PCIE_BOT.PCIE_LOGIC_OUTS_B15_R_19.PCIE_MIMRXRADDR7 always +PCIE_BOT.PCIE_LOGIC_OUTS_B16_L_0.PCIE_PIPETX3CHARISK1 always +PCIE_BOT.PCIE_LOGIC_OUTS_B16_L_1.PCIE_CFGINTERRUPTMMENABLE2 always +PCIE_BOT.PCIE_LOGIC_OUTS_B16_L_2.PCIE_PIPETX3CHARISK0 always +PCIE_BOT.PCIE_LOGIC_OUTS_B16_L_3.PCIE_TL2ERRHDR27 always +PCIE_BOT.PCIE_LOGIC_OUTS_B16_L_4.PCIE_PIPETX1CHARISK1 always +PCIE_BOT.PCIE_LOGIC_OUTS_B16_L_5.PCIE_CFGINTERRUPTMSIXFM always +PCIE_BOT.PCIE_LOGIC_OUTS_B16_L_6.PCIE_PIPETX1CHARISK0 always +PCIE_BOT.PCIE_LOGIC_OUTS_B16_L_7.PCIE_TL2ERRHDR41 always +PCIE_BOT.PCIE_LOGIC_OUTS_B16_L_8.PCIE_CFGCOMMANDSERREN always +PCIE_BOT.PCIE_LOGIC_OUTS_B16_L_9.PCIE_CFGDEVSTATUSCORRERRDETECTED always +PCIE_BOT.PCIE_LOGIC_OUTS_B16_L_10.PCIE_CFGDEVSTATUSFATALERRDETECTED always +PCIE_BOT.PCIE_LOGIC_OUTS_B16_L_11.PCIE_PIPETX2CHARISK1 always +PCIE_BOT.PCIE_LOGIC_OUTS_B16_L_12.PCIE_CFGMSGDATA6 always +PCIE_BOT.PCIE_LOGIC_OUTS_B16_L_13.PCIE_PIPETX2CHARISK0 always +PCIE_BOT.PCIE_LOGIC_OUTS_B16_L_14.PCIE_CFGMSGDATA12 always +PCIE_BOT.PCIE_LOGIC_OUTS_B16_L_15.PCIE_PIPETX0CHARISK1 always +PCIE_BOT.PCIE_LOGIC_OUTS_B16_L_16.PCIE_CFGDEVCONTROLMAXREADREQ0 always +PCIE_BOT.PCIE_LOGIC_OUTS_B16_L_17.PCIE_PIPETX0CHARISK0 always +PCIE_BOT.PCIE_LOGIC_OUTS_B16_L_18.PCIE_CFGMSGRECEIVEDPMETOACK always +PCIE_BOT.PCIE_LOGIC_OUTS_B16_L_19.PCIE_CFGROOTCONTROLPMEINTEN always +PCIE_BOT.PCIE_LOGIC_OUTS_B16_R_0.PCIE_PIPETX7CHARISK1 always +PCIE_BOT.PCIE_LOGIC_OUTS_B16_R_1.PCIE_MIMTXWDATA64 always +PCIE_BOT.PCIE_LOGIC_OUTS_B16_R_2.PCIE_PIPETX7CHARISK0 always +PCIE_BOT.PCIE_LOGIC_OUTS_B16_R_3.PCIE_DBGVECB28 always +PCIE_BOT.PCIE_LOGIC_OUTS_B16_R_4.PCIE_PIPETX5CHARISK1 always +PCIE_BOT.PCIE_LOGIC_OUTS_B16_R_5.PCIE_DBGVECB20 always +PCIE_BOT.PCIE_LOGIC_OUTS_B16_R_6.PCIE_PIPETX5CHARISK0 always +PCIE_BOT.PCIE_LOGIC_OUTS_B16_R_7.PCIE_MIMTXWDATA28 always +PCIE_BOT.PCIE_LOGIC_OUTS_B16_R_8.PCIE_DBGVECB0 always +PCIE_BOT.PCIE_LOGIC_OUTS_B16_R_9.PCIE_MIMTXWDATA15 always +PCIE_BOT.PCIE_LOGIC_OUTS_B16_R_10.PCIE_CFGINTERRUPTMMENABLE0 always +PCIE_BOT.PCIE_LOGIC_OUTS_B16_R_11.PCIE_PIPETX6CHARISK1 always +PCIE_BOT.PCIE_LOGIC_OUTS_B16_R_12.PCIE_CFGMGMTRDWRDONEN always +PCIE_BOT.PCIE_LOGIC_OUTS_B16_R_13.PCIE_PIPETX6CHARISK0 always +PCIE_BOT.PCIE_LOGIC_OUTS_B16_R_14.PCIE_CFGMGMTDO14 always +PCIE_BOT.PCIE_LOGIC_OUTS_B16_R_15.PCIE_PIPETX4CHARISK1 always +PCIE_BOT.PCIE_LOGIC_OUTS_B16_R_16.PCIE_MIMRXWDATA48 always +PCIE_BOT.PCIE_LOGIC_OUTS_B16_R_17.PCIE_PIPETX4CHARISK0 always +PCIE_BOT.PCIE_LOGIC_OUTS_B16_R_18.PCIE_MIMRXRADDR3 always +PCIE_BOT.PCIE_LOGIC_OUTS_B16_R_19.PCIE_MIMRXWADDR4 always +PCIE_BOT.PCIE_LOGIC_OUTS_B17_L_0.PCIE_PLTXPMSTATE0 always +PCIE_BOT.PCIE_LOGIC_OUTS_B17_L_1.PCIE_CFGINTERRUPTMSIENABLE always +PCIE_BOT.PCIE_LOGIC_OUTS_B17_L_2.PCIE_TL2ERRHDR24 always +PCIE_BOT.PCIE_LOGIC_OUTS_B17_L_3.PCIE_TL2ERRHDR28 always +PCIE_BOT.PCIE_LOGIC_OUTS_B17_L_4.PCIE_CFGINTERRUPTMSIXENABLE always +PCIE_BOT.PCIE_LOGIC_OUTS_B17_L_5.PCIE_CFGINTERRUPTDO0 always +PCIE_BOT.PCIE_LOGIC_OUTS_B17_L_6.PCIE_TL2ERRHDR38 always +PCIE_BOT.PCIE_LOGIC_OUTS_B17_L_7.PCIE_TL2ERRHDR42 always +PCIE_BOT.PCIE_LOGIC_OUTS_B17_L_8.PCIE_CFGBRIDGESERREN always +PCIE_BOT.PCIE_LOGIC_OUTS_B17_L_9.PCIE_CFGDEVSTATUSNONFATALERRDETECTED always +PCIE_BOT.PCIE_LOGIC_OUTS_B17_L_10.PCIE_CFGDEVSTATUSURDETECTED always +PCIE_BOT.PCIE_LOGIC_OUTS_B17_L_11.PCIE_CFGMSGDATA4 always +PCIE_BOT.PCIE_LOGIC_OUTS_B17_L_12.PCIE_CFGMSGDATA7 always +PCIE_BOT.PCIE_LOGIC_OUTS_B17_L_13.PCIE_TL2ERRMALFORMED always +PCIE_BOT.PCIE_LOGIC_OUTS_B17_L_14.PCIE_CFGMSGDATA13 always +PCIE_BOT.PCIE_LOGIC_OUTS_B17_L_15.PCIE_CFGDEVCONTROLEXTTAGEN always +PCIE_BOT.PCIE_LOGIC_OUTS_B17_L_16.PCIE_CFGDEVCONTROLMAXREADREQ1 always +PCIE_BOT.PCIE_LOGIC_OUTS_B17_L_17.PCIE_CFGMSGRECEIVEDASSERTINTC always +PCIE_BOT.PCIE_LOGIC_OUTS_B17_L_18.PCIE_CFGMSGRECEIVEDPMETO always +PCIE_BOT.PCIE_LOGIC_OUTS_B17_L_19.PCIE_CFGAERECRCCHECKEN always +PCIE_BOT.PCIE_LOGIC_OUTS_B17_R_0.PCIE_MIMTXWDATA58 always +PCIE_BOT.PCIE_LOGIC_OUTS_B17_R_2.PCIE_MIMTXRADDR6 always +PCIE_BOT.PCIE_LOGIC_OUTS_B17_R_3.PCIE_MIMTXWDATA45 always +PCIE_BOT.PCIE_LOGIC_OUTS_B17_R_4.PCIE_MIMTXRADDR7 always +PCIE_BOT.PCIE_LOGIC_OUTS_B17_R_5.PCIE_MIMTXWDATA0 always +PCIE_BOT.PCIE_LOGIC_OUTS_B17_R_6.PCIE_MIMTXWDATA22 always +PCIE_BOT.PCIE_LOGIC_OUTS_B17_R_7.PCIE_DBGVECB14 always +PCIE_BOT.PCIE_LOGIC_OUTS_B17_R_8.PCIE_DBGVECB1 always +PCIE_BOT.PCIE_LOGIC_OUTS_B17_R_9.PCIE_MIMTXWDATA35 always +PCIE_BOT.PCIE_LOGIC_OUTS_B17_R_10.PCIE_CFGINTERRUPTMMENABLE1 always +PCIE_BOT.PCIE_LOGIC_OUTS_B17_R_11.PCIE_DBGVECA50 always +PCIE_BOT.PCIE_LOGIC_OUTS_B17_R_12.PCIE_CFGERRAERHEADERLOGSETN always +PCIE_BOT.PCIE_LOGIC_OUTS_B17_R_13.PCIE_CFGMGMTDO11 always +PCIE_BOT.PCIE_LOGIC_OUTS_B17_R_14.PCIE_CFGMGMTDO15 always +PCIE_BOT.PCIE_LOGIC_OUTS_B17_R_15.PCIE_MIMRXWDATA36 always +PCIE_BOT.PCIE_LOGIC_OUTS_B17_R_16.PCIE_MIMRXWDATA50 always +PCIE_BOT.PCIE_LOGIC_OUTS_B17_R_17.PCIE_MIMRXWADDR6 always +PCIE_BOT.PCIE_LOGIC_OUTS_B17_R_18.PCIE_MIMRXWDATA45 always +PCIE_BOT.PCIE_LOGIC_OUTS_B17_R_19.PCIE_MIMRXWADDR9 always +PCIE_BOT.PCIE_LOGIC_OUTS_B18_L_0.PCIE_PLTXPMSTATE1 always +PCIE_BOT.PCIE_LOGIC_OUTS_B18_L_1.PCIE_DBGVECB39 always +PCIE_BOT.PCIE_LOGIC_OUTS_B18_L_2.PCIE_DBGVECB43 always +PCIE_BOT.PCIE_LOGIC_OUTS_B18_L_3.PCIE_DBGVECB47 always +PCIE_BOT.PCIE_LOGIC_OUTS_B18_L_4.PCIE_DBGVECB51 always +PCIE_BOT.PCIE_LOGIC_OUTS_B18_L_5.PCIE_DBGVECB55 always +PCIE_BOT.PCIE_LOGIC_OUTS_B18_L_6.PCIE_DBGVECB59 always +PCIE_BOT.PCIE_LOGIC_OUTS_B18_L_7.PCIE_DBGVECB63 always +PCIE_BOT.PCIE_LOGIC_OUTS_B18_L_8.PCIE_DBGVECC3 always +PCIE_BOT.PCIE_LOGIC_OUTS_B18_L_9.PCIE_DBGVECC7 always +PCIE_BOT.PCIE_LOGIC_OUTS_B18_L_10.PCIE_DBGVECC11 always +PCIE_BOT.PCIE_LOGIC_OUTS_B18_L_11.PCIE_CFGMSGDATA5 always +PCIE_BOT.PCIE_LOGIC_OUTS_B18_L_12.PCIE_CFGMSGDATA8 always +PCIE_BOT.PCIE_LOGIC_OUTS_B18_L_13.PCIE_TL2ERRRXOVERFLOW always +PCIE_BOT.PCIE_LOGIC_OUTS_B18_L_14.PCIE_CFGDEVCONTROLENABLERO always +PCIE_BOT.PCIE_LOGIC_OUTS_B18_L_15.PCIE_CFGDEVCONTROLPHANTOMEN always +PCIE_BOT.PCIE_LOGIC_OUTS_B18_L_16.PCIE_CFGDEVCONTROLMAXREADREQ2 always +PCIE_BOT.PCIE_LOGIC_OUTS_B18_L_17.PCIE_CFGMSGRECEIVEDDEASSERTINTC always +PCIE_BOT.PCIE_LOGIC_OUTS_B18_L_18.PCIE_CFGLINKSTATUSNEGOTIATEDWIDTH1 always +PCIE_BOT.PCIE_LOGIC_OUTS_B18_L_19.PCIE_CFGAERECRCGENEN always +PCIE_BOT.PCIE_LOGIC_OUTS_B18_R_0.PCIE_MIMTXWDATA38 always +PCIE_BOT.PCIE_LOGIC_OUTS_B18_R_2.PCIE_MIMTXWDATA66 always +PCIE_BOT.PCIE_LOGIC_OUTS_B18_R_3.PCIE_MIMTXWDATA41 always +PCIE_BOT.PCIE_LOGIC_OUTS_B18_R_4.PCIE_MIMTXWDATA47 always +PCIE_BOT.PCIE_LOGIC_OUTS_B18_R_5.PCIE_DBGVECB21 always +PCIE_BOT.PCIE_LOGIC_OUTS_B18_R_6.PCIE_MIMTXWDATA24 always +PCIE_BOT.PCIE_LOGIC_OUTS_B18_R_7.PCIE_DBGVECB15 always +PCIE_BOT.PCIE_LOGIC_OUTS_B18_R_8.PCIE_DBGVECB11 always +PCIE_BOT.PCIE_LOGIC_OUTS_B18_R_9.PCIE_MIMTXWDATA11 always +PCIE_BOT.PCIE_LOGIC_OUTS_B18_R_10.PCIE_DBGVECA54 always +PCIE_BOT.PCIE_LOGIC_OUTS_B18_R_11.PCIE_DBGVECA51 always +PCIE_BOT.PCIE_LOGIC_OUTS_B18_R_12.PCIE_DBGVECA46 always +PCIE_BOT.PCIE_LOGIC_OUTS_B18_R_13.PCIE_DBGVECA42 always +PCIE_BOT.PCIE_LOGIC_OUTS_B18_R_14.PCIE_CFGMGMTDO31 always +PCIE_BOT.PCIE_LOGIC_OUTS_B18_R_15.PCIE_MIMRXWDATA52 always +PCIE_BOT.PCIE_LOGIC_OUTS_B18_R_16.PCIE_MIMRXWDATA44 always +PCIE_BOT.PCIE_LOGIC_OUTS_B18_R_17.PCIE_MIMRXWDATA66 always +PCIE_BOT.PCIE_LOGIC_OUTS_B18_R_18.PCIE_MIMRXWDATA41 always +PCIE_BOT.PCIE_LOGIC_OUTS_B18_R_19.PCIE_MIMRXWDATA47 always +PCIE_BOT.PCIE_LOGIC_OUTS_B19_L_0.PCIE_PLTXPMSTATE2 always +PCIE_BOT.PCIE_LOGIC_OUTS_B19_L_1.PCIE_DBGVECB40 always +PCIE_BOT.PCIE_LOGIC_OUTS_B19_L_2.PCIE_DBGVECB44 always +PCIE_BOT.PCIE_LOGIC_OUTS_B19_L_3.PCIE_DBGVECB48 always +PCIE_BOT.PCIE_LOGIC_OUTS_B19_L_4.PCIE_DBGVECB52 always +PCIE_BOT.PCIE_LOGIC_OUTS_B19_L_5.PCIE_DBGVECB56 always +PCIE_BOT.PCIE_LOGIC_OUTS_B19_L_6.PCIE_DBGVECB60 always +PCIE_BOT.PCIE_LOGIC_OUTS_B19_L_7.PCIE_DBGVECC0 always +PCIE_BOT.PCIE_LOGIC_OUTS_B19_L_8.PCIE_DBGVECC4 always +PCIE_BOT.PCIE_LOGIC_OUTS_B19_L_9.PCIE_DBGVECC8 always +PCIE_BOT.PCIE_LOGIC_OUTS_B19_L_10.PCIE_DBGSCLRA always +PCIE_BOT.PCIE_LOGIC_OUTS_B19_L_11.PCIE_DBGSCLRD always +PCIE_BOT.PCIE_LOGIC_OUTS_B19_L_12.PCIE_CFGMSGDATA9 always +PCIE_BOT.PCIE_LOGIC_OUTS_B19_L_13.PCIE_TL2ERRFCPE always +PCIE_BOT.PCIE_LOGIC_OUTS_B19_L_14.PCIE_CFGDEVCONTROLMAXPAYLOAD0 always +PCIE_BOT.PCIE_LOGIC_OUTS_B19_L_15.PCIE_CFGDEVCONTROLAUXPOWEREN always +PCIE_BOT.PCIE_LOGIC_OUTS_B19_L_16.PCIE_CFGLINKSTATUSCURRENTSPEED0 always +PCIE_BOT.PCIE_LOGIC_OUTS_B19_L_17.PCIE_CFGMSGRECEIVEDASSERTINTD always +PCIE_BOT.PCIE_LOGIC_OUTS_B19_L_18.PCIE_CFGLINKSTATUSNEGOTIATEDWIDTH2 always +PCIE_BOT.PCIE_LOGIC_OUTS_B19_L_19.PCIE_CFGAERROOTERRCORRERRREPORTINGEN always +PCIE_BOT.PCIE_LOGIC_OUTS_B19_R_1.PCIE_MIMTXWDATA46 always +PCIE_BOT.PCIE_LOGIC_OUTS_B19_R_2.PCIE_MIMTXWDATA53 always +PCIE_BOT.PCIE_LOGIC_OUTS_B19_R_3.PCIE_MIMTXWDATA43 always +PCIE_BOT.PCIE_LOGIC_OUTS_B19_R_4.PCIE_DBGVECB25 always +PCIE_BOT.PCIE_LOGIC_OUTS_B19_R_5.PCIE_MIMTXWDATA1 always +PCIE_BOT.PCIE_LOGIC_OUTS_B19_R_6.PCIE_MIMTXRADDR5 always +PCIE_BOT.PCIE_LOGIC_OUTS_B19_R_7.PCIE_MIMTXWDATA32 always +PCIE_BOT.PCIE_LOGIC_OUTS_B19_R_8.PCIE_MIMTXWDATA7 always +PCIE_BOT.PCIE_LOGIC_OUTS_B19_R_9.PCIE_DBGVECA59 always +PCIE_BOT.PCIE_LOGIC_OUTS_B19_R_10.PCIE_DBGVECA55 always +PCIE_BOT.PCIE_LOGIC_OUTS_B19_R_11.PCIE_PIPETXRATE always +PCIE_BOT.PCIE_LOGIC_OUTS_B19_R_12.PCIE_DBGVECA47 always +PCIE_BOT.PCIE_LOGIC_OUTS_B19_R_13.PCIE_DBGVECA43 always +PCIE_BOT.PCIE_LOGIC_OUTS_B19_R_14.PCIE_DBGVECA38 always +PCIE_BOT.PCIE_LOGIC_OUTS_B19_R_15.PCIE_DBGVECA36 always +PCIE_BOT.PCIE_LOGIC_OUTS_B19_R_16.PCIE_MIMRXWDATA62 always +PCIE_BOT.PCIE_LOGIC_OUTS_B19_R_17.PCIE_LL2LINKSTATUS1 always +PCIE_BOT.PCIE_LOGIC_OUTS_B19_R_18.PCIE_MIMRXWDATA43 always +PCIE_BOT.PCIE_LOGIC_OUTS_B19_R_19.PCIE_PL2RXPMSTATE1 always +PCIE_BOT.PCIE_LOGIC_OUTS_B20_L_0.PCIE_DBGVECB36 always +PCIE_BOT.PCIE_LOGIC_OUTS_B20_L_1.PCIE_DBGVECB41 always +PCIE_BOT.PCIE_LOGIC_OUTS_B20_L_2.PCIE_DBGVECB45 always +PCIE_BOT.PCIE_LOGIC_OUTS_B20_L_3.PCIE_DBGVECB49 always +PCIE_BOT.PCIE_LOGIC_OUTS_B20_L_4.PCIE_DBGVECB53 always +PCIE_BOT.PCIE_LOGIC_OUTS_B20_L_5.PCIE_DBGVECB57 always +PCIE_BOT.PCIE_LOGIC_OUTS_B20_L_6.PCIE_DBGVECB61 always +PCIE_BOT.PCIE_LOGIC_OUTS_B20_L_7.PCIE_DBGVECC1 always +PCIE_BOT.PCIE_LOGIC_OUTS_B20_L_8.PCIE_DBGVECC5 always +PCIE_BOT.PCIE_LOGIC_OUTS_B20_L_9.PCIE_DBGVECC9 always +PCIE_BOT.PCIE_LOGIC_OUTS_B20_L_10.PCIE_DBGSCLRB always +PCIE_BOT.PCIE_LOGIC_OUTS_B20_L_11.PCIE_DBGSCLRE always +PCIE_BOT.PCIE_LOGIC_OUTS_B20_L_12.PCIE_CFGDEVCONTROLCORRERRREPORTINGEN always +PCIE_BOT.PCIE_LOGIC_OUTS_B20_L_13.PCIE_CFGDEVCONTROLFATALERRREPORTINGEN always +PCIE_BOT.PCIE_LOGIC_OUTS_B20_L_14.PCIE_CFGDEVCONTROLMAXPAYLOAD1 always +PCIE_BOT.PCIE_LOGIC_OUTS_B20_L_15.PCIE_CFGDEVCONTROLNOSNOOPEN always +PCIE_BOT.PCIE_LOGIC_OUTS_B20_L_16.PCIE_CFGROOTCONTROLSYSERRCORRERREN always +PCIE_BOT.PCIE_LOGIC_OUTS_B20_L_17.PCIE_CFGLINKSTATUSCURRENTSPEED1 always +PCIE_BOT.PCIE_LOGIC_OUTS_B20_L_18.PCIE_CFGLINKSTATUSNEGOTIATEDWIDTH3 always +PCIE_BOT.PCIE_LOGIC_OUTS_B20_L_19.PCIE_DRPDO7 always +PCIE_BOT.PCIE_LOGIC_OUTS_B20_R_2.PCIE_MIMTXWDATA55 always +PCIE_BOT.PCIE_LOGIC_OUTS_B20_R_3.PCIE_DBGVECB29 always +PCIE_BOT.PCIE_LOGIC_OUTS_B20_R_4.PCIE_MIMTXRADDR0 always +PCIE_BOT.PCIE_LOGIC_OUTS_B20_R_5.PCIE_MIMTXWDATA6 always +PCIE_BOT.PCIE_LOGIC_OUTS_B20_R_6.PCIE_MIMTXWDATA30 always +PCIE_BOT.PCIE_LOGIC_OUTS_B20_R_7.PCIE_PLDBGVEC9 always +PCIE_BOT.PCIE_LOGIC_OUTS_B20_R_8.PCIE_MIMTXWDATA23 always +PCIE_BOT.PCIE_LOGIC_OUTS_B20_R_9.PCIE_DBGVECA60 always +PCIE_BOT.PCIE_LOGIC_OUTS_B20_R_10.PCIE_DBGVECA56 always +PCIE_BOT.PCIE_LOGIC_OUTS_B20_R_11.PCIE_DBGVECA52 always +PCIE_BOT.PCIE_LOGIC_OUTS_B20_R_12.PCIE_DBGVECA48 always +PCIE_BOT.PCIE_LOGIC_OUTS_B20_R_13.PCIE_DBGVECA44 always +PCIE_BOT.PCIE_LOGIC_OUTS_B20_R_14.PCIE_DBGVECA39 always +PCIE_BOT.PCIE_LOGIC_OUTS_B20_R_15.PCIE_DBGVECA37 always +PCIE_BOT.PCIE_LOGIC_OUTS_B20_R_16.PCIE_LL2LINKSTATUS4 always +PCIE_BOT.PCIE_LOGIC_OUTS_B20_R_17.PCIE_DBGVECA29 always +PCIE_BOT.PCIE_LOGIC_OUTS_B20_R_18.PCIE_DBGVECA27 always +PCIE_BOT.PCIE_LOGIC_OUTS_B20_R_19.PCIE_PL2L0REQ always +PCIE_BOT.PCIE_LOGIC_OUTS_B21_L_0.PCIE_DBGVECB37 always +PCIE_BOT.PCIE_LOGIC_OUTS_B21_L_1.PCIE_DBGVECB42 always +PCIE_BOT.PCIE_LOGIC_OUTS_B21_L_2.PCIE_DBGVECB46 always +PCIE_BOT.PCIE_LOGIC_OUTS_B21_L_3.PCIE_DBGVECB50 always +PCIE_BOT.PCIE_LOGIC_OUTS_B21_L_4.PCIE_DBGVECB54 always +PCIE_BOT.PCIE_LOGIC_OUTS_B21_L_5.PCIE_DBGVECB58 always +PCIE_BOT.PCIE_LOGIC_OUTS_B21_L_6.PCIE_DBGVECB62 always +PCIE_BOT.PCIE_LOGIC_OUTS_B21_L_7.PCIE_DBGVECC2 always +PCIE_BOT.PCIE_LOGIC_OUTS_B21_L_8.PCIE_DBGVECC6 always +PCIE_BOT.PCIE_LOGIC_OUTS_B21_L_9.PCIE_DBGVECC10 always +PCIE_BOT.PCIE_LOGIC_OUTS_B21_L_10.PCIE_DBGSCLRC always +PCIE_BOT.PCIE_LOGIC_OUTS_B21_L_11.PCIE_DBGSCLRF always +PCIE_BOT.PCIE_LOGIC_OUTS_B21_L_12.PCIE_CFGDEVCONTROLNONFATALREPORTINGEN always +PCIE_BOT.PCIE_LOGIC_OUTS_B21_L_13.PCIE_CFGDEVCONTROLURERRREPORTINGEN always +PCIE_BOT.PCIE_LOGIC_OUTS_B21_L_14.PCIE_CFGDEVCONTROLMAXPAYLOAD2 always +PCIE_BOT.PCIE_LOGIC_OUTS_B21_L_15.PCIE_CFGDEVCONTROL2TLPPREFIXBLOCK always +PCIE_BOT.PCIE_LOGIC_OUTS_B21_L_16.PCIE_CFGROOTCONTROLSYSERRNONFATALERREN always +PCIE_BOT.PCIE_LOGIC_OUTS_B21_L_17.PCIE_CFGLINKSTATUSNEGOTIATEDWIDTH0 always +PCIE_BOT.PCIE_LOGIC_OUTS_B21_L_18.PCIE_CFGLINKSTATUSLINKTRAINING always +PCIE_BOT.PCIE_LOGIC_OUTS_B21_L_19.PCIE_DRPDO8 always +PCIE_BOT.PCIE_LOGIC_OUTS_B21_R_2.PCIE_MIMTXWDATA39 always +PCIE_BOT.PCIE_LOGIC_OUTS_B21_R_4.PCIE_MIMTXWADDR9 always +PCIE_BOT.PCIE_LOGIC_OUTS_B21_R_5.PCIE_PLDBGVEC10 always +PCIE_BOT.PCIE_LOGIC_OUTS_B21_R_6.PCIE_MIMTXWDATA14 always +PCIE_BOT.PCIE_LOGIC_OUTS_B21_R_8.PCIE_MIMTXWDATA9 always +PCIE_BOT.PCIE_LOGIC_OUTS_B21_R_9.PCIE_DBGVECA61 always +PCIE_BOT.PCIE_LOGIC_OUTS_B21_R_10.PCIE_DBGVECA57 always +PCIE_BOT.PCIE_LOGIC_OUTS_B21_R_11.PCIE_DBGVECA53 always +PCIE_BOT.PCIE_LOGIC_OUTS_B21_R_12.PCIE_DBGVECA49 always +PCIE_BOT.PCIE_LOGIC_OUTS_B21_R_13.PCIE_DBGVECA45 always +PCIE_BOT.PCIE_LOGIC_OUTS_B21_R_14.PCIE_DBGVECA40 always +PCIE_BOT.PCIE_LOGIC_OUTS_B21_R_15.PCIE_MIMRXRADDR12 always +PCIE_BOT.PCIE_LOGIC_OUTS_B21_R_16.PCIE_TL2PPMSUSPENDOK always +PCIE_BOT.PCIE_LOGIC_OUTS_B21_R_17.PCIE_DBGVECA30 always +PCIE_BOT.PCIE_LOGIC_OUTS_B21_R_18.PCIE_DBGVECA28 always +PCIE_BOT.PCIE_LOGIC_OUTS_B21_R_19.PCIE_DBGVECA22 always +PCIE_BOT.PCIE_LOGIC_OUTS_B22_L_0.PCIE_DBGVECB38 always +PCIE_BOT.PCIE_LOGIC_OUTS_B22_L_11.PCIE_DBGSCLRG always +PCIE_BOT.PCIE_LOGIC_OUTS_B22_L_12.PCIE_DBGSCLRH always +PCIE_BOT.PCIE_LOGIC_OUTS_B22_L_13.PCIE_DBGSCLRJ always +PCIE_BOT.PCIE_LOGIC_OUTS_B22_L_14.PCIE_PLDBGVEC0 always +PCIE_BOT.PCIE_LOGIC_OUTS_B22_L_15.PCIE_CFGSLOTCONTROLELECTROMECHILCTLPULSE always +PCIE_BOT.PCIE_LOGIC_OUTS_B22_L_16.PCIE_PLDBGVEC3 always +PCIE_BOT.PCIE_LOGIC_OUTS_B22_L_17.PCIE_PLDBGVEC5 always +PCIE_BOT.PCIE_LOGIC_OUTS_B22_L_18.PCIE_CFGROOTCONTROLSYSERRFATALERREN always +PCIE_BOT.PCIE_LOGIC_OUTS_B22_L_19.PCIE_DRPDO9 always +PCIE_BOT.PCIE_LOGIC_OUTS_B22_R_0.PCIE_DBGVECB35 always +PCIE_BOT.PCIE_LOGIC_OUTS_B22_R_1.PCIE_DBGVECB34 always +PCIE_BOT.PCIE_LOGIC_OUTS_B22_R_2.PCIE_DBGVECB33 always +PCIE_BOT.PCIE_LOGIC_OUTS_B22_R_3.PCIE_MIMTXRADDR8 always +PCIE_BOT.PCIE_LOGIC_OUTS_B22_R_4.PCIE_PLDBGVEC11 always +PCIE_BOT.PCIE_LOGIC_OUTS_B22_R_6.PCIE_MIMTXWDATA8 always +PCIE_BOT.PCIE_LOGIC_OUTS_B22_R_7.PCIE_MIMTXRADDR2 always +PCIE_BOT.PCIE_LOGIC_OUTS_B22_R_9.PCIE_DBGVECB2 always +PCIE_BOT.PCIE_LOGIC_OUTS_B22_R_10.PCIE_DBGVECB3 always +PCIE_BOT.PCIE_LOGIC_OUTS_B22_R_11.PCIE_DBGVECB4 always +PCIE_BOT.PCIE_LOGIC_OUTS_B22_R_12.PCIE_DBGVECB5 always +PCIE_BOT.PCIE_LOGIC_OUTS_B22_R_13.PCIE_DBGVECB6 always +PCIE_BOT.PCIE_LOGIC_OUTS_B22_R_14.PCIE_DBGVECA41 always +PCIE_BOT.PCIE_LOGIC_OUTS_B22_R_15.PCIE_DBGVECB8 always +PCIE_BOT.PCIE_LOGIC_OUTS_B22_R_16.PCIE_DBGVECA33 always +PCIE_BOT.PCIE_LOGIC_OUTS_B22_R_17.PCIE_DBGVECA31 always +PCIE_BOT.PCIE_LOGIC_OUTS_B22_R_18.PCIE_DBGVECB9 always +PCIE_BOT.PCIE_LOGIC_OUTS_B22_R_19.PCIE_DBGVECA23 always +PCIE_BOT.PCIE_LOGIC_OUTS_B23_L_12.PCIE_DBGSCLRI always +PCIE_BOT.PCIE_LOGIC_OUTS_B23_L_13.PCIE_DBGSCLRK always +PCIE_BOT.PCIE_LOGIC_OUTS_B23_L_14.PCIE_PLDBGVEC1 always +PCIE_BOT.PCIE_LOGIC_OUTS_B23_L_15.PCIE_PLDBGVEC2 always +PCIE_BOT.PCIE_LOGIC_OUTS_B23_L_16.PCIE_PLDBGVEC4 always +PCIE_BOT.PCIE_LOGIC_OUTS_B23_L_17.PCIE_PLDBGVEC6 always +PCIE_BOT.PCIE_LOGIC_OUTS_B23_L_18.PCIE_PLDBGVEC7 always +PCIE_BOT.PCIE_LOGIC_OUTS_B23_L_19.PCIE_DRPDO10 always +PCIE_BOT.PCIE_LOGIC_OUTS_B23_R_5.PCIE_MIMTXWADDR3 always +PCIE_BOT.PCIE_LOGIC_OUTS_B23_R_6.PCIE_MIMTXWDATA10 always +PCIE_BOT.PCIE_LOGIC_OUTS_B23_R_7.PCIE_MIMTXWADDR0 always +PCIE_BOT.PCIE_LOGIC_OUTS_B23_R_8.PCIE_MIMTXWADDR10 always +PCIE_BOT.PCIE_LOGIC_OUTS_B23_R_14.PCIE_DBGVECB7 always +PCIE_BOT.PCIE_LOGIC_OUTS_B23_R_16.PCIE_MIMRXWDATA46 always +PCIE_BOT.PCIE_LOGIC_OUTS_B23_R_17.PCIE_MIMRXWDATA39 always +PCIE_BOT.PCIE_LOGIC_OUTS_B23_R_19.PCIE_DBGVECA24 always +PCIE_BOT.PCIE_PIPECLK.PCIE_CLK0_R_11 always +PCIE_BOT.PCIE_PIPERX0ELECIDLE.PCIE_IMUX34_L_19 always +PCIE_BOT.PCIE_PIPERX1CHANISALIGNED.PCIE_IMUX33_L_9 always +PCIE_BOT.PCIE_PIPERX1ELECIDLE.PCIE_IMUX34_L_8 always +PCIE_BOT.PCIE_PIPERX1PHYSTATUS.PCIE_IMUX37_L_9 always +PCIE_BOT.PCIE_PIPERX1VALID.PCIE_IMUX36_L_9 always +PCIE_BOT.PCIE_PIPERX2CHANISALIGNED.PCIE_IMUX33_L_16 always +PCIE_BOT.PCIE_PIPERX2ELECIDLE.PCIE_IMUX34_L_15 always +PCIE_BOT.PCIE_PIPERX2PHYSTATUS.PCIE_IMUX37_L_16 always +PCIE_BOT.PCIE_PIPERX2VALID.PCIE_IMUX36_L_16 always +PCIE_BOT.PCIE_PIPERX3CHANISALIGNED.PCIE_IMUX33_L_5 always +PCIE_BOT.PCIE_PIPERX3ELECIDLE.PCIE_IMUX34_L_4 always +PCIE_BOT.PCIE_PIPERX3PHYSTATUS.PCIE_IMUX37_L_5 always +PCIE_BOT.PCIE_PIPERX3VALID.PCIE_IMUX36_L_5 always +PCIE_BOT.PCIE_PIPERX4ELECIDLE.PCIE_IMUX34_R_19 always +PCIE_BOT.PCIE_PIPERX5CHANISALIGNED.PCIE_IMUX33_R_9 always +PCIE_BOT.PCIE_PIPERX5ELECIDLE.PCIE_IMUX34_R_8 always +PCIE_BOT.PCIE_PIPERX5PHYSTATUS.PCIE_IMUX37_R_9 always +PCIE_BOT.PCIE_PIPERX5VALID.PCIE_IMUX36_R_9 always +PCIE_BOT.PCIE_PIPERX6CHANISALIGNED.PCIE_IMUX33_R_16 always +PCIE_BOT.PCIE_PIPERX6ELECIDLE.PCIE_IMUX34_R_15 always +PCIE_BOT.PCIE_PIPERX6PHYSTATUS.PCIE_IMUX37_R_16 always +PCIE_BOT.PCIE_PIPERX6VALID.PCIE_IMUX36_R_16 always +PCIE_BOT.PCIE_PIPERX7CHANISALIGNED.PCIE_IMUX33_R_5 always +PCIE_BOT.PCIE_PIPERX7ELECIDLE.PCIE_IMUX34_R_4 always +PCIE_BOT.PCIE_PIPERX7PHYSTATUS.PCIE_IMUX37_R_5 always +PCIE_BOT.PCIE_PIPERX7VALID.PCIE_IMUX36_R_5 always +PCIE_BOT.PCIE_PLDIRECTEDLINKAUTON.PCIE_IMUX5_L_0 always +PCIE_BOT.PCIE_PLDIRECTEDLINKSPEED.PCIE_IMUX4_L_0 always +PCIE_BOT.PCIE_PLDIRECTEDLTSSMNEWVLD.PCIE_IMUX8_L_0 always +PCIE_BOT.PCIE_PLDIRECTEDLTSSMSTALL.PCIE_IMUX2_L_1 always +PCIE_BOT.PCIE_PLDOWNSTREAMDEEMPHSOURCE.PCIE_IMUX7_L_0 always +PCIE_BOT.PCIE_PLRSTN.PCIE_CTRL0_R_3 always +PCIE_BOT.PCIE_PLTRANSMITHOTRST.PCIE_IMUX12_R_2 always +PCIE_BOT.PCIE_PLUPSTREAMPREFERDEEMPH.PCIE_IMUX6_L_0 always +PCIE_BOT.PCIE_SYSRSTN.PCIE_CTRL0_R_0 always +PCIE_BOT.PCIE_TLRSTN.PCIE_CTRL0_R_2 always +PCIE_BOT.PCIE_TRNRDSTRDY.PCIE_IMUX2_L_13 always +PCIE_BOT.PCIE_TRNRFCPRET.PCIE_IMUX0_L_14 always +PCIE_BOT.PCIE_TRNRNPOK.PCIE_IMUX1_L_14 always +PCIE_BOT.PCIE_TRNRNPREQ.PCIE_IMUX3_L_13 always +PCIE_BOT.PCIE_TRNTCFGGNT.PCIE_IMUX1_L_13 always +PCIE_BOT.PCIE_TRNTECRCGEN.PCIE_IMUX3_L_12 always +PCIE_BOT.PCIE_TRNTEOF.PCIE_IMUX3_L_11 always +PCIE_BOT.PCIE_TRNTERRFWD.PCIE_IMUX2_L_12 always +PCIE_BOT.PCIE_TRNTSOF.PCIE_IMUX2_L_11 always +PCIE_BOT.PCIE_TRNTSRCDSC.PCIE_IMUX1_L_12 always +PCIE_BOT.PCIE_TRNTSRCRDY.PCIE_IMUX0_L_12 always +PCIE_BOT.PCIE_TRNTSTR.PCIE_IMUX0_L_13 always +PCIE_BOT.PCIE_USERCLK.PCIE_CLK0_R_12 always +PCIE_BOT.PCIE_CFGAERINTERRUPTMSGNUM0.PCIE_IMUX12_L_14 always +PCIE_BOT.PCIE_CFGAERINTERRUPTMSGNUM1.PCIE_IMUX13_L_14 always +PCIE_BOT.PCIE_CFGAERINTERRUPTMSGNUM2.PCIE_IMUX14_L_14 always +PCIE_BOT.PCIE_CFGAERINTERRUPTMSGNUM3.PCIE_IMUX15_L_14 always +PCIE_BOT.PCIE_CFGAERINTERRUPTMSGNUM4.PCIE_IMUX12_L_16 always +PCIE_BOT.PCIE_CFGDSBUSNUMBER0.PCIE_IMUX14_R_12 always +PCIE_BOT.PCIE_CFGDSBUSNUMBER1.PCIE_IMUX15_R_12 always +PCIE_BOT.PCIE_CFGDSBUSNUMBER2.PCIE_IMUX16_R_12 always +PCIE_BOT.PCIE_CFGDSBUSNUMBER3.PCIE_IMUX13_R_11 always +PCIE_BOT.PCIE_CFGDSBUSNUMBER4.PCIE_IMUX14_R_11 always +PCIE_BOT.PCIE_CFGDSBUSNUMBER5.PCIE_IMUX15_R_11 always +PCIE_BOT.PCIE_CFGDSBUSNUMBER6.PCIE_IMUX16_R_11 always +PCIE_BOT.PCIE_CFGDSBUSNUMBER7.PCIE_IMUX13_R_10 always +PCIE_BOT.PCIE_CFGDSDEVICENUMBER0.PCIE_IMUX14_R_10 always +PCIE_BOT.PCIE_CFGDSDEVICENUMBER1.PCIE_IMUX15_R_10 always +PCIE_BOT.PCIE_CFGDSDEVICENUMBER2.PCIE_IMUX17_R_10 always +PCIE_BOT.PCIE_CFGDSDEVICENUMBER3.PCIE_IMUX20_R_2 always +PCIE_BOT.PCIE_CFGDSDEVICENUMBER4.PCIE_IMUX16_R_1 always +PCIE_BOT.PCIE_CFGDSFUNCTIONNUMBER0.PCIE_IMUX17_R_1 always +PCIE_BOT.PCIE_CFGDSFUNCTIONNUMBER1.PCIE_IMUX18_R_1 always +PCIE_BOT.PCIE_CFGDSFUNCTIONNUMBER2.PCIE_IMUX19_R_1 always +PCIE_BOT.PCIE_CFGDSN0.PCIE_IMUX11_L_5 always +PCIE_BOT.PCIE_CFGDSN1.PCIE_IMUX8_L_6 always +PCIE_BOT.PCIE_CFGDSN2.PCIE_IMUX9_L_6 always +PCIE_BOT.PCIE_CFGDSN3.PCIE_IMUX10_L_6 always +PCIE_BOT.PCIE_CFGDSN4.PCIE_IMUX11_L_6 always +PCIE_BOT.PCIE_CFGDSN5.PCIE_IMUX8_L_7 always +PCIE_BOT.PCIE_CFGDSN6.PCIE_IMUX9_L_7 always +PCIE_BOT.PCIE_CFGDSN7.PCIE_IMUX10_L_7 always +PCIE_BOT.PCIE_CFGDSN8.PCIE_IMUX11_L_7 always +PCIE_BOT.PCIE_CFGDSN9.PCIE_IMUX8_L_8 always +PCIE_BOT.PCIE_CFGDSN10.PCIE_IMUX9_L_8 always +PCIE_BOT.PCIE_CFGDSN11.PCIE_IMUX10_L_8 always +PCIE_BOT.PCIE_CFGDSN12.PCIE_IMUX11_L_8 always +PCIE_BOT.PCIE_CFGDSN13.PCIE_IMUX8_L_9 always +PCIE_BOT.PCIE_CFGDSN14.PCIE_IMUX9_L_9 always +PCIE_BOT.PCIE_CFGDSN15.PCIE_IMUX10_L_9 always +PCIE_BOT.PCIE_CFGDSN16.PCIE_IMUX11_L_9 always +PCIE_BOT.PCIE_CFGDSN17.PCIE_IMUX8_L_10 always +PCIE_BOT.PCIE_CFGDSN18.PCIE_IMUX9_L_10 always +PCIE_BOT.PCIE_CFGDSN19.PCIE_IMUX10_L_10 always +PCIE_BOT.PCIE_CFGDSN20.PCIE_IMUX11_L_10 always +PCIE_BOT.PCIE_CFGDSN21.PCIE_IMUX8_L_11 always +PCIE_BOT.PCIE_CFGDSN22.PCIE_IMUX9_L_11 always +PCIE_BOT.PCIE_CFGDSN23.PCIE_IMUX10_L_11 always +PCIE_BOT.PCIE_CFGDSN24.PCIE_IMUX11_L_11 always +PCIE_BOT.PCIE_CFGDSN25.PCIE_IMUX8_L_12 always +PCIE_BOT.PCIE_CFGDSN26.PCIE_IMUX9_L_12 always +PCIE_BOT.PCIE_CFGDSN27.PCIE_IMUX10_L_12 always +PCIE_BOT.PCIE_CFGDSN28.PCIE_IMUX11_L_12 always +PCIE_BOT.PCIE_CFGDSN29.PCIE_IMUX8_L_13 always +PCIE_BOT.PCIE_CFGDSN30.PCIE_IMUX9_L_13 always +PCIE_BOT.PCIE_CFGDSN31.PCIE_IMUX10_L_13 always +PCIE_BOT.PCIE_CFGDSN32.PCIE_IMUX11_L_13 always +PCIE_BOT.PCIE_CFGDSN33.PCIE_IMUX8_L_14 always +PCIE_BOT.PCIE_CFGDSN34.PCIE_IMUX9_L_14 always +PCIE_BOT.PCIE_CFGDSN35.PCIE_IMUX10_L_14 always +PCIE_BOT.PCIE_CFGDSN36.PCIE_IMUX11_L_14 always +PCIE_BOT.PCIE_CFGDSN37.PCIE_IMUX8_L_15 always +PCIE_BOT.PCIE_CFGDSN38.PCIE_IMUX9_L_15 always +PCIE_BOT.PCIE_CFGDSN39.PCIE_IMUX10_L_15 always +PCIE_BOT.PCIE_CFGDSN40.PCIE_IMUX11_L_15 always +PCIE_BOT.PCIE_CFGDSN41.PCIE_IMUX8_L_16 always +PCIE_BOT.PCIE_CFGDSN42.PCIE_IMUX9_L_16 always +PCIE_BOT.PCIE_CFGDSN43.PCIE_IMUX10_L_16 always +PCIE_BOT.PCIE_CFGDSN44.PCIE_IMUX11_L_16 always +PCIE_BOT.PCIE_CFGDSN45.PCIE_IMUX8_L_17 always +PCIE_BOT.PCIE_CFGDSN46.PCIE_IMUX9_L_17 always +PCIE_BOT.PCIE_CFGDSN47.PCIE_IMUX10_L_17 always +PCIE_BOT.PCIE_CFGDSN48.PCIE_IMUX11_L_17 always +PCIE_BOT.PCIE_CFGDSN49.PCIE_IMUX8_L_18 always +PCIE_BOT.PCIE_CFGDSN50.PCIE_IMUX9_L_18 always +PCIE_BOT.PCIE_CFGDSN51.PCIE_IMUX10_L_18 always +PCIE_BOT.PCIE_CFGDSN52.PCIE_IMUX11_L_18 always +PCIE_BOT.PCIE_CFGDSN53.PCIE_IMUX8_L_19 always +PCIE_BOT.PCIE_CFGDSN54.PCIE_IMUX9_L_19 always +PCIE_BOT.PCIE_CFGDSN55.PCIE_IMUX10_L_19 always +PCIE_BOT.PCIE_CFGDSN56.PCIE_IMUX11_L_19 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG12.PCIE_IMUX13_R_16 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG13.PCIE_IMUX14_R_16 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG14.PCIE_IMUX9_R_14 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG15.PCIE_IMUX10_R_14 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG16.PCIE_IMUX11_R_14 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG17.PCIE_IMUX12_R_14 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG18.PCIE_IMUX9_R_13 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG19.PCIE_IMUX10_R_13 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG20.PCIE_IMUX11_R_13 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG21.PCIE_IMUX12_R_13 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG22.PCIE_IMUX9_R_12 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG23.PCIE_IMUX10_R_12 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG24.PCIE_IMUX11_R_12 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG25.PCIE_IMUX12_R_12 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG26.PCIE_IMUX9_R_11 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG27.PCIE_IMUX10_R_11 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG28.PCIE_IMUX11_R_11 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG29.PCIE_IMUX12_R_11 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG30.PCIE_IMUX9_R_10 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG31.PCIE_IMUX10_R_10 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG32.PCIE_IMUX11_R_10 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG33.PCIE_IMUX12_R_10 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG34.PCIE_IMUX11_R_9 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG35.PCIE_IMUX12_R_9 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG36.PCIE_IMUX13_R_9 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG37.PCIE_IMUX14_R_9 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG38.PCIE_IMUX9_R_8 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG39.PCIE_IMUX10_R_8 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG40.PCIE_IMUX11_R_8 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG41.PCIE_IMUX12_R_8 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG42.PCIE_IMUX14_R_7 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG43.PCIE_IMUX15_R_7 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG44.PCIE_IMUX16_R_7 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG45.PCIE_IMUX17_R_7 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG46.PCIE_IMUX13_R_6 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG47.PCIE_IMUX14_R_6 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG48.PCIE_IMUX15_R_6 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG49.PCIE_IMUX17_R_6 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG50.PCIE_IMUX11_R_5 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG51.PCIE_IMUX12_R_5 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG52.PCIE_IMUX13_R_5 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG53.PCIE_IMUX14_R_5 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG54.PCIE_IMUX8_R_4 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG55.PCIE_IMUX9_R_4 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG56.PCIE_IMUX10_R_4 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG57.PCIE_IMUX11_R_4 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG58.PCIE_IMUX13_R_3 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG59.PCIE_IMUX14_R_3 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG60.PCIE_IMUX15_R_3 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG61.PCIE_IMUX16_R_3 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG62.PCIE_IMUX16_R_2 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG63.PCIE_IMUX17_R_2 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG64.PCIE_IMUX18_R_2 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG65.PCIE_IMUX19_R_2 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG66.PCIE_IMUX12_R_1 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG67.PCIE_IMUX13_R_1 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG68.PCIE_IMUX14_R_1 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG69.PCIE_IMUX15_R_1 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG70.PCIE_IMUX12_R_0 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG71.PCIE_IMUX13_R_0 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG72.PCIE_IMUX14_R_0 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG73.PCIE_IMUX15_R_0 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG74.PCIE_IMUX13_L_0 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG75.PCIE_IMUX14_L_0 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG76.PCIE_IMUX15_L_0 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG77.PCIE_IMUX16_L_0 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG78.PCIE_IMUX4_L_1 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG79.PCIE_IMUX5_L_1 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG80.PCIE_IMUX6_L_1 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG81.PCIE_IMUX7_L_1 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG82.PCIE_IMUX4_L_2 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG83.PCIE_IMUX5_L_2 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG84.PCIE_IMUX6_L_2 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG85.PCIE_IMUX7_L_2 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG86.PCIE_IMUX4_L_3 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG87.PCIE_IMUX5_L_3 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG88.PCIE_IMUX6_L_3 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG89.PCIE_IMUX7_L_3 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG90.PCIE_IMUX4_L_4 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG91.PCIE_IMUX5_L_4 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG92.PCIE_IMUX6_L_4 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG93.PCIE_IMUX7_L_4 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG94.PCIE_IMUX4_L_5 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG95.PCIE_IMUX5_L_5 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG96.PCIE_IMUX6_L_5 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG97.PCIE_IMUX7_L_5 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG98.PCIE_IMUX4_L_6 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG99.PCIE_IMUX5_L_6 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG100.PCIE_IMUX6_L_6 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG101.PCIE_IMUX7_L_6 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG102.PCIE_IMUX4_L_7 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG103.PCIE_IMUX5_L_7 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG104.PCIE_IMUX6_L_7 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG105.PCIE_IMUX7_L_7 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG106.PCIE_IMUX4_L_8 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG107.PCIE_IMUX5_L_8 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG108.PCIE_IMUX6_L_8 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG109.PCIE_IMUX7_L_8 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG110.PCIE_IMUX4_L_9 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG111.PCIE_IMUX5_L_9 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG112.PCIE_IMUX6_L_9 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG113.PCIE_IMUX7_L_9 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG114.PCIE_IMUX4_L_10 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG115.PCIE_IMUX5_L_10 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG116.PCIE_IMUX6_L_10 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG117.PCIE_IMUX7_L_10 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG118.PCIE_IMUX4_L_11 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG119.PCIE_IMUX5_L_11 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG120.PCIE_IMUX6_L_11 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG121.PCIE_IMUX7_L_11 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG122.PCIE_IMUX4_L_12 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG123.PCIE_IMUX5_L_12 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG124.PCIE_IMUX6_L_12 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG125.PCIE_IMUX7_L_12 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG126.PCIE_IMUX4_L_13 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG127.PCIE_IMUX5_L_13 always +PCIE_BOT.PCIE_CFGERRTLPCPLHEADER0.PCIE_IMUX6_L_13 always +PCIE_BOT.PCIE_CFGERRTLPCPLHEADER1.PCIE_IMUX7_L_13 always +PCIE_BOT.PCIE_CFGERRTLPCPLHEADER2.PCIE_IMUX4_L_14 always +PCIE_BOT.PCIE_CFGERRTLPCPLHEADER3.PCIE_IMUX5_L_14 always +PCIE_BOT.PCIE_CFGERRTLPCPLHEADER4.PCIE_IMUX6_L_14 always +PCIE_BOT.PCIE_CFGERRTLPCPLHEADER5.PCIE_IMUX7_L_14 always +PCIE_BOT.PCIE_CFGERRTLPCPLHEADER6.PCIE_IMUX4_L_15 always +PCIE_BOT.PCIE_CFGERRTLPCPLHEADER7.PCIE_IMUX5_L_15 always +PCIE_BOT.PCIE_CFGERRTLPCPLHEADER8.PCIE_IMUX6_L_15 always +PCIE_BOT.PCIE_CFGERRTLPCPLHEADER9.PCIE_IMUX7_L_15 always +PCIE_BOT.PCIE_CFGERRTLPCPLHEADER10.PCIE_IMUX4_L_16 always +PCIE_BOT.PCIE_CFGERRTLPCPLHEADER11.PCIE_IMUX5_L_16 always +PCIE_BOT.PCIE_CFGERRTLPCPLHEADER12.PCIE_IMUX6_L_16 always +PCIE_BOT.PCIE_CFGERRTLPCPLHEADER13.PCIE_IMUX7_L_16 always +PCIE_BOT.PCIE_CFGERRTLPCPLHEADER14.PCIE_IMUX4_L_17 always +PCIE_BOT.PCIE_CFGERRTLPCPLHEADER15.PCIE_IMUX5_L_17 always +PCIE_BOT.PCIE_CFGERRTLPCPLHEADER16.PCIE_IMUX6_L_17 always +PCIE_BOT.PCIE_CFGERRTLPCPLHEADER17.PCIE_IMUX7_L_17 always +PCIE_BOT.PCIE_CFGERRTLPCPLHEADER18.PCIE_IMUX4_L_18 always +PCIE_BOT.PCIE_CFGERRTLPCPLHEADER19.PCIE_IMUX5_L_18 always +PCIE_BOT.PCIE_CFGERRTLPCPLHEADER20.PCIE_IMUX6_L_18 always +PCIE_BOT.PCIE_CFGERRTLPCPLHEADER21.PCIE_IMUX7_L_18 always +PCIE_BOT.PCIE_CFGERRTLPCPLHEADER22.PCIE_IMUX4_L_19 always +PCIE_BOT.PCIE_CFGERRTLPCPLHEADER23.PCIE_IMUX5_L_19 always +PCIE_BOT.PCIE_CFGERRTLPCPLHEADER24.PCIE_IMUX6_L_19 always +PCIE_BOT.PCIE_CFGERRTLPCPLHEADER25.PCIE_IMUX7_L_19 always +PCIE_BOT.PCIE_CFGFORCEMPS0.PCIE_IMUX10_L_4 always +PCIE_BOT.PCIE_CFGFORCEMPS1.PCIE_IMUX11_L_4 always +PCIE_BOT.PCIE_CFGFORCEMPS2.PCIE_IMUX8_L_5 always +PCIE_BOT.PCIE_CFGINTERRUPTDI1.PCIE_IMUX13_R_14 always +PCIE_BOT.PCIE_CFGINTERRUPTDI2.PCIE_IMUX14_R_14 always +PCIE_BOT.PCIE_CFGINTERRUPTDI3.PCIE_IMUX15_R_14 always +PCIE_BOT.PCIE_CFGINTERRUPTDI4.PCIE_IMUX16_R_14 always +PCIE_BOT.PCIE_CFGINTERRUPTDI5.PCIE_IMUX13_R_13 always +PCIE_BOT.PCIE_CFGINTERRUPTDI6.PCIE_IMUX14_R_13 always +PCIE_BOT.PCIE_CFGINTERRUPTDI7.PCIE_IMUX15_R_13 always +PCIE_BOT.PCIE_CFGMGMTBYTEENN0.PCIE_IMUX6_R_10 always +PCIE_BOT.PCIE_CFGMGMTBYTEENN1.PCIE_IMUX7_R_10 always +PCIE_BOT.PCIE_CFGMGMTBYTEENN2.PCIE_IMUX8_R_10 always +PCIE_BOT.PCIE_CFGMGMTBYTEENN3.PCIE_IMUX5_R_11 always +PCIE_BOT.PCIE_CFGMGMTDI0.PCIE_IMUX13_R_2 always +PCIE_BOT.PCIE_CFGMGMTDI1.PCIE_IMUX14_R_2 always +PCIE_BOT.PCIE_CFGMGMTDI2.PCIE_IMUX15_R_2 always +PCIE_BOT.PCIE_CFGMGMTDI3.PCIE_IMUX9_R_3 always +PCIE_BOT.PCIE_CFGMGMTDI4.PCIE_IMUX10_R_3 always +PCIE_BOT.PCIE_CFGMGMTDI5.PCIE_IMUX11_R_3 always +PCIE_BOT.PCIE_CFGMGMTDI6.PCIE_IMUX12_R_3 always +PCIE_BOT.PCIE_CFGMGMTDI7.PCIE_IMUX4_R_4 always +PCIE_BOT.PCIE_CFGMGMTDI8.PCIE_IMUX5_R_4 always +PCIE_BOT.PCIE_CFGMGMTDI9.PCIE_IMUX6_R_4 always +PCIE_BOT.PCIE_CFGMGMTDI10.PCIE_IMUX7_R_4 always +PCIE_BOT.PCIE_CFGMGMTDI11.PCIE_IMUX7_R_5 always +PCIE_BOT.PCIE_CFGMGMTDI12.PCIE_IMUX8_R_5 always +PCIE_BOT.PCIE_CFGMGMTDI13.PCIE_IMUX9_R_5 always +PCIE_BOT.PCIE_CFGMGMTDI14.PCIE_IMUX10_R_5 always +PCIE_BOT.PCIE_CFGMGMTDI15.PCIE_IMUX9_R_6 always +PCIE_BOT.PCIE_CFGMGMTDI16.PCIE_IMUX10_R_6 always +PCIE_BOT.PCIE_CFGMGMTDI17.PCIE_IMUX11_R_6 always +PCIE_BOT.PCIE_CFGMGMTDI18.PCIE_IMUX12_R_6 always +PCIE_BOT.PCIE_CFGMGMTDI19.PCIE_IMUX10_R_7 always +PCIE_BOT.PCIE_CFGMGMTDI20.PCIE_IMUX11_R_7 always +PCIE_BOT.PCIE_CFGMGMTDI21.PCIE_IMUX12_R_7 always +PCIE_BOT.PCIE_CFGMGMTDI22.PCIE_IMUX13_R_7 always +PCIE_BOT.PCIE_CFGMGMTDI23.PCIE_IMUX5_R_8 always +PCIE_BOT.PCIE_CFGMGMTDI24.PCIE_IMUX6_R_8 always +PCIE_BOT.PCIE_CFGMGMTDI25.PCIE_IMUX7_R_8 always +PCIE_BOT.PCIE_CFGMGMTDI26.PCIE_IMUX8_R_8 always +PCIE_BOT.PCIE_CFGMGMTDI27.PCIE_IMUX7_R_9 always +PCIE_BOT.PCIE_CFGMGMTDI28.PCIE_IMUX8_R_9 always +PCIE_BOT.PCIE_CFGMGMTDI29.PCIE_IMUX9_R_9 always +PCIE_BOT.PCIE_CFGMGMTDI30.PCIE_IMUX10_R_9 always +PCIE_BOT.PCIE_CFGMGMTDI31.PCIE_IMUX5_R_10 always +PCIE_BOT.PCIE_CFGMGMTDWADDR0.PCIE_IMUX6_R_11 always +PCIE_BOT.PCIE_CFGMGMTDWADDR1.PCIE_IMUX7_R_11 always +PCIE_BOT.PCIE_CFGMGMTDWADDR2.PCIE_IMUX8_R_11 always +PCIE_BOT.PCIE_CFGMGMTDWADDR3.PCIE_IMUX5_R_12 always +PCIE_BOT.PCIE_CFGMGMTDWADDR4.PCIE_IMUX6_R_12 always +PCIE_BOT.PCIE_CFGMGMTDWADDR5.PCIE_IMUX7_R_12 always +PCIE_BOT.PCIE_CFGMGMTDWADDR6.PCIE_IMUX8_R_12 always +PCIE_BOT.PCIE_CFGMGMTDWADDR7.PCIE_IMUX5_R_13 always +PCIE_BOT.PCIE_CFGMGMTDWADDR8.PCIE_IMUX6_R_13 always +PCIE_BOT.PCIE_CFGMGMTDWADDR9.PCIE_IMUX7_R_13 always +PCIE_BOT.PCIE_CFGPCIECAPINTERRUPTMSGNUM0.PCIE_IMUX8_L_3 always +PCIE_BOT.PCIE_CFGPCIECAPINTERRUPTMSGNUM1.PCIE_IMUX9_L_3 always +PCIE_BOT.PCIE_CFGPCIECAPINTERRUPTMSGNUM2.PCIE_IMUX10_L_3 always +PCIE_BOT.PCIE_CFGPCIECAPINTERRUPTMSGNUM3.PCIE_IMUX11_L_3 always +PCIE_BOT.PCIE_CFGPCIECAPINTERRUPTMSGNUM4.PCIE_IMUX8_L_4 always +PCIE_BOT.PCIE_CFGPMFORCESTATE0.PCIE_IMUX11_L_1 always +PCIE_BOT.PCIE_CFGPMFORCESTATE1.PCIE_IMUX8_L_2 always +PCIE_BOT.PCIE_CFGPORTNUMBER0.PCIE_IMUX16_R_0 always +PCIE_BOT.PCIE_CFGPORTNUMBER1.PCIE_IMUX17_R_0 always +PCIE_BOT.PCIE_CFGPORTNUMBER2.PCIE_IMUX18_R_0 always +PCIE_BOT.PCIE_CFGPORTNUMBER3.PCIE_IMUX19_R_0 always +PCIE_BOT.PCIE_CFGPORTNUMBER4.PCIE_IMUX17_L_0 always +PCIE_BOT.PCIE_CFGPORTNUMBER5.PCIE_IMUX18_L_0 always +PCIE_BOT.PCIE_CFGPORTNUMBER6.PCIE_IMUX19_L_0 always +PCIE_BOT.PCIE_CFGPORTNUMBER7.PCIE_IMUX20_L_0 always +PCIE_BOT.PCIE_CFGREVID0.PCIE_IMUX12_L_1 always +PCIE_BOT.PCIE_CFGREVID1.PCIE_IMUX13_L_1 always +PCIE_BOT.PCIE_CFGREVID2.PCIE_IMUX14_L_1 always +PCIE_BOT.PCIE_CFGREVID3.PCIE_IMUX15_L_1 always +PCIE_BOT.PCIE_CFGREVID4.PCIE_IMUX12_L_2 always +PCIE_BOT.PCIE_CFGREVID5.PCIE_IMUX13_L_2 always +PCIE_BOT.PCIE_CFGREVID6.PCIE_IMUX14_L_2 always +PCIE_BOT.PCIE_CFGREVID7.PCIE_IMUX15_L_2 always +PCIE_BOT.PCIE_CFGSUBSYSID0.PCIE_IMUX12_L_3 always +PCIE_BOT.PCIE_CFGSUBSYSID1.PCIE_IMUX13_L_3 always +PCIE_BOT.PCIE_CFGSUBSYSID2.PCIE_IMUX14_L_3 always +PCIE_BOT.PCIE_CFGSUBSYSID3.PCIE_IMUX15_L_3 always +PCIE_BOT.PCIE_CFGSUBSYSID4.PCIE_IMUX12_L_5 always +PCIE_BOT.PCIE_CFGSUBSYSID5.PCIE_IMUX13_L_5 always +PCIE_BOT.PCIE_CFGSUBSYSID6.PCIE_IMUX12_L_6 always +PCIE_BOT.PCIE_CFGSUBSYSID7.PCIE_IMUX13_L_6 always +PCIE_BOT.PCIE_CFGSUBSYSID8.PCIE_IMUX14_L_6 always +PCIE_BOT.PCIE_CFGSUBSYSID9.PCIE_IMUX15_L_6 always +PCIE_BOT.PCIE_CFGSUBSYSID10.PCIE_IMUX12_L_7 always +PCIE_BOT.PCIE_CFGSUBSYSID11.PCIE_IMUX13_L_7 always +PCIE_BOT.PCIE_CFGSUBSYSID12.PCIE_IMUX14_L_7 always +PCIE_BOT.PCIE_CFGSUBSYSID13.PCIE_IMUX15_L_7 always +PCIE_BOT.PCIE_CFGSUBSYSID14.PCIE_IMUX12_L_9 always +PCIE_BOT.PCIE_CFGSUBSYSID15.PCIE_IMUX13_L_9 always +PCIE_BOT.PCIE_CFGSUBSYSVENDID0.PCIE_IMUX12_L_10 always +PCIE_BOT.PCIE_CFGSUBSYSVENDID1.PCIE_IMUX13_L_10 always +PCIE_BOT.PCIE_CFGSUBSYSVENDID2.PCIE_IMUX14_L_10 always +PCIE_BOT.PCIE_CFGSUBSYSVENDID3.PCIE_IMUX15_L_10 always +PCIE_BOT.PCIE_CFGSUBSYSVENDID4.PCIE_IMUX12_L_11 always +PCIE_BOT.PCIE_CFGSUBSYSVENDID5.PCIE_IMUX13_L_11 always +PCIE_BOT.PCIE_CFGSUBSYSVENDID6.PCIE_IMUX14_L_11 always +PCIE_BOT.PCIE_CFGSUBSYSVENDID7.PCIE_IMUX15_L_11 always +PCIE_BOT.PCIE_CFGSUBSYSVENDID8.PCIE_IMUX12_L_12 always +PCIE_BOT.PCIE_CFGSUBSYSVENDID9.PCIE_IMUX13_L_12 always +PCIE_BOT.PCIE_CFGSUBSYSVENDID10.PCIE_IMUX14_L_12 always +PCIE_BOT.PCIE_CFGSUBSYSVENDID11.PCIE_IMUX15_L_12 always +PCIE_BOT.PCIE_CFGSUBSYSVENDID12.PCIE_IMUX12_L_13 always +PCIE_BOT.PCIE_CFGSUBSYSVENDID13.PCIE_IMUX13_L_13 always +PCIE_BOT.PCIE_CFGSUBSYSVENDID14.PCIE_IMUX14_L_13 always +PCIE_BOT.PCIE_CFGSUBSYSVENDID15.PCIE_IMUX15_L_13 always +PCIE_BOT.PCIE_CFGVENDID1.PCIE_IMUX17_R_14 always +PCIE_BOT.PCIE_CFGVENDID2.PCIE_IMUX17_R_13 always +PCIE_BOT.PCIE_CFGVENDID3.PCIE_IMUX18_R_13 always +PCIE_BOT.PCIE_CFGVENDID4.PCIE_IMUX19_R_13 always +PCIE_BOT.PCIE_CFGVENDID5.PCIE_IMUX20_R_13 always +PCIE_BOT.PCIE_CFGVENDID6.PCIE_IMUX17_R_12 always +PCIE_BOT.PCIE_CFGVENDID7.PCIE_IMUX18_R_12 always +PCIE_BOT.PCIE_CFGVENDID8.PCIE_IMUX19_R_12 always +PCIE_BOT.PCIE_CFGVENDID9.PCIE_IMUX20_R_12 always +PCIE_BOT.PCIE_CFGVENDID10.PCIE_IMUX17_R_11 always +PCIE_BOT.PCIE_CFGVENDID11.PCIE_IMUX18_R_11 always +PCIE_BOT.PCIE_CFGVENDID12.PCIE_IMUX19_R_11 always +PCIE_BOT.PCIE_CFGVENDID13.PCIE_IMUX20_R_11 always +PCIE_BOT.PCIE_CFGVENDID14.PCIE_IMUX20_R_1 always +PCIE_BOT.PCIE_CFGVENDID15.PCIE_IMUX20_R_0 always +PCIE_BOT.PCIE_DBGMODE1.PCIE_IMUX21_R_13 always +PCIE_BOT.PCIE_DRPADDR0.PCIE_IMUX13_L_17 always +PCIE_BOT.PCIE_DRPADDR1.PCIE_IMUX14_L_17 always +PCIE_BOT.PCIE_DRPADDR2.PCIE_IMUX15_L_17 always +PCIE_BOT.PCIE_DRPADDR3.PCIE_IMUX12_L_18 always +PCIE_BOT.PCIE_DRPADDR4.PCIE_IMUX13_L_18 always +PCIE_BOT.PCIE_DRPADDR5.PCIE_IMUX14_L_18 always +PCIE_BOT.PCIE_DRPADDR6.PCIE_IMUX15_L_18 always +PCIE_BOT.PCIE_MIMRXRDATA0.PCIE_IMUX0_R_15 always +PCIE_BOT.PCIE_MIMRXRDATA1.PCIE_IMUX1_R_15 always +PCIE_BOT.PCIE_MIMRXRDATA2.PCIE_IMUX2_R_15 always +PCIE_BOT.PCIE_MIMRXRDATA3.PCIE_IMUX3_R_15 always +PCIE_BOT.PCIE_MIMRXRDATA4.PCIE_IMUX0_R_16 always +PCIE_BOT.PCIE_MIMRXRDATA5.PCIE_IMUX1_R_16 always +PCIE_BOT.PCIE_MIMRXRDATA6.PCIE_IMUX2_R_16 always +PCIE_BOT.PCIE_MIMRXRDATA7.PCIE_IMUX3_R_16 always +PCIE_BOT.PCIE_MIMRXRDATA8.PCIE_IMUX0_R_17 always +PCIE_BOT.PCIE_MIMRXRDATA9.PCIE_IMUX1_R_17 always +PCIE_BOT.PCIE_MIMRXRDATA10.PCIE_IMUX2_R_17 always +PCIE_BOT.PCIE_MIMRXRDATA11.PCIE_IMUX3_R_17 always +PCIE_BOT.PCIE_MIMRXRDATA12.PCIE_IMUX0_R_18 always +PCIE_BOT.PCIE_MIMRXRDATA13.PCIE_IMUX1_R_18 always +PCIE_BOT.PCIE_MIMRXRDATA14.PCIE_IMUX2_R_18 always +PCIE_BOT.PCIE_MIMRXRDATA15.PCIE_IMUX3_R_18 always +PCIE_BOT.PCIE_MIMRXRDATA16.PCIE_IMUX0_R_19 always +PCIE_BOT.PCIE_MIMRXRDATA17.PCIE_IMUX1_R_19 always +PCIE_BOT.PCIE_MIMRXRDATA18.PCIE_IMUX2_R_19 always +PCIE_BOT.PCIE_MIMRXRDATA19.PCIE_IMUX3_R_19 always +PCIE_BOT.PCIE_MIMRXRDATA56.PCIE_IMUX4_R_19 always +PCIE_BOT.PCIE_MIMRXRDATA57.PCIE_IMUX5_R_19 always +PCIE_BOT.PCIE_MIMRXRDATA58.PCIE_IMUX6_R_19 always +PCIE_BOT.PCIE_MIMRXRDATA59.PCIE_IMUX7_R_19 always +PCIE_BOT.PCIE_MIMRXRDATA60.PCIE_IMUX4_R_18 always +PCIE_BOT.PCIE_MIMRXRDATA61.PCIE_IMUX5_R_18 always +PCIE_BOT.PCIE_MIMRXRDATA62.PCIE_IMUX6_R_18 always +PCIE_BOT.PCIE_MIMRXRDATA63.PCIE_IMUX7_R_18 always +PCIE_BOT.PCIE_MIMRXRDATA64.PCIE_IMUX4_R_17 always +PCIE_BOT.PCIE_MIMRXRDATA65.PCIE_IMUX5_R_17 always +PCIE_BOT.PCIE_MIMRXRDATA66.PCIE_IMUX6_R_17 always +PCIE_BOT.PCIE_MIMRXRDATA67.PCIE_IMUX7_R_17 always +PCIE_BOT.PCIE_MIMTXRDATA0.PCIE_IMUX0_R_0 always +PCIE_BOT.PCIE_MIMTXRDATA1.PCIE_IMUX1_R_0 always +PCIE_BOT.PCIE_MIMTXRDATA2.PCIE_IMUX2_R_0 always +PCIE_BOT.PCIE_MIMTXRDATA3.PCIE_IMUX3_R_0 always +PCIE_BOT.PCIE_MIMTXRDATA4.PCIE_IMUX0_R_1 always +PCIE_BOT.PCIE_MIMTXRDATA5.PCIE_IMUX1_R_1 always +PCIE_BOT.PCIE_MIMTXRDATA6.PCIE_IMUX2_R_1 always +PCIE_BOT.PCIE_MIMTXRDATA7.PCIE_IMUX3_R_1 always +PCIE_BOT.PCIE_MIMTXRDATA8.PCIE_IMUX0_R_2 always +PCIE_BOT.PCIE_MIMTXRDATA9.PCIE_IMUX1_R_2 always +PCIE_BOT.PCIE_MIMTXRDATA10.PCIE_IMUX2_R_2 always +PCIE_BOT.PCIE_MIMTXRDATA11.PCIE_IMUX3_R_2 always +PCIE_BOT.PCIE_MIMTXRDATA12.PCIE_IMUX0_R_3 always +PCIE_BOT.PCIE_MIMTXRDATA13.PCIE_IMUX1_R_3 always +PCIE_BOT.PCIE_MIMTXRDATA14.PCIE_IMUX2_R_3 always +PCIE_BOT.PCIE_MIMTXRDATA15.PCIE_IMUX3_R_3 always +PCIE_BOT.PCIE_MIMTXRDATA16.PCIE_IMUX0_R_4 always +PCIE_BOT.PCIE_MIMTXRDATA17.PCIE_IMUX1_R_4 always +PCIE_BOT.PCIE_MIMTXRDATA18.PCIE_IMUX2_R_4 always +PCIE_BOT.PCIE_MIMTXRDATA19.PCIE_IMUX3_R_4 always +PCIE_BOT.PCIE_MIMTXRDATA20.PCIE_IMUX0_R_5 always +PCIE_BOT.PCIE_MIMTXRDATA21.PCIE_IMUX1_R_5 always +PCIE_BOT.PCIE_MIMTXRDATA22.PCIE_IMUX2_R_5 always +PCIE_BOT.PCIE_MIMTXRDATA23.PCIE_IMUX3_R_5 always +PCIE_BOT.PCIE_MIMTXRDATA24.PCIE_IMUX0_R_6 always +PCIE_BOT.PCIE_MIMTXRDATA25.PCIE_IMUX1_R_6 always +PCIE_BOT.PCIE_MIMTXRDATA26.PCIE_IMUX2_R_6 always +PCIE_BOT.PCIE_MIMTXRDATA27.PCIE_IMUX3_R_6 always +PCIE_BOT.PCIE_MIMTXRDATA28.PCIE_IMUX0_R_7 always +PCIE_BOT.PCIE_MIMTXRDATA29.PCIE_IMUX1_R_7 always +PCIE_BOT.PCIE_MIMTXRDATA30.PCIE_IMUX2_R_7 always +PCIE_BOT.PCIE_MIMTXRDATA31.PCIE_IMUX3_R_7 always +PCIE_BOT.PCIE_MIMTXRDATA32.PCIE_IMUX0_R_8 always +PCIE_BOT.PCIE_MIMTXRDATA33.PCIE_IMUX1_R_8 always +PCIE_BOT.PCIE_MIMTXRDATA34.PCIE_IMUX2_R_8 always +PCIE_BOT.PCIE_MIMTXRDATA35.PCIE_IMUX3_R_8 always +PCIE_BOT.PCIE_MIMTXRDATA36.PCIE_IMUX0_R_9 always +PCIE_BOT.PCIE_MIMTXRDATA37.PCIE_IMUX1_R_9 always +PCIE_BOT.PCIE_MIMTXRDATA38.PCIE_IMUX2_R_9 always +PCIE_BOT.PCIE_MIMTXRDATA39.PCIE_IMUX3_R_9 always +PCIE_BOT.PCIE_MIMTXRDATA40.PCIE_IMUX4_R_7 always +PCIE_BOT.PCIE_MIMTXRDATA41.PCIE_IMUX5_R_7 always +PCIE_BOT.PCIE_MIMTXRDATA42.PCIE_IMUX6_R_7 always +PCIE_BOT.PCIE_MIMTXRDATA43.PCIE_IMUX7_R_7 always +PCIE_BOT.PCIE_MIMTXRDATA44.PCIE_IMUX4_R_6 always +PCIE_BOT.PCIE_MIMTXRDATA45.PCIE_IMUX5_R_6 always +PCIE_BOT.PCIE_MIMTXRDATA46.PCIE_IMUX6_R_6 always +PCIE_BOT.PCIE_MIMTXRDATA47.PCIE_IMUX7_R_6 always +PCIE_BOT.PCIE_MIMTXRDATA48.PCIE_IMUX4_R_5 always +PCIE_BOT.PCIE_MIMTXRDATA49.PCIE_IMUX5_R_5 always +PCIE_BOT.PCIE_MIMTXRDATA50.PCIE_IMUX4_R_3 always +PCIE_BOT.PCIE_MIMTXRDATA51.PCIE_IMUX5_R_3 always +PCIE_BOT.PCIE_MIMTXRDATA52.PCIE_IMUX6_R_3 always +PCIE_BOT.PCIE_MIMTXRDATA53.PCIE_IMUX7_R_3 always +PCIE_BOT.PCIE_MIMTXRDATA54.PCIE_IMUX4_R_2 always +PCIE_BOT.PCIE_MIMTXRDATA55.PCIE_IMUX5_R_2 always +PCIE_BOT.PCIE_MIMTXRDATA56.PCIE_IMUX6_R_2 always +PCIE_BOT.PCIE_MIMTXRDATA57.PCIE_IMUX7_R_2 always +PCIE_BOT.PCIE_MIMTXRDATA58.PCIE_IMUX4_R_1 always +PCIE_BOT.PCIE_MIMTXRDATA59.PCIE_IMUX5_R_1 always +PCIE_BOT.PCIE_MIMTXRDATA60.PCIE_IMUX6_R_1 always +PCIE_BOT.PCIE_MIMTXRDATA61.PCIE_IMUX7_R_1 always +PCIE_BOT.PCIE_MIMTXRDATA62.PCIE_IMUX4_R_0 always +PCIE_BOT.PCIE_MIMTXRDATA63.PCIE_IMUX5_R_0 always +PCIE_BOT.PCIE_MIMTXRDATA64.PCIE_IMUX6_R_0 always +PCIE_BOT.PCIE_MIMTXRDATA65.PCIE_IMUX7_R_0 always +PCIE_BOT.PCIE_MIMTXRDATA66.PCIE_IMUX4_R_9 always +PCIE_BOT.PCIE_MIMTXRDATA67.PCIE_IMUX5_R_9 always +PCIE_BOT.PCIE_MIMTXRDATA68.PCIE_IMUX8_R_7 always +PCIE_BOT.PCIE_PIPERX0CHARISK1.PCIE_IMUX16_L_19 always +PCIE_BOT.PCIE_PIPERX0DATA8.PCIE_IMUX37_L_19 always +PCIE_BOT.PCIE_PIPERX0DATA9.PCIE_IMUX36_L_19 always +PCIE_BOT.PCIE_PIPERX0DATA10.PCIE_IMUX33_L_19 always +PCIE_BOT.PCIE_PIPERX0DATA11.PCIE_IMUX32_L_19 always +PCIE_BOT.PCIE_PIPERX0DATA12.PCIE_IMUX39_L_18 always +PCIE_BOT.PCIE_PIPERX0DATA13.PCIE_IMUX38_L_18 always +PCIE_BOT.PCIE_PIPERX0DATA14.PCIE_IMUX35_L_18 always +PCIE_BOT.PCIE_PIPERX0DATA15.PCIE_IMUX34_L_18 always +PCIE_BOT.PCIE_PIPERX0STATUS0.PCIE_IMUX39_L_19 always +PCIE_BOT.PCIE_PIPERX0STATUS1.PCIE_IMUX38_L_19 always +PCIE_BOT.PCIE_PIPERX0STATUS2.PCIE_IMUX35_L_19 always +PCIE_BOT.PCIE_PIPERX1CHARISK0.PCIE_IMUX16_L_10 always +PCIE_BOT.PCIE_PIPERX1CHARISK1.PCIE_IMUX16_L_8 always +PCIE_BOT.PCIE_PIPERX1DATA0.PCIE_IMUX37_L_10 always +PCIE_BOT.PCIE_PIPERX1DATA1.PCIE_IMUX36_L_10 always +PCIE_BOT.PCIE_PIPERX1DATA2.PCIE_IMUX33_L_10 always +PCIE_BOT.PCIE_PIPERX1DATA3.PCIE_IMUX32_L_10 always +PCIE_BOT.PCIE_PIPERX1DATA4.PCIE_IMUX39_L_9 always +PCIE_BOT.PCIE_PIPERX1DATA5.PCIE_IMUX38_L_9 always +PCIE_BOT.PCIE_PIPERX1DATA6.PCIE_IMUX35_L_9 always +PCIE_BOT.PCIE_PIPERX1DATA7.PCIE_IMUX34_L_9 always +PCIE_BOT.PCIE_PIPERX1DATA8.PCIE_IMUX37_L_8 always +PCIE_BOT.PCIE_PIPERX1DATA9.PCIE_IMUX36_L_8 always +PCIE_BOT.PCIE_PIPERX1DATA10.PCIE_IMUX33_L_8 always +PCIE_BOT.PCIE_PIPERX1DATA11.PCIE_IMUX32_L_8 always +PCIE_BOT.PCIE_PIPERX1DATA12.PCIE_IMUX39_L_7 always +PCIE_BOT.PCIE_PIPERX1DATA13.PCIE_IMUX38_L_7 always +PCIE_BOT.PCIE_PIPERX1DATA14.PCIE_IMUX35_L_7 always +PCIE_BOT.PCIE_PIPERX1DATA15.PCIE_IMUX34_L_7 always +PCIE_BOT.PCIE_PIPERX1STATUS0.PCIE_IMUX39_L_8 always +PCIE_BOT.PCIE_PIPERX1STATUS1.PCIE_IMUX38_L_8 always +PCIE_BOT.PCIE_PIPERX1STATUS2.PCIE_IMUX35_L_8 always +PCIE_BOT.PCIE_PIPERX2CHARISK0.PCIE_IMUX16_L_17 always +PCIE_BOT.PCIE_PIPERX2CHARISK1.PCIE_IMUX16_L_15 always +PCIE_BOT.PCIE_PIPERX2DATA0.PCIE_IMUX37_L_17 always +PCIE_BOT.PCIE_PIPERX2DATA1.PCIE_IMUX36_L_17 always +PCIE_BOT.PCIE_PIPERX2DATA2.PCIE_IMUX33_L_17 always +PCIE_BOT.PCIE_PIPERX2DATA3.PCIE_IMUX32_L_17 always +PCIE_BOT.PCIE_PIPERX2DATA4.PCIE_IMUX39_L_16 always +PCIE_BOT.PCIE_PIPERX2DATA5.PCIE_IMUX38_L_16 always +PCIE_BOT.PCIE_PIPERX2DATA6.PCIE_IMUX35_L_16 always +PCIE_BOT.PCIE_PIPERX2DATA7.PCIE_IMUX34_L_16 always +PCIE_BOT.PCIE_PIPERX2DATA8.PCIE_IMUX37_L_15 always +PCIE_BOT.PCIE_PIPERX2DATA9.PCIE_IMUX36_L_15 always +PCIE_BOT.PCIE_PIPERX2DATA10.PCIE_IMUX33_L_15 always +PCIE_BOT.PCIE_PIPERX2DATA11.PCIE_IMUX32_L_15 always +PCIE_BOT.PCIE_PIPERX2DATA12.PCIE_IMUX39_L_14 always +PCIE_BOT.PCIE_PIPERX2DATA13.PCIE_IMUX38_L_14 always +PCIE_BOT.PCIE_PIPERX2DATA14.PCIE_IMUX35_L_14 always +PCIE_BOT.PCIE_PIPERX2DATA15.PCIE_IMUX34_L_14 always +PCIE_BOT.PCIE_PIPERX2STATUS0.PCIE_IMUX39_L_15 always +PCIE_BOT.PCIE_PIPERX2STATUS1.PCIE_IMUX38_L_15 always +PCIE_BOT.PCIE_PIPERX2STATUS2.PCIE_IMUX35_L_15 always +PCIE_BOT.PCIE_PIPERX3CHARISK0.PCIE_IMUX16_L_6 always +PCIE_BOT.PCIE_PIPERX3CHARISK1.PCIE_IMUX16_L_4 always +PCIE_BOT.PCIE_PIPERX3DATA0.PCIE_IMUX37_L_6 always +PCIE_BOT.PCIE_PIPERX3DATA1.PCIE_IMUX36_L_6 always +PCIE_BOT.PCIE_PIPERX3DATA2.PCIE_IMUX33_L_6 always +PCIE_BOT.PCIE_PIPERX3DATA3.PCIE_IMUX32_L_6 always +PCIE_BOT.PCIE_PIPERX3DATA4.PCIE_IMUX39_L_5 always +PCIE_BOT.PCIE_PIPERX3DATA5.PCIE_IMUX38_L_5 always +PCIE_BOT.PCIE_PIPERX3DATA6.PCIE_IMUX35_L_5 always +PCIE_BOT.PCIE_PIPERX3DATA7.PCIE_IMUX34_L_5 always +PCIE_BOT.PCIE_PIPERX3DATA8.PCIE_IMUX37_L_4 always +PCIE_BOT.PCIE_PIPERX3DATA9.PCIE_IMUX36_L_4 always +PCIE_BOT.PCIE_PIPERX3DATA10.PCIE_IMUX33_L_4 always +PCIE_BOT.PCIE_PIPERX3DATA11.PCIE_IMUX32_L_4 always +PCIE_BOT.PCIE_PIPERX3DATA12.PCIE_IMUX39_L_3 always +PCIE_BOT.PCIE_PIPERX3DATA13.PCIE_IMUX38_L_3 always +PCIE_BOT.PCIE_PIPERX3DATA14.PCIE_IMUX35_L_3 always +PCIE_BOT.PCIE_PIPERX3DATA15.PCIE_IMUX34_L_3 always +PCIE_BOT.PCIE_PIPERX3STATUS0.PCIE_IMUX39_L_4 always +PCIE_BOT.PCIE_PIPERX3STATUS1.PCIE_IMUX38_L_4 always +PCIE_BOT.PCIE_PIPERX3STATUS2.PCIE_IMUX35_L_4 always +PCIE_BOT.PCIE_PIPERX4CHARISK1.PCIE_IMUX16_R_19 always +PCIE_BOT.PCIE_PIPERX4DATA8.PCIE_IMUX37_R_19 always +PCIE_BOT.PCIE_PIPERX4DATA9.PCIE_IMUX36_R_19 always +PCIE_BOT.PCIE_PIPERX4DATA10.PCIE_IMUX33_R_19 always +PCIE_BOT.PCIE_PIPERX4DATA11.PCIE_IMUX32_R_19 always +PCIE_BOT.PCIE_PIPERX4DATA12.PCIE_IMUX39_R_18 always +PCIE_BOT.PCIE_PIPERX4DATA13.PCIE_IMUX38_R_18 always +PCIE_BOT.PCIE_PIPERX4DATA14.PCIE_IMUX35_R_18 always +PCIE_BOT.PCIE_PIPERX4DATA15.PCIE_IMUX34_R_18 always +PCIE_BOT.PCIE_PIPERX4STATUS0.PCIE_IMUX39_R_19 always +PCIE_BOT.PCIE_PIPERX4STATUS1.PCIE_IMUX38_R_19 always +PCIE_BOT.PCIE_PIPERX4STATUS2.PCIE_IMUX35_R_19 always +PCIE_BOT.PCIE_PIPERX5CHARISK0.PCIE_IMUX16_R_10 always +PCIE_BOT.PCIE_PIPERX5CHARISK1.PCIE_IMUX16_R_8 always +PCIE_BOT.PCIE_PIPERX5DATA0.PCIE_IMUX37_R_10 always +PCIE_BOT.PCIE_PIPERX5DATA1.PCIE_IMUX36_R_10 always +PCIE_BOT.PCIE_PIPERX5DATA2.PCIE_IMUX33_R_10 always +PCIE_BOT.PCIE_PIPERX5DATA3.PCIE_IMUX32_R_10 always +PCIE_BOT.PCIE_PIPERX5DATA4.PCIE_IMUX39_R_9 always +PCIE_BOT.PCIE_PIPERX5DATA5.PCIE_IMUX38_R_9 always +PCIE_BOT.PCIE_PIPERX5DATA6.PCIE_IMUX35_R_9 always +PCIE_BOT.PCIE_PIPERX5DATA7.PCIE_IMUX34_R_9 always +PCIE_BOT.PCIE_PIPERX5DATA8.PCIE_IMUX37_R_8 always +PCIE_BOT.PCIE_PIPERX5DATA9.PCIE_IMUX36_R_8 always +PCIE_BOT.PCIE_PIPERX5DATA10.PCIE_IMUX33_R_8 always +PCIE_BOT.PCIE_PIPERX5DATA11.PCIE_IMUX32_R_8 always +PCIE_BOT.PCIE_PIPERX5DATA12.PCIE_IMUX39_R_7 always +PCIE_BOT.PCIE_PIPERX5DATA13.PCIE_IMUX38_R_7 always +PCIE_BOT.PCIE_PIPERX5DATA14.PCIE_IMUX35_R_7 always +PCIE_BOT.PCIE_PIPERX5DATA15.PCIE_IMUX34_R_7 always +PCIE_BOT.PCIE_PIPERX5STATUS0.PCIE_IMUX39_R_8 always +PCIE_BOT.PCIE_PIPERX5STATUS1.PCIE_IMUX38_R_8 always +PCIE_BOT.PCIE_PIPERX5STATUS2.PCIE_IMUX35_R_8 always +PCIE_BOT.PCIE_PIPERX6CHARISK0.PCIE_IMUX16_R_17 always +PCIE_BOT.PCIE_PIPERX6CHARISK1.PCIE_IMUX16_R_15 always +PCIE_BOT.PCIE_PIPERX6DATA0.PCIE_IMUX37_R_17 always +PCIE_BOT.PCIE_PIPERX6DATA1.PCIE_IMUX36_R_17 always +PCIE_BOT.PCIE_PIPERX6DATA2.PCIE_IMUX33_R_17 always +PCIE_BOT.PCIE_PIPERX6DATA3.PCIE_IMUX32_R_17 always +PCIE_BOT.PCIE_PIPERX6DATA4.PCIE_IMUX39_R_16 always +PCIE_BOT.PCIE_PIPERX6DATA5.PCIE_IMUX38_R_16 always +PCIE_BOT.PCIE_PIPERX6DATA6.PCIE_IMUX35_R_16 always +PCIE_BOT.PCIE_PIPERX6DATA7.PCIE_IMUX34_R_16 always +PCIE_BOT.PCIE_PIPERX6DATA8.PCIE_IMUX37_R_15 always +PCIE_BOT.PCIE_PIPERX6DATA9.PCIE_IMUX36_R_15 always +PCIE_BOT.PCIE_PIPERX6DATA10.PCIE_IMUX33_R_15 always +PCIE_BOT.PCIE_PIPERX6DATA11.PCIE_IMUX32_R_15 always +PCIE_BOT.PCIE_PIPERX6DATA12.PCIE_IMUX39_R_14 always +PCIE_BOT.PCIE_PIPERX6DATA13.PCIE_IMUX38_R_14 always +PCIE_BOT.PCIE_PIPERX6DATA14.PCIE_IMUX35_R_14 always +PCIE_BOT.PCIE_PIPERX6DATA15.PCIE_IMUX34_R_14 always +PCIE_BOT.PCIE_PIPERX6STATUS0.PCIE_IMUX39_R_15 always +PCIE_BOT.PCIE_PIPERX6STATUS1.PCIE_IMUX38_R_15 always +PCIE_BOT.PCIE_PIPERX6STATUS2.PCIE_IMUX35_R_15 always +PCIE_BOT.PCIE_PIPERX7CHARISK0.PCIE_IMUX16_R_6 always +PCIE_BOT.PCIE_PIPERX7CHARISK1.PCIE_IMUX16_R_4 always +PCIE_BOT.PCIE_PIPERX7DATA0.PCIE_IMUX37_R_6 always +PCIE_BOT.PCIE_PIPERX7DATA1.PCIE_IMUX36_R_6 always +PCIE_BOT.PCIE_PIPERX7DATA2.PCIE_IMUX33_R_6 always +PCIE_BOT.PCIE_PIPERX7DATA3.PCIE_IMUX32_R_6 always +PCIE_BOT.PCIE_PIPERX7DATA4.PCIE_IMUX39_R_5 always +PCIE_BOT.PCIE_PIPERX7DATA5.PCIE_IMUX38_R_5 always +PCIE_BOT.PCIE_PIPERX7DATA6.PCIE_IMUX35_R_5 always +PCIE_BOT.PCIE_PIPERX7DATA7.PCIE_IMUX34_R_5 always +PCIE_BOT.PCIE_PIPERX7DATA8.PCIE_IMUX37_R_4 always +PCIE_BOT.PCIE_PIPERX7DATA9.PCIE_IMUX36_R_4 always +PCIE_BOT.PCIE_PIPERX7DATA10.PCIE_IMUX33_R_4 always +PCIE_BOT.PCIE_PIPERX7DATA11.PCIE_IMUX32_R_4 always +PCIE_BOT.PCIE_PIPERX7DATA12.PCIE_IMUX39_R_3 always +PCIE_BOT.PCIE_PIPERX7DATA13.PCIE_IMUX38_R_3 always +PCIE_BOT.PCIE_PIPERX7DATA14.PCIE_IMUX35_R_3 always +PCIE_BOT.PCIE_PIPERX7DATA15.PCIE_IMUX34_R_3 always +PCIE_BOT.PCIE_PIPERX7STATUS0.PCIE_IMUX39_R_4 always +PCIE_BOT.PCIE_PIPERX7STATUS1.PCIE_IMUX38_R_4 always +PCIE_BOT.PCIE_PIPERX7STATUS2.PCIE_IMUX35_R_4 always +PCIE_BOT.PCIE_PLDBGMODE0.PCIE_IMUX21_R_11 always +PCIE_BOT.PCIE_PLDBGMODE1.PCIE_IMUX16_L_1 always +PCIE_BOT.PCIE_PLDBGMODE2.PCIE_IMUX17_L_1 always +PCIE_BOT.PCIE_PLDIRECTEDLINKCHANGE0.PCIE_IMUX0_L_0 always +PCIE_BOT.PCIE_PLDIRECTEDLINKCHANGE1.PCIE_IMUX1_L_0 always +PCIE_BOT.PCIE_PLDIRECTEDLINKWIDTH0.PCIE_IMUX2_L_0 always +PCIE_BOT.PCIE_PLDIRECTEDLINKWIDTH1.PCIE_IMUX3_L_0 always +PCIE_BOT.PCIE_PLDIRECTEDLTSSMNEW0.PCIE_IMUX9_L_0 always +PCIE_BOT.PCIE_PLDIRECTEDLTSSMNEW1.PCIE_IMUX10_L_0 always +PCIE_BOT.PCIE_PLDIRECTEDLTSSMNEW2.PCIE_IMUX11_L_0 always +PCIE_BOT.PCIE_PLDIRECTEDLTSSMNEW3.PCIE_IMUX12_L_0 always +PCIE_BOT.PCIE_PLDIRECTEDLTSSMNEW4.PCIE_IMUX0_L_1 always +PCIE_BOT.PCIE_PLDIRECTEDLTSSMNEW5.PCIE_IMUX1_L_1 always +PCIE_BOT.PCIE_TRNFCSEL0.PCIE_IMUX2_L_14 always +PCIE_BOT.PCIE_TRNFCSEL1.PCIE_IMUX3_L_14 always +PCIE_BOT.PCIE_TRNFCSEL2.PCIE_IMUX0_L_15 always +PCIE_BOT.PCIE_TRNTD0.PCIE_IMUX8_R_18 always +PCIE_BOT.PCIE_TRNTD1.PCIE_IMUX9_R_18 always +PCIE_BOT.PCIE_TRNTD2.PCIE_IMUX10_R_18 always +PCIE_BOT.PCIE_TRNTD3.PCIE_IMUX11_R_18 always +PCIE_BOT.PCIE_TRNTD4.PCIE_IMUX8_R_19 always +PCIE_BOT.PCIE_TRNTD5.PCIE_IMUX9_R_19 always +PCIE_BOT.PCIE_TRNTD6.PCIE_IMUX10_R_19 always +PCIE_BOT.PCIE_TRNTD7.PCIE_IMUX11_R_19 always +PCIE_BOT.PCIE_TRNTD42.PCIE_IMUX12_R_18 always +PCIE_BOT.PCIE_TRNTD43.PCIE_IMUX13_R_18 always +PCIE_BOT.PCIE_TRNTD44.PCIE_IMUX14_R_18 always +PCIE_BOT.PCIE_TRNTD45.PCIE_IMUX15_R_18 always +PCIE_BOT.PCIE_TRNTD46.PCIE_IMUX8_R_17 always +PCIE_BOT.PCIE_TRNTD47.PCIE_IMUX9_R_17 always +PCIE_BOT.PCIE_TRNTD48.PCIE_IMUX10_R_17 always +PCIE_BOT.PCIE_TRNTD49.PCIE_IMUX11_R_17 always +PCIE_BOT.PCIE_TRNTD50.PCIE_IMUX4_R_16 always +PCIE_BOT.PCIE_TRNTD51.PCIE_IMUX5_R_16 always +PCIE_BOT.PCIE_TRNTD52.PCIE_IMUX6_R_16 always +PCIE_BOT.PCIE_TRNTD53.PCIE_IMUX7_R_16 always +PCIE_BOT.PCIE_TRNTD54.PCIE_IMUX4_R_15 always +PCIE_BOT.PCIE_TRNTD55.PCIE_IMUX5_R_15 always +PCIE_BOT.PCIE_TRNTD56.PCIE_IMUX6_R_15 always +PCIE_BOT.PCIE_TRNTD57.PCIE_IMUX7_R_15 always +PCIE_BOT.PCIE_TRNTD58.PCIE_IMUX0_R_14 always +PCIE_BOT.PCIE_TRNTD59.PCIE_IMUX1_R_14 always +PCIE_BOT.PCIE_TRNTD60.PCIE_IMUX2_R_14 always +PCIE_BOT.PCIE_TRNTD61.PCIE_IMUX3_R_14 always +PCIE_BOT.PCIE_TRNTD62.PCIE_IMUX0_R_13 always +PCIE_BOT.PCIE_TRNTD63.PCIE_IMUX1_R_13 always +PCIE_BOT.PCIE_TRNTD64.PCIE_IMUX2_R_13 always +PCIE_BOT.PCIE_TRNTD65.PCIE_IMUX3_R_13 always +PCIE_BOT.PCIE_TRNTD66.PCIE_IMUX0_R_12 always +PCIE_BOT.PCIE_TRNTD67.PCIE_IMUX1_R_12 always +PCIE_BOT.PCIE_TRNTD68.PCIE_IMUX2_R_12 always +PCIE_BOT.PCIE_TRNTD69.PCIE_IMUX3_R_12 always +PCIE_BOT.PCIE_TRNTD70.PCIE_IMUX0_R_11 always +PCIE_BOT.PCIE_TRNTD71.PCIE_IMUX1_R_11 always +PCIE_BOT.PCIE_TRNTD72.PCIE_IMUX2_R_11 always +PCIE_BOT.PCIE_TRNTD73.PCIE_IMUX3_R_11 always +PCIE_BOT.PCIE_TRNTD74.PCIE_IMUX0_R_10 always +PCIE_BOT.PCIE_TRNTD75.PCIE_IMUX1_R_10 always +PCIE_BOT.PCIE_TRNTD76.PCIE_IMUX2_R_10 always +PCIE_BOT.PCIE_TRNTD77.PCIE_IMUX3_R_10 always +PCIE_BOT.PCIE_TRNTD78.PCIE_IMUX8_R_3 always +PCIE_BOT.PCIE_TRNTD79.PCIE_IMUX8_R_2 always +PCIE_BOT.PCIE_TRNTD80.PCIE_IMUX9_R_2 always +PCIE_BOT.PCIE_TRNTD81.PCIE_IMUX10_R_2 always +PCIE_BOT.PCIE_TRNTD82.PCIE_IMUX11_R_2 always +PCIE_BOT.PCIE_TRNTD83.PCIE_IMUX8_R_1 always +PCIE_BOT.PCIE_TRNTD84.PCIE_IMUX9_R_1 always +PCIE_BOT.PCIE_TRNTD85.PCIE_IMUX10_R_1 always +PCIE_BOT.PCIE_TRNTD86.PCIE_IMUX11_R_1 always +PCIE_BOT.PCIE_TRNTD87.PCIE_IMUX8_R_0 always +PCIE_BOT.PCIE_TRNTD88.PCIE_IMUX9_R_0 always +PCIE_BOT.PCIE_TRNTD89.PCIE_IMUX10_R_0 always +PCIE_BOT.PCIE_TRNTD90.PCIE_IMUX11_R_0 always +PCIE_BOT.PCIE_TRNTD91.PCIE_IMUX3_L_1 always +PCIE_BOT.PCIE_TRNTD92.PCIE_IMUX0_L_2 always +PCIE_BOT.PCIE_TRNTD93.PCIE_IMUX1_L_2 always +PCIE_BOT.PCIE_TRNTD94.PCIE_IMUX2_L_2 always +PCIE_BOT.PCIE_TRNTD95.PCIE_IMUX3_L_2 always +PCIE_BOT.PCIE_TRNTD96.PCIE_IMUX0_L_3 always +PCIE_BOT.PCIE_TRNTD97.PCIE_IMUX1_L_3 always +PCIE_BOT.PCIE_TRNTD98.PCIE_IMUX2_L_3 always +PCIE_BOT.PCIE_TRNTD99.PCIE_IMUX3_L_3 always +PCIE_BOT.PCIE_TRNTD100.PCIE_IMUX0_L_4 always +PCIE_BOT.PCIE_TRNTD101.PCIE_IMUX1_L_4 always +PCIE_BOT.PCIE_TRNTD102.PCIE_IMUX2_L_4 always +PCIE_BOT.PCIE_TRNTD103.PCIE_IMUX3_L_4 always +PCIE_BOT.PCIE_TRNTD104.PCIE_IMUX0_L_5 always +PCIE_BOT.PCIE_TRNTD105.PCIE_IMUX1_L_5 always +PCIE_BOT.PCIE_TRNTD106.PCIE_IMUX2_L_5 always +PCIE_BOT.PCIE_TRNTD107.PCIE_IMUX3_L_5 always +PCIE_BOT.PCIE_TRNTD108.PCIE_IMUX0_L_6 always +PCIE_BOT.PCIE_TRNTD109.PCIE_IMUX1_L_6 always +PCIE_BOT.PCIE_TRNTD110.PCIE_IMUX2_L_6 always +PCIE_BOT.PCIE_TRNTD111.PCIE_IMUX3_L_6 always +PCIE_BOT.PCIE_TRNTD112.PCIE_IMUX0_L_7 always +PCIE_BOT.PCIE_TRNTD113.PCIE_IMUX1_L_7 always +PCIE_BOT.PCIE_TRNTD114.PCIE_IMUX2_L_7 always +PCIE_BOT.PCIE_TRNTD115.PCIE_IMUX3_L_7 always +PCIE_BOT.PCIE_TRNTD116.PCIE_IMUX0_L_8 always +PCIE_BOT.PCIE_TRNTD117.PCIE_IMUX1_L_8 always +PCIE_BOT.PCIE_TRNTD118.PCIE_IMUX2_L_8 always +PCIE_BOT.PCIE_TRNTD119.PCIE_IMUX3_L_8 always +PCIE_BOT.PCIE_TRNTD120.PCIE_IMUX0_L_9 always +PCIE_BOT.PCIE_TRNTD121.PCIE_IMUX1_L_9 always +PCIE_BOT.PCIE_TRNTD122.PCIE_IMUX2_L_9 always +PCIE_BOT.PCIE_TRNTD123.PCIE_IMUX3_L_9 always +PCIE_BOT.PCIE_TRNTD124.PCIE_IMUX0_L_10 always +PCIE_BOT.PCIE_TRNTD125.PCIE_IMUX1_L_10 always +PCIE_BOT.PCIE_TRNTD126.PCIE_IMUX2_L_10 always +PCIE_BOT.PCIE_TRNTD127.PCIE_IMUX3_L_10 always +PCIE_BOT.PCIE_TRNTDLLPDATA0.PCIE_IMUX1_L_15 always +PCIE_BOT.PCIE_TRNTDLLPDATA1.PCIE_IMUX2_L_15 always +PCIE_BOT.PCIE_TRNTDLLPDATA2.PCIE_IMUX3_L_15 always +PCIE_BOT.PCIE_TRNTDLLPDATA3.PCIE_IMUX0_L_16 always +PCIE_BOT.PCIE_TRNTDLLPDATA4.PCIE_IMUX1_L_16 always +PCIE_BOT.PCIE_TRNTDLLPDATA5.PCIE_IMUX2_L_16 always +PCIE_BOT.PCIE_TRNTDLLPDATA6.PCIE_IMUX3_L_16 always +PCIE_BOT.PCIE_TRNTDLLPDATA7.PCIE_IMUX0_L_17 always +PCIE_BOT.PCIE_TRNTDLLPDATA8.PCIE_IMUX1_L_17 always +PCIE_BOT.PCIE_TRNTDLLPDATA9.PCIE_IMUX2_L_17 always +PCIE_BOT.PCIE_TRNTDLLPDATA10.PCIE_IMUX3_L_17 always +PCIE_BOT.PCIE_TRNTDLLPDATA11.PCIE_IMUX0_L_18 always +PCIE_BOT.PCIE_TRNTDLLPDATA12.PCIE_IMUX1_L_18 always +PCIE_BOT.PCIE_TRNTDLLPDATA13.PCIE_IMUX2_L_18 always +PCIE_BOT.PCIE_TRNTDLLPDATA14.PCIE_IMUX3_L_18 always +PCIE_BOT.PCIE_TRNTDLLPDATA15.PCIE_IMUX0_L_19 always +PCIE_BOT.PCIE_TRNTDLLPDATA16.PCIE_IMUX1_L_19 always +PCIE_BOT.PCIE_TRNTDLLPDATA17.PCIE_IMUX2_L_19 always +PCIE_BOT.PCIE_TRNTDLLPDATA18.PCIE_IMUX3_L_19 always +PCIE_BOT.PCIE_TRNTREM0.PCIE_IMUX0_L_11 always +PCIE_BOT.PCIE_TRNTREM1.PCIE_IMUX1_L_11 always +PCIE_BOT.PCIE_USERCLK2.PCIE_CLK1_R_12 always diff --git a/artix7/ppips_pcie_int_interface_l.db b/artix7/ppips_pcie_int_interface_l.db new file mode 100644 index 0000000..d0f9c55 --- /dev/null +++ b/artix7/ppips_pcie_int_interface_l.db @@ -0,0 +1,120 @@ +PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L0.INT_INTERFACE_LOGIC_OUTS_L_B0 always +PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L1.INT_INTERFACE_LOGIC_OUTS_L_B1 always +PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L2.INT_INTERFACE_LOGIC_OUTS_L_B2 always +PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L3.INT_INTERFACE_LOGIC_OUTS_L_B3 always +PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L4.INT_INTERFACE_LOGIC_OUTS_L_B4 always +PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L5.INT_INTERFACE_LOGIC_OUTS_L_B5 always +PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L6.INT_INTERFACE_LOGIC_OUTS_L_B6 always +PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L7.INT_INTERFACE_LOGIC_OUTS_L_B7 always +PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L8.INT_INTERFACE_LOGIC_OUTS_L_B8 always +PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L9.INT_INTERFACE_LOGIC_OUTS_L_B9 always +PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L10.INT_INTERFACE_LOGIC_OUTS_L_B10 always +PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L11.INT_INTERFACE_LOGIC_OUTS_L_B11 always +PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L12.INT_INTERFACE_LOGIC_OUTS_L_B12 always +PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L13.INT_INTERFACE_LOGIC_OUTS_L_B13 always +PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L14.INT_INTERFACE_LOGIC_OUTS_L_B14 always +PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L15.INT_INTERFACE_LOGIC_OUTS_L_B15 always +PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L16.INT_INTERFACE_LOGIC_OUTS_L_B16 always +PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L17.INT_INTERFACE_LOGIC_OUTS_L_B17 always +PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L18.INT_INTERFACE_LOGIC_OUTS_L_B18 always +PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L19.INT_INTERFACE_LOGIC_OUTS_L_B19 always +PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L20.INT_INTERFACE_LOGIC_OUTS_L_B20 always +PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L21.INT_INTERFACE_LOGIC_OUTS_L_B21 always +PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L22.INT_INTERFACE_LOGIC_OUTS_L_B22 always +PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L23.INT_INTERFACE_LOGIC_OUTS_L_B23 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT0.PCIE_INT_INTERFACE_IMUX_L_DELAY0 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT0.PCIE_INT_INTERFACE_IMUX_L0 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT1.PCIE_INT_INTERFACE_IMUX_L_DELAY1 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT1.PCIE_INT_INTERFACE_IMUX_L1 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT2.PCIE_INT_INTERFACE_IMUX_L_DELAY2 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT2.PCIE_INT_INTERFACE_IMUX_L2 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT3.PCIE_INT_INTERFACE_IMUX_L_DELAY3 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT3.PCIE_INT_INTERFACE_IMUX_L3 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT4.PCIE_INT_INTERFACE_IMUX_L_DELAY4 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT4.PCIE_INT_INTERFACE_IMUX_L4 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT5.PCIE_INT_INTERFACE_IMUX_L_DELAY5 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT5.PCIE_INT_INTERFACE_IMUX_L5 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT6.PCIE_INT_INTERFACE_IMUX_L_DELAY6 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT6.PCIE_INT_INTERFACE_IMUX_L6 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT7.PCIE_INT_INTERFACE_IMUX_L_DELAY7 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT7.PCIE_INT_INTERFACE_IMUX_L7 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT8.PCIE_INT_INTERFACE_IMUX_L_DELAY8 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT8.PCIE_INT_INTERFACE_IMUX_L8 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT9.PCIE_INT_INTERFACE_IMUX_L_DELAY9 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT9.PCIE_INT_INTERFACE_IMUX_L9 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT10.PCIE_INT_INTERFACE_IMUX_L_DELAY10 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT10.PCIE_INT_INTERFACE_IMUX_L10 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT11.PCIE_INT_INTERFACE_IMUX_L_DELAY11 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT11.PCIE_INT_INTERFACE_IMUX_L11 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT12.PCIE_INT_INTERFACE_IMUX_L_DELAY12 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT12.PCIE_INT_INTERFACE_IMUX_L12 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT13.PCIE_INT_INTERFACE_IMUX_L_DELAY13 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT13.PCIE_INT_INTERFACE_IMUX_L13 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT14.PCIE_INT_INTERFACE_IMUX_L_DELAY14 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT14.PCIE_INT_INTERFACE_IMUX_L14 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT15.PCIE_INT_INTERFACE_IMUX_L_DELAY15 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT15.PCIE_INT_INTERFACE_IMUX_L15 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT16.PCIE_INT_INTERFACE_IMUX_L_DELAY16 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT16.PCIE_INT_INTERFACE_IMUX_L16 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT17.PCIE_INT_INTERFACE_IMUX_L_DELAY17 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT17.PCIE_INT_INTERFACE_IMUX_L17 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT18.PCIE_INT_INTERFACE_IMUX_L_DELAY18 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT18.PCIE_INT_INTERFACE_IMUX_L18 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT19.PCIE_INT_INTERFACE_IMUX_L_DELAY19 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT19.PCIE_INT_INTERFACE_IMUX_L19 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT20.PCIE_INT_INTERFACE_IMUX_L_DELAY20 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT20.PCIE_INT_INTERFACE_IMUX_L20 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT21.PCIE_INT_INTERFACE_IMUX_L_DELAY21 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT21.PCIE_INT_INTERFACE_IMUX_L21 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT22.PCIE_INT_INTERFACE_IMUX_L_DELAY22 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT22.PCIE_INT_INTERFACE_IMUX_L22 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT23.PCIE_INT_INTERFACE_IMUX_L_DELAY23 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT23.PCIE_INT_INTERFACE_IMUX_L23 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT24.PCIE_INT_INTERFACE_IMUX_L_DELAY24 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT24.PCIE_INT_INTERFACE_IMUX_L24 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT25.PCIE_INT_INTERFACE_IMUX_L_DELAY25 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT25.PCIE_INT_INTERFACE_IMUX_L25 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT26.PCIE_INT_INTERFACE_IMUX_L_DELAY26 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT26.PCIE_INT_INTERFACE_IMUX_L26 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT27.PCIE_INT_INTERFACE_IMUX_L_DELAY27 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT27.PCIE_INT_INTERFACE_IMUX_L27 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT28.PCIE_INT_INTERFACE_IMUX_L_DELAY28 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT28.PCIE_INT_INTERFACE_IMUX_L28 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT29.PCIE_INT_INTERFACE_IMUX_L_DELAY29 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT29.PCIE_INT_INTERFACE_IMUX_L29 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT30.PCIE_INT_INTERFACE_IMUX_L_DELAY30 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT30.PCIE_INT_INTERFACE_IMUX_L30 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT31.PCIE_INT_INTERFACE_IMUX_L_DELAY31 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT31.PCIE_INT_INTERFACE_IMUX_L31 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT32.PCIE_INT_INTERFACE_IMUX_L_DELAY32 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT32.PCIE_INT_INTERFACE_IMUX_L32 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT33.PCIE_INT_INTERFACE_IMUX_L_DELAY33 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT33.PCIE_INT_INTERFACE_IMUX_L33 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT34.PCIE_INT_INTERFACE_IMUX_L_DELAY34 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT34.PCIE_INT_INTERFACE_IMUX_L34 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT35.PCIE_INT_INTERFACE_IMUX_L_DELAY35 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT35.PCIE_INT_INTERFACE_IMUX_L35 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT36.PCIE_INT_INTERFACE_IMUX_L_DELAY36 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT36.PCIE_INT_INTERFACE_IMUX_L36 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT37.PCIE_INT_INTERFACE_IMUX_L_DELAY37 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT37.PCIE_INT_INTERFACE_IMUX_L37 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT38.PCIE_INT_INTERFACE_IMUX_L_DELAY38 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT38.PCIE_INT_INTERFACE_IMUX_L38 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT39.PCIE_INT_INTERFACE_IMUX_L_DELAY39 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT39.PCIE_INT_INTERFACE_IMUX_L39 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT40.PCIE_INT_INTERFACE_IMUX_L_DELAY40 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT40.PCIE_INT_INTERFACE_IMUX_L40 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT41.PCIE_INT_INTERFACE_IMUX_L_DELAY41 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT41.PCIE_INT_INTERFACE_IMUX_L41 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT42.PCIE_INT_INTERFACE_IMUX_L_DELAY42 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT42.PCIE_INT_INTERFACE_IMUX_L42 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT43.PCIE_INT_INTERFACE_IMUX_L_DELAY43 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT43.PCIE_INT_INTERFACE_IMUX_L43 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT44.PCIE_INT_INTERFACE_IMUX_L_DELAY44 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT44.PCIE_INT_INTERFACE_IMUX_L44 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT45.PCIE_INT_INTERFACE_IMUX_L_DELAY45 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT45.PCIE_INT_INTERFACE_IMUX_L45 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT46.PCIE_INT_INTERFACE_IMUX_L_DELAY46 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT46.PCIE_INT_INTERFACE_IMUX_L46 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT47.PCIE_INT_INTERFACE_IMUX_L_DELAY47 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT47.PCIE_INT_INTERFACE_IMUX_L47 always diff --git a/artix7/ppips_pcie_int_interface_r.db b/artix7/ppips_pcie_int_interface_r.db new file mode 100644 index 0000000..013f200 --- /dev/null +++ b/artix7/ppips_pcie_int_interface_r.db @@ -0,0 +1,120 @@ +PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS0.INT_INTERFACE_LOGIC_OUTS_B0 always +PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS1.INT_INTERFACE_LOGIC_OUTS_B1 always +PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS2.INT_INTERFACE_LOGIC_OUTS_B2 always +PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS3.INT_INTERFACE_LOGIC_OUTS_B3 always +PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS4.INT_INTERFACE_LOGIC_OUTS_B4 always +PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS5.INT_INTERFACE_LOGIC_OUTS_B5 always +PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS6.INT_INTERFACE_LOGIC_OUTS_B6 always +PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS7.INT_INTERFACE_LOGIC_OUTS_B7 always +PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS8.INT_INTERFACE_LOGIC_OUTS_B8 always +PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS9.INT_INTERFACE_LOGIC_OUTS_B9 always +PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS10.INT_INTERFACE_LOGIC_OUTS_B10 always +PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS11.INT_INTERFACE_LOGIC_OUTS_B11 always +PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS12.INT_INTERFACE_LOGIC_OUTS_B12 always +PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS13.INT_INTERFACE_LOGIC_OUTS_B13 always +PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS14.INT_INTERFACE_LOGIC_OUTS_B14 always +PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS15.INT_INTERFACE_LOGIC_OUTS_B15 always +PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS16.INT_INTERFACE_LOGIC_OUTS_B16 always +PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS17.INT_INTERFACE_LOGIC_OUTS_B17 always +PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS18.INT_INTERFACE_LOGIC_OUTS_B18 always +PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS19.INT_INTERFACE_LOGIC_OUTS_B19 always +PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS20.INT_INTERFACE_LOGIC_OUTS_B20 always +PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS21.INT_INTERFACE_LOGIC_OUTS_B21 always +PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS22.INT_INTERFACE_LOGIC_OUTS_B22 always +PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS23.INT_INTERFACE_LOGIC_OUTS_B23 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT0.PCIE_INT_INTERFACE_IMUX_DELAY0 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT0.PCIE_INT_INTERFACE_IMUX0 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT1.PCIE_INT_INTERFACE_IMUX_DELAY1 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT1.PCIE_INT_INTERFACE_IMUX1 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT2.PCIE_INT_INTERFACE_IMUX_DELAY2 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT2.PCIE_INT_INTERFACE_IMUX2 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT3.PCIE_INT_INTERFACE_IMUX_DELAY3 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT3.PCIE_INT_INTERFACE_IMUX3 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT4.PCIE_INT_INTERFACE_IMUX_DELAY4 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT4.PCIE_INT_INTERFACE_IMUX4 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT5.PCIE_INT_INTERFACE_IMUX_DELAY5 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT5.PCIE_INT_INTERFACE_IMUX5 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT6.PCIE_INT_INTERFACE_IMUX_DELAY6 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT6.PCIE_INT_INTERFACE_IMUX6 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT7.PCIE_INT_INTERFACE_IMUX_DELAY7 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT7.PCIE_INT_INTERFACE_IMUX7 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT8.PCIE_INT_INTERFACE_IMUX_DELAY8 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT8.PCIE_INT_INTERFACE_IMUX8 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT9.PCIE_INT_INTERFACE_IMUX_DELAY9 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT9.PCIE_INT_INTERFACE_IMUX9 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT10.PCIE_INT_INTERFACE_IMUX_DELAY10 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT10.PCIE_INT_INTERFACE_IMUX10 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT11.PCIE_INT_INTERFACE_IMUX_DELAY11 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT11.PCIE_INT_INTERFACE_IMUX11 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT12.PCIE_INT_INTERFACE_IMUX_DELAY12 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT12.PCIE_INT_INTERFACE_IMUX12 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT13.PCIE_INT_INTERFACE_IMUX_DELAY13 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT13.PCIE_INT_INTERFACE_IMUX13 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT14.PCIE_INT_INTERFACE_IMUX_DELAY14 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT14.PCIE_INT_INTERFACE_IMUX14 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT15.PCIE_INT_INTERFACE_IMUX_DELAY15 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT15.PCIE_INT_INTERFACE_IMUX15 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT16.PCIE_INT_INTERFACE_IMUX_DELAY16 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT16.PCIE_INT_INTERFACE_IMUX16 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT17.PCIE_INT_INTERFACE_IMUX_DELAY17 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT17.PCIE_INT_INTERFACE_IMUX17 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT18.PCIE_INT_INTERFACE_IMUX_DELAY18 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT18.PCIE_INT_INTERFACE_IMUX18 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT19.PCIE_INT_INTERFACE_IMUX_DELAY19 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT19.PCIE_INT_INTERFACE_IMUX19 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT20.PCIE_INT_INTERFACE_IMUX_DELAY20 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT20.PCIE_INT_INTERFACE_IMUX20 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT21.PCIE_INT_INTERFACE_IMUX_DELAY21 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT21.PCIE_INT_INTERFACE_IMUX21 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT22.PCIE_INT_INTERFACE_IMUX_DELAY22 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT22.PCIE_INT_INTERFACE_IMUX22 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT23.PCIE_INT_INTERFACE_IMUX_DELAY23 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT23.PCIE_INT_INTERFACE_IMUX23 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT24.PCIE_INT_INTERFACE_IMUX_DELAY24 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT24.PCIE_INT_INTERFACE_IMUX24 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT25.PCIE_INT_INTERFACE_IMUX_DELAY25 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT25.PCIE_INT_INTERFACE_IMUX25 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT26.PCIE_INT_INTERFACE_IMUX_DELAY26 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT26.PCIE_INT_INTERFACE_IMUX26 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT27.PCIE_INT_INTERFACE_IMUX_DELAY27 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT27.PCIE_INT_INTERFACE_IMUX27 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT28.PCIE_INT_INTERFACE_IMUX_DELAY28 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT28.PCIE_INT_INTERFACE_IMUX28 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT29.PCIE_INT_INTERFACE_IMUX_DELAY29 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT29.PCIE_INT_INTERFACE_IMUX29 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT30.PCIE_INT_INTERFACE_IMUX_DELAY30 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT30.PCIE_INT_INTERFACE_IMUX30 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT31.PCIE_INT_INTERFACE_IMUX_DELAY31 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT31.PCIE_INT_INTERFACE_IMUX31 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT32.PCIE_INT_INTERFACE_IMUX_DELAY32 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT32.PCIE_INT_INTERFACE_IMUX32 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT33.PCIE_INT_INTERFACE_IMUX_DELAY33 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT33.PCIE_INT_INTERFACE_IMUX33 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT34.PCIE_INT_INTERFACE_IMUX_DELAY34 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT34.PCIE_INT_INTERFACE_IMUX34 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT35.PCIE_INT_INTERFACE_IMUX_DELAY35 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT35.PCIE_INT_INTERFACE_IMUX35 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT36.PCIE_INT_INTERFACE_IMUX_DELAY36 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT36.PCIE_INT_INTERFACE_IMUX36 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT37.PCIE_INT_INTERFACE_IMUX_DELAY37 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT37.PCIE_INT_INTERFACE_IMUX37 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT38.PCIE_INT_INTERFACE_IMUX_DELAY38 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT38.PCIE_INT_INTERFACE_IMUX38 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT39.PCIE_INT_INTERFACE_IMUX_DELAY39 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT39.PCIE_INT_INTERFACE_IMUX39 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT40.PCIE_INT_INTERFACE_IMUX_DELAY40 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT40.PCIE_INT_INTERFACE_IMUX40 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT41.PCIE_INT_INTERFACE_IMUX_DELAY41 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT41.PCIE_INT_INTERFACE_IMUX41 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT42.PCIE_INT_INTERFACE_IMUX_DELAY42 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT42.PCIE_INT_INTERFACE_IMUX42 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT43.PCIE_INT_INTERFACE_IMUX_DELAY43 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT43.PCIE_INT_INTERFACE_IMUX43 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT44.PCIE_INT_INTERFACE_IMUX_DELAY44 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT44.PCIE_INT_INTERFACE_IMUX44 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT45.PCIE_INT_INTERFACE_IMUX_DELAY45 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT45.PCIE_INT_INTERFACE_IMUX45 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT46.PCIE_INT_INTERFACE_IMUX_DELAY46 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT46.PCIE_INT_INTERFACE_IMUX46 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT47.PCIE_INT_INTERFACE_IMUX_DELAY47 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT47.PCIE_INT_INTERFACE_IMUX47 always diff --git a/artix7/ppips_pcie_top.db b/artix7/ppips_pcie_top.db new file mode 100644 index 0000000..2870e76 --- /dev/null +++ b/artix7/ppips_pcie_top.db @@ -0,0 +1,441 @@ +PCIE_TOP.PCIE_LOGIC_OUTS_B0_L_0.PCIE_TOP_TRNRD59 always +PCIE_TOP.PCIE_LOGIC_OUTS_B0_L_1.PCIE_TOP_TRNRD63 always +PCIE_TOP.PCIE_LOGIC_OUTS_B0_L_2.PCIE_TOP_TRNRD67 always +PCIE_TOP.PCIE_LOGIC_OUTS_B0_L_3.PCIE_TOP_TRNRD71 always +PCIE_TOP.PCIE_LOGIC_OUTS_B0_L_4.PCIE_TOP_TRNRD75 always +PCIE_TOP.PCIE_LOGIC_OUTS_B0_R_0.PCIE_TOP_MIMRXWDATA20 always +PCIE_TOP.PCIE_LOGIC_OUTS_B0_R_1.PCIE_TOP_MIMRXWDATA24 always +PCIE_TOP.PCIE_LOGIC_OUTS_B0_R_2.PCIE_TOP_MIMRXWADDR2 always +PCIE_TOP.PCIE_LOGIC_OUTS_B0_R_3.PCIE_TOP_TRNRD83 always +PCIE_TOP.PCIE_LOGIC_OUTS_B0_R_4.PCIE_TOP_TRNRD79 always +PCIE_TOP.PCIE_LOGIC_OUTS_B1_L_0.PCIE_TOP_TRNRD60 always +PCIE_TOP.PCIE_LOGIC_OUTS_B1_L_1.PCIE_TOP_TRNRD64 always +PCIE_TOP.PCIE_LOGIC_OUTS_B1_L_2.PCIE_TOP_TRNRD68 always +PCIE_TOP.PCIE_LOGIC_OUTS_B1_L_3.PCIE_TOP_TRNRD72 always +PCIE_TOP.PCIE_LOGIC_OUTS_B1_L_4.PCIE_TOP_TRNRD76 always +PCIE_TOP.PCIE_LOGIC_OUTS_B1_R_0.PCIE_TOP_MIMRXWADDR12 always +PCIE_TOP.PCIE_LOGIC_OUTS_B1_R_1.PCIE_TOP_TRNRD91 always +PCIE_TOP.PCIE_LOGIC_OUTS_B1_R_2.PCIE_TOP_MIMRXWDATA32 always +PCIE_TOP.PCIE_LOGIC_OUTS_B1_R_3.PCIE_TOP_TRNRD84 always +PCIE_TOP.PCIE_LOGIC_OUTS_B1_R_4.PCIE_TOP_TRNTDSTRDY3 always +PCIE_TOP.PCIE_LOGIC_OUTS_B2_L_0.PCIE_TOP_TRNRD61 always +PCIE_TOP.PCIE_LOGIC_OUTS_B2_L_1.PCIE_TOP_TRNRD65 always +PCIE_TOP.PCIE_LOGIC_OUTS_B2_L_2.PCIE_TOP_TRNRD69 always +PCIE_TOP.PCIE_LOGIC_OUTS_B2_L_3.PCIE_TOP_TRNRD73 always +PCIE_TOP.PCIE_LOGIC_OUTS_B2_L_4.PCIE_TOP_TRNRD77 always +PCIE_TOP.PCIE_LOGIC_OUTS_B2_R_0.PCIE_TOP_TRNRD95 always +PCIE_TOP.PCIE_LOGIC_OUTS_B2_R_1.PCIE_TOP_MIMRXWDATA12 always +PCIE_TOP.PCIE_LOGIC_OUTS_B2_R_2.PCIE_TOP_TRNRD87 always +PCIE_TOP.PCIE_LOGIC_OUTS_B2_R_3.PCIE_TOP_TRNRD85 always +PCIE_TOP.PCIE_LOGIC_OUTS_B2_R_4.PCIE_TOP_TRNRD80 always +PCIE_TOP.PCIE_LOGIC_OUTS_B3_L_0.PCIE_TOP_TRNRD62 always +PCIE_TOP.PCIE_LOGIC_OUTS_B3_L_1.PCIE_TOP_TRNRD66 always +PCIE_TOP.PCIE_LOGIC_OUTS_B3_L_2.PCIE_TOP_TRNRD70 always +PCIE_TOP.PCIE_LOGIC_OUTS_B3_L_3.PCIE_TOP_TRNRD74 always +PCIE_TOP.PCIE_LOGIC_OUTS_B3_L_4.PCIE_TOP_TRNRD78 always +PCIE_TOP.PCIE_LOGIC_OUTS_B3_R_0.PCIE_TOP_MIMRXRADDR10 always +PCIE_TOP.PCIE_LOGIC_OUTS_B3_R_1.PCIE_TOP_TRNRD92 always +PCIE_TOP.PCIE_LOGIC_OUTS_B3_R_2.PCIE_TOP_TRNRD88 always +PCIE_TOP.PCIE_LOGIC_OUTS_B3_R_3.PCIE_TOP_MIMRXWDATA9 always +PCIE_TOP.PCIE_LOGIC_OUTS_B3_R_4.PCIE_TOP_TRNRD81 always +PCIE_TOP.PCIE_LOGIC_OUTS_B4_L_0.PCIE_TOP_TRNRDLLPDATA32 always +PCIE_TOP.PCIE_LOGIC_OUTS_B4_L_1.PCIE_TOP_TRNRDLLPDATA36 always +PCIE_TOP.PCIE_LOGIC_OUTS_B4_L_2.PCIE_TOP_TRNRDLLPDATA40 always +PCIE_TOP.PCIE_LOGIC_OUTS_B4_L_3.PCIE_TOP_TRNRDLLPDATA44 always +PCIE_TOP.PCIE_LOGIC_OUTS_B4_L_4.PCIE_TOP_TRNRDLLPDATA48 always +PCIE_TOP.PCIE_LOGIC_OUTS_B4_R_0.PCIE_TOP_TRNRD96 always +PCIE_TOP.PCIE_LOGIC_OUTS_B4_R_1.PCIE_TOP_TRNRD93 always +PCIE_TOP.PCIE_LOGIC_OUTS_B4_R_2.PCIE_TOP_TRNRD89 always +PCIE_TOP.PCIE_LOGIC_OUTS_B4_R_3.PCIE_TOP_TRNRD86 always +PCIE_TOP.PCIE_LOGIC_OUTS_B4_R_4.PCIE_TOP_TRNRD82 always +PCIE_TOP.PCIE_LOGIC_OUTS_B5_L_0.PCIE_TOP_TRNRDLLPDATA33 always +PCIE_TOP.PCIE_LOGIC_OUTS_B5_L_1.PCIE_TOP_TRNRDLLPDATA37 always +PCIE_TOP.PCIE_LOGIC_OUTS_B5_L_2.PCIE_TOP_TRNRDLLPDATA41 always +PCIE_TOP.PCIE_LOGIC_OUTS_B5_L_3.PCIE_TOP_TRNRDLLPDATA45 always +PCIE_TOP.PCIE_LOGIC_OUTS_B5_L_4.PCIE_TOP_TRNRDLLPDATA49 always +PCIE_TOP.PCIE_LOGIC_OUTS_B5_R_0.PCIE_TOP_TRNRD97 always +PCIE_TOP.PCIE_LOGIC_OUTS_B5_R_1.PCIE_TOP_MIMRXWDATA49 always +PCIE_TOP.PCIE_LOGIC_OUTS_B5_R_2.PCIE_TOP_MIMRXRADDR4 always +PCIE_TOP.PCIE_LOGIC_OUTS_B5_R_3.PCIE_TOP_TRNRDLLPDATA56 always +PCIE_TOP.PCIE_LOGIC_OUTS_B5_R_4.PCIE_TOP_TRNRDLLPDATA52 always +PCIE_TOP.PCIE_LOGIC_OUTS_B6_L_0.PCIE_TOP_PIPETXMARGIN2 always +PCIE_TOP.PCIE_LOGIC_OUTS_B6_L_1.PCIE_TOP_TRNRDLLPDATA38 always +PCIE_TOP.PCIE_LOGIC_OUTS_B6_L_2.PCIE_TOP_TRNRDLLPDATA42 always +PCIE_TOP.PCIE_LOGIC_OUTS_B6_L_3.PCIE_TOP_TRNRDLLPDATA46 always +PCIE_TOP.PCIE_LOGIC_OUTS_B6_L_4.PCIE_TOP_TRNRDLLPDATA50 always +PCIE_TOP.PCIE_LOGIC_OUTS_B6_R_0.PCIE_TOP_TRNRD98 always +PCIE_TOP.PCIE_LOGIC_OUTS_B6_R_1.PCIE_TOP_TRNRD94 always +PCIE_TOP.PCIE_LOGIC_OUTS_B6_R_2.PCIE_TOP_TRNRD90 always +PCIE_TOP.PCIE_LOGIC_OUTS_B6_R_3.PCIE_TOP_TRNRDLLPDATA57 always +PCIE_TOP.PCIE_LOGIC_OUTS_B6_R_4.PCIE_TOP_TRNRDLLPDATA53 always +PCIE_TOP.PCIE_LOGIC_OUTS_B7_L_0.PCIE_TOP_TRNRDLLPDATA34 always +PCIE_TOP.PCIE_LOGIC_OUTS_B7_L_1.PCIE_TOP_TRNRDLLPDATA39 always +PCIE_TOP.PCIE_LOGIC_OUTS_B7_L_2.PCIE_TOP_TRNRDLLPDATA43 always +PCIE_TOP.PCIE_LOGIC_OUTS_B7_L_3.PCIE_TOP_TRNRDLLPDATA47 always +PCIE_TOP.PCIE_LOGIC_OUTS_B7_L_4.PCIE_TOP_TRNRDLLPDATA51 always +PCIE_TOP.PCIE_LOGIC_OUTS_B7_R_0.PCIE_TOP_PL2SUSPENDOK always +PCIE_TOP.PCIE_LOGIC_OUTS_B7_R_1.PCIE_TOP_MIMRXWDATA51 always +PCIE_TOP.PCIE_LOGIC_OUTS_B7_R_2.PCIE_TOP_TRNRDLLPDATA60 always +PCIE_TOP.PCIE_LOGIC_OUTS_B7_R_3.PCIE_TOP_TRNRDLLPDATA58 always +PCIE_TOP.PCIE_LOGIC_OUTS_B7_R_4.PCIE_TOP_TRNRDLLPDATA54 always +PCIE_TOP.PCIE_LOGIC_OUTS_B8_L_0.PCIE_TOP_TRNRDLLPDATA35 always +PCIE_TOP.PCIE_LOGIC_OUTS_B8_L_1.PCIE_TOP_CFGPMRCVENTERL23N always +PCIE_TOP.PCIE_LOGIC_OUTS_B8_L_2.PCIE_TOP_CFGPMCSRPMEEN always +PCIE_TOP.PCIE_LOGIC_OUTS_B8_L_3.PCIE_TOP_CFGTRANSACTIONADDR0 always +PCIE_TOP.PCIE_LOGIC_OUTS_B8_L_4.PCIE_TOP_CFGTRANSACTIONADDR4 always +PCIE_TOP.PCIE_LOGIC_OUTS_B8_R_0.PCIE_TOP_MIMRXRADDR9 always +PCIE_TOP.PCIE_LOGIC_OUTS_B8_R_1.PCIE_TOP_MIMRXWDATA8 always +PCIE_TOP.PCIE_LOGIC_OUTS_B8_R_2.PCIE_TOP_TRNRDLLPDATA61 always +PCIE_TOP.PCIE_LOGIC_OUTS_B8_R_3.PCIE_TOP_MIMRXWDATA19 always +PCIE_TOP.PCIE_LOGIC_OUTS_B8_R_4.PCIE_TOP_MIMRXWDATA29 always +PCIE_TOP.PCIE_LOGIC_OUTS_B9_L_0.PCIE_TOP_CFGPCIELINKSTATE1 always +PCIE_TOP.PCIE_LOGIC_OUTS_B9_L_1.PCIE_TOP_CFGPMRCVREQACKN always +PCIE_TOP.PCIE_LOGIC_OUTS_B9_L_2.PCIE_TOP_CFGPMCSRPMESTATUS always +PCIE_TOP.PCIE_LOGIC_OUTS_B9_L_3.PCIE_TOP_CFGTRANSACTIONADDR1 always +PCIE_TOP.PCIE_LOGIC_OUTS_B9_L_4.PCIE_TOP_CFGTRANSACTIONADDR5 always +PCIE_TOP.PCIE_LOGIC_OUTS_B9_R_0.PCIE_TOP_MIMRXWDATA4 always +PCIE_TOP.PCIE_LOGIC_OUTS_B9_R_1.PCIE_TOP_MIMRXWADDR5 always +PCIE_TOP.PCIE_LOGIC_OUTS_B9_R_2.PCIE_TOP_MIMRXWDATA17 always +PCIE_TOP.PCIE_LOGIC_OUTS_B9_R_3.PCIE_TOP_TRNRDLLPDATA59 always +PCIE_TOP.PCIE_LOGIC_OUTS_B9_R_4.PCIE_TOP_MIMRXWDATA13 always +PCIE_TOP.PCIE_LOGIC_OUTS_B10_L_0.PCIE_TOP_CFGPCIELINKSTATE2 always +PCIE_TOP.PCIE_LOGIC_OUTS_B10_L_1.PCIE_TOP_CFGPMCSRPOWERSTATE0 always +PCIE_TOP.PCIE_LOGIC_OUTS_B10_L_2.PCIE_TOP_CFGTRANSACTION always +PCIE_TOP.PCIE_LOGIC_OUTS_B10_L_3.PCIE_TOP_CFGTRANSACTIONADDR2 always +PCIE_TOP.PCIE_LOGIC_OUTS_B10_L_4.PCIE_TOP_CFGTRANSACTIONADDR6 always +PCIE_TOP.PCIE_LOGIC_OUTS_B10_R_0.PCIE_TOP_MIMRXRADDR11 always +PCIE_TOP.PCIE_LOGIC_OUTS_B10_R_1.PCIE_TOP_TRNRDLLPSRCRDY0 always +PCIE_TOP.PCIE_LOGIC_OUTS_B10_R_2.PCIE_TOP_TRNRDLLPDATA62 always +PCIE_TOP.PCIE_LOGIC_OUTS_B10_R_3.PCIE_TOP_MIMRXWDATA25 always +PCIE_TOP.PCIE_LOGIC_OUTS_B10_R_4.PCIE_TOP_MIMRXWDATA15 always +PCIE_TOP.PCIE_LOGIC_OUTS_B11_L_0.PCIE_TOP_CFGPMRCVASREQL1N always +PCIE_TOP.PCIE_LOGIC_OUTS_B11_L_1.PCIE_TOP_CFGPMCSRPOWERSTATE1 always +PCIE_TOP.PCIE_LOGIC_OUTS_B11_L_2.PCIE_TOP_CFGTRANSACTIONTYPE always +PCIE_TOP.PCIE_LOGIC_OUTS_B11_L_3.PCIE_TOP_CFGTRANSACTIONADDR3 always +PCIE_TOP.PCIE_LOGIC_OUTS_B11_L_4.PCIE_TOP_CFGCOMMANDIOENABLE always +PCIE_TOP.PCIE_LOGIC_OUTS_B11_R_0.PCIE_TOP_MIMRXWDATA0 always +PCIE_TOP.PCIE_LOGIC_OUTS_B11_R_1.PCIE_TOP_MIMRXRADDR1 always +PCIE_TOP.PCIE_LOGIC_OUTS_B11_R_2.PCIE_TOP_TRNRDLLPDATA63 always +PCIE_TOP.PCIE_LOGIC_OUTS_B11_R_3.PCIE_TOP_CFGMGMTDO20 always +PCIE_TOP.PCIE_LOGIC_OUTS_B11_R_4.PCIE_TOP_MIMRXWDATA35 always +PCIE_TOP.PCIE_LOGIC_OUTS_B12_L_0.PCIE_TOP_CFGPMRCVENTERL1N always +PCIE_TOP.PCIE_LOGIC_OUTS_B12_L_1.PCIE_TOP_CFGLINKCONTROLCOMMONCLOCK always +PCIE_TOP.PCIE_LOGIC_OUTS_B12_L_2.PCIE_TOP_CFGLINKCONTROLBANDWIDTHINTEN always +PCIE_TOP.PCIE_LOGIC_OUTS_B12_L_3.PCIE_TOP_CFGDEVCONTROL2CPLTIMEOUTVAL2 always +PCIE_TOP.PCIE_LOGIC_OUTS_B12_L_4.PCIE_TOP_CFGDEVCONTROL2ATOMICREQUESTEREN always +PCIE_TOP.PCIE_LOGIC_OUTS_B12_R_0.PCIE_TOP_PL2RECOVERY always +PCIE_TOP.PCIE_LOGIC_OUTS_B12_R_1.PCIE_TOP_MIMRXREN always +PCIE_TOP.PCIE_LOGIC_OUTS_B12_R_2.PCIE_TOP_MIMRXRADDR2 always +PCIE_TOP.PCIE_LOGIC_OUTS_B12_R_3.PCIE_TOP_CFGMGMTDO21 always +PCIE_TOP.PCIE_LOGIC_OUTS_B12_R_4.PCIE_TOP_TRNRDLLPDATA55 always +PCIE_TOP.PCIE_LOGIC_OUTS_B13_L_0.PCIE_TOP_CFGLINKCONTROLASPMCONTROL1 always +PCIE_TOP.PCIE_LOGIC_OUTS_B13_L_1.PCIE_TOP_CFGLINKCONTROLEXTENDEDSYNC always +PCIE_TOP.PCIE_LOGIC_OUTS_B13_L_2.PCIE_TOP_CFGLINKCONTROLAUTOBANDWIDTHINTEN always +PCIE_TOP.PCIE_LOGIC_OUTS_B13_L_3.PCIE_TOP_CFGDEVCONTROL2CPLTIMEOUTVAL3 always +PCIE_TOP.PCIE_LOGIC_OUTS_B13_L_4.PCIE_TOP_CFGDEVCONTROL2ATOMICEGRESSBLOCK always +PCIE_TOP.PCIE_LOGIC_OUTS_B13_R_0.PCIE_TOP_MIMRXWDATA1 always +PCIE_TOP.PCIE_LOGIC_OUTS_B13_R_1.PCIE_TOP_MIMRXWDATA26 always +PCIE_TOP.PCIE_LOGIC_OUTS_B13_R_2.PCIE_TOP_MIMRXRADDR0 always +PCIE_TOP.PCIE_LOGIC_OUTS_B13_R_3.PCIE_TOP_CFGMGMTDO22 always +PCIE_TOP.PCIE_LOGIC_OUTS_B13_R_4.PCIE_TOP_CFGMGMTDO24 always +PCIE_TOP.PCIE_LOGIC_OUTS_B14_L_0.PCIE_TOP_CFGLINKCONTROLRCB always +PCIE_TOP.PCIE_LOGIC_OUTS_B14_L_1.PCIE_TOP_CFGLINKCONTROLCLOCKPMEN always +PCIE_TOP.PCIE_LOGIC_OUTS_B14_L_2.PCIE_TOP_CFGDEVCONTROL2CPLTIMEOUTVAL0 always +PCIE_TOP.PCIE_LOGIC_OUTS_B14_L_3.PCIE_TOP_CFGDEVCONTROL2CPLTIMEOUTDIS always +PCIE_TOP.PCIE_LOGIC_OUTS_B14_L_4.PCIE_TOP_CFGDEVCONTROL2IDOREQEN always +PCIE_TOP.PCIE_LOGIC_OUTS_B14_R_0.PCIE_TOP_DBGVECA18 always +PCIE_TOP.PCIE_LOGIC_OUTS_B14_R_1.PCIE_TOP_TRNRDLLPSRCRDY1 always +PCIE_TOP.PCIE_LOGIC_OUTS_B14_R_2.PCIE_TOP_MIMRXWDATA28 always +PCIE_TOP.PCIE_LOGIC_OUTS_B14_R_3.PCIE_TOP_MIMRXWDATA23 always +PCIE_TOP.PCIE_LOGIC_OUTS_B14_R_4.PCIE_TOP_CFGMGMTDO25 always +PCIE_TOP.PCIE_LOGIC_OUTS_B15_L_0.PCIE_TOP_CFGLINKCONTROLLINKDISABLE always +PCIE_TOP.PCIE_LOGIC_OUTS_B15_L_1.PCIE_TOP_CFGLINKCONTROLHWAUTOWIDTHDIS always +PCIE_TOP.PCIE_LOGIC_OUTS_B15_L_2.PCIE_TOP_CFGDEVCONTROL2CPLTIMEOUTVAL1 always +PCIE_TOP.PCIE_LOGIC_OUTS_B15_L_3.PCIE_TOP_CFGDEVCONTROL2ARIFORWARDEN always +PCIE_TOP.PCIE_LOGIC_OUTS_B15_L_4.PCIE_TOP_CFGDEVCONTROL2IDOCPLEN always +PCIE_TOP.PCIE_LOGIC_OUTS_B15_R_0.PCIE_TOP_MIMRXWDATA22 always +PCIE_TOP.PCIE_LOGIC_OUTS_B15_R_1.PCIE_TOP_MIMRXWADDR1 always +PCIE_TOP.PCIE_LOGIC_OUTS_B15_R_2.PCIE_TOP_MIMRXWDATA3 always +PCIE_TOP.PCIE_LOGIC_OUTS_B15_R_3.PCIE_TOP_CFGMGMTDO23 always +PCIE_TOP.PCIE_LOGIC_OUTS_B15_R_4.PCIE_TOP_CFGMGMTDO26 always +PCIE_TOP.PCIE_LOGIC_OUTS_B16_L_0.PCIE_TOP_PIPETXMARGIN1 always +PCIE_TOP.PCIE_LOGIC_OUTS_B16_L_1.PCIE_TOP_CFGAERROOTERRFATALERRRECEIVED always +PCIE_TOP.PCIE_LOGIC_OUTS_B16_L_2.PCIE_TOP_CFGVCTCVCMAP3 always +PCIE_TOP.PCIE_LOGIC_OUTS_B16_L_3.PCIE_TOP_DRPRDY always +PCIE_TOP.PCIE_LOGIC_OUTS_B16_L_4.PCIE_TOP_DRPDO3 always +PCIE_TOP.PCIE_LOGIC_OUTS_B16_R_0.PCIE_TOP_MIMRXWDATA6 always +PCIE_TOP.PCIE_LOGIC_OUTS_B16_R_1.PCIE_TOP_LL2TFCINIT1SEQ always +PCIE_TOP.PCIE_LOGIC_OUTS_B16_R_2.PCIE_TOP_CFGMGMTDO17 always +PCIE_TOP.PCIE_LOGIC_OUTS_B16_R_3.PCIE_TOP_CFGMGMTDO28 always +PCIE_TOP.PCIE_LOGIC_OUTS_B16_R_4.PCIE_TOP_CFGMGMTDO27 always +PCIE_TOP.PCIE_LOGIC_OUTS_B17_L_0.PCIE_TOP_CFGLINKCONTROLRETRAINLINK always +PCIE_TOP.PCIE_LOGIC_OUTS_B17_L_1.PCIE_TOP_CFGVCTCVCMAP0 always +PCIE_TOP.PCIE_LOGIC_OUTS_B17_L_2.PCIE_TOP_CFGVCTCVCMAP4 always +PCIE_TOP.PCIE_LOGIC_OUTS_B17_L_3.PCIE_TOP_DRPDO0 always +PCIE_TOP.PCIE_LOGIC_OUTS_B17_L_4.PCIE_TOP_DRPDO4 always +PCIE_TOP.PCIE_LOGIC_OUTS_B17_R_0.PCIE_TOP_MIMRXRADDR8 always +PCIE_TOP.PCIE_LOGIC_OUTS_B17_R_1.PCIE_TOP_MIMRXWDATA34 always +PCIE_TOP.PCIE_LOGIC_OUTS_B17_R_2.PCIE_TOP_CFGMGMTDO18 always +PCIE_TOP.PCIE_LOGIC_OUTS_B17_R_3.PCIE_TOP_CFGMGMTDO29 always +PCIE_TOP.PCIE_LOGIC_OUTS_B17_R_4.PCIE_TOP_CFGCOMMANDMEMENABLE always +PCIE_TOP.PCIE_LOGIC_OUTS_B18_L_0.PCIE_TOP_PIPETXMARGIN0 always +PCIE_TOP.PCIE_LOGIC_OUTS_B18_L_1.PCIE_TOP_CFGVCTCVCMAP1 always +PCIE_TOP.PCIE_LOGIC_OUTS_B18_L_2.PCIE_TOP_CFGVCTCVCMAP5 always +PCIE_TOP.PCIE_LOGIC_OUTS_B18_L_3.PCIE_TOP_DRPDO1 always +PCIE_TOP.PCIE_LOGIC_OUTS_B18_L_4.PCIE_TOP_DRPDO5 always +PCIE_TOP.PCIE_LOGIC_OUTS_B18_R_0.PCIE_TOP_MIMRXWDATA2 always +PCIE_TOP.PCIE_LOGIC_OUTS_B18_R_1.PCIE_TOP_MIMRXWEN always +PCIE_TOP.PCIE_LOGIC_OUTS_B18_R_2.PCIE_TOP_MIMRXWDATA30 always +PCIE_TOP.PCIE_LOGIC_OUTS_B18_R_3.PCIE_TOP_CFGMGMTDO30 always +PCIE_TOP.PCIE_LOGIC_OUTS_B18_R_4.PCIE_TOP_MIMRXWDATA11 always +PCIE_TOP.PCIE_LOGIC_OUTS_B19_L_0.PCIE_TOP_CFGAERROOTERRNONFATALERRREPORTINGEN always +PCIE_TOP.PCIE_LOGIC_OUTS_B19_L_1.PCIE_TOP_CFGVCTCVCMAP2 always +PCIE_TOP.PCIE_LOGIC_OUTS_B19_L_2.PCIE_TOP_CFGVCTCVCMAP6 always +PCIE_TOP.PCIE_LOGIC_OUTS_B19_L_3.PCIE_TOP_DRPDO2 always +PCIE_TOP.PCIE_LOGIC_OUTS_B19_L_4.PCIE_TOP_DRPDO6 always +PCIE_TOP.PCIE_LOGIC_OUTS_B19_R_0.PCIE_TOP_DBGVECA19 always +PCIE_TOP.PCIE_LOGIC_OUTS_B19_R_1.PCIE_TOP_MIMRXWDATA10 always +PCIE_TOP.PCIE_LOGIC_OUTS_B19_R_2.PCIE_TOP_CFGMGMTDO19 always +PCIE_TOP.PCIE_LOGIC_OUTS_B19_R_3.PCIE_TOP_MIMRXWDATA21 always +PCIE_TOP.PCIE_LOGIC_OUTS_B19_R_4.PCIE_TOP_MIMRXWDATA27 always +PCIE_TOP.PCIE_LOGIC_OUTS_B20_L_0.PCIE_TOP_CFGAERROOTERRFATALERRREPORTINGEN always +PCIE_TOP.PCIE_LOGIC_OUTS_B20_L_1.PCIE_TOP_DRPDO11 always +PCIE_TOP.PCIE_LOGIC_OUTS_B20_L_2.PCIE_TOP_DRPDO15 always +PCIE_TOP.PCIE_LOGIC_OUTS_B20_L_3.PCIE_TOP_DBGVECA3 always +PCIE_TOP.PCIE_LOGIC_OUTS_B20_L_4.PCIE_TOP_DBGVECA7 always +PCIE_TOP.PCIE_LOGIC_OUTS_B20_R_0.PCIE_TOP_DBGVECA20 always +PCIE_TOP.PCIE_LOGIC_OUTS_B20_R_1.PCIE_TOP_LL2TFCINIT2SEQ always +PCIE_TOP.PCIE_LOGIC_OUTS_B20_R_2.PCIE_TOP_DBGVECA14 always +PCIE_TOP.PCIE_LOGIC_OUTS_B20_R_3.PCIE_TOP_DBGVECA12 always +PCIE_TOP.PCIE_LOGIC_OUTS_B20_R_4.PCIE_TOP_CFGCOMMANDBUSMASTERENABLE always +PCIE_TOP.PCIE_LOGIC_OUTS_B21_L_0.PCIE_TOP_CFGAERROOTERRCORRERRRECEIVED always +PCIE_TOP.PCIE_LOGIC_OUTS_B21_L_1.PCIE_TOP_DRPDO12 always +PCIE_TOP.PCIE_LOGIC_OUTS_B21_L_2.PCIE_TOP_DBGVECA0 always +PCIE_TOP.PCIE_LOGIC_OUTS_B21_L_3.PCIE_TOP_DBGVECA4 always +PCIE_TOP.PCIE_LOGIC_OUTS_B21_L_4.PCIE_TOP_DBGVECA8 always +PCIE_TOP.PCIE_LOGIC_OUTS_B21_R_0.PCIE_TOP_DBGVECA21 always +PCIE_TOP.PCIE_LOGIC_OUTS_B21_R_1.PCIE_TOP_CFGMGMTDO16 always +PCIE_TOP.PCIE_LOGIC_OUTS_B21_R_2.PCIE_TOP_MIMRXWDATA31 always +PCIE_TOP.PCIE_LOGIC_OUTS_B21_R_3.PCIE_TOP_DBGVECA13 always +PCIE_TOP.PCIE_LOGIC_OUTS_B21_R_4.PCIE_TOP_CFGCOMMANDINTERRUPTDISABLE always +PCIE_TOP.PCIE_LOGIC_OUTS_B22_L_0.PCIE_TOP_CFGAERROOTERRNONFATALERRRECEIVED always +PCIE_TOP.PCIE_LOGIC_OUTS_B22_L_1.PCIE_TOP_DRPDO13 always +PCIE_TOP.PCIE_LOGIC_OUTS_B22_L_2.PCIE_TOP_DBGVECA1 always +PCIE_TOP.PCIE_LOGIC_OUTS_B22_L_3.PCIE_TOP_DBGVECA5 always +PCIE_TOP.PCIE_LOGIC_OUTS_B22_L_4.PCIE_TOP_DBGVECA9 always +PCIE_TOP.PCIE_LOGIC_OUTS_B22_R_0.PCIE_TOP_DBGVECB10 always +PCIE_TOP.PCIE_LOGIC_OUTS_B22_R_1.PCIE_TOP_DBGVECA16 always +PCIE_TOP.PCIE_LOGIC_OUTS_B22_R_2.PCIE_TOP_MIMRXWDATA33 always +PCIE_TOP.PCIE_LOGIC_OUTS_B22_R_3.PCIE_TOP_MIMRXWDATA5 always +PCIE_TOP.PCIE_LOGIC_OUTS_B22_R_4.PCIE_TOP_DBGVECA11 always +PCIE_TOP.PCIE_LOGIC_OUTS_B23_L_0.PCIE_TOP_PLDBGVEC8 always +PCIE_TOP.PCIE_LOGIC_OUTS_B23_L_1.PCIE_TOP_DRPDO14 always +PCIE_TOP.PCIE_LOGIC_OUTS_B23_L_2.PCIE_TOP_DBGVECA2 always +PCIE_TOP.PCIE_LOGIC_OUTS_B23_L_3.PCIE_TOP_DBGVECA6 always +PCIE_TOP.PCIE_LOGIC_OUTS_B23_L_4.PCIE_TOP_DBGVECA10 always +PCIE_TOP.PCIE_LOGIC_OUTS_B23_R_1.PCIE_TOP_DBGVECA17 always +PCIE_TOP.PCIE_LOGIC_OUTS_B23_R_2.PCIE_TOP_DBGVECA15 always +PCIE_TOP.PCIE_LOGIC_OUTS_B23_R_3.PCIE_TOP_MIMRXWDATA7 always +PCIE_TOP.PCIE_LOGIC_OUTS_B23_R_4.PCIE_TOP_CFGDEVCONTROL2LTREN always +PCIE_TOP.PCIE_TOP_CFGERRLOCKEDN.PCIE_IMUX17_R_2 always +PCIE_TOP.PCIE_TOP_CFGERRNORECOVERYN.PCIE_IMUX18_R_2 always +PCIE_TOP.PCIE_TOP_CFGINTERRUPTN.PCIE_IMUX19_R_4 always +PCIE_TOP.PCIE_TOP_LL2SENDPMACK.PCIE_IMUX2_L_4 always +PCIE_TOP.PCIE_TOP_LL2SUSPENDNOW.PCIE_IMUX16_R_3 always +PCIE_TOP.PCIE_TOP_LL2TLPRCV.PCIE_IMUX2_L_3 always +PCIE_TOP.PCIE_TOP_PIPERX0CHANISALIGNED.PCIE_IMUX33_L_0 always +PCIE_TOP.PCIE_TOP_PIPERX0PHYSTATUS.PCIE_IMUX37_L_0 always +PCIE_TOP.PCIE_TOP_PIPERX0VALID.PCIE_IMUX36_L_0 always +PCIE_TOP.PCIE_TOP_PIPERX4CHANISALIGNED.PCIE_IMUX33_R_0 always +PCIE_TOP.PCIE_TOP_PIPERX4PHYSTATUS.PCIE_IMUX37_R_0 always +PCIE_TOP.PCIE_TOP_PIPERX4VALID.PCIE_IMUX36_R_0 always +PCIE_TOP.PCIE_TOP_TL2ASPMSUSPENDCREDITCHECK.PCIE_IMUX18_R_3 always +PCIE_TOP.PCIE_TOP_TL2PPMSUSPENDREQ.PCIE_IMUX17_R_3 always +PCIE_TOP.PCIE_TOP_TRNTDLLPSRCRDY.PCIE_IMUX1_L_3 always +PCIE_TOP.PCIE_TOP_CFGDEVID0.PCIE_IMUX11_L_1 always +PCIE_TOP.PCIE_TOP_CFGDEVID1.PCIE_IMUX8_L_2 always +PCIE_TOP.PCIE_TOP_CFGDEVID2.PCIE_IMUX9_L_2 always +PCIE_TOP.PCIE_TOP_CFGDEVID3.PCIE_IMUX10_L_2 always +PCIE_TOP.PCIE_TOP_CFGDEVID4.PCIE_IMUX11_L_2 always +PCIE_TOP.PCIE_TOP_CFGDEVID5.PCIE_IMUX8_L_3 always +PCIE_TOP.PCIE_TOP_CFGDEVID6.PCIE_IMUX9_L_3 always +PCIE_TOP.PCIE_TOP_CFGDEVID7.PCIE_IMUX10_L_3 always +PCIE_TOP.PCIE_TOP_CFGDEVID8.PCIE_IMUX11_L_3 always +PCIE_TOP.PCIE_TOP_CFGDEVID9.PCIE_IMUX8_L_4 always +PCIE_TOP.PCIE_TOP_CFGDEVID10.PCIE_IMUX9_L_4 always +PCIE_TOP.PCIE_TOP_CFGDEVID11.PCIE_IMUX10_L_4 always +PCIE_TOP.PCIE_TOP_CFGDEVID12.PCIE_IMUX11_L_4 always +PCIE_TOP.PCIE_TOP_CFGDEVID13.PCIE_IMUX21_R_4 always +PCIE_TOP.PCIE_TOP_CFGDEVID14.PCIE_IMUX22_R_4 always +PCIE_TOP.PCIE_TOP_CFGDEVID15.PCIE_IMUX23_R_4 always +PCIE_TOP.PCIE_TOP_CFGDSN57.PCIE_IMUX8_L_0 always +PCIE_TOP.PCIE_TOP_CFGDSN58.PCIE_IMUX9_L_0 always +PCIE_TOP.PCIE_TOP_CFGDSN59.PCIE_IMUX10_L_0 always +PCIE_TOP.PCIE_TOP_CFGDSN60.PCIE_IMUX11_L_0 always +PCIE_TOP.PCIE_TOP_CFGDSN61.PCIE_IMUX8_L_1 always +PCIE_TOP.PCIE_TOP_CFGDSN62.PCIE_IMUX9_L_1 always +PCIE_TOP.PCIE_TOP_CFGDSN63.PCIE_IMUX10_L_1 always +PCIE_TOP.PCIE_TOP_CFGERRAERHEADERLOG0.PCIE_IMUX19_R_2 always +PCIE_TOP.PCIE_TOP_CFGERRAERHEADERLOG1.PCIE_IMUX20_R_2 always +PCIE_TOP.PCIE_TOP_CFGERRAERHEADERLOG2.PCIE_IMUX20_R_3 always +PCIE_TOP.PCIE_TOP_CFGERRAERHEADERLOG3.PCIE_IMUX21_R_3 always +PCIE_TOP.PCIE_TOP_CFGERRAERHEADERLOG4.PCIE_IMUX22_R_3 always +PCIE_TOP.PCIE_TOP_CFGERRAERHEADERLOG5.PCIE_IMUX23_R_3 always +PCIE_TOP.PCIE_TOP_CFGERRAERHEADERLOG6.PCIE_IMUX13_R_4 always +PCIE_TOP.PCIE_TOP_CFGERRAERHEADERLOG7.PCIE_IMUX14_R_4 always +PCIE_TOP.PCIE_TOP_CFGERRAERHEADERLOG8.PCIE_IMUX15_R_4 always +PCIE_TOP.PCIE_TOP_CFGERRAERHEADERLOG9.PCIE_IMUX16_R_4 always +PCIE_TOP.PCIE_TOP_CFGERRAERHEADERLOG10.PCIE_IMUX24_R_3 always +PCIE_TOP.PCIE_TOP_CFGERRAERHEADERLOG11.PCIE_IMUX21_R_2 always +PCIE_TOP.PCIE_TOP_CFGERRTLPCPLHEADER26.PCIE_IMUX4_L_0 always +PCIE_TOP.PCIE_TOP_CFGERRTLPCPLHEADER27.PCIE_IMUX5_L_0 always +PCIE_TOP.PCIE_TOP_CFGERRTLPCPLHEADER28.PCIE_IMUX6_L_0 always +PCIE_TOP.PCIE_TOP_CFGERRTLPCPLHEADER29.PCIE_IMUX7_L_0 always +PCIE_TOP.PCIE_TOP_CFGERRTLPCPLHEADER30.PCIE_IMUX4_L_1 always +PCIE_TOP.PCIE_TOP_CFGERRTLPCPLHEADER31.PCIE_IMUX5_L_1 always +PCIE_TOP.PCIE_TOP_CFGERRTLPCPLHEADER32.PCIE_IMUX6_L_1 always +PCIE_TOP.PCIE_TOP_CFGERRTLPCPLHEADER33.PCIE_IMUX7_L_1 always +PCIE_TOP.PCIE_TOP_CFGERRTLPCPLHEADER34.PCIE_IMUX4_L_2 always +PCIE_TOP.PCIE_TOP_CFGERRTLPCPLHEADER35.PCIE_IMUX5_L_2 always +PCIE_TOP.PCIE_TOP_CFGERRTLPCPLHEADER36.PCIE_IMUX6_L_2 always +PCIE_TOP.PCIE_TOP_CFGERRTLPCPLHEADER37.PCIE_IMUX7_L_2 always +PCIE_TOP.PCIE_TOP_CFGERRTLPCPLHEADER38.PCIE_IMUX4_L_3 always +PCIE_TOP.PCIE_TOP_CFGERRTLPCPLHEADER39.PCIE_IMUX5_L_3 always +PCIE_TOP.PCIE_TOP_CFGERRTLPCPLHEADER40.PCIE_IMUX6_L_3 always +PCIE_TOP.PCIE_TOP_CFGERRTLPCPLHEADER41.PCIE_IMUX7_L_3 always +PCIE_TOP.PCIE_TOP_CFGERRTLPCPLHEADER42.PCIE_IMUX4_L_4 always +PCIE_TOP.PCIE_TOP_CFGERRTLPCPLHEADER43.PCIE_IMUX5_L_4 always +PCIE_TOP.PCIE_TOP_CFGERRTLPCPLHEADER44.PCIE_IMUX6_L_4 always +PCIE_TOP.PCIE_TOP_CFGERRTLPCPLHEADER45.PCIE_IMUX7_L_4 always +PCIE_TOP.PCIE_TOP_CFGERRTLPCPLHEADER46.PCIE_IMUX17_R_4 always +PCIE_TOP.PCIE_TOP_CFGERRTLPCPLHEADER47.PCIE_IMUX18_R_4 always +PCIE_TOP.PCIE_TOP_CFGINTERRUPTDI0.PCIE_IMUX20_R_4 always +PCIE_TOP.PCIE_TOP_CFGVENDID0.PCIE_IMUX24_R_4 always +PCIE_TOP.PCIE_TOP_DBGMODE0.PCIE_IMUX25_R_4 always +PCIE_TOP.PCIE_TOP_DRPADDR7.PCIE_IMUX12_L_0 always +PCIE_TOP.PCIE_TOP_DRPADDR8.PCIE_IMUX13_L_0 always +PCIE_TOP.PCIE_TOP_DRPDI0.PCIE_IMUX12_L_1 always +PCIE_TOP.PCIE_TOP_DRPDI1.PCIE_IMUX13_L_1 always +PCIE_TOP.PCIE_TOP_DRPDI2.PCIE_IMUX14_L_1 always +PCIE_TOP.PCIE_TOP_DRPDI3.PCIE_IMUX15_L_1 always +PCIE_TOP.PCIE_TOP_DRPDI4.PCIE_IMUX12_L_2 always +PCIE_TOP.PCIE_TOP_DRPDI5.PCIE_IMUX13_L_2 always +PCIE_TOP.PCIE_TOP_DRPDI6.PCIE_IMUX14_L_2 always +PCIE_TOP.PCIE_TOP_DRPDI7.PCIE_IMUX15_L_2 always +PCIE_TOP.PCIE_TOP_DRPDI8.PCIE_IMUX12_L_3 always +PCIE_TOP.PCIE_TOP_DRPDI9.PCIE_IMUX13_L_3 always +PCIE_TOP.PCIE_TOP_DRPDI10.PCIE_IMUX14_L_3 always +PCIE_TOP.PCIE_TOP_DRPDI11.PCIE_IMUX15_L_3 always +PCIE_TOP.PCIE_TOP_DRPDI12.PCIE_IMUX12_L_4 always +PCIE_TOP.PCIE_TOP_DRPDI13.PCIE_IMUX13_L_4 always +PCIE_TOP.PCIE_TOP_DRPDI14.PCIE_IMUX14_L_4 always +PCIE_TOP.PCIE_TOP_DRPDI15.PCIE_IMUX15_L_4 always +PCIE_TOP.PCIE_TOP_LL2SENDASREQL1.PCIE_IMUX1_L_4 always +PCIE_TOP.PCIE_TOP_LL2SENDENTERL1.PCIE_IMUX3_L_3 always +PCIE_TOP.PCIE_TOP_LL2SENDENTERL23.PCIE_IMUX0_L_4 always +PCIE_TOP.PCIE_TOP_MIMRXRDATA20.PCIE_IMUX0_R_0 always +PCIE_TOP.PCIE_TOP_MIMRXRDATA21.PCIE_IMUX1_R_0 always +PCIE_TOP.PCIE_TOP_MIMRXRDATA22.PCIE_IMUX2_R_0 always +PCIE_TOP.PCIE_TOP_MIMRXRDATA23.PCIE_IMUX3_R_0 always +PCIE_TOP.PCIE_TOP_MIMRXRDATA24.PCIE_IMUX0_R_1 always +PCIE_TOP.PCIE_TOP_MIMRXRDATA25.PCIE_IMUX1_R_1 always +PCIE_TOP.PCIE_TOP_MIMRXRDATA26.PCIE_IMUX2_R_1 always +PCIE_TOP.PCIE_TOP_MIMRXRDATA27.PCIE_IMUX3_R_1 always +PCIE_TOP.PCIE_TOP_MIMRXRDATA28.PCIE_IMUX0_R_2 always +PCIE_TOP.PCIE_TOP_MIMRXRDATA29.PCIE_IMUX1_R_2 always +PCIE_TOP.PCIE_TOP_MIMRXRDATA30.PCIE_IMUX2_R_2 always +PCIE_TOP.PCIE_TOP_MIMRXRDATA31.PCIE_IMUX3_R_2 always +PCIE_TOP.PCIE_TOP_MIMRXRDATA32.PCIE_IMUX0_R_3 always +PCIE_TOP.PCIE_TOP_MIMRXRDATA33.PCIE_IMUX1_R_3 always +PCIE_TOP.PCIE_TOP_MIMRXRDATA34.PCIE_IMUX2_R_3 always +PCIE_TOP.PCIE_TOP_MIMRXRDATA35.PCIE_IMUX3_R_3 always +PCIE_TOP.PCIE_TOP_MIMRXRDATA36.PCIE_IMUX0_R_4 always +PCIE_TOP.PCIE_TOP_MIMRXRDATA37.PCIE_IMUX1_R_4 always +PCIE_TOP.PCIE_TOP_MIMRXRDATA38.PCIE_IMUX2_R_4 always +PCIE_TOP.PCIE_TOP_MIMRXRDATA39.PCIE_IMUX3_R_4 always +PCIE_TOP.PCIE_TOP_MIMRXRDATA40.PCIE_IMUX4_R_3 always +PCIE_TOP.PCIE_TOP_MIMRXRDATA41.PCIE_IMUX5_R_3 always +PCIE_TOP.PCIE_TOP_MIMRXRDATA42.PCIE_IMUX6_R_3 always +PCIE_TOP.PCIE_TOP_MIMRXRDATA43.PCIE_IMUX7_R_3 always +PCIE_TOP.PCIE_TOP_MIMRXRDATA44.PCIE_IMUX4_R_2 always +PCIE_TOP.PCIE_TOP_MIMRXRDATA45.PCIE_IMUX5_R_2 always +PCIE_TOP.PCIE_TOP_MIMRXRDATA46.PCIE_IMUX6_R_2 always +PCIE_TOP.PCIE_TOP_MIMRXRDATA47.PCIE_IMUX7_R_2 always +PCIE_TOP.PCIE_TOP_MIMRXRDATA48.PCIE_IMUX4_R_1 always +PCIE_TOP.PCIE_TOP_MIMRXRDATA49.PCIE_IMUX5_R_1 always +PCIE_TOP.PCIE_TOP_MIMRXRDATA50.PCIE_IMUX6_R_1 always +PCIE_TOP.PCIE_TOP_MIMRXRDATA51.PCIE_IMUX7_R_1 always +PCIE_TOP.PCIE_TOP_MIMRXRDATA52.PCIE_IMUX4_R_0 always +PCIE_TOP.PCIE_TOP_MIMRXRDATA53.PCIE_IMUX5_R_0 always +PCIE_TOP.PCIE_TOP_MIMRXRDATA54.PCIE_IMUX6_R_0 always +PCIE_TOP.PCIE_TOP_MIMRXRDATA55.PCIE_IMUX7_R_0 always +PCIE_TOP.PCIE_TOP_PIPERX0CHARISK0.PCIE_IMUX16_L_1 always +PCIE_TOP.PCIE_TOP_PIPERX0DATA0.PCIE_IMUX37_L_1 always +PCIE_TOP.PCIE_TOP_PIPERX0DATA1.PCIE_IMUX36_L_1 always +PCIE_TOP.PCIE_TOP_PIPERX0DATA2.PCIE_IMUX33_L_1 always +PCIE_TOP.PCIE_TOP_PIPERX0DATA3.PCIE_IMUX32_L_1 always +PCIE_TOP.PCIE_TOP_PIPERX0DATA4.PCIE_IMUX39_L_0 always +PCIE_TOP.PCIE_TOP_PIPERX0DATA5.PCIE_IMUX38_L_0 always +PCIE_TOP.PCIE_TOP_PIPERX0DATA6.PCIE_IMUX35_L_0 always +PCIE_TOP.PCIE_TOP_PIPERX0DATA7.PCIE_IMUX34_L_0 always +PCIE_TOP.PCIE_TOP_PIPERX4CHARISK0.PCIE_IMUX16_R_1 always +PCIE_TOP.PCIE_TOP_PIPERX4DATA0.PCIE_IMUX37_R_1 always +PCIE_TOP.PCIE_TOP_PIPERX4DATA1.PCIE_IMUX36_R_1 always +PCIE_TOP.PCIE_TOP_PIPERX4DATA2.PCIE_IMUX33_R_1 always +PCIE_TOP.PCIE_TOP_PIPERX4DATA3.PCIE_IMUX32_R_1 always +PCIE_TOP.PCIE_TOP_PIPERX4DATA4.PCIE_IMUX39_R_0 always +PCIE_TOP.PCIE_TOP_PIPERX4DATA5.PCIE_IMUX38_R_0 always +PCIE_TOP.PCIE_TOP_PIPERX4DATA6.PCIE_IMUX35_R_0 always +PCIE_TOP.PCIE_TOP_PIPERX4DATA7.PCIE_IMUX34_R_0 always +PCIE_TOP.PCIE_TOP_PL2DIRECTEDLSTATE0.PCIE_IMUX3_L_4 always +PCIE_TOP.PCIE_TOP_PL2DIRECTEDLSTATE1.PCIE_IMUX8_R_4 always +PCIE_TOP.PCIE_TOP_PL2DIRECTEDLSTATE2.PCIE_IMUX9_R_4 always +PCIE_TOP.PCIE_TOP_PL2DIRECTEDLSTATE3.PCIE_IMUX10_R_4 always +PCIE_TOP.PCIE_TOP_PL2DIRECTEDLSTATE4.PCIE_IMUX11_R_4 always +PCIE_TOP.PCIE_TOP_TRNTD8.PCIE_IMUX8_R_0 always +PCIE_TOP.PCIE_TOP_TRNTD9.PCIE_IMUX9_R_0 always +PCIE_TOP.PCIE_TOP_TRNTD10.PCIE_IMUX10_R_0 always +PCIE_TOP.PCIE_TOP_TRNTD11.PCIE_IMUX11_R_0 always +PCIE_TOP.PCIE_TOP_TRNTD12.PCIE_IMUX8_R_1 always +PCIE_TOP.PCIE_TOP_TRNTD13.PCIE_IMUX9_R_1 always +PCIE_TOP.PCIE_TOP_TRNTD14.PCIE_IMUX10_R_1 always +PCIE_TOP.PCIE_TOP_TRNTD15.PCIE_IMUX11_R_1 always +PCIE_TOP.PCIE_TOP_TRNTD16.PCIE_IMUX8_R_2 always +PCIE_TOP.PCIE_TOP_TRNTD17.PCIE_IMUX9_R_2 always +PCIE_TOP.PCIE_TOP_TRNTD18.PCIE_IMUX10_R_2 always +PCIE_TOP.PCIE_TOP_TRNTD19.PCIE_IMUX11_R_2 always +PCIE_TOP.PCIE_TOP_TRNTD20.PCIE_IMUX8_R_3 always +PCIE_TOP.PCIE_TOP_TRNTD21.PCIE_IMUX9_R_3 always +PCIE_TOP.PCIE_TOP_TRNTD22.PCIE_IMUX10_R_3 always +PCIE_TOP.PCIE_TOP_TRNTD23.PCIE_IMUX11_R_3 always +PCIE_TOP.PCIE_TOP_TRNTD24.PCIE_IMUX4_R_4 always +PCIE_TOP.PCIE_TOP_TRNTD25.PCIE_IMUX5_R_4 always +PCIE_TOP.PCIE_TOP_TRNTD26.PCIE_IMUX6_R_4 always +PCIE_TOP.PCIE_TOP_TRNTD27.PCIE_IMUX7_R_4 always +PCIE_TOP.PCIE_TOP_TRNTD28.PCIE_IMUX12_R_3 always +PCIE_TOP.PCIE_TOP_TRNTD29.PCIE_IMUX13_R_3 always +PCIE_TOP.PCIE_TOP_TRNTD30.PCIE_IMUX14_R_3 always +PCIE_TOP.PCIE_TOP_TRNTD31.PCIE_IMUX15_R_3 always +PCIE_TOP.PCIE_TOP_TRNTD32.PCIE_IMUX12_R_2 always +PCIE_TOP.PCIE_TOP_TRNTD33.PCIE_IMUX13_R_2 always +PCIE_TOP.PCIE_TOP_TRNTD34.PCIE_IMUX14_R_2 always +PCIE_TOP.PCIE_TOP_TRNTD35.PCIE_IMUX15_R_2 always +PCIE_TOP.PCIE_TOP_TRNTD36.PCIE_IMUX12_R_1 always +PCIE_TOP.PCIE_TOP_TRNTD37.PCIE_IMUX13_R_1 always +PCIE_TOP.PCIE_TOP_TRNTD38.PCIE_IMUX14_R_1 always +PCIE_TOP.PCIE_TOP_TRNTD39.PCIE_IMUX15_R_1 always +PCIE_TOP.PCIE_TOP_TRNTD40.PCIE_IMUX12_R_0 always +PCIE_TOP.PCIE_TOP_TRNTD41.PCIE_IMUX13_R_0 always +PCIE_TOP.PCIE_TOP_TRNTDLLPDATA19.PCIE_IMUX0_L_0 always +PCIE_TOP.PCIE_TOP_TRNTDLLPDATA20.PCIE_IMUX1_L_0 always +PCIE_TOP.PCIE_TOP_TRNTDLLPDATA21.PCIE_IMUX2_L_0 always +PCIE_TOP.PCIE_TOP_TRNTDLLPDATA22.PCIE_IMUX3_L_0 always +PCIE_TOP.PCIE_TOP_TRNTDLLPDATA23.PCIE_IMUX0_L_1 always +PCIE_TOP.PCIE_TOP_TRNTDLLPDATA24.PCIE_IMUX1_L_1 always +PCIE_TOP.PCIE_TOP_TRNTDLLPDATA25.PCIE_IMUX2_L_1 always +PCIE_TOP.PCIE_TOP_TRNTDLLPDATA26.PCIE_IMUX3_L_1 always +PCIE_TOP.PCIE_TOP_TRNTDLLPDATA27.PCIE_IMUX0_L_2 always +PCIE_TOP.PCIE_TOP_TRNTDLLPDATA28.PCIE_IMUX1_L_2 always +PCIE_TOP.PCIE_TOP_TRNTDLLPDATA29.PCIE_IMUX2_L_2 always +PCIE_TOP.PCIE_TOP_TRNTDLLPDATA30.PCIE_IMUX3_L_2 always +PCIE_TOP.PCIE_TOP_TRNTDLLPDATA31.PCIE_IMUX0_L_3 always diff --git a/artix7/segbits_cmt_top_l_lower_b.db b/artix7/segbits_cmt_top_l_lower_b.db index b7af7a2..335ac39 100644 --- a/artix7/segbits_cmt_top_l_lower_b.db +++ b/artix7/segbits_cmt_top_l_lower_b.db @@ -25,381 +25,381 @@ CMT_TOP_L_LOWER_B.MMCM_CLK_FREQ_BB_NS2_ACTIVE 28_1068 28_1076 29_1057 CMT_TOP_L_LOWER_B.MMCM_CLK_FREQ_BB_NS2.MMCM_CLK_FREQ_BB_REBUF2_NS 28_1072 29_1067 29_1075 29_1079 CMT_TOP_L_LOWER_B.MMCM_CLK_FREQ_BB_NS3_ACTIVE 28_1058 28_1069 28_1077 CMT_TOP_L_LOWER_B.MMCM_CLK_FREQ_BB_NS3.MMCM_CLK_FREQ_BB_REBUF3_NS 28_1073 29_1068 29_1076 29_1080 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[0] 29_860 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[1] 28_860 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[2] 29_859 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[3] 28_859 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[4] 29_858 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[5] 28_858 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[0] 29_863 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[1] 28_863 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[2] 29_862 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[3] 28_862 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[4] 29_861 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[5] 28_861 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE[0] 29_857 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_PHASE_MUX[0] 28_857 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_PHASE_MUX[1] 29_856 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_PHASE_MUX[2] 28_856 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[0] 29_855 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[1] 28_855 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[2] 29_854 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[3] 28_854 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[4] 29_853 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[5] 28_853 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_EDGE[0] 28_852 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC[0] 29_849 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC[1] 28_849 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC[2] 29_848 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC_EN[0] 28_850 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC_WF_R[0] 29_850 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_MX[0] 29_851 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_MX[1] 28_851 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_NO_COUNT[0] 29_852 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_RESERVED[0] 28_848 -CMT_TOP_L_LOWER_B.MMCME2.COMP.Z_ZHOLD 28_979 28_1020 -CMT_TOP_L_LOWER_B.MMCME2.COMP.ZHOLD 28_1019 29_982 -CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_EDGE[0] 28_841 -CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[0] 29_844 -CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[1] 28_844 -CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[2] 29_843 -CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[3] 28_843 -CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[4] 29_842 -CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[5] 28_842 -CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[0] 29_847 -CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[1] 28_847 -CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[2] 29_846 -CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[3] 28_846 -CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[4] 29_845 -CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[5] 28_845 -CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_NO_COUNT[0] 29_841 -CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_RESERVED[0] 29_840 -CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_RESERVED[1] 28_840 -CMT_TOP_L_LOWER_B.MMCME2.IN_USE 28_18 28_21 28_22 28_23 28_24 28_25 28_27 28_28 28_31 28_32 28_33 28_34 28_36 28_37 28_38 28_39 28_40 28_44 28_46 28_47 28_48 28_49 28_50 28_51 28_52 28_54 28_63 28_65 28_66 28_70 28_72 28_73 28_75 28_77 28_78 28_428 28_429 28_430 28_433 28_434 28_466 28_488 28_492 28_772 28_773 28_774 28_787 28_976 28_978 28_989 28_991 28_1007 29_16 29_18 29_22 29_25 29_28 29_31 29_34 29_35 29_36 29_37 29_39 29_40 29_41 29_42 29_44 29_45 29_46 29_47 29_48 29_51 29_52 29_56 29_57 29_60 29_64 29_65 29_66 29_67 29_68 29_70 29_71 29_72 29_73 29_75 29_76 29_77 29_78 29_95 29_427 29_428 29_431 29_432 29_433 29_463 29_771 29_772 29_775 29_789 29_833 29_836 29_839 29_977 29_981 29_987 29_990 29_991 29_1007 29_1018 -CMT_TOP_L_LOWER_B.MMCME2.INV_CLKINSEL 29_109 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[0] 29_823 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[1] 28_823 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[2] 29_822 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[3] 28_822 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[4] 29_821 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[5] 28_821 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[6] 29_820 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[7] 28_820 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[8] 29_819 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[9] 28_819 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[10] 29_815 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[11] 28_815 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[12] 29_814 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[13] 28_814 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[14] 29_813 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[15] 28_813 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[16] 29_812 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[17] 28_812 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[18] 29_811 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[19] 28_811 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[20] 29_831 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[21] 28_831 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[22] 29_830 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[23] 28_830 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[24] 29_829 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[25] 28_829 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[26] 29_828 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[27] 28_828 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[28] 29_827 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[29] 28_827 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[30] 29_818 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[31] 28_818 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[32] 29_817 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[33] 28_817 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[34] 29_816 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[35] 29_810 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[36] 28_810 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[37] 29_809 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[38] 28_809 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[39] 29_808 -CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[0] 29_703 -CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[1] 28_703 -CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[2] 29_702 -CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[3] 28_702 -CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[4] 29_701 -CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[5] 28_701 -CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[6] 29_700 -CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[7] 28_700 -CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[8] 29_699 -CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[9] 28_699 -CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[10] 29_698 -CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[11] 28_698 -CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[12] 29_697 -CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[13] 28_697 -CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[14] 29_696 -CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[15] 28_696 -CMT_TOP_L_LOWER_B.MMCME2.SS_EN 28_95 28_388 28_696 28_698 28_700 28_702 28_850 28_915 29_389 29_697 29_701 29_703 -CMT_TOP_L_LOWER_B.MMCME2.STARTUP_WAIT 29_94 -CMT_TOP_L_LOWER_B.MMCME2.TABLE[0] 29_389 -CMT_TOP_L_LOWER_B.MMCME2.TABLE[1] 28_388 -CMT_TOP_L_LOWER_B.MMCME2.TABLE[2] 29_387 -CMT_TOP_L_LOWER_B.MMCME2.TABLE[3] 28_386 -CMT_TOP_L_LOWER_B.MMCME2.TABLE[4] 29_385 -CMT_TOP_L_LOWER_B.MMCME2.TABLE[5] 28_384 -CMT_TOP_L_LOWER_B.MMCME2.TABLE[6] 29_395 -CMT_TOP_L_LOWER_B.MMCME2.TABLE[7] 28_394 -CMT_TOP_L_LOWER_B.MMCME2.TABLE[8] 29_393 -CMT_TOP_L_LOWER_B.MMCME2.TABLE[9] 28_392 -CMT_TOP_L_LOWER_B.MMCME2.ZINV_PSEN 28_110 -CMT_TOP_L_LOWER_B.MMCME2.ZINV_PSINCDEC 29_110 -CMT_TOP_L_LOWER_B.MMCME2.ZINV_PWRDWN 28_111 -CMT_TOP_L_LOWER_B.MMCME2.ZINV_RST 29_111 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[0] 29_956 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[1] 28_956 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[2] 29_955 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[3] 28_955 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[4] 29_954 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[5] 28_954 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[0] 29_959 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[1] 28_959 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[2] 29_958 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[3] 28_958 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[4] 29_957 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[5] 28_957 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_OUTPUT_ENABLE[0] 29_953 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_PHASE_MUX[0] 28_953 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_PHASE_MUX[1] 29_952 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_PHASE_MUX[2] 28_952 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[0] 29_951 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[1] 28_951 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[2] 29_950 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[3] 28_950 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[4] 29_949 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[5] 28_949 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_EDGE[0] 28_948 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC[0] 29_945 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC[1] 28_945 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC[2] 29_944 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC_EN[0] 28_946 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC_WF_R[0] 29_946 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_MX[0] 29_947 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_MX[1] 28_947 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_NO_COUNT[0] 29_948 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_RESERVED[0] 28_944 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[0] 29_940 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[1] 28_940 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[2] 29_939 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[3] 28_939 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[4] 29_938 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[5] 28_938 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[0] 29_943 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[1] 28_943 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[2] 29_942 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[3] 28_942 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[4] 29_941 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[5] 28_941 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_OUTPUT_ENABLE[0] 29_937 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_PHASE_MUX[0] 28_937 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_PHASE_MUX[1] 29_936 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_PHASE_MUX[2] 28_936 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[0] 29_935 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[1] 28_935 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[2] 29_934 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[3] 28_934 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[4] 29_933 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[5] 28_933 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_EDGE[0] 28_932 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC[0] 29_929 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC[1] 28_929 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC[2] 29_928 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC_EN[0] 28_930 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC_WF_R[0] 29_930 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_MX[0] 29_931 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_MX[1] 28_931 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_NO_COUNT[0] 29_932 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_RESERVED[0] 28_928 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[0] 29_924 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[1] 28_924 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[2] 29_923 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[3] 28_923 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[4] 29_922 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[5] 28_922 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[0] 29_927 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[1] 28_927 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[2] 29_926 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[3] 28_926 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[4] 29_925 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[5] 28_925 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_OUTPUT_ENABLE[0] 29_921 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_PHASE_MUX[0] 28_921 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_PHASE_MUX[1] 29_920 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_PHASE_MUX[2] 28_920 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[0] 29_919 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[1] 28_919 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[2] 29_918 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[3] 28_918 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[4] 29_917 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[5] 28_917 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_EDGE[0] 28_916 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC[0] 29_913 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC[1] 28_913 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC[2] 29_912 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC_EN[0] 28_914 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC_WF_R[0] 29_914 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_MX[0] 29_915 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_MX[1] 28_915 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_NO_COUNT[0] 29_916 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_RESERVED[0] 28_912 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[0] 29_908 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[1] 28_908 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[2] 29_907 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[3] 28_907 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[4] 29_906 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[5] 28_906 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[0] 29_911 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[1] 28_911 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[2] 29_910 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[3] 28_910 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[4] 29_909 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[5] 28_909 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_OUTPUT_ENABLE[0] 29_905 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_PHASE_MUX[0] 28_905 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_PHASE_MUX[1] 29_904 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_PHASE_MUX[2] 28_904 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[0] 29_903 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[1] 28_903 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[2] 29_902 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[3] 28_902 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[4] 29_901 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[5] 28_901 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_EDGE[0] 28_900 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC[0] 29_897 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC[1] 28_897 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC[2] 29_896 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC_EN[0] 28_898 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC_WF_R[0] 29_898 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_MX[0] 29_899 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_MX[1] 28_899 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_NO_COUNT[0] 29_900 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_RESERVED[0] 28_896 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[0] 29_892 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[1] 28_892 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[2] 29_891 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[3] 28_891 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[4] 29_890 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[5] 28_890 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[0] 29_895 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[1] 28_895 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[2] 29_894 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[3] 28_894 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[4] 29_893 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[5] 28_893 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_OUTPUT_ENABLE[0] 29_889 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_PHASE_MUX[0] 28_889 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_PHASE_MUX[1] 29_888 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_PHASE_MUX[2] 28_888 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[0] 29_887 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[1] 28_887 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[2] 29_886 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[3] 28_886 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[4] 29_885 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[5] 28_885 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_EDGE[0] 28_884 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC[0] 29_881 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC[1] 28_881 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC[2] 29_880 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC_EN[0] 28_882 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC_WF_R[0] 29_882 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_MX[0] 29_883 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_MX[1] 28_883 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_NO_COUNT[0] 29_884 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_RESERVED[0] 28_880 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[0] 29_972 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[1] 28_972 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[2] 29_971 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[3] 28_971 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[4] 29_970 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[5] 28_970 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[0] 29_975 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[1] 28_975 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[2] 29_974 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[3] 28_974 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[4] 29_973 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[5] 28_973 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_OUTPUT_ENABLE[0] 29_969 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_PHASE_MUX[0] 28_969 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_PHASE_MUX[1] 29_968 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_PHASE_MUX[2] 28_968 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[0] 29_967 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[1] 28_967 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[2] 29_966 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[3] 28_966 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[4] 29_965 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[5] 28_965 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_EDGE[0] 28_964 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_FRAC_WF_F[0] 29_962 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_MX[0] 29_963 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_MX[1] 28_963 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_NO_COUNT[0] 29_964 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[0] 28_962 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[1] 29_961 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[2] 28_961 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_RESERVED[0] 29_960 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_RESERVED[1] 28_960 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[0] 29_876 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[1] 28_876 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[2] 29_875 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[3] 28_875 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[4] 29_874 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[5] 28_874 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[0] 29_879 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[1] 28_879 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[2] 29_878 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[3] 28_878 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[4] 29_877 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[5] 28_877 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_OUTPUT_ENABLE[0] 29_873 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_PHASE_MUX[0] 28_873 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_PHASE_MUX[1] 29_872 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_PHASE_MUX[2] 28_872 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[0] 29_871 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[1] 28_871 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[2] 29_870 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[3] 28_870 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[4] 29_869 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[5] 28_869 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_EDGE[0] 28_868 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_FRAC_WF_F[0] 29_866 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_MX[0] 29_867 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_MX[1] 28_867 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_NO_COUNT[0] 29_868 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[0] 28_866 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[1] 29_865 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[2] 28_865 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_RESERVED[0] 29_864 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_RESERVED[1] 28_864 -CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[0] 29_399 -CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[1] 28_399 -CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[2] 29_398 -CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[3] 28_398 -CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[4] 29_397 -CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[5] 28_397 -CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[6] 29_396 -CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[7] 28_396 -CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[8] 28_395 -CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[9] 29_394 -CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[10] 28_393 -CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[11] 29_392 -CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[0] 29_391 -CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[1] 28_391 -CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[2] 29_390 -CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[3] 28_390 -CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[4] 28_389 -CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[5] 29_388 -CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[6] 28_387 -CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[7] 29_386 -CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[8] 28_385 -CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[9] 29_384 -CMT_TOP_L_LOWER_B.MMCME2.LOCKREG1_RESERVED[0] 29_826 -CMT_TOP_L_LOWER_B.MMCME2.LOCKREG1_RESERVED[1] 28_826 -CMT_TOP_L_LOWER_B.MMCME2.LOCKREG1_RESERVED[2] 29_825 -CMT_TOP_L_LOWER_B.MMCME2.LOCKREG1_RESERVED[3] 28_825 -CMT_TOP_L_LOWER_B.MMCME2.LOCKREG1_RESERVED[4] 29_824 -CMT_TOP_L_LOWER_B.MMCME2.LOCKREG1_RESERVED[5] 28_824 -CMT_TOP_L_LOWER_B.MMCME2.LOCKREG2_RESERVED[0] 28_816 -CMT_TOP_L_LOWER_B.MMCME2.LOCKREG3_RESERVED[0] 28_808 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[0] 29_860 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[1] 28_860 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[2] 29_859 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[3] 28_859 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[4] 29_858 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[5] 28_858 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[0] 29_863 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[1] 28_863 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[2] 29_862 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[3] 28_862 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[4] 29_861 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[5] 28_861 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE[0] 29_857 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_PHASE_MUX[0] 28_857 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_PHASE_MUX[1] 29_856 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_PHASE_MUX[2] 28_856 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[0] 29_855 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[1] 28_855 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[2] 29_854 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[3] 28_854 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[4] 29_853 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[5] 28_853 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_EDGE[0] 28_852 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_FRAC[0] 29_849 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_FRAC[1] 28_849 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_FRAC[2] 29_848 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_FRAC_EN[0] 28_850 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_FRAC_WF_R[0] 29_850 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_MX[0] 29_851 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_MX[1] 28_851 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_NO_COUNT[0] 29_852 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_RESERVED[0] 28_848 +CMT_TOP_L_LOWER_B.MMCME2_ADV.COMP.Z_ZHOLD 28_979 28_1020 +CMT_TOP_L_LOWER_B.MMCME2_ADV.COMP.ZHOLD 28_1019 29_982 +CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_EDGE[0] 28_841 +CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_HIGH_TIME[0] 29_844 +CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_HIGH_TIME[1] 28_844 +CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_HIGH_TIME[2] 29_843 +CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_HIGH_TIME[3] 28_843 +CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_HIGH_TIME[4] 29_842 +CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_HIGH_TIME[5] 28_842 +CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_LOW_TIME[0] 29_847 +CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_LOW_TIME[1] 28_847 +CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_LOW_TIME[2] 29_846 +CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_LOW_TIME[3] 28_846 +CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_LOW_TIME[4] 29_845 +CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_LOW_TIME[5] 28_845 +CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_NO_COUNT[0] 29_841 +CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_RESERVED[0] 29_840 +CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_RESERVED[1] 28_840 +CMT_TOP_L_LOWER_B.MMCME2_ADV.IN_USE 28_18 28_21 28_22 28_23 28_24 28_25 28_27 28_28 28_31 28_32 28_33 28_34 28_36 28_37 28_38 28_39 28_40 28_44 28_46 28_47 28_48 28_49 28_50 28_51 28_52 28_54 28_63 28_65 28_66 28_70 28_72 28_73 28_75 28_77 28_78 28_428 28_429 28_430 28_433 28_434 28_466 28_488 28_492 28_772 28_773 28_774 28_787 28_976 28_978 28_989 28_991 28_1007 29_16 29_18 29_22 29_25 29_28 29_31 29_34 29_35 29_36 29_37 29_39 29_40 29_41 29_42 29_44 29_45 29_46 29_47 29_48 29_51 29_52 29_56 29_57 29_60 29_64 29_65 29_66 29_67 29_68 29_70 29_71 29_72 29_73 29_75 29_76 29_77 29_78 29_95 29_427 29_428 29_431 29_432 29_433 29_463 29_771 29_772 29_775 29_789 29_833 29_836 29_839 29_977 29_981 29_987 29_990 29_991 29_1007 29_1018 +CMT_TOP_L_LOWER_B.MMCME2_ADV.INV_CLKINSEL 29_109 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[0] 29_823 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[1] 28_823 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[2] 29_822 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[3] 28_822 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[4] 29_821 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[5] 28_821 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[6] 29_820 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[7] 28_820 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[8] 29_819 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[9] 28_819 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[10] 29_815 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[11] 28_815 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[12] 29_814 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[13] 28_814 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[14] 29_813 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[15] 28_813 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[16] 29_812 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[17] 28_812 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[18] 29_811 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[19] 28_811 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[20] 29_831 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[21] 28_831 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[22] 29_830 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[23] 28_830 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[24] 29_829 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[25] 28_829 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[26] 29_828 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[27] 28_828 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[28] 29_827 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[29] 28_827 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[30] 29_818 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[31] 28_818 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[32] 29_817 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[33] 28_817 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[34] 29_816 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[35] 29_810 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[36] 28_810 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[37] 29_809 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[38] 28_809 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[39] 29_808 +CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[0] 29_703 +CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[1] 28_703 +CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[2] 29_702 +CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[3] 28_702 +CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[4] 29_701 +CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[5] 28_701 +CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[6] 29_700 +CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[7] 28_700 +CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[8] 29_699 +CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[9] 28_699 +CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[10] 29_698 +CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[11] 28_698 +CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[12] 29_697 +CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[13] 28_697 +CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[14] 29_696 +CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[15] 28_696 +CMT_TOP_L_LOWER_B.MMCME2_ADV.SS_EN 28_95 28_388 28_696 28_698 28_700 28_702 28_850 28_915 29_389 29_697 29_701 29_703 +CMT_TOP_L_LOWER_B.MMCME2_ADV.STARTUP_WAIT 29_94 +CMT_TOP_L_LOWER_B.MMCME2_ADV.TABLE[0] 29_389 +CMT_TOP_L_LOWER_B.MMCME2_ADV.TABLE[1] 28_388 +CMT_TOP_L_LOWER_B.MMCME2_ADV.TABLE[2] 29_387 +CMT_TOP_L_LOWER_B.MMCME2_ADV.TABLE[3] 28_386 +CMT_TOP_L_LOWER_B.MMCME2_ADV.TABLE[4] 29_385 +CMT_TOP_L_LOWER_B.MMCME2_ADV.TABLE[5] 28_384 +CMT_TOP_L_LOWER_B.MMCME2_ADV.TABLE[6] 29_395 +CMT_TOP_L_LOWER_B.MMCME2_ADV.TABLE[7] 28_394 +CMT_TOP_L_LOWER_B.MMCME2_ADV.TABLE[8] 29_393 +CMT_TOP_L_LOWER_B.MMCME2_ADV.TABLE[9] 28_392 +CMT_TOP_L_LOWER_B.MMCME2_ADV.ZINV_PSEN 28_110 +CMT_TOP_L_LOWER_B.MMCME2_ADV.ZINV_PSINCDEC 29_110 +CMT_TOP_L_LOWER_B.MMCME2_ADV.ZINV_PWRDWN 28_111 +CMT_TOP_L_LOWER_B.MMCME2_ADV.ZINV_RST 29_111 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[0] 29_956 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[1] 28_956 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[2] 29_955 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[3] 28_955 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[4] 29_954 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[5] 28_954 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[0] 29_959 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[1] 28_959 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[2] 29_958 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[3] 28_958 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[4] 29_957 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[5] 28_957 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_OUTPUT_ENABLE[0] 29_953 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_PHASE_MUX[0] 28_953 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_PHASE_MUX[1] 29_952 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_PHASE_MUX[2] 28_952 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[0] 29_951 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[1] 28_951 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[2] 29_950 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[3] 28_950 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[4] 29_949 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[5] 28_949 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_EDGE[0] 28_948 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_FRAC[0] 29_945 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_FRAC[1] 28_945 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_FRAC[2] 29_944 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_FRAC_EN[0] 28_946 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_FRAC_WF_R[0] 29_946 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_MX[0] 29_947 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_MX[1] 28_947 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_NO_COUNT[0] 29_948 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_RESERVED[0] 28_944 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[0] 29_940 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[1] 28_940 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[2] 29_939 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[3] 28_939 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[4] 29_938 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[5] 28_938 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[0] 29_943 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[1] 28_943 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[2] 29_942 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[3] 28_942 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[4] 29_941 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[5] 28_941 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_OUTPUT_ENABLE[0] 29_937 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_PHASE_MUX[0] 28_937 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_PHASE_MUX[1] 29_936 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_PHASE_MUX[2] 28_936 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[0] 29_935 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[1] 28_935 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[2] 29_934 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[3] 28_934 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[4] 29_933 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[5] 28_933 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_EDGE[0] 28_932 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_FRAC[0] 29_929 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_FRAC[1] 28_929 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_FRAC[2] 29_928 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_FRAC_EN[0] 28_930 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_FRAC_WF_R[0] 29_930 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_MX[0] 29_931 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_MX[1] 28_931 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_NO_COUNT[0] 29_932 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_RESERVED[0] 28_928 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[0] 29_924 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[1] 28_924 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[2] 29_923 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[3] 28_923 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[4] 29_922 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[5] 28_922 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[0] 29_927 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[1] 28_927 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[2] 29_926 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[3] 28_926 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[4] 29_925 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[5] 28_925 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_OUTPUT_ENABLE[0] 29_921 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_PHASE_MUX[0] 28_921 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_PHASE_MUX[1] 29_920 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_PHASE_MUX[2] 28_920 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[0] 29_919 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[1] 28_919 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[2] 29_918 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[3] 28_918 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[4] 29_917 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[5] 28_917 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_EDGE[0] 28_916 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_FRAC[0] 29_913 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_FRAC[1] 28_913 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_FRAC[2] 29_912 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_FRAC_EN[0] 28_914 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_FRAC_WF_R[0] 29_914 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_MX[0] 29_915 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_MX[1] 28_915 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_NO_COUNT[0] 29_916 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_RESERVED[0] 28_912 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[0] 29_908 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[1] 28_908 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[2] 29_907 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[3] 28_907 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[4] 29_906 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[5] 28_906 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[0] 29_911 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[1] 28_911 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[2] 29_910 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[3] 28_910 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[4] 29_909 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[5] 28_909 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_OUTPUT_ENABLE[0] 29_905 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_PHASE_MUX[0] 28_905 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_PHASE_MUX[1] 29_904 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_PHASE_MUX[2] 28_904 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[0] 29_903 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[1] 28_903 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[2] 29_902 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[3] 28_902 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[4] 29_901 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[5] 28_901 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_EDGE[0] 28_900 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_FRAC[0] 29_897 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_FRAC[1] 28_897 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_FRAC[2] 29_896 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_FRAC_EN[0] 28_898 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_FRAC_WF_R[0] 29_898 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_MX[0] 29_899 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_MX[1] 28_899 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_NO_COUNT[0] 29_900 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_RESERVED[0] 28_896 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[0] 29_892 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[1] 28_892 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[2] 29_891 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[3] 28_891 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[4] 29_890 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[5] 28_890 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[0] 29_895 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[1] 28_895 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[2] 29_894 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[3] 28_894 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[4] 29_893 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[5] 28_893 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_OUTPUT_ENABLE[0] 29_889 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_PHASE_MUX[0] 28_889 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_PHASE_MUX[1] 29_888 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_PHASE_MUX[2] 28_888 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[0] 29_887 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[1] 28_887 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[2] 29_886 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[3] 28_886 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[4] 29_885 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[5] 28_885 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_EDGE[0] 28_884 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_FRAC[0] 29_881 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_FRAC[1] 28_881 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_FRAC[2] 29_880 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_FRAC_EN[0] 28_882 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_FRAC_WF_R[0] 29_882 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_MX[0] 29_883 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_MX[1] 28_883 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_NO_COUNT[0] 29_884 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_RESERVED[0] 28_880 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[0] 29_972 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[1] 28_972 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[2] 29_971 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[3] 28_971 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[4] 29_970 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[5] 28_970 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[0] 29_975 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[1] 28_975 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[2] 29_974 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[3] 28_974 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[4] 29_973 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[5] 28_973 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_OUTPUT_ENABLE[0] 29_969 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_PHASE_MUX[0] 28_969 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_PHASE_MUX[1] 29_968 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_PHASE_MUX[2] 28_968 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[0] 29_967 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[1] 28_967 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[2] 29_966 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[3] 28_966 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[4] 29_965 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[5] 28_965 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_EDGE[0] 28_964 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_FRAC_WF_F[0] 29_962 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_MX[0] 29_963 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_MX[1] 28_963 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_NO_COUNT[0] 29_964 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[0] 28_962 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[1] 29_961 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[2] 28_961 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_RESERVED[0] 29_960 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_RESERVED[1] 28_960 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_HIGH_TIME[0] 29_876 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_HIGH_TIME[1] 28_876 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_HIGH_TIME[2] 29_875 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_HIGH_TIME[3] 28_875 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_HIGH_TIME[4] 29_874 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_HIGH_TIME[5] 28_874 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_LOW_TIME[0] 29_879 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_LOW_TIME[1] 28_879 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_LOW_TIME[2] 29_878 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_LOW_TIME[3] 28_878 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_LOW_TIME[4] 29_877 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_LOW_TIME[5] 28_877 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_OUTPUT_ENABLE[0] 29_873 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_PHASE_MUX[0] 28_873 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_PHASE_MUX[1] 29_872 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_PHASE_MUX[2] 28_872 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[0] 29_871 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[1] 28_871 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[2] 29_870 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[3] 28_870 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[4] 29_869 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[5] 28_869 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_EDGE[0] 28_868 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_FRAC_WF_F[0] 29_866 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_MX[0] 29_867 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_MX[1] 28_867 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_NO_COUNT[0] 29_868 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[0] 28_866 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[1] 29_865 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[2] 28_865 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_RESERVED[0] 29_864 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_RESERVED[1] 28_864 +CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[0] 29_399 +CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[1] 28_399 +CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[2] 29_398 +CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[3] 28_398 +CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[4] 29_397 +CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[5] 28_397 +CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[6] 29_396 +CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[7] 28_396 +CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[8] 28_395 +CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[9] 29_394 +CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[10] 28_393 +CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[11] 29_392 +CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[0] 29_391 +CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[1] 28_391 +CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[2] 29_390 +CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[3] 28_390 +CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[4] 28_389 +CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[5] 29_388 +CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[6] 28_387 +CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[7] 29_386 +CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[8] 28_385 +CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[9] 29_384 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LOCKREG1_RESERVED[0] 29_826 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LOCKREG1_RESERVED[1] 28_826 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LOCKREG1_RESERVED[2] 29_825 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LOCKREG1_RESERVED[3] 28_825 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LOCKREG1_RESERVED[4] 29_824 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LOCKREG1_RESERVED[5] 28_824 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LOCKREG2_RESERVED[0] 28_816 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LOCKREG3_RESERVED[0] 28_808 diff --git a/artix7/segbits_cmt_top_l_lower_b.origin_info.db b/artix7/segbits_cmt_top_l_lower_b.origin_info.db index 26d659a..08fbfa6 100644 --- a/artix7/segbits_cmt_top_l_lower_b.origin_info.db +++ b/artix7/segbits_cmt_top_l_lower_b.origin_info.db @@ -25,381 +25,381 @@ CMT_TOP_L_LOWER_B.MMCM_CLK_FREQ_BB_NS2_ACTIVE origin:034b-cmt-mmcm-pips 28_1068 CMT_TOP_L_LOWER_B.MMCM_CLK_FREQ_BB_NS2.MMCM_CLK_FREQ_BB_REBUF2_NS origin:034b-cmt-mmcm-pips 28_1072 29_1067 29_1075 29_1079 CMT_TOP_L_LOWER_B.MMCM_CLK_FREQ_BB_NS3_ACTIVE origin:034b-cmt-mmcm-pips 28_1058 28_1069 28_1077 CMT_TOP_L_LOWER_B.MMCM_CLK_FREQ_BB_NS3.MMCM_CLK_FREQ_BB_REBUF3_NS origin:034b-cmt-mmcm-pips 28_1073 29_1068 29_1076 29_1080 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_860 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_860 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_859 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_859 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_858 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_858 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_863 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_863 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_862 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_862 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_861 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_861 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_857 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_857 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_856 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_856 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_855 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_855 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_854 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_854 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_853 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_853 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_852 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_849 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_849 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_848 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_850 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_850 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_851 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_851 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_852 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_848 -CMT_TOP_L_LOWER_B.MMCME2.COMP.Z_ZHOLD origin:031-cmt-mmcm 28_1020 28_979 -CMT_TOP_L_LOWER_B.MMCME2.COMP.ZHOLD origin:031-cmt-mmcm 28_1019 29_982 -CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_EDGE[0] origin:031-cmt-mmcm 28_841 -CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[0] origin:031-cmt-mmcm 29_844 -CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[1] origin:031-cmt-mmcm 28_844 -CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[2] origin:031-cmt-mmcm 29_843 -CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[3] origin:031-cmt-mmcm 28_843 -CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[4] origin:031-cmt-mmcm 29_842 -CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[5] origin:031-cmt-mmcm 28_842 -CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[0] origin:031-cmt-mmcm 29_847 -CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[1] origin:031-cmt-mmcm 28_847 -CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[2] origin:031-cmt-mmcm 29_846 -CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[3] origin:031-cmt-mmcm 28_846 -CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[4] origin:031-cmt-mmcm 29_845 -CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[5] origin:031-cmt-mmcm 28_845 -CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_NO_COUNT[0] origin:031-cmt-mmcm 29_841 -CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_RESERVED[0] origin:031-cmt-mmcm 29_840 -CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_RESERVED[1] origin:031-cmt-mmcm 28_840 -CMT_TOP_L_LOWER_B.MMCME2.IN_USE origin:031-cmt-mmcm 28_1007 28_18 28_21 28_22 28_23 28_24 28_25 28_27 28_28 28_31 28_32 28_33 28_34 28_36 28_37 28_38 28_39 28_40 28_428 28_429 28_430 28_433 28_434 28_44 28_46 28_466 28_47 28_48 28_488 28_49 28_492 28_50 28_51 28_52 28_54 28_63 28_65 28_66 28_70 28_72 28_73 28_75 28_77 28_772 28_773 28_774 28_78 28_787 28_976 28_978 28_989 28_991 29_1007 29_1018 29_16 29_18 29_22 29_25 29_28 29_31 29_34 29_35 29_36 29_37 29_39 29_40 29_41 29_42 29_427 29_428 29_431 29_432 29_433 29_44 29_45 29_46 29_463 29_47 29_48 29_51 29_52 29_56 29_57 29_60 29_64 29_65 29_66 29_67 29_68 29_70 29_71 29_72 29_73 29_75 29_76 29_77 29_771 29_772 29_775 29_78 29_789 29_833 29_836 29_839 29_95 29_977 29_981 29_987 29_990 29_991 -CMT_TOP_L_LOWER_B.MMCME2.INV_CLKINSEL origin:031-cmt-mmcm 29_109 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[0] origin:031-cmt-mmcm 29_823 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[1] origin:031-cmt-mmcm 28_823 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[2] origin:031-cmt-mmcm 29_822 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[3] origin:031-cmt-mmcm 28_822 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[4] origin:031-cmt-mmcm 29_821 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[5] origin:031-cmt-mmcm 28_821 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[6] origin:031-cmt-mmcm 29_820 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[7] origin:031-cmt-mmcm 28_820 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[8] origin:031-cmt-mmcm 29_819 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[9] origin:031-cmt-mmcm 28_819 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[10] origin:031-cmt-mmcm 29_815 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[11] origin:031-cmt-mmcm 28_815 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[12] origin:031-cmt-mmcm 29_814 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[13] origin:031-cmt-mmcm 28_814 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[14] origin:031-cmt-mmcm 29_813 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[15] origin:031-cmt-mmcm 28_813 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[16] origin:031-cmt-mmcm 29_812 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[17] origin:031-cmt-mmcm 28_812 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[18] origin:031-cmt-mmcm 29_811 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[19] origin:031-cmt-mmcm 28_811 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[20] origin:031-cmt-mmcm 29_831 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[21] origin:031-cmt-mmcm 28_831 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[22] origin:031-cmt-mmcm 29_830 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[23] origin:031-cmt-mmcm 28_830 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[24] origin:031-cmt-mmcm 29_829 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[25] origin:031-cmt-mmcm 28_829 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[26] origin:031-cmt-mmcm 29_828 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[27] origin:031-cmt-mmcm 28_828 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[28] origin:031-cmt-mmcm 29_827 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[29] origin:031-cmt-mmcm 28_827 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[30] origin:031-cmt-mmcm 29_818 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[31] origin:031-cmt-mmcm 28_818 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[32] origin:031-cmt-mmcm 29_817 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[33] origin:031-cmt-mmcm 28_817 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[34] origin:031-cmt-mmcm 29_816 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[35] origin:031-cmt-mmcm 29_810 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[36] origin:031-cmt-mmcm 28_810 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[37] origin:031-cmt-mmcm 29_809 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[38] origin:031-cmt-mmcm 28_809 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[39] origin:031-cmt-mmcm 29_808 -CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[0] origin:031-cmt-mmcm 29_703 -CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[1] origin:031-cmt-mmcm 28_703 -CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[2] origin:031-cmt-mmcm 29_702 -CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[3] origin:031-cmt-mmcm 28_702 -CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[4] origin:031-cmt-mmcm 29_701 -CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[5] origin:031-cmt-mmcm 28_701 -CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[6] origin:031-cmt-mmcm 29_700 -CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[7] origin:031-cmt-mmcm 28_700 -CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[8] origin:031-cmt-mmcm 29_699 -CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[9] origin:031-cmt-mmcm 28_699 -CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[10] origin:031-cmt-mmcm 29_698 -CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[11] origin:031-cmt-mmcm 28_698 -CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[12] origin:031-cmt-mmcm 29_697 -CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[13] origin:031-cmt-mmcm 28_697 -CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[14] origin:031-cmt-mmcm 29_696 -CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[15] origin:031-cmt-mmcm 28_696 -CMT_TOP_L_LOWER_B.MMCME2.SS_EN origin:031-cmt-mmcm 28_388 28_696 28_698 28_700 28_702 28_850 28_915 28_95 29_389 29_697 29_701 29_703 -CMT_TOP_L_LOWER_B.MMCME2.STARTUP_WAIT origin:031-cmt-mmcm 29_94 -CMT_TOP_L_LOWER_B.MMCME2.TABLE[0] origin:031-cmt-mmcm 29_389 -CMT_TOP_L_LOWER_B.MMCME2.TABLE[1] origin:031-cmt-mmcm 28_388 -CMT_TOP_L_LOWER_B.MMCME2.TABLE[2] origin:031-cmt-mmcm 29_387 -CMT_TOP_L_LOWER_B.MMCME2.TABLE[3] origin:031-cmt-mmcm 28_386 -CMT_TOP_L_LOWER_B.MMCME2.TABLE[4] origin:031-cmt-mmcm 29_385 -CMT_TOP_L_LOWER_B.MMCME2.TABLE[5] origin:031-cmt-mmcm 28_384 -CMT_TOP_L_LOWER_B.MMCME2.TABLE[6] origin:031-cmt-mmcm 29_395 -CMT_TOP_L_LOWER_B.MMCME2.TABLE[7] origin:031-cmt-mmcm 28_394 -CMT_TOP_L_LOWER_B.MMCME2.TABLE[8] origin:031-cmt-mmcm 29_393 -CMT_TOP_L_LOWER_B.MMCME2.TABLE[9] origin:031-cmt-mmcm 28_392 -CMT_TOP_L_LOWER_B.MMCME2.ZINV_PSEN origin:031-cmt-mmcm 28_110 -CMT_TOP_L_LOWER_B.MMCME2.ZINV_PSINCDEC origin:031-cmt-mmcm 29_110 -CMT_TOP_L_LOWER_B.MMCME2.ZINV_PWRDWN origin:031-cmt-mmcm 28_111 -CMT_TOP_L_LOWER_B.MMCME2.ZINV_RST origin:031-cmt-mmcm 29_111 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_956 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_956 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_955 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_955 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_954 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_954 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_959 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_959 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_958 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_958 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_957 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_957 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_953 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_953 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_952 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_952 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_951 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_951 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_950 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_950 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_949 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_949 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_948 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_945 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_945 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_944 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_946 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_946 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_947 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_947 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_948 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_944 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_940 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_940 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_939 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_939 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_938 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_938 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_943 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_943 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_942 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_942 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_941 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_941 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_937 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_937 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_936 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_936 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_935 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_935 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_934 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_934 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_933 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_933 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_932 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_929 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_929 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_928 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_930 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_930 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_931 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_931 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_932 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_928 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_924 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_924 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_923 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_923 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_922 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_922 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_927 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_927 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_926 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_926 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_925 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_925 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_921 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_921 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_920 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_920 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_919 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_919 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_918 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_918 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_917 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_917 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_916 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_913 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_913 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_912 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_914 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_914 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_915 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_915 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_916 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_912 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_908 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_908 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_907 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_907 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_906 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_906 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_911 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_911 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_910 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_910 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_909 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_909 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_905 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_905 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_904 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_904 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_903 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_903 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_902 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_902 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_901 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_901 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_900 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_897 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_897 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_896 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_898 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_898 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_899 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_899 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_900 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_896 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_892 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_892 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_891 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_891 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_890 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_890 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_895 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_895 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_894 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_894 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_893 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_893 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_889 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_889 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_888 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_888 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_887 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_887 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_886 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_886 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_885 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_885 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_884 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_881 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_881 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_880 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_882 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_882 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_883 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_883 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_884 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_880 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_972 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_972 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_971 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_971 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_970 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_970 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_975 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_975 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_974 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_974 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_973 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_973 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_969 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_969 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_968 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_968 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[0] origin:031-cmt-mmcm 29_967 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[1] origin:031-cmt-mmcm 28_967 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[2] origin:031-cmt-mmcm 29_966 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[3] origin:031-cmt-mmcm 28_966 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[4] origin:031-cmt-mmcm 29_965 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[5] origin:031-cmt-mmcm 28_965 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_EDGE[0] origin:031-cmt-mmcm 28_964 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_FRAC_WF_F[0] origin:031-cmt-mmcm 29_962 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_MX[0] origin:031-cmt-mmcm 29_963 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_MX[1] origin:031-cmt-mmcm 28_963 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_NO_COUNT[0] origin:031-cmt-mmcm 29_964 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[0] origin:031-cmt-mmcm 28_962 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[1] origin:031-cmt-mmcm 29_961 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[2] origin:031-cmt-mmcm 28_961 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_RESERVED[0] origin:031-cmt-mmcm 29_960 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_RESERVED[1] origin:031-cmt-mmcm 28_960 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_876 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_876 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_875 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_875 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_874 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_874 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_879 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_879 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_878 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_878 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_877 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_877 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_873 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_873 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_872 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_872 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[0] origin:031-cmt-mmcm 29_871 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[1] origin:031-cmt-mmcm 28_871 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[2] origin:031-cmt-mmcm 29_870 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[3] origin:031-cmt-mmcm 28_870 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[4] origin:031-cmt-mmcm 29_869 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[5] origin:031-cmt-mmcm 28_869 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_EDGE[0] origin:031-cmt-mmcm 28_868 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_FRAC_WF_F[0] origin:031-cmt-mmcm 29_866 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_MX[0] origin:031-cmt-mmcm 29_867 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_MX[1] origin:031-cmt-mmcm 28_867 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_NO_COUNT[0] origin:031-cmt-mmcm 29_868 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[0] origin:031-cmt-mmcm 28_866 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[1] origin:031-cmt-mmcm 29_865 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[2] origin:031-cmt-mmcm 28_865 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_RESERVED[0] origin:031-cmt-mmcm 29_864 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_RESERVED[1] origin:031-cmt-mmcm 28_864 -CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[0] origin:031-cmt-mmcm 29_399 -CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[1] origin:031-cmt-mmcm 28_399 -CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[2] origin:031-cmt-mmcm 29_398 -CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[3] origin:031-cmt-mmcm 28_398 -CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[4] origin:031-cmt-mmcm 29_397 -CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[5] origin:031-cmt-mmcm 28_397 -CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[6] origin:031-cmt-mmcm 29_396 -CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[7] origin:031-cmt-mmcm 28_396 -CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[8] origin:031-cmt-mmcm 28_395 -CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[9] origin:031-cmt-mmcm 29_394 -CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[10] origin:031-cmt-mmcm 28_393 -CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[11] origin:031-cmt-mmcm 29_392 -CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[0] origin:031-cmt-mmcm 29_391 -CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[1] origin:031-cmt-mmcm 28_391 -CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[2] origin:031-cmt-mmcm 29_390 -CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[3] origin:031-cmt-mmcm 28_390 -CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[4] origin:031-cmt-mmcm 28_389 -CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[5] origin:031-cmt-mmcm 29_388 -CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[6] origin:031-cmt-mmcm 28_387 -CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[7] origin:031-cmt-mmcm 29_386 -CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[8] origin:031-cmt-mmcm 28_385 -CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[9] origin:031-cmt-mmcm 29_384 -CMT_TOP_L_LOWER_B.MMCME2.LOCKREG1_RESERVED[0] origin:031-cmt-mmcm 29_826 -CMT_TOP_L_LOWER_B.MMCME2.LOCKREG1_RESERVED[1] origin:031-cmt-mmcm 28_826 -CMT_TOP_L_LOWER_B.MMCME2.LOCKREG1_RESERVED[2] origin:031-cmt-mmcm 29_825 -CMT_TOP_L_LOWER_B.MMCME2.LOCKREG1_RESERVED[3] origin:031-cmt-mmcm 28_825 -CMT_TOP_L_LOWER_B.MMCME2.LOCKREG1_RESERVED[4] origin:031-cmt-mmcm 29_824 -CMT_TOP_L_LOWER_B.MMCME2.LOCKREG1_RESERVED[5] origin:031-cmt-mmcm 28_824 -CMT_TOP_L_LOWER_B.MMCME2.LOCKREG2_RESERVED[0] origin:031-cmt-mmcm 28_816 -CMT_TOP_L_LOWER_B.MMCME2.LOCKREG3_RESERVED[0] origin:031-cmt-mmcm 28_808 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_860 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_860 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_859 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_859 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_858 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_858 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_863 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_863 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_862 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_862 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_861 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_861 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_857 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_857 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_856 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_856 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_855 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_855 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_854 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_854 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_853 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_853 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_852 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_849 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_849 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_848 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_850 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_850 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_851 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_851 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_852 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_848 +CMT_TOP_L_LOWER_B.MMCME2_ADV.COMP.Z_ZHOLD origin:031-cmt-mmcm 28_1020 28_979 +CMT_TOP_L_LOWER_B.MMCME2_ADV.COMP.ZHOLD origin:031-cmt-mmcm 28_1019 29_982 +CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_EDGE[0] origin:031-cmt-mmcm 28_841 +CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_HIGH_TIME[0] origin:031-cmt-mmcm 29_844 +CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_HIGH_TIME[1] origin:031-cmt-mmcm 28_844 +CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_HIGH_TIME[2] origin:031-cmt-mmcm 29_843 +CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_HIGH_TIME[3] origin:031-cmt-mmcm 28_843 +CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_HIGH_TIME[4] origin:031-cmt-mmcm 29_842 +CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_HIGH_TIME[5] origin:031-cmt-mmcm 28_842 +CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_LOW_TIME[0] origin:031-cmt-mmcm 29_847 +CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_LOW_TIME[1] origin:031-cmt-mmcm 28_847 +CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_LOW_TIME[2] origin:031-cmt-mmcm 29_846 +CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_LOW_TIME[3] origin:031-cmt-mmcm 28_846 +CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_LOW_TIME[4] origin:031-cmt-mmcm 29_845 +CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_LOW_TIME[5] origin:031-cmt-mmcm 28_845 +CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_NO_COUNT[0] origin:031-cmt-mmcm 29_841 +CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_RESERVED[0] origin:031-cmt-mmcm 29_840 +CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_RESERVED[1] origin:031-cmt-mmcm 28_840 +CMT_TOP_L_LOWER_B.MMCME2_ADV.IN_USE origin:031-cmt-mmcm 28_1007 28_18 28_21 28_22 28_23 28_24 28_25 28_27 28_28 28_31 28_32 28_33 28_34 28_36 28_37 28_38 28_39 28_40 28_428 28_429 28_430 28_433 28_434 28_44 28_46 28_466 28_47 28_48 28_488 28_49 28_492 28_50 28_51 28_52 28_54 28_63 28_65 28_66 28_70 28_72 28_73 28_75 28_77 28_772 28_773 28_774 28_78 28_787 28_976 28_978 28_989 28_991 29_1007 29_1018 29_16 29_18 29_22 29_25 29_28 29_31 29_34 29_35 29_36 29_37 29_39 29_40 29_41 29_42 29_427 29_428 29_431 29_432 29_433 29_44 29_45 29_46 29_463 29_47 29_48 29_51 29_52 29_56 29_57 29_60 29_64 29_65 29_66 29_67 29_68 29_70 29_71 29_72 29_73 29_75 29_76 29_77 29_771 29_772 29_775 29_78 29_789 29_833 29_836 29_839 29_95 29_977 29_981 29_987 29_990 29_991 +CMT_TOP_L_LOWER_B.MMCME2_ADV.INV_CLKINSEL origin:031-cmt-mmcm 29_109 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[0] origin:031-cmt-mmcm 29_823 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[1] origin:031-cmt-mmcm 28_823 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[2] origin:031-cmt-mmcm 29_822 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[3] origin:031-cmt-mmcm 28_822 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[4] origin:031-cmt-mmcm 29_821 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[5] origin:031-cmt-mmcm 28_821 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[6] origin:031-cmt-mmcm 29_820 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[7] origin:031-cmt-mmcm 28_820 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[8] origin:031-cmt-mmcm 29_819 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[9] origin:031-cmt-mmcm 28_819 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[10] origin:031-cmt-mmcm 29_815 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[11] origin:031-cmt-mmcm 28_815 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[12] origin:031-cmt-mmcm 29_814 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[13] origin:031-cmt-mmcm 28_814 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[14] origin:031-cmt-mmcm 29_813 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[15] origin:031-cmt-mmcm 28_813 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[16] origin:031-cmt-mmcm 29_812 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[17] origin:031-cmt-mmcm 28_812 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[18] origin:031-cmt-mmcm 29_811 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[19] origin:031-cmt-mmcm 28_811 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[20] origin:031-cmt-mmcm 29_831 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[21] origin:031-cmt-mmcm 28_831 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[22] origin:031-cmt-mmcm 29_830 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[23] origin:031-cmt-mmcm 28_830 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[24] origin:031-cmt-mmcm 29_829 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[25] origin:031-cmt-mmcm 28_829 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[26] origin:031-cmt-mmcm 29_828 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[27] origin:031-cmt-mmcm 28_828 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[28] origin:031-cmt-mmcm 29_827 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[29] origin:031-cmt-mmcm 28_827 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[30] origin:031-cmt-mmcm 29_818 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[31] origin:031-cmt-mmcm 28_818 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[32] origin:031-cmt-mmcm 29_817 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[33] origin:031-cmt-mmcm 28_817 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[34] origin:031-cmt-mmcm 29_816 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[35] origin:031-cmt-mmcm 29_810 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[36] origin:031-cmt-mmcm 28_810 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[37] origin:031-cmt-mmcm 29_809 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[38] origin:031-cmt-mmcm 28_809 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[39] origin:031-cmt-mmcm 29_808 +CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[0] origin:031-cmt-mmcm 29_703 +CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[1] origin:031-cmt-mmcm 28_703 +CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[2] origin:031-cmt-mmcm 29_702 +CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[3] origin:031-cmt-mmcm 28_702 +CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[4] origin:031-cmt-mmcm 29_701 +CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[5] origin:031-cmt-mmcm 28_701 +CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[6] origin:031-cmt-mmcm 29_700 +CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[7] origin:031-cmt-mmcm 28_700 +CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[8] origin:031-cmt-mmcm 29_699 +CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[9] origin:031-cmt-mmcm 28_699 +CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[10] origin:031-cmt-mmcm 29_698 +CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[11] origin:031-cmt-mmcm 28_698 +CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[12] origin:031-cmt-mmcm 29_697 +CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[13] origin:031-cmt-mmcm 28_697 +CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[14] origin:031-cmt-mmcm 29_696 +CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[15] origin:031-cmt-mmcm 28_696 +CMT_TOP_L_LOWER_B.MMCME2_ADV.SS_EN origin:031-cmt-mmcm 28_388 28_696 28_698 28_700 28_702 28_850 28_915 28_95 29_389 29_697 29_701 29_703 +CMT_TOP_L_LOWER_B.MMCME2_ADV.STARTUP_WAIT origin:031-cmt-mmcm 29_94 +CMT_TOP_L_LOWER_B.MMCME2_ADV.TABLE[0] origin:031-cmt-mmcm 29_389 +CMT_TOP_L_LOWER_B.MMCME2_ADV.TABLE[1] origin:031-cmt-mmcm 28_388 +CMT_TOP_L_LOWER_B.MMCME2_ADV.TABLE[2] origin:031-cmt-mmcm 29_387 +CMT_TOP_L_LOWER_B.MMCME2_ADV.TABLE[3] origin:031-cmt-mmcm 28_386 +CMT_TOP_L_LOWER_B.MMCME2_ADV.TABLE[4] origin:031-cmt-mmcm 29_385 +CMT_TOP_L_LOWER_B.MMCME2_ADV.TABLE[5] origin:031-cmt-mmcm 28_384 +CMT_TOP_L_LOWER_B.MMCME2_ADV.TABLE[6] origin:031-cmt-mmcm 29_395 +CMT_TOP_L_LOWER_B.MMCME2_ADV.TABLE[7] origin:031-cmt-mmcm 28_394 +CMT_TOP_L_LOWER_B.MMCME2_ADV.TABLE[8] origin:031-cmt-mmcm 29_393 +CMT_TOP_L_LOWER_B.MMCME2_ADV.TABLE[9] origin:031-cmt-mmcm 28_392 +CMT_TOP_L_LOWER_B.MMCME2_ADV.ZINV_PSEN origin:031-cmt-mmcm 28_110 +CMT_TOP_L_LOWER_B.MMCME2_ADV.ZINV_PSINCDEC origin:031-cmt-mmcm 29_110 +CMT_TOP_L_LOWER_B.MMCME2_ADV.ZINV_PWRDWN origin:031-cmt-mmcm 28_111 +CMT_TOP_L_LOWER_B.MMCME2_ADV.ZINV_RST origin:031-cmt-mmcm 29_111 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_956 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_956 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_955 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_955 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_954 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_954 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_959 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_959 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_958 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_958 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_957 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_957 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_953 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_953 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_952 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_952 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_951 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_951 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_950 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_950 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_949 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_949 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_948 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_945 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_945 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_944 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_946 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_946 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_947 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_947 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_948 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_944 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_940 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_940 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_939 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_939 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_938 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_938 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_943 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_943 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_942 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_942 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_941 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_941 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_937 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_937 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_936 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_936 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_935 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_935 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_934 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_934 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_933 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_933 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_932 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_929 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_929 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_928 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_930 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_930 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_931 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_931 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_932 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_928 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_924 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_924 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_923 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_923 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_922 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_922 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_927 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_927 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_926 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_926 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_925 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_925 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_921 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_921 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_920 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_920 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_919 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_919 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_918 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_918 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_917 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_917 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_916 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_913 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_913 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_912 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_914 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_914 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_915 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_915 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_916 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_912 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_908 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_908 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_907 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_907 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_906 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_906 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_911 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_911 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_910 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_910 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_909 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_909 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_905 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_905 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_904 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_904 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_903 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_903 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_902 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_902 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_901 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_901 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_900 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_897 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_897 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_896 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_898 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_898 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_899 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_899 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_900 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_896 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_892 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_892 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_891 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_891 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_890 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_890 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_895 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_895 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_894 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_894 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_893 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_893 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_889 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_889 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_888 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_888 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_887 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_887 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_886 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_886 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_885 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_885 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_884 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_881 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_881 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_880 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_882 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_882 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_883 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_883 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_884 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_880 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_972 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_972 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_971 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_971 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_970 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_970 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_975 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_975 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_974 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_974 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_973 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_973 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_969 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_969 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_968 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_968 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[0] origin:031-cmt-mmcm 29_967 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[1] origin:031-cmt-mmcm 28_967 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[2] origin:031-cmt-mmcm 29_966 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[3] origin:031-cmt-mmcm 28_966 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[4] origin:031-cmt-mmcm 29_965 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[5] origin:031-cmt-mmcm 28_965 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_EDGE[0] origin:031-cmt-mmcm 28_964 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_FRAC_WF_F[0] origin:031-cmt-mmcm 29_962 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_MX[0] origin:031-cmt-mmcm 29_963 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_MX[1] origin:031-cmt-mmcm 28_963 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_NO_COUNT[0] origin:031-cmt-mmcm 29_964 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[0] origin:031-cmt-mmcm 28_962 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[1] origin:031-cmt-mmcm 29_961 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[2] origin:031-cmt-mmcm 28_961 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_RESERVED[0] origin:031-cmt-mmcm 29_960 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_RESERVED[1] origin:031-cmt-mmcm 28_960 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_876 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_876 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_875 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_875 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_874 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_874 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_879 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_879 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_878 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_878 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_877 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_877 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_873 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_873 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_872 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_872 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[0] origin:031-cmt-mmcm 29_871 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[1] origin:031-cmt-mmcm 28_871 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[2] origin:031-cmt-mmcm 29_870 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[3] origin:031-cmt-mmcm 28_870 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[4] origin:031-cmt-mmcm 29_869 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[5] origin:031-cmt-mmcm 28_869 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_EDGE[0] origin:031-cmt-mmcm 28_868 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_FRAC_WF_F[0] origin:031-cmt-mmcm 29_866 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_MX[0] origin:031-cmt-mmcm 29_867 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_MX[1] origin:031-cmt-mmcm 28_867 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_NO_COUNT[0] origin:031-cmt-mmcm 29_868 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[0] origin:031-cmt-mmcm 28_866 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[1] origin:031-cmt-mmcm 29_865 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[2] origin:031-cmt-mmcm 28_865 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_RESERVED[0] origin:031-cmt-mmcm 29_864 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_RESERVED[1] origin:031-cmt-mmcm 28_864 +CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[0] origin:031-cmt-mmcm 29_399 +CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[1] origin:031-cmt-mmcm 28_399 +CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[2] origin:031-cmt-mmcm 29_398 +CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[3] origin:031-cmt-mmcm 28_398 +CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[4] origin:031-cmt-mmcm 29_397 +CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[5] origin:031-cmt-mmcm 28_397 +CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[6] origin:031-cmt-mmcm 29_396 +CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[7] origin:031-cmt-mmcm 28_396 +CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[8] origin:031-cmt-mmcm 28_395 +CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[9] origin:031-cmt-mmcm 29_394 +CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[10] origin:031-cmt-mmcm 28_393 +CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[11] origin:031-cmt-mmcm 29_392 +CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[0] origin:031-cmt-mmcm 29_391 +CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[1] origin:031-cmt-mmcm 28_391 +CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[2] origin:031-cmt-mmcm 29_390 +CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[3] origin:031-cmt-mmcm 28_390 +CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[4] origin:031-cmt-mmcm 28_389 +CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[5] origin:031-cmt-mmcm 29_388 +CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[6] origin:031-cmt-mmcm 28_387 +CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[7] origin:031-cmt-mmcm 29_386 +CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[8] origin:031-cmt-mmcm 28_385 +CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[9] origin:031-cmt-mmcm 29_384 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LOCKREG1_RESERVED[0] origin:031-cmt-mmcm 29_826 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LOCKREG1_RESERVED[1] origin:031-cmt-mmcm 28_826 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LOCKREG1_RESERVED[2] origin:031-cmt-mmcm 29_825 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LOCKREG1_RESERVED[3] origin:031-cmt-mmcm 28_825 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LOCKREG1_RESERVED[4] origin:031-cmt-mmcm 29_824 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LOCKREG1_RESERVED[5] origin:031-cmt-mmcm 28_824 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LOCKREG2_RESERVED[0] origin:031-cmt-mmcm 28_816 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LOCKREG3_RESERVED[0] origin:031-cmt-mmcm 28_808 diff --git a/artix7/segbits_cmt_top_l_upper_t.db b/artix7/segbits_cmt_top_l_upper_t.db index 07f73cc..ae5dabd 100644 --- a/artix7/segbits_cmt_top_l_upper_t.db +++ b/artix7/segbits_cmt_top_l_upper_t.db @@ -21,348 +21,348 @@ CMT_TOP_L_UPPER_T.PLL_CLK_FREQ_BB0_NS_ACTIVE 29_00 29_09 29_17 CMT_TOP_L_UPPER_T.PLL_CLK_FREQ_BB1_NS_ACTIVE 28_01 29_10 29_18 CMT_TOP_L_UPPER_T.PLL_CLK_FREQ_BB2_NS_ACTIVE 29_01 29_11 29_19 CMT_TOP_L_UPPER_T.PLL_CLK_FREQ_BB3_NS_ACTIVE 28_02 29_12 29_20 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[0] 28_195 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[1] 29_195 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[2] 28_196 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[3] 29_196 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[4] 28_197 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[5] 29_197 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[0] 28_192 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[1] 29_192 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[2] 28_193 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[3] 29_193 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[4] 28_194 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[5] 29_194 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE[0] 28_198 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[0] 29_198 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[1] 28_199 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[2] 29_199 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[0] 28_200 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[1] 29_200 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[2] 28_201 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[3] 29_201 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[4] 28_202 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[5] 29_202 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_EDGE[0] 29_203 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[0] 28_206 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[1] 29_206 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[2] 28_207 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC_EN[0] 29_205 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC_WF_R[0] 28_205 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_MX[0] 28_204 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_MX[1] 29_204 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_NO_COUNT[0] 28_203 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_RESERVED[0] 29_207 -CMT_TOP_L_UPPER_T.PLLE2.COMP.ZHOLD_NO_CLKIN_BUF_TOP 28_38 -CMT_TOP_L_UPPER_T.PLLE2.COMPENSATION.Z_ZHOLD_OR_CLKIN_BUF 29_35 29_76 -CMT_TOP_L_UPPER_T.PLLE2.COMPENSATION.ZHOLD_NO_CLKIN_BUF 28_73 29_36 -CMT_TOP_L_UPPER_T.PLLE2.COMPENSATION.ZHOLD_NO_CLKIN_BUF_NO_TOP 29_38 -CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_EDGE[0] 29_214 -CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[0] 28_211 -CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[1] 29_211 -CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[2] 28_212 -CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[3] 29_212 -CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[4] 28_213 -CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[5] 29_213 -CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[0] 28_208 -CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[1] 29_208 -CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[2] 28_209 -CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[3] 29_209 -CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[4] 28_210 -CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[5] 29_210 -CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_NO_COUNT[0] 28_214 -CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_RESERVED[0] 28_215 -CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_RESERVED[1] 29_215 -CMT_TOP_L_UPPER_T.PLLE2.IN_USE 28_37 28_48 28_74 28_78 28_216 28_219 28_222 28_266 28_280 28_283 28_284 28_592 28_622 28_623 28_624 28_627 28_628 28_768 28_785 28_786 28_787 28_788 28_790 28_791 28_792 28_793 28_795 28_796 28_797 28_798 28_799 28_803 28_806 28_807 28_811 28_812 28_815 28_816 28_817 28_818 28_819 28_821 28_822 28_823 28_824 28_826 28_827 28_828 28_829 28_832 28_835 28_838 28_841 28_845 28_847 29_48 29_77 29_78 29_79 29_268 29_281 29_282 29_283 29_563 29_567 29_589 29_621 29_622 29_625 29_626 29_627 29_785 29_786 29_788 29_790 29_791 29_793 29_797 29_798 29_800 29_809 29_811 29_812 29_813 29_814 29_815 29_816 29_817 29_819 29_823 29_824 29_825 29_826 29_827 29_829 29_830 29_831 29_832 29_835 29_836 29_838 29_839 29_840 29_841 29_842 29_845 -CMT_TOP_L_UPPER_T.PLLE2.INV_CLKINSEL 28_754 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[0] 28_232 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[1] 29_232 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[2] 28_233 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[3] 29_233 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[4] 28_234 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[5] 29_234 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[6] 28_235 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[7] 29_235 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[8] 28_236 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[9] 29_236 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[10] 28_240 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[11] 29_240 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[12] 28_241 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[13] 29_241 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[14] 28_242 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[15] 29_242 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[16] 28_243 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[17] 29_243 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[18] 28_244 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[19] 29_244 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[20] 28_224 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[21] 29_224 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[22] 28_225 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[23] 29_225 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[24] 28_226 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[25] 29_226 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[26] 28_227 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[27] 29_227 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[28] 28_228 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[29] 29_228 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[30] 28_237 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[31] 29_237 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[32] 28_238 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[33] 29_238 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[34] 28_239 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[35] 28_245 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[36] 29_245 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[37] 28_246 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[38] 29_246 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[39] 28_247 -CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[0] 28_352 -CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[1] 29_352 -CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[2] 28_353 -CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[3] 29_353 -CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[4] 28_354 -CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[5] 29_354 -CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[6] 28_355 -CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[7] 29_355 -CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[8] 28_356 -CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[9] 29_356 -CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[10] 28_357 -CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[11] 29_357 -CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[12] 28_358 -CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[13] 29_358 -CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[14] 28_359 -CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[15] 29_359 -CMT_TOP_L_UPPER_T.PLLE2.STARTUP_WAIT 28_769 -CMT_TOP_L_UPPER_T.PLLE2.TABLE[0] 28_666 -CMT_TOP_L_UPPER_T.PLLE2.TABLE[1] 29_667 -CMT_TOP_L_UPPER_T.PLLE2.TABLE[2] 28_668 -CMT_TOP_L_UPPER_T.PLLE2.TABLE[3] 29_669 -CMT_TOP_L_UPPER_T.PLLE2.TABLE[4] 28_670 -CMT_TOP_L_UPPER_T.PLLE2.TABLE[5] 29_671 -CMT_TOP_L_UPPER_T.PLLE2.TABLE[6] 28_660 -CMT_TOP_L_UPPER_T.PLLE2.TABLE[7] 29_661 -CMT_TOP_L_UPPER_T.PLLE2.TABLE[8] 28_662 -CMT_TOP_L_UPPER_T.PLLE2.TABLE[9] 29_663 -CMT_TOP_L_UPPER_T.PLLE2.ZINV_PWRDWN 29_752 -CMT_TOP_L_UPPER_T.PLLE2.ZINV_RST 28_752 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[0] 28_99 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[1] 29_99 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[2] 28_100 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[3] 29_100 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[4] 28_101 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[5] 29_101 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[0] 28_96 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[1] 29_96 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[2] 28_97 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[3] 29_97 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[4] 28_98 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[5] 29_98 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_OUTPUT_ENABLE[0] 28_102 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[0] 29_102 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[1] 28_103 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[2] 29_103 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[0] 28_104 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[1] 29_104 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[2] 28_105 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[3] 29_105 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[4] 28_106 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[5] 29_106 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_EDGE[0] 29_107 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[0] 28_110 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[1] 29_110 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[2] 28_111 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC_EN[0] 29_109 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC_WF_R[0] 28_109 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_MX[0] 28_108 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_MX[1] 29_108 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_NO_COUNT[0] 28_107 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_RESERVED[0] 29_111 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[0] 28_115 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[1] 29_115 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[2] 28_116 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[3] 29_116 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[4] 28_117 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[5] 29_117 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[0] 28_112 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[1] 29_112 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[2] 28_113 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[3] 29_113 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[4] 28_114 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[5] 29_114 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_OUTPUT_ENABLE[0] 28_118 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[0] 29_118 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[1] 28_119 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[2] 29_119 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[0] 28_120 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[1] 29_120 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[2] 28_121 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[3] 29_121 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[4] 28_122 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[5] 29_122 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_EDGE[0] 29_123 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[0] 28_126 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[1] 29_126 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[2] 28_127 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC_EN[0] 29_125 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC_WF_R[0] 28_125 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_MX[0] 28_124 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_MX[1] 29_124 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_NO_COUNT[0] 28_123 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_RESERVED[0] 29_127 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[0] 28_131 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[1] 29_131 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[2] 28_132 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[3] 29_132 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[4] 28_133 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[5] 29_133 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[0] 28_128 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[1] 29_128 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[2] 28_129 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[3] 29_129 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[4] 28_130 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[5] 29_130 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_OUTPUT_ENABLE[0] 28_134 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[0] 29_134 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[1] 28_135 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[2] 29_135 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[0] 28_136 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[1] 29_136 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[2] 28_137 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[3] 29_137 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[4] 28_138 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[5] 29_138 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_EDGE[0] 29_139 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[0] 28_142 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[1] 29_142 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[2] 28_143 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC_EN[0] 29_141 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC_WF_R[0] 28_141 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_MX[0] 28_140 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_MX[1] 29_140 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_NO_COUNT[0] 28_139 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_RESERVED[0] 29_143 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[0] 28_147 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[1] 29_147 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[2] 28_148 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[3] 29_148 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[4] 28_149 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[5] 29_149 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[0] 28_144 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[1] 29_144 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[2] 28_145 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[3] 29_145 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[4] 28_146 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[5] 29_146 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_OUTPUT_ENABLE[0] 28_150 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[0] 29_150 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[1] 28_151 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[2] 29_151 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[0] 28_152 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[1] 29_152 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[2] 28_153 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[3] 29_153 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[4] 28_154 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[5] 29_154 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_EDGE[0] 29_155 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[0] 28_158 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[1] 29_158 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[2] 28_159 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC_EN[0] 29_157 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC_WF_R[0] 28_157 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_MX[0] 28_156 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_MX[1] 29_156 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_NO_COUNT[0] 28_155 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_RESERVED[0] 29_159 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[0] 28_163 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[1] 29_163 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[2] 28_164 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[3] 29_164 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[4] 28_165 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[5] 29_165 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[0] 28_160 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[1] 29_160 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[2] 28_161 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[3] 29_161 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[4] 28_162 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[5] 29_162 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_OUTPUT_ENABLE[0] 28_166 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[0] 29_166 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[1] 28_167 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[2] 29_167 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[0] 28_168 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[1] 29_168 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[2] 28_169 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[3] 29_169 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[4] 28_170 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[5] 29_170 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_EDGE[0] 29_171 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[0] 28_174 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[1] 29_174 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[2] 28_175 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC_EN[0] 29_173 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC_WF_R[0] 28_173 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_MX[0] 28_172 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_MX[1] 29_172 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_NO_COUNT[0] 28_171 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_RESERVED[0] 29_175 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[0] 28_83 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[1] 29_83 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[2] 28_84 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[3] 29_84 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[4] 28_85 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[5] 29_85 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[0] 28_80 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[1] 29_80 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[2] 28_81 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[3] 29_81 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[4] 28_82 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[5] 29_82 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_OUTPUT_ENABLE[0] 28_86 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[0] 29_86 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[1] 28_87 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[2] 29_87 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[0] 28_88 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[1] 29_88 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[2] 28_89 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[3] 29_89 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[4] 28_90 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[5] 29_90 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_EDGE[0] 29_91 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[0] 28_94 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[1] 29_94 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[2] 28_95 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC_EN[0] 29_93 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC_WF_R[0] 28_93 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_MX[0] 28_92 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_MX[1] 29_92 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_NO_COUNT[0] 28_91 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_RESERVED[0] 29_95 -CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[0] 28_656 -CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[1] 29_656 -CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[2] 28_657 -CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[3] 29_657 -CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[4] 28_658 -CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[5] 29_658 -CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[6] 28_659 -CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[7] 29_659 -CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[8] 29_660 -CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[9] 28_661 -CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[10] 29_662 -CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[11] 28_663 -CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[0] 28_664 -CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[1] 29_664 -CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[2] 28_665 -CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[3] 29_665 -CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[4] 29_666 -CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[5] 28_667 -CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[6] 29_668 -CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[7] 28_669 -CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[8] 29_670 -CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[9] 28_671 -CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[0] 28_229 -CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[1] 29_229 -CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[2] 28_230 -CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[3] 29_230 -CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[4] 28_231 -CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[5] 29_231 -CMT_TOP_L_UPPER_T.PLLE2.LOCKREG2_RESERVED[0] 29_239 -CMT_TOP_L_UPPER_T.PLLE2.LOCKREG3_RESERVED[0] 29_247 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[0] 28_195 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[1] 29_195 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[2] 28_196 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[3] 29_196 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[4] 28_197 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[5] 29_197 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[0] 28_192 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[1] 29_192 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[2] 28_193 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[3] 29_193 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[4] 28_194 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[5] 29_194 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE[0] 28_198 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_PHASE_MUX[0] 29_198 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_PHASE_MUX[1] 28_199 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_PHASE_MUX[2] 29_199 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[0] 28_200 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[1] 29_200 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[2] 28_201 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[3] 29_201 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[4] 28_202 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[5] 29_202 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_EDGE[0] 29_203 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_FRAC[0] 28_206 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_FRAC[1] 29_206 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_FRAC[2] 28_207 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_FRAC_EN[0] 29_205 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_FRAC_WF_R[0] 28_205 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_MX[0] 28_204 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_MX[1] 29_204 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_NO_COUNT[0] 28_203 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_RESERVED[0] 29_207 +CMT_TOP_L_UPPER_T.PLLE2_ADV.COMP.ZHOLD_NO_CLKIN_BUF_TOP 28_38 +CMT_TOP_L_UPPER_T.PLLE2_ADV.COMPENSATION.Z_ZHOLD_OR_CLKIN_BUF 29_35 29_76 +CMT_TOP_L_UPPER_T.PLLE2_ADV.COMPENSATION.ZHOLD_NO_CLKIN_BUF 28_73 29_36 +CMT_TOP_L_UPPER_T.PLLE2_ADV.COMPENSATION.ZHOLD_NO_CLKIN_BUF_NO_TOP 29_38 +CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_EDGE[0] 29_214 +CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_HIGH_TIME[0] 28_211 +CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_HIGH_TIME[1] 29_211 +CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_HIGH_TIME[2] 28_212 +CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_HIGH_TIME[3] 29_212 +CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_HIGH_TIME[4] 28_213 +CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_HIGH_TIME[5] 29_213 +CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_LOW_TIME[0] 28_208 +CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_LOW_TIME[1] 29_208 +CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_LOW_TIME[2] 28_209 +CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_LOW_TIME[3] 29_209 +CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_LOW_TIME[4] 28_210 +CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_LOW_TIME[5] 29_210 +CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_NO_COUNT[0] 28_214 +CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_RESERVED[0] 28_215 +CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_RESERVED[1] 29_215 +CMT_TOP_L_UPPER_T.PLLE2_ADV.IN_USE 28_37 28_48 28_74 28_78 28_216 28_219 28_222 28_266 28_280 28_283 28_284 28_592 28_622 28_623 28_624 28_627 28_628 28_768 28_785 28_786 28_787 28_788 28_790 28_791 28_792 28_793 28_795 28_796 28_797 28_798 28_799 28_803 28_806 28_807 28_811 28_812 28_815 28_816 28_817 28_818 28_819 28_821 28_822 28_823 28_824 28_826 28_827 28_828 28_829 28_832 28_835 28_838 28_841 28_845 28_847 29_48 29_77 29_78 29_79 29_268 29_281 29_282 29_283 29_563 29_567 29_589 29_621 29_622 29_625 29_626 29_627 29_785 29_786 29_788 29_790 29_791 29_793 29_797 29_798 29_800 29_809 29_811 29_812 29_813 29_814 29_815 29_816 29_817 29_819 29_823 29_824 29_825 29_826 29_827 29_829 29_830 29_831 29_832 29_835 29_836 29_838 29_839 29_840 29_841 29_842 29_845 +CMT_TOP_L_UPPER_T.PLLE2_ADV.INV_CLKINSEL 28_754 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[0] 28_232 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[1] 29_232 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[2] 28_233 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[3] 29_233 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[4] 28_234 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[5] 29_234 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[6] 28_235 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[7] 29_235 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[8] 28_236 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[9] 29_236 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[10] 28_240 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[11] 29_240 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[12] 28_241 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[13] 29_241 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[14] 28_242 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[15] 29_242 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[16] 28_243 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[17] 29_243 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[18] 28_244 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[19] 29_244 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[20] 28_224 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[21] 29_224 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[22] 28_225 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[23] 29_225 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[24] 28_226 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[25] 29_226 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[26] 28_227 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[27] 29_227 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[28] 28_228 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[29] 29_228 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[30] 28_237 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[31] 29_237 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[32] 28_238 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[33] 29_238 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[34] 28_239 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[35] 28_245 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[36] 29_245 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[37] 28_246 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[38] 29_246 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[39] 28_247 +CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[0] 28_352 +CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[1] 29_352 +CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[2] 28_353 +CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[3] 29_353 +CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[4] 28_354 +CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[5] 29_354 +CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[6] 28_355 +CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[7] 29_355 +CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[8] 28_356 +CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[9] 29_356 +CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[10] 28_357 +CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[11] 29_357 +CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[12] 28_358 +CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[13] 29_358 +CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[14] 28_359 +CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[15] 29_359 +CMT_TOP_L_UPPER_T.PLLE2_ADV.STARTUP_WAIT 28_769 +CMT_TOP_L_UPPER_T.PLLE2_ADV.TABLE[0] 28_666 +CMT_TOP_L_UPPER_T.PLLE2_ADV.TABLE[1] 29_667 +CMT_TOP_L_UPPER_T.PLLE2_ADV.TABLE[2] 28_668 +CMT_TOP_L_UPPER_T.PLLE2_ADV.TABLE[3] 29_669 +CMT_TOP_L_UPPER_T.PLLE2_ADV.TABLE[4] 28_670 +CMT_TOP_L_UPPER_T.PLLE2_ADV.TABLE[5] 29_671 +CMT_TOP_L_UPPER_T.PLLE2_ADV.TABLE[6] 28_660 +CMT_TOP_L_UPPER_T.PLLE2_ADV.TABLE[7] 29_661 +CMT_TOP_L_UPPER_T.PLLE2_ADV.TABLE[8] 28_662 +CMT_TOP_L_UPPER_T.PLLE2_ADV.TABLE[9] 29_663 +CMT_TOP_L_UPPER_T.PLLE2_ADV.ZINV_PWRDWN 29_752 +CMT_TOP_L_UPPER_T.PLLE2_ADV.ZINV_RST 28_752 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[0] 28_99 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[1] 29_99 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[2] 28_100 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[3] 29_100 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[4] 28_101 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[5] 29_101 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[0] 28_96 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[1] 29_96 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[2] 28_97 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[3] 29_97 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[4] 28_98 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[5] 29_98 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_OUTPUT_ENABLE[0] 28_102 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_PHASE_MUX[0] 29_102 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_PHASE_MUX[1] 28_103 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_PHASE_MUX[2] 29_103 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[0] 28_104 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[1] 29_104 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[2] 28_105 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[3] 29_105 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[4] 28_106 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[5] 29_106 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_EDGE[0] 29_107 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_FRAC[0] 28_110 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_FRAC[1] 29_110 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_FRAC[2] 28_111 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_FRAC_EN[0] 29_109 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_FRAC_WF_R[0] 28_109 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_MX[0] 28_108 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_MX[1] 29_108 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_NO_COUNT[0] 28_107 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_RESERVED[0] 29_111 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[0] 28_115 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[1] 29_115 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[2] 28_116 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[3] 29_116 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[4] 28_117 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[5] 29_117 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[0] 28_112 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[1] 29_112 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[2] 28_113 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[3] 29_113 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[4] 28_114 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[5] 29_114 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_OUTPUT_ENABLE[0] 28_118 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_PHASE_MUX[0] 29_118 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_PHASE_MUX[1] 28_119 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_PHASE_MUX[2] 29_119 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[0] 28_120 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[1] 29_120 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[2] 28_121 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[3] 29_121 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[4] 28_122 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[5] 29_122 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_EDGE[0] 29_123 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_FRAC[0] 28_126 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_FRAC[1] 29_126 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_FRAC[2] 28_127 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_FRAC_EN[0] 29_125 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_FRAC_WF_R[0] 28_125 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_MX[0] 28_124 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_MX[1] 29_124 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_NO_COUNT[0] 28_123 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_RESERVED[0] 29_127 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[0] 28_131 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[1] 29_131 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[2] 28_132 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[3] 29_132 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[4] 28_133 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[5] 29_133 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[0] 28_128 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[1] 29_128 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[2] 28_129 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[3] 29_129 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[4] 28_130 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[5] 29_130 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_OUTPUT_ENABLE[0] 28_134 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_PHASE_MUX[0] 29_134 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_PHASE_MUX[1] 28_135 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_PHASE_MUX[2] 29_135 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[0] 28_136 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[1] 29_136 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[2] 28_137 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[3] 29_137 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[4] 28_138 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[5] 29_138 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_EDGE[0] 29_139 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_FRAC[0] 28_142 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_FRAC[1] 29_142 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_FRAC[2] 28_143 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_FRAC_EN[0] 29_141 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_FRAC_WF_R[0] 28_141 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_MX[0] 28_140 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_MX[1] 29_140 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_NO_COUNT[0] 28_139 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_RESERVED[0] 29_143 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[0] 28_147 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[1] 29_147 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[2] 28_148 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[3] 29_148 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[4] 28_149 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[5] 29_149 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[0] 28_144 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[1] 29_144 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[2] 28_145 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[3] 29_145 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[4] 28_146 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[5] 29_146 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_OUTPUT_ENABLE[0] 28_150 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_PHASE_MUX[0] 29_150 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_PHASE_MUX[1] 28_151 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_PHASE_MUX[2] 29_151 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[0] 28_152 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[1] 29_152 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[2] 28_153 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[3] 29_153 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[4] 28_154 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[5] 29_154 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_EDGE[0] 29_155 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_FRAC[0] 28_158 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_FRAC[1] 29_158 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_FRAC[2] 28_159 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_FRAC_EN[0] 29_157 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_FRAC_WF_R[0] 28_157 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_MX[0] 28_156 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_MX[1] 29_156 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_NO_COUNT[0] 28_155 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_RESERVED[0] 29_159 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[0] 28_163 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[1] 29_163 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[2] 28_164 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[3] 29_164 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[4] 28_165 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[5] 29_165 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[0] 28_160 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[1] 29_160 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[2] 28_161 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[3] 29_161 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[4] 28_162 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[5] 29_162 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_OUTPUT_ENABLE[0] 28_166 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_PHASE_MUX[0] 29_166 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_PHASE_MUX[1] 28_167 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_PHASE_MUX[2] 29_167 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[0] 28_168 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[1] 29_168 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[2] 28_169 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[3] 29_169 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[4] 28_170 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[5] 29_170 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_EDGE[0] 29_171 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_FRAC[0] 28_174 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_FRAC[1] 29_174 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_FRAC[2] 28_175 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_FRAC_EN[0] 29_173 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_FRAC_WF_R[0] 28_173 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_MX[0] 28_172 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_MX[1] 29_172 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_NO_COUNT[0] 28_171 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_RESERVED[0] 29_175 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[0] 28_83 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[1] 29_83 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[2] 28_84 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[3] 29_84 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[4] 28_85 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[5] 29_85 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[0] 28_80 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[1] 29_80 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[2] 28_81 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[3] 29_81 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[4] 28_82 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[5] 29_82 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_OUTPUT_ENABLE[0] 28_86 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_PHASE_MUX[0] 29_86 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_PHASE_MUX[1] 28_87 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_PHASE_MUX[2] 29_87 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_DELAY_TIME[0] 28_88 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_DELAY_TIME[1] 29_88 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_DELAY_TIME[2] 28_89 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_DELAY_TIME[3] 29_89 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_DELAY_TIME[4] 28_90 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_DELAY_TIME[5] 29_90 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_EDGE[0] 29_91 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_FRAC[0] 28_94 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_FRAC[1] 29_94 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_FRAC[2] 28_95 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_FRAC_EN[0] 29_93 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_FRAC_WF_R[0] 28_93 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_MX[0] 28_92 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_MX[1] 29_92 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_NO_COUNT[0] 28_91 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_RESERVED[0] 29_95 +CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[0] 28_656 +CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[1] 29_656 +CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[2] 28_657 +CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[3] 29_657 +CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[4] 28_658 +CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[5] 29_658 +CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[6] 28_659 +CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[7] 29_659 +CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[8] 29_660 +CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[9] 28_661 +CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[10] 29_662 +CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[11] 28_663 +CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[0] 28_664 +CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[1] 29_664 +CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[2] 28_665 +CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[3] 29_665 +CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[4] 29_666 +CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[5] 28_667 +CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[6] 29_668 +CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[7] 28_669 +CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[8] 29_670 +CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[9] 28_671 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LOCKREG1_RESERVED[0] 28_229 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LOCKREG1_RESERVED[1] 29_229 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LOCKREG1_RESERVED[2] 28_230 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LOCKREG1_RESERVED[3] 29_230 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LOCKREG1_RESERVED[4] 28_231 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LOCKREG1_RESERVED[5] 29_231 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LOCKREG2_RESERVED[0] 29_239 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LOCKREG3_RESERVED[0] 29_247 diff --git a/artix7/segbits_cmt_top_l_upper_t.origin_info.db b/artix7/segbits_cmt_top_l_upper_t.origin_info.db index fbdd8d9..1602151 100644 --- a/artix7/segbits_cmt_top_l_upper_t.origin_info.db +++ b/artix7/segbits_cmt_top_l_upper_t.origin_info.db @@ -21,348 +21,348 @@ CMT_TOP_L_UPPER_T.PLL_CLK_FREQ_BB0_NS_ACTIVE origin:034-cmt-pll-pips 29_00 29_09 CMT_TOP_L_UPPER_T.PLL_CLK_FREQ_BB1_NS_ACTIVE origin:034-cmt-pll-pips 28_01 29_10 29_18 CMT_TOP_L_UPPER_T.PLL_CLK_FREQ_BB2_NS_ACTIVE origin:034-cmt-pll-pips 29_01 29_11 29_19 CMT_TOP_L_UPPER_T.PLL_CLK_FREQ_BB3_NS_ACTIVE origin:034-cmt-pll-pips 28_02 29_12 29_20 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_195 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_195 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_196 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_196 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_197 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_197 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_192 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_192 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_193 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_193 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_194 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_194 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_198 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_198 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_199 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_199 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_200 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_200 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_201 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_201 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_202 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_202 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_203 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_206 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_206 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_207 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_205 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_205 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_MX[0] origin:032-cmt-pll 28_204 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_MX[1] origin:032-cmt-pll 29_204 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_203 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_207 -CMT_TOP_L_UPPER_T.PLLE2.COMP.ZHOLD_NO_CLKIN_BUF_TOP origin:032-cmt-pll 28_38 -CMT_TOP_L_UPPER_T.PLLE2.COMPENSATION.Z_ZHOLD_OR_CLKIN_BUF origin:032-cmt-pll 29_35 29_76 -CMT_TOP_L_UPPER_T.PLLE2.COMPENSATION.ZHOLD_NO_CLKIN_BUF origin:032-cmt-pll 28_73 29_36 -CMT_TOP_L_UPPER_T.PLLE2.COMPENSATION.ZHOLD_NO_CLKIN_BUF_NO_TOP origin:032-cmt-pll 29_38 -CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_EDGE[0] origin:032-cmt-pll 29_214 -CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[0] origin:032-cmt-pll 28_211 -CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[1] origin:032-cmt-pll 29_211 -CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[2] origin:032-cmt-pll 28_212 -CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[3] origin:032-cmt-pll 29_212 -CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[4] origin:032-cmt-pll 28_213 -CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[5] origin:032-cmt-pll 29_213 -CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[0] origin:032-cmt-pll 28_208 -CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[1] origin:032-cmt-pll 29_208 -CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[2] origin:032-cmt-pll 28_209 -CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[3] origin:032-cmt-pll 29_209 -CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[4] origin:032-cmt-pll 28_210 -CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[5] origin:032-cmt-pll 29_210 -CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_NO_COUNT[0] origin:032-cmt-pll 28_214 -CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_RESERVED[0] origin:032-cmt-pll 28_215 -CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_RESERVED[1] origin:032-cmt-pll 29_215 -CMT_TOP_L_UPPER_T.PLLE2.IN_USE origin:032-cmt-pll 28_216 28_219 28_222 28_266 28_280 28_283 28_284 28_37 28_48 28_592 28_622 28_623 28_624 28_627 28_628 28_74 28_768 28_78 28_785 28_786 28_787 28_788 28_790 28_791 28_792 28_793 28_795 28_796 28_797 28_798 28_799 28_803 28_806 28_807 28_811 28_812 28_815 28_816 28_817 28_818 28_819 28_821 28_822 28_823 28_824 28_826 28_827 28_828 28_829 28_832 28_835 28_838 28_841 28_845 28_847 29_268 29_281 29_282 29_283 29_48 29_563 29_567 29_589 29_621 29_622 29_625 29_626 29_627 29_77 29_78 29_785 29_786 29_788 29_79 29_790 29_791 29_793 29_797 29_798 29_800 29_809 29_811 29_812 29_813 29_814 29_815 29_816 29_817 29_819 29_823 29_824 29_825 29_826 29_827 29_829 29_830 29_831 29_832 29_835 29_836 29_838 29_839 29_840 29_841 29_842 29_845 -CMT_TOP_L_UPPER_T.PLLE2.INV_CLKINSEL origin:032-cmt-pll 28_754 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[0] origin:032-cmt-pll 28_232 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[1] origin:032-cmt-pll 29_232 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[2] origin:032-cmt-pll 28_233 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[3] origin:032-cmt-pll 29_233 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[4] origin:032-cmt-pll 28_234 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[5] origin:032-cmt-pll 29_234 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[6] origin:032-cmt-pll 28_235 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[7] origin:032-cmt-pll 29_235 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[8] origin:032-cmt-pll 28_236 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[9] origin:032-cmt-pll 29_236 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[10] origin:032-cmt-pll 28_240 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[11] origin:032-cmt-pll 29_240 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[12] origin:032-cmt-pll 28_241 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[13] origin:032-cmt-pll 29_241 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[14] origin:032-cmt-pll 28_242 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[15] origin:032-cmt-pll 29_242 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[16] origin:032-cmt-pll 28_243 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[17] origin:032-cmt-pll 29_243 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[18] origin:032-cmt-pll 28_244 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[19] origin:032-cmt-pll 29_244 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[20] origin:032-cmt-pll 28_224 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[21] origin:032-cmt-pll 29_224 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[22] origin:032-cmt-pll 28_225 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[23] origin:032-cmt-pll 29_225 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[24] origin:032-cmt-pll 28_226 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[25] origin:032-cmt-pll 29_226 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[26] origin:032-cmt-pll 28_227 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[27] origin:032-cmt-pll 29_227 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[28] origin:032-cmt-pll 28_228 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[29] origin:032-cmt-pll 29_228 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[30] origin:032-cmt-pll 28_237 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[31] origin:032-cmt-pll 29_237 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[32] origin:032-cmt-pll 28_238 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[33] origin:032-cmt-pll 29_238 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[34] origin:032-cmt-pll 28_239 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[35] origin:032-cmt-pll 28_245 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[36] origin:032-cmt-pll 29_245 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[37] origin:032-cmt-pll 28_246 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[38] origin:032-cmt-pll 29_246 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[39] origin:032-cmt-pll 28_247 -CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[0] origin:032-cmt-pll 28_352 -CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[1] origin:032-cmt-pll 29_352 -CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[2] origin:032-cmt-pll 28_353 -CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[3] origin:032-cmt-pll 29_353 -CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[4] origin:032-cmt-pll 28_354 -CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[5] origin:032-cmt-pll 29_354 -CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[6] origin:032-cmt-pll 28_355 -CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[7] origin:032-cmt-pll 29_355 -CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[8] origin:032-cmt-pll 28_356 -CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[9] origin:032-cmt-pll 29_356 -CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[10] origin:032-cmt-pll 28_357 -CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[11] origin:032-cmt-pll 29_357 -CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[12] origin:032-cmt-pll 28_358 -CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[13] origin:032-cmt-pll 29_358 -CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[14] origin:032-cmt-pll 28_359 -CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[15] origin:032-cmt-pll 29_359 -CMT_TOP_L_UPPER_T.PLLE2.STARTUP_WAIT origin:032-cmt-pll 28_769 -CMT_TOP_L_UPPER_T.PLLE2.TABLE[0] origin:032-cmt-pll 28_666 -CMT_TOP_L_UPPER_T.PLLE2.TABLE[1] origin:032-cmt-pll 29_667 -CMT_TOP_L_UPPER_T.PLLE2.TABLE[2] origin:032-cmt-pll 28_668 -CMT_TOP_L_UPPER_T.PLLE2.TABLE[3] origin:032-cmt-pll 29_669 -CMT_TOP_L_UPPER_T.PLLE2.TABLE[4] origin:032-cmt-pll 28_670 -CMT_TOP_L_UPPER_T.PLLE2.TABLE[5] origin:032-cmt-pll 29_671 -CMT_TOP_L_UPPER_T.PLLE2.TABLE[6] origin:032-cmt-pll 28_660 -CMT_TOP_L_UPPER_T.PLLE2.TABLE[7] origin:032-cmt-pll 29_661 -CMT_TOP_L_UPPER_T.PLLE2.TABLE[8] origin:032-cmt-pll 28_662 -CMT_TOP_L_UPPER_T.PLLE2.TABLE[9] origin:032-cmt-pll 29_663 -CMT_TOP_L_UPPER_T.PLLE2.ZINV_PWRDWN origin:032-cmt-pll 29_752 -CMT_TOP_L_UPPER_T.PLLE2.ZINV_RST origin:032-cmt-pll 28_752 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_99 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_99 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_100 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_100 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_101 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_101 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_96 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_96 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_97 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_97 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_98 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_98 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_102 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_102 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_103 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_103 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_104 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_104 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_105 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_105 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_106 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_106 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_107 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_110 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_110 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_111 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_109 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_109 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_MX[0] origin:032-cmt-pll 28_108 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_MX[1] origin:032-cmt-pll 29_108 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_107 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_111 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_115 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_115 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_116 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_116 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_117 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_117 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_112 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_112 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_113 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_113 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_114 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_114 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_118 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_118 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_119 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_119 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_120 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_120 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_121 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_121 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_122 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_122 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_123 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_126 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_126 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_127 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_125 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_125 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_MX[0] origin:032-cmt-pll 28_124 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_MX[1] origin:032-cmt-pll 29_124 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_123 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_127 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_131 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_131 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_132 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_132 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_133 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_133 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_128 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_128 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_129 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_129 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_130 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_130 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_134 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_134 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_135 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_135 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_136 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_136 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_137 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_137 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_138 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_138 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_139 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_142 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_142 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_143 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_141 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_141 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_MX[0] origin:032-cmt-pll 28_140 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_MX[1] origin:032-cmt-pll 29_140 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_139 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_143 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_147 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_147 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_148 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_148 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_149 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_149 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_144 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_144 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_145 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_145 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_146 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_146 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_150 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_150 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_151 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_151 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_152 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_152 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_153 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_153 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_154 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_154 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_155 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_158 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_158 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_159 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_157 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_157 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_MX[0] origin:032-cmt-pll 28_156 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_MX[1] origin:032-cmt-pll 29_156 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_155 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_159 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_163 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_163 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_164 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_164 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_165 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_165 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_160 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_160 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_161 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_161 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_162 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_162 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_166 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_166 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_167 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_167 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_168 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_168 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_169 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_169 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_170 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_170 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_171 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_174 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_174 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_175 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_173 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_173 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_MX[0] origin:032-cmt-pll 28_172 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_MX[1] origin:032-cmt-pll 29_172 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_171 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_175 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_83 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_83 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_84 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_84 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_85 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_85 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_80 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_80 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_81 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_81 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_82 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_82 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_86 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_86 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_87 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_87 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_88 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_88 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_89 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_89 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_90 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_90 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_91 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_94 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_94 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_95 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_93 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_93 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_MX[0] origin:032-cmt-pll 28_92 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_MX[1] origin:032-cmt-pll 29_92 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_91 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_95 -CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[0] origin:032-cmt-pll 28_656 -CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[1] origin:032-cmt-pll 29_656 -CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[2] origin:032-cmt-pll 28_657 -CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[3] origin:032-cmt-pll 29_657 -CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[4] origin:032-cmt-pll 28_658 -CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[5] origin:032-cmt-pll 29_658 -CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[6] origin:032-cmt-pll 28_659 -CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[7] origin:032-cmt-pll 29_659 -CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[8] origin:032-cmt-pll 29_660 -CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[9] origin:032-cmt-pll 28_661 -CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[10] origin:032-cmt-pll 29_662 -CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[11] origin:032-cmt-pll 28_663 -CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[0] origin:032-cmt-pll 28_664 -CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[1] origin:032-cmt-pll 29_664 -CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[2] origin:032-cmt-pll 28_665 -CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[3] origin:032-cmt-pll 29_665 -CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[4] origin:032-cmt-pll 29_666 -CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[5] origin:032-cmt-pll 28_667 -CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[6] origin:032-cmt-pll 29_668 -CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[7] origin:032-cmt-pll 28_669 -CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[8] origin:032-cmt-pll 29_670 -CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[9] origin:032-cmt-pll 28_671 -CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[0] origin:032-cmt-pll 28_229 -CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[1] origin:032-cmt-pll 29_229 -CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[2] origin:032-cmt-pll 28_230 -CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[3] origin:032-cmt-pll 29_230 -CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[4] origin:032-cmt-pll 28_231 -CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[5] origin:032-cmt-pll 29_231 -CMT_TOP_L_UPPER_T.PLLE2.LOCKREG2_RESERVED[0] origin:032-cmt-pll 29_239 -CMT_TOP_L_UPPER_T.PLLE2.LOCKREG3_RESERVED[0] origin:032-cmt-pll 29_247 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_195 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_195 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_196 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_196 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_197 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_197 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_192 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_192 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_193 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_193 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_194 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_194 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_198 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_198 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_199 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_199 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_200 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_200 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_201 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_201 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_202 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_202 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_203 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_206 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_206 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_207 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_205 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_205 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_MX[0] origin:032-cmt-pll 28_204 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_MX[1] origin:032-cmt-pll 29_204 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_203 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_207 +CMT_TOP_L_UPPER_T.PLLE2_ADV.COMP.ZHOLD_NO_CLKIN_BUF_TOP origin:032-cmt-pll 28_38 +CMT_TOP_L_UPPER_T.PLLE2_ADV.COMPENSATION.Z_ZHOLD_OR_CLKIN_BUF origin:032-cmt-pll 29_35 29_76 +CMT_TOP_L_UPPER_T.PLLE2_ADV.COMPENSATION.ZHOLD_NO_CLKIN_BUF origin:032-cmt-pll 28_73 29_36 +CMT_TOP_L_UPPER_T.PLLE2_ADV.COMPENSATION.ZHOLD_NO_CLKIN_BUF_NO_TOP origin:032-cmt-pll 29_38 +CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_EDGE[0] origin:032-cmt-pll 29_214 +CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_HIGH_TIME[0] origin:032-cmt-pll 28_211 +CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_HIGH_TIME[1] origin:032-cmt-pll 29_211 +CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_HIGH_TIME[2] origin:032-cmt-pll 28_212 +CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_HIGH_TIME[3] origin:032-cmt-pll 29_212 +CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_HIGH_TIME[4] origin:032-cmt-pll 28_213 +CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_HIGH_TIME[5] origin:032-cmt-pll 29_213 +CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_LOW_TIME[0] origin:032-cmt-pll 28_208 +CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_LOW_TIME[1] origin:032-cmt-pll 29_208 +CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_LOW_TIME[2] origin:032-cmt-pll 28_209 +CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_LOW_TIME[3] origin:032-cmt-pll 29_209 +CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_LOW_TIME[4] origin:032-cmt-pll 28_210 +CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_LOW_TIME[5] origin:032-cmt-pll 29_210 +CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_NO_COUNT[0] origin:032-cmt-pll 28_214 +CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_RESERVED[0] origin:032-cmt-pll 28_215 +CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_RESERVED[1] origin:032-cmt-pll 29_215 +CMT_TOP_L_UPPER_T.PLLE2_ADV.IN_USE origin:032-cmt-pll 28_216 28_219 28_222 28_266 28_280 28_283 28_284 28_37 28_48 28_592 28_622 28_623 28_624 28_627 28_628 28_74 28_768 28_78 28_785 28_786 28_787 28_788 28_790 28_791 28_792 28_793 28_795 28_796 28_797 28_798 28_799 28_803 28_806 28_807 28_811 28_812 28_815 28_816 28_817 28_818 28_819 28_821 28_822 28_823 28_824 28_826 28_827 28_828 28_829 28_832 28_835 28_838 28_841 28_845 28_847 29_268 29_281 29_282 29_283 29_48 29_563 29_567 29_589 29_621 29_622 29_625 29_626 29_627 29_77 29_78 29_785 29_786 29_788 29_79 29_790 29_791 29_793 29_797 29_798 29_800 29_809 29_811 29_812 29_813 29_814 29_815 29_816 29_817 29_819 29_823 29_824 29_825 29_826 29_827 29_829 29_830 29_831 29_832 29_835 29_836 29_838 29_839 29_840 29_841 29_842 29_845 +CMT_TOP_L_UPPER_T.PLLE2_ADV.INV_CLKINSEL origin:032-cmt-pll 28_754 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[0] origin:032-cmt-pll 28_232 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[1] origin:032-cmt-pll 29_232 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[2] origin:032-cmt-pll 28_233 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[3] origin:032-cmt-pll 29_233 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[4] origin:032-cmt-pll 28_234 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[5] origin:032-cmt-pll 29_234 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[6] origin:032-cmt-pll 28_235 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[7] origin:032-cmt-pll 29_235 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[8] origin:032-cmt-pll 28_236 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[9] origin:032-cmt-pll 29_236 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[10] origin:032-cmt-pll 28_240 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[11] origin:032-cmt-pll 29_240 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[12] origin:032-cmt-pll 28_241 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[13] origin:032-cmt-pll 29_241 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[14] origin:032-cmt-pll 28_242 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[15] origin:032-cmt-pll 29_242 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[16] origin:032-cmt-pll 28_243 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[17] origin:032-cmt-pll 29_243 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[18] origin:032-cmt-pll 28_244 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[19] origin:032-cmt-pll 29_244 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[20] origin:032-cmt-pll 28_224 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[21] origin:032-cmt-pll 29_224 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[22] origin:032-cmt-pll 28_225 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[23] origin:032-cmt-pll 29_225 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[24] origin:032-cmt-pll 28_226 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[25] origin:032-cmt-pll 29_226 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[26] origin:032-cmt-pll 28_227 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[27] origin:032-cmt-pll 29_227 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[28] origin:032-cmt-pll 28_228 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[29] origin:032-cmt-pll 29_228 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[30] origin:032-cmt-pll 28_237 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[31] origin:032-cmt-pll 29_237 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[32] origin:032-cmt-pll 28_238 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[33] origin:032-cmt-pll 29_238 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[34] origin:032-cmt-pll 28_239 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[35] origin:032-cmt-pll 28_245 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[36] origin:032-cmt-pll 29_245 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[37] origin:032-cmt-pll 28_246 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[38] origin:032-cmt-pll 29_246 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[39] origin:032-cmt-pll 28_247 +CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[0] origin:032-cmt-pll 28_352 +CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[1] origin:032-cmt-pll 29_352 +CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[2] origin:032-cmt-pll 28_353 +CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[3] origin:032-cmt-pll 29_353 +CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[4] origin:032-cmt-pll 28_354 +CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[5] origin:032-cmt-pll 29_354 +CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[6] origin:032-cmt-pll 28_355 +CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[7] origin:032-cmt-pll 29_355 +CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[8] origin:032-cmt-pll 28_356 +CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[9] origin:032-cmt-pll 29_356 +CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[10] origin:032-cmt-pll 28_357 +CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[11] origin:032-cmt-pll 29_357 +CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[12] origin:032-cmt-pll 28_358 +CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[13] origin:032-cmt-pll 29_358 +CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[14] origin:032-cmt-pll 28_359 +CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[15] origin:032-cmt-pll 29_359 +CMT_TOP_L_UPPER_T.PLLE2_ADV.STARTUP_WAIT origin:032-cmt-pll 28_769 +CMT_TOP_L_UPPER_T.PLLE2_ADV.TABLE[0] origin:032-cmt-pll 28_666 +CMT_TOP_L_UPPER_T.PLLE2_ADV.TABLE[1] origin:032-cmt-pll 29_667 +CMT_TOP_L_UPPER_T.PLLE2_ADV.TABLE[2] origin:032-cmt-pll 28_668 +CMT_TOP_L_UPPER_T.PLLE2_ADV.TABLE[3] origin:032-cmt-pll 29_669 +CMT_TOP_L_UPPER_T.PLLE2_ADV.TABLE[4] origin:032-cmt-pll 28_670 +CMT_TOP_L_UPPER_T.PLLE2_ADV.TABLE[5] origin:032-cmt-pll 29_671 +CMT_TOP_L_UPPER_T.PLLE2_ADV.TABLE[6] origin:032-cmt-pll 28_660 +CMT_TOP_L_UPPER_T.PLLE2_ADV.TABLE[7] origin:032-cmt-pll 29_661 +CMT_TOP_L_UPPER_T.PLLE2_ADV.TABLE[8] origin:032-cmt-pll 28_662 +CMT_TOP_L_UPPER_T.PLLE2_ADV.TABLE[9] origin:032-cmt-pll 29_663 +CMT_TOP_L_UPPER_T.PLLE2_ADV.ZINV_PWRDWN origin:032-cmt-pll 29_752 +CMT_TOP_L_UPPER_T.PLLE2_ADV.ZINV_RST origin:032-cmt-pll 28_752 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_99 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_99 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_100 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_100 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_101 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_101 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_96 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_96 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_97 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_97 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_98 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_98 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_102 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_102 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_103 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_103 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_104 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_104 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_105 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_105 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_106 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_106 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_107 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_110 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_110 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_111 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_109 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_109 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_MX[0] origin:032-cmt-pll 28_108 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_MX[1] origin:032-cmt-pll 29_108 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_107 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_111 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_115 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_115 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_116 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_116 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_117 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_117 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_112 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_112 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_113 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_113 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_114 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_114 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_118 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_118 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_119 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_119 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_120 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_120 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_121 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_121 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_122 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_122 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_123 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_126 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_126 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_127 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_125 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_125 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_MX[0] origin:032-cmt-pll 28_124 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_MX[1] origin:032-cmt-pll 29_124 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_123 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_127 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_131 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_131 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_132 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_132 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_133 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_133 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_128 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_128 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_129 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_129 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_130 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_130 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_134 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_134 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_135 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_135 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_136 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_136 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_137 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_137 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_138 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_138 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_139 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_142 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_142 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_143 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_141 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_141 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_MX[0] origin:032-cmt-pll 28_140 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_MX[1] origin:032-cmt-pll 29_140 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_139 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_143 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_147 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_147 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_148 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_148 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_149 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_149 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_144 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_144 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_145 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_145 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_146 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_146 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_150 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_150 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_151 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_151 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_152 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_152 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_153 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_153 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_154 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_154 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_155 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_158 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_158 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_159 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_157 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_157 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_MX[0] origin:032-cmt-pll 28_156 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_MX[1] origin:032-cmt-pll 29_156 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_155 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_159 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_163 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_163 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_164 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_164 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_165 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_165 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_160 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_160 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_161 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_161 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_162 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_162 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_166 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_166 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_167 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_167 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_168 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_168 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_169 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_169 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_170 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_170 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_171 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_174 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_174 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_175 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_173 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_173 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_MX[0] origin:032-cmt-pll 28_172 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_MX[1] origin:032-cmt-pll 29_172 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_171 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_175 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_83 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_83 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_84 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_84 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_85 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_85 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_80 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_80 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_81 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_81 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_82 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_82 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_86 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_86 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_87 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_87 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_88 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_88 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_89 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_89 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_90 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_90 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_91 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_94 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_94 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_95 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_93 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_93 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_MX[0] origin:032-cmt-pll 28_92 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_MX[1] origin:032-cmt-pll 29_92 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_91 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_95 +CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[0] origin:032-cmt-pll 28_656 +CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[1] origin:032-cmt-pll 29_656 +CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[2] origin:032-cmt-pll 28_657 +CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[3] origin:032-cmt-pll 29_657 +CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[4] origin:032-cmt-pll 28_658 +CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[5] origin:032-cmt-pll 29_658 +CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[6] origin:032-cmt-pll 28_659 +CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[7] origin:032-cmt-pll 29_659 +CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[8] origin:032-cmt-pll 29_660 +CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[9] origin:032-cmt-pll 28_661 +CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[10] origin:032-cmt-pll 29_662 +CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[11] origin:032-cmt-pll 28_663 +CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[0] origin:032-cmt-pll 28_664 +CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[1] origin:032-cmt-pll 29_664 +CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[2] origin:032-cmt-pll 28_665 +CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[3] origin:032-cmt-pll 29_665 +CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[4] origin:032-cmt-pll 29_666 +CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[5] origin:032-cmt-pll 28_667 +CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[6] origin:032-cmt-pll 29_668 +CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[7] origin:032-cmt-pll 28_669 +CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[8] origin:032-cmt-pll 29_670 +CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[9] origin:032-cmt-pll 28_671 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LOCKREG1_RESERVED[0] origin:032-cmt-pll 28_229 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LOCKREG1_RESERVED[1] origin:032-cmt-pll 29_229 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LOCKREG1_RESERVED[2] origin:032-cmt-pll 28_230 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LOCKREG1_RESERVED[3] origin:032-cmt-pll 29_230 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LOCKREG1_RESERVED[4] origin:032-cmt-pll 28_231 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LOCKREG1_RESERVED[5] origin:032-cmt-pll 29_231 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LOCKREG2_RESERVED[0] origin:032-cmt-pll 29_239 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LOCKREG3_RESERVED[0] origin:032-cmt-pll 29_247 diff --git a/artix7/segbits_cmt_top_r_lower_b.db b/artix7/segbits_cmt_top_r_lower_b.db index c725af6..1e746e5 100644 --- a/artix7/segbits_cmt_top_r_lower_b.db +++ b/artix7/segbits_cmt_top_r_lower_b.db @@ -25,381 +25,381 @@ CMT_TOP_R_LOWER_B.MMCM_CLK_FREQ_BB_NS2_ACTIVE 28_1068 28_1076 29_1057 CMT_TOP_R_LOWER_B.MMCM_CLK_FREQ_BB_NS2.MMCM_CLK_FREQ_BB_REBUF2_NS 28_1072 29_1067 29_1075 29_1079 CMT_TOP_R_LOWER_B.MMCM_CLK_FREQ_BB_NS3_ACTIVE 28_1058 28_1069 28_1077 CMT_TOP_R_LOWER_B.MMCM_CLK_FREQ_BB_NS3.MMCM_CLK_FREQ_BB_REBUF3_NS 28_1073 29_1068 29_1076 29_1080 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[0] 29_860 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[1] 28_860 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[2] 29_859 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[3] 28_859 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[4] 29_858 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[5] 28_858 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[0] 29_863 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[1] 28_863 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[2] 29_862 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[3] 28_862 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[4] 29_861 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[5] 28_861 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE[0] 29_857 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_PHASE_MUX[0] 28_857 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_PHASE_MUX[1] 29_856 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_PHASE_MUX[2] 28_856 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[0] 29_855 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[1] 28_855 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[2] 29_854 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[3] 28_854 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[4] 29_853 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[5] 28_853 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_EDGE[0] 28_852 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC[0] 29_849 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC[1] 28_849 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC[2] 29_848 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC_EN[0] 28_850 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC_WF_R[0] 29_850 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_MX[0] 29_851 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_MX[1] 28_851 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_NO_COUNT[0] 29_852 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_RESERVED[0] 28_848 -CMT_TOP_R_LOWER_B.MMCME2.COMP.Z_ZHOLD 28_979 28_1020 -CMT_TOP_R_LOWER_B.MMCME2.COMP.ZHOLD 28_1019 29_982 -CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_EDGE[0] 28_841 -CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[0] 29_844 -CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[1] 28_844 -CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[2] 29_843 -CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[3] 28_843 -CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[4] 29_842 -CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[5] 28_842 -CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[0] 29_847 -CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[1] 28_847 -CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[2] 29_846 -CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[3] 28_846 -CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[4] 29_845 -CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[5] 28_845 -CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_NO_COUNT[0] 29_841 -CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_RESERVED[0] 29_840 -CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_RESERVED[1] 28_840 -CMT_TOP_R_LOWER_B.MMCME2.IN_USE 28_18 28_21 28_22 28_23 28_24 28_25 28_27 28_28 28_31 28_32 28_33 28_34 28_36 28_37 28_38 28_39 28_40 28_44 28_46 28_47 28_48 28_49 28_50 28_51 28_52 28_54 28_63 28_65 28_66 28_70 28_72 28_73 28_75 28_77 28_78 28_428 28_429 28_430 28_433 28_434 28_466 28_488 28_492 28_772 28_773 28_774 28_787 28_976 28_978 28_989 28_991 28_1007 29_16 29_18 29_22 29_25 29_28 29_31 29_34 29_35 29_36 29_37 29_39 29_40 29_41 29_42 29_44 29_45 29_46 29_47 29_48 29_51 29_52 29_56 29_57 29_60 29_64 29_65 29_66 29_67 29_68 29_70 29_71 29_72 29_73 29_75 29_76 29_77 29_78 29_95 29_427 29_428 29_431 29_432 29_433 29_463 29_771 29_772 29_775 29_789 29_833 29_836 29_839 29_977 29_981 29_987 29_990 29_991 29_1007 29_1018 -CMT_TOP_R_LOWER_B.MMCME2.INV_CLKINSEL 29_109 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[0] 29_823 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[1] 28_823 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[2] 29_822 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[3] 28_822 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[4] 29_821 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[5] 28_821 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[6] 29_820 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[7] 28_820 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[8] 29_819 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[9] 28_819 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[10] 29_815 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[11] 28_815 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[12] 29_814 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[13] 28_814 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[14] 29_813 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[15] 28_813 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[16] 29_812 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[17] 28_812 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[18] 29_811 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[19] 28_811 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[20] 29_831 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[21] 28_831 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[22] 29_830 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[23] 28_830 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[24] 29_829 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[25] 28_829 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[26] 29_828 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[27] 28_828 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[28] 29_827 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[29] 28_827 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[30] 29_818 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[31] 28_818 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[32] 29_817 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[33] 28_817 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[34] 29_816 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[35] 29_810 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[36] 28_810 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[37] 29_809 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[38] 28_809 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[39] 29_808 -CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[0] 29_703 -CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[1] 28_703 -CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[2] 29_702 -CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[3] 28_702 -CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[4] 29_701 -CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[5] 28_701 -CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[6] 29_700 -CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[7] 28_700 -CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[8] 29_699 -CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[9] 28_699 -CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[10] 29_698 -CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[11] 28_698 -CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[12] 29_697 -CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[13] 28_697 -CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[14] 29_696 -CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[15] 28_696 -CMT_TOP_R_LOWER_B.MMCME2.SS_EN 28_95 28_388 28_696 28_698 28_700 28_702 28_850 28_915 29_389 29_697 29_701 29_703 -CMT_TOP_R_LOWER_B.MMCME2.STARTUP_WAIT 29_94 -CMT_TOP_R_LOWER_B.MMCME2.TABLE[0] 29_389 -CMT_TOP_R_LOWER_B.MMCME2.TABLE[1] 28_388 -CMT_TOP_R_LOWER_B.MMCME2.TABLE[2] 29_387 -CMT_TOP_R_LOWER_B.MMCME2.TABLE[3] 28_386 -CMT_TOP_R_LOWER_B.MMCME2.TABLE[4] 29_385 -CMT_TOP_R_LOWER_B.MMCME2.TABLE[5] 28_384 -CMT_TOP_R_LOWER_B.MMCME2.TABLE[6] 29_395 -CMT_TOP_R_LOWER_B.MMCME2.TABLE[7] 28_394 -CMT_TOP_R_LOWER_B.MMCME2.TABLE[8] 29_393 -CMT_TOP_R_LOWER_B.MMCME2.TABLE[9] 28_392 -CMT_TOP_R_LOWER_B.MMCME2.ZINV_PSEN 28_110 -CMT_TOP_R_LOWER_B.MMCME2.ZINV_PSINCDEC 29_110 -CMT_TOP_R_LOWER_B.MMCME2.ZINV_PWRDWN 28_111 -CMT_TOP_R_LOWER_B.MMCME2.ZINV_RST 29_111 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[0] 29_956 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[1] 28_956 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[2] 29_955 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[3] 28_955 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[4] 29_954 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[5] 28_954 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[0] 29_959 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[1] 28_959 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[2] 29_958 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[3] 28_958 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[4] 29_957 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[5] 28_957 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_OUTPUT_ENABLE[0] 29_953 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_PHASE_MUX[0] 28_953 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_PHASE_MUX[1] 29_952 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_PHASE_MUX[2] 28_952 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[0] 29_951 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[1] 28_951 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[2] 29_950 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[3] 28_950 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[4] 29_949 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[5] 28_949 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_EDGE[0] 28_948 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC[0] 29_945 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC[1] 28_945 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC[2] 29_944 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC_EN[0] 28_946 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC_WF_R[0] 29_946 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_MX[0] 29_947 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_MX[1] 28_947 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_NO_COUNT[0] 29_948 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_RESERVED[0] 28_944 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[0] 29_940 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[1] 28_940 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[2] 29_939 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[3] 28_939 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[4] 29_938 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[5] 28_938 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[0] 29_943 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[1] 28_943 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[2] 29_942 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[3] 28_942 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[4] 29_941 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[5] 28_941 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_OUTPUT_ENABLE[0] 29_937 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_PHASE_MUX[0] 28_937 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_PHASE_MUX[1] 29_936 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_PHASE_MUX[2] 28_936 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[0] 29_935 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[1] 28_935 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[2] 29_934 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[3] 28_934 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[4] 29_933 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[5] 28_933 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_EDGE[0] 28_932 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC[0] 29_929 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC[1] 28_929 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC[2] 29_928 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC_EN[0] 28_930 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC_WF_R[0] 29_930 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_MX[0] 29_931 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_MX[1] 28_931 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_NO_COUNT[0] 29_932 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_RESERVED[0] 28_928 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[0] 29_924 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[1] 28_924 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[2] 29_923 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[3] 28_923 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[4] 29_922 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[5] 28_922 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[0] 29_927 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[1] 28_927 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[2] 29_926 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[3] 28_926 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[4] 29_925 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[5] 28_925 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_OUTPUT_ENABLE[0] 29_921 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_PHASE_MUX[0] 28_921 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_PHASE_MUX[1] 29_920 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_PHASE_MUX[2] 28_920 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[0] 29_919 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[1] 28_919 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[2] 29_918 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[3] 28_918 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[4] 29_917 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[5] 28_917 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_EDGE[0] 28_916 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC[0] 29_913 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC[1] 28_913 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC[2] 29_912 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC_EN[0] 28_914 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC_WF_R[0] 29_914 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_MX[0] 29_915 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_MX[1] 28_915 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_NO_COUNT[0] 29_916 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_RESERVED[0] 28_912 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[0] 29_908 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[1] 28_908 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[2] 29_907 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[3] 28_907 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[4] 29_906 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[5] 28_906 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[0] 29_911 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[1] 28_911 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[2] 29_910 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[3] 28_910 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[4] 29_909 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[5] 28_909 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_OUTPUT_ENABLE[0] 29_905 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_PHASE_MUX[0] 28_905 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_PHASE_MUX[1] 29_904 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_PHASE_MUX[2] 28_904 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[0] 29_903 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[1] 28_903 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[2] 29_902 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[3] 28_902 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[4] 29_901 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[5] 28_901 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_EDGE[0] 28_900 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC[0] 29_897 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC[1] 28_897 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC[2] 29_896 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC_EN[0] 28_898 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC_WF_R[0] 29_898 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_MX[0] 29_899 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_MX[1] 28_899 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_NO_COUNT[0] 29_900 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_RESERVED[0] 28_896 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[0] 29_892 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[1] 28_892 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[2] 29_891 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[3] 28_891 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[4] 29_890 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[5] 28_890 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[0] 29_895 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[1] 28_895 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[2] 29_894 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[3] 28_894 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[4] 29_893 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[5] 28_893 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_OUTPUT_ENABLE[0] 29_889 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_PHASE_MUX[0] 28_889 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_PHASE_MUX[1] 29_888 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_PHASE_MUX[2] 28_888 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[0] 29_887 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[1] 28_887 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[2] 29_886 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[3] 28_886 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[4] 29_885 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[5] 28_885 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_EDGE[0] 28_884 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC[0] 29_881 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC[1] 28_881 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC[2] 29_880 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC_EN[0] 28_882 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC_WF_R[0] 29_882 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_MX[0] 29_883 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_MX[1] 28_883 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_NO_COUNT[0] 29_884 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_RESERVED[0] 28_880 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[0] 29_972 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[1] 28_972 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[2] 29_971 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[3] 28_971 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[4] 29_970 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[5] 28_970 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[0] 29_975 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[1] 28_975 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[2] 29_974 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[3] 28_974 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[4] 29_973 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[5] 28_973 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_OUTPUT_ENABLE[0] 29_969 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_PHASE_MUX[0] 28_969 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_PHASE_MUX[1] 29_968 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_PHASE_MUX[2] 28_968 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[0] 29_967 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[1] 28_967 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[2] 29_966 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[3] 28_966 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[4] 29_965 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[5] 28_965 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_EDGE[0] 28_964 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_FRAC_WF_F[0] 29_962 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_MX[0] 29_963 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_MX[1] 28_963 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_NO_COUNT[0] 29_964 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[0] 28_962 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[1] 29_961 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[2] 28_961 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_RESERVED[0] 29_960 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_RESERVED[1] 28_960 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[0] 29_876 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[1] 28_876 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[2] 29_875 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[3] 28_875 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[4] 29_874 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[5] 28_874 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[0] 29_879 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[1] 28_879 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[2] 29_878 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[3] 28_878 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[4] 29_877 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[5] 28_877 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_OUTPUT_ENABLE[0] 29_873 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_PHASE_MUX[0] 28_873 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_PHASE_MUX[1] 29_872 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_PHASE_MUX[2] 28_872 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[0] 29_871 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[1] 28_871 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[2] 29_870 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[3] 28_870 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[4] 29_869 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[5] 28_869 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_EDGE[0] 28_868 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_FRAC_WF_F[0] 29_866 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_MX[0] 29_867 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_MX[1] 28_867 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_NO_COUNT[0] 29_868 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[0] 28_866 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[1] 29_865 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[2] 28_865 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_RESERVED[0] 29_864 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_RESERVED[1] 28_864 -CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[0] 29_399 -CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[1] 28_399 -CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[2] 29_398 -CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[3] 28_398 -CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[4] 29_397 -CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[5] 28_397 -CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[6] 29_396 -CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[7] 28_396 -CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[8] 28_395 -CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[9] 29_394 -CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[10] 28_393 -CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[11] 29_392 -CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[0] 29_391 -CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[1] 28_391 -CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[2] 29_390 -CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[3] 28_390 -CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[4] 28_389 -CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[5] 29_388 -CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[6] 28_387 -CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[7] 29_386 -CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[8] 28_385 -CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[9] 29_384 -CMT_TOP_R_LOWER_B.MMCME2.LOCKREG1_RESERVED[0] 29_826 -CMT_TOP_R_LOWER_B.MMCME2.LOCKREG1_RESERVED[1] 28_826 -CMT_TOP_R_LOWER_B.MMCME2.LOCKREG1_RESERVED[2] 29_825 -CMT_TOP_R_LOWER_B.MMCME2.LOCKREG1_RESERVED[3] 28_825 -CMT_TOP_R_LOWER_B.MMCME2.LOCKREG1_RESERVED[4] 29_824 -CMT_TOP_R_LOWER_B.MMCME2.LOCKREG1_RESERVED[5] 28_824 -CMT_TOP_R_LOWER_B.MMCME2.LOCKREG2_RESERVED[0] 28_816 -CMT_TOP_R_LOWER_B.MMCME2.LOCKREG3_RESERVED[0] 28_808 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[0] 29_860 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[1] 28_860 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[2] 29_859 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[3] 28_859 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[4] 29_858 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[5] 28_858 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[0] 29_863 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[1] 28_863 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[2] 29_862 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[3] 28_862 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[4] 29_861 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[5] 28_861 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE[0] 29_857 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_PHASE_MUX[0] 28_857 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_PHASE_MUX[1] 29_856 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_PHASE_MUX[2] 28_856 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[0] 29_855 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[1] 28_855 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[2] 29_854 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[3] 28_854 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[4] 29_853 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[5] 28_853 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_EDGE[0] 28_852 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_FRAC[0] 29_849 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_FRAC[1] 28_849 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_FRAC[2] 29_848 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_FRAC_EN[0] 28_850 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_FRAC_WF_R[0] 29_850 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_MX[0] 29_851 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_MX[1] 28_851 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_NO_COUNT[0] 29_852 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_RESERVED[0] 28_848 +CMT_TOP_R_LOWER_B.MMCME2_ADV.COMP.Z_ZHOLD 28_979 28_1020 +CMT_TOP_R_LOWER_B.MMCME2_ADV.COMP.ZHOLD 28_1019 29_982 +CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_EDGE[0] 28_841 +CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_HIGH_TIME[0] 29_844 +CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_HIGH_TIME[1] 28_844 +CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_HIGH_TIME[2] 29_843 +CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_HIGH_TIME[3] 28_843 +CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_HIGH_TIME[4] 29_842 +CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_HIGH_TIME[5] 28_842 +CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_LOW_TIME[0] 29_847 +CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_LOW_TIME[1] 28_847 +CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_LOW_TIME[2] 29_846 +CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_LOW_TIME[3] 28_846 +CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_LOW_TIME[4] 29_845 +CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_LOW_TIME[5] 28_845 +CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_NO_COUNT[0] 29_841 +CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_RESERVED[0] 29_840 +CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_RESERVED[1] 28_840 +CMT_TOP_R_LOWER_B.MMCME2_ADV.IN_USE 28_18 28_21 28_22 28_23 28_24 28_25 28_27 28_28 28_31 28_32 28_33 28_34 28_36 28_37 28_38 28_39 28_40 28_44 28_46 28_47 28_48 28_49 28_50 28_51 28_52 28_54 28_63 28_65 28_66 28_70 28_72 28_73 28_75 28_77 28_78 28_428 28_429 28_430 28_433 28_434 28_466 28_488 28_492 28_772 28_773 28_774 28_787 28_976 28_978 28_989 28_991 28_1007 29_16 29_18 29_22 29_25 29_28 29_31 29_34 29_35 29_36 29_37 29_39 29_40 29_41 29_42 29_44 29_45 29_46 29_47 29_48 29_51 29_52 29_56 29_57 29_60 29_64 29_65 29_66 29_67 29_68 29_70 29_71 29_72 29_73 29_75 29_76 29_77 29_78 29_95 29_427 29_428 29_431 29_432 29_433 29_463 29_771 29_772 29_775 29_789 29_833 29_836 29_839 29_977 29_981 29_987 29_990 29_991 29_1007 29_1018 +CMT_TOP_R_LOWER_B.MMCME2_ADV.INV_CLKINSEL 29_109 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[0] 29_823 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[1] 28_823 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[2] 29_822 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[3] 28_822 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[4] 29_821 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[5] 28_821 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[6] 29_820 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[7] 28_820 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[8] 29_819 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[9] 28_819 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[10] 29_815 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[11] 28_815 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[12] 29_814 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[13] 28_814 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[14] 29_813 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[15] 28_813 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[16] 29_812 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[17] 28_812 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[18] 29_811 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[19] 28_811 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[20] 29_831 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[21] 28_831 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[22] 29_830 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[23] 28_830 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[24] 29_829 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[25] 28_829 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[26] 29_828 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[27] 28_828 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[28] 29_827 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[29] 28_827 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[30] 29_818 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[31] 28_818 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[32] 29_817 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[33] 28_817 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[34] 29_816 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[35] 29_810 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[36] 28_810 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[37] 29_809 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[38] 28_809 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[39] 29_808 +CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[0] 29_703 +CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[1] 28_703 +CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[2] 29_702 +CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[3] 28_702 +CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[4] 29_701 +CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[5] 28_701 +CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[6] 29_700 +CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[7] 28_700 +CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[8] 29_699 +CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[9] 28_699 +CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[10] 29_698 +CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[11] 28_698 +CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[12] 29_697 +CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[13] 28_697 +CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[14] 29_696 +CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[15] 28_696 +CMT_TOP_R_LOWER_B.MMCME2_ADV.SS_EN 28_95 28_388 28_696 28_698 28_700 28_702 28_850 28_915 29_389 29_697 29_701 29_703 +CMT_TOP_R_LOWER_B.MMCME2_ADV.STARTUP_WAIT 29_94 +CMT_TOP_R_LOWER_B.MMCME2_ADV.TABLE[0] 29_389 +CMT_TOP_R_LOWER_B.MMCME2_ADV.TABLE[1] 28_388 +CMT_TOP_R_LOWER_B.MMCME2_ADV.TABLE[2] 29_387 +CMT_TOP_R_LOWER_B.MMCME2_ADV.TABLE[3] 28_386 +CMT_TOP_R_LOWER_B.MMCME2_ADV.TABLE[4] 29_385 +CMT_TOP_R_LOWER_B.MMCME2_ADV.TABLE[5] 28_384 +CMT_TOP_R_LOWER_B.MMCME2_ADV.TABLE[6] 29_395 +CMT_TOP_R_LOWER_B.MMCME2_ADV.TABLE[7] 28_394 +CMT_TOP_R_LOWER_B.MMCME2_ADV.TABLE[8] 29_393 +CMT_TOP_R_LOWER_B.MMCME2_ADV.TABLE[9] 28_392 +CMT_TOP_R_LOWER_B.MMCME2_ADV.ZINV_PSEN 28_110 +CMT_TOP_R_LOWER_B.MMCME2_ADV.ZINV_PSINCDEC 29_110 +CMT_TOP_R_LOWER_B.MMCME2_ADV.ZINV_PWRDWN 28_111 +CMT_TOP_R_LOWER_B.MMCME2_ADV.ZINV_RST 29_111 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[0] 29_956 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[1] 28_956 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[2] 29_955 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[3] 28_955 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[4] 29_954 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[5] 28_954 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[0] 29_959 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[1] 28_959 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[2] 29_958 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[3] 28_958 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[4] 29_957 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[5] 28_957 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_OUTPUT_ENABLE[0] 29_953 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_PHASE_MUX[0] 28_953 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_PHASE_MUX[1] 29_952 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_PHASE_MUX[2] 28_952 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[0] 29_951 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[1] 28_951 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[2] 29_950 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[3] 28_950 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[4] 29_949 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[5] 28_949 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_EDGE[0] 28_948 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_FRAC[0] 29_945 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_FRAC[1] 28_945 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_FRAC[2] 29_944 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_FRAC_EN[0] 28_946 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_FRAC_WF_R[0] 29_946 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_MX[0] 29_947 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_MX[1] 28_947 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_NO_COUNT[0] 29_948 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_RESERVED[0] 28_944 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[0] 29_940 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[1] 28_940 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[2] 29_939 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[3] 28_939 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[4] 29_938 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[5] 28_938 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[0] 29_943 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[1] 28_943 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[2] 29_942 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[3] 28_942 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[4] 29_941 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[5] 28_941 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_OUTPUT_ENABLE[0] 29_937 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_PHASE_MUX[0] 28_937 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_PHASE_MUX[1] 29_936 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_PHASE_MUX[2] 28_936 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[0] 29_935 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[1] 28_935 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[2] 29_934 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[3] 28_934 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[4] 29_933 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[5] 28_933 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_EDGE[0] 28_932 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_FRAC[0] 29_929 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_FRAC[1] 28_929 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_FRAC[2] 29_928 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_FRAC_EN[0] 28_930 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_FRAC_WF_R[0] 29_930 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_MX[0] 29_931 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_MX[1] 28_931 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_NO_COUNT[0] 29_932 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_RESERVED[0] 28_928 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[0] 29_924 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[1] 28_924 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[2] 29_923 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[3] 28_923 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[4] 29_922 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[5] 28_922 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[0] 29_927 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[1] 28_927 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[2] 29_926 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[3] 28_926 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[4] 29_925 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[5] 28_925 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_OUTPUT_ENABLE[0] 29_921 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_PHASE_MUX[0] 28_921 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_PHASE_MUX[1] 29_920 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_PHASE_MUX[2] 28_920 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[0] 29_919 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[1] 28_919 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[2] 29_918 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[3] 28_918 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[4] 29_917 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[5] 28_917 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_EDGE[0] 28_916 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_FRAC[0] 29_913 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_FRAC[1] 28_913 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_FRAC[2] 29_912 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_FRAC_EN[0] 28_914 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_FRAC_WF_R[0] 29_914 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_MX[0] 29_915 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_MX[1] 28_915 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_NO_COUNT[0] 29_916 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_RESERVED[0] 28_912 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[0] 29_908 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[1] 28_908 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[2] 29_907 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[3] 28_907 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[4] 29_906 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[5] 28_906 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[0] 29_911 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[1] 28_911 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[2] 29_910 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[3] 28_910 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[4] 29_909 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[5] 28_909 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_OUTPUT_ENABLE[0] 29_905 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_PHASE_MUX[0] 28_905 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_PHASE_MUX[1] 29_904 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_PHASE_MUX[2] 28_904 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[0] 29_903 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[1] 28_903 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[2] 29_902 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[3] 28_902 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[4] 29_901 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[5] 28_901 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_EDGE[0] 28_900 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_FRAC[0] 29_897 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_FRAC[1] 28_897 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_FRAC[2] 29_896 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_FRAC_EN[0] 28_898 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_FRAC_WF_R[0] 29_898 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_MX[0] 29_899 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_MX[1] 28_899 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_NO_COUNT[0] 29_900 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_RESERVED[0] 28_896 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[0] 29_892 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[1] 28_892 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[2] 29_891 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[3] 28_891 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[4] 29_890 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[5] 28_890 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[0] 29_895 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[1] 28_895 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[2] 29_894 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[3] 28_894 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[4] 29_893 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[5] 28_893 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_OUTPUT_ENABLE[0] 29_889 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_PHASE_MUX[0] 28_889 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_PHASE_MUX[1] 29_888 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_PHASE_MUX[2] 28_888 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[0] 29_887 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[1] 28_887 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[2] 29_886 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[3] 28_886 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[4] 29_885 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[5] 28_885 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_EDGE[0] 28_884 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_FRAC[0] 29_881 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_FRAC[1] 28_881 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_FRAC[2] 29_880 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_FRAC_EN[0] 28_882 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_FRAC_WF_R[0] 29_882 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_MX[0] 29_883 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_MX[1] 28_883 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_NO_COUNT[0] 29_884 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_RESERVED[0] 28_880 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[0] 29_972 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[1] 28_972 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[2] 29_971 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[3] 28_971 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[4] 29_970 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[5] 28_970 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[0] 29_975 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[1] 28_975 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[2] 29_974 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[3] 28_974 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[4] 29_973 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[5] 28_973 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_OUTPUT_ENABLE[0] 29_969 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_PHASE_MUX[0] 28_969 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_PHASE_MUX[1] 29_968 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_PHASE_MUX[2] 28_968 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[0] 29_967 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[1] 28_967 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[2] 29_966 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[3] 28_966 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[4] 29_965 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[5] 28_965 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_EDGE[0] 28_964 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_FRAC_WF_F[0] 29_962 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_MX[0] 29_963 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_MX[1] 28_963 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_NO_COUNT[0] 29_964 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[0] 28_962 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[1] 29_961 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[2] 28_961 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_RESERVED[0] 29_960 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_RESERVED[1] 28_960 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_HIGH_TIME[0] 29_876 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_HIGH_TIME[1] 28_876 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_HIGH_TIME[2] 29_875 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_HIGH_TIME[3] 28_875 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_HIGH_TIME[4] 29_874 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_HIGH_TIME[5] 28_874 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_LOW_TIME[0] 29_879 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_LOW_TIME[1] 28_879 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_LOW_TIME[2] 29_878 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_LOW_TIME[3] 28_878 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_LOW_TIME[4] 29_877 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_LOW_TIME[5] 28_877 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_OUTPUT_ENABLE[0] 29_873 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_PHASE_MUX[0] 28_873 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_PHASE_MUX[1] 29_872 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_PHASE_MUX[2] 28_872 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[0] 29_871 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[1] 28_871 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[2] 29_870 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[3] 28_870 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[4] 29_869 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[5] 28_869 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_EDGE[0] 28_868 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_FRAC_WF_F[0] 29_866 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_MX[0] 29_867 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_MX[1] 28_867 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_NO_COUNT[0] 29_868 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[0] 28_866 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[1] 29_865 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[2] 28_865 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_RESERVED[0] 29_864 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_RESERVED[1] 28_864 +CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[0] 29_399 +CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[1] 28_399 +CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[2] 29_398 +CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[3] 28_398 +CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[4] 29_397 +CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[5] 28_397 +CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[6] 29_396 +CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[7] 28_396 +CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[8] 28_395 +CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[9] 29_394 +CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[10] 28_393 +CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[11] 29_392 +CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[0] 29_391 +CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[1] 28_391 +CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[2] 29_390 +CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[3] 28_390 +CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[4] 28_389 +CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[5] 29_388 +CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[6] 28_387 +CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[7] 29_386 +CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[8] 28_385 +CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[9] 29_384 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LOCKREG1_RESERVED[0] 29_826 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LOCKREG1_RESERVED[1] 28_826 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LOCKREG1_RESERVED[2] 29_825 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LOCKREG1_RESERVED[3] 28_825 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LOCKREG1_RESERVED[4] 29_824 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LOCKREG1_RESERVED[5] 28_824 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LOCKREG2_RESERVED[0] 28_816 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LOCKREG3_RESERVED[0] 28_808 diff --git a/artix7/segbits_cmt_top_r_lower_b.origin_info.db b/artix7/segbits_cmt_top_r_lower_b.origin_info.db index ad25957..07d55fa 100644 --- a/artix7/segbits_cmt_top_r_lower_b.origin_info.db +++ b/artix7/segbits_cmt_top_r_lower_b.origin_info.db @@ -25,381 +25,381 @@ CMT_TOP_R_LOWER_B.MMCM_CLK_FREQ_BB_NS2_ACTIVE origin:034b-cmt-mmcm-pips 28_1068 CMT_TOP_R_LOWER_B.MMCM_CLK_FREQ_BB_NS2.MMCM_CLK_FREQ_BB_REBUF2_NS origin:034b-cmt-mmcm-pips 28_1072 29_1067 29_1075 29_1079 CMT_TOP_R_LOWER_B.MMCM_CLK_FREQ_BB_NS3_ACTIVE origin:034b-cmt-mmcm-pips 28_1058 28_1069 28_1077 CMT_TOP_R_LOWER_B.MMCM_CLK_FREQ_BB_NS3.MMCM_CLK_FREQ_BB_REBUF3_NS origin:034b-cmt-mmcm-pips 28_1073 29_1068 29_1076 29_1080 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_860 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_860 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_859 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_859 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_858 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_858 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_863 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_863 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_862 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_862 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_861 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_861 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_857 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_857 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_856 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_856 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_855 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_855 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_854 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_854 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_853 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_853 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_852 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_849 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_849 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_848 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_850 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_850 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_851 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_851 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_852 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_848 -CMT_TOP_R_LOWER_B.MMCME2.COMP.Z_ZHOLD origin:031-cmt-mmcm 28_1020 28_979 -CMT_TOP_R_LOWER_B.MMCME2.COMP.ZHOLD origin:031-cmt-mmcm 28_1019 29_982 -CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_EDGE[0] origin:031-cmt-mmcm 28_841 -CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[0] origin:031-cmt-mmcm 29_844 -CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[1] origin:031-cmt-mmcm 28_844 -CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[2] origin:031-cmt-mmcm 29_843 -CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[3] origin:031-cmt-mmcm 28_843 -CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[4] origin:031-cmt-mmcm 29_842 -CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[5] origin:031-cmt-mmcm 28_842 -CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[0] origin:031-cmt-mmcm 29_847 -CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[1] origin:031-cmt-mmcm 28_847 -CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[2] origin:031-cmt-mmcm 29_846 -CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[3] origin:031-cmt-mmcm 28_846 -CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[4] origin:031-cmt-mmcm 29_845 -CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[5] origin:031-cmt-mmcm 28_845 -CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_NO_COUNT[0] origin:031-cmt-mmcm 29_841 -CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_RESERVED[0] origin:031-cmt-mmcm 29_840 -CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_RESERVED[1] origin:031-cmt-mmcm 28_840 -CMT_TOP_R_LOWER_B.MMCME2.IN_USE origin:031-cmt-mmcm 28_1007 28_18 28_21 28_22 28_23 28_24 28_25 28_27 28_28 28_31 28_32 28_33 28_34 28_36 28_37 28_38 28_39 28_40 28_428 28_429 28_430 28_433 28_434 28_44 28_46 28_466 28_47 28_48 28_488 28_49 28_492 28_50 28_51 28_52 28_54 28_63 28_65 28_66 28_70 28_72 28_73 28_75 28_77 28_772 28_773 28_774 28_78 28_787 28_976 28_978 28_989 28_991 29_1007 29_1018 29_16 29_18 29_22 29_25 29_28 29_31 29_34 29_35 29_36 29_37 29_39 29_40 29_41 29_42 29_427 29_428 29_431 29_432 29_433 29_44 29_45 29_46 29_463 29_47 29_48 29_51 29_52 29_56 29_57 29_60 29_64 29_65 29_66 29_67 29_68 29_70 29_71 29_72 29_73 29_75 29_76 29_77 29_771 29_772 29_775 29_78 29_789 29_833 29_836 29_839 29_95 29_977 29_981 29_987 29_990 29_991 -CMT_TOP_R_LOWER_B.MMCME2.INV_CLKINSEL origin:031-cmt-mmcm 29_109 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[0] origin:031-cmt-mmcm 29_823 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[1] origin:031-cmt-mmcm 28_823 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[2] origin:031-cmt-mmcm 29_822 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[3] origin:031-cmt-mmcm 28_822 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[4] origin:031-cmt-mmcm 29_821 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[5] origin:031-cmt-mmcm 28_821 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[6] origin:031-cmt-mmcm 29_820 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[7] origin:031-cmt-mmcm 28_820 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[8] origin:031-cmt-mmcm 29_819 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[9] origin:031-cmt-mmcm 28_819 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[10] origin:031-cmt-mmcm 29_815 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[11] origin:031-cmt-mmcm 28_815 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[12] origin:031-cmt-mmcm 29_814 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[13] origin:031-cmt-mmcm 28_814 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[14] origin:031-cmt-mmcm 29_813 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[15] origin:031-cmt-mmcm 28_813 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[16] origin:031-cmt-mmcm 29_812 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[17] origin:031-cmt-mmcm 28_812 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[18] origin:031-cmt-mmcm 29_811 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[19] origin:031-cmt-mmcm 28_811 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[20] origin:031-cmt-mmcm 29_831 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[21] origin:031-cmt-mmcm 28_831 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[22] origin:031-cmt-mmcm 29_830 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[23] origin:031-cmt-mmcm 28_830 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[24] origin:031-cmt-mmcm 29_829 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[25] origin:031-cmt-mmcm 28_829 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[26] origin:031-cmt-mmcm 29_828 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[27] origin:031-cmt-mmcm 28_828 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[28] origin:031-cmt-mmcm 29_827 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[29] origin:031-cmt-mmcm 28_827 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[30] origin:031-cmt-mmcm 29_818 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[31] origin:031-cmt-mmcm 28_818 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[32] origin:031-cmt-mmcm 29_817 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[33] origin:031-cmt-mmcm 28_817 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[34] origin:031-cmt-mmcm 29_816 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[35] origin:031-cmt-mmcm 29_810 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[36] origin:031-cmt-mmcm 28_810 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[37] origin:031-cmt-mmcm 29_809 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[38] origin:031-cmt-mmcm 28_809 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[39] origin:031-cmt-mmcm 29_808 -CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[0] origin:031-cmt-mmcm 29_703 -CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[1] origin:031-cmt-mmcm 28_703 -CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[2] origin:031-cmt-mmcm 29_702 -CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[3] origin:031-cmt-mmcm 28_702 -CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[4] origin:031-cmt-mmcm 29_701 -CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[5] origin:031-cmt-mmcm 28_701 -CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[6] origin:031-cmt-mmcm 29_700 -CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[7] origin:031-cmt-mmcm 28_700 -CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[8] origin:031-cmt-mmcm 29_699 -CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[9] origin:031-cmt-mmcm 28_699 -CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[10] origin:031-cmt-mmcm 29_698 -CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[11] origin:031-cmt-mmcm 28_698 -CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[12] origin:031-cmt-mmcm 29_697 -CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[13] origin:031-cmt-mmcm 28_697 -CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[14] origin:031-cmt-mmcm 29_696 -CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[15] origin:031-cmt-mmcm 28_696 -CMT_TOP_R_LOWER_B.MMCME2.SS_EN origin:031-cmt-mmcm 28_388 28_696 28_698 28_700 28_702 28_850 28_915 28_95 29_389 29_697 29_701 29_703 -CMT_TOP_R_LOWER_B.MMCME2.STARTUP_WAIT origin:031-cmt-mmcm 29_94 -CMT_TOP_R_LOWER_B.MMCME2.TABLE[0] origin:031-cmt-mmcm 29_389 -CMT_TOP_R_LOWER_B.MMCME2.TABLE[1] origin:031-cmt-mmcm 28_388 -CMT_TOP_R_LOWER_B.MMCME2.TABLE[2] origin:031-cmt-mmcm 29_387 -CMT_TOP_R_LOWER_B.MMCME2.TABLE[3] origin:031-cmt-mmcm 28_386 -CMT_TOP_R_LOWER_B.MMCME2.TABLE[4] origin:031-cmt-mmcm 29_385 -CMT_TOP_R_LOWER_B.MMCME2.TABLE[5] origin:031-cmt-mmcm 28_384 -CMT_TOP_R_LOWER_B.MMCME2.TABLE[6] origin:031-cmt-mmcm 29_395 -CMT_TOP_R_LOWER_B.MMCME2.TABLE[7] origin:031-cmt-mmcm 28_394 -CMT_TOP_R_LOWER_B.MMCME2.TABLE[8] origin:031-cmt-mmcm 29_393 -CMT_TOP_R_LOWER_B.MMCME2.TABLE[9] origin:031-cmt-mmcm 28_392 -CMT_TOP_R_LOWER_B.MMCME2.ZINV_PSEN origin:031-cmt-mmcm 28_110 -CMT_TOP_R_LOWER_B.MMCME2.ZINV_PSINCDEC origin:031-cmt-mmcm 29_110 -CMT_TOP_R_LOWER_B.MMCME2.ZINV_PWRDWN origin:031-cmt-mmcm 28_111 -CMT_TOP_R_LOWER_B.MMCME2.ZINV_RST origin:031-cmt-mmcm 29_111 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_956 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_956 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_955 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_955 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_954 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_954 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_959 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_959 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_958 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_958 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_957 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_957 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_953 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_953 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_952 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_952 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_951 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_951 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_950 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_950 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_949 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_949 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_948 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_945 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_945 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_944 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_946 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_946 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_947 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_947 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_948 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_944 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_940 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_940 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_939 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_939 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_938 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_938 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_943 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_943 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_942 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_942 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_941 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_941 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_937 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_937 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_936 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_936 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_935 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_935 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_934 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_934 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_933 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_933 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_932 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_929 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_929 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_928 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_930 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_930 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_931 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_931 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_932 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_928 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_924 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_924 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_923 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_923 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_922 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_922 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_927 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_927 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_926 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_926 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_925 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_925 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_921 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_921 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_920 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_920 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_919 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_919 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_918 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_918 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_917 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_917 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_916 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_913 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_913 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_912 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_914 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_914 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_915 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_915 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_916 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_912 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_908 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_908 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_907 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_907 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_906 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_906 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_911 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_911 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_910 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_910 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_909 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_909 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_905 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_905 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_904 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_904 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_903 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_903 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_902 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_902 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_901 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_901 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_900 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_897 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_897 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_896 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_898 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_898 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_899 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_899 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_900 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_896 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_892 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_892 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_891 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_891 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_890 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_890 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_895 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_895 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_894 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_894 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_893 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_893 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_889 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_889 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_888 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_888 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_887 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_887 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_886 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_886 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_885 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_885 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_884 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_881 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_881 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_880 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_882 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_882 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_883 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_883 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_884 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_880 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_972 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_972 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_971 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_971 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_970 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_970 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_975 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_975 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_974 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_974 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_973 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_973 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_969 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_969 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_968 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_968 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[0] origin:031-cmt-mmcm 29_967 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[1] origin:031-cmt-mmcm 28_967 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[2] origin:031-cmt-mmcm 29_966 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[3] origin:031-cmt-mmcm 28_966 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[4] origin:031-cmt-mmcm 29_965 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[5] origin:031-cmt-mmcm 28_965 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_EDGE[0] origin:031-cmt-mmcm 28_964 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_FRAC_WF_F[0] origin:031-cmt-mmcm 29_962 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_MX[0] origin:031-cmt-mmcm 29_963 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_MX[1] origin:031-cmt-mmcm 28_963 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_NO_COUNT[0] origin:031-cmt-mmcm 29_964 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[0] origin:031-cmt-mmcm 28_962 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[1] origin:031-cmt-mmcm 29_961 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[2] origin:031-cmt-mmcm 28_961 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_RESERVED[0] origin:031-cmt-mmcm 29_960 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_RESERVED[1] origin:031-cmt-mmcm 28_960 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_876 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_876 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_875 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_875 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_874 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_874 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_879 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_879 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_878 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_878 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_877 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_877 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_873 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_873 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_872 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_872 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[0] origin:031-cmt-mmcm 29_871 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[1] origin:031-cmt-mmcm 28_871 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[2] origin:031-cmt-mmcm 29_870 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[3] origin:031-cmt-mmcm 28_870 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[4] origin:031-cmt-mmcm 29_869 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[5] origin:031-cmt-mmcm 28_869 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_EDGE[0] origin:031-cmt-mmcm 28_868 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_FRAC_WF_F[0] origin:031-cmt-mmcm 29_866 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_MX[0] origin:031-cmt-mmcm 29_867 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_MX[1] origin:031-cmt-mmcm 28_867 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_NO_COUNT[0] origin:031-cmt-mmcm 29_868 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[0] origin:031-cmt-mmcm 28_866 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[1] origin:031-cmt-mmcm 29_865 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[2] origin:031-cmt-mmcm 28_865 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_RESERVED[0] origin:031-cmt-mmcm 29_864 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_RESERVED[1] origin:031-cmt-mmcm 28_864 -CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[0] origin:031-cmt-mmcm 29_399 -CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[1] origin:031-cmt-mmcm 28_399 -CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[2] origin:031-cmt-mmcm 29_398 -CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[3] origin:031-cmt-mmcm 28_398 -CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[4] origin:031-cmt-mmcm 29_397 -CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[5] origin:031-cmt-mmcm 28_397 -CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[6] origin:031-cmt-mmcm 29_396 -CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[7] origin:031-cmt-mmcm 28_396 -CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[8] origin:031-cmt-mmcm 28_395 -CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[9] origin:031-cmt-mmcm 29_394 -CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[10] origin:031-cmt-mmcm 28_393 -CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[11] origin:031-cmt-mmcm 29_392 -CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[0] origin:031-cmt-mmcm 29_391 -CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[1] origin:031-cmt-mmcm 28_391 -CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[2] origin:031-cmt-mmcm 29_390 -CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[3] origin:031-cmt-mmcm 28_390 -CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[4] origin:031-cmt-mmcm 28_389 -CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[5] origin:031-cmt-mmcm 29_388 -CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[6] origin:031-cmt-mmcm 28_387 -CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[7] origin:031-cmt-mmcm 29_386 -CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[8] origin:031-cmt-mmcm 28_385 -CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[9] origin:031-cmt-mmcm 29_384 -CMT_TOP_R_LOWER_B.MMCME2.LOCKREG1_RESERVED[0] origin:031-cmt-mmcm 29_826 -CMT_TOP_R_LOWER_B.MMCME2.LOCKREG1_RESERVED[1] origin:031-cmt-mmcm 28_826 -CMT_TOP_R_LOWER_B.MMCME2.LOCKREG1_RESERVED[2] origin:031-cmt-mmcm 29_825 -CMT_TOP_R_LOWER_B.MMCME2.LOCKREG1_RESERVED[3] origin:031-cmt-mmcm 28_825 -CMT_TOP_R_LOWER_B.MMCME2.LOCKREG1_RESERVED[4] origin:031-cmt-mmcm 29_824 -CMT_TOP_R_LOWER_B.MMCME2.LOCKREG1_RESERVED[5] origin:031-cmt-mmcm 28_824 -CMT_TOP_R_LOWER_B.MMCME2.LOCKREG2_RESERVED[0] origin:031-cmt-mmcm 28_816 -CMT_TOP_R_LOWER_B.MMCME2.LOCKREG3_RESERVED[0] origin:031-cmt-mmcm 28_808 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_860 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_860 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_859 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_859 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_858 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_858 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_863 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_863 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_862 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_862 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_861 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_861 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_857 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_857 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_856 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_856 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_855 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_855 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_854 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_854 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_853 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_853 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_852 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_849 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_849 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_848 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_850 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_850 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_851 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_851 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_852 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_848 +CMT_TOP_R_LOWER_B.MMCME2_ADV.COMP.Z_ZHOLD origin:031-cmt-mmcm 28_1020 28_979 +CMT_TOP_R_LOWER_B.MMCME2_ADV.COMP.ZHOLD origin:031-cmt-mmcm 28_1019 29_982 +CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_EDGE[0] origin:031-cmt-mmcm 28_841 +CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_HIGH_TIME[0] origin:031-cmt-mmcm 29_844 +CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_HIGH_TIME[1] origin:031-cmt-mmcm 28_844 +CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_HIGH_TIME[2] origin:031-cmt-mmcm 29_843 +CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_HIGH_TIME[3] origin:031-cmt-mmcm 28_843 +CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_HIGH_TIME[4] origin:031-cmt-mmcm 29_842 +CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_HIGH_TIME[5] origin:031-cmt-mmcm 28_842 +CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_LOW_TIME[0] origin:031-cmt-mmcm 29_847 +CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_LOW_TIME[1] origin:031-cmt-mmcm 28_847 +CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_LOW_TIME[2] origin:031-cmt-mmcm 29_846 +CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_LOW_TIME[3] origin:031-cmt-mmcm 28_846 +CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_LOW_TIME[4] origin:031-cmt-mmcm 29_845 +CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_LOW_TIME[5] origin:031-cmt-mmcm 28_845 +CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_NO_COUNT[0] origin:031-cmt-mmcm 29_841 +CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_RESERVED[0] origin:031-cmt-mmcm 29_840 +CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_RESERVED[1] origin:031-cmt-mmcm 28_840 +CMT_TOP_R_LOWER_B.MMCME2_ADV.IN_USE origin:031-cmt-mmcm 28_1007 28_18 28_21 28_22 28_23 28_24 28_25 28_27 28_28 28_31 28_32 28_33 28_34 28_36 28_37 28_38 28_39 28_40 28_428 28_429 28_430 28_433 28_434 28_44 28_46 28_466 28_47 28_48 28_488 28_49 28_492 28_50 28_51 28_52 28_54 28_63 28_65 28_66 28_70 28_72 28_73 28_75 28_77 28_772 28_773 28_774 28_78 28_787 28_976 28_978 28_989 28_991 29_1007 29_1018 29_16 29_18 29_22 29_25 29_28 29_31 29_34 29_35 29_36 29_37 29_39 29_40 29_41 29_42 29_427 29_428 29_431 29_432 29_433 29_44 29_45 29_46 29_463 29_47 29_48 29_51 29_52 29_56 29_57 29_60 29_64 29_65 29_66 29_67 29_68 29_70 29_71 29_72 29_73 29_75 29_76 29_77 29_771 29_772 29_775 29_78 29_789 29_833 29_836 29_839 29_95 29_977 29_981 29_987 29_990 29_991 +CMT_TOP_R_LOWER_B.MMCME2_ADV.INV_CLKINSEL origin:031-cmt-mmcm 29_109 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[0] origin:031-cmt-mmcm 29_823 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[1] origin:031-cmt-mmcm 28_823 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[2] origin:031-cmt-mmcm 29_822 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[3] origin:031-cmt-mmcm 28_822 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[4] origin:031-cmt-mmcm 29_821 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[5] origin:031-cmt-mmcm 28_821 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[6] origin:031-cmt-mmcm 29_820 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[7] origin:031-cmt-mmcm 28_820 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[8] origin:031-cmt-mmcm 29_819 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[9] origin:031-cmt-mmcm 28_819 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[10] origin:031-cmt-mmcm 29_815 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[11] origin:031-cmt-mmcm 28_815 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[12] origin:031-cmt-mmcm 29_814 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[13] origin:031-cmt-mmcm 28_814 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[14] origin:031-cmt-mmcm 29_813 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[15] origin:031-cmt-mmcm 28_813 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[16] origin:031-cmt-mmcm 29_812 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[17] origin:031-cmt-mmcm 28_812 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[18] origin:031-cmt-mmcm 29_811 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[19] origin:031-cmt-mmcm 28_811 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[20] origin:031-cmt-mmcm 29_831 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[21] origin:031-cmt-mmcm 28_831 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[22] origin:031-cmt-mmcm 29_830 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[23] origin:031-cmt-mmcm 28_830 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[24] origin:031-cmt-mmcm 29_829 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[25] origin:031-cmt-mmcm 28_829 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[26] origin:031-cmt-mmcm 29_828 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[27] origin:031-cmt-mmcm 28_828 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[28] origin:031-cmt-mmcm 29_827 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[29] origin:031-cmt-mmcm 28_827 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[30] origin:031-cmt-mmcm 29_818 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[31] origin:031-cmt-mmcm 28_818 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[32] origin:031-cmt-mmcm 29_817 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[33] origin:031-cmt-mmcm 28_817 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[34] origin:031-cmt-mmcm 29_816 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[35] origin:031-cmt-mmcm 29_810 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[36] origin:031-cmt-mmcm 28_810 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[37] origin:031-cmt-mmcm 29_809 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[38] origin:031-cmt-mmcm 28_809 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[39] origin:031-cmt-mmcm 29_808 +CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[0] origin:031-cmt-mmcm 29_703 +CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[1] origin:031-cmt-mmcm 28_703 +CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[2] origin:031-cmt-mmcm 29_702 +CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[3] origin:031-cmt-mmcm 28_702 +CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[4] origin:031-cmt-mmcm 29_701 +CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[5] origin:031-cmt-mmcm 28_701 +CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[6] origin:031-cmt-mmcm 29_700 +CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[7] origin:031-cmt-mmcm 28_700 +CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[8] origin:031-cmt-mmcm 29_699 +CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[9] origin:031-cmt-mmcm 28_699 +CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[10] origin:031-cmt-mmcm 29_698 +CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[11] origin:031-cmt-mmcm 28_698 +CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[12] origin:031-cmt-mmcm 29_697 +CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[13] origin:031-cmt-mmcm 28_697 +CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[14] origin:031-cmt-mmcm 29_696 +CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[15] origin:031-cmt-mmcm 28_696 +CMT_TOP_R_LOWER_B.MMCME2_ADV.SS_EN origin:031-cmt-mmcm 28_388 28_696 28_698 28_700 28_702 28_850 28_915 28_95 29_389 29_697 29_701 29_703 +CMT_TOP_R_LOWER_B.MMCME2_ADV.STARTUP_WAIT origin:031-cmt-mmcm 29_94 +CMT_TOP_R_LOWER_B.MMCME2_ADV.TABLE[0] origin:031-cmt-mmcm 29_389 +CMT_TOP_R_LOWER_B.MMCME2_ADV.TABLE[1] origin:031-cmt-mmcm 28_388 +CMT_TOP_R_LOWER_B.MMCME2_ADV.TABLE[2] origin:031-cmt-mmcm 29_387 +CMT_TOP_R_LOWER_B.MMCME2_ADV.TABLE[3] origin:031-cmt-mmcm 28_386 +CMT_TOP_R_LOWER_B.MMCME2_ADV.TABLE[4] origin:031-cmt-mmcm 29_385 +CMT_TOP_R_LOWER_B.MMCME2_ADV.TABLE[5] origin:031-cmt-mmcm 28_384 +CMT_TOP_R_LOWER_B.MMCME2_ADV.TABLE[6] origin:031-cmt-mmcm 29_395 +CMT_TOP_R_LOWER_B.MMCME2_ADV.TABLE[7] origin:031-cmt-mmcm 28_394 +CMT_TOP_R_LOWER_B.MMCME2_ADV.TABLE[8] origin:031-cmt-mmcm 29_393 +CMT_TOP_R_LOWER_B.MMCME2_ADV.TABLE[9] origin:031-cmt-mmcm 28_392 +CMT_TOP_R_LOWER_B.MMCME2_ADV.ZINV_PSEN origin:031-cmt-mmcm 28_110 +CMT_TOP_R_LOWER_B.MMCME2_ADV.ZINV_PSINCDEC origin:031-cmt-mmcm 29_110 +CMT_TOP_R_LOWER_B.MMCME2_ADV.ZINV_PWRDWN origin:031-cmt-mmcm 28_111 +CMT_TOP_R_LOWER_B.MMCME2_ADV.ZINV_RST origin:031-cmt-mmcm 29_111 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_956 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_956 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_955 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_955 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_954 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_954 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_959 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_959 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_958 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_958 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_957 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_957 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_953 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_953 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_952 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_952 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_951 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_951 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_950 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_950 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_949 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_949 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_948 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_945 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_945 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_944 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_946 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_946 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_947 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_947 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_948 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_944 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_940 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_940 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_939 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_939 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_938 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_938 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_943 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_943 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_942 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_942 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_941 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_941 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_937 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_937 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_936 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_936 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_935 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_935 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_934 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_934 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_933 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_933 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_932 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_929 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_929 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_928 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_930 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_930 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_931 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_931 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_932 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_928 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_924 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_924 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_923 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_923 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_922 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_922 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_927 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_927 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_926 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_926 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_925 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_925 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_921 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_921 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_920 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_920 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_919 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_919 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_918 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_918 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_917 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_917 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_916 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_913 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_913 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_912 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_914 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_914 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_915 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_915 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_916 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_912 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_908 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_908 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_907 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_907 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_906 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_906 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_911 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_911 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_910 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_910 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_909 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_909 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_905 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_905 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_904 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_904 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_903 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_903 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_902 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_902 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_901 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_901 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_900 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_897 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_897 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_896 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_898 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_898 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_899 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_899 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_900 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_896 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_892 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_892 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_891 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_891 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_890 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_890 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_895 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_895 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_894 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_894 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_893 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_893 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_889 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_889 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_888 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_888 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_887 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_887 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_886 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_886 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_885 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_885 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_884 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_881 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_881 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_880 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_882 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_882 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_883 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_883 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_884 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_880 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_972 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_972 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_971 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_971 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_970 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_970 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_975 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_975 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_974 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_974 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_973 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_973 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_969 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_969 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_968 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_968 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[0] origin:031-cmt-mmcm 29_967 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[1] origin:031-cmt-mmcm 28_967 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[2] origin:031-cmt-mmcm 29_966 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[3] origin:031-cmt-mmcm 28_966 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[4] origin:031-cmt-mmcm 29_965 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[5] origin:031-cmt-mmcm 28_965 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_EDGE[0] origin:031-cmt-mmcm 28_964 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_FRAC_WF_F[0] origin:031-cmt-mmcm 29_962 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_MX[0] origin:031-cmt-mmcm 29_963 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_MX[1] origin:031-cmt-mmcm 28_963 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_NO_COUNT[0] origin:031-cmt-mmcm 29_964 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[0] origin:031-cmt-mmcm 28_962 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[1] origin:031-cmt-mmcm 29_961 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[2] origin:031-cmt-mmcm 28_961 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_RESERVED[0] origin:031-cmt-mmcm 29_960 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_RESERVED[1] origin:031-cmt-mmcm 28_960 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_876 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_876 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_875 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_875 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_874 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_874 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_879 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_879 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_878 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_878 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_877 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_877 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_873 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_873 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_872 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_872 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[0] origin:031-cmt-mmcm 29_871 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[1] origin:031-cmt-mmcm 28_871 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[2] origin:031-cmt-mmcm 29_870 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[3] origin:031-cmt-mmcm 28_870 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[4] origin:031-cmt-mmcm 29_869 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[5] origin:031-cmt-mmcm 28_869 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_EDGE[0] origin:031-cmt-mmcm 28_868 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_FRAC_WF_F[0] origin:031-cmt-mmcm 29_866 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_MX[0] origin:031-cmt-mmcm 29_867 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_MX[1] origin:031-cmt-mmcm 28_867 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_NO_COUNT[0] origin:031-cmt-mmcm 29_868 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[0] origin:031-cmt-mmcm 28_866 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[1] origin:031-cmt-mmcm 29_865 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[2] origin:031-cmt-mmcm 28_865 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_RESERVED[0] origin:031-cmt-mmcm 29_864 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_RESERVED[1] origin:031-cmt-mmcm 28_864 +CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[0] origin:031-cmt-mmcm 29_399 +CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[1] origin:031-cmt-mmcm 28_399 +CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[2] origin:031-cmt-mmcm 29_398 +CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[3] origin:031-cmt-mmcm 28_398 +CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[4] origin:031-cmt-mmcm 29_397 +CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[5] origin:031-cmt-mmcm 28_397 +CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[6] origin:031-cmt-mmcm 29_396 +CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[7] origin:031-cmt-mmcm 28_396 +CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[8] origin:031-cmt-mmcm 28_395 +CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[9] origin:031-cmt-mmcm 29_394 +CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[10] origin:031-cmt-mmcm 28_393 +CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[11] origin:031-cmt-mmcm 29_392 +CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[0] origin:031-cmt-mmcm 29_391 +CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[1] origin:031-cmt-mmcm 28_391 +CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[2] origin:031-cmt-mmcm 29_390 +CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[3] origin:031-cmt-mmcm 28_390 +CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[4] origin:031-cmt-mmcm 28_389 +CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[5] origin:031-cmt-mmcm 29_388 +CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[6] origin:031-cmt-mmcm 28_387 +CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[7] origin:031-cmt-mmcm 29_386 +CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[8] origin:031-cmt-mmcm 28_385 +CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[9] origin:031-cmt-mmcm 29_384 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LOCKREG1_RESERVED[0] origin:031-cmt-mmcm 29_826 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LOCKREG1_RESERVED[1] origin:031-cmt-mmcm 28_826 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LOCKREG1_RESERVED[2] origin:031-cmt-mmcm 29_825 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LOCKREG1_RESERVED[3] origin:031-cmt-mmcm 28_825 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LOCKREG1_RESERVED[4] origin:031-cmt-mmcm 29_824 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LOCKREG1_RESERVED[5] origin:031-cmt-mmcm 28_824 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LOCKREG2_RESERVED[0] origin:031-cmt-mmcm 28_816 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LOCKREG3_RESERVED[0] origin:031-cmt-mmcm 28_808 diff --git a/artix7/segbits_cmt_top_r_upper_t.db b/artix7/segbits_cmt_top_r_upper_t.db index 0f8bc38..1e6ceaa 100644 --- a/artix7/segbits_cmt_top_r_upper_t.db +++ b/artix7/segbits_cmt_top_r_upper_t.db @@ -21,348 +21,348 @@ CMT_TOP_R_UPPER_T.PLL_CLK_FREQ_BB0_NS_ACTIVE 29_00 29_09 29_17 CMT_TOP_R_UPPER_T.PLL_CLK_FREQ_BB1_NS_ACTIVE 28_01 29_10 29_18 CMT_TOP_R_UPPER_T.PLL_CLK_FREQ_BB2_NS_ACTIVE 29_01 29_11 29_19 CMT_TOP_R_UPPER_T.PLL_CLK_FREQ_BB3_NS_ACTIVE 28_02 29_12 29_20 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[0] 28_195 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[1] 29_195 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[2] 28_196 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[3] 29_196 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[4] 28_197 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[5] 29_197 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[0] 28_192 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[1] 29_192 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[2] 28_193 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[3] 29_193 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[4] 28_194 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[5] 29_194 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE[0] 28_198 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[0] 29_198 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[1] 28_199 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[2] 29_199 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[0] 28_200 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[1] 29_200 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[2] 28_201 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[3] 29_201 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[4] 28_202 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[5] 29_202 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_EDGE[0] 29_203 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[0] 28_206 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[1] 29_206 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[2] 28_207 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC_EN[0] 29_205 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC_WF_R[0] 28_205 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_MX[0] 28_204 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_MX[1] 29_204 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_NO_COUNT[0] 28_203 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_RESERVED[0] 29_207 -CMT_TOP_R_UPPER_T.PLLE2.COMP.ZHOLD_NO_CLKIN_BUF_TOP 28_38 -CMT_TOP_R_UPPER_T.PLLE2.COMPENSATION.Z_ZHOLD_OR_CLKIN_BUF 29_35 29_76 -CMT_TOP_R_UPPER_T.PLLE2.COMPENSATION.ZHOLD_NO_CLKIN_BUF 28_73 29_36 -CMT_TOP_R_UPPER_T.PLLE2.COMPENSATION.ZHOLD_NO_CLKIN_BUF_NO_TOP 29_38 -CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_EDGE[0] 29_214 -CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[0] 28_211 -CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[1] 29_211 -CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[2] 28_212 -CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[3] 29_212 -CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[4] 28_213 -CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[5] 29_213 -CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[0] 28_208 -CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[1] 29_208 -CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[2] 28_209 -CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[3] 29_209 -CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[4] 28_210 -CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[5] 29_210 -CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_NO_COUNT[0] 28_214 -CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_RESERVED[0] 28_215 -CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_RESERVED[1] 29_215 -CMT_TOP_R_UPPER_T.PLLE2.IN_USE 28_37 28_48 28_74 28_78 28_216 28_219 28_222 28_266 28_280 28_283 28_284 28_592 28_622 28_623 28_624 28_627 28_628 28_768 28_785 28_786 28_787 28_788 28_790 28_791 28_792 28_793 28_795 28_796 28_797 28_798 28_799 28_803 28_806 28_807 28_811 28_812 28_815 28_816 28_817 28_818 28_819 28_821 28_822 28_823 28_824 28_826 28_827 28_828 28_829 28_832 28_835 28_838 28_841 28_845 28_847 29_48 29_77 29_78 29_79 29_268 29_281 29_282 29_283 29_563 29_567 29_589 29_621 29_622 29_625 29_626 29_627 29_785 29_786 29_788 29_790 29_791 29_793 29_797 29_798 29_800 29_809 29_811 29_812 29_813 29_814 29_815 29_816 29_817 29_819 29_823 29_824 29_825 29_826 29_827 29_829 29_830 29_831 29_832 29_835 29_836 29_838 29_839 29_840 29_841 29_842 29_845 -CMT_TOP_R_UPPER_T.PLLE2.INV_CLKINSEL 28_754 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[0] 28_232 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[1] 29_232 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[2] 28_233 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[3] 29_233 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[4] 28_234 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[5] 29_234 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[6] 28_235 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[7] 29_235 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[8] 28_236 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[9] 29_236 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[10] 28_240 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[11] 29_240 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[12] 28_241 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[13] 29_241 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[14] 28_242 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[15] 29_242 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[16] 28_243 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[17] 29_243 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[18] 28_244 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[19] 29_244 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[20] 28_224 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[21] 29_224 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[22] 28_225 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[23] 29_225 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[24] 28_226 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[25] 29_226 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[26] 28_227 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[27] 29_227 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[28] 28_228 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[29] 29_228 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[30] 28_237 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[31] 29_237 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[32] 28_238 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[33] 29_238 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[34] 28_239 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[35] 28_245 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[36] 29_245 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[37] 28_246 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[38] 29_246 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[39] 28_247 -CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[0] 28_352 -CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[1] 29_352 -CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[2] 28_353 -CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[3] 29_353 -CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[4] 28_354 -CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[5] 29_354 -CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[6] 28_355 -CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[7] 29_355 -CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[8] 28_356 -CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[9] 29_356 -CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[10] 28_357 -CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[11] 29_357 -CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[12] 28_358 -CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[13] 29_358 -CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[14] 28_359 -CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[15] 29_359 -CMT_TOP_R_UPPER_T.PLLE2.STARTUP_WAIT 28_769 -CMT_TOP_R_UPPER_T.PLLE2.TABLE[0] 28_666 -CMT_TOP_R_UPPER_T.PLLE2.TABLE[1] 29_667 -CMT_TOP_R_UPPER_T.PLLE2.TABLE[2] 28_668 -CMT_TOP_R_UPPER_T.PLLE2.TABLE[3] 29_669 -CMT_TOP_R_UPPER_T.PLLE2.TABLE[4] 28_670 -CMT_TOP_R_UPPER_T.PLLE2.TABLE[5] 29_671 -CMT_TOP_R_UPPER_T.PLLE2.TABLE[6] 28_660 -CMT_TOP_R_UPPER_T.PLLE2.TABLE[7] 29_661 -CMT_TOP_R_UPPER_T.PLLE2.TABLE[8] 28_662 -CMT_TOP_R_UPPER_T.PLLE2.TABLE[9] 29_663 -CMT_TOP_R_UPPER_T.PLLE2.ZINV_PWRDWN 29_752 -CMT_TOP_R_UPPER_T.PLLE2.ZINV_RST 28_752 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[0] 28_99 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[1] 29_99 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[2] 28_100 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[3] 29_100 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[4] 28_101 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[5] 29_101 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[0] 28_96 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[1] 29_96 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[2] 28_97 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[3] 29_97 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[4] 28_98 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[5] 29_98 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_OUTPUT_ENABLE[0] 28_102 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[0] 29_102 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[1] 28_103 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[2] 29_103 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[0] 28_104 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[1] 29_104 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[2] 28_105 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[3] 29_105 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[4] 28_106 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[5] 29_106 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_EDGE[0] 29_107 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[0] 28_110 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[1] 29_110 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[2] 28_111 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC_EN[0] 29_109 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC_WF_R[0] 28_109 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_MX[0] 28_108 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_MX[1] 29_108 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_NO_COUNT[0] 28_107 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_RESERVED[0] 29_111 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[0] 28_115 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[1] 29_115 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[2] 28_116 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[3] 29_116 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[4] 28_117 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[5] 29_117 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[0] 28_112 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[1] 29_112 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[2] 28_113 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[3] 29_113 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[4] 28_114 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[5] 29_114 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_OUTPUT_ENABLE[0] 28_118 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[0] 29_118 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[1] 28_119 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[2] 29_119 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[0] 28_120 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[1] 29_120 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[2] 28_121 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[3] 29_121 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[4] 28_122 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[5] 29_122 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_EDGE[0] 29_123 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[0] 28_126 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[1] 29_126 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[2] 28_127 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC_EN[0] 29_125 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC_WF_R[0] 28_125 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_MX[0] 28_124 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_MX[1] 29_124 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_NO_COUNT[0] 28_123 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_RESERVED[0] 29_127 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[0] 28_131 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[1] 29_131 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[2] 28_132 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[3] 29_132 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[4] 28_133 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[5] 29_133 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[0] 28_128 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[1] 29_128 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[2] 28_129 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[3] 29_129 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[4] 28_130 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[5] 29_130 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_OUTPUT_ENABLE[0] 28_134 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[0] 29_134 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[1] 28_135 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[2] 29_135 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[0] 28_136 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[1] 29_136 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[2] 28_137 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[3] 29_137 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[4] 28_138 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[5] 29_138 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_EDGE[0] 29_139 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[0] 28_142 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[1] 29_142 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[2] 28_143 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC_EN[0] 29_141 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC_WF_R[0] 28_141 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_MX[0] 28_140 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_MX[1] 29_140 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_NO_COUNT[0] 28_139 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_RESERVED[0] 29_143 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[0] 28_147 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[1] 29_147 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[2] 28_148 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[3] 29_148 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[4] 28_149 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[5] 29_149 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[0] 28_144 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[1] 29_144 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[2] 28_145 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[3] 29_145 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[4] 28_146 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[5] 29_146 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_OUTPUT_ENABLE[0] 28_150 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[0] 29_150 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[1] 28_151 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[2] 29_151 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[0] 28_152 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[1] 29_152 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[2] 28_153 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[3] 29_153 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[4] 28_154 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[5] 29_154 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_EDGE[0] 29_155 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[0] 28_158 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[1] 29_158 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[2] 28_159 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC_EN[0] 29_157 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC_WF_R[0] 28_157 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_MX[0] 28_156 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_MX[1] 29_156 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_NO_COUNT[0] 28_155 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_RESERVED[0] 29_159 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[0] 28_163 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[1] 29_163 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[2] 28_164 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[3] 29_164 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[4] 28_165 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[5] 29_165 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[0] 28_160 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[1] 29_160 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[2] 28_161 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[3] 29_161 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[4] 28_162 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[5] 29_162 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_OUTPUT_ENABLE[0] 28_166 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[0] 29_166 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[1] 28_167 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[2] 29_167 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[0] 28_168 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[1] 29_168 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[2] 28_169 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[3] 29_169 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[4] 28_170 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[5] 29_170 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_EDGE[0] 29_171 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[0] 28_174 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[1] 29_174 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[2] 28_175 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC_EN[0] 29_173 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC_WF_R[0] 28_173 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_MX[0] 28_172 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_MX[1] 29_172 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_NO_COUNT[0] 28_171 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_RESERVED[0] 29_175 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[0] 28_83 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[1] 29_83 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[2] 28_84 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[3] 29_84 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[4] 28_85 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[5] 29_85 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[0] 28_80 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[1] 29_80 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[2] 28_81 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[3] 29_81 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[4] 28_82 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[5] 29_82 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_OUTPUT_ENABLE[0] 28_86 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[0] 29_86 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[1] 28_87 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[2] 29_87 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[0] 28_88 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[1] 29_88 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[2] 28_89 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[3] 29_89 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[4] 28_90 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[5] 29_90 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_EDGE[0] 29_91 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[0] 28_94 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[1] 29_94 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[2] 28_95 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC_EN[0] 29_93 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC_WF_R[0] 28_93 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_MX[0] 28_92 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_MX[1] 29_92 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_NO_COUNT[0] 28_91 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_RESERVED[0] 29_95 -CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[0] 28_656 -CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[1] 29_656 -CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[2] 28_657 -CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[3] 29_657 -CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[4] 28_658 -CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[5] 29_658 -CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[6] 28_659 -CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[7] 29_659 -CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[8] 29_660 -CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[9] 28_661 -CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[10] 29_662 -CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[11] 28_663 -CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[0] 28_664 -CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[1] 29_664 -CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[2] 28_665 -CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[3] 29_665 -CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[4] 29_666 -CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[5] 28_667 -CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[6] 29_668 -CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[7] 28_669 -CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[8] 29_670 -CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[9] 28_671 -CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[0] 28_229 -CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[1] 29_229 -CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[2] 28_230 -CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[3] 29_230 -CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[4] 28_231 -CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[5] 29_231 -CMT_TOP_R_UPPER_T.PLLE2.LOCKREG2_RESERVED[0] 29_239 -CMT_TOP_R_UPPER_T.PLLE2.LOCKREG3_RESERVED[0] 29_247 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[0] 28_195 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[1] 29_195 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[2] 28_196 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[3] 29_196 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[4] 28_197 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[5] 29_197 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[0] 28_192 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[1] 29_192 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[2] 28_193 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[3] 29_193 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[4] 28_194 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[5] 29_194 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE[0] 28_198 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_PHASE_MUX[0] 29_198 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_PHASE_MUX[1] 28_199 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_PHASE_MUX[2] 29_199 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[0] 28_200 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[1] 29_200 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[2] 28_201 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[3] 29_201 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[4] 28_202 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[5] 29_202 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_EDGE[0] 29_203 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_FRAC[0] 28_206 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_FRAC[1] 29_206 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_FRAC[2] 28_207 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_FRAC_EN[0] 29_205 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_FRAC_WF_R[0] 28_205 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_MX[0] 28_204 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_MX[1] 29_204 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_NO_COUNT[0] 28_203 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_RESERVED[0] 29_207 +CMT_TOP_R_UPPER_T.PLLE2_ADV.COMP.ZHOLD_NO_CLKIN_BUF_TOP 28_38 +CMT_TOP_R_UPPER_T.PLLE2_ADV.COMPENSATION.Z_ZHOLD_OR_CLKIN_BUF 29_35 29_76 +CMT_TOP_R_UPPER_T.PLLE2_ADV.COMPENSATION.ZHOLD_NO_CLKIN_BUF 28_73 29_36 +CMT_TOP_R_UPPER_T.PLLE2_ADV.COMPENSATION.ZHOLD_NO_CLKIN_BUF_NO_TOP 29_38 +CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_EDGE[0] 29_214 +CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_HIGH_TIME[0] 28_211 +CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_HIGH_TIME[1] 29_211 +CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_HIGH_TIME[2] 28_212 +CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_HIGH_TIME[3] 29_212 +CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_HIGH_TIME[4] 28_213 +CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_HIGH_TIME[5] 29_213 +CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_LOW_TIME[0] 28_208 +CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_LOW_TIME[1] 29_208 +CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_LOW_TIME[2] 28_209 +CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_LOW_TIME[3] 29_209 +CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_LOW_TIME[4] 28_210 +CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_LOW_TIME[5] 29_210 +CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_NO_COUNT[0] 28_214 +CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_RESERVED[0] 28_215 +CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_RESERVED[1] 29_215 +CMT_TOP_R_UPPER_T.PLLE2_ADV.IN_USE 28_37 28_48 28_74 28_78 28_216 28_219 28_222 28_266 28_280 28_283 28_284 28_592 28_622 28_623 28_624 28_627 28_628 28_768 28_785 28_786 28_787 28_788 28_790 28_791 28_792 28_793 28_795 28_796 28_797 28_798 28_799 28_803 28_806 28_807 28_811 28_812 28_815 28_816 28_817 28_818 28_819 28_821 28_822 28_823 28_824 28_826 28_827 28_828 28_829 28_832 28_835 28_838 28_841 28_845 28_847 29_48 29_77 29_78 29_79 29_268 29_281 29_282 29_283 29_563 29_567 29_589 29_621 29_622 29_625 29_626 29_627 29_785 29_786 29_788 29_790 29_791 29_793 29_797 29_798 29_800 29_809 29_811 29_812 29_813 29_814 29_815 29_816 29_817 29_819 29_823 29_824 29_825 29_826 29_827 29_829 29_830 29_831 29_832 29_835 29_836 29_838 29_839 29_840 29_841 29_842 29_845 +CMT_TOP_R_UPPER_T.PLLE2_ADV.INV_CLKINSEL 28_754 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[0] 28_232 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[1] 29_232 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[2] 28_233 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[3] 29_233 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[4] 28_234 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[5] 29_234 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[6] 28_235 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[7] 29_235 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[8] 28_236 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[9] 29_236 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[10] 28_240 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[11] 29_240 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[12] 28_241 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[13] 29_241 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[14] 28_242 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[15] 29_242 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[16] 28_243 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[17] 29_243 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[18] 28_244 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[19] 29_244 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[20] 28_224 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[21] 29_224 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[22] 28_225 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[23] 29_225 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[24] 28_226 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[25] 29_226 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[26] 28_227 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[27] 29_227 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[28] 28_228 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[29] 29_228 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[30] 28_237 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[31] 29_237 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[32] 28_238 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[33] 29_238 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[34] 28_239 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[35] 28_245 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[36] 29_245 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[37] 28_246 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[38] 29_246 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[39] 28_247 +CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[0] 28_352 +CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[1] 29_352 +CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[2] 28_353 +CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[3] 29_353 +CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[4] 28_354 +CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[5] 29_354 +CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[6] 28_355 +CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[7] 29_355 +CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[8] 28_356 +CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[9] 29_356 +CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[10] 28_357 +CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[11] 29_357 +CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[12] 28_358 +CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[13] 29_358 +CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[14] 28_359 +CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[15] 29_359 +CMT_TOP_R_UPPER_T.PLLE2_ADV.STARTUP_WAIT 28_769 +CMT_TOP_R_UPPER_T.PLLE2_ADV.TABLE[0] 28_666 +CMT_TOP_R_UPPER_T.PLLE2_ADV.TABLE[1] 29_667 +CMT_TOP_R_UPPER_T.PLLE2_ADV.TABLE[2] 28_668 +CMT_TOP_R_UPPER_T.PLLE2_ADV.TABLE[3] 29_669 +CMT_TOP_R_UPPER_T.PLLE2_ADV.TABLE[4] 28_670 +CMT_TOP_R_UPPER_T.PLLE2_ADV.TABLE[5] 29_671 +CMT_TOP_R_UPPER_T.PLLE2_ADV.TABLE[6] 28_660 +CMT_TOP_R_UPPER_T.PLLE2_ADV.TABLE[7] 29_661 +CMT_TOP_R_UPPER_T.PLLE2_ADV.TABLE[8] 28_662 +CMT_TOP_R_UPPER_T.PLLE2_ADV.TABLE[9] 29_663 +CMT_TOP_R_UPPER_T.PLLE2_ADV.ZINV_PWRDWN 29_752 +CMT_TOP_R_UPPER_T.PLLE2_ADV.ZINV_RST 28_752 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[0] 28_99 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[1] 29_99 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[2] 28_100 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[3] 29_100 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[4] 28_101 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[5] 29_101 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[0] 28_96 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[1] 29_96 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[2] 28_97 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[3] 29_97 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[4] 28_98 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[5] 29_98 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_OUTPUT_ENABLE[0] 28_102 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_PHASE_MUX[0] 29_102 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_PHASE_MUX[1] 28_103 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_PHASE_MUX[2] 29_103 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[0] 28_104 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[1] 29_104 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[2] 28_105 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[3] 29_105 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[4] 28_106 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[5] 29_106 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_EDGE[0] 29_107 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_FRAC[0] 28_110 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_FRAC[1] 29_110 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_FRAC[2] 28_111 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_FRAC_EN[0] 29_109 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_FRAC_WF_R[0] 28_109 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_MX[0] 28_108 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_MX[1] 29_108 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_NO_COUNT[0] 28_107 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_RESERVED[0] 29_111 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[0] 28_115 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[1] 29_115 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[2] 28_116 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[3] 29_116 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[4] 28_117 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[5] 29_117 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[0] 28_112 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[1] 29_112 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[2] 28_113 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[3] 29_113 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[4] 28_114 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[5] 29_114 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_OUTPUT_ENABLE[0] 28_118 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_PHASE_MUX[0] 29_118 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_PHASE_MUX[1] 28_119 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_PHASE_MUX[2] 29_119 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[0] 28_120 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[1] 29_120 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[2] 28_121 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[3] 29_121 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[4] 28_122 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[5] 29_122 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_EDGE[0] 29_123 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_FRAC[0] 28_126 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_FRAC[1] 29_126 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_FRAC[2] 28_127 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_FRAC_EN[0] 29_125 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_FRAC_WF_R[0] 28_125 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_MX[0] 28_124 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_MX[1] 29_124 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_NO_COUNT[0] 28_123 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_RESERVED[0] 29_127 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[0] 28_131 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[1] 29_131 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[2] 28_132 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[3] 29_132 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[4] 28_133 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[5] 29_133 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[0] 28_128 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[1] 29_128 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[2] 28_129 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[3] 29_129 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[4] 28_130 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[5] 29_130 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_OUTPUT_ENABLE[0] 28_134 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_PHASE_MUX[0] 29_134 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_PHASE_MUX[1] 28_135 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_PHASE_MUX[2] 29_135 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[0] 28_136 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[1] 29_136 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[2] 28_137 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[3] 29_137 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[4] 28_138 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[5] 29_138 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_EDGE[0] 29_139 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_FRAC[0] 28_142 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_FRAC[1] 29_142 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_FRAC[2] 28_143 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_FRAC_EN[0] 29_141 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_FRAC_WF_R[0] 28_141 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_MX[0] 28_140 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_MX[1] 29_140 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_NO_COUNT[0] 28_139 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_RESERVED[0] 29_143 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[0] 28_147 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[1] 29_147 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[2] 28_148 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[3] 29_148 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[4] 28_149 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[5] 29_149 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[0] 28_144 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[1] 29_144 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[2] 28_145 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[3] 29_145 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[4] 28_146 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[5] 29_146 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_OUTPUT_ENABLE[0] 28_150 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_PHASE_MUX[0] 29_150 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_PHASE_MUX[1] 28_151 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_PHASE_MUX[2] 29_151 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[0] 28_152 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[1] 29_152 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[2] 28_153 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[3] 29_153 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[4] 28_154 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[5] 29_154 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_EDGE[0] 29_155 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_FRAC[0] 28_158 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_FRAC[1] 29_158 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_FRAC[2] 28_159 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_FRAC_EN[0] 29_157 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_FRAC_WF_R[0] 28_157 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_MX[0] 28_156 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_MX[1] 29_156 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_NO_COUNT[0] 28_155 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_RESERVED[0] 29_159 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[0] 28_163 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[1] 29_163 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[2] 28_164 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[3] 29_164 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[4] 28_165 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[5] 29_165 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[0] 28_160 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[1] 29_160 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[2] 28_161 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[3] 29_161 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[4] 28_162 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[5] 29_162 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_OUTPUT_ENABLE[0] 28_166 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_PHASE_MUX[0] 29_166 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_PHASE_MUX[1] 28_167 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_PHASE_MUX[2] 29_167 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[0] 28_168 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[1] 29_168 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[2] 28_169 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[3] 29_169 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[4] 28_170 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[5] 29_170 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_EDGE[0] 29_171 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_FRAC[0] 28_174 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_FRAC[1] 29_174 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_FRAC[2] 28_175 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_FRAC_EN[0] 29_173 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_FRAC_WF_R[0] 28_173 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_MX[0] 28_172 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_MX[1] 29_172 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_NO_COUNT[0] 28_171 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_RESERVED[0] 29_175 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[0] 28_83 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[1] 29_83 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[2] 28_84 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[3] 29_84 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[4] 28_85 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[5] 29_85 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[0] 28_80 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[1] 29_80 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[2] 28_81 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[3] 29_81 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[4] 28_82 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[5] 29_82 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_OUTPUT_ENABLE[0] 28_86 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_PHASE_MUX[0] 29_86 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_PHASE_MUX[1] 28_87 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_PHASE_MUX[2] 29_87 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_DELAY_TIME[0] 28_88 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_DELAY_TIME[1] 29_88 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_DELAY_TIME[2] 28_89 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_DELAY_TIME[3] 29_89 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_DELAY_TIME[4] 28_90 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_DELAY_TIME[5] 29_90 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_EDGE[0] 29_91 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_FRAC[0] 28_94 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_FRAC[1] 29_94 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_FRAC[2] 28_95 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_FRAC_EN[0] 29_93 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_FRAC_WF_R[0] 28_93 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_MX[0] 28_92 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_MX[1] 29_92 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_NO_COUNT[0] 28_91 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_RESERVED[0] 29_95 +CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[0] 28_656 +CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[1] 29_656 +CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[2] 28_657 +CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[3] 29_657 +CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[4] 28_658 +CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[5] 29_658 +CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[6] 28_659 +CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[7] 29_659 +CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[8] 29_660 +CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[9] 28_661 +CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[10] 29_662 +CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[11] 28_663 +CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[0] 28_664 +CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[1] 29_664 +CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[2] 28_665 +CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[3] 29_665 +CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[4] 29_666 +CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[5] 28_667 +CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[6] 29_668 +CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[7] 28_669 +CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[8] 29_670 +CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[9] 28_671 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LOCKREG1_RESERVED[0] 28_229 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LOCKREG1_RESERVED[1] 29_229 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LOCKREG1_RESERVED[2] 28_230 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LOCKREG1_RESERVED[3] 29_230 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LOCKREG1_RESERVED[4] 28_231 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LOCKREG1_RESERVED[5] 29_231 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LOCKREG2_RESERVED[0] 29_239 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LOCKREG3_RESERVED[0] 29_247 diff --git a/artix7/segbits_cmt_top_r_upper_t.origin_info.db b/artix7/segbits_cmt_top_r_upper_t.origin_info.db index 9afcdc3..4b0df8c 100644 --- a/artix7/segbits_cmt_top_r_upper_t.origin_info.db +++ b/artix7/segbits_cmt_top_r_upper_t.origin_info.db @@ -21,348 +21,348 @@ CMT_TOP_R_UPPER_T.PLL_CLK_FREQ_BB0_NS_ACTIVE origin:034-cmt-pll-pips 29_00 29_09 CMT_TOP_R_UPPER_T.PLL_CLK_FREQ_BB1_NS_ACTIVE origin:034-cmt-pll-pips 28_01 29_10 29_18 CMT_TOP_R_UPPER_T.PLL_CLK_FREQ_BB2_NS_ACTIVE origin:034-cmt-pll-pips 29_01 29_11 29_19 CMT_TOP_R_UPPER_T.PLL_CLK_FREQ_BB3_NS_ACTIVE origin:034-cmt-pll-pips 28_02 29_12 29_20 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_195 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_195 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_196 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_196 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_197 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_197 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_192 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_192 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_193 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_193 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_194 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_194 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_198 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_198 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_199 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_199 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_200 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_200 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_201 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_201 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_202 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_202 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_203 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_206 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_206 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_207 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_205 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_205 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_MX[0] origin:032-cmt-pll 28_204 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_MX[1] origin:032-cmt-pll 29_204 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_203 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_207 -CMT_TOP_R_UPPER_T.PLLE2.COMP.ZHOLD_NO_CLKIN_BUF_TOP origin:032-cmt-pll 28_38 -CMT_TOP_R_UPPER_T.PLLE2.COMPENSATION.Z_ZHOLD_OR_CLKIN_BUF origin:032-cmt-pll 29_35 29_76 -CMT_TOP_R_UPPER_T.PLLE2.COMPENSATION.ZHOLD_NO_CLKIN_BUF origin:032-cmt-pll 28_73 29_36 -CMT_TOP_R_UPPER_T.PLLE2.COMPENSATION.ZHOLD_NO_CLKIN_BUF_NO_TOP origin:032-cmt-pll 29_38 -CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_EDGE[0] origin:032-cmt-pll 29_214 -CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[0] origin:032-cmt-pll 28_211 -CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[1] origin:032-cmt-pll 29_211 -CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[2] origin:032-cmt-pll 28_212 -CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[3] origin:032-cmt-pll 29_212 -CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[4] origin:032-cmt-pll 28_213 -CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[5] origin:032-cmt-pll 29_213 -CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[0] origin:032-cmt-pll 28_208 -CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[1] origin:032-cmt-pll 29_208 -CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[2] origin:032-cmt-pll 28_209 -CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[3] origin:032-cmt-pll 29_209 -CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[4] origin:032-cmt-pll 28_210 -CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[5] origin:032-cmt-pll 29_210 -CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_NO_COUNT[0] origin:032-cmt-pll 28_214 -CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_RESERVED[0] origin:032-cmt-pll 28_215 -CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_RESERVED[1] origin:032-cmt-pll 29_215 -CMT_TOP_R_UPPER_T.PLLE2.IN_USE origin:032-cmt-pll 28_216 28_219 28_222 28_266 28_280 28_283 28_284 28_37 28_48 28_592 28_622 28_623 28_624 28_627 28_628 28_74 28_768 28_78 28_785 28_786 28_787 28_788 28_790 28_791 28_792 28_793 28_795 28_796 28_797 28_798 28_799 28_803 28_806 28_807 28_811 28_812 28_815 28_816 28_817 28_818 28_819 28_821 28_822 28_823 28_824 28_826 28_827 28_828 28_829 28_832 28_835 28_838 28_841 28_845 28_847 29_268 29_281 29_282 29_283 29_48 29_563 29_567 29_589 29_621 29_622 29_625 29_626 29_627 29_77 29_78 29_785 29_786 29_788 29_79 29_790 29_791 29_793 29_797 29_798 29_800 29_809 29_811 29_812 29_813 29_814 29_815 29_816 29_817 29_819 29_823 29_824 29_825 29_826 29_827 29_829 29_830 29_831 29_832 29_835 29_836 29_838 29_839 29_840 29_841 29_842 29_845 -CMT_TOP_R_UPPER_T.PLLE2.INV_CLKINSEL origin:032-cmt-pll 28_754 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[0] origin:032-cmt-pll 28_232 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[1] origin:032-cmt-pll 29_232 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[2] origin:032-cmt-pll 28_233 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[3] origin:032-cmt-pll 29_233 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[4] origin:032-cmt-pll 28_234 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[5] origin:032-cmt-pll 29_234 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[6] origin:032-cmt-pll 28_235 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[7] origin:032-cmt-pll 29_235 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[8] origin:032-cmt-pll 28_236 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[9] origin:032-cmt-pll 29_236 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[10] origin:032-cmt-pll 28_240 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[11] origin:032-cmt-pll 29_240 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[12] origin:032-cmt-pll 28_241 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[13] origin:032-cmt-pll 29_241 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[14] origin:032-cmt-pll 28_242 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[15] origin:032-cmt-pll 29_242 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[16] origin:032-cmt-pll 28_243 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[17] origin:032-cmt-pll 29_243 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[18] origin:032-cmt-pll 28_244 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[19] origin:032-cmt-pll 29_244 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[20] origin:032-cmt-pll 28_224 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[21] origin:032-cmt-pll 29_224 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[22] origin:032-cmt-pll 28_225 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[23] origin:032-cmt-pll 29_225 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[24] origin:032-cmt-pll 28_226 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[25] origin:032-cmt-pll 29_226 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[26] origin:032-cmt-pll 28_227 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[27] origin:032-cmt-pll 29_227 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[28] origin:032-cmt-pll 28_228 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[29] origin:032-cmt-pll 29_228 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[30] origin:032-cmt-pll 28_237 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[31] origin:032-cmt-pll 29_237 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[32] origin:032-cmt-pll 28_238 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[33] origin:032-cmt-pll 29_238 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[34] origin:032-cmt-pll 28_239 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[35] origin:032-cmt-pll 28_245 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[36] origin:032-cmt-pll 29_245 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[37] origin:032-cmt-pll 28_246 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[38] origin:032-cmt-pll 29_246 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[39] origin:032-cmt-pll 28_247 -CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[0] origin:032-cmt-pll 28_352 -CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[1] origin:032-cmt-pll 29_352 -CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[2] origin:032-cmt-pll 28_353 -CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[3] origin:032-cmt-pll 29_353 -CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[4] origin:032-cmt-pll 28_354 -CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[5] origin:032-cmt-pll 29_354 -CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[6] origin:032-cmt-pll 28_355 -CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[7] origin:032-cmt-pll 29_355 -CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[8] origin:032-cmt-pll 28_356 -CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[9] origin:032-cmt-pll 29_356 -CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[10] origin:032-cmt-pll 28_357 -CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[11] origin:032-cmt-pll 29_357 -CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[12] origin:032-cmt-pll 28_358 -CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[13] origin:032-cmt-pll 29_358 -CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[14] origin:032-cmt-pll 28_359 -CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[15] origin:032-cmt-pll 29_359 -CMT_TOP_R_UPPER_T.PLLE2.STARTUP_WAIT origin:032-cmt-pll 28_769 -CMT_TOP_R_UPPER_T.PLLE2.TABLE[0] origin:032-cmt-pll 28_666 -CMT_TOP_R_UPPER_T.PLLE2.TABLE[1] origin:032-cmt-pll 29_667 -CMT_TOP_R_UPPER_T.PLLE2.TABLE[2] origin:032-cmt-pll 28_668 -CMT_TOP_R_UPPER_T.PLLE2.TABLE[3] origin:032-cmt-pll 29_669 -CMT_TOP_R_UPPER_T.PLLE2.TABLE[4] origin:032-cmt-pll 28_670 -CMT_TOP_R_UPPER_T.PLLE2.TABLE[5] origin:032-cmt-pll 29_671 -CMT_TOP_R_UPPER_T.PLLE2.TABLE[6] origin:032-cmt-pll 28_660 -CMT_TOP_R_UPPER_T.PLLE2.TABLE[7] origin:032-cmt-pll 29_661 -CMT_TOP_R_UPPER_T.PLLE2.TABLE[8] origin:032-cmt-pll 28_662 -CMT_TOP_R_UPPER_T.PLLE2.TABLE[9] origin:032-cmt-pll 29_663 -CMT_TOP_R_UPPER_T.PLLE2.ZINV_PWRDWN origin:032-cmt-pll 29_752 -CMT_TOP_R_UPPER_T.PLLE2.ZINV_RST origin:032-cmt-pll 28_752 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_99 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_99 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_100 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_100 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_101 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_101 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_96 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_96 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_97 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_97 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_98 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_98 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_102 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_102 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_103 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_103 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_104 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_104 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_105 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_105 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_106 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_106 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_107 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_110 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_110 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_111 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_109 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_109 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_MX[0] origin:032-cmt-pll 28_108 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_MX[1] origin:032-cmt-pll 29_108 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_107 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_111 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_115 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_115 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_116 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_116 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_117 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_117 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_112 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_112 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_113 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_113 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_114 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_114 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_118 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_118 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_119 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_119 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_120 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_120 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_121 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_121 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_122 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_122 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_123 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_126 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_126 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_127 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_125 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_125 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_MX[0] origin:032-cmt-pll 28_124 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_MX[1] origin:032-cmt-pll 29_124 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_123 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_127 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_131 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_131 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_132 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_132 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_133 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_133 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_128 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_128 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_129 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_129 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_130 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_130 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_134 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_134 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_135 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_135 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_136 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_136 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_137 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_137 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_138 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_138 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_139 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_142 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_142 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_143 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_141 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_141 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_MX[0] origin:032-cmt-pll 28_140 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_MX[1] origin:032-cmt-pll 29_140 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_139 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_143 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_147 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_147 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_148 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_148 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_149 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_149 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_144 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_144 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_145 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_145 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_146 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_146 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_150 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_150 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_151 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_151 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_152 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_152 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_153 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_153 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_154 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_154 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_155 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_158 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_158 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_159 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_157 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_157 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_MX[0] origin:032-cmt-pll 28_156 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_MX[1] origin:032-cmt-pll 29_156 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_155 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_159 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_163 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_163 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_164 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_164 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_165 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_165 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_160 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_160 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_161 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_161 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_162 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_162 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_166 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_166 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_167 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_167 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_168 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_168 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_169 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_169 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_170 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_170 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_171 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_174 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_174 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_175 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_173 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_173 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_MX[0] origin:032-cmt-pll 28_172 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_MX[1] origin:032-cmt-pll 29_172 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_171 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_175 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_83 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_83 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_84 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_84 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_85 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_85 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_80 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_80 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_81 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_81 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_82 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_82 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_86 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_86 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_87 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_87 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_88 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_88 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_89 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_89 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_90 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_90 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_91 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_94 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_94 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_95 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_93 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_93 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_MX[0] origin:032-cmt-pll 28_92 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_MX[1] origin:032-cmt-pll 29_92 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_91 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_95 -CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[0] origin:032-cmt-pll 28_656 -CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[1] origin:032-cmt-pll 29_656 -CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[2] origin:032-cmt-pll 28_657 -CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[3] origin:032-cmt-pll 29_657 -CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[4] origin:032-cmt-pll 28_658 -CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[5] origin:032-cmt-pll 29_658 -CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[6] origin:032-cmt-pll 28_659 -CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[7] origin:032-cmt-pll 29_659 -CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[8] origin:032-cmt-pll 29_660 -CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[9] origin:032-cmt-pll 28_661 -CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[10] origin:032-cmt-pll 29_662 -CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[11] origin:032-cmt-pll 28_663 -CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[0] origin:032-cmt-pll 28_664 -CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[1] origin:032-cmt-pll 29_664 -CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[2] origin:032-cmt-pll 28_665 -CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[3] origin:032-cmt-pll 29_665 -CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[4] origin:032-cmt-pll 29_666 -CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[5] origin:032-cmt-pll 28_667 -CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[6] origin:032-cmt-pll 29_668 -CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[7] origin:032-cmt-pll 28_669 -CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[8] origin:032-cmt-pll 29_670 -CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[9] origin:032-cmt-pll 28_671 -CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[0] origin:032-cmt-pll 28_229 -CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[1] origin:032-cmt-pll 29_229 -CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[2] origin:032-cmt-pll 28_230 -CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[3] origin:032-cmt-pll 29_230 -CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[4] origin:032-cmt-pll 28_231 -CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[5] origin:032-cmt-pll 29_231 -CMT_TOP_R_UPPER_T.PLLE2.LOCKREG2_RESERVED[0] origin:032-cmt-pll 29_239 -CMT_TOP_R_UPPER_T.PLLE2.LOCKREG3_RESERVED[0] origin:032-cmt-pll 29_247 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_195 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_195 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_196 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_196 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_197 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_197 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_192 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_192 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_193 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_193 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_194 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_194 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_198 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_198 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_199 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_199 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_200 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_200 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_201 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_201 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_202 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_202 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_203 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_206 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_206 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_207 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_205 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_205 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_MX[0] origin:032-cmt-pll 28_204 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_MX[1] origin:032-cmt-pll 29_204 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_203 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_207 +CMT_TOP_R_UPPER_T.PLLE2_ADV.COMP.ZHOLD_NO_CLKIN_BUF_TOP origin:032-cmt-pll 28_38 +CMT_TOP_R_UPPER_T.PLLE2_ADV.COMPENSATION.Z_ZHOLD_OR_CLKIN_BUF origin:032-cmt-pll 29_35 29_76 +CMT_TOP_R_UPPER_T.PLLE2_ADV.COMPENSATION.ZHOLD_NO_CLKIN_BUF origin:032-cmt-pll 28_73 29_36 +CMT_TOP_R_UPPER_T.PLLE2_ADV.COMPENSATION.ZHOLD_NO_CLKIN_BUF_NO_TOP origin:032-cmt-pll 29_38 +CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_EDGE[0] origin:032-cmt-pll 29_214 +CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_HIGH_TIME[0] origin:032-cmt-pll 28_211 +CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_HIGH_TIME[1] origin:032-cmt-pll 29_211 +CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_HIGH_TIME[2] origin:032-cmt-pll 28_212 +CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_HIGH_TIME[3] origin:032-cmt-pll 29_212 +CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_HIGH_TIME[4] origin:032-cmt-pll 28_213 +CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_HIGH_TIME[5] origin:032-cmt-pll 29_213 +CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_LOW_TIME[0] origin:032-cmt-pll 28_208 +CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_LOW_TIME[1] origin:032-cmt-pll 29_208 +CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_LOW_TIME[2] origin:032-cmt-pll 28_209 +CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_LOW_TIME[3] origin:032-cmt-pll 29_209 +CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_LOW_TIME[4] origin:032-cmt-pll 28_210 +CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_LOW_TIME[5] origin:032-cmt-pll 29_210 +CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_NO_COUNT[0] origin:032-cmt-pll 28_214 +CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_RESERVED[0] origin:032-cmt-pll 28_215 +CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_RESERVED[1] origin:032-cmt-pll 29_215 +CMT_TOP_R_UPPER_T.PLLE2_ADV.IN_USE origin:032-cmt-pll 28_216 28_219 28_222 28_266 28_280 28_283 28_284 28_37 28_48 28_592 28_622 28_623 28_624 28_627 28_628 28_74 28_768 28_78 28_785 28_786 28_787 28_788 28_790 28_791 28_792 28_793 28_795 28_796 28_797 28_798 28_799 28_803 28_806 28_807 28_811 28_812 28_815 28_816 28_817 28_818 28_819 28_821 28_822 28_823 28_824 28_826 28_827 28_828 28_829 28_832 28_835 28_838 28_841 28_845 28_847 29_268 29_281 29_282 29_283 29_48 29_563 29_567 29_589 29_621 29_622 29_625 29_626 29_627 29_77 29_78 29_785 29_786 29_788 29_79 29_790 29_791 29_793 29_797 29_798 29_800 29_809 29_811 29_812 29_813 29_814 29_815 29_816 29_817 29_819 29_823 29_824 29_825 29_826 29_827 29_829 29_830 29_831 29_832 29_835 29_836 29_838 29_839 29_840 29_841 29_842 29_845 +CMT_TOP_R_UPPER_T.PLLE2_ADV.INV_CLKINSEL origin:032-cmt-pll 28_754 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[0] origin:032-cmt-pll 28_232 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[1] origin:032-cmt-pll 29_232 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[2] origin:032-cmt-pll 28_233 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[3] origin:032-cmt-pll 29_233 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[4] origin:032-cmt-pll 28_234 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[5] origin:032-cmt-pll 29_234 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[6] origin:032-cmt-pll 28_235 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[7] origin:032-cmt-pll 29_235 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[8] origin:032-cmt-pll 28_236 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[9] origin:032-cmt-pll 29_236 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[10] origin:032-cmt-pll 28_240 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[11] origin:032-cmt-pll 29_240 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[12] origin:032-cmt-pll 28_241 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[13] origin:032-cmt-pll 29_241 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[14] origin:032-cmt-pll 28_242 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[15] origin:032-cmt-pll 29_242 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[16] origin:032-cmt-pll 28_243 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[17] origin:032-cmt-pll 29_243 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[18] origin:032-cmt-pll 28_244 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[19] origin:032-cmt-pll 29_244 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[20] origin:032-cmt-pll 28_224 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[21] origin:032-cmt-pll 29_224 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[22] origin:032-cmt-pll 28_225 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[23] origin:032-cmt-pll 29_225 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[24] origin:032-cmt-pll 28_226 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[25] origin:032-cmt-pll 29_226 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[26] origin:032-cmt-pll 28_227 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[27] origin:032-cmt-pll 29_227 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[28] origin:032-cmt-pll 28_228 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[29] origin:032-cmt-pll 29_228 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[30] origin:032-cmt-pll 28_237 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[31] origin:032-cmt-pll 29_237 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[32] origin:032-cmt-pll 28_238 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[33] origin:032-cmt-pll 29_238 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[34] origin:032-cmt-pll 28_239 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[35] origin:032-cmt-pll 28_245 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[36] origin:032-cmt-pll 29_245 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[37] origin:032-cmt-pll 28_246 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[38] origin:032-cmt-pll 29_246 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[39] origin:032-cmt-pll 28_247 +CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[0] origin:032-cmt-pll 28_352 +CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[1] origin:032-cmt-pll 29_352 +CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[2] origin:032-cmt-pll 28_353 +CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[3] origin:032-cmt-pll 29_353 +CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[4] origin:032-cmt-pll 28_354 +CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[5] origin:032-cmt-pll 29_354 +CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[6] origin:032-cmt-pll 28_355 +CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[7] origin:032-cmt-pll 29_355 +CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[8] origin:032-cmt-pll 28_356 +CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[9] origin:032-cmt-pll 29_356 +CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[10] origin:032-cmt-pll 28_357 +CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[11] origin:032-cmt-pll 29_357 +CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[12] origin:032-cmt-pll 28_358 +CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[13] origin:032-cmt-pll 29_358 +CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[14] origin:032-cmt-pll 28_359 +CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[15] origin:032-cmt-pll 29_359 +CMT_TOP_R_UPPER_T.PLLE2_ADV.STARTUP_WAIT origin:032-cmt-pll 28_769 +CMT_TOP_R_UPPER_T.PLLE2_ADV.TABLE[0] origin:032-cmt-pll 28_666 +CMT_TOP_R_UPPER_T.PLLE2_ADV.TABLE[1] origin:032-cmt-pll 29_667 +CMT_TOP_R_UPPER_T.PLLE2_ADV.TABLE[2] origin:032-cmt-pll 28_668 +CMT_TOP_R_UPPER_T.PLLE2_ADV.TABLE[3] origin:032-cmt-pll 29_669 +CMT_TOP_R_UPPER_T.PLLE2_ADV.TABLE[4] origin:032-cmt-pll 28_670 +CMT_TOP_R_UPPER_T.PLLE2_ADV.TABLE[5] origin:032-cmt-pll 29_671 +CMT_TOP_R_UPPER_T.PLLE2_ADV.TABLE[6] origin:032-cmt-pll 28_660 +CMT_TOP_R_UPPER_T.PLLE2_ADV.TABLE[7] origin:032-cmt-pll 29_661 +CMT_TOP_R_UPPER_T.PLLE2_ADV.TABLE[8] origin:032-cmt-pll 28_662 +CMT_TOP_R_UPPER_T.PLLE2_ADV.TABLE[9] origin:032-cmt-pll 29_663 +CMT_TOP_R_UPPER_T.PLLE2_ADV.ZINV_PWRDWN origin:032-cmt-pll 29_752 +CMT_TOP_R_UPPER_T.PLLE2_ADV.ZINV_RST origin:032-cmt-pll 28_752 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_99 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_99 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_100 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_100 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_101 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_101 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_96 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_96 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_97 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_97 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_98 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_98 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_102 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_102 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_103 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_103 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_104 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_104 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_105 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_105 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_106 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_106 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_107 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_110 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_110 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_111 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_109 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_109 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_MX[0] origin:032-cmt-pll 28_108 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_MX[1] origin:032-cmt-pll 29_108 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_107 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_111 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_115 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_115 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_116 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_116 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_117 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_117 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_112 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_112 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_113 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_113 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_114 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_114 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_118 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_118 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_119 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_119 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_120 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_120 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_121 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_121 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_122 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_122 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_123 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_126 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_126 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_127 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_125 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_125 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_MX[0] origin:032-cmt-pll 28_124 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_MX[1] origin:032-cmt-pll 29_124 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_123 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_127 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_131 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_131 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_132 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_132 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_133 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_133 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_128 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_128 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_129 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_129 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_130 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_130 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_134 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_134 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_135 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_135 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_136 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_136 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_137 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_137 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_138 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_138 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_139 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_142 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_142 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_143 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_141 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_141 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_MX[0] origin:032-cmt-pll 28_140 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_MX[1] origin:032-cmt-pll 29_140 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_139 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_143 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_147 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_147 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_148 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_148 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_149 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_149 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_144 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_144 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_145 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_145 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_146 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_146 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_150 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_150 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_151 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_151 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_152 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_152 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_153 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_153 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_154 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_154 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_155 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_158 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_158 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_159 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_157 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_157 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_MX[0] origin:032-cmt-pll 28_156 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_MX[1] origin:032-cmt-pll 29_156 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_155 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_159 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_163 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_163 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_164 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_164 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_165 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_165 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_160 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_160 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_161 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_161 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_162 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_162 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_166 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_166 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_167 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_167 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_168 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_168 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_169 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_169 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_170 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_170 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_171 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_174 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_174 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_175 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_173 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_173 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_MX[0] origin:032-cmt-pll 28_172 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_MX[1] origin:032-cmt-pll 29_172 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_171 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_175 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_83 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_83 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_84 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_84 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_85 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_85 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_80 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_80 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_81 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_81 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_82 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_82 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_86 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_86 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_87 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_87 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_88 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_88 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_89 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_89 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_90 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_90 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_91 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_94 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_94 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_95 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_93 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_93 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_MX[0] origin:032-cmt-pll 28_92 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_MX[1] origin:032-cmt-pll 29_92 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_91 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_95 +CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[0] origin:032-cmt-pll 28_656 +CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[1] origin:032-cmt-pll 29_656 +CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[2] origin:032-cmt-pll 28_657 +CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[3] origin:032-cmt-pll 29_657 +CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[4] origin:032-cmt-pll 28_658 +CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[5] origin:032-cmt-pll 29_658 +CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[6] origin:032-cmt-pll 28_659 +CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[7] origin:032-cmt-pll 29_659 +CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[8] origin:032-cmt-pll 29_660 +CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[9] origin:032-cmt-pll 28_661 +CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[10] origin:032-cmt-pll 29_662 +CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[11] origin:032-cmt-pll 28_663 +CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[0] origin:032-cmt-pll 28_664 +CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[1] origin:032-cmt-pll 29_664 +CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[2] origin:032-cmt-pll 28_665 +CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[3] origin:032-cmt-pll 29_665 +CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[4] origin:032-cmt-pll 29_666 +CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[5] origin:032-cmt-pll 28_667 +CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[6] origin:032-cmt-pll 29_668 +CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[7] origin:032-cmt-pll 28_669 +CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[8] origin:032-cmt-pll 29_670 +CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[9] origin:032-cmt-pll 28_671 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LOCKREG1_RESERVED[0] origin:032-cmt-pll 28_229 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LOCKREG1_RESERVED[1] origin:032-cmt-pll 29_229 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LOCKREG1_RESERVED[2] origin:032-cmt-pll 28_230 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LOCKREG1_RESERVED[3] origin:032-cmt-pll 29_230 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LOCKREG1_RESERVED[4] origin:032-cmt-pll 28_231 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LOCKREG1_RESERVED[5] origin:032-cmt-pll 29_231 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LOCKREG2_RESERVED[0] origin:032-cmt-pll 29_239 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LOCKREG3_RESERVED[0] origin:032-cmt-pll 29_247 diff --git a/artix7/segbits_gtp_channel_0.db b/artix7/segbits_gtp_channel_0.db index 3f26ac3..01d3c39 100644 --- a/artix7/segbits_gtp_channel_0.db +++ b/artix7/segbits_gtp_channel_0.db @@ -1,1627 +1,1627 @@ -GTP_CHANNEL_0.GTPE2.ACJTAG_DEBUG_MODE[0] 28_07 -GTP_CHANNEL_0.GTPE2.ACJTAG_MODE[0] 29_06 -GTP_CHANNEL_0.GTPE2.ACJTAG_RESET[0] 29_07 -GTP_CHANNEL_0.GTPE2.ADAPT_CFG0[0] 30_464 -GTP_CHANNEL_0.GTPE2.ADAPT_CFG0[1] 31_464 -GTP_CHANNEL_0.GTPE2.ADAPT_CFG0[2] 30_465 -GTP_CHANNEL_0.GTPE2.ADAPT_CFG0[3] 31_465 -GTP_CHANNEL_0.GTPE2.ADAPT_CFG0[4] 30_466 -GTP_CHANNEL_0.GTPE2.ADAPT_CFG0[5] 31_466 -GTP_CHANNEL_0.GTPE2.ADAPT_CFG0[6] 30_467 -GTP_CHANNEL_0.GTPE2.ADAPT_CFG0[7] 31_467 -GTP_CHANNEL_0.GTPE2.ADAPT_CFG0[8] 30_468 -GTP_CHANNEL_0.GTPE2.ADAPT_CFG0[9] 31_468 -GTP_CHANNEL_0.GTPE2.ADAPT_CFG0[10] 30_469 -GTP_CHANNEL_0.GTPE2.ADAPT_CFG0[11] 31_469 -GTP_CHANNEL_0.GTPE2.ADAPT_CFG0[12] 30_470 -GTP_CHANNEL_0.GTPE2.ADAPT_CFG0[13] 31_470 -GTP_CHANNEL_0.GTPE2.ADAPT_CFG0[14] 30_471 -GTP_CHANNEL_0.GTPE2.ADAPT_CFG0[15] 31_471 -GTP_CHANNEL_0.GTPE2.ADAPT_CFG0[16] 30_472 -GTP_CHANNEL_0.GTPE2.ADAPT_CFG0[17] 31_472 -GTP_CHANNEL_0.GTPE2.ADAPT_CFG0[18] 30_473 -GTP_CHANNEL_0.GTPE2.ADAPT_CFG0[19] 31_473 -GTP_CHANNEL_0.GTPE2.ALIGN_COMMA_DOUBLE 28_522 -GTP_CHANNEL_0.GTPE2.ALIGN_COMMA_ENABLE[0] 28_496 -GTP_CHANNEL_0.GTPE2.ALIGN_COMMA_ENABLE[1] 29_496 -GTP_CHANNEL_0.GTPE2.ALIGN_COMMA_ENABLE[2] 28_497 -GTP_CHANNEL_0.GTPE2.ALIGN_COMMA_ENABLE[3] 29_497 -GTP_CHANNEL_0.GTPE2.ALIGN_COMMA_ENABLE[4] 28_498 -GTP_CHANNEL_0.GTPE2.ALIGN_COMMA_ENABLE[5] 29_498 -GTP_CHANNEL_0.GTPE2.ALIGN_COMMA_ENABLE[6] 28_499 -GTP_CHANNEL_0.GTPE2.ALIGN_COMMA_ENABLE[7] 29_499 -GTP_CHANNEL_0.GTPE2.ALIGN_COMMA_ENABLE[8] 28_500 -GTP_CHANNEL_0.GTPE2.ALIGN_COMMA_ENABLE[9] 29_500 -GTP_CHANNEL_0.GTPE2.ALIGN_COMMA_WORD[0] 29_526 -GTP_CHANNEL_0.GTPE2.ALIGN_COMMA_WORD[1] 28_527 -GTP_CHANNEL_0.GTPE2.ALIGN_MCOMMA_DET 28_523 -GTP_CHANNEL_0.GTPE2.ALIGN_MCOMMA_VALUE[0] 28_504 -GTP_CHANNEL_0.GTPE2.ALIGN_MCOMMA_VALUE[1] 29_504 -GTP_CHANNEL_0.GTPE2.ALIGN_MCOMMA_VALUE[2] 28_505 -GTP_CHANNEL_0.GTPE2.ALIGN_MCOMMA_VALUE[3] 29_505 -GTP_CHANNEL_0.GTPE2.ALIGN_MCOMMA_VALUE[4] 28_506 -GTP_CHANNEL_0.GTPE2.ALIGN_MCOMMA_VALUE[5] 29_506 -GTP_CHANNEL_0.GTPE2.ALIGN_MCOMMA_VALUE[6] 28_507 -GTP_CHANNEL_0.GTPE2.ALIGN_MCOMMA_VALUE[7] 29_507 -GTP_CHANNEL_0.GTPE2.ALIGN_MCOMMA_VALUE[8] 28_508 -GTP_CHANNEL_0.GTPE2.ALIGN_MCOMMA_VALUE[9] 29_508 -GTP_CHANNEL_0.GTPE2.ALIGN_PCOMMA_DET 29_523 -GTP_CHANNEL_0.GTPE2.ALIGN_PCOMMA_VALUE[0] 28_512 -GTP_CHANNEL_0.GTPE2.ALIGN_PCOMMA_VALUE[1] 29_512 -GTP_CHANNEL_0.GTPE2.ALIGN_PCOMMA_VALUE[2] 28_513 -GTP_CHANNEL_0.GTPE2.ALIGN_PCOMMA_VALUE[3] 29_513 -GTP_CHANNEL_0.GTPE2.ALIGN_PCOMMA_VALUE[4] 28_514 -GTP_CHANNEL_0.GTPE2.ALIGN_PCOMMA_VALUE[5] 29_514 -GTP_CHANNEL_0.GTPE2.ALIGN_PCOMMA_VALUE[6] 28_515 -GTP_CHANNEL_0.GTPE2.ALIGN_PCOMMA_VALUE[7] 29_515 -GTP_CHANNEL_0.GTPE2.ALIGN_PCOMMA_VALUE[8] 28_516 -GTP_CHANNEL_0.GTPE2.ALIGN_PCOMMA_VALUE[9] 29_516 -GTP_CHANNEL_0.GTPE2.CBCC_DATA_SOURCE_SEL.DECODED 29_661 -GTP_CHANNEL_0.GTPE2.CFOK_CFG[0] 30_392 -GTP_CHANNEL_0.GTPE2.CFOK_CFG[1] 31_392 -GTP_CHANNEL_0.GTPE2.CFOK_CFG[2] 30_393 -GTP_CHANNEL_0.GTPE2.CFOK_CFG[3] 31_393 -GTP_CHANNEL_0.GTPE2.CFOK_CFG[4] 30_394 -GTP_CHANNEL_0.GTPE2.CFOK_CFG[5] 31_394 -GTP_CHANNEL_0.GTPE2.CFOK_CFG[6] 30_395 -GTP_CHANNEL_0.GTPE2.CFOK_CFG[7] 31_395 -GTP_CHANNEL_0.GTPE2.CFOK_CFG[8] 30_396 -GTP_CHANNEL_0.GTPE2.CFOK_CFG[9] 31_396 -GTP_CHANNEL_0.GTPE2.CFOK_CFG[10] 30_397 -GTP_CHANNEL_0.GTPE2.CFOK_CFG[11] 31_397 -GTP_CHANNEL_0.GTPE2.CFOK_CFG[12] 30_398 -GTP_CHANNEL_0.GTPE2.CFOK_CFG[13] 31_398 -GTP_CHANNEL_0.GTPE2.CFOK_CFG[14] 30_399 -GTP_CHANNEL_0.GTPE2.CFOK_CFG[15] 31_399 -GTP_CHANNEL_0.GTPE2.CFOK_CFG[16] 30_400 -GTP_CHANNEL_0.GTPE2.CFOK_CFG[17] 31_400 -GTP_CHANNEL_0.GTPE2.CFOK_CFG[18] 30_401 -GTP_CHANNEL_0.GTPE2.CFOK_CFG[19] 31_401 -GTP_CHANNEL_0.GTPE2.CFOK_CFG[20] 30_402 -GTP_CHANNEL_0.GTPE2.CFOK_CFG[21] 31_402 -GTP_CHANNEL_0.GTPE2.CFOK_CFG[22] 30_403 -GTP_CHANNEL_0.GTPE2.CFOK_CFG[23] 31_403 -GTP_CHANNEL_0.GTPE2.CFOK_CFG[24] 30_404 -GTP_CHANNEL_0.GTPE2.CFOK_CFG[25] 31_404 -GTP_CHANNEL_0.GTPE2.CFOK_CFG[26] 30_405 -GTP_CHANNEL_0.GTPE2.CFOK_CFG[27] 31_405 -GTP_CHANNEL_0.GTPE2.CFOK_CFG[28] 30_406 -GTP_CHANNEL_0.GTPE2.CFOK_CFG[29] 31_406 -GTP_CHANNEL_0.GTPE2.CFOK_CFG[30] 30_407 -GTP_CHANNEL_0.GTPE2.CFOK_CFG[31] 31_407 -GTP_CHANNEL_0.GTPE2.CFOK_CFG[32] 30_408 -GTP_CHANNEL_0.GTPE2.CFOK_CFG[33] 31_408 -GTP_CHANNEL_0.GTPE2.CFOK_CFG[34] 30_409 -GTP_CHANNEL_0.GTPE2.CFOK_CFG[35] 31_409 -GTP_CHANNEL_0.GTPE2.CFOK_CFG[36] 30_410 -GTP_CHANNEL_0.GTPE2.CFOK_CFG[37] 31_410 -GTP_CHANNEL_0.GTPE2.CFOK_CFG[38] 30_411 -GTP_CHANNEL_0.GTPE2.CFOK_CFG[39] 31_411 -GTP_CHANNEL_0.GTPE2.CFOK_CFG[40] 30_412 -GTP_CHANNEL_0.GTPE2.CFOK_CFG[41] 31_412 -GTP_CHANNEL_0.GTPE2.CFOK_CFG[42] 30_413 -GTP_CHANNEL_0.GTPE2.CFOK_CFG2[0] 30_459 -GTP_CHANNEL_0.GTPE2.CFOK_CFG2[1] 31_459 -GTP_CHANNEL_0.GTPE2.CFOK_CFG2[2] 30_460 -GTP_CHANNEL_0.GTPE2.CFOK_CFG2[3] 31_460 -GTP_CHANNEL_0.GTPE2.CFOK_CFG2[4] 30_461 -GTP_CHANNEL_0.GTPE2.CFOK_CFG2[5] 31_461 -GTP_CHANNEL_0.GTPE2.CFOK_CFG2[6] 30_462 -GTP_CHANNEL_0.GTPE2.CFOK_CFG3[0] 30_416 -GTP_CHANNEL_0.GTPE2.CFOK_CFG3[1] 31_416 -GTP_CHANNEL_0.GTPE2.CFOK_CFG3[2] 30_417 -GTP_CHANNEL_0.GTPE2.CFOK_CFG3[3] 31_417 -GTP_CHANNEL_0.GTPE2.CFOK_CFG3[4] 30_418 -GTP_CHANNEL_0.GTPE2.CFOK_CFG3[5] 31_418 -GTP_CHANNEL_0.GTPE2.CFOK_CFG3[6] 30_419 -GTP_CHANNEL_0.GTPE2.CFOK_CFG4[0] 31_438 -GTP_CHANNEL_0.GTPE2.CFOK_CFG5[0] 30_429 -GTP_CHANNEL_0.GTPE2.CFOK_CFG5[1] 31_429 -GTP_CHANNEL_0.GTPE2.CFOK_CFG6[0] 31_436 -GTP_CHANNEL_0.GTPE2.CFOK_CFG6[1] 30_437 -GTP_CHANNEL_0.GTPE2.CFOK_CFG6[2] 31_437 -GTP_CHANNEL_0.GTPE2.CFOK_CFG6[3] 30_438 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_KEEP_ALIGN 29_631 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_MAX_SKEW[0] 28_670 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_MAX_SKEW[1] 29_670 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_MAX_SKEW[2] 28_671 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_MAX_SKEW[3] 29_671 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_1_1[0] 28_608 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_1_1[1] 29_608 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_1_1[2] 28_609 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_1_1[3] 29_609 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_1_1[4] 28_610 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_1_1[5] 29_610 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_1_1[6] 28_611 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_1_1[7] 29_611 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_1_1[8] 28_612 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_1_1[9] 29_612 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_1_2[0] 28_616 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_1_2[1] 29_616 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_1_2[2] 28_617 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_1_2[3] 29_617 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_1_2[4] 28_618 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_1_2[5] 29_618 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_1_2[6] 28_619 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_1_2[7] 29_619 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_1_2[8] 28_620 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_1_2[9] 29_620 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_1_3[0] 28_624 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_1_3[1] 29_624 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_1_3[2] 28_625 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_1_3[3] 29_625 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_1_3[4] 28_626 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_1_3[5] 29_626 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_1_3[6] 28_627 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_1_3[7] 29_627 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_1_3[8] 28_628 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_1_3[9] 29_628 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_1_4[0] 28_632 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_1_4[1] 29_632 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_1_4[2] 28_633 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_1_4[3] 29_633 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_1_4[4] 28_634 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_1_4[5] 29_634 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_1_4[6] 28_635 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_1_4[7] 29_635 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_1_4[8] 28_636 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_1_4[9] 29_636 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_1_ENABLE[0] 28_614 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_1_ENABLE[1] 29_614 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_1_ENABLE[2] 28_615 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_1_ENABLE[3] 29_615 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_2_1[0] 28_640 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_2_1[1] 29_640 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_2_1[2] 28_641 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_2_1[3] 29_641 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_2_1[4] 28_642 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_2_1[5] 29_642 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_2_1[6] 28_643 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_2_1[7] 29_643 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_2_1[8] 28_644 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_2_1[9] 29_644 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_2_2[0] 28_648 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_2_2[1] 29_648 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_2_2[2] 28_649 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_2_2[3] 29_649 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_2_2[4] 28_650 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_2_2[5] 29_650 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_2_2[6] 28_651 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_2_2[7] 29_651 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_2_2[8] 28_652 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_2_2[9] 29_652 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_2_3[0] 28_656 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_2_3[1] 29_656 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_2_3[2] 28_657 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_2_3[3] 29_657 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_2_3[4] 28_658 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_2_3[5] 29_658 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_2_3[6] 28_659 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_2_3[7] 29_659 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_2_3[8] 28_660 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_2_3[9] 29_660 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_2_4[0] 28_664 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_2_4[1] 29_664 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_2_4[2] 28_665 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_2_4[3] 29_665 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_2_4[4] 28_666 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_2_4[5] 29_666 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_2_4[6] 28_667 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_2_4[7] 29_667 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_2_4[8] 28_668 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_2_4[9] 29_668 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_2_ENABLE[0] 28_646 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_2_ENABLE[1] 29_646 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_2_ENABLE[2] 28_647 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_2_ENABLE[3] 29_647 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_2_USE 29_645 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_LEN[0] 28_623 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_LEN[1] 29_623 -GTP_CHANNEL_0.GTPE2.CLK_COMMON_SWING[0] 31_311 -GTP_CHANNEL_0.GTPE2.CLK_COR_KEEP_IDLE 28_591 -GTP_CHANNEL_0.GTPE2.CLK_COR_MAX_LAT[0] 28_557 -GTP_CHANNEL_0.GTPE2.CLK_COR_MAX_LAT[1] 29_557 -GTP_CHANNEL_0.GTPE2.CLK_COR_MAX_LAT[2] 28_558 -GTP_CHANNEL_0.GTPE2.CLK_COR_MAX_LAT[3] 29_558 -GTP_CHANNEL_0.GTPE2.CLK_COR_MAX_LAT[4] 28_559 -GTP_CHANNEL_0.GTPE2.CLK_COR_MAX_LAT[5] 29_559 -GTP_CHANNEL_0.GTPE2.CLK_COR_MIN_LAT[0] 28_565 -GTP_CHANNEL_0.GTPE2.CLK_COR_MIN_LAT[1] 29_565 -GTP_CHANNEL_0.GTPE2.CLK_COR_MIN_LAT[2] 28_566 -GTP_CHANNEL_0.GTPE2.CLK_COR_MIN_LAT[3] 29_566 -GTP_CHANNEL_0.GTPE2.CLK_COR_MIN_LAT[4] 28_567 -GTP_CHANNEL_0.GTPE2.CLK_COR_MIN_LAT[5] 29_567 -GTP_CHANNEL_0.GTPE2.CLK_COR_PRECEDENCE 28_590 -GTP_CHANNEL_0.GTPE2.CLK_COR_REPEAT_WAIT[0] 28_573 -GTP_CHANNEL_0.GTPE2.CLK_COR_REPEAT_WAIT[1] 29_573 -GTP_CHANNEL_0.GTPE2.CLK_COR_REPEAT_WAIT[2] 28_574 -GTP_CHANNEL_0.GTPE2.CLK_COR_REPEAT_WAIT[3] 29_574 -GTP_CHANNEL_0.GTPE2.CLK_COR_REPEAT_WAIT[4] 28_575 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_1_1[0] 28_544 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_1_1[1] 29_544 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_1_1[2] 28_545 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_1_1[3] 29_545 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_1_1[4] 28_546 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_1_1[5] 29_546 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_1_1[6] 28_547 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_1_1[7] 29_547 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_1_1[8] 28_548 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_1_1[9] 29_548 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_1_2[0] 28_552 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_1_2[1] 29_552 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_1_2[2] 28_553 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_1_2[3] 29_553 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_1_2[4] 28_554 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_1_2[5] 29_554 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_1_2[6] 28_555 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_1_2[7] 29_555 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_1_2[8] 28_556 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_1_2[9] 29_556 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_1_3[0] 28_560 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_1_3[1] 29_560 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_1_3[2] 28_561 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_1_3[3] 29_561 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_1_3[4] 28_562 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_1_3[5] 29_562 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_1_3[6] 28_563 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_1_3[7] 29_563 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_1_3[8] 28_564 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_1_3[9] 29_564 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_1_4[0] 28_568 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_1_4[1] 29_568 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_1_4[2] 28_569 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_1_4[3] 29_569 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_1_4[4] 28_570 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_1_4[5] 29_570 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_1_4[6] 28_571 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_1_4[7] 29_571 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_1_4[8] 28_572 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_1_4[9] 29_572 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_1_ENABLE[0] 28_549 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_1_ENABLE[1] 29_549 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_1_ENABLE[2] 28_550 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_1_ENABLE[3] 29_550 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_2_1[0] 28_576 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_2_1[1] 29_576 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_2_1[2] 28_577 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_2_1[3] 29_577 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_2_1[4] 28_578 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_2_1[5] 29_578 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_2_1[6] 28_579 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_2_1[7] 29_579 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_2_1[8] 28_580 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_2_1[9] 29_580 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_2_2[0] 28_584 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_2_2[1] 29_584 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_2_2[2] 28_585 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_2_2[3] 29_585 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_2_2[4] 28_586 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_2_2[5] 29_586 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_2_2[6] 28_587 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_2_2[7] 29_587 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_2_2[8] 28_588 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_2_2[9] 29_588 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_2_3[0] 28_592 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_2_3[1] 29_592 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_2_3[2] 28_593 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_2_3[3] 29_593 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_2_3[4] 28_594 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_2_3[5] 29_594 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_2_3[6] 28_595 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_2_3[7] 29_595 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_2_3[8] 28_596 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_2_3[9] 29_596 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_2_4[0] 28_600 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_2_4[1] 29_600 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_2_4[2] 28_601 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_2_4[3] 29_601 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_2_4[4] 28_602 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_2_4[5] 29_602 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_2_4[6] 28_603 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_2_4[7] 29_603 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_2_4[8] 28_604 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_2_4[9] 29_604 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_2_ENABLE[0] 28_581 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_2_ENABLE[1] 29_581 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_2_ENABLE[2] 28_582 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_2_ENABLE[3] 29_582 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_2_USE 28_583 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_LEN[0] 28_589 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_LEN[1] 29_589 -GTP_CHANNEL_0.GTPE2.CLK_CORRECT_USE 28_551 -GTP_CHANNEL_0.GTPE2.DEC_MCOMMA_DETECT 29_494 -GTP_CHANNEL_0.GTPE2.DEC_PCOMMA_DETECT 28_495 -GTP_CHANNEL_0.GTPE2.DEC_VALID_COMMA_ONLY 28_494 -GTP_CHANNEL_0.GTPE2.DMONITOR_CFG[0] 30_368 -GTP_CHANNEL_0.GTPE2.DMONITOR_CFG[1] 31_368 -GTP_CHANNEL_0.GTPE2.DMONITOR_CFG[2] 30_369 -GTP_CHANNEL_0.GTPE2.DMONITOR_CFG[3] 31_369 -GTP_CHANNEL_0.GTPE2.DMONITOR_CFG[4] 30_370 -GTP_CHANNEL_0.GTPE2.DMONITOR_CFG[5] 31_370 -GTP_CHANNEL_0.GTPE2.DMONITOR_CFG[6] 30_371 -GTP_CHANNEL_0.GTPE2.DMONITOR_CFG[7] 31_371 -GTP_CHANNEL_0.GTPE2.DMONITOR_CFG[8] 30_372 -GTP_CHANNEL_0.GTPE2.DMONITOR_CFG[9] 31_372 -GTP_CHANNEL_0.GTPE2.DMONITOR_CFG[10] 30_373 -GTP_CHANNEL_0.GTPE2.DMONITOR_CFG[11] 31_373 -GTP_CHANNEL_0.GTPE2.DMONITOR_CFG[12] 30_374 -GTP_CHANNEL_0.GTPE2.DMONITOR_CFG[13] 31_374 -GTP_CHANNEL_0.GTPE2.DMONITOR_CFG[14] 30_375 -GTP_CHANNEL_0.GTPE2.DMONITOR_CFG[15] 31_375 -GTP_CHANNEL_0.GTPE2.DMONITOR_CFG[16] 30_376 -GTP_CHANNEL_0.GTPE2.DMONITOR_CFG[17] 31_376 -GTP_CHANNEL_0.GTPE2.DMONITOR_CFG[18] 30_377 -GTP_CHANNEL_0.GTPE2.DMONITOR_CFG[19] 31_377 -GTP_CHANNEL_0.GTPE2.DMONITOR_CFG[20] 30_378 -GTP_CHANNEL_0.GTPE2.DMONITOR_CFG[21] 31_378 -GTP_CHANNEL_0.GTPE2.DMONITOR_CFG[22] 30_379 -GTP_CHANNEL_0.GTPE2.DMONITOR_CFG[23] 31_379 -GTP_CHANNEL_0.GTPE2.ES_CLK_PHASE_SEL[0] 31_463 -GTP_CHANNEL_0.GTPE2.ES_CONTROL[0] 28_488 -GTP_CHANNEL_0.GTPE2.ES_CONTROL[1] 29_488 -GTP_CHANNEL_0.GTPE2.ES_CONTROL[2] 28_489 -GTP_CHANNEL_0.GTPE2.ES_CONTROL[3] 29_489 -GTP_CHANNEL_0.GTPE2.ES_CONTROL[4] 28_490 -GTP_CHANNEL_0.GTPE2.ES_CONTROL[5] 29_490 -GTP_CHANNEL_0.GTPE2.ES_ERRDET_EN 29_492 -GTP_CHANNEL_0.GTPE2.ES_EYE_SCAN_EN 28_492 -GTP_CHANNEL_0.GTPE2.ES_HORZ_OFFSET[0] 28_480 -GTP_CHANNEL_0.GTPE2.ES_HORZ_OFFSET[1] 29_480 -GTP_CHANNEL_0.GTPE2.ES_HORZ_OFFSET[2] 28_481 -GTP_CHANNEL_0.GTPE2.ES_HORZ_OFFSET[3] 29_481 -GTP_CHANNEL_0.GTPE2.ES_HORZ_OFFSET[4] 28_482 -GTP_CHANNEL_0.GTPE2.ES_HORZ_OFFSET[5] 29_482 -GTP_CHANNEL_0.GTPE2.ES_HORZ_OFFSET[6] 28_483 -GTP_CHANNEL_0.GTPE2.ES_HORZ_OFFSET[7] 29_483 -GTP_CHANNEL_0.GTPE2.ES_HORZ_OFFSET[8] 28_484 -GTP_CHANNEL_0.GTPE2.ES_HORZ_OFFSET[9] 29_484 -GTP_CHANNEL_0.GTPE2.ES_HORZ_OFFSET[10] 28_485 -GTP_CHANNEL_0.GTPE2.ES_HORZ_OFFSET[11] 29_485 -GTP_CHANNEL_0.GTPE2.ES_PMA_CFG[0] 30_624 -GTP_CHANNEL_0.GTPE2.ES_PMA_CFG[1] 31_624 -GTP_CHANNEL_0.GTPE2.ES_PMA_CFG[2] 30_625 -GTP_CHANNEL_0.GTPE2.ES_PMA_CFG[3] 31_625 -GTP_CHANNEL_0.GTPE2.ES_PMA_CFG[4] 30_626 -GTP_CHANNEL_0.GTPE2.ES_PMA_CFG[5] 31_626 -GTP_CHANNEL_0.GTPE2.ES_PMA_CFG[6] 30_627 -GTP_CHANNEL_0.GTPE2.ES_PMA_CFG[7] 31_627 -GTP_CHANNEL_0.GTPE2.ES_PMA_CFG[8] 30_628 -GTP_CHANNEL_0.GTPE2.ES_PMA_CFG[9] 31_628 -GTP_CHANNEL_0.GTPE2.ES_PRESCALE[0] 29_477 -GTP_CHANNEL_0.GTPE2.ES_PRESCALE[1] 28_478 -GTP_CHANNEL_0.GTPE2.ES_PRESCALE[2] 29_478 -GTP_CHANNEL_0.GTPE2.ES_PRESCALE[3] 28_479 -GTP_CHANNEL_0.GTPE2.ES_PRESCALE[4] 29_479 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[0] 28_392 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[1] 29_392 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[2] 28_393 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[3] 29_393 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[4] 28_394 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[5] 29_394 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[6] 28_395 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[7] 29_395 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[8] 28_396 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[9] 29_396 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[10] 28_397 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[11] 29_397 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[12] 28_398 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[13] 29_398 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[14] 28_399 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[15] 29_399 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[16] 28_400 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[17] 29_400 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[18] 28_401 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[19] 29_401 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[20] 28_402 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[21] 29_402 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[22] 28_403 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[23] 29_403 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[24] 28_404 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[25] 29_404 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[26] 28_405 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[27] 29_405 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[28] 28_406 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[29] 29_406 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[30] 28_407 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[31] 29_407 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[32] 28_408 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[33] 29_408 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[34] 28_409 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[35] 29_409 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[36] 28_410 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[37] 29_410 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[38] 28_411 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[39] 29_411 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[40] 28_412 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[41] 29_412 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[42] 28_413 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[43] 29_413 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[44] 28_414 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[45] 29_414 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[46] 28_415 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[47] 29_415 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[48] 28_416 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[49] 29_416 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[50] 28_417 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[51] 29_417 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[52] 28_418 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[53] 29_418 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[54] 28_419 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[55] 29_419 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[56] 28_420 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[57] 29_420 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[58] 28_421 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[59] 29_421 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[60] 28_422 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[61] 29_422 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[62] 28_423 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[63] 29_423 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[64] 28_424 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[65] 29_424 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[66] 28_425 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[67] 29_425 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[68] 28_426 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[69] 29_426 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[70] 28_427 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[71] 29_427 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[72] 28_428 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[73] 29_428 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[74] 28_429 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[75] 29_429 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[76] 28_430 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[77] 29_430 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[78] 28_431 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[79] 29_431 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[0] 28_352 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[1] 29_352 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[2] 28_353 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[3] 29_353 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[4] 28_354 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[5] 29_354 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[6] 28_355 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[7] 29_355 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[8] 28_356 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[9] 29_356 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[10] 28_357 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[11] 29_357 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[12] 28_358 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[13] 29_358 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[14] 28_359 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[15] 29_359 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[16] 28_360 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[17] 29_360 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[18] 28_361 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[19] 29_361 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[20] 28_362 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[21] 29_362 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[22] 28_363 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[23] 29_363 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[24] 28_364 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[25] 29_364 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[26] 28_365 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[27] 29_365 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[28] 28_366 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[29] 29_366 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[30] 28_367 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[31] 29_367 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[32] 28_368 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[33] 29_368 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[34] 28_369 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[35] 29_369 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[36] 28_370 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[37] 29_370 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[38] 28_371 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[39] 29_371 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[40] 28_372 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[41] 29_372 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[42] 28_373 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[43] 29_373 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[44] 28_374 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[45] 29_374 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[46] 28_375 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[47] 29_375 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[48] 28_376 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[49] 29_376 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[50] 28_377 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[51] 29_377 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[52] 28_378 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[53] 29_378 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[54] 28_379 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[55] 29_379 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[56] 28_380 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[57] 29_380 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[58] 28_381 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[59] 29_381 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[60] 28_382 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[61] 29_382 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[62] 28_383 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[63] 29_383 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[64] 28_384 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[65] 29_384 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[66] 28_385 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[67] 29_385 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[68] 28_386 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[69] 29_386 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[70] 28_387 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[71] 29_387 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[72] 28_388 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[73] 29_388 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[74] 28_389 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[75] 29_389 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[76] 28_390 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[77] 29_390 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[78] 28_391 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[79] 29_391 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[0] 28_432 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[1] 29_432 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[2] 28_433 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[3] 29_433 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[4] 28_434 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[5] 29_434 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[6] 28_435 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[7] 29_435 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[8] 28_436 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[9] 29_436 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[10] 28_437 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[11] 29_437 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[12] 28_438 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[13] 29_438 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[14] 28_439 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[15] 29_439 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[16] 28_440 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[17] 29_440 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[18] 28_441 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[19] 29_441 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[20] 28_442 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[21] 29_442 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[22] 28_443 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[23] 29_443 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[24] 28_444 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[25] 29_444 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[26] 28_445 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[27] 29_445 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[28] 28_446 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[29] 29_446 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[30] 28_447 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[31] 29_447 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[32] 28_448 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[33] 29_448 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[34] 28_449 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[35] 29_449 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[36] 28_450 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[37] 29_450 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[38] 28_451 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[39] 29_451 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[40] 28_452 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[41] 29_452 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[42] 28_453 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[43] 29_453 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[44] 28_454 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[45] 29_454 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[46] 28_455 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[47] 29_455 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[48] 28_456 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[49] 29_456 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[50] 28_457 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[51] 29_457 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[52] 28_458 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[53] 29_458 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[54] 28_459 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[55] 29_459 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[56] 28_460 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[57] 29_460 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[58] 28_461 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[59] 29_461 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[60] 28_462 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[61] 29_462 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[62] 28_463 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[63] 29_463 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[64] 28_464 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[65] 29_464 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[66] 28_465 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[67] 29_465 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[68] 28_466 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[69] 29_466 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[70] 28_467 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[71] 29_467 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[72] 28_468 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[73] 29_468 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[74] 28_469 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[75] 29_469 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[76] 28_470 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[77] 29_470 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[78] 28_471 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[79] 29_471 -GTP_CHANNEL_0.GTPE2.ES_VERT_OFFSET[0] 28_472 -GTP_CHANNEL_0.GTPE2.ES_VERT_OFFSET[1] 29_472 -GTP_CHANNEL_0.GTPE2.ES_VERT_OFFSET[2] 28_473 -GTP_CHANNEL_0.GTPE2.ES_VERT_OFFSET[3] 29_473 -GTP_CHANNEL_0.GTPE2.ES_VERT_OFFSET[4] 28_474 -GTP_CHANNEL_0.GTPE2.ES_VERT_OFFSET[5] 29_474 -GTP_CHANNEL_0.GTPE2.ES_VERT_OFFSET[6] 28_475 -GTP_CHANNEL_0.GTPE2.ES_VERT_OFFSET[7] 29_475 -GTP_CHANNEL_0.GTPE2.ES_VERT_OFFSET[8] 28_476 -GTP_CHANNEL_0.GTPE2.FTS_DESKEW_SEQ_ENABLE[0] 28_662 -GTP_CHANNEL_0.GTPE2.FTS_DESKEW_SEQ_ENABLE[1] 29_662 -GTP_CHANNEL_0.GTPE2.FTS_DESKEW_SEQ_ENABLE[2] 28_663 -GTP_CHANNEL_0.GTPE2.FTS_DESKEW_SEQ_ENABLE[3] 29_663 -GTP_CHANNEL_0.GTPE2.FTS_LANE_DESKEW_CFG[0] 28_654 -GTP_CHANNEL_0.GTPE2.FTS_LANE_DESKEW_CFG[1] 29_654 -GTP_CHANNEL_0.GTPE2.FTS_LANE_DESKEW_CFG[2] 28_655 -GTP_CHANNEL_0.GTPE2.FTS_LANE_DESKEW_CFG[3] 29_655 -GTP_CHANNEL_0.GTPE2.FTS_LANE_DESKEW_EN 29_653 -GTP_CHANNEL_0.GTPE2.GEARBOX_MODE[0] 28_224 -GTP_CHANNEL_0.GTPE2.GEARBOX_MODE[1] 29_224 -GTP_CHANNEL_0.GTPE2.GEARBOX_MODE[2] 28_225 -GTP_CHANNEL_0.GTPE2.IN_USE 28_00 28_01 28_47 28_52 28_53 28_65 29_01 29_47 30_129 -GTP_CHANNEL_0.GTPE2.LOOPBACK_CFG[0] 30_20 -GTP_CHANNEL_0.GTPE2.OUTREFCLK_SEL_INV[0] 28_149 -GTP_CHANNEL_0.GTPE2.OUTREFCLK_SEL_INV[1] 29_149 -GTP_CHANNEL_0.GTPE2.PCS_PCIE_EN 28_216 -GTP_CHANNEL_0.GTPE2.PCS_RSVD_ATTR[0] 30_184 -GTP_CHANNEL_0.GTPE2.PCS_RSVD_ATTR[1] 31_184 -GTP_CHANNEL_0.GTPE2.PCS_RSVD_ATTR[2] 30_185 -GTP_CHANNEL_0.GTPE2.PCS_RSVD_ATTR[3] 31_185 -GTP_CHANNEL_0.GTPE2.PCS_RSVD_ATTR[4] 30_186 -GTP_CHANNEL_0.GTPE2.PCS_RSVD_ATTR[5] 31_186 -GTP_CHANNEL_0.GTPE2.PCS_RSVD_ATTR[6] 30_187 -GTP_CHANNEL_0.GTPE2.PCS_RSVD_ATTR[7] 31_187 -GTP_CHANNEL_0.GTPE2.PCS_RSVD_ATTR[8] 30_188 -GTP_CHANNEL_0.GTPE2.PCS_RSVD_ATTR[9] 31_188 -GTP_CHANNEL_0.GTPE2.PCS_RSVD_ATTR[10] 30_189 -GTP_CHANNEL_0.GTPE2.PCS_RSVD_ATTR[11] 31_189 -GTP_CHANNEL_0.GTPE2.PCS_RSVD_ATTR[12] 30_190 -GTP_CHANNEL_0.GTPE2.PCS_RSVD_ATTR[13] 31_190 -GTP_CHANNEL_0.GTPE2.PCS_RSVD_ATTR[14] 30_191 -GTP_CHANNEL_0.GTPE2.PCS_RSVD_ATTR[15] 31_191 -GTP_CHANNEL_0.GTPE2.PCS_RSVD_ATTR[16] 30_192 -GTP_CHANNEL_0.GTPE2.PCS_RSVD_ATTR[17] 31_192 -GTP_CHANNEL_0.GTPE2.PCS_RSVD_ATTR[18] 30_193 -GTP_CHANNEL_0.GTPE2.PCS_RSVD_ATTR[19] 31_193 -GTP_CHANNEL_0.GTPE2.PCS_RSVD_ATTR[20] 30_194 -GTP_CHANNEL_0.GTPE2.PCS_RSVD_ATTR[21] 31_194 -GTP_CHANNEL_0.GTPE2.PCS_RSVD_ATTR[22] 30_195 -GTP_CHANNEL_0.GTPE2.PCS_RSVD_ATTR[23] 31_195 -GTP_CHANNEL_0.GTPE2.PCS_RSVD_ATTR[24] 30_196 -GTP_CHANNEL_0.GTPE2.PCS_RSVD_ATTR[25] 31_196 -GTP_CHANNEL_0.GTPE2.PCS_RSVD_ATTR[26] 30_197 -GTP_CHANNEL_0.GTPE2.PCS_RSVD_ATTR[27] 31_197 -GTP_CHANNEL_0.GTPE2.PCS_RSVD_ATTR[28] 30_198 -GTP_CHANNEL_0.GTPE2.PCS_RSVD_ATTR[29] 31_198 -GTP_CHANNEL_0.GTPE2.PCS_RSVD_ATTR[30] 30_199 -GTP_CHANNEL_0.GTPE2.PCS_RSVD_ATTR[31] 31_199 -GTP_CHANNEL_0.GTPE2.PCS_RSVD_ATTR[32] 30_200 -GTP_CHANNEL_0.GTPE2.PCS_RSVD_ATTR[33] 31_200 -GTP_CHANNEL_0.GTPE2.PCS_RSVD_ATTR[34] 30_201 -GTP_CHANNEL_0.GTPE2.PCS_RSVD_ATTR[35] 31_201 -GTP_CHANNEL_0.GTPE2.PCS_RSVD_ATTR[36] 30_202 -GTP_CHANNEL_0.GTPE2.PCS_RSVD_ATTR[37] 31_202 -GTP_CHANNEL_0.GTPE2.PCS_RSVD_ATTR[38] 30_203 -GTP_CHANNEL_0.GTPE2.PCS_RSVD_ATTR[39] 31_203 -GTP_CHANNEL_0.GTPE2.PCS_RSVD_ATTR[40] 30_204 -GTP_CHANNEL_0.GTPE2.PCS_RSVD_ATTR[41] 31_204 -GTP_CHANNEL_0.GTPE2.PCS_RSVD_ATTR[42] 30_205 -GTP_CHANNEL_0.GTPE2.PCS_RSVD_ATTR[43] 31_205 -GTP_CHANNEL_0.GTPE2.PCS_RSVD_ATTR[44] 30_206 -GTP_CHANNEL_0.GTPE2.PCS_RSVD_ATTR[45] 31_206 -GTP_CHANNEL_0.GTPE2.PCS_RSVD_ATTR[46] 30_207 -GTP_CHANNEL_0.GTPE2.PCS_RSVD_ATTR[47] 31_207 -GTP_CHANNEL_0.GTPE2.PD_TRANS_TIME_FROM_P2[0] 29_216 -GTP_CHANNEL_0.GTPE2.PD_TRANS_TIME_FROM_P2[1] 28_217 -GTP_CHANNEL_0.GTPE2.PD_TRANS_TIME_FROM_P2[2] 29_217 -GTP_CHANNEL_0.GTPE2.PD_TRANS_TIME_FROM_P2[3] 28_218 -GTP_CHANNEL_0.GTPE2.PD_TRANS_TIME_FROM_P2[4] 29_218 -GTP_CHANNEL_0.GTPE2.PD_TRANS_TIME_FROM_P2[5] 28_219 -GTP_CHANNEL_0.GTPE2.PD_TRANS_TIME_FROM_P2[6] 29_219 -GTP_CHANNEL_0.GTPE2.PD_TRANS_TIME_FROM_P2[7] 28_220 -GTP_CHANNEL_0.GTPE2.PD_TRANS_TIME_FROM_P2[8] 29_220 -GTP_CHANNEL_0.GTPE2.PD_TRANS_TIME_FROM_P2[9] 28_221 -GTP_CHANNEL_0.GTPE2.PD_TRANS_TIME_FROM_P2[10] 29_221 -GTP_CHANNEL_0.GTPE2.PD_TRANS_TIME_FROM_P2[11] 28_222 -GTP_CHANNEL_0.GTPE2.PD_TRANS_TIME_NONE_P2[0] 28_208 -GTP_CHANNEL_0.GTPE2.PD_TRANS_TIME_NONE_P2[1] 29_208 -GTP_CHANNEL_0.GTPE2.PD_TRANS_TIME_NONE_P2[2] 28_209 -GTP_CHANNEL_0.GTPE2.PD_TRANS_TIME_NONE_P2[3] 29_209 -GTP_CHANNEL_0.GTPE2.PD_TRANS_TIME_NONE_P2[4] 28_210 -GTP_CHANNEL_0.GTPE2.PD_TRANS_TIME_NONE_P2[5] 29_210 -GTP_CHANNEL_0.GTPE2.PD_TRANS_TIME_NONE_P2[6] 28_211 -GTP_CHANNEL_0.GTPE2.PD_TRANS_TIME_NONE_P2[7] 29_211 -GTP_CHANNEL_0.GTPE2.PD_TRANS_TIME_TO_P2[0] 28_212 -GTP_CHANNEL_0.GTPE2.PD_TRANS_TIME_TO_P2[1] 29_212 -GTP_CHANNEL_0.GTPE2.PD_TRANS_TIME_TO_P2[2] 28_213 -GTP_CHANNEL_0.GTPE2.PD_TRANS_TIME_TO_P2[3] 29_213 -GTP_CHANNEL_0.GTPE2.PD_TRANS_TIME_TO_P2[4] 28_214 -GTP_CHANNEL_0.GTPE2.PD_TRANS_TIME_TO_P2[5] 29_214 -GTP_CHANNEL_0.GTPE2.PD_TRANS_TIME_TO_P2[6] 28_215 -GTP_CHANNEL_0.GTPE2.PD_TRANS_TIME_TO_P2[7] 29_215 -GTP_CHANNEL_0.GTPE2.PMA_LOOPBACK_CFG[0] 29_207 -GTP_CHANNEL_0.GTPE2.PMA_RSV[0] 30_520 -GTP_CHANNEL_0.GTPE2.PMA_RSV[1] 31_520 -GTP_CHANNEL_0.GTPE2.PMA_RSV[2] 30_521 -GTP_CHANNEL_0.GTPE2.PMA_RSV[3] 31_521 -GTP_CHANNEL_0.GTPE2.PMA_RSV[4] 30_522 -GTP_CHANNEL_0.GTPE2.PMA_RSV[5] 31_522 -GTP_CHANNEL_0.GTPE2.PMA_RSV[6] 30_523 -GTP_CHANNEL_0.GTPE2.PMA_RSV[7] 31_523 -GTP_CHANNEL_0.GTPE2.PMA_RSV[8] 30_524 -GTP_CHANNEL_0.GTPE2.PMA_RSV[9] 31_524 -GTP_CHANNEL_0.GTPE2.PMA_RSV[10] 30_525 -GTP_CHANNEL_0.GTPE2.PMA_RSV[11] 31_525 -GTP_CHANNEL_0.GTPE2.PMA_RSV[12] 30_526 -GTP_CHANNEL_0.GTPE2.PMA_RSV[13] 31_526 -GTP_CHANNEL_0.GTPE2.PMA_RSV[14] 30_527 -GTP_CHANNEL_0.GTPE2.PMA_RSV[15] 31_527 -GTP_CHANNEL_0.GTPE2.PMA_RSV[16] 30_528 -GTP_CHANNEL_0.GTPE2.PMA_RSV[17] 31_528 -GTP_CHANNEL_0.GTPE2.PMA_RSV[18] 30_529 -GTP_CHANNEL_0.GTPE2.PMA_RSV[19] 31_529 -GTP_CHANNEL_0.GTPE2.PMA_RSV[20] 30_530 -GTP_CHANNEL_0.GTPE2.PMA_RSV[21] 31_530 -GTP_CHANNEL_0.GTPE2.PMA_RSV[22] 30_531 -GTP_CHANNEL_0.GTPE2.PMA_RSV[23] 31_531 -GTP_CHANNEL_0.GTPE2.PMA_RSV[24] 30_532 -GTP_CHANNEL_0.GTPE2.PMA_RSV[25] 31_532 -GTP_CHANNEL_0.GTPE2.PMA_RSV[26] 30_533 -GTP_CHANNEL_0.GTPE2.PMA_RSV[27] 31_533 -GTP_CHANNEL_0.GTPE2.PMA_RSV[28] 30_534 -GTP_CHANNEL_0.GTPE2.PMA_RSV[29] 31_534 -GTP_CHANNEL_0.GTPE2.PMA_RSV[30] 30_535 -GTP_CHANNEL_0.GTPE2.PMA_RSV[31] 31_535 -GTP_CHANNEL_0.GTPE2.PMA_RSV2[0] 30_336 -GTP_CHANNEL_0.GTPE2.PMA_RSV2[1] 31_336 -GTP_CHANNEL_0.GTPE2.PMA_RSV2[2] 30_337 -GTP_CHANNEL_0.GTPE2.PMA_RSV2[3] 31_337 -GTP_CHANNEL_0.GTPE2.PMA_RSV2[4] 30_338 -GTP_CHANNEL_0.GTPE2.PMA_RSV2[5] 31_338 -GTP_CHANNEL_0.GTPE2.PMA_RSV2[6] 30_339 -GTP_CHANNEL_0.GTPE2.PMA_RSV2[7] 31_339 -GTP_CHANNEL_0.GTPE2.PMA_RSV2[8] 30_340 -GTP_CHANNEL_0.GTPE2.PMA_RSV2[9] 31_340 -GTP_CHANNEL_0.GTPE2.PMA_RSV2[10] 30_341 -GTP_CHANNEL_0.GTPE2.PMA_RSV2[11] 31_341 -GTP_CHANNEL_0.GTPE2.PMA_RSV2[12] 30_342 -GTP_CHANNEL_0.GTPE2.PMA_RSV2[13] 31_342 -GTP_CHANNEL_0.GTPE2.PMA_RSV2[14] 30_343 -GTP_CHANNEL_0.GTPE2.PMA_RSV2[15] 31_343 -GTP_CHANNEL_0.GTPE2.PMA_RSV2[16] 30_344 -GTP_CHANNEL_0.GTPE2.PMA_RSV2[17] 31_344 -GTP_CHANNEL_0.GTPE2.PMA_RSV2[18] 30_345 -GTP_CHANNEL_0.GTPE2.PMA_RSV2[19] 31_345 -GTP_CHANNEL_0.GTPE2.PMA_RSV2[20] 30_346 -GTP_CHANNEL_0.GTPE2.PMA_RSV2[21] 31_346 -GTP_CHANNEL_0.GTPE2.PMA_RSV2[22] 30_347 -GTP_CHANNEL_0.GTPE2.PMA_RSV2[23] 31_347 -GTP_CHANNEL_0.GTPE2.PMA_RSV2[24] 30_348 -GTP_CHANNEL_0.GTPE2.PMA_RSV2[25] 31_348 -GTP_CHANNEL_0.GTPE2.PMA_RSV2[26] 30_349 -GTP_CHANNEL_0.GTPE2.PMA_RSV2[27] 31_349 -GTP_CHANNEL_0.GTPE2.PMA_RSV2[28] 30_350 -GTP_CHANNEL_0.GTPE2.PMA_RSV2[29] 31_350 -GTP_CHANNEL_0.GTPE2.PMA_RSV2[30] 30_351 -GTP_CHANNEL_0.GTPE2.PMA_RSV2[31] 31_351 -GTP_CHANNEL_0.GTPE2.PMA_RSV3[0] 30_288 -GTP_CHANNEL_0.GTPE2.PMA_RSV3[1] 31_288 -GTP_CHANNEL_0.GTPE2.PMA_RSV4[0] 30_156 -GTP_CHANNEL_0.GTPE2.PMA_RSV4[1] 31_156 -GTP_CHANNEL_0.GTPE2.PMA_RSV4[2] 30_157 -GTP_CHANNEL_0.GTPE2.PMA_RSV4[3] 31_157 -GTP_CHANNEL_0.GTPE2.PMA_RSV5[0] 31_159 -GTP_CHANNEL_0.GTPE2.PMA_RSV6[0] 30_303 -GTP_CHANNEL_0.GTPE2.PMA_RSV7[0] 31_303 -GTP_CHANNEL_0.GTPE2.RX_BIAS_CFG[0] 30_112 -GTP_CHANNEL_0.GTPE2.RX_BIAS_CFG[1] 31_112 -GTP_CHANNEL_0.GTPE2.RX_BIAS_CFG[2] 30_113 -GTP_CHANNEL_0.GTPE2.RX_BIAS_CFG[3] 31_113 -GTP_CHANNEL_0.GTPE2.RX_BIAS_CFG[4] 30_114 -GTP_CHANNEL_0.GTPE2.RX_BIAS_CFG[5] 31_114 -GTP_CHANNEL_0.GTPE2.RX_BIAS_CFG[6] 30_115 -GTP_CHANNEL_0.GTPE2.RX_BIAS_CFG[7] 31_115 -GTP_CHANNEL_0.GTPE2.RX_BIAS_CFG[8] 30_116 -GTP_CHANNEL_0.GTPE2.RX_BIAS_CFG[9] 31_116 -GTP_CHANNEL_0.GTPE2.RX_BIAS_CFG[10] 30_117 -GTP_CHANNEL_0.GTPE2.RX_BIAS_CFG[11] 31_117 -GTP_CHANNEL_0.GTPE2.RX_BIAS_CFG[12] 30_118 -GTP_CHANNEL_0.GTPE2.RX_BIAS_CFG[13] 31_118 -GTP_CHANNEL_0.GTPE2.RX_BIAS_CFG[14] 30_119 -GTP_CHANNEL_0.GTPE2.RX_BIAS_CFG[15] 31_119 -GTP_CHANNEL_0.GTPE2.RX_BUFFER_CFG[0] 30_536 -GTP_CHANNEL_0.GTPE2.RX_BUFFER_CFG[1] 31_536 -GTP_CHANNEL_0.GTPE2.RX_BUFFER_CFG[2] 30_537 -GTP_CHANNEL_0.GTPE2.RX_BUFFER_CFG[3] 31_537 -GTP_CHANNEL_0.GTPE2.RX_BUFFER_CFG[4] 30_538 -GTP_CHANNEL_0.GTPE2.RX_BUFFER_CFG[5] 31_538 -GTP_CHANNEL_0.GTPE2.RX_CLKMUX_EN[0] 30_128 -GTP_CHANNEL_0.GTPE2.RX_CM_SEL[0] 28_138 -GTP_CHANNEL_0.GTPE2.RX_CM_SEL[1] 29_138 -GTP_CHANNEL_0.GTPE2.RX_CM_TRIM[0] 30_304 -GTP_CHANNEL_0.GTPE2.RX_CM_TRIM[1] 31_304 -GTP_CHANNEL_0.GTPE2.RX_CM_TRIM[2] 30_305 -GTP_CHANNEL_0.GTPE2.RX_CM_TRIM[3] 31_305 -GTP_CHANNEL_0.GTPE2.RX_DATA_WIDTH[0] 29_141 -GTP_CHANNEL_0.GTPE2.RX_DATA_WIDTH[1] 28_142 -GTP_CHANNEL_0.GTPE2.RX_DATA_WIDTH[2] 29_142 -GTP_CHANNEL_0.GTPE2.RX_DDI_SEL[0] 28_696 -GTP_CHANNEL_0.GTPE2.RX_DDI_SEL[1] 29_696 -GTP_CHANNEL_0.GTPE2.RX_DDI_SEL[2] 28_697 -GTP_CHANNEL_0.GTPE2.RX_DDI_SEL[3] 29_697 -GTP_CHANNEL_0.GTPE2.RX_DDI_SEL[4] 28_698 -GTP_CHANNEL_0.GTPE2.RX_DDI_SEL[5] 29_698 -GTP_CHANNEL_0.GTPE2.RX_DEBUG_CFG[0] 30_616 -GTP_CHANNEL_0.GTPE2.RX_DEBUG_CFG[1] 31_616 -GTP_CHANNEL_0.GTPE2.RX_DEBUG_CFG[2] 30_617 -GTP_CHANNEL_0.GTPE2.RX_DEBUG_CFG[3] 31_617 -GTP_CHANNEL_0.GTPE2.RX_DEBUG_CFG[4] 30_618 -GTP_CHANNEL_0.GTPE2.RX_DEBUG_CFG[5] 31_618 -GTP_CHANNEL_0.GTPE2.RX_DEBUG_CFG[6] 30_619 -GTP_CHANNEL_0.GTPE2.RX_DEBUG_CFG[7] 31_619 -GTP_CHANNEL_0.GTPE2.RX_DEBUG_CFG[8] 30_620 -GTP_CHANNEL_0.GTPE2.RX_DEBUG_CFG[9] 31_620 -GTP_CHANNEL_0.GTPE2.RX_DEBUG_CFG[10] 30_621 -GTP_CHANNEL_0.GTPE2.RX_DEBUG_CFG[11] 31_621 -GTP_CHANNEL_0.GTPE2.RX_DEBUG_CFG[12] 30_622 -GTP_CHANNEL_0.GTPE2.RX_DEBUG_CFG[13] 31_622 -GTP_CHANNEL_0.GTPE2.RX_DEFER_RESET_BUF_EN 30_552 -GTP_CHANNEL_0.GTPE2.RX_DISPERR_SEQ_MATCH 29_495 -GTP_CHANNEL_0.GTPE2.RX_OS_CFG[0] 28_288 -GTP_CHANNEL_0.GTPE2.RX_OS_CFG[1] 29_288 -GTP_CHANNEL_0.GTPE2.RX_OS_CFG[2] 28_289 -GTP_CHANNEL_0.GTPE2.RX_OS_CFG[3] 29_289 -GTP_CHANNEL_0.GTPE2.RX_OS_CFG[4] 28_290 -GTP_CHANNEL_0.GTPE2.RX_OS_CFG[5] 29_290 -GTP_CHANNEL_0.GTPE2.RX_OS_CFG[6] 28_291 -GTP_CHANNEL_0.GTPE2.RX_OS_CFG[7] 29_291 -GTP_CHANNEL_0.GTPE2.RX_OS_CFG[8] 28_292 -GTP_CHANNEL_0.GTPE2.RX_OS_CFG[9] 29_292 -GTP_CHANNEL_0.GTPE2.RX_OS_CFG[10] 28_293 -GTP_CHANNEL_0.GTPE2.RX_OS_CFG[11] 29_293 -GTP_CHANNEL_0.GTPE2.RX_OS_CFG[12] 28_294 -GTP_CHANNEL_0.GTPE2.RX_SIG_VALID_DLY[0] 28_524 -GTP_CHANNEL_0.GTPE2.RX_SIG_VALID_DLY[1] 29_524 -GTP_CHANNEL_0.GTPE2.RX_SIG_VALID_DLY[2] 28_525 -GTP_CHANNEL_0.GTPE2.RX_SIG_VALID_DLY[3] 29_525 -GTP_CHANNEL_0.GTPE2.RX_SIG_VALID_DLY[4] 28_526 -GTP_CHANNEL_0.GTPE2.RX_XCLK_SEL.RXUSR 28_143 -GTP_CHANNEL_0.GTPE2.RX_CLK25_DIV[0] 28_139 -GTP_CHANNEL_0.GTPE2.RX_CLK25_DIV[1] 29_139 -GTP_CHANNEL_0.GTPE2.RX_CLK25_DIV[2] 28_140 -GTP_CHANNEL_0.GTPE2.RX_CLK25_DIV[3] 29_140 -GTP_CHANNEL_0.GTPE2.RX_CLK25_DIV[4] 28_141 -GTP_CHANNEL_0.GTPE2.RXBUF_ADDR_MODE.FAST 31_555 -GTP_CHANNEL_0.GTPE2.RXBUF_EIDLE_HI_CNT[0] 30_558 -GTP_CHANNEL_0.GTPE2.RXBUF_EIDLE_HI_CNT[1] 31_558 -GTP_CHANNEL_0.GTPE2.RXBUF_EIDLE_HI_CNT[2] 30_559 -GTP_CHANNEL_0.GTPE2.RXBUF_EIDLE_HI_CNT[3] 31_559 -GTP_CHANNEL_0.GTPE2.RXBUF_EIDLE_LO_CNT[0] 30_556 -GTP_CHANNEL_0.GTPE2.RXBUF_EIDLE_LO_CNT[1] 31_556 -GTP_CHANNEL_0.GTPE2.RXBUF_EIDLE_LO_CNT[2] 30_557 -GTP_CHANNEL_0.GTPE2.RXBUF_EIDLE_LO_CNT[3] 31_557 -GTP_CHANNEL_0.GTPE2.RXBUF_EN 30_11 -GTP_CHANNEL_0.GTPE2.RXBUF_RESET_ON_CB_CHANGE 30_560 -GTP_CHANNEL_0.GTPE2.RXBUF_RESET_ON_COMMAALIGN 30_561 -GTP_CHANNEL_0.GTPE2.RXBUF_RESET_ON_EIDLE 30_547 -GTP_CHANNEL_0.GTPE2.RXBUF_RESET_ON_RATE_CHANGE 31_560 -GTP_CHANNEL_0.GTPE2.RXBUF_THRESH_OVFLW[0] 31_552 -GTP_CHANNEL_0.GTPE2.RXBUF_THRESH_OVFLW[1] 30_553 -GTP_CHANNEL_0.GTPE2.RXBUF_THRESH_OVFLW[2] 31_553 -GTP_CHANNEL_0.GTPE2.RXBUF_THRESH_OVFLW[3] 30_554 -GTP_CHANNEL_0.GTPE2.RXBUF_THRESH_OVFLW[4] 31_554 -GTP_CHANNEL_0.GTPE2.RXBUF_THRESH_OVFLW[5] 30_555 -GTP_CHANNEL_0.GTPE2.RXBUF_THRESH_OVRD 30_548 -GTP_CHANNEL_0.GTPE2.RXBUF_THRESH_UNDFLW[0] 30_544 -GTP_CHANNEL_0.GTPE2.RXBUF_THRESH_UNDFLW[1] 31_544 -GTP_CHANNEL_0.GTPE2.RXBUF_THRESH_UNDFLW[2] 30_545 -GTP_CHANNEL_0.GTPE2.RXBUF_THRESH_UNDFLW[3] 31_545 -GTP_CHANNEL_0.GTPE2.RXBUF_THRESH_UNDFLW[4] 30_546 -GTP_CHANNEL_0.GTPE2.RXBUF_THRESH_UNDFLW[5] 31_546 -GTP_CHANNEL_0.GTPE2.RXBUFRESET_TIME[0] 29_101 -GTP_CHANNEL_0.GTPE2.RXBUFRESET_TIME[1] 28_102 -GTP_CHANNEL_0.GTPE2.RXBUFRESET_TIME[2] 29_102 -GTP_CHANNEL_0.GTPE2.RXBUFRESET_TIME[3] 28_103 -GTP_CHANNEL_0.GTPE2.RXBUFRESET_TIME[4] 29_103 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[0] 30_640 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[1] 31_640 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[2] 30_641 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[3] 31_641 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[4] 30_642 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[5] 31_642 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[6] 30_643 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[7] 31_643 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[8] 30_644 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[9] 31_644 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[10] 30_645 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[11] 31_645 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[12] 30_646 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[13] 31_646 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[14] 30_647 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[15] 31_647 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[16] 30_648 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[17] 31_648 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[18] 30_649 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[19] 31_649 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[20] 30_650 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[21] 31_650 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[22] 30_651 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[23] 31_651 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[24] 30_652 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[25] 31_652 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[26] 30_653 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[27] 31_653 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[28] 30_654 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[29] 31_654 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[30] 30_655 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[31] 31_655 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[32] 30_656 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[33] 31_656 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[34] 30_657 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[35] 31_657 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[36] 30_658 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[37] 31_658 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[38] 30_659 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[39] 31_659 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[40] 30_660 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[41] 31_660 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[42] 30_661 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[43] 31_661 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[44] 30_662 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[45] 31_662 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[46] 30_663 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[47] 31_663 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[48] 30_664 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[49] 31_664 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[50] 30_665 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[51] 31_665 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[52] 30_666 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[53] 31_666 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[54] 30_667 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[55] 31_667 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[56] 30_668 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[57] 31_668 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[58] 30_669 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[59] 31_669 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[60] 30_670 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[61] 31_670 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[62] 30_671 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[63] 31_671 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[64] 30_672 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[65] 31_672 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[66] 30_673 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[67] 31_673 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[68] 30_674 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[69] 31_674 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[70] 30_675 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[71] 31_675 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[72] 30_676 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[73] 31_676 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[74] 30_677 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[75] 31_677 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[76] 30_678 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[77] 31_678 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[78] 30_679 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[79] 31_679 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[80] 30_680 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[81] 31_680 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[82] 30_681 -GTP_CHANNEL_0.GTPE2.RXCDR_FR_RESET_ON_EIDLE[0] 30_638 -GTP_CHANNEL_0.GTPE2.RXCDR_HOLD_DURING_EIDLE[0] 31_637 -GTP_CHANNEL_0.GTPE2.RXCDR_LOCK_CFG[0] 30_632 -GTP_CHANNEL_0.GTPE2.RXCDR_LOCK_CFG[1] 31_632 -GTP_CHANNEL_0.GTPE2.RXCDR_LOCK_CFG[2] 30_633 -GTP_CHANNEL_0.GTPE2.RXCDR_LOCK_CFG[3] 31_633 -GTP_CHANNEL_0.GTPE2.RXCDR_LOCK_CFG[4] 30_634 -GTP_CHANNEL_0.GTPE2.RXCDR_LOCK_CFG[5] 31_634 -GTP_CHANNEL_0.GTPE2.RXCDR_PH_RESET_ON_EIDLE[0] 31_638 -GTP_CHANNEL_0.GTPE2.RXCDRFREQRESET_TIME[0] 29_106 -GTP_CHANNEL_0.GTPE2.RXCDRFREQRESET_TIME[1] 28_107 -GTP_CHANNEL_0.GTPE2.RXCDRFREQRESET_TIME[2] 29_107 -GTP_CHANNEL_0.GTPE2.RXCDRFREQRESET_TIME[3] 28_108 -GTP_CHANNEL_0.GTPE2.RXCDRFREQRESET_TIME[4] 29_108 -GTP_CHANNEL_0.GTPE2.RXCDRPHRESET_TIME[0] 28_109 -GTP_CHANNEL_0.GTPE2.RXCDRPHRESET_TIME[1] 29_109 -GTP_CHANNEL_0.GTPE2.RXCDRPHRESET_TIME[2] 28_110 -GTP_CHANNEL_0.GTPE2.RXCDRPHRESET_TIME[3] 29_110 -GTP_CHANNEL_0.GTPE2.RXCDRPHRESET_TIME[4] 28_111 -GTP_CHANNEL_0.GTPE2.RXDLY_CFG[0] 28_680 -GTP_CHANNEL_0.GTPE2.RXDLY_CFG[1] 29_680 -GTP_CHANNEL_0.GTPE2.RXDLY_CFG[2] 28_681 -GTP_CHANNEL_0.GTPE2.RXDLY_CFG[3] 29_681 -GTP_CHANNEL_0.GTPE2.RXDLY_CFG[4] 28_682 -GTP_CHANNEL_0.GTPE2.RXDLY_CFG[5] 29_682 -GTP_CHANNEL_0.GTPE2.RXDLY_CFG[6] 28_683 -GTP_CHANNEL_0.GTPE2.RXDLY_CFG[7] 29_683 -GTP_CHANNEL_0.GTPE2.RXDLY_CFG[8] 28_684 -GTP_CHANNEL_0.GTPE2.RXDLY_CFG[9] 29_684 -GTP_CHANNEL_0.GTPE2.RXDLY_CFG[10] 28_685 -GTP_CHANNEL_0.GTPE2.RXDLY_CFG[11] 29_685 -GTP_CHANNEL_0.GTPE2.RXDLY_CFG[12] 28_686 -GTP_CHANNEL_0.GTPE2.RXDLY_CFG[13] 29_686 -GTP_CHANNEL_0.GTPE2.RXDLY_CFG[14] 28_687 -GTP_CHANNEL_0.GTPE2.RXDLY_CFG[15] 29_687 -GTP_CHANNEL_0.GTPE2.RXDLY_LCFG[0] 30_576 -GTP_CHANNEL_0.GTPE2.RXDLY_LCFG[1] 31_576 -GTP_CHANNEL_0.GTPE2.RXDLY_LCFG[2] 30_577 -GTP_CHANNEL_0.GTPE2.RXDLY_LCFG[3] 31_577 -GTP_CHANNEL_0.GTPE2.RXDLY_LCFG[4] 30_578 -GTP_CHANNEL_0.GTPE2.RXDLY_LCFG[5] 31_578 -GTP_CHANNEL_0.GTPE2.RXDLY_LCFG[6] 30_579 -GTP_CHANNEL_0.GTPE2.RXDLY_LCFG[7] 31_579 -GTP_CHANNEL_0.GTPE2.RXDLY_LCFG[8] 30_580 -GTP_CHANNEL_0.GTPE2.RXDLY_TAP_CFG[0] 28_672 -GTP_CHANNEL_0.GTPE2.RXDLY_TAP_CFG[1] 29_672 -GTP_CHANNEL_0.GTPE2.RXDLY_TAP_CFG[2] 28_673 -GTP_CHANNEL_0.GTPE2.RXDLY_TAP_CFG[3] 29_673 -GTP_CHANNEL_0.GTPE2.RXDLY_TAP_CFG[4] 28_674 -GTP_CHANNEL_0.GTPE2.RXDLY_TAP_CFG[5] 29_674 -GTP_CHANNEL_0.GTPE2.RXDLY_TAP_CFG[6] 28_675 -GTP_CHANNEL_0.GTPE2.RXDLY_TAP_CFG[7] 29_675 -GTP_CHANNEL_0.GTPE2.RXDLY_TAP_CFG[8] 28_676 -GTP_CHANNEL_0.GTPE2.RXDLY_TAP_CFG[9] 29_676 -GTP_CHANNEL_0.GTPE2.RXDLY_TAP_CFG[10] 28_677 -GTP_CHANNEL_0.GTPE2.RXDLY_TAP_CFG[11] 29_677 -GTP_CHANNEL_0.GTPE2.RXDLY_TAP_CFG[12] 28_678 -GTP_CHANNEL_0.GTPE2.RXDLY_TAP_CFG[13] 29_678 -GTP_CHANNEL_0.GTPE2.RXDLY_TAP_CFG[14] 28_679 -GTP_CHANNEL_0.GTPE2.RXDLY_TAP_CFG[15] 29_679 -GTP_CHANNEL_0.GTPE2.RXGEARBOX_EN 29_607 -GTP_CHANNEL_0.GTPE2.RXISCANRESET_TIME[0] 29_123 -GTP_CHANNEL_0.GTPE2.RXISCANRESET_TIME[1] 28_124 -GTP_CHANNEL_0.GTPE2.RXISCANRESET_TIME[2] 29_124 -GTP_CHANNEL_0.GTPE2.RXISCANRESET_TIME[3] 28_125 -GTP_CHANNEL_0.GTPE2.RXISCANRESET_TIME[4] 29_125 -GTP_CHANNEL_0.GTPE2.RXLPM_BIAS_STARTUP_DISABLE[0] 31_391 -GTP_CHANNEL_0.GTPE2.RXLPM_CFG[0] 30_328 -GTP_CHANNEL_0.GTPE2.RXLPM_CFG[1] 31_328 -GTP_CHANNEL_0.GTPE2.RXLPM_CFG[2] 30_329 -GTP_CHANNEL_0.GTPE2.RXLPM_CFG[3] 31_329 -GTP_CHANNEL_0.GTPE2.RXLPM_CM_CFG[0] 30_430 -GTP_CHANNEL_0.GTPE2.RXLPM_GC_CFG[0] 30_432 -GTP_CHANNEL_0.GTPE2.RXLPM_GC_CFG[1] 31_432 -GTP_CHANNEL_0.GTPE2.RXLPM_GC_CFG[2] 30_433 -GTP_CHANNEL_0.GTPE2.RXLPM_GC_CFG[3] 31_433 -GTP_CHANNEL_0.GTPE2.RXLPM_GC_CFG[4] 30_434 -GTP_CHANNEL_0.GTPE2.RXLPM_GC_CFG[5] 31_434 -GTP_CHANNEL_0.GTPE2.RXLPM_GC_CFG[6] 30_435 -GTP_CHANNEL_0.GTPE2.RXLPM_GC_CFG[7] 31_435 -GTP_CHANNEL_0.GTPE2.RXLPM_GC_CFG[8] 30_436 -GTP_CHANNEL_0.GTPE2.RXLPM_GC_CFG2[0] 31_442 -GTP_CHANNEL_0.GTPE2.RXLPM_GC_CFG2[1] 30_443 -GTP_CHANNEL_0.GTPE2.RXLPM_GC_CFG2[2] 31_443 -GTP_CHANNEL_0.GTPE2.RXLPM_HF_CFG[0] 28_336 -GTP_CHANNEL_0.GTPE2.RXLPM_HF_CFG[1] 29_336 -GTP_CHANNEL_0.GTPE2.RXLPM_HF_CFG[2] 28_337 -GTP_CHANNEL_0.GTPE2.RXLPM_HF_CFG[3] 29_337 -GTP_CHANNEL_0.GTPE2.RXLPM_HF_CFG[4] 28_338 -GTP_CHANNEL_0.GTPE2.RXLPM_HF_CFG[5] 29_338 -GTP_CHANNEL_0.GTPE2.RXLPM_HF_CFG[6] 28_339 -GTP_CHANNEL_0.GTPE2.RXLPM_HF_CFG[7] 29_339 -GTP_CHANNEL_0.GTPE2.RXLPM_HF_CFG[8] 28_340 -GTP_CHANNEL_0.GTPE2.RXLPM_HF_CFG[9] 29_340 -GTP_CHANNEL_0.GTPE2.RXLPM_HF_CFG[10] 28_341 -GTP_CHANNEL_0.GTPE2.RXLPM_HF_CFG[11] 29_341 -GTP_CHANNEL_0.GTPE2.RXLPM_HF_CFG[12] 28_342 -GTP_CHANNEL_0.GTPE2.RXLPM_HF_CFG[13] 29_342 -GTP_CHANNEL_0.GTPE2.RXLPM_HF_CFG2[0] 30_424 -GTP_CHANNEL_0.GTPE2.RXLPM_HF_CFG2[1] 31_424 -GTP_CHANNEL_0.GTPE2.RXLPM_HF_CFG2[2] 30_425 -GTP_CHANNEL_0.GTPE2.RXLPM_HF_CFG2[3] 31_425 -GTP_CHANNEL_0.GTPE2.RXLPM_HF_CFG2[4] 30_426 -GTP_CHANNEL_0.GTPE2.RXLPM_HF_CFG3[0] 31_389 -GTP_CHANNEL_0.GTPE2.RXLPM_HF_CFG3[1] 30_390 -GTP_CHANNEL_0.GTPE2.RXLPM_HF_CFG3[2] 31_390 -GTP_CHANNEL_0.GTPE2.RXLPM_HF_CFG3[3] 30_391 -GTP_CHANNEL_0.GTPE2.RXLPM_HOLD_DURING_EIDLE[0] 28_247 -GTP_CHANNEL_0.GTPE2.RXLPM_INCM_CFG[0] 30_439 -GTP_CHANNEL_0.GTPE2.RXLPM_IPCM_CFG[0] 31_439 -GTP_CHANNEL_0.GTPE2.RXLPM_LF_CFG[0] 28_344 -GTP_CHANNEL_0.GTPE2.RXLPM_LF_CFG[1] 29_344 -GTP_CHANNEL_0.GTPE2.RXLPM_LF_CFG[2] 28_345 -GTP_CHANNEL_0.GTPE2.RXLPM_LF_CFG[3] 29_345 -GTP_CHANNEL_0.GTPE2.RXLPM_LF_CFG[4] 28_346 -GTP_CHANNEL_0.GTPE2.RXLPM_LF_CFG[5] 29_346 -GTP_CHANNEL_0.GTPE2.RXLPM_LF_CFG[6] 28_347 -GTP_CHANNEL_0.GTPE2.RXLPM_LF_CFG[7] 29_347 -GTP_CHANNEL_0.GTPE2.RXLPM_LF_CFG[8] 28_348 -GTP_CHANNEL_0.GTPE2.RXLPM_LF_CFG[9] 29_348 -GTP_CHANNEL_0.GTPE2.RXLPM_LF_CFG[10] 28_349 -GTP_CHANNEL_0.GTPE2.RXLPM_LF_CFG[11] 29_349 -GTP_CHANNEL_0.GTPE2.RXLPM_LF_CFG[12] 28_350 -GTP_CHANNEL_0.GTPE2.RXLPM_LF_CFG[13] 29_350 -GTP_CHANNEL_0.GTPE2.RXLPM_LF_CFG[14] 28_351 -GTP_CHANNEL_0.GTPE2.RXLPM_LF_CFG[15] 29_351 -GTP_CHANNEL_0.GTPE2.RXLPM_LF_CFG[16] 28_343 -GTP_CHANNEL_0.GTPE2.RXLPM_LF_CFG[17] 29_343 -GTP_CHANNEL_0.GTPE2.RXLPM_LF_CFG2[0] 31_426 -GTP_CHANNEL_0.GTPE2.RXLPM_LF_CFG2[1] 30_427 -GTP_CHANNEL_0.GTPE2.RXLPM_LF_CFG2[2] 31_427 -GTP_CHANNEL_0.GTPE2.RXLPM_LF_CFG2[3] 30_428 -GTP_CHANNEL_0.GTPE2.RXLPM_LF_CFG2[4] 31_428 -GTP_CHANNEL_0.GTPE2.RXLPM_OSINT_CFG[0] 30_440 -GTP_CHANNEL_0.GTPE2.RXLPM_OSINT_CFG[1] 31_440 -GTP_CHANNEL_0.GTPE2.RXLPM_OSINT_CFG[2] 30_441 -GTP_CHANNEL_0.GTPE2.RXLPM_CFG1[0] 30_330 -GTP_CHANNEL_0.GTPE2.RXLPMRESET_TIME[0] 28_112 -GTP_CHANNEL_0.GTPE2.RXLPMRESET_TIME[1] 29_112 -GTP_CHANNEL_0.GTPE2.RXLPMRESET_TIME[2] 28_113 -GTP_CHANNEL_0.GTPE2.RXLPMRESET_TIME[3] 29_113 -GTP_CHANNEL_0.GTPE2.RXLPMRESET_TIME[4] 28_114 -GTP_CHANNEL_0.GTPE2.RXLPMRESET_TIME[5] 29_114 -GTP_CHANNEL_0.GTPE2.RXLPMRESET_TIME[6] 28_115 -GTP_CHANNEL_0.GTPE2.RXOOB_CFG[0] 28_144 -GTP_CHANNEL_0.GTPE2.RXOOB_CFG[1] 29_144 -GTP_CHANNEL_0.GTPE2.RXOOB_CFG[2] 28_145 -GTP_CHANNEL_0.GTPE2.RXOOB_CFG[3] 29_145 -GTP_CHANNEL_0.GTPE2.RXOOB_CFG[4] 28_146 -GTP_CHANNEL_0.GTPE2.RXOOB_CFG[5] 29_146 -GTP_CHANNEL_0.GTPE2.RXOOB_CFG[6] 28_147 -GTP_CHANNEL_0.GTPE2.RXOOB_CLK_CFG.FABRIC 31_129 -GTP_CHANNEL_0.GTPE2.RXOSCALRESET_TIME[0] 28_187 -GTP_CHANNEL_0.GTPE2.RXOSCALRESET_TIME[1] 29_187 -GTP_CHANNEL_0.GTPE2.RXOSCALRESET_TIME[2] 28_188 -GTP_CHANNEL_0.GTPE2.RXOSCALRESET_TIME[3] 29_188 -GTP_CHANNEL_0.GTPE2.RXOSCALRESET_TIME[4] 28_189 -GTP_CHANNEL_0.GTPE2.RXOSCALRESET_TIMEOUT[0] 29_189 -GTP_CHANNEL_0.GTPE2.RXOSCALRESET_TIMEOUT[1] 28_190 -GTP_CHANNEL_0.GTPE2.RXOSCALRESET_TIMEOUT[2] 29_190 -GTP_CHANNEL_0.GTPE2.RXOSCALRESET_TIMEOUT[3] 28_191 -GTP_CHANNEL_0.GTPE2.RXOSCALRESET_TIMEOUT[4] 29_191 -GTP_CHANNEL_0.GTPE2.RXOUT_DIV[0] 30_384 -GTP_CHANNEL_0.GTPE2.RXOUT_DIV[1] 31_384 -GTP_CHANNEL_0.GTPE2.RXPCSRESET_TIME[0] 29_115 -GTP_CHANNEL_0.GTPE2.RXPCSRESET_TIME[1] 28_116 -GTP_CHANNEL_0.GTPE2.RXPCSRESET_TIME[2] 29_116 -GTP_CHANNEL_0.GTPE2.RXPCSRESET_TIME[3] 28_117 -GTP_CHANNEL_0.GTPE2.RXPCSRESET_TIME[4] 29_117 -GTP_CHANNEL_0.GTPE2.RXPH_CFG[0] 30_584 -GTP_CHANNEL_0.GTPE2.RXPH_CFG[1] 31_584 -GTP_CHANNEL_0.GTPE2.RXPH_CFG[2] 30_585 -GTP_CHANNEL_0.GTPE2.RXPH_CFG[3] 31_585 -GTP_CHANNEL_0.GTPE2.RXPH_CFG[4] 30_586 -GTP_CHANNEL_0.GTPE2.RXPH_CFG[5] 31_586 -GTP_CHANNEL_0.GTPE2.RXPH_CFG[6] 30_587 -GTP_CHANNEL_0.GTPE2.RXPH_CFG[7] 31_587 -GTP_CHANNEL_0.GTPE2.RXPH_CFG[8] 30_588 -GTP_CHANNEL_0.GTPE2.RXPH_CFG[9] 31_588 -GTP_CHANNEL_0.GTPE2.RXPH_CFG[10] 30_589 -GTP_CHANNEL_0.GTPE2.RXPH_CFG[11] 31_589 -GTP_CHANNEL_0.GTPE2.RXPH_CFG[12] 30_590 -GTP_CHANNEL_0.GTPE2.RXPH_CFG[13] 31_590 -GTP_CHANNEL_0.GTPE2.RXPH_CFG[14] 30_591 -GTP_CHANNEL_0.GTPE2.RXPH_CFG[15] 31_591 -GTP_CHANNEL_0.GTPE2.RXPH_CFG[16] 30_592 -GTP_CHANNEL_0.GTPE2.RXPH_CFG[17] 31_592 -GTP_CHANNEL_0.GTPE2.RXPH_CFG[18] 30_593 -GTP_CHANNEL_0.GTPE2.RXPH_CFG[19] 31_593 -GTP_CHANNEL_0.GTPE2.RXPH_CFG[20] 30_594 -GTP_CHANNEL_0.GTPE2.RXPH_CFG[21] 31_594 -GTP_CHANNEL_0.GTPE2.RXPH_CFG[22] 30_595 -GTP_CHANNEL_0.GTPE2.RXPH_CFG[23] 31_595 -GTP_CHANNEL_0.GTPE2.RXPH_MONITOR_SEL[0] 28_700 -GTP_CHANNEL_0.GTPE2.RXPH_MONITOR_SEL[1] 29_700 -GTP_CHANNEL_0.GTPE2.RXPH_MONITOR_SEL[2] 28_701 -GTP_CHANNEL_0.GTPE2.RXPH_MONITOR_SEL[3] 29_701 -GTP_CHANNEL_0.GTPE2.RXPH_MONITOR_SEL[4] 28_702 -GTP_CHANNEL_0.GTPE2.RXPHDLY_CFG[0] 30_600 -GTP_CHANNEL_0.GTPE2.RXPHDLY_CFG[1] 31_600 -GTP_CHANNEL_0.GTPE2.RXPHDLY_CFG[2] 30_601 -GTP_CHANNEL_0.GTPE2.RXPHDLY_CFG[3] 31_601 -GTP_CHANNEL_0.GTPE2.RXPHDLY_CFG[4] 30_602 -GTP_CHANNEL_0.GTPE2.RXPHDLY_CFG[5] 31_602 -GTP_CHANNEL_0.GTPE2.RXPHDLY_CFG[6] 30_603 -GTP_CHANNEL_0.GTPE2.RXPHDLY_CFG[7] 31_603 -GTP_CHANNEL_0.GTPE2.RXPHDLY_CFG[8] 30_604 -GTP_CHANNEL_0.GTPE2.RXPHDLY_CFG[9] 31_604 -GTP_CHANNEL_0.GTPE2.RXPHDLY_CFG[10] 30_605 -GTP_CHANNEL_0.GTPE2.RXPHDLY_CFG[11] 31_605 -GTP_CHANNEL_0.GTPE2.RXPHDLY_CFG[12] 30_606 -GTP_CHANNEL_0.GTPE2.RXPHDLY_CFG[13] 31_606 -GTP_CHANNEL_0.GTPE2.RXPHDLY_CFG[14] 30_607 -GTP_CHANNEL_0.GTPE2.RXPHDLY_CFG[15] 31_607 -GTP_CHANNEL_0.GTPE2.RXPHDLY_CFG[16] 30_608 -GTP_CHANNEL_0.GTPE2.RXPHDLY_CFG[17] 31_608 -GTP_CHANNEL_0.GTPE2.RXPHDLY_CFG[18] 30_609 -GTP_CHANNEL_0.GTPE2.RXPHDLY_CFG[19] 31_609 -GTP_CHANNEL_0.GTPE2.RXPHDLY_CFG[20] 30_610 -GTP_CHANNEL_0.GTPE2.RXPHDLY_CFG[21] 31_610 -GTP_CHANNEL_0.GTPE2.RXPHDLY_CFG[22] 30_611 -GTP_CHANNEL_0.GTPE2.RXPHDLY_CFG[23] 31_611 -GTP_CHANNEL_0.GTPE2.RXPI_CFG0[0] 31_430 -GTP_CHANNEL_0.GTPE2.RXPI_CFG0[1] 30_431 -GTP_CHANNEL_0.GTPE2.RXPI_CFG0[2] 31_431 -GTP_CHANNEL_0.GTPE2.RXPI_CFG1[0] 30_442 -GTP_CHANNEL_0.GTPE2.RXPI_CFG2[0] 31_441 -GTP_CHANNEL_0.GTPE2.RXPMARESET_TIME[0] 28_104 -GTP_CHANNEL_0.GTPE2.RXPMARESET_TIME[1] 29_104 -GTP_CHANNEL_0.GTPE2.RXPMARESET_TIME[2] 28_105 -GTP_CHANNEL_0.GTPE2.RXPMARESET_TIME[3] 29_105 -GTP_CHANNEL_0.GTPE2.RXPMARESET_TIME[4] 28_106 -GTP_CHANNEL_0.GTPE2.RXPRBS_ERR_LOOPBACK[0] 28_136 -GTP_CHANNEL_0.GTPE2.RXSLIDE_AUTO_WAIT[0] 28_520 -GTP_CHANNEL_0.GTPE2.RXSLIDE_AUTO_WAIT[1] 29_520 -GTP_CHANNEL_0.GTPE2.RXSLIDE_AUTO_WAIT[2] 28_521 -GTP_CHANNEL_0.GTPE2.RXSLIDE_AUTO_WAIT[3] 29_521 -GTP_CHANNEL_0.GTPE2.RXSLIDE_MODE.AUTO 28_519 !29_519 -GTP_CHANNEL_0.GTPE2.RXSLIDE_MODE.PCS !28_519 29_519 -GTP_CHANNEL_0.GTPE2.RXSLIDE_MODE.PMA 28_519 29_519 -GTP_CHANNEL_0.GTPE2.RXSYNC_MULTILANE[0] 28_133 -GTP_CHANNEL_0.GTPE2.RXSYNC_OVRD[0] 29_135 -GTP_CHANNEL_0.GTPE2.RXSYNC_SKIP_DA[0] 29_134 -GTP_CHANNEL_0.GTPE2.SAS_MAX_COM[0] 28_171 -GTP_CHANNEL_0.GTPE2.SAS_MAX_COM[1] 29_171 -GTP_CHANNEL_0.GTPE2.SAS_MAX_COM[2] 28_172 -GTP_CHANNEL_0.GTPE2.SAS_MAX_COM[3] 29_172 -GTP_CHANNEL_0.GTPE2.SAS_MAX_COM[4] 28_173 -GTP_CHANNEL_0.GTPE2.SAS_MAX_COM[5] 29_173 -GTP_CHANNEL_0.GTPE2.SAS_MAX_COM[6] 28_174 -GTP_CHANNEL_0.GTPE2.SAS_MIN_COM[0] 29_156 -GTP_CHANNEL_0.GTPE2.SAS_MIN_COM[1] 28_157 -GTP_CHANNEL_0.GTPE2.SAS_MIN_COM[2] 29_157 -GTP_CHANNEL_0.GTPE2.SAS_MIN_COM[3] 28_158 -GTP_CHANNEL_0.GTPE2.SAS_MIN_COM[4] 29_158 -GTP_CHANNEL_0.GTPE2.SAS_MIN_COM[5] 28_159 -GTP_CHANNEL_0.GTPE2.SATA_BURST_SEQ_LEN[0] 28_150 -GTP_CHANNEL_0.GTPE2.SATA_BURST_SEQ_LEN[1] 29_150 -GTP_CHANNEL_0.GTPE2.SATA_BURST_SEQ_LEN[2] 28_151 -GTP_CHANNEL_0.GTPE2.SATA_BURST_SEQ_LEN[3] 29_151 -GTP_CHANNEL_0.GTPE2.SATA_BURST_VAL[0] 29_147 -GTP_CHANNEL_0.GTPE2.SATA_BURST_VAL[1] 28_148 -GTP_CHANNEL_0.GTPE2.SATA_BURST_VAL[2] 29_148 -GTP_CHANNEL_0.GTPE2.SATA_EIDLE_VAL[0] 28_152 -GTP_CHANNEL_0.GTPE2.SATA_EIDLE_VAL[1] 29_152 -GTP_CHANNEL_0.GTPE2.SATA_EIDLE_VAL[2] 28_153 -GTP_CHANNEL_0.GTPE2.SATA_MAX_BURST[0] 28_168 -GTP_CHANNEL_0.GTPE2.SATA_MAX_BURST[1] 29_168 -GTP_CHANNEL_0.GTPE2.SATA_MAX_BURST[2] 28_169 -GTP_CHANNEL_0.GTPE2.SATA_MAX_BURST[3] 29_169 -GTP_CHANNEL_0.GTPE2.SATA_MAX_BURST[4] 28_170 -GTP_CHANNEL_0.GTPE2.SATA_MAX_BURST[5] 29_170 -GTP_CHANNEL_0.GTPE2.SATA_MAX_INIT[0] 28_176 -GTP_CHANNEL_0.GTPE2.SATA_MAX_INIT[1] 29_176 -GTP_CHANNEL_0.GTPE2.SATA_MAX_INIT[2] 28_177 -GTP_CHANNEL_0.GTPE2.SATA_MAX_INIT[3] 29_177 -GTP_CHANNEL_0.GTPE2.SATA_MAX_INIT[4] 28_178 -GTP_CHANNEL_0.GTPE2.SATA_MAX_INIT[5] 29_178 -GTP_CHANNEL_0.GTPE2.SATA_MAX_WAKE[0] 28_179 -GTP_CHANNEL_0.GTPE2.SATA_MAX_WAKE[1] 29_179 -GTP_CHANNEL_0.GTPE2.SATA_MAX_WAKE[2] 28_180 -GTP_CHANNEL_0.GTPE2.SATA_MAX_WAKE[3] 29_180 -GTP_CHANNEL_0.GTPE2.SATA_MAX_WAKE[4] 28_181 -GTP_CHANNEL_0.GTPE2.SATA_MAX_WAKE[5] 29_181 -GTP_CHANNEL_0.GTPE2.SATA_MIN_BURST[0] 29_153 -GTP_CHANNEL_0.GTPE2.SATA_MIN_BURST[1] 28_154 -GTP_CHANNEL_0.GTPE2.SATA_MIN_BURST[2] 29_154 -GTP_CHANNEL_0.GTPE2.SATA_MIN_BURST[3] 28_155 -GTP_CHANNEL_0.GTPE2.SATA_MIN_BURST[4] 29_155 -GTP_CHANNEL_0.GTPE2.SATA_MIN_BURST[5] 28_156 -GTP_CHANNEL_0.GTPE2.SATA_MIN_INIT[0] 28_160 -GTP_CHANNEL_0.GTPE2.SATA_MIN_INIT[1] 29_160 -GTP_CHANNEL_0.GTPE2.SATA_MIN_INIT[2] 28_161 -GTP_CHANNEL_0.GTPE2.SATA_MIN_INIT[3] 29_161 -GTP_CHANNEL_0.GTPE2.SATA_MIN_INIT[4] 28_162 -GTP_CHANNEL_0.GTPE2.SATA_MIN_INIT[5] 29_162 -GTP_CHANNEL_0.GTPE2.SATA_MIN_WAKE[0] 28_163 -GTP_CHANNEL_0.GTPE2.SATA_MIN_WAKE[1] 29_163 -GTP_CHANNEL_0.GTPE2.SATA_MIN_WAKE[2] 28_164 -GTP_CHANNEL_0.GTPE2.SATA_MIN_WAKE[3] 29_164 -GTP_CHANNEL_0.GTPE2.SATA_MIN_WAKE[4] 28_165 -GTP_CHANNEL_0.GTPE2.SATA_MIN_WAKE[5] 29_165 -GTP_CHANNEL_0.GTPE2.SATA_PLL_CFG.VCO_1500MHZ 30_55 -GTP_CHANNEL_0.GTPE2.SATA_PLL_CFG.VCO_750MHZ 31_55 -GTP_CHANNEL_0.GTPE2.SHOW_REALIGN_COMMA 29_522 -GTP_CHANNEL_0.GTPE2.TERM_RCAL_CFG[0] 30_136 -GTP_CHANNEL_0.GTPE2.TERM_RCAL_CFG[1] 31_136 -GTP_CHANNEL_0.GTPE2.TERM_RCAL_CFG[2] 30_137 -GTP_CHANNEL_0.GTPE2.TERM_RCAL_CFG[3] 31_137 -GTP_CHANNEL_0.GTPE2.TERM_RCAL_CFG[4] 30_138 -GTP_CHANNEL_0.GTPE2.TERM_RCAL_CFG[5] 31_138 -GTP_CHANNEL_0.GTPE2.TERM_RCAL_CFG[6] 30_139 -GTP_CHANNEL_0.GTPE2.TERM_RCAL_CFG[7] 31_139 -GTP_CHANNEL_0.GTPE2.TERM_RCAL_CFG[8] 30_140 -GTP_CHANNEL_0.GTPE2.TERM_RCAL_CFG[9] 31_140 -GTP_CHANNEL_0.GTPE2.TERM_RCAL_CFG[10] 30_141 -GTP_CHANNEL_0.GTPE2.TERM_RCAL_CFG[11] 31_141 -GTP_CHANNEL_0.GTPE2.TERM_RCAL_CFG[12] 30_142 -GTP_CHANNEL_0.GTPE2.TERM_RCAL_CFG[13] 31_142 -GTP_CHANNEL_0.GTPE2.TERM_RCAL_CFG[14] 30_143 -GTP_CHANNEL_0.GTPE2.TERM_RCAL_OVRD[0] 31_150 -GTP_CHANNEL_0.GTPE2.TERM_RCAL_OVRD[1] 30_151 -GTP_CHANNEL_0.GTPE2.TERM_RCAL_OVRD[2] 31_151 -GTP_CHANNEL_0.GTPE2.TRANS_TIME_RATE[0] 28_192 -GTP_CHANNEL_0.GTPE2.TRANS_TIME_RATE[1] 29_192 -GTP_CHANNEL_0.GTPE2.TRANS_TIME_RATE[2] 28_193 -GTP_CHANNEL_0.GTPE2.TRANS_TIME_RATE[3] 29_193 -GTP_CHANNEL_0.GTPE2.TRANS_TIME_RATE[4] 28_194 -GTP_CHANNEL_0.GTPE2.TRANS_TIME_RATE[5] 29_194 -GTP_CHANNEL_0.GTPE2.TRANS_TIME_RATE[6] 28_195 -GTP_CHANNEL_0.GTPE2.TRANS_TIME_RATE[7] 29_195 -GTP_CHANNEL_0.GTPE2.TST_RSV[0] 30_504 -GTP_CHANNEL_0.GTPE2.TST_RSV[1] 31_504 -GTP_CHANNEL_0.GTPE2.TST_RSV[2] 30_505 -GTP_CHANNEL_0.GTPE2.TST_RSV[3] 31_505 -GTP_CHANNEL_0.GTPE2.TST_RSV[4] 30_506 -GTP_CHANNEL_0.GTPE2.TST_RSV[5] 31_506 -GTP_CHANNEL_0.GTPE2.TST_RSV[6] 30_507 -GTP_CHANNEL_0.GTPE2.TST_RSV[7] 31_507 -GTP_CHANNEL_0.GTPE2.TST_RSV[8] 30_508 -GTP_CHANNEL_0.GTPE2.TST_RSV[9] 31_508 -GTP_CHANNEL_0.GTPE2.TST_RSV[10] 30_509 -GTP_CHANNEL_0.GTPE2.TST_RSV[11] 31_509 -GTP_CHANNEL_0.GTPE2.TST_RSV[12] 30_510 -GTP_CHANNEL_0.GTPE2.TST_RSV[13] 31_510 -GTP_CHANNEL_0.GTPE2.TST_RSV[14] 30_511 -GTP_CHANNEL_0.GTPE2.TST_RSV[15] 31_511 -GTP_CHANNEL_0.GTPE2.TST_RSV[16] 30_512 -GTP_CHANNEL_0.GTPE2.TST_RSV[17] 31_512 -GTP_CHANNEL_0.GTPE2.TST_RSV[18] 30_513 -GTP_CHANNEL_0.GTPE2.TST_RSV[19] 31_513 -GTP_CHANNEL_0.GTPE2.TST_RSV[20] 30_514 -GTP_CHANNEL_0.GTPE2.TST_RSV[21] 31_514 -GTP_CHANNEL_0.GTPE2.TST_RSV[22] 30_515 -GTP_CHANNEL_0.GTPE2.TST_RSV[23] 31_515 -GTP_CHANNEL_0.GTPE2.TST_RSV[24] 30_516 -GTP_CHANNEL_0.GTPE2.TST_RSV[25] 31_516 -GTP_CHANNEL_0.GTPE2.TST_RSV[26] 30_517 -GTP_CHANNEL_0.GTPE2.TST_RSV[27] 31_517 -GTP_CHANNEL_0.GTPE2.TST_RSV[28] 30_518 -GTP_CHANNEL_0.GTPE2.TST_RSV[29] 31_518 -GTP_CHANNEL_0.GTPE2.TST_RSV[30] 30_519 -GTP_CHANNEL_0.GTPE2.TST_RSV[31] 31_519 -GTP_CHANNEL_0.GTPE2.TX_CLKMUX_EN[0] 31_128 -GTP_CHANNEL_0.GTPE2.TX_DATA_WIDTH[0] 30_152 -GTP_CHANNEL_0.GTPE2.TX_DATA_WIDTH[1] 31_152 -GTP_CHANNEL_0.GTPE2.TX_DATA_WIDTH[2] 30_153 -GTP_CHANNEL_0.GTPE2.TX_DRIVE_MODE.PIPE 28_200 -GTP_CHANNEL_0.GTPE2.TX_EIDLE_ASSERT_DELAY[0] 28_203 -GTP_CHANNEL_0.GTPE2.TX_EIDLE_ASSERT_DELAY[1] 29_203 -GTP_CHANNEL_0.GTPE2.TX_EIDLE_ASSERT_DELAY[2] 28_204 -GTP_CHANNEL_0.GTPE2.TX_EIDLE_DEASSERT_DELAY[0] 29_204 -GTP_CHANNEL_0.GTPE2.TX_EIDLE_DEASSERT_DELAY[1] 28_205 -GTP_CHANNEL_0.GTPE2.TX_EIDLE_DEASSERT_DELAY[2] 29_205 -GTP_CHANNEL_0.GTPE2.TX_LOOPBACK_DRIVE_HIZ 29_202 -GTP_CHANNEL_0.GTPE2.TX_MAINCURSOR_SEL[0] 31_289 -GTP_CHANNEL_0.GTPE2.TX_MARGIN_FULL_0[0] 30_232 -GTP_CHANNEL_0.GTPE2.TX_MARGIN_FULL_0[1] 31_232 -GTP_CHANNEL_0.GTPE2.TX_MARGIN_FULL_0[2] 30_233 -GTP_CHANNEL_0.GTPE2.TX_MARGIN_FULL_0[3] 31_233 -GTP_CHANNEL_0.GTPE2.TX_MARGIN_FULL_0[4] 30_234 -GTP_CHANNEL_0.GTPE2.TX_MARGIN_FULL_0[5] 31_234 -GTP_CHANNEL_0.GTPE2.TX_MARGIN_FULL_0[6] 30_235 -GTP_CHANNEL_0.GTPE2.TX_MARGIN_FULL_1[0] 30_236 -GTP_CHANNEL_0.GTPE2.TX_MARGIN_FULL_1[1] 31_236 -GTP_CHANNEL_0.GTPE2.TX_MARGIN_FULL_1[2] 30_237 -GTP_CHANNEL_0.GTPE2.TX_MARGIN_FULL_1[3] 31_237 -GTP_CHANNEL_0.GTPE2.TX_MARGIN_FULL_1[4] 30_238 -GTP_CHANNEL_0.GTPE2.TX_MARGIN_FULL_1[5] 31_238 -GTP_CHANNEL_0.GTPE2.TX_MARGIN_FULL_1[6] 30_239 -GTP_CHANNEL_0.GTPE2.TX_MARGIN_FULL_2[0] 30_240 -GTP_CHANNEL_0.GTPE2.TX_MARGIN_FULL_2[1] 31_240 -GTP_CHANNEL_0.GTPE2.TX_MARGIN_FULL_2[2] 30_241 -GTP_CHANNEL_0.GTPE2.TX_MARGIN_FULL_2[3] 31_241 -GTP_CHANNEL_0.GTPE2.TX_MARGIN_FULL_2[4] 30_242 -GTP_CHANNEL_0.GTPE2.TX_MARGIN_FULL_2[5] 31_242 -GTP_CHANNEL_0.GTPE2.TX_MARGIN_FULL_2[6] 30_243 -GTP_CHANNEL_0.GTPE2.TX_MARGIN_FULL_3[0] 30_244 -GTP_CHANNEL_0.GTPE2.TX_MARGIN_FULL_3[1] 31_244 -GTP_CHANNEL_0.GTPE2.TX_MARGIN_FULL_3[2] 30_245 -GTP_CHANNEL_0.GTPE2.TX_MARGIN_FULL_3[3] 31_245 -GTP_CHANNEL_0.GTPE2.TX_MARGIN_FULL_3[4] 30_246 -GTP_CHANNEL_0.GTPE2.TX_MARGIN_FULL_3[5] 31_246 -GTP_CHANNEL_0.GTPE2.TX_MARGIN_FULL_3[6] 30_247 -GTP_CHANNEL_0.GTPE2.TX_MARGIN_FULL_4[0] 30_248 -GTP_CHANNEL_0.GTPE2.TX_MARGIN_FULL_4[1] 31_248 -GTP_CHANNEL_0.GTPE2.TX_MARGIN_FULL_4[2] 30_249 -GTP_CHANNEL_0.GTPE2.TX_MARGIN_FULL_4[3] 31_249 -GTP_CHANNEL_0.GTPE2.TX_MARGIN_FULL_4[4] 30_250 -GTP_CHANNEL_0.GTPE2.TX_MARGIN_FULL_4[5] 31_250 -GTP_CHANNEL_0.GTPE2.TX_MARGIN_FULL_4[6] 30_251 -GTP_CHANNEL_0.GTPE2.TX_MARGIN_LOW_0[0] 30_252 -GTP_CHANNEL_0.GTPE2.TX_MARGIN_LOW_0[1] 31_252 -GTP_CHANNEL_0.GTPE2.TX_MARGIN_LOW_0[2] 30_253 -GTP_CHANNEL_0.GTPE2.TX_MARGIN_LOW_0[3] 31_253 -GTP_CHANNEL_0.GTPE2.TX_MARGIN_LOW_0[4] 30_254 -GTP_CHANNEL_0.GTPE2.TX_MARGIN_LOW_0[5] 31_254 -GTP_CHANNEL_0.GTPE2.TX_MARGIN_LOW_0[6] 30_255 -GTP_CHANNEL_0.GTPE2.TX_MARGIN_LOW_1[0] 30_256 -GTP_CHANNEL_0.GTPE2.TX_MARGIN_LOW_1[1] 31_256 -GTP_CHANNEL_0.GTPE2.TX_MARGIN_LOW_1[2] 30_257 -GTP_CHANNEL_0.GTPE2.TX_MARGIN_LOW_1[3] 31_257 -GTP_CHANNEL_0.GTPE2.TX_MARGIN_LOW_1[4] 30_258 -GTP_CHANNEL_0.GTPE2.TX_MARGIN_LOW_1[5] 31_258 -GTP_CHANNEL_0.GTPE2.TX_MARGIN_LOW_1[6] 30_259 -GTP_CHANNEL_0.GTPE2.TX_MARGIN_LOW_2[0] 30_260 -GTP_CHANNEL_0.GTPE2.TX_MARGIN_LOW_2[1] 31_260 -GTP_CHANNEL_0.GTPE2.TX_MARGIN_LOW_2[2] 30_261 -GTP_CHANNEL_0.GTPE2.TX_MARGIN_LOW_2[3] 31_261 -GTP_CHANNEL_0.GTPE2.TX_MARGIN_LOW_2[4] 30_262 -GTP_CHANNEL_0.GTPE2.TX_MARGIN_LOW_2[5] 31_262 -GTP_CHANNEL_0.GTPE2.TX_MARGIN_LOW_2[6] 30_263 -GTP_CHANNEL_0.GTPE2.TX_MARGIN_LOW_3[0] 30_264 -GTP_CHANNEL_0.GTPE2.TX_MARGIN_LOW_3[1] 31_264 -GTP_CHANNEL_0.GTPE2.TX_MARGIN_LOW_3[2] 30_265 -GTP_CHANNEL_0.GTPE2.TX_MARGIN_LOW_3[3] 31_265 -GTP_CHANNEL_0.GTPE2.TX_MARGIN_LOW_3[4] 30_266 -GTP_CHANNEL_0.GTPE2.TX_MARGIN_LOW_3[5] 31_266 -GTP_CHANNEL_0.GTPE2.TX_MARGIN_LOW_3[6] 30_267 -GTP_CHANNEL_0.GTPE2.TX_MARGIN_LOW_4[0] 30_268 -GTP_CHANNEL_0.GTPE2.TX_MARGIN_LOW_4[1] 31_268 -GTP_CHANNEL_0.GTPE2.TX_MARGIN_LOW_4[2] 30_269 -GTP_CHANNEL_0.GTPE2.TX_MARGIN_LOW_4[3] 31_269 -GTP_CHANNEL_0.GTPE2.TX_MARGIN_LOW_4[4] 30_270 -GTP_CHANNEL_0.GTPE2.TX_MARGIN_LOW_4[5] 31_270 -GTP_CHANNEL_0.GTPE2.TX_MARGIN_LOW_4[6] 30_271 -GTP_CHANNEL_0.GTPE2.TX_PREDRIVER_MODE[0] 28_206 -GTP_CHANNEL_0.GTPE2.TX_RXDETECT_CFG[0] 30_296 -GTP_CHANNEL_0.GTPE2.TX_RXDETECT_CFG[1] 31_296 -GTP_CHANNEL_0.GTPE2.TX_RXDETECT_CFG[2] 30_297 -GTP_CHANNEL_0.GTPE2.TX_RXDETECT_CFG[3] 31_297 -GTP_CHANNEL_0.GTPE2.TX_RXDETECT_CFG[4] 30_298 -GTP_CHANNEL_0.GTPE2.TX_RXDETECT_CFG[5] 31_298 -GTP_CHANNEL_0.GTPE2.TX_RXDETECT_CFG[6] 30_299 -GTP_CHANNEL_0.GTPE2.TX_RXDETECT_CFG[7] 31_299 -GTP_CHANNEL_0.GTPE2.TX_RXDETECT_CFG[8] 30_300 -GTP_CHANNEL_0.GTPE2.TX_RXDETECT_CFG[9] 31_300 -GTP_CHANNEL_0.GTPE2.TX_RXDETECT_CFG[10] 30_301 -GTP_CHANNEL_0.GTPE2.TX_RXDETECT_CFG[11] 31_301 -GTP_CHANNEL_0.GTPE2.TX_RXDETECT_CFG[12] 30_302 -GTP_CHANNEL_0.GTPE2.TX_RXDETECT_CFG[13] 31_302 -GTP_CHANNEL_0.GTPE2.TX_RXDETECT_REF[0] 30_292 -GTP_CHANNEL_0.GTPE2.TX_RXDETECT_REF[1] 31_292 -GTP_CHANNEL_0.GTPE2.TX_RXDETECT_REF[2] 30_293 -GTP_CHANNEL_0.GTPE2.TX_XCLK_SEL.TXUSR 31_11 -GTP_CHANNEL_0.GTPE2.TX_CLK25_DIV[0] 30_144 -GTP_CHANNEL_0.GTPE2.TX_CLK25_DIV[1] 31_144 -GTP_CHANNEL_0.GTPE2.TX_CLK25_DIV[2] 30_145 -GTP_CHANNEL_0.GTPE2.TX_CLK25_DIV[3] 31_145 -GTP_CHANNEL_0.GTPE2.TX_CLK25_DIV[4] 30_146 -GTP_CHANNEL_0.GTPE2.TX_DEEMPH0[0] 30_272 -GTP_CHANNEL_0.GTPE2.TX_DEEMPH0[1] 31_272 -GTP_CHANNEL_0.GTPE2.TX_DEEMPH0[2] 30_273 -GTP_CHANNEL_0.GTPE2.TX_DEEMPH0[3] 31_273 -GTP_CHANNEL_0.GTPE2.TX_DEEMPH0[4] 30_274 -GTP_CHANNEL_0.GTPE2.TX_DEEMPH0[5] 31_274 -GTP_CHANNEL_0.GTPE2.TX_DEEMPH1[0] 30_276 -GTP_CHANNEL_0.GTPE2.TX_DEEMPH1[1] 31_276 -GTP_CHANNEL_0.GTPE2.TX_DEEMPH1[2] 30_277 -GTP_CHANNEL_0.GTPE2.TX_DEEMPH1[3] 31_277 -GTP_CHANNEL_0.GTPE2.TX_DEEMPH1[4] 30_278 -GTP_CHANNEL_0.GTPE2.TX_DEEMPH1[5] 31_278 -GTP_CHANNEL_0.GTPE2.TXBUF_EN 28_231 -GTP_CHANNEL_0.GTPE2.TXBUF_RESET_ON_RATE_CHANGE 29_231 -GTP_CHANNEL_0.GTPE2.TXDLY_CFG[0] 30_80 -GTP_CHANNEL_0.GTPE2.TXDLY_CFG[1] 31_80 -GTP_CHANNEL_0.GTPE2.TXDLY_CFG[2] 30_81 -GTP_CHANNEL_0.GTPE2.TXDLY_CFG[3] 31_81 -GTP_CHANNEL_0.GTPE2.TXDLY_CFG[4] 30_82 -GTP_CHANNEL_0.GTPE2.TXDLY_CFG[5] 31_82 -GTP_CHANNEL_0.GTPE2.TXDLY_CFG[6] 30_83 -GTP_CHANNEL_0.GTPE2.TXDLY_CFG[7] 31_83 -GTP_CHANNEL_0.GTPE2.TXDLY_CFG[8] 30_84 -GTP_CHANNEL_0.GTPE2.TXDLY_CFG[9] 31_84 -GTP_CHANNEL_0.GTPE2.TXDLY_CFG[10] 30_85 -GTP_CHANNEL_0.GTPE2.TXDLY_CFG[11] 31_85 -GTP_CHANNEL_0.GTPE2.TXDLY_CFG[12] 30_86 -GTP_CHANNEL_0.GTPE2.TXDLY_CFG[13] 31_86 -GTP_CHANNEL_0.GTPE2.TXDLY_CFG[14] 30_87 -GTP_CHANNEL_0.GTPE2.TXDLY_CFG[15] 31_87 -GTP_CHANNEL_0.GTPE2.TXDLY_LCFG[0] 30_568 -GTP_CHANNEL_0.GTPE2.TXDLY_LCFG[1] 31_568 -GTP_CHANNEL_0.GTPE2.TXDLY_LCFG[2] 30_569 -GTP_CHANNEL_0.GTPE2.TXDLY_LCFG[3] 31_569 -GTP_CHANNEL_0.GTPE2.TXDLY_LCFG[4] 30_570 -GTP_CHANNEL_0.GTPE2.TXDLY_LCFG[5] 31_570 -GTP_CHANNEL_0.GTPE2.TXDLY_LCFG[6] 30_571 -GTP_CHANNEL_0.GTPE2.TXDLY_LCFG[7] 31_571 -GTP_CHANNEL_0.GTPE2.TXDLY_LCFG[8] 30_572 -GTP_CHANNEL_0.GTPE2.TXDLY_TAP_CFG[0] 30_88 -GTP_CHANNEL_0.GTPE2.TXDLY_TAP_CFG[1] 31_88 -GTP_CHANNEL_0.GTPE2.TXDLY_TAP_CFG[2] 30_89 -GTP_CHANNEL_0.GTPE2.TXDLY_TAP_CFG[3] 31_89 -GTP_CHANNEL_0.GTPE2.TXDLY_TAP_CFG[4] 30_90 -GTP_CHANNEL_0.GTPE2.TXDLY_TAP_CFG[5] 31_90 -GTP_CHANNEL_0.GTPE2.TXDLY_TAP_CFG[6] 30_91 -GTP_CHANNEL_0.GTPE2.TXDLY_TAP_CFG[7] 31_91 -GTP_CHANNEL_0.GTPE2.TXDLY_TAP_CFG[8] 30_92 -GTP_CHANNEL_0.GTPE2.TXDLY_TAP_CFG[9] 31_92 -GTP_CHANNEL_0.GTPE2.TXDLY_TAP_CFG[10] 30_93 -GTP_CHANNEL_0.GTPE2.TXDLY_TAP_CFG[11] 31_93 -GTP_CHANNEL_0.GTPE2.TXDLY_TAP_CFG[12] 30_94 -GTP_CHANNEL_0.GTPE2.TXDLY_TAP_CFG[13] 31_94 -GTP_CHANNEL_0.GTPE2.TXDLY_TAP_CFG[14] 30_95 -GTP_CHANNEL_0.GTPE2.TXDLY_TAP_CFG[15] 31_95 -GTP_CHANNEL_0.GTPE2.TXGEARBOX_EN 29_226 -GTP_CHANNEL_0.GTPE2.TXOOB_CFG[0] 31_20 -GTP_CHANNEL_0.GTPE2.TXOUT_DIV[0] 30_386 -GTP_CHANNEL_0.GTPE2.TXOUT_DIV[1] 31_386 -GTP_CHANNEL_0.GTPE2.TXPCSRESET_TIME[0] 29_130 -GTP_CHANNEL_0.GTPE2.TXPCSRESET_TIME[1] 28_131 -GTP_CHANNEL_0.GTPE2.TXPCSRESET_TIME[2] 29_131 -GTP_CHANNEL_0.GTPE2.TXPCSRESET_TIME[3] 28_132 -GTP_CHANNEL_0.GTPE2.TXPCSRESET_TIME[4] 29_132 -GTP_CHANNEL_0.GTPE2.TXPH_CFG[0] 30_96 -GTP_CHANNEL_0.GTPE2.TXPH_CFG[1] 31_96 -GTP_CHANNEL_0.GTPE2.TXPH_CFG[2] 30_97 -GTP_CHANNEL_0.GTPE2.TXPH_CFG[3] 31_97 -GTP_CHANNEL_0.GTPE2.TXPH_CFG[4] 30_98 -GTP_CHANNEL_0.GTPE2.TXPH_CFG[5] 31_98 -GTP_CHANNEL_0.GTPE2.TXPH_CFG[6] 30_99 -GTP_CHANNEL_0.GTPE2.TXPH_CFG[7] 31_99 -GTP_CHANNEL_0.GTPE2.TXPH_CFG[8] 30_100 -GTP_CHANNEL_0.GTPE2.TXPH_CFG[9] 31_100 -GTP_CHANNEL_0.GTPE2.TXPH_CFG[10] 30_101 -GTP_CHANNEL_0.GTPE2.TXPH_CFG[11] 31_101 -GTP_CHANNEL_0.GTPE2.TXPH_CFG[12] 30_102 -GTP_CHANNEL_0.GTPE2.TXPH_CFG[13] 31_102 -GTP_CHANNEL_0.GTPE2.TXPH_CFG[14] 30_103 -GTP_CHANNEL_0.GTPE2.TXPH_CFG[15] 31_103 -GTP_CHANNEL_0.GTPE2.TXPH_MONITOR_SEL[0] 30_108 -GTP_CHANNEL_0.GTPE2.TXPH_MONITOR_SEL[1] 31_108 -GTP_CHANNEL_0.GTPE2.TXPH_MONITOR_SEL[2] 30_109 -GTP_CHANNEL_0.GTPE2.TXPH_MONITOR_SEL[3] 31_109 -GTP_CHANNEL_0.GTPE2.TXPH_MONITOR_SEL[4] 30_110 -GTP_CHANNEL_0.GTPE2.TXPHDLY_CFG[0] 30_64 -GTP_CHANNEL_0.GTPE2.TXPHDLY_CFG[1] 31_64 -GTP_CHANNEL_0.GTPE2.TXPHDLY_CFG[2] 30_65 -GTP_CHANNEL_0.GTPE2.TXPHDLY_CFG[3] 31_65 -GTP_CHANNEL_0.GTPE2.TXPHDLY_CFG[4] 30_66 -GTP_CHANNEL_0.GTPE2.TXPHDLY_CFG[5] 31_66 -GTP_CHANNEL_0.GTPE2.TXPHDLY_CFG[6] 30_67 -GTP_CHANNEL_0.GTPE2.TXPHDLY_CFG[7] 31_67 -GTP_CHANNEL_0.GTPE2.TXPHDLY_CFG[8] 30_68 -GTP_CHANNEL_0.GTPE2.TXPHDLY_CFG[9] 31_68 -GTP_CHANNEL_0.GTPE2.TXPHDLY_CFG[10] 30_69 -GTP_CHANNEL_0.GTPE2.TXPHDLY_CFG[11] 31_69 -GTP_CHANNEL_0.GTPE2.TXPHDLY_CFG[12] 30_70 -GTP_CHANNEL_0.GTPE2.TXPHDLY_CFG[13] 31_70 -GTP_CHANNEL_0.GTPE2.TXPHDLY_CFG[14] 30_71 -GTP_CHANNEL_0.GTPE2.TXPHDLY_CFG[15] 31_71 -GTP_CHANNEL_0.GTPE2.TXPHDLY_CFG[16] 30_72 -GTP_CHANNEL_0.GTPE2.TXPHDLY_CFG[17] 31_72 -GTP_CHANNEL_0.GTPE2.TXPHDLY_CFG[18] 30_73 -GTP_CHANNEL_0.GTPE2.TXPHDLY_CFG[19] 31_73 -GTP_CHANNEL_0.GTPE2.TXPHDLY_CFG[20] 30_74 -GTP_CHANNEL_0.GTPE2.TXPHDLY_CFG[21] 31_74 -GTP_CHANNEL_0.GTPE2.TXPHDLY_CFG[22] 30_75 -GTP_CHANNEL_0.GTPE2.TXPHDLY_CFG[23] 31_75 -GTP_CHANNEL_0.GTPE2.TXPI_GREY_SEL[0] 31_498 -GTP_CHANNEL_0.GTPE2.TXPI_INVSTROBE_SEL[0] 30_498 -GTP_CHANNEL_0.GTPE2.TXPI_PPM_CFG[0] 30_488 -GTP_CHANNEL_0.GTPE2.TXPI_PPM_CFG[1] 31_488 -GTP_CHANNEL_0.GTPE2.TXPI_PPM_CFG[2] 30_489 -GTP_CHANNEL_0.GTPE2.TXPI_PPM_CFG[3] 31_489 -GTP_CHANNEL_0.GTPE2.TXPI_PPM_CFG[4] 30_490 -GTP_CHANNEL_0.GTPE2.TXPI_PPM_CFG[5] 31_490 -GTP_CHANNEL_0.GTPE2.TXPI_PPM_CFG[6] 30_491 -GTP_CHANNEL_0.GTPE2.TXPI_PPM_CFG[7] 31_491 -GTP_CHANNEL_0.GTPE2.TXPI_PPMCLK_SEL.TXUSRCLK2 31_497 -GTP_CHANNEL_0.GTPE2.TXPI_SYNFREQ_PPM[0] 30_496 -GTP_CHANNEL_0.GTPE2.TXPI_SYNFREQ_PPM[1] 31_496 -GTP_CHANNEL_0.GTPE2.TXPI_SYNFREQ_PPM[2] 30_497 -GTP_CHANNEL_0.GTPE2.TXPI_CFG0[0] 30_40 -GTP_CHANNEL_0.GTPE2.TXPI_CFG0[1] 31_40 -GTP_CHANNEL_0.GTPE2.TXPI_CFG1[0] 30_41 -GTP_CHANNEL_0.GTPE2.TXPI_CFG1[1] 31_41 -GTP_CHANNEL_0.GTPE2.TXPI_CFG2[0] 30_42 -GTP_CHANNEL_0.GTPE2.TXPI_CFG2[1] 31_42 -GTP_CHANNEL_0.GTPE2.TXPI_CFG3[0] 30_43 -GTP_CHANNEL_0.GTPE2.TXPI_CFG4[0] 31_43 -GTP_CHANNEL_0.GTPE2.TXPI_CFG5[0] 30_44 -GTP_CHANNEL_0.GTPE2.TXPI_CFG5[1] 31_44 -GTP_CHANNEL_0.GTPE2.TXPI_CFG5[2] 30_45 -GTP_CHANNEL_0.GTPE2.TXPMARESET_TIME[0] 28_128 -GTP_CHANNEL_0.GTPE2.TXPMARESET_TIME[1] 29_128 -GTP_CHANNEL_0.GTPE2.TXPMARESET_TIME[2] 28_129 -GTP_CHANNEL_0.GTPE2.TXPMARESET_TIME[3] 29_129 -GTP_CHANNEL_0.GTPE2.TXPMARESET_TIME[4] 28_130 -GTP_CHANNEL_0.GTPE2.TXSYNC_MULTILANE[0] 29_133 -GTP_CHANNEL_0.GTPE2.TXSYNC_OVRD[0] 28_135 -GTP_CHANNEL_0.GTPE2.TXSYNC_SKIP_DA[0] 28_134 -GTP_CHANNEL_0.GTPE2.UCODEER_CLR[0] 29_00 -GTP_CHANNEL_0.GTPE2.USE_PCS_CLK_PHASE_SEL[0] 30_463 -GTP_CHANNEL_0.GTPE2.ZINV_DMONITORCLK 30_13 -GTP_CHANNEL_0.GTPE2.ZINV_DRPCLK 30_00 -GTP_CHANNEL_0.GTPE2.ZINV_RXUSRCLK 31_01 -GTP_CHANNEL_0.GTPE2.ZINV_SIGVALIDCLK 31_13 -GTP_CHANNEL_0.GTPE2.ZINV_TXPHDLYTSTCLK 30_03 -GTP_CHANNEL_0.GTPE2.ZINV_TXUSRCLK 31_04 -GTP_CHANNEL_0.GTPE2.ZINV_CLKRSVD0 30_23 -GTP_CHANNEL_0.GTPE2.ZINV_CLKRSVD1 31_23 -GTP_CHANNEL_0.GTPE2.ZINV_RXUSRCLK2 30_02 -GTP_CHANNEL_0.GTPE2.ZINV_TXUSRCLK2 30_05 +GTP_CHANNEL_0.GTPE2_CHANNEL.ACJTAG_DEBUG_MODE[0] 28_07 +GTP_CHANNEL_0.GTPE2_CHANNEL.ACJTAG_MODE[0] 29_06 +GTP_CHANNEL_0.GTPE2_CHANNEL.ACJTAG_RESET[0] 29_07 +GTP_CHANNEL_0.GTPE2_CHANNEL.ADAPT_CFG0[0] 30_464 +GTP_CHANNEL_0.GTPE2_CHANNEL.ADAPT_CFG0[1] 31_464 +GTP_CHANNEL_0.GTPE2_CHANNEL.ADAPT_CFG0[2] 30_465 +GTP_CHANNEL_0.GTPE2_CHANNEL.ADAPT_CFG0[3] 31_465 +GTP_CHANNEL_0.GTPE2_CHANNEL.ADAPT_CFG0[4] 30_466 +GTP_CHANNEL_0.GTPE2_CHANNEL.ADAPT_CFG0[5] 31_466 +GTP_CHANNEL_0.GTPE2_CHANNEL.ADAPT_CFG0[6] 30_467 +GTP_CHANNEL_0.GTPE2_CHANNEL.ADAPT_CFG0[7] 31_467 +GTP_CHANNEL_0.GTPE2_CHANNEL.ADAPT_CFG0[8] 30_468 +GTP_CHANNEL_0.GTPE2_CHANNEL.ADAPT_CFG0[9] 31_468 +GTP_CHANNEL_0.GTPE2_CHANNEL.ADAPT_CFG0[10] 30_469 +GTP_CHANNEL_0.GTPE2_CHANNEL.ADAPT_CFG0[11] 31_469 +GTP_CHANNEL_0.GTPE2_CHANNEL.ADAPT_CFG0[12] 30_470 +GTP_CHANNEL_0.GTPE2_CHANNEL.ADAPT_CFG0[13] 31_470 +GTP_CHANNEL_0.GTPE2_CHANNEL.ADAPT_CFG0[14] 30_471 +GTP_CHANNEL_0.GTPE2_CHANNEL.ADAPT_CFG0[15] 31_471 +GTP_CHANNEL_0.GTPE2_CHANNEL.ADAPT_CFG0[16] 30_472 +GTP_CHANNEL_0.GTPE2_CHANNEL.ADAPT_CFG0[17] 31_472 +GTP_CHANNEL_0.GTPE2_CHANNEL.ADAPT_CFG0[18] 30_473 +GTP_CHANNEL_0.GTPE2_CHANNEL.ADAPT_CFG0[19] 31_473 +GTP_CHANNEL_0.GTPE2_CHANNEL.ALIGN_COMMA_DOUBLE 28_522 +GTP_CHANNEL_0.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[0] 28_496 +GTP_CHANNEL_0.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[1] 29_496 +GTP_CHANNEL_0.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[2] 28_497 +GTP_CHANNEL_0.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[3] 29_497 +GTP_CHANNEL_0.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[4] 28_498 +GTP_CHANNEL_0.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[5] 29_498 +GTP_CHANNEL_0.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[6] 28_499 +GTP_CHANNEL_0.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[7] 29_499 +GTP_CHANNEL_0.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[8] 28_500 +GTP_CHANNEL_0.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[9] 29_500 +GTP_CHANNEL_0.GTPE2_CHANNEL.ALIGN_COMMA_WORD[0] 29_526 +GTP_CHANNEL_0.GTPE2_CHANNEL.ALIGN_COMMA_WORD[1] 28_527 +GTP_CHANNEL_0.GTPE2_CHANNEL.ALIGN_MCOMMA_DET 28_523 +GTP_CHANNEL_0.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[0] 28_504 +GTP_CHANNEL_0.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[1] 29_504 +GTP_CHANNEL_0.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[2] 28_505 +GTP_CHANNEL_0.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[3] 29_505 +GTP_CHANNEL_0.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[4] 28_506 +GTP_CHANNEL_0.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[5] 29_506 +GTP_CHANNEL_0.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[6] 28_507 +GTP_CHANNEL_0.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[7] 29_507 +GTP_CHANNEL_0.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[8] 28_508 +GTP_CHANNEL_0.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[9] 29_508 +GTP_CHANNEL_0.GTPE2_CHANNEL.ALIGN_PCOMMA_DET 29_523 +GTP_CHANNEL_0.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[0] 28_512 +GTP_CHANNEL_0.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[1] 29_512 +GTP_CHANNEL_0.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[2] 28_513 +GTP_CHANNEL_0.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[3] 29_513 +GTP_CHANNEL_0.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[4] 28_514 +GTP_CHANNEL_0.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[5] 29_514 +GTP_CHANNEL_0.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[6] 28_515 +GTP_CHANNEL_0.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[7] 29_515 +GTP_CHANNEL_0.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[8] 28_516 +GTP_CHANNEL_0.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[9] 29_516 +GTP_CHANNEL_0.GTPE2_CHANNEL.CBCC_DATA_SOURCE_SEL.DECODED 29_661 +GTP_CHANNEL_0.GTPE2_CHANNEL.CFOK_CFG[0] 30_392 +GTP_CHANNEL_0.GTPE2_CHANNEL.CFOK_CFG[1] 31_392 +GTP_CHANNEL_0.GTPE2_CHANNEL.CFOK_CFG[2] 30_393 +GTP_CHANNEL_0.GTPE2_CHANNEL.CFOK_CFG[3] 31_393 +GTP_CHANNEL_0.GTPE2_CHANNEL.CFOK_CFG[4] 30_394 +GTP_CHANNEL_0.GTPE2_CHANNEL.CFOK_CFG[5] 31_394 +GTP_CHANNEL_0.GTPE2_CHANNEL.CFOK_CFG[6] 30_395 +GTP_CHANNEL_0.GTPE2_CHANNEL.CFOK_CFG[7] 31_395 +GTP_CHANNEL_0.GTPE2_CHANNEL.CFOK_CFG[8] 30_396 +GTP_CHANNEL_0.GTPE2_CHANNEL.CFOK_CFG[9] 31_396 +GTP_CHANNEL_0.GTPE2_CHANNEL.CFOK_CFG[10] 30_397 +GTP_CHANNEL_0.GTPE2_CHANNEL.CFOK_CFG[11] 31_397 +GTP_CHANNEL_0.GTPE2_CHANNEL.CFOK_CFG[12] 30_398 +GTP_CHANNEL_0.GTPE2_CHANNEL.CFOK_CFG[13] 31_398 +GTP_CHANNEL_0.GTPE2_CHANNEL.CFOK_CFG[14] 30_399 +GTP_CHANNEL_0.GTPE2_CHANNEL.CFOK_CFG[15] 31_399 +GTP_CHANNEL_0.GTPE2_CHANNEL.CFOK_CFG[16] 30_400 +GTP_CHANNEL_0.GTPE2_CHANNEL.CFOK_CFG[17] 31_400 +GTP_CHANNEL_0.GTPE2_CHANNEL.CFOK_CFG[18] 30_401 +GTP_CHANNEL_0.GTPE2_CHANNEL.CFOK_CFG[19] 31_401 +GTP_CHANNEL_0.GTPE2_CHANNEL.CFOK_CFG[20] 30_402 +GTP_CHANNEL_0.GTPE2_CHANNEL.CFOK_CFG[21] 31_402 +GTP_CHANNEL_0.GTPE2_CHANNEL.CFOK_CFG[22] 30_403 +GTP_CHANNEL_0.GTPE2_CHANNEL.CFOK_CFG[23] 31_403 +GTP_CHANNEL_0.GTPE2_CHANNEL.CFOK_CFG[24] 30_404 +GTP_CHANNEL_0.GTPE2_CHANNEL.CFOK_CFG[25] 31_404 +GTP_CHANNEL_0.GTPE2_CHANNEL.CFOK_CFG[26] 30_405 +GTP_CHANNEL_0.GTPE2_CHANNEL.CFOK_CFG[27] 31_405 +GTP_CHANNEL_0.GTPE2_CHANNEL.CFOK_CFG[28] 30_406 +GTP_CHANNEL_0.GTPE2_CHANNEL.CFOK_CFG[29] 31_406 +GTP_CHANNEL_0.GTPE2_CHANNEL.CFOK_CFG[30] 30_407 +GTP_CHANNEL_0.GTPE2_CHANNEL.CFOK_CFG[31] 31_407 +GTP_CHANNEL_0.GTPE2_CHANNEL.CFOK_CFG[32] 30_408 +GTP_CHANNEL_0.GTPE2_CHANNEL.CFOK_CFG[33] 31_408 +GTP_CHANNEL_0.GTPE2_CHANNEL.CFOK_CFG[34] 30_409 +GTP_CHANNEL_0.GTPE2_CHANNEL.CFOK_CFG[35] 31_409 +GTP_CHANNEL_0.GTPE2_CHANNEL.CFOK_CFG[36] 30_410 +GTP_CHANNEL_0.GTPE2_CHANNEL.CFOK_CFG[37] 31_410 +GTP_CHANNEL_0.GTPE2_CHANNEL.CFOK_CFG[38] 30_411 +GTP_CHANNEL_0.GTPE2_CHANNEL.CFOK_CFG[39] 31_411 +GTP_CHANNEL_0.GTPE2_CHANNEL.CFOK_CFG[40] 30_412 +GTP_CHANNEL_0.GTPE2_CHANNEL.CFOK_CFG[41] 31_412 +GTP_CHANNEL_0.GTPE2_CHANNEL.CFOK_CFG[42] 30_413 +GTP_CHANNEL_0.GTPE2_CHANNEL.CFOK_CFG2[0] 30_459 +GTP_CHANNEL_0.GTPE2_CHANNEL.CFOK_CFG2[1] 31_459 +GTP_CHANNEL_0.GTPE2_CHANNEL.CFOK_CFG2[2] 30_460 +GTP_CHANNEL_0.GTPE2_CHANNEL.CFOK_CFG2[3] 31_460 +GTP_CHANNEL_0.GTPE2_CHANNEL.CFOK_CFG2[4] 30_461 +GTP_CHANNEL_0.GTPE2_CHANNEL.CFOK_CFG2[5] 31_461 +GTP_CHANNEL_0.GTPE2_CHANNEL.CFOK_CFG2[6] 30_462 +GTP_CHANNEL_0.GTPE2_CHANNEL.CFOK_CFG3[0] 30_416 +GTP_CHANNEL_0.GTPE2_CHANNEL.CFOK_CFG3[1] 31_416 +GTP_CHANNEL_0.GTPE2_CHANNEL.CFOK_CFG3[2] 30_417 +GTP_CHANNEL_0.GTPE2_CHANNEL.CFOK_CFG3[3] 31_417 +GTP_CHANNEL_0.GTPE2_CHANNEL.CFOK_CFG3[4] 30_418 +GTP_CHANNEL_0.GTPE2_CHANNEL.CFOK_CFG3[5] 31_418 +GTP_CHANNEL_0.GTPE2_CHANNEL.CFOK_CFG3[6] 30_419 +GTP_CHANNEL_0.GTPE2_CHANNEL.CFOK_CFG4[0] 31_438 +GTP_CHANNEL_0.GTPE2_CHANNEL.CFOK_CFG5[0] 30_429 +GTP_CHANNEL_0.GTPE2_CHANNEL.CFOK_CFG5[1] 31_429 +GTP_CHANNEL_0.GTPE2_CHANNEL.CFOK_CFG6[0] 31_436 +GTP_CHANNEL_0.GTPE2_CHANNEL.CFOK_CFG6[1] 30_437 +GTP_CHANNEL_0.GTPE2_CHANNEL.CFOK_CFG6[2] 31_437 +GTP_CHANNEL_0.GTPE2_CHANNEL.CFOK_CFG6[3] 30_438 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_KEEP_ALIGN 29_631 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_MAX_SKEW[0] 28_670 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_MAX_SKEW[1] 29_670 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_MAX_SKEW[2] 28_671 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_MAX_SKEW[3] 29_671 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[0] 28_608 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[1] 29_608 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[2] 28_609 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[3] 29_609 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[4] 28_610 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[5] 29_610 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[6] 28_611 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[7] 29_611 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[8] 28_612 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[9] 29_612 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[0] 28_616 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[1] 29_616 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[2] 28_617 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[3] 29_617 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[4] 28_618 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[5] 29_618 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[6] 28_619 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[7] 29_619 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[8] 28_620 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[9] 29_620 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[0] 28_624 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[1] 29_624 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[2] 28_625 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[3] 29_625 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[4] 28_626 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[5] 29_626 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[6] 28_627 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[7] 29_627 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[8] 28_628 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[9] 29_628 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[0] 28_632 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[1] 29_632 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[2] 28_633 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[3] 29_633 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[4] 28_634 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[5] 29_634 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[6] 28_635 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[7] 29_635 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[8] 28_636 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[9] 29_636 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_ENABLE[0] 28_614 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_ENABLE[1] 29_614 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_ENABLE[2] 28_615 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_ENABLE[3] 29_615 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[0] 28_640 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[1] 29_640 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[2] 28_641 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[3] 29_641 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[4] 28_642 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[5] 29_642 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[6] 28_643 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[7] 29_643 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[8] 28_644 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[9] 29_644 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[0] 28_648 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[1] 29_648 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[2] 28_649 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[3] 29_649 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[4] 28_650 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[5] 29_650 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[6] 28_651 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[7] 29_651 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[8] 28_652 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[9] 29_652 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[0] 28_656 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[1] 29_656 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[2] 28_657 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[3] 29_657 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[4] 28_658 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[5] 29_658 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[6] 28_659 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[7] 29_659 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[8] 28_660 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[9] 29_660 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[0] 28_664 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[1] 29_664 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[2] 28_665 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[3] 29_665 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[4] 28_666 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[5] 29_666 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[6] 28_667 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[7] 29_667 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[8] 28_668 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[9] 29_668 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_ENABLE[0] 28_646 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_ENABLE[1] 29_646 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_ENABLE[2] 28_647 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_ENABLE[3] 29_647 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_USE 29_645 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_LEN[0] 28_623 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_LEN[1] 29_623 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COMMON_SWING[0] 31_311 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_KEEP_IDLE 28_591 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_MAX_LAT[0] 28_557 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_MAX_LAT[1] 29_557 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_MAX_LAT[2] 28_558 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_MAX_LAT[3] 29_558 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_MAX_LAT[4] 28_559 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_MAX_LAT[5] 29_559 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_MIN_LAT[0] 28_565 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_MIN_LAT[1] 29_565 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_MIN_LAT[2] 28_566 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_MIN_LAT[3] 29_566 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_MIN_LAT[4] 28_567 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_MIN_LAT[5] 29_567 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_PRECEDENCE 28_590 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_REPEAT_WAIT[0] 28_573 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_REPEAT_WAIT[1] 29_573 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_REPEAT_WAIT[2] 28_574 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_REPEAT_WAIT[3] 29_574 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_REPEAT_WAIT[4] 28_575 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[0] 28_544 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[1] 29_544 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[2] 28_545 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[3] 29_545 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[4] 28_546 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[5] 29_546 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[6] 28_547 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[7] 29_547 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[8] 28_548 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[9] 29_548 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[0] 28_552 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[1] 29_552 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[2] 28_553 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[3] 29_553 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[4] 28_554 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[5] 29_554 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[6] 28_555 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[7] 29_555 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[8] 28_556 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[9] 29_556 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[0] 28_560 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[1] 29_560 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[2] 28_561 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[3] 29_561 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[4] 28_562 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[5] 29_562 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[6] 28_563 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[7] 29_563 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[8] 28_564 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[9] 29_564 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[0] 28_568 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[1] 29_568 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[2] 28_569 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[3] 29_569 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[4] 28_570 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[5] 29_570 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[6] 28_571 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[7] 29_571 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[8] 28_572 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[9] 29_572 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_1_ENABLE[0] 28_549 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_1_ENABLE[1] 29_549 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_1_ENABLE[2] 28_550 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_1_ENABLE[3] 29_550 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[0] 28_576 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[1] 29_576 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[2] 28_577 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[3] 29_577 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[4] 28_578 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[5] 29_578 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[6] 28_579 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[7] 29_579 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[8] 28_580 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[9] 29_580 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[0] 28_584 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[1] 29_584 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[2] 28_585 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[3] 29_585 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[4] 28_586 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[5] 29_586 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[6] 28_587 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[7] 29_587 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[8] 28_588 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[9] 29_588 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[0] 28_592 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[1] 29_592 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[2] 28_593 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[3] 29_593 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[4] 28_594 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[5] 29_594 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[6] 28_595 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[7] 29_595 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[8] 28_596 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[9] 29_596 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[0] 28_600 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[1] 29_600 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[2] 28_601 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[3] 29_601 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[4] 28_602 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[5] 29_602 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[6] 28_603 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[7] 29_603 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[8] 28_604 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[9] 29_604 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_2_ENABLE[0] 28_581 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_2_ENABLE[1] 29_581 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_2_ENABLE[2] 28_582 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_2_ENABLE[3] 29_582 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_2_USE 28_583 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_LEN[0] 28_589 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_LEN[1] 29_589 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_CORRECT_USE 28_551 +GTP_CHANNEL_0.GTPE2_CHANNEL.DEC_MCOMMA_DETECT 29_494 +GTP_CHANNEL_0.GTPE2_CHANNEL.DEC_PCOMMA_DETECT 28_495 +GTP_CHANNEL_0.GTPE2_CHANNEL.DEC_VALID_COMMA_ONLY 28_494 +GTP_CHANNEL_0.GTPE2_CHANNEL.DMONITOR_CFG[0] 30_368 +GTP_CHANNEL_0.GTPE2_CHANNEL.DMONITOR_CFG[1] 31_368 +GTP_CHANNEL_0.GTPE2_CHANNEL.DMONITOR_CFG[2] 30_369 +GTP_CHANNEL_0.GTPE2_CHANNEL.DMONITOR_CFG[3] 31_369 +GTP_CHANNEL_0.GTPE2_CHANNEL.DMONITOR_CFG[4] 30_370 +GTP_CHANNEL_0.GTPE2_CHANNEL.DMONITOR_CFG[5] 31_370 +GTP_CHANNEL_0.GTPE2_CHANNEL.DMONITOR_CFG[6] 30_371 +GTP_CHANNEL_0.GTPE2_CHANNEL.DMONITOR_CFG[7] 31_371 +GTP_CHANNEL_0.GTPE2_CHANNEL.DMONITOR_CFG[8] 30_372 +GTP_CHANNEL_0.GTPE2_CHANNEL.DMONITOR_CFG[9] 31_372 +GTP_CHANNEL_0.GTPE2_CHANNEL.DMONITOR_CFG[10] 30_373 +GTP_CHANNEL_0.GTPE2_CHANNEL.DMONITOR_CFG[11] 31_373 +GTP_CHANNEL_0.GTPE2_CHANNEL.DMONITOR_CFG[12] 30_374 +GTP_CHANNEL_0.GTPE2_CHANNEL.DMONITOR_CFG[13] 31_374 +GTP_CHANNEL_0.GTPE2_CHANNEL.DMONITOR_CFG[14] 30_375 +GTP_CHANNEL_0.GTPE2_CHANNEL.DMONITOR_CFG[15] 31_375 +GTP_CHANNEL_0.GTPE2_CHANNEL.DMONITOR_CFG[16] 30_376 +GTP_CHANNEL_0.GTPE2_CHANNEL.DMONITOR_CFG[17] 31_376 +GTP_CHANNEL_0.GTPE2_CHANNEL.DMONITOR_CFG[18] 30_377 +GTP_CHANNEL_0.GTPE2_CHANNEL.DMONITOR_CFG[19] 31_377 +GTP_CHANNEL_0.GTPE2_CHANNEL.DMONITOR_CFG[20] 30_378 +GTP_CHANNEL_0.GTPE2_CHANNEL.DMONITOR_CFG[21] 31_378 +GTP_CHANNEL_0.GTPE2_CHANNEL.DMONITOR_CFG[22] 30_379 +GTP_CHANNEL_0.GTPE2_CHANNEL.DMONITOR_CFG[23] 31_379 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_CLK_PHASE_SEL[0] 31_463 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_CONTROL[0] 28_488 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_CONTROL[1] 29_488 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_CONTROL[2] 28_489 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_CONTROL[3] 29_489 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_CONTROL[4] 28_490 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_CONTROL[5] 29_490 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_ERRDET_EN 29_492 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_EYE_SCAN_EN 28_492 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_HORZ_OFFSET[0] 28_480 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_HORZ_OFFSET[1] 29_480 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_HORZ_OFFSET[2] 28_481 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_HORZ_OFFSET[3] 29_481 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_HORZ_OFFSET[4] 28_482 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_HORZ_OFFSET[5] 29_482 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_HORZ_OFFSET[6] 28_483 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_HORZ_OFFSET[7] 29_483 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_HORZ_OFFSET[8] 28_484 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_HORZ_OFFSET[9] 29_484 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_HORZ_OFFSET[10] 28_485 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_HORZ_OFFSET[11] 29_485 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_PMA_CFG[0] 30_624 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_PMA_CFG[1] 31_624 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_PMA_CFG[2] 30_625 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_PMA_CFG[3] 31_625 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_PMA_CFG[4] 30_626 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_PMA_CFG[5] 31_626 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_PMA_CFG[6] 30_627 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_PMA_CFG[7] 31_627 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_PMA_CFG[8] 30_628 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_PMA_CFG[9] 31_628 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_PRESCALE[0] 29_477 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_PRESCALE[1] 28_478 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_PRESCALE[2] 29_478 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_PRESCALE[3] 28_479 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_PRESCALE[4] 29_479 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[0] 28_392 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[1] 29_392 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[2] 28_393 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[3] 29_393 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[4] 28_394 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[5] 29_394 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[6] 28_395 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[7] 29_395 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[8] 28_396 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[9] 29_396 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[10] 28_397 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[11] 29_397 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[12] 28_398 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[13] 29_398 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[14] 28_399 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[15] 29_399 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[16] 28_400 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[17] 29_400 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[18] 28_401 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[19] 29_401 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[20] 28_402 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[21] 29_402 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[22] 28_403 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[23] 29_403 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[24] 28_404 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[25] 29_404 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[26] 28_405 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[27] 29_405 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[28] 28_406 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[29] 29_406 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[30] 28_407 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[31] 29_407 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[32] 28_408 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[33] 29_408 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[34] 28_409 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[35] 29_409 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[36] 28_410 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[37] 29_410 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[38] 28_411 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[39] 29_411 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[40] 28_412 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[41] 29_412 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[42] 28_413 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[43] 29_413 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[44] 28_414 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[45] 29_414 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[46] 28_415 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[47] 29_415 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[48] 28_416 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[49] 29_416 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[50] 28_417 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[51] 29_417 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[52] 28_418 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[53] 29_418 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[54] 28_419 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[55] 29_419 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[56] 28_420 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[57] 29_420 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[58] 28_421 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[59] 29_421 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[60] 28_422 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[61] 29_422 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[62] 28_423 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[63] 29_423 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[64] 28_424 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[65] 29_424 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[66] 28_425 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[67] 29_425 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[68] 28_426 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[69] 29_426 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[70] 28_427 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[71] 29_427 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[72] 28_428 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[73] 29_428 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[74] 28_429 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[75] 29_429 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[76] 28_430 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[77] 29_430 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[78] 28_431 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[79] 29_431 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[0] 28_352 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[1] 29_352 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[2] 28_353 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[3] 29_353 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[4] 28_354 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[5] 29_354 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[6] 28_355 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[7] 29_355 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[8] 28_356 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[9] 29_356 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[10] 28_357 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[11] 29_357 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[12] 28_358 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[13] 29_358 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[14] 28_359 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[15] 29_359 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[16] 28_360 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[17] 29_360 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[18] 28_361 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[19] 29_361 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[20] 28_362 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[21] 29_362 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[22] 28_363 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[23] 29_363 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[24] 28_364 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[25] 29_364 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[26] 28_365 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[27] 29_365 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[28] 28_366 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[29] 29_366 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[30] 28_367 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[31] 29_367 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[32] 28_368 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[33] 29_368 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[34] 28_369 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[35] 29_369 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[36] 28_370 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[37] 29_370 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[38] 28_371 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[39] 29_371 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[40] 28_372 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[41] 29_372 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[42] 28_373 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[43] 29_373 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[44] 28_374 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[45] 29_374 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[46] 28_375 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[47] 29_375 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[48] 28_376 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[49] 29_376 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[50] 28_377 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[51] 29_377 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[52] 28_378 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[53] 29_378 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[54] 28_379 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[55] 29_379 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[56] 28_380 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[57] 29_380 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[58] 28_381 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[59] 29_381 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[60] 28_382 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[61] 29_382 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[62] 28_383 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[63] 29_383 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[64] 28_384 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[65] 29_384 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[66] 28_385 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[67] 29_385 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[68] 28_386 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[69] 29_386 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[70] 28_387 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[71] 29_387 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[72] 28_388 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[73] 29_388 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[74] 28_389 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[75] 29_389 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[76] 28_390 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[77] 29_390 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[78] 28_391 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[79] 29_391 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[0] 28_432 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[1] 29_432 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[2] 28_433 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[3] 29_433 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[4] 28_434 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[5] 29_434 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[6] 28_435 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[7] 29_435 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[8] 28_436 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[9] 29_436 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[10] 28_437 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[11] 29_437 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[12] 28_438 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[13] 29_438 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[14] 28_439 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[15] 29_439 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[16] 28_440 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[17] 29_440 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[18] 28_441 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[19] 29_441 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[20] 28_442 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[21] 29_442 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[22] 28_443 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[23] 29_443 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[24] 28_444 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[25] 29_444 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[26] 28_445 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[27] 29_445 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[28] 28_446 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[29] 29_446 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[30] 28_447 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[31] 29_447 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[32] 28_448 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[33] 29_448 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[34] 28_449 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[35] 29_449 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[36] 28_450 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[37] 29_450 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[38] 28_451 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[39] 29_451 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[40] 28_452 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[41] 29_452 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[42] 28_453 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[43] 29_453 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[44] 28_454 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[45] 29_454 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[46] 28_455 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[47] 29_455 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[48] 28_456 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[49] 29_456 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[50] 28_457 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[51] 29_457 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[52] 28_458 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[53] 29_458 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[54] 28_459 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[55] 29_459 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[56] 28_460 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[57] 29_460 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[58] 28_461 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[59] 29_461 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[60] 28_462 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[61] 29_462 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[62] 28_463 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[63] 29_463 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[64] 28_464 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[65] 29_464 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[66] 28_465 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[67] 29_465 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[68] 28_466 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[69] 29_466 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[70] 28_467 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[71] 29_467 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[72] 28_468 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[73] 29_468 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[74] 28_469 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[75] 29_469 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[76] 28_470 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[77] 29_470 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[78] 28_471 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[79] 29_471 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_VERT_OFFSET[0] 28_472 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_VERT_OFFSET[1] 29_472 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_VERT_OFFSET[2] 28_473 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_VERT_OFFSET[3] 29_473 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_VERT_OFFSET[4] 28_474 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_VERT_OFFSET[5] 29_474 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_VERT_OFFSET[6] 28_475 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_VERT_OFFSET[7] 29_475 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_VERT_OFFSET[8] 28_476 +GTP_CHANNEL_0.GTPE2_CHANNEL.FTS_DESKEW_SEQ_ENABLE[0] 28_662 +GTP_CHANNEL_0.GTPE2_CHANNEL.FTS_DESKEW_SEQ_ENABLE[1] 29_662 +GTP_CHANNEL_0.GTPE2_CHANNEL.FTS_DESKEW_SEQ_ENABLE[2] 28_663 +GTP_CHANNEL_0.GTPE2_CHANNEL.FTS_DESKEW_SEQ_ENABLE[3] 29_663 +GTP_CHANNEL_0.GTPE2_CHANNEL.FTS_LANE_DESKEW_CFG[0] 28_654 +GTP_CHANNEL_0.GTPE2_CHANNEL.FTS_LANE_DESKEW_CFG[1] 29_654 +GTP_CHANNEL_0.GTPE2_CHANNEL.FTS_LANE_DESKEW_CFG[2] 28_655 +GTP_CHANNEL_0.GTPE2_CHANNEL.FTS_LANE_DESKEW_CFG[3] 29_655 +GTP_CHANNEL_0.GTPE2_CHANNEL.FTS_LANE_DESKEW_EN 29_653 +GTP_CHANNEL_0.GTPE2_CHANNEL.GEARBOX_MODE[0] 28_224 +GTP_CHANNEL_0.GTPE2_CHANNEL.GEARBOX_MODE[1] 29_224 +GTP_CHANNEL_0.GTPE2_CHANNEL.GEARBOX_MODE[2] 28_225 +GTP_CHANNEL_0.GTPE2_CHANNEL.IN_USE 28_00 28_01 28_47 28_52 28_53 28_65 29_01 29_47 30_129 +GTP_CHANNEL_0.GTPE2_CHANNEL.INV_DMONITORCLK 30_13 +GTP_CHANNEL_0.GTPE2_CHANNEL.INV_DRPCLK 30_00 +GTP_CHANNEL_0.GTPE2_CHANNEL.INV_RXUSRCLK 31_01 +GTP_CHANNEL_0.GTPE2_CHANNEL.INV_SIGVALIDCLK 31_13 +GTP_CHANNEL_0.GTPE2_CHANNEL.INV_TXPHDLYTSTCLK 30_03 +GTP_CHANNEL_0.GTPE2_CHANNEL.INV_TXUSRCLK 31_04 +GTP_CHANNEL_0.GTPE2_CHANNEL.INV_CLKRSVD0 30_23 +GTP_CHANNEL_0.GTPE2_CHANNEL.INV_CLKRSVD1 31_23 +GTP_CHANNEL_0.GTPE2_CHANNEL.INV_RXUSRCLK2 30_02 +GTP_CHANNEL_0.GTPE2_CHANNEL.INV_TXUSRCLK2 30_05 +GTP_CHANNEL_0.GTPE2_CHANNEL.LOOPBACK_CFG[0] 30_20 +GTP_CHANNEL_0.GTPE2_CHANNEL.OUTREFCLK_SEL_INV[0] 28_149 +GTP_CHANNEL_0.GTPE2_CHANNEL.OUTREFCLK_SEL_INV[1] 29_149 +GTP_CHANNEL_0.GTPE2_CHANNEL.PCS_PCIE_EN 28_216 +GTP_CHANNEL_0.GTPE2_CHANNEL.PCS_RSVD_ATTR[0] 30_184 +GTP_CHANNEL_0.GTPE2_CHANNEL.PCS_RSVD_ATTR[1] 31_184 +GTP_CHANNEL_0.GTPE2_CHANNEL.PCS_RSVD_ATTR[2] 30_185 +GTP_CHANNEL_0.GTPE2_CHANNEL.PCS_RSVD_ATTR[3] 31_185 +GTP_CHANNEL_0.GTPE2_CHANNEL.PCS_RSVD_ATTR[4] 30_186 +GTP_CHANNEL_0.GTPE2_CHANNEL.PCS_RSVD_ATTR[5] 31_186 +GTP_CHANNEL_0.GTPE2_CHANNEL.PCS_RSVD_ATTR[6] 30_187 +GTP_CHANNEL_0.GTPE2_CHANNEL.PCS_RSVD_ATTR[7] 31_187 +GTP_CHANNEL_0.GTPE2_CHANNEL.PCS_RSVD_ATTR[8] 30_188 +GTP_CHANNEL_0.GTPE2_CHANNEL.PCS_RSVD_ATTR[9] 31_188 +GTP_CHANNEL_0.GTPE2_CHANNEL.PCS_RSVD_ATTR[10] 30_189 +GTP_CHANNEL_0.GTPE2_CHANNEL.PCS_RSVD_ATTR[11] 31_189 +GTP_CHANNEL_0.GTPE2_CHANNEL.PCS_RSVD_ATTR[12] 30_190 +GTP_CHANNEL_0.GTPE2_CHANNEL.PCS_RSVD_ATTR[13] 31_190 +GTP_CHANNEL_0.GTPE2_CHANNEL.PCS_RSVD_ATTR[14] 30_191 +GTP_CHANNEL_0.GTPE2_CHANNEL.PCS_RSVD_ATTR[15] 31_191 +GTP_CHANNEL_0.GTPE2_CHANNEL.PCS_RSVD_ATTR[16] 30_192 +GTP_CHANNEL_0.GTPE2_CHANNEL.PCS_RSVD_ATTR[17] 31_192 +GTP_CHANNEL_0.GTPE2_CHANNEL.PCS_RSVD_ATTR[18] 30_193 +GTP_CHANNEL_0.GTPE2_CHANNEL.PCS_RSVD_ATTR[19] 31_193 +GTP_CHANNEL_0.GTPE2_CHANNEL.PCS_RSVD_ATTR[20] 30_194 +GTP_CHANNEL_0.GTPE2_CHANNEL.PCS_RSVD_ATTR[21] 31_194 +GTP_CHANNEL_0.GTPE2_CHANNEL.PCS_RSVD_ATTR[22] 30_195 +GTP_CHANNEL_0.GTPE2_CHANNEL.PCS_RSVD_ATTR[23] 31_195 +GTP_CHANNEL_0.GTPE2_CHANNEL.PCS_RSVD_ATTR[24] 30_196 +GTP_CHANNEL_0.GTPE2_CHANNEL.PCS_RSVD_ATTR[25] 31_196 +GTP_CHANNEL_0.GTPE2_CHANNEL.PCS_RSVD_ATTR[26] 30_197 +GTP_CHANNEL_0.GTPE2_CHANNEL.PCS_RSVD_ATTR[27] 31_197 +GTP_CHANNEL_0.GTPE2_CHANNEL.PCS_RSVD_ATTR[28] 30_198 +GTP_CHANNEL_0.GTPE2_CHANNEL.PCS_RSVD_ATTR[29] 31_198 +GTP_CHANNEL_0.GTPE2_CHANNEL.PCS_RSVD_ATTR[30] 30_199 +GTP_CHANNEL_0.GTPE2_CHANNEL.PCS_RSVD_ATTR[31] 31_199 +GTP_CHANNEL_0.GTPE2_CHANNEL.PCS_RSVD_ATTR[32] 30_200 +GTP_CHANNEL_0.GTPE2_CHANNEL.PCS_RSVD_ATTR[33] 31_200 +GTP_CHANNEL_0.GTPE2_CHANNEL.PCS_RSVD_ATTR[34] 30_201 +GTP_CHANNEL_0.GTPE2_CHANNEL.PCS_RSVD_ATTR[35] 31_201 +GTP_CHANNEL_0.GTPE2_CHANNEL.PCS_RSVD_ATTR[36] 30_202 +GTP_CHANNEL_0.GTPE2_CHANNEL.PCS_RSVD_ATTR[37] 31_202 +GTP_CHANNEL_0.GTPE2_CHANNEL.PCS_RSVD_ATTR[38] 30_203 +GTP_CHANNEL_0.GTPE2_CHANNEL.PCS_RSVD_ATTR[39] 31_203 +GTP_CHANNEL_0.GTPE2_CHANNEL.PCS_RSVD_ATTR[40] 30_204 +GTP_CHANNEL_0.GTPE2_CHANNEL.PCS_RSVD_ATTR[41] 31_204 +GTP_CHANNEL_0.GTPE2_CHANNEL.PCS_RSVD_ATTR[42] 30_205 +GTP_CHANNEL_0.GTPE2_CHANNEL.PCS_RSVD_ATTR[43] 31_205 +GTP_CHANNEL_0.GTPE2_CHANNEL.PCS_RSVD_ATTR[44] 30_206 +GTP_CHANNEL_0.GTPE2_CHANNEL.PCS_RSVD_ATTR[45] 31_206 +GTP_CHANNEL_0.GTPE2_CHANNEL.PCS_RSVD_ATTR[46] 30_207 +GTP_CHANNEL_0.GTPE2_CHANNEL.PCS_RSVD_ATTR[47] 31_207 +GTP_CHANNEL_0.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[0] 29_216 +GTP_CHANNEL_0.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[1] 28_217 +GTP_CHANNEL_0.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[2] 29_217 +GTP_CHANNEL_0.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[3] 28_218 +GTP_CHANNEL_0.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[4] 29_218 +GTP_CHANNEL_0.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[5] 28_219 +GTP_CHANNEL_0.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[6] 29_219 +GTP_CHANNEL_0.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[7] 28_220 +GTP_CHANNEL_0.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[8] 29_220 +GTP_CHANNEL_0.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[9] 28_221 +GTP_CHANNEL_0.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[10] 29_221 +GTP_CHANNEL_0.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[11] 28_222 +GTP_CHANNEL_0.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[0] 28_208 +GTP_CHANNEL_0.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[1] 29_208 +GTP_CHANNEL_0.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[2] 28_209 +GTP_CHANNEL_0.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[3] 29_209 +GTP_CHANNEL_0.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[4] 28_210 +GTP_CHANNEL_0.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[5] 29_210 +GTP_CHANNEL_0.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[6] 28_211 +GTP_CHANNEL_0.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[7] 29_211 +GTP_CHANNEL_0.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[0] 28_212 +GTP_CHANNEL_0.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[1] 29_212 +GTP_CHANNEL_0.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[2] 28_213 +GTP_CHANNEL_0.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[3] 29_213 +GTP_CHANNEL_0.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[4] 28_214 +GTP_CHANNEL_0.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[5] 29_214 +GTP_CHANNEL_0.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[6] 28_215 +GTP_CHANNEL_0.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[7] 29_215 +GTP_CHANNEL_0.GTPE2_CHANNEL.PMA_LOOPBACK_CFG[0] 29_207 +GTP_CHANNEL_0.GTPE2_CHANNEL.PMA_RSV[0] 30_520 +GTP_CHANNEL_0.GTPE2_CHANNEL.PMA_RSV[1] 31_520 +GTP_CHANNEL_0.GTPE2_CHANNEL.PMA_RSV[2] 30_521 +GTP_CHANNEL_0.GTPE2_CHANNEL.PMA_RSV[3] 31_521 +GTP_CHANNEL_0.GTPE2_CHANNEL.PMA_RSV[4] 30_522 +GTP_CHANNEL_0.GTPE2_CHANNEL.PMA_RSV[5] 31_522 +GTP_CHANNEL_0.GTPE2_CHANNEL.PMA_RSV[6] 30_523 +GTP_CHANNEL_0.GTPE2_CHANNEL.PMA_RSV[7] 31_523 +GTP_CHANNEL_0.GTPE2_CHANNEL.PMA_RSV[8] 30_524 +GTP_CHANNEL_0.GTPE2_CHANNEL.PMA_RSV[9] 31_524 +GTP_CHANNEL_0.GTPE2_CHANNEL.PMA_RSV[10] 30_525 +GTP_CHANNEL_0.GTPE2_CHANNEL.PMA_RSV[11] 31_525 +GTP_CHANNEL_0.GTPE2_CHANNEL.PMA_RSV[12] 30_526 +GTP_CHANNEL_0.GTPE2_CHANNEL.PMA_RSV[13] 31_526 +GTP_CHANNEL_0.GTPE2_CHANNEL.PMA_RSV[14] 30_527 +GTP_CHANNEL_0.GTPE2_CHANNEL.PMA_RSV[15] 31_527 +GTP_CHANNEL_0.GTPE2_CHANNEL.PMA_RSV[16] 30_528 +GTP_CHANNEL_0.GTPE2_CHANNEL.PMA_RSV[17] 31_528 +GTP_CHANNEL_0.GTPE2_CHANNEL.PMA_RSV[18] 30_529 +GTP_CHANNEL_0.GTPE2_CHANNEL.PMA_RSV[19] 31_529 +GTP_CHANNEL_0.GTPE2_CHANNEL.PMA_RSV[20] 30_530 +GTP_CHANNEL_0.GTPE2_CHANNEL.PMA_RSV[21] 31_530 +GTP_CHANNEL_0.GTPE2_CHANNEL.PMA_RSV[22] 30_531 +GTP_CHANNEL_0.GTPE2_CHANNEL.PMA_RSV[23] 31_531 +GTP_CHANNEL_0.GTPE2_CHANNEL.PMA_RSV[24] 30_532 +GTP_CHANNEL_0.GTPE2_CHANNEL.PMA_RSV[25] 31_532 +GTP_CHANNEL_0.GTPE2_CHANNEL.PMA_RSV[26] 30_533 +GTP_CHANNEL_0.GTPE2_CHANNEL.PMA_RSV[27] 31_533 +GTP_CHANNEL_0.GTPE2_CHANNEL.PMA_RSV[28] 30_534 +GTP_CHANNEL_0.GTPE2_CHANNEL.PMA_RSV[29] 31_534 +GTP_CHANNEL_0.GTPE2_CHANNEL.PMA_RSV[30] 30_535 +GTP_CHANNEL_0.GTPE2_CHANNEL.PMA_RSV[31] 31_535 +GTP_CHANNEL_0.GTPE2_CHANNEL.PMA_RSV2[0] 30_336 +GTP_CHANNEL_0.GTPE2_CHANNEL.PMA_RSV2[1] 31_336 +GTP_CHANNEL_0.GTPE2_CHANNEL.PMA_RSV2[2] 30_337 +GTP_CHANNEL_0.GTPE2_CHANNEL.PMA_RSV2[3] 31_337 +GTP_CHANNEL_0.GTPE2_CHANNEL.PMA_RSV2[4] 30_338 +GTP_CHANNEL_0.GTPE2_CHANNEL.PMA_RSV2[5] 31_338 +GTP_CHANNEL_0.GTPE2_CHANNEL.PMA_RSV2[6] 30_339 +GTP_CHANNEL_0.GTPE2_CHANNEL.PMA_RSV2[7] 31_339 +GTP_CHANNEL_0.GTPE2_CHANNEL.PMA_RSV2[8] 30_340 +GTP_CHANNEL_0.GTPE2_CHANNEL.PMA_RSV2[9] 31_340 +GTP_CHANNEL_0.GTPE2_CHANNEL.PMA_RSV2[10] 30_341 +GTP_CHANNEL_0.GTPE2_CHANNEL.PMA_RSV2[11] 31_341 +GTP_CHANNEL_0.GTPE2_CHANNEL.PMA_RSV2[12] 30_342 +GTP_CHANNEL_0.GTPE2_CHANNEL.PMA_RSV2[13] 31_342 +GTP_CHANNEL_0.GTPE2_CHANNEL.PMA_RSV2[14] 30_343 +GTP_CHANNEL_0.GTPE2_CHANNEL.PMA_RSV2[15] 31_343 +GTP_CHANNEL_0.GTPE2_CHANNEL.PMA_RSV2[16] 30_344 +GTP_CHANNEL_0.GTPE2_CHANNEL.PMA_RSV2[17] 31_344 +GTP_CHANNEL_0.GTPE2_CHANNEL.PMA_RSV2[18] 30_345 +GTP_CHANNEL_0.GTPE2_CHANNEL.PMA_RSV2[19] 31_345 +GTP_CHANNEL_0.GTPE2_CHANNEL.PMA_RSV2[20] 30_346 +GTP_CHANNEL_0.GTPE2_CHANNEL.PMA_RSV2[21] 31_346 +GTP_CHANNEL_0.GTPE2_CHANNEL.PMA_RSV2[22] 30_347 +GTP_CHANNEL_0.GTPE2_CHANNEL.PMA_RSV2[23] 31_347 +GTP_CHANNEL_0.GTPE2_CHANNEL.PMA_RSV2[24] 30_348 +GTP_CHANNEL_0.GTPE2_CHANNEL.PMA_RSV2[25] 31_348 +GTP_CHANNEL_0.GTPE2_CHANNEL.PMA_RSV2[26] 30_349 +GTP_CHANNEL_0.GTPE2_CHANNEL.PMA_RSV2[27] 31_349 +GTP_CHANNEL_0.GTPE2_CHANNEL.PMA_RSV2[28] 30_350 +GTP_CHANNEL_0.GTPE2_CHANNEL.PMA_RSV2[29] 31_350 +GTP_CHANNEL_0.GTPE2_CHANNEL.PMA_RSV2[30] 30_351 +GTP_CHANNEL_0.GTPE2_CHANNEL.PMA_RSV2[31] 31_351 +GTP_CHANNEL_0.GTPE2_CHANNEL.PMA_RSV3[0] 30_288 +GTP_CHANNEL_0.GTPE2_CHANNEL.PMA_RSV3[1] 31_288 +GTP_CHANNEL_0.GTPE2_CHANNEL.PMA_RSV4[0] 30_156 +GTP_CHANNEL_0.GTPE2_CHANNEL.PMA_RSV4[1] 31_156 +GTP_CHANNEL_0.GTPE2_CHANNEL.PMA_RSV4[2] 30_157 +GTP_CHANNEL_0.GTPE2_CHANNEL.PMA_RSV4[3] 31_157 +GTP_CHANNEL_0.GTPE2_CHANNEL.PMA_RSV5[0] 31_159 +GTP_CHANNEL_0.GTPE2_CHANNEL.PMA_RSV6[0] 30_303 +GTP_CHANNEL_0.GTPE2_CHANNEL.PMA_RSV7[0] 31_303 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_BIAS_CFG[0] 30_112 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_BIAS_CFG[1] 31_112 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_BIAS_CFG[2] 30_113 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_BIAS_CFG[3] 31_113 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_BIAS_CFG[4] 30_114 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_BIAS_CFG[5] 31_114 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_BIAS_CFG[6] 30_115 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_BIAS_CFG[7] 31_115 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_BIAS_CFG[8] 30_116 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_BIAS_CFG[9] 31_116 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_BIAS_CFG[10] 30_117 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_BIAS_CFG[11] 31_117 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_BIAS_CFG[12] 30_118 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_BIAS_CFG[13] 31_118 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_BIAS_CFG[14] 30_119 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_BIAS_CFG[15] 31_119 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_BUFFER_CFG[0] 30_536 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_BUFFER_CFG[1] 31_536 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_BUFFER_CFG[2] 30_537 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_BUFFER_CFG[3] 31_537 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_BUFFER_CFG[4] 30_538 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_BUFFER_CFG[5] 31_538 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_CLKMUX_EN[0] 30_128 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_CM_SEL[0] 28_138 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_CM_SEL[1] 29_138 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_CM_TRIM[0] 30_304 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_CM_TRIM[1] 31_304 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_CM_TRIM[2] 30_305 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_CM_TRIM[3] 31_305 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_DATA_WIDTH[0] 29_141 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_DATA_WIDTH[1] 28_142 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_DATA_WIDTH[2] 29_142 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_DDI_SEL[0] 28_696 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_DDI_SEL[1] 29_696 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_DDI_SEL[2] 28_697 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_DDI_SEL[3] 29_697 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_DDI_SEL[4] 28_698 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_DDI_SEL[5] 29_698 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_DEBUG_CFG[0] 30_616 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_DEBUG_CFG[1] 31_616 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_DEBUG_CFG[2] 30_617 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_DEBUG_CFG[3] 31_617 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_DEBUG_CFG[4] 30_618 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_DEBUG_CFG[5] 31_618 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_DEBUG_CFG[6] 30_619 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_DEBUG_CFG[7] 31_619 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_DEBUG_CFG[8] 30_620 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_DEBUG_CFG[9] 31_620 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_DEBUG_CFG[10] 30_621 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_DEBUG_CFG[11] 31_621 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_DEBUG_CFG[12] 30_622 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_DEBUG_CFG[13] 31_622 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_DEFER_RESET_BUF_EN 30_552 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_DISPERR_SEQ_MATCH 29_495 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_OS_CFG[0] 28_288 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_OS_CFG[1] 29_288 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_OS_CFG[2] 28_289 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_OS_CFG[3] 29_289 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_OS_CFG[4] 28_290 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_OS_CFG[5] 29_290 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_OS_CFG[6] 28_291 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_OS_CFG[7] 29_291 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_OS_CFG[8] 28_292 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_OS_CFG[9] 29_292 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_OS_CFG[10] 28_293 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_OS_CFG[11] 29_293 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_OS_CFG[12] 28_294 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_SIG_VALID_DLY[0] 28_524 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_SIG_VALID_DLY[1] 29_524 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_SIG_VALID_DLY[2] 28_525 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_SIG_VALID_DLY[3] 29_525 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_SIG_VALID_DLY[4] 28_526 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_XCLK_SEL.RXUSR 28_143 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_CLK25_DIV[0] 28_139 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_CLK25_DIV[1] 29_139 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_CLK25_DIV[2] 28_140 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_CLK25_DIV[3] 29_140 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_CLK25_DIV[4] 28_141 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXBUF_ADDR_MODE.FAST 31_555 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXBUF_EIDLE_HI_CNT[0] 30_558 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXBUF_EIDLE_HI_CNT[1] 31_558 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXBUF_EIDLE_HI_CNT[2] 30_559 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXBUF_EIDLE_HI_CNT[3] 31_559 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXBUF_EIDLE_LO_CNT[0] 30_556 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXBUF_EIDLE_LO_CNT[1] 31_556 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXBUF_EIDLE_LO_CNT[2] 30_557 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXBUF_EIDLE_LO_CNT[3] 31_557 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXBUF_EN 30_11 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXBUF_RESET_ON_CB_CHANGE 30_560 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXBUF_RESET_ON_COMMAALIGN 30_561 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXBUF_RESET_ON_EIDLE 30_547 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXBUF_RESET_ON_RATE_CHANGE 31_560 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXBUF_THRESH_OVFLW[0] 31_552 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXBUF_THRESH_OVFLW[1] 30_553 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXBUF_THRESH_OVFLW[2] 31_553 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXBUF_THRESH_OVFLW[3] 30_554 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXBUF_THRESH_OVFLW[4] 31_554 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXBUF_THRESH_OVFLW[5] 30_555 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXBUF_THRESH_OVRD 30_548 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXBUF_THRESH_UNDFLW[0] 30_544 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXBUF_THRESH_UNDFLW[1] 31_544 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXBUF_THRESH_UNDFLW[2] 30_545 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXBUF_THRESH_UNDFLW[3] 31_545 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXBUF_THRESH_UNDFLW[4] 30_546 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXBUF_THRESH_UNDFLW[5] 31_546 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXBUFRESET_TIME[0] 29_101 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXBUFRESET_TIME[1] 28_102 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXBUFRESET_TIME[2] 29_102 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXBUFRESET_TIME[3] 28_103 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXBUFRESET_TIME[4] 29_103 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[0] 30_640 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[1] 31_640 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[2] 30_641 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[3] 31_641 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[4] 30_642 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[5] 31_642 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[6] 30_643 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[7] 31_643 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[8] 30_644 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[9] 31_644 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[10] 30_645 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[11] 31_645 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[12] 30_646 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[13] 31_646 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[14] 30_647 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[15] 31_647 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[16] 30_648 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[17] 31_648 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[18] 30_649 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[19] 31_649 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[20] 30_650 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[21] 31_650 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[22] 30_651 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[23] 31_651 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[24] 30_652 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[25] 31_652 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[26] 30_653 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[27] 31_653 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[28] 30_654 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[29] 31_654 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[30] 30_655 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[31] 31_655 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[32] 30_656 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[33] 31_656 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[34] 30_657 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[35] 31_657 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[36] 30_658 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[37] 31_658 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[38] 30_659 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[39] 31_659 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[40] 30_660 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[41] 31_660 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[42] 30_661 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[43] 31_661 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[44] 30_662 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[45] 31_662 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[46] 30_663 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[47] 31_663 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[48] 30_664 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[49] 31_664 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[50] 30_665 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[51] 31_665 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[52] 30_666 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[53] 31_666 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[54] 30_667 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[55] 31_667 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[56] 30_668 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[57] 31_668 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[58] 30_669 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[59] 31_669 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[60] 30_670 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[61] 31_670 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[62] 30_671 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[63] 31_671 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[64] 30_672 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[65] 31_672 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[66] 30_673 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[67] 31_673 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[68] 30_674 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[69] 31_674 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[70] 30_675 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[71] 31_675 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[72] 30_676 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[73] 31_676 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[74] 30_677 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[75] 31_677 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[76] 30_678 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[77] 31_678 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[78] 30_679 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[79] 31_679 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[80] 30_680 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[81] 31_680 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[82] 30_681 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_FR_RESET_ON_EIDLE[0] 30_638 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_HOLD_DURING_EIDLE[0] 31_637 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_LOCK_CFG[0] 30_632 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_LOCK_CFG[1] 31_632 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_LOCK_CFG[2] 30_633 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_LOCK_CFG[3] 31_633 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_LOCK_CFG[4] 30_634 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_LOCK_CFG[5] 31_634 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_PH_RESET_ON_EIDLE[0] 31_638 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDRFREQRESET_TIME[0] 29_106 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDRFREQRESET_TIME[1] 28_107 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDRFREQRESET_TIME[2] 29_107 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDRFREQRESET_TIME[3] 28_108 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDRFREQRESET_TIME[4] 29_108 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDRPHRESET_TIME[0] 28_109 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDRPHRESET_TIME[1] 29_109 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDRPHRESET_TIME[2] 28_110 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDRPHRESET_TIME[3] 29_110 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDRPHRESET_TIME[4] 28_111 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXDLY_CFG[0] 28_680 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXDLY_CFG[1] 29_680 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXDLY_CFG[2] 28_681 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXDLY_CFG[3] 29_681 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXDLY_CFG[4] 28_682 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXDLY_CFG[5] 29_682 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXDLY_CFG[6] 28_683 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXDLY_CFG[7] 29_683 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXDLY_CFG[8] 28_684 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXDLY_CFG[9] 29_684 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXDLY_CFG[10] 28_685 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXDLY_CFG[11] 29_685 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXDLY_CFG[12] 28_686 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXDLY_CFG[13] 29_686 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXDLY_CFG[14] 28_687 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXDLY_CFG[15] 29_687 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXDLY_LCFG[0] 30_576 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXDLY_LCFG[1] 31_576 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXDLY_LCFG[2] 30_577 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXDLY_LCFG[3] 31_577 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXDLY_LCFG[4] 30_578 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXDLY_LCFG[5] 31_578 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXDLY_LCFG[6] 30_579 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXDLY_LCFG[7] 31_579 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXDLY_LCFG[8] 30_580 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXDLY_TAP_CFG[0] 28_672 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXDLY_TAP_CFG[1] 29_672 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXDLY_TAP_CFG[2] 28_673 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXDLY_TAP_CFG[3] 29_673 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXDLY_TAP_CFG[4] 28_674 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXDLY_TAP_CFG[5] 29_674 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXDLY_TAP_CFG[6] 28_675 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXDLY_TAP_CFG[7] 29_675 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXDLY_TAP_CFG[8] 28_676 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXDLY_TAP_CFG[9] 29_676 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXDLY_TAP_CFG[10] 28_677 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXDLY_TAP_CFG[11] 29_677 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXDLY_TAP_CFG[12] 28_678 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXDLY_TAP_CFG[13] 29_678 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXDLY_TAP_CFG[14] 28_679 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXDLY_TAP_CFG[15] 29_679 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXGEARBOX_EN 29_607 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXISCANRESET_TIME[0] 29_123 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXISCANRESET_TIME[1] 28_124 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXISCANRESET_TIME[2] 29_124 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXISCANRESET_TIME[3] 28_125 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXISCANRESET_TIME[4] 29_125 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPM_BIAS_STARTUP_DISABLE[0] 31_391 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPM_CFG[0] 30_328 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPM_CFG[1] 31_328 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPM_CFG[2] 30_329 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPM_CFG[3] 31_329 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPM_CM_CFG[0] 30_430 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPM_GC_CFG[0] 30_432 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPM_GC_CFG[1] 31_432 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPM_GC_CFG[2] 30_433 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPM_GC_CFG[3] 31_433 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPM_GC_CFG[4] 30_434 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPM_GC_CFG[5] 31_434 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPM_GC_CFG[6] 30_435 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPM_GC_CFG[7] 31_435 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPM_GC_CFG[8] 30_436 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPM_GC_CFG2[0] 31_442 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPM_GC_CFG2[1] 30_443 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPM_GC_CFG2[2] 31_443 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPM_HF_CFG[0] 28_336 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPM_HF_CFG[1] 29_336 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPM_HF_CFG[2] 28_337 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPM_HF_CFG[3] 29_337 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPM_HF_CFG[4] 28_338 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPM_HF_CFG[5] 29_338 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPM_HF_CFG[6] 28_339 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPM_HF_CFG[7] 29_339 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPM_HF_CFG[8] 28_340 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPM_HF_CFG[9] 29_340 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPM_HF_CFG[10] 28_341 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPM_HF_CFG[11] 29_341 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPM_HF_CFG[12] 28_342 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPM_HF_CFG[13] 29_342 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPM_HF_CFG2[0] 30_424 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPM_HF_CFG2[1] 31_424 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPM_HF_CFG2[2] 30_425 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPM_HF_CFG2[3] 31_425 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPM_HF_CFG2[4] 30_426 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPM_HF_CFG3[0] 31_389 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPM_HF_CFG3[1] 30_390 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPM_HF_CFG3[2] 31_390 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPM_HF_CFG3[3] 30_391 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPM_HOLD_DURING_EIDLE[0] 28_247 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPM_INCM_CFG[0] 30_439 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPM_IPCM_CFG[0] 31_439 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPM_LF_CFG[0] 28_344 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPM_LF_CFG[1] 29_344 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPM_LF_CFG[2] 28_345 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPM_LF_CFG[3] 29_345 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPM_LF_CFG[4] 28_346 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPM_LF_CFG[5] 29_346 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPM_LF_CFG[6] 28_347 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPM_LF_CFG[7] 29_347 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPM_LF_CFG[8] 28_348 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPM_LF_CFG[9] 29_348 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPM_LF_CFG[10] 28_349 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPM_LF_CFG[11] 29_349 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPM_LF_CFG[12] 28_350 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPM_LF_CFG[13] 29_350 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPM_LF_CFG[14] 28_351 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPM_LF_CFG[15] 29_351 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPM_LF_CFG[16] 28_343 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPM_LF_CFG[17] 29_343 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPM_LF_CFG2[0] 31_426 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPM_LF_CFG2[1] 30_427 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPM_LF_CFG2[2] 31_427 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPM_LF_CFG2[3] 30_428 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPM_LF_CFG2[4] 31_428 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPM_OSINT_CFG[0] 30_440 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPM_OSINT_CFG[1] 31_440 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPM_OSINT_CFG[2] 30_441 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPM_CFG1[0] 30_330 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPMRESET_TIME[0] 28_112 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPMRESET_TIME[1] 29_112 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPMRESET_TIME[2] 28_113 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPMRESET_TIME[3] 29_113 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPMRESET_TIME[4] 28_114 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPMRESET_TIME[5] 29_114 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPMRESET_TIME[6] 28_115 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXOOB_CFG[0] 28_144 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXOOB_CFG[1] 29_144 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXOOB_CFG[2] 28_145 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXOOB_CFG[3] 29_145 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXOOB_CFG[4] 28_146 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXOOB_CFG[5] 29_146 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXOOB_CFG[6] 28_147 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXOOB_CLK_CFG.FABRIC 31_129 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXOSCALRESET_TIME[0] 28_187 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXOSCALRESET_TIME[1] 29_187 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXOSCALRESET_TIME[2] 28_188 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXOSCALRESET_TIME[3] 29_188 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXOSCALRESET_TIME[4] 28_189 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXOSCALRESET_TIMEOUT[0] 29_189 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXOSCALRESET_TIMEOUT[1] 28_190 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXOSCALRESET_TIMEOUT[2] 29_190 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXOSCALRESET_TIMEOUT[3] 28_191 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXOSCALRESET_TIMEOUT[4] 29_191 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXOUT_DIV[0] 30_384 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXOUT_DIV[1] 31_384 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXPCSRESET_TIME[0] 29_115 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXPCSRESET_TIME[1] 28_116 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXPCSRESET_TIME[2] 29_116 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXPCSRESET_TIME[3] 28_117 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXPCSRESET_TIME[4] 29_117 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXPH_CFG[0] 30_584 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXPH_CFG[1] 31_584 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXPH_CFG[2] 30_585 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXPH_CFG[3] 31_585 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXPH_CFG[4] 30_586 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXPH_CFG[5] 31_586 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXPH_CFG[6] 30_587 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXPH_CFG[7] 31_587 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXPH_CFG[8] 30_588 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXPH_CFG[9] 31_588 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXPH_CFG[10] 30_589 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXPH_CFG[11] 31_589 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXPH_CFG[12] 30_590 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXPH_CFG[13] 31_590 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXPH_CFG[14] 30_591 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXPH_CFG[15] 31_591 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXPH_CFG[16] 30_592 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXPH_CFG[17] 31_592 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXPH_CFG[18] 30_593 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXPH_CFG[19] 31_593 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXPH_CFG[20] 30_594 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXPH_CFG[21] 31_594 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXPH_CFG[22] 30_595 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXPH_CFG[23] 31_595 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXPH_MONITOR_SEL[0] 28_700 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXPH_MONITOR_SEL[1] 29_700 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXPH_MONITOR_SEL[2] 28_701 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXPH_MONITOR_SEL[3] 29_701 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXPH_MONITOR_SEL[4] 28_702 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXPHDLY_CFG[0] 30_600 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXPHDLY_CFG[1] 31_600 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXPHDLY_CFG[2] 30_601 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXPHDLY_CFG[3] 31_601 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXPHDLY_CFG[4] 30_602 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXPHDLY_CFG[5] 31_602 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXPHDLY_CFG[6] 30_603 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXPHDLY_CFG[7] 31_603 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXPHDLY_CFG[8] 30_604 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXPHDLY_CFG[9] 31_604 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXPHDLY_CFG[10] 30_605 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXPHDLY_CFG[11] 31_605 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXPHDLY_CFG[12] 30_606 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXPHDLY_CFG[13] 31_606 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXPHDLY_CFG[14] 30_607 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXPHDLY_CFG[15] 31_607 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXPHDLY_CFG[16] 30_608 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXPHDLY_CFG[17] 31_608 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXPHDLY_CFG[18] 30_609 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXPHDLY_CFG[19] 31_609 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXPHDLY_CFG[20] 30_610 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXPHDLY_CFG[21] 31_610 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXPHDLY_CFG[22] 30_611 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXPHDLY_CFG[23] 31_611 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXPI_CFG0[0] 31_430 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXPI_CFG0[1] 30_431 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXPI_CFG0[2] 31_431 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXPI_CFG1[0] 30_442 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXPI_CFG2[0] 31_441 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXPMARESET_TIME[0] 28_104 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXPMARESET_TIME[1] 29_104 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXPMARESET_TIME[2] 28_105 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXPMARESET_TIME[3] 29_105 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXPMARESET_TIME[4] 28_106 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXPRBS_ERR_LOOPBACK[0] 28_136 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXSLIDE_AUTO_WAIT[0] 28_520 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXSLIDE_AUTO_WAIT[1] 29_520 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXSLIDE_AUTO_WAIT[2] 28_521 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXSLIDE_AUTO_WAIT[3] 29_521 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXSLIDE_MODE.AUTO 28_519 !29_519 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXSLIDE_MODE.PCS !28_519 29_519 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXSLIDE_MODE.PMA 28_519 29_519 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXSYNC_MULTILANE[0] 28_133 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXSYNC_OVRD[0] 29_135 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXSYNC_SKIP_DA[0] 29_134 +GTP_CHANNEL_0.GTPE2_CHANNEL.SAS_MAX_COM[0] 28_171 +GTP_CHANNEL_0.GTPE2_CHANNEL.SAS_MAX_COM[1] 29_171 +GTP_CHANNEL_0.GTPE2_CHANNEL.SAS_MAX_COM[2] 28_172 +GTP_CHANNEL_0.GTPE2_CHANNEL.SAS_MAX_COM[3] 29_172 +GTP_CHANNEL_0.GTPE2_CHANNEL.SAS_MAX_COM[4] 28_173 +GTP_CHANNEL_0.GTPE2_CHANNEL.SAS_MAX_COM[5] 29_173 +GTP_CHANNEL_0.GTPE2_CHANNEL.SAS_MAX_COM[6] 28_174 +GTP_CHANNEL_0.GTPE2_CHANNEL.SAS_MIN_COM[0] 29_156 +GTP_CHANNEL_0.GTPE2_CHANNEL.SAS_MIN_COM[1] 28_157 +GTP_CHANNEL_0.GTPE2_CHANNEL.SAS_MIN_COM[2] 29_157 +GTP_CHANNEL_0.GTPE2_CHANNEL.SAS_MIN_COM[3] 28_158 +GTP_CHANNEL_0.GTPE2_CHANNEL.SAS_MIN_COM[4] 29_158 +GTP_CHANNEL_0.GTPE2_CHANNEL.SAS_MIN_COM[5] 28_159 +GTP_CHANNEL_0.GTPE2_CHANNEL.SATA_BURST_SEQ_LEN[0] 28_150 +GTP_CHANNEL_0.GTPE2_CHANNEL.SATA_BURST_SEQ_LEN[1] 29_150 +GTP_CHANNEL_0.GTPE2_CHANNEL.SATA_BURST_SEQ_LEN[2] 28_151 +GTP_CHANNEL_0.GTPE2_CHANNEL.SATA_BURST_SEQ_LEN[3] 29_151 +GTP_CHANNEL_0.GTPE2_CHANNEL.SATA_BURST_VAL[0] 29_147 +GTP_CHANNEL_0.GTPE2_CHANNEL.SATA_BURST_VAL[1] 28_148 +GTP_CHANNEL_0.GTPE2_CHANNEL.SATA_BURST_VAL[2] 29_148 +GTP_CHANNEL_0.GTPE2_CHANNEL.SATA_EIDLE_VAL[0] 28_152 +GTP_CHANNEL_0.GTPE2_CHANNEL.SATA_EIDLE_VAL[1] 29_152 +GTP_CHANNEL_0.GTPE2_CHANNEL.SATA_EIDLE_VAL[2] 28_153 +GTP_CHANNEL_0.GTPE2_CHANNEL.SATA_MAX_BURST[0] 28_168 +GTP_CHANNEL_0.GTPE2_CHANNEL.SATA_MAX_BURST[1] 29_168 +GTP_CHANNEL_0.GTPE2_CHANNEL.SATA_MAX_BURST[2] 28_169 +GTP_CHANNEL_0.GTPE2_CHANNEL.SATA_MAX_BURST[3] 29_169 +GTP_CHANNEL_0.GTPE2_CHANNEL.SATA_MAX_BURST[4] 28_170 +GTP_CHANNEL_0.GTPE2_CHANNEL.SATA_MAX_BURST[5] 29_170 +GTP_CHANNEL_0.GTPE2_CHANNEL.SATA_MAX_INIT[0] 28_176 +GTP_CHANNEL_0.GTPE2_CHANNEL.SATA_MAX_INIT[1] 29_176 +GTP_CHANNEL_0.GTPE2_CHANNEL.SATA_MAX_INIT[2] 28_177 +GTP_CHANNEL_0.GTPE2_CHANNEL.SATA_MAX_INIT[3] 29_177 +GTP_CHANNEL_0.GTPE2_CHANNEL.SATA_MAX_INIT[4] 28_178 +GTP_CHANNEL_0.GTPE2_CHANNEL.SATA_MAX_INIT[5] 29_178 +GTP_CHANNEL_0.GTPE2_CHANNEL.SATA_MAX_WAKE[0] 28_179 +GTP_CHANNEL_0.GTPE2_CHANNEL.SATA_MAX_WAKE[1] 29_179 +GTP_CHANNEL_0.GTPE2_CHANNEL.SATA_MAX_WAKE[2] 28_180 +GTP_CHANNEL_0.GTPE2_CHANNEL.SATA_MAX_WAKE[3] 29_180 +GTP_CHANNEL_0.GTPE2_CHANNEL.SATA_MAX_WAKE[4] 28_181 +GTP_CHANNEL_0.GTPE2_CHANNEL.SATA_MAX_WAKE[5] 29_181 +GTP_CHANNEL_0.GTPE2_CHANNEL.SATA_MIN_BURST[0] 29_153 +GTP_CHANNEL_0.GTPE2_CHANNEL.SATA_MIN_BURST[1] 28_154 +GTP_CHANNEL_0.GTPE2_CHANNEL.SATA_MIN_BURST[2] 29_154 +GTP_CHANNEL_0.GTPE2_CHANNEL.SATA_MIN_BURST[3] 28_155 +GTP_CHANNEL_0.GTPE2_CHANNEL.SATA_MIN_BURST[4] 29_155 +GTP_CHANNEL_0.GTPE2_CHANNEL.SATA_MIN_BURST[5] 28_156 +GTP_CHANNEL_0.GTPE2_CHANNEL.SATA_MIN_INIT[0] 28_160 +GTP_CHANNEL_0.GTPE2_CHANNEL.SATA_MIN_INIT[1] 29_160 +GTP_CHANNEL_0.GTPE2_CHANNEL.SATA_MIN_INIT[2] 28_161 +GTP_CHANNEL_0.GTPE2_CHANNEL.SATA_MIN_INIT[3] 29_161 +GTP_CHANNEL_0.GTPE2_CHANNEL.SATA_MIN_INIT[4] 28_162 +GTP_CHANNEL_0.GTPE2_CHANNEL.SATA_MIN_INIT[5] 29_162 +GTP_CHANNEL_0.GTPE2_CHANNEL.SATA_MIN_WAKE[0] 28_163 +GTP_CHANNEL_0.GTPE2_CHANNEL.SATA_MIN_WAKE[1] 29_163 +GTP_CHANNEL_0.GTPE2_CHANNEL.SATA_MIN_WAKE[2] 28_164 +GTP_CHANNEL_0.GTPE2_CHANNEL.SATA_MIN_WAKE[3] 29_164 +GTP_CHANNEL_0.GTPE2_CHANNEL.SATA_MIN_WAKE[4] 28_165 +GTP_CHANNEL_0.GTPE2_CHANNEL.SATA_MIN_WAKE[5] 29_165 +GTP_CHANNEL_0.GTPE2_CHANNEL.SATA_PLL_CFG.VCO_1500MHZ 30_55 +GTP_CHANNEL_0.GTPE2_CHANNEL.SATA_PLL_CFG.VCO_750MHZ 31_55 +GTP_CHANNEL_0.GTPE2_CHANNEL.SHOW_REALIGN_COMMA 29_522 +GTP_CHANNEL_0.GTPE2_CHANNEL.TERM_RCAL_CFG[0] 30_136 +GTP_CHANNEL_0.GTPE2_CHANNEL.TERM_RCAL_CFG[1] 31_136 +GTP_CHANNEL_0.GTPE2_CHANNEL.TERM_RCAL_CFG[2] 30_137 +GTP_CHANNEL_0.GTPE2_CHANNEL.TERM_RCAL_CFG[3] 31_137 +GTP_CHANNEL_0.GTPE2_CHANNEL.TERM_RCAL_CFG[4] 30_138 +GTP_CHANNEL_0.GTPE2_CHANNEL.TERM_RCAL_CFG[5] 31_138 +GTP_CHANNEL_0.GTPE2_CHANNEL.TERM_RCAL_CFG[6] 30_139 +GTP_CHANNEL_0.GTPE2_CHANNEL.TERM_RCAL_CFG[7] 31_139 +GTP_CHANNEL_0.GTPE2_CHANNEL.TERM_RCAL_CFG[8] 30_140 +GTP_CHANNEL_0.GTPE2_CHANNEL.TERM_RCAL_CFG[9] 31_140 +GTP_CHANNEL_0.GTPE2_CHANNEL.TERM_RCAL_CFG[10] 30_141 +GTP_CHANNEL_0.GTPE2_CHANNEL.TERM_RCAL_CFG[11] 31_141 +GTP_CHANNEL_0.GTPE2_CHANNEL.TERM_RCAL_CFG[12] 30_142 +GTP_CHANNEL_0.GTPE2_CHANNEL.TERM_RCAL_CFG[13] 31_142 +GTP_CHANNEL_0.GTPE2_CHANNEL.TERM_RCAL_CFG[14] 30_143 +GTP_CHANNEL_0.GTPE2_CHANNEL.TERM_RCAL_OVRD[0] 31_150 +GTP_CHANNEL_0.GTPE2_CHANNEL.TERM_RCAL_OVRD[1] 30_151 +GTP_CHANNEL_0.GTPE2_CHANNEL.TERM_RCAL_OVRD[2] 31_151 +GTP_CHANNEL_0.GTPE2_CHANNEL.TRANS_TIME_RATE[0] 28_192 +GTP_CHANNEL_0.GTPE2_CHANNEL.TRANS_TIME_RATE[1] 29_192 +GTP_CHANNEL_0.GTPE2_CHANNEL.TRANS_TIME_RATE[2] 28_193 +GTP_CHANNEL_0.GTPE2_CHANNEL.TRANS_TIME_RATE[3] 29_193 +GTP_CHANNEL_0.GTPE2_CHANNEL.TRANS_TIME_RATE[4] 28_194 +GTP_CHANNEL_0.GTPE2_CHANNEL.TRANS_TIME_RATE[5] 29_194 +GTP_CHANNEL_0.GTPE2_CHANNEL.TRANS_TIME_RATE[6] 28_195 +GTP_CHANNEL_0.GTPE2_CHANNEL.TRANS_TIME_RATE[7] 29_195 +GTP_CHANNEL_0.GTPE2_CHANNEL.TST_RSV[0] 30_504 +GTP_CHANNEL_0.GTPE2_CHANNEL.TST_RSV[1] 31_504 +GTP_CHANNEL_0.GTPE2_CHANNEL.TST_RSV[2] 30_505 +GTP_CHANNEL_0.GTPE2_CHANNEL.TST_RSV[3] 31_505 +GTP_CHANNEL_0.GTPE2_CHANNEL.TST_RSV[4] 30_506 +GTP_CHANNEL_0.GTPE2_CHANNEL.TST_RSV[5] 31_506 +GTP_CHANNEL_0.GTPE2_CHANNEL.TST_RSV[6] 30_507 +GTP_CHANNEL_0.GTPE2_CHANNEL.TST_RSV[7] 31_507 +GTP_CHANNEL_0.GTPE2_CHANNEL.TST_RSV[8] 30_508 +GTP_CHANNEL_0.GTPE2_CHANNEL.TST_RSV[9] 31_508 +GTP_CHANNEL_0.GTPE2_CHANNEL.TST_RSV[10] 30_509 +GTP_CHANNEL_0.GTPE2_CHANNEL.TST_RSV[11] 31_509 +GTP_CHANNEL_0.GTPE2_CHANNEL.TST_RSV[12] 30_510 +GTP_CHANNEL_0.GTPE2_CHANNEL.TST_RSV[13] 31_510 +GTP_CHANNEL_0.GTPE2_CHANNEL.TST_RSV[14] 30_511 +GTP_CHANNEL_0.GTPE2_CHANNEL.TST_RSV[15] 31_511 +GTP_CHANNEL_0.GTPE2_CHANNEL.TST_RSV[16] 30_512 +GTP_CHANNEL_0.GTPE2_CHANNEL.TST_RSV[17] 31_512 +GTP_CHANNEL_0.GTPE2_CHANNEL.TST_RSV[18] 30_513 +GTP_CHANNEL_0.GTPE2_CHANNEL.TST_RSV[19] 31_513 +GTP_CHANNEL_0.GTPE2_CHANNEL.TST_RSV[20] 30_514 +GTP_CHANNEL_0.GTPE2_CHANNEL.TST_RSV[21] 31_514 +GTP_CHANNEL_0.GTPE2_CHANNEL.TST_RSV[22] 30_515 +GTP_CHANNEL_0.GTPE2_CHANNEL.TST_RSV[23] 31_515 +GTP_CHANNEL_0.GTPE2_CHANNEL.TST_RSV[24] 30_516 +GTP_CHANNEL_0.GTPE2_CHANNEL.TST_RSV[25] 31_516 +GTP_CHANNEL_0.GTPE2_CHANNEL.TST_RSV[26] 30_517 +GTP_CHANNEL_0.GTPE2_CHANNEL.TST_RSV[27] 31_517 +GTP_CHANNEL_0.GTPE2_CHANNEL.TST_RSV[28] 30_518 +GTP_CHANNEL_0.GTPE2_CHANNEL.TST_RSV[29] 31_518 +GTP_CHANNEL_0.GTPE2_CHANNEL.TST_RSV[30] 30_519 +GTP_CHANNEL_0.GTPE2_CHANNEL.TST_RSV[31] 31_519 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_CLKMUX_EN[0] 31_128 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_DATA_WIDTH[0] 30_152 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_DATA_WIDTH[1] 31_152 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_DATA_WIDTH[2] 30_153 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_DRIVE_MODE.PIPE 28_200 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_EIDLE_ASSERT_DELAY[0] 28_203 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_EIDLE_ASSERT_DELAY[1] 29_203 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_EIDLE_ASSERT_DELAY[2] 28_204 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_EIDLE_DEASSERT_DELAY[0] 29_204 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_EIDLE_DEASSERT_DELAY[1] 28_205 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_EIDLE_DEASSERT_DELAY[2] 29_205 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_LOOPBACK_DRIVE_HIZ 29_202 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_MAINCURSOR_SEL[0] 31_289 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_MARGIN_FULL_0[0] 30_232 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_MARGIN_FULL_0[1] 31_232 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_MARGIN_FULL_0[2] 30_233 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_MARGIN_FULL_0[3] 31_233 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_MARGIN_FULL_0[4] 30_234 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_MARGIN_FULL_0[5] 31_234 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_MARGIN_FULL_0[6] 30_235 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_MARGIN_FULL_1[0] 30_236 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_MARGIN_FULL_1[1] 31_236 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_MARGIN_FULL_1[2] 30_237 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_MARGIN_FULL_1[3] 31_237 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_MARGIN_FULL_1[4] 30_238 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_MARGIN_FULL_1[5] 31_238 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_MARGIN_FULL_1[6] 30_239 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_MARGIN_FULL_2[0] 30_240 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_MARGIN_FULL_2[1] 31_240 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_MARGIN_FULL_2[2] 30_241 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_MARGIN_FULL_2[3] 31_241 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_MARGIN_FULL_2[4] 30_242 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_MARGIN_FULL_2[5] 31_242 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_MARGIN_FULL_2[6] 30_243 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_MARGIN_FULL_3[0] 30_244 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_MARGIN_FULL_3[1] 31_244 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_MARGIN_FULL_3[2] 30_245 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_MARGIN_FULL_3[3] 31_245 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_MARGIN_FULL_3[4] 30_246 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_MARGIN_FULL_3[5] 31_246 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_MARGIN_FULL_3[6] 30_247 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_MARGIN_FULL_4[0] 30_248 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_MARGIN_FULL_4[1] 31_248 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_MARGIN_FULL_4[2] 30_249 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_MARGIN_FULL_4[3] 31_249 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_MARGIN_FULL_4[4] 30_250 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_MARGIN_FULL_4[5] 31_250 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_MARGIN_FULL_4[6] 30_251 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_MARGIN_LOW_0[0] 30_252 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_MARGIN_LOW_0[1] 31_252 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_MARGIN_LOW_0[2] 30_253 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_MARGIN_LOW_0[3] 31_253 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_MARGIN_LOW_0[4] 30_254 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_MARGIN_LOW_0[5] 31_254 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_MARGIN_LOW_0[6] 30_255 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_MARGIN_LOW_1[0] 30_256 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_MARGIN_LOW_1[1] 31_256 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_MARGIN_LOW_1[2] 30_257 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_MARGIN_LOW_1[3] 31_257 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_MARGIN_LOW_1[4] 30_258 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_MARGIN_LOW_1[5] 31_258 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_MARGIN_LOW_1[6] 30_259 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_MARGIN_LOW_2[0] 30_260 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_MARGIN_LOW_2[1] 31_260 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_MARGIN_LOW_2[2] 30_261 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_MARGIN_LOW_2[3] 31_261 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_MARGIN_LOW_2[4] 30_262 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_MARGIN_LOW_2[5] 31_262 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_MARGIN_LOW_2[6] 30_263 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_MARGIN_LOW_3[0] 30_264 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_MARGIN_LOW_3[1] 31_264 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_MARGIN_LOW_3[2] 30_265 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_MARGIN_LOW_3[3] 31_265 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_MARGIN_LOW_3[4] 30_266 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_MARGIN_LOW_3[5] 31_266 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_MARGIN_LOW_3[6] 30_267 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_MARGIN_LOW_4[0] 30_268 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_MARGIN_LOW_4[1] 31_268 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_MARGIN_LOW_4[2] 30_269 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_MARGIN_LOW_4[3] 31_269 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_MARGIN_LOW_4[4] 30_270 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_MARGIN_LOW_4[5] 31_270 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_MARGIN_LOW_4[6] 30_271 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_PREDRIVER_MODE[0] 28_206 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_RXDETECT_CFG[0] 30_296 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_RXDETECT_CFG[1] 31_296 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_RXDETECT_CFG[2] 30_297 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_RXDETECT_CFG[3] 31_297 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_RXDETECT_CFG[4] 30_298 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_RXDETECT_CFG[5] 31_298 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_RXDETECT_CFG[6] 30_299 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_RXDETECT_CFG[7] 31_299 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_RXDETECT_CFG[8] 30_300 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_RXDETECT_CFG[9] 31_300 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_RXDETECT_CFG[10] 30_301 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_RXDETECT_CFG[11] 31_301 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_RXDETECT_CFG[12] 30_302 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_RXDETECT_CFG[13] 31_302 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_RXDETECT_REF[0] 30_292 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_RXDETECT_REF[1] 31_292 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_RXDETECT_REF[2] 30_293 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_XCLK_SEL.TXUSR 31_11 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_CLK25_DIV[0] 30_144 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_CLK25_DIV[1] 31_144 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_CLK25_DIV[2] 30_145 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_CLK25_DIV[3] 31_145 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_CLK25_DIV[4] 30_146 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_DEEMPH0[0] 30_272 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_DEEMPH0[1] 31_272 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_DEEMPH0[2] 30_273 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_DEEMPH0[3] 31_273 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_DEEMPH0[4] 30_274 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_DEEMPH0[5] 31_274 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_DEEMPH1[0] 30_276 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_DEEMPH1[1] 31_276 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_DEEMPH1[2] 30_277 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_DEEMPH1[3] 31_277 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_DEEMPH1[4] 30_278 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_DEEMPH1[5] 31_278 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXBUF_EN 28_231 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXBUF_RESET_ON_RATE_CHANGE 29_231 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXDLY_CFG[0] 30_80 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXDLY_CFG[1] 31_80 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXDLY_CFG[2] 30_81 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXDLY_CFG[3] 31_81 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXDLY_CFG[4] 30_82 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXDLY_CFG[5] 31_82 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXDLY_CFG[6] 30_83 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXDLY_CFG[7] 31_83 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXDLY_CFG[8] 30_84 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXDLY_CFG[9] 31_84 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXDLY_CFG[10] 30_85 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXDLY_CFG[11] 31_85 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXDLY_CFG[12] 30_86 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXDLY_CFG[13] 31_86 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXDLY_CFG[14] 30_87 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXDLY_CFG[15] 31_87 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXDLY_LCFG[0] 30_568 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXDLY_LCFG[1] 31_568 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXDLY_LCFG[2] 30_569 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXDLY_LCFG[3] 31_569 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXDLY_LCFG[4] 30_570 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXDLY_LCFG[5] 31_570 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXDLY_LCFG[6] 30_571 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXDLY_LCFG[7] 31_571 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXDLY_LCFG[8] 30_572 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXDLY_TAP_CFG[0] 30_88 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXDLY_TAP_CFG[1] 31_88 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXDLY_TAP_CFG[2] 30_89 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXDLY_TAP_CFG[3] 31_89 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXDLY_TAP_CFG[4] 30_90 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXDLY_TAP_CFG[5] 31_90 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXDLY_TAP_CFG[6] 30_91 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXDLY_TAP_CFG[7] 31_91 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXDLY_TAP_CFG[8] 30_92 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXDLY_TAP_CFG[9] 31_92 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXDLY_TAP_CFG[10] 30_93 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXDLY_TAP_CFG[11] 31_93 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXDLY_TAP_CFG[12] 30_94 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXDLY_TAP_CFG[13] 31_94 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXDLY_TAP_CFG[14] 30_95 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXDLY_TAP_CFG[15] 31_95 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXGEARBOX_EN 29_226 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXOOB_CFG[0] 31_20 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXOUT_DIV[0] 30_386 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXOUT_DIV[1] 31_386 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPCSRESET_TIME[0] 29_130 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPCSRESET_TIME[1] 28_131 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPCSRESET_TIME[2] 29_131 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPCSRESET_TIME[3] 28_132 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPCSRESET_TIME[4] 29_132 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPH_CFG[0] 30_96 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPH_CFG[1] 31_96 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPH_CFG[2] 30_97 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPH_CFG[3] 31_97 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPH_CFG[4] 30_98 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPH_CFG[5] 31_98 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPH_CFG[6] 30_99 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPH_CFG[7] 31_99 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPH_CFG[8] 30_100 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPH_CFG[9] 31_100 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPH_CFG[10] 30_101 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPH_CFG[11] 31_101 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPH_CFG[12] 30_102 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPH_CFG[13] 31_102 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPH_CFG[14] 30_103 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPH_CFG[15] 31_103 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPH_MONITOR_SEL[0] 30_108 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPH_MONITOR_SEL[1] 31_108 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPH_MONITOR_SEL[2] 30_109 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPH_MONITOR_SEL[3] 31_109 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPH_MONITOR_SEL[4] 30_110 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPHDLY_CFG[0] 30_64 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPHDLY_CFG[1] 31_64 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPHDLY_CFG[2] 30_65 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPHDLY_CFG[3] 31_65 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPHDLY_CFG[4] 30_66 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPHDLY_CFG[5] 31_66 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPHDLY_CFG[6] 30_67 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPHDLY_CFG[7] 31_67 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPHDLY_CFG[8] 30_68 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPHDLY_CFG[9] 31_68 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPHDLY_CFG[10] 30_69 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPHDLY_CFG[11] 31_69 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPHDLY_CFG[12] 30_70 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPHDLY_CFG[13] 31_70 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPHDLY_CFG[14] 30_71 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPHDLY_CFG[15] 31_71 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPHDLY_CFG[16] 30_72 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPHDLY_CFG[17] 31_72 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPHDLY_CFG[18] 30_73 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPHDLY_CFG[19] 31_73 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPHDLY_CFG[20] 30_74 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPHDLY_CFG[21] 31_74 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPHDLY_CFG[22] 30_75 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPHDLY_CFG[23] 31_75 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPI_GREY_SEL[0] 31_498 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPI_INVSTROBE_SEL[0] 30_498 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPI_PPM_CFG[0] 30_488 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPI_PPM_CFG[1] 31_488 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPI_PPM_CFG[2] 30_489 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPI_PPM_CFG[3] 31_489 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPI_PPM_CFG[4] 30_490 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPI_PPM_CFG[5] 31_490 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPI_PPM_CFG[6] 30_491 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPI_PPM_CFG[7] 31_491 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPI_PPMCLK_SEL.TXUSRCLK2 31_497 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPI_SYNFREQ_PPM[0] 30_496 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPI_SYNFREQ_PPM[1] 31_496 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPI_SYNFREQ_PPM[2] 30_497 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPI_CFG0[0] 30_40 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPI_CFG0[1] 31_40 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPI_CFG1[0] 30_41 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPI_CFG1[1] 31_41 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPI_CFG2[0] 30_42 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPI_CFG2[1] 31_42 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPI_CFG3[0] 30_43 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPI_CFG4[0] 31_43 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPI_CFG5[0] 30_44 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPI_CFG5[1] 31_44 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPI_CFG5[2] 30_45 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPMARESET_TIME[0] 28_128 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPMARESET_TIME[1] 29_128 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPMARESET_TIME[2] 28_129 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPMARESET_TIME[3] 29_129 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPMARESET_TIME[4] 28_130 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXSYNC_MULTILANE[0] 29_133 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXSYNC_OVRD[0] 28_135 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXSYNC_SKIP_DA[0] 28_134 +GTP_CHANNEL_0.GTPE2_CHANNEL.UCODEER_CLR[0] 29_00 +GTP_CHANNEL_0.GTPE2_CHANNEL.USE_PCS_CLK_PHASE_SEL[0] 30_463 diff --git a/artix7/segbits_gtp_channel_0.origin_info.db b/artix7/segbits_gtp_channel_0.origin_info.db index b72f73f..436ded3 100644 --- a/artix7/segbits_gtp_channel_0.origin_info.db +++ b/artix7/segbits_gtp_channel_0.origin_info.db @@ -1,1627 +1,1627 @@ -GTP_CHANNEL_0.GTPE2.ACJTAG_DEBUG_MODE[0] origin:064-gtp-channel-conf 28_07 -GTP_CHANNEL_0.GTPE2.ACJTAG_MODE[0] origin:064-gtp-channel-conf 29_06 -GTP_CHANNEL_0.GTPE2.ACJTAG_RESET[0] origin:064-gtp-channel-conf 29_07 -GTP_CHANNEL_0.GTPE2.ADAPT_CFG0[0] origin:064-gtp-channel-conf 30_464 -GTP_CHANNEL_0.GTPE2.ADAPT_CFG0[1] origin:064-gtp-channel-conf 31_464 -GTP_CHANNEL_0.GTPE2.ADAPT_CFG0[2] origin:064-gtp-channel-conf 30_465 -GTP_CHANNEL_0.GTPE2.ADAPT_CFG0[3] origin:064-gtp-channel-conf 31_465 -GTP_CHANNEL_0.GTPE2.ADAPT_CFG0[4] origin:064-gtp-channel-conf 30_466 -GTP_CHANNEL_0.GTPE2.ADAPT_CFG0[5] origin:064-gtp-channel-conf 31_466 -GTP_CHANNEL_0.GTPE2.ADAPT_CFG0[6] origin:064-gtp-channel-conf 30_467 -GTP_CHANNEL_0.GTPE2.ADAPT_CFG0[7] origin:064-gtp-channel-conf 31_467 -GTP_CHANNEL_0.GTPE2.ADAPT_CFG0[8] origin:064-gtp-channel-conf 30_468 -GTP_CHANNEL_0.GTPE2.ADAPT_CFG0[9] origin:064-gtp-channel-conf 31_468 -GTP_CHANNEL_0.GTPE2.ADAPT_CFG0[10] origin:064-gtp-channel-conf 30_469 -GTP_CHANNEL_0.GTPE2.ADAPT_CFG0[11] origin:064-gtp-channel-conf 31_469 -GTP_CHANNEL_0.GTPE2.ADAPT_CFG0[12] origin:064-gtp-channel-conf 30_470 -GTP_CHANNEL_0.GTPE2.ADAPT_CFG0[13] origin:064-gtp-channel-conf 31_470 -GTP_CHANNEL_0.GTPE2.ADAPT_CFG0[14] origin:064-gtp-channel-conf 30_471 -GTP_CHANNEL_0.GTPE2.ADAPT_CFG0[15] origin:064-gtp-channel-conf 31_471 -GTP_CHANNEL_0.GTPE2.ADAPT_CFG0[16] origin:064-gtp-channel-conf 30_472 -GTP_CHANNEL_0.GTPE2.ADAPT_CFG0[17] origin:064-gtp-channel-conf 31_472 -GTP_CHANNEL_0.GTPE2.ADAPT_CFG0[18] origin:064-gtp-channel-conf 30_473 -GTP_CHANNEL_0.GTPE2.ADAPT_CFG0[19] origin:064-gtp-channel-conf 31_473 -GTP_CHANNEL_0.GTPE2.ALIGN_COMMA_DOUBLE origin:064-gtp-channel-conf 28_522 -GTP_CHANNEL_0.GTPE2.ALIGN_COMMA_ENABLE[0] origin:064-gtp-channel-conf 28_496 -GTP_CHANNEL_0.GTPE2.ALIGN_COMMA_ENABLE[1] origin:064-gtp-channel-conf 29_496 -GTP_CHANNEL_0.GTPE2.ALIGN_COMMA_ENABLE[2] origin:064-gtp-channel-conf 28_497 -GTP_CHANNEL_0.GTPE2.ALIGN_COMMA_ENABLE[3] origin:064-gtp-channel-conf 29_497 -GTP_CHANNEL_0.GTPE2.ALIGN_COMMA_ENABLE[4] origin:064-gtp-channel-conf 28_498 -GTP_CHANNEL_0.GTPE2.ALIGN_COMMA_ENABLE[5] origin:064-gtp-channel-conf 29_498 -GTP_CHANNEL_0.GTPE2.ALIGN_COMMA_ENABLE[6] origin:064-gtp-channel-conf 28_499 -GTP_CHANNEL_0.GTPE2.ALIGN_COMMA_ENABLE[7] origin:064-gtp-channel-conf 29_499 -GTP_CHANNEL_0.GTPE2.ALIGN_COMMA_ENABLE[8] origin:064-gtp-channel-conf 28_500 -GTP_CHANNEL_0.GTPE2.ALIGN_COMMA_ENABLE[9] origin:064-gtp-channel-conf 29_500 -GTP_CHANNEL_0.GTPE2.ALIGN_COMMA_WORD[0] origin:064-gtp-channel-conf 29_526 -GTP_CHANNEL_0.GTPE2.ALIGN_COMMA_WORD[1] origin:064-gtp-channel-conf 28_527 -GTP_CHANNEL_0.GTPE2.ALIGN_MCOMMA_DET origin:064-gtp-channel-conf 28_523 -GTP_CHANNEL_0.GTPE2.ALIGN_MCOMMA_VALUE[0] origin:064-gtp-channel-conf 28_504 -GTP_CHANNEL_0.GTPE2.ALIGN_MCOMMA_VALUE[1] origin:064-gtp-channel-conf 29_504 -GTP_CHANNEL_0.GTPE2.ALIGN_MCOMMA_VALUE[2] origin:064-gtp-channel-conf 28_505 -GTP_CHANNEL_0.GTPE2.ALIGN_MCOMMA_VALUE[3] origin:064-gtp-channel-conf 29_505 -GTP_CHANNEL_0.GTPE2.ALIGN_MCOMMA_VALUE[4] origin:064-gtp-channel-conf 28_506 -GTP_CHANNEL_0.GTPE2.ALIGN_MCOMMA_VALUE[5] origin:064-gtp-channel-conf 29_506 -GTP_CHANNEL_0.GTPE2.ALIGN_MCOMMA_VALUE[6] origin:064-gtp-channel-conf 28_507 -GTP_CHANNEL_0.GTPE2.ALIGN_MCOMMA_VALUE[7] origin:064-gtp-channel-conf 29_507 -GTP_CHANNEL_0.GTPE2.ALIGN_MCOMMA_VALUE[8] origin:064-gtp-channel-conf 28_508 -GTP_CHANNEL_0.GTPE2.ALIGN_MCOMMA_VALUE[9] origin:064-gtp-channel-conf 29_508 -GTP_CHANNEL_0.GTPE2.ALIGN_PCOMMA_DET origin:064-gtp-channel-conf 29_523 -GTP_CHANNEL_0.GTPE2.ALIGN_PCOMMA_VALUE[0] origin:064-gtp-channel-conf 28_512 -GTP_CHANNEL_0.GTPE2.ALIGN_PCOMMA_VALUE[1] origin:064-gtp-channel-conf 29_512 -GTP_CHANNEL_0.GTPE2.ALIGN_PCOMMA_VALUE[2] origin:064-gtp-channel-conf 28_513 -GTP_CHANNEL_0.GTPE2.ALIGN_PCOMMA_VALUE[3] origin:064-gtp-channel-conf 29_513 -GTP_CHANNEL_0.GTPE2.ALIGN_PCOMMA_VALUE[4] origin:064-gtp-channel-conf 28_514 -GTP_CHANNEL_0.GTPE2.ALIGN_PCOMMA_VALUE[5] origin:064-gtp-channel-conf 29_514 -GTP_CHANNEL_0.GTPE2.ALIGN_PCOMMA_VALUE[6] origin:064-gtp-channel-conf 28_515 -GTP_CHANNEL_0.GTPE2.ALIGN_PCOMMA_VALUE[7] origin:064-gtp-channel-conf 29_515 -GTP_CHANNEL_0.GTPE2.ALIGN_PCOMMA_VALUE[8] origin:064-gtp-channel-conf 28_516 -GTP_CHANNEL_0.GTPE2.ALIGN_PCOMMA_VALUE[9] origin:064-gtp-channel-conf 29_516 -GTP_CHANNEL_0.GTPE2.CBCC_DATA_SOURCE_SEL.DECODED origin:064-gtp-channel-conf 29_661 -GTP_CHANNEL_0.GTPE2.CFOK_CFG[0] origin:064-gtp-channel-conf 30_392 -GTP_CHANNEL_0.GTPE2.CFOK_CFG[1] origin:064-gtp-channel-conf 31_392 -GTP_CHANNEL_0.GTPE2.CFOK_CFG[2] origin:064-gtp-channel-conf 30_393 -GTP_CHANNEL_0.GTPE2.CFOK_CFG[3] origin:064-gtp-channel-conf 31_393 -GTP_CHANNEL_0.GTPE2.CFOK_CFG[4] origin:064-gtp-channel-conf 30_394 -GTP_CHANNEL_0.GTPE2.CFOK_CFG[5] origin:064-gtp-channel-conf 31_394 -GTP_CHANNEL_0.GTPE2.CFOK_CFG[6] origin:064-gtp-channel-conf 30_395 -GTP_CHANNEL_0.GTPE2.CFOK_CFG[7] origin:064-gtp-channel-conf 31_395 -GTP_CHANNEL_0.GTPE2.CFOK_CFG[8] origin:064-gtp-channel-conf 30_396 -GTP_CHANNEL_0.GTPE2.CFOK_CFG[9] origin:064-gtp-channel-conf 31_396 -GTP_CHANNEL_0.GTPE2.CFOK_CFG[10] origin:064-gtp-channel-conf 30_397 -GTP_CHANNEL_0.GTPE2.CFOK_CFG[11] origin:064-gtp-channel-conf 31_397 -GTP_CHANNEL_0.GTPE2.CFOK_CFG[12] origin:064-gtp-channel-conf 30_398 -GTP_CHANNEL_0.GTPE2.CFOK_CFG[13] origin:064-gtp-channel-conf 31_398 -GTP_CHANNEL_0.GTPE2.CFOK_CFG[14] origin:064-gtp-channel-conf 30_399 -GTP_CHANNEL_0.GTPE2.CFOK_CFG[15] origin:064-gtp-channel-conf 31_399 -GTP_CHANNEL_0.GTPE2.CFOK_CFG[16] origin:064-gtp-channel-conf 30_400 -GTP_CHANNEL_0.GTPE2.CFOK_CFG[17] origin:064-gtp-channel-conf 31_400 -GTP_CHANNEL_0.GTPE2.CFOK_CFG[18] origin:064-gtp-channel-conf 30_401 -GTP_CHANNEL_0.GTPE2.CFOK_CFG[19] origin:064-gtp-channel-conf 31_401 -GTP_CHANNEL_0.GTPE2.CFOK_CFG[20] origin:064-gtp-channel-conf 30_402 -GTP_CHANNEL_0.GTPE2.CFOK_CFG[21] origin:064-gtp-channel-conf 31_402 -GTP_CHANNEL_0.GTPE2.CFOK_CFG[22] origin:064-gtp-channel-conf 30_403 -GTP_CHANNEL_0.GTPE2.CFOK_CFG[23] origin:064-gtp-channel-conf 31_403 -GTP_CHANNEL_0.GTPE2.CFOK_CFG[24] origin:064-gtp-channel-conf 30_404 -GTP_CHANNEL_0.GTPE2.CFOK_CFG[25] origin:064-gtp-channel-conf 31_404 -GTP_CHANNEL_0.GTPE2.CFOK_CFG[26] origin:064-gtp-channel-conf 30_405 -GTP_CHANNEL_0.GTPE2.CFOK_CFG[27] origin:064-gtp-channel-conf 31_405 -GTP_CHANNEL_0.GTPE2.CFOK_CFG[28] origin:064-gtp-channel-conf 30_406 -GTP_CHANNEL_0.GTPE2.CFOK_CFG[29] origin:064-gtp-channel-conf 31_406 -GTP_CHANNEL_0.GTPE2.CFOK_CFG[30] origin:064-gtp-channel-conf 30_407 -GTP_CHANNEL_0.GTPE2.CFOK_CFG[31] origin:064-gtp-channel-conf 31_407 -GTP_CHANNEL_0.GTPE2.CFOK_CFG[32] origin:064-gtp-channel-conf 30_408 -GTP_CHANNEL_0.GTPE2.CFOK_CFG[33] origin:064-gtp-channel-conf 31_408 -GTP_CHANNEL_0.GTPE2.CFOK_CFG[34] origin:064-gtp-channel-conf 30_409 -GTP_CHANNEL_0.GTPE2.CFOK_CFG[35] origin:064-gtp-channel-conf 31_409 -GTP_CHANNEL_0.GTPE2.CFOK_CFG[36] origin:064-gtp-channel-conf 30_410 -GTP_CHANNEL_0.GTPE2.CFOK_CFG[37] origin:064-gtp-channel-conf 31_410 -GTP_CHANNEL_0.GTPE2.CFOK_CFG[38] origin:064-gtp-channel-conf 30_411 -GTP_CHANNEL_0.GTPE2.CFOK_CFG[39] origin:064-gtp-channel-conf 31_411 -GTP_CHANNEL_0.GTPE2.CFOK_CFG[40] origin:064-gtp-channel-conf 30_412 -GTP_CHANNEL_0.GTPE2.CFOK_CFG[41] origin:064-gtp-channel-conf 31_412 -GTP_CHANNEL_0.GTPE2.CFOK_CFG[42] origin:064-gtp-channel-conf 30_413 -GTP_CHANNEL_0.GTPE2.CFOK_CFG2[0] origin:064-gtp-channel-conf 30_459 -GTP_CHANNEL_0.GTPE2.CFOK_CFG2[1] origin:064-gtp-channel-conf 31_459 -GTP_CHANNEL_0.GTPE2.CFOK_CFG2[2] origin:064-gtp-channel-conf 30_460 -GTP_CHANNEL_0.GTPE2.CFOK_CFG2[3] origin:064-gtp-channel-conf 31_460 -GTP_CHANNEL_0.GTPE2.CFOK_CFG2[4] origin:064-gtp-channel-conf 30_461 -GTP_CHANNEL_0.GTPE2.CFOK_CFG2[5] origin:064-gtp-channel-conf 31_461 -GTP_CHANNEL_0.GTPE2.CFOK_CFG2[6] origin:064-gtp-channel-conf 30_462 -GTP_CHANNEL_0.GTPE2.CFOK_CFG3[0] origin:064-gtp-channel-conf 30_416 -GTP_CHANNEL_0.GTPE2.CFOK_CFG3[1] origin:064-gtp-channel-conf 31_416 -GTP_CHANNEL_0.GTPE2.CFOK_CFG3[2] origin:064-gtp-channel-conf 30_417 -GTP_CHANNEL_0.GTPE2.CFOK_CFG3[3] origin:064-gtp-channel-conf 31_417 -GTP_CHANNEL_0.GTPE2.CFOK_CFG3[4] origin:064-gtp-channel-conf 30_418 -GTP_CHANNEL_0.GTPE2.CFOK_CFG3[5] origin:064-gtp-channel-conf 31_418 -GTP_CHANNEL_0.GTPE2.CFOK_CFG3[6] origin:064-gtp-channel-conf 30_419 -GTP_CHANNEL_0.GTPE2.CFOK_CFG4[0] origin:064-gtp-channel-conf 31_438 -GTP_CHANNEL_0.GTPE2.CFOK_CFG5[0] origin:064-gtp-channel-conf 30_429 -GTP_CHANNEL_0.GTPE2.CFOK_CFG5[1] origin:064-gtp-channel-conf 31_429 -GTP_CHANNEL_0.GTPE2.CFOK_CFG6[0] origin:064-gtp-channel-conf 31_436 -GTP_CHANNEL_0.GTPE2.CFOK_CFG6[1] origin:064-gtp-channel-conf 30_437 -GTP_CHANNEL_0.GTPE2.CFOK_CFG6[2] origin:064-gtp-channel-conf 31_437 -GTP_CHANNEL_0.GTPE2.CFOK_CFG6[3] origin:064-gtp-channel-conf 30_438 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_KEEP_ALIGN origin:064-gtp-channel-conf 29_631 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_MAX_SKEW[0] origin:064-gtp-channel-conf 28_670 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_MAX_SKEW[1] origin:064-gtp-channel-conf 29_670 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_MAX_SKEW[2] origin:064-gtp-channel-conf 28_671 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_MAX_SKEW[3] origin:064-gtp-channel-conf 29_671 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_1_1[0] origin:064-gtp-channel-conf 28_608 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_1_1[1] origin:064-gtp-channel-conf 29_608 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_1_1[2] origin:064-gtp-channel-conf 28_609 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_1_1[3] origin:064-gtp-channel-conf 29_609 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_1_1[4] origin:064-gtp-channel-conf 28_610 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_1_1[5] origin:064-gtp-channel-conf 29_610 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_1_1[6] origin:064-gtp-channel-conf 28_611 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_1_1[7] origin:064-gtp-channel-conf 29_611 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_1_1[8] origin:064-gtp-channel-conf 28_612 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_1_1[9] origin:064-gtp-channel-conf 29_612 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_1_2[0] origin:064-gtp-channel-conf 28_616 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_1_2[1] origin:064-gtp-channel-conf 29_616 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_1_2[2] origin:064-gtp-channel-conf 28_617 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_1_2[3] origin:064-gtp-channel-conf 29_617 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_1_2[4] origin:064-gtp-channel-conf 28_618 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_1_2[5] origin:064-gtp-channel-conf 29_618 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_1_2[6] origin:064-gtp-channel-conf 28_619 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_1_2[7] origin:064-gtp-channel-conf 29_619 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_1_2[8] origin:064-gtp-channel-conf 28_620 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_1_2[9] origin:064-gtp-channel-conf 29_620 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_1_3[0] origin:064-gtp-channel-conf 28_624 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_1_3[1] origin:064-gtp-channel-conf 29_624 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_1_3[2] origin:064-gtp-channel-conf 28_625 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_1_3[3] origin:064-gtp-channel-conf 29_625 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_1_3[4] origin:064-gtp-channel-conf 28_626 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_1_3[5] origin:064-gtp-channel-conf 29_626 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_1_3[6] origin:064-gtp-channel-conf 28_627 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_1_3[7] origin:064-gtp-channel-conf 29_627 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_1_3[8] origin:064-gtp-channel-conf 28_628 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_1_3[9] origin:064-gtp-channel-conf 29_628 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_1_4[0] origin:064-gtp-channel-conf 28_632 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_1_4[1] origin:064-gtp-channel-conf 29_632 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_1_4[2] origin:064-gtp-channel-conf 28_633 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_1_4[3] origin:064-gtp-channel-conf 29_633 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_1_4[4] origin:064-gtp-channel-conf 28_634 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_1_4[5] origin:064-gtp-channel-conf 29_634 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_1_4[6] origin:064-gtp-channel-conf 28_635 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_1_4[7] origin:064-gtp-channel-conf 29_635 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_1_4[8] origin:064-gtp-channel-conf 28_636 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_1_4[9] origin:064-gtp-channel-conf 29_636 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_1_ENABLE[0] origin:064-gtp-channel-conf 28_614 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_1_ENABLE[1] origin:064-gtp-channel-conf 29_614 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_1_ENABLE[2] origin:064-gtp-channel-conf 28_615 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_1_ENABLE[3] origin:064-gtp-channel-conf 29_615 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_2_1[0] origin:064-gtp-channel-conf 28_640 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_2_1[1] origin:064-gtp-channel-conf 29_640 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_2_1[2] origin:064-gtp-channel-conf 28_641 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_2_1[3] origin:064-gtp-channel-conf 29_641 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_2_1[4] origin:064-gtp-channel-conf 28_642 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_2_1[5] origin:064-gtp-channel-conf 29_642 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_2_1[6] origin:064-gtp-channel-conf 28_643 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_2_1[7] origin:064-gtp-channel-conf 29_643 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_2_1[8] origin:064-gtp-channel-conf 28_644 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_2_1[9] origin:064-gtp-channel-conf 29_644 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_2_2[0] origin:064-gtp-channel-conf 28_648 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_2_2[1] origin:064-gtp-channel-conf 29_648 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_2_2[2] origin:064-gtp-channel-conf 28_649 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_2_2[3] origin:064-gtp-channel-conf 29_649 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_2_2[4] origin:064-gtp-channel-conf 28_650 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_2_2[5] origin:064-gtp-channel-conf 29_650 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_2_2[6] origin:064-gtp-channel-conf 28_651 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_2_2[7] origin:064-gtp-channel-conf 29_651 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_2_2[8] origin:064-gtp-channel-conf 28_652 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_2_2[9] origin:064-gtp-channel-conf 29_652 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_2_3[0] origin:064-gtp-channel-conf 28_656 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_2_3[1] origin:064-gtp-channel-conf 29_656 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_2_3[2] origin:064-gtp-channel-conf 28_657 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_2_3[3] origin:064-gtp-channel-conf 29_657 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_2_3[4] origin:064-gtp-channel-conf 28_658 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_2_3[5] origin:064-gtp-channel-conf 29_658 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_2_3[6] origin:064-gtp-channel-conf 28_659 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_2_3[7] origin:064-gtp-channel-conf 29_659 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_2_3[8] origin:064-gtp-channel-conf 28_660 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_2_3[9] origin:064-gtp-channel-conf 29_660 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_2_4[0] origin:064-gtp-channel-conf 28_664 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_2_4[1] origin:064-gtp-channel-conf 29_664 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_2_4[2] origin:064-gtp-channel-conf 28_665 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_2_4[3] origin:064-gtp-channel-conf 29_665 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_2_4[4] origin:064-gtp-channel-conf 28_666 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_2_4[5] origin:064-gtp-channel-conf 29_666 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_2_4[6] origin:064-gtp-channel-conf 28_667 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_2_4[7] origin:064-gtp-channel-conf 29_667 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_2_4[8] origin:064-gtp-channel-conf 28_668 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_2_4[9] origin:064-gtp-channel-conf 29_668 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_2_ENABLE[0] origin:064-gtp-channel-conf 28_646 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_2_ENABLE[1] origin:064-gtp-channel-conf 29_646 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_2_ENABLE[2] origin:064-gtp-channel-conf 28_647 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_2_ENABLE[3] origin:064-gtp-channel-conf 29_647 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_2_USE origin:064-gtp-channel-conf 29_645 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_LEN[0] origin:064-gtp-channel-conf 28_623 -GTP_CHANNEL_0.GTPE2.CHAN_BOND_SEQ_LEN[1] origin:064-gtp-channel-conf 29_623 -GTP_CHANNEL_0.GTPE2.CLK_COMMON_SWING[0] origin:064-gtp-channel-conf 31_311 -GTP_CHANNEL_0.GTPE2.CLK_COR_KEEP_IDLE origin:064-gtp-channel-conf 28_591 -GTP_CHANNEL_0.GTPE2.CLK_COR_MAX_LAT[0] origin:064-gtp-channel-conf 28_557 -GTP_CHANNEL_0.GTPE2.CLK_COR_MAX_LAT[1] origin:064-gtp-channel-conf 29_557 -GTP_CHANNEL_0.GTPE2.CLK_COR_MAX_LAT[2] origin:064-gtp-channel-conf 28_558 -GTP_CHANNEL_0.GTPE2.CLK_COR_MAX_LAT[3] origin:064-gtp-channel-conf 29_558 -GTP_CHANNEL_0.GTPE2.CLK_COR_MAX_LAT[4] origin:064-gtp-channel-conf 28_559 -GTP_CHANNEL_0.GTPE2.CLK_COR_MAX_LAT[5] origin:064-gtp-channel-conf 29_559 -GTP_CHANNEL_0.GTPE2.CLK_COR_MIN_LAT[0] origin:064-gtp-channel-conf 28_565 -GTP_CHANNEL_0.GTPE2.CLK_COR_MIN_LAT[1] origin:064-gtp-channel-conf 29_565 -GTP_CHANNEL_0.GTPE2.CLK_COR_MIN_LAT[2] origin:064-gtp-channel-conf 28_566 -GTP_CHANNEL_0.GTPE2.CLK_COR_MIN_LAT[3] origin:064-gtp-channel-conf 29_566 -GTP_CHANNEL_0.GTPE2.CLK_COR_MIN_LAT[4] origin:064-gtp-channel-conf 28_567 -GTP_CHANNEL_0.GTPE2.CLK_COR_MIN_LAT[5] origin:064-gtp-channel-conf 29_567 -GTP_CHANNEL_0.GTPE2.CLK_COR_PRECEDENCE origin:064-gtp-channel-conf 28_590 -GTP_CHANNEL_0.GTPE2.CLK_COR_REPEAT_WAIT[0] origin:064-gtp-channel-conf 28_573 -GTP_CHANNEL_0.GTPE2.CLK_COR_REPEAT_WAIT[1] origin:064-gtp-channel-conf 29_573 -GTP_CHANNEL_0.GTPE2.CLK_COR_REPEAT_WAIT[2] origin:064-gtp-channel-conf 28_574 -GTP_CHANNEL_0.GTPE2.CLK_COR_REPEAT_WAIT[3] origin:064-gtp-channel-conf 29_574 -GTP_CHANNEL_0.GTPE2.CLK_COR_REPEAT_WAIT[4] origin:064-gtp-channel-conf 28_575 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_1_1[0] origin:064-gtp-channel-conf 28_544 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_1_1[1] origin:064-gtp-channel-conf 29_544 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_1_1[2] origin:064-gtp-channel-conf 28_545 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_1_1[3] origin:064-gtp-channel-conf 29_545 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_1_1[4] origin:064-gtp-channel-conf 28_546 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_1_1[5] origin:064-gtp-channel-conf 29_546 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_1_1[6] origin:064-gtp-channel-conf 28_547 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_1_1[7] origin:064-gtp-channel-conf 29_547 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_1_1[8] origin:064-gtp-channel-conf 28_548 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_1_1[9] origin:064-gtp-channel-conf 29_548 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_1_2[0] origin:064-gtp-channel-conf 28_552 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_1_2[1] origin:064-gtp-channel-conf 29_552 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_1_2[2] origin:064-gtp-channel-conf 28_553 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_1_2[3] origin:064-gtp-channel-conf 29_553 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_1_2[4] origin:064-gtp-channel-conf 28_554 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_1_2[5] origin:064-gtp-channel-conf 29_554 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_1_2[6] origin:064-gtp-channel-conf 28_555 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_1_2[7] origin:064-gtp-channel-conf 29_555 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_1_2[8] origin:064-gtp-channel-conf 28_556 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_1_2[9] origin:064-gtp-channel-conf 29_556 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_1_3[0] origin:064-gtp-channel-conf 28_560 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_1_3[1] origin:064-gtp-channel-conf 29_560 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_1_3[2] origin:064-gtp-channel-conf 28_561 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_1_3[3] origin:064-gtp-channel-conf 29_561 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_1_3[4] origin:064-gtp-channel-conf 28_562 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_1_3[5] origin:064-gtp-channel-conf 29_562 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_1_3[6] origin:064-gtp-channel-conf 28_563 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_1_3[7] origin:064-gtp-channel-conf 29_563 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_1_3[8] origin:064-gtp-channel-conf 28_564 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_1_3[9] origin:064-gtp-channel-conf 29_564 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_1_4[0] origin:064-gtp-channel-conf 28_568 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_1_4[1] origin:064-gtp-channel-conf 29_568 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_1_4[2] origin:064-gtp-channel-conf 28_569 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_1_4[3] origin:064-gtp-channel-conf 29_569 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_1_4[4] origin:064-gtp-channel-conf 28_570 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_1_4[5] origin:064-gtp-channel-conf 29_570 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_1_4[6] origin:064-gtp-channel-conf 28_571 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_1_4[7] origin:064-gtp-channel-conf 29_571 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_1_4[8] origin:064-gtp-channel-conf 28_572 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_1_4[9] origin:064-gtp-channel-conf 29_572 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_1_ENABLE[0] origin:064-gtp-channel-conf 28_549 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_1_ENABLE[1] origin:064-gtp-channel-conf 29_549 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_1_ENABLE[2] origin:064-gtp-channel-conf 28_550 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_1_ENABLE[3] origin:064-gtp-channel-conf 29_550 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_2_1[0] origin:064-gtp-channel-conf 28_576 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_2_1[1] origin:064-gtp-channel-conf 29_576 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_2_1[2] origin:064-gtp-channel-conf 28_577 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_2_1[3] origin:064-gtp-channel-conf 29_577 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_2_1[4] origin:064-gtp-channel-conf 28_578 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_2_1[5] origin:064-gtp-channel-conf 29_578 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_2_1[6] origin:064-gtp-channel-conf 28_579 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_2_1[7] origin:064-gtp-channel-conf 29_579 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_2_1[8] origin:064-gtp-channel-conf 28_580 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_2_1[9] origin:064-gtp-channel-conf 29_580 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_2_2[0] origin:064-gtp-channel-conf 28_584 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_2_2[1] origin:064-gtp-channel-conf 29_584 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_2_2[2] origin:064-gtp-channel-conf 28_585 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_2_2[3] origin:064-gtp-channel-conf 29_585 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_2_2[4] origin:064-gtp-channel-conf 28_586 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_2_2[5] origin:064-gtp-channel-conf 29_586 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_2_2[6] origin:064-gtp-channel-conf 28_587 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_2_2[7] origin:064-gtp-channel-conf 29_587 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_2_2[8] origin:064-gtp-channel-conf 28_588 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_2_2[9] origin:064-gtp-channel-conf 29_588 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_2_3[0] origin:064-gtp-channel-conf 28_592 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_2_3[1] origin:064-gtp-channel-conf 29_592 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_2_3[2] origin:064-gtp-channel-conf 28_593 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_2_3[3] origin:064-gtp-channel-conf 29_593 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_2_3[4] origin:064-gtp-channel-conf 28_594 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_2_3[5] origin:064-gtp-channel-conf 29_594 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_2_3[6] origin:064-gtp-channel-conf 28_595 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_2_3[7] origin:064-gtp-channel-conf 29_595 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_2_3[8] origin:064-gtp-channel-conf 28_596 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_2_3[9] origin:064-gtp-channel-conf 29_596 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_2_4[0] origin:064-gtp-channel-conf 28_600 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_2_4[1] origin:064-gtp-channel-conf 29_600 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_2_4[2] origin:064-gtp-channel-conf 28_601 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_2_4[3] origin:064-gtp-channel-conf 29_601 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_2_4[4] origin:064-gtp-channel-conf 28_602 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_2_4[5] origin:064-gtp-channel-conf 29_602 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_2_4[6] origin:064-gtp-channel-conf 28_603 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_2_4[7] origin:064-gtp-channel-conf 29_603 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_2_4[8] origin:064-gtp-channel-conf 28_604 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_2_4[9] origin:064-gtp-channel-conf 29_604 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_2_ENABLE[0] origin:064-gtp-channel-conf 28_581 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_2_ENABLE[1] origin:064-gtp-channel-conf 29_581 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_2_ENABLE[2] origin:064-gtp-channel-conf 28_582 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_2_ENABLE[3] origin:064-gtp-channel-conf 29_582 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_2_USE origin:064-gtp-channel-conf 28_583 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_LEN[0] origin:064-gtp-channel-conf 28_589 -GTP_CHANNEL_0.GTPE2.CLK_COR_SEQ_LEN[1] origin:064-gtp-channel-conf 29_589 -GTP_CHANNEL_0.GTPE2.CLK_CORRECT_USE origin:064-gtp-channel-conf 28_551 -GTP_CHANNEL_0.GTPE2.DEC_MCOMMA_DETECT origin:064-gtp-channel-conf 29_494 -GTP_CHANNEL_0.GTPE2.DEC_PCOMMA_DETECT origin:064-gtp-channel-conf 28_495 -GTP_CHANNEL_0.GTPE2.DEC_VALID_COMMA_ONLY origin:064-gtp-channel-conf 28_494 -GTP_CHANNEL_0.GTPE2.DMONITOR_CFG[0] origin:064-gtp-channel-conf 30_368 -GTP_CHANNEL_0.GTPE2.DMONITOR_CFG[1] origin:064-gtp-channel-conf 31_368 -GTP_CHANNEL_0.GTPE2.DMONITOR_CFG[2] origin:064-gtp-channel-conf 30_369 -GTP_CHANNEL_0.GTPE2.DMONITOR_CFG[3] origin:064-gtp-channel-conf 31_369 -GTP_CHANNEL_0.GTPE2.DMONITOR_CFG[4] origin:064-gtp-channel-conf 30_370 -GTP_CHANNEL_0.GTPE2.DMONITOR_CFG[5] origin:064-gtp-channel-conf 31_370 -GTP_CHANNEL_0.GTPE2.DMONITOR_CFG[6] origin:064-gtp-channel-conf 30_371 -GTP_CHANNEL_0.GTPE2.DMONITOR_CFG[7] origin:064-gtp-channel-conf 31_371 -GTP_CHANNEL_0.GTPE2.DMONITOR_CFG[8] origin:064-gtp-channel-conf 30_372 -GTP_CHANNEL_0.GTPE2.DMONITOR_CFG[9] origin:064-gtp-channel-conf 31_372 -GTP_CHANNEL_0.GTPE2.DMONITOR_CFG[10] origin:064-gtp-channel-conf 30_373 -GTP_CHANNEL_0.GTPE2.DMONITOR_CFG[11] origin:064-gtp-channel-conf 31_373 -GTP_CHANNEL_0.GTPE2.DMONITOR_CFG[12] origin:064-gtp-channel-conf 30_374 -GTP_CHANNEL_0.GTPE2.DMONITOR_CFG[13] origin:064-gtp-channel-conf 31_374 -GTP_CHANNEL_0.GTPE2.DMONITOR_CFG[14] origin:064-gtp-channel-conf 30_375 -GTP_CHANNEL_0.GTPE2.DMONITOR_CFG[15] origin:064-gtp-channel-conf 31_375 -GTP_CHANNEL_0.GTPE2.DMONITOR_CFG[16] origin:064-gtp-channel-conf 30_376 -GTP_CHANNEL_0.GTPE2.DMONITOR_CFG[17] origin:064-gtp-channel-conf 31_376 -GTP_CHANNEL_0.GTPE2.DMONITOR_CFG[18] origin:064-gtp-channel-conf 30_377 -GTP_CHANNEL_0.GTPE2.DMONITOR_CFG[19] origin:064-gtp-channel-conf 31_377 -GTP_CHANNEL_0.GTPE2.DMONITOR_CFG[20] origin:064-gtp-channel-conf 30_378 -GTP_CHANNEL_0.GTPE2.DMONITOR_CFG[21] origin:064-gtp-channel-conf 31_378 -GTP_CHANNEL_0.GTPE2.DMONITOR_CFG[22] origin:064-gtp-channel-conf 30_379 -GTP_CHANNEL_0.GTPE2.DMONITOR_CFG[23] origin:064-gtp-channel-conf 31_379 -GTP_CHANNEL_0.GTPE2.ES_CLK_PHASE_SEL[0] origin:064-gtp-channel-conf 31_463 -GTP_CHANNEL_0.GTPE2.ES_CONTROL[0] origin:064-gtp-channel-conf 28_488 -GTP_CHANNEL_0.GTPE2.ES_CONTROL[1] origin:064-gtp-channel-conf 29_488 -GTP_CHANNEL_0.GTPE2.ES_CONTROL[2] origin:064-gtp-channel-conf 28_489 -GTP_CHANNEL_0.GTPE2.ES_CONTROL[3] origin:064-gtp-channel-conf 29_489 -GTP_CHANNEL_0.GTPE2.ES_CONTROL[4] origin:064-gtp-channel-conf 28_490 -GTP_CHANNEL_0.GTPE2.ES_CONTROL[5] origin:064-gtp-channel-conf 29_490 -GTP_CHANNEL_0.GTPE2.ES_ERRDET_EN origin:064-gtp-channel-conf 29_492 -GTP_CHANNEL_0.GTPE2.ES_EYE_SCAN_EN origin:064-gtp-channel-conf 28_492 -GTP_CHANNEL_0.GTPE2.ES_HORZ_OFFSET[0] origin:064-gtp-channel-conf 28_480 -GTP_CHANNEL_0.GTPE2.ES_HORZ_OFFSET[1] origin:064-gtp-channel-conf 29_480 -GTP_CHANNEL_0.GTPE2.ES_HORZ_OFFSET[2] origin:064-gtp-channel-conf 28_481 -GTP_CHANNEL_0.GTPE2.ES_HORZ_OFFSET[3] origin:064-gtp-channel-conf 29_481 -GTP_CHANNEL_0.GTPE2.ES_HORZ_OFFSET[4] origin:064-gtp-channel-conf 28_482 -GTP_CHANNEL_0.GTPE2.ES_HORZ_OFFSET[5] origin:064-gtp-channel-conf 29_482 -GTP_CHANNEL_0.GTPE2.ES_HORZ_OFFSET[6] origin:064-gtp-channel-conf 28_483 -GTP_CHANNEL_0.GTPE2.ES_HORZ_OFFSET[7] origin:064-gtp-channel-conf 29_483 -GTP_CHANNEL_0.GTPE2.ES_HORZ_OFFSET[8] origin:064-gtp-channel-conf 28_484 -GTP_CHANNEL_0.GTPE2.ES_HORZ_OFFSET[9] origin:064-gtp-channel-conf 29_484 -GTP_CHANNEL_0.GTPE2.ES_HORZ_OFFSET[10] origin:064-gtp-channel-conf 28_485 -GTP_CHANNEL_0.GTPE2.ES_HORZ_OFFSET[11] origin:064-gtp-channel-conf 29_485 -GTP_CHANNEL_0.GTPE2.ES_PMA_CFG[0] origin:064-gtp-channel-conf 30_624 -GTP_CHANNEL_0.GTPE2.ES_PMA_CFG[1] origin:064-gtp-channel-conf 31_624 -GTP_CHANNEL_0.GTPE2.ES_PMA_CFG[2] origin:064-gtp-channel-conf 30_625 -GTP_CHANNEL_0.GTPE2.ES_PMA_CFG[3] origin:064-gtp-channel-conf 31_625 -GTP_CHANNEL_0.GTPE2.ES_PMA_CFG[4] origin:064-gtp-channel-conf 30_626 -GTP_CHANNEL_0.GTPE2.ES_PMA_CFG[5] origin:064-gtp-channel-conf 31_626 -GTP_CHANNEL_0.GTPE2.ES_PMA_CFG[6] origin:064-gtp-channel-conf 30_627 -GTP_CHANNEL_0.GTPE2.ES_PMA_CFG[7] origin:064-gtp-channel-conf 31_627 -GTP_CHANNEL_0.GTPE2.ES_PMA_CFG[8] origin:064-gtp-channel-conf 30_628 -GTP_CHANNEL_0.GTPE2.ES_PMA_CFG[9] origin:064-gtp-channel-conf 31_628 -GTP_CHANNEL_0.GTPE2.ES_PRESCALE[0] origin:064-gtp-channel-conf 29_477 -GTP_CHANNEL_0.GTPE2.ES_PRESCALE[1] origin:064-gtp-channel-conf 28_478 -GTP_CHANNEL_0.GTPE2.ES_PRESCALE[2] origin:064-gtp-channel-conf 29_478 -GTP_CHANNEL_0.GTPE2.ES_PRESCALE[3] origin:064-gtp-channel-conf 28_479 -GTP_CHANNEL_0.GTPE2.ES_PRESCALE[4] origin:064-gtp-channel-conf 29_479 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[0] origin:064-gtp-channel-conf 28_392 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[1] origin:064-gtp-channel-conf 29_392 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[2] origin:064-gtp-channel-conf 28_393 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[3] origin:064-gtp-channel-conf 29_393 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[4] origin:064-gtp-channel-conf 28_394 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[5] origin:064-gtp-channel-conf 29_394 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[6] origin:064-gtp-channel-conf 28_395 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[7] origin:064-gtp-channel-conf 29_395 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[8] origin:064-gtp-channel-conf 28_396 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[9] origin:064-gtp-channel-conf 29_396 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[10] origin:064-gtp-channel-conf 28_397 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[11] origin:064-gtp-channel-conf 29_397 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[12] origin:064-gtp-channel-conf 28_398 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[13] origin:064-gtp-channel-conf 29_398 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[14] origin:064-gtp-channel-conf 28_399 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[15] origin:064-gtp-channel-conf 29_399 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[16] origin:064-gtp-channel-conf 28_400 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[17] origin:064-gtp-channel-conf 29_400 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[18] origin:064-gtp-channel-conf 28_401 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[19] origin:064-gtp-channel-conf 29_401 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[20] origin:064-gtp-channel-conf 28_402 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[21] origin:064-gtp-channel-conf 29_402 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[22] origin:064-gtp-channel-conf 28_403 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[23] origin:064-gtp-channel-conf 29_403 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[24] origin:064-gtp-channel-conf 28_404 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[25] origin:064-gtp-channel-conf 29_404 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[26] origin:064-gtp-channel-conf 28_405 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[27] origin:064-gtp-channel-conf 29_405 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[28] origin:064-gtp-channel-conf 28_406 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[29] origin:064-gtp-channel-conf 29_406 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[30] origin:064-gtp-channel-conf 28_407 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[31] origin:064-gtp-channel-conf 29_407 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[32] origin:064-gtp-channel-conf 28_408 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[33] origin:064-gtp-channel-conf 29_408 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[34] origin:064-gtp-channel-conf 28_409 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[35] origin:064-gtp-channel-conf 29_409 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[36] origin:064-gtp-channel-conf 28_410 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[37] origin:064-gtp-channel-conf 29_410 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[38] origin:064-gtp-channel-conf 28_411 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[39] origin:064-gtp-channel-conf 29_411 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[40] origin:064-gtp-channel-conf 28_412 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[41] origin:064-gtp-channel-conf 29_412 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[42] origin:064-gtp-channel-conf 28_413 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[43] origin:064-gtp-channel-conf 29_413 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[44] origin:064-gtp-channel-conf 28_414 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[45] origin:064-gtp-channel-conf 29_414 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[46] origin:064-gtp-channel-conf 28_415 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[47] origin:064-gtp-channel-conf 29_415 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[48] origin:064-gtp-channel-conf 28_416 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[49] origin:064-gtp-channel-conf 29_416 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[50] origin:064-gtp-channel-conf 28_417 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[51] origin:064-gtp-channel-conf 29_417 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[52] origin:064-gtp-channel-conf 28_418 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[53] origin:064-gtp-channel-conf 29_418 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[54] origin:064-gtp-channel-conf 28_419 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[55] origin:064-gtp-channel-conf 29_419 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[56] origin:064-gtp-channel-conf 28_420 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[57] origin:064-gtp-channel-conf 29_420 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[58] origin:064-gtp-channel-conf 28_421 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[59] origin:064-gtp-channel-conf 29_421 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[60] origin:064-gtp-channel-conf 28_422 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[61] origin:064-gtp-channel-conf 29_422 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[62] origin:064-gtp-channel-conf 28_423 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[63] origin:064-gtp-channel-conf 29_423 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[64] origin:064-gtp-channel-conf 28_424 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[65] origin:064-gtp-channel-conf 29_424 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[66] origin:064-gtp-channel-conf 28_425 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[67] origin:064-gtp-channel-conf 29_425 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[68] origin:064-gtp-channel-conf 28_426 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[69] origin:064-gtp-channel-conf 29_426 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[70] origin:064-gtp-channel-conf 28_427 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[71] origin:064-gtp-channel-conf 29_427 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[72] origin:064-gtp-channel-conf 28_428 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[73] origin:064-gtp-channel-conf 29_428 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[74] origin:064-gtp-channel-conf 28_429 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[75] origin:064-gtp-channel-conf 29_429 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[76] origin:064-gtp-channel-conf 28_430 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[77] origin:064-gtp-channel-conf 29_430 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[78] origin:064-gtp-channel-conf 28_431 -GTP_CHANNEL_0.GTPE2.ES_QUAL_MASK[79] origin:064-gtp-channel-conf 29_431 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[0] origin:064-gtp-channel-conf 28_352 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[1] origin:064-gtp-channel-conf 29_352 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[2] origin:064-gtp-channel-conf 28_353 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[3] origin:064-gtp-channel-conf 29_353 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[4] origin:064-gtp-channel-conf 28_354 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[5] origin:064-gtp-channel-conf 29_354 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[6] origin:064-gtp-channel-conf 28_355 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[7] origin:064-gtp-channel-conf 29_355 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[8] origin:064-gtp-channel-conf 28_356 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[9] origin:064-gtp-channel-conf 29_356 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[10] origin:064-gtp-channel-conf 28_357 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[11] origin:064-gtp-channel-conf 29_357 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[12] origin:064-gtp-channel-conf 28_358 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[13] origin:064-gtp-channel-conf 29_358 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[14] origin:064-gtp-channel-conf 28_359 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[15] origin:064-gtp-channel-conf 29_359 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[16] origin:064-gtp-channel-conf 28_360 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[17] origin:064-gtp-channel-conf 29_360 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[18] origin:064-gtp-channel-conf 28_361 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[19] origin:064-gtp-channel-conf 29_361 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[20] origin:064-gtp-channel-conf 28_362 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[21] origin:064-gtp-channel-conf 29_362 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[22] origin:064-gtp-channel-conf 28_363 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[23] origin:064-gtp-channel-conf 29_363 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[24] origin:064-gtp-channel-conf 28_364 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[25] origin:064-gtp-channel-conf 29_364 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[26] origin:064-gtp-channel-conf 28_365 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[27] origin:064-gtp-channel-conf 29_365 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[28] origin:064-gtp-channel-conf 28_366 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[29] origin:064-gtp-channel-conf 29_366 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[30] origin:064-gtp-channel-conf 28_367 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[31] origin:064-gtp-channel-conf 29_367 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[32] origin:064-gtp-channel-conf 28_368 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[33] origin:064-gtp-channel-conf 29_368 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[34] origin:064-gtp-channel-conf 28_369 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[35] origin:064-gtp-channel-conf 29_369 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[36] origin:064-gtp-channel-conf 28_370 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[37] origin:064-gtp-channel-conf 29_370 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[38] origin:064-gtp-channel-conf 28_371 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[39] origin:064-gtp-channel-conf 29_371 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[40] origin:064-gtp-channel-conf 28_372 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[41] origin:064-gtp-channel-conf 29_372 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[42] origin:064-gtp-channel-conf 28_373 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[43] origin:064-gtp-channel-conf 29_373 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[44] origin:064-gtp-channel-conf 28_374 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[45] origin:064-gtp-channel-conf 29_374 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[46] origin:064-gtp-channel-conf 28_375 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[47] origin:064-gtp-channel-conf 29_375 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[48] origin:064-gtp-channel-conf 28_376 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[49] origin:064-gtp-channel-conf 29_376 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[50] origin:064-gtp-channel-conf 28_377 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[51] origin:064-gtp-channel-conf 29_377 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[52] origin:064-gtp-channel-conf 28_378 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[53] origin:064-gtp-channel-conf 29_378 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[54] origin:064-gtp-channel-conf 28_379 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[55] origin:064-gtp-channel-conf 29_379 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[56] origin:064-gtp-channel-conf 28_380 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[57] origin:064-gtp-channel-conf 29_380 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[58] origin:064-gtp-channel-conf 28_381 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[59] origin:064-gtp-channel-conf 29_381 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[60] origin:064-gtp-channel-conf 28_382 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[61] origin:064-gtp-channel-conf 29_382 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[62] origin:064-gtp-channel-conf 28_383 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[63] origin:064-gtp-channel-conf 29_383 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[64] origin:064-gtp-channel-conf 28_384 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[65] origin:064-gtp-channel-conf 29_384 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[66] origin:064-gtp-channel-conf 28_385 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[67] origin:064-gtp-channel-conf 29_385 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[68] origin:064-gtp-channel-conf 28_386 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[69] origin:064-gtp-channel-conf 29_386 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[70] origin:064-gtp-channel-conf 28_387 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[71] origin:064-gtp-channel-conf 29_387 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[72] origin:064-gtp-channel-conf 28_388 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[73] origin:064-gtp-channel-conf 29_388 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[74] origin:064-gtp-channel-conf 28_389 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[75] origin:064-gtp-channel-conf 29_389 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[76] origin:064-gtp-channel-conf 28_390 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[77] origin:064-gtp-channel-conf 29_390 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[78] origin:064-gtp-channel-conf 28_391 -GTP_CHANNEL_0.GTPE2.ES_QUALIFIER[79] origin:064-gtp-channel-conf 29_391 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[0] origin:064-gtp-channel-conf 28_432 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[1] origin:064-gtp-channel-conf 29_432 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[2] origin:064-gtp-channel-conf 28_433 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[3] origin:064-gtp-channel-conf 29_433 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[4] origin:064-gtp-channel-conf 28_434 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[5] origin:064-gtp-channel-conf 29_434 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[6] origin:064-gtp-channel-conf 28_435 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[7] origin:064-gtp-channel-conf 29_435 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[8] origin:064-gtp-channel-conf 28_436 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[9] origin:064-gtp-channel-conf 29_436 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[10] origin:064-gtp-channel-conf 28_437 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[11] origin:064-gtp-channel-conf 29_437 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[12] origin:064-gtp-channel-conf 28_438 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[13] origin:064-gtp-channel-conf 29_438 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[14] origin:064-gtp-channel-conf 28_439 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[15] origin:064-gtp-channel-conf 29_439 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[16] origin:064-gtp-channel-conf 28_440 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[17] origin:064-gtp-channel-conf 29_440 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[18] origin:064-gtp-channel-conf 28_441 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[19] origin:064-gtp-channel-conf 29_441 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[20] origin:064-gtp-channel-conf 28_442 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[21] origin:064-gtp-channel-conf 29_442 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[22] origin:064-gtp-channel-conf 28_443 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[23] origin:064-gtp-channel-conf 29_443 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[24] origin:064-gtp-channel-conf 28_444 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[25] origin:064-gtp-channel-conf 29_444 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[26] origin:064-gtp-channel-conf 28_445 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[27] origin:064-gtp-channel-conf 29_445 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[28] origin:064-gtp-channel-conf 28_446 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[29] origin:064-gtp-channel-conf 29_446 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[30] origin:064-gtp-channel-conf 28_447 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[31] origin:064-gtp-channel-conf 29_447 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[32] origin:064-gtp-channel-conf 28_448 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[33] origin:064-gtp-channel-conf 29_448 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[34] origin:064-gtp-channel-conf 28_449 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[35] origin:064-gtp-channel-conf 29_449 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[36] origin:064-gtp-channel-conf 28_450 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[37] origin:064-gtp-channel-conf 29_450 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[38] origin:064-gtp-channel-conf 28_451 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[39] origin:064-gtp-channel-conf 29_451 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[40] origin:064-gtp-channel-conf 28_452 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[41] origin:064-gtp-channel-conf 29_452 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[42] origin:064-gtp-channel-conf 28_453 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[43] origin:064-gtp-channel-conf 29_453 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[44] origin:064-gtp-channel-conf 28_454 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[45] origin:064-gtp-channel-conf 29_454 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[46] origin:064-gtp-channel-conf 28_455 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[47] origin:064-gtp-channel-conf 29_455 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[48] origin:064-gtp-channel-conf 28_456 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[49] origin:064-gtp-channel-conf 29_456 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[50] origin:064-gtp-channel-conf 28_457 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[51] origin:064-gtp-channel-conf 29_457 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[52] origin:064-gtp-channel-conf 28_458 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[53] origin:064-gtp-channel-conf 29_458 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[54] origin:064-gtp-channel-conf 28_459 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[55] origin:064-gtp-channel-conf 29_459 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[56] origin:064-gtp-channel-conf 28_460 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[57] origin:064-gtp-channel-conf 29_460 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[58] origin:064-gtp-channel-conf 28_461 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[59] origin:064-gtp-channel-conf 29_461 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[60] origin:064-gtp-channel-conf 28_462 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[61] origin:064-gtp-channel-conf 29_462 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[62] origin:064-gtp-channel-conf 28_463 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[63] origin:064-gtp-channel-conf 29_463 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[64] origin:064-gtp-channel-conf 28_464 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[65] origin:064-gtp-channel-conf 29_464 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[66] origin:064-gtp-channel-conf 28_465 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[67] origin:064-gtp-channel-conf 29_465 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[68] origin:064-gtp-channel-conf 28_466 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[69] origin:064-gtp-channel-conf 29_466 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[70] origin:064-gtp-channel-conf 28_467 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[71] origin:064-gtp-channel-conf 29_467 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[72] origin:064-gtp-channel-conf 28_468 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[73] origin:064-gtp-channel-conf 29_468 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[74] origin:064-gtp-channel-conf 28_469 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[75] origin:064-gtp-channel-conf 29_469 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[76] origin:064-gtp-channel-conf 28_470 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[77] origin:064-gtp-channel-conf 29_470 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[78] origin:064-gtp-channel-conf 28_471 -GTP_CHANNEL_0.GTPE2.ES_SDATA_MASK[79] origin:064-gtp-channel-conf 29_471 -GTP_CHANNEL_0.GTPE2.ES_VERT_OFFSET[0] origin:064-gtp-channel-conf 28_472 -GTP_CHANNEL_0.GTPE2.ES_VERT_OFFSET[1] origin:064-gtp-channel-conf 29_472 -GTP_CHANNEL_0.GTPE2.ES_VERT_OFFSET[2] origin:064-gtp-channel-conf 28_473 -GTP_CHANNEL_0.GTPE2.ES_VERT_OFFSET[3] origin:064-gtp-channel-conf 29_473 -GTP_CHANNEL_0.GTPE2.ES_VERT_OFFSET[4] origin:064-gtp-channel-conf 28_474 -GTP_CHANNEL_0.GTPE2.ES_VERT_OFFSET[5] origin:064-gtp-channel-conf 29_474 -GTP_CHANNEL_0.GTPE2.ES_VERT_OFFSET[6] origin:064-gtp-channel-conf 28_475 -GTP_CHANNEL_0.GTPE2.ES_VERT_OFFSET[7] origin:064-gtp-channel-conf 29_475 -GTP_CHANNEL_0.GTPE2.ES_VERT_OFFSET[8] origin:064-gtp-channel-conf 28_476 -GTP_CHANNEL_0.GTPE2.FTS_DESKEW_SEQ_ENABLE[0] origin:064-gtp-channel-conf 28_662 -GTP_CHANNEL_0.GTPE2.FTS_DESKEW_SEQ_ENABLE[1] origin:064-gtp-channel-conf 29_662 -GTP_CHANNEL_0.GTPE2.FTS_DESKEW_SEQ_ENABLE[2] origin:064-gtp-channel-conf 28_663 -GTP_CHANNEL_0.GTPE2.FTS_DESKEW_SEQ_ENABLE[3] origin:064-gtp-channel-conf 29_663 -GTP_CHANNEL_0.GTPE2.FTS_LANE_DESKEW_CFG[0] origin:064-gtp-channel-conf 28_654 -GTP_CHANNEL_0.GTPE2.FTS_LANE_DESKEW_CFG[1] origin:064-gtp-channel-conf 29_654 -GTP_CHANNEL_0.GTPE2.FTS_LANE_DESKEW_CFG[2] origin:064-gtp-channel-conf 28_655 -GTP_CHANNEL_0.GTPE2.FTS_LANE_DESKEW_CFG[3] origin:064-gtp-channel-conf 29_655 -GTP_CHANNEL_0.GTPE2.FTS_LANE_DESKEW_EN origin:064-gtp-channel-conf 29_653 -GTP_CHANNEL_0.GTPE2.GEARBOX_MODE[0] origin:064-gtp-channel-conf 28_224 -GTP_CHANNEL_0.GTPE2.GEARBOX_MODE[1] origin:064-gtp-channel-conf 29_224 -GTP_CHANNEL_0.GTPE2.GEARBOX_MODE[2] origin:064-gtp-channel-conf 28_225 -GTP_CHANNEL_0.GTPE2.IN_USE origin:064-gtp-channel-conf 28_00 28_01 28_47 28_52 28_53 28_65 29_01 29_47 30_129 -GTP_CHANNEL_0.GTPE2.LOOPBACK_CFG[0] origin:064-gtp-channel-conf 30_20 -GTP_CHANNEL_0.GTPE2.OUTREFCLK_SEL_INV[0] origin:064-gtp-channel-conf 28_149 -GTP_CHANNEL_0.GTPE2.OUTREFCLK_SEL_INV[1] origin:064-gtp-channel-conf 29_149 -GTP_CHANNEL_0.GTPE2.PCS_PCIE_EN origin:064-gtp-channel-conf 28_216 -GTP_CHANNEL_0.GTPE2.PCS_RSVD_ATTR[0] origin:064-gtp-channel-conf 30_184 -GTP_CHANNEL_0.GTPE2.PCS_RSVD_ATTR[1] origin:064-gtp-channel-conf 31_184 -GTP_CHANNEL_0.GTPE2.PCS_RSVD_ATTR[2] origin:064-gtp-channel-conf 30_185 -GTP_CHANNEL_0.GTPE2.PCS_RSVD_ATTR[3] origin:064-gtp-channel-conf 31_185 -GTP_CHANNEL_0.GTPE2.PCS_RSVD_ATTR[4] origin:064-gtp-channel-conf 30_186 -GTP_CHANNEL_0.GTPE2.PCS_RSVD_ATTR[5] origin:064-gtp-channel-conf 31_186 -GTP_CHANNEL_0.GTPE2.PCS_RSVD_ATTR[6] origin:064-gtp-channel-conf 30_187 -GTP_CHANNEL_0.GTPE2.PCS_RSVD_ATTR[7] origin:064-gtp-channel-conf 31_187 -GTP_CHANNEL_0.GTPE2.PCS_RSVD_ATTR[8] origin:064-gtp-channel-conf 30_188 -GTP_CHANNEL_0.GTPE2.PCS_RSVD_ATTR[9] origin:064-gtp-channel-conf 31_188 -GTP_CHANNEL_0.GTPE2.PCS_RSVD_ATTR[10] origin:064-gtp-channel-conf 30_189 -GTP_CHANNEL_0.GTPE2.PCS_RSVD_ATTR[11] origin:064-gtp-channel-conf 31_189 -GTP_CHANNEL_0.GTPE2.PCS_RSVD_ATTR[12] origin:064-gtp-channel-conf 30_190 -GTP_CHANNEL_0.GTPE2.PCS_RSVD_ATTR[13] origin:064-gtp-channel-conf 31_190 -GTP_CHANNEL_0.GTPE2.PCS_RSVD_ATTR[14] origin:064-gtp-channel-conf 30_191 -GTP_CHANNEL_0.GTPE2.PCS_RSVD_ATTR[15] origin:064-gtp-channel-conf 31_191 -GTP_CHANNEL_0.GTPE2.PCS_RSVD_ATTR[16] origin:064-gtp-channel-conf 30_192 -GTP_CHANNEL_0.GTPE2.PCS_RSVD_ATTR[17] origin:064-gtp-channel-conf 31_192 -GTP_CHANNEL_0.GTPE2.PCS_RSVD_ATTR[18] origin:064-gtp-channel-conf 30_193 -GTP_CHANNEL_0.GTPE2.PCS_RSVD_ATTR[19] origin:064-gtp-channel-conf 31_193 -GTP_CHANNEL_0.GTPE2.PCS_RSVD_ATTR[20] origin:064-gtp-channel-conf 30_194 -GTP_CHANNEL_0.GTPE2.PCS_RSVD_ATTR[21] origin:064-gtp-channel-conf 31_194 -GTP_CHANNEL_0.GTPE2.PCS_RSVD_ATTR[22] origin:064-gtp-channel-conf 30_195 -GTP_CHANNEL_0.GTPE2.PCS_RSVD_ATTR[23] origin:064-gtp-channel-conf 31_195 -GTP_CHANNEL_0.GTPE2.PCS_RSVD_ATTR[24] origin:064-gtp-channel-conf 30_196 -GTP_CHANNEL_0.GTPE2.PCS_RSVD_ATTR[25] origin:064-gtp-channel-conf 31_196 -GTP_CHANNEL_0.GTPE2.PCS_RSVD_ATTR[26] origin:064-gtp-channel-conf 30_197 -GTP_CHANNEL_0.GTPE2.PCS_RSVD_ATTR[27] origin:064-gtp-channel-conf 31_197 -GTP_CHANNEL_0.GTPE2.PCS_RSVD_ATTR[28] origin:064-gtp-channel-conf 30_198 -GTP_CHANNEL_0.GTPE2.PCS_RSVD_ATTR[29] origin:064-gtp-channel-conf 31_198 -GTP_CHANNEL_0.GTPE2.PCS_RSVD_ATTR[30] origin:064-gtp-channel-conf 30_199 -GTP_CHANNEL_0.GTPE2.PCS_RSVD_ATTR[31] origin:064-gtp-channel-conf 31_199 -GTP_CHANNEL_0.GTPE2.PCS_RSVD_ATTR[32] origin:064-gtp-channel-conf 30_200 -GTP_CHANNEL_0.GTPE2.PCS_RSVD_ATTR[33] origin:064-gtp-channel-conf 31_200 -GTP_CHANNEL_0.GTPE2.PCS_RSVD_ATTR[34] origin:064-gtp-channel-conf 30_201 -GTP_CHANNEL_0.GTPE2.PCS_RSVD_ATTR[35] origin:064-gtp-channel-conf 31_201 -GTP_CHANNEL_0.GTPE2.PCS_RSVD_ATTR[36] origin:064-gtp-channel-conf 30_202 -GTP_CHANNEL_0.GTPE2.PCS_RSVD_ATTR[37] origin:064-gtp-channel-conf 31_202 -GTP_CHANNEL_0.GTPE2.PCS_RSVD_ATTR[38] origin:064-gtp-channel-conf 30_203 -GTP_CHANNEL_0.GTPE2.PCS_RSVD_ATTR[39] origin:064-gtp-channel-conf 31_203 -GTP_CHANNEL_0.GTPE2.PCS_RSVD_ATTR[40] origin:064-gtp-channel-conf 30_204 -GTP_CHANNEL_0.GTPE2.PCS_RSVD_ATTR[41] origin:064-gtp-channel-conf 31_204 -GTP_CHANNEL_0.GTPE2.PCS_RSVD_ATTR[42] origin:064-gtp-channel-conf 30_205 -GTP_CHANNEL_0.GTPE2.PCS_RSVD_ATTR[43] origin:064-gtp-channel-conf 31_205 -GTP_CHANNEL_0.GTPE2.PCS_RSVD_ATTR[44] origin:064-gtp-channel-conf 30_206 -GTP_CHANNEL_0.GTPE2.PCS_RSVD_ATTR[45] origin:064-gtp-channel-conf 31_206 -GTP_CHANNEL_0.GTPE2.PCS_RSVD_ATTR[46] origin:064-gtp-channel-conf 30_207 -GTP_CHANNEL_0.GTPE2.PCS_RSVD_ATTR[47] origin:064-gtp-channel-conf 31_207 -GTP_CHANNEL_0.GTPE2.PD_TRANS_TIME_FROM_P2[0] origin:064-gtp-channel-conf 29_216 -GTP_CHANNEL_0.GTPE2.PD_TRANS_TIME_FROM_P2[1] origin:064-gtp-channel-conf 28_217 -GTP_CHANNEL_0.GTPE2.PD_TRANS_TIME_FROM_P2[2] origin:064-gtp-channel-conf 29_217 -GTP_CHANNEL_0.GTPE2.PD_TRANS_TIME_FROM_P2[3] origin:064-gtp-channel-conf 28_218 -GTP_CHANNEL_0.GTPE2.PD_TRANS_TIME_FROM_P2[4] origin:064-gtp-channel-conf 29_218 -GTP_CHANNEL_0.GTPE2.PD_TRANS_TIME_FROM_P2[5] origin:064-gtp-channel-conf 28_219 -GTP_CHANNEL_0.GTPE2.PD_TRANS_TIME_FROM_P2[6] origin:064-gtp-channel-conf 29_219 -GTP_CHANNEL_0.GTPE2.PD_TRANS_TIME_FROM_P2[7] origin:064-gtp-channel-conf 28_220 -GTP_CHANNEL_0.GTPE2.PD_TRANS_TIME_FROM_P2[8] origin:064-gtp-channel-conf 29_220 -GTP_CHANNEL_0.GTPE2.PD_TRANS_TIME_FROM_P2[9] origin:064-gtp-channel-conf 28_221 -GTP_CHANNEL_0.GTPE2.PD_TRANS_TIME_FROM_P2[10] origin:064-gtp-channel-conf 29_221 -GTP_CHANNEL_0.GTPE2.PD_TRANS_TIME_FROM_P2[11] origin:064-gtp-channel-conf 28_222 -GTP_CHANNEL_0.GTPE2.PD_TRANS_TIME_NONE_P2[0] origin:064-gtp-channel-conf 28_208 -GTP_CHANNEL_0.GTPE2.PD_TRANS_TIME_NONE_P2[1] origin:064-gtp-channel-conf 29_208 -GTP_CHANNEL_0.GTPE2.PD_TRANS_TIME_NONE_P2[2] origin:064-gtp-channel-conf 28_209 -GTP_CHANNEL_0.GTPE2.PD_TRANS_TIME_NONE_P2[3] origin:064-gtp-channel-conf 29_209 -GTP_CHANNEL_0.GTPE2.PD_TRANS_TIME_NONE_P2[4] origin:064-gtp-channel-conf 28_210 -GTP_CHANNEL_0.GTPE2.PD_TRANS_TIME_NONE_P2[5] origin:064-gtp-channel-conf 29_210 -GTP_CHANNEL_0.GTPE2.PD_TRANS_TIME_NONE_P2[6] origin:064-gtp-channel-conf 28_211 -GTP_CHANNEL_0.GTPE2.PD_TRANS_TIME_NONE_P2[7] origin:064-gtp-channel-conf 29_211 -GTP_CHANNEL_0.GTPE2.PD_TRANS_TIME_TO_P2[0] origin:064-gtp-channel-conf 28_212 -GTP_CHANNEL_0.GTPE2.PD_TRANS_TIME_TO_P2[1] origin:064-gtp-channel-conf 29_212 -GTP_CHANNEL_0.GTPE2.PD_TRANS_TIME_TO_P2[2] origin:064-gtp-channel-conf 28_213 -GTP_CHANNEL_0.GTPE2.PD_TRANS_TIME_TO_P2[3] origin:064-gtp-channel-conf 29_213 -GTP_CHANNEL_0.GTPE2.PD_TRANS_TIME_TO_P2[4] origin:064-gtp-channel-conf 28_214 -GTP_CHANNEL_0.GTPE2.PD_TRANS_TIME_TO_P2[5] origin:064-gtp-channel-conf 29_214 -GTP_CHANNEL_0.GTPE2.PD_TRANS_TIME_TO_P2[6] origin:064-gtp-channel-conf 28_215 -GTP_CHANNEL_0.GTPE2.PD_TRANS_TIME_TO_P2[7] origin:064-gtp-channel-conf 29_215 -GTP_CHANNEL_0.GTPE2.PMA_LOOPBACK_CFG[0] origin:064-gtp-channel-conf 29_207 -GTP_CHANNEL_0.GTPE2.PMA_RSV[0] origin:064-gtp-channel-conf 30_520 -GTP_CHANNEL_0.GTPE2.PMA_RSV[1] origin:064-gtp-channel-conf 31_520 -GTP_CHANNEL_0.GTPE2.PMA_RSV[2] origin:064-gtp-channel-conf 30_521 -GTP_CHANNEL_0.GTPE2.PMA_RSV[3] origin:064-gtp-channel-conf 31_521 -GTP_CHANNEL_0.GTPE2.PMA_RSV[4] origin:064-gtp-channel-conf 30_522 -GTP_CHANNEL_0.GTPE2.PMA_RSV[5] origin:064-gtp-channel-conf 31_522 -GTP_CHANNEL_0.GTPE2.PMA_RSV[6] origin:064-gtp-channel-conf 30_523 -GTP_CHANNEL_0.GTPE2.PMA_RSV[7] origin:064-gtp-channel-conf 31_523 -GTP_CHANNEL_0.GTPE2.PMA_RSV[8] origin:064-gtp-channel-conf 30_524 -GTP_CHANNEL_0.GTPE2.PMA_RSV[9] origin:064-gtp-channel-conf 31_524 -GTP_CHANNEL_0.GTPE2.PMA_RSV[10] origin:064-gtp-channel-conf 30_525 -GTP_CHANNEL_0.GTPE2.PMA_RSV[11] origin:064-gtp-channel-conf 31_525 -GTP_CHANNEL_0.GTPE2.PMA_RSV[12] origin:064-gtp-channel-conf 30_526 -GTP_CHANNEL_0.GTPE2.PMA_RSV[13] origin:064-gtp-channel-conf 31_526 -GTP_CHANNEL_0.GTPE2.PMA_RSV[14] origin:064-gtp-channel-conf 30_527 -GTP_CHANNEL_0.GTPE2.PMA_RSV[15] origin:064-gtp-channel-conf 31_527 -GTP_CHANNEL_0.GTPE2.PMA_RSV[16] origin:064-gtp-channel-conf 30_528 -GTP_CHANNEL_0.GTPE2.PMA_RSV[17] origin:064-gtp-channel-conf 31_528 -GTP_CHANNEL_0.GTPE2.PMA_RSV[18] origin:064-gtp-channel-conf 30_529 -GTP_CHANNEL_0.GTPE2.PMA_RSV[19] origin:064-gtp-channel-conf 31_529 -GTP_CHANNEL_0.GTPE2.PMA_RSV[20] origin:064-gtp-channel-conf 30_530 -GTP_CHANNEL_0.GTPE2.PMA_RSV[21] origin:064-gtp-channel-conf 31_530 -GTP_CHANNEL_0.GTPE2.PMA_RSV[22] origin:064-gtp-channel-conf 30_531 -GTP_CHANNEL_0.GTPE2.PMA_RSV[23] origin:064-gtp-channel-conf 31_531 -GTP_CHANNEL_0.GTPE2.PMA_RSV[24] origin:064-gtp-channel-conf 30_532 -GTP_CHANNEL_0.GTPE2.PMA_RSV[25] origin:064-gtp-channel-conf 31_532 -GTP_CHANNEL_0.GTPE2.PMA_RSV[26] origin:064-gtp-channel-conf 30_533 -GTP_CHANNEL_0.GTPE2.PMA_RSV[27] origin:064-gtp-channel-conf 31_533 -GTP_CHANNEL_0.GTPE2.PMA_RSV[28] origin:064-gtp-channel-conf 30_534 -GTP_CHANNEL_0.GTPE2.PMA_RSV[29] origin:064-gtp-channel-conf 31_534 -GTP_CHANNEL_0.GTPE2.PMA_RSV[30] origin:064-gtp-channel-conf 30_535 -GTP_CHANNEL_0.GTPE2.PMA_RSV[31] origin:064-gtp-channel-conf 31_535 -GTP_CHANNEL_0.GTPE2.PMA_RSV2[0] origin:064-gtp-channel-conf 30_336 -GTP_CHANNEL_0.GTPE2.PMA_RSV2[1] origin:064-gtp-channel-conf 31_336 -GTP_CHANNEL_0.GTPE2.PMA_RSV2[2] origin:064-gtp-channel-conf 30_337 -GTP_CHANNEL_0.GTPE2.PMA_RSV2[3] origin:064-gtp-channel-conf 31_337 -GTP_CHANNEL_0.GTPE2.PMA_RSV2[4] origin:064-gtp-channel-conf 30_338 -GTP_CHANNEL_0.GTPE2.PMA_RSV2[5] origin:064-gtp-channel-conf 31_338 -GTP_CHANNEL_0.GTPE2.PMA_RSV2[6] origin:064-gtp-channel-conf 30_339 -GTP_CHANNEL_0.GTPE2.PMA_RSV2[7] origin:064-gtp-channel-conf 31_339 -GTP_CHANNEL_0.GTPE2.PMA_RSV2[8] origin:064-gtp-channel-conf 30_340 -GTP_CHANNEL_0.GTPE2.PMA_RSV2[9] origin:064-gtp-channel-conf 31_340 -GTP_CHANNEL_0.GTPE2.PMA_RSV2[10] origin:064-gtp-channel-conf 30_341 -GTP_CHANNEL_0.GTPE2.PMA_RSV2[11] origin:064-gtp-channel-conf 31_341 -GTP_CHANNEL_0.GTPE2.PMA_RSV2[12] origin:064-gtp-channel-conf 30_342 -GTP_CHANNEL_0.GTPE2.PMA_RSV2[13] origin:064-gtp-channel-conf 31_342 -GTP_CHANNEL_0.GTPE2.PMA_RSV2[14] origin:064-gtp-channel-conf 30_343 -GTP_CHANNEL_0.GTPE2.PMA_RSV2[15] origin:064-gtp-channel-conf 31_343 -GTP_CHANNEL_0.GTPE2.PMA_RSV2[16] origin:064-gtp-channel-conf 30_344 -GTP_CHANNEL_0.GTPE2.PMA_RSV2[17] origin:064-gtp-channel-conf 31_344 -GTP_CHANNEL_0.GTPE2.PMA_RSV2[18] origin:064-gtp-channel-conf 30_345 -GTP_CHANNEL_0.GTPE2.PMA_RSV2[19] origin:064-gtp-channel-conf 31_345 -GTP_CHANNEL_0.GTPE2.PMA_RSV2[20] origin:064-gtp-channel-conf 30_346 -GTP_CHANNEL_0.GTPE2.PMA_RSV2[21] origin:064-gtp-channel-conf 31_346 -GTP_CHANNEL_0.GTPE2.PMA_RSV2[22] origin:064-gtp-channel-conf 30_347 -GTP_CHANNEL_0.GTPE2.PMA_RSV2[23] origin:064-gtp-channel-conf 31_347 -GTP_CHANNEL_0.GTPE2.PMA_RSV2[24] origin:064-gtp-channel-conf 30_348 -GTP_CHANNEL_0.GTPE2.PMA_RSV2[25] origin:064-gtp-channel-conf 31_348 -GTP_CHANNEL_0.GTPE2.PMA_RSV2[26] origin:064-gtp-channel-conf 30_349 -GTP_CHANNEL_0.GTPE2.PMA_RSV2[27] origin:064-gtp-channel-conf 31_349 -GTP_CHANNEL_0.GTPE2.PMA_RSV2[28] origin:064-gtp-channel-conf 30_350 -GTP_CHANNEL_0.GTPE2.PMA_RSV2[29] origin:064-gtp-channel-conf 31_350 -GTP_CHANNEL_0.GTPE2.PMA_RSV2[30] origin:064-gtp-channel-conf 30_351 -GTP_CHANNEL_0.GTPE2.PMA_RSV2[31] origin:064-gtp-channel-conf 31_351 -GTP_CHANNEL_0.GTPE2.PMA_RSV3[0] origin:064-gtp-channel-conf 30_288 -GTP_CHANNEL_0.GTPE2.PMA_RSV3[1] origin:064-gtp-channel-conf 31_288 -GTP_CHANNEL_0.GTPE2.PMA_RSV4[0] origin:064-gtp-channel-conf 30_156 -GTP_CHANNEL_0.GTPE2.PMA_RSV4[1] origin:064-gtp-channel-conf 31_156 -GTP_CHANNEL_0.GTPE2.PMA_RSV4[2] origin:064-gtp-channel-conf 30_157 -GTP_CHANNEL_0.GTPE2.PMA_RSV4[3] origin:064-gtp-channel-conf 31_157 -GTP_CHANNEL_0.GTPE2.PMA_RSV5[0] origin:064-gtp-channel-conf 31_159 -GTP_CHANNEL_0.GTPE2.PMA_RSV6[0] origin:064-gtp-channel-conf 30_303 -GTP_CHANNEL_0.GTPE2.PMA_RSV7[0] origin:064-gtp-channel-conf 31_303 -GTP_CHANNEL_0.GTPE2.RX_BIAS_CFG[0] origin:064-gtp-channel-conf 30_112 -GTP_CHANNEL_0.GTPE2.RX_BIAS_CFG[1] origin:064-gtp-channel-conf 31_112 -GTP_CHANNEL_0.GTPE2.RX_BIAS_CFG[2] origin:064-gtp-channel-conf 30_113 -GTP_CHANNEL_0.GTPE2.RX_BIAS_CFG[3] origin:064-gtp-channel-conf 31_113 -GTP_CHANNEL_0.GTPE2.RX_BIAS_CFG[4] origin:064-gtp-channel-conf 30_114 -GTP_CHANNEL_0.GTPE2.RX_BIAS_CFG[5] origin:064-gtp-channel-conf 31_114 -GTP_CHANNEL_0.GTPE2.RX_BIAS_CFG[6] origin:064-gtp-channel-conf 30_115 -GTP_CHANNEL_0.GTPE2.RX_BIAS_CFG[7] origin:064-gtp-channel-conf 31_115 -GTP_CHANNEL_0.GTPE2.RX_BIAS_CFG[8] origin:064-gtp-channel-conf 30_116 -GTP_CHANNEL_0.GTPE2.RX_BIAS_CFG[9] origin:064-gtp-channel-conf 31_116 -GTP_CHANNEL_0.GTPE2.RX_BIAS_CFG[10] origin:064-gtp-channel-conf 30_117 -GTP_CHANNEL_0.GTPE2.RX_BIAS_CFG[11] origin:064-gtp-channel-conf 31_117 -GTP_CHANNEL_0.GTPE2.RX_BIAS_CFG[12] origin:064-gtp-channel-conf 30_118 -GTP_CHANNEL_0.GTPE2.RX_BIAS_CFG[13] origin:064-gtp-channel-conf 31_118 -GTP_CHANNEL_0.GTPE2.RX_BIAS_CFG[14] origin:064-gtp-channel-conf 30_119 -GTP_CHANNEL_0.GTPE2.RX_BIAS_CFG[15] origin:064-gtp-channel-conf 31_119 -GTP_CHANNEL_0.GTPE2.RX_BUFFER_CFG[0] origin:064-gtp-channel-conf 30_536 -GTP_CHANNEL_0.GTPE2.RX_BUFFER_CFG[1] origin:064-gtp-channel-conf 31_536 -GTP_CHANNEL_0.GTPE2.RX_BUFFER_CFG[2] origin:064-gtp-channel-conf 30_537 -GTP_CHANNEL_0.GTPE2.RX_BUFFER_CFG[3] origin:064-gtp-channel-conf 31_537 -GTP_CHANNEL_0.GTPE2.RX_BUFFER_CFG[4] origin:064-gtp-channel-conf 30_538 -GTP_CHANNEL_0.GTPE2.RX_BUFFER_CFG[5] origin:064-gtp-channel-conf 31_538 -GTP_CHANNEL_0.GTPE2.RX_CLKMUX_EN[0] origin:064-gtp-channel-conf 30_128 -GTP_CHANNEL_0.GTPE2.RX_CM_SEL[0] origin:064-gtp-channel-conf 28_138 -GTP_CHANNEL_0.GTPE2.RX_CM_SEL[1] origin:064-gtp-channel-conf 29_138 -GTP_CHANNEL_0.GTPE2.RX_CM_TRIM[0] origin:064-gtp-channel-conf 30_304 -GTP_CHANNEL_0.GTPE2.RX_CM_TRIM[1] origin:064-gtp-channel-conf 31_304 -GTP_CHANNEL_0.GTPE2.RX_CM_TRIM[2] origin:064-gtp-channel-conf 30_305 -GTP_CHANNEL_0.GTPE2.RX_CM_TRIM[3] origin:064-gtp-channel-conf 31_305 -GTP_CHANNEL_0.GTPE2.RX_DATA_WIDTH[0] origin:064-gtp-channel-conf 29_141 -GTP_CHANNEL_0.GTPE2.RX_DATA_WIDTH[1] origin:064-gtp-channel-conf 28_142 -GTP_CHANNEL_0.GTPE2.RX_DATA_WIDTH[2] origin:064-gtp-channel-conf 29_142 -GTP_CHANNEL_0.GTPE2.RX_DDI_SEL[0] origin:064-gtp-channel-conf 28_696 -GTP_CHANNEL_0.GTPE2.RX_DDI_SEL[1] origin:064-gtp-channel-conf 29_696 -GTP_CHANNEL_0.GTPE2.RX_DDI_SEL[2] origin:064-gtp-channel-conf 28_697 -GTP_CHANNEL_0.GTPE2.RX_DDI_SEL[3] origin:064-gtp-channel-conf 29_697 -GTP_CHANNEL_0.GTPE2.RX_DDI_SEL[4] origin:064-gtp-channel-conf 28_698 -GTP_CHANNEL_0.GTPE2.RX_DDI_SEL[5] origin:064-gtp-channel-conf 29_698 -GTP_CHANNEL_0.GTPE2.RX_DEBUG_CFG[0] origin:064-gtp-channel-conf 30_616 -GTP_CHANNEL_0.GTPE2.RX_DEBUG_CFG[1] origin:064-gtp-channel-conf 31_616 -GTP_CHANNEL_0.GTPE2.RX_DEBUG_CFG[2] origin:064-gtp-channel-conf 30_617 -GTP_CHANNEL_0.GTPE2.RX_DEBUG_CFG[3] origin:064-gtp-channel-conf 31_617 -GTP_CHANNEL_0.GTPE2.RX_DEBUG_CFG[4] origin:064-gtp-channel-conf 30_618 -GTP_CHANNEL_0.GTPE2.RX_DEBUG_CFG[5] origin:064-gtp-channel-conf 31_618 -GTP_CHANNEL_0.GTPE2.RX_DEBUG_CFG[6] origin:064-gtp-channel-conf 30_619 -GTP_CHANNEL_0.GTPE2.RX_DEBUG_CFG[7] origin:064-gtp-channel-conf 31_619 -GTP_CHANNEL_0.GTPE2.RX_DEBUG_CFG[8] origin:064-gtp-channel-conf 30_620 -GTP_CHANNEL_0.GTPE2.RX_DEBUG_CFG[9] origin:064-gtp-channel-conf 31_620 -GTP_CHANNEL_0.GTPE2.RX_DEBUG_CFG[10] origin:064-gtp-channel-conf 30_621 -GTP_CHANNEL_0.GTPE2.RX_DEBUG_CFG[11] origin:064-gtp-channel-conf 31_621 -GTP_CHANNEL_0.GTPE2.RX_DEBUG_CFG[12] origin:064-gtp-channel-conf 30_622 -GTP_CHANNEL_0.GTPE2.RX_DEBUG_CFG[13] origin:064-gtp-channel-conf 31_622 -GTP_CHANNEL_0.GTPE2.RX_DEFER_RESET_BUF_EN origin:064-gtp-channel-conf 30_552 -GTP_CHANNEL_0.GTPE2.RX_DISPERR_SEQ_MATCH origin:064-gtp-channel-conf 29_495 -GTP_CHANNEL_0.GTPE2.RX_OS_CFG[0] origin:064-gtp-channel-conf 28_288 -GTP_CHANNEL_0.GTPE2.RX_OS_CFG[1] origin:064-gtp-channel-conf 29_288 -GTP_CHANNEL_0.GTPE2.RX_OS_CFG[2] origin:064-gtp-channel-conf 28_289 -GTP_CHANNEL_0.GTPE2.RX_OS_CFG[3] origin:064-gtp-channel-conf 29_289 -GTP_CHANNEL_0.GTPE2.RX_OS_CFG[4] origin:064-gtp-channel-conf 28_290 -GTP_CHANNEL_0.GTPE2.RX_OS_CFG[5] origin:064-gtp-channel-conf 29_290 -GTP_CHANNEL_0.GTPE2.RX_OS_CFG[6] origin:064-gtp-channel-conf 28_291 -GTP_CHANNEL_0.GTPE2.RX_OS_CFG[7] origin:064-gtp-channel-conf 29_291 -GTP_CHANNEL_0.GTPE2.RX_OS_CFG[8] origin:064-gtp-channel-conf 28_292 -GTP_CHANNEL_0.GTPE2.RX_OS_CFG[9] origin:064-gtp-channel-conf 29_292 -GTP_CHANNEL_0.GTPE2.RX_OS_CFG[10] origin:064-gtp-channel-conf 28_293 -GTP_CHANNEL_0.GTPE2.RX_OS_CFG[11] origin:064-gtp-channel-conf 29_293 -GTP_CHANNEL_0.GTPE2.RX_OS_CFG[12] origin:064-gtp-channel-conf 28_294 -GTP_CHANNEL_0.GTPE2.RX_SIG_VALID_DLY[0] origin:064-gtp-channel-conf 28_524 -GTP_CHANNEL_0.GTPE2.RX_SIG_VALID_DLY[1] origin:064-gtp-channel-conf 29_524 -GTP_CHANNEL_0.GTPE2.RX_SIG_VALID_DLY[2] origin:064-gtp-channel-conf 28_525 -GTP_CHANNEL_0.GTPE2.RX_SIG_VALID_DLY[3] origin:064-gtp-channel-conf 29_525 -GTP_CHANNEL_0.GTPE2.RX_SIG_VALID_DLY[4] origin:064-gtp-channel-conf 28_526 -GTP_CHANNEL_0.GTPE2.RX_XCLK_SEL.RXUSR origin:064-gtp-channel-conf 28_143 -GTP_CHANNEL_0.GTPE2.RX_CLK25_DIV[0] origin:064-gtp-channel-conf 28_139 -GTP_CHANNEL_0.GTPE2.RX_CLK25_DIV[1] origin:064-gtp-channel-conf 29_139 -GTP_CHANNEL_0.GTPE2.RX_CLK25_DIV[2] origin:064-gtp-channel-conf 28_140 -GTP_CHANNEL_0.GTPE2.RX_CLK25_DIV[3] origin:064-gtp-channel-conf 29_140 -GTP_CHANNEL_0.GTPE2.RX_CLK25_DIV[4] origin:064-gtp-channel-conf 28_141 -GTP_CHANNEL_0.GTPE2.RXBUF_ADDR_MODE.FAST origin:064-gtp-channel-conf 31_555 -GTP_CHANNEL_0.GTPE2.RXBUF_EIDLE_HI_CNT[0] origin:064-gtp-channel-conf 30_558 -GTP_CHANNEL_0.GTPE2.RXBUF_EIDLE_HI_CNT[1] origin:064-gtp-channel-conf 31_558 -GTP_CHANNEL_0.GTPE2.RXBUF_EIDLE_HI_CNT[2] origin:064-gtp-channel-conf 30_559 -GTP_CHANNEL_0.GTPE2.RXBUF_EIDLE_HI_CNT[3] origin:064-gtp-channel-conf 31_559 -GTP_CHANNEL_0.GTPE2.RXBUF_EIDLE_LO_CNT[0] origin:064-gtp-channel-conf 30_556 -GTP_CHANNEL_0.GTPE2.RXBUF_EIDLE_LO_CNT[1] origin:064-gtp-channel-conf 31_556 -GTP_CHANNEL_0.GTPE2.RXBUF_EIDLE_LO_CNT[2] origin:064-gtp-channel-conf 30_557 -GTP_CHANNEL_0.GTPE2.RXBUF_EIDLE_LO_CNT[3] origin:064-gtp-channel-conf 31_557 -GTP_CHANNEL_0.GTPE2.RXBUF_EN origin:064-gtp-channel-conf 30_11 -GTP_CHANNEL_0.GTPE2.RXBUF_RESET_ON_CB_CHANGE origin:064-gtp-channel-conf 30_560 -GTP_CHANNEL_0.GTPE2.RXBUF_RESET_ON_COMMAALIGN origin:064-gtp-channel-conf 30_561 -GTP_CHANNEL_0.GTPE2.RXBUF_RESET_ON_EIDLE origin:064-gtp-channel-conf 30_547 -GTP_CHANNEL_0.GTPE2.RXBUF_RESET_ON_RATE_CHANGE origin:064-gtp-channel-conf 31_560 -GTP_CHANNEL_0.GTPE2.RXBUF_THRESH_OVFLW[0] origin:064-gtp-channel-conf 31_552 -GTP_CHANNEL_0.GTPE2.RXBUF_THRESH_OVFLW[1] origin:064-gtp-channel-conf 30_553 -GTP_CHANNEL_0.GTPE2.RXBUF_THRESH_OVFLW[2] origin:064-gtp-channel-conf 31_553 -GTP_CHANNEL_0.GTPE2.RXBUF_THRESH_OVFLW[3] origin:064-gtp-channel-conf 30_554 -GTP_CHANNEL_0.GTPE2.RXBUF_THRESH_OVFLW[4] origin:064-gtp-channel-conf 31_554 -GTP_CHANNEL_0.GTPE2.RXBUF_THRESH_OVFLW[5] origin:064-gtp-channel-conf 30_555 -GTP_CHANNEL_0.GTPE2.RXBUF_THRESH_OVRD origin:064-gtp-channel-conf 30_548 -GTP_CHANNEL_0.GTPE2.RXBUF_THRESH_UNDFLW[0] origin:064-gtp-channel-conf 30_544 -GTP_CHANNEL_0.GTPE2.RXBUF_THRESH_UNDFLW[1] origin:064-gtp-channel-conf 31_544 -GTP_CHANNEL_0.GTPE2.RXBUF_THRESH_UNDFLW[2] origin:064-gtp-channel-conf 30_545 -GTP_CHANNEL_0.GTPE2.RXBUF_THRESH_UNDFLW[3] origin:064-gtp-channel-conf 31_545 -GTP_CHANNEL_0.GTPE2.RXBUF_THRESH_UNDFLW[4] origin:064-gtp-channel-conf 30_546 -GTP_CHANNEL_0.GTPE2.RXBUF_THRESH_UNDFLW[5] origin:064-gtp-channel-conf 31_546 -GTP_CHANNEL_0.GTPE2.RXBUFRESET_TIME[0] origin:064-gtp-channel-conf 29_101 -GTP_CHANNEL_0.GTPE2.RXBUFRESET_TIME[1] origin:064-gtp-channel-conf 28_102 -GTP_CHANNEL_0.GTPE2.RXBUFRESET_TIME[2] origin:064-gtp-channel-conf 29_102 -GTP_CHANNEL_0.GTPE2.RXBUFRESET_TIME[3] origin:064-gtp-channel-conf 28_103 -GTP_CHANNEL_0.GTPE2.RXBUFRESET_TIME[4] origin:064-gtp-channel-conf 29_103 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[0] origin:064-gtp-channel-conf 30_640 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[1] origin:064-gtp-channel-conf 31_640 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[2] origin:064-gtp-channel-conf 30_641 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[3] origin:064-gtp-channel-conf 31_641 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[4] origin:064-gtp-channel-conf 30_642 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[5] origin:064-gtp-channel-conf 31_642 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[6] origin:064-gtp-channel-conf 30_643 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[7] origin:064-gtp-channel-conf 31_643 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[8] origin:064-gtp-channel-conf 30_644 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[9] origin:064-gtp-channel-conf 31_644 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[10] origin:064-gtp-channel-conf 30_645 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[11] origin:064-gtp-channel-conf 31_645 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[12] origin:064-gtp-channel-conf 30_646 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[13] origin:064-gtp-channel-conf 31_646 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[14] origin:064-gtp-channel-conf 30_647 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[15] origin:064-gtp-channel-conf 31_647 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[16] origin:064-gtp-channel-conf 30_648 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[17] origin:064-gtp-channel-conf 31_648 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[18] origin:064-gtp-channel-conf 30_649 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[19] origin:064-gtp-channel-conf 31_649 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[20] origin:064-gtp-channel-conf 30_650 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[21] origin:064-gtp-channel-conf 31_650 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[22] origin:064-gtp-channel-conf 30_651 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[23] origin:064-gtp-channel-conf 31_651 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[24] origin:064-gtp-channel-conf 30_652 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[25] origin:064-gtp-channel-conf 31_652 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[26] origin:064-gtp-channel-conf 30_653 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[27] origin:064-gtp-channel-conf 31_653 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[28] origin:064-gtp-channel-conf 30_654 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[29] origin:064-gtp-channel-conf 31_654 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[30] origin:064-gtp-channel-conf 30_655 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[31] origin:064-gtp-channel-conf 31_655 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[32] origin:064-gtp-channel-conf 30_656 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[33] origin:064-gtp-channel-conf 31_656 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[34] origin:064-gtp-channel-conf 30_657 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[35] origin:064-gtp-channel-conf 31_657 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[36] origin:064-gtp-channel-conf 30_658 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[37] origin:064-gtp-channel-conf 31_658 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[38] origin:064-gtp-channel-conf 30_659 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[39] origin:064-gtp-channel-conf 31_659 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[40] origin:064-gtp-channel-conf 30_660 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[41] origin:064-gtp-channel-conf 31_660 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[42] origin:064-gtp-channel-conf 30_661 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[43] origin:064-gtp-channel-conf 31_661 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[44] origin:064-gtp-channel-conf 30_662 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[45] origin:064-gtp-channel-conf 31_662 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[46] origin:064-gtp-channel-conf 30_663 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[47] origin:064-gtp-channel-conf 31_663 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[48] origin:064-gtp-channel-conf 30_664 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[49] origin:064-gtp-channel-conf 31_664 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[50] origin:064-gtp-channel-conf 30_665 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[51] origin:064-gtp-channel-conf 31_665 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[52] origin:064-gtp-channel-conf 30_666 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[53] origin:064-gtp-channel-conf 31_666 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[54] origin:064-gtp-channel-conf 30_667 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[55] origin:064-gtp-channel-conf 31_667 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[56] origin:064-gtp-channel-conf 30_668 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[57] origin:064-gtp-channel-conf 31_668 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[58] origin:064-gtp-channel-conf 30_669 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[59] origin:064-gtp-channel-conf 31_669 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[60] origin:064-gtp-channel-conf 30_670 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[61] origin:064-gtp-channel-conf 31_670 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[62] origin:064-gtp-channel-conf 30_671 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[63] origin:064-gtp-channel-conf 31_671 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[64] origin:064-gtp-channel-conf 30_672 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[65] origin:064-gtp-channel-conf 31_672 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[66] origin:064-gtp-channel-conf 30_673 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[67] origin:064-gtp-channel-conf 31_673 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[68] origin:064-gtp-channel-conf 30_674 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[69] origin:064-gtp-channel-conf 31_674 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[70] origin:064-gtp-channel-conf 30_675 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[71] origin:064-gtp-channel-conf 31_675 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[72] origin:064-gtp-channel-conf 30_676 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[73] origin:064-gtp-channel-conf 31_676 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[74] origin:064-gtp-channel-conf 30_677 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[75] origin:064-gtp-channel-conf 31_677 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[76] origin:064-gtp-channel-conf 30_678 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[77] origin:064-gtp-channel-conf 31_678 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[78] origin:064-gtp-channel-conf 30_679 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[79] origin:064-gtp-channel-conf 31_679 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[80] origin:064-gtp-channel-conf 30_680 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[81] origin:064-gtp-channel-conf 31_680 -GTP_CHANNEL_0.GTPE2.RXCDR_CFG[82] origin:064-gtp-channel-conf 30_681 -GTP_CHANNEL_0.GTPE2.RXCDR_FR_RESET_ON_EIDLE[0] origin:064-gtp-channel-conf 30_638 -GTP_CHANNEL_0.GTPE2.RXCDR_HOLD_DURING_EIDLE[0] origin:064-gtp-channel-conf 31_637 -GTP_CHANNEL_0.GTPE2.RXCDR_LOCK_CFG[0] origin:064-gtp-channel-conf 30_632 -GTP_CHANNEL_0.GTPE2.RXCDR_LOCK_CFG[1] origin:064-gtp-channel-conf 31_632 -GTP_CHANNEL_0.GTPE2.RXCDR_LOCK_CFG[2] origin:064-gtp-channel-conf 30_633 -GTP_CHANNEL_0.GTPE2.RXCDR_LOCK_CFG[3] origin:064-gtp-channel-conf 31_633 -GTP_CHANNEL_0.GTPE2.RXCDR_LOCK_CFG[4] origin:064-gtp-channel-conf 30_634 -GTP_CHANNEL_0.GTPE2.RXCDR_LOCK_CFG[5] origin:064-gtp-channel-conf 31_634 -GTP_CHANNEL_0.GTPE2.RXCDR_PH_RESET_ON_EIDLE[0] origin:064-gtp-channel-conf 31_638 -GTP_CHANNEL_0.GTPE2.RXCDRFREQRESET_TIME[0] origin:064-gtp-channel-conf 29_106 -GTP_CHANNEL_0.GTPE2.RXCDRFREQRESET_TIME[1] origin:064-gtp-channel-conf 28_107 -GTP_CHANNEL_0.GTPE2.RXCDRFREQRESET_TIME[2] origin:064-gtp-channel-conf 29_107 -GTP_CHANNEL_0.GTPE2.RXCDRFREQRESET_TIME[3] origin:064-gtp-channel-conf 28_108 -GTP_CHANNEL_0.GTPE2.RXCDRFREQRESET_TIME[4] origin:064-gtp-channel-conf 29_108 -GTP_CHANNEL_0.GTPE2.RXCDRPHRESET_TIME[0] origin:064-gtp-channel-conf 28_109 -GTP_CHANNEL_0.GTPE2.RXCDRPHRESET_TIME[1] origin:064-gtp-channel-conf 29_109 -GTP_CHANNEL_0.GTPE2.RXCDRPHRESET_TIME[2] origin:064-gtp-channel-conf 28_110 -GTP_CHANNEL_0.GTPE2.RXCDRPHRESET_TIME[3] origin:064-gtp-channel-conf 29_110 -GTP_CHANNEL_0.GTPE2.RXCDRPHRESET_TIME[4] origin:064-gtp-channel-conf 28_111 -GTP_CHANNEL_0.GTPE2.RXDLY_CFG[0] origin:064-gtp-channel-conf 28_680 -GTP_CHANNEL_0.GTPE2.RXDLY_CFG[1] origin:064-gtp-channel-conf 29_680 -GTP_CHANNEL_0.GTPE2.RXDLY_CFG[2] origin:064-gtp-channel-conf 28_681 -GTP_CHANNEL_0.GTPE2.RXDLY_CFG[3] origin:064-gtp-channel-conf 29_681 -GTP_CHANNEL_0.GTPE2.RXDLY_CFG[4] origin:064-gtp-channel-conf 28_682 -GTP_CHANNEL_0.GTPE2.RXDLY_CFG[5] origin:064-gtp-channel-conf 29_682 -GTP_CHANNEL_0.GTPE2.RXDLY_CFG[6] origin:064-gtp-channel-conf 28_683 -GTP_CHANNEL_0.GTPE2.RXDLY_CFG[7] origin:064-gtp-channel-conf 29_683 -GTP_CHANNEL_0.GTPE2.RXDLY_CFG[8] origin:064-gtp-channel-conf 28_684 -GTP_CHANNEL_0.GTPE2.RXDLY_CFG[9] origin:064-gtp-channel-conf 29_684 -GTP_CHANNEL_0.GTPE2.RXDLY_CFG[10] origin:064-gtp-channel-conf 28_685 -GTP_CHANNEL_0.GTPE2.RXDLY_CFG[11] origin:064-gtp-channel-conf 29_685 -GTP_CHANNEL_0.GTPE2.RXDLY_CFG[12] origin:064-gtp-channel-conf 28_686 -GTP_CHANNEL_0.GTPE2.RXDLY_CFG[13] origin:064-gtp-channel-conf 29_686 -GTP_CHANNEL_0.GTPE2.RXDLY_CFG[14] origin:064-gtp-channel-conf 28_687 -GTP_CHANNEL_0.GTPE2.RXDLY_CFG[15] origin:064-gtp-channel-conf 29_687 -GTP_CHANNEL_0.GTPE2.RXDLY_LCFG[0] origin:064-gtp-channel-conf 30_576 -GTP_CHANNEL_0.GTPE2.RXDLY_LCFG[1] origin:064-gtp-channel-conf 31_576 -GTP_CHANNEL_0.GTPE2.RXDLY_LCFG[2] origin:064-gtp-channel-conf 30_577 -GTP_CHANNEL_0.GTPE2.RXDLY_LCFG[3] origin:064-gtp-channel-conf 31_577 -GTP_CHANNEL_0.GTPE2.RXDLY_LCFG[4] origin:064-gtp-channel-conf 30_578 -GTP_CHANNEL_0.GTPE2.RXDLY_LCFG[5] origin:064-gtp-channel-conf 31_578 -GTP_CHANNEL_0.GTPE2.RXDLY_LCFG[6] origin:064-gtp-channel-conf 30_579 -GTP_CHANNEL_0.GTPE2.RXDLY_LCFG[7] origin:064-gtp-channel-conf 31_579 -GTP_CHANNEL_0.GTPE2.RXDLY_LCFG[8] origin:064-gtp-channel-conf 30_580 -GTP_CHANNEL_0.GTPE2.RXDLY_TAP_CFG[0] origin:064-gtp-channel-conf 28_672 -GTP_CHANNEL_0.GTPE2.RXDLY_TAP_CFG[1] origin:064-gtp-channel-conf 29_672 -GTP_CHANNEL_0.GTPE2.RXDLY_TAP_CFG[2] origin:064-gtp-channel-conf 28_673 -GTP_CHANNEL_0.GTPE2.RXDLY_TAP_CFG[3] origin:064-gtp-channel-conf 29_673 -GTP_CHANNEL_0.GTPE2.RXDLY_TAP_CFG[4] origin:064-gtp-channel-conf 28_674 -GTP_CHANNEL_0.GTPE2.RXDLY_TAP_CFG[5] origin:064-gtp-channel-conf 29_674 -GTP_CHANNEL_0.GTPE2.RXDLY_TAP_CFG[6] origin:064-gtp-channel-conf 28_675 -GTP_CHANNEL_0.GTPE2.RXDLY_TAP_CFG[7] origin:064-gtp-channel-conf 29_675 -GTP_CHANNEL_0.GTPE2.RXDLY_TAP_CFG[8] origin:064-gtp-channel-conf 28_676 -GTP_CHANNEL_0.GTPE2.RXDLY_TAP_CFG[9] origin:064-gtp-channel-conf 29_676 -GTP_CHANNEL_0.GTPE2.RXDLY_TAP_CFG[10] origin:064-gtp-channel-conf 28_677 -GTP_CHANNEL_0.GTPE2.RXDLY_TAP_CFG[11] origin:064-gtp-channel-conf 29_677 -GTP_CHANNEL_0.GTPE2.RXDLY_TAP_CFG[12] origin:064-gtp-channel-conf 28_678 -GTP_CHANNEL_0.GTPE2.RXDLY_TAP_CFG[13] origin:064-gtp-channel-conf 29_678 -GTP_CHANNEL_0.GTPE2.RXDLY_TAP_CFG[14] origin:064-gtp-channel-conf 28_679 -GTP_CHANNEL_0.GTPE2.RXDLY_TAP_CFG[15] origin:064-gtp-channel-conf 29_679 -GTP_CHANNEL_0.GTPE2.RXGEARBOX_EN origin:064-gtp-channel-conf 29_607 -GTP_CHANNEL_0.GTPE2.RXISCANRESET_TIME[0] origin:064-gtp-channel-conf 29_123 -GTP_CHANNEL_0.GTPE2.RXISCANRESET_TIME[1] origin:064-gtp-channel-conf 28_124 -GTP_CHANNEL_0.GTPE2.RXISCANRESET_TIME[2] origin:064-gtp-channel-conf 29_124 -GTP_CHANNEL_0.GTPE2.RXISCANRESET_TIME[3] origin:064-gtp-channel-conf 28_125 -GTP_CHANNEL_0.GTPE2.RXISCANRESET_TIME[4] origin:064-gtp-channel-conf 29_125 -GTP_CHANNEL_0.GTPE2.RXLPM_BIAS_STARTUP_DISABLE[0] origin:064-gtp-channel-conf 31_391 -GTP_CHANNEL_0.GTPE2.RXLPM_CFG[0] origin:064-gtp-channel-conf 30_328 -GTP_CHANNEL_0.GTPE2.RXLPM_CFG[1] origin:064-gtp-channel-conf 31_328 -GTP_CHANNEL_0.GTPE2.RXLPM_CFG[2] origin:064-gtp-channel-conf 30_329 -GTP_CHANNEL_0.GTPE2.RXLPM_CFG[3] origin:064-gtp-channel-conf 31_329 -GTP_CHANNEL_0.GTPE2.RXLPM_CM_CFG[0] origin:064-gtp-channel-conf 30_430 -GTP_CHANNEL_0.GTPE2.RXLPM_GC_CFG[0] origin:064-gtp-channel-conf 30_432 -GTP_CHANNEL_0.GTPE2.RXLPM_GC_CFG[1] origin:064-gtp-channel-conf 31_432 -GTP_CHANNEL_0.GTPE2.RXLPM_GC_CFG[2] origin:064-gtp-channel-conf 30_433 -GTP_CHANNEL_0.GTPE2.RXLPM_GC_CFG[3] origin:064-gtp-channel-conf 31_433 -GTP_CHANNEL_0.GTPE2.RXLPM_GC_CFG[4] origin:064-gtp-channel-conf 30_434 -GTP_CHANNEL_0.GTPE2.RXLPM_GC_CFG[5] origin:064-gtp-channel-conf 31_434 -GTP_CHANNEL_0.GTPE2.RXLPM_GC_CFG[6] origin:064-gtp-channel-conf 30_435 -GTP_CHANNEL_0.GTPE2.RXLPM_GC_CFG[7] origin:064-gtp-channel-conf 31_435 -GTP_CHANNEL_0.GTPE2.RXLPM_GC_CFG[8] origin:064-gtp-channel-conf 30_436 -GTP_CHANNEL_0.GTPE2.RXLPM_GC_CFG2[0] origin:064-gtp-channel-conf 31_442 -GTP_CHANNEL_0.GTPE2.RXLPM_GC_CFG2[1] origin:064-gtp-channel-conf 30_443 -GTP_CHANNEL_0.GTPE2.RXLPM_GC_CFG2[2] origin:064-gtp-channel-conf 31_443 -GTP_CHANNEL_0.GTPE2.RXLPM_HF_CFG[0] origin:064-gtp-channel-conf 28_336 -GTP_CHANNEL_0.GTPE2.RXLPM_HF_CFG[1] origin:064-gtp-channel-conf 29_336 -GTP_CHANNEL_0.GTPE2.RXLPM_HF_CFG[2] origin:064-gtp-channel-conf 28_337 -GTP_CHANNEL_0.GTPE2.RXLPM_HF_CFG[3] origin:064-gtp-channel-conf 29_337 -GTP_CHANNEL_0.GTPE2.RXLPM_HF_CFG[4] origin:064-gtp-channel-conf 28_338 -GTP_CHANNEL_0.GTPE2.RXLPM_HF_CFG[5] origin:064-gtp-channel-conf 29_338 -GTP_CHANNEL_0.GTPE2.RXLPM_HF_CFG[6] origin:064-gtp-channel-conf 28_339 -GTP_CHANNEL_0.GTPE2.RXLPM_HF_CFG[7] origin:064-gtp-channel-conf 29_339 -GTP_CHANNEL_0.GTPE2.RXLPM_HF_CFG[8] origin:064-gtp-channel-conf 28_340 -GTP_CHANNEL_0.GTPE2.RXLPM_HF_CFG[9] origin:064-gtp-channel-conf 29_340 -GTP_CHANNEL_0.GTPE2.RXLPM_HF_CFG[10] origin:064-gtp-channel-conf 28_341 -GTP_CHANNEL_0.GTPE2.RXLPM_HF_CFG[11] origin:064-gtp-channel-conf 29_341 -GTP_CHANNEL_0.GTPE2.RXLPM_HF_CFG[12] origin:064-gtp-channel-conf 28_342 -GTP_CHANNEL_0.GTPE2.RXLPM_HF_CFG[13] origin:064-gtp-channel-conf 29_342 -GTP_CHANNEL_0.GTPE2.RXLPM_HF_CFG2[0] origin:064-gtp-channel-conf 30_424 -GTP_CHANNEL_0.GTPE2.RXLPM_HF_CFG2[1] origin:064-gtp-channel-conf 31_424 -GTP_CHANNEL_0.GTPE2.RXLPM_HF_CFG2[2] origin:064-gtp-channel-conf 30_425 -GTP_CHANNEL_0.GTPE2.RXLPM_HF_CFG2[3] origin:064-gtp-channel-conf 31_425 -GTP_CHANNEL_0.GTPE2.RXLPM_HF_CFG2[4] origin:064-gtp-channel-conf 30_426 -GTP_CHANNEL_0.GTPE2.RXLPM_HF_CFG3[0] origin:064-gtp-channel-conf 31_389 -GTP_CHANNEL_0.GTPE2.RXLPM_HF_CFG3[1] origin:064-gtp-channel-conf 30_390 -GTP_CHANNEL_0.GTPE2.RXLPM_HF_CFG3[2] origin:064-gtp-channel-conf 31_390 -GTP_CHANNEL_0.GTPE2.RXLPM_HF_CFG3[3] origin:064-gtp-channel-conf 30_391 -GTP_CHANNEL_0.GTPE2.RXLPM_HOLD_DURING_EIDLE[0] origin:064-gtp-channel-conf 28_247 -GTP_CHANNEL_0.GTPE2.RXLPM_INCM_CFG[0] origin:064-gtp-channel-conf 30_439 -GTP_CHANNEL_0.GTPE2.RXLPM_IPCM_CFG[0] origin:064-gtp-channel-conf 31_439 -GTP_CHANNEL_0.GTPE2.RXLPM_LF_CFG[0] origin:064-gtp-channel-conf 28_344 -GTP_CHANNEL_0.GTPE2.RXLPM_LF_CFG[1] origin:064-gtp-channel-conf 29_344 -GTP_CHANNEL_0.GTPE2.RXLPM_LF_CFG[2] origin:064-gtp-channel-conf 28_345 -GTP_CHANNEL_0.GTPE2.RXLPM_LF_CFG[3] origin:064-gtp-channel-conf 29_345 -GTP_CHANNEL_0.GTPE2.RXLPM_LF_CFG[4] origin:064-gtp-channel-conf 28_346 -GTP_CHANNEL_0.GTPE2.RXLPM_LF_CFG[5] origin:064-gtp-channel-conf 29_346 -GTP_CHANNEL_0.GTPE2.RXLPM_LF_CFG[6] origin:064-gtp-channel-conf 28_347 -GTP_CHANNEL_0.GTPE2.RXLPM_LF_CFG[7] origin:064-gtp-channel-conf 29_347 -GTP_CHANNEL_0.GTPE2.RXLPM_LF_CFG[8] origin:064-gtp-channel-conf 28_348 -GTP_CHANNEL_0.GTPE2.RXLPM_LF_CFG[9] origin:064-gtp-channel-conf 29_348 -GTP_CHANNEL_0.GTPE2.RXLPM_LF_CFG[10] origin:064-gtp-channel-conf 28_349 -GTP_CHANNEL_0.GTPE2.RXLPM_LF_CFG[11] origin:064-gtp-channel-conf 29_349 -GTP_CHANNEL_0.GTPE2.RXLPM_LF_CFG[12] origin:064-gtp-channel-conf 28_350 -GTP_CHANNEL_0.GTPE2.RXLPM_LF_CFG[13] origin:064-gtp-channel-conf 29_350 -GTP_CHANNEL_0.GTPE2.RXLPM_LF_CFG[14] origin:064-gtp-channel-conf 28_351 -GTP_CHANNEL_0.GTPE2.RXLPM_LF_CFG[15] origin:064-gtp-channel-conf 29_351 -GTP_CHANNEL_0.GTPE2.RXLPM_LF_CFG[16] origin:064-gtp-channel-conf 28_343 -GTP_CHANNEL_0.GTPE2.RXLPM_LF_CFG[17] origin:064-gtp-channel-conf 29_343 -GTP_CHANNEL_0.GTPE2.RXLPM_LF_CFG2[0] origin:064-gtp-channel-conf 31_426 -GTP_CHANNEL_0.GTPE2.RXLPM_LF_CFG2[1] origin:064-gtp-channel-conf 30_427 -GTP_CHANNEL_0.GTPE2.RXLPM_LF_CFG2[2] origin:064-gtp-channel-conf 31_427 -GTP_CHANNEL_0.GTPE2.RXLPM_LF_CFG2[3] origin:064-gtp-channel-conf 30_428 -GTP_CHANNEL_0.GTPE2.RXLPM_LF_CFG2[4] origin:064-gtp-channel-conf 31_428 -GTP_CHANNEL_0.GTPE2.RXLPM_OSINT_CFG[0] origin:064-gtp-channel-conf 30_440 -GTP_CHANNEL_0.GTPE2.RXLPM_OSINT_CFG[1] origin:064-gtp-channel-conf 31_440 -GTP_CHANNEL_0.GTPE2.RXLPM_OSINT_CFG[2] origin:064-gtp-channel-conf 30_441 -GTP_CHANNEL_0.GTPE2.RXLPM_CFG1[0] origin:064-gtp-channel-conf 30_330 -GTP_CHANNEL_0.GTPE2.RXLPMRESET_TIME[0] origin:064-gtp-channel-conf 28_112 -GTP_CHANNEL_0.GTPE2.RXLPMRESET_TIME[1] origin:064-gtp-channel-conf 29_112 -GTP_CHANNEL_0.GTPE2.RXLPMRESET_TIME[2] origin:064-gtp-channel-conf 28_113 -GTP_CHANNEL_0.GTPE2.RXLPMRESET_TIME[3] origin:064-gtp-channel-conf 29_113 -GTP_CHANNEL_0.GTPE2.RXLPMRESET_TIME[4] origin:064-gtp-channel-conf 28_114 -GTP_CHANNEL_0.GTPE2.RXLPMRESET_TIME[5] origin:064-gtp-channel-conf 29_114 -GTP_CHANNEL_0.GTPE2.RXLPMRESET_TIME[6] origin:064-gtp-channel-conf 28_115 -GTP_CHANNEL_0.GTPE2.RXOOB_CFG[0] origin:064-gtp-channel-conf 28_144 -GTP_CHANNEL_0.GTPE2.RXOOB_CFG[1] origin:064-gtp-channel-conf 29_144 -GTP_CHANNEL_0.GTPE2.RXOOB_CFG[2] origin:064-gtp-channel-conf 28_145 -GTP_CHANNEL_0.GTPE2.RXOOB_CFG[3] origin:064-gtp-channel-conf 29_145 -GTP_CHANNEL_0.GTPE2.RXOOB_CFG[4] origin:064-gtp-channel-conf 28_146 -GTP_CHANNEL_0.GTPE2.RXOOB_CFG[5] origin:064-gtp-channel-conf 29_146 -GTP_CHANNEL_0.GTPE2.RXOOB_CFG[6] origin:064-gtp-channel-conf 28_147 -GTP_CHANNEL_0.GTPE2.RXOOB_CLK_CFG.FABRIC origin:064-gtp-channel-conf 31_129 -GTP_CHANNEL_0.GTPE2.RXOSCALRESET_TIME[0] origin:064-gtp-channel-conf 28_187 -GTP_CHANNEL_0.GTPE2.RXOSCALRESET_TIME[1] origin:064-gtp-channel-conf 29_187 -GTP_CHANNEL_0.GTPE2.RXOSCALRESET_TIME[2] origin:064-gtp-channel-conf 28_188 -GTP_CHANNEL_0.GTPE2.RXOSCALRESET_TIME[3] origin:064-gtp-channel-conf 29_188 -GTP_CHANNEL_0.GTPE2.RXOSCALRESET_TIME[4] origin:064-gtp-channel-conf 28_189 -GTP_CHANNEL_0.GTPE2.RXOSCALRESET_TIMEOUT[0] origin:064-gtp-channel-conf 29_189 -GTP_CHANNEL_0.GTPE2.RXOSCALRESET_TIMEOUT[1] origin:064-gtp-channel-conf 28_190 -GTP_CHANNEL_0.GTPE2.RXOSCALRESET_TIMEOUT[2] origin:064-gtp-channel-conf 29_190 -GTP_CHANNEL_0.GTPE2.RXOSCALRESET_TIMEOUT[3] origin:064-gtp-channel-conf 28_191 -GTP_CHANNEL_0.GTPE2.RXOSCALRESET_TIMEOUT[4] origin:064-gtp-channel-conf 29_191 -GTP_CHANNEL_0.GTPE2.RXOUT_DIV[0] origin:064-gtp-channel-conf 30_384 -GTP_CHANNEL_0.GTPE2.RXOUT_DIV[1] origin:064-gtp-channel-conf 31_384 -GTP_CHANNEL_0.GTPE2.RXPCSRESET_TIME[0] origin:064-gtp-channel-conf 29_115 -GTP_CHANNEL_0.GTPE2.RXPCSRESET_TIME[1] origin:064-gtp-channel-conf 28_116 -GTP_CHANNEL_0.GTPE2.RXPCSRESET_TIME[2] origin:064-gtp-channel-conf 29_116 -GTP_CHANNEL_0.GTPE2.RXPCSRESET_TIME[3] origin:064-gtp-channel-conf 28_117 -GTP_CHANNEL_0.GTPE2.RXPCSRESET_TIME[4] origin:064-gtp-channel-conf 29_117 -GTP_CHANNEL_0.GTPE2.RXPH_CFG[0] origin:064-gtp-channel-conf 30_584 -GTP_CHANNEL_0.GTPE2.RXPH_CFG[1] origin:064-gtp-channel-conf 31_584 -GTP_CHANNEL_0.GTPE2.RXPH_CFG[2] origin:064-gtp-channel-conf 30_585 -GTP_CHANNEL_0.GTPE2.RXPH_CFG[3] origin:064-gtp-channel-conf 31_585 -GTP_CHANNEL_0.GTPE2.RXPH_CFG[4] origin:064-gtp-channel-conf 30_586 -GTP_CHANNEL_0.GTPE2.RXPH_CFG[5] origin:064-gtp-channel-conf 31_586 -GTP_CHANNEL_0.GTPE2.RXPH_CFG[6] origin:064-gtp-channel-conf 30_587 -GTP_CHANNEL_0.GTPE2.RXPH_CFG[7] origin:064-gtp-channel-conf 31_587 -GTP_CHANNEL_0.GTPE2.RXPH_CFG[8] origin:064-gtp-channel-conf 30_588 -GTP_CHANNEL_0.GTPE2.RXPH_CFG[9] origin:064-gtp-channel-conf 31_588 -GTP_CHANNEL_0.GTPE2.RXPH_CFG[10] origin:064-gtp-channel-conf 30_589 -GTP_CHANNEL_0.GTPE2.RXPH_CFG[11] origin:064-gtp-channel-conf 31_589 -GTP_CHANNEL_0.GTPE2.RXPH_CFG[12] origin:064-gtp-channel-conf 30_590 -GTP_CHANNEL_0.GTPE2.RXPH_CFG[13] origin:064-gtp-channel-conf 31_590 -GTP_CHANNEL_0.GTPE2.RXPH_CFG[14] origin:064-gtp-channel-conf 30_591 -GTP_CHANNEL_0.GTPE2.RXPH_CFG[15] origin:064-gtp-channel-conf 31_591 -GTP_CHANNEL_0.GTPE2.RXPH_CFG[16] origin:064-gtp-channel-conf 30_592 -GTP_CHANNEL_0.GTPE2.RXPH_CFG[17] origin:064-gtp-channel-conf 31_592 -GTP_CHANNEL_0.GTPE2.RXPH_CFG[18] origin:064-gtp-channel-conf 30_593 -GTP_CHANNEL_0.GTPE2.RXPH_CFG[19] origin:064-gtp-channel-conf 31_593 -GTP_CHANNEL_0.GTPE2.RXPH_CFG[20] origin:064-gtp-channel-conf 30_594 -GTP_CHANNEL_0.GTPE2.RXPH_CFG[21] origin:064-gtp-channel-conf 31_594 -GTP_CHANNEL_0.GTPE2.RXPH_CFG[22] origin:064-gtp-channel-conf 30_595 -GTP_CHANNEL_0.GTPE2.RXPH_CFG[23] origin:064-gtp-channel-conf 31_595 -GTP_CHANNEL_0.GTPE2.RXPH_MONITOR_SEL[0] origin:064-gtp-channel-conf 28_700 -GTP_CHANNEL_0.GTPE2.RXPH_MONITOR_SEL[1] origin:064-gtp-channel-conf 29_700 -GTP_CHANNEL_0.GTPE2.RXPH_MONITOR_SEL[2] origin:064-gtp-channel-conf 28_701 -GTP_CHANNEL_0.GTPE2.RXPH_MONITOR_SEL[3] origin:064-gtp-channel-conf 29_701 -GTP_CHANNEL_0.GTPE2.RXPH_MONITOR_SEL[4] origin:064-gtp-channel-conf 28_702 -GTP_CHANNEL_0.GTPE2.RXPHDLY_CFG[0] origin:064-gtp-channel-conf 30_600 -GTP_CHANNEL_0.GTPE2.RXPHDLY_CFG[1] origin:064-gtp-channel-conf 31_600 -GTP_CHANNEL_0.GTPE2.RXPHDLY_CFG[2] origin:064-gtp-channel-conf 30_601 -GTP_CHANNEL_0.GTPE2.RXPHDLY_CFG[3] origin:064-gtp-channel-conf 31_601 -GTP_CHANNEL_0.GTPE2.RXPHDLY_CFG[4] origin:064-gtp-channel-conf 30_602 -GTP_CHANNEL_0.GTPE2.RXPHDLY_CFG[5] origin:064-gtp-channel-conf 31_602 -GTP_CHANNEL_0.GTPE2.RXPHDLY_CFG[6] origin:064-gtp-channel-conf 30_603 -GTP_CHANNEL_0.GTPE2.RXPHDLY_CFG[7] origin:064-gtp-channel-conf 31_603 -GTP_CHANNEL_0.GTPE2.RXPHDLY_CFG[8] origin:064-gtp-channel-conf 30_604 -GTP_CHANNEL_0.GTPE2.RXPHDLY_CFG[9] origin:064-gtp-channel-conf 31_604 -GTP_CHANNEL_0.GTPE2.RXPHDLY_CFG[10] origin:064-gtp-channel-conf 30_605 -GTP_CHANNEL_0.GTPE2.RXPHDLY_CFG[11] origin:064-gtp-channel-conf 31_605 -GTP_CHANNEL_0.GTPE2.RXPHDLY_CFG[12] origin:064-gtp-channel-conf 30_606 -GTP_CHANNEL_0.GTPE2.RXPHDLY_CFG[13] origin:064-gtp-channel-conf 31_606 -GTP_CHANNEL_0.GTPE2.RXPHDLY_CFG[14] origin:064-gtp-channel-conf 30_607 -GTP_CHANNEL_0.GTPE2.RXPHDLY_CFG[15] origin:064-gtp-channel-conf 31_607 -GTP_CHANNEL_0.GTPE2.RXPHDLY_CFG[16] origin:064-gtp-channel-conf 30_608 -GTP_CHANNEL_0.GTPE2.RXPHDLY_CFG[17] origin:064-gtp-channel-conf 31_608 -GTP_CHANNEL_0.GTPE2.RXPHDLY_CFG[18] origin:064-gtp-channel-conf 30_609 -GTP_CHANNEL_0.GTPE2.RXPHDLY_CFG[19] origin:064-gtp-channel-conf 31_609 -GTP_CHANNEL_0.GTPE2.RXPHDLY_CFG[20] origin:064-gtp-channel-conf 30_610 -GTP_CHANNEL_0.GTPE2.RXPHDLY_CFG[21] origin:064-gtp-channel-conf 31_610 -GTP_CHANNEL_0.GTPE2.RXPHDLY_CFG[22] origin:064-gtp-channel-conf 30_611 -GTP_CHANNEL_0.GTPE2.RXPHDLY_CFG[23] origin:064-gtp-channel-conf 31_611 -GTP_CHANNEL_0.GTPE2.RXPI_CFG0[0] origin:064-gtp-channel-conf 31_430 -GTP_CHANNEL_0.GTPE2.RXPI_CFG0[1] origin:064-gtp-channel-conf 30_431 -GTP_CHANNEL_0.GTPE2.RXPI_CFG0[2] origin:064-gtp-channel-conf 31_431 -GTP_CHANNEL_0.GTPE2.RXPI_CFG1[0] origin:064-gtp-channel-conf 30_442 -GTP_CHANNEL_0.GTPE2.RXPI_CFG2[0] origin:064-gtp-channel-conf 31_441 -GTP_CHANNEL_0.GTPE2.RXPMARESET_TIME[0] origin:064-gtp-channel-conf 28_104 -GTP_CHANNEL_0.GTPE2.RXPMARESET_TIME[1] origin:064-gtp-channel-conf 29_104 -GTP_CHANNEL_0.GTPE2.RXPMARESET_TIME[2] origin:064-gtp-channel-conf 28_105 -GTP_CHANNEL_0.GTPE2.RXPMARESET_TIME[3] origin:064-gtp-channel-conf 29_105 -GTP_CHANNEL_0.GTPE2.RXPMARESET_TIME[4] origin:064-gtp-channel-conf 28_106 -GTP_CHANNEL_0.GTPE2.RXPRBS_ERR_LOOPBACK[0] origin:064-gtp-channel-conf 28_136 -GTP_CHANNEL_0.GTPE2.RXSLIDE_AUTO_WAIT[0] origin:064-gtp-channel-conf 28_520 -GTP_CHANNEL_0.GTPE2.RXSLIDE_AUTO_WAIT[1] origin:064-gtp-channel-conf 29_520 -GTP_CHANNEL_0.GTPE2.RXSLIDE_AUTO_WAIT[2] origin:064-gtp-channel-conf 28_521 -GTP_CHANNEL_0.GTPE2.RXSLIDE_AUTO_WAIT[3] origin:064-gtp-channel-conf 29_521 -GTP_CHANNEL_0.GTPE2.RXSLIDE_MODE.AUTO origin:064-gtp-channel-conf !29_519 28_519 -GTP_CHANNEL_0.GTPE2.RXSLIDE_MODE.PCS origin:064-gtp-channel-conf !28_519 29_519 -GTP_CHANNEL_0.GTPE2.RXSLIDE_MODE.PMA origin:064-gtp-channel-conf 28_519 29_519 -GTP_CHANNEL_0.GTPE2.RXSYNC_MULTILANE[0] origin:064-gtp-channel-conf 28_133 -GTP_CHANNEL_0.GTPE2.RXSYNC_OVRD[0] origin:064-gtp-channel-conf 29_135 -GTP_CHANNEL_0.GTPE2.RXSYNC_SKIP_DA[0] origin:064-gtp-channel-conf 29_134 -GTP_CHANNEL_0.GTPE2.SAS_MAX_COM[0] origin:064-gtp-channel-conf 28_171 -GTP_CHANNEL_0.GTPE2.SAS_MAX_COM[1] origin:064-gtp-channel-conf 29_171 -GTP_CHANNEL_0.GTPE2.SAS_MAX_COM[2] origin:064-gtp-channel-conf 28_172 -GTP_CHANNEL_0.GTPE2.SAS_MAX_COM[3] origin:064-gtp-channel-conf 29_172 -GTP_CHANNEL_0.GTPE2.SAS_MAX_COM[4] origin:064-gtp-channel-conf 28_173 -GTP_CHANNEL_0.GTPE2.SAS_MAX_COM[5] origin:064-gtp-channel-conf 29_173 -GTP_CHANNEL_0.GTPE2.SAS_MAX_COM[6] origin:064-gtp-channel-conf 28_174 -GTP_CHANNEL_0.GTPE2.SAS_MIN_COM[0] origin:064-gtp-channel-conf 29_156 -GTP_CHANNEL_0.GTPE2.SAS_MIN_COM[1] origin:064-gtp-channel-conf 28_157 -GTP_CHANNEL_0.GTPE2.SAS_MIN_COM[2] origin:064-gtp-channel-conf 29_157 -GTP_CHANNEL_0.GTPE2.SAS_MIN_COM[3] origin:064-gtp-channel-conf 28_158 -GTP_CHANNEL_0.GTPE2.SAS_MIN_COM[4] origin:064-gtp-channel-conf 29_158 -GTP_CHANNEL_0.GTPE2.SAS_MIN_COM[5] origin:064-gtp-channel-conf 28_159 -GTP_CHANNEL_0.GTPE2.SATA_BURST_SEQ_LEN[0] origin:064-gtp-channel-conf 28_150 -GTP_CHANNEL_0.GTPE2.SATA_BURST_SEQ_LEN[1] origin:064-gtp-channel-conf 29_150 -GTP_CHANNEL_0.GTPE2.SATA_BURST_SEQ_LEN[2] origin:064-gtp-channel-conf 28_151 -GTP_CHANNEL_0.GTPE2.SATA_BURST_SEQ_LEN[3] origin:064-gtp-channel-conf 29_151 -GTP_CHANNEL_0.GTPE2.SATA_BURST_VAL[0] origin:064-gtp-channel-conf 29_147 -GTP_CHANNEL_0.GTPE2.SATA_BURST_VAL[1] origin:064-gtp-channel-conf 28_148 -GTP_CHANNEL_0.GTPE2.SATA_BURST_VAL[2] origin:064-gtp-channel-conf 29_148 -GTP_CHANNEL_0.GTPE2.SATA_EIDLE_VAL[0] origin:064-gtp-channel-conf 28_152 -GTP_CHANNEL_0.GTPE2.SATA_EIDLE_VAL[1] origin:064-gtp-channel-conf 29_152 -GTP_CHANNEL_0.GTPE2.SATA_EIDLE_VAL[2] origin:064-gtp-channel-conf 28_153 -GTP_CHANNEL_0.GTPE2.SATA_MAX_BURST[0] origin:064-gtp-channel-conf 28_168 -GTP_CHANNEL_0.GTPE2.SATA_MAX_BURST[1] origin:064-gtp-channel-conf 29_168 -GTP_CHANNEL_0.GTPE2.SATA_MAX_BURST[2] origin:064-gtp-channel-conf 28_169 -GTP_CHANNEL_0.GTPE2.SATA_MAX_BURST[3] origin:064-gtp-channel-conf 29_169 -GTP_CHANNEL_0.GTPE2.SATA_MAX_BURST[4] origin:064-gtp-channel-conf 28_170 -GTP_CHANNEL_0.GTPE2.SATA_MAX_BURST[5] origin:064-gtp-channel-conf 29_170 -GTP_CHANNEL_0.GTPE2.SATA_MAX_INIT[0] origin:064-gtp-channel-conf 28_176 -GTP_CHANNEL_0.GTPE2.SATA_MAX_INIT[1] origin:064-gtp-channel-conf 29_176 -GTP_CHANNEL_0.GTPE2.SATA_MAX_INIT[2] origin:064-gtp-channel-conf 28_177 -GTP_CHANNEL_0.GTPE2.SATA_MAX_INIT[3] origin:064-gtp-channel-conf 29_177 -GTP_CHANNEL_0.GTPE2.SATA_MAX_INIT[4] origin:064-gtp-channel-conf 28_178 -GTP_CHANNEL_0.GTPE2.SATA_MAX_INIT[5] origin:064-gtp-channel-conf 29_178 -GTP_CHANNEL_0.GTPE2.SATA_MAX_WAKE[0] origin:064-gtp-channel-conf 28_179 -GTP_CHANNEL_0.GTPE2.SATA_MAX_WAKE[1] origin:064-gtp-channel-conf 29_179 -GTP_CHANNEL_0.GTPE2.SATA_MAX_WAKE[2] origin:064-gtp-channel-conf 28_180 -GTP_CHANNEL_0.GTPE2.SATA_MAX_WAKE[3] origin:064-gtp-channel-conf 29_180 -GTP_CHANNEL_0.GTPE2.SATA_MAX_WAKE[4] origin:064-gtp-channel-conf 28_181 -GTP_CHANNEL_0.GTPE2.SATA_MAX_WAKE[5] origin:064-gtp-channel-conf 29_181 -GTP_CHANNEL_0.GTPE2.SATA_MIN_BURST[0] origin:064-gtp-channel-conf 29_153 -GTP_CHANNEL_0.GTPE2.SATA_MIN_BURST[1] origin:064-gtp-channel-conf 28_154 -GTP_CHANNEL_0.GTPE2.SATA_MIN_BURST[2] origin:064-gtp-channel-conf 29_154 -GTP_CHANNEL_0.GTPE2.SATA_MIN_BURST[3] origin:064-gtp-channel-conf 28_155 -GTP_CHANNEL_0.GTPE2.SATA_MIN_BURST[4] origin:064-gtp-channel-conf 29_155 -GTP_CHANNEL_0.GTPE2.SATA_MIN_BURST[5] origin:064-gtp-channel-conf 28_156 -GTP_CHANNEL_0.GTPE2.SATA_MIN_INIT[0] origin:064-gtp-channel-conf 28_160 -GTP_CHANNEL_0.GTPE2.SATA_MIN_INIT[1] origin:064-gtp-channel-conf 29_160 -GTP_CHANNEL_0.GTPE2.SATA_MIN_INIT[2] origin:064-gtp-channel-conf 28_161 -GTP_CHANNEL_0.GTPE2.SATA_MIN_INIT[3] origin:064-gtp-channel-conf 29_161 -GTP_CHANNEL_0.GTPE2.SATA_MIN_INIT[4] origin:064-gtp-channel-conf 28_162 -GTP_CHANNEL_0.GTPE2.SATA_MIN_INIT[5] origin:064-gtp-channel-conf 29_162 -GTP_CHANNEL_0.GTPE2.SATA_MIN_WAKE[0] origin:064-gtp-channel-conf 28_163 -GTP_CHANNEL_0.GTPE2.SATA_MIN_WAKE[1] origin:064-gtp-channel-conf 29_163 -GTP_CHANNEL_0.GTPE2.SATA_MIN_WAKE[2] origin:064-gtp-channel-conf 28_164 -GTP_CHANNEL_0.GTPE2.SATA_MIN_WAKE[3] origin:064-gtp-channel-conf 29_164 -GTP_CHANNEL_0.GTPE2.SATA_MIN_WAKE[4] origin:064-gtp-channel-conf 28_165 -GTP_CHANNEL_0.GTPE2.SATA_MIN_WAKE[5] origin:064-gtp-channel-conf 29_165 -GTP_CHANNEL_0.GTPE2.SATA_PLL_CFG.VCO_1500MHZ origin:064-gtp-channel-conf 30_55 -GTP_CHANNEL_0.GTPE2.SATA_PLL_CFG.VCO_750MHZ origin:064-gtp-channel-conf 31_55 -GTP_CHANNEL_0.GTPE2.SHOW_REALIGN_COMMA origin:064-gtp-channel-conf 29_522 -GTP_CHANNEL_0.GTPE2.TERM_RCAL_CFG[0] origin:064-gtp-channel-conf 30_136 -GTP_CHANNEL_0.GTPE2.TERM_RCAL_CFG[1] origin:064-gtp-channel-conf 31_136 -GTP_CHANNEL_0.GTPE2.TERM_RCAL_CFG[2] origin:064-gtp-channel-conf 30_137 -GTP_CHANNEL_0.GTPE2.TERM_RCAL_CFG[3] origin:064-gtp-channel-conf 31_137 -GTP_CHANNEL_0.GTPE2.TERM_RCAL_CFG[4] origin:064-gtp-channel-conf 30_138 -GTP_CHANNEL_0.GTPE2.TERM_RCAL_CFG[5] origin:064-gtp-channel-conf 31_138 -GTP_CHANNEL_0.GTPE2.TERM_RCAL_CFG[6] origin:064-gtp-channel-conf 30_139 -GTP_CHANNEL_0.GTPE2.TERM_RCAL_CFG[7] origin:064-gtp-channel-conf 31_139 -GTP_CHANNEL_0.GTPE2.TERM_RCAL_CFG[8] origin:064-gtp-channel-conf 30_140 -GTP_CHANNEL_0.GTPE2.TERM_RCAL_CFG[9] origin:064-gtp-channel-conf 31_140 -GTP_CHANNEL_0.GTPE2.TERM_RCAL_CFG[10] origin:064-gtp-channel-conf 30_141 -GTP_CHANNEL_0.GTPE2.TERM_RCAL_CFG[11] origin:064-gtp-channel-conf 31_141 -GTP_CHANNEL_0.GTPE2.TERM_RCAL_CFG[12] origin:064-gtp-channel-conf 30_142 -GTP_CHANNEL_0.GTPE2.TERM_RCAL_CFG[13] origin:064-gtp-channel-conf 31_142 -GTP_CHANNEL_0.GTPE2.TERM_RCAL_CFG[14] origin:064-gtp-channel-conf 30_143 -GTP_CHANNEL_0.GTPE2.TERM_RCAL_OVRD[0] origin:064-gtp-channel-conf 31_150 -GTP_CHANNEL_0.GTPE2.TERM_RCAL_OVRD[1] origin:064-gtp-channel-conf 30_151 -GTP_CHANNEL_0.GTPE2.TERM_RCAL_OVRD[2] origin:064-gtp-channel-conf 31_151 -GTP_CHANNEL_0.GTPE2.TRANS_TIME_RATE[0] origin:064-gtp-channel-conf 28_192 -GTP_CHANNEL_0.GTPE2.TRANS_TIME_RATE[1] origin:064-gtp-channel-conf 29_192 -GTP_CHANNEL_0.GTPE2.TRANS_TIME_RATE[2] origin:064-gtp-channel-conf 28_193 -GTP_CHANNEL_0.GTPE2.TRANS_TIME_RATE[3] origin:064-gtp-channel-conf 29_193 -GTP_CHANNEL_0.GTPE2.TRANS_TIME_RATE[4] origin:064-gtp-channel-conf 28_194 -GTP_CHANNEL_0.GTPE2.TRANS_TIME_RATE[5] origin:064-gtp-channel-conf 29_194 -GTP_CHANNEL_0.GTPE2.TRANS_TIME_RATE[6] origin:064-gtp-channel-conf 28_195 -GTP_CHANNEL_0.GTPE2.TRANS_TIME_RATE[7] origin:064-gtp-channel-conf 29_195 -GTP_CHANNEL_0.GTPE2.TST_RSV[0] origin:064-gtp-channel-conf 30_504 -GTP_CHANNEL_0.GTPE2.TST_RSV[1] origin:064-gtp-channel-conf 31_504 -GTP_CHANNEL_0.GTPE2.TST_RSV[2] origin:064-gtp-channel-conf 30_505 -GTP_CHANNEL_0.GTPE2.TST_RSV[3] origin:064-gtp-channel-conf 31_505 -GTP_CHANNEL_0.GTPE2.TST_RSV[4] origin:064-gtp-channel-conf 30_506 -GTP_CHANNEL_0.GTPE2.TST_RSV[5] origin:064-gtp-channel-conf 31_506 -GTP_CHANNEL_0.GTPE2.TST_RSV[6] origin:064-gtp-channel-conf 30_507 -GTP_CHANNEL_0.GTPE2.TST_RSV[7] origin:064-gtp-channel-conf 31_507 -GTP_CHANNEL_0.GTPE2.TST_RSV[8] origin:064-gtp-channel-conf 30_508 -GTP_CHANNEL_0.GTPE2.TST_RSV[9] origin:064-gtp-channel-conf 31_508 -GTP_CHANNEL_0.GTPE2.TST_RSV[10] origin:064-gtp-channel-conf 30_509 -GTP_CHANNEL_0.GTPE2.TST_RSV[11] origin:064-gtp-channel-conf 31_509 -GTP_CHANNEL_0.GTPE2.TST_RSV[12] origin:064-gtp-channel-conf 30_510 -GTP_CHANNEL_0.GTPE2.TST_RSV[13] origin:064-gtp-channel-conf 31_510 -GTP_CHANNEL_0.GTPE2.TST_RSV[14] origin:064-gtp-channel-conf 30_511 -GTP_CHANNEL_0.GTPE2.TST_RSV[15] origin:064-gtp-channel-conf 31_511 -GTP_CHANNEL_0.GTPE2.TST_RSV[16] origin:064-gtp-channel-conf 30_512 -GTP_CHANNEL_0.GTPE2.TST_RSV[17] origin:064-gtp-channel-conf 31_512 -GTP_CHANNEL_0.GTPE2.TST_RSV[18] origin:064-gtp-channel-conf 30_513 -GTP_CHANNEL_0.GTPE2.TST_RSV[19] origin:064-gtp-channel-conf 31_513 -GTP_CHANNEL_0.GTPE2.TST_RSV[20] origin:064-gtp-channel-conf 30_514 -GTP_CHANNEL_0.GTPE2.TST_RSV[21] origin:064-gtp-channel-conf 31_514 -GTP_CHANNEL_0.GTPE2.TST_RSV[22] origin:064-gtp-channel-conf 30_515 -GTP_CHANNEL_0.GTPE2.TST_RSV[23] origin:064-gtp-channel-conf 31_515 -GTP_CHANNEL_0.GTPE2.TST_RSV[24] origin:064-gtp-channel-conf 30_516 -GTP_CHANNEL_0.GTPE2.TST_RSV[25] origin:064-gtp-channel-conf 31_516 -GTP_CHANNEL_0.GTPE2.TST_RSV[26] origin:064-gtp-channel-conf 30_517 -GTP_CHANNEL_0.GTPE2.TST_RSV[27] origin:064-gtp-channel-conf 31_517 -GTP_CHANNEL_0.GTPE2.TST_RSV[28] origin:064-gtp-channel-conf 30_518 -GTP_CHANNEL_0.GTPE2.TST_RSV[29] origin:064-gtp-channel-conf 31_518 -GTP_CHANNEL_0.GTPE2.TST_RSV[30] origin:064-gtp-channel-conf 30_519 -GTP_CHANNEL_0.GTPE2.TST_RSV[31] origin:064-gtp-channel-conf 31_519 -GTP_CHANNEL_0.GTPE2.TX_CLKMUX_EN[0] origin:064-gtp-channel-conf 31_128 -GTP_CHANNEL_0.GTPE2.TX_DATA_WIDTH[0] origin:064-gtp-channel-conf 30_152 -GTP_CHANNEL_0.GTPE2.TX_DATA_WIDTH[1] origin:064-gtp-channel-conf 31_152 -GTP_CHANNEL_0.GTPE2.TX_DATA_WIDTH[2] origin:064-gtp-channel-conf 30_153 -GTP_CHANNEL_0.GTPE2.TX_DRIVE_MODE.PIPE origin:064-gtp-channel-conf 28_200 -GTP_CHANNEL_0.GTPE2.TX_EIDLE_ASSERT_DELAY[0] origin:064-gtp-channel-conf 28_203 -GTP_CHANNEL_0.GTPE2.TX_EIDLE_ASSERT_DELAY[1] origin:064-gtp-channel-conf 29_203 -GTP_CHANNEL_0.GTPE2.TX_EIDLE_ASSERT_DELAY[2] origin:064-gtp-channel-conf 28_204 -GTP_CHANNEL_0.GTPE2.TX_EIDLE_DEASSERT_DELAY[0] origin:064-gtp-channel-conf 29_204 -GTP_CHANNEL_0.GTPE2.TX_EIDLE_DEASSERT_DELAY[1] origin:064-gtp-channel-conf 28_205 -GTP_CHANNEL_0.GTPE2.TX_EIDLE_DEASSERT_DELAY[2] origin:064-gtp-channel-conf 29_205 -GTP_CHANNEL_0.GTPE2.TX_LOOPBACK_DRIVE_HIZ origin:064-gtp-channel-conf 29_202 -GTP_CHANNEL_0.GTPE2.TX_MAINCURSOR_SEL[0] origin:064-gtp-channel-conf 31_289 -GTP_CHANNEL_0.GTPE2.TX_MARGIN_FULL_0[0] origin:064-gtp-channel-conf 30_232 -GTP_CHANNEL_0.GTPE2.TX_MARGIN_FULL_0[1] origin:064-gtp-channel-conf 31_232 -GTP_CHANNEL_0.GTPE2.TX_MARGIN_FULL_0[2] origin:064-gtp-channel-conf 30_233 -GTP_CHANNEL_0.GTPE2.TX_MARGIN_FULL_0[3] origin:064-gtp-channel-conf 31_233 -GTP_CHANNEL_0.GTPE2.TX_MARGIN_FULL_0[4] origin:064-gtp-channel-conf 30_234 -GTP_CHANNEL_0.GTPE2.TX_MARGIN_FULL_0[5] origin:064-gtp-channel-conf 31_234 -GTP_CHANNEL_0.GTPE2.TX_MARGIN_FULL_0[6] origin:064-gtp-channel-conf 30_235 -GTP_CHANNEL_0.GTPE2.TX_MARGIN_FULL_1[0] origin:064-gtp-channel-conf 30_236 -GTP_CHANNEL_0.GTPE2.TX_MARGIN_FULL_1[1] origin:064-gtp-channel-conf 31_236 -GTP_CHANNEL_0.GTPE2.TX_MARGIN_FULL_1[2] origin:064-gtp-channel-conf 30_237 -GTP_CHANNEL_0.GTPE2.TX_MARGIN_FULL_1[3] origin:064-gtp-channel-conf 31_237 -GTP_CHANNEL_0.GTPE2.TX_MARGIN_FULL_1[4] origin:064-gtp-channel-conf 30_238 -GTP_CHANNEL_0.GTPE2.TX_MARGIN_FULL_1[5] origin:064-gtp-channel-conf 31_238 -GTP_CHANNEL_0.GTPE2.TX_MARGIN_FULL_1[6] origin:064-gtp-channel-conf 30_239 -GTP_CHANNEL_0.GTPE2.TX_MARGIN_FULL_2[0] origin:064-gtp-channel-conf 30_240 -GTP_CHANNEL_0.GTPE2.TX_MARGIN_FULL_2[1] origin:064-gtp-channel-conf 31_240 -GTP_CHANNEL_0.GTPE2.TX_MARGIN_FULL_2[2] origin:064-gtp-channel-conf 30_241 -GTP_CHANNEL_0.GTPE2.TX_MARGIN_FULL_2[3] origin:064-gtp-channel-conf 31_241 -GTP_CHANNEL_0.GTPE2.TX_MARGIN_FULL_2[4] origin:064-gtp-channel-conf 30_242 -GTP_CHANNEL_0.GTPE2.TX_MARGIN_FULL_2[5] origin:064-gtp-channel-conf 31_242 -GTP_CHANNEL_0.GTPE2.TX_MARGIN_FULL_2[6] origin:064-gtp-channel-conf 30_243 -GTP_CHANNEL_0.GTPE2.TX_MARGIN_FULL_3[0] origin:064-gtp-channel-conf 30_244 -GTP_CHANNEL_0.GTPE2.TX_MARGIN_FULL_3[1] origin:064-gtp-channel-conf 31_244 -GTP_CHANNEL_0.GTPE2.TX_MARGIN_FULL_3[2] origin:064-gtp-channel-conf 30_245 -GTP_CHANNEL_0.GTPE2.TX_MARGIN_FULL_3[3] origin:064-gtp-channel-conf 31_245 -GTP_CHANNEL_0.GTPE2.TX_MARGIN_FULL_3[4] origin:064-gtp-channel-conf 30_246 -GTP_CHANNEL_0.GTPE2.TX_MARGIN_FULL_3[5] origin:064-gtp-channel-conf 31_246 -GTP_CHANNEL_0.GTPE2.TX_MARGIN_FULL_3[6] origin:064-gtp-channel-conf 30_247 -GTP_CHANNEL_0.GTPE2.TX_MARGIN_FULL_4[0] origin:064-gtp-channel-conf 30_248 -GTP_CHANNEL_0.GTPE2.TX_MARGIN_FULL_4[1] origin:064-gtp-channel-conf 31_248 -GTP_CHANNEL_0.GTPE2.TX_MARGIN_FULL_4[2] origin:064-gtp-channel-conf 30_249 -GTP_CHANNEL_0.GTPE2.TX_MARGIN_FULL_4[3] origin:064-gtp-channel-conf 31_249 -GTP_CHANNEL_0.GTPE2.TX_MARGIN_FULL_4[4] origin:064-gtp-channel-conf 30_250 -GTP_CHANNEL_0.GTPE2.TX_MARGIN_FULL_4[5] origin:064-gtp-channel-conf 31_250 -GTP_CHANNEL_0.GTPE2.TX_MARGIN_FULL_4[6] origin:064-gtp-channel-conf 30_251 -GTP_CHANNEL_0.GTPE2.TX_MARGIN_LOW_0[0] origin:064-gtp-channel-conf 30_252 -GTP_CHANNEL_0.GTPE2.TX_MARGIN_LOW_0[1] origin:064-gtp-channel-conf 31_252 -GTP_CHANNEL_0.GTPE2.TX_MARGIN_LOW_0[2] origin:064-gtp-channel-conf 30_253 -GTP_CHANNEL_0.GTPE2.TX_MARGIN_LOW_0[3] origin:064-gtp-channel-conf 31_253 -GTP_CHANNEL_0.GTPE2.TX_MARGIN_LOW_0[4] origin:064-gtp-channel-conf 30_254 -GTP_CHANNEL_0.GTPE2.TX_MARGIN_LOW_0[5] origin:064-gtp-channel-conf 31_254 -GTP_CHANNEL_0.GTPE2.TX_MARGIN_LOW_0[6] origin:064-gtp-channel-conf 30_255 -GTP_CHANNEL_0.GTPE2.TX_MARGIN_LOW_1[0] origin:064-gtp-channel-conf 30_256 -GTP_CHANNEL_0.GTPE2.TX_MARGIN_LOW_1[1] origin:064-gtp-channel-conf 31_256 -GTP_CHANNEL_0.GTPE2.TX_MARGIN_LOW_1[2] origin:064-gtp-channel-conf 30_257 -GTP_CHANNEL_0.GTPE2.TX_MARGIN_LOW_1[3] origin:064-gtp-channel-conf 31_257 -GTP_CHANNEL_0.GTPE2.TX_MARGIN_LOW_1[4] origin:064-gtp-channel-conf 30_258 -GTP_CHANNEL_0.GTPE2.TX_MARGIN_LOW_1[5] origin:064-gtp-channel-conf 31_258 -GTP_CHANNEL_0.GTPE2.TX_MARGIN_LOW_1[6] origin:064-gtp-channel-conf 30_259 -GTP_CHANNEL_0.GTPE2.TX_MARGIN_LOW_2[0] origin:064-gtp-channel-conf 30_260 -GTP_CHANNEL_0.GTPE2.TX_MARGIN_LOW_2[1] origin:064-gtp-channel-conf 31_260 -GTP_CHANNEL_0.GTPE2.TX_MARGIN_LOW_2[2] origin:064-gtp-channel-conf 30_261 -GTP_CHANNEL_0.GTPE2.TX_MARGIN_LOW_2[3] origin:064-gtp-channel-conf 31_261 -GTP_CHANNEL_0.GTPE2.TX_MARGIN_LOW_2[4] origin:064-gtp-channel-conf 30_262 -GTP_CHANNEL_0.GTPE2.TX_MARGIN_LOW_2[5] origin:064-gtp-channel-conf 31_262 -GTP_CHANNEL_0.GTPE2.TX_MARGIN_LOW_2[6] origin:064-gtp-channel-conf 30_263 -GTP_CHANNEL_0.GTPE2.TX_MARGIN_LOW_3[0] origin:064-gtp-channel-conf 30_264 -GTP_CHANNEL_0.GTPE2.TX_MARGIN_LOW_3[1] origin:064-gtp-channel-conf 31_264 -GTP_CHANNEL_0.GTPE2.TX_MARGIN_LOW_3[2] origin:064-gtp-channel-conf 30_265 -GTP_CHANNEL_0.GTPE2.TX_MARGIN_LOW_3[3] origin:064-gtp-channel-conf 31_265 -GTP_CHANNEL_0.GTPE2.TX_MARGIN_LOW_3[4] origin:064-gtp-channel-conf 30_266 -GTP_CHANNEL_0.GTPE2.TX_MARGIN_LOW_3[5] origin:064-gtp-channel-conf 31_266 -GTP_CHANNEL_0.GTPE2.TX_MARGIN_LOW_3[6] origin:064-gtp-channel-conf 30_267 -GTP_CHANNEL_0.GTPE2.TX_MARGIN_LOW_4[0] origin:064-gtp-channel-conf 30_268 -GTP_CHANNEL_0.GTPE2.TX_MARGIN_LOW_4[1] origin:064-gtp-channel-conf 31_268 -GTP_CHANNEL_0.GTPE2.TX_MARGIN_LOW_4[2] origin:064-gtp-channel-conf 30_269 -GTP_CHANNEL_0.GTPE2.TX_MARGIN_LOW_4[3] origin:064-gtp-channel-conf 31_269 -GTP_CHANNEL_0.GTPE2.TX_MARGIN_LOW_4[4] origin:064-gtp-channel-conf 30_270 -GTP_CHANNEL_0.GTPE2.TX_MARGIN_LOW_4[5] origin:064-gtp-channel-conf 31_270 -GTP_CHANNEL_0.GTPE2.TX_MARGIN_LOW_4[6] origin:064-gtp-channel-conf 30_271 -GTP_CHANNEL_0.GTPE2.TX_PREDRIVER_MODE[0] origin:064-gtp-channel-conf 28_206 -GTP_CHANNEL_0.GTPE2.TX_RXDETECT_CFG[0] origin:064-gtp-channel-conf 30_296 -GTP_CHANNEL_0.GTPE2.TX_RXDETECT_CFG[1] origin:064-gtp-channel-conf 31_296 -GTP_CHANNEL_0.GTPE2.TX_RXDETECT_CFG[2] origin:064-gtp-channel-conf 30_297 -GTP_CHANNEL_0.GTPE2.TX_RXDETECT_CFG[3] origin:064-gtp-channel-conf 31_297 -GTP_CHANNEL_0.GTPE2.TX_RXDETECT_CFG[4] origin:064-gtp-channel-conf 30_298 -GTP_CHANNEL_0.GTPE2.TX_RXDETECT_CFG[5] origin:064-gtp-channel-conf 31_298 -GTP_CHANNEL_0.GTPE2.TX_RXDETECT_CFG[6] origin:064-gtp-channel-conf 30_299 -GTP_CHANNEL_0.GTPE2.TX_RXDETECT_CFG[7] origin:064-gtp-channel-conf 31_299 -GTP_CHANNEL_0.GTPE2.TX_RXDETECT_CFG[8] origin:064-gtp-channel-conf 30_300 -GTP_CHANNEL_0.GTPE2.TX_RXDETECT_CFG[9] origin:064-gtp-channel-conf 31_300 -GTP_CHANNEL_0.GTPE2.TX_RXDETECT_CFG[10] origin:064-gtp-channel-conf 30_301 -GTP_CHANNEL_0.GTPE2.TX_RXDETECT_CFG[11] origin:064-gtp-channel-conf 31_301 -GTP_CHANNEL_0.GTPE2.TX_RXDETECT_CFG[12] origin:064-gtp-channel-conf 30_302 -GTP_CHANNEL_0.GTPE2.TX_RXDETECT_CFG[13] origin:064-gtp-channel-conf 31_302 -GTP_CHANNEL_0.GTPE2.TX_RXDETECT_REF[0] origin:064-gtp-channel-conf 30_292 -GTP_CHANNEL_0.GTPE2.TX_RXDETECT_REF[1] origin:064-gtp-channel-conf 31_292 -GTP_CHANNEL_0.GTPE2.TX_RXDETECT_REF[2] origin:064-gtp-channel-conf 30_293 -GTP_CHANNEL_0.GTPE2.TX_XCLK_SEL.TXUSR origin:064-gtp-channel-conf 31_11 -GTP_CHANNEL_0.GTPE2.TX_CLK25_DIV[0] origin:064-gtp-channel-conf 30_144 -GTP_CHANNEL_0.GTPE2.TX_CLK25_DIV[1] origin:064-gtp-channel-conf 31_144 -GTP_CHANNEL_0.GTPE2.TX_CLK25_DIV[2] origin:064-gtp-channel-conf 30_145 -GTP_CHANNEL_0.GTPE2.TX_CLK25_DIV[3] origin:064-gtp-channel-conf 31_145 -GTP_CHANNEL_0.GTPE2.TX_CLK25_DIV[4] origin:064-gtp-channel-conf 30_146 -GTP_CHANNEL_0.GTPE2.TX_DEEMPH0[0] origin:064-gtp-channel-conf 30_272 -GTP_CHANNEL_0.GTPE2.TX_DEEMPH0[1] origin:064-gtp-channel-conf 31_272 -GTP_CHANNEL_0.GTPE2.TX_DEEMPH0[2] origin:064-gtp-channel-conf 30_273 -GTP_CHANNEL_0.GTPE2.TX_DEEMPH0[3] origin:064-gtp-channel-conf 31_273 -GTP_CHANNEL_0.GTPE2.TX_DEEMPH0[4] origin:064-gtp-channel-conf 30_274 -GTP_CHANNEL_0.GTPE2.TX_DEEMPH0[5] origin:064-gtp-channel-conf 31_274 -GTP_CHANNEL_0.GTPE2.TX_DEEMPH1[0] origin:064-gtp-channel-conf 30_276 -GTP_CHANNEL_0.GTPE2.TX_DEEMPH1[1] origin:064-gtp-channel-conf 31_276 -GTP_CHANNEL_0.GTPE2.TX_DEEMPH1[2] origin:064-gtp-channel-conf 30_277 -GTP_CHANNEL_0.GTPE2.TX_DEEMPH1[3] origin:064-gtp-channel-conf 31_277 -GTP_CHANNEL_0.GTPE2.TX_DEEMPH1[4] origin:064-gtp-channel-conf 30_278 -GTP_CHANNEL_0.GTPE2.TX_DEEMPH1[5] origin:064-gtp-channel-conf 31_278 -GTP_CHANNEL_0.GTPE2.TXBUF_EN origin:064-gtp-channel-conf 28_231 -GTP_CHANNEL_0.GTPE2.TXBUF_RESET_ON_RATE_CHANGE origin:064-gtp-channel-conf 29_231 -GTP_CHANNEL_0.GTPE2.TXDLY_CFG[0] origin:064-gtp-channel-conf 30_80 -GTP_CHANNEL_0.GTPE2.TXDLY_CFG[1] origin:064-gtp-channel-conf 31_80 -GTP_CHANNEL_0.GTPE2.TXDLY_CFG[2] origin:064-gtp-channel-conf 30_81 -GTP_CHANNEL_0.GTPE2.TXDLY_CFG[3] origin:064-gtp-channel-conf 31_81 -GTP_CHANNEL_0.GTPE2.TXDLY_CFG[4] origin:064-gtp-channel-conf 30_82 -GTP_CHANNEL_0.GTPE2.TXDLY_CFG[5] origin:064-gtp-channel-conf 31_82 -GTP_CHANNEL_0.GTPE2.TXDLY_CFG[6] origin:064-gtp-channel-conf 30_83 -GTP_CHANNEL_0.GTPE2.TXDLY_CFG[7] origin:064-gtp-channel-conf 31_83 -GTP_CHANNEL_0.GTPE2.TXDLY_CFG[8] origin:064-gtp-channel-conf 30_84 -GTP_CHANNEL_0.GTPE2.TXDLY_CFG[9] origin:064-gtp-channel-conf 31_84 -GTP_CHANNEL_0.GTPE2.TXDLY_CFG[10] origin:064-gtp-channel-conf 30_85 -GTP_CHANNEL_0.GTPE2.TXDLY_CFG[11] origin:064-gtp-channel-conf 31_85 -GTP_CHANNEL_0.GTPE2.TXDLY_CFG[12] origin:064-gtp-channel-conf 30_86 -GTP_CHANNEL_0.GTPE2.TXDLY_CFG[13] origin:064-gtp-channel-conf 31_86 -GTP_CHANNEL_0.GTPE2.TXDLY_CFG[14] origin:064-gtp-channel-conf 30_87 -GTP_CHANNEL_0.GTPE2.TXDLY_CFG[15] origin:064-gtp-channel-conf 31_87 -GTP_CHANNEL_0.GTPE2.TXDLY_LCFG[0] origin:064-gtp-channel-conf 30_568 -GTP_CHANNEL_0.GTPE2.TXDLY_LCFG[1] origin:064-gtp-channel-conf 31_568 -GTP_CHANNEL_0.GTPE2.TXDLY_LCFG[2] origin:064-gtp-channel-conf 30_569 -GTP_CHANNEL_0.GTPE2.TXDLY_LCFG[3] origin:064-gtp-channel-conf 31_569 -GTP_CHANNEL_0.GTPE2.TXDLY_LCFG[4] origin:064-gtp-channel-conf 30_570 -GTP_CHANNEL_0.GTPE2.TXDLY_LCFG[5] origin:064-gtp-channel-conf 31_570 -GTP_CHANNEL_0.GTPE2.TXDLY_LCFG[6] origin:064-gtp-channel-conf 30_571 -GTP_CHANNEL_0.GTPE2.TXDLY_LCFG[7] origin:064-gtp-channel-conf 31_571 -GTP_CHANNEL_0.GTPE2.TXDLY_LCFG[8] origin:064-gtp-channel-conf 30_572 -GTP_CHANNEL_0.GTPE2.TXDLY_TAP_CFG[0] origin:064-gtp-channel-conf 30_88 -GTP_CHANNEL_0.GTPE2.TXDLY_TAP_CFG[1] origin:064-gtp-channel-conf 31_88 -GTP_CHANNEL_0.GTPE2.TXDLY_TAP_CFG[2] origin:064-gtp-channel-conf 30_89 -GTP_CHANNEL_0.GTPE2.TXDLY_TAP_CFG[3] origin:064-gtp-channel-conf 31_89 -GTP_CHANNEL_0.GTPE2.TXDLY_TAP_CFG[4] origin:064-gtp-channel-conf 30_90 -GTP_CHANNEL_0.GTPE2.TXDLY_TAP_CFG[5] origin:064-gtp-channel-conf 31_90 -GTP_CHANNEL_0.GTPE2.TXDLY_TAP_CFG[6] origin:064-gtp-channel-conf 30_91 -GTP_CHANNEL_0.GTPE2.TXDLY_TAP_CFG[7] origin:064-gtp-channel-conf 31_91 -GTP_CHANNEL_0.GTPE2.TXDLY_TAP_CFG[8] origin:064-gtp-channel-conf 30_92 -GTP_CHANNEL_0.GTPE2.TXDLY_TAP_CFG[9] origin:064-gtp-channel-conf 31_92 -GTP_CHANNEL_0.GTPE2.TXDLY_TAP_CFG[10] origin:064-gtp-channel-conf 30_93 -GTP_CHANNEL_0.GTPE2.TXDLY_TAP_CFG[11] origin:064-gtp-channel-conf 31_93 -GTP_CHANNEL_0.GTPE2.TXDLY_TAP_CFG[12] origin:064-gtp-channel-conf 30_94 -GTP_CHANNEL_0.GTPE2.TXDLY_TAP_CFG[13] origin:064-gtp-channel-conf 31_94 -GTP_CHANNEL_0.GTPE2.TXDLY_TAP_CFG[14] origin:064-gtp-channel-conf 30_95 -GTP_CHANNEL_0.GTPE2.TXDLY_TAP_CFG[15] origin:064-gtp-channel-conf 31_95 -GTP_CHANNEL_0.GTPE2.TXGEARBOX_EN origin:064-gtp-channel-conf 29_226 -GTP_CHANNEL_0.GTPE2.TXOOB_CFG[0] origin:064-gtp-channel-conf 31_20 -GTP_CHANNEL_0.GTPE2.TXOUT_DIV[0] origin:064-gtp-channel-conf 30_386 -GTP_CHANNEL_0.GTPE2.TXOUT_DIV[1] origin:064-gtp-channel-conf 31_386 -GTP_CHANNEL_0.GTPE2.TXPCSRESET_TIME[0] origin:064-gtp-channel-conf 29_130 -GTP_CHANNEL_0.GTPE2.TXPCSRESET_TIME[1] origin:064-gtp-channel-conf 28_131 -GTP_CHANNEL_0.GTPE2.TXPCSRESET_TIME[2] origin:064-gtp-channel-conf 29_131 -GTP_CHANNEL_0.GTPE2.TXPCSRESET_TIME[3] origin:064-gtp-channel-conf 28_132 -GTP_CHANNEL_0.GTPE2.TXPCSRESET_TIME[4] origin:064-gtp-channel-conf 29_132 -GTP_CHANNEL_0.GTPE2.TXPH_CFG[0] origin:064-gtp-channel-conf 30_96 -GTP_CHANNEL_0.GTPE2.TXPH_CFG[1] origin:064-gtp-channel-conf 31_96 -GTP_CHANNEL_0.GTPE2.TXPH_CFG[2] origin:064-gtp-channel-conf 30_97 -GTP_CHANNEL_0.GTPE2.TXPH_CFG[3] origin:064-gtp-channel-conf 31_97 -GTP_CHANNEL_0.GTPE2.TXPH_CFG[4] origin:064-gtp-channel-conf 30_98 -GTP_CHANNEL_0.GTPE2.TXPH_CFG[5] origin:064-gtp-channel-conf 31_98 -GTP_CHANNEL_0.GTPE2.TXPH_CFG[6] origin:064-gtp-channel-conf 30_99 -GTP_CHANNEL_0.GTPE2.TXPH_CFG[7] origin:064-gtp-channel-conf 31_99 -GTP_CHANNEL_0.GTPE2.TXPH_CFG[8] origin:064-gtp-channel-conf 30_100 -GTP_CHANNEL_0.GTPE2.TXPH_CFG[9] origin:064-gtp-channel-conf 31_100 -GTP_CHANNEL_0.GTPE2.TXPH_CFG[10] origin:064-gtp-channel-conf 30_101 -GTP_CHANNEL_0.GTPE2.TXPH_CFG[11] origin:064-gtp-channel-conf 31_101 -GTP_CHANNEL_0.GTPE2.TXPH_CFG[12] origin:064-gtp-channel-conf 30_102 -GTP_CHANNEL_0.GTPE2.TXPH_CFG[13] origin:064-gtp-channel-conf 31_102 -GTP_CHANNEL_0.GTPE2.TXPH_CFG[14] origin:064-gtp-channel-conf 30_103 -GTP_CHANNEL_0.GTPE2.TXPH_CFG[15] origin:064-gtp-channel-conf 31_103 -GTP_CHANNEL_0.GTPE2.TXPH_MONITOR_SEL[0] origin:064-gtp-channel-conf 30_108 -GTP_CHANNEL_0.GTPE2.TXPH_MONITOR_SEL[1] origin:064-gtp-channel-conf 31_108 -GTP_CHANNEL_0.GTPE2.TXPH_MONITOR_SEL[2] origin:064-gtp-channel-conf 30_109 -GTP_CHANNEL_0.GTPE2.TXPH_MONITOR_SEL[3] origin:064-gtp-channel-conf 31_109 -GTP_CHANNEL_0.GTPE2.TXPH_MONITOR_SEL[4] origin:064-gtp-channel-conf 30_110 -GTP_CHANNEL_0.GTPE2.TXPHDLY_CFG[0] origin:064-gtp-channel-conf 30_64 -GTP_CHANNEL_0.GTPE2.TXPHDLY_CFG[1] origin:064-gtp-channel-conf 31_64 -GTP_CHANNEL_0.GTPE2.TXPHDLY_CFG[2] origin:064-gtp-channel-conf 30_65 -GTP_CHANNEL_0.GTPE2.TXPHDLY_CFG[3] origin:064-gtp-channel-conf 31_65 -GTP_CHANNEL_0.GTPE2.TXPHDLY_CFG[4] origin:064-gtp-channel-conf 30_66 -GTP_CHANNEL_0.GTPE2.TXPHDLY_CFG[5] origin:064-gtp-channel-conf 31_66 -GTP_CHANNEL_0.GTPE2.TXPHDLY_CFG[6] origin:064-gtp-channel-conf 30_67 -GTP_CHANNEL_0.GTPE2.TXPHDLY_CFG[7] origin:064-gtp-channel-conf 31_67 -GTP_CHANNEL_0.GTPE2.TXPHDLY_CFG[8] origin:064-gtp-channel-conf 30_68 -GTP_CHANNEL_0.GTPE2.TXPHDLY_CFG[9] origin:064-gtp-channel-conf 31_68 -GTP_CHANNEL_0.GTPE2.TXPHDLY_CFG[10] origin:064-gtp-channel-conf 30_69 -GTP_CHANNEL_0.GTPE2.TXPHDLY_CFG[11] origin:064-gtp-channel-conf 31_69 -GTP_CHANNEL_0.GTPE2.TXPHDLY_CFG[12] origin:064-gtp-channel-conf 30_70 -GTP_CHANNEL_0.GTPE2.TXPHDLY_CFG[13] origin:064-gtp-channel-conf 31_70 -GTP_CHANNEL_0.GTPE2.TXPHDLY_CFG[14] origin:064-gtp-channel-conf 30_71 -GTP_CHANNEL_0.GTPE2.TXPHDLY_CFG[15] origin:064-gtp-channel-conf 31_71 -GTP_CHANNEL_0.GTPE2.TXPHDLY_CFG[16] origin:064-gtp-channel-conf 30_72 -GTP_CHANNEL_0.GTPE2.TXPHDLY_CFG[17] origin:064-gtp-channel-conf 31_72 -GTP_CHANNEL_0.GTPE2.TXPHDLY_CFG[18] origin:064-gtp-channel-conf 30_73 -GTP_CHANNEL_0.GTPE2.TXPHDLY_CFG[19] origin:064-gtp-channel-conf 31_73 -GTP_CHANNEL_0.GTPE2.TXPHDLY_CFG[20] origin:064-gtp-channel-conf 30_74 -GTP_CHANNEL_0.GTPE2.TXPHDLY_CFG[21] origin:064-gtp-channel-conf 31_74 -GTP_CHANNEL_0.GTPE2.TXPHDLY_CFG[22] origin:064-gtp-channel-conf 30_75 -GTP_CHANNEL_0.GTPE2.TXPHDLY_CFG[23] origin:064-gtp-channel-conf 31_75 -GTP_CHANNEL_0.GTPE2.TXPI_GREY_SEL[0] origin:064-gtp-channel-conf 31_498 -GTP_CHANNEL_0.GTPE2.TXPI_INVSTROBE_SEL[0] origin:064-gtp-channel-conf 30_498 -GTP_CHANNEL_0.GTPE2.TXPI_PPM_CFG[0] origin:064-gtp-channel-conf 30_488 -GTP_CHANNEL_0.GTPE2.TXPI_PPM_CFG[1] origin:064-gtp-channel-conf 31_488 -GTP_CHANNEL_0.GTPE2.TXPI_PPM_CFG[2] origin:064-gtp-channel-conf 30_489 -GTP_CHANNEL_0.GTPE2.TXPI_PPM_CFG[3] origin:064-gtp-channel-conf 31_489 -GTP_CHANNEL_0.GTPE2.TXPI_PPM_CFG[4] origin:064-gtp-channel-conf 30_490 -GTP_CHANNEL_0.GTPE2.TXPI_PPM_CFG[5] origin:064-gtp-channel-conf 31_490 -GTP_CHANNEL_0.GTPE2.TXPI_PPM_CFG[6] origin:064-gtp-channel-conf 30_491 -GTP_CHANNEL_0.GTPE2.TXPI_PPM_CFG[7] origin:064-gtp-channel-conf 31_491 -GTP_CHANNEL_0.GTPE2.TXPI_PPMCLK_SEL.TXUSRCLK2 origin:064-gtp-channel-conf 31_497 -GTP_CHANNEL_0.GTPE2.TXPI_SYNFREQ_PPM[0] origin:064-gtp-channel-conf 30_496 -GTP_CHANNEL_0.GTPE2.TXPI_SYNFREQ_PPM[1] origin:064-gtp-channel-conf 31_496 -GTP_CHANNEL_0.GTPE2.TXPI_SYNFREQ_PPM[2] origin:064-gtp-channel-conf 30_497 -GTP_CHANNEL_0.GTPE2.TXPI_CFG0[0] origin:064-gtp-channel-conf 30_40 -GTP_CHANNEL_0.GTPE2.TXPI_CFG0[1] origin:064-gtp-channel-conf 31_40 -GTP_CHANNEL_0.GTPE2.TXPI_CFG1[0] origin:064-gtp-channel-conf 30_41 -GTP_CHANNEL_0.GTPE2.TXPI_CFG1[1] origin:064-gtp-channel-conf 31_41 -GTP_CHANNEL_0.GTPE2.TXPI_CFG2[0] origin:064-gtp-channel-conf 30_42 -GTP_CHANNEL_0.GTPE2.TXPI_CFG2[1] origin:064-gtp-channel-conf 31_42 -GTP_CHANNEL_0.GTPE2.TXPI_CFG3[0] origin:064-gtp-channel-conf 30_43 -GTP_CHANNEL_0.GTPE2.TXPI_CFG4[0] origin:064-gtp-channel-conf 31_43 -GTP_CHANNEL_0.GTPE2.TXPI_CFG5[0] origin:064-gtp-channel-conf 30_44 -GTP_CHANNEL_0.GTPE2.TXPI_CFG5[1] origin:064-gtp-channel-conf 31_44 -GTP_CHANNEL_0.GTPE2.TXPI_CFG5[2] origin:064-gtp-channel-conf 30_45 -GTP_CHANNEL_0.GTPE2.TXPMARESET_TIME[0] origin:064-gtp-channel-conf 28_128 -GTP_CHANNEL_0.GTPE2.TXPMARESET_TIME[1] origin:064-gtp-channel-conf 29_128 -GTP_CHANNEL_0.GTPE2.TXPMARESET_TIME[2] origin:064-gtp-channel-conf 28_129 -GTP_CHANNEL_0.GTPE2.TXPMARESET_TIME[3] origin:064-gtp-channel-conf 29_129 -GTP_CHANNEL_0.GTPE2.TXPMARESET_TIME[4] origin:064-gtp-channel-conf 28_130 -GTP_CHANNEL_0.GTPE2.TXSYNC_MULTILANE[0] origin:064-gtp-channel-conf 29_133 -GTP_CHANNEL_0.GTPE2.TXSYNC_OVRD[0] origin:064-gtp-channel-conf 28_135 -GTP_CHANNEL_0.GTPE2.TXSYNC_SKIP_DA[0] origin:064-gtp-channel-conf 28_134 -GTP_CHANNEL_0.GTPE2.UCODEER_CLR[0] origin:064-gtp-channel-conf 29_00 -GTP_CHANNEL_0.GTPE2.USE_PCS_CLK_PHASE_SEL[0] origin:064-gtp-channel-conf 30_463 -GTP_CHANNEL_0.GTPE2.ZINV_DMONITORCLK origin:064-gtp-channel-conf 30_13 -GTP_CHANNEL_0.GTPE2.ZINV_DRPCLK origin:064-gtp-channel-conf 30_00 -GTP_CHANNEL_0.GTPE2.ZINV_RXUSRCLK origin:064-gtp-channel-conf 31_01 -GTP_CHANNEL_0.GTPE2.ZINV_SIGVALIDCLK origin:064-gtp-channel-conf 31_13 -GTP_CHANNEL_0.GTPE2.ZINV_TXPHDLYTSTCLK origin:064-gtp-channel-conf 30_03 -GTP_CHANNEL_0.GTPE2.ZINV_TXUSRCLK origin:064-gtp-channel-conf 31_04 -GTP_CHANNEL_0.GTPE2.ZINV_CLKRSVD0 origin:064-gtp-channel-conf 30_23 -GTP_CHANNEL_0.GTPE2.ZINV_CLKRSVD1 origin:064-gtp-channel-conf 31_23 -GTP_CHANNEL_0.GTPE2.ZINV_RXUSRCLK2 origin:064-gtp-channel-conf 30_02 -GTP_CHANNEL_0.GTPE2.ZINV_TXUSRCLK2 origin:064-gtp-channel-conf 30_05 +GTP_CHANNEL_0.GTPE2_CHANNEL.ACJTAG_DEBUG_MODE[0] origin:064-gtp-channel-conf 28_07 +GTP_CHANNEL_0.GTPE2_CHANNEL.ACJTAG_MODE[0] origin:064-gtp-channel-conf 29_06 +GTP_CHANNEL_0.GTPE2_CHANNEL.ACJTAG_RESET[0] origin:064-gtp-channel-conf 29_07 +GTP_CHANNEL_0.GTPE2_CHANNEL.ADAPT_CFG0[0] origin:064-gtp-channel-conf 30_464 +GTP_CHANNEL_0.GTPE2_CHANNEL.ADAPT_CFG0[1] origin:064-gtp-channel-conf 31_464 +GTP_CHANNEL_0.GTPE2_CHANNEL.ADAPT_CFG0[2] origin:064-gtp-channel-conf 30_465 +GTP_CHANNEL_0.GTPE2_CHANNEL.ADAPT_CFG0[3] origin:064-gtp-channel-conf 31_465 +GTP_CHANNEL_0.GTPE2_CHANNEL.ADAPT_CFG0[4] origin:064-gtp-channel-conf 30_466 +GTP_CHANNEL_0.GTPE2_CHANNEL.ADAPT_CFG0[5] origin:064-gtp-channel-conf 31_466 +GTP_CHANNEL_0.GTPE2_CHANNEL.ADAPT_CFG0[6] origin:064-gtp-channel-conf 30_467 +GTP_CHANNEL_0.GTPE2_CHANNEL.ADAPT_CFG0[7] origin:064-gtp-channel-conf 31_467 +GTP_CHANNEL_0.GTPE2_CHANNEL.ADAPT_CFG0[8] origin:064-gtp-channel-conf 30_468 +GTP_CHANNEL_0.GTPE2_CHANNEL.ADAPT_CFG0[9] origin:064-gtp-channel-conf 31_468 +GTP_CHANNEL_0.GTPE2_CHANNEL.ADAPT_CFG0[10] origin:064-gtp-channel-conf 30_469 +GTP_CHANNEL_0.GTPE2_CHANNEL.ADAPT_CFG0[11] origin:064-gtp-channel-conf 31_469 +GTP_CHANNEL_0.GTPE2_CHANNEL.ADAPT_CFG0[12] origin:064-gtp-channel-conf 30_470 +GTP_CHANNEL_0.GTPE2_CHANNEL.ADAPT_CFG0[13] origin:064-gtp-channel-conf 31_470 +GTP_CHANNEL_0.GTPE2_CHANNEL.ADAPT_CFG0[14] origin:064-gtp-channel-conf 30_471 +GTP_CHANNEL_0.GTPE2_CHANNEL.ADAPT_CFG0[15] origin:064-gtp-channel-conf 31_471 +GTP_CHANNEL_0.GTPE2_CHANNEL.ADAPT_CFG0[16] origin:064-gtp-channel-conf 30_472 +GTP_CHANNEL_0.GTPE2_CHANNEL.ADAPT_CFG0[17] origin:064-gtp-channel-conf 31_472 +GTP_CHANNEL_0.GTPE2_CHANNEL.ADAPT_CFG0[18] origin:064-gtp-channel-conf 30_473 +GTP_CHANNEL_0.GTPE2_CHANNEL.ADAPT_CFG0[19] origin:064-gtp-channel-conf 31_473 +GTP_CHANNEL_0.GTPE2_CHANNEL.ALIGN_COMMA_DOUBLE origin:064-gtp-channel-conf 28_522 +GTP_CHANNEL_0.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[0] origin:064-gtp-channel-conf 28_496 +GTP_CHANNEL_0.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[1] origin:064-gtp-channel-conf 29_496 +GTP_CHANNEL_0.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[2] origin:064-gtp-channel-conf 28_497 +GTP_CHANNEL_0.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[3] origin:064-gtp-channel-conf 29_497 +GTP_CHANNEL_0.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[4] origin:064-gtp-channel-conf 28_498 +GTP_CHANNEL_0.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[5] origin:064-gtp-channel-conf 29_498 +GTP_CHANNEL_0.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[6] origin:064-gtp-channel-conf 28_499 +GTP_CHANNEL_0.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[7] origin:064-gtp-channel-conf 29_499 +GTP_CHANNEL_0.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[8] origin:064-gtp-channel-conf 28_500 +GTP_CHANNEL_0.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[9] origin:064-gtp-channel-conf 29_500 +GTP_CHANNEL_0.GTPE2_CHANNEL.ALIGN_COMMA_WORD[0] origin:064-gtp-channel-conf 29_526 +GTP_CHANNEL_0.GTPE2_CHANNEL.ALIGN_COMMA_WORD[1] origin:064-gtp-channel-conf 28_527 +GTP_CHANNEL_0.GTPE2_CHANNEL.ALIGN_MCOMMA_DET origin:064-gtp-channel-conf 28_523 +GTP_CHANNEL_0.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[0] origin:064-gtp-channel-conf 28_504 +GTP_CHANNEL_0.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[1] origin:064-gtp-channel-conf 29_504 +GTP_CHANNEL_0.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[2] origin:064-gtp-channel-conf 28_505 +GTP_CHANNEL_0.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[3] origin:064-gtp-channel-conf 29_505 +GTP_CHANNEL_0.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[4] origin:064-gtp-channel-conf 28_506 +GTP_CHANNEL_0.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[5] origin:064-gtp-channel-conf 29_506 +GTP_CHANNEL_0.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[6] origin:064-gtp-channel-conf 28_507 +GTP_CHANNEL_0.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[7] origin:064-gtp-channel-conf 29_507 +GTP_CHANNEL_0.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[8] origin:064-gtp-channel-conf 28_508 +GTP_CHANNEL_0.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[9] origin:064-gtp-channel-conf 29_508 +GTP_CHANNEL_0.GTPE2_CHANNEL.ALIGN_PCOMMA_DET origin:064-gtp-channel-conf 29_523 +GTP_CHANNEL_0.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[0] origin:064-gtp-channel-conf 28_512 +GTP_CHANNEL_0.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[1] origin:064-gtp-channel-conf 29_512 +GTP_CHANNEL_0.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[2] origin:064-gtp-channel-conf 28_513 +GTP_CHANNEL_0.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[3] origin:064-gtp-channel-conf 29_513 +GTP_CHANNEL_0.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[4] origin:064-gtp-channel-conf 28_514 +GTP_CHANNEL_0.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[5] origin:064-gtp-channel-conf 29_514 +GTP_CHANNEL_0.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[6] origin:064-gtp-channel-conf 28_515 +GTP_CHANNEL_0.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[7] origin:064-gtp-channel-conf 29_515 +GTP_CHANNEL_0.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[8] origin:064-gtp-channel-conf 28_516 +GTP_CHANNEL_0.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[9] origin:064-gtp-channel-conf 29_516 +GTP_CHANNEL_0.GTPE2_CHANNEL.CBCC_DATA_SOURCE_SEL.DECODED origin:064-gtp-channel-conf 29_661 +GTP_CHANNEL_0.GTPE2_CHANNEL.CFOK_CFG[0] origin:064-gtp-channel-conf 30_392 +GTP_CHANNEL_0.GTPE2_CHANNEL.CFOK_CFG[1] origin:064-gtp-channel-conf 31_392 +GTP_CHANNEL_0.GTPE2_CHANNEL.CFOK_CFG[2] origin:064-gtp-channel-conf 30_393 +GTP_CHANNEL_0.GTPE2_CHANNEL.CFOK_CFG[3] origin:064-gtp-channel-conf 31_393 +GTP_CHANNEL_0.GTPE2_CHANNEL.CFOK_CFG[4] origin:064-gtp-channel-conf 30_394 +GTP_CHANNEL_0.GTPE2_CHANNEL.CFOK_CFG[5] origin:064-gtp-channel-conf 31_394 +GTP_CHANNEL_0.GTPE2_CHANNEL.CFOK_CFG[6] origin:064-gtp-channel-conf 30_395 +GTP_CHANNEL_0.GTPE2_CHANNEL.CFOK_CFG[7] origin:064-gtp-channel-conf 31_395 +GTP_CHANNEL_0.GTPE2_CHANNEL.CFOK_CFG[8] origin:064-gtp-channel-conf 30_396 +GTP_CHANNEL_0.GTPE2_CHANNEL.CFOK_CFG[9] origin:064-gtp-channel-conf 31_396 +GTP_CHANNEL_0.GTPE2_CHANNEL.CFOK_CFG[10] origin:064-gtp-channel-conf 30_397 +GTP_CHANNEL_0.GTPE2_CHANNEL.CFOK_CFG[11] origin:064-gtp-channel-conf 31_397 +GTP_CHANNEL_0.GTPE2_CHANNEL.CFOK_CFG[12] origin:064-gtp-channel-conf 30_398 +GTP_CHANNEL_0.GTPE2_CHANNEL.CFOK_CFG[13] origin:064-gtp-channel-conf 31_398 +GTP_CHANNEL_0.GTPE2_CHANNEL.CFOK_CFG[14] origin:064-gtp-channel-conf 30_399 +GTP_CHANNEL_0.GTPE2_CHANNEL.CFOK_CFG[15] origin:064-gtp-channel-conf 31_399 +GTP_CHANNEL_0.GTPE2_CHANNEL.CFOK_CFG[16] origin:064-gtp-channel-conf 30_400 +GTP_CHANNEL_0.GTPE2_CHANNEL.CFOK_CFG[17] origin:064-gtp-channel-conf 31_400 +GTP_CHANNEL_0.GTPE2_CHANNEL.CFOK_CFG[18] origin:064-gtp-channel-conf 30_401 +GTP_CHANNEL_0.GTPE2_CHANNEL.CFOK_CFG[19] origin:064-gtp-channel-conf 31_401 +GTP_CHANNEL_0.GTPE2_CHANNEL.CFOK_CFG[20] origin:064-gtp-channel-conf 30_402 +GTP_CHANNEL_0.GTPE2_CHANNEL.CFOK_CFG[21] origin:064-gtp-channel-conf 31_402 +GTP_CHANNEL_0.GTPE2_CHANNEL.CFOK_CFG[22] origin:064-gtp-channel-conf 30_403 +GTP_CHANNEL_0.GTPE2_CHANNEL.CFOK_CFG[23] origin:064-gtp-channel-conf 31_403 +GTP_CHANNEL_0.GTPE2_CHANNEL.CFOK_CFG[24] origin:064-gtp-channel-conf 30_404 +GTP_CHANNEL_0.GTPE2_CHANNEL.CFOK_CFG[25] origin:064-gtp-channel-conf 31_404 +GTP_CHANNEL_0.GTPE2_CHANNEL.CFOK_CFG[26] origin:064-gtp-channel-conf 30_405 +GTP_CHANNEL_0.GTPE2_CHANNEL.CFOK_CFG[27] origin:064-gtp-channel-conf 31_405 +GTP_CHANNEL_0.GTPE2_CHANNEL.CFOK_CFG[28] origin:064-gtp-channel-conf 30_406 +GTP_CHANNEL_0.GTPE2_CHANNEL.CFOK_CFG[29] origin:064-gtp-channel-conf 31_406 +GTP_CHANNEL_0.GTPE2_CHANNEL.CFOK_CFG[30] origin:064-gtp-channel-conf 30_407 +GTP_CHANNEL_0.GTPE2_CHANNEL.CFOK_CFG[31] origin:064-gtp-channel-conf 31_407 +GTP_CHANNEL_0.GTPE2_CHANNEL.CFOK_CFG[32] origin:064-gtp-channel-conf 30_408 +GTP_CHANNEL_0.GTPE2_CHANNEL.CFOK_CFG[33] origin:064-gtp-channel-conf 31_408 +GTP_CHANNEL_0.GTPE2_CHANNEL.CFOK_CFG[34] origin:064-gtp-channel-conf 30_409 +GTP_CHANNEL_0.GTPE2_CHANNEL.CFOK_CFG[35] origin:064-gtp-channel-conf 31_409 +GTP_CHANNEL_0.GTPE2_CHANNEL.CFOK_CFG[36] origin:064-gtp-channel-conf 30_410 +GTP_CHANNEL_0.GTPE2_CHANNEL.CFOK_CFG[37] origin:064-gtp-channel-conf 31_410 +GTP_CHANNEL_0.GTPE2_CHANNEL.CFOK_CFG[38] origin:064-gtp-channel-conf 30_411 +GTP_CHANNEL_0.GTPE2_CHANNEL.CFOK_CFG[39] origin:064-gtp-channel-conf 31_411 +GTP_CHANNEL_0.GTPE2_CHANNEL.CFOK_CFG[40] origin:064-gtp-channel-conf 30_412 +GTP_CHANNEL_0.GTPE2_CHANNEL.CFOK_CFG[41] origin:064-gtp-channel-conf 31_412 +GTP_CHANNEL_0.GTPE2_CHANNEL.CFOK_CFG[42] origin:064-gtp-channel-conf 30_413 +GTP_CHANNEL_0.GTPE2_CHANNEL.CFOK_CFG2[0] origin:064-gtp-channel-conf 30_459 +GTP_CHANNEL_0.GTPE2_CHANNEL.CFOK_CFG2[1] origin:064-gtp-channel-conf 31_459 +GTP_CHANNEL_0.GTPE2_CHANNEL.CFOK_CFG2[2] origin:064-gtp-channel-conf 30_460 +GTP_CHANNEL_0.GTPE2_CHANNEL.CFOK_CFG2[3] origin:064-gtp-channel-conf 31_460 +GTP_CHANNEL_0.GTPE2_CHANNEL.CFOK_CFG2[4] origin:064-gtp-channel-conf 30_461 +GTP_CHANNEL_0.GTPE2_CHANNEL.CFOK_CFG2[5] origin:064-gtp-channel-conf 31_461 +GTP_CHANNEL_0.GTPE2_CHANNEL.CFOK_CFG2[6] origin:064-gtp-channel-conf 30_462 +GTP_CHANNEL_0.GTPE2_CHANNEL.CFOK_CFG3[0] origin:064-gtp-channel-conf 30_416 +GTP_CHANNEL_0.GTPE2_CHANNEL.CFOK_CFG3[1] origin:064-gtp-channel-conf 31_416 +GTP_CHANNEL_0.GTPE2_CHANNEL.CFOK_CFG3[2] origin:064-gtp-channel-conf 30_417 +GTP_CHANNEL_0.GTPE2_CHANNEL.CFOK_CFG3[3] origin:064-gtp-channel-conf 31_417 +GTP_CHANNEL_0.GTPE2_CHANNEL.CFOK_CFG3[4] origin:064-gtp-channel-conf 30_418 +GTP_CHANNEL_0.GTPE2_CHANNEL.CFOK_CFG3[5] origin:064-gtp-channel-conf 31_418 +GTP_CHANNEL_0.GTPE2_CHANNEL.CFOK_CFG3[6] origin:064-gtp-channel-conf 30_419 +GTP_CHANNEL_0.GTPE2_CHANNEL.CFOK_CFG4[0] origin:064-gtp-channel-conf 31_438 +GTP_CHANNEL_0.GTPE2_CHANNEL.CFOK_CFG5[0] origin:064-gtp-channel-conf 30_429 +GTP_CHANNEL_0.GTPE2_CHANNEL.CFOK_CFG5[1] origin:064-gtp-channel-conf 31_429 +GTP_CHANNEL_0.GTPE2_CHANNEL.CFOK_CFG6[0] origin:064-gtp-channel-conf 31_436 +GTP_CHANNEL_0.GTPE2_CHANNEL.CFOK_CFG6[1] origin:064-gtp-channel-conf 30_437 +GTP_CHANNEL_0.GTPE2_CHANNEL.CFOK_CFG6[2] origin:064-gtp-channel-conf 31_437 +GTP_CHANNEL_0.GTPE2_CHANNEL.CFOK_CFG6[3] origin:064-gtp-channel-conf 30_438 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_KEEP_ALIGN origin:064-gtp-channel-conf 29_631 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_MAX_SKEW[0] origin:064-gtp-channel-conf 28_670 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_MAX_SKEW[1] origin:064-gtp-channel-conf 29_670 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_MAX_SKEW[2] origin:064-gtp-channel-conf 28_671 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_MAX_SKEW[3] origin:064-gtp-channel-conf 29_671 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[0] origin:064-gtp-channel-conf 28_608 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[1] origin:064-gtp-channel-conf 29_608 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[2] origin:064-gtp-channel-conf 28_609 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[3] origin:064-gtp-channel-conf 29_609 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[4] origin:064-gtp-channel-conf 28_610 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[5] origin:064-gtp-channel-conf 29_610 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[6] origin:064-gtp-channel-conf 28_611 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[7] origin:064-gtp-channel-conf 29_611 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[8] origin:064-gtp-channel-conf 28_612 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[9] origin:064-gtp-channel-conf 29_612 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[0] origin:064-gtp-channel-conf 28_616 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[1] origin:064-gtp-channel-conf 29_616 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[2] origin:064-gtp-channel-conf 28_617 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[3] origin:064-gtp-channel-conf 29_617 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[4] origin:064-gtp-channel-conf 28_618 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[5] origin:064-gtp-channel-conf 29_618 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[6] origin:064-gtp-channel-conf 28_619 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[7] origin:064-gtp-channel-conf 29_619 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[8] origin:064-gtp-channel-conf 28_620 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[9] origin:064-gtp-channel-conf 29_620 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[0] origin:064-gtp-channel-conf 28_624 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[1] origin:064-gtp-channel-conf 29_624 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[2] origin:064-gtp-channel-conf 28_625 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[3] origin:064-gtp-channel-conf 29_625 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[4] origin:064-gtp-channel-conf 28_626 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[5] origin:064-gtp-channel-conf 29_626 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[6] origin:064-gtp-channel-conf 28_627 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[7] origin:064-gtp-channel-conf 29_627 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[8] origin:064-gtp-channel-conf 28_628 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[9] origin:064-gtp-channel-conf 29_628 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[0] origin:064-gtp-channel-conf 28_632 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[1] origin:064-gtp-channel-conf 29_632 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[2] origin:064-gtp-channel-conf 28_633 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[3] origin:064-gtp-channel-conf 29_633 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[4] origin:064-gtp-channel-conf 28_634 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[5] origin:064-gtp-channel-conf 29_634 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[6] origin:064-gtp-channel-conf 28_635 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[7] origin:064-gtp-channel-conf 29_635 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[8] origin:064-gtp-channel-conf 28_636 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[9] origin:064-gtp-channel-conf 29_636 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_ENABLE[0] origin:064-gtp-channel-conf 28_614 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_ENABLE[1] origin:064-gtp-channel-conf 29_614 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_ENABLE[2] origin:064-gtp-channel-conf 28_615 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_ENABLE[3] origin:064-gtp-channel-conf 29_615 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[0] origin:064-gtp-channel-conf 28_640 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[1] origin:064-gtp-channel-conf 29_640 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[2] origin:064-gtp-channel-conf 28_641 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[3] origin:064-gtp-channel-conf 29_641 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[4] origin:064-gtp-channel-conf 28_642 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[5] origin:064-gtp-channel-conf 29_642 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[6] origin:064-gtp-channel-conf 28_643 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[7] origin:064-gtp-channel-conf 29_643 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[8] origin:064-gtp-channel-conf 28_644 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[9] origin:064-gtp-channel-conf 29_644 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[0] origin:064-gtp-channel-conf 28_648 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[1] origin:064-gtp-channel-conf 29_648 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[2] origin:064-gtp-channel-conf 28_649 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[3] origin:064-gtp-channel-conf 29_649 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[4] origin:064-gtp-channel-conf 28_650 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[5] origin:064-gtp-channel-conf 29_650 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[6] origin:064-gtp-channel-conf 28_651 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[7] origin:064-gtp-channel-conf 29_651 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[8] origin:064-gtp-channel-conf 28_652 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[9] origin:064-gtp-channel-conf 29_652 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[0] origin:064-gtp-channel-conf 28_656 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[1] origin:064-gtp-channel-conf 29_656 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[2] origin:064-gtp-channel-conf 28_657 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[3] origin:064-gtp-channel-conf 29_657 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[4] origin:064-gtp-channel-conf 28_658 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[5] origin:064-gtp-channel-conf 29_658 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[6] origin:064-gtp-channel-conf 28_659 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[7] origin:064-gtp-channel-conf 29_659 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[8] origin:064-gtp-channel-conf 28_660 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[9] origin:064-gtp-channel-conf 29_660 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[0] origin:064-gtp-channel-conf 28_664 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[1] origin:064-gtp-channel-conf 29_664 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[2] origin:064-gtp-channel-conf 28_665 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[3] origin:064-gtp-channel-conf 29_665 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[4] origin:064-gtp-channel-conf 28_666 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[5] origin:064-gtp-channel-conf 29_666 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[6] origin:064-gtp-channel-conf 28_667 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[7] origin:064-gtp-channel-conf 29_667 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[8] origin:064-gtp-channel-conf 28_668 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[9] origin:064-gtp-channel-conf 29_668 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_ENABLE[0] origin:064-gtp-channel-conf 28_646 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_ENABLE[1] origin:064-gtp-channel-conf 29_646 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_ENABLE[2] origin:064-gtp-channel-conf 28_647 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_ENABLE[3] origin:064-gtp-channel-conf 29_647 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_USE origin:064-gtp-channel-conf 29_645 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_LEN[0] origin:064-gtp-channel-conf 28_623 +GTP_CHANNEL_0.GTPE2_CHANNEL.CHAN_BOND_SEQ_LEN[1] origin:064-gtp-channel-conf 29_623 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COMMON_SWING[0] origin:064-gtp-channel-conf 31_311 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_KEEP_IDLE origin:064-gtp-channel-conf 28_591 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_MAX_LAT[0] origin:064-gtp-channel-conf 28_557 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_MAX_LAT[1] origin:064-gtp-channel-conf 29_557 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_MAX_LAT[2] origin:064-gtp-channel-conf 28_558 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_MAX_LAT[3] origin:064-gtp-channel-conf 29_558 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_MAX_LAT[4] origin:064-gtp-channel-conf 28_559 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_MAX_LAT[5] origin:064-gtp-channel-conf 29_559 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_MIN_LAT[0] origin:064-gtp-channel-conf 28_565 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_MIN_LAT[1] origin:064-gtp-channel-conf 29_565 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_MIN_LAT[2] origin:064-gtp-channel-conf 28_566 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_MIN_LAT[3] origin:064-gtp-channel-conf 29_566 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_MIN_LAT[4] origin:064-gtp-channel-conf 28_567 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_MIN_LAT[5] origin:064-gtp-channel-conf 29_567 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_PRECEDENCE origin:064-gtp-channel-conf 28_590 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_REPEAT_WAIT[0] origin:064-gtp-channel-conf 28_573 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_REPEAT_WAIT[1] origin:064-gtp-channel-conf 29_573 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_REPEAT_WAIT[2] origin:064-gtp-channel-conf 28_574 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_REPEAT_WAIT[3] origin:064-gtp-channel-conf 29_574 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_REPEAT_WAIT[4] origin:064-gtp-channel-conf 28_575 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[0] origin:064-gtp-channel-conf 28_544 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[1] origin:064-gtp-channel-conf 29_544 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[2] origin:064-gtp-channel-conf 28_545 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[3] origin:064-gtp-channel-conf 29_545 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[4] origin:064-gtp-channel-conf 28_546 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[5] origin:064-gtp-channel-conf 29_546 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[6] origin:064-gtp-channel-conf 28_547 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[7] origin:064-gtp-channel-conf 29_547 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[8] origin:064-gtp-channel-conf 28_548 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[9] origin:064-gtp-channel-conf 29_548 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[0] origin:064-gtp-channel-conf 28_552 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[1] origin:064-gtp-channel-conf 29_552 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[2] origin:064-gtp-channel-conf 28_553 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[3] origin:064-gtp-channel-conf 29_553 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[4] origin:064-gtp-channel-conf 28_554 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[5] origin:064-gtp-channel-conf 29_554 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[6] origin:064-gtp-channel-conf 28_555 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[7] origin:064-gtp-channel-conf 29_555 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[8] origin:064-gtp-channel-conf 28_556 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[9] origin:064-gtp-channel-conf 29_556 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[0] origin:064-gtp-channel-conf 28_560 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[1] origin:064-gtp-channel-conf 29_560 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[2] origin:064-gtp-channel-conf 28_561 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[3] origin:064-gtp-channel-conf 29_561 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[4] origin:064-gtp-channel-conf 28_562 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[5] origin:064-gtp-channel-conf 29_562 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[6] origin:064-gtp-channel-conf 28_563 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[7] origin:064-gtp-channel-conf 29_563 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[8] origin:064-gtp-channel-conf 28_564 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[9] origin:064-gtp-channel-conf 29_564 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[0] origin:064-gtp-channel-conf 28_568 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[1] origin:064-gtp-channel-conf 29_568 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[2] origin:064-gtp-channel-conf 28_569 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[3] origin:064-gtp-channel-conf 29_569 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[4] origin:064-gtp-channel-conf 28_570 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[5] origin:064-gtp-channel-conf 29_570 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[6] origin:064-gtp-channel-conf 28_571 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[7] origin:064-gtp-channel-conf 29_571 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[8] origin:064-gtp-channel-conf 28_572 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[9] origin:064-gtp-channel-conf 29_572 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_1_ENABLE[0] origin:064-gtp-channel-conf 28_549 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_1_ENABLE[1] origin:064-gtp-channel-conf 29_549 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_1_ENABLE[2] origin:064-gtp-channel-conf 28_550 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_1_ENABLE[3] origin:064-gtp-channel-conf 29_550 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[0] origin:064-gtp-channel-conf 28_576 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[1] origin:064-gtp-channel-conf 29_576 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[2] origin:064-gtp-channel-conf 28_577 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[3] origin:064-gtp-channel-conf 29_577 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[4] origin:064-gtp-channel-conf 28_578 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[5] origin:064-gtp-channel-conf 29_578 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[6] origin:064-gtp-channel-conf 28_579 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[7] origin:064-gtp-channel-conf 29_579 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[8] origin:064-gtp-channel-conf 28_580 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[9] origin:064-gtp-channel-conf 29_580 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[0] origin:064-gtp-channel-conf 28_584 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[1] origin:064-gtp-channel-conf 29_584 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[2] origin:064-gtp-channel-conf 28_585 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[3] origin:064-gtp-channel-conf 29_585 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[4] origin:064-gtp-channel-conf 28_586 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[5] origin:064-gtp-channel-conf 29_586 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[6] origin:064-gtp-channel-conf 28_587 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[7] origin:064-gtp-channel-conf 29_587 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[8] origin:064-gtp-channel-conf 28_588 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[9] origin:064-gtp-channel-conf 29_588 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[0] origin:064-gtp-channel-conf 28_592 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[1] origin:064-gtp-channel-conf 29_592 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[2] origin:064-gtp-channel-conf 28_593 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[3] origin:064-gtp-channel-conf 29_593 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[4] origin:064-gtp-channel-conf 28_594 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[5] origin:064-gtp-channel-conf 29_594 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[6] origin:064-gtp-channel-conf 28_595 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[7] origin:064-gtp-channel-conf 29_595 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[8] origin:064-gtp-channel-conf 28_596 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[9] origin:064-gtp-channel-conf 29_596 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[0] origin:064-gtp-channel-conf 28_600 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[1] origin:064-gtp-channel-conf 29_600 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[2] origin:064-gtp-channel-conf 28_601 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[3] origin:064-gtp-channel-conf 29_601 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[4] origin:064-gtp-channel-conf 28_602 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[5] origin:064-gtp-channel-conf 29_602 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[6] origin:064-gtp-channel-conf 28_603 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[7] origin:064-gtp-channel-conf 29_603 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[8] origin:064-gtp-channel-conf 28_604 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[9] origin:064-gtp-channel-conf 29_604 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_2_ENABLE[0] origin:064-gtp-channel-conf 28_581 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_2_ENABLE[1] origin:064-gtp-channel-conf 29_581 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_2_ENABLE[2] origin:064-gtp-channel-conf 28_582 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_2_ENABLE[3] origin:064-gtp-channel-conf 29_582 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_2_USE origin:064-gtp-channel-conf 28_583 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_LEN[0] origin:064-gtp-channel-conf 28_589 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_COR_SEQ_LEN[1] origin:064-gtp-channel-conf 29_589 +GTP_CHANNEL_0.GTPE2_CHANNEL.CLK_CORRECT_USE origin:064-gtp-channel-conf 28_551 +GTP_CHANNEL_0.GTPE2_CHANNEL.DEC_MCOMMA_DETECT origin:064-gtp-channel-conf 29_494 +GTP_CHANNEL_0.GTPE2_CHANNEL.DEC_PCOMMA_DETECT origin:064-gtp-channel-conf 28_495 +GTP_CHANNEL_0.GTPE2_CHANNEL.DEC_VALID_COMMA_ONLY origin:064-gtp-channel-conf 28_494 +GTP_CHANNEL_0.GTPE2_CHANNEL.DMONITOR_CFG[0] origin:064-gtp-channel-conf 30_368 +GTP_CHANNEL_0.GTPE2_CHANNEL.DMONITOR_CFG[1] origin:064-gtp-channel-conf 31_368 +GTP_CHANNEL_0.GTPE2_CHANNEL.DMONITOR_CFG[2] origin:064-gtp-channel-conf 30_369 +GTP_CHANNEL_0.GTPE2_CHANNEL.DMONITOR_CFG[3] origin:064-gtp-channel-conf 31_369 +GTP_CHANNEL_0.GTPE2_CHANNEL.DMONITOR_CFG[4] origin:064-gtp-channel-conf 30_370 +GTP_CHANNEL_0.GTPE2_CHANNEL.DMONITOR_CFG[5] origin:064-gtp-channel-conf 31_370 +GTP_CHANNEL_0.GTPE2_CHANNEL.DMONITOR_CFG[6] origin:064-gtp-channel-conf 30_371 +GTP_CHANNEL_0.GTPE2_CHANNEL.DMONITOR_CFG[7] origin:064-gtp-channel-conf 31_371 +GTP_CHANNEL_0.GTPE2_CHANNEL.DMONITOR_CFG[8] origin:064-gtp-channel-conf 30_372 +GTP_CHANNEL_0.GTPE2_CHANNEL.DMONITOR_CFG[9] origin:064-gtp-channel-conf 31_372 +GTP_CHANNEL_0.GTPE2_CHANNEL.DMONITOR_CFG[10] origin:064-gtp-channel-conf 30_373 +GTP_CHANNEL_0.GTPE2_CHANNEL.DMONITOR_CFG[11] origin:064-gtp-channel-conf 31_373 +GTP_CHANNEL_0.GTPE2_CHANNEL.DMONITOR_CFG[12] origin:064-gtp-channel-conf 30_374 +GTP_CHANNEL_0.GTPE2_CHANNEL.DMONITOR_CFG[13] origin:064-gtp-channel-conf 31_374 +GTP_CHANNEL_0.GTPE2_CHANNEL.DMONITOR_CFG[14] origin:064-gtp-channel-conf 30_375 +GTP_CHANNEL_0.GTPE2_CHANNEL.DMONITOR_CFG[15] origin:064-gtp-channel-conf 31_375 +GTP_CHANNEL_0.GTPE2_CHANNEL.DMONITOR_CFG[16] origin:064-gtp-channel-conf 30_376 +GTP_CHANNEL_0.GTPE2_CHANNEL.DMONITOR_CFG[17] origin:064-gtp-channel-conf 31_376 +GTP_CHANNEL_0.GTPE2_CHANNEL.DMONITOR_CFG[18] origin:064-gtp-channel-conf 30_377 +GTP_CHANNEL_0.GTPE2_CHANNEL.DMONITOR_CFG[19] origin:064-gtp-channel-conf 31_377 +GTP_CHANNEL_0.GTPE2_CHANNEL.DMONITOR_CFG[20] origin:064-gtp-channel-conf 30_378 +GTP_CHANNEL_0.GTPE2_CHANNEL.DMONITOR_CFG[21] origin:064-gtp-channel-conf 31_378 +GTP_CHANNEL_0.GTPE2_CHANNEL.DMONITOR_CFG[22] origin:064-gtp-channel-conf 30_379 +GTP_CHANNEL_0.GTPE2_CHANNEL.DMONITOR_CFG[23] origin:064-gtp-channel-conf 31_379 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_CLK_PHASE_SEL[0] origin:064-gtp-channel-conf 31_463 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_CONTROL[0] origin:064-gtp-channel-conf 28_488 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_CONTROL[1] origin:064-gtp-channel-conf 29_488 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_CONTROL[2] origin:064-gtp-channel-conf 28_489 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_CONTROL[3] origin:064-gtp-channel-conf 29_489 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_CONTROL[4] origin:064-gtp-channel-conf 28_490 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_CONTROL[5] origin:064-gtp-channel-conf 29_490 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_ERRDET_EN origin:064-gtp-channel-conf 29_492 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_EYE_SCAN_EN origin:064-gtp-channel-conf 28_492 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_HORZ_OFFSET[0] origin:064-gtp-channel-conf 28_480 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_HORZ_OFFSET[1] origin:064-gtp-channel-conf 29_480 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_HORZ_OFFSET[2] origin:064-gtp-channel-conf 28_481 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_HORZ_OFFSET[3] origin:064-gtp-channel-conf 29_481 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_HORZ_OFFSET[4] origin:064-gtp-channel-conf 28_482 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_HORZ_OFFSET[5] origin:064-gtp-channel-conf 29_482 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_HORZ_OFFSET[6] origin:064-gtp-channel-conf 28_483 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_HORZ_OFFSET[7] origin:064-gtp-channel-conf 29_483 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_HORZ_OFFSET[8] origin:064-gtp-channel-conf 28_484 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_HORZ_OFFSET[9] origin:064-gtp-channel-conf 29_484 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_HORZ_OFFSET[10] origin:064-gtp-channel-conf 28_485 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_HORZ_OFFSET[11] origin:064-gtp-channel-conf 29_485 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_PMA_CFG[0] origin:064-gtp-channel-conf 30_624 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_PMA_CFG[1] origin:064-gtp-channel-conf 31_624 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_PMA_CFG[2] origin:064-gtp-channel-conf 30_625 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_PMA_CFG[3] origin:064-gtp-channel-conf 31_625 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_PMA_CFG[4] origin:064-gtp-channel-conf 30_626 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_PMA_CFG[5] origin:064-gtp-channel-conf 31_626 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_PMA_CFG[6] origin:064-gtp-channel-conf 30_627 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_PMA_CFG[7] origin:064-gtp-channel-conf 31_627 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_PMA_CFG[8] origin:064-gtp-channel-conf 30_628 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_PMA_CFG[9] origin:064-gtp-channel-conf 31_628 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_PRESCALE[0] origin:064-gtp-channel-conf 29_477 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_PRESCALE[1] origin:064-gtp-channel-conf 28_478 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_PRESCALE[2] origin:064-gtp-channel-conf 29_478 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_PRESCALE[3] origin:064-gtp-channel-conf 28_479 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_PRESCALE[4] origin:064-gtp-channel-conf 29_479 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[0] origin:064-gtp-channel-conf 28_392 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[1] origin:064-gtp-channel-conf 29_392 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[2] origin:064-gtp-channel-conf 28_393 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[3] origin:064-gtp-channel-conf 29_393 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[4] origin:064-gtp-channel-conf 28_394 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[5] origin:064-gtp-channel-conf 29_394 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[6] origin:064-gtp-channel-conf 28_395 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[7] origin:064-gtp-channel-conf 29_395 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[8] origin:064-gtp-channel-conf 28_396 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[9] origin:064-gtp-channel-conf 29_396 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[10] origin:064-gtp-channel-conf 28_397 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[11] origin:064-gtp-channel-conf 29_397 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[12] origin:064-gtp-channel-conf 28_398 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[13] origin:064-gtp-channel-conf 29_398 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[14] origin:064-gtp-channel-conf 28_399 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[15] origin:064-gtp-channel-conf 29_399 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[16] origin:064-gtp-channel-conf 28_400 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[17] origin:064-gtp-channel-conf 29_400 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[18] origin:064-gtp-channel-conf 28_401 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[19] origin:064-gtp-channel-conf 29_401 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[20] origin:064-gtp-channel-conf 28_402 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[21] origin:064-gtp-channel-conf 29_402 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[22] origin:064-gtp-channel-conf 28_403 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[23] origin:064-gtp-channel-conf 29_403 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[24] origin:064-gtp-channel-conf 28_404 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[25] origin:064-gtp-channel-conf 29_404 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[26] origin:064-gtp-channel-conf 28_405 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[27] origin:064-gtp-channel-conf 29_405 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[28] origin:064-gtp-channel-conf 28_406 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[29] origin:064-gtp-channel-conf 29_406 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[30] origin:064-gtp-channel-conf 28_407 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[31] origin:064-gtp-channel-conf 29_407 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[32] origin:064-gtp-channel-conf 28_408 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[33] origin:064-gtp-channel-conf 29_408 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[34] origin:064-gtp-channel-conf 28_409 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[35] origin:064-gtp-channel-conf 29_409 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[36] origin:064-gtp-channel-conf 28_410 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[37] origin:064-gtp-channel-conf 29_410 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[38] origin:064-gtp-channel-conf 28_411 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[39] origin:064-gtp-channel-conf 29_411 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[40] origin:064-gtp-channel-conf 28_412 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[41] origin:064-gtp-channel-conf 29_412 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[42] origin:064-gtp-channel-conf 28_413 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[43] origin:064-gtp-channel-conf 29_413 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[44] origin:064-gtp-channel-conf 28_414 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[45] origin:064-gtp-channel-conf 29_414 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[46] origin:064-gtp-channel-conf 28_415 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[47] origin:064-gtp-channel-conf 29_415 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[48] origin:064-gtp-channel-conf 28_416 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[49] origin:064-gtp-channel-conf 29_416 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[50] origin:064-gtp-channel-conf 28_417 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[51] origin:064-gtp-channel-conf 29_417 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[52] origin:064-gtp-channel-conf 28_418 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[53] origin:064-gtp-channel-conf 29_418 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[54] origin:064-gtp-channel-conf 28_419 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[55] origin:064-gtp-channel-conf 29_419 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[56] origin:064-gtp-channel-conf 28_420 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[57] origin:064-gtp-channel-conf 29_420 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[58] origin:064-gtp-channel-conf 28_421 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[59] origin:064-gtp-channel-conf 29_421 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[60] origin:064-gtp-channel-conf 28_422 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[61] origin:064-gtp-channel-conf 29_422 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[62] origin:064-gtp-channel-conf 28_423 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[63] origin:064-gtp-channel-conf 29_423 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[64] origin:064-gtp-channel-conf 28_424 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[65] origin:064-gtp-channel-conf 29_424 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[66] origin:064-gtp-channel-conf 28_425 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[67] origin:064-gtp-channel-conf 29_425 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[68] origin:064-gtp-channel-conf 28_426 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[69] origin:064-gtp-channel-conf 29_426 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[70] origin:064-gtp-channel-conf 28_427 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[71] origin:064-gtp-channel-conf 29_427 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[72] origin:064-gtp-channel-conf 28_428 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[73] origin:064-gtp-channel-conf 29_428 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[74] origin:064-gtp-channel-conf 28_429 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[75] origin:064-gtp-channel-conf 29_429 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[76] origin:064-gtp-channel-conf 28_430 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[77] origin:064-gtp-channel-conf 29_430 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[78] origin:064-gtp-channel-conf 28_431 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUAL_MASK[79] origin:064-gtp-channel-conf 29_431 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[0] origin:064-gtp-channel-conf 28_352 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[1] origin:064-gtp-channel-conf 29_352 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[2] origin:064-gtp-channel-conf 28_353 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[3] origin:064-gtp-channel-conf 29_353 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[4] origin:064-gtp-channel-conf 28_354 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[5] origin:064-gtp-channel-conf 29_354 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[6] origin:064-gtp-channel-conf 28_355 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[7] origin:064-gtp-channel-conf 29_355 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[8] origin:064-gtp-channel-conf 28_356 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[9] origin:064-gtp-channel-conf 29_356 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[10] origin:064-gtp-channel-conf 28_357 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[11] origin:064-gtp-channel-conf 29_357 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[12] origin:064-gtp-channel-conf 28_358 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[13] origin:064-gtp-channel-conf 29_358 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[14] origin:064-gtp-channel-conf 28_359 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[15] origin:064-gtp-channel-conf 29_359 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[16] origin:064-gtp-channel-conf 28_360 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[17] origin:064-gtp-channel-conf 29_360 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[18] origin:064-gtp-channel-conf 28_361 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[19] origin:064-gtp-channel-conf 29_361 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[20] origin:064-gtp-channel-conf 28_362 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[21] origin:064-gtp-channel-conf 29_362 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[22] origin:064-gtp-channel-conf 28_363 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[23] origin:064-gtp-channel-conf 29_363 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[24] origin:064-gtp-channel-conf 28_364 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[25] origin:064-gtp-channel-conf 29_364 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[26] origin:064-gtp-channel-conf 28_365 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[27] origin:064-gtp-channel-conf 29_365 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[28] origin:064-gtp-channel-conf 28_366 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[29] origin:064-gtp-channel-conf 29_366 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[30] origin:064-gtp-channel-conf 28_367 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[31] origin:064-gtp-channel-conf 29_367 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[32] origin:064-gtp-channel-conf 28_368 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[33] origin:064-gtp-channel-conf 29_368 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[34] origin:064-gtp-channel-conf 28_369 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[35] origin:064-gtp-channel-conf 29_369 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[36] origin:064-gtp-channel-conf 28_370 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[37] origin:064-gtp-channel-conf 29_370 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[38] origin:064-gtp-channel-conf 28_371 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[39] origin:064-gtp-channel-conf 29_371 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[40] origin:064-gtp-channel-conf 28_372 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[41] origin:064-gtp-channel-conf 29_372 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[42] origin:064-gtp-channel-conf 28_373 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[43] origin:064-gtp-channel-conf 29_373 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[44] origin:064-gtp-channel-conf 28_374 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[45] origin:064-gtp-channel-conf 29_374 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[46] origin:064-gtp-channel-conf 28_375 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[47] origin:064-gtp-channel-conf 29_375 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[48] origin:064-gtp-channel-conf 28_376 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[49] origin:064-gtp-channel-conf 29_376 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[50] origin:064-gtp-channel-conf 28_377 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[51] origin:064-gtp-channel-conf 29_377 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[52] origin:064-gtp-channel-conf 28_378 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[53] origin:064-gtp-channel-conf 29_378 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[54] origin:064-gtp-channel-conf 28_379 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[55] origin:064-gtp-channel-conf 29_379 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[56] origin:064-gtp-channel-conf 28_380 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[57] origin:064-gtp-channel-conf 29_380 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[58] origin:064-gtp-channel-conf 28_381 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[59] origin:064-gtp-channel-conf 29_381 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[60] origin:064-gtp-channel-conf 28_382 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[61] origin:064-gtp-channel-conf 29_382 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[62] origin:064-gtp-channel-conf 28_383 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[63] origin:064-gtp-channel-conf 29_383 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[64] origin:064-gtp-channel-conf 28_384 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[65] origin:064-gtp-channel-conf 29_384 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[66] origin:064-gtp-channel-conf 28_385 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[67] origin:064-gtp-channel-conf 29_385 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[68] origin:064-gtp-channel-conf 28_386 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[69] origin:064-gtp-channel-conf 29_386 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[70] origin:064-gtp-channel-conf 28_387 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[71] origin:064-gtp-channel-conf 29_387 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[72] origin:064-gtp-channel-conf 28_388 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[73] origin:064-gtp-channel-conf 29_388 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[74] origin:064-gtp-channel-conf 28_389 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[75] origin:064-gtp-channel-conf 29_389 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[76] origin:064-gtp-channel-conf 28_390 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[77] origin:064-gtp-channel-conf 29_390 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[78] origin:064-gtp-channel-conf 28_391 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_QUALIFIER[79] origin:064-gtp-channel-conf 29_391 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[0] origin:064-gtp-channel-conf 28_432 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[1] origin:064-gtp-channel-conf 29_432 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[2] origin:064-gtp-channel-conf 28_433 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[3] origin:064-gtp-channel-conf 29_433 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[4] origin:064-gtp-channel-conf 28_434 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[5] origin:064-gtp-channel-conf 29_434 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[6] origin:064-gtp-channel-conf 28_435 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[7] origin:064-gtp-channel-conf 29_435 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[8] origin:064-gtp-channel-conf 28_436 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[9] origin:064-gtp-channel-conf 29_436 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[10] origin:064-gtp-channel-conf 28_437 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[11] origin:064-gtp-channel-conf 29_437 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[12] origin:064-gtp-channel-conf 28_438 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[13] origin:064-gtp-channel-conf 29_438 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[14] origin:064-gtp-channel-conf 28_439 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[15] origin:064-gtp-channel-conf 29_439 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[16] origin:064-gtp-channel-conf 28_440 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[17] origin:064-gtp-channel-conf 29_440 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[18] origin:064-gtp-channel-conf 28_441 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[19] origin:064-gtp-channel-conf 29_441 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[20] origin:064-gtp-channel-conf 28_442 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[21] origin:064-gtp-channel-conf 29_442 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[22] origin:064-gtp-channel-conf 28_443 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[23] origin:064-gtp-channel-conf 29_443 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[24] origin:064-gtp-channel-conf 28_444 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[25] origin:064-gtp-channel-conf 29_444 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[26] origin:064-gtp-channel-conf 28_445 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[27] origin:064-gtp-channel-conf 29_445 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[28] origin:064-gtp-channel-conf 28_446 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[29] origin:064-gtp-channel-conf 29_446 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[30] origin:064-gtp-channel-conf 28_447 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[31] origin:064-gtp-channel-conf 29_447 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[32] origin:064-gtp-channel-conf 28_448 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[33] origin:064-gtp-channel-conf 29_448 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[34] origin:064-gtp-channel-conf 28_449 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[35] origin:064-gtp-channel-conf 29_449 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[36] origin:064-gtp-channel-conf 28_450 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[37] origin:064-gtp-channel-conf 29_450 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[38] origin:064-gtp-channel-conf 28_451 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[39] origin:064-gtp-channel-conf 29_451 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[40] origin:064-gtp-channel-conf 28_452 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[41] origin:064-gtp-channel-conf 29_452 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[42] origin:064-gtp-channel-conf 28_453 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[43] origin:064-gtp-channel-conf 29_453 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[44] origin:064-gtp-channel-conf 28_454 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[45] origin:064-gtp-channel-conf 29_454 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[46] origin:064-gtp-channel-conf 28_455 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[47] origin:064-gtp-channel-conf 29_455 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[48] origin:064-gtp-channel-conf 28_456 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[49] origin:064-gtp-channel-conf 29_456 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[50] origin:064-gtp-channel-conf 28_457 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[51] origin:064-gtp-channel-conf 29_457 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[52] origin:064-gtp-channel-conf 28_458 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[53] origin:064-gtp-channel-conf 29_458 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[54] origin:064-gtp-channel-conf 28_459 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[55] origin:064-gtp-channel-conf 29_459 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[56] origin:064-gtp-channel-conf 28_460 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[57] origin:064-gtp-channel-conf 29_460 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[58] origin:064-gtp-channel-conf 28_461 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[59] origin:064-gtp-channel-conf 29_461 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[60] origin:064-gtp-channel-conf 28_462 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[61] origin:064-gtp-channel-conf 29_462 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[62] origin:064-gtp-channel-conf 28_463 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[63] origin:064-gtp-channel-conf 29_463 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[64] origin:064-gtp-channel-conf 28_464 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[65] origin:064-gtp-channel-conf 29_464 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[66] origin:064-gtp-channel-conf 28_465 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[67] origin:064-gtp-channel-conf 29_465 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[68] origin:064-gtp-channel-conf 28_466 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[69] origin:064-gtp-channel-conf 29_466 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[70] origin:064-gtp-channel-conf 28_467 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[71] origin:064-gtp-channel-conf 29_467 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[72] origin:064-gtp-channel-conf 28_468 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[73] origin:064-gtp-channel-conf 29_468 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[74] origin:064-gtp-channel-conf 28_469 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[75] origin:064-gtp-channel-conf 29_469 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[76] origin:064-gtp-channel-conf 28_470 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[77] origin:064-gtp-channel-conf 29_470 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[78] origin:064-gtp-channel-conf 28_471 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_SDATA_MASK[79] origin:064-gtp-channel-conf 29_471 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_VERT_OFFSET[0] origin:064-gtp-channel-conf 28_472 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_VERT_OFFSET[1] origin:064-gtp-channel-conf 29_472 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_VERT_OFFSET[2] origin:064-gtp-channel-conf 28_473 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_VERT_OFFSET[3] origin:064-gtp-channel-conf 29_473 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_VERT_OFFSET[4] origin:064-gtp-channel-conf 28_474 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_VERT_OFFSET[5] origin:064-gtp-channel-conf 29_474 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_VERT_OFFSET[6] origin:064-gtp-channel-conf 28_475 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_VERT_OFFSET[7] origin:064-gtp-channel-conf 29_475 +GTP_CHANNEL_0.GTPE2_CHANNEL.ES_VERT_OFFSET[8] origin:064-gtp-channel-conf 28_476 +GTP_CHANNEL_0.GTPE2_CHANNEL.FTS_DESKEW_SEQ_ENABLE[0] origin:064-gtp-channel-conf 28_662 +GTP_CHANNEL_0.GTPE2_CHANNEL.FTS_DESKEW_SEQ_ENABLE[1] origin:064-gtp-channel-conf 29_662 +GTP_CHANNEL_0.GTPE2_CHANNEL.FTS_DESKEW_SEQ_ENABLE[2] origin:064-gtp-channel-conf 28_663 +GTP_CHANNEL_0.GTPE2_CHANNEL.FTS_DESKEW_SEQ_ENABLE[3] origin:064-gtp-channel-conf 29_663 +GTP_CHANNEL_0.GTPE2_CHANNEL.FTS_LANE_DESKEW_CFG[0] origin:064-gtp-channel-conf 28_654 +GTP_CHANNEL_0.GTPE2_CHANNEL.FTS_LANE_DESKEW_CFG[1] origin:064-gtp-channel-conf 29_654 +GTP_CHANNEL_0.GTPE2_CHANNEL.FTS_LANE_DESKEW_CFG[2] origin:064-gtp-channel-conf 28_655 +GTP_CHANNEL_0.GTPE2_CHANNEL.FTS_LANE_DESKEW_CFG[3] origin:064-gtp-channel-conf 29_655 +GTP_CHANNEL_0.GTPE2_CHANNEL.FTS_LANE_DESKEW_EN origin:064-gtp-channel-conf 29_653 +GTP_CHANNEL_0.GTPE2_CHANNEL.GEARBOX_MODE[0] origin:064-gtp-channel-conf 28_224 +GTP_CHANNEL_0.GTPE2_CHANNEL.GEARBOX_MODE[1] origin:064-gtp-channel-conf 29_224 +GTP_CHANNEL_0.GTPE2_CHANNEL.GEARBOX_MODE[2] origin:064-gtp-channel-conf 28_225 +GTP_CHANNEL_0.GTPE2_CHANNEL.IN_USE origin:064-gtp-channel-conf 28_00 28_01 28_47 28_52 28_53 28_65 29_01 29_47 30_129 +GTP_CHANNEL_0.GTPE2_CHANNEL.INV_DMONITORCLK origin:064-gtp-channel-conf 30_13 +GTP_CHANNEL_0.GTPE2_CHANNEL.INV_DRPCLK origin:064-gtp-channel-conf 30_00 +GTP_CHANNEL_0.GTPE2_CHANNEL.INV_RXUSRCLK origin:064-gtp-channel-conf 31_01 +GTP_CHANNEL_0.GTPE2_CHANNEL.INV_SIGVALIDCLK origin:064-gtp-channel-conf 31_13 +GTP_CHANNEL_0.GTPE2_CHANNEL.INV_TXPHDLYTSTCLK origin:064-gtp-channel-conf 30_03 +GTP_CHANNEL_0.GTPE2_CHANNEL.INV_TXUSRCLK origin:064-gtp-channel-conf 31_04 +GTP_CHANNEL_0.GTPE2_CHANNEL.INV_CLKRSVD0 origin:064-gtp-channel-conf 30_23 +GTP_CHANNEL_0.GTPE2_CHANNEL.INV_CLKRSVD1 origin:064-gtp-channel-conf 31_23 +GTP_CHANNEL_0.GTPE2_CHANNEL.INV_RXUSRCLK2 origin:064-gtp-channel-conf 30_02 +GTP_CHANNEL_0.GTPE2_CHANNEL.INV_TXUSRCLK2 origin:064-gtp-channel-conf 30_05 +GTP_CHANNEL_0.GTPE2_CHANNEL.LOOPBACK_CFG[0] origin:064-gtp-channel-conf 30_20 +GTP_CHANNEL_0.GTPE2_CHANNEL.OUTREFCLK_SEL_INV[0] origin:064-gtp-channel-conf 28_149 +GTP_CHANNEL_0.GTPE2_CHANNEL.OUTREFCLK_SEL_INV[1] origin:064-gtp-channel-conf 29_149 +GTP_CHANNEL_0.GTPE2_CHANNEL.PCS_PCIE_EN origin:064-gtp-channel-conf 28_216 +GTP_CHANNEL_0.GTPE2_CHANNEL.PCS_RSVD_ATTR[0] origin:064-gtp-channel-conf 30_184 +GTP_CHANNEL_0.GTPE2_CHANNEL.PCS_RSVD_ATTR[1] origin:064-gtp-channel-conf 31_184 +GTP_CHANNEL_0.GTPE2_CHANNEL.PCS_RSVD_ATTR[2] origin:064-gtp-channel-conf 30_185 +GTP_CHANNEL_0.GTPE2_CHANNEL.PCS_RSVD_ATTR[3] origin:064-gtp-channel-conf 31_185 +GTP_CHANNEL_0.GTPE2_CHANNEL.PCS_RSVD_ATTR[4] origin:064-gtp-channel-conf 30_186 +GTP_CHANNEL_0.GTPE2_CHANNEL.PCS_RSVD_ATTR[5] origin:064-gtp-channel-conf 31_186 +GTP_CHANNEL_0.GTPE2_CHANNEL.PCS_RSVD_ATTR[6] origin:064-gtp-channel-conf 30_187 +GTP_CHANNEL_0.GTPE2_CHANNEL.PCS_RSVD_ATTR[7] origin:064-gtp-channel-conf 31_187 +GTP_CHANNEL_0.GTPE2_CHANNEL.PCS_RSVD_ATTR[8] origin:064-gtp-channel-conf 30_188 +GTP_CHANNEL_0.GTPE2_CHANNEL.PCS_RSVD_ATTR[9] origin:064-gtp-channel-conf 31_188 +GTP_CHANNEL_0.GTPE2_CHANNEL.PCS_RSVD_ATTR[10] origin:064-gtp-channel-conf 30_189 +GTP_CHANNEL_0.GTPE2_CHANNEL.PCS_RSVD_ATTR[11] origin:064-gtp-channel-conf 31_189 +GTP_CHANNEL_0.GTPE2_CHANNEL.PCS_RSVD_ATTR[12] origin:064-gtp-channel-conf 30_190 +GTP_CHANNEL_0.GTPE2_CHANNEL.PCS_RSVD_ATTR[13] origin:064-gtp-channel-conf 31_190 +GTP_CHANNEL_0.GTPE2_CHANNEL.PCS_RSVD_ATTR[14] origin:064-gtp-channel-conf 30_191 +GTP_CHANNEL_0.GTPE2_CHANNEL.PCS_RSVD_ATTR[15] origin:064-gtp-channel-conf 31_191 +GTP_CHANNEL_0.GTPE2_CHANNEL.PCS_RSVD_ATTR[16] origin:064-gtp-channel-conf 30_192 +GTP_CHANNEL_0.GTPE2_CHANNEL.PCS_RSVD_ATTR[17] origin:064-gtp-channel-conf 31_192 +GTP_CHANNEL_0.GTPE2_CHANNEL.PCS_RSVD_ATTR[18] origin:064-gtp-channel-conf 30_193 +GTP_CHANNEL_0.GTPE2_CHANNEL.PCS_RSVD_ATTR[19] origin:064-gtp-channel-conf 31_193 +GTP_CHANNEL_0.GTPE2_CHANNEL.PCS_RSVD_ATTR[20] origin:064-gtp-channel-conf 30_194 +GTP_CHANNEL_0.GTPE2_CHANNEL.PCS_RSVD_ATTR[21] origin:064-gtp-channel-conf 31_194 +GTP_CHANNEL_0.GTPE2_CHANNEL.PCS_RSVD_ATTR[22] origin:064-gtp-channel-conf 30_195 +GTP_CHANNEL_0.GTPE2_CHANNEL.PCS_RSVD_ATTR[23] origin:064-gtp-channel-conf 31_195 +GTP_CHANNEL_0.GTPE2_CHANNEL.PCS_RSVD_ATTR[24] origin:064-gtp-channel-conf 30_196 +GTP_CHANNEL_0.GTPE2_CHANNEL.PCS_RSVD_ATTR[25] origin:064-gtp-channel-conf 31_196 +GTP_CHANNEL_0.GTPE2_CHANNEL.PCS_RSVD_ATTR[26] origin:064-gtp-channel-conf 30_197 +GTP_CHANNEL_0.GTPE2_CHANNEL.PCS_RSVD_ATTR[27] origin:064-gtp-channel-conf 31_197 +GTP_CHANNEL_0.GTPE2_CHANNEL.PCS_RSVD_ATTR[28] origin:064-gtp-channel-conf 30_198 +GTP_CHANNEL_0.GTPE2_CHANNEL.PCS_RSVD_ATTR[29] origin:064-gtp-channel-conf 31_198 +GTP_CHANNEL_0.GTPE2_CHANNEL.PCS_RSVD_ATTR[30] origin:064-gtp-channel-conf 30_199 +GTP_CHANNEL_0.GTPE2_CHANNEL.PCS_RSVD_ATTR[31] origin:064-gtp-channel-conf 31_199 +GTP_CHANNEL_0.GTPE2_CHANNEL.PCS_RSVD_ATTR[32] origin:064-gtp-channel-conf 30_200 +GTP_CHANNEL_0.GTPE2_CHANNEL.PCS_RSVD_ATTR[33] origin:064-gtp-channel-conf 31_200 +GTP_CHANNEL_0.GTPE2_CHANNEL.PCS_RSVD_ATTR[34] origin:064-gtp-channel-conf 30_201 +GTP_CHANNEL_0.GTPE2_CHANNEL.PCS_RSVD_ATTR[35] origin:064-gtp-channel-conf 31_201 +GTP_CHANNEL_0.GTPE2_CHANNEL.PCS_RSVD_ATTR[36] origin:064-gtp-channel-conf 30_202 +GTP_CHANNEL_0.GTPE2_CHANNEL.PCS_RSVD_ATTR[37] origin:064-gtp-channel-conf 31_202 +GTP_CHANNEL_0.GTPE2_CHANNEL.PCS_RSVD_ATTR[38] origin:064-gtp-channel-conf 30_203 +GTP_CHANNEL_0.GTPE2_CHANNEL.PCS_RSVD_ATTR[39] origin:064-gtp-channel-conf 31_203 +GTP_CHANNEL_0.GTPE2_CHANNEL.PCS_RSVD_ATTR[40] origin:064-gtp-channel-conf 30_204 +GTP_CHANNEL_0.GTPE2_CHANNEL.PCS_RSVD_ATTR[41] origin:064-gtp-channel-conf 31_204 +GTP_CHANNEL_0.GTPE2_CHANNEL.PCS_RSVD_ATTR[42] origin:064-gtp-channel-conf 30_205 +GTP_CHANNEL_0.GTPE2_CHANNEL.PCS_RSVD_ATTR[43] origin:064-gtp-channel-conf 31_205 +GTP_CHANNEL_0.GTPE2_CHANNEL.PCS_RSVD_ATTR[44] origin:064-gtp-channel-conf 30_206 +GTP_CHANNEL_0.GTPE2_CHANNEL.PCS_RSVD_ATTR[45] origin:064-gtp-channel-conf 31_206 +GTP_CHANNEL_0.GTPE2_CHANNEL.PCS_RSVD_ATTR[46] origin:064-gtp-channel-conf 30_207 +GTP_CHANNEL_0.GTPE2_CHANNEL.PCS_RSVD_ATTR[47] origin:064-gtp-channel-conf 31_207 +GTP_CHANNEL_0.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[0] origin:064-gtp-channel-conf 29_216 +GTP_CHANNEL_0.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[1] origin:064-gtp-channel-conf 28_217 +GTP_CHANNEL_0.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[2] origin:064-gtp-channel-conf 29_217 +GTP_CHANNEL_0.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[3] origin:064-gtp-channel-conf 28_218 +GTP_CHANNEL_0.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[4] origin:064-gtp-channel-conf 29_218 +GTP_CHANNEL_0.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[5] origin:064-gtp-channel-conf 28_219 +GTP_CHANNEL_0.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[6] origin:064-gtp-channel-conf 29_219 +GTP_CHANNEL_0.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[7] origin:064-gtp-channel-conf 28_220 +GTP_CHANNEL_0.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[8] origin:064-gtp-channel-conf 29_220 +GTP_CHANNEL_0.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[9] origin:064-gtp-channel-conf 28_221 +GTP_CHANNEL_0.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[10] origin:064-gtp-channel-conf 29_221 +GTP_CHANNEL_0.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[11] origin:064-gtp-channel-conf 28_222 +GTP_CHANNEL_0.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[0] origin:064-gtp-channel-conf 28_208 +GTP_CHANNEL_0.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[1] origin:064-gtp-channel-conf 29_208 +GTP_CHANNEL_0.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[2] origin:064-gtp-channel-conf 28_209 +GTP_CHANNEL_0.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[3] origin:064-gtp-channel-conf 29_209 +GTP_CHANNEL_0.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[4] origin:064-gtp-channel-conf 28_210 +GTP_CHANNEL_0.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[5] origin:064-gtp-channel-conf 29_210 +GTP_CHANNEL_0.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[6] origin:064-gtp-channel-conf 28_211 +GTP_CHANNEL_0.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[7] origin:064-gtp-channel-conf 29_211 +GTP_CHANNEL_0.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[0] origin:064-gtp-channel-conf 28_212 +GTP_CHANNEL_0.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[1] origin:064-gtp-channel-conf 29_212 +GTP_CHANNEL_0.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[2] origin:064-gtp-channel-conf 28_213 +GTP_CHANNEL_0.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[3] origin:064-gtp-channel-conf 29_213 +GTP_CHANNEL_0.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[4] origin:064-gtp-channel-conf 28_214 +GTP_CHANNEL_0.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[5] origin:064-gtp-channel-conf 29_214 +GTP_CHANNEL_0.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[6] origin:064-gtp-channel-conf 28_215 +GTP_CHANNEL_0.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[7] origin:064-gtp-channel-conf 29_215 +GTP_CHANNEL_0.GTPE2_CHANNEL.PMA_LOOPBACK_CFG[0] origin:064-gtp-channel-conf 29_207 +GTP_CHANNEL_0.GTPE2_CHANNEL.PMA_RSV[0] origin:064-gtp-channel-conf 30_520 +GTP_CHANNEL_0.GTPE2_CHANNEL.PMA_RSV[1] origin:064-gtp-channel-conf 31_520 +GTP_CHANNEL_0.GTPE2_CHANNEL.PMA_RSV[2] origin:064-gtp-channel-conf 30_521 +GTP_CHANNEL_0.GTPE2_CHANNEL.PMA_RSV[3] origin:064-gtp-channel-conf 31_521 +GTP_CHANNEL_0.GTPE2_CHANNEL.PMA_RSV[4] origin:064-gtp-channel-conf 30_522 +GTP_CHANNEL_0.GTPE2_CHANNEL.PMA_RSV[5] origin:064-gtp-channel-conf 31_522 +GTP_CHANNEL_0.GTPE2_CHANNEL.PMA_RSV[6] origin:064-gtp-channel-conf 30_523 +GTP_CHANNEL_0.GTPE2_CHANNEL.PMA_RSV[7] origin:064-gtp-channel-conf 31_523 +GTP_CHANNEL_0.GTPE2_CHANNEL.PMA_RSV[8] origin:064-gtp-channel-conf 30_524 +GTP_CHANNEL_0.GTPE2_CHANNEL.PMA_RSV[9] origin:064-gtp-channel-conf 31_524 +GTP_CHANNEL_0.GTPE2_CHANNEL.PMA_RSV[10] origin:064-gtp-channel-conf 30_525 +GTP_CHANNEL_0.GTPE2_CHANNEL.PMA_RSV[11] origin:064-gtp-channel-conf 31_525 +GTP_CHANNEL_0.GTPE2_CHANNEL.PMA_RSV[12] origin:064-gtp-channel-conf 30_526 +GTP_CHANNEL_0.GTPE2_CHANNEL.PMA_RSV[13] origin:064-gtp-channel-conf 31_526 +GTP_CHANNEL_0.GTPE2_CHANNEL.PMA_RSV[14] origin:064-gtp-channel-conf 30_527 +GTP_CHANNEL_0.GTPE2_CHANNEL.PMA_RSV[15] origin:064-gtp-channel-conf 31_527 +GTP_CHANNEL_0.GTPE2_CHANNEL.PMA_RSV[16] origin:064-gtp-channel-conf 30_528 +GTP_CHANNEL_0.GTPE2_CHANNEL.PMA_RSV[17] origin:064-gtp-channel-conf 31_528 +GTP_CHANNEL_0.GTPE2_CHANNEL.PMA_RSV[18] origin:064-gtp-channel-conf 30_529 +GTP_CHANNEL_0.GTPE2_CHANNEL.PMA_RSV[19] origin:064-gtp-channel-conf 31_529 +GTP_CHANNEL_0.GTPE2_CHANNEL.PMA_RSV[20] origin:064-gtp-channel-conf 30_530 +GTP_CHANNEL_0.GTPE2_CHANNEL.PMA_RSV[21] origin:064-gtp-channel-conf 31_530 +GTP_CHANNEL_0.GTPE2_CHANNEL.PMA_RSV[22] origin:064-gtp-channel-conf 30_531 +GTP_CHANNEL_0.GTPE2_CHANNEL.PMA_RSV[23] origin:064-gtp-channel-conf 31_531 +GTP_CHANNEL_0.GTPE2_CHANNEL.PMA_RSV[24] origin:064-gtp-channel-conf 30_532 +GTP_CHANNEL_0.GTPE2_CHANNEL.PMA_RSV[25] origin:064-gtp-channel-conf 31_532 +GTP_CHANNEL_0.GTPE2_CHANNEL.PMA_RSV[26] origin:064-gtp-channel-conf 30_533 +GTP_CHANNEL_0.GTPE2_CHANNEL.PMA_RSV[27] origin:064-gtp-channel-conf 31_533 +GTP_CHANNEL_0.GTPE2_CHANNEL.PMA_RSV[28] origin:064-gtp-channel-conf 30_534 +GTP_CHANNEL_0.GTPE2_CHANNEL.PMA_RSV[29] origin:064-gtp-channel-conf 31_534 +GTP_CHANNEL_0.GTPE2_CHANNEL.PMA_RSV[30] origin:064-gtp-channel-conf 30_535 +GTP_CHANNEL_0.GTPE2_CHANNEL.PMA_RSV[31] origin:064-gtp-channel-conf 31_535 +GTP_CHANNEL_0.GTPE2_CHANNEL.PMA_RSV2[0] origin:064-gtp-channel-conf 30_336 +GTP_CHANNEL_0.GTPE2_CHANNEL.PMA_RSV2[1] origin:064-gtp-channel-conf 31_336 +GTP_CHANNEL_0.GTPE2_CHANNEL.PMA_RSV2[2] origin:064-gtp-channel-conf 30_337 +GTP_CHANNEL_0.GTPE2_CHANNEL.PMA_RSV2[3] origin:064-gtp-channel-conf 31_337 +GTP_CHANNEL_0.GTPE2_CHANNEL.PMA_RSV2[4] origin:064-gtp-channel-conf 30_338 +GTP_CHANNEL_0.GTPE2_CHANNEL.PMA_RSV2[5] origin:064-gtp-channel-conf 31_338 +GTP_CHANNEL_0.GTPE2_CHANNEL.PMA_RSV2[6] origin:064-gtp-channel-conf 30_339 +GTP_CHANNEL_0.GTPE2_CHANNEL.PMA_RSV2[7] origin:064-gtp-channel-conf 31_339 +GTP_CHANNEL_0.GTPE2_CHANNEL.PMA_RSV2[8] origin:064-gtp-channel-conf 30_340 +GTP_CHANNEL_0.GTPE2_CHANNEL.PMA_RSV2[9] origin:064-gtp-channel-conf 31_340 +GTP_CHANNEL_0.GTPE2_CHANNEL.PMA_RSV2[10] origin:064-gtp-channel-conf 30_341 +GTP_CHANNEL_0.GTPE2_CHANNEL.PMA_RSV2[11] origin:064-gtp-channel-conf 31_341 +GTP_CHANNEL_0.GTPE2_CHANNEL.PMA_RSV2[12] origin:064-gtp-channel-conf 30_342 +GTP_CHANNEL_0.GTPE2_CHANNEL.PMA_RSV2[13] origin:064-gtp-channel-conf 31_342 +GTP_CHANNEL_0.GTPE2_CHANNEL.PMA_RSV2[14] origin:064-gtp-channel-conf 30_343 +GTP_CHANNEL_0.GTPE2_CHANNEL.PMA_RSV2[15] origin:064-gtp-channel-conf 31_343 +GTP_CHANNEL_0.GTPE2_CHANNEL.PMA_RSV2[16] origin:064-gtp-channel-conf 30_344 +GTP_CHANNEL_0.GTPE2_CHANNEL.PMA_RSV2[17] origin:064-gtp-channel-conf 31_344 +GTP_CHANNEL_0.GTPE2_CHANNEL.PMA_RSV2[18] origin:064-gtp-channel-conf 30_345 +GTP_CHANNEL_0.GTPE2_CHANNEL.PMA_RSV2[19] origin:064-gtp-channel-conf 31_345 +GTP_CHANNEL_0.GTPE2_CHANNEL.PMA_RSV2[20] origin:064-gtp-channel-conf 30_346 +GTP_CHANNEL_0.GTPE2_CHANNEL.PMA_RSV2[21] origin:064-gtp-channel-conf 31_346 +GTP_CHANNEL_0.GTPE2_CHANNEL.PMA_RSV2[22] origin:064-gtp-channel-conf 30_347 +GTP_CHANNEL_0.GTPE2_CHANNEL.PMA_RSV2[23] origin:064-gtp-channel-conf 31_347 +GTP_CHANNEL_0.GTPE2_CHANNEL.PMA_RSV2[24] origin:064-gtp-channel-conf 30_348 +GTP_CHANNEL_0.GTPE2_CHANNEL.PMA_RSV2[25] origin:064-gtp-channel-conf 31_348 +GTP_CHANNEL_0.GTPE2_CHANNEL.PMA_RSV2[26] origin:064-gtp-channel-conf 30_349 +GTP_CHANNEL_0.GTPE2_CHANNEL.PMA_RSV2[27] origin:064-gtp-channel-conf 31_349 +GTP_CHANNEL_0.GTPE2_CHANNEL.PMA_RSV2[28] origin:064-gtp-channel-conf 30_350 +GTP_CHANNEL_0.GTPE2_CHANNEL.PMA_RSV2[29] origin:064-gtp-channel-conf 31_350 +GTP_CHANNEL_0.GTPE2_CHANNEL.PMA_RSV2[30] origin:064-gtp-channel-conf 30_351 +GTP_CHANNEL_0.GTPE2_CHANNEL.PMA_RSV2[31] origin:064-gtp-channel-conf 31_351 +GTP_CHANNEL_0.GTPE2_CHANNEL.PMA_RSV3[0] origin:064-gtp-channel-conf 30_288 +GTP_CHANNEL_0.GTPE2_CHANNEL.PMA_RSV3[1] origin:064-gtp-channel-conf 31_288 +GTP_CHANNEL_0.GTPE2_CHANNEL.PMA_RSV4[0] origin:064-gtp-channel-conf 30_156 +GTP_CHANNEL_0.GTPE2_CHANNEL.PMA_RSV4[1] origin:064-gtp-channel-conf 31_156 +GTP_CHANNEL_0.GTPE2_CHANNEL.PMA_RSV4[2] origin:064-gtp-channel-conf 30_157 +GTP_CHANNEL_0.GTPE2_CHANNEL.PMA_RSV4[3] origin:064-gtp-channel-conf 31_157 +GTP_CHANNEL_0.GTPE2_CHANNEL.PMA_RSV5[0] origin:064-gtp-channel-conf 31_159 +GTP_CHANNEL_0.GTPE2_CHANNEL.PMA_RSV6[0] origin:064-gtp-channel-conf 30_303 +GTP_CHANNEL_0.GTPE2_CHANNEL.PMA_RSV7[0] origin:064-gtp-channel-conf 31_303 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_BIAS_CFG[0] origin:064-gtp-channel-conf 30_112 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_BIAS_CFG[1] origin:064-gtp-channel-conf 31_112 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_BIAS_CFG[2] origin:064-gtp-channel-conf 30_113 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_BIAS_CFG[3] origin:064-gtp-channel-conf 31_113 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_BIAS_CFG[4] origin:064-gtp-channel-conf 30_114 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_BIAS_CFG[5] origin:064-gtp-channel-conf 31_114 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_BIAS_CFG[6] origin:064-gtp-channel-conf 30_115 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_BIAS_CFG[7] origin:064-gtp-channel-conf 31_115 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_BIAS_CFG[8] origin:064-gtp-channel-conf 30_116 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_BIAS_CFG[9] origin:064-gtp-channel-conf 31_116 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_BIAS_CFG[10] origin:064-gtp-channel-conf 30_117 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_BIAS_CFG[11] origin:064-gtp-channel-conf 31_117 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_BIAS_CFG[12] origin:064-gtp-channel-conf 30_118 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_BIAS_CFG[13] origin:064-gtp-channel-conf 31_118 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_BIAS_CFG[14] origin:064-gtp-channel-conf 30_119 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_BIAS_CFG[15] origin:064-gtp-channel-conf 31_119 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_BUFFER_CFG[0] origin:064-gtp-channel-conf 30_536 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_BUFFER_CFG[1] origin:064-gtp-channel-conf 31_536 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_BUFFER_CFG[2] origin:064-gtp-channel-conf 30_537 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_BUFFER_CFG[3] origin:064-gtp-channel-conf 31_537 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_BUFFER_CFG[4] origin:064-gtp-channel-conf 30_538 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_BUFFER_CFG[5] origin:064-gtp-channel-conf 31_538 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_CLKMUX_EN[0] origin:064-gtp-channel-conf 30_128 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_CM_SEL[0] origin:064-gtp-channel-conf 28_138 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_CM_SEL[1] origin:064-gtp-channel-conf 29_138 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_CM_TRIM[0] origin:064-gtp-channel-conf 30_304 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_CM_TRIM[1] origin:064-gtp-channel-conf 31_304 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_CM_TRIM[2] origin:064-gtp-channel-conf 30_305 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_CM_TRIM[3] origin:064-gtp-channel-conf 31_305 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_DATA_WIDTH[0] origin:064-gtp-channel-conf 29_141 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_DATA_WIDTH[1] origin:064-gtp-channel-conf 28_142 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_DATA_WIDTH[2] origin:064-gtp-channel-conf 29_142 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_DDI_SEL[0] origin:064-gtp-channel-conf 28_696 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_DDI_SEL[1] origin:064-gtp-channel-conf 29_696 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_DDI_SEL[2] origin:064-gtp-channel-conf 28_697 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_DDI_SEL[3] origin:064-gtp-channel-conf 29_697 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_DDI_SEL[4] origin:064-gtp-channel-conf 28_698 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_DDI_SEL[5] origin:064-gtp-channel-conf 29_698 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_DEBUG_CFG[0] origin:064-gtp-channel-conf 30_616 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_DEBUG_CFG[1] origin:064-gtp-channel-conf 31_616 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_DEBUG_CFG[2] origin:064-gtp-channel-conf 30_617 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_DEBUG_CFG[3] origin:064-gtp-channel-conf 31_617 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_DEBUG_CFG[4] origin:064-gtp-channel-conf 30_618 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_DEBUG_CFG[5] origin:064-gtp-channel-conf 31_618 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_DEBUG_CFG[6] origin:064-gtp-channel-conf 30_619 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_DEBUG_CFG[7] origin:064-gtp-channel-conf 31_619 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_DEBUG_CFG[8] origin:064-gtp-channel-conf 30_620 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_DEBUG_CFG[9] origin:064-gtp-channel-conf 31_620 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_DEBUG_CFG[10] origin:064-gtp-channel-conf 30_621 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_DEBUG_CFG[11] origin:064-gtp-channel-conf 31_621 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_DEBUG_CFG[12] origin:064-gtp-channel-conf 30_622 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_DEBUG_CFG[13] origin:064-gtp-channel-conf 31_622 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_DEFER_RESET_BUF_EN origin:064-gtp-channel-conf 30_552 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_DISPERR_SEQ_MATCH origin:064-gtp-channel-conf 29_495 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_OS_CFG[0] origin:064-gtp-channel-conf 28_288 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_OS_CFG[1] origin:064-gtp-channel-conf 29_288 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_OS_CFG[2] origin:064-gtp-channel-conf 28_289 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_OS_CFG[3] origin:064-gtp-channel-conf 29_289 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_OS_CFG[4] origin:064-gtp-channel-conf 28_290 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_OS_CFG[5] origin:064-gtp-channel-conf 29_290 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_OS_CFG[6] origin:064-gtp-channel-conf 28_291 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_OS_CFG[7] origin:064-gtp-channel-conf 29_291 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_OS_CFG[8] origin:064-gtp-channel-conf 28_292 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_OS_CFG[9] origin:064-gtp-channel-conf 29_292 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_OS_CFG[10] origin:064-gtp-channel-conf 28_293 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_OS_CFG[11] origin:064-gtp-channel-conf 29_293 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_OS_CFG[12] origin:064-gtp-channel-conf 28_294 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_SIG_VALID_DLY[0] origin:064-gtp-channel-conf 28_524 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_SIG_VALID_DLY[1] origin:064-gtp-channel-conf 29_524 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_SIG_VALID_DLY[2] origin:064-gtp-channel-conf 28_525 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_SIG_VALID_DLY[3] origin:064-gtp-channel-conf 29_525 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_SIG_VALID_DLY[4] origin:064-gtp-channel-conf 28_526 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_XCLK_SEL.RXUSR origin:064-gtp-channel-conf 28_143 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_CLK25_DIV[0] origin:064-gtp-channel-conf 28_139 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_CLK25_DIV[1] origin:064-gtp-channel-conf 29_139 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_CLK25_DIV[2] origin:064-gtp-channel-conf 28_140 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_CLK25_DIV[3] origin:064-gtp-channel-conf 29_140 +GTP_CHANNEL_0.GTPE2_CHANNEL.RX_CLK25_DIV[4] origin:064-gtp-channel-conf 28_141 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXBUF_ADDR_MODE.FAST origin:064-gtp-channel-conf 31_555 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXBUF_EIDLE_HI_CNT[0] origin:064-gtp-channel-conf 30_558 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXBUF_EIDLE_HI_CNT[1] origin:064-gtp-channel-conf 31_558 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXBUF_EIDLE_HI_CNT[2] origin:064-gtp-channel-conf 30_559 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXBUF_EIDLE_HI_CNT[3] origin:064-gtp-channel-conf 31_559 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXBUF_EIDLE_LO_CNT[0] origin:064-gtp-channel-conf 30_556 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXBUF_EIDLE_LO_CNT[1] origin:064-gtp-channel-conf 31_556 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXBUF_EIDLE_LO_CNT[2] origin:064-gtp-channel-conf 30_557 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXBUF_EIDLE_LO_CNT[3] origin:064-gtp-channel-conf 31_557 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXBUF_EN origin:064-gtp-channel-conf 30_11 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXBUF_RESET_ON_CB_CHANGE origin:064-gtp-channel-conf 30_560 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXBUF_RESET_ON_COMMAALIGN origin:064-gtp-channel-conf 30_561 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXBUF_RESET_ON_EIDLE origin:064-gtp-channel-conf 30_547 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXBUF_RESET_ON_RATE_CHANGE origin:064-gtp-channel-conf 31_560 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXBUF_THRESH_OVFLW[0] origin:064-gtp-channel-conf 31_552 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXBUF_THRESH_OVFLW[1] origin:064-gtp-channel-conf 30_553 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXBUF_THRESH_OVFLW[2] origin:064-gtp-channel-conf 31_553 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXBUF_THRESH_OVFLW[3] origin:064-gtp-channel-conf 30_554 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXBUF_THRESH_OVFLW[4] origin:064-gtp-channel-conf 31_554 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXBUF_THRESH_OVFLW[5] origin:064-gtp-channel-conf 30_555 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXBUF_THRESH_OVRD origin:064-gtp-channel-conf 30_548 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXBUF_THRESH_UNDFLW[0] origin:064-gtp-channel-conf 30_544 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXBUF_THRESH_UNDFLW[1] origin:064-gtp-channel-conf 31_544 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXBUF_THRESH_UNDFLW[2] origin:064-gtp-channel-conf 30_545 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXBUF_THRESH_UNDFLW[3] origin:064-gtp-channel-conf 31_545 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXBUF_THRESH_UNDFLW[4] origin:064-gtp-channel-conf 30_546 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXBUF_THRESH_UNDFLW[5] origin:064-gtp-channel-conf 31_546 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXBUFRESET_TIME[0] origin:064-gtp-channel-conf 29_101 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXBUFRESET_TIME[1] origin:064-gtp-channel-conf 28_102 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXBUFRESET_TIME[2] origin:064-gtp-channel-conf 29_102 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXBUFRESET_TIME[3] origin:064-gtp-channel-conf 28_103 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXBUFRESET_TIME[4] origin:064-gtp-channel-conf 29_103 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[0] origin:064-gtp-channel-conf 30_640 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[1] origin:064-gtp-channel-conf 31_640 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[2] origin:064-gtp-channel-conf 30_641 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[3] origin:064-gtp-channel-conf 31_641 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[4] origin:064-gtp-channel-conf 30_642 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[5] origin:064-gtp-channel-conf 31_642 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[6] origin:064-gtp-channel-conf 30_643 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[7] origin:064-gtp-channel-conf 31_643 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[8] origin:064-gtp-channel-conf 30_644 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[9] origin:064-gtp-channel-conf 31_644 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[10] origin:064-gtp-channel-conf 30_645 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[11] origin:064-gtp-channel-conf 31_645 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[12] origin:064-gtp-channel-conf 30_646 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[13] origin:064-gtp-channel-conf 31_646 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[14] origin:064-gtp-channel-conf 30_647 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[15] origin:064-gtp-channel-conf 31_647 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[16] origin:064-gtp-channel-conf 30_648 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[17] origin:064-gtp-channel-conf 31_648 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[18] origin:064-gtp-channel-conf 30_649 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[19] origin:064-gtp-channel-conf 31_649 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[20] origin:064-gtp-channel-conf 30_650 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[21] origin:064-gtp-channel-conf 31_650 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[22] origin:064-gtp-channel-conf 30_651 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[23] origin:064-gtp-channel-conf 31_651 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[24] origin:064-gtp-channel-conf 30_652 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[25] origin:064-gtp-channel-conf 31_652 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[26] origin:064-gtp-channel-conf 30_653 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[27] origin:064-gtp-channel-conf 31_653 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[28] origin:064-gtp-channel-conf 30_654 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[29] origin:064-gtp-channel-conf 31_654 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[30] origin:064-gtp-channel-conf 30_655 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[31] origin:064-gtp-channel-conf 31_655 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[32] origin:064-gtp-channel-conf 30_656 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[33] origin:064-gtp-channel-conf 31_656 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[34] origin:064-gtp-channel-conf 30_657 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[35] origin:064-gtp-channel-conf 31_657 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[36] origin:064-gtp-channel-conf 30_658 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[37] origin:064-gtp-channel-conf 31_658 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[38] origin:064-gtp-channel-conf 30_659 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[39] origin:064-gtp-channel-conf 31_659 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[40] origin:064-gtp-channel-conf 30_660 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[41] origin:064-gtp-channel-conf 31_660 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[42] origin:064-gtp-channel-conf 30_661 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[43] origin:064-gtp-channel-conf 31_661 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[44] origin:064-gtp-channel-conf 30_662 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[45] origin:064-gtp-channel-conf 31_662 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[46] origin:064-gtp-channel-conf 30_663 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[47] origin:064-gtp-channel-conf 31_663 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[48] origin:064-gtp-channel-conf 30_664 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[49] origin:064-gtp-channel-conf 31_664 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[50] origin:064-gtp-channel-conf 30_665 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[51] origin:064-gtp-channel-conf 31_665 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[52] origin:064-gtp-channel-conf 30_666 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[53] origin:064-gtp-channel-conf 31_666 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[54] origin:064-gtp-channel-conf 30_667 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[55] origin:064-gtp-channel-conf 31_667 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[56] origin:064-gtp-channel-conf 30_668 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[57] origin:064-gtp-channel-conf 31_668 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[58] origin:064-gtp-channel-conf 30_669 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[59] origin:064-gtp-channel-conf 31_669 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[60] origin:064-gtp-channel-conf 30_670 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[61] origin:064-gtp-channel-conf 31_670 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[62] origin:064-gtp-channel-conf 30_671 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[63] origin:064-gtp-channel-conf 31_671 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[64] origin:064-gtp-channel-conf 30_672 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[65] origin:064-gtp-channel-conf 31_672 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[66] origin:064-gtp-channel-conf 30_673 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[67] origin:064-gtp-channel-conf 31_673 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[68] origin:064-gtp-channel-conf 30_674 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[69] origin:064-gtp-channel-conf 31_674 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[70] origin:064-gtp-channel-conf 30_675 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[71] origin:064-gtp-channel-conf 31_675 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[72] origin:064-gtp-channel-conf 30_676 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[73] origin:064-gtp-channel-conf 31_676 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[74] origin:064-gtp-channel-conf 30_677 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[75] origin:064-gtp-channel-conf 31_677 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[76] origin:064-gtp-channel-conf 30_678 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[77] origin:064-gtp-channel-conf 31_678 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[78] origin:064-gtp-channel-conf 30_679 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[79] origin:064-gtp-channel-conf 31_679 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[80] origin:064-gtp-channel-conf 30_680 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[81] origin:064-gtp-channel-conf 31_680 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_CFG[82] origin:064-gtp-channel-conf 30_681 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_FR_RESET_ON_EIDLE[0] origin:064-gtp-channel-conf 30_638 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_HOLD_DURING_EIDLE[0] origin:064-gtp-channel-conf 31_637 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_LOCK_CFG[0] origin:064-gtp-channel-conf 30_632 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_LOCK_CFG[1] origin:064-gtp-channel-conf 31_632 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_LOCK_CFG[2] origin:064-gtp-channel-conf 30_633 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_LOCK_CFG[3] origin:064-gtp-channel-conf 31_633 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_LOCK_CFG[4] origin:064-gtp-channel-conf 30_634 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_LOCK_CFG[5] origin:064-gtp-channel-conf 31_634 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDR_PH_RESET_ON_EIDLE[0] origin:064-gtp-channel-conf 31_638 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDRFREQRESET_TIME[0] origin:064-gtp-channel-conf 29_106 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDRFREQRESET_TIME[1] origin:064-gtp-channel-conf 28_107 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDRFREQRESET_TIME[2] origin:064-gtp-channel-conf 29_107 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDRFREQRESET_TIME[3] origin:064-gtp-channel-conf 28_108 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDRFREQRESET_TIME[4] origin:064-gtp-channel-conf 29_108 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDRPHRESET_TIME[0] origin:064-gtp-channel-conf 28_109 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDRPHRESET_TIME[1] origin:064-gtp-channel-conf 29_109 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDRPHRESET_TIME[2] origin:064-gtp-channel-conf 28_110 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDRPHRESET_TIME[3] origin:064-gtp-channel-conf 29_110 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXCDRPHRESET_TIME[4] origin:064-gtp-channel-conf 28_111 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXDLY_CFG[0] origin:064-gtp-channel-conf 28_680 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXDLY_CFG[1] origin:064-gtp-channel-conf 29_680 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXDLY_CFG[2] origin:064-gtp-channel-conf 28_681 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXDLY_CFG[3] origin:064-gtp-channel-conf 29_681 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXDLY_CFG[4] origin:064-gtp-channel-conf 28_682 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXDLY_CFG[5] origin:064-gtp-channel-conf 29_682 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXDLY_CFG[6] origin:064-gtp-channel-conf 28_683 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXDLY_CFG[7] origin:064-gtp-channel-conf 29_683 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXDLY_CFG[8] origin:064-gtp-channel-conf 28_684 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXDLY_CFG[9] origin:064-gtp-channel-conf 29_684 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXDLY_CFG[10] origin:064-gtp-channel-conf 28_685 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXDLY_CFG[11] origin:064-gtp-channel-conf 29_685 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXDLY_CFG[12] origin:064-gtp-channel-conf 28_686 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXDLY_CFG[13] origin:064-gtp-channel-conf 29_686 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXDLY_CFG[14] origin:064-gtp-channel-conf 28_687 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXDLY_CFG[15] origin:064-gtp-channel-conf 29_687 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXDLY_LCFG[0] origin:064-gtp-channel-conf 30_576 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXDLY_LCFG[1] origin:064-gtp-channel-conf 31_576 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXDLY_LCFG[2] origin:064-gtp-channel-conf 30_577 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXDLY_LCFG[3] origin:064-gtp-channel-conf 31_577 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXDLY_LCFG[4] origin:064-gtp-channel-conf 30_578 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXDLY_LCFG[5] origin:064-gtp-channel-conf 31_578 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXDLY_LCFG[6] origin:064-gtp-channel-conf 30_579 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXDLY_LCFG[7] origin:064-gtp-channel-conf 31_579 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXDLY_LCFG[8] origin:064-gtp-channel-conf 30_580 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXDLY_TAP_CFG[0] origin:064-gtp-channel-conf 28_672 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXDLY_TAP_CFG[1] origin:064-gtp-channel-conf 29_672 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXDLY_TAP_CFG[2] origin:064-gtp-channel-conf 28_673 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXDLY_TAP_CFG[3] origin:064-gtp-channel-conf 29_673 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXDLY_TAP_CFG[4] origin:064-gtp-channel-conf 28_674 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXDLY_TAP_CFG[5] origin:064-gtp-channel-conf 29_674 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXDLY_TAP_CFG[6] origin:064-gtp-channel-conf 28_675 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXDLY_TAP_CFG[7] origin:064-gtp-channel-conf 29_675 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXDLY_TAP_CFG[8] origin:064-gtp-channel-conf 28_676 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXDLY_TAP_CFG[9] origin:064-gtp-channel-conf 29_676 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXDLY_TAP_CFG[10] origin:064-gtp-channel-conf 28_677 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXDLY_TAP_CFG[11] origin:064-gtp-channel-conf 29_677 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXDLY_TAP_CFG[12] origin:064-gtp-channel-conf 28_678 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXDLY_TAP_CFG[13] origin:064-gtp-channel-conf 29_678 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXDLY_TAP_CFG[14] origin:064-gtp-channel-conf 28_679 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXDLY_TAP_CFG[15] origin:064-gtp-channel-conf 29_679 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXGEARBOX_EN origin:064-gtp-channel-conf 29_607 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXISCANRESET_TIME[0] origin:064-gtp-channel-conf 29_123 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXISCANRESET_TIME[1] origin:064-gtp-channel-conf 28_124 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXISCANRESET_TIME[2] origin:064-gtp-channel-conf 29_124 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXISCANRESET_TIME[3] origin:064-gtp-channel-conf 28_125 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXISCANRESET_TIME[4] origin:064-gtp-channel-conf 29_125 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPM_BIAS_STARTUP_DISABLE[0] origin:064-gtp-channel-conf 31_391 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPM_CFG[0] origin:064-gtp-channel-conf 30_328 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPM_CFG[1] origin:064-gtp-channel-conf 31_328 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPM_CFG[2] origin:064-gtp-channel-conf 30_329 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPM_CFG[3] origin:064-gtp-channel-conf 31_329 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPM_CM_CFG[0] origin:064-gtp-channel-conf 30_430 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPM_GC_CFG[0] origin:064-gtp-channel-conf 30_432 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPM_GC_CFG[1] origin:064-gtp-channel-conf 31_432 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPM_GC_CFG[2] origin:064-gtp-channel-conf 30_433 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPM_GC_CFG[3] origin:064-gtp-channel-conf 31_433 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPM_GC_CFG[4] origin:064-gtp-channel-conf 30_434 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPM_GC_CFG[5] origin:064-gtp-channel-conf 31_434 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPM_GC_CFG[6] origin:064-gtp-channel-conf 30_435 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPM_GC_CFG[7] origin:064-gtp-channel-conf 31_435 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPM_GC_CFG[8] origin:064-gtp-channel-conf 30_436 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPM_GC_CFG2[0] origin:064-gtp-channel-conf 31_442 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPM_GC_CFG2[1] origin:064-gtp-channel-conf 30_443 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPM_GC_CFG2[2] origin:064-gtp-channel-conf 31_443 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPM_HF_CFG[0] origin:064-gtp-channel-conf 28_336 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPM_HF_CFG[1] origin:064-gtp-channel-conf 29_336 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPM_HF_CFG[2] origin:064-gtp-channel-conf 28_337 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPM_HF_CFG[3] origin:064-gtp-channel-conf 29_337 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPM_HF_CFG[4] origin:064-gtp-channel-conf 28_338 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPM_HF_CFG[5] origin:064-gtp-channel-conf 29_338 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPM_HF_CFG[6] origin:064-gtp-channel-conf 28_339 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPM_HF_CFG[7] origin:064-gtp-channel-conf 29_339 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPM_HF_CFG[8] origin:064-gtp-channel-conf 28_340 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPM_HF_CFG[9] origin:064-gtp-channel-conf 29_340 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPM_HF_CFG[10] origin:064-gtp-channel-conf 28_341 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPM_HF_CFG[11] origin:064-gtp-channel-conf 29_341 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPM_HF_CFG[12] origin:064-gtp-channel-conf 28_342 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPM_HF_CFG[13] origin:064-gtp-channel-conf 29_342 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPM_HF_CFG2[0] origin:064-gtp-channel-conf 30_424 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPM_HF_CFG2[1] origin:064-gtp-channel-conf 31_424 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPM_HF_CFG2[2] origin:064-gtp-channel-conf 30_425 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPM_HF_CFG2[3] origin:064-gtp-channel-conf 31_425 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPM_HF_CFG2[4] origin:064-gtp-channel-conf 30_426 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPM_HF_CFG3[0] origin:064-gtp-channel-conf 31_389 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPM_HF_CFG3[1] origin:064-gtp-channel-conf 30_390 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPM_HF_CFG3[2] origin:064-gtp-channel-conf 31_390 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPM_HF_CFG3[3] origin:064-gtp-channel-conf 30_391 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPM_HOLD_DURING_EIDLE[0] origin:064-gtp-channel-conf 28_247 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPM_INCM_CFG[0] origin:064-gtp-channel-conf 30_439 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPM_IPCM_CFG[0] origin:064-gtp-channel-conf 31_439 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPM_LF_CFG[0] origin:064-gtp-channel-conf 28_344 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPM_LF_CFG[1] origin:064-gtp-channel-conf 29_344 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPM_LF_CFG[2] origin:064-gtp-channel-conf 28_345 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPM_LF_CFG[3] origin:064-gtp-channel-conf 29_345 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPM_LF_CFG[4] origin:064-gtp-channel-conf 28_346 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPM_LF_CFG[5] origin:064-gtp-channel-conf 29_346 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPM_LF_CFG[6] origin:064-gtp-channel-conf 28_347 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPM_LF_CFG[7] origin:064-gtp-channel-conf 29_347 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPM_LF_CFG[8] origin:064-gtp-channel-conf 28_348 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPM_LF_CFG[9] origin:064-gtp-channel-conf 29_348 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPM_LF_CFG[10] origin:064-gtp-channel-conf 28_349 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPM_LF_CFG[11] origin:064-gtp-channel-conf 29_349 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPM_LF_CFG[12] origin:064-gtp-channel-conf 28_350 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPM_LF_CFG[13] origin:064-gtp-channel-conf 29_350 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPM_LF_CFG[14] origin:064-gtp-channel-conf 28_351 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPM_LF_CFG[15] origin:064-gtp-channel-conf 29_351 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPM_LF_CFG[16] origin:064-gtp-channel-conf 28_343 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPM_LF_CFG[17] origin:064-gtp-channel-conf 29_343 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPM_LF_CFG2[0] origin:064-gtp-channel-conf 31_426 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPM_LF_CFG2[1] origin:064-gtp-channel-conf 30_427 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPM_LF_CFG2[2] origin:064-gtp-channel-conf 31_427 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPM_LF_CFG2[3] origin:064-gtp-channel-conf 30_428 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPM_LF_CFG2[4] origin:064-gtp-channel-conf 31_428 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPM_OSINT_CFG[0] origin:064-gtp-channel-conf 30_440 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPM_OSINT_CFG[1] origin:064-gtp-channel-conf 31_440 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPM_OSINT_CFG[2] origin:064-gtp-channel-conf 30_441 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPM_CFG1[0] origin:064-gtp-channel-conf 30_330 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPMRESET_TIME[0] origin:064-gtp-channel-conf 28_112 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPMRESET_TIME[1] origin:064-gtp-channel-conf 29_112 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPMRESET_TIME[2] origin:064-gtp-channel-conf 28_113 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPMRESET_TIME[3] origin:064-gtp-channel-conf 29_113 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPMRESET_TIME[4] origin:064-gtp-channel-conf 28_114 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPMRESET_TIME[5] origin:064-gtp-channel-conf 29_114 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXLPMRESET_TIME[6] origin:064-gtp-channel-conf 28_115 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXOOB_CFG[0] origin:064-gtp-channel-conf 28_144 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXOOB_CFG[1] origin:064-gtp-channel-conf 29_144 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXOOB_CFG[2] origin:064-gtp-channel-conf 28_145 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXOOB_CFG[3] origin:064-gtp-channel-conf 29_145 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXOOB_CFG[4] origin:064-gtp-channel-conf 28_146 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXOOB_CFG[5] origin:064-gtp-channel-conf 29_146 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXOOB_CFG[6] origin:064-gtp-channel-conf 28_147 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXOOB_CLK_CFG.FABRIC origin:064-gtp-channel-conf 31_129 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXOSCALRESET_TIME[0] origin:064-gtp-channel-conf 28_187 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXOSCALRESET_TIME[1] origin:064-gtp-channel-conf 29_187 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXOSCALRESET_TIME[2] origin:064-gtp-channel-conf 28_188 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXOSCALRESET_TIME[3] origin:064-gtp-channel-conf 29_188 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXOSCALRESET_TIME[4] origin:064-gtp-channel-conf 28_189 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXOSCALRESET_TIMEOUT[0] origin:064-gtp-channel-conf 29_189 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXOSCALRESET_TIMEOUT[1] origin:064-gtp-channel-conf 28_190 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXOSCALRESET_TIMEOUT[2] origin:064-gtp-channel-conf 29_190 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXOSCALRESET_TIMEOUT[3] origin:064-gtp-channel-conf 28_191 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXOSCALRESET_TIMEOUT[4] origin:064-gtp-channel-conf 29_191 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXOUT_DIV[0] origin:064-gtp-channel-conf 30_384 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXOUT_DIV[1] origin:064-gtp-channel-conf 31_384 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXPCSRESET_TIME[0] origin:064-gtp-channel-conf 29_115 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXPCSRESET_TIME[1] origin:064-gtp-channel-conf 28_116 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXPCSRESET_TIME[2] origin:064-gtp-channel-conf 29_116 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXPCSRESET_TIME[3] origin:064-gtp-channel-conf 28_117 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXPCSRESET_TIME[4] origin:064-gtp-channel-conf 29_117 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXPH_CFG[0] origin:064-gtp-channel-conf 30_584 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXPH_CFG[1] origin:064-gtp-channel-conf 31_584 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXPH_CFG[2] origin:064-gtp-channel-conf 30_585 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXPH_CFG[3] origin:064-gtp-channel-conf 31_585 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXPH_CFG[4] origin:064-gtp-channel-conf 30_586 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXPH_CFG[5] origin:064-gtp-channel-conf 31_586 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXPH_CFG[6] origin:064-gtp-channel-conf 30_587 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXPH_CFG[7] origin:064-gtp-channel-conf 31_587 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXPH_CFG[8] origin:064-gtp-channel-conf 30_588 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXPH_CFG[9] origin:064-gtp-channel-conf 31_588 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXPH_CFG[10] origin:064-gtp-channel-conf 30_589 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXPH_CFG[11] origin:064-gtp-channel-conf 31_589 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXPH_CFG[12] origin:064-gtp-channel-conf 30_590 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXPH_CFG[13] origin:064-gtp-channel-conf 31_590 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXPH_CFG[14] origin:064-gtp-channel-conf 30_591 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXPH_CFG[15] origin:064-gtp-channel-conf 31_591 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXPH_CFG[16] origin:064-gtp-channel-conf 30_592 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXPH_CFG[17] origin:064-gtp-channel-conf 31_592 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXPH_CFG[18] origin:064-gtp-channel-conf 30_593 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXPH_CFG[19] origin:064-gtp-channel-conf 31_593 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXPH_CFG[20] origin:064-gtp-channel-conf 30_594 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXPH_CFG[21] origin:064-gtp-channel-conf 31_594 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXPH_CFG[22] origin:064-gtp-channel-conf 30_595 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXPH_CFG[23] origin:064-gtp-channel-conf 31_595 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXPH_MONITOR_SEL[0] origin:064-gtp-channel-conf 28_700 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXPH_MONITOR_SEL[1] origin:064-gtp-channel-conf 29_700 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXPH_MONITOR_SEL[2] origin:064-gtp-channel-conf 28_701 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXPH_MONITOR_SEL[3] origin:064-gtp-channel-conf 29_701 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXPH_MONITOR_SEL[4] origin:064-gtp-channel-conf 28_702 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXPHDLY_CFG[0] origin:064-gtp-channel-conf 30_600 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXPHDLY_CFG[1] origin:064-gtp-channel-conf 31_600 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXPHDLY_CFG[2] origin:064-gtp-channel-conf 30_601 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXPHDLY_CFG[3] origin:064-gtp-channel-conf 31_601 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXPHDLY_CFG[4] origin:064-gtp-channel-conf 30_602 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXPHDLY_CFG[5] origin:064-gtp-channel-conf 31_602 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXPHDLY_CFG[6] origin:064-gtp-channel-conf 30_603 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXPHDLY_CFG[7] origin:064-gtp-channel-conf 31_603 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXPHDLY_CFG[8] origin:064-gtp-channel-conf 30_604 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXPHDLY_CFG[9] origin:064-gtp-channel-conf 31_604 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXPHDLY_CFG[10] origin:064-gtp-channel-conf 30_605 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXPHDLY_CFG[11] origin:064-gtp-channel-conf 31_605 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXPHDLY_CFG[12] origin:064-gtp-channel-conf 30_606 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXPHDLY_CFG[13] origin:064-gtp-channel-conf 31_606 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXPHDLY_CFG[14] origin:064-gtp-channel-conf 30_607 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXPHDLY_CFG[15] origin:064-gtp-channel-conf 31_607 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXPHDLY_CFG[16] origin:064-gtp-channel-conf 30_608 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXPHDLY_CFG[17] origin:064-gtp-channel-conf 31_608 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXPHDLY_CFG[18] origin:064-gtp-channel-conf 30_609 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXPHDLY_CFG[19] origin:064-gtp-channel-conf 31_609 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXPHDLY_CFG[20] origin:064-gtp-channel-conf 30_610 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXPHDLY_CFG[21] origin:064-gtp-channel-conf 31_610 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXPHDLY_CFG[22] origin:064-gtp-channel-conf 30_611 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXPHDLY_CFG[23] origin:064-gtp-channel-conf 31_611 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXPI_CFG0[0] origin:064-gtp-channel-conf 31_430 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXPI_CFG0[1] origin:064-gtp-channel-conf 30_431 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXPI_CFG0[2] origin:064-gtp-channel-conf 31_431 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXPI_CFG1[0] origin:064-gtp-channel-conf 30_442 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXPI_CFG2[0] origin:064-gtp-channel-conf 31_441 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXPMARESET_TIME[0] origin:064-gtp-channel-conf 28_104 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXPMARESET_TIME[1] origin:064-gtp-channel-conf 29_104 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXPMARESET_TIME[2] origin:064-gtp-channel-conf 28_105 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXPMARESET_TIME[3] origin:064-gtp-channel-conf 29_105 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXPMARESET_TIME[4] origin:064-gtp-channel-conf 28_106 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXPRBS_ERR_LOOPBACK[0] origin:064-gtp-channel-conf 28_136 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXSLIDE_AUTO_WAIT[0] origin:064-gtp-channel-conf 28_520 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXSLIDE_AUTO_WAIT[1] origin:064-gtp-channel-conf 29_520 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXSLIDE_AUTO_WAIT[2] origin:064-gtp-channel-conf 28_521 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXSLIDE_AUTO_WAIT[3] origin:064-gtp-channel-conf 29_521 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXSLIDE_MODE.AUTO origin:064-gtp-channel-conf !29_519 28_519 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXSLIDE_MODE.PCS origin:064-gtp-channel-conf !28_519 29_519 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXSLIDE_MODE.PMA origin:064-gtp-channel-conf 28_519 29_519 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXSYNC_MULTILANE[0] origin:064-gtp-channel-conf 28_133 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXSYNC_OVRD[0] origin:064-gtp-channel-conf 29_135 +GTP_CHANNEL_0.GTPE2_CHANNEL.RXSYNC_SKIP_DA[0] origin:064-gtp-channel-conf 29_134 +GTP_CHANNEL_0.GTPE2_CHANNEL.SAS_MAX_COM[0] origin:064-gtp-channel-conf 28_171 +GTP_CHANNEL_0.GTPE2_CHANNEL.SAS_MAX_COM[1] origin:064-gtp-channel-conf 29_171 +GTP_CHANNEL_0.GTPE2_CHANNEL.SAS_MAX_COM[2] origin:064-gtp-channel-conf 28_172 +GTP_CHANNEL_0.GTPE2_CHANNEL.SAS_MAX_COM[3] origin:064-gtp-channel-conf 29_172 +GTP_CHANNEL_0.GTPE2_CHANNEL.SAS_MAX_COM[4] origin:064-gtp-channel-conf 28_173 +GTP_CHANNEL_0.GTPE2_CHANNEL.SAS_MAX_COM[5] origin:064-gtp-channel-conf 29_173 +GTP_CHANNEL_0.GTPE2_CHANNEL.SAS_MAX_COM[6] origin:064-gtp-channel-conf 28_174 +GTP_CHANNEL_0.GTPE2_CHANNEL.SAS_MIN_COM[0] origin:064-gtp-channel-conf 29_156 +GTP_CHANNEL_0.GTPE2_CHANNEL.SAS_MIN_COM[1] origin:064-gtp-channel-conf 28_157 +GTP_CHANNEL_0.GTPE2_CHANNEL.SAS_MIN_COM[2] origin:064-gtp-channel-conf 29_157 +GTP_CHANNEL_0.GTPE2_CHANNEL.SAS_MIN_COM[3] origin:064-gtp-channel-conf 28_158 +GTP_CHANNEL_0.GTPE2_CHANNEL.SAS_MIN_COM[4] origin:064-gtp-channel-conf 29_158 +GTP_CHANNEL_0.GTPE2_CHANNEL.SAS_MIN_COM[5] origin:064-gtp-channel-conf 28_159 +GTP_CHANNEL_0.GTPE2_CHANNEL.SATA_BURST_SEQ_LEN[0] origin:064-gtp-channel-conf 28_150 +GTP_CHANNEL_0.GTPE2_CHANNEL.SATA_BURST_SEQ_LEN[1] origin:064-gtp-channel-conf 29_150 +GTP_CHANNEL_0.GTPE2_CHANNEL.SATA_BURST_SEQ_LEN[2] origin:064-gtp-channel-conf 28_151 +GTP_CHANNEL_0.GTPE2_CHANNEL.SATA_BURST_SEQ_LEN[3] origin:064-gtp-channel-conf 29_151 +GTP_CHANNEL_0.GTPE2_CHANNEL.SATA_BURST_VAL[0] origin:064-gtp-channel-conf 29_147 +GTP_CHANNEL_0.GTPE2_CHANNEL.SATA_BURST_VAL[1] origin:064-gtp-channel-conf 28_148 +GTP_CHANNEL_0.GTPE2_CHANNEL.SATA_BURST_VAL[2] origin:064-gtp-channel-conf 29_148 +GTP_CHANNEL_0.GTPE2_CHANNEL.SATA_EIDLE_VAL[0] origin:064-gtp-channel-conf 28_152 +GTP_CHANNEL_0.GTPE2_CHANNEL.SATA_EIDLE_VAL[1] origin:064-gtp-channel-conf 29_152 +GTP_CHANNEL_0.GTPE2_CHANNEL.SATA_EIDLE_VAL[2] origin:064-gtp-channel-conf 28_153 +GTP_CHANNEL_0.GTPE2_CHANNEL.SATA_MAX_BURST[0] origin:064-gtp-channel-conf 28_168 +GTP_CHANNEL_0.GTPE2_CHANNEL.SATA_MAX_BURST[1] origin:064-gtp-channel-conf 29_168 +GTP_CHANNEL_0.GTPE2_CHANNEL.SATA_MAX_BURST[2] origin:064-gtp-channel-conf 28_169 +GTP_CHANNEL_0.GTPE2_CHANNEL.SATA_MAX_BURST[3] origin:064-gtp-channel-conf 29_169 +GTP_CHANNEL_0.GTPE2_CHANNEL.SATA_MAX_BURST[4] origin:064-gtp-channel-conf 28_170 +GTP_CHANNEL_0.GTPE2_CHANNEL.SATA_MAX_BURST[5] origin:064-gtp-channel-conf 29_170 +GTP_CHANNEL_0.GTPE2_CHANNEL.SATA_MAX_INIT[0] origin:064-gtp-channel-conf 28_176 +GTP_CHANNEL_0.GTPE2_CHANNEL.SATA_MAX_INIT[1] origin:064-gtp-channel-conf 29_176 +GTP_CHANNEL_0.GTPE2_CHANNEL.SATA_MAX_INIT[2] origin:064-gtp-channel-conf 28_177 +GTP_CHANNEL_0.GTPE2_CHANNEL.SATA_MAX_INIT[3] origin:064-gtp-channel-conf 29_177 +GTP_CHANNEL_0.GTPE2_CHANNEL.SATA_MAX_INIT[4] origin:064-gtp-channel-conf 28_178 +GTP_CHANNEL_0.GTPE2_CHANNEL.SATA_MAX_INIT[5] origin:064-gtp-channel-conf 29_178 +GTP_CHANNEL_0.GTPE2_CHANNEL.SATA_MAX_WAKE[0] origin:064-gtp-channel-conf 28_179 +GTP_CHANNEL_0.GTPE2_CHANNEL.SATA_MAX_WAKE[1] origin:064-gtp-channel-conf 29_179 +GTP_CHANNEL_0.GTPE2_CHANNEL.SATA_MAX_WAKE[2] origin:064-gtp-channel-conf 28_180 +GTP_CHANNEL_0.GTPE2_CHANNEL.SATA_MAX_WAKE[3] origin:064-gtp-channel-conf 29_180 +GTP_CHANNEL_0.GTPE2_CHANNEL.SATA_MAX_WAKE[4] origin:064-gtp-channel-conf 28_181 +GTP_CHANNEL_0.GTPE2_CHANNEL.SATA_MAX_WAKE[5] origin:064-gtp-channel-conf 29_181 +GTP_CHANNEL_0.GTPE2_CHANNEL.SATA_MIN_BURST[0] origin:064-gtp-channel-conf 29_153 +GTP_CHANNEL_0.GTPE2_CHANNEL.SATA_MIN_BURST[1] origin:064-gtp-channel-conf 28_154 +GTP_CHANNEL_0.GTPE2_CHANNEL.SATA_MIN_BURST[2] origin:064-gtp-channel-conf 29_154 +GTP_CHANNEL_0.GTPE2_CHANNEL.SATA_MIN_BURST[3] origin:064-gtp-channel-conf 28_155 +GTP_CHANNEL_0.GTPE2_CHANNEL.SATA_MIN_BURST[4] origin:064-gtp-channel-conf 29_155 +GTP_CHANNEL_0.GTPE2_CHANNEL.SATA_MIN_BURST[5] origin:064-gtp-channel-conf 28_156 +GTP_CHANNEL_0.GTPE2_CHANNEL.SATA_MIN_INIT[0] origin:064-gtp-channel-conf 28_160 +GTP_CHANNEL_0.GTPE2_CHANNEL.SATA_MIN_INIT[1] origin:064-gtp-channel-conf 29_160 +GTP_CHANNEL_0.GTPE2_CHANNEL.SATA_MIN_INIT[2] origin:064-gtp-channel-conf 28_161 +GTP_CHANNEL_0.GTPE2_CHANNEL.SATA_MIN_INIT[3] origin:064-gtp-channel-conf 29_161 +GTP_CHANNEL_0.GTPE2_CHANNEL.SATA_MIN_INIT[4] origin:064-gtp-channel-conf 28_162 +GTP_CHANNEL_0.GTPE2_CHANNEL.SATA_MIN_INIT[5] origin:064-gtp-channel-conf 29_162 +GTP_CHANNEL_0.GTPE2_CHANNEL.SATA_MIN_WAKE[0] origin:064-gtp-channel-conf 28_163 +GTP_CHANNEL_0.GTPE2_CHANNEL.SATA_MIN_WAKE[1] origin:064-gtp-channel-conf 29_163 +GTP_CHANNEL_0.GTPE2_CHANNEL.SATA_MIN_WAKE[2] origin:064-gtp-channel-conf 28_164 +GTP_CHANNEL_0.GTPE2_CHANNEL.SATA_MIN_WAKE[3] origin:064-gtp-channel-conf 29_164 +GTP_CHANNEL_0.GTPE2_CHANNEL.SATA_MIN_WAKE[4] origin:064-gtp-channel-conf 28_165 +GTP_CHANNEL_0.GTPE2_CHANNEL.SATA_MIN_WAKE[5] origin:064-gtp-channel-conf 29_165 +GTP_CHANNEL_0.GTPE2_CHANNEL.SATA_PLL_CFG.VCO_1500MHZ origin:064-gtp-channel-conf 30_55 +GTP_CHANNEL_0.GTPE2_CHANNEL.SATA_PLL_CFG.VCO_750MHZ origin:064-gtp-channel-conf 31_55 +GTP_CHANNEL_0.GTPE2_CHANNEL.SHOW_REALIGN_COMMA origin:064-gtp-channel-conf 29_522 +GTP_CHANNEL_0.GTPE2_CHANNEL.TERM_RCAL_CFG[0] origin:064-gtp-channel-conf 30_136 +GTP_CHANNEL_0.GTPE2_CHANNEL.TERM_RCAL_CFG[1] origin:064-gtp-channel-conf 31_136 +GTP_CHANNEL_0.GTPE2_CHANNEL.TERM_RCAL_CFG[2] origin:064-gtp-channel-conf 30_137 +GTP_CHANNEL_0.GTPE2_CHANNEL.TERM_RCAL_CFG[3] origin:064-gtp-channel-conf 31_137 +GTP_CHANNEL_0.GTPE2_CHANNEL.TERM_RCAL_CFG[4] origin:064-gtp-channel-conf 30_138 +GTP_CHANNEL_0.GTPE2_CHANNEL.TERM_RCAL_CFG[5] origin:064-gtp-channel-conf 31_138 +GTP_CHANNEL_0.GTPE2_CHANNEL.TERM_RCAL_CFG[6] origin:064-gtp-channel-conf 30_139 +GTP_CHANNEL_0.GTPE2_CHANNEL.TERM_RCAL_CFG[7] origin:064-gtp-channel-conf 31_139 +GTP_CHANNEL_0.GTPE2_CHANNEL.TERM_RCAL_CFG[8] origin:064-gtp-channel-conf 30_140 +GTP_CHANNEL_0.GTPE2_CHANNEL.TERM_RCAL_CFG[9] origin:064-gtp-channel-conf 31_140 +GTP_CHANNEL_0.GTPE2_CHANNEL.TERM_RCAL_CFG[10] origin:064-gtp-channel-conf 30_141 +GTP_CHANNEL_0.GTPE2_CHANNEL.TERM_RCAL_CFG[11] origin:064-gtp-channel-conf 31_141 +GTP_CHANNEL_0.GTPE2_CHANNEL.TERM_RCAL_CFG[12] origin:064-gtp-channel-conf 30_142 +GTP_CHANNEL_0.GTPE2_CHANNEL.TERM_RCAL_CFG[13] origin:064-gtp-channel-conf 31_142 +GTP_CHANNEL_0.GTPE2_CHANNEL.TERM_RCAL_CFG[14] origin:064-gtp-channel-conf 30_143 +GTP_CHANNEL_0.GTPE2_CHANNEL.TERM_RCAL_OVRD[0] origin:064-gtp-channel-conf 31_150 +GTP_CHANNEL_0.GTPE2_CHANNEL.TERM_RCAL_OVRD[1] origin:064-gtp-channel-conf 30_151 +GTP_CHANNEL_0.GTPE2_CHANNEL.TERM_RCAL_OVRD[2] origin:064-gtp-channel-conf 31_151 +GTP_CHANNEL_0.GTPE2_CHANNEL.TRANS_TIME_RATE[0] origin:064-gtp-channel-conf 28_192 +GTP_CHANNEL_0.GTPE2_CHANNEL.TRANS_TIME_RATE[1] origin:064-gtp-channel-conf 29_192 +GTP_CHANNEL_0.GTPE2_CHANNEL.TRANS_TIME_RATE[2] origin:064-gtp-channel-conf 28_193 +GTP_CHANNEL_0.GTPE2_CHANNEL.TRANS_TIME_RATE[3] origin:064-gtp-channel-conf 29_193 +GTP_CHANNEL_0.GTPE2_CHANNEL.TRANS_TIME_RATE[4] origin:064-gtp-channel-conf 28_194 +GTP_CHANNEL_0.GTPE2_CHANNEL.TRANS_TIME_RATE[5] origin:064-gtp-channel-conf 29_194 +GTP_CHANNEL_0.GTPE2_CHANNEL.TRANS_TIME_RATE[6] origin:064-gtp-channel-conf 28_195 +GTP_CHANNEL_0.GTPE2_CHANNEL.TRANS_TIME_RATE[7] origin:064-gtp-channel-conf 29_195 +GTP_CHANNEL_0.GTPE2_CHANNEL.TST_RSV[0] origin:064-gtp-channel-conf 30_504 +GTP_CHANNEL_0.GTPE2_CHANNEL.TST_RSV[1] origin:064-gtp-channel-conf 31_504 +GTP_CHANNEL_0.GTPE2_CHANNEL.TST_RSV[2] origin:064-gtp-channel-conf 30_505 +GTP_CHANNEL_0.GTPE2_CHANNEL.TST_RSV[3] origin:064-gtp-channel-conf 31_505 +GTP_CHANNEL_0.GTPE2_CHANNEL.TST_RSV[4] origin:064-gtp-channel-conf 30_506 +GTP_CHANNEL_0.GTPE2_CHANNEL.TST_RSV[5] origin:064-gtp-channel-conf 31_506 +GTP_CHANNEL_0.GTPE2_CHANNEL.TST_RSV[6] origin:064-gtp-channel-conf 30_507 +GTP_CHANNEL_0.GTPE2_CHANNEL.TST_RSV[7] origin:064-gtp-channel-conf 31_507 +GTP_CHANNEL_0.GTPE2_CHANNEL.TST_RSV[8] origin:064-gtp-channel-conf 30_508 +GTP_CHANNEL_0.GTPE2_CHANNEL.TST_RSV[9] origin:064-gtp-channel-conf 31_508 +GTP_CHANNEL_0.GTPE2_CHANNEL.TST_RSV[10] origin:064-gtp-channel-conf 30_509 +GTP_CHANNEL_0.GTPE2_CHANNEL.TST_RSV[11] origin:064-gtp-channel-conf 31_509 +GTP_CHANNEL_0.GTPE2_CHANNEL.TST_RSV[12] origin:064-gtp-channel-conf 30_510 +GTP_CHANNEL_0.GTPE2_CHANNEL.TST_RSV[13] origin:064-gtp-channel-conf 31_510 +GTP_CHANNEL_0.GTPE2_CHANNEL.TST_RSV[14] origin:064-gtp-channel-conf 30_511 +GTP_CHANNEL_0.GTPE2_CHANNEL.TST_RSV[15] origin:064-gtp-channel-conf 31_511 +GTP_CHANNEL_0.GTPE2_CHANNEL.TST_RSV[16] origin:064-gtp-channel-conf 30_512 +GTP_CHANNEL_0.GTPE2_CHANNEL.TST_RSV[17] origin:064-gtp-channel-conf 31_512 +GTP_CHANNEL_0.GTPE2_CHANNEL.TST_RSV[18] origin:064-gtp-channel-conf 30_513 +GTP_CHANNEL_0.GTPE2_CHANNEL.TST_RSV[19] origin:064-gtp-channel-conf 31_513 +GTP_CHANNEL_0.GTPE2_CHANNEL.TST_RSV[20] origin:064-gtp-channel-conf 30_514 +GTP_CHANNEL_0.GTPE2_CHANNEL.TST_RSV[21] origin:064-gtp-channel-conf 31_514 +GTP_CHANNEL_0.GTPE2_CHANNEL.TST_RSV[22] origin:064-gtp-channel-conf 30_515 +GTP_CHANNEL_0.GTPE2_CHANNEL.TST_RSV[23] origin:064-gtp-channel-conf 31_515 +GTP_CHANNEL_0.GTPE2_CHANNEL.TST_RSV[24] origin:064-gtp-channel-conf 30_516 +GTP_CHANNEL_0.GTPE2_CHANNEL.TST_RSV[25] origin:064-gtp-channel-conf 31_516 +GTP_CHANNEL_0.GTPE2_CHANNEL.TST_RSV[26] origin:064-gtp-channel-conf 30_517 +GTP_CHANNEL_0.GTPE2_CHANNEL.TST_RSV[27] origin:064-gtp-channel-conf 31_517 +GTP_CHANNEL_0.GTPE2_CHANNEL.TST_RSV[28] origin:064-gtp-channel-conf 30_518 +GTP_CHANNEL_0.GTPE2_CHANNEL.TST_RSV[29] origin:064-gtp-channel-conf 31_518 +GTP_CHANNEL_0.GTPE2_CHANNEL.TST_RSV[30] origin:064-gtp-channel-conf 30_519 +GTP_CHANNEL_0.GTPE2_CHANNEL.TST_RSV[31] origin:064-gtp-channel-conf 31_519 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_CLKMUX_EN[0] origin:064-gtp-channel-conf 31_128 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_DATA_WIDTH[0] origin:064-gtp-channel-conf 30_152 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_DATA_WIDTH[1] origin:064-gtp-channel-conf 31_152 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_DATA_WIDTH[2] origin:064-gtp-channel-conf 30_153 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_DRIVE_MODE.PIPE origin:064-gtp-channel-conf 28_200 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_EIDLE_ASSERT_DELAY[0] origin:064-gtp-channel-conf 28_203 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_EIDLE_ASSERT_DELAY[1] origin:064-gtp-channel-conf 29_203 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_EIDLE_ASSERT_DELAY[2] origin:064-gtp-channel-conf 28_204 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_EIDLE_DEASSERT_DELAY[0] origin:064-gtp-channel-conf 29_204 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_EIDLE_DEASSERT_DELAY[1] origin:064-gtp-channel-conf 28_205 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_EIDLE_DEASSERT_DELAY[2] origin:064-gtp-channel-conf 29_205 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_LOOPBACK_DRIVE_HIZ origin:064-gtp-channel-conf 29_202 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_MAINCURSOR_SEL[0] origin:064-gtp-channel-conf 31_289 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_MARGIN_FULL_0[0] origin:064-gtp-channel-conf 30_232 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_MARGIN_FULL_0[1] origin:064-gtp-channel-conf 31_232 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_MARGIN_FULL_0[2] origin:064-gtp-channel-conf 30_233 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_MARGIN_FULL_0[3] origin:064-gtp-channel-conf 31_233 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_MARGIN_FULL_0[4] origin:064-gtp-channel-conf 30_234 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_MARGIN_FULL_0[5] origin:064-gtp-channel-conf 31_234 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_MARGIN_FULL_0[6] origin:064-gtp-channel-conf 30_235 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_MARGIN_FULL_1[0] origin:064-gtp-channel-conf 30_236 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_MARGIN_FULL_1[1] origin:064-gtp-channel-conf 31_236 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_MARGIN_FULL_1[2] origin:064-gtp-channel-conf 30_237 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_MARGIN_FULL_1[3] origin:064-gtp-channel-conf 31_237 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_MARGIN_FULL_1[4] origin:064-gtp-channel-conf 30_238 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_MARGIN_FULL_1[5] origin:064-gtp-channel-conf 31_238 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_MARGIN_FULL_1[6] origin:064-gtp-channel-conf 30_239 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_MARGIN_FULL_2[0] origin:064-gtp-channel-conf 30_240 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_MARGIN_FULL_2[1] origin:064-gtp-channel-conf 31_240 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_MARGIN_FULL_2[2] origin:064-gtp-channel-conf 30_241 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_MARGIN_FULL_2[3] origin:064-gtp-channel-conf 31_241 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_MARGIN_FULL_2[4] origin:064-gtp-channel-conf 30_242 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_MARGIN_FULL_2[5] origin:064-gtp-channel-conf 31_242 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_MARGIN_FULL_2[6] origin:064-gtp-channel-conf 30_243 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_MARGIN_FULL_3[0] origin:064-gtp-channel-conf 30_244 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_MARGIN_FULL_3[1] origin:064-gtp-channel-conf 31_244 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_MARGIN_FULL_3[2] origin:064-gtp-channel-conf 30_245 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_MARGIN_FULL_3[3] origin:064-gtp-channel-conf 31_245 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_MARGIN_FULL_3[4] origin:064-gtp-channel-conf 30_246 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_MARGIN_FULL_3[5] origin:064-gtp-channel-conf 31_246 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_MARGIN_FULL_3[6] origin:064-gtp-channel-conf 30_247 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_MARGIN_FULL_4[0] origin:064-gtp-channel-conf 30_248 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_MARGIN_FULL_4[1] origin:064-gtp-channel-conf 31_248 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_MARGIN_FULL_4[2] origin:064-gtp-channel-conf 30_249 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_MARGIN_FULL_4[3] origin:064-gtp-channel-conf 31_249 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_MARGIN_FULL_4[4] origin:064-gtp-channel-conf 30_250 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_MARGIN_FULL_4[5] origin:064-gtp-channel-conf 31_250 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_MARGIN_FULL_4[6] origin:064-gtp-channel-conf 30_251 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_MARGIN_LOW_0[0] origin:064-gtp-channel-conf 30_252 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_MARGIN_LOW_0[1] origin:064-gtp-channel-conf 31_252 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_MARGIN_LOW_0[2] origin:064-gtp-channel-conf 30_253 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_MARGIN_LOW_0[3] origin:064-gtp-channel-conf 31_253 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_MARGIN_LOW_0[4] origin:064-gtp-channel-conf 30_254 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_MARGIN_LOW_0[5] origin:064-gtp-channel-conf 31_254 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_MARGIN_LOW_0[6] origin:064-gtp-channel-conf 30_255 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_MARGIN_LOW_1[0] origin:064-gtp-channel-conf 30_256 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_MARGIN_LOW_1[1] origin:064-gtp-channel-conf 31_256 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_MARGIN_LOW_1[2] origin:064-gtp-channel-conf 30_257 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_MARGIN_LOW_1[3] origin:064-gtp-channel-conf 31_257 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_MARGIN_LOW_1[4] origin:064-gtp-channel-conf 30_258 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_MARGIN_LOW_1[5] origin:064-gtp-channel-conf 31_258 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_MARGIN_LOW_1[6] origin:064-gtp-channel-conf 30_259 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_MARGIN_LOW_2[0] origin:064-gtp-channel-conf 30_260 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_MARGIN_LOW_2[1] origin:064-gtp-channel-conf 31_260 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_MARGIN_LOW_2[2] origin:064-gtp-channel-conf 30_261 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_MARGIN_LOW_2[3] origin:064-gtp-channel-conf 31_261 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_MARGIN_LOW_2[4] origin:064-gtp-channel-conf 30_262 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_MARGIN_LOW_2[5] origin:064-gtp-channel-conf 31_262 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_MARGIN_LOW_2[6] origin:064-gtp-channel-conf 30_263 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_MARGIN_LOW_3[0] origin:064-gtp-channel-conf 30_264 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_MARGIN_LOW_3[1] origin:064-gtp-channel-conf 31_264 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_MARGIN_LOW_3[2] origin:064-gtp-channel-conf 30_265 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_MARGIN_LOW_3[3] origin:064-gtp-channel-conf 31_265 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_MARGIN_LOW_3[4] origin:064-gtp-channel-conf 30_266 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_MARGIN_LOW_3[5] origin:064-gtp-channel-conf 31_266 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_MARGIN_LOW_3[6] origin:064-gtp-channel-conf 30_267 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_MARGIN_LOW_4[0] origin:064-gtp-channel-conf 30_268 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_MARGIN_LOW_4[1] origin:064-gtp-channel-conf 31_268 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_MARGIN_LOW_4[2] origin:064-gtp-channel-conf 30_269 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_MARGIN_LOW_4[3] origin:064-gtp-channel-conf 31_269 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_MARGIN_LOW_4[4] origin:064-gtp-channel-conf 30_270 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_MARGIN_LOW_4[5] origin:064-gtp-channel-conf 31_270 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_MARGIN_LOW_4[6] origin:064-gtp-channel-conf 30_271 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_PREDRIVER_MODE[0] origin:064-gtp-channel-conf 28_206 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_RXDETECT_CFG[0] origin:064-gtp-channel-conf 30_296 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_RXDETECT_CFG[1] origin:064-gtp-channel-conf 31_296 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_RXDETECT_CFG[2] origin:064-gtp-channel-conf 30_297 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_RXDETECT_CFG[3] origin:064-gtp-channel-conf 31_297 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_RXDETECT_CFG[4] origin:064-gtp-channel-conf 30_298 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_RXDETECT_CFG[5] origin:064-gtp-channel-conf 31_298 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_RXDETECT_CFG[6] origin:064-gtp-channel-conf 30_299 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_RXDETECT_CFG[7] origin:064-gtp-channel-conf 31_299 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_RXDETECT_CFG[8] origin:064-gtp-channel-conf 30_300 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_RXDETECT_CFG[9] origin:064-gtp-channel-conf 31_300 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_RXDETECT_CFG[10] origin:064-gtp-channel-conf 30_301 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_RXDETECT_CFG[11] origin:064-gtp-channel-conf 31_301 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_RXDETECT_CFG[12] origin:064-gtp-channel-conf 30_302 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_RXDETECT_CFG[13] origin:064-gtp-channel-conf 31_302 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_RXDETECT_REF[0] origin:064-gtp-channel-conf 30_292 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_RXDETECT_REF[1] origin:064-gtp-channel-conf 31_292 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_RXDETECT_REF[2] origin:064-gtp-channel-conf 30_293 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_XCLK_SEL.TXUSR origin:064-gtp-channel-conf 31_11 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_CLK25_DIV[0] origin:064-gtp-channel-conf 30_144 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_CLK25_DIV[1] origin:064-gtp-channel-conf 31_144 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_CLK25_DIV[2] origin:064-gtp-channel-conf 30_145 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_CLK25_DIV[3] origin:064-gtp-channel-conf 31_145 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_CLK25_DIV[4] origin:064-gtp-channel-conf 30_146 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_DEEMPH0[0] origin:064-gtp-channel-conf 30_272 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_DEEMPH0[1] origin:064-gtp-channel-conf 31_272 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_DEEMPH0[2] origin:064-gtp-channel-conf 30_273 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_DEEMPH0[3] origin:064-gtp-channel-conf 31_273 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_DEEMPH0[4] origin:064-gtp-channel-conf 30_274 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_DEEMPH0[5] origin:064-gtp-channel-conf 31_274 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_DEEMPH1[0] origin:064-gtp-channel-conf 30_276 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_DEEMPH1[1] origin:064-gtp-channel-conf 31_276 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_DEEMPH1[2] origin:064-gtp-channel-conf 30_277 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_DEEMPH1[3] origin:064-gtp-channel-conf 31_277 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_DEEMPH1[4] origin:064-gtp-channel-conf 30_278 +GTP_CHANNEL_0.GTPE2_CHANNEL.TX_DEEMPH1[5] origin:064-gtp-channel-conf 31_278 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXBUF_EN origin:064-gtp-channel-conf 28_231 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXBUF_RESET_ON_RATE_CHANGE origin:064-gtp-channel-conf 29_231 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXDLY_CFG[0] origin:064-gtp-channel-conf 30_80 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXDLY_CFG[1] origin:064-gtp-channel-conf 31_80 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXDLY_CFG[2] origin:064-gtp-channel-conf 30_81 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXDLY_CFG[3] origin:064-gtp-channel-conf 31_81 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXDLY_CFG[4] origin:064-gtp-channel-conf 30_82 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXDLY_CFG[5] origin:064-gtp-channel-conf 31_82 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXDLY_CFG[6] origin:064-gtp-channel-conf 30_83 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXDLY_CFG[7] origin:064-gtp-channel-conf 31_83 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXDLY_CFG[8] origin:064-gtp-channel-conf 30_84 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXDLY_CFG[9] origin:064-gtp-channel-conf 31_84 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXDLY_CFG[10] origin:064-gtp-channel-conf 30_85 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXDLY_CFG[11] origin:064-gtp-channel-conf 31_85 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXDLY_CFG[12] origin:064-gtp-channel-conf 30_86 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXDLY_CFG[13] origin:064-gtp-channel-conf 31_86 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXDLY_CFG[14] origin:064-gtp-channel-conf 30_87 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXDLY_CFG[15] origin:064-gtp-channel-conf 31_87 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXDLY_LCFG[0] origin:064-gtp-channel-conf 30_568 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXDLY_LCFG[1] origin:064-gtp-channel-conf 31_568 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXDLY_LCFG[2] origin:064-gtp-channel-conf 30_569 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXDLY_LCFG[3] origin:064-gtp-channel-conf 31_569 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXDLY_LCFG[4] origin:064-gtp-channel-conf 30_570 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXDLY_LCFG[5] origin:064-gtp-channel-conf 31_570 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXDLY_LCFG[6] origin:064-gtp-channel-conf 30_571 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXDLY_LCFG[7] origin:064-gtp-channel-conf 31_571 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXDLY_LCFG[8] origin:064-gtp-channel-conf 30_572 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXDLY_TAP_CFG[0] origin:064-gtp-channel-conf 30_88 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXDLY_TAP_CFG[1] origin:064-gtp-channel-conf 31_88 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXDLY_TAP_CFG[2] origin:064-gtp-channel-conf 30_89 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXDLY_TAP_CFG[3] origin:064-gtp-channel-conf 31_89 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXDLY_TAP_CFG[4] origin:064-gtp-channel-conf 30_90 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXDLY_TAP_CFG[5] origin:064-gtp-channel-conf 31_90 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXDLY_TAP_CFG[6] origin:064-gtp-channel-conf 30_91 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXDLY_TAP_CFG[7] origin:064-gtp-channel-conf 31_91 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXDLY_TAP_CFG[8] origin:064-gtp-channel-conf 30_92 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXDLY_TAP_CFG[9] origin:064-gtp-channel-conf 31_92 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXDLY_TAP_CFG[10] origin:064-gtp-channel-conf 30_93 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXDLY_TAP_CFG[11] origin:064-gtp-channel-conf 31_93 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXDLY_TAP_CFG[12] origin:064-gtp-channel-conf 30_94 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXDLY_TAP_CFG[13] origin:064-gtp-channel-conf 31_94 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXDLY_TAP_CFG[14] origin:064-gtp-channel-conf 30_95 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXDLY_TAP_CFG[15] origin:064-gtp-channel-conf 31_95 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXGEARBOX_EN origin:064-gtp-channel-conf 29_226 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXOOB_CFG[0] origin:064-gtp-channel-conf 31_20 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXOUT_DIV[0] origin:064-gtp-channel-conf 30_386 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXOUT_DIV[1] origin:064-gtp-channel-conf 31_386 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPCSRESET_TIME[0] origin:064-gtp-channel-conf 29_130 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPCSRESET_TIME[1] origin:064-gtp-channel-conf 28_131 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPCSRESET_TIME[2] origin:064-gtp-channel-conf 29_131 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPCSRESET_TIME[3] origin:064-gtp-channel-conf 28_132 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPCSRESET_TIME[4] origin:064-gtp-channel-conf 29_132 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPH_CFG[0] origin:064-gtp-channel-conf 30_96 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPH_CFG[1] origin:064-gtp-channel-conf 31_96 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPH_CFG[2] origin:064-gtp-channel-conf 30_97 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPH_CFG[3] origin:064-gtp-channel-conf 31_97 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPH_CFG[4] origin:064-gtp-channel-conf 30_98 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPH_CFG[5] origin:064-gtp-channel-conf 31_98 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPH_CFG[6] origin:064-gtp-channel-conf 30_99 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPH_CFG[7] origin:064-gtp-channel-conf 31_99 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPH_CFG[8] origin:064-gtp-channel-conf 30_100 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPH_CFG[9] origin:064-gtp-channel-conf 31_100 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPH_CFG[10] origin:064-gtp-channel-conf 30_101 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPH_CFG[11] origin:064-gtp-channel-conf 31_101 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPH_CFG[12] origin:064-gtp-channel-conf 30_102 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPH_CFG[13] origin:064-gtp-channel-conf 31_102 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPH_CFG[14] origin:064-gtp-channel-conf 30_103 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPH_CFG[15] origin:064-gtp-channel-conf 31_103 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPH_MONITOR_SEL[0] origin:064-gtp-channel-conf 30_108 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPH_MONITOR_SEL[1] origin:064-gtp-channel-conf 31_108 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPH_MONITOR_SEL[2] origin:064-gtp-channel-conf 30_109 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPH_MONITOR_SEL[3] origin:064-gtp-channel-conf 31_109 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPH_MONITOR_SEL[4] origin:064-gtp-channel-conf 30_110 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPHDLY_CFG[0] origin:064-gtp-channel-conf 30_64 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPHDLY_CFG[1] origin:064-gtp-channel-conf 31_64 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPHDLY_CFG[2] origin:064-gtp-channel-conf 30_65 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPHDLY_CFG[3] origin:064-gtp-channel-conf 31_65 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPHDLY_CFG[4] origin:064-gtp-channel-conf 30_66 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPHDLY_CFG[5] origin:064-gtp-channel-conf 31_66 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPHDLY_CFG[6] origin:064-gtp-channel-conf 30_67 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPHDLY_CFG[7] origin:064-gtp-channel-conf 31_67 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPHDLY_CFG[8] origin:064-gtp-channel-conf 30_68 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPHDLY_CFG[9] origin:064-gtp-channel-conf 31_68 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPHDLY_CFG[10] origin:064-gtp-channel-conf 30_69 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPHDLY_CFG[11] origin:064-gtp-channel-conf 31_69 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPHDLY_CFG[12] origin:064-gtp-channel-conf 30_70 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPHDLY_CFG[13] origin:064-gtp-channel-conf 31_70 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPHDLY_CFG[14] origin:064-gtp-channel-conf 30_71 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPHDLY_CFG[15] origin:064-gtp-channel-conf 31_71 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPHDLY_CFG[16] origin:064-gtp-channel-conf 30_72 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPHDLY_CFG[17] origin:064-gtp-channel-conf 31_72 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPHDLY_CFG[18] origin:064-gtp-channel-conf 30_73 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPHDLY_CFG[19] origin:064-gtp-channel-conf 31_73 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPHDLY_CFG[20] origin:064-gtp-channel-conf 30_74 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPHDLY_CFG[21] origin:064-gtp-channel-conf 31_74 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPHDLY_CFG[22] origin:064-gtp-channel-conf 30_75 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPHDLY_CFG[23] origin:064-gtp-channel-conf 31_75 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPI_GREY_SEL[0] origin:064-gtp-channel-conf 31_498 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPI_INVSTROBE_SEL[0] origin:064-gtp-channel-conf 30_498 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPI_PPM_CFG[0] origin:064-gtp-channel-conf 30_488 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPI_PPM_CFG[1] origin:064-gtp-channel-conf 31_488 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPI_PPM_CFG[2] origin:064-gtp-channel-conf 30_489 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPI_PPM_CFG[3] origin:064-gtp-channel-conf 31_489 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPI_PPM_CFG[4] origin:064-gtp-channel-conf 30_490 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPI_PPM_CFG[5] origin:064-gtp-channel-conf 31_490 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPI_PPM_CFG[6] origin:064-gtp-channel-conf 30_491 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPI_PPM_CFG[7] origin:064-gtp-channel-conf 31_491 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPI_PPMCLK_SEL.TXUSRCLK2 origin:064-gtp-channel-conf 31_497 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPI_SYNFREQ_PPM[0] origin:064-gtp-channel-conf 30_496 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPI_SYNFREQ_PPM[1] origin:064-gtp-channel-conf 31_496 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPI_SYNFREQ_PPM[2] origin:064-gtp-channel-conf 30_497 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPI_CFG0[0] origin:064-gtp-channel-conf 30_40 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPI_CFG0[1] origin:064-gtp-channel-conf 31_40 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPI_CFG1[0] origin:064-gtp-channel-conf 30_41 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPI_CFG1[1] origin:064-gtp-channel-conf 31_41 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPI_CFG2[0] origin:064-gtp-channel-conf 30_42 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPI_CFG2[1] origin:064-gtp-channel-conf 31_42 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPI_CFG3[0] origin:064-gtp-channel-conf 30_43 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPI_CFG4[0] origin:064-gtp-channel-conf 31_43 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPI_CFG5[0] origin:064-gtp-channel-conf 30_44 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPI_CFG5[1] origin:064-gtp-channel-conf 31_44 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPI_CFG5[2] origin:064-gtp-channel-conf 30_45 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPMARESET_TIME[0] origin:064-gtp-channel-conf 28_128 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPMARESET_TIME[1] origin:064-gtp-channel-conf 29_128 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPMARESET_TIME[2] origin:064-gtp-channel-conf 28_129 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPMARESET_TIME[3] origin:064-gtp-channel-conf 29_129 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXPMARESET_TIME[4] origin:064-gtp-channel-conf 28_130 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXSYNC_MULTILANE[0] origin:064-gtp-channel-conf 29_133 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXSYNC_OVRD[0] origin:064-gtp-channel-conf 28_135 +GTP_CHANNEL_0.GTPE2_CHANNEL.TXSYNC_SKIP_DA[0] origin:064-gtp-channel-conf 28_134 +GTP_CHANNEL_0.GTPE2_CHANNEL.UCODEER_CLR[0] origin:064-gtp-channel-conf 29_00 +GTP_CHANNEL_0.GTPE2_CHANNEL.USE_PCS_CLK_PHASE_SEL[0] origin:064-gtp-channel-conf 30_463 diff --git a/artix7/segbits_gtp_channel_0_mid_left.db b/artix7/segbits_gtp_channel_0_mid_left.db index 464880a..d4d2c96 100644 --- a/artix7/segbits_gtp_channel_0_mid_left.db +++ b/artix7/segbits_gtp_channel_0_mid_left.db @@ -1,1627 +1,1627 @@ -GTP_CHANNEL_0_MID_LEFT.GTPE2.ACJTAG_DEBUG_MODE[0] 00_07 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ACJTAG_MODE[0] 01_06 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ACJTAG_RESET[0] 01_07 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ADAPT_CFG0[0] 02_464 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ADAPT_CFG0[1] 03_464 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ADAPT_CFG0[2] 02_465 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ADAPT_CFG0[3] 03_465 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ADAPT_CFG0[4] 02_466 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ADAPT_CFG0[5] 03_466 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ADAPT_CFG0[6] 02_467 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ADAPT_CFG0[7] 03_467 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ADAPT_CFG0[8] 02_468 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ADAPT_CFG0[9] 03_468 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ADAPT_CFG0[10] 02_469 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ADAPT_CFG0[11] 03_469 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ADAPT_CFG0[12] 02_470 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ADAPT_CFG0[13] 03_470 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ADAPT_CFG0[14] 02_471 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ADAPT_CFG0[15] 03_471 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ADAPT_CFG0[16] 02_472 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ADAPT_CFG0[17] 03_472 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ADAPT_CFG0[18] 02_473 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ADAPT_CFG0[19] 03_473 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ALIGN_COMMA_DOUBLE 00_522 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ALIGN_COMMA_ENABLE[0] 00_496 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ALIGN_COMMA_ENABLE[1] 01_496 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ALIGN_COMMA_ENABLE[2] 00_497 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ALIGN_COMMA_ENABLE[3] 01_497 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ALIGN_COMMA_ENABLE[4] 00_498 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ALIGN_COMMA_ENABLE[5] 01_498 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ALIGN_COMMA_ENABLE[6] 00_499 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ALIGN_COMMA_ENABLE[7] 01_499 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ALIGN_COMMA_ENABLE[8] 00_500 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ALIGN_COMMA_ENABLE[9] 01_500 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ALIGN_COMMA_WORD[0] 01_526 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ALIGN_COMMA_WORD[1] 00_527 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ALIGN_MCOMMA_DET 00_523 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ALIGN_MCOMMA_VALUE[0] 00_504 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ALIGN_MCOMMA_VALUE[1] 01_504 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ALIGN_MCOMMA_VALUE[2] 00_505 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ALIGN_MCOMMA_VALUE[3] 01_505 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ALIGN_MCOMMA_VALUE[4] 00_506 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ALIGN_MCOMMA_VALUE[5] 01_506 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ALIGN_MCOMMA_VALUE[6] 00_507 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ALIGN_MCOMMA_VALUE[7] 01_507 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ALIGN_MCOMMA_VALUE[8] 00_508 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ALIGN_MCOMMA_VALUE[9] 01_508 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ALIGN_PCOMMA_DET 01_523 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ALIGN_PCOMMA_VALUE[0] 00_512 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ALIGN_PCOMMA_VALUE[1] 01_512 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ALIGN_PCOMMA_VALUE[2] 00_513 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ALIGN_PCOMMA_VALUE[3] 01_513 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ALIGN_PCOMMA_VALUE[4] 00_514 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ALIGN_PCOMMA_VALUE[5] 01_514 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ALIGN_PCOMMA_VALUE[6] 00_515 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ALIGN_PCOMMA_VALUE[7] 01_515 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ALIGN_PCOMMA_VALUE[8] 00_516 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ALIGN_PCOMMA_VALUE[9] 01_516 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CBCC_DATA_SOURCE_SEL.DECODED 01_661 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CFOK_CFG[0] 02_392 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CFOK_CFG[1] 03_392 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CFOK_CFG[2] 02_393 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CFOK_CFG[3] 03_393 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CFOK_CFG[4] 02_394 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CFOK_CFG[5] 03_394 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CFOK_CFG[6] 02_395 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CFOK_CFG[7] 03_395 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CFOK_CFG[8] 02_396 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CFOK_CFG[9] 03_396 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CFOK_CFG[10] 02_397 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CFOK_CFG[11] 03_397 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CFOK_CFG[12] 02_398 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CFOK_CFG[13] 03_398 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CFOK_CFG[14] 02_399 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CFOK_CFG[15] 03_399 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CFOK_CFG[16] 02_400 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CFOK_CFG[17] 03_400 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CFOK_CFG[18] 02_401 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CFOK_CFG[19] 03_401 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CFOK_CFG[20] 02_402 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CFOK_CFG[21] 03_402 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CFOK_CFG[22] 02_403 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CFOK_CFG[23] 03_403 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CFOK_CFG[24] 02_404 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CFOK_CFG[25] 03_404 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CFOK_CFG[26] 02_405 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CFOK_CFG[27] 03_405 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CFOK_CFG[28] 02_406 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CFOK_CFG[29] 03_406 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CFOK_CFG[30] 02_407 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CFOK_CFG[31] 03_407 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CFOK_CFG[32] 02_408 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CFOK_CFG[33] 03_408 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CFOK_CFG[34] 02_409 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CFOK_CFG[35] 03_409 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CFOK_CFG[36] 02_410 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CFOK_CFG[37] 03_410 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CFOK_CFG[38] 02_411 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CFOK_CFG[39] 03_411 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CFOK_CFG[40] 02_412 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CFOK_CFG[41] 03_412 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CFOK_CFG[42] 02_413 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CFOK_CFG2[0] 02_459 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CFOK_CFG2[1] 03_459 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CFOK_CFG2[2] 02_460 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CFOK_CFG2[3] 03_460 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CFOK_CFG2[4] 02_461 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CFOK_CFG2[5] 03_461 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CFOK_CFG2[6] 02_462 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CFOK_CFG3[0] 02_416 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CFOK_CFG3[1] 03_416 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CFOK_CFG3[2] 02_417 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CFOK_CFG3[3] 03_417 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CFOK_CFG3[4] 02_418 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CFOK_CFG3[5] 03_418 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CFOK_CFG3[6] 02_419 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CFOK_CFG4[0] 03_438 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CFOK_CFG5[0] 02_429 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CFOK_CFG5[1] 03_429 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CFOK_CFG6[0] 03_436 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CFOK_CFG6[1] 02_437 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CFOK_CFG6[2] 03_437 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CFOK_CFG6[3] 02_438 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_KEEP_ALIGN 01_631 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_MAX_SKEW[0] 00_670 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_MAX_SKEW[1] 01_670 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_MAX_SKEW[2] 00_671 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_MAX_SKEW[3] 01_671 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_1[0] 00_608 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_1[1] 01_608 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_1[2] 00_609 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_1[3] 01_609 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_1[4] 00_610 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_1[5] 01_610 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_1[6] 00_611 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_1[7] 01_611 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_1[8] 00_612 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_1[9] 01_612 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_2[0] 00_616 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_2[1] 01_616 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_2[2] 00_617 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_2[3] 01_617 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_2[4] 00_618 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_2[5] 01_618 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_2[6] 00_619 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_2[7] 01_619 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_2[8] 00_620 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_2[9] 01_620 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_3[0] 00_624 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_3[1] 01_624 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_3[2] 00_625 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_3[3] 01_625 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_3[4] 00_626 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_3[5] 01_626 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_3[6] 00_627 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_3[7] 01_627 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_3[8] 00_628 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_3[9] 01_628 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_4[0] 00_632 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_4[1] 01_632 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_4[2] 00_633 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_4[3] 01_633 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_4[4] 00_634 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_4[5] 01_634 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_4[6] 00_635 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_4[7] 01_635 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_4[8] 00_636 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_4[9] 01_636 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_ENABLE[0] 00_614 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_ENABLE[1] 01_614 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_ENABLE[2] 00_615 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_ENABLE[3] 01_615 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_1[0] 00_640 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_1[1] 01_640 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_1[2] 00_641 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_1[3] 01_641 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_1[4] 00_642 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_1[5] 01_642 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_1[6] 00_643 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_1[7] 01_643 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_1[8] 00_644 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_1[9] 01_644 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_2[0] 00_648 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_2[1] 01_648 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_2[2] 00_649 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_2[3] 01_649 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_2[4] 00_650 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_2[5] 01_650 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_2[6] 00_651 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_2[7] 01_651 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_2[8] 00_652 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_2[9] 01_652 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_3[0] 00_656 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_3[1] 01_656 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_3[2] 00_657 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_3[3] 01_657 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_3[4] 00_658 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_3[5] 01_658 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_3[6] 00_659 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_3[7] 01_659 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_3[8] 00_660 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_3[9] 01_660 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_4[0] 00_664 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_4[1] 01_664 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_4[2] 00_665 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_4[3] 01_665 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_4[4] 00_666 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_4[5] 01_666 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_4[6] 00_667 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_4[7] 01_667 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_4[8] 00_668 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_4[9] 01_668 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_ENABLE[0] 00_646 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_ENABLE[1] 01_646 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_ENABLE[2] 00_647 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_ENABLE[3] 01_647 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_USE 01_645 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_LEN[0] 00_623 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_LEN[1] 01_623 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COMMON_SWING[0] 03_311 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_KEEP_IDLE 00_591 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_MAX_LAT[0] 00_557 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_MAX_LAT[1] 01_557 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_MAX_LAT[2] 00_558 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_MAX_LAT[3] 01_558 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_MAX_LAT[4] 00_559 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_MAX_LAT[5] 01_559 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_MIN_LAT[0] 00_565 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_MIN_LAT[1] 01_565 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_MIN_LAT[2] 00_566 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_MIN_LAT[3] 01_566 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_MIN_LAT[4] 00_567 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_MIN_LAT[5] 01_567 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_PRECEDENCE 00_590 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_REPEAT_WAIT[0] 00_573 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_REPEAT_WAIT[1] 01_573 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_REPEAT_WAIT[2] 00_574 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_REPEAT_WAIT[3] 01_574 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_REPEAT_WAIT[4] 00_575 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_1_1[0] 00_544 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_1_1[1] 01_544 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_1_1[2] 00_545 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_1_1[3] 01_545 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_1_1[4] 00_546 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_1_1[5] 01_546 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_1_1[6] 00_547 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_1_1[7] 01_547 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_1_1[8] 00_548 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_1_1[9] 01_548 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_1_2[0] 00_552 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_1_2[1] 01_552 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_1_2[2] 00_553 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_1_2[3] 01_553 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_1_2[4] 00_554 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_1_2[5] 01_554 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_1_2[6] 00_555 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_1_2[7] 01_555 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_1_2[8] 00_556 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_1_2[9] 01_556 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_1_3[0] 00_560 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_1_3[1] 01_560 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_1_3[2] 00_561 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_1_3[3] 01_561 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_1_3[4] 00_562 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_1_3[5] 01_562 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_1_3[6] 00_563 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_1_3[7] 01_563 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_1_3[8] 00_564 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_1_3[9] 01_564 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_1_4[0] 00_568 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_1_4[1] 01_568 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_1_4[2] 00_569 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_1_4[3] 01_569 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_1_4[4] 00_570 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_1_4[5] 01_570 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_1_4[6] 00_571 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_1_4[7] 01_571 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_1_4[8] 00_572 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_1_4[9] 01_572 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_1_ENABLE[0] 00_549 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_1_ENABLE[1] 01_549 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_1_ENABLE[2] 00_550 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_1_ENABLE[3] 01_550 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_2_1[0] 00_576 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_2_1[1] 01_576 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_2_1[2] 00_577 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_2_1[3] 01_577 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_2_1[4] 00_578 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_2_1[5] 01_578 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_2_1[6] 00_579 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_2_1[7] 01_579 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_2_1[8] 00_580 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_2_1[9] 01_580 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_2_2[0] 00_584 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_2_2[1] 01_584 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_2_2[2] 00_585 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_2_2[3] 01_585 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_2_2[4] 00_586 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_2_2[5] 01_586 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_2_2[6] 00_587 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_2_2[7] 01_587 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_2_2[8] 00_588 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_2_2[9] 01_588 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_2_3[0] 00_592 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_2_3[1] 01_592 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_2_3[2] 00_593 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_2_3[3] 01_593 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_2_3[4] 00_594 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_2_3[5] 01_594 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_2_3[6] 00_595 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_2_3[7] 01_595 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_2_3[8] 00_596 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_2_3[9] 01_596 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_2_4[0] 00_600 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_2_4[1] 01_600 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_2_4[2] 00_601 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_2_4[3] 01_601 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_2_4[4] 00_602 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_2_4[5] 01_602 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_2_4[6] 00_603 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_2_4[7] 01_603 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_2_4[8] 00_604 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_2_4[9] 01_604 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_2_ENABLE[0] 00_581 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_2_ENABLE[1] 01_581 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_2_ENABLE[2] 00_582 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_2_ENABLE[3] 01_582 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_2_USE 00_583 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_LEN[0] 00_589 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_LEN[1] 01_589 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_CORRECT_USE 00_551 -GTP_CHANNEL_0_MID_LEFT.GTPE2.DEC_MCOMMA_DETECT 01_494 -GTP_CHANNEL_0_MID_LEFT.GTPE2.DEC_PCOMMA_DETECT 00_495 -GTP_CHANNEL_0_MID_LEFT.GTPE2.DEC_VALID_COMMA_ONLY 00_494 -GTP_CHANNEL_0_MID_LEFT.GTPE2.DMONITOR_CFG[0] 02_368 -GTP_CHANNEL_0_MID_LEFT.GTPE2.DMONITOR_CFG[1] 03_368 -GTP_CHANNEL_0_MID_LEFT.GTPE2.DMONITOR_CFG[2] 02_369 -GTP_CHANNEL_0_MID_LEFT.GTPE2.DMONITOR_CFG[3] 03_369 -GTP_CHANNEL_0_MID_LEFT.GTPE2.DMONITOR_CFG[4] 02_370 -GTP_CHANNEL_0_MID_LEFT.GTPE2.DMONITOR_CFG[5] 03_370 -GTP_CHANNEL_0_MID_LEFT.GTPE2.DMONITOR_CFG[6] 02_371 -GTP_CHANNEL_0_MID_LEFT.GTPE2.DMONITOR_CFG[7] 03_371 -GTP_CHANNEL_0_MID_LEFT.GTPE2.DMONITOR_CFG[8] 02_372 -GTP_CHANNEL_0_MID_LEFT.GTPE2.DMONITOR_CFG[9] 03_372 -GTP_CHANNEL_0_MID_LEFT.GTPE2.DMONITOR_CFG[10] 02_373 -GTP_CHANNEL_0_MID_LEFT.GTPE2.DMONITOR_CFG[11] 03_373 -GTP_CHANNEL_0_MID_LEFT.GTPE2.DMONITOR_CFG[12] 02_374 -GTP_CHANNEL_0_MID_LEFT.GTPE2.DMONITOR_CFG[13] 03_374 -GTP_CHANNEL_0_MID_LEFT.GTPE2.DMONITOR_CFG[14] 02_375 -GTP_CHANNEL_0_MID_LEFT.GTPE2.DMONITOR_CFG[15] 03_375 -GTP_CHANNEL_0_MID_LEFT.GTPE2.DMONITOR_CFG[16] 02_376 -GTP_CHANNEL_0_MID_LEFT.GTPE2.DMONITOR_CFG[17] 03_376 -GTP_CHANNEL_0_MID_LEFT.GTPE2.DMONITOR_CFG[18] 02_377 -GTP_CHANNEL_0_MID_LEFT.GTPE2.DMONITOR_CFG[19] 03_377 -GTP_CHANNEL_0_MID_LEFT.GTPE2.DMONITOR_CFG[20] 02_378 -GTP_CHANNEL_0_MID_LEFT.GTPE2.DMONITOR_CFG[21] 03_378 -GTP_CHANNEL_0_MID_LEFT.GTPE2.DMONITOR_CFG[22] 02_379 -GTP_CHANNEL_0_MID_LEFT.GTPE2.DMONITOR_CFG[23] 03_379 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_CLK_PHASE_SEL[0] 03_463 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_CONTROL[0] 00_488 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_CONTROL[1] 01_488 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_CONTROL[2] 00_489 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_CONTROL[3] 01_489 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_CONTROL[4] 00_490 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_CONTROL[5] 01_490 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_ERRDET_EN 01_492 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_EYE_SCAN_EN 00_492 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_HORZ_OFFSET[0] 00_480 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_HORZ_OFFSET[1] 01_480 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_HORZ_OFFSET[2] 00_481 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_HORZ_OFFSET[3] 01_481 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_HORZ_OFFSET[4] 00_482 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_HORZ_OFFSET[5] 01_482 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_HORZ_OFFSET[6] 00_483 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_HORZ_OFFSET[7] 01_483 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_HORZ_OFFSET[8] 00_484 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_HORZ_OFFSET[9] 01_484 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_HORZ_OFFSET[10] 00_485 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_HORZ_OFFSET[11] 01_485 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_PMA_CFG[0] 02_624 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_PMA_CFG[1] 03_624 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_PMA_CFG[2] 02_625 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_PMA_CFG[3] 03_625 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_PMA_CFG[4] 02_626 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_PMA_CFG[5] 03_626 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_PMA_CFG[6] 02_627 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_PMA_CFG[7] 03_627 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_PMA_CFG[8] 02_628 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_PMA_CFG[9] 03_628 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_PRESCALE[0] 01_477 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_PRESCALE[1] 00_478 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_PRESCALE[2] 01_478 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_PRESCALE[3] 00_479 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_PRESCALE[4] 01_479 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[0] 00_392 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[1] 01_392 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[2] 00_393 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[3] 01_393 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[4] 00_394 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[5] 01_394 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[6] 00_395 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[7] 01_395 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[8] 00_396 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[9] 01_396 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[10] 00_397 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[11] 01_397 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[12] 00_398 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[13] 01_398 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[14] 00_399 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[15] 01_399 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[16] 00_400 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[17] 01_400 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[18] 00_401 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[19] 01_401 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[20] 00_402 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[21] 01_402 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[22] 00_403 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[23] 01_403 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[24] 00_404 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[25] 01_404 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[26] 00_405 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[27] 01_405 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[28] 00_406 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[29] 01_406 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[30] 00_407 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[31] 01_407 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[32] 00_408 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[33] 01_408 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[34] 00_409 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[35] 01_409 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[36] 00_410 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[37] 01_410 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[38] 00_411 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[39] 01_411 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[40] 00_412 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[41] 01_412 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[42] 00_413 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[43] 01_413 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[44] 00_414 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[45] 01_414 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[46] 00_415 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[47] 01_415 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[48] 00_416 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[49] 01_416 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[50] 00_417 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[51] 01_417 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[52] 00_418 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[53] 01_418 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[54] 00_419 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[55] 01_419 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[56] 00_420 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[57] 01_420 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[58] 00_421 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[59] 01_421 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[60] 00_422 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[61] 01_422 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[62] 00_423 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[63] 01_423 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[64] 00_424 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[65] 01_424 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[66] 00_425 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[67] 01_425 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[68] 00_426 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[69] 01_426 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[70] 00_427 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[71] 01_427 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[72] 00_428 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[73] 01_428 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[74] 00_429 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[75] 01_429 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[76] 00_430 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[77] 01_430 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[78] 00_431 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[79] 01_431 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[0] 00_352 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[1] 01_352 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[2] 00_353 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[3] 01_353 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[4] 00_354 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[5] 01_354 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[6] 00_355 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[7] 01_355 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[8] 00_356 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[9] 01_356 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[10] 00_357 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[11] 01_357 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[12] 00_358 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[13] 01_358 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[14] 00_359 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[15] 01_359 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[16] 00_360 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[17] 01_360 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[18] 00_361 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[19] 01_361 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[20] 00_362 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[21] 01_362 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[22] 00_363 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[23] 01_363 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[24] 00_364 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[25] 01_364 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[26] 00_365 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[27] 01_365 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[28] 00_366 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[29] 01_366 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[30] 00_367 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[31] 01_367 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[32] 00_368 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[33] 01_368 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[34] 00_369 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[35] 01_369 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[36] 00_370 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[37] 01_370 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[38] 00_371 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[39] 01_371 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[40] 00_372 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[41] 01_372 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[42] 00_373 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[43] 01_373 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[44] 00_374 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[45] 01_374 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[46] 00_375 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[47] 01_375 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[48] 00_376 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[49] 01_376 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[50] 00_377 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[51] 01_377 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[52] 00_378 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[53] 01_378 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[54] 00_379 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[55] 01_379 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[56] 00_380 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[57] 01_380 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[58] 00_381 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[59] 01_381 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[60] 00_382 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[61] 01_382 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[62] 00_383 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[63] 01_383 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[64] 00_384 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[65] 01_384 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[66] 00_385 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[67] 01_385 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[68] 00_386 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[69] 01_386 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[70] 00_387 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[71] 01_387 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[72] 00_388 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[73] 01_388 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[74] 00_389 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[75] 01_389 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[76] 00_390 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[77] 01_390 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[78] 00_391 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[79] 01_391 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[0] 00_432 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[1] 01_432 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[2] 00_433 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[3] 01_433 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[4] 00_434 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[5] 01_434 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[6] 00_435 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[7] 01_435 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[8] 00_436 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[9] 01_436 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[10] 00_437 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[11] 01_437 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[12] 00_438 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[13] 01_438 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[14] 00_439 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[15] 01_439 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[16] 00_440 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[17] 01_440 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[18] 00_441 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[19] 01_441 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[20] 00_442 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[21] 01_442 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[22] 00_443 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[23] 01_443 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[24] 00_444 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[25] 01_444 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[26] 00_445 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[27] 01_445 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[28] 00_446 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[29] 01_446 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[30] 00_447 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[31] 01_447 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[32] 00_448 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[33] 01_448 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[34] 00_449 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[35] 01_449 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[36] 00_450 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[37] 01_450 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[38] 00_451 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[39] 01_451 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[40] 00_452 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[41] 01_452 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[42] 00_453 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[43] 01_453 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[44] 00_454 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[45] 01_454 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[46] 00_455 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[47] 01_455 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[48] 00_456 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[49] 01_456 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[50] 00_457 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[51] 01_457 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[52] 00_458 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[53] 01_458 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[54] 00_459 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[55] 01_459 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[56] 00_460 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[57] 01_460 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[58] 00_461 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[59] 01_461 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[60] 00_462 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[61] 01_462 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[62] 00_463 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[63] 01_463 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[64] 00_464 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[65] 01_464 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[66] 00_465 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[67] 01_465 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[68] 00_466 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[69] 01_466 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[70] 00_467 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[71] 01_467 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[72] 00_468 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[73] 01_468 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[74] 00_469 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[75] 01_469 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[76] 00_470 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[77] 01_470 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[78] 00_471 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[79] 01_471 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_VERT_OFFSET[0] 00_472 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_VERT_OFFSET[1] 01_472 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_VERT_OFFSET[2] 00_473 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_VERT_OFFSET[3] 01_473 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_VERT_OFFSET[4] 00_474 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_VERT_OFFSET[5] 01_474 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_VERT_OFFSET[6] 00_475 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_VERT_OFFSET[7] 01_475 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_VERT_OFFSET[8] 00_476 -GTP_CHANNEL_0_MID_LEFT.GTPE2.FTS_DESKEW_SEQ_ENABLE[0] 00_662 -GTP_CHANNEL_0_MID_LEFT.GTPE2.FTS_DESKEW_SEQ_ENABLE[1] 01_662 -GTP_CHANNEL_0_MID_LEFT.GTPE2.FTS_DESKEW_SEQ_ENABLE[2] 00_663 -GTP_CHANNEL_0_MID_LEFT.GTPE2.FTS_DESKEW_SEQ_ENABLE[3] 01_663 -GTP_CHANNEL_0_MID_LEFT.GTPE2.FTS_LANE_DESKEW_CFG[0] 00_654 -GTP_CHANNEL_0_MID_LEFT.GTPE2.FTS_LANE_DESKEW_CFG[1] 01_654 -GTP_CHANNEL_0_MID_LEFT.GTPE2.FTS_LANE_DESKEW_CFG[2] 00_655 -GTP_CHANNEL_0_MID_LEFT.GTPE2.FTS_LANE_DESKEW_CFG[3] 01_655 -GTP_CHANNEL_0_MID_LEFT.GTPE2.FTS_LANE_DESKEW_EN 01_653 -GTP_CHANNEL_0_MID_LEFT.GTPE2.GEARBOX_MODE[0] 00_224 -GTP_CHANNEL_0_MID_LEFT.GTPE2.GEARBOX_MODE[1] 01_224 -GTP_CHANNEL_0_MID_LEFT.GTPE2.GEARBOX_MODE[2] 00_225 -GTP_CHANNEL_0_MID_LEFT.GTPE2.IN_USE 00_00 00_01 00_47 00_52 00_53 00_65 01_01 01_47 02_129 -GTP_CHANNEL_0_MID_LEFT.GTPE2.LOOPBACK_CFG[0] 02_20 -GTP_CHANNEL_0_MID_LEFT.GTPE2.OUTREFCLK_SEL_INV[0] 00_149 -GTP_CHANNEL_0_MID_LEFT.GTPE2.OUTREFCLK_SEL_INV[1] 01_149 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PCS_PCIE_EN 00_216 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PCS_RSVD_ATTR[0] 02_184 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PCS_RSVD_ATTR[1] 03_184 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PCS_RSVD_ATTR[2] 02_185 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PCS_RSVD_ATTR[3] 03_185 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PCS_RSVD_ATTR[4] 02_186 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PCS_RSVD_ATTR[5] 03_186 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PCS_RSVD_ATTR[6] 02_187 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PCS_RSVD_ATTR[7] 03_187 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PCS_RSVD_ATTR[8] 02_188 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PCS_RSVD_ATTR[9] 03_188 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PCS_RSVD_ATTR[10] 02_189 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PCS_RSVD_ATTR[11] 03_189 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PCS_RSVD_ATTR[12] 02_190 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PCS_RSVD_ATTR[13] 03_190 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PCS_RSVD_ATTR[14] 02_191 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PCS_RSVD_ATTR[15] 03_191 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PCS_RSVD_ATTR[16] 02_192 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PCS_RSVD_ATTR[17] 03_192 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PCS_RSVD_ATTR[18] 02_193 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PCS_RSVD_ATTR[19] 03_193 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PCS_RSVD_ATTR[20] 02_194 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PCS_RSVD_ATTR[21] 03_194 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PCS_RSVD_ATTR[22] 02_195 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PCS_RSVD_ATTR[23] 03_195 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PCS_RSVD_ATTR[24] 02_196 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PCS_RSVD_ATTR[25] 03_196 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PCS_RSVD_ATTR[26] 02_197 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PCS_RSVD_ATTR[27] 03_197 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PCS_RSVD_ATTR[28] 02_198 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PCS_RSVD_ATTR[29] 03_198 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PCS_RSVD_ATTR[30] 02_199 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PCS_RSVD_ATTR[31] 03_199 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PCS_RSVD_ATTR[32] 02_200 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PCS_RSVD_ATTR[33] 03_200 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PCS_RSVD_ATTR[34] 02_201 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PCS_RSVD_ATTR[35] 03_201 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PCS_RSVD_ATTR[36] 02_202 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PCS_RSVD_ATTR[37] 03_202 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PCS_RSVD_ATTR[38] 02_203 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PCS_RSVD_ATTR[39] 03_203 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PCS_RSVD_ATTR[40] 02_204 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PCS_RSVD_ATTR[41] 03_204 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PCS_RSVD_ATTR[42] 02_205 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PCS_RSVD_ATTR[43] 03_205 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PCS_RSVD_ATTR[44] 02_206 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PCS_RSVD_ATTR[45] 03_206 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PCS_RSVD_ATTR[46] 02_207 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PCS_RSVD_ATTR[47] 03_207 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PD_TRANS_TIME_FROM_P2[0] 01_216 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PD_TRANS_TIME_FROM_P2[1] 00_217 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PD_TRANS_TIME_FROM_P2[2] 01_217 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PD_TRANS_TIME_FROM_P2[3] 00_218 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PD_TRANS_TIME_FROM_P2[4] 01_218 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PD_TRANS_TIME_FROM_P2[5] 00_219 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PD_TRANS_TIME_FROM_P2[6] 01_219 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PD_TRANS_TIME_FROM_P2[7] 00_220 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PD_TRANS_TIME_FROM_P2[8] 01_220 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PD_TRANS_TIME_FROM_P2[9] 00_221 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PD_TRANS_TIME_FROM_P2[10] 01_221 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PD_TRANS_TIME_FROM_P2[11] 00_222 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PD_TRANS_TIME_NONE_P2[0] 00_208 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PD_TRANS_TIME_NONE_P2[1] 01_208 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PD_TRANS_TIME_NONE_P2[2] 00_209 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PD_TRANS_TIME_NONE_P2[3] 01_209 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PD_TRANS_TIME_NONE_P2[4] 00_210 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PD_TRANS_TIME_NONE_P2[5] 01_210 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PD_TRANS_TIME_NONE_P2[6] 00_211 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PD_TRANS_TIME_NONE_P2[7] 01_211 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PD_TRANS_TIME_TO_P2[0] 00_212 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PD_TRANS_TIME_TO_P2[1] 01_212 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PD_TRANS_TIME_TO_P2[2] 00_213 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PD_TRANS_TIME_TO_P2[3] 01_213 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PD_TRANS_TIME_TO_P2[4] 00_214 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PD_TRANS_TIME_TO_P2[5] 01_214 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PD_TRANS_TIME_TO_P2[6] 00_215 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PD_TRANS_TIME_TO_P2[7] 01_215 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PMA_LOOPBACK_CFG[0] 01_207 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PMA_RSV[0] 02_520 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PMA_RSV[1] 03_520 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PMA_RSV[2] 02_521 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PMA_RSV[3] 03_521 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PMA_RSV[4] 02_522 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PMA_RSV[5] 03_522 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PMA_RSV[6] 02_523 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PMA_RSV[7] 03_523 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PMA_RSV[8] 02_524 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PMA_RSV[9] 03_524 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PMA_RSV[10] 02_525 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PMA_RSV[11] 03_525 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PMA_RSV[12] 02_526 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PMA_RSV[13] 03_526 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PMA_RSV[14] 02_527 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PMA_RSV[15] 03_527 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PMA_RSV[16] 02_528 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PMA_RSV[17] 03_528 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PMA_RSV[18] 02_529 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PMA_RSV[19] 03_529 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PMA_RSV[20] 02_530 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PMA_RSV[21] 03_530 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PMA_RSV[22] 02_531 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PMA_RSV[23] 03_531 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PMA_RSV[24] 02_532 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PMA_RSV[25] 03_532 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PMA_RSV[26] 02_533 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PMA_RSV[27] 03_533 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PMA_RSV[28] 02_534 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PMA_RSV[29] 03_534 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PMA_RSV[30] 02_535 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PMA_RSV[31] 03_535 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PMA_RSV2[0] 02_336 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PMA_RSV2[1] 03_336 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PMA_RSV2[2] 02_337 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PMA_RSV2[3] 03_337 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PMA_RSV2[4] 02_338 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PMA_RSV2[5] 03_338 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PMA_RSV2[6] 02_339 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PMA_RSV2[7] 03_339 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PMA_RSV2[8] 02_340 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PMA_RSV2[9] 03_340 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PMA_RSV2[10] 02_341 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PMA_RSV2[11] 03_341 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PMA_RSV2[12] 02_342 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PMA_RSV2[13] 03_342 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PMA_RSV2[14] 02_343 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PMA_RSV2[15] 03_343 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PMA_RSV2[16] 02_344 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PMA_RSV2[17] 03_344 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PMA_RSV2[18] 02_345 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PMA_RSV2[19] 03_345 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PMA_RSV2[20] 02_346 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PMA_RSV2[21] 03_346 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PMA_RSV2[22] 02_347 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PMA_RSV2[23] 03_347 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PMA_RSV2[24] 02_348 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PMA_RSV2[25] 03_348 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PMA_RSV2[26] 02_349 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PMA_RSV2[27] 03_349 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PMA_RSV2[28] 02_350 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PMA_RSV2[29] 03_350 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PMA_RSV2[30] 02_351 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PMA_RSV2[31] 03_351 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PMA_RSV3[0] 02_288 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PMA_RSV3[1] 03_288 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PMA_RSV4[0] 02_156 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PMA_RSV4[1] 03_156 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PMA_RSV4[2] 02_157 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PMA_RSV4[3] 03_157 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PMA_RSV5[0] 03_159 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PMA_RSV6[0] 02_303 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PMA_RSV7[0] 03_303 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_BIAS_CFG[0] 02_112 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_BIAS_CFG[1] 03_112 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_BIAS_CFG[2] 02_113 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_BIAS_CFG[3] 03_113 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_BIAS_CFG[4] 02_114 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_BIAS_CFG[5] 03_114 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_BIAS_CFG[6] 02_115 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_BIAS_CFG[7] 03_115 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_BIAS_CFG[8] 02_116 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_BIAS_CFG[9] 03_116 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_BIAS_CFG[10] 02_117 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_BIAS_CFG[11] 03_117 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_BIAS_CFG[12] 02_118 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_BIAS_CFG[13] 03_118 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_BIAS_CFG[14] 02_119 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_BIAS_CFG[15] 03_119 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_BUFFER_CFG[0] 02_536 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_BUFFER_CFG[1] 03_536 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_BUFFER_CFG[2] 02_537 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_BUFFER_CFG[3] 03_537 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_BUFFER_CFG[4] 02_538 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_BUFFER_CFG[5] 03_538 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_CLKMUX_EN[0] 02_128 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_CM_SEL[0] 00_138 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_CM_SEL[1] 01_138 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_CM_TRIM[0] 02_304 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_CM_TRIM[1] 03_304 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_CM_TRIM[2] 02_305 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_CM_TRIM[3] 03_305 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_DATA_WIDTH[0] 01_141 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_DATA_WIDTH[1] 00_142 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_DATA_WIDTH[2] 01_142 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_DDI_SEL[0] 00_696 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_DDI_SEL[1] 01_696 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_DDI_SEL[2] 00_697 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_DDI_SEL[3] 01_697 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_DDI_SEL[4] 00_698 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_DDI_SEL[5] 01_698 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_DEBUG_CFG[0] 02_616 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_DEBUG_CFG[1] 03_616 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_DEBUG_CFG[2] 02_617 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_DEBUG_CFG[3] 03_617 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_DEBUG_CFG[4] 02_618 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_DEBUG_CFG[5] 03_618 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_DEBUG_CFG[6] 02_619 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_DEBUG_CFG[7] 03_619 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_DEBUG_CFG[8] 02_620 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_DEBUG_CFG[9] 03_620 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_DEBUG_CFG[10] 02_621 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_DEBUG_CFG[11] 03_621 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_DEBUG_CFG[12] 02_622 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_DEBUG_CFG[13] 03_622 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_DEFER_RESET_BUF_EN 02_552 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_DISPERR_SEQ_MATCH 01_495 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_OS_CFG[0] 00_288 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_OS_CFG[1] 01_288 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_OS_CFG[2] 00_289 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_OS_CFG[3] 01_289 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_OS_CFG[4] 00_290 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_OS_CFG[5] 01_290 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_OS_CFG[6] 00_291 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_OS_CFG[7] 01_291 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_OS_CFG[8] 00_292 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_OS_CFG[9] 01_292 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_OS_CFG[10] 00_293 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_OS_CFG[11] 01_293 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_OS_CFG[12] 00_294 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_SIG_VALID_DLY[0] 00_524 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_SIG_VALID_DLY[1] 01_524 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_SIG_VALID_DLY[2] 00_525 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_SIG_VALID_DLY[3] 01_525 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_SIG_VALID_DLY[4] 00_526 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_XCLK_SEL.RXUSR 00_143 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_CLK25_DIV[0] 00_139 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_CLK25_DIV[1] 01_139 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_CLK25_DIV[2] 00_140 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_CLK25_DIV[3] 01_140 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_CLK25_DIV[4] 00_141 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXBUF_ADDR_MODE.FAST 03_555 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXBUF_EIDLE_HI_CNT[0] 02_558 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXBUF_EIDLE_HI_CNT[1] 03_558 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXBUF_EIDLE_HI_CNT[2] 02_559 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXBUF_EIDLE_HI_CNT[3] 03_559 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXBUF_EIDLE_LO_CNT[0] 02_556 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXBUF_EIDLE_LO_CNT[1] 03_556 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXBUF_EIDLE_LO_CNT[2] 02_557 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXBUF_EIDLE_LO_CNT[3] 03_557 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXBUF_EN 02_11 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXBUF_RESET_ON_CB_CHANGE 02_560 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXBUF_RESET_ON_COMMAALIGN 02_561 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXBUF_RESET_ON_EIDLE 02_547 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXBUF_RESET_ON_RATE_CHANGE 03_560 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXBUF_THRESH_OVFLW[0] 03_552 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXBUF_THRESH_OVFLW[1] 02_553 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXBUF_THRESH_OVFLW[2] 03_553 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXBUF_THRESH_OVFLW[3] 02_554 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXBUF_THRESH_OVFLW[4] 03_554 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXBUF_THRESH_OVFLW[5] 02_555 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXBUF_THRESH_OVRD 02_548 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXBUF_THRESH_UNDFLW[0] 02_544 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXBUF_THRESH_UNDFLW[1] 03_544 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXBUF_THRESH_UNDFLW[2] 02_545 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXBUF_THRESH_UNDFLW[3] 03_545 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXBUF_THRESH_UNDFLW[4] 02_546 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXBUF_THRESH_UNDFLW[5] 03_546 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXBUFRESET_TIME[0] 01_101 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXBUFRESET_TIME[1] 00_102 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXBUFRESET_TIME[2] 01_102 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXBUFRESET_TIME[3] 00_103 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXBUFRESET_TIME[4] 01_103 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[0] 02_640 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[1] 03_640 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[2] 02_641 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[3] 03_641 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[4] 02_642 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[5] 03_642 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[6] 02_643 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[7] 03_643 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[8] 02_644 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[9] 03_644 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[10] 02_645 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[11] 03_645 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[12] 02_646 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[13] 03_646 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[14] 02_647 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[15] 03_647 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[16] 02_648 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[17] 03_648 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[18] 02_649 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[19] 03_649 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[20] 02_650 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[21] 03_650 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[22] 02_651 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[23] 03_651 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[24] 02_652 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[25] 03_652 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[26] 02_653 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[27] 03_653 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[28] 02_654 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[29] 03_654 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[30] 02_655 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[31] 03_655 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[32] 02_656 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[33] 03_656 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[34] 02_657 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[35] 03_657 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[36] 02_658 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[37] 03_658 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[38] 02_659 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[39] 03_659 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[40] 02_660 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[41] 03_660 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[42] 02_661 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[43] 03_661 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[44] 02_662 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[45] 03_662 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[46] 02_663 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[47] 03_663 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[48] 02_664 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[49] 03_664 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[50] 02_665 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[51] 03_665 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[52] 02_666 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[53] 03_666 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[54] 02_667 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[55] 03_667 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[56] 02_668 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[57] 03_668 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[58] 02_669 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[59] 03_669 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[60] 02_670 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[61] 03_670 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[62] 02_671 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[63] 03_671 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[64] 02_672 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[65] 03_672 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[66] 02_673 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[67] 03_673 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[68] 02_674 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[69] 03_674 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[70] 02_675 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[71] 03_675 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[72] 02_676 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[73] 03_676 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[74] 02_677 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[75] 03_677 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[76] 02_678 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[77] 03_678 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[78] 02_679 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[79] 03_679 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[80] 02_680 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[81] 03_680 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[82] 02_681 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_FR_RESET_ON_EIDLE[0] 02_638 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_HOLD_DURING_EIDLE[0] 03_637 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_LOCK_CFG[0] 02_632 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_LOCK_CFG[1] 03_632 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_LOCK_CFG[2] 02_633 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_LOCK_CFG[3] 03_633 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_LOCK_CFG[4] 02_634 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_LOCK_CFG[5] 03_634 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_PH_RESET_ON_EIDLE[0] 03_638 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDRFREQRESET_TIME[0] 01_106 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDRFREQRESET_TIME[1] 00_107 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDRFREQRESET_TIME[2] 01_107 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDRFREQRESET_TIME[3] 00_108 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDRFREQRESET_TIME[4] 01_108 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDRPHRESET_TIME[0] 00_109 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDRPHRESET_TIME[1] 01_109 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDRPHRESET_TIME[2] 00_110 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDRPHRESET_TIME[3] 01_110 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDRPHRESET_TIME[4] 00_111 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXDLY_CFG[0] 00_680 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXDLY_CFG[1] 01_680 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXDLY_CFG[2] 00_681 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXDLY_CFG[3] 01_681 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXDLY_CFG[4] 00_682 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXDLY_CFG[5] 01_682 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXDLY_CFG[6] 00_683 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXDLY_CFG[7] 01_683 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXDLY_CFG[8] 00_684 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXDLY_CFG[9] 01_684 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXDLY_CFG[10] 00_685 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXDLY_CFG[11] 01_685 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXDLY_CFG[12] 00_686 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXDLY_CFG[13] 01_686 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXDLY_CFG[14] 00_687 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXDLY_CFG[15] 01_687 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXDLY_LCFG[0] 02_576 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXDLY_LCFG[1] 03_576 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXDLY_LCFG[2] 02_577 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXDLY_LCFG[3] 03_577 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXDLY_LCFG[4] 02_578 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXDLY_LCFG[5] 03_578 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXDLY_LCFG[6] 02_579 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXDLY_LCFG[7] 03_579 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXDLY_LCFG[8] 02_580 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXDLY_TAP_CFG[0] 00_672 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXDLY_TAP_CFG[1] 01_672 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXDLY_TAP_CFG[2] 00_673 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXDLY_TAP_CFG[3] 01_673 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXDLY_TAP_CFG[4] 00_674 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXDLY_TAP_CFG[5] 01_674 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXDLY_TAP_CFG[6] 00_675 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXDLY_TAP_CFG[7] 01_675 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXDLY_TAP_CFG[8] 00_676 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXDLY_TAP_CFG[9] 01_676 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXDLY_TAP_CFG[10] 00_677 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXDLY_TAP_CFG[11] 01_677 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXDLY_TAP_CFG[12] 00_678 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXDLY_TAP_CFG[13] 01_678 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXDLY_TAP_CFG[14] 00_679 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXDLY_TAP_CFG[15] 01_679 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXGEARBOX_EN 01_607 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXISCANRESET_TIME[0] 01_123 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXISCANRESET_TIME[1] 00_124 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXISCANRESET_TIME[2] 01_124 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXISCANRESET_TIME[3] 00_125 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXISCANRESET_TIME[4] 01_125 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPM_BIAS_STARTUP_DISABLE[0] 03_391 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPM_CFG[0] 02_328 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPM_CFG[1] 03_328 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPM_CFG[2] 02_329 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPM_CFG[3] 03_329 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPM_CM_CFG[0] 02_430 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPM_GC_CFG[0] 02_432 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPM_GC_CFG[1] 03_432 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPM_GC_CFG[2] 02_433 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPM_GC_CFG[3] 03_433 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPM_GC_CFG[4] 02_434 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPM_GC_CFG[5] 03_434 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPM_GC_CFG[6] 02_435 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPM_GC_CFG[7] 03_435 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPM_GC_CFG[8] 02_436 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPM_GC_CFG2[0] 03_442 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPM_GC_CFG2[1] 02_443 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPM_GC_CFG2[2] 03_443 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPM_HF_CFG[0] 00_336 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPM_HF_CFG[1] 01_336 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPM_HF_CFG[2] 00_337 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPM_HF_CFG[3] 01_337 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPM_HF_CFG[4] 00_338 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPM_HF_CFG[5] 01_338 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPM_HF_CFG[6] 00_339 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPM_HF_CFG[7] 01_339 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPM_HF_CFG[8] 00_340 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPM_HF_CFG[9] 01_340 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPM_HF_CFG[10] 00_341 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPM_HF_CFG[11] 01_341 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPM_HF_CFG[12] 00_342 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPM_HF_CFG[13] 01_342 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPM_HF_CFG2[0] 02_424 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPM_HF_CFG2[1] 03_424 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPM_HF_CFG2[2] 02_425 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPM_HF_CFG2[3] 03_425 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPM_HF_CFG2[4] 02_426 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPM_HF_CFG3[0] 03_389 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPM_HF_CFG3[1] 02_390 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPM_HF_CFG3[2] 03_390 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPM_HF_CFG3[3] 02_391 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPM_HOLD_DURING_EIDLE[0] 00_247 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPM_INCM_CFG[0] 02_439 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPM_IPCM_CFG[0] 03_439 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPM_LF_CFG[0] 00_344 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPM_LF_CFG[1] 01_344 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPM_LF_CFG[2] 00_345 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPM_LF_CFG[3] 01_345 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPM_LF_CFG[4] 00_346 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPM_LF_CFG[5] 01_346 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPM_LF_CFG[6] 00_347 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPM_LF_CFG[7] 01_347 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPM_LF_CFG[8] 00_348 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPM_LF_CFG[9] 01_348 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPM_LF_CFG[10] 00_349 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPM_LF_CFG[11] 01_349 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPM_LF_CFG[12] 00_350 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPM_LF_CFG[13] 01_350 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPM_LF_CFG[14] 00_351 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPM_LF_CFG[15] 01_351 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPM_LF_CFG[16] 00_343 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPM_LF_CFG[17] 01_343 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPM_LF_CFG2[0] 03_426 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPM_LF_CFG2[1] 02_427 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPM_LF_CFG2[2] 03_427 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPM_LF_CFG2[3] 02_428 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPM_LF_CFG2[4] 03_428 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPM_OSINT_CFG[0] 02_440 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPM_OSINT_CFG[1] 03_440 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPM_OSINT_CFG[2] 02_441 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPM_CFG1[0] 02_330 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPMRESET_TIME[0] 00_112 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPMRESET_TIME[1] 01_112 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPMRESET_TIME[2] 00_113 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPMRESET_TIME[3] 01_113 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPMRESET_TIME[4] 00_114 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPMRESET_TIME[5] 01_114 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPMRESET_TIME[6] 00_115 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXOOB_CFG[0] 00_144 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXOOB_CFG[1] 01_144 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXOOB_CFG[2] 00_145 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXOOB_CFG[3] 01_145 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXOOB_CFG[4] 00_146 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXOOB_CFG[5] 01_146 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXOOB_CFG[6] 00_147 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXOOB_CLK_CFG.FABRIC 03_129 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXOSCALRESET_TIME[0] 00_187 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXOSCALRESET_TIME[1] 01_187 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXOSCALRESET_TIME[2] 00_188 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXOSCALRESET_TIME[3] 01_188 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXOSCALRESET_TIME[4] 00_189 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXOSCALRESET_TIMEOUT[0] 01_189 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXOSCALRESET_TIMEOUT[1] 00_190 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXOSCALRESET_TIMEOUT[2] 01_190 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXOSCALRESET_TIMEOUT[3] 00_191 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXOSCALRESET_TIMEOUT[4] 01_191 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXOUT_DIV[0] 02_384 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXOUT_DIV[1] 03_384 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXPCSRESET_TIME[0] 01_115 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXPCSRESET_TIME[1] 00_116 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXPCSRESET_TIME[2] 01_116 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXPCSRESET_TIME[3] 00_117 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXPCSRESET_TIME[4] 01_117 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXPH_CFG[0] 02_584 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXPH_CFG[1] 03_584 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXPH_CFG[2] 02_585 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXPH_CFG[3] 03_585 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXPH_CFG[4] 02_586 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXPH_CFG[5] 03_586 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXPH_CFG[6] 02_587 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXPH_CFG[7] 03_587 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXPH_CFG[8] 02_588 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXPH_CFG[9] 03_588 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXPH_CFG[10] 02_589 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXPH_CFG[11] 03_589 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXPH_CFG[12] 02_590 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXPH_CFG[13] 03_590 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXPH_CFG[14] 02_591 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXPH_CFG[15] 03_591 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXPH_CFG[16] 02_592 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXPH_CFG[17] 03_592 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXPH_CFG[18] 02_593 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXPH_CFG[19] 03_593 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXPH_CFG[20] 02_594 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXPH_CFG[21] 03_594 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXPH_CFG[22] 02_595 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXPH_CFG[23] 03_595 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXPH_MONITOR_SEL[0] 00_700 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXPH_MONITOR_SEL[1] 01_700 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXPH_MONITOR_SEL[2] 00_701 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXPH_MONITOR_SEL[3] 01_701 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXPH_MONITOR_SEL[4] 00_702 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXPHDLY_CFG[0] 02_600 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXPHDLY_CFG[1] 03_600 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXPHDLY_CFG[2] 02_601 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXPHDLY_CFG[3] 03_601 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXPHDLY_CFG[4] 02_602 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXPHDLY_CFG[5] 03_602 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXPHDLY_CFG[6] 02_603 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXPHDLY_CFG[7] 03_603 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXPHDLY_CFG[8] 02_604 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXPHDLY_CFG[9] 03_604 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXPHDLY_CFG[10] 02_605 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXPHDLY_CFG[11] 03_605 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXPHDLY_CFG[12] 02_606 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXPHDLY_CFG[13] 03_606 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXPHDLY_CFG[14] 02_607 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXPHDLY_CFG[15] 03_607 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXPHDLY_CFG[16] 02_608 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXPHDLY_CFG[17] 03_608 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXPHDLY_CFG[18] 02_609 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXPHDLY_CFG[19] 03_609 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXPHDLY_CFG[20] 02_610 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXPHDLY_CFG[21] 03_610 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXPHDLY_CFG[22] 02_611 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXPHDLY_CFG[23] 03_611 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXPI_CFG0[0] 03_430 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXPI_CFG0[1] 02_431 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXPI_CFG0[2] 03_431 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXPI_CFG1[0] 02_442 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXPI_CFG2[0] 03_441 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXPMARESET_TIME[0] 00_104 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXPMARESET_TIME[1] 01_104 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXPMARESET_TIME[2] 00_105 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXPMARESET_TIME[3] 01_105 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXPMARESET_TIME[4] 00_106 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXPRBS_ERR_LOOPBACK[0] 00_136 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXSLIDE_AUTO_WAIT[0] 00_520 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXSLIDE_AUTO_WAIT[1] 01_520 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXSLIDE_AUTO_WAIT[2] 00_521 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXSLIDE_AUTO_WAIT[3] 01_521 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXSLIDE_MODE.AUTO 00_519 !01_519 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXSLIDE_MODE.PCS !00_519 01_519 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXSLIDE_MODE.PMA 00_519 01_519 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXSYNC_MULTILANE[0] 00_133 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXSYNC_OVRD[0] 01_135 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXSYNC_SKIP_DA[0] 01_134 -GTP_CHANNEL_0_MID_LEFT.GTPE2.SAS_MAX_COM[0] 00_171 -GTP_CHANNEL_0_MID_LEFT.GTPE2.SAS_MAX_COM[1] 01_171 -GTP_CHANNEL_0_MID_LEFT.GTPE2.SAS_MAX_COM[2] 00_172 -GTP_CHANNEL_0_MID_LEFT.GTPE2.SAS_MAX_COM[3] 01_172 -GTP_CHANNEL_0_MID_LEFT.GTPE2.SAS_MAX_COM[4] 00_173 -GTP_CHANNEL_0_MID_LEFT.GTPE2.SAS_MAX_COM[5] 01_173 -GTP_CHANNEL_0_MID_LEFT.GTPE2.SAS_MAX_COM[6] 00_174 -GTP_CHANNEL_0_MID_LEFT.GTPE2.SAS_MIN_COM[0] 01_156 -GTP_CHANNEL_0_MID_LEFT.GTPE2.SAS_MIN_COM[1] 00_157 -GTP_CHANNEL_0_MID_LEFT.GTPE2.SAS_MIN_COM[2] 01_157 -GTP_CHANNEL_0_MID_LEFT.GTPE2.SAS_MIN_COM[3] 00_158 -GTP_CHANNEL_0_MID_LEFT.GTPE2.SAS_MIN_COM[4] 01_158 -GTP_CHANNEL_0_MID_LEFT.GTPE2.SAS_MIN_COM[5] 00_159 -GTP_CHANNEL_0_MID_LEFT.GTPE2.SATA_BURST_SEQ_LEN[0] 00_150 -GTP_CHANNEL_0_MID_LEFT.GTPE2.SATA_BURST_SEQ_LEN[1] 01_150 -GTP_CHANNEL_0_MID_LEFT.GTPE2.SATA_BURST_SEQ_LEN[2] 00_151 -GTP_CHANNEL_0_MID_LEFT.GTPE2.SATA_BURST_SEQ_LEN[3] 01_151 -GTP_CHANNEL_0_MID_LEFT.GTPE2.SATA_BURST_VAL[0] 01_147 -GTP_CHANNEL_0_MID_LEFT.GTPE2.SATA_BURST_VAL[1] 00_148 -GTP_CHANNEL_0_MID_LEFT.GTPE2.SATA_BURST_VAL[2] 01_148 -GTP_CHANNEL_0_MID_LEFT.GTPE2.SATA_EIDLE_VAL[0] 00_152 -GTP_CHANNEL_0_MID_LEFT.GTPE2.SATA_EIDLE_VAL[1] 01_152 -GTP_CHANNEL_0_MID_LEFT.GTPE2.SATA_EIDLE_VAL[2] 00_153 -GTP_CHANNEL_0_MID_LEFT.GTPE2.SATA_MAX_BURST[0] 00_168 -GTP_CHANNEL_0_MID_LEFT.GTPE2.SATA_MAX_BURST[1] 01_168 -GTP_CHANNEL_0_MID_LEFT.GTPE2.SATA_MAX_BURST[2] 00_169 -GTP_CHANNEL_0_MID_LEFT.GTPE2.SATA_MAX_BURST[3] 01_169 -GTP_CHANNEL_0_MID_LEFT.GTPE2.SATA_MAX_BURST[4] 00_170 -GTP_CHANNEL_0_MID_LEFT.GTPE2.SATA_MAX_BURST[5] 01_170 -GTP_CHANNEL_0_MID_LEFT.GTPE2.SATA_MAX_INIT[0] 00_176 -GTP_CHANNEL_0_MID_LEFT.GTPE2.SATA_MAX_INIT[1] 01_176 -GTP_CHANNEL_0_MID_LEFT.GTPE2.SATA_MAX_INIT[2] 00_177 -GTP_CHANNEL_0_MID_LEFT.GTPE2.SATA_MAX_INIT[3] 01_177 -GTP_CHANNEL_0_MID_LEFT.GTPE2.SATA_MAX_INIT[4] 00_178 -GTP_CHANNEL_0_MID_LEFT.GTPE2.SATA_MAX_INIT[5] 01_178 -GTP_CHANNEL_0_MID_LEFT.GTPE2.SATA_MAX_WAKE[0] 00_179 -GTP_CHANNEL_0_MID_LEFT.GTPE2.SATA_MAX_WAKE[1] 01_179 -GTP_CHANNEL_0_MID_LEFT.GTPE2.SATA_MAX_WAKE[2] 00_180 -GTP_CHANNEL_0_MID_LEFT.GTPE2.SATA_MAX_WAKE[3] 01_180 -GTP_CHANNEL_0_MID_LEFT.GTPE2.SATA_MAX_WAKE[4] 00_181 -GTP_CHANNEL_0_MID_LEFT.GTPE2.SATA_MAX_WAKE[5] 01_181 -GTP_CHANNEL_0_MID_LEFT.GTPE2.SATA_MIN_BURST[0] 01_153 -GTP_CHANNEL_0_MID_LEFT.GTPE2.SATA_MIN_BURST[1] 00_154 -GTP_CHANNEL_0_MID_LEFT.GTPE2.SATA_MIN_BURST[2] 01_154 -GTP_CHANNEL_0_MID_LEFT.GTPE2.SATA_MIN_BURST[3] 00_155 -GTP_CHANNEL_0_MID_LEFT.GTPE2.SATA_MIN_BURST[4] 01_155 -GTP_CHANNEL_0_MID_LEFT.GTPE2.SATA_MIN_BURST[5] 00_156 -GTP_CHANNEL_0_MID_LEFT.GTPE2.SATA_MIN_INIT[0] 00_160 -GTP_CHANNEL_0_MID_LEFT.GTPE2.SATA_MIN_INIT[1] 01_160 -GTP_CHANNEL_0_MID_LEFT.GTPE2.SATA_MIN_INIT[2] 00_161 -GTP_CHANNEL_0_MID_LEFT.GTPE2.SATA_MIN_INIT[3] 01_161 -GTP_CHANNEL_0_MID_LEFT.GTPE2.SATA_MIN_INIT[4] 00_162 -GTP_CHANNEL_0_MID_LEFT.GTPE2.SATA_MIN_INIT[5] 01_162 -GTP_CHANNEL_0_MID_LEFT.GTPE2.SATA_MIN_WAKE[0] 00_163 -GTP_CHANNEL_0_MID_LEFT.GTPE2.SATA_MIN_WAKE[1] 01_163 -GTP_CHANNEL_0_MID_LEFT.GTPE2.SATA_MIN_WAKE[2] 00_164 -GTP_CHANNEL_0_MID_LEFT.GTPE2.SATA_MIN_WAKE[3] 01_164 -GTP_CHANNEL_0_MID_LEFT.GTPE2.SATA_MIN_WAKE[4] 00_165 -GTP_CHANNEL_0_MID_LEFT.GTPE2.SATA_MIN_WAKE[5] 01_165 -GTP_CHANNEL_0_MID_LEFT.GTPE2.SATA_PLL_CFG.VCO_1500MHZ 02_55 -GTP_CHANNEL_0_MID_LEFT.GTPE2.SATA_PLL_CFG.VCO_750MHZ 03_55 -GTP_CHANNEL_0_MID_LEFT.GTPE2.SHOW_REALIGN_COMMA 01_522 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TERM_RCAL_CFG[0] 02_136 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TERM_RCAL_CFG[1] 03_136 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TERM_RCAL_CFG[2] 02_137 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TERM_RCAL_CFG[3] 03_137 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TERM_RCAL_CFG[4] 02_138 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TERM_RCAL_CFG[5] 03_138 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TERM_RCAL_CFG[6] 02_139 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TERM_RCAL_CFG[7] 03_139 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TERM_RCAL_CFG[8] 02_140 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TERM_RCAL_CFG[9] 03_140 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TERM_RCAL_CFG[10] 02_141 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TERM_RCAL_CFG[11] 03_141 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TERM_RCAL_CFG[12] 02_142 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TERM_RCAL_CFG[13] 03_142 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TERM_RCAL_CFG[14] 02_143 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TERM_RCAL_OVRD[0] 03_150 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TERM_RCAL_OVRD[1] 02_151 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TERM_RCAL_OVRD[2] 03_151 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TRANS_TIME_RATE[0] 00_192 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TRANS_TIME_RATE[1] 01_192 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TRANS_TIME_RATE[2] 00_193 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TRANS_TIME_RATE[3] 01_193 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TRANS_TIME_RATE[4] 00_194 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TRANS_TIME_RATE[5] 01_194 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TRANS_TIME_RATE[6] 00_195 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TRANS_TIME_RATE[7] 01_195 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TST_RSV[0] 02_504 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TST_RSV[1] 03_504 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TST_RSV[2] 02_505 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TST_RSV[3] 03_505 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TST_RSV[4] 02_506 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TST_RSV[5] 03_506 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TST_RSV[6] 02_507 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TST_RSV[7] 03_507 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TST_RSV[8] 02_508 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TST_RSV[9] 03_508 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TST_RSV[10] 02_509 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TST_RSV[11] 03_509 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TST_RSV[12] 02_510 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TST_RSV[13] 03_510 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TST_RSV[14] 02_511 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TST_RSV[15] 03_511 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TST_RSV[16] 02_512 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TST_RSV[17] 03_512 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TST_RSV[18] 02_513 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TST_RSV[19] 03_513 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TST_RSV[20] 02_514 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TST_RSV[21] 03_514 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TST_RSV[22] 02_515 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TST_RSV[23] 03_515 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TST_RSV[24] 02_516 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TST_RSV[25] 03_516 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TST_RSV[26] 02_517 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TST_RSV[27] 03_517 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TST_RSV[28] 02_518 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TST_RSV[29] 03_518 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TST_RSV[30] 02_519 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TST_RSV[31] 03_519 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_CLKMUX_EN[0] 03_128 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_DATA_WIDTH[0] 02_152 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_DATA_WIDTH[1] 03_152 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_DATA_WIDTH[2] 02_153 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_DRIVE_MODE.PIPE 00_200 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_EIDLE_ASSERT_DELAY[0] 00_203 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_EIDLE_ASSERT_DELAY[1] 01_203 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_EIDLE_ASSERT_DELAY[2] 00_204 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_EIDLE_DEASSERT_DELAY[0] 01_204 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_EIDLE_DEASSERT_DELAY[1] 00_205 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_EIDLE_DEASSERT_DELAY[2] 01_205 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_LOOPBACK_DRIVE_HIZ 01_202 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_MAINCURSOR_SEL[0] 03_289 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_MARGIN_FULL_0[0] 02_232 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_MARGIN_FULL_0[1] 03_232 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_MARGIN_FULL_0[2] 02_233 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_MARGIN_FULL_0[3] 03_233 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_MARGIN_FULL_0[4] 02_234 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_MARGIN_FULL_0[5] 03_234 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_MARGIN_FULL_0[6] 02_235 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_MARGIN_FULL_1[0] 02_236 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_MARGIN_FULL_1[1] 03_236 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_MARGIN_FULL_1[2] 02_237 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_MARGIN_FULL_1[3] 03_237 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_MARGIN_FULL_1[4] 02_238 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_MARGIN_FULL_1[5] 03_238 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_MARGIN_FULL_1[6] 02_239 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_MARGIN_FULL_2[0] 02_240 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_MARGIN_FULL_2[1] 03_240 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_MARGIN_FULL_2[2] 02_241 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_MARGIN_FULL_2[3] 03_241 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_MARGIN_FULL_2[4] 02_242 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_MARGIN_FULL_2[5] 03_242 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_MARGIN_FULL_2[6] 02_243 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_MARGIN_FULL_3[0] 02_244 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_MARGIN_FULL_3[1] 03_244 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_MARGIN_FULL_3[2] 02_245 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_MARGIN_FULL_3[3] 03_245 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_MARGIN_FULL_3[4] 02_246 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_MARGIN_FULL_3[5] 03_246 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_MARGIN_FULL_3[6] 02_247 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_MARGIN_FULL_4[0] 02_248 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_MARGIN_FULL_4[1] 03_248 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_MARGIN_FULL_4[2] 02_249 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_MARGIN_FULL_4[3] 03_249 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_MARGIN_FULL_4[4] 02_250 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_MARGIN_FULL_4[5] 03_250 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_MARGIN_FULL_4[6] 02_251 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_MARGIN_LOW_0[0] 02_252 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_MARGIN_LOW_0[1] 03_252 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_MARGIN_LOW_0[2] 02_253 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_MARGIN_LOW_0[3] 03_253 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_MARGIN_LOW_0[4] 02_254 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_MARGIN_LOW_0[5] 03_254 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_MARGIN_LOW_0[6] 02_255 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_MARGIN_LOW_1[0] 02_256 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_MARGIN_LOW_1[1] 03_256 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_MARGIN_LOW_1[2] 02_257 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_MARGIN_LOW_1[3] 03_257 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_MARGIN_LOW_1[4] 02_258 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_MARGIN_LOW_1[5] 03_258 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_MARGIN_LOW_1[6] 02_259 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_MARGIN_LOW_2[0] 02_260 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_MARGIN_LOW_2[1] 03_260 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_MARGIN_LOW_2[2] 02_261 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_MARGIN_LOW_2[3] 03_261 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_MARGIN_LOW_2[4] 02_262 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_MARGIN_LOW_2[5] 03_262 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_MARGIN_LOW_2[6] 02_263 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_MARGIN_LOW_3[0] 02_264 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_MARGIN_LOW_3[1] 03_264 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_MARGIN_LOW_3[2] 02_265 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_MARGIN_LOW_3[3] 03_265 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_MARGIN_LOW_3[4] 02_266 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_MARGIN_LOW_3[5] 03_266 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_MARGIN_LOW_3[6] 02_267 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_MARGIN_LOW_4[0] 02_268 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_MARGIN_LOW_4[1] 03_268 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_MARGIN_LOW_4[2] 02_269 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_MARGIN_LOW_4[3] 03_269 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_MARGIN_LOW_4[4] 02_270 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_MARGIN_LOW_4[5] 03_270 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_MARGIN_LOW_4[6] 02_271 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_PREDRIVER_MODE[0] 00_206 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_RXDETECT_CFG[0] 02_296 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_RXDETECT_CFG[1] 03_296 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_RXDETECT_CFG[2] 02_297 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_RXDETECT_CFG[3] 03_297 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_RXDETECT_CFG[4] 02_298 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_RXDETECT_CFG[5] 03_298 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_RXDETECT_CFG[6] 02_299 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_RXDETECT_CFG[7] 03_299 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_RXDETECT_CFG[8] 02_300 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_RXDETECT_CFG[9] 03_300 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_RXDETECT_CFG[10] 02_301 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_RXDETECT_CFG[11] 03_301 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_RXDETECT_CFG[12] 02_302 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_RXDETECT_CFG[13] 03_302 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_RXDETECT_REF[0] 02_292 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_RXDETECT_REF[1] 03_292 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_RXDETECT_REF[2] 02_293 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_XCLK_SEL.TXUSR 03_11 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_CLK25_DIV[0] 02_144 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_CLK25_DIV[1] 03_144 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_CLK25_DIV[2] 02_145 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_CLK25_DIV[3] 03_145 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_CLK25_DIV[4] 02_146 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_DEEMPH0[0] 02_272 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_DEEMPH0[1] 03_272 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_DEEMPH0[2] 02_273 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_DEEMPH0[3] 03_273 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_DEEMPH0[4] 02_274 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_DEEMPH0[5] 03_274 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_DEEMPH1[0] 02_276 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_DEEMPH1[1] 03_276 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_DEEMPH1[2] 02_277 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_DEEMPH1[3] 03_277 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_DEEMPH1[4] 02_278 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_DEEMPH1[5] 03_278 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXBUF_EN 00_231 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXBUF_RESET_ON_RATE_CHANGE 01_231 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXDLY_CFG[0] 02_80 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXDLY_CFG[1] 03_80 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXDLY_CFG[2] 02_81 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXDLY_CFG[3] 03_81 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXDLY_CFG[4] 02_82 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXDLY_CFG[5] 03_82 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXDLY_CFG[6] 02_83 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXDLY_CFG[7] 03_83 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXDLY_CFG[8] 02_84 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXDLY_CFG[9] 03_84 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXDLY_CFG[10] 02_85 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXDLY_CFG[11] 03_85 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXDLY_CFG[12] 02_86 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXDLY_CFG[13] 03_86 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXDLY_CFG[14] 02_87 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXDLY_CFG[15] 03_87 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXDLY_LCFG[0] 02_568 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXDLY_LCFG[1] 03_568 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXDLY_LCFG[2] 02_569 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXDLY_LCFG[3] 03_569 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXDLY_LCFG[4] 02_570 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXDLY_LCFG[5] 03_570 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXDLY_LCFG[6] 02_571 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXDLY_LCFG[7] 03_571 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXDLY_LCFG[8] 02_572 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXDLY_TAP_CFG[0] 02_88 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXDLY_TAP_CFG[1] 03_88 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXDLY_TAP_CFG[2] 02_89 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXDLY_TAP_CFG[3] 03_89 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXDLY_TAP_CFG[4] 02_90 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXDLY_TAP_CFG[5] 03_90 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXDLY_TAP_CFG[6] 02_91 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXDLY_TAP_CFG[7] 03_91 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXDLY_TAP_CFG[8] 02_92 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXDLY_TAP_CFG[9] 03_92 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXDLY_TAP_CFG[10] 02_93 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXDLY_TAP_CFG[11] 03_93 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXDLY_TAP_CFG[12] 02_94 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXDLY_TAP_CFG[13] 03_94 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXDLY_TAP_CFG[14] 02_95 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXDLY_TAP_CFG[15] 03_95 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXGEARBOX_EN 01_226 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXOOB_CFG[0] 03_20 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXOUT_DIV[0] 02_386 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXOUT_DIV[1] 03_386 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPCSRESET_TIME[0] 01_130 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPCSRESET_TIME[1] 00_131 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPCSRESET_TIME[2] 01_131 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPCSRESET_TIME[3] 00_132 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPCSRESET_TIME[4] 01_132 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPH_CFG[0] 02_96 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPH_CFG[1] 03_96 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPH_CFG[2] 02_97 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPH_CFG[3] 03_97 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPH_CFG[4] 02_98 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPH_CFG[5] 03_98 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPH_CFG[6] 02_99 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPH_CFG[7] 03_99 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPH_CFG[8] 02_100 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPH_CFG[9] 03_100 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPH_CFG[10] 02_101 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPH_CFG[11] 03_101 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPH_CFG[12] 02_102 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPH_CFG[13] 03_102 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPH_CFG[14] 02_103 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPH_CFG[15] 03_103 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPH_MONITOR_SEL[0] 02_108 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPH_MONITOR_SEL[1] 03_108 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPH_MONITOR_SEL[2] 02_109 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPH_MONITOR_SEL[3] 03_109 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPH_MONITOR_SEL[4] 02_110 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPHDLY_CFG[0] 02_64 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPHDLY_CFG[1] 03_64 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPHDLY_CFG[2] 02_65 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPHDLY_CFG[3] 03_65 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPHDLY_CFG[4] 02_66 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPHDLY_CFG[5] 03_66 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPHDLY_CFG[6] 02_67 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPHDLY_CFG[7] 03_67 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPHDLY_CFG[8] 02_68 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPHDLY_CFG[9] 03_68 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPHDLY_CFG[10] 02_69 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPHDLY_CFG[11] 03_69 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPHDLY_CFG[12] 02_70 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPHDLY_CFG[13] 03_70 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPHDLY_CFG[14] 02_71 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPHDLY_CFG[15] 03_71 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPHDLY_CFG[16] 02_72 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPHDLY_CFG[17] 03_72 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPHDLY_CFG[18] 02_73 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPHDLY_CFG[19] 03_73 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPHDLY_CFG[20] 02_74 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPHDLY_CFG[21] 03_74 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPHDLY_CFG[22] 02_75 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPHDLY_CFG[23] 03_75 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPI_GREY_SEL[0] 03_498 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPI_INVSTROBE_SEL[0] 02_498 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPI_PPM_CFG[0] 02_488 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPI_PPM_CFG[1] 03_488 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPI_PPM_CFG[2] 02_489 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPI_PPM_CFG[3] 03_489 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPI_PPM_CFG[4] 02_490 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPI_PPM_CFG[5] 03_490 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPI_PPM_CFG[6] 02_491 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPI_PPM_CFG[7] 03_491 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPI_PPMCLK_SEL.TXUSRCLK2 03_497 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPI_SYNFREQ_PPM[0] 02_496 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPI_SYNFREQ_PPM[1] 03_496 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPI_SYNFREQ_PPM[2] 02_497 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPI_CFG0[0] 02_40 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPI_CFG0[1] 03_40 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPI_CFG1[0] 02_41 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPI_CFG1[1] 03_41 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPI_CFG2[0] 02_42 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPI_CFG2[1] 03_42 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPI_CFG3[0] 02_43 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPI_CFG4[0] 03_43 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPI_CFG5[0] 02_44 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPI_CFG5[1] 03_44 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPI_CFG5[2] 02_45 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPMARESET_TIME[0] 00_128 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPMARESET_TIME[1] 01_128 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPMARESET_TIME[2] 00_129 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPMARESET_TIME[3] 01_129 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPMARESET_TIME[4] 00_130 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXSYNC_MULTILANE[0] 01_133 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXSYNC_OVRD[0] 00_135 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXSYNC_SKIP_DA[0] 00_134 -GTP_CHANNEL_0_MID_LEFT.GTPE2.UCODEER_CLR[0] 01_00 -GTP_CHANNEL_0_MID_LEFT.GTPE2.USE_PCS_CLK_PHASE_SEL[0] 02_463 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ZINV_DMONITORCLK 02_13 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ZINV_DRPCLK 02_00 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ZINV_RXUSRCLK 03_01 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ZINV_SIGVALIDCLK 03_13 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ZINV_TXPHDLYTSTCLK 02_03 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ZINV_TXUSRCLK 03_04 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ZINV_CLKRSVD0 02_23 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ZINV_CLKRSVD1 03_23 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ZINV_RXUSRCLK2 02_02 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ZINV_TXUSRCLK2 02_05 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ACJTAG_DEBUG_MODE[0] 00_07 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ACJTAG_MODE[0] 01_06 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ACJTAG_RESET[0] 01_07 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[0] 02_464 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[1] 03_464 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[2] 02_465 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[3] 03_465 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[4] 02_466 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[5] 03_466 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[6] 02_467 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[7] 03_467 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[8] 02_468 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[9] 03_468 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[10] 02_469 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[11] 03_469 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[12] 02_470 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[13] 03_470 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[14] 02_471 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[15] 03_471 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[16] 02_472 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[17] 03_472 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[18] 02_473 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[19] 03_473 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ALIGN_COMMA_DOUBLE 00_522 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[0] 00_496 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[1] 01_496 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[2] 00_497 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[3] 01_497 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[4] 00_498 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[5] 01_498 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[6] 00_499 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[7] 01_499 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[8] 00_500 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[9] 01_500 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ALIGN_COMMA_WORD[0] 01_526 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ALIGN_COMMA_WORD[1] 00_527 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ALIGN_MCOMMA_DET 00_523 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[0] 00_504 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[1] 01_504 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[2] 00_505 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[3] 01_505 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[4] 00_506 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[5] 01_506 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[6] 00_507 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[7] 01_507 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[8] 00_508 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[9] 01_508 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ALIGN_PCOMMA_DET 01_523 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[0] 00_512 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[1] 01_512 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[2] 00_513 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[3] 01_513 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[4] 00_514 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[5] 01_514 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[6] 00_515 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[7] 01_515 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[8] 00_516 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[9] 01_516 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CBCC_DATA_SOURCE_SEL.DECODED 01_661 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[0] 02_392 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[1] 03_392 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[2] 02_393 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[3] 03_393 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[4] 02_394 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[5] 03_394 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[6] 02_395 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[7] 03_395 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[8] 02_396 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[9] 03_396 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[10] 02_397 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[11] 03_397 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[12] 02_398 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[13] 03_398 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[14] 02_399 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[15] 03_399 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[16] 02_400 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[17] 03_400 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[18] 02_401 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[19] 03_401 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[20] 02_402 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[21] 03_402 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[22] 02_403 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[23] 03_403 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[24] 02_404 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[25] 03_404 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[26] 02_405 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[27] 03_405 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[28] 02_406 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[29] 03_406 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[30] 02_407 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[31] 03_407 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[32] 02_408 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[33] 03_408 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[34] 02_409 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[35] 03_409 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[36] 02_410 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[37] 03_410 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[38] 02_411 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[39] 03_411 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[40] 02_412 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[41] 03_412 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[42] 02_413 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG2[0] 02_459 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG2[1] 03_459 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG2[2] 02_460 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG2[3] 03_460 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG2[4] 02_461 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG2[5] 03_461 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG2[6] 02_462 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG3[0] 02_416 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG3[1] 03_416 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG3[2] 02_417 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG3[3] 03_417 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG3[4] 02_418 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG3[5] 03_418 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG3[6] 02_419 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG4[0] 03_438 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG5[0] 02_429 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG5[1] 03_429 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG6[0] 03_436 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG6[1] 02_437 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG6[2] 03_437 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG6[3] 02_438 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_KEEP_ALIGN 01_631 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_MAX_SKEW[0] 00_670 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_MAX_SKEW[1] 01_670 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_MAX_SKEW[2] 00_671 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_MAX_SKEW[3] 01_671 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[0] 00_608 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[1] 01_608 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[2] 00_609 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[3] 01_609 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[4] 00_610 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[5] 01_610 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[6] 00_611 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[7] 01_611 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[8] 00_612 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[9] 01_612 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[0] 00_616 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[1] 01_616 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[2] 00_617 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[3] 01_617 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[4] 00_618 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[5] 01_618 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[6] 00_619 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[7] 01_619 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[8] 00_620 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[9] 01_620 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[0] 00_624 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[1] 01_624 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[2] 00_625 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[3] 01_625 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[4] 00_626 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[5] 01_626 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[6] 00_627 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[7] 01_627 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[8] 00_628 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[9] 01_628 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[0] 00_632 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[1] 01_632 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[2] 00_633 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[3] 01_633 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[4] 00_634 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[5] 01_634 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[6] 00_635 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[7] 01_635 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[8] 00_636 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[9] 01_636 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_ENABLE[0] 00_614 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_ENABLE[1] 01_614 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_ENABLE[2] 00_615 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_ENABLE[3] 01_615 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[0] 00_640 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[1] 01_640 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[2] 00_641 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[3] 01_641 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[4] 00_642 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[5] 01_642 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[6] 00_643 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[7] 01_643 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[8] 00_644 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[9] 01_644 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[0] 00_648 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[1] 01_648 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[2] 00_649 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[3] 01_649 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[4] 00_650 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[5] 01_650 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[6] 00_651 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[7] 01_651 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[8] 00_652 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[9] 01_652 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[0] 00_656 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[1] 01_656 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[2] 00_657 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[3] 01_657 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[4] 00_658 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[5] 01_658 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[6] 00_659 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[7] 01_659 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[8] 00_660 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[9] 01_660 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[0] 00_664 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[1] 01_664 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[2] 00_665 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[3] 01_665 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[4] 00_666 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[5] 01_666 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[6] 00_667 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[7] 01_667 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[8] 00_668 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[9] 01_668 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_ENABLE[0] 00_646 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_ENABLE[1] 01_646 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_ENABLE[2] 00_647 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_ENABLE[3] 01_647 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_USE 01_645 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_LEN[0] 00_623 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_LEN[1] 01_623 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COMMON_SWING[0] 03_311 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_KEEP_IDLE 00_591 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_MAX_LAT[0] 00_557 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_MAX_LAT[1] 01_557 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_MAX_LAT[2] 00_558 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_MAX_LAT[3] 01_558 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_MAX_LAT[4] 00_559 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_MAX_LAT[5] 01_559 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_MIN_LAT[0] 00_565 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_MIN_LAT[1] 01_565 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_MIN_LAT[2] 00_566 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_MIN_LAT[3] 01_566 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_MIN_LAT[4] 00_567 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_MIN_LAT[5] 01_567 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_PRECEDENCE 00_590 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_REPEAT_WAIT[0] 00_573 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_REPEAT_WAIT[1] 01_573 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_REPEAT_WAIT[2] 00_574 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_REPEAT_WAIT[3] 01_574 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_REPEAT_WAIT[4] 00_575 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[0] 00_544 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[1] 01_544 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[2] 00_545 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[3] 01_545 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[4] 00_546 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[5] 01_546 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[6] 00_547 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[7] 01_547 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[8] 00_548 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[9] 01_548 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[0] 00_552 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[1] 01_552 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[2] 00_553 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[3] 01_553 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[4] 00_554 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[5] 01_554 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[6] 00_555 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[7] 01_555 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[8] 00_556 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[9] 01_556 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[0] 00_560 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[1] 01_560 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[2] 00_561 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[3] 01_561 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[4] 00_562 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[5] 01_562 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[6] 00_563 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[7] 01_563 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[8] 00_564 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[9] 01_564 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[0] 00_568 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[1] 01_568 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[2] 00_569 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[3] 01_569 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[4] 00_570 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[5] 01_570 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[6] 00_571 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[7] 01_571 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[8] 00_572 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[9] 01_572 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_ENABLE[0] 00_549 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_ENABLE[1] 01_549 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_ENABLE[2] 00_550 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_ENABLE[3] 01_550 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[0] 00_576 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[1] 01_576 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[2] 00_577 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[3] 01_577 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[4] 00_578 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[5] 01_578 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[6] 00_579 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[7] 01_579 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[8] 00_580 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[9] 01_580 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[0] 00_584 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[1] 01_584 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[2] 00_585 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[3] 01_585 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[4] 00_586 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[5] 01_586 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[6] 00_587 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[7] 01_587 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[8] 00_588 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[9] 01_588 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[0] 00_592 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[1] 01_592 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[2] 00_593 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[3] 01_593 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[4] 00_594 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[5] 01_594 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[6] 00_595 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[7] 01_595 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[8] 00_596 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[9] 01_596 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[0] 00_600 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[1] 01_600 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[2] 00_601 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[3] 01_601 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[4] 00_602 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[5] 01_602 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[6] 00_603 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[7] 01_603 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[8] 00_604 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[9] 01_604 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_ENABLE[0] 00_581 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_ENABLE[1] 01_581 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_ENABLE[2] 00_582 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_ENABLE[3] 01_582 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_USE 00_583 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_LEN[0] 00_589 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_LEN[1] 01_589 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_CORRECT_USE 00_551 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.DEC_MCOMMA_DETECT 01_494 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.DEC_PCOMMA_DETECT 00_495 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.DEC_VALID_COMMA_ONLY 00_494 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[0] 02_368 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[1] 03_368 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[2] 02_369 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[3] 03_369 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[4] 02_370 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[5] 03_370 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[6] 02_371 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[7] 03_371 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[8] 02_372 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[9] 03_372 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[10] 02_373 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[11] 03_373 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[12] 02_374 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[13] 03_374 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[14] 02_375 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[15] 03_375 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[16] 02_376 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[17] 03_376 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[18] 02_377 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[19] 03_377 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[20] 02_378 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[21] 03_378 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[22] 02_379 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[23] 03_379 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_CLK_PHASE_SEL[0] 03_463 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_CONTROL[0] 00_488 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_CONTROL[1] 01_488 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_CONTROL[2] 00_489 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_CONTROL[3] 01_489 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_CONTROL[4] 00_490 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_CONTROL[5] 01_490 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_ERRDET_EN 01_492 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_EYE_SCAN_EN 00_492 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_HORZ_OFFSET[0] 00_480 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_HORZ_OFFSET[1] 01_480 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_HORZ_OFFSET[2] 00_481 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_HORZ_OFFSET[3] 01_481 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_HORZ_OFFSET[4] 00_482 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_HORZ_OFFSET[5] 01_482 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_HORZ_OFFSET[6] 00_483 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_HORZ_OFFSET[7] 01_483 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_HORZ_OFFSET[8] 00_484 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_HORZ_OFFSET[9] 01_484 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_HORZ_OFFSET[10] 00_485 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_HORZ_OFFSET[11] 01_485 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_PMA_CFG[0] 02_624 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_PMA_CFG[1] 03_624 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_PMA_CFG[2] 02_625 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_PMA_CFG[3] 03_625 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_PMA_CFG[4] 02_626 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_PMA_CFG[5] 03_626 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_PMA_CFG[6] 02_627 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_PMA_CFG[7] 03_627 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_PMA_CFG[8] 02_628 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_PMA_CFG[9] 03_628 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_PRESCALE[0] 01_477 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_PRESCALE[1] 00_478 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_PRESCALE[2] 01_478 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_PRESCALE[3] 00_479 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_PRESCALE[4] 01_479 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[0] 00_392 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[1] 01_392 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[2] 00_393 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[3] 01_393 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[4] 00_394 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[5] 01_394 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[6] 00_395 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[7] 01_395 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[8] 00_396 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[9] 01_396 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[10] 00_397 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[11] 01_397 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[12] 00_398 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[13] 01_398 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[14] 00_399 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[15] 01_399 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[16] 00_400 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[17] 01_400 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[18] 00_401 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[19] 01_401 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[20] 00_402 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[21] 01_402 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[22] 00_403 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[23] 01_403 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[24] 00_404 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[25] 01_404 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[26] 00_405 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[27] 01_405 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[28] 00_406 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[29] 01_406 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[30] 00_407 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[31] 01_407 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[32] 00_408 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[33] 01_408 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[34] 00_409 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[35] 01_409 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[36] 00_410 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[37] 01_410 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[38] 00_411 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[39] 01_411 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[40] 00_412 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[41] 01_412 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[42] 00_413 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[43] 01_413 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[44] 00_414 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[45] 01_414 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[46] 00_415 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[47] 01_415 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[48] 00_416 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[49] 01_416 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[50] 00_417 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[51] 01_417 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[52] 00_418 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[53] 01_418 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[54] 00_419 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[55] 01_419 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[56] 00_420 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[57] 01_420 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[58] 00_421 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[59] 01_421 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[60] 00_422 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[61] 01_422 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[62] 00_423 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[63] 01_423 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[64] 00_424 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[65] 01_424 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[66] 00_425 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[67] 01_425 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[68] 00_426 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[69] 01_426 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[70] 00_427 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[71] 01_427 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[72] 00_428 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[73] 01_428 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[74] 00_429 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[75] 01_429 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[76] 00_430 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[77] 01_430 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[78] 00_431 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[79] 01_431 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[0] 00_352 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[1] 01_352 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[2] 00_353 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[3] 01_353 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[4] 00_354 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[5] 01_354 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[6] 00_355 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[7] 01_355 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[8] 00_356 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[9] 01_356 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[10] 00_357 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[11] 01_357 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[12] 00_358 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[13] 01_358 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[14] 00_359 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[15] 01_359 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[16] 00_360 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[17] 01_360 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[18] 00_361 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[19] 01_361 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[20] 00_362 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[21] 01_362 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[22] 00_363 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[23] 01_363 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[24] 00_364 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[25] 01_364 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[26] 00_365 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[27] 01_365 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[28] 00_366 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[29] 01_366 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[30] 00_367 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[31] 01_367 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[32] 00_368 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[33] 01_368 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[34] 00_369 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[35] 01_369 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[36] 00_370 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[37] 01_370 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[38] 00_371 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[39] 01_371 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[40] 00_372 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[41] 01_372 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[42] 00_373 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[43] 01_373 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[44] 00_374 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[45] 01_374 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[46] 00_375 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[47] 01_375 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[48] 00_376 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[49] 01_376 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[50] 00_377 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[51] 01_377 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[52] 00_378 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[53] 01_378 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[54] 00_379 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[55] 01_379 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[56] 00_380 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[57] 01_380 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[58] 00_381 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[59] 01_381 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[60] 00_382 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[61] 01_382 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[62] 00_383 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[63] 01_383 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[64] 00_384 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[65] 01_384 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[66] 00_385 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[67] 01_385 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[68] 00_386 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[69] 01_386 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[70] 00_387 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[71] 01_387 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[72] 00_388 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[73] 01_388 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[74] 00_389 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[75] 01_389 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[76] 00_390 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[77] 01_390 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[78] 00_391 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[79] 01_391 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[0] 00_432 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[1] 01_432 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[2] 00_433 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[3] 01_433 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[4] 00_434 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[5] 01_434 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[6] 00_435 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[7] 01_435 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[8] 00_436 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[9] 01_436 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[10] 00_437 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[11] 01_437 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[12] 00_438 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[13] 01_438 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[14] 00_439 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[15] 01_439 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[16] 00_440 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[17] 01_440 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[18] 00_441 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[19] 01_441 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[20] 00_442 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[21] 01_442 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[22] 00_443 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[23] 01_443 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[24] 00_444 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[25] 01_444 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[26] 00_445 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[27] 01_445 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[28] 00_446 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[29] 01_446 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[30] 00_447 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[31] 01_447 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[32] 00_448 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[33] 01_448 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[34] 00_449 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[35] 01_449 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[36] 00_450 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[37] 01_450 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[38] 00_451 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[39] 01_451 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[40] 00_452 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[41] 01_452 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[42] 00_453 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[43] 01_453 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[44] 00_454 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[45] 01_454 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[46] 00_455 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[47] 01_455 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[48] 00_456 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[49] 01_456 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[50] 00_457 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[51] 01_457 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[52] 00_458 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[53] 01_458 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[54] 00_459 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[55] 01_459 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[56] 00_460 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[57] 01_460 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[58] 00_461 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[59] 01_461 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[60] 00_462 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[61] 01_462 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[62] 00_463 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[63] 01_463 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[64] 00_464 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[65] 01_464 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[66] 00_465 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[67] 01_465 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[68] 00_466 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[69] 01_466 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[70] 00_467 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[71] 01_467 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[72] 00_468 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[73] 01_468 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[74] 00_469 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[75] 01_469 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[76] 00_470 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[77] 01_470 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[78] 00_471 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[79] 01_471 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_VERT_OFFSET[0] 00_472 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_VERT_OFFSET[1] 01_472 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_VERT_OFFSET[2] 00_473 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_VERT_OFFSET[3] 01_473 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_VERT_OFFSET[4] 00_474 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_VERT_OFFSET[5] 01_474 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_VERT_OFFSET[6] 00_475 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_VERT_OFFSET[7] 01_475 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_VERT_OFFSET[8] 00_476 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.FTS_DESKEW_SEQ_ENABLE[0] 00_662 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.FTS_DESKEW_SEQ_ENABLE[1] 01_662 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.FTS_DESKEW_SEQ_ENABLE[2] 00_663 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.FTS_DESKEW_SEQ_ENABLE[3] 01_663 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.FTS_LANE_DESKEW_CFG[0] 00_654 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.FTS_LANE_DESKEW_CFG[1] 01_654 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.FTS_LANE_DESKEW_CFG[2] 00_655 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.FTS_LANE_DESKEW_CFG[3] 01_655 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.FTS_LANE_DESKEW_EN 01_653 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.GEARBOX_MODE[0] 00_224 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.GEARBOX_MODE[1] 01_224 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.GEARBOX_MODE[2] 00_225 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.IN_USE 00_00 00_01 00_47 00_52 00_53 00_65 01_01 01_47 02_129 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.INV_DMONITORCLK 02_13 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.INV_DRPCLK 02_00 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.INV_RXUSRCLK 03_01 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.INV_SIGVALIDCLK 03_13 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.INV_TXPHDLYTSTCLK 02_03 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.INV_TXUSRCLK 03_04 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.INV_CLKRSVD0 02_23 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.INV_CLKRSVD1 03_23 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.INV_RXUSRCLK2 02_02 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.INV_TXUSRCLK2 02_05 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.LOOPBACK_CFG[0] 02_20 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.OUTREFCLK_SEL_INV[0] 00_149 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.OUTREFCLK_SEL_INV[1] 01_149 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PCS_PCIE_EN 00_216 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[0] 02_184 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[1] 03_184 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[2] 02_185 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[3] 03_185 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[4] 02_186 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[5] 03_186 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[6] 02_187 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[7] 03_187 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[8] 02_188 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[9] 03_188 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[10] 02_189 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[11] 03_189 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[12] 02_190 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[13] 03_190 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[14] 02_191 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[15] 03_191 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[16] 02_192 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[17] 03_192 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[18] 02_193 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[19] 03_193 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[20] 02_194 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[21] 03_194 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[22] 02_195 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[23] 03_195 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[24] 02_196 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[25] 03_196 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[26] 02_197 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[27] 03_197 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[28] 02_198 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[29] 03_198 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[30] 02_199 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[31] 03_199 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[32] 02_200 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[33] 03_200 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[34] 02_201 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[35] 03_201 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[36] 02_202 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[37] 03_202 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[38] 02_203 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[39] 03_203 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[40] 02_204 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[41] 03_204 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[42] 02_205 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[43] 03_205 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[44] 02_206 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[45] 03_206 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[46] 02_207 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[47] 03_207 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[0] 01_216 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[1] 00_217 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[2] 01_217 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[3] 00_218 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[4] 01_218 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[5] 00_219 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[6] 01_219 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[7] 00_220 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[8] 01_220 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[9] 00_221 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[10] 01_221 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[11] 00_222 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[0] 00_208 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[1] 01_208 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[2] 00_209 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[3] 01_209 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[4] 00_210 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[5] 01_210 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[6] 00_211 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[7] 01_211 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[0] 00_212 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[1] 01_212 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[2] 00_213 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[3] 01_213 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[4] 00_214 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[5] 01_214 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[6] 00_215 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[7] 01_215 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PMA_LOOPBACK_CFG[0] 01_207 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[0] 02_520 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[1] 03_520 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[2] 02_521 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[3] 03_521 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[4] 02_522 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[5] 03_522 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[6] 02_523 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[7] 03_523 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[8] 02_524 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[9] 03_524 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[10] 02_525 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[11] 03_525 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[12] 02_526 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[13] 03_526 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[14] 02_527 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[15] 03_527 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[16] 02_528 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[17] 03_528 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[18] 02_529 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[19] 03_529 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[20] 02_530 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[21] 03_530 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[22] 02_531 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[23] 03_531 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[24] 02_532 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[25] 03_532 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[26] 02_533 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[27] 03_533 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[28] 02_534 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[29] 03_534 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[30] 02_535 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[31] 03_535 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[0] 02_336 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[1] 03_336 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[2] 02_337 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[3] 03_337 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[4] 02_338 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[5] 03_338 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[6] 02_339 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[7] 03_339 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[8] 02_340 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[9] 03_340 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[10] 02_341 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[11] 03_341 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[12] 02_342 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[13] 03_342 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[14] 02_343 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[15] 03_343 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[16] 02_344 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[17] 03_344 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[18] 02_345 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[19] 03_345 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[20] 02_346 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[21] 03_346 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[22] 02_347 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[23] 03_347 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[24] 02_348 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[25] 03_348 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[26] 02_349 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[27] 03_349 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[28] 02_350 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[29] 03_350 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[30] 02_351 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[31] 03_351 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PMA_RSV3[0] 02_288 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PMA_RSV3[1] 03_288 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PMA_RSV4[0] 02_156 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PMA_RSV4[1] 03_156 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PMA_RSV4[2] 02_157 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PMA_RSV4[3] 03_157 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PMA_RSV5[0] 03_159 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PMA_RSV6[0] 02_303 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PMA_RSV7[0] 03_303 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_BIAS_CFG[0] 02_112 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_BIAS_CFG[1] 03_112 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_BIAS_CFG[2] 02_113 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_BIAS_CFG[3] 03_113 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_BIAS_CFG[4] 02_114 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_BIAS_CFG[5] 03_114 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_BIAS_CFG[6] 02_115 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_BIAS_CFG[7] 03_115 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_BIAS_CFG[8] 02_116 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_BIAS_CFG[9] 03_116 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_BIAS_CFG[10] 02_117 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_BIAS_CFG[11] 03_117 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_BIAS_CFG[12] 02_118 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_BIAS_CFG[13] 03_118 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_BIAS_CFG[14] 02_119 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_BIAS_CFG[15] 03_119 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_BUFFER_CFG[0] 02_536 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_BUFFER_CFG[1] 03_536 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_BUFFER_CFG[2] 02_537 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_BUFFER_CFG[3] 03_537 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_BUFFER_CFG[4] 02_538 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_BUFFER_CFG[5] 03_538 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_CLKMUX_EN[0] 02_128 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_CM_SEL[0] 00_138 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_CM_SEL[1] 01_138 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_CM_TRIM[0] 02_304 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_CM_TRIM[1] 03_304 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_CM_TRIM[2] 02_305 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_CM_TRIM[3] 03_305 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_DATA_WIDTH[0] 01_141 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_DATA_WIDTH[1] 00_142 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_DATA_WIDTH[2] 01_142 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_DDI_SEL[0] 00_696 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_DDI_SEL[1] 01_696 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_DDI_SEL[2] 00_697 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_DDI_SEL[3] 01_697 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_DDI_SEL[4] 00_698 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_DDI_SEL[5] 01_698 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_DEBUG_CFG[0] 02_616 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_DEBUG_CFG[1] 03_616 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_DEBUG_CFG[2] 02_617 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_DEBUG_CFG[3] 03_617 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_DEBUG_CFG[4] 02_618 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_DEBUG_CFG[5] 03_618 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_DEBUG_CFG[6] 02_619 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_DEBUG_CFG[7] 03_619 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_DEBUG_CFG[8] 02_620 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_DEBUG_CFG[9] 03_620 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_DEBUG_CFG[10] 02_621 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_DEBUG_CFG[11] 03_621 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_DEBUG_CFG[12] 02_622 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_DEBUG_CFG[13] 03_622 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_DEFER_RESET_BUF_EN 02_552 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_DISPERR_SEQ_MATCH 01_495 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_OS_CFG[0] 00_288 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_OS_CFG[1] 01_288 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_OS_CFG[2] 00_289 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_OS_CFG[3] 01_289 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_OS_CFG[4] 00_290 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_OS_CFG[5] 01_290 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_OS_CFG[6] 00_291 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_OS_CFG[7] 01_291 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_OS_CFG[8] 00_292 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_OS_CFG[9] 01_292 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_OS_CFG[10] 00_293 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_OS_CFG[11] 01_293 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_OS_CFG[12] 00_294 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_SIG_VALID_DLY[0] 00_524 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_SIG_VALID_DLY[1] 01_524 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_SIG_VALID_DLY[2] 00_525 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_SIG_VALID_DLY[3] 01_525 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_SIG_VALID_DLY[4] 00_526 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_XCLK_SEL.RXUSR 00_143 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_CLK25_DIV[0] 00_139 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_CLK25_DIV[1] 01_139 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_CLK25_DIV[2] 00_140 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_CLK25_DIV[3] 01_140 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_CLK25_DIV[4] 00_141 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXBUF_ADDR_MODE.FAST 03_555 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXBUF_EIDLE_HI_CNT[0] 02_558 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXBUF_EIDLE_HI_CNT[1] 03_558 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXBUF_EIDLE_HI_CNT[2] 02_559 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXBUF_EIDLE_HI_CNT[3] 03_559 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXBUF_EIDLE_LO_CNT[0] 02_556 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXBUF_EIDLE_LO_CNT[1] 03_556 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXBUF_EIDLE_LO_CNT[2] 02_557 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXBUF_EIDLE_LO_CNT[3] 03_557 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXBUF_EN 02_11 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXBUF_RESET_ON_CB_CHANGE 02_560 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXBUF_RESET_ON_COMMAALIGN 02_561 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXBUF_RESET_ON_EIDLE 02_547 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXBUF_RESET_ON_RATE_CHANGE 03_560 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXBUF_THRESH_OVFLW[0] 03_552 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXBUF_THRESH_OVFLW[1] 02_553 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXBUF_THRESH_OVFLW[2] 03_553 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXBUF_THRESH_OVFLW[3] 02_554 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXBUF_THRESH_OVFLW[4] 03_554 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXBUF_THRESH_OVFLW[5] 02_555 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXBUF_THRESH_OVRD 02_548 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXBUF_THRESH_UNDFLW[0] 02_544 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXBUF_THRESH_UNDFLW[1] 03_544 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXBUF_THRESH_UNDFLW[2] 02_545 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXBUF_THRESH_UNDFLW[3] 03_545 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXBUF_THRESH_UNDFLW[4] 02_546 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXBUF_THRESH_UNDFLW[5] 03_546 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXBUFRESET_TIME[0] 01_101 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXBUFRESET_TIME[1] 00_102 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXBUFRESET_TIME[2] 01_102 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXBUFRESET_TIME[3] 00_103 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXBUFRESET_TIME[4] 01_103 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[0] 02_640 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[1] 03_640 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[2] 02_641 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[3] 03_641 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[4] 02_642 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[5] 03_642 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[6] 02_643 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[7] 03_643 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[8] 02_644 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[9] 03_644 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[10] 02_645 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[11] 03_645 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[12] 02_646 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[13] 03_646 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[14] 02_647 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[15] 03_647 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[16] 02_648 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[17] 03_648 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[18] 02_649 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[19] 03_649 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[20] 02_650 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[21] 03_650 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[22] 02_651 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[23] 03_651 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[24] 02_652 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[25] 03_652 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[26] 02_653 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[27] 03_653 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[28] 02_654 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[29] 03_654 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[30] 02_655 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[31] 03_655 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[32] 02_656 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[33] 03_656 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[34] 02_657 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[35] 03_657 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[36] 02_658 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[37] 03_658 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[38] 02_659 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[39] 03_659 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[40] 02_660 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[41] 03_660 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[42] 02_661 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[43] 03_661 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[44] 02_662 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[45] 03_662 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[46] 02_663 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[47] 03_663 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[48] 02_664 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[49] 03_664 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[50] 02_665 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[51] 03_665 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[52] 02_666 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[53] 03_666 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[54] 02_667 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[55] 03_667 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[56] 02_668 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[57] 03_668 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[58] 02_669 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[59] 03_669 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[60] 02_670 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[61] 03_670 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[62] 02_671 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[63] 03_671 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[64] 02_672 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[65] 03_672 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[66] 02_673 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[67] 03_673 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[68] 02_674 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[69] 03_674 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[70] 02_675 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[71] 03_675 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[72] 02_676 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[73] 03_676 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[74] 02_677 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[75] 03_677 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[76] 02_678 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[77] 03_678 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[78] 02_679 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[79] 03_679 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[80] 02_680 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[81] 03_680 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[82] 02_681 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_FR_RESET_ON_EIDLE[0] 02_638 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_HOLD_DURING_EIDLE[0] 03_637 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_LOCK_CFG[0] 02_632 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_LOCK_CFG[1] 03_632 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_LOCK_CFG[2] 02_633 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_LOCK_CFG[3] 03_633 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_LOCK_CFG[4] 02_634 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_LOCK_CFG[5] 03_634 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_PH_RESET_ON_EIDLE[0] 03_638 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDRFREQRESET_TIME[0] 01_106 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDRFREQRESET_TIME[1] 00_107 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDRFREQRESET_TIME[2] 01_107 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDRFREQRESET_TIME[3] 00_108 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDRFREQRESET_TIME[4] 01_108 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDRPHRESET_TIME[0] 00_109 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDRPHRESET_TIME[1] 01_109 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDRPHRESET_TIME[2] 00_110 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDRPHRESET_TIME[3] 01_110 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDRPHRESET_TIME[4] 00_111 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXDLY_CFG[0] 00_680 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXDLY_CFG[1] 01_680 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXDLY_CFG[2] 00_681 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXDLY_CFG[3] 01_681 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXDLY_CFG[4] 00_682 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXDLY_CFG[5] 01_682 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXDLY_CFG[6] 00_683 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXDLY_CFG[7] 01_683 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXDLY_CFG[8] 00_684 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXDLY_CFG[9] 01_684 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXDLY_CFG[10] 00_685 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXDLY_CFG[11] 01_685 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXDLY_CFG[12] 00_686 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXDLY_CFG[13] 01_686 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXDLY_CFG[14] 00_687 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXDLY_CFG[15] 01_687 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXDLY_LCFG[0] 02_576 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXDLY_LCFG[1] 03_576 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXDLY_LCFG[2] 02_577 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXDLY_LCFG[3] 03_577 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXDLY_LCFG[4] 02_578 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXDLY_LCFG[5] 03_578 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXDLY_LCFG[6] 02_579 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXDLY_LCFG[7] 03_579 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXDLY_LCFG[8] 02_580 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXDLY_TAP_CFG[0] 00_672 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXDLY_TAP_CFG[1] 01_672 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXDLY_TAP_CFG[2] 00_673 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXDLY_TAP_CFG[3] 01_673 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXDLY_TAP_CFG[4] 00_674 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXDLY_TAP_CFG[5] 01_674 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXDLY_TAP_CFG[6] 00_675 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXDLY_TAP_CFG[7] 01_675 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXDLY_TAP_CFG[8] 00_676 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXDLY_TAP_CFG[9] 01_676 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXDLY_TAP_CFG[10] 00_677 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXDLY_TAP_CFG[11] 01_677 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXDLY_TAP_CFG[12] 00_678 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXDLY_TAP_CFG[13] 01_678 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXDLY_TAP_CFG[14] 00_679 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXDLY_TAP_CFG[15] 01_679 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXGEARBOX_EN 01_607 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXISCANRESET_TIME[0] 01_123 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXISCANRESET_TIME[1] 00_124 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXISCANRESET_TIME[2] 01_124 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXISCANRESET_TIME[3] 00_125 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXISCANRESET_TIME[4] 01_125 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPM_BIAS_STARTUP_DISABLE[0] 03_391 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPM_CFG[0] 02_328 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPM_CFG[1] 03_328 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPM_CFG[2] 02_329 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPM_CFG[3] 03_329 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPM_CM_CFG[0] 02_430 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPM_GC_CFG[0] 02_432 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPM_GC_CFG[1] 03_432 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPM_GC_CFG[2] 02_433 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPM_GC_CFG[3] 03_433 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPM_GC_CFG[4] 02_434 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPM_GC_CFG[5] 03_434 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPM_GC_CFG[6] 02_435 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPM_GC_CFG[7] 03_435 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPM_GC_CFG[8] 02_436 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPM_GC_CFG2[0] 03_442 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPM_GC_CFG2[1] 02_443 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPM_GC_CFG2[2] 03_443 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG[0] 00_336 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG[1] 01_336 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG[2] 00_337 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG[3] 01_337 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG[4] 00_338 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG[5] 01_338 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG[6] 00_339 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG[7] 01_339 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG[8] 00_340 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG[9] 01_340 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG[10] 00_341 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG[11] 01_341 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG[12] 00_342 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG[13] 01_342 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG2[0] 02_424 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG2[1] 03_424 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG2[2] 02_425 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG2[3] 03_425 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG2[4] 02_426 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG3[0] 03_389 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG3[1] 02_390 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG3[2] 03_390 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG3[3] 02_391 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPM_HOLD_DURING_EIDLE[0] 00_247 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPM_INCM_CFG[0] 02_439 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPM_IPCM_CFG[0] 03_439 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG[0] 00_344 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG[1] 01_344 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG[2] 00_345 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG[3] 01_345 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG[4] 00_346 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG[5] 01_346 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG[6] 00_347 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG[7] 01_347 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG[8] 00_348 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG[9] 01_348 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG[10] 00_349 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG[11] 01_349 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG[12] 00_350 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG[13] 01_350 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG[14] 00_351 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG[15] 01_351 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG[16] 00_343 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG[17] 01_343 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG2[0] 03_426 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG2[1] 02_427 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG2[2] 03_427 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG2[3] 02_428 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG2[4] 03_428 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPM_OSINT_CFG[0] 02_440 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPM_OSINT_CFG[1] 03_440 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPM_OSINT_CFG[2] 02_441 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPM_CFG1[0] 02_330 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPMRESET_TIME[0] 00_112 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPMRESET_TIME[1] 01_112 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPMRESET_TIME[2] 00_113 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPMRESET_TIME[3] 01_113 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPMRESET_TIME[4] 00_114 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPMRESET_TIME[5] 01_114 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPMRESET_TIME[6] 00_115 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXOOB_CFG[0] 00_144 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXOOB_CFG[1] 01_144 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXOOB_CFG[2] 00_145 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXOOB_CFG[3] 01_145 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXOOB_CFG[4] 00_146 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXOOB_CFG[5] 01_146 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXOOB_CFG[6] 00_147 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXOOB_CLK_CFG.FABRIC 03_129 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXOSCALRESET_TIME[0] 00_187 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXOSCALRESET_TIME[1] 01_187 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXOSCALRESET_TIME[2] 00_188 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXOSCALRESET_TIME[3] 01_188 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXOSCALRESET_TIME[4] 00_189 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXOSCALRESET_TIMEOUT[0] 01_189 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXOSCALRESET_TIMEOUT[1] 00_190 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXOSCALRESET_TIMEOUT[2] 01_190 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXOSCALRESET_TIMEOUT[3] 00_191 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXOSCALRESET_TIMEOUT[4] 01_191 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXOUT_DIV[0] 02_384 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXOUT_DIV[1] 03_384 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXPCSRESET_TIME[0] 01_115 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXPCSRESET_TIME[1] 00_116 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXPCSRESET_TIME[2] 01_116 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXPCSRESET_TIME[3] 00_117 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXPCSRESET_TIME[4] 01_117 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[0] 02_584 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[1] 03_584 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[2] 02_585 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[3] 03_585 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[4] 02_586 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[5] 03_586 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[6] 02_587 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[7] 03_587 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[8] 02_588 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[9] 03_588 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[10] 02_589 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[11] 03_589 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[12] 02_590 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[13] 03_590 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[14] 02_591 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[15] 03_591 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[16] 02_592 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[17] 03_592 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[18] 02_593 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[19] 03_593 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[20] 02_594 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[21] 03_594 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[22] 02_595 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[23] 03_595 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXPH_MONITOR_SEL[0] 00_700 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXPH_MONITOR_SEL[1] 01_700 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXPH_MONITOR_SEL[2] 00_701 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXPH_MONITOR_SEL[3] 01_701 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXPH_MONITOR_SEL[4] 00_702 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[0] 02_600 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[1] 03_600 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[2] 02_601 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[3] 03_601 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[4] 02_602 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[5] 03_602 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[6] 02_603 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[7] 03_603 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[8] 02_604 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[9] 03_604 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[10] 02_605 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[11] 03_605 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[12] 02_606 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[13] 03_606 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[14] 02_607 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[15] 03_607 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[16] 02_608 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[17] 03_608 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[18] 02_609 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[19] 03_609 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[20] 02_610 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[21] 03_610 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[22] 02_611 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[23] 03_611 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXPI_CFG0[0] 03_430 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXPI_CFG0[1] 02_431 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXPI_CFG0[2] 03_431 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXPI_CFG1[0] 02_442 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXPI_CFG2[0] 03_441 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXPMARESET_TIME[0] 00_104 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXPMARESET_TIME[1] 01_104 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXPMARESET_TIME[2] 00_105 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXPMARESET_TIME[3] 01_105 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXPMARESET_TIME[4] 00_106 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXPRBS_ERR_LOOPBACK[0] 00_136 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXSLIDE_AUTO_WAIT[0] 00_520 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXSLIDE_AUTO_WAIT[1] 01_520 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXSLIDE_AUTO_WAIT[2] 00_521 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXSLIDE_AUTO_WAIT[3] 01_521 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXSLIDE_MODE.AUTO 00_519 !01_519 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXSLIDE_MODE.PCS !00_519 01_519 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXSLIDE_MODE.PMA 00_519 01_519 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXSYNC_MULTILANE[0] 00_133 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXSYNC_OVRD[0] 01_135 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXSYNC_SKIP_DA[0] 01_134 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.SAS_MAX_COM[0] 00_171 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.SAS_MAX_COM[1] 01_171 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.SAS_MAX_COM[2] 00_172 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.SAS_MAX_COM[3] 01_172 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.SAS_MAX_COM[4] 00_173 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.SAS_MAX_COM[5] 01_173 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.SAS_MAX_COM[6] 00_174 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.SAS_MIN_COM[0] 01_156 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.SAS_MIN_COM[1] 00_157 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.SAS_MIN_COM[2] 01_157 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.SAS_MIN_COM[3] 00_158 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.SAS_MIN_COM[4] 01_158 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.SAS_MIN_COM[5] 00_159 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.SATA_BURST_SEQ_LEN[0] 00_150 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.SATA_BURST_SEQ_LEN[1] 01_150 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.SATA_BURST_SEQ_LEN[2] 00_151 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.SATA_BURST_SEQ_LEN[3] 01_151 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.SATA_BURST_VAL[0] 01_147 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.SATA_BURST_VAL[1] 00_148 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.SATA_BURST_VAL[2] 01_148 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.SATA_EIDLE_VAL[0] 00_152 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.SATA_EIDLE_VAL[1] 01_152 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.SATA_EIDLE_VAL[2] 00_153 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.SATA_MAX_BURST[0] 00_168 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.SATA_MAX_BURST[1] 01_168 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.SATA_MAX_BURST[2] 00_169 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.SATA_MAX_BURST[3] 01_169 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.SATA_MAX_BURST[4] 00_170 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.SATA_MAX_BURST[5] 01_170 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.SATA_MAX_INIT[0] 00_176 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.SATA_MAX_INIT[1] 01_176 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.SATA_MAX_INIT[2] 00_177 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.SATA_MAX_INIT[3] 01_177 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.SATA_MAX_INIT[4] 00_178 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.SATA_MAX_INIT[5] 01_178 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.SATA_MAX_WAKE[0] 00_179 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.SATA_MAX_WAKE[1] 01_179 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.SATA_MAX_WAKE[2] 00_180 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.SATA_MAX_WAKE[3] 01_180 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.SATA_MAX_WAKE[4] 00_181 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.SATA_MAX_WAKE[5] 01_181 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.SATA_MIN_BURST[0] 01_153 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.SATA_MIN_BURST[1] 00_154 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.SATA_MIN_BURST[2] 01_154 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.SATA_MIN_BURST[3] 00_155 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.SATA_MIN_BURST[4] 01_155 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.SATA_MIN_BURST[5] 00_156 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.SATA_MIN_INIT[0] 00_160 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.SATA_MIN_INIT[1] 01_160 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.SATA_MIN_INIT[2] 00_161 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.SATA_MIN_INIT[3] 01_161 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.SATA_MIN_INIT[4] 00_162 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.SATA_MIN_INIT[5] 01_162 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.SATA_MIN_WAKE[0] 00_163 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.SATA_MIN_WAKE[1] 01_163 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.SATA_MIN_WAKE[2] 00_164 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.SATA_MIN_WAKE[3] 01_164 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.SATA_MIN_WAKE[4] 00_165 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.SATA_MIN_WAKE[5] 01_165 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.SATA_PLL_CFG.VCO_1500MHZ 02_55 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.SATA_PLL_CFG.VCO_750MHZ 03_55 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.SHOW_REALIGN_COMMA 01_522 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TERM_RCAL_CFG[0] 02_136 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TERM_RCAL_CFG[1] 03_136 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TERM_RCAL_CFG[2] 02_137 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TERM_RCAL_CFG[3] 03_137 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TERM_RCAL_CFG[4] 02_138 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TERM_RCAL_CFG[5] 03_138 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TERM_RCAL_CFG[6] 02_139 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TERM_RCAL_CFG[7] 03_139 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TERM_RCAL_CFG[8] 02_140 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TERM_RCAL_CFG[9] 03_140 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TERM_RCAL_CFG[10] 02_141 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TERM_RCAL_CFG[11] 03_141 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TERM_RCAL_CFG[12] 02_142 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TERM_RCAL_CFG[13] 03_142 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TERM_RCAL_CFG[14] 02_143 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TERM_RCAL_OVRD[0] 03_150 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TERM_RCAL_OVRD[1] 02_151 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TERM_RCAL_OVRD[2] 03_151 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TRANS_TIME_RATE[0] 00_192 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TRANS_TIME_RATE[1] 01_192 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TRANS_TIME_RATE[2] 00_193 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TRANS_TIME_RATE[3] 01_193 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TRANS_TIME_RATE[4] 00_194 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TRANS_TIME_RATE[5] 01_194 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TRANS_TIME_RATE[6] 00_195 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TRANS_TIME_RATE[7] 01_195 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TST_RSV[0] 02_504 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TST_RSV[1] 03_504 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TST_RSV[2] 02_505 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TST_RSV[3] 03_505 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TST_RSV[4] 02_506 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TST_RSV[5] 03_506 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TST_RSV[6] 02_507 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TST_RSV[7] 03_507 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TST_RSV[8] 02_508 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TST_RSV[9] 03_508 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TST_RSV[10] 02_509 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TST_RSV[11] 03_509 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TST_RSV[12] 02_510 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TST_RSV[13] 03_510 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TST_RSV[14] 02_511 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TST_RSV[15] 03_511 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TST_RSV[16] 02_512 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TST_RSV[17] 03_512 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TST_RSV[18] 02_513 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TST_RSV[19] 03_513 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TST_RSV[20] 02_514 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TST_RSV[21] 03_514 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TST_RSV[22] 02_515 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TST_RSV[23] 03_515 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TST_RSV[24] 02_516 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TST_RSV[25] 03_516 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TST_RSV[26] 02_517 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TST_RSV[27] 03_517 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TST_RSV[28] 02_518 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TST_RSV[29] 03_518 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TST_RSV[30] 02_519 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TST_RSV[31] 03_519 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_CLKMUX_EN[0] 03_128 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_DATA_WIDTH[0] 02_152 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_DATA_WIDTH[1] 03_152 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_DATA_WIDTH[2] 02_153 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_DRIVE_MODE.PIPE 00_200 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_EIDLE_ASSERT_DELAY[0] 00_203 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_EIDLE_ASSERT_DELAY[1] 01_203 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_EIDLE_ASSERT_DELAY[2] 00_204 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_EIDLE_DEASSERT_DELAY[0] 01_204 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_EIDLE_DEASSERT_DELAY[1] 00_205 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_EIDLE_DEASSERT_DELAY[2] 01_205 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_LOOPBACK_DRIVE_HIZ 01_202 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_MAINCURSOR_SEL[0] 03_289 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_0[0] 02_232 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_0[1] 03_232 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_0[2] 02_233 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_0[3] 03_233 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_0[4] 02_234 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_0[5] 03_234 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_0[6] 02_235 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_1[0] 02_236 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_1[1] 03_236 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_1[2] 02_237 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_1[3] 03_237 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_1[4] 02_238 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_1[5] 03_238 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_1[6] 02_239 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_2[0] 02_240 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_2[1] 03_240 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_2[2] 02_241 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_2[3] 03_241 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_2[4] 02_242 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_2[5] 03_242 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_2[6] 02_243 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_3[0] 02_244 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_3[1] 03_244 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_3[2] 02_245 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_3[3] 03_245 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_3[4] 02_246 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_3[5] 03_246 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_3[6] 02_247 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_4[0] 02_248 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_4[1] 03_248 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_4[2] 02_249 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_4[3] 03_249 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_4[4] 02_250 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_4[5] 03_250 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_4[6] 02_251 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_0[0] 02_252 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_0[1] 03_252 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_0[2] 02_253 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_0[3] 03_253 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_0[4] 02_254 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_0[5] 03_254 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_0[6] 02_255 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_1[0] 02_256 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_1[1] 03_256 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_1[2] 02_257 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_1[3] 03_257 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_1[4] 02_258 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_1[5] 03_258 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_1[6] 02_259 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_2[0] 02_260 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_2[1] 03_260 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_2[2] 02_261 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_2[3] 03_261 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_2[4] 02_262 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_2[5] 03_262 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_2[6] 02_263 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_3[0] 02_264 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_3[1] 03_264 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_3[2] 02_265 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_3[3] 03_265 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_3[4] 02_266 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_3[5] 03_266 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_3[6] 02_267 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_4[0] 02_268 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_4[1] 03_268 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_4[2] 02_269 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_4[3] 03_269 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_4[4] 02_270 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_4[5] 03_270 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_4[6] 02_271 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_PREDRIVER_MODE[0] 00_206 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_RXDETECT_CFG[0] 02_296 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_RXDETECT_CFG[1] 03_296 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_RXDETECT_CFG[2] 02_297 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_RXDETECT_CFG[3] 03_297 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_RXDETECT_CFG[4] 02_298 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_RXDETECT_CFG[5] 03_298 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_RXDETECT_CFG[6] 02_299 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_RXDETECT_CFG[7] 03_299 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_RXDETECT_CFG[8] 02_300 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_RXDETECT_CFG[9] 03_300 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_RXDETECT_CFG[10] 02_301 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_RXDETECT_CFG[11] 03_301 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_RXDETECT_CFG[12] 02_302 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_RXDETECT_CFG[13] 03_302 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_RXDETECT_REF[0] 02_292 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_RXDETECT_REF[1] 03_292 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_RXDETECT_REF[2] 02_293 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_XCLK_SEL.TXUSR 03_11 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_CLK25_DIV[0] 02_144 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_CLK25_DIV[1] 03_144 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_CLK25_DIV[2] 02_145 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_CLK25_DIV[3] 03_145 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_CLK25_DIV[4] 02_146 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_DEEMPH0[0] 02_272 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_DEEMPH0[1] 03_272 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_DEEMPH0[2] 02_273 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_DEEMPH0[3] 03_273 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_DEEMPH0[4] 02_274 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_DEEMPH0[5] 03_274 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_DEEMPH1[0] 02_276 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_DEEMPH1[1] 03_276 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_DEEMPH1[2] 02_277 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_DEEMPH1[3] 03_277 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_DEEMPH1[4] 02_278 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_DEEMPH1[5] 03_278 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXBUF_EN 00_231 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXBUF_RESET_ON_RATE_CHANGE 01_231 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXDLY_CFG[0] 02_80 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXDLY_CFG[1] 03_80 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXDLY_CFG[2] 02_81 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXDLY_CFG[3] 03_81 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXDLY_CFG[4] 02_82 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXDLY_CFG[5] 03_82 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXDLY_CFG[6] 02_83 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXDLY_CFG[7] 03_83 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXDLY_CFG[8] 02_84 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXDLY_CFG[9] 03_84 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXDLY_CFG[10] 02_85 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXDLY_CFG[11] 03_85 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXDLY_CFG[12] 02_86 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXDLY_CFG[13] 03_86 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXDLY_CFG[14] 02_87 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXDLY_CFG[15] 03_87 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXDLY_LCFG[0] 02_568 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXDLY_LCFG[1] 03_568 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXDLY_LCFG[2] 02_569 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXDLY_LCFG[3] 03_569 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXDLY_LCFG[4] 02_570 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXDLY_LCFG[5] 03_570 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXDLY_LCFG[6] 02_571 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXDLY_LCFG[7] 03_571 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXDLY_LCFG[8] 02_572 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXDLY_TAP_CFG[0] 02_88 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXDLY_TAP_CFG[1] 03_88 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXDLY_TAP_CFG[2] 02_89 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXDLY_TAP_CFG[3] 03_89 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXDLY_TAP_CFG[4] 02_90 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXDLY_TAP_CFG[5] 03_90 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXDLY_TAP_CFG[6] 02_91 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXDLY_TAP_CFG[7] 03_91 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXDLY_TAP_CFG[8] 02_92 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXDLY_TAP_CFG[9] 03_92 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXDLY_TAP_CFG[10] 02_93 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXDLY_TAP_CFG[11] 03_93 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXDLY_TAP_CFG[12] 02_94 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXDLY_TAP_CFG[13] 03_94 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXDLY_TAP_CFG[14] 02_95 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXDLY_TAP_CFG[15] 03_95 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXGEARBOX_EN 01_226 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXOOB_CFG[0] 03_20 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXOUT_DIV[0] 02_386 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXOUT_DIV[1] 03_386 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPCSRESET_TIME[0] 01_130 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPCSRESET_TIME[1] 00_131 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPCSRESET_TIME[2] 01_131 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPCSRESET_TIME[3] 00_132 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPCSRESET_TIME[4] 01_132 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPH_CFG[0] 02_96 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPH_CFG[1] 03_96 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPH_CFG[2] 02_97 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPH_CFG[3] 03_97 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPH_CFG[4] 02_98 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPH_CFG[5] 03_98 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPH_CFG[6] 02_99 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPH_CFG[7] 03_99 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPH_CFG[8] 02_100 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPH_CFG[9] 03_100 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPH_CFG[10] 02_101 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPH_CFG[11] 03_101 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPH_CFG[12] 02_102 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPH_CFG[13] 03_102 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPH_CFG[14] 02_103 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPH_CFG[15] 03_103 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPH_MONITOR_SEL[0] 02_108 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPH_MONITOR_SEL[1] 03_108 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPH_MONITOR_SEL[2] 02_109 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPH_MONITOR_SEL[3] 03_109 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPH_MONITOR_SEL[4] 02_110 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[0] 02_64 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[1] 03_64 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[2] 02_65 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[3] 03_65 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[4] 02_66 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[5] 03_66 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[6] 02_67 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[7] 03_67 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[8] 02_68 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[9] 03_68 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[10] 02_69 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[11] 03_69 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[12] 02_70 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[13] 03_70 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[14] 02_71 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[15] 03_71 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[16] 02_72 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[17] 03_72 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[18] 02_73 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[19] 03_73 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[20] 02_74 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[21] 03_74 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[22] 02_75 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[23] 03_75 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPI_GREY_SEL[0] 03_498 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPI_INVSTROBE_SEL[0] 02_498 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPI_PPM_CFG[0] 02_488 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPI_PPM_CFG[1] 03_488 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPI_PPM_CFG[2] 02_489 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPI_PPM_CFG[3] 03_489 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPI_PPM_CFG[4] 02_490 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPI_PPM_CFG[5] 03_490 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPI_PPM_CFG[6] 02_491 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPI_PPM_CFG[7] 03_491 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPI_PPMCLK_SEL.TXUSRCLK2 03_497 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPI_SYNFREQ_PPM[0] 02_496 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPI_SYNFREQ_PPM[1] 03_496 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPI_SYNFREQ_PPM[2] 02_497 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPI_CFG0[0] 02_40 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPI_CFG0[1] 03_40 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPI_CFG1[0] 02_41 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPI_CFG1[1] 03_41 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPI_CFG2[0] 02_42 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPI_CFG2[1] 03_42 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPI_CFG3[0] 02_43 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPI_CFG4[0] 03_43 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPI_CFG5[0] 02_44 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPI_CFG5[1] 03_44 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPI_CFG5[2] 02_45 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPMARESET_TIME[0] 00_128 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPMARESET_TIME[1] 01_128 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPMARESET_TIME[2] 00_129 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPMARESET_TIME[3] 01_129 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPMARESET_TIME[4] 00_130 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXSYNC_MULTILANE[0] 01_133 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXSYNC_OVRD[0] 00_135 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXSYNC_SKIP_DA[0] 00_134 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.UCODEER_CLR[0] 01_00 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.USE_PCS_CLK_PHASE_SEL[0] 02_463 diff --git a/artix7/segbits_gtp_channel_0_mid_left.origin_info.db b/artix7/segbits_gtp_channel_0_mid_left.origin_info.db index 8691662..c6a22e5 100644 --- a/artix7/segbits_gtp_channel_0_mid_left.origin_info.db +++ b/artix7/segbits_gtp_channel_0_mid_left.origin_info.db @@ -1,1627 +1,1627 @@ -GTP_CHANNEL_0_MID_LEFT.GTPE2.ACJTAG_DEBUG_MODE[0] origin:064-gtp-channel-conf 00_07 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ACJTAG_MODE[0] origin:064-gtp-channel-conf 01_06 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ACJTAG_RESET[0] origin:064-gtp-channel-conf 01_07 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ADAPT_CFG0[0] origin:064-gtp-channel-conf 02_464 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ADAPT_CFG0[1] origin:064-gtp-channel-conf 03_464 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ADAPT_CFG0[2] origin:064-gtp-channel-conf 02_465 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ADAPT_CFG0[3] origin:064-gtp-channel-conf 03_465 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ADAPT_CFG0[4] origin:064-gtp-channel-conf 02_466 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ADAPT_CFG0[5] origin:064-gtp-channel-conf 03_466 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ADAPT_CFG0[6] origin:064-gtp-channel-conf 02_467 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ADAPT_CFG0[7] origin:064-gtp-channel-conf 03_467 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ADAPT_CFG0[8] origin:064-gtp-channel-conf 02_468 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ADAPT_CFG0[9] origin:064-gtp-channel-conf 03_468 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ADAPT_CFG0[10] origin:064-gtp-channel-conf 02_469 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ADAPT_CFG0[11] origin:064-gtp-channel-conf 03_469 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ADAPT_CFG0[12] origin:064-gtp-channel-conf 02_470 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ADAPT_CFG0[13] origin:064-gtp-channel-conf 03_470 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ADAPT_CFG0[14] origin:064-gtp-channel-conf 02_471 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ADAPT_CFG0[15] origin:064-gtp-channel-conf 03_471 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ADAPT_CFG0[16] origin:064-gtp-channel-conf 02_472 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ADAPT_CFG0[17] origin:064-gtp-channel-conf 03_472 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ADAPT_CFG0[18] origin:064-gtp-channel-conf 02_473 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ADAPT_CFG0[19] origin:064-gtp-channel-conf 03_473 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ALIGN_COMMA_DOUBLE origin:064-gtp-channel-conf 00_522 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ALIGN_COMMA_ENABLE[0] origin:064-gtp-channel-conf 00_496 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ALIGN_COMMA_ENABLE[1] origin:064-gtp-channel-conf 01_496 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ALIGN_COMMA_ENABLE[2] origin:064-gtp-channel-conf 00_497 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ALIGN_COMMA_ENABLE[3] origin:064-gtp-channel-conf 01_497 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ALIGN_COMMA_ENABLE[4] origin:064-gtp-channel-conf 00_498 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ALIGN_COMMA_ENABLE[5] origin:064-gtp-channel-conf 01_498 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ALIGN_COMMA_ENABLE[6] origin:064-gtp-channel-conf 00_499 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ALIGN_COMMA_ENABLE[7] origin:064-gtp-channel-conf 01_499 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ALIGN_COMMA_ENABLE[8] origin:064-gtp-channel-conf 00_500 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ALIGN_COMMA_ENABLE[9] origin:064-gtp-channel-conf 01_500 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ALIGN_COMMA_WORD[0] origin:064-gtp-channel-conf 01_526 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ALIGN_COMMA_WORD[1] origin:064-gtp-channel-conf 00_527 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ALIGN_MCOMMA_DET origin:064-gtp-channel-conf 00_523 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ALIGN_MCOMMA_VALUE[0] origin:064-gtp-channel-conf 00_504 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ALIGN_MCOMMA_VALUE[1] origin:064-gtp-channel-conf 01_504 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ALIGN_MCOMMA_VALUE[2] origin:064-gtp-channel-conf 00_505 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ALIGN_MCOMMA_VALUE[3] origin:064-gtp-channel-conf 01_505 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ALIGN_MCOMMA_VALUE[4] origin:064-gtp-channel-conf 00_506 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ALIGN_MCOMMA_VALUE[5] origin:064-gtp-channel-conf 01_506 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ALIGN_MCOMMA_VALUE[6] origin:064-gtp-channel-conf 00_507 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ALIGN_MCOMMA_VALUE[7] origin:064-gtp-channel-conf 01_507 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ALIGN_MCOMMA_VALUE[8] origin:064-gtp-channel-conf 00_508 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ALIGN_MCOMMA_VALUE[9] origin:064-gtp-channel-conf 01_508 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ALIGN_PCOMMA_DET origin:064-gtp-channel-conf 01_523 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ALIGN_PCOMMA_VALUE[0] origin:064-gtp-channel-conf 00_512 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ALIGN_PCOMMA_VALUE[1] origin:064-gtp-channel-conf 01_512 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ALIGN_PCOMMA_VALUE[2] origin:064-gtp-channel-conf 00_513 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ALIGN_PCOMMA_VALUE[3] origin:064-gtp-channel-conf 01_513 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ALIGN_PCOMMA_VALUE[4] origin:064-gtp-channel-conf 00_514 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ALIGN_PCOMMA_VALUE[5] origin:064-gtp-channel-conf 01_514 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ALIGN_PCOMMA_VALUE[6] origin:064-gtp-channel-conf 00_515 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ALIGN_PCOMMA_VALUE[7] origin:064-gtp-channel-conf 01_515 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ALIGN_PCOMMA_VALUE[8] origin:064-gtp-channel-conf 00_516 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ALIGN_PCOMMA_VALUE[9] origin:064-gtp-channel-conf 01_516 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CBCC_DATA_SOURCE_SEL.DECODED origin:064-gtp-channel-conf 01_661 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CFOK_CFG[0] origin:064-gtp-channel-conf 02_392 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CFOK_CFG[1] origin:064-gtp-channel-conf 03_392 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CFOK_CFG[2] origin:064-gtp-channel-conf 02_393 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CFOK_CFG[3] origin:064-gtp-channel-conf 03_393 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CFOK_CFG[4] origin:064-gtp-channel-conf 02_394 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CFOK_CFG[5] origin:064-gtp-channel-conf 03_394 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CFOK_CFG[6] origin:064-gtp-channel-conf 02_395 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CFOK_CFG[7] origin:064-gtp-channel-conf 03_395 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CFOK_CFG[8] origin:064-gtp-channel-conf 02_396 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CFOK_CFG[9] origin:064-gtp-channel-conf 03_396 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CFOK_CFG[10] origin:064-gtp-channel-conf 02_397 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CFOK_CFG[11] origin:064-gtp-channel-conf 03_397 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CFOK_CFG[12] origin:064-gtp-channel-conf 02_398 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CFOK_CFG[13] origin:064-gtp-channel-conf 03_398 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CFOK_CFG[14] origin:064-gtp-channel-conf 02_399 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CFOK_CFG[15] origin:064-gtp-channel-conf 03_399 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CFOK_CFG[16] origin:064-gtp-channel-conf 02_400 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CFOK_CFG[17] origin:064-gtp-channel-conf 03_400 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CFOK_CFG[18] origin:064-gtp-channel-conf 02_401 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CFOK_CFG[19] origin:064-gtp-channel-conf 03_401 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CFOK_CFG[20] origin:064-gtp-channel-conf 02_402 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CFOK_CFG[21] origin:064-gtp-channel-conf 03_402 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CFOK_CFG[22] origin:064-gtp-channel-conf 02_403 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CFOK_CFG[23] origin:064-gtp-channel-conf 03_403 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CFOK_CFG[24] origin:064-gtp-channel-conf 02_404 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CFOK_CFG[25] origin:064-gtp-channel-conf 03_404 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CFOK_CFG[26] origin:064-gtp-channel-conf 02_405 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CFOK_CFG[27] origin:064-gtp-channel-conf 03_405 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CFOK_CFG[28] origin:064-gtp-channel-conf 02_406 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CFOK_CFG[29] origin:064-gtp-channel-conf 03_406 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CFOK_CFG[30] origin:064-gtp-channel-conf 02_407 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CFOK_CFG[31] origin:064-gtp-channel-conf 03_407 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CFOK_CFG[32] origin:064-gtp-channel-conf 02_408 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CFOK_CFG[33] origin:064-gtp-channel-conf 03_408 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CFOK_CFG[34] origin:064-gtp-channel-conf 02_409 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CFOK_CFG[35] origin:064-gtp-channel-conf 03_409 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CFOK_CFG[36] origin:064-gtp-channel-conf 02_410 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CFOK_CFG[37] origin:064-gtp-channel-conf 03_410 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CFOK_CFG[38] origin:064-gtp-channel-conf 02_411 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CFOK_CFG[39] origin:064-gtp-channel-conf 03_411 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CFOK_CFG[40] origin:064-gtp-channel-conf 02_412 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CFOK_CFG[41] origin:064-gtp-channel-conf 03_412 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CFOK_CFG[42] origin:064-gtp-channel-conf 02_413 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CFOK_CFG2[0] origin:064-gtp-channel-conf 02_459 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CFOK_CFG2[1] origin:064-gtp-channel-conf 03_459 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CFOK_CFG2[2] origin:064-gtp-channel-conf 02_460 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CFOK_CFG2[3] origin:064-gtp-channel-conf 03_460 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CFOK_CFG2[4] origin:064-gtp-channel-conf 02_461 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CFOK_CFG2[5] origin:064-gtp-channel-conf 03_461 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CFOK_CFG2[6] origin:064-gtp-channel-conf 02_462 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CFOK_CFG3[0] origin:064-gtp-channel-conf 02_416 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CFOK_CFG3[1] origin:064-gtp-channel-conf 03_416 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CFOK_CFG3[2] origin:064-gtp-channel-conf 02_417 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CFOK_CFG3[3] origin:064-gtp-channel-conf 03_417 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CFOK_CFG3[4] origin:064-gtp-channel-conf 02_418 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CFOK_CFG3[5] origin:064-gtp-channel-conf 03_418 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CFOK_CFG3[6] origin:064-gtp-channel-conf 02_419 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CFOK_CFG4[0] origin:064-gtp-channel-conf 03_438 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CFOK_CFG5[0] origin:064-gtp-channel-conf 02_429 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CFOK_CFG5[1] origin:064-gtp-channel-conf 03_429 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CFOK_CFG6[0] origin:064-gtp-channel-conf 03_436 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CFOK_CFG6[1] origin:064-gtp-channel-conf 02_437 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CFOK_CFG6[2] origin:064-gtp-channel-conf 03_437 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CFOK_CFG6[3] origin:064-gtp-channel-conf 02_438 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_KEEP_ALIGN origin:064-gtp-channel-conf 01_631 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_MAX_SKEW[0] origin:064-gtp-channel-conf 00_670 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_MAX_SKEW[1] origin:064-gtp-channel-conf 01_670 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_MAX_SKEW[2] origin:064-gtp-channel-conf 00_671 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_MAX_SKEW[3] origin:064-gtp-channel-conf 01_671 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_1[0] origin:064-gtp-channel-conf 00_608 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_1[1] origin:064-gtp-channel-conf 01_608 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_1[2] origin:064-gtp-channel-conf 00_609 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_1[3] origin:064-gtp-channel-conf 01_609 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_1[4] origin:064-gtp-channel-conf 00_610 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_1[5] origin:064-gtp-channel-conf 01_610 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_1[6] origin:064-gtp-channel-conf 00_611 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_1[7] origin:064-gtp-channel-conf 01_611 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_1[8] origin:064-gtp-channel-conf 00_612 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_1[9] origin:064-gtp-channel-conf 01_612 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_2[0] origin:064-gtp-channel-conf 00_616 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_2[1] origin:064-gtp-channel-conf 01_616 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_2[2] origin:064-gtp-channel-conf 00_617 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_2[3] origin:064-gtp-channel-conf 01_617 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_2[4] origin:064-gtp-channel-conf 00_618 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_2[5] origin:064-gtp-channel-conf 01_618 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_2[6] origin:064-gtp-channel-conf 00_619 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_2[7] origin:064-gtp-channel-conf 01_619 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_2[8] origin:064-gtp-channel-conf 00_620 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_2[9] origin:064-gtp-channel-conf 01_620 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_3[0] origin:064-gtp-channel-conf 00_624 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_3[1] origin:064-gtp-channel-conf 01_624 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_3[2] origin:064-gtp-channel-conf 00_625 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_3[3] origin:064-gtp-channel-conf 01_625 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_3[4] origin:064-gtp-channel-conf 00_626 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_3[5] origin:064-gtp-channel-conf 01_626 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_3[6] origin:064-gtp-channel-conf 00_627 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_3[7] origin:064-gtp-channel-conf 01_627 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_3[8] origin:064-gtp-channel-conf 00_628 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_3[9] origin:064-gtp-channel-conf 01_628 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_4[0] origin:064-gtp-channel-conf 00_632 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_4[1] origin:064-gtp-channel-conf 01_632 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_4[2] origin:064-gtp-channel-conf 00_633 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_4[3] origin:064-gtp-channel-conf 01_633 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_4[4] origin:064-gtp-channel-conf 00_634 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_4[5] origin:064-gtp-channel-conf 01_634 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_4[6] origin:064-gtp-channel-conf 00_635 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_4[7] origin:064-gtp-channel-conf 01_635 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_4[8] origin:064-gtp-channel-conf 00_636 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_4[9] origin:064-gtp-channel-conf 01_636 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_ENABLE[0] origin:064-gtp-channel-conf 00_614 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_ENABLE[1] origin:064-gtp-channel-conf 01_614 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_ENABLE[2] origin:064-gtp-channel-conf 00_615 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_ENABLE[3] origin:064-gtp-channel-conf 01_615 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_1[0] origin:064-gtp-channel-conf 00_640 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_1[1] origin:064-gtp-channel-conf 01_640 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_1[2] origin:064-gtp-channel-conf 00_641 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_1[3] origin:064-gtp-channel-conf 01_641 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_1[4] origin:064-gtp-channel-conf 00_642 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_1[5] origin:064-gtp-channel-conf 01_642 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_1[6] origin:064-gtp-channel-conf 00_643 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_1[7] origin:064-gtp-channel-conf 01_643 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_1[8] origin:064-gtp-channel-conf 00_644 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_1[9] origin:064-gtp-channel-conf 01_644 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_2[0] origin:064-gtp-channel-conf 00_648 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_2[1] origin:064-gtp-channel-conf 01_648 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_2[2] origin:064-gtp-channel-conf 00_649 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_2[3] origin:064-gtp-channel-conf 01_649 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_2[4] origin:064-gtp-channel-conf 00_650 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_2[5] origin:064-gtp-channel-conf 01_650 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_2[6] origin:064-gtp-channel-conf 00_651 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_2[7] origin:064-gtp-channel-conf 01_651 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_2[8] origin:064-gtp-channel-conf 00_652 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_2[9] origin:064-gtp-channel-conf 01_652 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_3[0] origin:064-gtp-channel-conf 00_656 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_3[1] origin:064-gtp-channel-conf 01_656 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_3[2] origin:064-gtp-channel-conf 00_657 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_3[3] origin:064-gtp-channel-conf 01_657 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_3[4] origin:064-gtp-channel-conf 00_658 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_3[5] origin:064-gtp-channel-conf 01_658 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_3[6] origin:064-gtp-channel-conf 00_659 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_3[7] origin:064-gtp-channel-conf 01_659 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_3[8] origin:064-gtp-channel-conf 00_660 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_3[9] origin:064-gtp-channel-conf 01_660 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_4[0] origin:064-gtp-channel-conf 00_664 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_4[1] origin:064-gtp-channel-conf 01_664 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_4[2] origin:064-gtp-channel-conf 00_665 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_4[3] origin:064-gtp-channel-conf 01_665 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_4[4] origin:064-gtp-channel-conf 00_666 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_4[5] origin:064-gtp-channel-conf 01_666 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_4[6] origin:064-gtp-channel-conf 00_667 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_4[7] origin:064-gtp-channel-conf 01_667 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_4[8] origin:064-gtp-channel-conf 00_668 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_4[9] origin:064-gtp-channel-conf 01_668 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_ENABLE[0] origin:064-gtp-channel-conf 00_646 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_ENABLE[1] origin:064-gtp-channel-conf 01_646 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_ENABLE[2] origin:064-gtp-channel-conf 00_647 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_ENABLE[3] origin:064-gtp-channel-conf 01_647 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_USE origin:064-gtp-channel-conf 01_645 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_LEN[0] origin:064-gtp-channel-conf 00_623 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CHAN_BOND_SEQ_LEN[1] origin:064-gtp-channel-conf 01_623 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COMMON_SWING[0] origin:064-gtp-channel-conf 03_311 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_KEEP_IDLE origin:064-gtp-channel-conf 00_591 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_MAX_LAT[0] origin:064-gtp-channel-conf 00_557 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_MAX_LAT[1] origin:064-gtp-channel-conf 01_557 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_MAX_LAT[2] origin:064-gtp-channel-conf 00_558 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_MAX_LAT[3] origin:064-gtp-channel-conf 01_558 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_MAX_LAT[4] origin:064-gtp-channel-conf 00_559 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_MAX_LAT[5] origin:064-gtp-channel-conf 01_559 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_MIN_LAT[0] origin:064-gtp-channel-conf 00_565 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_MIN_LAT[1] origin:064-gtp-channel-conf 01_565 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_MIN_LAT[2] origin:064-gtp-channel-conf 00_566 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_MIN_LAT[3] origin:064-gtp-channel-conf 01_566 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_MIN_LAT[4] origin:064-gtp-channel-conf 00_567 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_MIN_LAT[5] origin:064-gtp-channel-conf 01_567 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_PRECEDENCE origin:064-gtp-channel-conf 00_590 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_REPEAT_WAIT[0] origin:064-gtp-channel-conf 00_573 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_REPEAT_WAIT[1] origin:064-gtp-channel-conf 01_573 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_REPEAT_WAIT[2] origin:064-gtp-channel-conf 00_574 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_REPEAT_WAIT[3] origin:064-gtp-channel-conf 01_574 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_REPEAT_WAIT[4] origin:064-gtp-channel-conf 00_575 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_1_1[0] origin:064-gtp-channel-conf 00_544 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_1_1[1] origin:064-gtp-channel-conf 01_544 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_1_1[2] origin:064-gtp-channel-conf 00_545 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_1_1[3] origin:064-gtp-channel-conf 01_545 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_1_1[4] origin:064-gtp-channel-conf 00_546 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_1_1[5] origin:064-gtp-channel-conf 01_546 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_1_1[6] origin:064-gtp-channel-conf 00_547 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_1_1[7] origin:064-gtp-channel-conf 01_547 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_1_1[8] origin:064-gtp-channel-conf 00_548 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_1_1[9] origin:064-gtp-channel-conf 01_548 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_1_2[0] origin:064-gtp-channel-conf 00_552 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_1_2[1] origin:064-gtp-channel-conf 01_552 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_1_2[2] origin:064-gtp-channel-conf 00_553 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_1_2[3] origin:064-gtp-channel-conf 01_553 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_1_2[4] origin:064-gtp-channel-conf 00_554 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_1_2[5] origin:064-gtp-channel-conf 01_554 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_1_2[6] origin:064-gtp-channel-conf 00_555 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_1_2[7] origin:064-gtp-channel-conf 01_555 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_1_2[8] origin:064-gtp-channel-conf 00_556 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_1_2[9] origin:064-gtp-channel-conf 01_556 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_1_3[0] origin:064-gtp-channel-conf 00_560 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_1_3[1] origin:064-gtp-channel-conf 01_560 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_1_3[2] origin:064-gtp-channel-conf 00_561 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_1_3[3] origin:064-gtp-channel-conf 01_561 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_1_3[4] origin:064-gtp-channel-conf 00_562 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_1_3[5] origin:064-gtp-channel-conf 01_562 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_1_3[6] origin:064-gtp-channel-conf 00_563 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_1_3[7] origin:064-gtp-channel-conf 01_563 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_1_3[8] origin:064-gtp-channel-conf 00_564 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_1_3[9] origin:064-gtp-channel-conf 01_564 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_1_4[0] origin:064-gtp-channel-conf 00_568 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_1_4[1] origin:064-gtp-channel-conf 01_568 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_1_4[2] origin:064-gtp-channel-conf 00_569 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_1_4[3] origin:064-gtp-channel-conf 01_569 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_1_4[4] origin:064-gtp-channel-conf 00_570 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_1_4[5] origin:064-gtp-channel-conf 01_570 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_1_4[6] origin:064-gtp-channel-conf 00_571 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_1_4[7] origin:064-gtp-channel-conf 01_571 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_1_4[8] origin:064-gtp-channel-conf 00_572 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_1_4[9] origin:064-gtp-channel-conf 01_572 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_1_ENABLE[0] origin:064-gtp-channel-conf 00_549 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_1_ENABLE[1] origin:064-gtp-channel-conf 01_549 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_1_ENABLE[2] origin:064-gtp-channel-conf 00_550 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_1_ENABLE[3] origin:064-gtp-channel-conf 01_550 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_2_1[0] origin:064-gtp-channel-conf 00_576 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_2_1[1] origin:064-gtp-channel-conf 01_576 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_2_1[2] origin:064-gtp-channel-conf 00_577 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_2_1[3] origin:064-gtp-channel-conf 01_577 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_2_1[4] origin:064-gtp-channel-conf 00_578 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_2_1[5] origin:064-gtp-channel-conf 01_578 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_2_1[6] origin:064-gtp-channel-conf 00_579 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_2_1[7] origin:064-gtp-channel-conf 01_579 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_2_1[8] origin:064-gtp-channel-conf 00_580 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_2_1[9] origin:064-gtp-channel-conf 01_580 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_2_2[0] origin:064-gtp-channel-conf 00_584 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_2_2[1] origin:064-gtp-channel-conf 01_584 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_2_2[2] origin:064-gtp-channel-conf 00_585 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_2_2[3] origin:064-gtp-channel-conf 01_585 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_2_2[4] origin:064-gtp-channel-conf 00_586 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_2_2[5] origin:064-gtp-channel-conf 01_586 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_2_2[6] origin:064-gtp-channel-conf 00_587 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_2_2[7] origin:064-gtp-channel-conf 01_587 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_2_2[8] origin:064-gtp-channel-conf 00_588 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_2_2[9] origin:064-gtp-channel-conf 01_588 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_2_3[0] origin:064-gtp-channel-conf 00_592 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_2_3[1] origin:064-gtp-channel-conf 01_592 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_2_3[2] origin:064-gtp-channel-conf 00_593 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_2_3[3] origin:064-gtp-channel-conf 01_593 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_2_3[4] origin:064-gtp-channel-conf 00_594 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_2_3[5] origin:064-gtp-channel-conf 01_594 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_2_3[6] origin:064-gtp-channel-conf 00_595 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_2_3[7] origin:064-gtp-channel-conf 01_595 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_2_3[8] origin:064-gtp-channel-conf 00_596 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_2_3[9] origin:064-gtp-channel-conf 01_596 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_2_4[0] origin:064-gtp-channel-conf 00_600 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_2_4[1] origin:064-gtp-channel-conf 01_600 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_2_4[2] origin:064-gtp-channel-conf 00_601 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_2_4[3] origin:064-gtp-channel-conf 01_601 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_2_4[4] origin:064-gtp-channel-conf 00_602 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_2_4[5] origin:064-gtp-channel-conf 01_602 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_2_4[6] origin:064-gtp-channel-conf 00_603 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_2_4[7] origin:064-gtp-channel-conf 01_603 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_2_4[8] origin:064-gtp-channel-conf 00_604 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_2_4[9] origin:064-gtp-channel-conf 01_604 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_2_ENABLE[0] origin:064-gtp-channel-conf 00_581 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_2_ENABLE[1] origin:064-gtp-channel-conf 01_581 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_2_ENABLE[2] origin:064-gtp-channel-conf 00_582 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_2_ENABLE[3] origin:064-gtp-channel-conf 01_582 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_2_USE origin:064-gtp-channel-conf 00_583 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_LEN[0] origin:064-gtp-channel-conf 00_589 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_COR_SEQ_LEN[1] origin:064-gtp-channel-conf 01_589 -GTP_CHANNEL_0_MID_LEFT.GTPE2.CLK_CORRECT_USE origin:064-gtp-channel-conf 00_551 -GTP_CHANNEL_0_MID_LEFT.GTPE2.DEC_MCOMMA_DETECT origin:064-gtp-channel-conf 01_494 -GTP_CHANNEL_0_MID_LEFT.GTPE2.DEC_PCOMMA_DETECT origin:064-gtp-channel-conf 00_495 -GTP_CHANNEL_0_MID_LEFT.GTPE2.DEC_VALID_COMMA_ONLY origin:064-gtp-channel-conf 00_494 -GTP_CHANNEL_0_MID_LEFT.GTPE2.DMONITOR_CFG[0] origin:064-gtp-channel-conf 02_368 -GTP_CHANNEL_0_MID_LEFT.GTPE2.DMONITOR_CFG[1] origin:064-gtp-channel-conf 03_368 -GTP_CHANNEL_0_MID_LEFT.GTPE2.DMONITOR_CFG[2] origin:064-gtp-channel-conf 02_369 -GTP_CHANNEL_0_MID_LEFT.GTPE2.DMONITOR_CFG[3] origin:064-gtp-channel-conf 03_369 -GTP_CHANNEL_0_MID_LEFT.GTPE2.DMONITOR_CFG[4] origin:064-gtp-channel-conf 02_370 -GTP_CHANNEL_0_MID_LEFT.GTPE2.DMONITOR_CFG[5] origin:064-gtp-channel-conf 03_370 -GTP_CHANNEL_0_MID_LEFT.GTPE2.DMONITOR_CFG[6] origin:064-gtp-channel-conf 02_371 -GTP_CHANNEL_0_MID_LEFT.GTPE2.DMONITOR_CFG[7] origin:064-gtp-channel-conf 03_371 -GTP_CHANNEL_0_MID_LEFT.GTPE2.DMONITOR_CFG[8] origin:064-gtp-channel-conf 02_372 -GTP_CHANNEL_0_MID_LEFT.GTPE2.DMONITOR_CFG[9] origin:064-gtp-channel-conf 03_372 -GTP_CHANNEL_0_MID_LEFT.GTPE2.DMONITOR_CFG[10] origin:064-gtp-channel-conf 02_373 -GTP_CHANNEL_0_MID_LEFT.GTPE2.DMONITOR_CFG[11] origin:064-gtp-channel-conf 03_373 -GTP_CHANNEL_0_MID_LEFT.GTPE2.DMONITOR_CFG[12] origin:064-gtp-channel-conf 02_374 -GTP_CHANNEL_0_MID_LEFT.GTPE2.DMONITOR_CFG[13] origin:064-gtp-channel-conf 03_374 -GTP_CHANNEL_0_MID_LEFT.GTPE2.DMONITOR_CFG[14] origin:064-gtp-channel-conf 02_375 -GTP_CHANNEL_0_MID_LEFT.GTPE2.DMONITOR_CFG[15] origin:064-gtp-channel-conf 03_375 -GTP_CHANNEL_0_MID_LEFT.GTPE2.DMONITOR_CFG[16] origin:064-gtp-channel-conf 02_376 -GTP_CHANNEL_0_MID_LEFT.GTPE2.DMONITOR_CFG[17] origin:064-gtp-channel-conf 03_376 -GTP_CHANNEL_0_MID_LEFT.GTPE2.DMONITOR_CFG[18] origin:064-gtp-channel-conf 02_377 -GTP_CHANNEL_0_MID_LEFT.GTPE2.DMONITOR_CFG[19] origin:064-gtp-channel-conf 03_377 -GTP_CHANNEL_0_MID_LEFT.GTPE2.DMONITOR_CFG[20] origin:064-gtp-channel-conf 02_378 -GTP_CHANNEL_0_MID_LEFT.GTPE2.DMONITOR_CFG[21] origin:064-gtp-channel-conf 03_378 -GTP_CHANNEL_0_MID_LEFT.GTPE2.DMONITOR_CFG[22] origin:064-gtp-channel-conf 02_379 -GTP_CHANNEL_0_MID_LEFT.GTPE2.DMONITOR_CFG[23] origin:064-gtp-channel-conf 03_379 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_CLK_PHASE_SEL[0] origin:064-gtp-channel-conf 03_463 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_CONTROL[0] origin:064-gtp-channel-conf 00_488 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_CONTROL[1] origin:064-gtp-channel-conf 01_488 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_CONTROL[2] origin:064-gtp-channel-conf 00_489 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_CONTROL[3] origin:064-gtp-channel-conf 01_489 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_CONTROL[4] origin:064-gtp-channel-conf 00_490 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_CONTROL[5] origin:064-gtp-channel-conf 01_490 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_ERRDET_EN origin:064-gtp-channel-conf 01_492 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_EYE_SCAN_EN origin:064-gtp-channel-conf 00_492 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_HORZ_OFFSET[0] origin:064-gtp-channel-conf 00_480 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_HORZ_OFFSET[1] origin:064-gtp-channel-conf 01_480 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_HORZ_OFFSET[2] origin:064-gtp-channel-conf 00_481 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_HORZ_OFFSET[3] origin:064-gtp-channel-conf 01_481 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_HORZ_OFFSET[4] origin:064-gtp-channel-conf 00_482 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_HORZ_OFFSET[5] origin:064-gtp-channel-conf 01_482 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_HORZ_OFFSET[6] origin:064-gtp-channel-conf 00_483 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_HORZ_OFFSET[7] origin:064-gtp-channel-conf 01_483 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_HORZ_OFFSET[8] origin:064-gtp-channel-conf 00_484 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_HORZ_OFFSET[9] origin:064-gtp-channel-conf 01_484 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_HORZ_OFFSET[10] origin:064-gtp-channel-conf 00_485 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_HORZ_OFFSET[11] origin:064-gtp-channel-conf 01_485 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_PMA_CFG[0] origin:064-gtp-channel-conf 02_624 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_PMA_CFG[1] origin:064-gtp-channel-conf 03_624 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_PMA_CFG[2] origin:064-gtp-channel-conf 02_625 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_PMA_CFG[3] origin:064-gtp-channel-conf 03_625 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_PMA_CFG[4] origin:064-gtp-channel-conf 02_626 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_PMA_CFG[5] origin:064-gtp-channel-conf 03_626 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_PMA_CFG[6] origin:064-gtp-channel-conf 02_627 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_PMA_CFG[7] origin:064-gtp-channel-conf 03_627 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_PMA_CFG[8] origin:064-gtp-channel-conf 02_628 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_PMA_CFG[9] origin:064-gtp-channel-conf 03_628 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_PRESCALE[0] origin:064-gtp-channel-conf 01_477 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_PRESCALE[1] origin:064-gtp-channel-conf 00_478 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_PRESCALE[2] origin:064-gtp-channel-conf 01_478 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_PRESCALE[3] origin:064-gtp-channel-conf 00_479 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_PRESCALE[4] origin:064-gtp-channel-conf 01_479 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[0] origin:064-gtp-channel-conf 00_392 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[1] origin:064-gtp-channel-conf 01_392 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[2] origin:064-gtp-channel-conf 00_393 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[3] origin:064-gtp-channel-conf 01_393 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[4] origin:064-gtp-channel-conf 00_394 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[5] origin:064-gtp-channel-conf 01_394 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[6] origin:064-gtp-channel-conf 00_395 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[7] origin:064-gtp-channel-conf 01_395 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[8] origin:064-gtp-channel-conf 00_396 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[9] origin:064-gtp-channel-conf 01_396 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[10] origin:064-gtp-channel-conf 00_397 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[11] origin:064-gtp-channel-conf 01_397 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[12] origin:064-gtp-channel-conf 00_398 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[13] origin:064-gtp-channel-conf 01_398 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[14] origin:064-gtp-channel-conf 00_399 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[15] origin:064-gtp-channel-conf 01_399 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[16] origin:064-gtp-channel-conf 00_400 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[17] origin:064-gtp-channel-conf 01_400 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[18] origin:064-gtp-channel-conf 00_401 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[19] origin:064-gtp-channel-conf 01_401 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[20] origin:064-gtp-channel-conf 00_402 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[21] origin:064-gtp-channel-conf 01_402 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[22] origin:064-gtp-channel-conf 00_403 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[23] origin:064-gtp-channel-conf 01_403 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[24] origin:064-gtp-channel-conf 00_404 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[25] origin:064-gtp-channel-conf 01_404 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[26] origin:064-gtp-channel-conf 00_405 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[27] origin:064-gtp-channel-conf 01_405 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[28] origin:064-gtp-channel-conf 00_406 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[29] origin:064-gtp-channel-conf 01_406 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[30] origin:064-gtp-channel-conf 00_407 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[31] origin:064-gtp-channel-conf 01_407 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[32] origin:064-gtp-channel-conf 00_408 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[33] origin:064-gtp-channel-conf 01_408 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[34] origin:064-gtp-channel-conf 00_409 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[35] origin:064-gtp-channel-conf 01_409 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[36] origin:064-gtp-channel-conf 00_410 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[37] origin:064-gtp-channel-conf 01_410 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[38] origin:064-gtp-channel-conf 00_411 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[39] origin:064-gtp-channel-conf 01_411 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[40] origin:064-gtp-channel-conf 00_412 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[41] origin:064-gtp-channel-conf 01_412 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[42] origin:064-gtp-channel-conf 00_413 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[43] origin:064-gtp-channel-conf 01_413 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[44] origin:064-gtp-channel-conf 00_414 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[45] origin:064-gtp-channel-conf 01_414 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[46] origin:064-gtp-channel-conf 00_415 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[47] origin:064-gtp-channel-conf 01_415 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[48] origin:064-gtp-channel-conf 00_416 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[49] origin:064-gtp-channel-conf 01_416 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[50] origin:064-gtp-channel-conf 00_417 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[51] origin:064-gtp-channel-conf 01_417 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[52] origin:064-gtp-channel-conf 00_418 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[53] origin:064-gtp-channel-conf 01_418 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[54] origin:064-gtp-channel-conf 00_419 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[55] origin:064-gtp-channel-conf 01_419 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[56] origin:064-gtp-channel-conf 00_420 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[57] origin:064-gtp-channel-conf 01_420 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[58] origin:064-gtp-channel-conf 00_421 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[59] origin:064-gtp-channel-conf 01_421 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[60] origin:064-gtp-channel-conf 00_422 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[61] origin:064-gtp-channel-conf 01_422 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[62] origin:064-gtp-channel-conf 00_423 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[63] origin:064-gtp-channel-conf 01_423 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[64] origin:064-gtp-channel-conf 00_424 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[65] origin:064-gtp-channel-conf 01_424 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[66] origin:064-gtp-channel-conf 00_425 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[67] origin:064-gtp-channel-conf 01_425 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[68] origin:064-gtp-channel-conf 00_426 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[69] origin:064-gtp-channel-conf 01_426 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[70] origin:064-gtp-channel-conf 00_427 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[71] origin:064-gtp-channel-conf 01_427 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[72] origin:064-gtp-channel-conf 00_428 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[73] origin:064-gtp-channel-conf 01_428 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[74] origin:064-gtp-channel-conf 00_429 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[75] origin:064-gtp-channel-conf 01_429 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[76] origin:064-gtp-channel-conf 00_430 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[77] origin:064-gtp-channel-conf 01_430 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[78] origin:064-gtp-channel-conf 00_431 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUAL_MASK[79] origin:064-gtp-channel-conf 01_431 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[0] origin:064-gtp-channel-conf 00_352 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[1] origin:064-gtp-channel-conf 01_352 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[2] origin:064-gtp-channel-conf 00_353 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[3] origin:064-gtp-channel-conf 01_353 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[4] origin:064-gtp-channel-conf 00_354 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[5] origin:064-gtp-channel-conf 01_354 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[6] origin:064-gtp-channel-conf 00_355 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[7] origin:064-gtp-channel-conf 01_355 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[8] origin:064-gtp-channel-conf 00_356 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[9] origin:064-gtp-channel-conf 01_356 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[10] origin:064-gtp-channel-conf 00_357 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[11] origin:064-gtp-channel-conf 01_357 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[12] origin:064-gtp-channel-conf 00_358 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[13] origin:064-gtp-channel-conf 01_358 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[14] origin:064-gtp-channel-conf 00_359 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[15] origin:064-gtp-channel-conf 01_359 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[16] origin:064-gtp-channel-conf 00_360 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[17] origin:064-gtp-channel-conf 01_360 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[18] origin:064-gtp-channel-conf 00_361 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[19] origin:064-gtp-channel-conf 01_361 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[20] origin:064-gtp-channel-conf 00_362 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[21] origin:064-gtp-channel-conf 01_362 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[22] origin:064-gtp-channel-conf 00_363 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[23] origin:064-gtp-channel-conf 01_363 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[24] origin:064-gtp-channel-conf 00_364 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[25] origin:064-gtp-channel-conf 01_364 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[26] origin:064-gtp-channel-conf 00_365 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[27] origin:064-gtp-channel-conf 01_365 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[28] origin:064-gtp-channel-conf 00_366 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[29] origin:064-gtp-channel-conf 01_366 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[30] origin:064-gtp-channel-conf 00_367 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[31] origin:064-gtp-channel-conf 01_367 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[32] origin:064-gtp-channel-conf 00_368 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[33] origin:064-gtp-channel-conf 01_368 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[34] origin:064-gtp-channel-conf 00_369 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[35] origin:064-gtp-channel-conf 01_369 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[36] origin:064-gtp-channel-conf 00_370 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[37] origin:064-gtp-channel-conf 01_370 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[38] origin:064-gtp-channel-conf 00_371 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[39] origin:064-gtp-channel-conf 01_371 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[40] origin:064-gtp-channel-conf 00_372 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[41] origin:064-gtp-channel-conf 01_372 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[42] origin:064-gtp-channel-conf 00_373 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[43] origin:064-gtp-channel-conf 01_373 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[44] origin:064-gtp-channel-conf 00_374 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[45] origin:064-gtp-channel-conf 01_374 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[46] origin:064-gtp-channel-conf 00_375 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[47] origin:064-gtp-channel-conf 01_375 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[48] origin:064-gtp-channel-conf 00_376 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[49] origin:064-gtp-channel-conf 01_376 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[50] origin:064-gtp-channel-conf 00_377 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[51] origin:064-gtp-channel-conf 01_377 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[52] origin:064-gtp-channel-conf 00_378 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[53] origin:064-gtp-channel-conf 01_378 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[54] origin:064-gtp-channel-conf 00_379 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[55] origin:064-gtp-channel-conf 01_379 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[56] origin:064-gtp-channel-conf 00_380 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[57] origin:064-gtp-channel-conf 01_380 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[58] origin:064-gtp-channel-conf 00_381 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[59] origin:064-gtp-channel-conf 01_381 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[60] origin:064-gtp-channel-conf 00_382 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[61] origin:064-gtp-channel-conf 01_382 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[62] origin:064-gtp-channel-conf 00_383 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[63] origin:064-gtp-channel-conf 01_383 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[64] origin:064-gtp-channel-conf 00_384 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[65] origin:064-gtp-channel-conf 01_384 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[66] origin:064-gtp-channel-conf 00_385 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[67] origin:064-gtp-channel-conf 01_385 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[68] origin:064-gtp-channel-conf 00_386 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[69] origin:064-gtp-channel-conf 01_386 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[70] origin:064-gtp-channel-conf 00_387 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[71] origin:064-gtp-channel-conf 01_387 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[72] origin:064-gtp-channel-conf 00_388 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[73] origin:064-gtp-channel-conf 01_388 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[74] origin:064-gtp-channel-conf 00_389 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[75] origin:064-gtp-channel-conf 01_389 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[76] origin:064-gtp-channel-conf 00_390 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[77] origin:064-gtp-channel-conf 01_390 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[78] origin:064-gtp-channel-conf 00_391 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_QUALIFIER[79] origin:064-gtp-channel-conf 01_391 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[0] origin:064-gtp-channel-conf 00_432 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[1] origin:064-gtp-channel-conf 01_432 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[2] origin:064-gtp-channel-conf 00_433 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[3] origin:064-gtp-channel-conf 01_433 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[4] origin:064-gtp-channel-conf 00_434 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[5] origin:064-gtp-channel-conf 01_434 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[6] origin:064-gtp-channel-conf 00_435 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[7] origin:064-gtp-channel-conf 01_435 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[8] origin:064-gtp-channel-conf 00_436 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[9] origin:064-gtp-channel-conf 01_436 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[10] origin:064-gtp-channel-conf 00_437 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[11] origin:064-gtp-channel-conf 01_437 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[12] origin:064-gtp-channel-conf 00_438 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[13] origin:064-gtp-channel-conf 01_438 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[14] origin:064-gtp-channel-conf 00_439 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[15] origin:064-gtp-channel-conf 01_439 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[16] origin:064-gtp-channel-conf 00_440 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[17] origin:064-gtp-channel-conf 01_440 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[18] origin:064-gtp-channel-conf 00_441 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[19] origin:064-gtp-channel-conf 01_441 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[20] origin:064-gtp-channel-conf 00_442 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[21] origin:064-gtp-channel-conf 01_442 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[22] origin:064-gtp-channel-conf 00_443 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[23] origin:064-gtp-channel-conf 01_443 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[24] origin:064-gtp-channel-conf 00_444 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[25] origin:064-gtp-channel-conf 01_444 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[26] origin:064-gtp-channel-conf 00_445 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[27] origin:064-gtp-channel-conf 01_445 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[28] origin:064-gtp-channel-conf 00_446 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[29] origin:064-gtp-channel-conf 01_446 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[30] origin:064-gtp-channel-conf 00_447 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[31] origin:064-gtp-channel-conf 01_447 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[32] origin:064-gtp-channel-conf 00_448 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[33] origin:064-gtp-channel-conf 01_448 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[34] origin:064-gtp-channel-conf 00_449 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[35] origin:064-gtp-channel-conf 01_449 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[36] origin:064-gtp-channel-conf 00_450 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[37] origin:064-gtp-channel-conf 01_450 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[38] origin:064-gtp-channel-conf 00_451 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[39] origin:064-gtp-channel-conf 01_451 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[40] origin:064-gtp-channel-conf 00_452 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[41] origin:064-gtp-channel-conf 01_452 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[42] origin:064-gtp-channel-conf 00_453 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[43] origin:064-gtp-channel-conf 01_453 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[44] origin:064-gtp-channel-conf 00_454 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[45] origin:064-gtp-channel-conf 01_454 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[46] origin:064-gtp-channel-conf 00_455 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[47] origin:064-gtp-channel-conf 01_455 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[48] origin:064-gtp-channel-conf 00_456 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[49] origin:064-gtp-channel-conf 01_456 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[50] origin:064-gtp-channel-conf 00_457 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[51] origin:064-gtp-channel-conf 01_457 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[52] origin:064-gtp-channel-conf 00_458 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[53] origin:064-gtp-channel-conf 01_458 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[54] origin:064-gtp-channel-conf 00_459 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[55] origin:064-gtp-channel-conf 01_459 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[56] origin:064-gtp-channel-conf 00_460 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[57] origin:064-gtp-channel-conf 01_460 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[58] origin:064-gtp-channel-conf 00_461 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[59] origin:064-gtp-channel-conf 01_461 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[60] origin:064-gtp-channel-conf 00_462 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[61] origin:064-gtp-channel-conf 01_462 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[62] origin:064-gtp-channel-conf 00_463 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[63] origin:064-gtp-channel-conf 01_463 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[64] origin:064-gtp-channel-conf 00_464 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[65] origin:064-gtp-channel-conf 01_464 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[66] origin:064-gtp-channel-conf 00_465 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[67] origin:064-gtp-channel-conf 01_465 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[68] origin:064-gtp-channel-conf 00_466 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[69] origin:064-gtp-channel-conf 01_466 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[70] origin:064-gtp-channel-conf 00_467 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[71] origin:064-gtp-channel-conf 01_467 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[72] origin:064-gtp-channel-conf 00_468 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[73] origin:064-gtp-channel-conf 01_468 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[74] origin:064-gtp-channel-conf 00_469 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[75] origin:064-gtp-channel-conf 01_469 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[76] origin:064-gtp-channel-conf 00_470 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[77] origin:064-gtp-channel-conf 01_470 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[78] origin:064-gtp-channel-conf 00_471 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_SDATA_MASK[79] origin:064-gtp-channel-conf 01_471 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_VERT_OFFSET[0] origin:064-gtp-channel-conf 00_472 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_VERT_OFFSET[1] origin:064-gtp-channel-conf 01_472 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_VERT_OFFSET[2] origin:064-gtp-channel-conf 00_473 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_VERT_OFFSET[3] origin:064-gtp-channel-conf 01_473 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_VERT_OFFSET[4] origin:064-gtp-channel-conf 00_474 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_VERT_OFFSET[5] origin:064-gtp-channel-conf 01_474 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_VERT_OFFSET[6] origin:064-gtp-channel-conf 00_475 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_VERT_OFFSET[7] origin:064-gtp-channel-conf 01_475 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ES_VERT_OFFSET[8] origin:064-gtp-channel-conf 00_476 -GTP_CHANNEL_0_MID_LEFT.GTPE2.FTS_DESKEW_SEQ_ENABLE[0] origin:064-gtp-channel-conf 00_662 -GTP_CHANNEL_0_MID_LEFT.GTPE2.FTS_DESKEW_SEQ_ENABLE[1] origin:064-gtp-channel-conf 01_662 -GTP_CHANNEL_0_MID_LEFT.GTPE2.FTS_DESKEW_SEQ_ENABLE[2] origin:064-gtp-channel-conf 00_663 -GTP_CHANNEL_0_MID_LEFT.GTPE2.FTS_DESKEW_SEQ_ENABLE[3] origin:064-gtp-channel-conf 01_663 -GTP_CHANNEL_0_MID_LEFT.GTPE2.FTS_LANE_DESKEW_CFG[0] origin:064-gtp-channel-conf 00_654 -GTP_CHANNEL_0_MID_LEFT.GTPE2.FTS_LANE_DESKEW_CFG[1] origin:064-gtp-channel-conf 01_654 -GTP_CHANNEL_0_MID_LEFT.GTPE2.FTS_LANE_DESKEW_CFG[2] origin:064-gtp-channel-conf 00_655 -GTP_CHANNEL_0_MID_LEFT.GTPE2.FTS_LANE_DESKEW_CFG[3] origin:064-gtp-channel-conf 01_655 -GTP_CHANNEL_0_MID_LEFT.GTPE2.FTS_LANE_DESKEW_EN origin:064-gtp-channel-conf 01_653 -GTP_CHANNEL_0_MID_LEFT.GTPE2.GEARBOX_MODE[0] origin:064-gtp-channel-conf 00_224 -GTP_CHANNEL_0_MID_LEFT.GTPE2.GEARBOX_MODE[1] origin:064-gtp-channel-conf 01_224 -GTP_CHANNEL_0_MID_LEFT.GTPE2.GEARBOX_MODE[2] origin:064-gtp-channel-conf 00_225 -GTP_CHANNEL_0_MID_LEFT.GTPE2.IN_USE origin:064-gtp-channel-conf 00_00 00_01 00_47 00_52 00_53 00_65 01_01 01_47 02_129 -GTP_CHANNEL_0_MID_LEFT.GTPE2.LOOPBACK_CFG[0] origin:064-gtp-channel-conf 02_20 -GTP_CHANNEL_0_MID_LEFT.GTPE2.OUTREFCLK_SEL_INV[0] origin:064-gtp-channel-conf 00_149 -GTP_CHANNEL_0_MID_LEFT.GTPE2.OUTREFCLK_SEL_INV[1] origin:064-gtp-channel-conf 01_149 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PCS_PCIE_EN origin:064-gtp-channel-conf 00_216 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PCS_RSVD_ATTR[0] origin:064-gtp-channel-conf 02_184 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PCS_RSVD_ATTR[1] origin:064-gtp-channel-conf 03_184 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PCS_RSVD_ATTR[2] origin:064-gtp-channel-conf 02_185 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PCS_RSVD_ATTR[3] origin:064-gtp-channel-conf 03_185 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PCS_RSVD_ATTR[4] origin:064-gtp-channel-conf 02_186 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PCS_RSVD_ATTR[5] origin:064-gtp-channel-conf 03_186 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PCS_RSVD_ATTR[6] origin:064-gtp-channel-conf 02_187 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PCS_RSVD_ATTR[7] origin:064-gtp-channel-conf 03_187 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PCS_RSVD_ATTR[8] origin:064-gtp-channel-conf 02_188 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PCS_RSVD_ATTR[9] origin:064-gtp-channel-conf 03_188 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PCS_RSVD_ATTR[10] origin:064-gtp-channel-conf 02_189 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PCS_RSVD_ATTR[11] origin:064-gtp-channel-conf 03_189 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PCS_RSVD_ATTR[12] origin:064-gtp-channel-conf 02_190 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PCS_RSVD_ATTR[13] origin:064-gtp-channel-conf 03_190 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PCS_RSVD_ATTR[14] origin:064-gtp-channel-conf 02_191 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PCS_RSVD_ATTR[15] origin:064-gtp-channel-conf 03_191 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PCS_RSVD_ATTR[16] origin:064-gtp-channel-conf 02_192 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PCS_RSVD_ATTR[17] origin:064-gtp-channel-conf 03_192 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PCS_RSVD_ATTR[18] origin:064-gtp-channel-conf 02_193 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PCS_RSVD_ATTR[19] origin:064-gtp-channel-conf 03_193 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PCS_RSVD_ATTR[20] origin:064-gtp-channel-conf 02_194 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PCS_RSVD_ATTR[21] origin:064-gtp-channel-conf 03_194 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PCS_RSVD_ATTR[22] origin:064-gtp-channel-conf 02_195 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PCS_RSVD_ATTR[23] origin:064-gtp-channel-conf 03_195 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PCS_RSVD_ATTR[24] origin:064-gtp-channel-conf 02_196 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PCS_RSVD_ATTR[25] origin:064-gtp-channel-conf 03_196 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PCS_RSVD_ATTR[26] origin:064-gtp-channel-conf 02_197 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PCS_RSVD_ATTR[27] origin:064-gtp-channel-conf 03_197 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PCS_RSVD_ATTR[28] origin:064-gtp-channel-conf 02_198 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PCS_RSVD_ATTR[29] origin:064-gtp-channel-conf 03_198 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PCS_RSVD_ATTR[30] origin:064-gtp-channel-conf 02_199 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PCS_RSVD_ATTR[31] origin:064-gtp-channel-conf 03_199 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PCS_RSVD_ATTR[32] origin:064-gtp-channel-conf 02_200 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PCS_RSVD_ATTR[33] origin:064-gtp-channel-conf 03_200 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PCS_RSVD_ATTR[34] origin:064-gtp-channel-conf 02_201 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PCS_RSVD_ATTR[35] origin:064-gtp-channel-conf 03_201 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PCS_RSVD_ATTR[36] origin:064-gtp-channel-conf 02_202 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PCS_RSVD_ATTR[37] origin:064-gtp-channel-conf 03_202 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PCS_RSVD_ATTR[38] origin:064-gtp-channel-conf 02_203 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PCS_RSVD_ATTR[39] origin:064-gtp-channel-conf 03_203 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PCS_RSVD_ATTR[40] origin:064-gtp-channel-conf 02_204 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PCS_RSVD_ATTR[41] origin:064-gtp-channel-conf 03_204 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PCS_RSVD_ATTR[42] origin:064-gtp-channel-conf 02_205 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PCS_RSVD_ATTR[43] origin:064-gtp-channel-conf 03_205 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PCS_RSVD_ATTR[44] origin:064-gtp-channel-conf 02_206 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PCS_RSVD_ATTR[45] origin:064-gtp-channel-conf 03_206 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PCS_RSVD_ATTR[46] origin:064-gtp-channel-conf 02_207 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PCS_RSVD_ATTR[47] origin:064-gtp-channel-conf 03_207 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PD_TRANS_TIME_FROM_P2[0] origin:064-gtp-channel-conf 01_216 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PD_TRANS_TIME_FROM_P2[1] origin:064-gtp-channel-conf 00_217 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PD_TRANS_TIME_FROM_P2[2] origin:064-gtp-channel-conf 01_217 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PD_TRANS_TIME_FROM_P2[3] origin:064-gtp-channel-conf 00_218 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PD_TRANS_TIME_FROM_P2[4] origin:064-gtp-channel-conf 01_218 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PD_TRANS_TIME_FROM_P2[5] origin:064-gtp-channel-conf 00_219 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PD_TRANS_TIME_FROM_P2[6] origin:064-gtp-channel-conf 01_219 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PD_TRANS_TIME_FROM_P2[7] origin:064-gtp-channel-conf 00_220 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PD_TRANS_TIME_FROM_P2[8] origin:064-gtp-channel-conf 01_220 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PD_TRANS_TIME_FROM_P2[9] origin:064-gtp-channel-conf 00_221 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PD_TRANS_TIME_FROM_P2[10] origin:064-gtp-channel-conf 01_221 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PD_TRANS_TIME_FROM_P2[11] origin:064-gtp-channel-conf 00_222 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PD_TRANS_TIME_NONE_P2[0] origin:064-gtp-channel-conf 00_208 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PD_TRANS_TIME_NONE_P2[1] origin:064-gtp-channel-conf 01_208 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PD_TRANS_TIME_NONE_P2[2] origin:064-gtp-channel-conf 00_209 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PD_TRANS_TIME_NONE_P2[3] origin:064-gtp-channel-conf 01_209 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PD_TRANS_TIME_NONE_P2[4] origin:064-gtp-channel-conf 00_210 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PD_TRANS_TIME_NONE_P2[5] origin:064-gtp-channel-conf 01_210 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PD_TRANS_TIME_NONE_P2[6] origin:064-gtp-channel-conf 00_211 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PD_TRANS_TIME_NONE_P2[7] origin:064-gtp-channel-conf 01_211 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PD_TRANS_TIME_TO_P2[0] origin:064-gtp-channel-conf 00_212 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PD_TRANS_TIME_TO_P2[1] origin:064-gtp-channel-conf 01_212 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PD_TRANS_TIME_TO_P2[2] origin:064-gtp-channel-conf 00_213 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PD_TRANS_TIME_TO_P2[3] origin:064-gtp-channel-conf 01_213 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PD_TRANS_TIME_TO_P2[4] origin:064-gtp-channel-conf 00_214 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PD_TRANS_TIME_TO_P2[5] origin:064-gtp-channel-conf 01_214 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PD_TRANS_TIME_TO_P2[6] origin:064-gtp-channel-conf 00_215 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PD_TRANS_TIME_TO_P2[7] origin:064-gtp-channel-conf 01_215 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PMA_LOOPBACK_CFG[0] origin:064-gtp-channel-conf 01_207 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PMA_RSV[0] origin:064-gtp-channel-conf 02_520 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PMA_RSV[1] origin:064-gtp-channel-conf 03_520 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PMA_RSV[2] origin:064-gtp-channel-conf 02_521 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PMA_RSV[3] origin:064-gtp-channel-conf 03_521 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PMA_RSV[4] origin:064-gtp-channel-conf 02_522 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PMA_RSV[5] origin:064-gtp-channel-conf 03_522 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PMA_RSV[6] origin:064-gtp-channel-conf 02_523 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PMA_RSV[7] origin:064-gtp-channel-conf 03_523 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PMA_RSV[8] origin:064-gtp-channel-conf 02_524 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PMA_RSV[9] origin:064-gtp-channel-conf 03_524 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PMA_RSV[10] origin:064-gtp-channel-conf 02_525 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PMA_RSV[11] origin:064-gtp-channel-conf 03_525 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PMA_RSV[12] origin:064-gtp-channel-conf 02_526 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PMA_RSV[13] origin:064-gtp-channel-conf 03_526 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PMA_RSV[14] origin:064-gtp-channel-conf 02_527 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PMA_RSV[15] origin:064-gtp-channel-conf 03_527 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PMA_RSV[16] origin:064-gtp-channel-conf 02_528 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PMA_RSV[17] origin:064-gtp-channel-conf 03_528 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PMA_RSV[18] origin:064-gtp-channel-conf 02_529 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PMA_RSV[19] origin:064-gtp-channel-conf 03_529 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PMA_RSV[20] origin:064-gtp-channel-conf 02_530 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PMA_RSV[21] origin:064-gtp-channel-conf 03_530 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PMA_RSV[22] origin:064-gtp-channel-conf 02_531 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PMA_RSV[23] origin:064-gtp-channel-conf 03_531 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PMA_RSV[24] origin:064-gtp-channel-conf 02_532 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PMA_RSV[25] origin:064-gtp-channel-conf 03_532 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PMA_RSV[26] origin:064-gtp-channel-conf 02_533 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PMA_RSV[27] origin:064-gtp-channel-conf 03_533 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PMA_RSV[28] origin:064-gtp-channel-conf 02_534 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PMA_RSV[29] origin:064-gtp-channel-conf 03_534 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PMA_RSV[30] origin:064-gtp-channel-conf 02_535 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PMA_RSV[31] origin:064-gtp-channel-conf 03_535 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PMA_RSV2[0] origin:064-gtp-channel-conf 02_336 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PMA_RSV2[1] origin:064-gtp-channel-conf 03_336 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PMA_RSV2[2] origin:064-gtp-channel-conf 02_337 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PMA_RSV2[3] origin:064-gtp-channel-conf 03_337 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PMA_RSV2[4] origin:064-gtp-channel-conf 02_338 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PMA_RSV2[5] origin:064-gtp-channel-conf 03_338 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PMA_RSV2[6] origin:064-gtp-channel-conf 02_339 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PMA_RSV2[7] origin:064-gtp-channel-conf 03_339 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PMA_RSV2[8] origin:064-gtp-channel-conf 02_340 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PMA_RSV2[9] origin:064-gtp-channel-conf 03_340 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PMA_RSV2[10] origin:064-gtp-channel-conf 02_341 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PMA_RSV2[11] origin:064-gtp-channel-conf 03_341 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PMA_RSV2[12] origin:064-gtp-channel-conf 02_342 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PMA_RSV2[13] origin:064-gtp-channel-conf 03_342 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PMA_RSV2[14] origin:064-gtp-channel-conf 02_343 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PMA_RSV2[15] origin:064-gtp-channel-conf 03_343 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PMA_RSV2[16] origin:064-gtp-channel-conf 02_344 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PMA_RSV2[17] origin:064-gtp-channel-conf 03_344 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PMA_RSV2[18] origin:064-gtp-channel-conf 02_345 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PMA_RSV2[19] origin:064-gtp-channel-conf 03_345 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PMA_RSV2[20] origin:064-gtp-channel-conf 02_346 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PMA_RSV2[21] origin:064-gtp-channel-conf 03_346 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PMA_RSV2[22] origin:064-gtp-channel-conf 02_347 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PMA_RSV2[23] origin:064-gtp-channel-conf 03_347 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PMA_RSV2[24] origin:064-gtp-channel-conf 02_348 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PMA_RSV2[25] origin:064-gtp-channel-conf 03_348 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PMA_RSV2[26] origin:064-gtp-channel-conf 02_349 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PMA_RSV2[27] origin:064-gtp-channel-conf 03_349 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PMA_RSV2[28] origin:064-gtp-channel-conf 02_350 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PMA_RSV2[29] origin:064-gtp-channel-conf 03_350 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PMA_RSV2[30] origin:064-gtp-channel-conf 02_351 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PMA_RSV2[31] origin:064-gtp-channel-conf 03_351 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PMA_RSV3[0] origin:064-gtp-channel-conf 02_288 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PMA_RSV3[1] origin:064-gtp-channel-conf 03_288 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PMA_RSV4[0] origin:064-gtp-channel-conf 02_156 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PMA_RSV4[1] origin:064-gtp-channel-conf 03_156 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PMA_RSV4[2] origin:064-gtp-channel-conf 02_157 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PMA_RSV4[3] origin:064-gtp-channel-conf 03_157 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PMA_RSV5[0] origin:064-gtp-channel-conf 03_159 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PMA_RSV6[0] origin:064-gtp-channel-conf 02_303 -GTP_CHANNEL_0_MID_LEFT.GTPE2.PMA_RSV7[0] origin:064-gtp-channel-conf 03_303 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_BIAS_CFG[0] origin:064-gtp-channel-conf 02_112 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_BIAS_CFG[1] origin:064-gtp-channel-conf 03_112 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_BIAS_CFG[2] origin:064-gtp-channel-conf 02_113 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_BIAS_CFG[3] origin:064-gtp-channel-conf 03_113 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_BIAS_CFG[4] origin:064-gtp-channel-conf 02_114 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_BIAS_CFG[5] origin:064-gtp-channel-conf 03_114 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_BIAS_CFG[6] origin:064-gtp-channel-conf 02_115 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_BIAS_CFG[7] origin:064-gtp-channel-conf 03_115 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_BIAS_CFG[8] origin:064-gtp-channel-conf 02_116 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_BIAS_CFG[9] origin:064-gtp-channel-conf 03_116 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_BIAS_CFG[10] origin:064-gtp-channel-conf 02_117 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_BIAS_CFG[11] origin:064-gtp-channel-conf 03_117 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_BIAS_CFG[12] origin:064-gtp-channel-conf 02_118 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_BIAS_CFG[13] origin:064-gtp-channel-conf 03_118 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_BIAS_CFG[14] origin:064-gtp-channel-conf 02_119 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_BIAS_CFG[15] origin:064-gtp-channel-conf 03_119 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_BUFFER_CFG[0] origin:064-gtp-channel-conf 02_536 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_BUFFER_CFG[1] origin:064-gtp-channel-conf 03_536 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_BUFFER_CFG[2] origin:064-gtp-channel-conf 02_537 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_BUFFER_CFG[3] origin:064-gtp-channel-conf 03_537 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_BUFFER_CFG[4] origin:064-gtp-channel-conf 02_538 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_BUFFER_CFG[5] origin:064-gtp-channel-conf 03_538 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_CLKMUX_EN[0] origin:064-gtp-channel-conf 02_128 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_CM_SEL[0] origin:064-gtp-channel-conf 00_138 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_CM_SEL[1] origin:064-gtp-channel-conf 01_138 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_CM_TRIM[0] origin:064-gtp-channel-conf 02_304 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_CM_TRIM[1] origin:064-gtp-channel-conf 03_304 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_CM_TRIM[2] origin:064-gtp-channel-conf 02_305 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_CM_TRIM[3] origin:064-gtp-channel-conf 03_305 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_DATA_WIDTH[0] origin:064-gtp-channel-conf 01_141 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_DATA_WIDTH[1] origin:064-gtp-channel-conf 00_142 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_DATA_WIDTH[2] origin:064-gtp-channel-conf 01_142 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_DDI_SEL[0] origin:064-gtp-channel-conf 00_696 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_DDI_SEL[1] origin:064-gtp-channel-conf 01_696 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_DDI_SEL[2] origin:064-gtp-channel-conf 00_697 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_DDI_SEL[3] origin:064-gtp-channel-conf 01_697 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_DDI_SEL[4] origin:064-gtp-channel-conf 00_698 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_DDI_SEL[5] origin:064-gtp-channel-conf 01_698 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_DEBUG_CFG[0] origin:064-gtp-channel-conf 02_616 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_DEBUG_CFG[1] origin:064-gtp-channel-conf 03_616 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_DEBUG_CFG[2] origin:064-gtp-channel-conf 02_617 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_DEBUG_CFG[3] origin:064-gtp-channel-conf 03_617 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_DEBUG_CFG[4] origin:064-gtp-channel-conf 02_618 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_DEBUG_CFG[5] origin:064-gtp-channel-conf 03_618 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_DEBUG_CFG[6] origin:064-gtp-channel-conf 02_619 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_DEBUG_CFG[7] origin:064-gtp-channel-conf 03_619 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_DEBUG_CFG[8] origin:064-gtp-channel-conf 02_620 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_DEBUG_CFG[9] origin:064-gtp-channel-conf 03_620 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_DEBUG_CFG[10] origin:064-gtp-channel-conf 02_621 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_DEBUG_CFG[11] origin:064-gtp-channel-conf 03_621 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_DEBUG_CFG[12] origin:064-gtp-channel-conf 02_622 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_DEBUG_CFG[13] origin:064-gtp-channel-conf 03_622 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_DEFER_RESET_BUF_EN origin:064-gtp-channel-conf 02_552 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_DISPERR_SEQ_MATCH origin:064-gtp-channel-conf 01_495 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_OS_CFG[0] origin:064-gtp-channel-conf 00_288 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_OS_CFG[1] origin:064-gtp-channel-conf 01_288 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_OS_CFG[2] origin:064-gtp-channel-conf 00_289 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_OS_CFG[3] origin:064-gtp-channel-conf 01_289 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_OS_CFG[4] origin:064-gtp-channel-conf 00_290 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_OS_CFG[5] origin:064-gtp-channel-conf 01_290 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_OS_CFG[6] origin:064-gtp-channel-conf 00_291 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_OS_CFG[7] origin:064-gtp-channel-conf 01_291 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_OS_CFG[8] origin:064-gtp-channel-conf 00_292 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_OS_CFG[9] origin:064-gtp-channel-conf 01_292 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_OS_CFG[10] origin:064-gtp-channel-conf 00_293 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_OS_CFG[11] origin:064-gtp-channel-conf 01_293 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_OS_CFG[12] origin:064-gtp-channel-conf 00_294 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_SIG_VALID_DLY[0] origin:064-gtp-channel-conf 00_524 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_SIG_VALID_DLY[1] origin:064-gtp-channel-conf 01_524 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_SIG_VALID_DLY[2] origin:064-gtp-channel-conf 00_525 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_SIG_VALID_DLY[3] origin:064-gtp-channel-conf 01_525 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_SIG_VALID_DLY[4] origin:064-gtp-channel-conf 00_526 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_XCLK_SEL.RXUSR origin:064-gtp-channel-conf 00_143 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_CLK25_DIV[0] origin:064-gtp-channel-conf 00_139 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_CLK25_DIV[1] origin:064-gtp-channel-conf 01_139 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_CLK25_DIV[2] origin:064-gtp-channel-conf 00_140 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_CLK25_DIV[3] origin:064-gtp-channel-conf 01_140 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RX_CLK25_DIV[4] origin:064-gtp-channel-conf 00_141 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXBUF_ADDR_MODE.FAST origin:064-gtp-channel-conf 03_555 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXBUF_EIDLE_HI_CNT[0] origin:064-gtp-channel-conf 02_558 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXBUF_EIDLE_HI_CNT[1] origin:064-gtp-channel-conf 03_558 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXBUF_EIDLE_HI_CNT[2] origin:064-gtp-channel-conf 02_559 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXBUF_EIDLE_HI_CNT[3] origin:064-gtp-channel-conf 03_559 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXBUF_EIDLE_LO_CNT[0] origin:064-gtp-channel-conf 02_556 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXBUF_EIDLE_LO_CNT[1] origin:064-gtp-channel-conf 03_556 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXBUF_EIDLE_LO_CNT[2] origin:064-gtp-channel-conf 02_557 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXBUF_EIDLE_LO_CNT[3] origin:064-gtp-channel-conf 03_557 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXBUF_EN origin:064-gtp-channel-conf 02_11 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXBUF_RESET_ON_CB_CHANGE origin:064-gtp-channel-conf 02_560 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXBUF_RESET_ON_COMMAALIGN origin:064-gtp-channel-conf 02_561 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXBUF_RESET_ON_EIDLE origin:064-gtp-channel-conf 02_547 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXBUF_RESET_ON_RATE_CHANGE origin:064-gtp-channel-conf 03_560 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXBUF_THRESH_OVFLW[0] origin:064-gtp-channel-conf 03_552 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXBUF_THRESH_OVFLW[1] origin:064-gtp-channel-conf 02_553 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXBUF_THRESH_OVFLW[2] origin:064-gtp-channel-conf 03_553 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXBUF_THRESH_OVFLW[3] origin:064-gtp-channel-conf 02_554 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXBUF_THRESH_OVFLW[4] origin:064-gtp-channel-conf 03_554 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXBUF_THRESH_OVFLW[5] origin:064-gtp-channel-conf 02_555 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXBUF_THRESH_OVRD origin:064-gtp-channel-conf 02_548 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXBUF_THRESH_UNDFLW[0] origin:064-gtp-channel-conf 02_544 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXBUF_THRESH_UNDFLW[1] origin:064-gtp-channel-conf 03_544 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXBUF_THRESH_UNDFLW[2] origin:064-gtp-channel-conf 02_545 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXBUF_THRESH_UNDFLW[3] origin:064-gtp-channel-conf 03_545 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXBUF_THRESH_UNDFLW[4] origin:064-gtp-channel-conf 02_546 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXBUF_THRESH_UNDFLW[5] origin:064-gtp-channel-conf 03_546 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXBUFRESET_TIME[0] origin:064-gtp-channel-conf 01_101 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXBUFRESET_TIME[1] origin:064-gtp-channel-conf 00_102 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXBUFRESET_TIME[2] origin:064-gtp-channel-conf 01_102 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXBUFRESET_TIME[3] origin:064-gtp-channel-conf 00_103 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXBUFRESET_TIME[4] origin:064-gtp-channel-conf 01_103 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[0] origin:064-gtp-channel-conf 02_640 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[1] origin:064-gtp-channel-conf 03_640 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[2] origin:064-gtp-channel-conf 02_641 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[3] origin:064-gtp-channel-conf 03_641 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[4] origin:064-gtp-channel-conf 02_642 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[5] origin:064-gtp-channel-conf 03_642 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[6] origin:064-gtp-channel-conf 02_643 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[7] origin:064-gtp-channel-conf 03_643 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[8] origin:064-gtp-channel-conf 02_644 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[9] origin:064-gtp-channel-conf 03_644 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[10] origin:064-gtp-channel-conf 02_645 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[11] origin:064-gtp-channel-conf 03_645 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[12] origin:064-gtp-channel-conf 02_646 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[13] origin:064-gtp-channel-conf 03_646 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[14] origin:064-gtp-channel-conf 02_647 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[15] origin:064-gtp-channel-conf 03_647 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[16] origin:064-gtp-channel-conf 02_648 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[17] origin:064-gtp-channel-conf 03_648 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[18] origin:064-gtp-channel-conf 02_649 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[19] origin:064-gtp-channel-conf 03_649 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[20] origin:064-gtp-channel-conf 02_650 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[21] origin:064-gtp-channel-conf 03_650 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[22] origin:064-gtp-channel-conf 02_651 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[23] origin:064-gtp-channel-conf 03_651 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[24] origin:064-gtp-channel-conf 02_652 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[25] origin:064-gtp-channel-conf 03_652 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[26] origin:064-gtp-channel-conf 02_653 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[27] origin:064-gtp-channel-conf 03_653 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[28] origin:064-gtp-channel-conf 02_654 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[29] origin:064-gtp-channel-conf 03_654 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[30] origin:064-gtp-channel-conf 02_655 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[31] origin:064-gtp-channel-conf 03_655 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[32] origin:064-gtp-channel-conf 02_656 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[33] origin:064-gtp-channel-conf 03_656 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[34] origin:064-gtp-channel-conf 02_657 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[35] origin:064-gtp-channel-conf 03_657 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[36] origin:064-gtp-channel-conf 02_658 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[37] origin:064-gtp-channel-conf 03_658 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[38] origin:064-gtp-channel-conf 02_659 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[39] origin:064-gtp-channel-conf 03_659 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[40] origin:064-gtp-channel-conf 02_660 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[41] origin:064-gtp-channel-conf 03_660 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[42] origin:064-gtp-channel-conf 02_661 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[43] origin:064-gtp-channel-conf 03_661 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[44] origin:064-gtp-channel-conf 02_662 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[45] origin:064-gtp-channel-conf 03_662 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[46] origin:064-gtp-channel-conf 02_663 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[47] origin:064-gtp-channel-conf 03_663 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[48] origin:064-gtp-channel-conf 02_664 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[49] origin:064-gtp-channel-conf 03_664 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[50] origin:064-gtp-channel-conf 02_665 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[51] origin:064-gtp-channel-conf 03_665 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[52] origin:064-gtp-channel-conf 02_666 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[53] origin:064-gtp-channel-conf 03_666 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[54] origin:064-gtp-channel-conf 02_667 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[55] origin:064-gtp-channel-conf 03_667 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[56] origin:064-gtp-channel-conf 02_668 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[57] origin:064-gtp-channel-conf 03_668 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[58] origin:064-gtp-channel-conf 02_669 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[59] origin:064-gtp-channel-conf 03_669 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[60] origin:064-gtp-channel-conf 02_670 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[61] origin:064-gtp-channel-conf 03_670 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[62] origin:064-gtp-channel-conf 02_671 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[63] origin:064-gtp-channel-conf 03_671 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[64] origin:064-gtp-channel-conf 02_672 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[65] origin:064-gtp-channel-conf 03_672 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[66] origin:064-gtp-channel-conf 02_673 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[67] origin:064-gtp-channel-conf 03_673 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[68] origin:064-gtp-channel-conf 02_674 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[69] origin:064-gtp-channel-conf 03_674 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[70] origin:064-gtp-channel-conf 02_675 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[71] origin:064-gtp-channel-conf 03_675 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[72] origin:064-gtp-channel-conf 02_676 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[73] origin:064-gtp-channel-conf 03_676 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[74] origin:064-gtp-channel-conf 02_677 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[75] origin:064-gtp-channel-conf 03_677 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[76] origin:064-gtp-channel-conf 02_678 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[77] origin:064-gtp-channel-conf 03_678 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[78] origin:064-gtp-channel-conf 02_679 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[79] origin:064-gtp-channel-conf 03_679 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[80] origin:064-gtp-channel-conf 02_680 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[81] origin:064-gtp-channel-conf 03_680 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_CFG[82] origin:064-gtp-channel-conf 02_681 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_FR_RESET_ON_EIDLE[0] origin:064-gtp-channel-conf 02_638 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_HOLD_DURING_EIDLE[0] origin:064-gtp-channel-conf 03_637 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_LOCK_CFG[0] origin:064-gtp-channel-conf 02_632 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_LOCK_CFG[1] origin:064-gtp-channel-conf 03_632 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_LOCK_CFG[2] origin:064-gtp-channel-conf 02_633 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_LOCK_CFG[3] origin:064-gtp-channel-conf 03_633 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_LOCK_CFG[4] origin:064-gtp-channel-conf 02_634 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_LOCK_CFG[5] origin:064-gtp-channel-conf 03_634 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDR_PH_RESET_ON_EIDLE[0] origin:064-gtp-channel-conf 03_638 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDRFREQRESET_TIME[0] origin:064-gtp-channel-conf 01_106 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDRFREQRESET_TIME[1] origin:064-gtp-channel-conf 00_107 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDRFREQRESET_TIME[2] origin:064-gtp-channel-conf 01_107 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDRFREQRESET_TIME[3] origin:064-gtp-channel-conf 00_108 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDRFREQRESET_TIME[4] origin:064-gtp-channel-conf 01_108 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDRPHRESET_TIME[0] origin:064-gtp-channel-conf 00_109 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDRPHRESET_TIME[1] origin:064-gtp-channel-conf 01_109 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDRPHRESET_TIME[2] origin:064-gtp-channel-conf 00_110 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDRPHRESET_TIME[3] origin:064-gtp-channel-conf 01_110 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXCDRPHRESET_TIME[4] origin:064-gtp-channel-conf 00_111 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXDLY_CFG[0] origin:064-gtp-channel-conf 00_680 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXDLY_CFG[1] origin:064-gtp-channel-conf 01_680 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXDLY_CFG[2] origin:064-gtp-channel-conf 00_681 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXDLY_CFG[3] origin:064-gtp-channel-conf 01_681 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXDLY_CFG[4] origin:064-gtp-channel-conf 00_682 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXDLY_CFG[5] origin:064-gtp-channel-conf 01_682 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXDLY_CFG[6] origin:064-gtp-channel-conf 00_683 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXDLY_CFG[7] origin:064-gtp-channel-conf 01_683 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXDLY_CFG[8] origin:064-gtp-channel-conf 00_684 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXDLY_CFG[9] origin:064-gtp-channel-conf 01_684 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXDLY_CFG[10] origin:064-gtp-channel-conf 00_685 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXDLY_CFG[11] origin:064-gtp-channel-conf 01_685 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXDLY_CFG[12] origin:064-gtp-channel-conf 00_686 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXDLY_CFG[13] origin:064-gtp-channel-conf 01_686 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXDLY_CFG[14] origin:064-gtp-channel-conf 00_687 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXDLY_CFG[15] origin:064-gtp-channel-conf 01_687 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXDLY_LCFG[0] origin:064-gtp-channel-conf 02_576 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXDLY_LCFG[1] origin:064-gtp-channel-conf 03_576 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXDLY_LCFG[2] origin:064-gtp-channel-conf 02_577 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXDLY_LCFG[3] origin:064-gtp-channel-conf 03_577 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXDLY_LCFG[4] origin:064-gtp-channel-conf 02_578 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXDLY_LCFG[5] origin:064-gtp-channel-conf 03_578 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXDLY_LCFG[6] origin:064-gtp-channel-conf 02_579 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXDLY_LCFG[7] origin:064-gtp-channel-conf 03_579 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXDLY_LCFG[8] origin:064-gtp-channel-conf 02_580 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXDLY_TAP_CFG[0] origin:064-gtp-channel-conf 00_672 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXDLY_TAP_CFG[1] origin:064-gtp-channel-conf 01_672 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXDLY_TAP_CFG[2] origin:064-gtp-channel-conf 00_673 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXDLY_TAP_CFG[3] origin:064-gtp-channel-conf 01_673 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXDLY_TAP_CFG[4] origin:064-gtp-channel-conf 00_674 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXDLY_TAP_CFG[5] origin:064-gtp-channel-conf 01_674 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXDLY_TAP_CFG[6] origin:064-gtp-channel-conf 00_675 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXDLY_TAP_CFG[7] origin:064-gtp-channel-conf 01_675 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXDLY_TAP_CFG[8] origin:064-gtp-channel-conf 00_676 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXDLY_TAP_CFG[9] origin:064-gtp-channel-conf 01_676 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXDLY_TAP_CFG[10] origin:064-gtp-channel-conf 00_677 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXDLY_TAP_CFG[11] origin:064-gtp-channel-conf 01_677 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXDLY_TAP_CFG[12] origin:064-gtp-channel-conf 00_678 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXDLY_TAP_CFG[13] origin:064-gtp-channel-conf 01_678 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXDLY_TAP_CFG[14] origin:064-gtp-channel-conf 00_679 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXDLY_TAP_CFG[15] origin:064-gtp-channel-conf 01_679 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXGEARBOX_EN origin:064-gtp-channel-conf 01_607 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXISCANRESET_TIME[0] origin:064-gtp-channel-conf 01_123 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXISCANRESET_TIME[1] origin:064-gtp-channel-conf 00_124 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXISCANRESET_TIME[2] origin:064-gtp-channel-conf 01_124 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXISCANRESET_TIME[3] origin:064-gtp-channel-conf 00_125 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXISCANRESET_TIME[4] origin:064-gtp-channel-conf 01_125 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPM_BIAS_STARTUP_DISABLE[0] origin:064-gtp-channel-conf 03_391 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPM_CFG[0] origin:064-gtp-channel-conf 02_328 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPM_CFG[1] origin:064-gtp-channel-conf 03_328 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPM_CFG[2] origin:064-gtp-channel-conf 02_329 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPM_CFG[3] origin:064-gtp-channel-conf 03_329 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPM_CM_CFG[0] origin:064-gtp-channel-conf 02_430 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPM_GC_CFG[0] origin:064-gtp-channel-conf 02_432 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPM_GC_CFG[1] origin:064-gtp-channel-conf 03_432 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPM_GC_CFG[2] origin:064-gtp-channel-conf 02_433 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPM_GC_CFG[3] origin:064-gtp-channel-conf 03_433 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPM_GC_CFG[4] origin:064-gtp-channel-conf 02_434 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPM_GC_CFG[5] origin:064-gtp-channel-conf 03_434 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPM_GC_CFG[6] origin:064-gtp-channel-conf 02_435 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPM_GC_CFG[7] origin:064-gtp-channel-conf 03_435 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPM_GC_CFG[8] origin:064-gtp-channel-conf 02_436 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPM_GC_CFG2[0] origin:064-gtp-channel-conf 03_442 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPM_GC_CFG2[1] origin:064-gtp-channel-conf 02_443 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPM_GC_CFG2[2] origin:064-gtp-channel-conf 03_443 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPM_HF_CFG[0] origin:064-gtp-channel-conf 00_336 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPM_HF_CFG[1] origin:064-gtp-channel-conf 01_336 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPM_HF_CFG[2] origin:064-gtp-channel-conf 00_337 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPM_HF_CFG[3] origin:064-gtp-channel-conf 01_337 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPM_HF_CFG[4] origin:064-gtp-channel-conf 00_338 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPM_HF_CFG[5] origin:064-gtp-channel-conf 01_338 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPM_HF_CFG[6] origin:064-gtp-channel-conf 00_339 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPM_HF_CFG[7] origin:064-gtp-channel-conf 01_339 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPM_HF_CFG[8] origin:064-gtp-channel-conf 00_340 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPM_HF_CFG[9] origin:064-gtp-channel-conf 01_340 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPM_HF_CFG[10] origin:064-gtp-channel-conf 00_341 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPM_HF_CFG[11] origin:064-gtp-channel-conf 01_341 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPM_HF_CFG[12] origin:064-gtp-channel-conf 00_342 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPM_HF_CFG[13] origin:064-gtp-channel-conf 01_342 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPM_HF_CFG2[0] origin:064-gtp-channel-conf 02_424 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPM_HF_CFG2[1] origin:064-gtp-channel-conf 03_424 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPM_HF_CFG2[2] origin:064-gtp-channel-conf 02_425 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPM_HF_CFG2[3] origin:064-gtp-channel-conf 03_425 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPM_HF_CFG2[4] origin:064-gtp-channel-conf 02_426 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPM_HF_CFG3[0] origin:064-gtp-channel-conf 03_389 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPM_HF_CFG3[1] origin:064-gtp-channel-conf 02_390 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPM_HF_CFG3[2] origin:064-gtp-channel-conf 03_390 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPM_HF_CFG3[3] origin:064-gtp-channel-conf 02_391 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPM_HOLD_DURING_EIDLE[0] origin:064-gtp-channel-conf 00_247 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPM_INCM_CFG[0] origin:064-gtp-channel-conf 02_439 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPM_IPCM_CFG[0] origin:064-gtp-channel-conf 03_439 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPM_LF_CFG[0] origin:064-gtp-channel-conf 00_344 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPM_LF_CFG[1] origin:064-gtp-channel-conf 01_344 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPM_LF_CFG[2] origin:064-gtp-channel-conf 00_345 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPM_LF_CFG[3] origin:064-gtp-channel-conf 01_345 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPM_LF_CFG[4] origin:064-gtp-channel-conf 00_346 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPM_LF_CFG[5] origin:064-gtp-channel-conf 01_346 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPM_LF_CFG[6] origin:064-gtp-channel-conf 00_347 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPM_LF_CFG[7] origin:064-gtp-channel-conf 01_347 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPM_LF_CFG[8] origin:064-gtp-channel-conf 00_348 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPM_LF_CFG[9] origin:064-gtp-channel-conf 01_348 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPM_LF_CFG[10] origin:064-gtp-channel-conf 00_349 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPM_LF_CFG[11] origin:064-gtp-channel-conf 01_349 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPM_LF_CFG[12] origin:064-gtp-channel-conf 00_350 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPM_LF_CFG[13] origin:064-gtp-channel-conf 01_350 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPM_LF_CFG[14] origin:064-gtp-channel-conf 00_351 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPM_LF_CFG[15] origin:064-gtp-channel-conf 01_351 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPM_LF_CFG[16] origin:064-gtp-channel-conf 00_343 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPM_LF_CFG[17] origin:064-gtp-channel-conf 01_343 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPM_LF_CFG2[0] origin:064-gtp-channel-conf 03_426 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPM_LF_CFG2[1] origin:064-gtp-channel-conf 02_427 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPM_LF_CFG2[2] origin:064-gtp-channel-conf 03_427 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPM_LF_CFG2[3] origin:064-gtp-channel-conf 02_428 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPM_LF_CFG2[4] origin:064-gtp-channel-conf 03_428 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPM_OSINT_CFG[0] origin:064-gtp-channel-conf 02_440 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPM_OSINT_CFG[1] origin:064-gtp-channel-conf 03_440 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPM_OSINT_CFG[2] origin:064-gtp-channel-conf 02_441 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPM_CFG1[0] origin:064-gtp-channel-conf 02_330 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPMRESET_TIME[0] origin:064-gtp-channel-conf 00_112 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPMRESET_TIME[1] origin:064-gtp-channel-conf 01_112 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPMRESET_TIME[2] origin:064-gtp-channel-conf 00_113 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPMRESET_TIME[3] origin:064-gtp-channel-conf 01_113 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPMRESET_TIME[4] origin:064-gtp-channel-conf 00_114 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPMRESET_TIME[5] origin:064-gtp-channel-conf 01_114 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXLPMRESET_TIME[6] origin:064-gtp-channel-conf 00_115 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXOOB_CFG[0] origin:064-gtp-channel-conf 00_144 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXOOB_CFG[1] origin:064-gtp-channel-conf 01_144 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXOOB_CFG[2] origin:064-gtp-channel-conf 00_145 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXOOB_CFG[3] origin:064-gtp-channel-conf 01_145 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXOOB_CFG[4] origin:064-gtp-channel-conf 00_146 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXOOB_CFG[5] origin:064-gtp-channel-conf 01_146 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXOOB_CFG[6] origin:064-gtp-channel-conf 00_147 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXOOB_CLK_CFG.FABRIC origin:064-gtp-channel-conf 03_129 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXOSCALRESET_TIME[0] origin:064-gtp-channel-conf 00_187 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXOSCALRESET_TIME[1] origin:064-gtp-channel-conf 01_187 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXOSCALRESET_TIME[2] origin:064-gtp-channel-conf 00_188 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXOSCALRESET_TIME[3] origin:064-gtp-channel-conf 01_188 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXOSCALRESET_TIME[4] origin:064-gtp-channel-conf 00_189 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXOSCALRESET_TIMEOUT[0] origin:064-gtp-channel-conf 01_189 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXOSCALRESET_TIMEOUT[1] origin:064-gtp-channel-conf 00_190 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXOSCALRESET_TIMEOUT[2] origin:064-gtp-channel-conf 01_190 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXOSCALRESET_TIMEOUT[3] origin:064-gtp-channel-conf 00_191 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXOSCALRESET_TIMEOUT[4] origin:064-gtp-channel-conf 01_191 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXOUT_DIV[0] origin:064-gtp-channel-conf 02_384 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXOUT_DIV[1] origin:064-gtp-channel-conf 03_384 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXPCSRESET_TIME[0] origin:064-gtp-channel-conf 01_115 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXPCSRESET_TIME[1] origin:064-gtp-channel-conf 00_116 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXPCSRESET_TIME[2] origin:064-gtp-channel-conf 01_116 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXPCSRESET_TIME[3] origin:064-gtp-channel-conf 00_117 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXPCSRESET_TIME[4] origin:064-gtp-channel-conf 01_117 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXPH_CFG[0] origin:064-gtp-channel-conf 02_584 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXPH_CFG[1] origin:064-gtp-channel-conf 03_584 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXPH_CFG[2] origin:064-gtp-channel-conf 02_585 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXPH_CFG[3] origin:064-gtp-channel-conf 03_585 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXPH_CFG[4] origin:064-gtp-channel-conf 02_586 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXPH_CFG[5] origin:064-gtp-channel-conf 03_586 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXPH_CFG[6] origin:064-gtp-channel-conf 02_587 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXPH_CFG[7] origin:064-gtp-channel-conf 03_587 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXPH_CFG[8] origin:064-gtp-channel-conf 02_588 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXPH_CFG[9] origin:064-gtp-channel-conf 03_588 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXPH_CFG[10] origin:064-gtp-channel-conf 02_589 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXPH_CFG[11] origin:064-gtp-channel-conf 03_589 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXPH_CFG[12] origin:064-gtp-channel-conf 02_590 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXPH_CFG[13] origin:064-gtp-channel-conf 03_590 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXPH_CFG[14] origin:064-gtp-channel-conf 02_591 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXPH_CFG[15] origin:064-gtp-channel-conf 03_591 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXPH_CFG[16] origin:064-gtp-channel-conf 02_592 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXPH_CFG[17] origin:064-gtp-channel-conf 03_592 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXPH_CFG[18] origin:064-gtp-channel-conf 02_593 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXPH_CFG[19] origin:064-gtp-channel-conf 03_593 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXPH_CFG[20] origin:064-gtp-channel-conf 02_594 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXPH_CFG[21] origin:064-gtp-channel-conf 03_594 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXPH_CFG[22] origin:064-gtp-channel-conf 02_595 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXPH_CFG[23] origin:064-gtp-channel-conf 03_595 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXPH_MONITOR_SEL[0] origin:064-gtp-channel-conf 00_700 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXPH_MONITOR_SEL[1] origin:064-gtp-channel-conf 01_700 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXPH_MONITOR_SEL[2] origin:064-gtp-channel-conf 00_701 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXPH_MONITOR_SEL[3] origin:064-gtp-channel-conf 01_701 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXPH_MONITOR_SEL[4] origin:064-gtp-channel-conf 00_702 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXPHDLY_CFG[0] origin:064-gtp-channel-conf 02_600 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXPHDLY_CFG[1] origin:064-gtp-channel-conf 03_600 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXPHDLY_CFG[2] origin:064-gtp-channel-conf 02_601 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXPHDLY_CFG[3] origin:064-gtp-channel-conf 03_601 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXPHDLY_CFG[4] origin:064-gtp-channel-conf 02_602 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXPHDLY_CFG[5] origin:064-gtp-channel-conf 03_602 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXPHDLY_CFG[6] origin:064-gtp-channel-conf 02_603 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXPHDLY_CFG[7] origin:064-gtp-channel-conf 03_603 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXPHDLY_CFG[8] origin:064-gtp-channel-conf 02_604 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXPHDLY_CFG[9] origin:064-gtp-channel-conf 03_604 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXPHDLY_CFG[10] origin:064-gtp-channel-conf 02_605 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXPHDLY_CFG[11] origin:064-gtp-channel-conf 03_605 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXPHDLY_CFG[12] origin:064-gtp-channel-conf 02_606 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXPHDLY_CFG[13] origin:064-gtp-channel-conf 03_606 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXPHDLY_CFG[14] origin:064-gtp-channel-conf 02_607 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXPHDLY_CFG[15] origin:064-gtp-channel-conf 03_607 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXPHDLY_CFG[16] origin:064-gtp-channel-conf 02_608 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXPHDLY_CFG[17] origin:064-gtp-channel-conf 03_608 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXPHDLY_CFG[18] origin:064-gtp-channel-conf 02_609 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXPHDLY_CFG[19] origin:064-gtp-channel-conf 03_609 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXPHDLY_CFG[20] origin:064-gtp-channel-conf 02_610 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXPHDLY_CFG[21] origin:064-gtp-channel-conf 03_610 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXPHDLY_CFG[22] origin:064-gtp-channel-conf 02_611 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXPHDLY_CFG[23] origin:064-gtp-channel-conf 03_611 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXPI_CFG0[0] origin:064-gtp-channel-conf 03_430 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXPI_CFG0[1] origin:064-gtp-channel-conf 02_431 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXPI_CFG0[2] origin:064-gtp-channel-conf 03_431 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXPI_CFG1[0] origin:064-gtp-channel-conf 02_442 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXPI_CFG2[0] origin:064-gtp-channel-conf 03_441 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXPMARESET_TIME[0] origin:064-gtp-channel-conf 00_104 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXPMARESET_TIME[1] origin:064-gtp-channel-conf 01_104 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXPMARESET_TIME[2] origin:064-gtp-channel-conf 00_105 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXPMARESET_TIME[3] origin:064-gtp-channel-conf 01_105 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXPMARESET_TIME[4] origin:064-gtp-channel-conf 00_106 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXPRBS_ERR_LOOPBACK[0] origin:064-gtp-channel-conf 00_136 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXSLIDE_AUTO_WAIT[0] origin:064-gtp-channel-conf 00_520 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXSLIDE_AUTO_WAIT[1] origin:064-gtp-channel-conf 01_520 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXSLIDE_AUTO_WAIT[2] origin:064-gtp-channel-conf 00_521 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXSLIDE_AUTO_WAIT[3] origin:064-gtp-channel-conf 01_521 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXSLIDE_MODE.AUTO origin:064-gtp-channel-conf !01_519 00_519 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXSLIDE_MODE.PCS origin:064-gtp-channel-conf !00_519 01_519 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXSLIDE_MODE.PMA origin:064-gtp-channel-conf 00_519 01_519 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXSYNC_MULTILANE[0] origin:064-gtp-channel-conf 00_133 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXSYNC_OVRD[0] origin:064-gtp-channel-conf 01_135 -GTP_CHANNEL_0_MID_LEFT.GTPE2.RXSYNC_SKIP_DA[0] origin:064-gtp-channel-conf 01_134 -GTP_CHANNEL_0_MID_LEFT.GTPE2.SAS_MAX_COM[0] origin:064-gtp-channel-conf 00_171 -GTP_CHANNEL_0_MID_LEFT.GTPE2.SAS_MAX_COM[1] origin:064-gtp-channel-conf 01_171 -GTP_CHANNEL_0_MID_LEFT.GTPE2.SAS_MAX_COM[2] origin:064-gtp-channel-conf 00_172 -GTP_CHANNEL_0_MID_LEFT.GTPE2.SAS_MAX_COM[3] origin:064-gtp-channel-conf 01_172 -GTP_CHANNEL_0_MID_LEFT.GTPE2.SAS_MAX_COM[4] origin:064-gtp-channel-conf 00_173 -GTP_CHANNEL_0_MID_LEFT.GTPE2.SAS_MAX_COM[5] origin:064-gtp-channel-conf 01_173 -GTP_CHANNEL_0_MID_LEFT.GTPE2.SAS_MAX_COM[6] origin:064-gtp-channel-conf 00_174 -GTP_CHANNEL_0_MID_LEFT.GTPE2.SAS_MIN_COM[0] origin:064-gtp-channel-conf 01_156 -GTP_CHANNEL_0_MID_LEFT.GTPE2.SAS_MIN_COM[1] origin:064-gtp-channel-conf 00_157 -GTP_CHANNEL_0_MID_LEFT.GTPE2.SAS_MIN_COM[2] origin:064-gtp-channel-conf 01_157 -GTP_CHANNEL_0_MID_LEFT.GTPE2.SAS_MIN_COM[3] origin:064-gtp-channel-conf 00_158 -GTP_CHANNEL_0_MID_LEFT.GTPE2.SAS_MIN_COM[4] origin:064-gtp-channel-conf 01_158 -GTP_CHANNEL_0_MID_LEFT.GTPE2.SAS_MIN_COM[5] origin:064-gtp-channel-conf 00_159 -GTP_CHANNEL_0_MID_LEFT.GTPE2.SATA_BURST_SEQ_LEN[0] origin:064-gtp-channel-conf 00_150 -GTP_CHANNEL_0_MID_LEFT.GTPE2.SATA_BURST_SEQ_LEN[1] origin:064-gtp-channel-conf 01_150 -GTP_CHANNEL_0_MID_LEFT.GTPE2.SATA_BURST_SEQ_LEN[2] origin:064-gtp-channel-conf 00_151 -GTP_CHANNEL_0_MID_LEFT.GTPE2.SATA_BURST_SEQ_LEN[3] origin:064-gtp-channel-conf 01_151 -GTP_CHANNEL_0_MID_LEFT.GTPE2.SATA_BURST_VAL[0] origin:064-gtp-channel-conf 01_147 -GTP_CHANNEL_0_MID_LEFT.GTPE2.SATA_BURST_VAL[1] origin:064-gtp-channel-conf 00_148 -GTP_CHANNEL_0_MID_LEFT.GTPE2.SATA_BURST_VAL[2] origin:064-gtp-channel-conf 01_148 -GTP_CHANNEL_0_MID_LEFT.GTPE2.SATA_EIDLE_VAL[0] origin:064-gtp-channel-conf 00_152 -GTP_CHANNEL_0_MID_LEFT.GTPE2.SATA_EIDLE_VAL[1] origin:064-gtp-channel-conf 01_152 -GTP_CHANNEL_0_MID_LEFT.GTPE2.SATA_EIDLE_VAL[2] origin:064-gtp-channel-conf 00_153 -GTP_CHANNEL_0_MID_LEFT.GTPE2.SATA_MAX_BURST[0] origin:064-gtp-channel-conf 00_168 -GTP_CHANNEL_0_MID_LEFT.GTPE2.SATA_MAX_BURST[1] origin:064-gtp-channel-conf 01_168 -GTP_CHANNEL_0_MID_LEFT.GTPE2.SATA_MAX_BURST[2] origin:064-gtp-channel-conf 00_169 -GTP_CHANNEL_0_MID_LEFT.GTPE2.SATA_MAX_BURST[3] origin:064-gtp-channel-conf 01_169 -GTP_CHANNEL_0_MID_LEFT.GTPE2.SATA_MAX_BURST[4] origin:064-gtp-channel-conf 00_170 -GTP_CHANNEL_0_MID_LEFT.GTPE2.SATA_MAX_BURST[5] origin:064-gtp-channel-conf 01_170 -GTP_CHANNEL_0_MID_LEFT.GTPE2.SATA_MAX_INIT[0] origin:064-gtp-channel-conf 00_176 -GTP_CHANNEL_0_MID_LEFT.GTPE2.SATA_MAX_INIT[1] origin:064-gtp-channel-conf 01_176 -GTP_CHANNEL_0_MID_LEFT.GTPE2.SATA_MAX_INIT[2] origin:064-gtp-channel-conf 00_177 -GTP_CHANNEL_0_MID_LEFT.GTPE2.SATA_MAX_INIT[3] origin:064-gtp-channel-conf 01_177 -GTP_CHANNEL_0_MID_LEFT.GTPE2.SATA_MAX_INIT[4] origin:064-gtp-channel-conf 00_178 -GTP_CHANNEL_0_MID_LEFT.GTPE2.SATA_MAX_INIT[5] origin:064-gtp-channel-conf 01_178 -GTP_CHANNEL_0_MID_LEFT.GTPE2.SATA_MAX_WAKE[0] origin:064-gtp-channel-conf 00_179 -GTP_CHANNEL_0_MID_LEFT.GTPE2.SATA_MAX_WAKE[1] origin:064-gtp-channel-conf 01_179 -GTP_CHANNEL_0_MID_LEFT.GTPE2.SATA_MAX_WAKE[2] origin:064-gtp-channel-conf 00_180 -GTP_CHANNEL_0_MID_LEFT.GTPE2.SATA_MAX_WAKE[3] origin:064-gtp-channel-conf 01_180 -GTP_CHANNEL_0_MID_LEFT.GTPE2.SATA_MAX_WAKE[4] origin:064-gtp-channel-conf 00_181 -GTP_CHANNEL_0_MID_LEFT.GTPE2.SATA_MAX_WAKE[5] origin:064-gtp-channel-conf 01_181 -GTP_CHANNEL_0_MID_LEFT.GTPE2.SATA_MIN_BURST[0] origin:064-gtp-channel-conf 01_153 -GTP_CHANNEL_0_MID_LEFT.GTPE2.SATA_MIN_BURST[1] origin:064-gtp-channel-conf 00_154 -GTP_CHANNEL_0_MID_LEFT.GTPE2.SATA_MIN_BURST[2] origin:064-gtp-channel-conf 01_154 -GTP_CHANNEL_0_MID_LEFT.GTPE2.SATA_MIN_BURST[3] origin:064-gtp-channel-conf 00_155 -GTP_CHANNEL_0_MID_LEFT.GTPE2.SATA_MIN_BURST[4] origin:064-gtp-channel-conf 01_155 -GTP_CHANNEL_0_MID_LEFT.GTPE2.SATA_MIN_BURST[5] origin:064-gtp-channel-conf 00_156 -GTP_CHANNEL_0_MID_LEFT.GTPE2.SATA_MIN_INIT[0] origin:064-gtp-channel-conf 00_160 -GTP_CHANNEL_0_MID_LEFT.GTPE2.SATA_MIN_INIT[1] origin:064-gtp-channel-conf 01_160 -GTP_CHANNEL_0_MID_LEFT.GTPE2.SATA_MIN_INIT[2] origin:064-gtp-channel-conf 00_161 -GTP_CHANNEL_0_MID_LEFT.GTPE2.SATA_MIN_INIT[3] origin:064-gtp-channel-conf 01_161 -GTP_CHANNEL_0_MID_LEFT.GTPE2.SATA_MIN_INIT[4] origin:064-gtp-channel-conf 00_162 -GTP_CHANNEL_0_MID_LEFT.GTPE2.SATA_MIN_INIT[5] origin:064-gtp-channel-conf 01_162 -GTP_CHANNEL_0_MID_LEFT.GTPE2.SATA_MIN_WAKE[0] origin:064-gtp-channel-conf 00_163 -GTP_CHANNEL_0_MID_LEFT.GTPE2.SATA_MIN_WAKE[1] origin:064-gtp-channel-conf 01_163 -GTP_CHANNEL_0_MID_LEFT.GTPE2.SATA_MIN_WAKE[2] origin:064-gtp-channel-conf 00_164 -GTP_CHANNEL_0_MID_LEFT.GTPE2.SATA_MIN_WAKE[3] origin:064-gtp-channel-conf 01_164 -GTP_CHANNEL_0_MID_LEFT.GTPE2.SATA_MIN_WAKE[4] origin:064-gtp-channel-conf 00_165 -GTP_CHANNEL_0_MID_LEFT.GTPE2.SATA_MIN_WAKE[5] origin:064-gtp-channel-conf 01_165 -GTP_CHANNEL_0_MID_LEFT.GTPE2.SATA_PLL_CFG.VCO_1500MHZ origin:064-gtp-channel-conf 02_55 -GTP_CHANNEL_0_MID_LEFT.GTPE2.SATA_PLL_CFG.VCO_750MHZ origin:064-gtp-channel-conf 03_55 -GTP_CHANNEL_0_MID_LEFT.GTPE2.SHOW_REALIGN_COMMA origin:064-gtp-channel-conf 01_522 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TERM_RCAL_CFG[0] origin:064-gtp-channel-conf 02_136 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TERM_RCAL_CFG[1] origin:064-gtp-channel-conf 03_136 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TERM_RCAL_CFG[2] origin:064-gtp-channel-conf 02_137 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TERM_RCAL_CFG[3] origin:064-gtp-channel-conf 03_137 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TERM_RCAL_CFG[4] origin:064-gtp-channel-conf 02_138 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TERM_RCAL_CFG[5] origin:064-gtp-channel-conf 03_138 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TERM_RCAL_CFG[6] origin:064-gtp-channel-conf 02_139 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TERM_RCAL_CFG[7] origin:064-gtp-channel-conf 03_139 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TERM_RCAL_CFG[8] origin:064-gtp-channel-conf 02_140 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TERM_RCAL_CFG[9] origin:064-gtp-channel-conf 03_140 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TERM_RCAL_CFG[10] origin:064-gtp-channel-conf 02_141 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TERM_RCAL_CFG[11] origin:064-gtp-channel-conf 03_141 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TERM_RCAL_CFG[12] origin:064-gtp-channel-conf 02_142 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TERM_RCAL_CFG[13] origin:064-gtp-channel-conf 03_142 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TERM_RCAL_CFG[14] origin:064-gtp-channel-conf 02_143 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TERM_RCAL_OVRD[0] origin:064-gtp-channel-conf 03_150 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TERM_RCAL_OVRD[1] origin:064-gtp-channel-conf 02_151 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TERM_RCAL_OVRD[2] origin:064-gtp-channel-conf 03_151 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TRANS_TIME_RATE[0] origin:064-gtp-channel-conf 00_192 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TRANS_TIME_RATE[1] origin:064-gtp-channel-conf 01_192 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TRANS_TIME_RATE[2] origin:064-gtp-channel-conf 00_193 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TRANS_TIME_RATE[3] origin:064-gtp-channel-conf 01_193 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TRANS_TIME_RATE[4] origin:064-gtp-channel-conf 00_194 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TRANS_TIME_RATE[5] origin:064-gtp-channel-conf 01_194 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TRANS_TIME_RATE[6] origin:064-gtp-channel-conf 00_195 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TRANS_TIME_RATE[7] origin:064-gtp-channel-conf 01_195 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TST_RSV[0] origin:064-gtp-channel-conf 02_504 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TST_RSV[1] origin:064-gtp-channel-conf 03_504 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TST_RSV[2] origin:064-gtp-channel-conf 02_505 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TST_RSV[3] origin:064-gtp-channel-conf 03_505 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TST_RSV[4] origin:064-gtp-channel-conf 02_506 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TST_RSV[5] origin:064-gtp-channel-conf 03_506 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TST_RSV[6] origin:064-gtp-channel-conf 02_507 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TST_RSV[7] origin:064-gtp-channel-conf 03_507 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TST_RSV[8] origin:064-gtp-channel-conf 02_508 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TST_RSV[9] origin:064-gtp-channel-conf 03_508 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TST_RSV[10] origin:064-gtp-channel-conf 02_509 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TST_RSV[11] origin:064-gtp-channel-conf 03_509 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TST_RSV[12] origin:064-gtp-channel-conf 02_510 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TST_RSV[13] origin:064-gtp-channel-conf 03_510 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TST_RSV[14] origin:064-gtp-channel-conf 02_511 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TST_RSV[15] origin:064-gtp-channel-conf 03_511 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TST_RSV[16] origin:064-gtp-channel-conf 02_512 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TST_RSV[17] origin:064-gtp-channel-conf 03_512 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TST_RSV[18] origin:064-gtp-channel-conf 02_513 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TST_RSV[19] origin:064-gtp-channel-conf 03_513 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TST_RSV[20] origin:064-gtp-channel-conf 02_514 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TST_RSV[21] origin:064-gtp-channel-conf 03_514 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TST_RSV[22] origin:064-gtp-channel-conf 02_515 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TST_RSV[23] origin:064-gtp-channel-conf 03_515 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TST_RSV[24] origin:064-gtp-channel-conf 02_516 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TST_RSV[25] origin:064-gtp-channel-conf 03_516 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TST_RSV[26] origin:064-gtp-channel-conf 02_517 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TST_RSV[27] origin:064-gtp-channel-conf 03_517 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TST_RSV[28] origin:064-gtp-channel-conf 02_518 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TST_RSV[29] origin:064-gtp-channel-conf 03_518 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TST_RSV[30] origin:064-gtp-channel-conf 02_519 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TST_RSV[31] origin:064-gtp-channel-conf 03_519 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_CLKMUX_EN[0] origin:064-gtp-channel-conf 03_128 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_DATA_WIDTH[0] origin:064-gtp-channel-conf 02_152 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_DATA_WIDTH[1] origin:064-gtp-channel-conf 03_152 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_DATA_WIDTH[2] origin:064-gtp-channel-conf 02_153 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_DRIVE_MODE.PIPE origin:064-gtp-channel-conf 00_200 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_EIDLE_ASSERT_DELAY[0] origin:064-gtp-channel-conf 00_203 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_EIDLE_ASSERT_DELAY[1] origin:064-gtp-channel-conf 01_203 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_EIDLE_ASSERT_DELAY[2] origin:064-gtp-channel-conf 00_204 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_EIDLE_DEASSERT_DELAY[0] origin:064-gtp-channel-conf 01_204 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_EIDLE_DEASSERT_DELAY[1] origin:064-gtp-channel-conf 00_205 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_EIDLE_DEASSERT_DELAY[2] origin:064-gtp-channel-conf 01_205 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_LOOPBACK_DRIVE_HIZ origin:064-gtp-channel-conf 01_202 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_MAINCURSOR_SEL[0] origin:064-gtp-channel-conf 03_289 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_MARGIN_FULL_0[0] origin:064-gtp-channel-conf 02_232 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_MARGIN_FULL_0[1] origin:064-gtp-channel-conf 03_232 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_MARGIN_FULL_0[2] origin:064-gtp-channel-conf 02_233 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_MARGIN_FULL_0[3] origin:064-gtp-channel-conf 03_233 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_MARGIN_FULL_0[4] origin:064-gtp-channel-conf 02_234 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_MARGIN_FULL_0[5] origin:064-gtp-channel-conf 03_234 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_MARGIN_FULL_0[6] origin:064-gtp-channel-conf 02_235 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_MARGIN_FULL_1[0] origin:064-gtp-channel-conf 02_236 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_MARGIN_FULL_1[1] origin:064-gtp-channel-conf 03_236 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_MARGIN_FULL_1[2] origin:064-gtp-channel-conf 02_237 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_MARGIN_FULL_1[3] origin:064-gtp-channel-conf 03_237 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_MARGIN_FULL_1[4] origin:064-gtp-channel-conf 02_238 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_MARGIN_FULL_1[5] origin:064-gtp-channel-conf 03_238 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_MARGIN_FULL_1[6] origin:064-gtp-channel-conf 02_239 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_MARGIN_FULL_2[0] origin:064-gtp-channel-conf 02_240 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_MARGIN_FULL_2[1] origin:064-gtp-channel-conf 03_240 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_MARGIN_FULL_2[2] origin:064-gtp-channel-conf 02_241 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_MARGIN_FULL_2[3] origin:064-gtp-channel-conf 03_241 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_MARGIN_FULL_2[4] origin:064-gtp-channel-conf 02_242 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_MARGIN_FULL_2[5] origin:064-gtp-channel-conf 03_242 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_MARGIN_FULL_2[6] origin:064-gtp-channel-conf 02_243 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_MARGIN_FULL_3[0] origin:064-gtp-channel-conf 02_244 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_MARGIN_FULL_3[1] origin:064-gtp-channel-conf 03_244 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_MARGIN_FULL_3[2] origin:064-gtp-channel-conf 02_245 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_MARGIN_FULL_3[3] origin:064-gtp-channel-conf 03_245 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_MARGIN_FULL_3[4] origin:064-gtp-channel-conf 02_246 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_MARGIN_FULL_3[5] origin:064-gtp-channel-conf 03_246 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_MARGIN_FULL_3[6] origin:064-gtp-channel-conf 02_247 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_MARGIN_FULL_4[0] origin:064-gtp-channel-conf 02_248 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_MARGIN_FULL_4[1] origin:064-gtp-channel-conf 03_248 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_MARGIN_FULL_4[2] origin:064-gtp-channel-conf 02_249 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_MARGIN_FULL_4[3] origin:064-gtp-channel-conf 03_249 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_MARGIN_FULL_4[4] origin:064-gtp-channel-conf 02_250 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_MARGIN_FULL_4[5] origin:064-gtp-channel-conf 03_250 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_MARGIN_FULL_4[6] origin:064-gtp-channel-conf 02_251 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_MARGIN_LOW_0[0] origin:064-gtp-channel-conf 02_252 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_MARGIN_LOW_0[1] origin:064-gtp-channel-conf 03_252 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_MARGIN_LOW_0[2] origin:064-gtp-channel-conf 02_253 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_MARGIN_LOW_0[3] origin:064-gtp-channel-conf 03_253 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_MARGIN_LOW_0[4] origin:064-gtp-channel-conf 02_254 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_MARGIN_LOW_0[5] origin:064-gtp-channel-conf 03_254 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_MARGIN_LOW_0[6] origin:064-gtp-channel-conf 02_255 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_MARGIN_LOW_1[0] origin:064-gtp-channel-conf 02_256 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_MARGIN_LOW_1[1] origin:064-gtp-channel-conf 03_256 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_MARGIN_LOW_1[2] origin:064-gtp-channel-conf 02_257 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_MARGIN_LOW_1[3] origin:064-gtp-channel-conf 03_257 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_MARGIN_LOW_1[4] origin:064-gtp-channel-conf 02_258 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_MARGIN_LOW_1[5] origin:064-gtp-channel-conf 03_258 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_MARGIN_LOW_1[6] origin:064-gtp-channel-conf 02_259 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_MARGIN_LOW_2[0] origin:064-gtp-channel-conf 02_260 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_MARGIN_LOW_2[1] origin:064-gtp-channel-conf 03_260 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_MARGIN_LOW_2[2] origin:064-gtp-channel-conf 02_261 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_MARGIN_LOW_2[3] origin:064-gtp-channel-conf 03_261 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_MARGIN_LOW_2[4] origin:064-gtp-channel-conf 02_262 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_MARGIN_LOW_2[5] origin:064-gtp-channel-conf 03_262 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_MARGIN_LOW_2[6] origin:064-gtp-channel-conf 02_263 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_MARGIN_LOW_3[0] origin:064-gtp-channel-conf 02_264 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_MARGIN_LOW_3[1] origin:064-gtp-channel-conf 03_264 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_MARGIN_LOW_3[2] origin:064-gtp-channel-conf 02_265 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_MARGIN_LOW_3[3] origin:064-gtp-channel-conf 03_265 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_MARGIN_LOW_3[4] origin:064-gtp-channel-conf 02_266 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_MARGIN_LOW_3[5] origin:064-gtp-channel-conf 03_266 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_MARGIN_LOW_3[6] origin:064-gtp-channel-conf 02_267 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_MARGIN_LOW_4[0] origin:064-gtp-channel-conf 02_268 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_MARGIN_LOW_4[1] origin:064-gtp-channel-conf 03_268 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_MARGIN_LOW_4[2] origin:064-gtp-channel-conf 02_269 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_MARGIN_LOW_4[3] origin:064-gtp-channel-conf 03_269 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_MARGIN_LOW_4[4] origin:064-gtp-channel-conf 02_270 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_MARGIN_LOW_4[5] origin:064-gtp-channel-conf 03_270 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_MARGIN_LOW_4[6] origin:064-gtp-channel-conf 02_271 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_PREDRIVER_MODE[0] origin:064-gtp-channel-conf 00_206 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_RXDETECT_CFG[0] origin:064-gtp-channel-conf 02_296 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_RXDETECT_CFG[1] origin:064-gtp-channel-conf 03_296 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_RXDETECT_CFG[2] origin:064-gtp-channel-conf 02_297 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_RXDETECT_CFG[3] origin:064-gtp-channel-conf 03_297 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_RXDETECT_CFG[4] origin:064-gtp-channel-conf 02_298 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_RXDETECT_CFG[5] origin:064-gtp-channel-conf 03_298 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_RXDETECT_CFG[6] origin:064-gtp-channel-conf 02_299 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_RXDETECT_CFG[7] origin:064-gtp-channel-conf 03_299 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_RXDETECT_CFG[8] origin:064-gtp-channel-conf 02_300 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_RXDETECT_CFG[9] origin:064-gtp-channel-conf 03_300 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_RXDETECT_CFG[10] origin:064-gtp-channel-conf 02_301 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_RXDETECT_CFG[11] origin:064-gtp-channel-conf 03_301 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_RXDETECT_CFG[12] origin:064-gtp-channel-conf 02_302 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_RXDETECT_CFG[13] origin:064-gtp-channel-conf 03_302 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_RXDETECT_REF[0] origin:064-gtp-channel-conf 02_292 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_RXDETECT_REF[1] origin:064-gtp-channel-conf 03_292 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_RXDETECT_REF[2] origin:064-gtp-channel-conf 02_293 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_XCLK_SEL.TXUSR origin:064-gtp-channel-conf 03_11 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_CLK25_DIV[0] origin:064-gtp-channel-conf 02_144 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_CLK25_DIV[1] origin:064-gtp-channel-conf 03_144 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_CLK25_DIV[2] origin:064-gtp-channel-conf 02_145 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_CLK25_DIV[3] origin:064-gtp-channel-conf 03_145 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_CLK25_DIV[4] origin:064-gtp-channel-conf 02_146 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_DEEMPH0[0] origin:064-gtp-channel-conf 02_272 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_DEEMPH0[1] origin:064-gtp-channel-conf 03_272 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_DEEMPH0[2] origin:064-gtp-channel-conf 02_273 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_DEEMPH0[3] origin:064-gtp-channel-conf 03_273 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_DEEMPH0[4] origin:064-gtp-channel-conf 02_274 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_DEEMPH0[5] origin:064-gtp-channel-conf 03_274 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_DEEMPH1[0] origin:064-gtp-channel-conf 02_276 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_DEEMPH1[1] origin:064-gtp-channel-conf 03_276 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_DEEMPH1[2] origin:064-gtp-channel-conf 02_277 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_DEEMPH1[3] origin:064-gtp-channel-conf 03_277 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_DEEMPH1[4] origin:064-gtp-channel-conf 02_278 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TX_DEEMPH1[5] origin:064-gtp-channel-conf 03_278 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXBUF_EN origin:064-gtp-channel-conf 00_231 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXBUF_RESET_ON_RATE_CHANGE origin:064-gtp-channel-conf 01_231 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXDLY_CFG[0] origin:064-gtp-channel-conf 02_80 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXDLY_CFG[1] origin:064-gtp-channel-conf 03_80 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXDLY_CFG[2] origin:064-gtp-channel-conf 02_81 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXDLY_CFG[3] origin:064-gtp-channel-conf 03_81 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXDLY_CFG[4] origin:064-gtp-channel-conf 02_82 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXDLY_CFG[5] origin:064-gtp-channel-conf 03_82 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXDLY_CFG[6] origin:064-gtp-channel-conf 02_83 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXDLY_CFG[7] origin:064-gtp-channel-conf 03_83 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXDLY_CFG[8] origin:064-gtp-channel-conf 02_84 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXDLY_CFG[9] origin:064-gtp-channel-conf 03_84 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXDLY_CFG[10] origin:064-gtp-channel-conf 02_85 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXDLY_CFG[11] origin:064-gtp-channel-conf 03_85 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXDLY_CFG[12] origin:064-gtp-channel-conf 02_86 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXDLY_CFG[13] origin:064-gtp-channel-conf 03_86 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXDLY_CFG[14] origin:064-gtp-channel-conf 02_87 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXDLY_CFG[15] origin:064-gtp-channel-conf 03_87 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXDLY_LCFG[0] origin:064-gtp-channel-conf 02_568 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXDLY_LCFG[1] origin:064-gtp-channel-conf 03_568 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXDLY_LCFG[2] origin:064-gtp-channel-conf 02_569 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXDLY_LCFG[3] origin:064-gtp-channel-conf 03_569 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXDLY_LCFG[4] origin:064-gtp-channel-conf 02_570 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXDLY_LCFG[5] origin:064-gtp-channel-conf 03_570 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXDLY_LCFG[6] origin:064-gtp-channel-conf 02_571 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXDLY_LCFG[7] origin:064-gtp-channel-conf 03_571 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXDLY_LCFG[8] origin:064-gtp-channel-conf 02_572 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXDLY_TAP_CFG[0] origin:064-gtp-channel-conf 02_88 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXDLY_TAP_CFG[1] origin:064-gtp-channel-conf 03_88 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXDLY_TAP_CFG[2] origin:064-gtp-channel-conf 02_89 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXDLY_TAP_CFG[3] origin:064-gtp-channel-conf 03_89 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXDLY_TAP_CFG[4] origin:064-gtp-channel-conf 02_90 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXDLY_TAP_CFG[5] origin:064-gtp-channel-conf 03_90 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXDLY_TAP_CFG[6] origin:064-gtp-channel-conf 02_91 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXDLY_TAP_CFG[7] origin:064-gtp-channel-conf 03_91 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXDLY_TAP_CFG[8] origin:064-gtp-channel-conf 02_92 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXDLY_TAP_CFG[9] origin:064-gtp-channel-conf 03_92 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXDLY_TAP_CFG[10] origin:064-gtp-channel-conf 02_93 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXDLY_TAP_CFG[11] origin:064-gtp-channel-conf 03_93 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXDLY_TAP_CFG[12] origin:064-gtp-channel-conf 02_94 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXDLY_TAP_CFG[13] origin:064-gtp-channel-conf 03_94 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXDLY_TAP_CFG[14] origin:064-gtp-channel-conf 02_95 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXDLY_TAP_CFG[15] origin:064-gtp-channel-conf 03_95 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXGEARBOX_EN origin:064-gtp-channel-conf 01_226 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXOOB_CFG[0] origin:064-gtp-channel-conf 03_20 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXOUT_DIV[0] origin:064-gtp-channel-conf 02_386 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXOUT_DIV[1] origin:064-gtp-channel-conf 03_386 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPCSRESET_TIME[0] origin:064-gtp-channel-conf 01_130 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPCSRESET_TIME[1] origin:064-gtp-channel-conf 00_131 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPCSRESET_TIME[2] origin:064-gtp-channel-conf 01_131 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPCSRESET_TIME[3] origin:064-gtp-channel-conf 00_132 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPCSRESET_TIME[4] origin:064-gtp-channel-conf 01_132 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPH_CFG[0] origin:064-gtp-channel-conf 02_96 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPH_CFG[1] origin:064-gtp-channel-conf 03_96 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPH_CFG[2] origin:064-gtp-channel-conf 02_97 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPH_CFG[3] origin:064-gtp-channel-conf 03_97 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPH_CFG[4] origin:064-gtp-channel-conf 02_98 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPH_CFG[5] origin:064-gtp-channel-conf 03_98 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPH_CFG[6] origin:064-gtp-channel-conf 02_99 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPH_CFG[7] origin:064-gtp-channel-conf 03_99 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPH_CFG[8] origin:064-gtp-channel-conf 02_100 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPH_CFG[9] origin:064-gtp-channel-conf 03_100 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPH_CFG[10] origin:064-gtp-channel-conf 02_101 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPH_CFG[11] origin:064-gtp-channel-conf 03_101 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPH_CFG[12] origin:064-gtp-channel-conf 02_102 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPH_CFG[13] origin:064-gtp-channel-conf 03_102 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPH_CFG[14] origin:064-gtp-channel-conf 02_103 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPH_CFG[15] origin:064-gtp-channel-conf 03_103 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPH_MONITOR_SEL[0] origin:064-gtp-channel-conf 02_108 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPH_MONITOR_SEL[1] origin:064-gtp-channel-conf 03_108 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPH_MONITOR_SEL[2] origin:064-gtp-channel-conf 02_109 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPH_MONITOR_SEL[3] origin:064-gtp-channel-conf 03_109 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPH_MONITOR_SEL[4] origin:064-gtp-channel-conf 02_110 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPHDLY_CFG[0] origin:064-gtp-channel-conf 02_64 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPHDLY_CFG[1] origin:064-gtp-channel-conf 03_64 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPHDLY_CFG[2] origin:064-gtp-channel-conf 02_65 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPHDLY_CFG[3] origin:064-gtp-channel-conf 03_65 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPHDLY_CFG[4] origin:064-gtp-channel-conf 02_66 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPHDLY_CFG[5] origin:064-gtp-channel-conf 03_66 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPHDLY_CFG[6] origin:064-gtp-channel-conf 02_67 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPHDLY_CFG[7] origin:064-gtp-channel-conf 03_67 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPHDLY_CFG[8] origin:064-gtp-channel-conf 02_68 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPHDLY_CFG[9] origin:064-gtp-channel-conf 03_68 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPHDLY_CFG[10] origin:064-gtp-channel-conf 02_69 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPHDLY_CFG[11] origin:064-gtp-channel-conf 03_69 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPHDLY_CFG[12] origin:064-gtp-channel-conf 02_70 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPHDLY_CFG[13] origin:064-gtp-channel-conf 03_70 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPHDLY_CFG[14] origin:064-gtp-channel-conf 02_71 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPHDLY_CFG[15] origin:064-gtp-channel-conf 03_71 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPHDLY_CFG[16] origin:064-gtp-channel-conf 02_72 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPHDLY_CFG[17] origin:064-gtp-channel-conf 03_72 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPHDLY_CFG[18] origin:064-gtp-channel-conf 02_73 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPHDLY_CFG[19] origin:064-gtp-channel-conf 03_73 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPHDLY_CFG[20] origin:064-gtp-channel-conf 02_74 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPHDLY_CFG[21] origin:064-gtp-channel-conf 03_74 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPHDLY_CFG[22] origin:064-gtp-channel-conf 02_75 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPHDLY_CFG[23] origin:064-gtp-channel-conf 03_75 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPI_GREY_SEL[0] origin:064-gtp-channel-conf 03_498 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPI_INVSTROBE_SEL[0] origin:064-gtp-channel-conf 02_498 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPI_PPM_CFG[0] origin:064-gtp-channel-conf 02_488 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPI_PPM_CFG[1] origin:064-gtp-channel-conf 03_488 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPI_PPM_CFG[2] origin:064-gtp-channel-conf 02_489 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPI_PPM_CFG[3] origin:064-gtp-channel-conf 03_489 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPI_PPM_CFG[4] origin:064-gtp-channel-conf 02_490 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPI_PPM_CFG[5] origin:064-gtp-channel-conf 03_490 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPI_PPM_CFG[6] origin:064-gtp-channel-conf 02_491 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPI_PPM_CFG[7] origin:064-gtp-channel-conf 03_491 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPI_PPMCLK_SEL.TXUSRCLK2 origin:064-gtp-channel-conf 03_497 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPI_SYNFREQ_PPM[0] origin:064-gtp-channel-conf 02_496 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPI_SYNFREQ_PPM[1] origin:064-gtp-channel-conf 03_496 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPI_SYNFREQ_PPM[2] origin:064-gtp-channel-conf 02_497 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPI_CFG0[0] origin:064-gtp-channel-conf 02_40 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPI_CFG0[1] origin:064-gtp-channel-conf 03_40 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPI_CFG1[0] origin:064-gtp-channel-conf 02_41 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPI_CFG1[1] origin:064-gtp-channel-conf 03_41 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPI_CFG2[0] origin:064-gtp-channel-conf 02_42 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPI_CFG2[1] origin:064-gtp-channel-conf 03_42 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPI_CFG3[0] origin:064-gtp-channel-conf 02_43 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPI_CFG4[0] origin:064-gtp-channel-conf 03_43 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPI_CFG5[0] origin:064-gtp-channel-conf 02_44 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPI_CFG5[1] origin:064-gtp-channel-conf 03_44 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPI_CFG5[2] origin:064-gtp-channel-conf 02_45 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPMARESET_TIME[0] origin:064-gtp-channel-conf 00_128 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPMARESET_TIME[1] origin:064-gtp-channel-conf 01_128 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPMARESET_TIME[2] origin:064-gtp-channel-conf 00_129 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPMARESET_TIME[3] origin:064-gtp-channel-conf 01_129 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXPMARESET_TIME[4] origin:064-gtp-channel-conf 00_130 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXSYNC_MULTILANE[0] origin:064-gtp-channel-conf 01_133 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXSYNC_OVRD[0] origin:064-gtp-channel-conf 00_135 -GTP_CHANNEL_0_MID_LEFT.GTPE2.TXSYNC_SKIP_DA[0] origin:064-gtp-channel-conf 00_134 -GTP_CHANNEL_0_MID_LEFT.GTPE2.UCODEER_CLR[0] origin:064-gtp-channel-conf 01_00 -GTP_CHANNEL_0_MID_LEFT.GTPE2.USE_PCS_CLK_PHASE_SEL[0] origin:064-gtp-channel-conf 02_463 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ZINV_DMONITORCLK origin:064-gtp-channel-conf 02_13 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ZINV_DRPCLK origin:064-gtp-channel-conf 02_00 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ZINV_RXUSRCLK origin:064-gtp-channel-conf 03_01 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ZINV_SIGVALIDCLK origin:064-gtp-channel-conf 03_13 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ZINV_TXPHDLYTSTCLK origin:064-gtp-channel-conf 02_03 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ZINV_TXUSRCLK origin:064-gtp-channel-conf 03_04 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ZINV_CLKRSVD0 origin:064-gtp-channel-conf 02_23 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ZINV_CLKRSVD1 origin:064-gtp-channel-conf 03_23 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ZINV_RXUSRCLK2 origin:064-gtp-channel-conf 02_02 -GTP_CHANNEL_0_MID_LEFT.GTPE2.ZINV_TXUSRCLK2 origin:064-gtp-channel-conf 02_05 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ACJTAG_DEBUG_MODE[0] origin:064-gtp-channel-conf 00_07 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ACJTAG_MODE[0] origin:064-gtp-channel-conf 01_06 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ACJTAG_RESET[0] origin:064-gtp-channel-conf 01_07 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[0] origin:064-gtp-channel-conf 02_464 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[1] origin:064-gtp-channel-conf 03_464 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[2] origin:064-gtp-channel-conf 02_465 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[3] origin:064-gtp-channel-conf 03_465 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[4] origin:064-gtp-channel-conf 02_466 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[5] origin:064-gtp-channel-conf 03_466 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[6] origin:064-gtp-channel-conf 02_467 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[7] origin:064-gtp-channel-conf 03_467 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[8] origin:064-gtp-channel-conf 02_468 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[9] origin:064-gtp-channel-conf 03_468 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[10] origin:064-gtp-channel-conf 02_469 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[11] origin:064-gtp-channel-conf 03_469 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[12] origin:064-gtp-channel-conf 02_470 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[13] origin:064-gtp-channel-conf 03_470 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[14] origin:064-gtp-channel-conf 02_471 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[15] origin:064-gtp-channel-conf 03_471 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[16] origin:064-gtp-channel-conf 02_472 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[17] origin:064-gtp-channel-conf 03_472 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[18] origin:064-gtp-channel-conf 02_473 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[19] origin:064-gtp-channel-conf 03_473 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ALIGN_COMMA_DOUBLE origin:064-gtp-channel-conf 00_522 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[0] origin:064-gtp-channel-conf 00_496 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[1] origin:064-gtp-channel-conf 01_496 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[2] origin:064-gtp-channel-conf 00_497 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[3] origin:064-gtp-channel-conf 01_497 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[4] origin:064-gtp-channel-conf 00_498 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[5] origin:064-gtp-channel-conf 01_498 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[6] origin:064-gtp-channel-conf 00_499 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[7] origin:064-gtp-channel-conf 01_499 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[8] origin:064-gtp-channel-conf 00_500 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[9] origin:064-gtp-channel-conf 01_500 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ALIGN_COMMA_WORD[0] origin:064-gtp-channel-conf 01_526 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ALIGN_COMMA_WORD[1] origin:064-gtp-channel-conf 00_527 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ALIGN_MCOMMA_DET origin:064-gtp-channel-conf 00_523 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[0] origin:064-gtp-channel-conf 00_504 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[1] origin:064-gtp-channel-conf 01_504 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[2] origin:064-gtp-channel-conf 00_505 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[3] origin:064-gtp-channel-conf 01_505 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[4] origin:064-gtp-channel-conf 00_506 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[5] origin:064-gtp-channel-conf 01_506 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[6] origin:064-gtp-channel-conf 00_507 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[7] origin:064-gtp-channel-conf 01_507 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[8] origin:064-gtp-channel-conf 00_508 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[9] origin:064-gtp-channel-conf 01_508 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ALIGN_PCOMMA_DET origin:064-gtp-channel-conf 01_523 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[0] origin:064-gtp-channel-conf 00_512 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[1] origin:064-gtp-channel-conf 01_512 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[2] origin:064-gtp-channel-conf 00_513 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[3] origin:064-gtp-channel-conf 01_513 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[4] origin:064-gtp-channel-conf 00_514 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[5] origin:064-gtp-channel-conf 01_514 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[6] origin:064-gtp-channel-conf 00_515 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[7] origin:064-gtp-channel-conf 01_515 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[8] origin:064-gtp-channel-conf 00_516 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[9] origin:064-gtp-channel-conf 01_516 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CBCC_DATA_SOURCE_SEL.DECODED origin:064-gtp-channel-conf 01_661 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[0] origin:064-gtp-channel-conf 02_392 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[1] origin:064-gtp-channel-conf 03_392 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[2] origin:064-gtp-channel-conf 02_393 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[3] origin:064-gtp-channel-conf 03_393 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[4] origin:064-gtp-channel-conf 02_394 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[5] origin:064-gtp-channel-conf 03_394 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[6] origin:064-gtp-channel-conf 02_395 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[7] origin:064-gtp-channel-conf 03_395 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[8] origin:064-gtp-channel-conf 02_396 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[9] origin:064-gtp-channel-conf 03_396 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[10] origin:064-gtp-channel-conf 02_397 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[11] origin:064-gtp-channel-conf 03_397 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[12] origin:064-gtp-channel-conf 02_398 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[13] origin:064-gtp-channel-conf 03_398 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[14] origin:064-gtp-channel-conf 02_399 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[15] origin:064-gtp-channel-conf 03_399 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[16] origin:064-gtp-channel-conf 02_400 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[17] origin:064-gtp-channel-conf 03_400 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[18] origin:064-gtp-channel-conf 02_401 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[19] origin:064-gtp-channel-conf 03_401 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[20] origin:064-gtp-channel-conf 02_402 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[21] origin:064-gtp-channel-conf 03_402 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[22] origin:064-gtp-channel-conf 02_403 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[23] origin:064-gtp-channel-conf 03_403 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[24] origin:064-gtp-channel-conf 02_404 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[25] origin:064-gtp-channel-conf 03_404 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[26] origin:064-gtp-channel-conf 02_405 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[27] origin:064-gtp-channel-conf 03_405 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[28] origin:064-gtp-channel-conf 02_406 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[29] origin:064-gtp-channel-conf 03_406 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[30] origin:064-gtp-channel-conf 02_407 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[31] origin:064-gtp-channel-conf 03_407 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[32] origin:064-gtp-channel-conf 02_408 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[33] origin:064-gtp-channel-conf 03_408 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[34] origin:064-gtp-channel-conf 02_409 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[35] origin:064-gtp-channel-conf 03_409 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[36] origin:064-gtp-channel-conf 02_410 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[37] origin:064-gtp-channel-conf 03_410 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[38] origin:064-gtp-channel-conf 02_411 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[39] origin:064-gtp-channel-conf 03_411 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[40] origin:064-gtp-channel-conf 02_412 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[41] origin:064-gtp-channel-conf 03_412 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[42] origin:064-gtp-channel-conf 02_413 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG2[0] origin:064-gtp-channel-conf 02_459 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG2[1] origin:064-gtp-channel-conf 03_459 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG2[2] origin:064-gtp-channel-conf 02_460 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG2[3] origin:064-gtp-channel-conf 03_460 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG2[4] origin:064-gtp-channel-conf 02_461 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG2[5] origin:064-gtp-channel-conf 03_461 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG2[6] origin:064-gtp-channel-conf 02_462 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG3[0] origin:064-gtp-channel-conf 02_416 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG3[1] origin:064-gtp-channel-conf 03_416 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG3[2] origin:064-gtp-channel-conf 02_417 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG3[3] origin:064-gtp-channel-conf 03_417 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG3[4] origin:064-gtp-channel-conf 02_418 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG3[5] origin:064-gtp-channel-conf 03_418 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG3[6] origin:064-gtp-channel-conf 02_419 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG4[0] origin:064-gtp-channel-conf 03_438 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG5[0] origin:064-gtp-channel-conf 02_429 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG5[1] origin:064-gtp-channel-conf 03_429 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG6[0] origin:064-gtp-channel-conf 03_436 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG6[1] origin:064-gtp-channel-conf 02_437 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG6[2] origin:064-gtp-channel-conf 03_437 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG6[3] origin:064-gtp-channel-conf 02_438 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_KEEP_ALIGN origin:064-gtp-channel-conf 01_631 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_MAX_SKEW[0] origin:064-gtp-channel-conf 00_670 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_MAX_SKEW[1] origin:064-gtp-channel-conf 01_670 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_MAX_SKEW[2] origin:064-gtp-channel-conf 00_671 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_MAX_SKEW[3] origin:064-gtp-channel-conf 01_671 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[0] origin:064-gtp-channel-conf 00_608 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[1] origin:064-gtp-channel-conf 01_608 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[2] origin:064-gtp-channel-conf 00_609 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[3] origin:064-gtp-channel-conf 01_609 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[4] origin:064-gtp-channel-conf 00_610 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[5] origin:064-gtp-channel-conf 01_610 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[6] origin:064-gtp-channel-conf 00_611 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[7] origin:064-gtp-channel-conf 01_611 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[8] origin:064-gtp-channel-conf 00_612 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[9] origin:064-gtp-channel-conf 01_612 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[0] origin:064-gtp-channel-conf 00_616 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[1] origin:064-gtp-channel-conf 01_616 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[2] origin:064-gtp-channel-conf 00_617 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[3] origin:064-gtp-channel-conf 01_617 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[4] origin:064-gtp-channel-conf 00_618 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[5] origin:064-gtp-channel-conf 01_618 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[6] origin:064-gtp-channel-conf 00_619 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[7] origin:064-gtp-channel-conf 01_619 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[8] origin:064-gtp-channel-conf 00_620 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[9] origin:064-gtp-channel-conf 01_620 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[0] origin:064-gtp-channel-conf 00_624 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[1] origin:064-gtp-channel-conf 01_624 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[2] origin:064-gtp-channel-conf 00_625 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[3] origin:064-gtp-channel-conf 01_625 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[4] origin:064-gtp-channel-conf 00_626 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[5] origin:064-gtp-channel-conf 01_626 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[6] origin:064-gtp-channel-conf 00_627 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[7] origin:064-gtp-channel-conf 01_627 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[8] origin:064-gtp-channel-conf 00_628 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[9] origin:064-gtp-channel-conf 01_628 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[0] origin:064-gtp-channel-conf 00_632 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[1] origin:064-gtp-channel-conf 01_632 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[2] origin:064-gtp-channel-conf 00_633 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[3] origin:064-gtp-channel-conf 01_633 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[4] origin:064-gtp-channel-conf 00_634 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[5] origin:064-gtp-channel-conf 01_634 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[6] origin:064-gtp-channel-conf 00_635 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[7] origin:064-gtp-channel-conf 01_635 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[8] origin:064-gtp-channel-conf 00_636 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[9] origin:064-gtp-channel-conf 01_636 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_ENABLE[0] origin:064-gtp-channel-conf 00_614 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_ENABLE[1] origin:064-gtp-channel-conf 01_614 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_ENABLE[2] origin:064-gtp-channel-conf 00_615 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_ENABLE[3] origin:064-gtp-channel-conf 01_615 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[0] origin:064-gtp-channel-conf 00_640 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[1] origin:064-gtp-channel-conf 01_640 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[2] origin:064-gtp-channel-conf 00_641 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[3] origin:064-gtp-channel-conf 01_641 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[4] origin:064-gtp-channel-conf 00_642 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[5] origin:064-gtp-channel-conf 01_642 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[6] origin:064-gtp-channel-conf 00_643 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[7] origin:064-gtp-channel-conf 01_643 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[8] origin:064-gtp-channel-conf 00_644 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[9] origin:064-gtp-channel-conf 01_644 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[0] origin:064-gtp-channel-conf 00_648 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[1] origin:064-gtp-channel-conf 01_648 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[2] origin:064-gtp-channel-conf 00_649 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[3] origin:064-gtp-channel-conf 01_649 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[4] origin:064-gtp-channel-conf 00_650 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[5] origin:064-gtp-channel-conf 01_650 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[6] origin:064-gtp-channel-conf 00_651 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[7] origin:064-gtp-channel-conf 01_651 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[8] origin:064-gtp-channel-conf 00_652 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[9] origin:064-gtp-channel-conf 01_652 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[0] origin:064-gtp-channel-conf 00_656 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[1] origin:064-gtp-channel-conf 01_656 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[2] origin:064-gtp-channel-conf 00_657 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[3] origin:064-gtp-channel-conf 01_657 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[4] origin:064-gtp-channel-conf 00_658 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[5] origin:064-gtp-channel-conf 01_658 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[6] origin:064-gtp-channel-conf 00_659 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[7] origin:064-gtp-channel-conf 01_659 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[8] origin:064-gtp-channel-conf 00_660 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[9] origin:064-gtp-channel-conf 01_660 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[0] origin:064-gtp-channel-conf 00_664 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[1] origin:064-gtp-channel-conf 01_664 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[2] origin:064-gtp-channel-conf 00_665 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[3] origin:064-gtp-channel-conf 01_665 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[4] origin:064-gtp-channel-conf 00_666 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[5] origin:064-gtp-channel-conf 01_666 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[6] origin:064-gtp-channel-conf 00_667 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[7] origin:064-gtp-channel-conf 01_667 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[8] origin:064-gtp-channel-conf 00_668 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[9] origin:064-gtp-channel-conf 01_668 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_ENABLE[0] origin:064-gtp-channel-conf 00_646 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_ENABLE[1] origin:064-gtp-channel-conf 01_646 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_ENABLE[2] origin:064-gtp-channel-conf 00_647 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_ENABLE[3] origin:064-gtp-channel-conf 01_647 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_USE origin:064-gtp-channel-conf 01_645 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_LEN[0] origin:064-gtp-channel-conf 00_623 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_LEN[1] origin:064-gtp-channel-conf 01_623 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COMMON_SWING[0] origin:064-gtp-channel-conf 03_311 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_KEEP_IDLE origin:064-gtp-channel-conf 00_591 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_MAX_LAT[0] origin:064-gtp-channel-conf 00_557 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_MAX_LAT[1] origin:064-gtp-channel-conf 01_557 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_MAX_LAT[2] origin:064-gtp-channel-conf 00_558 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_MAX_LAT[3] origin:064-gtp-channel-conf 01_558 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_MAX_LAT[4] origin:064-gtp-channel-conf 00_559 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_MAX_LAT[5] origin:064-gtp-channel-conf 01_559 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_MIN_LAT[0] origin:064-gtp-channel-conf 00_565 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_MIN_LAT[1] origin:064-gtp-channel-conf 01_565 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_MIN_LAT[2] origin:064-gtp-channel-conf 00_566 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_MIN_LAT[3] origin:064-gtp-channel-conf 01_566 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_MIN_LAT[4] origin:064-gtp-channel-conf 00_567 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_MIN_LAT[5] origin:064-gtp-channel-conf 01_567 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_PRECEDENCE origin:064-gtp-channel-conf 00_590 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_REPEAT_WAIT[0] origin:064-gtp-channel-conf 00_573 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_REPEAT_WAIT[1] origin:064-gtp-channel-conf 01_573 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_REPEAT_WAIT[2] origin:064-gtp-channel-conf 00_574 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_REPEAT_WAIT[3] origin:064-gtp-channel-conf 01_574 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_REPEAT_WAIT[4] origin:064-gtp-channel-conf 00_575 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[0] origin:064-gtp-channel-conf 00_544 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[1] origin:064-gtp-channel-conf 01_544 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[2] origin:064-gtp-channel-conf 00_545 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[3] origin:064-gtp-channel-conf 01_545 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[4] origin:064-gtp-channel-conf 00_546 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[5] origin:064-gtp-channel-conf 01_546 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[6] origin:064-gtp-channel-conf 00_547 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[7] origin:064-gtp-channel-conf 01_547 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[8] origin:064-gtp-channel-conf 00_548 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[9] origin:064-gtp-channel-conf 01_548 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[0] origin:064-gtp-channel-conf 00_552 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[1] origin:064-gtp-channel-conf 01_552 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[2] origin:064-gtp-channel-conf 00_553 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[3] origin:064-gtp-channel-conf 01_553 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[4] origin:064-gtp-channel-conf 00_554 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[5] origin:064-gtp-channel-conf 01_554 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[6] origin:064-gtp-channel-conf 00_555 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[7] origin:064-gtp-channel-conf 01_555 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[8] origin:064-gtp-channel-conf 00_556 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[9] origin:064-gtp-channel-conf 01_556 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[0] origin:064-gtp-channel-conf 00_560 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[1] origin:064-gtp-channel-conf 01_560 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[2] origin:064-gtp-channel-conf 00_561 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[3] origin:064-gtp-channel-conf 01_561 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[4] origin:064-gtp-channel-conf 00_562 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[5] origin:064-gtp-channel-conf 01_562 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[6] origin:064-gtp-channel-conf 00_563 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[7] origin:064-gtp-channel-conf 01_563 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[8] origin:064-gtp-channel-conf 00_564 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[9] origin:064-gtp-channel-conf 01_564 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[0] origin:064-gtp-channel-conf 00_568 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[1] origin:064-gtp-channel-conf 01_568 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[2] origin:064-gtp-channel-conf 00_569 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[3] origin:064-gtp-channel-conf 01_569 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[4] origin:064-gtp-channel-conf 00_570 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[5] origin:064-gtp-channel-conf 01_570 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[6] origin:064-gtp-channel-conf 00_571 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[7] origin:064-gtp-channel-conf 01_571 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[8] origin:064-gtp-channel-conf 00_572 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[9] origin:064-gtp-channel-conf 01_572 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_ENABLE[0] origin:064-gtp-channel-conf 00_549 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_ENABLE[1] origin:064-gtp-channel-conf 01_549 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_ENABLE[2] origin:064-gtp-channel-conf 00_550 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_ENABLE[3] origin:064-gtp-channel-conf 01_550 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[0] origin:064-gtp-channel-conf 00_576 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[1] origin:064-gtp-channel-conf 01_576 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[2] origin:064-gtp-channel-conf 00_577 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[3] origin:064-gtp-channel-conf 01_577 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[4] origin:064-gtp-channel-conf 00_578 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[5] origin:064-gtp-channel-conf 01_578 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[6] origin:064-gtp-channel-conf 00_579 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[7] origin:064-gtp-channel-conf 01_579 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[8] origin:064-gtp-channel-conf 00_580 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[9] origin:064-gtp-channel-conf 01_580 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[0] origin:064-gtp-channel-conf 00_584 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[1] origin:064-gtp-channel-conf 01_584 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[2] origin:064-gtp-channel-conf 00_585 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[3] origin:064-gtp-channel-conf 01_585 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[4] origin:064-gtp-channel-conf 00_586 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[5] origin:064-gtp-channel-conf 01_586 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[6] origin:064-gtp-channel-conf 00_587 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[7] origin:064-gtp-channel-conf 01_587 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[8] origin:064-gtp-channel-conf 00_588 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[9] origin:064-gtp-channel-conf 01_588 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[0] origin:064-gtp-channel-conf 00_592 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[1] origin:064-gtp-channel-conf 01_592 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[2] origin:064-gtp-channel-conf 00_593 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[3] origin:064-gtp-channel-conf 01_593 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[4] origin:064-gtp-channel-conf 00_594 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[5] origin:064-gtp-channel-conf 01_594 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[6] origin:064-gtp-channel-conf 00_595 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[7] origin:064-gtp-channel-conf 01_595 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[8] origin:064-gtp-channel-conf 00_596 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[9] origin:064-gtp-channel-conf 01_596 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[0] origin:064-gtp-channel-conf 00_600 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[1] origin:064-gtp-channel-conf 01_600 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[2] origin:064-gtp-channel-conf 00_601 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[3] origin:064-gtp-channel-conf 01_601 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[4] origin:064-gtp-channel-conf 00_602 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[5] origin:064-gtp-channel-conf 01_602 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[6] origin:064-gtp-channel-conf 00_603 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[7] origin:064-gtp-channel-conf 01_603 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[8] origin:064-gtp-channel-conf 00_604 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[9] origin:064-gtp-channel-conf 01_604 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_ENABLE[0] origin:064-gtp-channel-conf 00_581 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_ENABLE[1] origin:064-gtp-channel-conf 01_581 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_ENABLE[2] origin:064-gtp-channel-conf 00_582 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_ENABLE[3] origin:064-gtp-channel-conf 01_582 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_USE origin:064-gtp-channel-conf 00_583 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_LEN[0] origin:064-gtp-channel-conf 00_589 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_LEN[1] origin:064-gtp-channel-conf 01_589 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.CLK_CORRECT_USE origin:064-gtp-channel-conf 00_551 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.DEC_MCOMMA_DETECT origin:064-gtp-channel-conf 01_494 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.DEC_PCOMMA_DETECT origin:064-gtp-channel-conf 00_495 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.DEC_VALID_COMMA_ONLY origin:064-gtp-channel-conf 00_494 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[0] origin:064-gtp-channel-conf 02_368 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[1] origin:064-gtp-channel-conf 03_368 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[2] origin:064-gtp-channel-conf 02_369 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[3] origin:064-gtp-channel-conf 03_369 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[4] origin:064-gtp-channel-conf 02_370 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[5] origin:064-gtp-channel-conf 03_370 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[6] origin:064-gtp-channel-conf 02_371 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[7] origin:064-gtp-channel-conf 03_371 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[8] origin:064-gtp-channel-conf 02_372 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[9] origin:064-gtp-channel-conf 03_372 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[10] origin:064-gtp-channel-conf 02_373 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[11] origin:064-gtp-channel-conf 03_373 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[12] origin:064-gtp-channel-conf 02_374 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[13] origin:064-gtp-channel-conf 03_374 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[14] origin:064-gtp-channel-conf 02_375 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[15] origin:064-gtp-channel-conf 03_375 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[16] origin:064-gtp-channel-conf 02_376 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[17] origin:064-gtp-channel-conf 03_376 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[18] origin:064-gtp-channel-conf 02_377 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[19] origin:064-gtp-channel-conf 03_377 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[20] origin:064-gtp-channel-conf 02_378 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[21] origin:064-gtp-channel-conf 03_378 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[22] origin:064-gtp-channel-conf 02_379 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[23] origin:064-gtp-channel-conf 03_379 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_CLK_PHASE_SEL[0] origin:064-gtp-channel-conf 03_463 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_CONTROL[0] origin:064-gtp-channel-conf 00_488 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_CONTROL[1] origin:064-gtp-channel-conf 01_488 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_CONTROL[2] origin:064-gtp-channel-conf 00_489 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_CONTROL[3] origin:064-gtp-channel-conf 01_489 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_CONTROL[4] origin:064-gtp-channel-conf 00_490 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_CONTROL[5] origin:064-gtp-channel-conf 01_490 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_ERRDET_EN origin:064-gtp-channel-conf 01_492 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_EYE_SCAN_EN origin:064-gtp-channel-conf 00_492 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_HORZ_OFFSET[0] origin:064-gtp-channel-conf 00_480 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_HORZ_OFFSET[1] origin:064-gtp-channel-conf 01_480 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_HORZ_OFFSET[2] origin:064-gtp-channel-conf 00_481 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_HORZ_OFFSET[3] origin:064-gtp-channel-conf 01_481 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_HORZ_OFFSET[4] origin:064-gtp-channel-conf 00_482 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_HORZ_OFFSET[5] origin:064-gtp-channel-conf 01_482 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_HORZ_OFFSET[6] origin:064-gtp-channel-conf 00_483 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_HORZ_OFFSET[7] origin:064-gtp-channel-conf 01_483 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_HORZ_OFFSET[8] origin:064-gtp-channel-conf 00_484 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_HORZ_OFFSET[9] origin:064-gtp-channel-conf 01_484 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_HORZ_OFFSET[10] origin:064-gtp-channel-conf 00_485 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_HORZ_OFFSET[11] origin:064-gtp-channel-conf 01_485 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_PMA_CFG[0] origin:064-gtp-channel-conf 02_624 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_PMA_CFG[1] origin:064-gtp-channel-conf 03_624 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_PMA_CFG[2] origin:064-gtp-channel-conf 02_625 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_PMA_CFG[3] origin:064-gtp-channel-conf 03_625 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_PMA_CFG[4] origin:064-gtp-channel-conf 02_626 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_PMA_CFG[5] origin:064-gtp-channel-conf 03_626 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_PMA_CFG[6] origin:064-gtp-channel-conf 02_627 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_PMA_CFG[7] origin:064-gtp-channel-conf 03_627 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_PMA_CFG[8] origin:064-gtp-channel-conf 02_628 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_PMA_CFG[9] origin:064-gtp-channel-conf 03_628 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_PRESCALE[0] origin:064-gtp-channel-conf 01_477 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_PRESCALE[1] origin:064-gtp-channel-conf 00_478 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_PRESCALE[2] origin:064-gtp-channel-conf 01_478 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_PRESCALE[3] origin:064-gtp-channel-conf 00_479 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_PRESCALE[4] origin:064-gtp-channel-conf 01_479 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[0] origin:064-gtp-channel-conf 00_392 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[1] origin:064-gtp-channel-conf 01_392 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[2] origin:064-gtp-channel-conf 00_393 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[3] origin:064-gtp-channel-conf 01_393 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[4] origin:064-gtp-channel-conf 00_394 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[5] origin:064-gtp-channel-conf 01_394 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[6] origin:064-gtp-channel-conf 00_395 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[7] origin:064-gtp-channel-conf 01_395 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[8] origin:064-gtp-channel-conf 00_396 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[9] origin:064-gtp-channel-conf 01_396 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[10] origin:064-gtp-channel-conf 00_397 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[11] origin:064-gtp-channel-conf 01_397 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[12] origin:064-gtp-channel-conf 00_398 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[13] origin:064-gtp-channel-conf 01_398 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[14] origin:064-gtp-channel-conf 00_399 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[15] origin:064-gtp-channel-conf 01_399 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[16] origin:064-gtp-channel-conf 00_400 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[17] origin:064-gtp-channel-conf 01_400 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[18] origin:064-gtp-channel-conf 00_401 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[19] origin:064-gtp-channel-conf 01_401 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[20] origin:064-gtp-channel-conf 00_402 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[21] origin:064-gtp-channel-conf 01_402 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[22] origin:064-gtp-channel-conf 00_403 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[23] origin:064-gtp-channel-conf 01_403 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[24] origin:064-gtp-channel-conf 00_404 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[25] origin:064-gtp-channel-conf 01_404 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[26] origin:064-gtp-channel-conf 00_405 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[27] origin:064-gtp-channel-conf 01_405 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[28] origin:064-gtp-channel-conf 00_406 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[29] origin:064-gtp-channel-conf 01_406 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[30] origin:064-gtp-channel-conf 00_407 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[31] origin:064-gtp-channel-conf 01_407 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[32] origin:064-gtp-channel-conf 00_408 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[33] origin:064-gtp-channel-conf 01_408 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[34] origin:064-gtp-channel-conf 00_409 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[35] origin:064-gtp-channel-conf 01_409 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[36] origin:064-gtp-channel-conf 00_410 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[37] origin:064-gtp-channel-conf 01_410 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[38] origin:064-gtp-channel-conf 00_411 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[39] origin:064-gtp-channel-conf 01_411 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[40] origin:064-gtp-channel-conf 00_412 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[41] origin:064-gtp-channel-conf 01_412 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[42] origin:064-gtp-channel-conf 00_413 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[43] origin:064-gtp-channel-conf 01_413 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[44] origin:064-gtp-channel-conf 00_414 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[45] origin:064-gtp-channel-conf 01_414 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[46] origin:064-gtp-channel-conf 00_415 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[47] origin:064-gtp-channel-conf 01_415 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[48] origin:064-gtp-channel-conf 00_416 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[49] origin:064-gtp-channel-conf 01_416 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[50] origin:064-gtp-channel-conf 00_417 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[51] origin:064-gtp-channel-conf 01_417 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[52] origin:064-gtp-channel-conf 00_418 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[53] origin:064-gtp-channel-conf 01_418 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[54] origin:064-gtp-channel-conf 00_419 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[55] origin:064-gtp-channel-conf 01_419 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[56] origin:064-gtp-channel-conf 00_420 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[57] origin:064-gtp-channel-conf 01_420 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[58] origin:064-gtp-channel-conf 00_421 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[59] origin:064-gtp-channel-conf 01_421 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[60] origin:064-gtp-channel-conf 00_422 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[61] origin:064-gtp-channel-conf 01_422 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[62] origin:064-gtp-channel-conf 00_423 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[63] origin:064-gtp-channel-conf 01_423 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[64] origin:064-gtp-channel-conf 00_424 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[65] origin:064-gtp-channel-conf 01_424 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[66] origin:064-gtp-channel-conf 00_425 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[67] origin:064-gtp-channel-conf 01_425 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[68] origin:064-gtp-channel-conf 00_426 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[69] origin:064-gtp-channel-conf 01_426 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[70] origin:064-gtp-channel-conf 00_427 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[71] origin:064-gtp-channel-conf 01_427 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[72] origin:064-gtp-channel-conf 00_428 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[73] origin:064-gtp-channel-conf 01_428 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[74] origin:064-gtp-channel-conf 00_429 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[75] origin:064-gtp-channel-conf 01_429 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[76] origin:064-gtp-channel-conf 00_430 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[77] origin:064-gtp-channel-conf 01_430 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[78] origin:064-gtp-channel-conf 00_431 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[79] origin:064-gtp-channel-conf 01_431 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[0] origin:064-gtp-channel-conf 00_352 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[1] origin:064-gtp-channel-conf 01_352 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[2] origin:064-gtp-channel-conf 00_353 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[3] origin:064-gtp-channel-conf 01_353 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[4] origin:064-gtp-channel-conf 00_354 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[5] origin:064-gtp-channel-conf 01_354 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[6] origin:064-gtp-channel-conf 00_355 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[7] origin:064-gtp-channel-conf 01_355 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[8] origin:064-gtp-channel-conf 00_356 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[9] origin:064-gtp-channel-conf 01_356 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[10] origin:064-gtp-channel-conf 00_357 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[11] origin:064-gtp-channel-conf 01_357 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[12] origin:064-gtp-channel-conf 00_358 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[13] origin:064-gtp-channel-conf 01_358 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[14] origin:064-gtp-channel-conf 00_359 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[15] origin:064-gtp-channel-conf 01_359 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[16] origin:064-gtp-channel-conf 00_360 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[17] origin:064-gtp-channel-conf 01_360 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[18] origin:064-gtp-channel-conf 00_361 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[19] origin:064-gtp-channel-conf 01_361 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[20] origin:064-gtp-channel-conf 00_362 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[21] origin:064-gtp-channel-conf 01_362 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[22] origin:064-gtp-channel-conf 00_363 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[23] origin:064-gtp-channel-conf 01_363 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[24] origin:064-gtp-channel-conf 00_364 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[25] origin:064-gtp-channel-conf 01_364 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[26] origin:064-gtp-channel-conf 00_365 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[27] origin:064-gtp-channel-conf 01_365 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[28] origin:064-gtp-channel-conf 00_366 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[29] origin:064-gtp-channel-conf 01_366 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[30] origin:064-gtp-channel-conf 00_367 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[31] origin:064-gtp-channel-conf 01_367 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[32] origin:064-gtp-channel-conf 00_368 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[33] origin:064-gtp-channel-conf 01_368 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[34] origin:064-gtp-channel-conf 00_369 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[35] origin:064-gtp-channel-conf 01_369 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[36] origin:064-gtp-channel-conf 00_370 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[37] origin:064-gtp-channel-conf 01_370 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[38] origin:064-gtp-channel-conf 00_371 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[39] origin:064-gtp-channel-conf 01_371 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[40] origin:064-gtp-channel-conf 00_372 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[41] origin:064-gtp-channel-conf 01_372 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[42] origin:064-gtp-channel-conf 00_373 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[43] origin:064-gtp-channel-conf 01_373 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[44] origin:064-gtp-channel-conf 00_374 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[45] origin:064-gtp-channel-conf 01_374 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[46] origin:064-gtp-channel-conf 00_375 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[47] origin:064-gtp-channel-conf 01_375 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[48] origin:064-gtp-channel-conf 00_376 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[49] origin:064-gtp-channel-conf 01_376 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[50] origin:064-gtp-channel-conf 00_377 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[51] origin:064-gtp-channel-conf 01_377 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[52] origin:064-gtp-channel-conf 00_378 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[53] origin:064-gtp-channel-conf 01_378 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[54] origin:064-gtp-channel-conf 00_379 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[55] origin:064-gtp-channel-conf 01_379 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[56] origin:064-gtp-channel-conf 00_380 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[57] origin:064-gtp-channel-conf 01_380 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[58] origin:064-gtp-channel-conf 00_381 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[59] origin:064-gtp-channel-conf 01_381 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[60] origin:064-gtp-channel-conf 00_382 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[61] origin:064-gtp-channel-conf 01_382 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[62] origin:064-gtp-channel-conf 00_383 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[63] origin:064-gtp-channel-conf 01_383 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[64] origin:064-gtp-channel-conf 00_384 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[65] origin:064-gtp-channel-conf 01_384 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[66] origin:064-gtp-channel-conf 00_385 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[67] origin:064-gtp-channel-conf 01_385 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[68] origin:064-gtp-channel-conf 00_386 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[69] origin:064-gtp-channel-conf 01_386 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[70] origin:064-gtp-channel-conf 00_387 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[71] origin:064-gtp-channel-conf 01_387 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[72] origin:064-gtp-channel-conf 00_388 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[73] origin:064-gtp-channel-conf 01_388 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[74] origin:064-gtp-channel-conf 00_389 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[75] origin:064-gtp-channel-conf 01_389 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[76] origin:064-gtp-channel-conf 00_390 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[77] origin:064-gtp-channel-conf 01_390 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[78] origin:064-gtp-channel-conf 00_391 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[79] origin:064-gtp-channel-conf 01_391 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[0] origin:064-gtp-channel-conf 00_432 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[1] origin:064-gtp-channel-conf 01_432 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[2] origin:064-gtp-channel-conf 00_433 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[3] origin:064-gtp-channel-conf 01_433 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[4] origin:064-gtp-channel-conf 00_434 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[5] origin:064-gtp-channel-conf 01_434 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[6] origin:064-gtp-channel-conf 00_435 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[7] origin:064-gtp-channel-conf 01_435 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[8] origin:064-gtp-channel-conf 00_436 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[9] origin:064-gtp-channel-conf 01_436 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[10] origin:064-gtp-channel-conf 00_437 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[11] origin:064-gtp-channel-conf 01_437 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[12] origin:064-gtp-channel-conf 00_438 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[13] origin:064-gtp-channel-conf 01_438 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[14] origin:064-gtp-channel-conf 00_439 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[15] origin:064-gtp-channel-conf 01_439 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[16] origin:064-gtp-channel-conf 00_440 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[17] origin:064-gtp-channel-conf 01_440 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[18] origin:064-gtp-channel-conf 00_441 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[19] origin:064-gtp-channel-conf 01_441 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[20] origin:064-gtp-channel-conf 00_442 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[21] origin:064-gtp-channel-conf 01_442 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[22] origin:064-gtp-channel-conf 00_443 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[23] origin:064-gtp-channel-conf 01_443 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[24] origin:064-gtp-channel-conf 00_444 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[25] origin:064-gtp-channel-conf 01_444 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[26] origin:064-gtp-channel-conf 00_445 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[27] origin:064-gtp-channel-conf 01_445 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[28] origin:064-gtp-channel-conf 00_446 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[29] origin:064-gtp-channel-conf 01_446 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[30] origin:064-gtp-channel-conf 00_447 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[31] origin:064-gtp-channel-conf 01_447 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[32] origin:064-gtp-channel-conf 00_448 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[33] origin:064-gtp-channel-conf 01_448 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[34] origin:064-gtp-channel-conf 00_449 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[35] origin:064-gtp-channel-conf 01_449 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[36] origin:064-gtp-channel-conf 00_450 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[37] origin:064-gtp-channel-conf 01_450 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[38] origin:064-gtp-channel-conf 00_451 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[39] origin:064-gtp-channel-conf 01_451 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[40] origin:064-gtp-channel-conf 00_452 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[41] origin:064-gtp-channel-conf 01_452 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[42] origin:064-gtp-channel-conf 00_453 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[43] origin:064-gtp-channel-conf 01_453 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[44] origin:064-gtp-channel-conf 00_454 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[45] origin:064-gtp-channel-conf 01_454 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[46] origin:064-gtp-channel-conf 00_455 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[47] origin:064-gtp-channel-conf 01_455 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[48] origin:064-gtp-channel-conf 00_456 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[49] origin:064-gtp-channel-conf 01_456 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[50] origin:064-gtp-channel-conf 00_457 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[51] origin:064-gtp-channel-conf 01_457 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[52] origin:064-gtp-channel-conf 00_458 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[53] origin:064-gtp-channel-conf 01_458 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[54] origin:064-gtp-channel-conf 00_459 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[55] origin:064-gtp-channel-conf 01_459 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[56] origin:064-gtp-channel-conf 00_460 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[57] origin:064-gtp-channel-conf 01_460 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[58] origin:064-gtp-channel-conf 00_461 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[59] origin:064-gtp-channel-conf 01_461 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[60] origin:064-gtp-channel-conf 00_462 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[61] origin:064-gtp-channel-conf 01_462 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[62] origin:064-gtp-channel-conf 00_463 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[63] origin:064-gtp-channel-conf 01_463 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[64] origin:064-gtp-channel-conf 00_464 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[65] origin:064-gtp-channel-conf 01_464 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[66] origin:064-gtp-channel-conf 00_465 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[67] origin:064-gtp-channel-conf 01_465 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[68] origin:064-gtp-channel-conf 00_466 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[69] origin:064-gtp-channel-conf 01_466 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[70] origin:064-gtp-channel-conf 00_467 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[71] origin:064-gtp-channel-conf 01_467 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[72] origin:064-gtp-channel-conf 00_468 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[73] origin:064-gtp-channel-conf 01_468 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[74] origin:064-gtp-channel-conf 00_469 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[75] origin:064-gtp-channel-conf 01_469 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[76] origin:064-gtp-channel-conf 00_470 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[77] origin:064-gtp-channel-conf 01_470 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[78] origin:064-gtp-channel-conf 00_471 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[79] origin:064-gtp-channel-conf 01_471 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_VERT_OFFSET[0] origin:064-gtp-channel-conf 00_472 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_VERT_OFFSET[1] origin:064-gtp-channel-conf 01_472 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_VERT_OFFSET[2] origin:064-gtp-channel-conf 00_473 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_VERT_OFFSET[3] origin:064-gtp-channel-conf 01_473 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_VERT_OFFSET[4] origin:064-gtp-channel-conf 00_474 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_VERT_OFFSET[5] origin:064-gtp-channel-conf 01_474 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_VERT_OFFSET[6] origin:064-gtp-channel-conf 00_475 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_VERT_OFFSET[7] origin:064-gtp-channel-conf 01_475 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.ES_VERT_OFFSET[8] origin:064-gtp-channel-conf 00_476 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.FTS_DESKEW_SEQ_ENABLE[0] origin:064-gtp-channel-conf 00_662 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.FTS_DESKEW_SEQ_ENABLE[1] origin:064-gtp-channel-conf 01_662 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.FTS_DESKEW_SEQ_ENABLE[2] origin:064-gtp-channel-conf 00_663 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.FTS_DESKEW_SEQ_ENABLE[3] origin:064-gtp-channel-conf 01_663 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.FTS_LANE_DESKEW_CFG[0] origin:064-gtp-channel-conf 00_654 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.FTS_LANE_DESKEW_CFG[1] origin:064-gtp-channel-conf 01_654 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.FTS_LANE_DESKEW_CFG[2] origin:064-gtp-channel-conf 00_655 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.FTS_LANE_DESKEW_CFG[3] origin:064-gtp-channel-conf 01_655 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.FTS_LANE_DESKEW_EN origin:064-gtp-channel-conf 01_653 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.GEARBOX_MODE[0] origin:064-gtp-channel-conf 00_224 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.GEARBOX_MODE[1] origin:064-gtp-channel-conf 01_224 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.GEARBOX_MODE[2] origin:064-gtp-channel-conf 00_225 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.IN_USE origin:064-gtp-channel-conf 00_00 00_01 00_47 00_52 00_53 00_65 01_01 01_47 02_129 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.INV_DMONITORCLK origin:064-gtp-channel-conf 02_13 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.INV_DRPCLK origin:064-gtp-channel-conf 02_00 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.INV_RXUSRCLK origin:064-gtp-channel-conf 03_01 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.INV_SIGVALIDCLK origin:064-gtp-channel-conf 03_13 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.INV_TXPHDLYTSTCLK origin:064-gtp-channel-conf 02_03 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.INV_TXUSRCLK origin:064-gtp-channel-conf 03_04 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.INV_CLKRSVD0 origin:064-gtp-channel-conf 02_23 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.INV_CLKRSVD1 origin:064-gtp-channel-conf 03_23 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.INV_RXUSRCLK2 origin:064-gtp-channel-conf 02_02 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.INV_TXUSRCLK2 origin:064-gtp-channel-conf 02_05 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.LOOPBACK_CFG[0] origin:064-gtp-channel-conf 02_20 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.OUTREFCLK_SEL_INV[0] origin:064-gtp-channel-conf 00_149 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.OUTREFCLK_SEL_INV[1] origin:064-gtp-channel-conf 01_149 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PCS_PCIE_EN origin:064-gtp-channel-conf 00_216 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[0] origin:064-gtp-channel-conf 02_184 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[1] origin:064-gtp-channel-conf 03_184 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[2] origin:064-gtp-channel-conf 02_185 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[3] origin:064-gtp-channel-conf 03_185 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[4] origin:064-gtp-channel-conf 02_186 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[5] origin:064-gtp-channel-conf 03_186 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[6] origin:064-gtp-channel-conf 02_187 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[7] origin:064-gtp-channel-conf 03_187 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[8] origin:064-gtp-channel-conf 02_188 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[9] origin:064-gtp-channel-conf 03_188 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[10] origin:064-gtp-channel-conf 02_189 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[11] origin:064-gtp-channel-conf 03_189 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[12] origin:064-gtp-channel-conf 02_190 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[13] origin:064-gtp-channel-conf 03_190 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[14] origin:064-gtp-channel-conf 02_191 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[15] origin:064-gtp-channel-conf 03_191 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[16] origin:064-gtp-channel-conf 02_192 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[17] origin:064-gtp-channel-conf 03_192 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[18] origin:064-gtp-channel-conf 02_193 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[19] origin:064-gtp-channel-conf 03_193 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[20] origin:064-gtp-channel-conf 02_194 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[21] origin:064-gtp-channel-conf 03_194 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[22] origin:064-gtp-channel-conf 02_195 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[23] origin:064-gtp-channel-conf 03_195 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[24] origin:064-gtp-channel-conf 02_196 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[25] origin:064-gtp-channel-conf 03_196 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[26] origin:064-gtp-channel-conf 02_197 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[27] origin:064-gtp-channel-conf 03_197 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[28] origin:064-gtp-channel-conf 02_198 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[29] origin:064-gtp-channel-conf 03_198 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[30] origin:064-gtp-channel-conf 02_199 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[31] origin:064-gtp-channel-conf 03_199 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[32] origin:064-gtp-channel-conf 02_200 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[33] origin:064-gtp-channel-conf 03_200 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[34] origin:064-gtp-channel-conf 02_201 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[35] origin:064-gtp-channel-conf 03_201 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[36] origin:064-gtp-channel-conf 02_202 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[37] origin:064-gtp-channel-conf 03_202 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[38] origin:064-gtp-channel-conf 02_203 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[39] origin:064-gtp-channel-conf 03_203 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[40] origin:064-gtp-channel-conf 02_204 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[41] origin:064-gtp-channel-conf 03_204 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[42] origin:064-gtp-channel-conf 02_205 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[43] origin:064-gtp-channel-conf 03_205 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[44] origin:064-gtp-channel-conf 02_206 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[45] origin:064-gtp-channel-conf 03_206 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[46] origin:064-gtp-channel-conf 02_207 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[47] origin:064-gtp-channel-conf 03_207 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[0] origin:064-gtp-channel-conf 01_216 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[1] origin:064-gtp-channel-conf 00_217 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[2] origin:064-gtp-channel-conf 01_217 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[3] origin:064-gtp-channel-conf 00_218 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[4] origin:064-gtp-channel-conf 01_218 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[5] origin:064-gtp-channel-conf 00_219 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[6] origin:064-gtp-channel-conf 01_219 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[7] origin:064-gtp-channel-conf 00_220 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[8] origin:064-gtp-channel-conf 01_220 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[9] origin:064-gtp-channel-conf 00_221 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[10] origin:064-gtp-channel-conf 01_221 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[11] origin:064-gtp-channel-conf 00_222 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[0] origin:064-gtp-channel-conf 00_208 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[1] origin:064-gtp-channel-conf 01_208 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[2] origin:064-gtp-channel-conf 00_209 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[3] origin:064-gtp-channel-conf 01_209 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[4] origin:064-gtp-channel-conf 00_210 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[5] origin:064-gtp-channel-conf 01_210 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[6] origin:064-gtp-channel-conf 00_211 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[7] origin:064-gtp-channel-conf 01_211 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[0] origin:064-gtp-channel-conf 00_212 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[1] origin:064-gtp-channel-conf 01_212 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[2] origin:064-gtp-channel-conf 00_213 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[3] origin:064-gtp-channel-conf 01_213 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[4] origin:064-gtp-channel-conf 00_214 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[5] origin:064-gtp-channel-conf 01_214 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[6] origin:064-gtp-channel-conf 00_215 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[7] origin:064-gtp-channel-conf 01_215 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PMA_LOOPBACK_CFG[0] origin:064-gtp-channel-conf 01_207 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[0] origin:064-gtp-channel-conf 02_520 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[1] origin:064-gtp-channel-conf 03_520 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[2] origin:064-gtp-channel-conf 02_521 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[3] origin:064-gtp-channel-conf 03_521 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[4] origin:064-gtp-channel-conf 02_522 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[5] origin:064-gtp-channel-conf 03_522 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[6] origin:064-gtp-channel-conf 02_523 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[7] origin:064-gtp-channel-conf 03_523 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[8] origin:064-gtp-channel-conf 02_524 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[9] origin:064-gtp-channel-conf 03_524 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[10] origin:064-gtp-channel-conf 02_525 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[11] origin:064-gtp-channel-conf 03_525 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[12] origin:064-gtp-channel-conf 02_526 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[13] origin:064-gtp-channel-conf 03_526 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[14] origin:064-gtp-channel-conf 02_527 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[15] origin:064-gtp-channel-conf 03_527 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[16] origin:064-gtp-channel-conf 02_528 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[17] origin:064-gtp-channel-conf 03_528 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[18] origin:064-gtp-channel-conf 02_529 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[19] origin:064-gtp-channel-conf 03_529 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[20] origin:064-gtp-channel-conf 02_530 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[21] origin:064-gtp-channel-conf 03_530 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[22] origin:064-gtp-channel-conf 02_531 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[23] origin:064-gtp-channel-conf 03_531 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[24] origin:064-gtp-channel-conf 02_532 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[25] origin:064-gtp-channel-conf 03_532 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[26] origin:064-gtp-channel-conf 02_533 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[27] origin:064-gtp-channel-conf 03_533 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[28] origin:064-gtp-channel-conf 02_534 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[29] origin:064-gtp-channel-conf 03_534 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[30] origin:064-gtp-channel-conf 02_535 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[31] origin:064-gtp-channel-conf 03_535 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[0] origin:064-gtp-channel-conf 02_336 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[1] origin:064-gtp-channel-conf 03_336 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[2] origin:064-gtp-channel-conf 02_337 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[3] origin:064-gtp-channel-conf 03_337 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[4] origin:064-gtp-channel-conf 02_338 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[5] origin:064-gtp-channel-conf 03_338 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[6] origin:064-gtp-channel-conf 02_339 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[7] origin:064-gtp-channel-conf 03_339 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[8] origin:064-gtp-channel-conf 02_340 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[9] origin:064-gtp-channel-conf 03_340 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[10] origin:064-gtp-channel-conf 02_341 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[11] origin:064-gtp-channel-conf 03_341 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[12] origin:064-gtp-channel-conf 02_342 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[13] origin:064-gtp-channel-conf 03_342 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[14] origin:064-gtp-channel-conf 02_343 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[15] origin:064-gtp-channel-conf 03_343 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[16] origin:064-gtp-channel-conf 02_344 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[17] origin:064-gtp-channel-conf 03_344 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[18] origin:064-gtp-channel-conf 02_345 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[19] origin:064-gtp-channel-conf 03_345 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[20] origin:064-gtp-channel-conf 02_346 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[21] origin:064-gtp-channel-conf 03_346 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[22] origin:064-gtp-channel-conf 02_347 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[23] origin:064-gtp-channel-conf 03_347 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[24] origin:064-gtp-channel-conf 02_348 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[25] origin:064-gtp-channel-conf 03_348 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[26] origin:064-gtp-channel-conf 02_349 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[27] origin:064-gtp-channel-conf 03_349 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[28] origin:064-gtp-channel-conf 02_350 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[29] origin:064-gtp-channel-conf 03_350 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[30] origin:064-gtp-channel-conf 02_351 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[31] origin:064-gtp-channel-conf 03_351 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PMA_RSV3[0] origin:064-gtp-channel-conf 02_288 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PMA_RSV3[1] origin:064-gtp-channel-conf 03_288 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PMA_RSV4[0] origin:064-gtp-channel-conf 02_156 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PMA_RSV4[1] origin:064-gtp-channel-conf 03_156 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PMA_RSV4[2] origin:064-gtp-channel-conf 02_157 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PMA_RSV4[3] origin:064-gtp-channel-conf 03_157 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PMA_RSV5[0] origin:064-gtp-channel-conf 03_159 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PMA_RSV6[0] origin:064-gtp-channel-conf 02_303 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.PMA_RSV7[0] origin:064-gtp-channel-conf 03_303 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_BIAS_CFG[0] origin:064-gtp-channel-conf 02_112 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_BIAS_CFG[1] origin:064-gtp-channel-conf 03_112 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_BIAS_CFG[2] origin:064-gtp-channel-conf 02_113 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_BIAS_CFG[3] origin:064-gtp-channel-conf 03_113 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_BIAS_CFG[4] origin:064-gtp-channel-conf 02_114 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_BIAS_CFG[5] origin:064-gtp-channel-conf 03_114 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_BIAS_CFG[6] origin:064-gtp-channel-conf 02_115 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_BIAS_CFG[7] origin:064-gtp-channel-conf 03_115 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_BIAS_CFG[8] origin:064-gtp-channel-conf 02_116 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_BIAS_CFG[9] origin:064-gtp-channel-conf 03_116 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_BIAS_CFG[10] origin:064-gtp-channel-conf 02_117 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_BIAS_CFG[11] origin:064-gtp-channel-conf 03_117 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_BIAS_CFG[12] origin:064-gtp-channel-conf 02_118 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_BIAS_CFG[13] origin:064-gtp-channel-conf 03_118 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_BIAS_CFG[14] origin:064-gtp-channel-conf 02_119 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_BIAS_CFG[15] origin:064-gtp-channel-conf 03_119 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_BUFFER_CFG[0] origin:064-gtp-channel-conf 02_536 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_BUFFER_CFG[1] origin:064-gtp-channel-conf 03_536 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_BUFFER_CFG[2] origin:064-gtp-channel-conf 02_537 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_BUFFER_CFG[3] origin:064-gtp-channel-conf 03_537 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_BUFFER_CFG[4] origin:064-gtp-channel-conf 02_538 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_BUFFER_CFG[5] origin:064-gtp-channel-conf 03_538 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_CLKMUX_EN[0] origin:064-gtp-channel-conf 02_128 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_CM_SEL[0] origin:064-gtp-channel-conf 00_138 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_CM_SEL[1] origin:064-gtp-channel-conf 01_138 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_CM_TRIM[0] origin:064-gtp-channel-conf 02_304 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_CM_TRIM[1] origin:064-gtp-channel-conf 03_304 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_CM_TRIM[2] origin:064-gtp-channel-conf 02_305 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_CM_TRIM[3] origin:064-gtp-channel-conf 03_305 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_DATA_WIDTH[0] origin:064-gtp-channel-conf 01_141 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_DATA_WIDTH[1] origin:064-gtp-channel-conf 00_142 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_DATA_WIDTH[2] origin:064-gtp-channel-conf 01_142 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_DDI_SEL[0] origin:064-gtp-channel-conf 00_696 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_DDI_SEL[1] origin:064-gtp-channel-conf 01_696 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_DDI_SEL[2] origin:064-gtp-channel-conf 00_697 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_DDI_SEL[3] origin:064-gtp-channel-conf 01_697 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_DDI_SEL[4] origin:064-gtp-channel-conf 00_698 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_DDI_SEL[5] origin:064-gtp-channel-conf 01_698 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_DEBUG_CFG[0] origin:064-gtp-channel-conf 02_616 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_DEBUG_CFG[1] origin:064-gtp-channel-conf 03_616 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_DEBUG_CFG[2] origin:064-gtp-channel-conf 02_617 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_DEBUG_CFG[3] origin:064-gtp-channel-conf 03_617 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_DEBUG_CFG[4] origin:064-gtp-channel-conf 02_618 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_DEBUG_CFG[5] origin:064-gtp-channel-conf 03_618 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_DEBUG_CFG[6] origin:064-gtp-channel-conf 02_619 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_DEBUG_CFG[7] origin:064-gtp-channel-conf 03_619 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_DEBUG_CFG[8] origin:064-gtp-channel-conf 02_620 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_DEBUG_CFG[9] origin:064-gtp-channel-conf 03_620 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_DEBUG_CFG[10] origin:064-gtp-channel-conf 02_621 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_DEBUG_CFG[11] origin:064-gtp-channel-conf 03_621 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_DEBUG_CFG[12] origin:064-gtp-channel-conf 02_622 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_DEBUG_CFG[13] origin:064-gtp-channel-conf 03_622 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_DEFER_RESET_BUF_EN origin:064-gtp-channel-conf 02_552 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_DISPERR_SEQ_MATCH origin:064-gtp-channel-conf 01_495 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_OS_CFG[0] origin:064-gtp-channel-conf 00_288 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_OS_CFG[1] origin:064-gtp-channel-conf 01_288 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_OS_CFG[2] origin:064-gtp-channel-conf 00_289 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_OS_CFG[3] origin:064-gtp-channel-conf 01_289 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_OS_CFG[4] origin:064-gtp-channel-conf 00_290 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_OS_CFG[5] origin:064-gtp-channel-conf 01_290 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_OS_CFG[6] origin:064-gtp-channel-conf 00_291 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_OS_CFG[7] origin:064-gtp-channel-conf 01_291 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_OS_CFG[8] origin:064-gtp-channel-conf 00_292 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_OS_CFG[9] origin:064-gtp-channel-conf 01_292 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_OS_CFG[10] origin:064-gtp-channel-conf 00_293 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_OS_CFG[11] origin:064-gtp-channel-conf 01_293 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_OS_CFG[12] origin:064-gtp-channel-conf 00_294 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_SIG_VALID_DLY[0] origin:064-gtp-channel-conf 00_524 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_SIG_VALID_DLY[1] origin:064-gtp-channel-conf 01_524 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_SIG_VALID_DLY[2] origin:064-gtp-channel-conf 00_525 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_SIG_VALID_DLY[3] origin:064-gtp-channel-conf 01_525 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_SIG_VALID_DLY[4] origin:064-gtp-channel-conf 00_526 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_XCLK_SEL.RXUSR origin:064-gtp-channel-conf 00_143 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_CLK25_DIV[0] origin:064-gtp-channel-conf 00_139 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_CLK25_DIV[1] origin:064-gtp-channel-conf 01_139 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_CLK25_DIV[2] origin:064-gtp-channel-conf 00_140 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_CLK25_DIV[3] origin:064-gtp-channel-conf 01_140 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RX_CLK25_DIV[4] origin:064-gtp-channel-conf 00_141 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXBUF_ADDR_MODE.FAST origin:064-gtp-channel-conf 03_555 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXBUF_EIDLE_HI_CNT[0] origin:064-gtp-channel-conf 02_558 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXBUF_EIDLE_HI_CNT[1] origin:064-gtp-channel-conf 03_558 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXBUF_EIDLE_HI_CNT[2] origin:064-gtp-channel-conf 02_559 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXBUF_EIDLE_HI_CNT[3] origin:064-gtp-channel-conf 03_559 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXBUF_EIDLE_LO_CNT[0] origin:064-gtp-channel-conf 02_556 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXBUF_EIDLE_LO_CNT[1] origin:064-gtp-channel-conf 03_556 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXBUF_EIDLE_LO_CNT[2] origin:064-gtp-channel-conf 02_557 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXBUF_EIDLE_LO_CNT[3] origin:064-gtp-channel-conf 03_557 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXBUF_EN origin:064-gtp-channel-conf 02_11 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXBUF_RESET_ON_CB_CHANGE origin:064-gtp-channel-conf 02_560 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXBUF_RESET_ON_COMMAALIGN origin:064-gtp-channel-conf 02_561 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXBUF_RESET_ON_EIDLE origin:064-gtp-channel-conf 02_547 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXBUF_RESET_ON_RATE_CHANGE origin:064-gtp-channel-conf 03_560 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXBUF_THRESH_OVFLW[0] origin:064-gtp-channel-conf 03_552 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXBUF_THRESH_OVFLW[1] origin:064-gtp-channel-conf 02_553 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXBUF_THRESH_OVFLW[2] origin:064-gtp-channel-conf 03_553 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXBUF_THRESH_OVFLW[3] origin:064-gtp-channel-conf 02_554 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXBUF_THRESH_OVFLW[4] origin:064-gtp-channel-conf 03_554 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXBUF_THRESH_OVFLW[5] origin:064-gtp-channel-conf 02_555 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXBUF_THRESH_OVRD origin:064-gtp-channel-conf 02_548 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXBUF_THRESH_UNDFLW[0] origin:064-gtp-channel-conf 02_544 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXBUF_THRESH_UNDFLW[1] origin:064-gtp-channel-conf 03_544 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXBUF_THRESH_UNDFLW[2] origin:064-gtp-channel-conf 02_545 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXBUF_THRESH_UNDFLW[3] origin:064-gtp-channel-conf 03_545 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXBUF_THRESH_UNDFLW[4] origin:064-gtp-channel-conf 02_546 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXBUF_THRESH_UNDFLW[5] origin:064-gtp-channel-conf 03_546 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXBUFRESET_TIME[0] origin:064-gtp-channel-conf 01_101 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXBUFRESET_TIME[1] origin:064-gtp-channel-conf 00_102 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXBUFRESET_TIME[2] origin:064-gtp-channel-conf 01_102 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXBUFRESET_TIME[3] origin:064-gtp-channel-conf 00_103 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXBUFRESET_TIME[4] origin:064-gtp-channel-conf 01_103 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[0] origin:064-gtp-channel-conf 02_640 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[1] origin:064-gtp-channel-conf 03_640 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[2] origin:064-gtp-channel-conf 02_641 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[3] origin:064-gtp-channel-conf 03_641 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[4] origin:064-gtp-channel-conf 02_642 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[5] origin:064-gtp-channel-conf 03_642 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[6] origin:064-gtp-channel-conf 02_643 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[7] origin:064-gtp-channel-conf 03_643 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[8] origin:064-gtp-channel-conf 02_644 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[9] origin:064-gtp-channel-conf 03_644 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[10] origin:064-gtp-channel-conf 02_645 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[11] origin:064-gtp-channel-conf 03_645 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[12] origin:064-gtp-channel-conf 02_646 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[13] origin:064-gtp-channel-conf 03_646 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[14] origin:064-gtp-channel-conf 02_647 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[15] origin:064-gtp-channel-conf 03_647 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[16] origin:064-gtp-channel-conf 02_648 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[17] origin:064-gtp-channel-conf 03_648 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[18] origin:064-gtp-channel-conf 02_649 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[19] origin:064-gtp-channel-conf 03_649 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[20] origin:064-gtp-channel-conf 02_650 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[21] origin:064-gtp-channel-conf 03_650 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[22] origin:064-gtp-channel-conf 02_651 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[23] origin:064-gtp-channel-conf 03_651 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[24] origin:064-gtp-channel-conf 02_652 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[25] origin:064-gtp-channel-conf 03_652 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[26] origin:064-gtp-channel-conf 02_653 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[27] origin:064-gtp-channel-conf 03_653 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[28] origin:064-gtp-channel-conf 02_654 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[29] origin:064-gtp-channel-conf 03_654 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[30] origin:064-gtp-channel-conf 02_655 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[31] origin:064-gtp-channel-conf 03_655 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[32] origin:064-gtp-channel-conf 02_656 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[33] origin:064-gtp-channel-conf 03_656 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[34] origin:064-gtp-channel-conf 02_657 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[35] origin:064-gtp-channel-conf 03_657 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[36] origin:064-gtp-channel-conf 02_658 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[37] origin:064-gtp-channel-conf 03_658 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[38] origin:064-gtp-channel-conf 02_659 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[39] origin:064-gtp-channel-conf 03_659 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[40] origin:064-gtp-channel-conf 02_660 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[41] origin:064-gtp-channel-conf 03_660 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[42] origin:064-gtp-channel-conf 02_661 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[43] origin:064-gtp-channel-conf 03_661 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[44] origin:064-gtp-channel-conf 02_662 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[45] origin:064-gtp-channel-conf 03_662 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[46] origin:064-gtp-channel-conf 02_663 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[47] origin:064-gtp-channel-conf 03_663 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[48] origin:064-gtp-channel-conf 02_664 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[49] origin:064-gtp-channel-conf 03_664 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[50] origin:064-gtp-channel-conf 02_665 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[51] origin:064-gtp-channel-conf 03_665 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[52] origin:064-gtp-channel-conf 02_666 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[53] origin:064-gtp-channel-conf 03_666 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[54] origin:064-gtp-channel-conf 02_667 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[55] origin:064-gtp-channel-conf 03_667 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[56] origin:064-gtp-channel-conf 02_668 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[57] origin:064-gtp-channel-conf 03_668 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[58] origin:064-gtp-channel-conf 02_669 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[59] origin:064-gtp-channel-conf 03_669 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[60] origin:064-gtp-channel-conf 02_670 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[61] origin:064-gtp-channel-conf 03_670 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[62] origin:064-gtp-channel-conf 02_671 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[63] origin:064-gtp-channel-conf 03_671 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[64] origin:064-gtp-channel-conf 02_672 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[65] origin:064-gtp-channel-conf 03_672 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[66] origin:064-gtp-channel-conf 02_673 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[67] origin:064-gtp-channel-conf 03_673 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[68] origin:064-gtp-channel-conf 02_674 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[69] origin:064-gtp-channel-conf 03_674 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[70] origin:064-gtp-channel-conf 02_675 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[71] origin:064-gtp-channel-conf 03_675 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[72] origin:064-gtp-channel-conf 02_676 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[73] origin:064-gtp-channel-conf 03_676 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[74] origin:064-gtp-channel-conf 02_677 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[75] origin:064-gtp-channel-conf 03_677 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[76] origin:064-gtp-channel-conf 02_678 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[77] origin:064-gtp-channel-conf 03_678 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[78] origin:064-gtp-channel-conf 02_679 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[79] origin:064-gtp-channel-conf 03_679 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[80] origin:064-gtp-channel-conf 02_680 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[81] origin:064-gtp-channel-conf 03_680 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[82] origin:064-gtp-channel-conf 02_681 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_FR_RESET_ON_EIDLE[0] origin:064-gtp-channel-conf 02_638 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_HOLD_DURING_EIDLE[0] origin:064-gtp-channel-conf 03_637 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_LOCK_CFG[0] origin:064-gtp-channel-conf 02_632 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_LOCK_CFG[1] origin:064-gtp-channel-conf 03_632 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_LOCK_CFG[2] origin:064-gtp-channel-conf 02_633 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_LOCK_CFG[3] origin:064-gtp-channel-conf 03_633 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_LOCK_CFG[4] origin:064-gtp-channel-conf 02_634 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_LOCK_CFG[5] origin:064-gtp-channel-conf 03_634 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDR_PH_RESET_ON_EIDLE[0] origin:064-gtp-channel-conf 03_638 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDRFREQRESET_TIME[0] origin:064-gtp-channel-conf 01_106 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDRFREQRESET_TIME[1] origin:064-gtp-channel-conf 00_107 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDRFREQRESET_TIME[2] origin:064-gtp-channel-conf 01_107 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDRFREQRESET_TIME[3] origin:064-gtp-channel-conf 00_108 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDRFREQRESET_TIME[4] origin:064-gtp-channel-conf 01_108 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDRPHRESET_TIME[0] origin:064-gtp-channel-conf 00_109 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDRPHRESET_TIME[1] origin:064-gtp-channel-conf 01_109 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDRPHRESET_TIME[2] origin:064-gtp-channel-conf 00_110 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDRPHRESET_TIME[3] origin:064-gtp-channel-conf 01_110 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXCDRPHRESET_TIME[4] origin:064-gtp-channel-conf 00_111 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXDLY_CFG[0] origin:064-gtp-channel-conf 00_680 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXDLY_CFG[1] origin:064-gtp-channel-conf 01_680 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXDLY_CFG[2] origin:064-gtp-channel-conf 00_681 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXDLY_CFG[3] origin:064-gtp-channel-conf 01_681 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXDLY_CFG[4] origin:064-gtp-channel-conf 00_682 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXDLY_CFG[5] origin:064-gtp-channel-conf 01_682 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXDLY_CFG[6] origin:064-gtp-channel-conf 00_683 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXDLY_CFG[7] origin:064-gtp-channel-conf 01_683 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXDLY_CFG[8] origin:064-gtp-channel-conf 00_684 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXDLY_CFG[9] origin:064-gtp-channel-conf 01_684 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXDLY_CFG[10] origin:064-gtp-channel-conf 00_685 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXDLY_CFG[11] origin:064-gtp-channel-conf 01_685 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXDLY_CFG[12] origin:064-gtp-channel-conf 00_686 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXDLY_CFG[13] origin:064-gtp-channel-conf 01_686 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXDLY_CFG[14] origin:064-gtp-channel-conf 00_687 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXDLY_CFG[15] origin:064-gtp-channel-conf 01_687 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXDLY_LCFG[0] origin:064-gtp-channel-conf 02_576 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXDLY_LCFG[1] origin:064-gtp-channel-conf 03_576 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXDLY_LCFG[2] origin:064-gtp-channel-conf 02_577 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXDLY_LCFG[3] origin:064-gtp-channel-conf 03_577 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXDLY_LCFG[4] origin:064-gtp-channel-conf 02_578 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXDLY_LCFG[5] origin:064-gtp-channel-conf 03_578 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXDLY_LCFG[6] origin:064-gtp-channel-conf 02_579 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXDLY_LCFG[7] origin:064-gtp-channel-conf 03_579 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXDLY_LCFG[8] origin:064-gtp-channel-conf 02_580 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXDLY_TAP_CFG[0] origin:064-gtp-channel-conf 00_672 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXDLY_TAP_CFG[1] origin:064-gtp-channel-conf 01_672 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXDLY_TAP_CFG[2] origin:064-gtp-channel-conf 00_673 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXDLY_TAP_CFG[3] origin:064-gtp-channel-conf 01_673 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXDLY_TAP_CFG[4] origin:064-gtp-channel-conf 00_674 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXDLY_TAP_CFG[5] origin:064-gtp-channel-conf 01_674 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXDLY_TAP_CFG[6] origin:064-gtp-channel-conf 00_675 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXDLY_TAP_CFG[7] origin:064-gtp-channel-conf 01_675 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXDLY_TAP_CFG[8] origin:064-gtp-channel-conf 00_676 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXDLY_TAP_CFG[9] origin:064-gtp-channel-conf 01_676 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXDLY_TAP_CFG[10] origin:064-gtp-channel-conf 00_677 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXDLY_TAP_CFG[11] origin:064-gtp-channel-conf 01_677 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXDLY_TAP_CFG[12] origin:064-gtp-channel-conf 00_678 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXDLY_TAP_CFG[13] origin:064-gtp-channel-conf 01_678 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXDLY_TAP_CFG[14] origin:064-gtp-channel-conf 00_679 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXDLY_TAP_CFG[15] origin:064-gtp-channel-conf 01_679 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXGEARBOX_EN origin:064-gtp-channel-conf 01_607 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXISCANRESET_TIME[0] origin:064-gtp-channel-conf 01_123 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXISCANRESET_TIME[1] origin:064-gtp-channel-conf 00_124 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXISCANRESET_TIME[2] origin:064-gtp-channel-conf 01_124 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXISCANRESET_TIME[3] origin:064-gtp-channel-conf 00_125 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXISCANRESET_TIME[4] origin:064-gtp-channel-conf 01_125 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPM_BIAS_STARTUP_DISABLE[0] origin:064-gtp-channel-conf 03_391 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPM_CFG[0] origin:064-gtp-channel-conf 02_328 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPM_CFG[1] origin:064-gtp-channel-conf 03_328 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPM_CFG[2] origin:064-gtp-channel-conf 02_329 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPM_CFG[3] origin:064-gtp-channel-conf 03_329 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPM_CM_CFG[0] origin:064-gtp-channel-conf 02_430 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPM_GC_CFG[0] origin:064-gtp-channel-conf 02_432 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPM_GC_CFG[1] origin:064-gtp-channel-conf 03_432 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPM_GC_CFG[2] origin:064-gtp-channel-conf 02_433 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPM_GC_CFG[3] origin:064-gtp-channel-conf 03_433 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPM_GC_CFG[4] origin:064-gtp-channel-conf 02_434 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPM_GC_CFG[5] origin:064-gtp-channel-conf 03_434 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPM_GC_CFG[6] origin:064-gtp-channel-conf 02_435 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPM_GC_CFG[7] origin:064-gtp-channel-conf 03_435 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPM_GC_CFG[8] origin:064-gtp-channel-conf 02_436 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPM_GC_CFG2[0] origin:064-gtp-channel-conf 03_442 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPM_GC_CFG2[1] origin:064-gtp-channel-conf 02_443 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPM_GC_CFG2[2] origin:064-gtp-channel-conf 03_443 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG[0] origin:064-gtp-channel-conf 00_336 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG[1] origin:064-gtp-channel-conf 01_336 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG[2] origin:064-gtp-channel-conf 00_337 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG[3] origin:064-gtp-channel-conf 01_337 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG[4] origin:064-gtp-channel-conf 00_338 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG[5] origin:064-gtp-channel-conf 01_338 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG[6] origin:064-gtp-channel-conf 00_339 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG[7] origin:064-gtp-channel-conf 01_339 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG[8] origin:064-gtp-channel-conf 00_340 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG[9] origin:064-gtp-channel-conf 01_340 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG[10] origin:064-gtp-channel-conf 00_341 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG[11] origin:064-gtp-channel-conf 01_341 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG[12] origin:064-gtp-channel-conf 00_342 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG[13] origin:064-gtp-channel-conf 01_342 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG2[0] origin:064-gtp-channel-conf 02_424 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG2[1] origin:064-gtp-channel-conf 03_424 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG2[2] origin:064-gtp-channel-conf 02_425 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG2[3] origin:064-gtp-channel-conf 03_425 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG2[4] origin:064-gtp-channel-conf 02_426 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG3[0] origin:064-gtp-channel-conf 03_389 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG3[1] origin:064-gtp-channel-conf 02_390 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG3[2] origin:064-gtp-channel-conf 03_390 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG3[3] origin:064-gtp-channel-conf 02_391 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPM_HOLD_DURING_EIDLE[0] origin:064-gtp-channel-conf 00_247 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPM_INCM_CFG[0] origin:064-gtp-channel-conf 02_439 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPM_IPCM_CFG[0] origin:064-gtp-channel-conf 03_439 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG[0] origin:064-gtp-channel-conf 00_344 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG[1] origin:064-gtp-channel-conf 01_344 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG[2] origin:064-gtp-channel-conf 00_345 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG[3] origin:064-gtp-channel-conf 01_345 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG[4] origin:064-gtp-channel-conf 00_346 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG[5] origin:064-gtp-channel-conf 01_346 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG[6] origin:064-gtp-channel-conf 00_347 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG[7] origin:064-gtp-channel-conf 01_347 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG[8] origin:064-gtp-channel-conf 00_348 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG[9] origin:064-gtp-channel-conf 01_348 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG[10] origin:064-gtp-channel-conf 00_349 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG[11] origin:064-gtp-channel-conf 01_349 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG[12] origin:064-gtp-channel-conf 00_350 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG[13] origin:064-gtp-channel-conf 01_350 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG[14] origin:064-gtp-channel-conf 00_351 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG[15] origin:064-gtp-channel-conf 01_351 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG[16] origin:064-gtp-channel-conf 00_343 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG[17] origin:064-gtp-channel-conf 01_343 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG2[0] origin:064-gtp-channel-conf 03_426 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG2[1] origin:064-gtp-channel-conf 02_427 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG2[2] origin:064-gtp-channel-conf 03_427 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG2[3] origin:064-gtp-channel-conf 02_428 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG2[4] origin:064-gtp-channel-conf 03_428 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPM_OSINT_CFG[0] origin:064-gtp-channel-conf 02_440 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPM_OSINT_CFG[1] origin:064-gtp-channel-conf 03_440 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPM_OSINT_CFG[2] origin:064-gtp-channel-conf 02_441 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPM_CFG1[0] origin:064-gtp-channel-conf 02_330 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPMRESET_TIME[0] origin:064-gtp-channel-conf 00_112 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPMRESET_TIME[1] origin:064-gtp-channel-conf 01_112 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPMRESET_TIME[2] origin:064-gtp-channel-conf 00_113 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPMRESET_TIME[3] origin:064-gtp-channel-conf 01_113 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPMRESET_TIME[4] origin:064-gtp-channel-conf 00_114 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPMRESET_TIME[5] origin:064-gtp-channel-conf 01_114 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXLPMRESET_TIME[6] origin:064-gtp-channel-conf 00_115 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXOOB_CFG[0] origin:064-gtp-channel-conf 00_144 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXOOB_CFG[1] origin:064-gtp-channel-conf 01_144 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXOOB_CFG[2] origin:064-gtp-channel-conf 00_145 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXOOB_CFG[3] origin:064-gtp-channel-conf 01_145 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXOOB_CFG[4] origin:064-gtp-channel-conf 00_146 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXOOB_CFG[5] origin:064-gtp-channel-conf 01_146 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXOOB_CFG[6] origin:064-gtp-channel-conf 00_147 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXOOB_CLK_CFG.FABRIC origin:064-gtp-channel-conf 03_129 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXOSCALRESET_TIME[0] origin:064-gtp-channel-conf 00_187 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXOSCALRESET_TIME[1] origin:064-gtp-channel-conf 01_187 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXOSCALRESET_TIME[2] origin:064-gtp-channel-conf 00_188 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXOSCALRESET_TIME[3] origin:064-gtp-channel-conf 01_188 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXOSCALRESET_TIME[4] origin:064-gtp-channel-conf 00_189 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXOSCALRESET_TIMEOUT[0] origin:064-gtp-channel-conf 01_189 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXOSCALRESET_TIMEOUT[1] origin:064-gtp-channel-conf 00_190 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXOSCALRESET_TIMEOUT[2] origin:064-gtp-channel-conf 01_190 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXOSCALRESET_TIMEOUT[3] origin:064-gtp-channel-conf 00_191 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXOSCALRESET_TIMEOUT[4] origin:064-gtp-channel-conf 01_191 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXOUT_DIV[0] origin:064-gtp-channel-conf 02_384 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXOUT_DIV[1] origin:064-gtp-channel-conf 03_384 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXPCSRESET_TIME[0] origin:064-gtp-channel-conf 01_115 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXPCSRESET_TIME[1] origin:064-gtp-channel-conf 00_116 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXPCSRESET_TIME[2] origin:064-gtp-channel-conf 01_116 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXPCSRESET_TIME[3] origin:064-gtp-channel-conf 00_117 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXPCSRESET_TIME[4] origin:064-gtp-channel-conf 01_117 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[0] origin:064-gtp-channel-conf 02_584 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[1] origin:064-gtp-channel-conf 03_584 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[2] origin:064-gtp-channel-conf 02_585 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[3] origin:064-gtp-channel-conf 03_585 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[4] origin:064-gtp-channel-conf 02_586 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[5] origin:064-gtp-channel-conf 03_586 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[6] origin:064-gtp-channel-conf 02_587 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[7] origin:064-gtp-channel-conf 03_587 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[8] origin:064-gtp-channel-conf 02_588 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[9] origin:064-gtp-channel-conf 03_588 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[10] origin:064-gtp-channel-conf 02_589 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[11] origin:064-gtp-channel-conf 03_589 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[12] origin:064-gtp-channel-conf 02_590 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[13] origin:064-gtp-channel-conf 03_590 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[14] origin:064-gtp-channel-conf 02_591 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[15] origin:064-gtp-channel-conf 03_591 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[16] origin:064-gtp-channel-conf 02_592 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[17] origin:064-gtp-channel-conf 03_592 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[18] origin:064-gtp-channel-conf 02_593 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[19] origin:064-gtp-channel-conf 03_593 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[20] origin:064-gtp-channel-conf 02_594 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[21] origin:064-gtp-channel-conf 03_594 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[22] origin:064-gtp-channel-conf 02_595 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[23] origin:064-gtp-channel-conf 03_595 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXPH_MONITOR_SEL[0] origin:064-gtp-channel-conf 00_700 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXPH_MONITOR_SEL[1] origin:064-gtp-channel-conf 01_700 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXPH_MONITOR_SEL[2] origin:064-gtp-channel-conf 00_701 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXPH_MONITOR_SEL[3] origin:064-gtp-channel-conf 01_701 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXPH_MONITOR_SEL[4] origin:064-gtp-channel-conf 00_702 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[0] origin:064-gtp-channel-conf 02_600 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[1] origin:064-gtp-channel-conf 03_600 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[2] origin:064-gtp-channel-conf 02_601 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[3] origin:064-gtp-channel-conf 03_601 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[4] origin:064-gtp-channel-conf 02_602 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[5] origin:064-gtp-channel-conf 03_602 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[6] origin:064-gtp-channel-conf 02_603 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[7] origin:064-gtp-channel-conf 03_603 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[8] origin:064-gtp-channel-conf 02_604 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[9] origin:064-gtp-channel-conf 03_604 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[10] origin:064-gtp-channel-conf 02_605 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[11] origin:064-gtp-channel-conf 03_605 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[12] origin:064-gtp-channel-conf 02_606 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[13] origin:064-gtp-channel-conf 03_606 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[14] origin:064-gtp-channel-conf 02_607 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[15] origin:064-gtp-channel-conf 03_607 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[16] origin:064-gtp-channel-conf 02_608 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[17] origin:064-gtp-channel-conf 03_608 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[18] origin:064-gtp-channel-conf 02_609 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[19] origin:064-gtp-channel-conf 03_609 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[20] origin:064-gtp-channel-conf 02_610 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[21] origin:064-gtp-channel-conf 03_610 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[22] origin:064-gtp-channel-conf 02_611 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[23] origin:064-gtp-channel-conf 03_611 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXPI_CFG0[0] origin:064-gtp-channel-conf 03_430 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXPI_CFG0[1] origin:064-gtp-channel-conf 02_431 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXPI_CFG0[2] origin:064-gtp-channel-conf 03_431 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXPI_CFG1[0] origin:064-gtp-channel-conf 02_442 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXPI_CFG2[0] origin:064-gtp-channel-conf 03_441 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXPMARESET_TIME[0] origin:064-gtp-channel-conf 00_104 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXPMARESET_TIME[1] origin:064-gtp-channel-conf 01_104 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXPMARESET_TIME[2] origin:064-gtp-channel-conf 00_105 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXPMARESET_TIME[3] origin:064-gtp-channel-conf 01_105 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXPMARESET_TIME[4] origin:064-gtp-channel-conf 00_106 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXPRBS_ERR_LOOPBACK[0] origin:064-gtp-channel-conf 00_136 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXSLIDE_AUTO_WAIT[0] origin:064-gtp-channel-conf 00_520 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXSLIDE_AUTO_WAIT[1] origin:064-gtp-channel-conf 01_520 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXSLIDE_AUTO_WAIT[2] origin:064-gtp-channel-conf 00_521 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXSLIDE_AUTO_WAIT[3] origin:064-gtp-channel-conf 01_521 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXSLIDE_MODE.AUTO origin:064-gtp-channel-conf !01_519 00_519 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXSLIDE_MODE.PCS origin:064-gtp-channel-conf !00_519 01_519 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXSLIDE_MODE.PMA origin:064-gtp-channel-conf 00_519 01_519 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXSYNC_MULTILANE[0] origin:064-gtp-channel-conf 00_133 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXSYNC_OVRD[0] origin:064-gtp-channel-conf 01_135 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.RXSYNC_SKIP_DA[0] origin:064-gtp-channel-conf 01_134 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.SAS_MAX_COM[0] origin:064-gtp-channel-conf 00_171 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.SAS_MAX_COM[1] origin:064-gtp-channel-conf 01_171 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.SAS_MAX_COM[2] origin:064-gtp-channel-conf 00_172 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.SAS_MAX_COM[3] origin:064-gtp-channel-conf 01_172 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.SAS_MAX_COM[4] origin:064-gtp-channel-conf 00_173 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.SAS_MAX_COM[5] origin:064-gtp-channel-conf 01_173 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.SAS_MAX_COM[6] origin:064-gtp-channel-conf 00_174 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.SAS_MIN_COM[0] origin:064-gtp-channel-conf 01_156 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.SAS_MIN_COM[1] origin:064-gtp-channel-conf 00_157 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.SAS_MIN_COM[2] origin:064-gtp-channel-conf 01_157 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.SAS_MIN_COM[3] origin:064-gtp-channel-conf 00_158 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.SAS_MIN_COM[4] origin:064-gtp-channel-conf 01_158 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.SAS_MIN_COM[5] origin:064-gtp-channel-conf 00_159 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.SATA_BURST_SEQ_LEN[0] origin:064-gtp-channel-conf 00_150 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.SATA_BURST_SEQ_LEN[1] origin:064-gtp-channel-conf 01_150 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.SATA_BURST_SEQ_LEN[2] origin:064-gtp-channel-conf 00_151 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.SATA_BURST_SEQ_LEN[3] origin:064-gtp-channel-conf 01_151 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.SATA_BURST_VAL[0] origin:064-gtp-channel-conf 01_147 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.SATA_BURST_VAL[1] origin:064-gtp-channel-conf 00_148 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.SATA_BURST_VAL[2] origin:064-gtp-channel-conf 01_148 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.SATA_EIDLE_VAL[0] origin:064-gtp-channel-conf 00_152 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.SATA_EIDLE_VAL[1] origin:064-gtp-channel-conf 01_152 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.SATA_EIDLE_VAL[2] origin:064-gtp-channel-conf 00_153 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.SATA_MAX_BURST[0] origin:064-gtp-channel-conf 00_168 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.SATA_MAX_BURST[1] origin:064-gtp-channel-conf 01_168 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.SATA_MAX_BURST[2] origin:064-gtp-channel-conf 00_169 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.SATA_MAX_BURST[3] origin:064-gtp-channel-conf 01_169 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.SATA_MAX_BURST[4] origin:064-gtp-channel-conf 00_170 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.SATA_MAX_BURST[5] origin:064-gtp-channel-conf 01_170 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.SATA_MAX_INIT[0] origin:064-gtp-channel-conf 00_176 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.SATA_MAX_INIT[1] origin:064-gtp-channel-conf 01_176 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.SATA_MAX_INIT[2] origin:064-gtp-channel-conf 00_177 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.SATA_MAX_INIT[3] origin:064-gtp-channel-conf 01_177 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.SATA_MAX_INIT[4] origin:064-gtp-channel-conf 00_178 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.SATA_MAX_INIT[5] origin:064-gtp-channel-conf 01_178 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.SATA_MAX_WAKE[0] origin:064-gtp-channel-conf 00_179 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.SATA_MAX_WAKE[1] origin:064-gtp-channel-conf 01_179 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.SATA_MAX_WAKE[2] origin:064-gtp-channel-conf 00_180 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.SATA_MAX_WAKE[3] origin:064-gtp-channel-conf 01_180 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.SATA_MAX_WAKE[4] origin:064-gtp-channel-conf 00_181 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.SATA_MAX_WAKE[5] origin:064-gtp-channel-conf 01_181 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.SATA_MIN_BURST[0] origin:064-gtp-channel-conf 01_153 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.SATA_MIN_BURST[1] origin:064-gtp-channel-conf 00_154 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.SATA_MIN_BURST[2] origin:064-gtp-channel-conf 01_154 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.SATA_MIN_BURST[3] origin:064-gtp-channel-conf 00_155 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.SATA_MIN_BURST[4] origin:064-gtp-channel-conf 01_155 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.SATA_MIN_BURST[5] origin:064-gtp-channel-conf 00_156 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.SATA_MIN_INIT[0] origin:064-gtp-channel-conf 00_160 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.SATA_MIN_INIT[1] origin:064-gtp-channel-conf 01_160 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.SATA_MIN_INIT[2] origin:064-gtp-channel-conf 00_161 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.SATA_MIN_INIT[3] origin:064-gtp-channel-conf 01_161 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.SATA_MIN_INIT[4] origin:064-gtp-channel-conf 00_162 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.SATA_MIN_INIT[5] origin:064-gtp-channel-conf 01_162 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.SATA_MIN_WAKE[0] origin:064-gtp-channel-conf 00_163 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.SATA_MIN_WAKE[1] origin:064-gtp-channel-conf 01_163 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.SATA_MIN_WAKE[2] origin:064-gtp-channel-conf 00_164 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.SATA_MIN_WAKE[3] origin:064-gtp-channel-conf 01_164 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.SATA_MIN_WAKE[4] origin:064-gtp-channel-conf 00_165 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.SATA_MIN_WAKE[5] origin:064-gtp-channel-conf 01_165 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.SATA_PLL_CFG.VCO_1500MHZ origin:064-gtp-channel-conf 02_55 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.SATA_PLL_CFG.VCO_750MHZ origin:064-gtp-channel-conf 03_55 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.SHOW_REALIGN_COMMA origin:064-gtp-channel-conf 01_522 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TERM_RCAL_CFG[0] origin:064-gtp-channel-conf 02_136 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TERM_RCAL_CFG[1] origin:064-gtp-channel-conf 03_136 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TERM_RCAL_CFG[2] origin:064-gtp-channel-conf 02_137 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TERM_RCAL_CFG[3] origin:064-gtp-channel-conf 03_137 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TERM_RCAL_CFG[4] origin:064-gtp-channel-conf 02_138 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TERM_RCAL_CFG[5] origin:064-gtp-channel-conf 03_138 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TERM_RCAL_CFG[6] origin:064-gtp-channel-conf 02_139 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TERM_RCAL_CFG[7] origin:064-gtp-channel-conf 03_139 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TERM_RCAL_CFG[8] origin:064-gtp-channel-conf 02_140 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TERM_RCAL_CFG[9] origin:064-gtp-channel-conf 03_140 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TERM_RCAL_CFG[10] origin:064-gtp-channel-conf 02_141 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TERM_RCAL_CFG[11] origin:064-gtp-channel-conf 03_141 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TERM_RCAL_CFG[12] origin:064-gtp-channel-conf 02_142 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TERM_RCAL_CFG[13] origin:064-gtp-channel-conf 03_142 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TERM_RCAL_CFG[14] origin:064-gtp-channel-conf 02_143 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TERM_RCAL_OVRD[0] origin:064-gtp-channel-conf 03_150 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TERM_RCAL_OVRD[1] origin:064-gtp-channel-conf 02_151 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TERM_RCAL_OVRD[2] origin:064-gtp-channel-conf 03_151 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TRANS_TIME_RATE[0] origin:064-gtp-channel-conf 00_192 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TRANS_TIME_RATE[1] origin:064-gtp-channel-conf 01_192 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TRANS_TIME_RATE[2] origin:064-gtp-channel-conf 00_193 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TRANS_TIME_RATE[3] origin:064-gtp-channel-conf 01_193 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TRANS_TIME_RATE[4] origin:064-gtp-channel-conf 00_194 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TRANS_TIME_RATE[5] origin:064-gtp-channel-conf 01_194 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TRANS_TIME_RATE[6] origin:064-gtp-channel-conf 00_195 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TRANS_TIME_RATE[7] origin:064-gtp-channel-conf 01_195 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TST_RSV[0] origin:064-gtp-channel-conf 02_504 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TST_RSV[1] origin:064-gtp-channel-conf 03_504 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TST_RSV[2] origin:064-gtp-channel-conf 02_505 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TST_RSV[3] origin:064-gtp-channel-conf 03_505 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TST_RSV[4] origin:064-gtp-channel-conf 02_506 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TST_RSV[5] origin:064-gtp-channel-conf 03_506 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TST_RSV[6] origin:064-gtp-channel-conf 02_507 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TST_RSV[7] origin:064-gtp-channel-conf 03_507 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TST_RSV[8] origin:064-gtp-channel-conf 02_508 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TST_RSV[9] origin:064-gtp-channel-conf 03_508 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TST_RSV[10] origin:064-gtp-channel-conf 02_509 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TST_RSV[11] origin:064-gtp-channel-conf 03_509 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TST_RSV[12] origin:064-gtp-channel-conf 02_510 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TST_RSV[13] origin:064-gtp-channel-conf 03_510 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TST_RSV[14] origin:064-gtp-channel-conf 02_511 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TST_RSV[15] origin:064-gtp-channel-conf 03_511 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TST_RSV[16] origin:064-gtp-channel-conf 02_512 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TST_RSV[17] origin:064-gtp-channel-conf 03_512 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TST_RSV[18] origin:064-gtp-channel-conf 02_513 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TST_RSV[19] origin:064-gtp-channel-conf 03_513 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TST_RSV[20] origin:064-gtp-channel-conf 02_514 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TST_RSV[21] origin:064-gtp-channel-conf 03_514 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TST_RSV[22] origin:064-gtp-channel-conf 02_515 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TST_RSV[23] origin:064-gtp-channel-conf 03_515 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TST_RSV[24] origin:064-gtp-channel-conf 02_516 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TST_RSV[25] origin:064-gtp-channel-conf 03_516 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TST_RSV[26] origin:064-gtp-channel-conf 02_517 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TST_RSV[27] origin:064-gtp-channel-conf 03_517 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TST_RSV[28] origin:064-gtp-channel-conf 02_518 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TST_RSV[29] origin:064-gtp-channel-conf 03_518 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TST_RSV[30] origin:064-gtp-channel-conf 02_519 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TST_RSV[31] origin:064-gtp-channel-conf 03_519 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_CLKMUX_EN[0] origin:064-gtp-channel-conf 03_128 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_DATA_WIDTH[0] origin:064-gtp-channel-conf 02_152 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_DATA_WIDTH[1] origin:064-gtp-channel-conf 03_152 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_DATA_WIDTH[2] origin:064-gtp-channel-conf 02_153 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_DRIVE_MODE.PIPE origin:064-gtp-channel-conf 00_200 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_EIDLE_ASSERT_DELAY[0] origin:064-gtp-channel-conf 00_203 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_EIDLE_ASSERT_DELAY[1] origin:064-gtp-channel-conf 01_203 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_EIDLE_ASSERT_DELAY[2] origin:064-gtp-channel-conf 00_204 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_EIDLE_DEASSERT_DELAY[0] origin:064-gtp-channel-conf 01_204 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_EIDLE_DEASSERT_DELAY[1] origin:064-gtp-channel-conf 00_205 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_EIDLE_DEASSERT_DELAY[2] origin:064-gtp-channel-conf 01_205 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_LOOPBACK_DRIVE_HIZ origin:064-gtp-channel-conf 01_202 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_MAINCURSOR_SEL[0] origin:064-gtp-channel-conf 03_289 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_0[0] origin:064-gtp-channel-conf 02_232 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_0[1] origin:064-gtp-channel-conf 03_232 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_0[2] origin:064-gtp-channel-conf 02_233 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_0[3] origin:064-gtp-channel-conf 03_233 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_0[4] origin:064-gtp-channel-conf 02_234 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_0[5] origin:064-gtp-channel-conf 03_234 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_0[6] origin:064-gtp-channel-conf 02_235 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_1[0] origin:064-gtp-channel-conf 02_236 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_1[1] origin:064-gtp-channel-conf 03_236 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_1[2] origin:064-gtp-channel-conf 02_237 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_1[3] origin:064-gtp-channel-conf 03_237 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_1[4] origin:064-gtp-channel-conf 02_238 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_1[5] origin:064-gtp-channel-conf 03_238 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_1[6] origin:064-gtp-channel-conf 02_239 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_2[0] origin:064-gtp-channel-conf 02_240 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_2[1] origin:064-gtp-channel-conf 03_240 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_2[2] origin:064-gtp-channel-conf 02_241 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_2[3] origin:064-gtp-channel-conf 03_241 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_2[4] origin:064-gtp-channel-conf 02_242 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_2[5] origin:064-gtp-channel-conf 03_242 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_2[6] origin:064-gtp-channel-conf 02_243 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_3[0] origin:064-gtp-channel-conf 02_244 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_3[1] origin:064-gtp-channel-conf 03_244 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_3[2] origin:064-gtp-channel-conf 02_245 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_3[3] origin:064-gtp-channel-conf 03_245 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_3[4] origin:064-gtp-channel-conf 02_246 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_3[5] origin:064-gtp-channel-conf 03_246 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_3[6] origin:064-gtp-channel-conf 02_247 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_4[0] origin:064-gtp-channel-conf 02_248 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_4[1] origin:064-gtp-channel-conf 03_248 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_4[2] origin:064-gtp-channel-conf 02_249 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_4[3] origin:064-gtp-channel-conf 03_249 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_4[4] origin:064-gtp-channel-conf 02_250 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_4[5] origin:064-gtp-channel-conf 03_250 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_4[6] origin:064-gtp-channel-conf 02_251 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_0[0] origin:064-gtp-channel-conf 02_252 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_0[1] origin:064-gtp-channel-conf 03_252 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_0[2] origin:064-gtp-channel-conf 02_253 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_0[3] origin:064-gtp-channel-conf 03_253 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_0[4] origin:064-gtp-channel-conf 02_254 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_0[5] origin:064-gtp-channel-conf 03_254 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_0[6] origin:064-gtp-channel-conf 02_255 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_1[0] origin:064-gtp-channel-conf 02_256 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_1[1] origin:064-gtp-channel-conf 03_256 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_1[2] origin:064-gtp-channel-conf 02_257 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_1[3] origin:064-gtp-channel-conf 03_257 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_1[4] origin:064-gtp-channel-conf 02_258 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_1[5] origin:064-gtp-channel-conf 03_258 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_1[6] origin:064-gtp-channel-conf 02_259 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_2[0] origin:064-gtp-channel-conf 02_260 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_2[1] origin:064-gtp-channel-conf 03_260 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_2[2] origin:064-gtp-channel-conf 02_261 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_2[3] origin:064-gtp-channel-conf 03_261 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_2[4] origin:064-gtp-channel-conf 02_262 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_2[5] origin:064-gtp-channel-conf 03_262 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_2[6] origin:064-gtp-channel-conf 02_263 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_3[0] origin:064-gtp-channel-conf 02_264 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_3[1] origin:064-gtp-channel-conf 03_264 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_3[2] origin:064-gtp-channel-conf 02_265 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_3[3] origin:064-gtp-channel-conf 03_265 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_3[4] origin:064-gtp-channel-conf 02_266 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_3[5] origin:064-gtp-channel-conf 03_266 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_3[6] origin:064-gtp-channel-conf 02_267 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_4[0] origin:064-gtp-channel-conf 02_268 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_4[1] origin:064-gtp-channel-conf 03_268 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_4[2] origin:064-gtp-channel-conf 02_269 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_4[3] origin:064-gtp-channel-conf 03_269 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_4[4] origin:064-gtp-channel-conf 02_270 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_4[5] origin:064-gtp-channel-conf 03_270 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_4[6] origin:064-gtp-channel-conf 02_271 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_PREDRIVER_MODE[0] origin:064-gtp-channel-conf 00_206 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_RXDETECT_CFG[0] origin:064-gtp-channel-conf 02_296 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_RXDETECT_CFG[1] origin:064-gtp-channel-conf 03_296 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_RXDETECT_CFG[2] origin:064-gtp-channel-conf 02_297 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_RXDETECT_CFG[3] origin:064-gtp-channel-conf 03_297 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_RXDETECT_CFG[4] origin:064-gtp-channel-conf 02_298 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_RXDETECT_CFG[5] origin:064-gtp-channel-conf 03_298 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_RXDETECT_CFG[6] origin:064-gtp-channel-conf 02_299 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_RXDETECT_CFG[7] origin:064-gtp-channel-conf 03_299 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_RXDETECT_CFG[8] origin:064-gtp-channel-conf 02_300 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_RXDETECT_CFG[9] origin:064-gtp-channel-conf 03_300 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_RXDETECT_CFG[10] origin:064-gtp-channel-conf 02_301 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_RXDETECT_CFG[11] origin:064-gtp-channel-conf 03_301 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_RXDETECT_CFG[12] origin:064-gtp-channel-conf 02_302 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_RXDETECT_CFG[13] origin:064-gtp-channel-conf 03_302 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_RXDETECT_REF[0] origin:064-gtp-channel-conf 02_292 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_RXDETECT_REF[1] origin:064-gtp-channel-conf 03_292 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_RXDETECT_REF[2] origin:064-gtp-channel-conf 02_293 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_XCLK_SEL.TXUSR origin:064-gtp-channel-conf 03_11 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_CLK25_DIV[0] origin:064-gtp-channel-conf 02_144 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_CLK25_DIV[1] origin:064-gtp-channel-conf 03_144 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_CLK25_DIV[2] origin:064-gtp-channel-conf 02_145 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_CLK25_DIV[3] origin:064-gtp-channel-conf 03_145 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_CLK25_DIV[4] origin:064-gtp-channel-conf 02_146 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_DEEMPH0[0] origin:064-gtp-channel-conf 02_272 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_DEEMPH0[1] origin:064-gtp-channel-conf 03_272 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_DEEMPH0[2] origin:064-gtp-channel-conf 02_273 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_DEEMPH0[3] origin:064-gtp-channel-conf 03_273 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_DEEMPH0[4] origin:064-gtp-channel-conf 02_274 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_DEEMPH0[5] origin:064-gtp-channel-conf 03_274 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_DEEMPH1[0] origin:064-gtp-channel-conf 02_276 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_DEEMPH1[1] origin:064-gtp-channel-conf 03_276 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_DEEMPH1[2] origin:064-gtp-channel-conf 02_277 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_DEEMPH1[3] origin:064-gtp-channel-conf 03_277 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_DEEMPH1[4] origin:064-gtp-channel-conf 02_278 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TX_DEEMPH1[5] origin:064-gtp-channel-conf 03_278 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXBUF_EN origin:064-gtp-channel-conf 00_231 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXBUF_RESET_ON_RATE_CHANGE origin:064-gtp-channel-conf 01_231 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXDLY_CFG[0] origin:064-gtp-channel-conf 02_80 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXDLY_CFG[1] origin:064-gtp-channel-conf 03_80 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXDLY_CFG[2] origin:064-gtp-channel-conf 02_81 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXDLY_CFG[3] origin:064-gtp-channel-conf 03_81 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXDLY_CFG[4] origin:064-gtp-channel-conf 02_82 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXDLY_CFG[5] origin:064-gtp-channel-conf 03_82 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXDLY_CFG[6] origin:064-gtp-channel-conf 02_83 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXDLY_CFG[7] origin:064-gtp-channel-conf 03_83 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXDLY_CFG[8] origin:064-gtp-channel-conf 02_84 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXDLY_CFG[9] origin:064-gtp-channel-conf 03_84 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXDLY_CFG[10] origin:064-gtp-channel-conf 02_85 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXDLY_CFG[11] origin:064-gtp-channel-conf 03_85 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXDLY_CFG[12] origin:064-gtp-channel-conf 02_86 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXDLY_CFG[13] origin:064-gtp-channel-conf 03_86 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXDLY_CFG[14] origin:064-gtp-channel-conf 02_87 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXDLY_CFG[15] origin:064-gtp-channel-conf 03_87 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXDLY_LCFG[0] origin:064-gtp-channel-conf 02_568 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXDLY_LCFG[1] origin:064-gtp-channel-conf 03_568 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXDLY_LCFG[2] origin:064-gtp-channel-conf 02_569 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXDLY_LCFG[3] origin:064-gtp-channel-conf 03_569 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXDLY_LCFG[4] origin:064-gtp-channel-conf 02_570 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXDLY_LCFG[5] origin:064-gtp-channel-conf 03_570 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXDLY_LCFG[6] origin:064-gtp-channel-conf 02_571 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXDLY_LCFG[7] origin:064-gtp-channel-conf 03_571 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXDLY_LCFG[8] origin:064-gtp-channel-conf 02_572 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXDLY_TAP_CFG[0] origin:064-gtp-channel-conf 02_88 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXDLY_TAP_CFG[1] origin:064-gtp-channel-conf 03_88 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXDLY_TAP_CFG[2] origin:064-gtp-channel-conf 02_89 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXDLY_TAP_CFG[3] origin:064-gtp-channel-conf 03_89 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXDLY_TAP_CFG[4] origin:064-gtp-channel-conf 02_90 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXDLY_TAP_CFG[5] origin:064-gtp-channel-conf 03_90 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXDLY_TAP_CFG[6] origin:064-gtp-channel-conf 02_91 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXDLY_TAP_CFG[7] origin:064-gtp-channel-conf 03_91 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXDLY_TAP_CFG[8] origin:064-gtp-channel-conf 02_92 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXDLY_TAP_CFG[9] origin:064-gtp-channel-conf 03_92 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXDLY_TAP_CFG[10] origin:064-gtp-channel-conf 02_93 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXDLY_TAP_CFG[11] origin:064-gtp-channel-conf 03_93 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXDLY_TAP_CFG[12] origin:064-gtp-channel-conf 02_94 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXDLY_TAP_CFG[13] origin:064-gtp-channel-conf 03_94 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXDLY_TAP_CFG[14] origin:064-gtp-channel-conf 02_95 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXDLY_TAP_CFG[15] origin:064-gtp-channel-conf 03_95 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXGEARBOX_EN origin:064-gtp-channel-conf 01_226 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXOOB_CFG[0] origin:064-gtp-channel-conf 03_20 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXOUT_DIV[0] origin:064-gtp-channel-conf 02_386 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXOUT_DIV[1] origin:064-gtp-channel-conf 03_386 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPCSRESET_TIME[0] origin:064-gtp-channel-conf 01_130 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPCSRESET_TIME[1] origin:064-gtp-channel-conf 00_131 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPCSRESET_TIME[2] origin:064-gtp-channel-conf 01_131 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPCSRESET_TIME[3] origin:064-gtp-channel-conf 00_132 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPCSRESET_TIME[4] origin:064-gtp-channel-conf 01_132 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPH_CFG[0] origin:064-gtp-channel-conf 02_96 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPH_CFG[1] origin:064-gtp-channel-conf 03_96 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPH_CFG[2] origin:064-gtp-channel-conf 02_97 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPH_CFG[3] origin:064-gtp-channel-conf 03_97 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPH_CFG[4] origin:064-gtp-channel-conf 02_98 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPH_CFG[5] origin:064-gtp-channel-conf 03_98 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPH_CFG[6] origin:064-gtp-channel-conf 02_99 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPH_CFG[7] origin:064-gtp-channel-conf 03_99 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPH_CFG[8] origin:064-gtp-channel-conf 02_100 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPH_CFG[9] origin:064-gtp-channel-conf 03_100 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPH_CFG[10] origin:064-gtp-channel-conf 02_101 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPH_CFG[11] origin:064-gtp-channel-conf 03_101 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPH_CFG[12] origin:064-gtp-channel-conf 02_102 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPH_CFG[13] origin:064-gtp-channel-conf 03_102 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPH_CFG[14] origin:064-gtp-channel-conf 02_103 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPH_CFG[15] origin:064-gtp-channel-conf 03_103 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPH_MONITOR_SEL[0] origin:064-gtp-channel-conf 02_108 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPH_MONITOR_SEL[1] origin:064-gtp-channel-conf 03_108 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPH_MONITOR_SEL[2] origin:064-gtp-channel-conf 02_109 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPH_MONITOR_SEL[3] origin:064-gtp-channel-conf 03_109 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPH_MONITOR_SEL[4] origin:064-gtp-channel-conf 02_110 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[0] origin:064-gtp-channel-conf 02_64 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[1] origin:064-gtp-channel-conf 03_64 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[2] origin:064-gtp-channel-conf 02_65 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[3] origin:064-gtp-channel-conf 03_65 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[4] origin:064-gtp-channel-conf 02_66 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[5] origin:064-gtp-channel-conf 03_66 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[6] origin:064-gtp-channel-conf 02_67 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[7] origin:064-gtp-channel-conf 03_67 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[8] origin:064-gtp-channel-conf 02_68 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[9] origin:064-gtp-channel-conf 03_68 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[10] origin:064-gtp-channel-conf 02_69 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[11] origin:064-gtp-channel-conf 03_69 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[12] origin:064-gtp-channel-conf 02_70 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[13] origin:064-gtp-channel-conf 03_70 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[14] origin:064-gtp-channel-conf 02_71 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[15] origin:064-gtp-channel-conf 03_71 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[16] origin:064-gtp-channel-conf 02_72 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[17] origin:064-gtp-channel-conf 03_72 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[18] origin:064-gtp-channel-conf 02_73 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[19] origin:064-gtp-channel-conf 03_73 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[20] origin:064-gtp-channel-conf 02_74 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[21] origin:064-gtp-channel-conf 03_74 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[22] origin:064-gtp-channel-conf 02_75 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[23] origin:064-gtp-channel-conf 03_75 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPI_GREY_SEL[0] origin:064-gtp-channel-conf 03_498 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPI_INVSTROBE_SEL[0] origin:064-gtp-channel-conf 02_498 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPI_PPM_CFG[0] origin:064-gtp-channel-conf 02_488 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPI_PPM_CFG[1] origin:064-gtp-channel-conf 03_488 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPI_PPM_CFG[2] origin:064-gtp-channel-conf 02_489 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPI_PPM_CFG[3] origin:064-gtp-channel-conf 03_489 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPI_PPM_CFG[4] origin:064-gtp-channel-conf 02_490 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPI_PPM_CFG[5] origin:064-gtp-channel-conf 03_490 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPI_PPM_CFG[6] origin:064-gtp-channel-conf 02_491 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPI_PPM_CFG[7] origin:064-gtp-channel-conf 03_491 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPI_PPMCLK_SEL.TXUSRCLK2 origin:064-gtp-channel-conf 03_497 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPI_SYNFREQ_PPM[0] origin:064-gtp-channel-conf 02_496 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPI_SYNFREQ_PPM[1] origin:064-gtp-channel-conf 03_496 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPI_SYNFREQ_PPM[2] origin:064-gtp-channel-conf 02_497 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPI_CFG0[0] origin:064-gtp-channel-conf 02_40 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPI_CFG0[1] origin:064-gtp-channel-conf 03_40 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPI_CFG1[0] origin:064-gtp-channel-conf 02_41 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPI_CFG1[1] origin:064-gtp-channel-conf 03_41 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPI_CFG2[0] origin:064-gtp-channel-conf 02_42 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPI_CFG2[1] origin:064-gtp-channel-conf 03_42 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPI_CFG3[0] origin:064-gtp-channel-conf 02_43 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPI_CFG4[0] origin:064-gtp-channel-conf 03_43 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPI_CFG5[0] origin:064-gtp-channel-conf 02_44 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPI_CFG5[1] origin:064-gtp-channel-conf 03_44 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPI_CFG5[2] origin:064-gtp-channel-conf 02_45 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPMARESET_TIME[0] origin:064-gtp-channel-conf 00_128 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPMARESET_TIME[1] origin:064-gtp-channel-conf 01_128 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPMARESET_TIME[2] origin:064-gtp-channel-conf 00_129 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPMARESET_TIME[3] origin:064-gtp-channel-conf 01_129 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXPMARESET_TIME[4] origin:064-gtp-channel-conf 00_130 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXSYNC_MULTILANE[0] origin:064-gtp-channel-conf 01_133 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXSYNC_OVRD[0] origin:064-gtp-channel-conf 00_135 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.TXSYNC_SKIP_DA[0] origin:064-gtp-channel-conf 00_134 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.UCODEER_CLR[0] origin:064-gtp-channel-conf 01_00 +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL.USE_PCS_CLK_PHASE_SEL[0] origin:064-gtp-channel-conf 02_463 diff --git a/artix7/segbits_gtp_channel_0_mid_right.db b/artix7/segbits_gtp_channel_0_mid_right.db index 506c21d..7914d85 100644 --- a/artix7/segbits_gtp_channel_0_mid_right.db +++ b/artix7/segbits_gtp_channel_0_mid_right.db @@ -1,1627 +1,1627 @@ -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ACJTAG_DEBUG_MODE[0] 00_07 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ACJTAG_MODE[0] 01_06 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ACJTAG_RESET[0] 01_07 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ADAPT_CFG0[0] 02_464 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ADAPT_CFG0[1] 03_464 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ADAPT_CFG0[2] 02_465 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ADAPT_CFG0[3] 03_465 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ADAPT_CFG0[4] 02_466 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ADAPT_CFG0[5] 03_466 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ADAPT_CFG0[6] 02_467 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ADAPT_CFG0[7] 03_467 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ADAPT_CFG0[8] 02_468 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ADAPT_CFG0[9] 03_468 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ADAPT_CFG0[10] 02_469 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ADAPT_CFG0[11] 03_469 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ADAPT_CFG0[12] 02_470 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ADAPT_CFG0[13] 03_470 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ADAPT_CFG0[14] 02_471 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ADAPT_CFG0[15] 03_471 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ADAPT_CFG0[16] 02_472 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ADAPT_CFG0[17] 03_472 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ADAPT_CFG0[18] 02_473 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ADAPT_CFG0[19] 03_473 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ALIGN_COMMA_DOUBLE 00_522 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ALIGN_COMMA_ENABLE[0] 00_496 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ALIGN_COMMA_ENABLE[1] 01_496 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ALIGN_COMMA_ENABLE[2] 00_497 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ALIGN_COMMA_ENABLE[3] 01_497 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ALIGN_COMMA_ENABLE[4] 00_498 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ALIGN_COMMA_ENABLE[5] 01_498 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ALIGN_COMMA_ENABLE[6] 00_499 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ALIGN_COMMA_ENABLE[7] 01_499 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ALIGN_COMMA_ENABLE[8] 00_500 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ALIGN_COMMA_ENABLE[9] 01_500 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ALIGN_COMMA_WORD[0] 01_526 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ALIGN_COMMA_WORD[1] 00_527 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ALIGN_MCOMMA_DET 00_523 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ALIGN_MCOMMA_VALUE[0] 00_504 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ALIGN_MCOMMA_VALUE[1] 01_504 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ALIGN_MCOMMA_VALUE[2] 00_505 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ALIGN_MCOMMA_VALUE[3] 01_505 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ALIGN_MCOMMA_VALUE[4] 00_506 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ALIGN_MCOMMA_VALUE[5] 01_506 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ALIGN_MCOMMA_VALUE[6] 00_507 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ALIGN_MCOMMA_VALUE[7] 01_507 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ALIGN_MCOMMA_VALUE[8] 00_508 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ALIGN_MCOMMA_VALUE[9] 01_508 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ALIGN_PCOMMA_DET 01_523 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ALIGN_PCOMMA_VALUE[0] 00_512 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ALIGN_PCOMMA_VALUE[1] 01_512 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ALIGN_PCOMMA_VALUE[2] 00_513 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ALIGN_PCOMMA_VALUE[3] 01_513 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ALIGN_PCOMMA_VALUE[4] 00_514 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ALIGN_PCOMMA_VALUE[5] 01_514 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ALIGN_PCOMMA_VALUE[6] 00_515 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ALIGN_PCOMMA_VALUE[7] 01_515 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ALIGN_PCOMMA_VALUE[8] 00_516 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ALIGN_PCOMMA_VALUE[9] 01_516 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CBCC_DATA_SOURCE_SEL.DECODED 01_661 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CFOK_CFG[0] 02_392 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CFOK_CFG[1] 03_392 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CFOK_CFG[2] 02_393 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CFOK_CFG[3] 03_393 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CFOK_CFG[4] 02_394 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CFOK_CFG[5] 03_394 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CFOK_CFG[6] 02_395 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CFOK_CFG[7] 03_395 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CFOK_CFG[8] 02_396 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CFOK_CFG[9] 03_396 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CFOK_CFG[10] 02_397 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CFOK_CFG[11] 03_397 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CFOK_CFG[12] 02_398 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CFOK_CFG[13] 03_398 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CFOK_CFG[14] 02_399 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CFOK_CFG[15] 03_399 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CFOK_CFG[16] 02_400 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CFOK_CFG[17] 03_400 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CFOK_CFG[18] 02_401 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CFOK_CFG[19] 03_401 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CFOK_CFG[20] 02_402 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CFOK_CFG[21] 03_402 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CFOK_CFG[22] 02_403 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CFOK_CFG[23] 03_403 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CFOK_CFG[24] 02_404 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CFOK_CFG[25] 03_404 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CFOK_CFG[26] 02_405 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CFOK_CFG[27] 03_405 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CFOK_CFG[28] 02_406 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CFOK_CFG[29] 03_406 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CFOK_CFG[30] 02_407 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CFOK_CFG[31] 03_407 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CFOK_CFG[32] 02_408 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CFOK_CFG[33] 03_408 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CFOK_CFG[34] 02_409 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CFOK_CFG[35] 03_409 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CFOK_CFG[36] 02_410 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CFOK_CFG[37] 03_410 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CFOK_CFG[38] 02_411 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CFOK_CFG[39] 03_411 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CFOK_CFG[40] 02_412 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CFOK_CFG[41] 03_412 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CFOK_CFG[42] 02_413 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CFOK_CFG2[0] 02_459 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CFOK_CFG2[1] 03_459 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CFOK_CFG2[2] 02_460 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CFOK_CFG2[3] 03_460 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CFOK_CFG2[4] 02_461 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CFOK_CFG2[5] 03_461 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CFOK_CFG2[6] 02_462 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CFOK_CFG3[0] 02_416 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CFOK_CFG3[1] 03_416 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CFOK_CFG3[2] 02_417 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CFOK_CFG3[3] 03_417 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CFOK_CFG3[4] 02_418 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CFOK_CFG3[5] 03_418 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CFOK_CFG3[6] 02_419 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CFOK_CFG4[0] 03_438 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CFOK_CFG5[0] 02_429 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CFOK_CFG5[1] 03_429 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CFOK_CFG6[0] 03_436 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CFOK_CFG6[1] 02_437 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CFOK_CFG6[2] 03_437 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CFOK_CFG6[3] 02_438 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_KEEP_ALIGN 01_631 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_MAX_SKEW[0] 00_670 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_MAX_SKEW[1] 01_670 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_MAX_SKEW[2] 00_671 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_MAX_SKEW[3] 01_671 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_1[0] 00_608 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_1[1] 01_608 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_1[2] 00_609 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_1[3] 01_609 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_1[4] 00_610 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_1[5] 01_610 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_1[6] 00_611 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_1[7] 01_611 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_1[8] 00_612 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_1[9] 01_612 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_2[0] 00_616 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_2[1] 01_616 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_2[2] 00_617 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_2[3] 01_617 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_2[4] 00_618 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_2[5] 01_618 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_2[6] 00_619 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_2[7] 01_619 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_2[8] 00_620 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_2[9] 01_620 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_3[0] 00_624 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_3[1] 01_624 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_3[2] 00_625 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_3[3] 01_625 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_3[4] 00_626 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_3[5] 01_626 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_3[6] 00_627 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_3[7] 01_627 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_3[8] 00_628 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_3[9] 01_628 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_4[0] 00_632 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_4[1] 01_632 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_4[2] 00_633 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_4[3] 01_633 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_4[4] 00_634 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_4[5] 01_634 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_4[6] 00_635 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_4[7] 01_635 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_4[8] 00_636 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_4[9] 01_636 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_ENABLE[0] 00_614 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_ENABLE[1] 01_614 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_ENABLE[2] 00_615 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_ENABLE[3] 01_615 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_1[0] 00_640 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_1[1] 01_640 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_1[2] 00_641 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_1[3] 01_641 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_1[4] 00_642 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_1[5] 01_642 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_1[6] 00_643 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_1[7] 01_643 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_1[8] 00_644 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_1[9] 01_644 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_2[0] 00_648 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_2[1] 01_648 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_2[2] 00_649 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_2[3] 01_649 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_2[4] 00_650 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_2[5] 01_650 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_2[6] 00_651 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_2[7] 01_651 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_2[8] 00_652 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_2[9] 01_652 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_3[0] 00_656 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_3[1] 01_656 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_3[2] 00_657 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_3[3] 01_657 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_3[4] 00_658 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_3[5] 01_658 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_3[6] 00_659 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_3[7] 01_659 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_3[8] 00_660 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_3[9] 01_660 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_4[0] 00_664 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_4[1] 01_664 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_4[2] 00_665 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_4[3] 01_665 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_4[4] 00_666 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_4[5] 01_666 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_4[6] 00_667 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_4[7] 01_667 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_4[8] 00_668 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_4[9] 01_668 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_ENABLE[0] 00_646 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_ENABLE[1] 01_646 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_ENABLE[2] 00_647 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_ENABLE[3] 01_647 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_USE 01_645 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_LEN[0] 00_623 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_LEN[1] 01_623 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COMMON_SWING[0] 03_311 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_KEEP_IDLE 00_591 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_MAX_LAT[0] 00_557 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_MAX_LAT[1] 01_557 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_MAX_LAT[2] 00_558 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_MAX_LAT[3] 01_558 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_MAX_LAT[4] 00_559 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_MAX_LAT[5] 01_559 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_MIN_LAT[0] 00_565 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_MIN_LAT[1] 01_565 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_MIN_LAT[2] 00_566 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_MIN_LAT[3] 01_566 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_MIN_LAT[4] 00_567 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_MIN_LAT[5] 01_567 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_PRECEDENCE 00_590 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_REPEAT_WAIT[0] 00_573 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_REPEAT_WAIT[1] 01_573 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_REPEAT_WAIT[2] 00_574 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_REPEAT_WAIT[3] 01_574 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_REPEAT_WAIT[4] 00_575 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_1[0] 00_544 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_1[1] 01_544 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_1[2] 00_545 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_1[3] 01_545 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_1[4] 00_546 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_1[5] 01_546 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_1[6] 00_547 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_1[7] 01_547 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_1[8] 00_548 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_1[9] 01_548 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_2[0] 00_552 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_2[1] 01_552 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_2[2] 00_553 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_2[3] 01_553 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_2[4] 00_554 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_2[5] 01_554 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_2[6] 00_555 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_2[7] 01_555 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_2[8] 00_556 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_2[9] 01_556 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_3[0] 00_560 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_3[1] 01_560 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_3[2] 00_561 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_3[3] 01_561 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_3[4] 00_562 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_3[5] 01_562 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_3[6] 00_563 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_3[7] 01_563 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_3[8] 00_564 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_3[9] 01_564 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_4[0] 00_568 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_4[1] 01_568 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_4[2] 00_569 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_4[3] 01_569 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_4[4] 00_570 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_4[5] 01_570 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_4[6] 00_571 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_4[7] 01_571 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_4[8] 00_572 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_4[9] 01_572 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_ENABLE[0] 00_549 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_ENABLE[1] 01_549 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_ENABLE[2] 00_550 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_ENABLE[3] 01_550 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_1[0] 00_576 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_1[1] 01_576 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_1[2] 00_577 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_1[3] 01_577 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_1[4] 00_578 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_1[5] 01_578 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_1[6] 00_579 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_1[7] 01_579 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_1[8] 00_580 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_1[9] 01_580 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_2[0] 00_584 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_2[1] 01_584 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_2[2] 00_585 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_2[3] 01_585 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_2[4] 00_586 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_2[5] 01_586 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_2[6] 00_587 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_2[7] 01_587 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_2[8] 00_588 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_2[9] 01_588 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_3[0] 00_592 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_3[1] 01_592 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_3[2] 00_593 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_3[3] 01_593 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_3[4] 00_594 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_3[5] 01_594 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_3[6] 00_595 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_3[7] 01_595 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_3[8] 00_596 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_3[9] 01_596 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_4[0] 00_600 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_4[1] 01_600 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_4[2] 00_601 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_4[3] 01_601 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_4[4] 00_602 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_4[5] 01_602 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_4[6] 00_603 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_4[7] 01_603 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_4[8] 00_604 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_4[9] 01_604 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_ENABLE[0] 00_581 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_ENABLE[1] 01_581 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_ENABLE[2] 00_582 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_ENABLE[3] 01_582 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_USE 00_583 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_LEN[0] 00_589 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_LEN[1] 01_589 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_CORRECT_USE 00_551 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.DEC_MCOMMA_DETECT 01_494 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.DEC_PCOMMA_DETECT 00_495 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.DEC_VALID_COMMA_ONLY 00_494 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.DMONITOR_CFG[0] 02_368 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.DMONITOR_CFG[1] 03_368 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.DMONITOR_CFG[2] 02_369 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.DMONITOR_CFG[3] 03_369 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.DMONITOR_CFG[4] 02_370 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.DMONITOR_CFG[5] 03_370 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.DMONITOR_CFG[6] 02_371 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.DMONITOR_CFG[7] 03_371 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.DMONITOR_CFG[8] 02_372 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.DMONITOR_CFG[9] 03_372 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.DMONITOR_CFG[10] 02_373 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.DMONITOR_CFG[11] 03_373 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.DMONITOR_CFG[12] 02_374 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.DMONITOR_CFG[13] 03_374 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.DMONITOR_CFG[14] 02_375 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.DMONITOR_CFG[15] 03_375 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.DMONITOR_CFG[16] 02_376 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.DMONITOR_CFG[17] 03_376 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.DMONITOR_CFG[18] 02_377 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.DMONITOR_CFG[19] 03_377 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.DMONITOR_CFG[20] 02_378 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.DMONITOR_CFG[21] 03_378 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.DMONITOR_CFG[22] 02_379 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.DMONITOR_CFG[23] 03_379 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_CLK_PHASE_SEL[0] 03_463 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_CONTROL[0] 00_488 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_CONTROL[1] 01_488 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_CONTROL[2] 00_489 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_CONTROL[3] 01_489 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_CONTROL[4] 00_490 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_CONTROL[5] 01_490 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_ERRDET_EN 01_492 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_EYE_SCAN_EN 00_492 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_HORZ_OFFSET[0] 00_480 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_HORZ_OFFSET[1] 01_480 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_HORZ_OFFSET[2] 00_481 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_HORZ_OFFSET[3] 01_481 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_HORZ_OFFSET[4] 00_482 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_HORZ_OFFSET[5] 01_482 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_HORZ_OFFSET[6] 00_483 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_HORZ_OFFSET[7] 01_483 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_HORZ_OFFSET[8] 00_484 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_HORZ_OFFSET[9] 01_484 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_HORZ_OFFSET[10] 00_485 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_HORZ_OFFSET[11] 01_485 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_PMA_CFG[0] 02_624 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_PMA_CFG[1] 03_624 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_PMA_CFG[2] 02_625 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_PMA_CFG[3] 03_625 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_PMA_CFG[4] 02_626 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_PMA_CFG[5] 03_626 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_PMA_CFG[6] 02_627 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_PMA_CFG[7] 03_627 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_PMA_CFG[8] 02_628 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_PMA_CFG[9] 03_628 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_PRESCALE[0] 01_477 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_PRESCALE[1] 00_478 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_PRESCALE[2] 01_478 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_PRESCALE[3] 00_479 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_PRESCALE[4] 01_479 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[0] 00_392 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[1] 01_392 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[2] 00_393 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[3] 01_393 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[4] 00_394 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[5] 01_394 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[6] 00_395 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[7] 01_395 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[8] 00_396 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[9] 01_396 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[10] 00_397 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[11] 01_397 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[12] 00_398 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[13] 01_398 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[14] 00_399 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[15] 01_399 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[16] 00_400 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[17] 01_400 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[18] 00_401 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[19] 01_401 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[20] 00_402 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[21] 01_402 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[22] 00_403 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[23] 01_403 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[24] 00_404 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[25] 01_404 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[26] 00_405 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[27] 01_405 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[28] 00_406 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[29] 01_406 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[30] 00_407 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[31] 01_407 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[32] 00_408 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[33] 01_408 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[34] 00_409 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[35] 01_409 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[36] 00_410 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[37] 01_410 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[38] 00_411 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[39] 01_411 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[40] 00_412 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[41] 01_412 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[42] 00_413 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[43] 01_413 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[44] 00_414 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[45] 01_414 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[46] 00_415 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[47] 01_415 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[48] 00_416 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[49] 01_416 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[50] 00_417 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[51] 01_417 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[52] 00_418 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[53] 01_418 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[54] 00_419 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[55] 01_419 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[56] 00_420 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[57] 01_420 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[58] 00_421 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[59] 01_421 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[60] 00_422 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[61] 01_422 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[62] 00_423 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[63] 01_423 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[64] 00_424 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[65] 01_424 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[66] 00_425 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[67] 01_425 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[68] 00_426 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[69] 01_426 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[70] 00_427 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[71] 01_427 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[72] 00_428 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[73] 01_428 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[74] 00_429 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[75] 01_429 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[76] 00_430 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[77] 01_430 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[78] 00_431 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[79] 01_431 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[0] 00_352 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[1] 01_352 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[2] 00_353 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[3] 01_353 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[4] 00_354 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[5] 01_354 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[6] 00_355 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[7] 01_355 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[8] 00_356 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[9] 01_356 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[10] 00_357 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[11] 01_357 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[12] 00_358 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[13] 01_358 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[14] 00_359 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[15] 01_359 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[16] 00_360 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[17] 01_360 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[18] 00_361 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[19] 01_361 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[20] 00_362 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[21] 01_362 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[22] 00_363 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[23] 01_363 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[24] 00_364 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[25] 01_364 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[26] 00_365 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[27] 01_365 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[28] 00_366 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[29] 01_366 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[30] 00_367 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[31] 01_367 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[32] 00_368 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[33] 01_368 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[34] 00_369 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[35] 01_369 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[36] 00_370 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[37] 01_370 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[38] 00_371 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[39] 01_371 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[40] 00_372 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[41] 01_372 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[42] 00_373 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[43] 01_373 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[44] 00_374 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[45] 01_374 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[46] 00_375 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[47] 01_375 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[48] 00_376 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[49] 01_376 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[50] 00_377 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[51] 01_377 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[52] 00_378 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[53] 01_378 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[54] 00_379 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[55] 01_379 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[56] 00_380 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[57] 01_380 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[58] 00_381 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[59] 01_381 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[60] 00_382 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[61] 01_382 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[62] 00_383 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[63] 01_383 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[64] 00_384 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[65] 01_384 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[66] 00_385 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[67] 01_385 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[68] 00_386 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[69] 01_386 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[70] 00_387 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[71] 01_387 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[72] 00_388 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[73] 01_388 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[74] 00_389 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[75] 01_389 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[76] 00_390 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[77] 01_390 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[78] 00_391 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[79] 01_391 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[0] 00_432 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[1] 01_432 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[2] 00_433 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[3] 01_433 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[4] 00_434 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[5] 01_434 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[6] 00_435 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[7] 01_435 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[8] 00_436 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[9] 01_436 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[10] 00_437 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[11] 01_437 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[12] 00_438 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[13] 01_438 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[14] 00_439 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[15] 01_439 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[16] 00_440 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[17] 01_440 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[18] 00_441 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[19] 01_441 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[20] 00_442 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[21] 01_442 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[22] 00_443 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[23] 01_443 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[24] 00_444 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[25] 01_444 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[26] 00_445 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[27] 01_445 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[28] 00_446 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[29] 01_446 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[30] 00_447 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[31] 01_447 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[32] 00_448 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[33] 01_448 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[34] 00_449 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[35] 01_449 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[36] 00_450 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[37] 01_450 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[38] 00_451 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[39] 01_451 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[40] 00_452 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[41] 01_452 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[42] 00_453 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[43] 01_453 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[44] 00_454 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[45] 01_454 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[46] 00_455 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[47] 01_455 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[48] 00_456 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[49] 01_456 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[50] 00_457 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[51] 01_457 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[52] 00_458 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[53] 01_458 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[54] 00_459 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[55] 01_459 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[56] 00_460 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[57] 01_460 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[58] 00_461 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[59] 01_461 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[60] 00_462 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[61] 01_462 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[62] 00_463 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[63] 01_463 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[64] 00_464 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[65] 01_464 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[66] 00_465 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[67] 01_465 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[68] 00_466 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[69] 01_466 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[70] 00_467 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[71] 01_467 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[72] 00_468 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[73] 01_468 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[74] 00_469 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[75] 01_469 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[76] 00_470 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[77] 01_470 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[78] 00_471 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[79] 01_471 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_VERT_OFFSET[0] 00_472 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_VERT_OFFSET[1] 01_472 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_VERT_OFFSET[2] 00_473 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_VERT_OFFSET[3] 01_473 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_VERT_OFFSET[4] 00_474 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_VERT_OFFSET[5] 01_474 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_VERT_OFFSET[6] 00_475 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_VERT_OFFSET[7] 01_475 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_VERT_OFFSET[8] 00_476 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.FTS_DESKEW_SEQ_ENABLE[0] 00_662 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.FTS_DESKEW_SEQ_ENABLE[1] 01_662 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.FTS_DESKEW_SEQ_ENABLE[2] 00_663 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.FTS_DESKEW_SEQ_ENABLE[3] 01_663 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.FTS_LANE_DESKEW_CFG[0] 00_654 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.FTS_LANE_DESKEW_CFG[1] 01_654 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.FTS_LANE_DESKEW_CFG[2] 00_655 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.FTS_LANE_DESKEW_CFG[3] 01_655 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.FTS_LANE_DESKEW_EN 01_653 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.GEARBOX_MODE[0] 00_224 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.GEARBOX_MODE[1] 01_224 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.GEARBOX_MODE[2] 00_225 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.IN_USE 00_00 00_01 00_47 00_52 00_53 00_65 01_01 01_47 02_129 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.LOOPBACK_CFG[0] 02_20 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.OUTREFCLK_SEL_INV[0] 00_149 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.OUTREFCLK_SEL_INV[1] 01_149 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PCS_PCIE_EN 00_216 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[0] 02_184 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[1] 03_184 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[2] 02_185 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[3] 03_185 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[4] 02_186 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[5] 03_186 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[6] 02_187 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[7] 03_187 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[8] 02_188 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[9] 03_188 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[10] 02_189 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[11] 03_189 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[12] 02_190 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[13] 03_190 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[14] 02_191 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[15] 03_191 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[16] 02_192 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[17] 03_192 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[18] 02_193 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[19] 03_193 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[20] 02_194 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[21] 03_194 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[22] 02_195 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[23] 03_195 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[24] 02_196 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[25] 03_196 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[26] 02_197 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[27] 03_197 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[28] 02_198 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[29] 03_198 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[30] 02_199 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[31] 03_199 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[32] 02_200 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[33] 03_200 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[34] 02_201 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[35] 03_201 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[36] 02_202 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[37] 03_202 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[38] 02_203 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[39] 03_203 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[40] 02_204 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[41] 03_204 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[42] 02_205 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[43] 03_205 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[44] 02_206 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[45] 03_206 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[46] 02_207 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[47] 03_207 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PD_TRANS_TIME_FROM_P2[0] 01_216 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PD_TRANS_TIME_FROM_P2[1] 00_217 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PD_TRANS_TIME_FROM_P2[2] 01_217 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PD_TRANS_TIME_FROM_P2[3] 00_218 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PD_TRANS_TIME_FROM_P2[4] 01_218 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PD_TRANS_TIME_FROM_P2[5] 00_219 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PD_TRANS_TIME_FROM_P2[6] 01_219 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PD_TRANS_TIME_FROM_P2[7] 00_220 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PD_TRANS_TIME_FROM_P2[8] 01_220 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PD_TRANS_TIME_FROM_P2[9] 00_221 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PD_TRANS_TIME_FROM_P2[10] 01_221 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PD_TRANS_TIME_FROM_P2[11] 00_222 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PD_TRANS_TIME_NONE_P2[0] 00_208 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PD_TRANS_TIME_NONE_P2[1] 01_208 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PD_TRANS_TIME_NONE_P2[2] 00_209 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PD_TRANS_TIME_NONE_P2[3] 01_209 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PD_TRANS_TIME_NONE_P2[4] 00_210 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PD_TRANS_TIME_NONE_P2[5] 01_210 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PD_TRANS_TIME_NONE_P2[6] 00_211 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PD_TRANS_TIME_NONE_P2[7] 01_211 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PD_TRANS_TIME_TO_P2[0] 00_212 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PD_TRANS_TIME_TO_P2[1] 01_212 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PD_TRANS_TIME_TO_P2[2] 00_213 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PD_TRANS_TIME_TO_P2[3] 01_213 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PD_TRANS_TIME_TO_P2[4] 00_214 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PD_TRANS_TIME_TO_P2[5] 01_214 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PD_TRANS_TIME_TO_P2[6] 00_215 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PD_TRANS_TIME_TO_P2[7] 01_215 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PMA_LOOPBACK_CFG[0] 01_207 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PMA_RSV[0] 02_520 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PMA_RSV[1] 03_520 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PMA_RSV[2] 02_521 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PMA_RSV[3] 03_521 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PMA_RSV[4] 02_522 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PMA_RSV[5] 03_522 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PMA_RSV[6] 02_523 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PMA_RSV[7] 03_523 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PMA_RSV[8] 02_524 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PMA_RSV[9] 03_524 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PMA_RSV[10] 02_525 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PMA_RSV[11] 03_525 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PMA_RSV[12] 02_526 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PMA_RSV[13] 03_526 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PMA_RSV[14] 02_527 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PMA_RSV[15] 03_527 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PMA_RSV[16] 02_528 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PMA_RSV[17] 03_528 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PMA_RSV[18] 02_529 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PMA_RSV[19] 03_529 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PMA_RSV[20] 02_530 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PMA_RSV[21] 03_530 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PMA_RSV[22] 02_531 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PMA_RSV[23] 03_531 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PMA_RSV[24] 02_532 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PMA_RSV[25] 03_532 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PMA_RSV[26] 02_533 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PMA_RSV[27] 03_533 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PMA_RSV[28] 02_534 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PMA_RSV[29] 03_534 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PMA_RSV[30] 02_535 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PMA_RSV[31] 03_535 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PMA_RSV2[0] 02_336 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PMA_RSV2[1] 03_336 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PMA_RSV2[2] 02_337 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PMA_RSV2[3] 03_337 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PMA_RSV2[4] 02_338 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PMA_RSV2[5] 03_338 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PMA_RSV2[6] 02_339 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PMA_RSV2[7] 03_339 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PMA_RSV2[8] 02_340 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PMA_RSV2[9] 03_340 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PMA_RSV2[10] 02_341 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PMA_RSV2[11] 03_341 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PMA_RSV2[12] 02_342 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PMA_RSV2[13] 03_342 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PMA_RSV2[14] 02_343 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PMA_RSV2[15] 03_343 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PMA_RSV2[16] 02_344 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PMA_RSV2[17] 03_344 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PMA_RSV2[18] 02_345 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PMA_RSV2[19] 03_345 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PMA_RSV2[20] 02_346 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PMA_RSV2[21] 03_346 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PMA_RSV2[22] 02_347 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PMA_RSV2[23] 03_347 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PMA_RSV2[24] 02_348 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PMA_RSV2[25] 03_348 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PMA_RSV2[26] 02_349 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PMA_RSV2[27] 03_349 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PMA_RSV2[28] 02_350 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PMA_RSV2[29] 03_350 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PMA_RSV2[30] 02_351 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PMA_RSV2[31] 03_351 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PMA_RSV3[0] 02_288 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PMA_RSV3[1] 03_288 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PMA_RSV4[0] 02_156 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PMA_RSV4[1] 03_156 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PMA_RSV4[2] 02_157 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PMA_RSV4[3] 03_157 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PMA_RSV5[0] 03_159 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PMA_RSV6[0] 02_303 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PMA_RSV7[0] 03_303 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_BIAS_CFG[0] 02_112 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_BIAS_CFG[1] 03_112 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_BIAS_CFG[2] 02_113 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_BIAS_CFG[3] 03_113 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_BIAS_CFG[4] 02_114 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_BIAS_CFG[5] 03_114 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_BIAS_CFG[6] 02_115 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_BIAS_CFG[7] 03_115 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_BIAS_CFG[8] 02_116 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_BIAS_CFG[9] 03_116 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_BIAS_CFG[10] 02_117 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_BIAS_CFG[11] 03_117 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_BIAS_CFG[12] 02_118 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_BIAS_CFG[13] 03_118 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_BIAS_CFG[14] 02_119 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_BIAS_CFG[15] 03_119 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_BUFFER_CFG[0] 02_536 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_BUFFER_CFG[1] 03_536 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_BUFFER_CFG[2] 02_537 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_BUFFER_CFG[3] 03_537 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_BUFFER_CFG[4] 02_538 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_BUFFER_CFG[5] 03_538 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_CLKMUX_EN[0] 02_128 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_CM_SEL[0] 00_138 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_CM_SEL[1] 01_138 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_CM_TRIM[0] 02_304 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_CM_TRIM[1] 03_304 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_CM_TRIM[2] 02_305 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_CM_TRIM[3] 03_305 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_DATA_WIDTH[0] 01_141 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_DATA_WIDTH[1] 00_142 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_DATA_WIDTH[2] 01_142 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_DDI_SEL[0] 00_696 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_DDI_SEL[1] 01_696 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_DDI_SEL[2] 00_697 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_DDI_SEL[3] 01_697 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_DDI_SEL[4] 00_698 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_DDI_SEL[5] 01_698 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_DEBUG_CFG[0] 02_616 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_DEBUG_CFG[1] 03_616 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_DEBUG_CFG[2] 02_617 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_DEBUG_CFG[3] 03_617 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_DEBUG_CFG[4] 02_618 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_DEBUG_CFG[5] 03_618 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_DEBUG_CFG[6] 02_619 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_DEBUG_CFG[7] 03_619 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_DEBUG_CFG[8] 02_620 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_DEBUG_CFG[9] 03_620 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_DEBUG_CFG[10] 02_621 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_DEBUG_CFG[11] 03_621 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_DEBUG_CFG[12] 02_622 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_DEBUG_CFG[13] 03_622 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_DEFER_RESET_BUF_EN 02_552 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_DISPERR_SEQ_MATCH 01_495 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_OS_CFG[0] 00_288 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_OS_CFG[1] 01_288 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_OS_CFG[2] 00_289 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_OS_CFG[3] 01_289 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_OS_CFG[4] 00_290 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_OS_CFG[5] 01_290 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_OS_CFG[6] 00_291 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_OS_CFG[7] 01_291 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_OS_CFG[8] 00_292 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_OS_CFG[9] 01_292 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_OS_CFG[10] 00_293 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_OS_CFG[11] 01_293 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_OS_CFG[12] 00_294 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_SIG_VALID_DLY[0] 00_524 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_SIG_VALID_DLY[1] 01_524 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_SIG_VALID_DLY[2] 00_525 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_SIG_VALID_DLY[3] 01_525 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_SIG_VALID_DLY[4] 00_526 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_XCLK_SEL.RXUSR 00_143 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_CLK25_DIV[0] 00_139 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_CLK25_DIV[1] 01_139 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_CLK25_DIV[2] 00_140 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_CLK25_DIV[3] 01_140 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_CLK25_DIV[4] 00_141 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXBUF_ADDR_MODE.FAST 03_555 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXBUF_EIDLE_HI_CNT[0] 02_558 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXBUF_EIDLE_HI_CNT[1] 03_558 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXBUF_EIDLE_HI_CNT[2] 02_559 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXBUF_EIDLE_HI_CNT[3] 03_559 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXBUF_EIDLE_LO_CNT[0] 02_556 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXBUF_EIDLE_LO_CNT[1] 03_556 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXBUF_EIDLE_LO_CNT[2] 02_557 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXBUF_EIDLE_LO_CNT[3] 03_557 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXBUF_EN 02_11 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXBUF_RESET_ON_CB_CHANGE 02_560 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXBUF_RESET_ON_COMMAALIGN 02_561 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXBUF_RESET_ON_EIDLE 02_547 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXBUF_RESET_ON_RATE_CHANGE 03_560 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXBUF_THRESH_OVFLW[0] 03_552 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXBUF_THRESH_OVFLW[1] 02_553 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXBUF_THRESH_OVFLW[2] 03_553 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXBUF_THRESH_OVFLW[3] 02_554 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXBUF_THRESH_OVFLW[4] 03_554 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXBUF_THRESH_OVFLW[5] 02_555 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXBUF_THRESH_OVRD 02_548 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXBUF_THRESH_UNDFLW[0] 02_544 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXBUF_THRESH_UNDFLW[1] 03_544 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXBUF_THRESH_UNDFLW[2] 02_545 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXBUF_THRESH_UNDFLW[3] 03_545 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXBUF_THRESH_UNDFLW[4] 02_546 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXBUF_THRESH_UNDFLW[5] 03_546 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXBUFRESET_TIME[0] 01_101 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXBUFRESET_TIME[1] 00_102 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXBUFRESET_TIME[2] 01_102 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXBUFRESET_TIME[3] 00_103 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXBUFRESET_TIME[4] 01_103 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[0] 02_640 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[1] 03_640 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[2] 02_641 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[3] 03_641 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[4] 02_642 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[5] 03_642 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[6] 02_643 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[7] 03_643 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[8] 02_644 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[9] 03_644 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[10] 02_645 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[11] 03_645 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[12] 02_646 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[13] 03_646 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[14] 02_647 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[15] 03_647 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[16] 02_648 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[17] 03_648 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[18] 02_649 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[19] 03_649 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[20] 02_650 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[21] 03_650 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[22] 02_651 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[23] 03_651 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[24] 02_652 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[25] 03_652 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[26] 02_653 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[27] 03_653 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[28] 02_654 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[29] 03_654 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[30] 02_655 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[31] 03_655 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[32] 02_656 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[33] 03_656 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[34] 02_657 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[35] 03_657 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[36] 02_658 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[37] 03_658 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[38] 02_659 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[39] 03_659 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[40] 02_660 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[41] 03_660 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[42] 02_661 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[43] 03_661 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[44] 02_662 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[45] 03_662 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[46] 02_663 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[47] 03_663 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[48] 02_664 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[49] 03_664 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[50] 02_665 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[51] 03_665 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[52] 02_666 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[53] 03_666 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[54] 02_667 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[55] 03_667 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[56] 02_668 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[57] 03_668 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[58] 02_669 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[59] 03_669 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[60] 02_670 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[61] 03_670 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[62] 02_671 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[63] 03_671 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[64] 02_672 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[65] 03_672 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[66] 02_673 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[67] 03_673 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[68] 02_674 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[69] 03_674 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[70] 02_675 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[71] 03_675 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[72] 02_676 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[73] 03_676 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[74] 02_677 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[75] 03_677 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[76] 02_678 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[77] 03_678 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[78] 02_679 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[79] 03_679 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[80] 02_680 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[81] 03_680 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[82] 02_681 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_FR_RESET_ON_EIDLE[0] 02_638 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_HOLD_DURING_EIDLE[0] 03_637 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_LOCK_CFG[0] 02_632 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_LOCK_CFG[1] 03_632 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_LOCK_CFG[2] 02_633 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_LOCK_CFG[3] 03_633 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_LOCK_CFG[4] 02_634 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_LOCK_CFG[5] 03_634 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_PH_RESET_ON_EIDLE[0] 03_638 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDRFREQRESET_TIME[0] 01_106 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDRFREQRESET_TIME[1] 00_107 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDRFREQRESET_TIME[2] 01_107 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDRFREQRESET_TIME[3] 00_108 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDRFREQRESET_TIME[4] 01_108 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDRPHRESET_TIME[0] 00_109 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDRPHRESET_TIME[1] 01_109 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDRPHRESET_TIME[2] 00_110 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDRPHRESET_TIME[3] 01_110 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDRPHRESET_TIME[4] 00_111 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXDLY_CFG[0] 00_680 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXDLY_CFG[1] 01_680 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXDLY_CFG[2] 00_681 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXDLY_CFG[3] 01_681 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXDLY_CFG[4] 00_682 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXDLY_CFG[5] 01_682 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXDLY_CFG[6] 00_683 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXDLY_CFG[7] 01_683 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXDLY_CFG[8] 00_684 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXDLY_CFG[9] 01_684 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXDLY_CFG[10] 00_685 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXDLY_CFG[11] 01_685 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXDLY_CFG[12] 00_686 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXDLY_CFG[13] 01_686 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXDLY_CFG[14] 00_687 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXDLY_CFG[15] 01_687 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXDLY_LCFG[0] 02_576 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXDLY_LCFG[1] 03_576 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXDLY_LCFG[2] 02_577 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXDLY_LCFG[3] 03_577 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXDLY_LCFG[4] 02_578 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXDLY_LCFG[5] 03_578 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXDLY_LCFG[6] 02_579 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXDLY_LCFG[7] 03_579 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXDLY_LCFG[8] 02_580 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXDLY_TAP_CFG[0] 00_672 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXDLY_TAP_CFG[1] 01_672 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXDLY_TAP_CFG[2] 00_673 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXDLY_TAP_CFG[3] 01_673 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXDLY_TAP_CFG[4] 00_674 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXDLY_TAP_CFG[5] 01_674 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXDLY_TAP_CFG[6] 00_675 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXDLY_TAP_CFG[7] 01_675 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXDLY_TAP_CFG[8] 00_676 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXDLY_TAP_CFG[9] 01_676 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXDLY_TAP_CFG[10] 00_677 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXDLY_TAP_CFG[11] 01_677 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXDLY_TAP_CFG[12] 00_678 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXDLY_TAP_CFG[13] 01_678 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXDLY_TAP_CFG[14] 00_679 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXDLY_TAP_CFG[15] 01_679 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXGEARBOX_EN 01_607 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXISCANRESET_TIME[0] 01_123 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXISCANRESET_TIME[1] 00_124 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXISCANRESET_TIME[2] 01_124 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXISCANRESET_TIME[3] 00_125 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXISCANRESET_TIME[4] 01_125 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPM_BIAS_STARTUP_DISABLE[0] 03_391 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPM_CFG[0] 02_328 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPM_CFG[1] 03_328 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPM_CFG[2] 02_329 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPM_CFG[3] 03_329 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPM_CM_CFG[0] 02_430 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPM_GC_CFG[0] 02_432 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPM_GC_CFG[1] 03_432 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPM_GC_CFG[2] 02_433 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPM_GC_CFG[3] 03_433 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPM_GC_CFG[4] 02_434 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPM_GC_CFG[5] 03_434 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPM_GC_CFG[6] 02_435 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPM_GC_CFG[7] 03_435 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPM_GC_CFG[8] 02_436 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPM_GC_CFG2[0] 03_442 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPM_GC_CFG2[1] 02_443 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPM_GC_CFG2[2] 03_443 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPM_HF_CFG[0] 00_336 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPM_HF_CFG[1] 01_336 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPM_HF_CFG[2] 00_337 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPM_HF_CFG[3] 01_337 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPM_HF_CFG[4] 00_338 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPM_HF_CFG[5] 01_338 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPM_HF_CFG[6] 00_339 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPM_HF_CFG[7] 01_339 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPM_HF_CFG[8] 00_340 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPM_HF_CFG[9] 01_340 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPM_HF_CFG[10] 00_341 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPM_HF_CFG[11] 01_341 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPM_HF_CFG[12] 00_342 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPM_HF_CFG[13] 01_342 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPM_HF_CFG2[0] 02_424 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPM_HF_CFG2[1] 03_424 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPM_HF_CFG2[2] 02_425 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPM_HF_CFG2[3] 03_425 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPM_HF_CFG2[4] 02_426 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPM_HF_CFG3[0] 03_389 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPM_HF_CFG3[1] 02_390 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPM_HF_CFG3[2] 03_390 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPM_HF_CFG3[3] 02_391 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPM_HOLD_DURING_EIDLE[0] 00_247 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPM_INCM_CFG[0] 02_439 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPM_IPCM_CFG[0] 03_439 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPM_LF_CFG[0] 00_344 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPM_LF_CFG[1] 01_344 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPM_LF_CFG[2] 00_345 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPM_LF_CFG[3] 01_345 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPM_LF_CFG[4] 00_346 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPM_LF_CFG[5] 01_346 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPM_LF_CFG[6] 00_347 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPM_LF_CFG[7] 01_347 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPM_LF_CFG[8] 00_348 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPM_LF_CFG[9] 01_348 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPM_LF_CFG[10] 00_349 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPM_LF_CFG[11] 01_349 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPM_LF_CFG[12] 00_350 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPM_LF_CFG[13] 01_350 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPM_LF_CFG[14] 00_351 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPM_LF_CFG[15] 01_351 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPM_LF_CFG[16] 00_343 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPM_LF_CFG[17] 01_343 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPM_LF_CFG2[0] 03_426 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPM_LF_CFG2[1] 02_427 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPM_LF_CFG2[2] 03_427 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPM_LF_CFG2[3] 02_428 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPM_LF_CFG2[4] 03_428 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPM_OSINT_CFG[0] 02_440 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPM_OSINT_CFG[1] 03_440 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPM_OSINT_CFG[2] 02_441 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPM_CFG1[0] 02_330 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPMRESET_TIME[0] 00_112 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPMRESET_TIME[1] 01_112 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPMRESET_TIME[2] 00_113 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPMRESET_TIME[3] 01_113 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPMRESET_TIME[4] 00_114 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPMRESET_TIME[5] 01_114 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPMRESET_TIME[6] 00_115 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXOOB_CFG[0] 00_144 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXOOB_CFG[1] 01_144 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXOOB_CFG[2] 00_145 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXOOB_CFG[3] 01_145 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXOOB_CFG[4] 00_146 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXOOB_CFG[5] 01_146 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXOOB_CFG[6] 00_147 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXOOB_CLK_CFG.FABRIC 03_129 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXOSCALRESET_TIME[0] 00_187 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXOSCALRESET_TIME[1] 01_187 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXOSCALRESET_TIME[2] 00_188 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXOSCALRESET_TIME[3] 01_188 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXOSCALRESET_TIME[4] 00_189 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXOSCALRESET_TIMEOUT[0] 01_189 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXOSCALRESET_TIMEOUT[1] 00_190 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXOSCALRESET_TIMEOUT[2] 01_190 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXOSCALRESET_TIMEOUT[3] 00_191 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXOSCALRESET_TIMEOUT[4] 01_191 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXOUT_DIV[0] 02_384 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXOUT_DIV[1] 03_384 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXPCSRESET_TIME[0] 01_115 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXPCSRESET_TIME[1] 00_116 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXPCSRESET_TIME[2] 01_116 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXPCSRESET_TIME[3] 00_117 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXPCSRESET_TIME[4] 01_117 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXPH_CFG[0] 02_584 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXPH_CFG[1] 03_584 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXPH_CFG[2] 02_585 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXPH_CFG[3] 03_585 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXPH_CFG[4] 02_586 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXPH_CFG[5] 03_586 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXPH_CFG[6] 02_587 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXPH_CFG[7] 03_587 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXPH_CFG[8] 02_588 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXPH_CFG[9] 03_588 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXPH_CFG[10] 02_589 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXPH_CFG[11] 03_589 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXPH_CFG[12] 02_590 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXPH_CFG[13] 03_590 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXPH_CFG[14] 02_591 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXPH_CFG[15] 03_591 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXPH_CFG[16] 02_592 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXPH_CFG[17] 03_592 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXPH_CFG[18] 02_593 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXPH_CFG[19] 03_593 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXPH_CFG[20] 02_594 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXPH_CFG[21] 03_594 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXPH_CFG[22] 02_595 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXPH_CFG[23] 03_595 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXPH_MONITOR_SEL[0] 00_700 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXPH_MONITOR_SEL[1] 01_700 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXPH_MONITOR_SEL[2] 00_701 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXPH_MONITOR_SEL[3] 01_701 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXPH_MONITOR_SEL[4] 00_702 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXPHDLY_CFG[0] 02_600 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXPHDLY_CFG[1] 03_600 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXPHDLY_CFG[2] 02_601 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXPHDLY_CFG[3] 03_601 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXPHDLY_CFG[4] 02_602 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXPHDLY_CFG[5] 03_602 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXPHDLY_CFG[6] 02_603 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXPHDLY_CFG[7] 03_603 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXPHDLY_CFG[8] 02_604 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXPHDLY_CFG[9] 03_604 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXPHDLY_CFG[10] 02_605 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXPHDLY_CFG[11] 03_605 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXPHDLY_CFG[12] 02_606 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXPHDLY_CFG[13] 03_606 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXPHDLY_CFG[14] 02_607 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXPHDLY_CFG[15] 03_607 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXPHDLY_CFG[16] 02_608 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXPHDLY_CFG[17] 03_608 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXPHDLY_CFG[18] 02_609 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXPHDLY_CFG[19] 03_609 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXPHDLY_CFG[20] 02_610 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXPHDLY_CFG[21] 03_610 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXPHDLY_CFG[22] 02_611 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXPHDLY_CFG[23] 03_611 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXPI_CFG0[0] 03_430 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXPI_CFG0[1] 02_431 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXPI_CFG0[2] 03_431 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXPI_CFG1[0] 02_442 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXPI_CFG2[0] 03_441 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXPMARESET_TIME[0] 00_104 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXPMARESET_TIME[1] 01_104 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXPMARESET_TIME[2] 00_105 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXPMARESET_TIME[3] 01_105 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXPMARESET_TIME[4] 00_106 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXPRBS_ERR_LOOPBACK[0] 00_136 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXSLIDE_AUTO_WAIT[0] 00_520 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXSLIDE_AUTO_WAIT[1] 01_520 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXSLIDE_AUTO_WAIT[2] 00_521 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXSLIDE_AUTO_WAIT[3] 01_521 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXSLIDE_MODE.AUTO 00_519 !01_519 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXSLIDE_MODE.PCS !00_519 01_519 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXSLIDE_MODE.PMA 00_519 01_519 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXSYNC_MULTILANE[0] 00_133 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXSYNC_OVRD[0] 01_135 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXSYNC_SKIP_DA[0] 01_134 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.SAS_MAX_COM[0] 00_171 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.SAS_MAX_COM[1] 01_171 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.SAS_MAX_COM[2] 00_172 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.SAS_MAX_COM[3] 01_172 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.SAS_MAX_COM[4] 00_173 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.SAS_MAX_COM[5] 01_173 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.SAS_MAX_COM[6] 00_174 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.SAS_MIN_COM[0] 01_156 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.SAS_MIN_COM[1] 00_157 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.SAS_MIN_COM[2] 01_157 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.SAS_MIN_COM[3] 00_158 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.SAS_MIN_COM[4] 01_158 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.SAS_MIN_COM[5] 00_159 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.SATA_BURST_SEQ_LEN[0] 00_150 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.SATA_BURST_SEQ_LEN[1] 01_150 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.SATA_BURST_SEQ_LEN[2] 00_151 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.SATA_BURST_SEQ_LEN[3] 01_151 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.SATA_BURST_VAL[0] 01_147 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.SATA_BURST_VAL[1] 00_148 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.SATA_BURST_VAL[2] 01_148 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.SATA_EIDLE_VAL[0] 00_152 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.SATA_EIDLE_VAL[1] 01_152 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.SATA_EIDLE_VAL[2] 00_153 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.SATA_MAX_BURST[0] 00_168 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.SATA_MAX_BURST[1] 01_168 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.SATA_MAX_BURST[2] 00_169 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.SATA_MAX_BURST[3] 01_169 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.SATA_MAX_BURST[4] 00_170 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.SATA_MAX_BURST[5] 01_170 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.SATA_MAX_INIT[0] 00_176 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.SATA_MAX_INIT[1] 01_176 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.SATA_MAX_INIT[2] 00_177 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.SATA_MAX_INIT[3] 01_177 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.SATA_MAX_INIT[4] 00_178 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.SATA_MAX_INIT[5] 01_178 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.SATA_MAX_WAKE[0] 00_179 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.SATA_MAX_WAKE[1] 01_179 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.SATA_MAX_WAKE[2] 00_180 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.SATA_MAX_WAKE[3] 01_180 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.SATA_MAX_WAKE[4] 00_181 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.SATA_MAX_WAKE[5] 01_181 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.SATA_MIN_BURST[0] 01_153 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.SATA_MIN_BURST[1] 00_154 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.SATA_MIN_BURST[2] 01_154 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.SATA_MIN_BURST[3] 00_155 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.SATA_MIN_BURST[4] 01_155 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.SATA_MIN_BURST[5] 00_156 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.SATA_MIN_INIT[0] 00_160 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.SATA_MIN_INIT[1] 01_160 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.SATA_MIN_INIT[2] 00_161 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.SATA_MIN_INIT[3] 01_161 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.SATA_MIN_INIT[4] 00_162 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.SATA_MIN_INIT[5] 01_162 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.SATA_MIN_WAKE[0] 00_163 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.SATA_MIN_WAKE[1] 01_163 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.SATA_MIN_WAKE[2] 00_164 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.SATA_MIN_WAKE[3] 01_164 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.SATA_MIN_WAKE[4] 00_165 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.SATA_MIN_WAKE[5] 01_165 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.SATA_PLL_CFG.VCO_1500MHZ 02_55 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.SATA_PLL_CFG.VCO_750MHZ 03_55 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.SHOW_REALIGN_COMMA 01_522 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TERM_RCAL_CFG[0] 02_136 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TERM_RCAL_CFG[1] 03_136 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TERM_RCAL_CFG[2] 02_137 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TERM_RCAL_CFG[3] 03_137 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TERM_RCAL_CFG[4] 02_138 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TERM_RCAL_CFG[5] 03_138 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TERM_RCAL_CFG[6] 02_139 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TERM_RCAL_CFG[7] 03_139 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TERM_RCAL_CFG[8] 02_140 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TERM_RCAL_CFG[9] 03_140 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TERM_RCAL_CFG[10] 02_141 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TERM_RCAL_CFG[11] 03_141 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TERM_RCAL_CFG[12] 02_142 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TERM_RCAL_CFG[13] 03_142 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TERM_RCAL_CFG[14] 02_143 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TERM_RCAL_OVRD[0] 03_150 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TERM_RCAL_OVRD[1] 02_151 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TERM_RCAL_OVRD[2] 03_151 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TRANS_TIME_RATE[0] 00_192 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TRANS_TIME_RATE[1] 01_192 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TRANS_TIME_RATE[2] 00_193 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TRANS_TIME_RATE[3] 01_193 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TRANS_TIME_RATE[4] 00_194 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TRANS_TIME_RATE[5] 01_194 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TRANS_TIME_RATE[6] 00_195 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TRANS_TIME_RATE[7] 01_195 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TST_RSV[0] 02_504 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TST_RSV[1] 03_504 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TST_RSV[2] 02_505 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TST_RSV[3] 03_505 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TST_RSV[4] 02_506 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TST_RSV[5] 03_506 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TST_RSV[6] 02_507 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TST_RSV[7] 03_507 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TST_RSV[8] 02_508 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TST_RSV[9] 03_508 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TST_RSV[10] 02_509 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TST_RSV[11] 03_509 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TST_RSV[12] 02_510 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TST_RSV[13] 03_510 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TST_RSV[14] 02_511 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TST_RSV[15] 03_511 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TST_RSV[16] 02_512 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TST_RSV[17] 03_512 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TST_RSV[18] 02_513 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TST_RSV[19] 03_513 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TST_RSV[20] 02_514 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TST_RSV[21] 03_514 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TST_RSV[22] 02_515 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TST_RSV[23] 03_515 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TST_RSV[24] 02_516 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TST_RSV[25] 03_516 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TST_RSV[26] 02_517 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TST_RSV[27] 03_517 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TST_RSV[28] 02_518 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TST_RSV[29] 03_518 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TST_RSV[30] 02_519 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TST_RSV[31] 03_519 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_CLKMUX_EN[0] 03_128 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_DATA_WIDTH[0] 02_152 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_DATA_WIDTH[1] 03_152 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_DATA_WIDTH[2] 02_153 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_DRIVE_MODE.PIPE 00_200 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_EIDLE_ASSERT_DELAY[0] 00_203 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_EIDLE_ASSERT_DELAY[1] 01_203 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_EIDLE_ASSERT_DELAY[2] 00_204 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_EIDLE_DEASSERT_DELAY[0] 01_204 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_EIDLE_DEASSERT_DELAY[1] 00_205 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_EIDLE_DEASSERT_DELAY[2] 01_205 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_LOOPBACK_DRIVE_HIZ 01_202 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_MAINCURSOR_SEL[0] 03_289 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_MARGIN_FULL_0[0] 02_232 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_MARGIN_FULL_0[1] 03_232 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_MARGIN_FULL_0[2] 02_233 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_MARGIN_FULL_0[3] 03_233 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_MARGIN_FULL_0[4] 02_234 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_MARGIN_FULL_0[5] 03_234 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_MARGIN_FULL_0[6] 02_235 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_MARGIN_FULL_1[0] 02_236 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_MARGIN_FULL_1[1] 03_236 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_MARGIN_FULL_1[2] 02_237 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_MARGIN_FULL_1[3] 03_237 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_MARGIN_FULL_1[4] 02_238 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_MARGIN_FULL_1[5] 03_238 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_MARGIN_FULL_1[6] 02_239 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_MARGIN_FULL_2[0] 02_240 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_MARGIN_FULL_2[1] 03_240 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_MARGIN_FULL_2[2] 02_241 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_MARGIN_FULL_2[3] 03_241 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_MARGIN_FULL_2[4] 02_242 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_MARGIN_FULL_2[5] 03_242 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_MARGIN_FULL_2[6] 02_243 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_MARGIN_FULL_3[0] 02_244 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_MARGIN_FULL_3[1] 03_244 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_MARGIN_FULL_3[2] 02_245 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_MARGIN_FULL_3[3] 03_245 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_MARGIN_FULL_3[4] 02_246 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_MARGIN_FULL_3[5] 03_246 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_MARGIN_FULL_3[6] 02_247 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_MARGIN_FULL_4[0] 02_248 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_MARGIN_FULL_4[1] 03_248 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_MARGIN_FULL_4[2] 02_249 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_MARGIN_FULL_4[3] 03_249 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_MARGIN_FULL_4[4] 02_250 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_MARGIN_FULL_4[5] 03_250 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_MARGIN_FULL_4[6] 02_251 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_MARGIN_LOW_0[0] 02_252 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_MARGIN_LOW_0[1] 03_252 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_MARGIN_LOW_0[2] 02_253 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_MARGIN_LOW_0[3] 03_253 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_MARGIN_LOW_0[4] 02_254 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_MARGIN_LOW_0[5] 03_254 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_MARGIN_LOW_0[6] 02_255 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_MARGIN_LOW_1[0] 02_256 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_MARGIN_LOW_1[1] 03_256 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_MARGIN_LOW_1[2] 02_257 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_MARGIN_LOW_1[3] 03_257 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_MARGIN_LOW_1[4] 02_258 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_MARGIN_LOW_1[5] 03_258 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_MARGIN_LOW_1[6] 02_259 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_MARGIN_LOW_2[0] 02_260 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_MARGIN_LOW_2[1] 03_260 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_MARGIN_LOW_2[2] 02_261 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_MARGIN_LOW_2[3] 03_261 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_MARGIN_LOW_2[4] 02_262 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_MARGIN_LOW_2[5] 03_262 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_MARGIN_LOW_2[6] 02_263 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_MARGIN_LOW_3[0] 02_264 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_MARGIN_LOW_3[1] 03_264 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_MARGIN_LOW_3[2] 02_265 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_MARGIN_LOW_3[3] 03_265 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_MARGIN_LOW_3[4] 02_266 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_MARGIN_LOW_3[5] 03_266 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_MARGIN_LOW_3[6] 02_267 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_MARGIN_LOW_4[0] 02_268 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_MARGIN_LOW_4[1] 03_268 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_MARGIN_LOW_4[2] 02_269 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_MARGIN_LOW_4[3] 03_269 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_MARGIN_LOW_4[4] 02_270 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_MARGIN_LOW_4[5] 03_270 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_MARGIN_LOW_4[6] 02_271 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_PREDRIVER_MODE[0] 00_206 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_RXDETECT_CFG[0] 02_296 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_RXDETECT_CFG[1] 03_296 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_RXDETECT_CFG[2] 02_297 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_RXDETECT_CFG[3] 03_297 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_RXDETECT_CFG[4] 02_298 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_RXDETECT_CFG[5] 03_298 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_RXDETECT_CFG[6] 02_299 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_RXDETECT_CFG[7] 03_299 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_RXDETECT_CFG[8] 02_300 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_RXDETECT_CFG[9] 03_300 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_RXDETECT_CFG[10] 02_301 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_RXDETECT_CFG[11] 03_301 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_RXDETECT_CFG[12] 02_302 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_RXDETECT_CFG[13] 03_302 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_RXDETECT_REF[0] 02_292 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_RXDETECT_REF[1] 03_292 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_RXDETECT_REF[2] 02_293 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_XCLK_SEL.TXUSR 03_11 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_CLK25_DIV[0] 02_144 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_CLK25_DIV[1] 03_144 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_CLK25_DIV[2] 02_145 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_CLK25_DIV[3] 03_145 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_CLK25_DIV[4] 02_146 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_DEEMPH0[0] 02_272 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_DEEMPH0[1] 03_272 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_DEEMPH0[2] 02_273 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_DEEMPH0[3] 03_273 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_DEEMPH0[4] 02_274 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_DEEMPH0[5] 03_274 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_DEEMPH1[0] 02_276 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_DEEMPH1[1] 03_276 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_DEEMPH1[2] 02_277 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_DEEMPH1[3] 03_277 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_DEEMPH1[4] 02_278 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_DEEMPH1[5] 03_278 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXBUF_EN 00_231 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXBUF_RESET_ON_RATE_CHANGE 01_231 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXDLY_CFG[0] 02_80 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXDLY_CFG[1] 03_80 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXDLY_CFG[2] 02_81 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXDLY_CFG[3] 03_81 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXDLY_CFG[4] 02_82 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXDLY_CFG[5] 03_82 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXDLY_CFG[6] 02_83 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXDLY_CFG[7] 03_83 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXDLY_CFG[8] 02_84 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXDLY_CFG[9] 03_84 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXDLY_CFG[10] 02_85 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXDLY_CFG[11] 03_85 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXDLY_CFG[12] 02_86 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXDLY_CFG[13] 03_86 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXDLY_CFG[14] 02_87 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXDLY_CFG[15] 03_87 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXDLY_LCFG[0] 02_568 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXDLY_LCFG[1] 03_568 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXDLY_LCFG[2] 02_569 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXDLY_LCFG[3] 03_569 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXDLY_LCFG[4] 02_570 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXDLY_LCFG[5] 03_570 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXDLY_LCFG[6] 02_571 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXDLY_LCFG[7] 03_571 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXDLY_LCFG[8] 02_572 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXDLY_TAP_CFG[0] 02_88 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXDLY_TAP_CFG[1] 03_88 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXDLY_TAP_CFG[2] 02_89 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXDLY_TAP_CFG[3] 03_89 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXDLY_TAP_CFG[4] 02_90 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXDLY_TAP_CFG[5] 03_90 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXDLY_TAP_CFG[6] 02_91 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXDLY_TAP_CFG[7] 03_91 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXDLY_TAP_CFG[8] 02_92 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXDLY_TAP_CFG[9] 03_92 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXDLY_TAP_CFG[10] 02_93 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXDLY_TAP_CFG[11] 03_93 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXDLY_TAP_CFG[12] 02_94 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXDLY_TAP_CFG[13] 03_94 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXDLY_TAP_CFG[14] 02_95 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXDLY_TAP_CFG[15] 03_95 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXGEARBOX_EN 01_226 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXOOB_CFG[0] 03_20 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXOUT_DIV[0] 02_386 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXOUT_DIV[1] 03_386 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPCSRESET_TIME[0] 01_130 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPCSRESET_TIME[1] 00_131 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPCSRESET_TIME[2] 01_131 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPCSRESET_TIME[3] 00_132 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPCSRESET_TIME[4] 01_132 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPH_CFG[0] 02_96 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPH_CFG[1] 03_96 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPH_CFG[2] 02_97 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPH_CFG[3] 03_97 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPH_CFG[4] 02_98 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPH_CFG[5] 03_98 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPH_CFG[6] 02_99 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPH_CFG[7] 03_99 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPH_CFG[8] 02_100 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPH_CFG[9] 03_100 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPH_CFG[10] 02_101 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPH_CFG[11] 03_101 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPH_CFG[12] 02_102 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPH_CFG[13] 03_102 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPH_CFG[14] 02_103 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPH_CFG[15] 03_103 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPH_MONITOR_SEL[0] 02_108 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPH_MONITOR_SEL[1] 03_108 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPH_MONITOR_SEL[2] 02_109 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPH_MONITOR_SEL[3] 03_109 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPH_MONITOR_SEL[4] 02_110 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPHDLY_CFG[0] 02_64 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPHDLY_CFG[1] 03_64 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPHDLY_CFG[2] 02_65 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPHDLY_CFG[3] 03_65 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPHDLY_CFG[4] 02_66 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPHDLY_CFG[5] 03_66 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPHDLY_CFG[6] 02_67 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPHDLY_CFG[7] 03_67 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPHDLY_CFG[8] 02_68 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPHDLY_CFG[9] 03_68 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPHDLY_CFG[10] 02_69 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPHDLY_CFG[11] 03_69 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPHDLY_CFG[12] 02_70 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPHDLY_CFG[13] 03_70 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPHDLY_CFG[14] 02_71 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPHDLY_CFG[15] 03_71 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPHDLY_CFG[16] 02_72 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPHDLY_CFG[17] 03_72 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPHDLY_CFG[18] 02_73 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPHDLY_CFG[19] 03_73 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPHDLY_CFG[20] 02_74 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPHDLY_CFG[21] 03_74 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPHDLY_CFG[22] 02_75 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPHDLY_CFG[23] 03_75 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPI_GREY_SEL[0] 03_498 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPI_INVSTROBE_SEL[0] 02_498 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPI_PPM_CFG[0] 02_488 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPI_PPM_CFG[1] 03_488 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPI_PPM_CFG[2] 02_489 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPI_PPM_CFG[3] 03_489 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPI_PPM_CFG[4] 02_490 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPI_PPM_CFG[5] 03_490 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPI_PPM_CFG[6] 02_491 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPI_PPM_CFG[7] 03_491 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPI_PPMCLK_SEL.TXUSRCLK2 03_497 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPI_SYNFREQ_PPM[0] 02_496 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPI_SYNFREQ_PPM[1] 03_496 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPI_SYNFREQ_PPM[2] 02_497 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPI_CFG0[0] 02_40 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPI_CFG0[1] 03_40 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPI_CFG1[0] 02_41 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPI_CFG1[1] 03_41 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPI_CFG2[0] 02_42 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPI_CFG2[1] 03_42 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPI_CFG3[0] 02_43 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPI_CFG4[0] 03_43 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPI_CFG5[0] 02_44 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPI_CFG5[1] 03_44 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPI_CFG5[2] 02_45 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPMARESET_TIME[0] 00_128 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPMARESET_TIME[1] 01_128 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPMARESET_TIME[2] 00_129 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPMARESET_TIME[3] 01_129 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPMARESET_TIME[4] 00_130 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXSYNC_MULTILANE[0] 01_133 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXSYNC_OVRD[0] 00_135 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXSYNC_SKIP_DA[0] 00_134 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.UCODEER_CLR[0] 01_00 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.USE_PCS_CLK_PHASE_SEL[0] 02_463 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ZINV_DMONITORCLK 02_13 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ZINV_DRPCLK 02_00 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ZINV_RXUSRCLK 03_01 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ZINV_SIGVALIDCLK 03_13 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ZINV_TXPHDLYTSTCLK 02_03 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ZINV_TXUSRCLK 03_04 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ZINV_CLKRSVD0 02_23 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ZINV_CLKRSVD1 03_23 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ZINV_RXUSRCLK2 02_02 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ZINV_TXUSRCLK2 02_05 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ACJTAG_DEBUG_MODE[0] 00_07 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ACJTAG_MODE[0] 01_06 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ACJTAG_RESET[0] 01_07 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[0] 02_464 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[1] 03_464 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[2] 02_465 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[3] 03_465 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[4] 02_466 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[5] 03_466 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[6] 02_467 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[7] 03_467 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[8] 02_468 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[9] 03_468 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[10] 02_469 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[11] 03_469 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[12] 02_470 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[13] 03_470 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[14] 02_471 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[15] 03_471 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[16] 02_472 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[17] 03_472 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[18] 02_473 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[19] 03_473 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ALIGN_COMMA_DOUBLE 00_522 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[0] 00_496 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[1] 01_496 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[2] 00_497 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[3] 01_497 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[4] 00_498 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[5] 01_498 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[6] 00_499 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[7] 01_499 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[8] 00_500 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[9] 01_500 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ALIGN_COMMA_WORD[0] 01_526 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ALIGN_COMMA_WORD[1] 00_527 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ALIGN_MCOMMA_DET 00_523 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[0] 00_504 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[1] 01_504 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[2] 00_505 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[3] 01_505 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[4] 00_506 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[5] 01_506 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[6] 00_507 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[7] 01_507 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[8] 00_508 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[9] 01_508 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ALIGN_PCOMMA_DET 01_523 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[0] 00_512 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[1] 01_512 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[2] 00_513 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[3] 01_513 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[4] 00_514 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[5] 01_514 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[6] 00_515 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[7] 01_515 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[8] 00_516 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[9] 01_516 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CBCC_DATA_SOURCE_SEL.DECODED 01_661 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[0] 02_392 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[1] 03_392 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[2] 02_393 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[3] 03_393 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[4] 02_394 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[5] 03_394 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[6] 02_395 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[7] 03_395 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[8] 02_396 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[9] 03_396 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[10] 02_397 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[11] 03_397 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[12] 02_398 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[13] 03_398 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[14] 02_399 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[15] 03_399 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[16] 02_400 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[17] 03_400 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[18] 02_401 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[19] 03_401 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[20] 02_402 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[21] 03_402 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[22] 02_403 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[23] 03_403 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[24] 02_404 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[25] 03_404 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[26] 02_405 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[27] 03_405 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[28] 02_406 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[29] 03_406 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[30] 02_407 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[31] 03_407 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[32] 02_408 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[33] 03_408 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[34] 02_409 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[35] 03_409 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[36] 02_410 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[37] 03_410 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[38] 02_411 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[39] 03_411 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[40] 02_412 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[41] 03_412 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[42] 02_413 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG2[0] 02_459 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG2[1] 03_459 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG2[2] 02_460 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG2[3] 03_460 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG2[4] 02_461 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG2[5] 03_461 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG2[6] 02_462 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG3[0] 02_416 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG3[1] 03_416 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG3[2] 02_417 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG3[3] 03_417 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG3[4] 02_418 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG3[5] 03_418 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG3[6] 02_419 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG4[0] 03_438 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG5[0] 02_429 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG5[1] 03_429 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG6[0] 03_436 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG6[1] 02_437 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG6[2] 03_437 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG6[3] 02_438 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_KEEP_ALIGN 01_631 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_MAX_SKEW[0] 00_670 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_MAX_SKEW[1] 01_670 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_MAX_SKEW[2] 00_671 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_MAX_SKEW[3] 01_671 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[0] 00_608 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[1] 01_608 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[2] 00_609 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[3] 01_609 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[4] 00_610 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[5] 01_610 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[6] 00_611 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[7] 01_611 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[8] 00_612 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[9] 01_612 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[0] 00_616 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[1] 01_616 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[2] 00_617 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[3] 01_617 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[4] 00_618 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[5] 01_618 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[6] 00_619 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[7] 01_619 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[8] 00_620 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[9] 01_620 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[0] 00_624 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[1] 01_624 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[2] 00_625 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[3] 01_625 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[4] 00_626 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[5] 01_626 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[6] 00_627 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[7] 01_627 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[8] 00_628 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[9] 01_628 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[0] 00_632 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[1] 01_632 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[2] 00_633 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[3] 01_633 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[4] 00_634 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[5] 01_634 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[6] 00_635 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[7] 01_635 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[8] 00_636 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[9] 01_636 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_ENABLE[0] 00_614 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_ENABLE[1] 01_614 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_ENABLE[2] 00_615 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_ENABLE[3] 01_615 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[0] 00_640 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[1] 01_640 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[2] 00_641 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[3] 01_641 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[4] 00_642 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[5] 01_642 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[6] 00_643 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[7] 01_643 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[8] 00_644 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[9] 01_644 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[0] 00_648 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[1] 01_648 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[2] 00_649 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[3] 01_649 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[4] 00_650 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[5] 01_650 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[6] 00_651 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[7] 01_651 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[8] 00_652 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[9] 01_652 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[0] 00_656 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[1] 01_656 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[2] 00_657 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[3] 01_657 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[4] 00_658 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[5] 01_658 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[6] 00_659 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[7] 01_659 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[8] 00_660 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[9] 01_660 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[0] 00_664 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[1] 01_664 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[2] 00_665 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[3] 01_665 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[4] 00_666 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[5] 01_666 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[6] 00_667 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[7] 01_667 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[8] 00_668 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[9] 01_668 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_ENABLE[0] 00_646 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_ENABLE[1] 01_646 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_ENABLE[2] 00_647 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_ENABLE[3] 01_647 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_USE 01_645 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_LEN[0] 00_623 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_LEN[1] 01_623 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COMMON_SWING[0] 03_311 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_KEEP_IDLE 00_591 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_MAX_LAT[0] 00_557 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_MAX_LAT[1] 01_557 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_MAX_LAT[2] 00_558 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_MAX_LAT[3] 01_558 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_MAX_LAT[4] 00_559 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_MAX_LAT[5] 01_559 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_MIN_LAT[0] 00_565 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_MIN_LAT[1] 01_565 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_MIN_LAT[2] 00_566 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_MIN_LAT[3] 01_566 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_MIN_LAT[4] 00_567 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_MIN_LAT[5] 01_567 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_PRECEDENCE 00_590 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_REPEAT_WAIT[0] 00_573 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_REPEAT_WAIT[1] 01_573 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_REPEAT_WAIT[2] 00_574 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_REPEAT_WAIT[3] 01_574 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_REPEAT_WAIT[4] 00_575 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[0] 00_544 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[1] 01_544 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[2] 00_545 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[3] 01_545 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[4] 00_546 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[5] 01_546 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[6] 00_547 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[7] 01_547 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[8] 00_548 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[9] 01_548 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[0] 00_552 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[1] 01_552 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[2] 00_553 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[3] 01_553 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[4] 00_554 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[5] 01_554 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[6] 00_555 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[7] 01_555 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[8] 00_556 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[9] 01_556 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[0] 00_560 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[1] 01_560 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[2] 00_561 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[3] 01_561 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[4] 00_562 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[5] 01_562 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[6] 00_563 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[7] 01_563 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[8] 00_564 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[9] 01_564 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[0] 00_568 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[1] 01_568 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[2] 00_569 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[3] 01_569 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[4] 00_570 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[5] 01_570 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[6] 00_571 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[7] 01_571 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[8] 00_572 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[9] 01_572 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_ENABLE[0] 00_549 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_ENABLE[1] 01_549 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_ENABLE[2] 00_550 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_ENABLE[3] 01_550 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[0] 00_576 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[1] 01_576 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[2] 00_577 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[3] 01_577 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[4] 00_578 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[5] 01_578 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[6] 00_579 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[7] 01_579 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[8] 00_580 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[9] 01_580 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[0] 00_584 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[1] 01_584 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[2] 00_585 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[3] 01_585 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[4] 00_586 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[5] 01_586 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[6] 00_587 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[7] 01_587 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[8] 00_588 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[9] 01_588 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[0] 00_592 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[1] 01_592 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[2] 00_593 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[3] 01_593 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[4] 00_594 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[5] 01_594 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[6] 00_595 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[7] 01_595 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[8] 00_596 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[9] 01_596 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[0] 00_600 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[1] 01_600 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[2] 00_601 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[3] 01_601 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[4] 00_602 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[5] 01_602 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[6] 00_603 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[7] 01_603 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[8] 00_604 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[9] 01_604 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_ENABLE[0] 00_581 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_ENABLE[1] 01_581 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_ENABLE[2] 00_582 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_ENABLE[3] 01_582 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_USE 00_583 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_LEN[0] 00_589 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_LEN[1] 01_589 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_CORRECT_USE 00_551 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.DEC_MCOMMA_DETECT 01_494 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.DEC_PCOMMA_DETECT 00_495 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.DEC_VALID_COMMA_ONLY 00_494 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[0] 02_368 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[1] 03_368 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[2] 02_369 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[3] 03_369 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[4] 02_370 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[5] 03_370 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[6] 02_371 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[7] 03_371 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[8] 02_372 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[9] 03_372 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[10] 02_373 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[11] 03_373 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[12] 02_374 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[13] 03_374 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[14] 02_375 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[15] 03_375 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[16] 02_376 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[17] 03_376 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[18] 02_377 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[19] 03_377 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[20] 02_378 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[21] 03_378 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[22] 02_379 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[23] 03_379 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_CLK_PHASE_SEL[0] 03_463 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_CONTROL[0] 00_488 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_CONTROL[1] 01_488 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_CONTROL[2] 00_489 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_CONTROL[3] 01_489 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_CONTROL[4] 00_490 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_CONTROL[5] 01_490 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_ERRDET_EN 01_492 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_EYE_SCAN_EN 00_492 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_HORZ_OFFSET[0] 00_480 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_HORZ_OFFSET[1] 01_480 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_HORZ_OFFSET[2] 00_481 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_HORZ_OFFSET[3] 01_481 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_HORZ_OFFSET[4] 00_482 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_HORZ_OFFSET[5] 01_482 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_HORZ_OFFSET[6] 00_483 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_HORZ_OFFSET[7] 01_483 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_HORZ_OFFSET[8] 00_484 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_HORZ_OFFSET[9] 01_484 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_HORZ_OFFSET[10] 00_485 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_HORZ_OFFSET[11] 01_485 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_PMA_CFG[0] 02_624 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_PMA_CFG[1] 03_624 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_PMA_CFG[2] 02_625 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_PMA_CFG[3] 03_625 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_PMA_CFG[4] 02_626 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_PMA_CFG[5] 03_626 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_PMA_CFG[6] 02_627 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_PMA_CFG[7] 03_627 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_PMA_CFG[8] 02_628 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_PMA_CFG[9] 03_628 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_PRESCALE[0] 01_477 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_PRESCALE[1] 00_478 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_PRESCALE[2] 01_478 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_PRESCALE[3] 00_479 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_PRESCALE[4] 01_479 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[0] 00_392 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[1] 01_392 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[2] 00_393 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[3] 01_393 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[4] 00_394 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[5] 01_394 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[6] 00_395 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[7] 01_395 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[8] 00_396 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[9] 01_396 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[10] 00_397 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[11] 01_397 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[12] 00_398 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[13] 01_398 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[14] 00_399 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[15] 01_399 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[16] 00_400 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[17] 01_400 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[18] 00_401 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[19] 01_401 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[20] 00_402 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[21] 01_402 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[22] 00_403 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[23] 01_403 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[24] 00_404 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[25] 01_404 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[26] 00_405 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[27] 01_405 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[28] 00_406 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[29] 01_406 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[30] 00_407 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[31] 01_407 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[32] 00_408 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[33] 01_408 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[34] 00_409 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[35] 01_409 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[36] 00_410 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[37] 01_410 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[38] 00_411 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[39] 01_411 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[40] 00_412 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[41] 01_412 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[42] 00_413 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[43] 01_413 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[44] 00_414 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[45] 01_414 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[46] 00_415 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[47] 01_415 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[48] 00_416 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[49] 01_416 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[50] 00_417 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[51] 01_417 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[52] 00_418 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[53] 01_418 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[54] 00_419 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[55] 01_419 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[56] 00_420 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[57] 01_420 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[58] 00_421 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[59] 01_421 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[60] 00_422 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[61] 01_422 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[62] 00_423 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[63] 01_423 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[64] 00_424 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[65] 01_424 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[66] 00_425 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[67] 01_425 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[68] 00_426 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[69] 01_426 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[70] 00_427 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[71] 01_427 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[72] 00_428 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[73] 01_428 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[74] 00_429 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[75] 01_429 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[76] 00_430 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[77] 01_430 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[78] 00_431 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[79] 01_431 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[0] 00_352 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[1] 01_352 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[2] 00_353 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[3] 01_353 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[4] 00_354 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[5] 01_354 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[6] 00_355 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[7] 01_355 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[8] 00_356 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[9] 01_356 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[10] 00_357 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[11] 01_357 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[12] 00_358 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[13] 01_358 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[14] 00_359 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[15] 01_359 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[16] 00_360 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[17] 01_360 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[18] 00_361 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[19] 01_361 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[20] 00_362 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[21] 01_362 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[22] 00_363 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[23] 01_363 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[24] 00_364 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[25] 01_364 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[26] 00_365 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[27] 01_365 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[28] 00_366 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[29] 01_366 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[30] 00_367 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[31] 01_367 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[32] 00_368 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[33] 01_368 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[34] 00_369 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[35] 01_369 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[36] 00_370 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[37] 01_370 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[38] 00_371 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[39] 01_371 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[40] 00_372 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[41] 01_372 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[42] 00_373 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[43] 01_373 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[44] 00_374 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[45] 01_374 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[46] 00_375 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[47] 01_375 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[48] 00_376 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[49] 01_376 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[50] 00_377 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[51] 01_377 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[52] 00_378 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[53] 01_378 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[54] 00_379 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[55] 01_379 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[56] 00_380 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[57] 01_380 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[58] 00_381 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[59] 01_381 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[60] 00_382 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[61] 01_382 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[62] 00_383 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[63] 01_383 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[64] 00_384 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[65] 01_384 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[66] 00_385 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[67] 01_385 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[68] 00_386 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[69] 01_386 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[70] 00_387 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[71] 01_387 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[72] 00_388 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[73] 01_388 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[74] 00_389 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[75] 01_389 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[76] 00_390 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[77] 01_390 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[78] 00_391 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[79] 01_391 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[0] 00_432 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[1] 01_432 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[2] 00_433 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[3] 01_433 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[4] 00_434 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[5] 01_434 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[6] 00_435 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[7] 01_435 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[8] 00_436 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[9] 01_436 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[10] 00_437 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[11] 01_437 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[12] 00_438 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[13] 01_438 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[14] 00_439 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[15] 01_439 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[16] 00_440 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[17] 01_440 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[18] 00_441 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[19] 01_441 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[20] 00_442 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[21] 01_442 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[22] 00_443 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[23] 01_443 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[24] 00_444 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[25] 01_444 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[26] 00_445 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[27] 01_445 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[28] 00_446 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[29] 01_446 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[30] 00_447 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[31] 01_447 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[32] 00_448 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[33] 01_448 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[34] 00_449 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[35] 01_449 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[36] 00_450 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[37] 01_450 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[38] 00_451 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[39] 01_451 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[40] 00_452 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[41] 01_452 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[42] 00_453 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[43] 01_453 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[44] 00_454 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[45] 01_454 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[46] 00_455 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[47] 01_455 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[48] 00_456 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[49] 01_456 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[50] 00_457 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[51] 01_457 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[52] 00_458 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[53] 01_458 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[54] 00_459 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[55] 01_459 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[56] 00_460 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[57] 01_460 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[58] 00_461 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[59] 01_461 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[60] 00_462 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[61] 01_462 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[62] 00_463 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[63] 01_463 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[64] 00_464 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[65] 01_464 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[66] 00_465 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[67] 01_465 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[68] 00_466 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[69] 01_466 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[70] 00_467 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[71] 01_467 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[72] 00_468 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[73] 01_468 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[74] 00_469 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[75] 01_469 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[76] 00_470 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[77] 01_470 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[78] 00_471 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[79] 01_471 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_VERT_OFFSET[0] 00_472 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_VERT_OFFSET[1] 01_472 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_VERT_OFFSET[2] 00_473 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_VERT_OFFSET[3] 01_473 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_VERT_OFFSET[4] 00_474 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_VERT_OFFSET[5] 01_474 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_VERT_OFFSET[6] 00_475 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_VERT_OFFSET[7] 01_475 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_VERT_OFFSET[8] 00_476 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.FTS_DESKEW_SEQ_ENABLE[0] 00_662 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.FTS_DESKEW_SEQ_ENABLE[1] 01_662 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.FTS_DESKEW_SEQ_ENABLE[2] 00_663 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.FTS_DESKEW_SEQ_ENABLE[3] 01_663 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.FTS_LANE_DESKEW_CFG[0] 00_654 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.FTS_LANE_DESKEW_CFG[1] 01_654 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.FTS_LANE_DESKEW_CFG[2] 00_655 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.FTS_LANE_DESKEW_CFG[3] 01_655 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.FTS_LANE_DESKEW_EN 01_653 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.GEARBOX_MODE[0] 00_224 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.GEARBOX_MODE[1] 01_224 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.GEARBOX_MODE[2] 00_225 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.IN_USE 00_00 00_01 00_47 00_52 00_53 00_65 01_01 01_47 02_129 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.INV_DMONITORCLK 02_13 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.INV_DRPCLK 02_00 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.INV_RXUSRCLK 03_01 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.INV_SIGVALIDCLK 03_13 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.INV_TXPHDLYTSTCLK 02_03 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.INV_TXUSRCLK 03_04 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.INV_CLKRSVD0 02_23 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.INV_CLKRSVD1 03_23 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.INV_RXUSRCLK2 02_02 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.INV_TXUSRCLK2 02_05 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.LOOPBACK_CFG[0] 02_20 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.OUTREFCLK_SEL_INV[0] 00_149 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.OUTREFCLK_SEL_INV[1] 01_149 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PCS_PCIE_EN 00_216 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[0] 02_184 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[1] 03_184 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[2] 02_185 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[3] 03_185 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[4] 02_186 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[5] 03_186 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[6] 02_187 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[7] 03_187 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[8] 02_188 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[9] 03_188 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[10] 02_189 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[11] 03_189 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[12] 02_190 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[13] 03_190 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[14] 02_191 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[15] 03_191 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[16] 02_192 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[17] 03_192 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[18] 02_193 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[19] 03_193 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[20] 02_194 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[21] 03_194 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[22] 02_195 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[23] 03_195 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[24] 02_196 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[25] 03_196 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[26] 02_197 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[27] 03_197 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[28] 02_198 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[29] 03_198 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[30] 02_199 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[31] 03_199 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[32] 02_200 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[33] 03_200 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[34] 02_201 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[35] 03_201 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[36] 02_202 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[37] 03_202 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[38] 02_203 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[39] 03_203 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[40] 02_204 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[41] 03_204 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[42] 02_205 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[43] 03_205 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[44] 02_206 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[45] 03_206 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[46] 02_207 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[47] 03_207 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[0] 01_216 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[1] 00_217 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[2] 01_217 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[3] 00_218 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[4] 01_218 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[5] 00_219 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[6] 01_219 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[7] 00_220 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[8] 01_220 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[9] 00_221 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[10] 01_221 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[11] 00_222 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[0] 00_208 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[1] 01_208 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[2] 00_209 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[3] 01_209 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[4] 00_210 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[5] 01_210 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[6] 00_211 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[7] 01_211 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[0] 00_212 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[1] 01_212 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[2] 00_213 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[3] 01_213 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[4] 00_214 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[5] 01_214 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[6] 00_215 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[7] 01_215 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PMA_LOOPBACK_CFG[0] 01_207 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[0] 02_520 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[1] 03_520 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[2] 02_521 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[3] 03_521 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[4] 02_522 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[5] 03_522 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[6] 02_523 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[7] 03_523 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[8] 02_524 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[9] 03_524 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[10] 02_525 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[11] 03_525 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[12] 02_526 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[13] 03_526 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[14] 02_527 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[15] 03_527 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[16] 02_528 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[17] 03_528 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[18] 02_529 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[19] 03_529 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[20] 02_530 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[21] 03_530 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[22] 02_531 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[23] 03_531 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[24] 02_532 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[25] 03_532 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[26] 02_533 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[27] 03_533 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[28] 02_534 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[29] 03_534 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[30] 02_535 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[31] 03_535 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[0] 02_336 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[1] 03_336 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[2] 02_337 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[3] 03_337 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[4] 02_338 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[5] 03_338 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[6] 02_339 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[7] 03_339 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[8] 02_340 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[9] 03_340 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[10] 02_341 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[11] 03_341 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[12] 02_342 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[13] 03_342 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[14] 02_343 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[15] 03_343 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[16] 02_344 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[17] 03_344 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[18] 02_345 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[19] 03_345 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[20] 02_346 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[21] 03_346 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[22] 02_347 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[23] 03_347 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[24] 02_348 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[25] 03_348 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[26] 02_349 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[27] 03_349 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[28] 02_350 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[29] 03_350 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[30] 02_351 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[31] 03_351 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV3[0] 02_288 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV3[1] 03_288 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV4[0] 02_156 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV4[1] 03_156 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV4[2] 02_157 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV4[3] 03_157 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV5[0] 03_159 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV6[0] 02_303 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV7[0] 03_303 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_BIAS_CFG[0] 02_112 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_BIAS_CFG[1] 03_112 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_BIAS_CFG[2] 02_113 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_BIAS_CFG[3] 03_113 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_BIAS_CFG[4] 02_114 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_BIAS_CFG[5] 03_114 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_BIAS_CFG[6] 02_115 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_BIAS_CFG[7] 03_115 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_BIAS_CFG[8] 02_116 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_BIAS_CFG[9] 03_116 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_BIAS_CFG[10] 02_117 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_BIAS_CFG[11] 03_117 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_BIAS_CFG[12] 02_118 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_BIAS_CFG[13] 03_118 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_BIAS_CFG[14] 02_119 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_BIAS_CFG[15] 03_119 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_BUFFER_CFG[0] 02_536 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_BUFFER_CFG[1] 03_536 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_BUFFER_CFG[2] 02_537 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_BUFFER_CFG[3] 03_537 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_BUFFER_CFG[4] 02_538 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_BUFFER_CFG[5] 03_538 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_CLKMUX_EN[0] 02_128 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_CM_SEL[0] 00_138 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_CM_SEL[1] 01_138 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_CM_TRIM[0] 02_304 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_CM_TRIM[1] 03_304 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_CM_TRIM[2] 02_305 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_CM_TRIM[3] 03_305 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_DATA_WIDTH[0] 01_141 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_DATA_WIDTH[1] 00_142 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_DATA_WIDTH[2] 01_142 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_DDI_SEL[0] 00_696 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_DDI_SEL[1] 01_696 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_DDI_SEL[2] 00_697 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_DDI_SEL[3] 01_697 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_DDI_SEL[4] 00_698 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_DDI_SEL[5] 01_698 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_DEBUG_CFG[0] 02_616 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_DEBUG_CFG[1] 03_616 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_DEBUG_CFG[2] 02_617 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_DEBUG_CFG[3] 03_617 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_DEBUG_CFG[4] 02_618 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_DEBUG_CFG[5] 03_618 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_DEBUG_CFG[6] 02_619 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_DEBUG_CFG[7] 03_619 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_DEBUG_CFG[8] 02_620 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_DEBUG_CFG[9] 03_620 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_DEBUG_CFG[10] 02_621 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_DEBUG_CFG[11] 03_621 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_DEBUG_CFG[12] 02_622 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_DEBUG_CFG[13] 03_622 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_DEFER_RESET_BUF_EN 02_552 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_DISPERR_SEQ_MATCH 01_495 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_OS_CFG[0] 00_288 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_OS_CFG[1] 01_288 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_OS_CFG[2] 00_289 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_OS_CFG[3] 01_289 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_OS_CFG[4] 00_290 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_OS_CFG[5] 01_290 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_OS_CFG[6] 00_291 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_OS_CFG[7] 01_291 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_OS_CFG[8] 00_292 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_OS_CFG[9] 01_292 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_OS_CFG[10] 00_293 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_OS_CFG[11] 01_293 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_OS_CFG[12] 00_294 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_SIG_VALID_DLY[0] 00_524 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_SIG_VALID_DLY[1] 01_524 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_SIG_VALID_DLY[2] 00_525 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_SIG_VALID_DLY[3] 01_525 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_SIG_VALID_DLY[4] 00_526 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_XCLK_SEL.RXUSR 00_143 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_CLK25_DIV[0] 00_139 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_CLK25_DIV[1] 01_139 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_CLK25_DIV[2] 00_140 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_CLK25_DIV[3] 01_140 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_CLK25_DIV[4] 00_141 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXBUF_ADDR_MODE.FAST 03_555 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXBUF_EIDLE_HI_CNT[0] 02_558 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXBUF_EIDLE_HI_CNT[1] 03_558 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXBUF_EIDLE_HI_CNT[2] 02_559 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXBUF_EIDLE_HI_CNT[3] 03_559 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXBUF_EIDLE_LO_CNT[0] 02_556 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXBUF_EIDLE_LO_CNT[1] 03_556 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXBUF_EIDLE_LO_CNT[2] 02_557 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXBUF_EIDLE_LO_CNT[3] 03_557 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXBUF_EN 02_11 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXBUF_RESET_ON_CB_CHANGE 02_560 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXBUF_RESET_ON_COMMAALIGN 02_561 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXBUF_RESET_ON_EIDLE 02_547 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXBUF_RESET_ON_RATE_CHANGE 03_560 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXBUF_THRESH_OVFLW[0] 03_552 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXBUF_THRESH_OVFLW[1] 02_553 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXBUF_THRESH_OVFLW[2] 03_553 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXBUF_THRESH_OVFLW[3] 02_554 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXBUF_THRESH_OVFLW[4] 03_554 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXBUF_THRESH_OVFLW[5] 02_555 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXBUF_THRESH_OVRD 02_548 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXBUF_THRESH_UNDFLW[0] 02_544 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXBUF_THRESH_UNDFLW[1] 03_544 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXBUF_THRESH_UNDFLW[2] 02_545 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXBUF_THRESH_UNDFLW[3] 03_545 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXBUF_THRESH_UNDFLW[4] 02_546 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXBUF_THRESH_UNDFLW[5] 03_546 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXBUFRESET_TIME[0] 01_101 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXBUFRESET_TIME[1] 00_102 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXBUFRESET_TIME[2] 01_102 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXBUFRESET_TIME[3] 00_103 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXBUFRESET_TIME[4] 01_103 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[0] 02_640 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[1] 03_640 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[2] 02_641 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[3] 03_641 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[4] 02_642 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[5] 03_642 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[6] 02_643 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[7] 03_643 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[8] 02_644 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[9] 03_644 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[10] 02_645 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[11] 03_645 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[12] 02_646 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[13] 03_646 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[14] 02_647 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[15] 03_647 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[16] 02_648 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[17] 03_648 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[18] 02_649 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[19] 03_649 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[20] 02_650 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[21] 03_650 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[22] 02_651 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[23] 03_651 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[24] 02_652 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[25] 03_652 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[26] 02_653 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[27] 03_653 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[28] 02_654 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[29] 03_654 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[30] 02_655 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[31] 03_655 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[32] 02_656 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[33] 03_656 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[34] 02_657 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[35] 03_657 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[36] 02_658 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[37] 03_658 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[38] 02_659 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[39] 03_659 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[40] 02_660 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[41] 03_660 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[42] 02_661 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[43] 03_661 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[44] 02_662 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[45] 03_662 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[46] 02_663 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[47] 03_663 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[48] 02_664 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[49] 03_664 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[50] 02_665 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[51] 03_665 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[52] 02_666 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[53] 03_666 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[54] 02_667 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[55] 03_667 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[56] 02_668 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[57] 03_668 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[58] 02_669 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[59] 03_669 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[60] 02_670 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[61] 03_670 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[62] 02_671 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[63] 03_671 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[64] 02_672 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[65] 03_672 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[66] 02_673 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[67] 03_673 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[68] 02_674 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[69] 03_674 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[70] 02_675 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[71] 03_675 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[72] 02_676 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[73] 03_676 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[74] 02_677 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[75] 03_677 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[76] 02_678 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[77] 03_678 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[78] 02_679 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[79] 03_679 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[80] 02_680 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[81] 03_680 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[82] 02_681 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_FR_RESET_ON_EIDLE[0] 02_638 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_HOLD_DURING_EIDLE[0] 03_637 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_LOCK_CFG[0] 02_632 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_LOCK_CFG[1] 03_632 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_LOCK_CFG[2] 02_633 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_LOCK_CFG[3] 03_633 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_LOCK_CFG[4] 02_634 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_LOCK_CFG[5] 03_634 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_PH_RESET_ON_EIDLE[0] 03_638 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDRFREQRESET_TIME[0] 01_106 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDRFREQRESET_TIME[1] 00_107 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDRFREQRESET_TIME[2] 01_107 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDRFREQRESET_TIME[3] 00_108 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDRFREQRESET_TIME[4] 01_108 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDRPHRESET_TIME[0] 00_109 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDRPHRESET_TIME[1] 01_109 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDRPHRESET_TIME[2] 00_110 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDRPHRESET_TIME[3] 01_110 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDRPHRESET_TIME[4] 00_111 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXDLY_CFG[0] 00_680 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXDLY_CFG[1] 01_680 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXDLY_CFG[2] 00_681 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXDLY_CFG[3] 01_681 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXDLY_CFG[4] 00_682 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXDLY_CFG[5] 01_682 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXDLY_CFG[6] 00_683 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXDLY_CFG[7] 01_683 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXDLY_CFG[8] 00_684 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXDLY_CFG[9] 01_684 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXDLY_CFG[10] 00_685 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXDLY_CFG[11] 01_685 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXDLY_CFG[12] 00_686 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXDLY_CFG[13] 01_686 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXDLY_CFG[14] 00_687 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXDLY_CFG[15] 01_687 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXDLY_LCFG[0] 02_576 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXDLY_LCFG[1] 03_576 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXDLY_LCFG[2] 02_577 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXDLY_LCFG[3] 03_577 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXDLY_LCFG[4] 02_578 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXDLY_LCFG[5] 03_578 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXDLY_LCFG[6] 02_579 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXDLY_LCFG[7] 03_579 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXDLY_LCFG[8] 02_580 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXDLY_TAP_CFG[0] 00_672 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXDLY_TAP_CFG[1] 01_672 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXDLY_TAP_CFG[2] 00_673 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXDLY_TAP_CFG[3] 01_673 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXDLY_TAP_CFG[4] 00_674 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXDLY_TAP_CFG[5] 01_674 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXDLY_TAP_CFG[6] 00_675 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXDLY_TAP_CFG[7] 01_675 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXDLY_TAP_CFG[8] 00_676 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXDLY_TAP_CFG[9] 01_676 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXDLY_TAP_CFG[10] 00_677 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXDLY_TAP_CFG[11] 01_677 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXDLY_TAP_CFG[12] 00_678 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXDLY_TAP_CFG[13] 01_678 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXDLY_TAP_CFG[14] 00_679 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXDLY_TAP_CFG[15] 01_679 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXGEARBOX_EN 01_607 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXISCANRESET_TIME[0] 01_123 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXISCANRESET_TIME[1] 00_124 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXISCANRESET_TIME[2] 01_124 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXISCANRESET_TIME[3] 00_125 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXISCANRESET_TIME[4] 01_125 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPM_BIAS_STARTUP_DISABLE[0] 03_391 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPM_CFG[0] 02_328 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPM_CFG[1] 03_328 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPM_CFG[2] 02_329 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPM_CFG[3] 03_329 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPM_CM_CFG[0] 02_430 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPM_GC_CFG[0] 02_432 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPM_GC_CFG[1] 03_432 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPM_GC_CFG[2] 02_433 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPM_GC_CFG[3] 03_433 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPM_GC_CFG[4] 02_434 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPM_GC_CFG[5] 03_434 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPM_GC_CFG[6] 02_435 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPM_GC_CFG[7] 03_435 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPM_GC_CFG[8] 02_436 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPM_GC_CFG2[0] 03_442 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPM_GC_CFG2[1] 02_443 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPM_GC_CFG2[2] 03_443 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG[0] 00_336 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG[1] 01_336 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG[2] 00_337 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG[3] 01_337 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG[4] 00_338 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG[5] 01_338 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG[6] 00_339 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG[7] 01_339 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG[8] 00_340 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG[9] 01_340 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG[10] 00_341 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG[11] 01_341 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG[12] 00_342 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG[13] 01_342 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG2[0] 02_424 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG2[1] 03_424 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG2[2] 02_425 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG2[3] 03_425 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG2[4] 02_426 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG3[0] 03_389 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG3[1] 02_390 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG3[2] 03_390 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG3[3] 02_391 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HOLD_DURING_EIDLE[0] 00_247 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPM_INCM_CFG[0] 02_439 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPM_IPCM_CFG[0] 03_439 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG[0] 00_344 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG[1] 01_344 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG[2] 00_345 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG[3] 01_345 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG[4] 00_346 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG[5] 01_346 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG[6] 00_347 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG[7] 01_347 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG[8] 00_348 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG[9] 01_348 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG[10] 00_349 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG[11] 01_349 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG[12] 00_350 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG[13] 01_350 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG[14] 00_351 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG[15] 01_351 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG[16] 00_343 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG[17] 01_343 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG2[0] 03_426 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG2[1] 02_427 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG2[2] 03_427 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG2[3] 02_428 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG2[4] 03_428 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPM_OSINT_CFG[0] 02_440 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPM_OSINT_CFG[1] 03_440 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPM_OSINT_CFG[2] 02_441 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPM_CFG1[0] 02_330 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPMRESET_TIME[0] 00_112 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPMRESET_TIME[1] 01_112 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPMRESET_TIME[2] 00_113 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPMRESET_TIME[3] 01_113 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPMRESET_TIME[4] 00_114 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPMRESET_TIME[5] 01_114 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPMRESET_TIME[6] 00_115 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXOOB_CFG[0] 00_144 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXOOB_CFG[1] 01_144 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXOOB_CFG[2] 00_145 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXOOB_CFG[3] 01_145 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXOOB_CFG[4] 00_146 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXOOB_CFG[5] 01_146 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXOOB_CFG[6] 00_147 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXOOB_CLK_CFG.FABRIC 03_129 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXOSCALRESET_TIME[0] 00_187 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXOSCALRESET_TIME[1] 01_187 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXOSCALRESET_TIME[2] 00_188 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXOSCALRESET_TIME[3] 01_188 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXOSCALRESET_TIME[4] 00_189 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXOSCALRESET_TIMEOUT[0] 01_189 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXOSCALRESET_TIMEOUT[1] 00_190 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXOSCALRESET_TIMEOUT[2] 01_190 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXOSCALRESET_TIMEOUT[3] 00_191 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXOSCALRESET_TIMEOUT[4] 01_191 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXOUT_DIV[0] 02_384 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXOUT_DIV[1] 03_384 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXPCSRESET_TIME[0] 01_115 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXPCSRESET_TIME[1] 00_116 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXPCSRESET_TIME[2] 01_116 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXPCSRESET_TIME[3] 00_117 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXPCSRESET_TIME[4] 01_117 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[0] 02_584 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[1] 03_584 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[2] 02_585 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[3] 03_585 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[4] 02_586 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[5] 03_586 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[6] 02_587 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[7] 03_587 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[8] 02_588 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[9] 03_588 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[10] 02_589 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[11] 03_589 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[12] 02_590 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[13] 03_590 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[14] 02_591 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[15] 03_591 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[16] 02_592 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[17] 03_592 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[18] 02_593 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[19] 03_593 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[20] 02_594 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[21] 03_594 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[22] 02_595 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[23] 03_595 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXPH_MONITOR_SEL[0] 00_700 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXPH_MONITOR_SEL[1] 01_700 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXPH_MONITOR_SEL[2] 00_701 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXPH_MONITOR_SEL[3] 01_701 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXPH_MONITOR_SEL[4] 00_702 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[0] 02_600 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[1] 03_600 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[2] 02_601 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[3] 03_601 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[4] 02_602 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[5] 03_602 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[6] 02_603 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[7] 03_603 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[8] 02_604 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[9] 03_604 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[10] 02_605 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[11] 03_605 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[12] 02_606 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[13] 03_606 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[14] 02_607 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[15] 03_607 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[16] 02_608 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[17] 03_608 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[18] 02_609 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[19] 03_609 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[20] 02_610 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[21] 03_610 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[22] 02_611 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[23] 03_611 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXPI_CFG0[0] 03_430 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXPI_CFG0[1] 02_431 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXPI_CFG0[2] 03_431 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXPI_CFG1[0] 02_442 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXPI_CFG2[0] 03_441 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXPMARESET_TIME[0] 00_104 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXPMARESET_TIME[1] 01_104 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXPMARESET_TIME[2] 00_105 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXPMARESET_TIME[3] 01_105 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXPMARESET_TIME[4] 00_106 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXPRBS_ERR_LOOPBACK[0] 00_136 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXSLIDE_AUTO_WAIT[0] 00_520 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXSLIDE_AUTO_WAIT[1] 01_520 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXSLIDE_AUTO_WAIT[2] 00_521 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXSLIDE_AUTO_WAIT[3] 01_521 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXSLIDE_MODE.AUTO 00_519 !01_519 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXSLIDE_MODE.PCS !00_519 01_519 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXSLIDE_MODE.PMA 00_519 01_519 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXSYNC_MULTILANE[0] 00_133 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXSYNC_OVRD[0] 01_135 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXSYNC_SKIP_DA[0] 01_134 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.SAS_MAX_COM[0] 00_171 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.SAS_MAX_COM[1] 01_171 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.SAS_MAX_COM[2] 00_172 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.SAS_MAX_COM[3] 01_172 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.SAS_MAX_COM[4] 00_173 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.SAS_MAX_COM[5] 01_173 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.SAS_MAX_COM[6] 00_174 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.SAS_MIN_COM[0] 01_156 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.SAS_MIN_COM[1] 00_157 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.SAS_MIN_COM[2] 01_157 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.SAS_MIN_COM[3] 00_158 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.SAS_MIN_COM[4] 01_158 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.SAS_MIN_COM[5] 00_159 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.SATA_BURST_SEQ_LEN[0] 00_150 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.SATA_BURST_SEQ_LEN[1] 01_150 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.SATA_BURST_SEQ_LEN[2] 00_151 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.SATA_BURST_SEQ_LEN[3] 01_151 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.SATA_BURST_VAL[0] 01_147 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.SATA_BURST_VAL[1] 00_148 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.SATA_BURST_VAL[2] 01_148 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.SATA_EIDLE_VAL[0] 00_152 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.SATA_EIDLE_VAL[1] 01_152 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.SATA_EIDLE_VAL[2] 00_153 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.SATA_MAX_BURST[0] 00_168 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.SATA_MAX_BURST[1] 01_168 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.SATA_MAX_BURST[2] 00_169 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.SATA_MAX_BURST[3] 01_169 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.SATA_MAX_BURST[4] 00_170 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.SATA_MAX_BURST[5] 01_170 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.SATA_MAX_INIT[0] 00_176 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.SATA_MAX_INIT[1] 01_176 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.SATA_MAX_INIT[2] 00_177 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.SATA_MAX_INIT[3] 01_177 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.SATA_MAX_INIT[4] 00_178 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.SATA_MAX_INIT[5] 01_178 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.SATA_MAX_WAKE[0] 00_179 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.SATA_MAX_WAKE[1] 01_179 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.SATA_MAX_WAKE[2] 00_180 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.SATA_MAX_WAKE[3] 01_180 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.SATA_MAX_WAKE[4] 00_181 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.SATA_MAX_WAKE[5] 01_181 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.SATA_MIN_BURST[0] 01_153 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.SATA_MIN_BURST[1] 00_154 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.SATA_MIN_BURST[2] 01_154 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.SATA_MIN_BURST[3] 00_155 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.SATA_MIN_BURST[4] 01_155 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.SATA_MIN_BURST[5] 00_156 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.SATA_MIN_INIT[0] 00_160 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.SATA_MIN_INIT[1] 01_160 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.SATA_MIN_INIT[2] 00_161 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.SATA_MIN_INIT[3] 01_161 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.SATA_MIN_INIT[4] 00_162 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.SATA_MIN_INIT[5] 01_162 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.SATA_MIN_WAKE[0] 00_163 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.SATA_MIN_WAKE[1] 01_163 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.SATA_MIN_WAKE[2] 00_164 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.SATA_MIN_WAKE[3] 01_164 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.SATA_MIN_WAKE[4] 00_165 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.SATA_MIN_WAKE[5] 01_165 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.SATA_PLL_CFG.VCO_1500MHZ 02_55 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.SATA_PLL_CFG.VCO_750MHZ 03_55 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.SHOW_REALIGN_COMMA 01_522 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TERM_RCAL_CFG[0] 02_136 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TERM_RCAL_CFG[1] 03_136 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TERM_RCAL_CFG[2] 02_137 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TERM_RCAL_CFG[3] 03_137 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TERM_RCAL_CFG[4] 02_138 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TERM_RCAL_CFG[5] 03_138 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TERM_RCAL_CFG[6] 02_139 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TERM_RCAL_CFG[7] 03_139 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TERM_RCAL_CFG[8] 02_140 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TERM_RCAL_CFG[9] 03_140 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TERM_RCAL_CFG[10] 02_141 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TERM_RCAL_CFG[11] 03_141 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TERM_RCAL_CFG[12] 02_142 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TERM_RCAL_CFG[13] 03_142 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TERM_RCAL_CFG[14] 02_143 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TERM_RCAL_OVRD[0] 03_150 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TERM_RCAL_OVRD[1] 02_151 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TERM_RCAL_OVRD[2] 03_151 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TRANS_TIME_RATE[0] 00_192 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TRANS_TIME_RATE[1] 01_192 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TRANS_TIME_RATE[2] 00_193 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TRANS_TIME_RATE[3] 01_193 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TRANS_TIME_RATE[4] 00_194 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TRANS_TIME_RATE[5] 01_194 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TRANS_TIME_RATE[6] 00_195 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TRANS_TIME_RATE[7] 01_195 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[0] 02_504 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[1] 03_504 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[2] 02_505 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[3] 03_505 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[4] 02_506 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[5] 03_506 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[6] 02_507 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[7] 03_507 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[8] 02_508 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[9] 03_508 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[10] 02_509 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[11] 03_509 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[12] 02_510 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[13] 03_510 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[14] 02_511 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[15] 03_511 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[16] 02_512 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[17] 03_512 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[18] 02_513 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[19] 03_513 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[20] 02_514 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[21] 03_514 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[22] 02_515 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[23] 03_515 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[24] 02_516 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[25] 03_516 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[26] 02_517 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[27] 03_517 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[28] 02_518 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[29] 03_518 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[30] 02_519 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[31] 03_519 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_CLKMUX_EN[0] 03_128 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_DATA_WIDTH[0] 02_152 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_DATA_WIDTH[1] 03_152 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_DATA_WIDTH[2] 02_153 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_DRIVE_MODE.PIPE 00_200 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_EIDLE_ASSERT_DELAY[0] 00_203 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_EIDLE_ASSERT_DELAY[1] 01_203 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_EIDLE_ASSERT_DELAY[2] 00_204 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_EIDLE_DEASSERT_DELAY[0] 01_204 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_EIDLE_DEASSERT_DELAY[1] 00_205 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_EIDLE_DEASSERT_DELAY[2] 01_205 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_LOOPBACK_DRIVE_HIZ 01_202 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_MAINCURSOR_SEL[0] 03_289 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_0[0] 02_232 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_0[1] 03_232 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_0[2] 02_233 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_0[3] 03_233 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_0[4] 02_234 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_0[5] 03_234 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_0[6] 02_235 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_1[0] 02_236 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_1[1] 03_236 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_1[2] 02_237 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_1[3] 03_237 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_1[4] 02_238 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_1[5] 03_238 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_1[6] 02_239 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_2[0] 02_240 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_2[1] 03_240 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_2[2] 02_241 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_2[3] 03_241 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_2[4] 02_242 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_2[5] 03_242 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_2[6] 02_243 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_3[0] 02_244 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_3[1] 03_244 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_3[2] 02_245 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_3[3] 03_245 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_3[4] 02_246 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_3[5] 03_246 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_3[6] 02_247 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_4[0] 02_248 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_4[1] 03_248 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_4[2] 02_249 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_4[3] 03_249 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_4[4] 02_250 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_4[5] 03_250 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_4[6] 02_251 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_0[0] 02_252 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_0[1] 03_252 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_0[2] 02_253 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_0[3] 03_253 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_0[4] 02_254 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_0[5] 03_254 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_0[6] 02_255 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_1[0] 02_256 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_1[1] 03_256 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_1[2] 02_257 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_1[3] 03_257 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_1[4] 02_258 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_1[5] 03_258 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_1[6] 02_259 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_2[0] 02_260 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_2[1] 03_260 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_2[2] 02_261 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_2[3] 03_261 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_2[4] 02_262 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_2[5] 03_262 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_2[6] 02_263 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_3[0] 02_264 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_3[1] 03_264 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_3[2] 02_265 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_3[3] 03_265 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_3[4] 02_266 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_3[5] 03_266 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_3[6] 02_267 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_4[0] 02_268 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_4[1] 03_268 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_4[2] 02_269 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_4[3] 03_269 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_4[4] 02_270 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_4[5] 03_270 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_4[6] 02_271 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_PREDRIVER_MODE[0] 00_206 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_RXDETECT_CFG[0] 02_296 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_RXDETECT_CFG[1] 03_296 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_RXDETECT_CFG[2] 02_297 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_RXDETECT_CFG[3] 03_297 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_RXDETECT_CFG[4] 02_298 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_RXDETECT_CFG[5] 03_298 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_RXDETECT_CFG[6] 02_299 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_RXDETECT_CFG[7] 03_299 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_RXDETECT_CFG[8] 02_300 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_RXDETECT_CFG[9] 03_300 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_RXDETECT_CFG[10] 02_301 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_RXDETECT_CFG[11] 03_301 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_RXDETECT_CFG[12] 02_302 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_RXDETECT_CFG[13] 03_302 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_RXDETECT_REF[0] 02_292 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_RXDETECT_REF[1] 03_292 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_RXDETECT_REF[2] 02_293 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_XCLK_SEL.TXUSR 03_11 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_CLK25_DIV[0] 02_144 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_CLK25_DIV[1] 03_144 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_CLK25_DIV[2] 02_145 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_CLK25_DIV[3] 03_145 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_CLK25_DIV[4] 02_146 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_DEEMPH0[0] 02_272 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_DEEMPH0[1] 03_272 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_DEEMPH0[2] 02_273 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_DEEMPH0[3] 03_273 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_DEEMPH0[4] 02_274 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_DEEMPH0[5] 03_274 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_DEEMPH1[0] 02_276 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_DEEMPH1[1] 03_276 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_DEEMPH1[2] 02_277 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_DEEMPH1[3] 03_277 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_DEEMPH1[4] 02_278 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_DEEMPH1[5] 03_278 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXBUF_EN 00_231 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXBUF_RESET_ON_RATE_CHANGE 01_231 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXDLY_CFG[0] 02_80 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXDLY_CFG[1] 03_80 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXDLY_CFG[2] 02_81 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXDLY_CFG[3] 03_81 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXDLY_CFG[4] 02_82 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXDLY_CFG[5] 03_82 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXDLY_CFG[6] 02_83 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXDLY_CFG[7] 03_83 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXDLY_CFG[8] 02_84 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXDLY_CFG[9] 03_84 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXDLY_CFG[10] 02_85 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXDLY_CFG[11] 03_85 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXDLY_CFG[12] 02_86 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXDLY_CFG[13] 03_86 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXDLY_CFG[14] 02_87 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXDLY_CFG[15] 03_87 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXDLY_LCFG[0] 02_568 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXDLY_LCFG[1] 03_568 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXDLY_LCFG[2] 02_569 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXDLY_LCFG[3] 03_569 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXDLY_LCFG[4] 02_570 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXDLY_LCFG[5] 03_570 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXDLY_LCFG[6] 02_571 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXDLY_LCFG[7] 03_571 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXDLY_LCFG[8] 02_572 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXDLY_TAP_CFG[0] 02_88 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXDLY_TAP_CFG[1] 03_88 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXDLY_TAP_CFG[2] 02_89 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXDLY_TAP_CFG[3] 03_89 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXDLY_TAP_CFG[4] 02_90 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXDLY_TAP_CFG[5] 03_90 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXDLY_TAP_CFG[6] 02_91 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXDLY_TAP_CFG[7] 03_91 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXDLY_TAP_CFG[8] 02_92 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXDLY_TAP_CFG[9] 03_92 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXDLY_TAP_CFG[10] 02_93 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXDLY_TAP_CFG[11] 03_93 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXDLY_TAP_CFG[12] 02_94 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXDLY_TAP_CFG[13] 03_94 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXDLY_TAP_CFG[14] 02_95 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXDLY_TAP_CFG[15] 03_95 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXGEARBOX_EN 01_226 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXOOB_CFG[0] 03_20 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXOUT_DIV[0] 02_386 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXOUT_DIV[1] 03_386 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPCSRESET_TIME[0] 01_130 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPCSRESET_TIME[1] 00_131 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPCSRESET_TIME[2] 01_131 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPCSRESET_TIME[3] 00_132 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPCSRESET_TIME[4] 01_132 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPH_CFG[0] 02_96 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPH_CFG[1] 03_96 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPH_CFG[2] 02_97 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPH_CFG[3] 03_97 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPH_CFG[4] 02_98 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPH_CFG[5] 03_98 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPH_CFG[6] 02_99 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPH_CFG[7] 03_99 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPH_CFG[8] 02_100 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPH_CFG[9] 03_100 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPH_CFG[10] 02_101 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPH_CFG[11] 03_101 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPH_CFG[12] 02_102 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPH_CFG[13] 03_102 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPH_CFG[14] 02_103 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPH_CFG[15] 03_103 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPH_MONITOR_SEL[0] 02_108 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPH_MONITOR_SEL[1] 03_108 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPH_MONITOR_SEL[2] 02_109 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPH_MONITOR_SEL[3] 03_109 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPH_MONITOR_SEL[4] 02_110 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[0] 02_64 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[1] 03_64 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[2] 02_65 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[3] 03_65 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[4] 02_66 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[5] 03_66 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[6] 02_67 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[7] 03_67 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[8] 02_68 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[9] 03_68 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[10] 02_69 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[11] 03_69 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[12] 02_70 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[13] 03_70 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[14] 02_71 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[15] 03_71 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[16] 02_72 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[17] 03_72 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[18] 02_73 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[19] 03_73 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[20] 02_74 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[21] 03_74 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[22] 02_75 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[23] 03_75 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPI_GREY_SEL[0] 03_498 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPI_INVSTROBE_SEL[0] 02_498 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPI_PPM_CFG[0] 02_488 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPI_PPM_CFG[1] 03_488 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPI_PPM_CFG[2] 02_489 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPI_PPM_CFG[3] 03_489 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPI_PPM_CFG[4] 02_490 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPI_PPM_CFG[5] 03_490 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPI_PPM_CFG[6] 02_491 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPI_PPM_CFG[7] 03_491 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPI_PPMCLK_SEL.TXUSRCLK2 03_497 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPI_SYNFREQ_PPM[0] 02_496 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPI_SYNFREQ_PPM[1] 03_496 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPI_SYNFREQ_PPM[2] 02_497 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPI_CFG0[0] 02_40 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPI_CFG0[1] 03_40 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPI_CFG1[0] 02_41 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPI_CFG1[1] 03_41 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPI_CFG2[0] 02_42 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPI_CFG2[1] 03_42 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPI_CFG3[0] 02_43 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPI_CFG4[0] 03_43 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPI_CFG5[0] 02_44 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPI_CFG5[1] 03_44 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPI_CFG5[2] 02_45 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPMARESET_TIME[0] 00_128 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPMARESET_TIME[1] 01_128 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPMARESET_TIME[2] 00_129 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPMARESET_TIME[3] 01_129 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPMARESET_TIME[4] 00_130 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXSYNC_MULTILANE[0] 01_133 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXSYNC_OVRD[0] 00_135 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXSYNC_SKIP_DA[0] 00_134 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.UCODEER_CLR[0] 01_00 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.USE_PCS_CLK_PHASE_SEL[0] 02_463 diff --git a/artix7/segbits_gtp_channel_0_mid_right.origin_info.db b/artix7/segbits_gtp_channel_0_mid_right.origin_info.db index 856b8cf..13ed43d 100644 --- a/artix7/segbits_gtp_channel_0_mid_right.origin_info.db +++ b/artix7/segbits_gtp_channel_0_mid_right.origin_info.db @@ -1,1627 +1,1627 @@ -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ACJTAG_DEBUG_MODE[0] origin:064-gtp-channel-conf 00_07 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ACJTAG_MODE[0] origin:064-gtp-channel-conf 01_06 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ACJTAG_RESET[0] origin:064-gtp-channel-conf 01_07 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ADAPT_CFG0[0] origin:064-gtp-channel-conf 02_464 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ADAPT_CFG0[1] origin:064-gtp-channel-conf 03_464 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ADAPT_CFG0[2] origin:064-gtp-channel-conf 02_465 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ADAPT_CFG0[3] origin:064-gtp-channel-conf 03_465 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ADAPT_CFG0[4] origin:064-gtp-channel-conf 02_466 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ADAPT_CFG0[5] origin:064-gtp-channel-conf 03_466 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ADAPT_CFG0[6] origin:064-gtp-channel-conf 02_467 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ADAPT_CFG0[7] origin:064-gtp-channel-conf 03_467 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ADAPT_CFG0[8] origin:064-gtp-channel-conf 02_468 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ADAPT_CFG0[9] origin:064-gtp-channel-conf 03_468 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ADAPT_CFG0[10] origin:064-gtp-channel-conf 02_469 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ADAPT_CFG0[11] origin:064-gtp-channel-conf 03_469 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ADAPT_CFG0[12] origin:064-gtp-channel-conf 02_470 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ADAPT_CFG0[13] origin:064-gtp-channel-conf 03_470 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ADAPT_CFG0[14] origin:064-gtp-channel-conf 02_471 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ADAPT_CFG0[15] origin:064-gtp-channel-conf 03_471 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ADAPT_CFG0[16] origin:064-gtp-channel-conf 02_472 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ADAPT_CFG0[17] origin:064-gtp-channel-conf 03_472 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ADAPT_CFG0[18] origin:064-gtp-channel-conf 02_473 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ADAPT_CFG0[19] origin:064-gtp-channel-conf 03_473 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ALIGN_COMMA_DOUBLE origin:064-gtp-channel-conf 00_522 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ALIGN_COMMA_ENABLE[0] origin:064-gtp-channel-conf 00_496 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ALIGN_COMMA_ENABLE[1] origin:064-gtp-channel-conf 01_496 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ALIGN_COMMA_ENABLE[2] origin:064-gtp-channel-conf 00_497 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ALIGN_COMMA_ENABLE[3] origin:064-gtp-channel-conf 01_497 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ALIGN_COMMA_ENABLE[4] origin:064-gtp-channel-conf 00_498 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ALIGN_COMMA_ENABLE[5] origin:064-gtp-channel-conf 01_498 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ALIGN_COMMA_ENABLE[6] origin:064-gtp-channel-conf 00_499 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ALIGN_COMMA_ENABLE[7] origin:064-gtp-channel-conf 01_499 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ALIGN_COMMA_ENABLE[8] origin:064-gtp-channel-conf 00_500 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ALIGN_COMMA_ENABLE[9] origin:064-gtp-channel-conf 01_500 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ALIGN_COMMA_WORD[0] origin:064-gtp-channel-conf 01_526 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ALIGN_COMMA_WORD[1] origin:064-gtp-channel-conf 00_527 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ALIGN_MCOMMA_DET origin:064-gtp-channel-conf 00_523 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ALIGN_MCOMMA_VALUE[0] origin:064-gtp-channel-conf 00_504 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ALIGN_MCOMMA_VALUE[1] origin:064-gtp-channel-conf 01_504 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ALIGN_MCOMMA_VALUE[2] origin:064-gtp-channel-conf 00_505 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ALIGN_MCOMMA_VALUE[3] origin:064-gtp-channel-conf 01_505 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ALIGN_MCOMMA_VALUE[4] origin:064-gtp-channel-conf 00_506 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ALIGN_MCOMMA_VALUE[5] origin:064-gtp-channel-conf 01_506 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ALIGN_MCOMMA_VALUE[6] origin:064-gtp-channel-conf 00_507 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ALIGN_MCOMMA_VALUE[7] origin:064-gtp-channel-conf 01_507 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ALIGN_MCOMMA_VALUE[8] origin:064-gtp-channel-conf 00_508 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ALIGN_MCOMMA_VALUE[9] origin:064-gtp-channel-conf 01_508 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ALIGN_PCOMMA_DET origin:064-gtp-channel-conf 01_523 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ALIGN_PCOMMA_VALUE[0] origin:064-gtp-channel-conf 00_512 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ALIGN_PCOMMA_VALUE[1] origin:064-gtp-channel-conf 01_512 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ALIGN_PCOMMA_VALUE[2] origin:064-gtp-channel-conf 00_513 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ALIGN_PCOMMA_VALUE[3] origin:064-gtp-channel-conf 01_513 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ALIGN_PCOMMA_VALUE[4] origin:064-gtp-channel-conf 00_514 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ALIGN_PCOMMA_VALUE[5] origin:064-gtp-channel-conf 01_514 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ALIGN_PCOMMA_VALUE[6] origin:064-gtp-channel-conf 00_515 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ALIGN_PCOMMA_VALUE[7] origin:064-gtp-channel-conf 01_515 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ALIGN_PCOMMA_VALUE[8] origin:064-gtp-channel-conf 00_516 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ALIGN_PCOMMA_VALUE[9] origin:064-gtp-channel-conf 01_516 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CBCC_DATA_SOURCE_SEL.DECODED origin:064-gtp-channel-conf 01_661 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CFOK_CFG[0] origin:064-gtp-channel-conf 02_392 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CFOK_CFG[1] origin:064-gtp-channel-conf 03_392 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CFOK_CFG[2] origin:064-gtp-channel-conf 02_393 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CFOK_CFG[3] origin:064-gtp-channel-conf 03_393 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CFOK_CFG[4] origin:064-gtp-channel-conf 02_394 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CFOK_CFG[5] origin:064-gtp-channel-conf 03_394 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CFOK_CFG[6] origin:064-gtp-channel-conf 02_395 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CFOK_CFG[7] origin:064-gtp-channel-conf 03_395 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CFOK_CFG[8] origin:064-gtp-channel-conf 02_396 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CFOK_CFG[9] origin:064-gtp-channel-conf 03_396 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CFOK_CFG[10] origin:064-gtp-channel-conf 02_397 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CFOK_CFG[11] origin:064-gtp-channel-conf 03_397 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CFOK_CFG[12] origin:064-gtp-channel-conf 02_398 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CFOK_CFG[13] origin:064-gtp-channel-conf 03_398 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CFOK_CFG[14] origin:064-gtp-channel-conf 02_399 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CFOK_CFG[15] origin:064-gtp-channel-conf 03_399 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CFOK_CFG[16] origin:064-gtp-channel-conf 02_400 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CFOK_CFG[17] origin:064-gtp-channel-conf 03_400 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CFOK_CFG[18] origin:064-gtp-channel-conf 02_401 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CFOK_CFG[19] origin:064-gtp-channel-conf 03_401 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CFOK_CFG[20] origin:064-gtp-channel-conf 02_402 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CFOK_CFG[21] origin:064-gtp-channel-conf 03_402 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CFOK_CFG[22] origin:064-gtp-channel-conf 02_403 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CFOK_CFG[23] origin:064-gtp-channel-conf 03_403 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CFOK_CFG[24] origin:064-gtp-channel-conf 02_404 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CFOK_CFG[25] origin:064-gtp-channel-conf 03_404 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CFOK_CFG[26] origin:064-gtp-channel-conf 02_405 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CFOK_CFG[27] origin:064-gtp-channel-conf 03_405 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CFOK_CFG[28] origin:064-gtp-channel-conf 02_406 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CFOK_CFG[29] origin:064-gtp-channel-conf 03_406 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CFOK_CFG[30] origin:064-gtp-channel-conf 02_407 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CFOK_CFG[31] origin:064-gtp-channel-conf 03_407 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CFOK_CFG[32] origin:064-gtp-channel-conf 02_408 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CFOK_CFG[33] origin:064-gtp-channel-conf 03_408 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CFOK_CFG[34] origin:064-gtp-channel-conf 02_409 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CFOK_CFG[35] origin:064-gtp-channel-conf 03_409 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CFOK_CFG[36] origin:064-gtp-channel-conf 02_410 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CFOK_CFG[37] origin:064-gtp-channel-conf 03_410 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CFOK_CFG[38] origin:064-gtp-channel-conf 02_411 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CFOK_CFG[39] origin:064-gtp-channel-conf 03_411 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CFOK_CFG[40] origin:064-gtp-channel-conf 02_412 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CFOK_CFG[41] origin:064-gtp-channel-conf 03_412 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CFOK_CFG[42] origin:064-gtp-channel-conf 02_413 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CFOK_CFG2[0] origin:064-gtp-channel-conf 02_459 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CFOK_CFG2[1] origin:064-gtp-channel-conf 03_459 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CFOK_CFG2[2] origin:064-gtp-channel-conf 02_460 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CFOK_CFG2[3] origin:064-gtp-channel-conf 03_460 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CFOK_CFG2[4] origin:064-gtp-channel-conf 02_461 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CFOK_CFG2[5] origin:064-gtp-channel-conf 03_461 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CFOK_CFG2[6] origin:064-gtp-channel-conf 02_462 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CFOK_CFG3[0] origin:064-gtp-channel-conf 02_416 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CFOK_CFG3[1] origin:064-gtp-channel-conf 03_416 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CFOK_CFG3[2] origin:064-gtp-channel-conf 02_417 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CFOK_CFG3[3] origin:064-gtp-channel-conf 03_417 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CFOK_CFG3[4] origin:064-gtp-channel-conf 02_418 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CFOK_CFG3[5] origin:064-gtp-channel-conf 03_418 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CFOK_CFG3[6] origin:064-gtp-channel-conf 02_419 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CFOK_CFG4[0] origin:064-gtp-channel-conf 03_438 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CFOK_CFG5[0] origin:064-gtp-channel-conf 02_429 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CFOK_CFG5[1] origin:064-gtp-channel-conf 03_429 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CFOK_CFG6[0] origin:064-gtp-channel-conf 03_436 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CFOK_CFG6[1] origin:064-gtp-channel-conf 02_437 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CFOK_CFG6[2] origin:064-gtp-channel-conf 03_437 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CFOK_CFG6[3] origin:064-gtp-channel-conf 02_438 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_KEEP_ALIGN origin:064-gtp-channel-conf 01_631 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_MAX_SKEW[0] origin:064-gtp-channel-conf 00_670 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_MAX_SKEW[1] origin:064-gtp-channel-conf 01_670 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_MAX_SKEW[2] origin:064-gtp-channel-conf 00_671 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_MAX_SKEW[3] origin:064-gtp-channel-conf 01_671 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_1[0] origin:064-gtp-channel-conf 00_608 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_1[1] origin:064-gtp-channel-conf 01_608 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_1[2] origin:064-gtp-channel-conf 00_609 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_1[3] origin:064-gtp-channel-conf 01_609 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_1[4] origin:064-gtp-channel-conf 00_610 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_1[5] origin:064-gtp-channel-conf 01_610 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_1[6] origin:064-gtp-channel-conf 00_611 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_1[7] origin:064-gtp-channel-conf 01_611 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_1[8] origin:064-gtp-channel-conf 00_612 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_1[9] origin:064-gtp-channel-conf 01_612 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_2[0] origin:064-gtp-channel-conf 00_616 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_2[1] origin:064-gtp-channel-conf 01_616 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_2[2] origin:064-gtp-channel-conf 00_617 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_2[3] origin:064-gtp-channel-conf 01_617 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_2[4] origin:064-gtp-channel-conf 00_618 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_2[5] origin:064-gtp-channel-conf 01_618 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_2[6] origin:064-gtp-channel-conf 00_619 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_2[7] origin:064-gtp-channel-conf 01_619 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_2[8] origin:064-gtp-channel-conf 00_620 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_2[9] origin:064-gtp-channel-conf 01_620 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_3[0] origin:064-gtp-channel-conf 00_624 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_3[1] origin:064-gtp-channel-conf 01_624 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_3[2] origin:064-gtp-channel-conf 00_625 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_3[3] origin:064-gtp-channel-conf 01_625 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_3[4] origin:064-gtp-channel-conf 00_626 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_3[5] origin:064-gtp-channel-conf 01_626 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_3[6] origin:064-gtp-channel-conf 00_627 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_3[7] origin:064-gtp-channel-conf 01_627 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_3[8] origin:064-gtp-channel-conf 00_628 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_3[9] origin:064-gtp-channel-conf 01_628 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_4[0] origin:064-gtp-channel-conf 00_632 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_4[1] origin:064-gtp-channel-conf 01_632 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_4[2] origin:064-gtp-channel-conf 00_633 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_4[3] origin:064-gtp-channel-conf 01_633 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_4[4] origin:064-gtp-channel-conf 00_634 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_4[5] origin:064-gtp-channel-conf 01_634 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_4[6] origin:064-gtp-channel-conf 00_635 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_4[7] origin:064-gtp-channel-conf 01_635 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_4[8] origin:064-gtp-channel-conf 00_636 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_4[9] origin:064-gtp-channel-conf 01_636 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_ENABLE[0] origin:064-gtp-channel-conf 00_614 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_ENABLE[1] origin:064-gtp-channel-conf 01_614 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_ENABLE[2] origin:064-gtp-channel-conf 00_615 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_ENABLE[3] origin:064-gtp-channel-conf 01_615 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_1[0] origin:064-gtp-channel-conf 00_640 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_1[1] origin:064-gtp-channel-conf 01_640 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_1[2] origin:064-gtp-channel-conf 00_641 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_1[3] origin:064-gtp-channel-conf 01_641 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_1[4] origin:064-gtp-channel-conf 00_642 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_1[5] origin:064-gtp-channel-conf 01_642 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_1[6] origin:064-gtp-channel-conf 00_643 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_1[7] origin:064-gtp-channel-conf 01_643 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_1[8] origin:064-gtp-channel-conf 00_644 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_1[9] origin:064-gtp-channel-conf 01_644 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_2[0] origin:064-gtp-channel-conf 00_648 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_2[1] origin:064-gtp-channel-conf 01_648 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_2[2] origin:064-gtp-channel-conf 00_649 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_2[3] origin:064-gtp-channel-conf 01_649 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_2[4] origin:064-gtp-channel-conf 00_650 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_2[5] origin:064-gtp-channel-conf 01_650 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_2[6] origin:064-gtp-channel-conf 00_651 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_2[7] origin:064-gtp-channel-conf 01_651 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_2[8] origin:064-gtp-channel-conf 00_652 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_2[9] origin:064-gtp-channel-conf 01_652 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_3[0] origin:064-gtp-channel-conf 00_656 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_3[1] origin:064-gtp-channel-conf 01_656 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_3[2] origin:064-gtp-channel-conf 00_657 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_3[3] origin:064-gtp-channel-conf 01_657 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_3[4] origin:064-gtp-channel-conf 00_658 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_3[5] origin:064-gtp-channel-conf 01_658 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_3[6] origin:064-gtp-channel-conf 00_659 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_3[7] origin:064-gtp-channel-conf 01_659 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_3[8] origin:064-gtp-channel-conf 00_660 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_3[9] origin:064-gtp-channel-conf 01_660 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_4[0] origin:064-gtp-channel-conf 00_664 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_4[1] origin:064-gtp-channel-conf 01_664 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_4[2] origin:064-gtp-channel-conf 00_665 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_4[3] origin:064-gtp-channel-conf 01_665 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_4[4] origin:064-gtp-channel-conf 00_666 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_4[5] origin:064-gtp-channel-conf 01_666 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_4[6] origin:064-gtp-channel-conf 00_667 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_4[7] origin:064-gtp-channel-conf 01_667 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_4[8] origin:064-gtp-channel-conf 00_668 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_4[9] origin:064-gtp-channel-conf 01_668 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_ENABLE[0] origin:064-gtp-channel-conf 00_646 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_ENABLE[1] origin:064-gtp-channel-conf 01_646 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_ENABLE[2] origin:064-gtp-channel-conf 00_647 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_ENABLE[3] origin:064-gtp-channel-conf 01_647 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_USE origin:064-gtp-channel-conf 01_645 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_LEN[0] origin:064-gtp-channel-conf 00_623 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_LEN[1] origin:064-gtp-channel-conf 01_623 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COMMON_SWING[0] origin:064-gtp-channel-conf 03_311 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_KEEP_IDLE origin:064-gtp-channel-conf 00_591 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_MAX_LAT[0] origin:064-gtp-channel-conf 00_557 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_MAX_LAT[1] origin:064-gtp-channel-conf 01_557 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_MAX_LAT[2] origin:064-gtp-channel-conf 00_558 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_MAX_LAT[3] origin:064-gtp-channel-conf 01_558 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_MAX_LAT[4] origin:064-gtp-channel-conf 00_559 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_MAX_LAT[5] origin:064-gtp-channel-conf 01_559 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_MIN_LAT[0] origin:064-gtp-channel-conf 00_565 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_MIN_LAT[1] origin:064-gtp-channel-conf 01_565 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_MIN_LAT[2] origin:064-gtp-channel-conf 00_566 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_MIN_LAT[3] origin:064-gtp-channel-conf 01_566 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_MIN_LAT[4] origin:064-gtp-channel-conf 00_567 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_MIN_LAT[5] origin:064-gtp-channel-conf 01_567 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_PRECEDENCE origin:064-gtp-channel-conf 00_590 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_REPEAT_WAIT[0] origin:064-gtp-channel-conf 00_573 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_REPEAT_WAIT[1] origin:064-gtp-channel-conf 01_573 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_REPEAT_WAIT[2] origin:064-gtp-channel-conf 00_574 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_REPEAT_WAIT[3] origin:064-gtp-channel-conf 01_574 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_REPEAT_WAIT[4] origin:064-gtp-channel-conf 00_575 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_1[0] origin:064-gtp-channel-conf 00_544 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_1[1] origin:064-gtp-channel-conf 01_544 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_1[2] origin:064-gtp-channel-conf 00_545 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_1[3] origin:064-gtp-channel-conf 01_545 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_1[4] origin:064-gtp-channel-conf 00_546 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_1[5] origin:064-gtp-channel-conf 01_546 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_1[6] origin:064-gtp-channel-conf 00_547 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_1[7] origin:064-gtp-channel-conf 01_547 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_1[8] origin:064-gtp-channel-conf 00_548 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_1[9] origin:064-gtp-channel-conf 01_548 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_2[0] origin:064-gtp-channel-conf 00_552 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_2[1] origin:064-gtp-channel-conf 01_552 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_2[2] origin:064-gtp-channel-conf 00_553 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_2[3] origin:064-gtp-channel-conf 01_553 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_2[4] origin:064-gtp-channel-conf 00_554 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_2[5] origin:064-gtp-channel-conf 01_554 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_2[6] origin:064-gtp-channel-conf 00_555 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_2[7] origin:064-gtp-channel-conf 01_555 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_2[8] origin:064-gtp-channel-conf 00_556 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_2[9] origin:064-gtp-channel-conf 01_556 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_3[0] origin:064-gtp-channel-conf 00_560 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_3[1] origin:064-gtp-channel-conf 01_560 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_3[2] origin:064-gtp-channel-conf 00_561 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_3[3] origin:064-gtp-channel-conf 01_561 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_3[4] origin:064-gtp-channel-conf 00_562 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_3[5] origin:064-gtp-channel-conf 01_562 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_3[6] origin:064-gtp-channel-conf 00_563 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_3[7] origin:064-gtp-channel-conf 01_563 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_3[8] origin:064-gtp-channel-conf 00_564 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_3[9] origin:064-gtp-channel-conf 01_564 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_4[0] origin:064-gtp-channel-conf 00_568 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_4[1] origin:064-gtp-channel-conf 01_568 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_4[2] origin:064-gtp-channel-conf 00_569 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_4[3] origin:064-gtp-channel-conf 01_569 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_4[4] origin:064-gtp-channel-conf 00_570 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_4[5] origin:064-gtp-channel-conf 01_570 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_4[6] origin:064-gtp-channel-conf 00_571 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_4[7] origin:064-gtp-channel-conf 01_571 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_4[8] origin:064-gtp-channel-conf 00_572 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_4[9] origin:064-gtp-channel-conf 01_572 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_ENABLE[0] origin:064-gtp-channel-conf 00_549 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_ENABLE[1] origin:064-gtp-channel-conf 01_549 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_ENABLE[2] origin:064-gtp-channel-conf 00_550 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_ENABLE[3] origin:064-gtp-channel-conf 01_550 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_1[0] origin:064-gtp-channel-conf 00_576 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_1[1] origin:064-gtp-channel-conf 01_576 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_1[2] origin:064-gtp-channel-conf 00_577 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_1[3] origin:064-gtp-channel-conf 01_577 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_1[4] origin:064-gtp-channel-conf 00_578 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_1[5] origin:064-gtp-channel-conf 01_578 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_1[6] origin:064-gtp-channel-conf 00_579 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_1[7] origin:064-gtp-channel-conf 01_579 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_1[8] origin:064-gtp-channel-conf 00_580 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_1[9] origin:064-gtp-channel-conf 01_580 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_2[0] origin:064-gtp-channel-conf 00_584 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_2[1] origin:064-gtp-channel-conf 01_584 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_2[2] origin:064-gtp-channel-conf 00_585 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_2[3] origin:064-gtp-channel-conf 01_585 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_2[4] origin:064-gtp-channel-conf 00_586 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_2[5] origin:064-gtp-channel-conf 01_586 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_2[6] origin:064-gtp-channel-conf 00_587 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_2[7] origin:064-gtp-channel-conf 01_587 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_2[8] origin:064-gtp-channel-conf 00_588 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_2[9] origin:064-gtp-channel-conf 01_588 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_3[0] origin:064-gtp-channel-conf 00_592 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_3[1] origin:064-gtp-channel-conf 01_592 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_3[2] origin:064-gtp-channel-conf 00_593 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_3[3] origin:064-gtp-channel-conf 01_593 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_3[4] origin:064-gtp-channel-conf 00_594 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_3[5] origin:064-gtp-channel-conf 01_594 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_3[6] origin:064-gtp-channel-conf 00_595 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_3[7] origin:064-gtp-channel-conf 01_595 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_3[8] origin:064-gtp-channel-conf 00_596 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_3[9] origin:064-gtp-channel-conf 01_596 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_4[0] origin:064-gtp-channel-conf 00_600 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_4[1] origin:064-gtp-channel-conf 01_600 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_4[2] origin:064-gtp-channel-conf 00_601 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_4[3] origin:064-gtp-channel-conf 01_601 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_4[4] origin:064-gtp-channel-conf 00_602 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_4[5] origin:064-gtp-channel-conf 01_602 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_4[6] origin:064-gtp-channel-conf 00_603 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_4[7] origin:064-gtp-channel-conf 01_603 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_4[8] origin:064-gtp-channel-conf 00_604 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_4[9] origin:064-gtp-channel-conf 01_604 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_ENABLE[0] origin:064-gtp-channel-conf 00_581 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_ENABLE[1] origin:064-gtp-channel-conf 01_581 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_ENABLE[2] origin:064-gtp-channel-conf 00_582 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_ENABLE[3] origin:064-gtp-channel-conf 01_582 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_USE origin:064-gtp-channel-conf 00_583 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_LEN[0] origin:064-gtp-channel-conf 00_589 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_COR_SEQ_LEN[1] origin:064-gtp-channel-conf 01_589 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.CLK_CORRECT_USE origin:064-gtp-channel-conf 00_551 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.DEC_MCOMMA_DETECT origin:064-gtp-channel-conf 01_494 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.DEC_PCOMMA_DETECT origin:064-gtp-channel-conf 00_495 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.DEC_VALID_COMMA_ONLY origin:064-gtp-channel-conf 00_494 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.DMONITOR_CFG[0] origin:064-gtp-channel-conf 02_368 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.DMONITOR_CFG[1] origin:064-gtp-channel-conf 03_368 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.DMONITOR_CFG[2] origin:064-gtp-channel-conf 02_369 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.DMONITOR_CFG[3] origin:064-gtp-channel-conf 03_369 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.DMONITOR_CFG[4] origin:064-gtp-channel-conf 02_370 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.DMONITOR_CFG[5] origin:064-gtp-channel-conf 03_370 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.DMONITOR_CFG[6] origin:064-gtp-channel-conf 02_371 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.DMONITOR_CFG[7] origin:064-gtp-channel-conf 03_371 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.DMONITOR_CFG[8] origin:064-gtp-channel-conf 02_372 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.DMONITOR_CFG[9] origin:064-gtp-channel-conf 03_372 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.DMONITOR_CFG[10] origin:064-gtp-channel-conf 02_373 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.DMONITOR_CFG[11] origin:064-gtp-channel-conf 03_373 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.DMONITOR_CFG[12] origin:064-gtp-channel-conf 02_374 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.DMONITOR_CFG[13] origin:064-gtp-channel-conf 03_374 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.DMONITOR_CFG[14] origin:064-gtp-channel-conf 02_375 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.DMONITOR_CFG[15] origin:064-gtp-channel-conf 03_375 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.DMONITOR_CFG[16] origin:064-gtp-channel-conf 02_376 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.DMONITOR_CFG[17] origin:064-gtp-channel-conf 03_376 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.DMONITOR_CFG[18] origin:064-gtp-channel-conf 02_377 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.DMONITOR_CFG[19] origin:064-gtp-channel-conf 03_377 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.DMONITOR_CFG[20] origin:064-gtp-channel-conf 02_378 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.DMONITOR_CFG[21] origin:064-gtp-channel-conf 03_378 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.DMONITOR_CFG[22] origin:064-gtp-channel-conf 02_379 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.DMONITOR_CFG[23] origin:064-gtp-channel-conf 03_379 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_CLK_PHASE_SEL[0] origin:064-gtp-channel-conf 03_463 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_CONTROL[0] origin:064-gtp-channel-conf 00_488 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_CONTROL[1] origin:064-gtp-channel-conf 01_488 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_CONTROL[2] origin:064-gtp-channel-conf 00_489 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_CONTROL[3] origin:064-gtp-channel-conf 01_489 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_CONTROL[4] origin:064-gtp-channel-conf 00_490 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_CONTROL[5] origin:064-gtp-channel-conf 01_490 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_ERRDET_EN origin:064-gtp-channel-conf 01_492 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_EYE_SCAN_EN origin:064-gtp-channel-conf 00_492 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_HORZ_OFFSET[0] origin:064-gtp-channel-conf 00_480 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_HORZ_OFFSET[1] origin:064-gtp-channel-conf 01_480 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_HORZ_OFFSET[2] origin:064-gtp-channel-conf 00_481 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_HORZ_OFFSET[3] origin:064-gtp-channel-conf 01_481 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_HORZ_OFFSET[4] origin:064-gtp-channel-conf 00_482 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_HORZ_OFFSET[5] origin:064-gtp-channel-conf 01_482 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_HORZ_OFFSET[6] origin:064-gtp-channel-conf 00_483 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_HORZ_OFFSET[7] origin:064-gtp-channel-conf 01_483 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_HORZ_OFFSET[8] origin:064-gtp-channel-conf 00_484 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_HORZ_OFFSET[9] origin:064-gtp-channel-conf 01_484 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_HORZ_OFFSET[10] origin:064-gtp-channel-conf 00_485 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_HORZ_OFFSET[11] origin:064-gtp-channel-conf 01_485 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_PMA_CFG[0] origin:064-gtp-channel-conf 02_624 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_PMA_CFG[1] origin:064-gtp-channel-conf 03_624 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_PMA_CFG[2] origin:064-gtp-channel-conf 02_625 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_PMA_CFG[3] origin:064-gtp-channel-conf 03_625 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_PMA_CFG[4] origin:064-gtp-channel-conf 02_626 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_PMA_CFG[5] origin:064-gtp-channel-conf 03_626 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_PMA_CFG[6] origin:064-gtp-channel-conf 02_627 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_PMA_CFG[7] origin:064-gtp-channel-conf 03_627 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_PMA_CFG[8] origin:064-gtp-channel-conf 02_628 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_PMA_CFG[9] origin:064-gtp-channel-conf 03_628 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_PRESCALE[0] origin:064-gtp-channel-conf 01_477 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_PRESCALE[1] origin:064-gtp-channel-conf 00_478 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_PRESCALE[2] origin:064-gtp-channel-conf 01_478 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_PRESCALE[3] origin:064-gtp-channel-conf 00_479 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_PRESCALE[4] origin:064-gtp-channel-conf 01_479 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[0] origin:064-gtp-channel-conf 00_392 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[1] origin:064-gtp-channel-conf 01_392 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[2] origin:064-gtp-channel-conf 00_393 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[3] origin:064-gtp-channel-conf 01_393 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[4] origin:064-gtp-channel-conf 00_394 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[5] origin:064-gtp-channel-conf 01_394 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[6] origin:064-gtp-channel-conf 00_395 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[7] origin:064-gtp-channel-conf 01_395 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[8] origin:064-gtp-channel-conf 00_396 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[9] origin:064-gtp-channel-conf 01_396 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[10] origin:064-gtp-channel-conf 00_397 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[11] origin:064-gtp-channel-conf 01_397 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[12] origin:064-gtp-channel-conf 00_398 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[13] origin:064-gtp-channel-conf 01_398 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[14] origin:064-gtp-channel-conf 00_399 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[15] origin:064-gtp-channel-conf 01_399 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[16] origin:064-gtp-channel-conf 00_400 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[17] origin:064-gtp-channel-conf 01_400 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[18] origin:064-gtp-channel-conf 00_401 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[19] origin:064-gtp-channel-conf 01_401 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[20] origin:064-gtp-channel-conf 00_402 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[21] origin:064-gtp-channel-conf 01_402 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[22] origin:064-gtp-channel-conf 00_403 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[23] origin:064-gtp-channel-conf 01_403 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[24] origin:064-gtp-channel-conf 00_404 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[25] origin:064-gtp-channel-conf 01_404 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[26] origin:064-gtp-channel-conf 00_405 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[27] origin:064-gtp-channel-conf 01_405 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[28] origin:064-gtp-channel-conf 00_406 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[29] origin:064-gtp-channel-conf 01_406 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[30] origin:064-gtp-channel-conf 00_407 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[31] origin:064-gtp-channel-conf 01_407 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[32] origin:064-gtp-channel-conf 00_408 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[33] origin:064-gtp-channel-conf 01_408 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[34] origin:064-gtp-channel-conf 00_409 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[35] origin:064-gtp-channel-conf 01_409 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[36] origin:064-gtp-channel-conf 00_410 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[37] origin:064-gtp-channel-conf 01_410 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[38] origin:064-gtp-channel-conf 00_411 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[39] origin:064-gtp-channel-conf 01_411 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[40] origin:064-gtp-channel-conf 00_412 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[41] origin:064-gtp-channel-conf 01_412 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[42] origin:064-gtp-channel-conf 00_413 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[43] origin:064-gtp-channel-conf 01_413 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[44] origin:064-gtp-channel-conf 00_414 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[45] origin:064-gtp-channel-conf 01_414 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[46] origin:064-gtp-channel-conf 00_415 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[47] origin:064-gtp-channel-conf 01_415 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[48] origin:064-gtp-channel-conf 00_416 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[49] origin:064-gtp-channel-conf 01_416 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[50] origin:064-gtp-channel-conf 00_417 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[51] origin:064-gtp-channel-conf 01_417 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[52] origin:064-gtp-channel-conf 00_418 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[53] origin:064-gtp-channel-conf 01_418 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[54] origin:064-gtp-channel-conf 00_419 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[55] origin:064-gtp-channel-conf 01_419 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[56] origin:064-gtp-channel-conf 00_420 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[57] origin:064-gtp-channel-conf 01_420 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[58] origin:064-gtp-channel-conf 00_421 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[59] origin:064-gtp-channel-conf 01_421 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[60] origin:064-gtp-channel-conf 00_422 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[61] origin:064-gtp-channel-conf 01_422 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[62] origin:064-gtp-channel-conf 00_423 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[63] origin:064-gtp-channel-conf 01_423 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[64] origin:064-gtp-channel-conf 00_424 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[65] origin:064-gtp-channel-conf 01_424 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[66] origin:064-gtp-channel-conf 00_425 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[67] origin:064-gtp-channel-conf 01_425 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[68] origin:064-gtp-channel-conf 00_426 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[69] origin:064-gtp-channel-conf 01_426 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[70] origin:064-gtp-channel-conf 00_427 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[71] origin:064-gtp-channel-conf 01_427 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[72] origin:064-gtp-channel-conf 00_428 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[73] origin:064-gtp-channel-conf 01_428 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[74] origin:064-gtp-channel-conf 00_429 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[75] origin:064-gtp-channel-conf 01_429 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[76] origin:064-gtp-channel-conf 00_430 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[77] origin:064-gtp-channel-conf 01_430 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[78] origin:064-gtp-channel-conf 00_431 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUAL_MASK[79] origin:064-gtp-channel-conf 01_431 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[0] origin:064-gtp-channel-conf 00_352 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[1] origin:064-gtp-channel-conf 01_352 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[2] origin:064-gtp-channel-conf 00_353 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[3] origin:064-gtp-channel-conf 01_353 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[4] origin:064-gtp-channel-conf 00_354 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[5] origin:064-gtp-channel-conf 01_354 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[6] origin:064-gtp-channel-conf 00_355 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[7] origin:064-gtp-channel-conf 01_355 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[8] origin:064-gtp-channel-conf 00_356 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[9] origin:064-gtp-channel-conf 01_356 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[10] origin:064-gtp-channel-conf 00_357 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[11] origin:064-gtp-channel-conf 01_357 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[12] origin:064-gtp-channel-conf 00_358 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[13] origin:064-gtp-channel-conf 01_358 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[14] origin:064-gtp-channel-conf 00_359 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[15] origin:064-gtp-channel-conf 01_359 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[16] origin:064-gtp-channel-conf 00_360 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[17] origin:064-gtp-channel-conf 01_360 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[18] origin:064-gtp-channel-conf 00_361 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[19] origin:064-gtp-channel-conf 01_361 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[20] origin:064-gtp-channel-conf 00_362 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[21] origin:064-gtp-channel-conf 01_362 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[22] origin:064-gtp-channel-conf 00_363 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[23] origin:064-gtp-channel-conf 01_363 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[24] origin:064-gtp-channel-conf 00_364 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[25] origin:064-gtp-channel-conf 01_364 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[26] origin:064-gtp-channel-conf 00_365 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[27] origin:064-gtp-channel-conf 01_365 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[28] origin:064-gtp-channel-conf 00_366 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[29] origin:064-gtp-channel-conf 01_366 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[30] origin:064-gtp-channel-conf 00_367 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[31] origin:064-gtp-channel-conf 01_367 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[32] origin:064-gtp-channel-conf 00_368 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[33] origin:064-gtp-channel-conf 01_368 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[34] origin:064-gtp-channel-conf 00_369 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[35] origin:064-gtp-channel-conf 01_369 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[36] origin:064-gtp-channel-conf 00_370 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[37] origin:064-gtp-channel-conf 01_370 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[38] origin:064-gtp-channel-conf 00_371 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[39] origin:064-gtp-channel-conf 01_371 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[40] origin:064-gtp-channel-conf 00_372 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[41] origin:064-gtp-channel-conf 01_372 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[42] origin:064-gtp-channel-conf 00_373 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[43] origin:064-gtp-channel-conf 01_373 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[44] origin:064-gtp-channel-conf 00_374 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[45] origin:064-gtp-channel-conf 01_374 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[46] origin:064-gtp-channel-conf 00_375 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[47] origin:064-gtp-channel-conf 01_375 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[48] origin:064-gtp-channel-conf 00_376 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[49] origin:064-gtp-channel-conf 01_376 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[50] origin:064-gtp-channel-conf 00_377 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[51] origin:064-gtp-channel-conf 01_377 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[52] origin:064-gtp-channel-conf 00_378 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[53] origin:064-gtp-channel-conf 01_378 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[54] origin:064-gtp-channel-conf 00_379 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[55] origin:064-gtp-channel-conf 01_379 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[56] origin:064-gtp-channel-conf 00_380 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[57] origin:064-gtp-channel-conf 01_380 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[58] origin:064-gtp-channel-conf 00_381 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[59] origin:064-gtp-channel-conf 01_381 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[60] origin:064-gtp-channel-conf 00_382 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[61] origin:064-gtp-channel-conf 01_382 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[62] origin:064-gtp-channel-conf 00_383 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[63] origin:064-gtp-channel-conf 01_383 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[64] origin:064-gtp-channel-conf 00_384 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[65] origin:064-gtp-channel-conf 01_384 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[66] origin:064-gtp-channel-conf 00_385 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[67] origin:064-gtp-channel-conf 01_385 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[68] origin:064-gtp-channel-conf 00_386 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[69] origin:064-gtp-channel-conf 01_386 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[70] origin:064-gtp-channel-conf 00_387 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[71] origin:064-gtp-channel-conf 01_387 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[72] origin:064-gtp-channel-conf 00_388 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[73] origin:064-gtp-channel-conf 01_388 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[74] origin:064-gtp-channel-conf 00_389 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[75] origin:064-gtp-channel-conf 01_389 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[76] origin:064-gtp-channel-conf 00_390 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[77] origin:064-gtp-channel-conf 01_390 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[78] origin:064-gtp-channel-conf 00_391 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_QUALIFIER[79] origin:064-gtp-channel-conf 01_391 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[0] origin:064-gtp-channel-conf 00_432 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[1] origin:064-gtp-channel-conf 01_432 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[2] origin:064-gtp-channel-conf 00_433 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[3] origin:064-gtp-channel-conf 01_433 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[4] origin:064-gtp-channel-conf 00_434 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[5] origin:064-gtp-channel-conf 01_434 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[6] origin:064-gtp-channel-conf 00_435 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[7] origin:064-gtp-channel-conf 01_435 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[8] origin:064-gtp-channel-conf 00_436 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[9] origin:064-gtp-channel-conf 01_436 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[10] origin:064-gtp-channel-conf 00_437 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[11] origin:064-gtp-channel-conf 01_437 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[12] origin:064-gtp-channel-conf 00_438 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[13] origin:064-gtp-channel-conf 01_438 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[14] origin:064-gtp-channel-conf 00_439 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[15] origin:064-gtp-channel-conf 01_439 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[16] origin:064-gtp-channel-conf 00_440 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[17] origin:064-gtp-channel-conf 01_440 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[18] origin:064-gtp-channel-conf 00_441 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[19] origin:064-gtp-channel-conf 01_441 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[20] origin:064-gtp-channel-conf 00_442 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[21] origin:064-gtp-channel-conf 01_442 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[22] origin:064-gtp-channel-conf 00_443 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[23] origin:064-gtp-channel-conf 01_443 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[24] origin:064-gtp-channel-conf 00_444 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[25] origin:064-gtp-channel-conf 01_444 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[26] origin:064-gtp-channel-conf 00_445 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[27] origin:064-gtp-channel-conf 01_445 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[28] origin:064-gtp-channel-conf 00_446 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[29] origin:064-gtp-channel-conf 01_446 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[30] origin:064-gtp-channel-conf 00_447 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[31] origin:064-gtp-channel-conf 01_447 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[32] origin:064-gtp-channel-conf 00_448 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[33] origin:064-gtp-channel-conf 01_448 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[34] origin:064-gtp-channel-conf 00_449 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[35] origin:064-gtp-channel-conf 01_449 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[36] origin:064-gtp-channel-conf 00_450 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[37] origin:064-gtp-channel-conf 01_450 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[38] origin:064-gtp-channel-conf 00_451 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[39] origin:064-gtp-channel-conf 01_451 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[40] origin:064-gtp-channel-conf 00_452 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[41] origin:064-gtp-channel-conf 01_452 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[42] origin:064-gtp-channel-conf 00_453 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[43] origin:064-gtp-channel-conf 01_453 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[44] origin:064-gtp-channel-conf 00_454 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[45] origin:064-gtp-channel-conf 01_454 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[46] origin:064-gtp-channel-conf 00_455 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[47] origin:064-gtp-channel-conf 01_455 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[48] origin:064-gtp-channel-conf 00_456 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[49] origin:064-gtp-channel-conf 01_456 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[50] origin:064-gtp-channel-conf 00_457 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[51] origin:064-gtp-channel-conf 01_457 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[52] origin:064-gtp-channel-conf 00_458 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[53] origin:064-gtp-channel-conf 01_458 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[54] origin:064-gtp-channel-conf 00_459 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[55] origin:064-gtp-channel-conf 01_459 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[56] origin:064-gtp-channel-conf 00_460 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[57] origin:064-gtp-channel-conf 01_460 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[58] origin:064-gtp-channel-conf 00_461 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[59] origin:064-gtp-channel-conf 01_461 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[60] origin:064-gtp-channel-conf 00_462 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[61] origin:064-gtp-channel-conf 01_462 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[62] origin:064-gtp-channel-conf 00_463 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[63] origin:064-gtp-channel-conf 01_463 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[64] origin:064-gtp-channel-conf 00_464 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[65] origin:064-gtp-channel-conf 01_464 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[66] origin:064-gtp-channel-conf 00_465 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[67] origin:064-gtp-channel-conf 01_465 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[68] origin:064-gtp-channel-conf 00_466 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[69] origin:064-gtp-channel-conf 01_466 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[70] origin:064-gtp-channel-conf 00_467 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[71] origin:064-gtp-channel-conf 01_467 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[72] origin:064-gtp-channel-conf 00_468 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[73] origin:064-gtp-channel-conf 01_468 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[74] origin:064-gtp-channel-conf 00_469 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[75] origin:064-gtp-channel-conf 01_469 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[76] origin:064-gtp-channel-conf 00_470 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[77] origin:064-gtp-channel-conf 01_470 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[78] origin:064-gtp-channel-conf 00_471 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_SDATA_MASK[79] origin:064-gtp-channel-conf 01_471 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_VERT_OFFSET[0] origin:064-gtp-channel-conf 00_472 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_VERT_OFFSET[1] origin:064-gtp-channel-conf 01_472 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_VERT_OFFSET[2] origin:064-gtp-channel-conf 00_473 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_VERT_OFFSET[3] origin:064-gtp-channel-conf 01_473 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_VERT_OFFSET[4] origin:064-gtp-channel-conf 00_474 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_VERT_OFFSET[5] origin:064-gtp-channel-conf 01_474 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_VERT_OFFSET[6] origin:064-gtp-channel-conf 00_475 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_VERT_OFFSET[7] origin:064-gtp-channel-conf 01_475 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ES_VERT_OFFSET[8] origin:064-gtp-channel-conf 00_476 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.FTS_DESKEW_SEQ_ENABLE[0] origin:064-gtp-channel-conf 00_662 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.FTS_DESKEW_SEQ_ENABLE[1] origin:064-gtp-channel-conf 01_662 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.FTS_DESKEW_SEQ_ENABLE[2] origin:064-gtp-channel-conf 00_663 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.FTS_DESKEW_SEQ_ENABLE[3] origin:064-gtp-channel-conf 01_663 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.FTS_LANE_DESKEW_CFG[0] origin:064-gtp-channel-conf 00_654 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.FTS_LANE_DESKEW_CFG[1] origin:064-gtp-channel-conf 01_654 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.FTS_LANE_DESKEW_CFG[2] origin:064-gtp-channel-conf 00_655 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.FTS_LANE_DESKEW_CFG[3] origin:064-gtp-channel-conf 01_655 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.FTS_LANE_DESKEW_EN origin:064-gtp-channel-conf 01_653 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.GEARBOX_MODE[0] origin:064-gtp-channel-conf 00_224 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.GEARBOX_MODE[1] origin:064-gtp-channel-conf 01_224 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.GEARBOX_MODE[2] origin:064-gtp-channel-conf 00_225 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.IN_USE origin:064-gtp-channel-conf 00_00 00_01 00_47 00_52 00_53 00_65 01_01 01_47 02_129 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.LOOPBACK_CFG[0] origin:064-gtp-channel-conf 02_20 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.OUTREFCLK_SEL_INV[0] origin:064-gtp-channel-conf 00_149 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.OUTREFCLK_SEL_INV[1] origin:064-gtp-channel-conf 01_149 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PCS_PCIE_EN origin:064-gtp-channel-conf 00_216 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[0] origin:064-gtp-channel-conf 02_184 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[1] origin:064-gtp-channel-conf 03_184 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[2] origin:064-gtp-channel-conf 02_185 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[3] origin:064-gtp-channel-conf 03_185 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[4] origin:064-gtp-channel-conf 02_186 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[5] origin:064-gtp-channel-conf 03_186 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[6] origin:064-gtp-channel-conf 02_187 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[7] origin:064-gtp-channel-conf 03_187 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[8] origin:064-gtp-channel-conf 02_188 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[9] origin:064-gtp-channel-conf 03_188 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[10] origin:064-gtp-channel-conf 02_189 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[11] origin:064-gtp-channel-conf 03_189 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[12] origin:064-gtp-channel-conf 02_190 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[13] origin:064-gtp-channel-conf 03_190 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[14] origin:064-gtp-channel-conf 02_191 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[15] origin:064-gtp-channel-conf 03_191 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[16] origin:064-gtp-channel-conf 02_192 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[17] origin:064-gtp-channel-conf 03_192 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[18] origin:064-gtp-channel-conf 02_193 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[19] origin:064-gtp-channel-conf 03_193 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[20] origin:064-gtp-channel-conf 02_194 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[21] origin:064-gtp-channel-conf 03_194 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[22] origin:064-gtp-channel-conf 02_195 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[23] origin:064-gtp-channel-conf 03_195 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[24] origin:064-gtp-channel-conf 02_196 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[25] origin:064-gtp-channel-conf 03_196 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[26] origin:064-gtp-channel-conf 02_197 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[27] origin:064-gtp-channel-conf 03_197 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[28] origin:064-gtp-channel-conf 02_198 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[29] origin:064-gtp-channel-conf 03_198 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[30] origin:064-gtp-channel-conf 02_199 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[31] origin:064-gtp-channel-conf 03_199 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[32] origin:064-gtp-channel-conf 02_200 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[33] origin:064-gtp-channel-conf 03_200 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[34] origin:064-gtp-channel-conf 02_201 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[35] origin:064-gtp-channel-conf 03_201 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[36] origin:064-gtp-channel-conf 02_202 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[37] origin:064-gtp-channel-conf 03_202 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[38] origin:064-gtp-channel-conf 02_203 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[39] origin:064-gtp-channel-conf 03_203 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[40] origin:064-gtp-channel-conf 02_204 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[41] origin:064-gtp-channel-conf 03_204 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[42] origin:064-gtp-channel-conf 02_205 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[43] origin:064-gtp-channel-conf 03_205 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[44] origin:064-gtp-channel-conf 02_206 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[45] origin:064-gtp-channel-conf 03_206 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[46] origin:064-gtp-channel-conf 02_207 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[47] origin:064-gtp-channel-conf 03_207 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PD_TRANS_TIME_FROM_P2[0] origin:064-gtp-channel-conf 01_216 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PD_TRANS_TIME_FROM_P2[1] origin:064-gtp-channel-conf 00_217 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PD_TRANS_TIME_FROM_P2[2] origin:064-gtp-channel-conf 01_217 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PD_TRANS_TIME_FROM_P2[3] origin:064-gtp-channel-conf 00_218 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PD_TRANS_TIME_FROM_P2[4] origin:064-gtp-channel-conf 01_218 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PD_TRANS_TIME_FROM_P2[5] origin:064-gtp-channel-conf 00_219 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PD_TRANS_TIME_FROM_P2[6] origin:064-gtp-channel-conf 01_219 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PD_TRANS_TIME_FROM_P2[7] origin:064-gtp-channel-conf 00_220 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PD_TRANS_TIME_FROM_P2[8] origin:064-gtp-channel-conf 01_220 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PD_TRANS_TIME_FROM_P2[9] origin:064-gtp-channel-conf 00_221 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PD_TRANS_TIME_FROM_P2[10] origin:064-gtp-channel-conf 01_221 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PD_TRANS_TIME_FROM_P2[11] origin:064-gtp-channel-conf 00_222 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PD_TRANS_TIME_NONE_P2[0] origin:064-gtp-channel-conf 00_208 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PD_TRANS_TIME_NONE_P2[1] origin:064-gtp-channel-conf 01_208 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PD_TRANS_TIME_NONE_P2[2] origin:064-gtp-channel-conf 00_209 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PD_TRANS_TIME_NONE_P2[3] origin:064-gtp-channel-conf 01_209 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PD_TRANS_TIME_NONE_P2[4] origin:064-gtp-channel-conf 00_210 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PD_TRANS_TIME_NONE_P2[5] origin:064-gtp-channel-conf 01_210 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PD_TRANS_TIME_NONE_P2[6] origin:064-gtp-channel-conf 00_211 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PD_TRANS_TIME_NONE_P2[7] origin:064-gtp-channel-conf 01_211 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PD_TRANS_TIME_TO_P2[0] origin:064-gtp-channel-conf 00_212 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PD_TRANS_TIME_TO_P2[1] origin:064-gtp-channel-conf 01_212 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PD_TRANS_TIME_TO_P2[2] origin:064-gtp-channel-conf 00_213 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PD_TRANS_TIME_TO_P2[3] origin:064-gtp-channel-conf 01_213 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PD_TRANS_TIME_TO_P2[4] origin:064-gtp-channel-conf 00_214 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PD_TRANS_TIME_TO_P2[5] origin:064-gtp-channel-conf 01_214 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PD_TRANS_TIME_TO_P2[6] origin:064-gtp-channel-conf 00_215 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PD_TRANS_TIME_TO_P2[7] origin:064-gtp-channel-conf 01_215 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PMA_LOOPBACK_CFG[0] origin:064-gtp-channel-conf 01_207 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PMA_RSV[0] origin:064-gtp-channel-conf 02_520 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PMA_RSV[1] origin:064-gtp-channel-conf 03_520 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PMA_RSV[2] origin:064-gtp-channel-conf 02_521 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PMA_RSV[3] origin:064-gtp-channel-conf 03_521 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PMA_RSV[4] origin:064-gtp-channel-conf 02_522 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PMA_RSV[5] origin:064-gtp-channel-conf 03_522 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PMA_RSV[6] origin:064-gtp-channel-conf 02_523 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PMA_RSV[7] origin:064-gtp-channel-conf 03_523 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PMA_RSV[8] origin:064-gtp-channel-conf 02_524 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PMA_RSV[9] origin:064-gtp-channel-conf 03_524 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PMA_RSV[10] origin:064-gtp-channel-conf 02_525 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PMA_RSV[11] origin:064-gtp-channel-conf 03_525 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PMA_RSV[12] origin:064-gtp-channel-conf 02_526 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PMA_RSV[13] origin:064-gtp-channel-conf 03_526 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PMA_RSV[14] origin:064-gtp-channel-conf 02_527 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PMA_RSV[15] origin:064-gtp-channel-conf 03_527 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PMA_RSV[16] origin:064-gtp-channel-conf 02_528 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PMA_RSV[17] origin:064-gtp-channel-conf 03_528 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PMA_RSV[18] origin:064-gtp-channel-conf 02_529 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PMA_RSV[19] origin:064-gtp-channel-conf 03_529 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PMA_RSV[20] origin:064-gtp-channel-conf 02_530 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PMA_RSV[21] origin:064-gtp-channel-conf 03_530 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PMA_RSV[22] origin:064-gtp-channel-conf 02_531 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PMA_RSV[23] origin:064-gtp-channel-conf 03_531 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PMA_RSV[24] origin:064-gtp-channel-conf 02_532 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PMA_RSV[25] origin:064-gtp-channel-conf 03_532 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PMA_RSV[26] origin:064-gtp-channel-conf 02_533 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PMA_RSV[27] origin:064-gtp-channel-conf 03_533 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PMA_RSV[28] origin:064-gtp-channel-conf 02_534 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PMA_RSV[29] origin:064-gtp-channel-conf 03_534 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PMA_RSV[30] origin:064-gtp-channel-conf 02_535 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PMA_RSV[31] origin:064-gtp-channel-conf 03_535 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PMA_RSV2[0] origin:064-gtp-channel-conf 02_336 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PMA_RSV2[1] origin:064-gtp-channel-conf 03_336 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PMA_RSV2[2] origin:064-gtp-channel-conf 02_337 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PMA_RSV2[3] origin:064-gtp-channel-conf 03_337 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PMA_RSV2[4] origin:064-gtp-channel-conf 02_338 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PMA_RSV2[5] origin:064-gtp-channel-conf 03_338 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PMA_RSV2[6] origin:064-gtp-channel-conf 02_339 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PMA_RSV2[7] origin:064-gtp-channel-conf 03_339 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PMA_RSV2[8] origin:064-gtp-channel-conf 02_340 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PMA_RSV2[9] origin:064-gtp-channel-conf 03_340 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PMA_RSV2[10] origin:064-gtp-channel-conf 02_341 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PMA_RSV2[11] origin:064-gtp-channel-conf 03_341 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PMA_RSV2[12] origin:064-gtp-channel-conf 02_342 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PMA_RSV2[13] origin:064-gtp-channel-conf 03_342 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PMA_RSV2[14] origin:064-gtp-channel-conf 02_343 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PMA_RSV2[15] origin:064-gtp-channel-conf 03_343 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PMA_RSV2[16] origin:064-gtp-channel-conf 02_344 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PMA_RSV2[17] origin:064-gtp-channel-conf 03_344 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PMA_RSV2[18] origin:064-gtp-channel-conf 02_345 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PMA_RSV2[19] origin:064-gtp-channel-conf 03_345 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PMA_RSV2[20] origin:064-gtp-channel-conf 02_346 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PMA_RSV2[21] origin:064-gtp-channel-conf 03_346 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PMA_RSV2[22] origin:064-gtp-channel-conf 02_347 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PMA_RSV2[23] origin:064-gtp-channel-conf 03_347 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PMA_RSV2[24] origin:064-gtp-channel-conf 02_348 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PMA_RSV2[25] origin:064-gtp-channel-conf 03_348 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PMA_RSV2[26] origin:064-gtp-channel-conf 02_349 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PMA_RSV2[27] origin:064-gtp-channel-conf 03_349 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PMA_RSV2[28] origin:064-gtp-channel-conf 02_350 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PMA_RSV2[29] origin:064-gtp-channel-conf 03_350 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PMA_RSV2[30] origin:064-gtp-channel-conf 02_351 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PMA_RSV2[31] origin:064-gtp-channel-conf 03_351 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PMA_RSV3[0] origin:064-gtp-channel-conf 02_288 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PMA_RSV3[1] origin:064-gtp-channel-conf 03_288 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PMA_RSV4[0] origin:064-gtp-channel-conf 02_156 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PMA_RSV4[1] origin:064-gtp-channel-conf 03_156 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PMA_RSV4[2] origin:064-gtp-channel-conf 02_157 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PMA_RSV4[3] origin:064-gtp-channel-conf 03_157 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PMA_RSV5[0] origin:064-gtp-channel-conf 03_159 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PMA_RSV6[0] origin:064-gtp-channel-conf 02_303 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.PMA_RSV7[0] origin:064-gtp-channel-conf 03_303 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_BIAS_CFG[0] origin:064-gtp-channel-conf 02_112 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_BIAS_CFG[1] origin:064-gtp-channel-conf 03_112 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_BIAS_CFG[2] origin:064-gtp-channel-conf 02_113 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_BIAS_CFG[3] origin:064-gtp-channel-conf 03_113 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_BIAS_CFG[4] origin:064-gtp-channel-conf 02_114 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_BIAS_CFG[5] origin:064-gtp-channel-conf 03_114 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_BIAS_CFG[6] origin:064-gtp-channel-conf 02_115 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_BIAS_CFG[7] origin:064-gtp-channel-conf 03_115 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_BIAS_CFG[8] origin:064-gtp-channel-conf 02_116 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_BIAS_CFG[9] origin:064-gtp-channel-conf 03_116 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_BIAS_CFG[10] origin:064-gtp-channel-conf 02_117 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_BIAS_CFG[11] origin:064-gtp-channel-conf 03_117 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_BIAS_CFG[12] origin:064-gtp-channel-conf 02_118 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_BIAS_CFG[13] origin:064-gtp-channel-conf 03_118 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_BIAS_CFG[14] origin:064-gtp-channel-conf 02_119 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_BIAS_CFG[15] origin:064-gtp-channel-conf 03_119 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_BUFFER_CFG[0] origin:064-gtp-channel-conf 02_536 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_BUFFER_CFG[1] origin:064-gtp-channel-conf 03_536 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_BUFFER_CFG[2] origin:064-gtp-channel-conf 02_537 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_BUFFER_CFG[3] origin:064-gtp-channel-conf 03_537 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_BUFFER_CFG[4] origin:064-gtp-channel-conf 02_538 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_BUFFER_CFG[5] origin:064-gtp-channel-conf 03_538 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_CLKMUX_EN[0] origin:064-gtp-channel-conf 02_128 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_CM_SEL[0] origin:064-gtp-channel-conf 00_138 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_CM_SEL[1] origin:064-gtp-channel-conf 01_138 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_CM_TRIM[0] origin:064-gtp-channel-conf 02_304 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_CM_TRIM[1] origin:064-gtp-channel-conf 03_304 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_CM_TRIM[2] origin:064-gtp-channel-conf 02_305 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_CM_TRIM[3] origin:064-gtp-channel-conf 03_305 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_DATA_WIDTH[0] origin:064-gtp-channel-conf 01_141 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_DATA_WIDTH[1] origin:064-gtp-channel-conf 00_142 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_DATA_WIDTH[2] origin:064-gtp-channel-conf 01_142 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_DDI_SEL[0] origin:064-gtp-channel-conf 00_696 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_DDI_SEL[1] origin:064-gtp-channel-conf 01_696 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_DDI_SEL[2] origin:064-gtp-channel-conf 00_697 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_DDI_SEL[3] origin:064-gtp-channel-conf 01_697 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_DDI_SEL[4] origin:064-gtp-channel-conf 00_698 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_DDI_SEL[5] origin:064-gtp-channel-conf 01_698 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_DEBUG_CFG[0] origin:064-gtp-channel-conf 02_616 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_DEBUG_CFG[1] origin:064-gtp-channel-conf 03_616 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_DEBUG_CFG[2] origin:064-gtp-channel-conf 02_617 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_DEBUG_CFG[3] origin:064-gtp-channel-conf 03_617 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_DEBUG_CFG[4] origin:064-gtp-channel-conf 02_618 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_DEBUG_CFG[5] origin:064-gtp-channel-conf 03_618 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_DEBUG_CFG[6] origin:064-gtp-channel-conf 02_619 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_DEBUG_CFG[7] origin:064-gtp-channel-conf 03_619 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_DEBUG_CFG[8] origin:064-gtp-channel-conf 02_620 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_DEBUG_CFG[9] origin:064-gtp-channel-conf 03_620 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_DEBUG_CFG[10] origin:064-gtp-channel-conf 02_621 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_DEBUG_CFG[11] origin:064-gtp-channel-conf 03_621 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_DEBUG_CFG[12] origin:064-gtp-channel-conf 02_622 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_DEBUG_CFG[13] origin:064-gtp-channel-conf 03_622 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_DEFER_RESET_BUF_EN origin:064-gtp-channel-conf 02_552 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_DISPERR_SEQ_MATCH origin:064-gtp-channel-conf 01_495 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_OS_CFG[0] origin:064-gtp-channel-conf 00_288 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_OS_CFG[1] origin:064-gtp-channel-conf 01_288 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_OS_CFG[2] origin:064-gtp-channel-conf 00_289 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_OS_CFG[3] origin:064-gtp-channel-conf 01_289 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_OS_CFG[4] origin:064-gtp-channel-conf 00_290 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_OS_CFG[5] origin:064-gtp-channel-conf 01_290 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_OS_CFG[6] origin:064-gtp-channel-conf 00_291 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_OS_CFG[7] origin:064-gtp-channel-conf 01_291 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_OS_CFG[8] origin:064-gtp-channel-conf 00_292 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_OS_CFG[9] origin:064-gtp-channel-conf 01_292 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_OS_CFG[10] origin:064-gtp-channel-conf 00_293 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_OS_CFG[11] origin:064-gtp-channel-conf 01_293 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_OS_CFG[12] origin:064-gtp-channel-conf 00_294 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_SIG_VALID_DLY[0] origin:064-gtp-channel-conf 00_524 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_SIG_VALID_DLY[1] origin:064-gtp-channel-conf 01_524 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_SIG_VALID_DLY[2] origin:064-gtp-channel-conf 00_525 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_SIG_VALID_DLY[3] origin:064-gtp-channel-conf 01_525 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_SIG_VALID_DLY[4] origin:064-gtp-channel-conf 00_526 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_XCLK_SEL.RXUSR origin:064-gtp-channel-conf 00_143 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_CLK25_DIV[0] origin:064-gtp-channel-conf 00_139 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_CLK25_DIV[1] origin:064-gtp-channel-conf 01_139 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_CLK25_DIV[2] origin:064-gtp-channel-conf 00_140 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_CLK25_DIV[3] origin:064-gtp-channel-conf 01_140 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RX_CLK25_DIV[4] origin:064-gtp-channel-conf 00_141 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXBUF_ADDR_MODE.FAST origin:064-gtp-channel-conf 03_555 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXBUF_EIDLE_HI_CNT[0] origin:064-gtp-channel-conf 02_558 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXBUF_EIDLE_HI_CNT[1] origin:064-gtp-channel-conf 03_558 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXBUF_EIDLE_HI_CNT[2] origin:064-gtp-channel-conf 02_559 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXBUF_EIDLE_HI_CNT[3] origin:064-gtp-channel-conf 03_559 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXBUF_EIDLE_LO_CNT[0] origin:064-gtp-channel-conf 02_556 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXBUF_EIDLE_LO_CNT[1] origin:064-gtp-channel-conf 03_556 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXBUF_EIDLE_LO_CNT[2] origin:064-gtp-channel-conf 02_557 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXBUF_EIDLE_LO_CNT[3] origin:064-gtp-channel-conf 03_557 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXBUF_EN origin:064-gtp-channel-conf 02_11 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXBUF_RESET_ON_CB_CHANGE origin:064-gtp-channel-conf 02_560 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXBUF_RESET_ON_COMMAALIGN origin:064-gtp-channel-conf 02_561 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXBUF_RESET_ON_EIDLE origin:064-gtp-channel-conf 02_547 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXBUF_RESET_ON_RATE_CHANGE origin:064-gtp-channel-conf 03_560 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXBUF_THRESH_OVFLW[0] origin:064-gtp-channel-conf 03_552 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXBUF_THRESH_OVFLW[1] origin:064-gtp-channel-conf 02_553 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXBUF_THRESH_OVFLW[2] origin:064-gtp-channel-conf 03_553 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXBUF_THRESH_OVFLW[3] origin:064-gtp-channel-conf 02_554 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXBUF_THRESH_OVFLW[4] origin:064-gtp-channel-conf 03_554 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXBUF_THRESH_OVFLW[5] origin:064-gtp-channel-conf 02_555 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXBUF_THRESH_OVRD origin:064-gtp-channel-conf 02_548 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXBUF_THRESH_UNDFLW[0] origin:064-gtp-channel-conf 02_544 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXBUF_THRESH_UNDFLW[1] origin:064-gtp-channel-conf 03_544 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXBUF_THRESH_UNDFLW[2] origin:064-gtp-channel-conf 02_545 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXBUF_THRESH_UNDFLW[3] origin:064-gtp-channel-conf 03_545 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXBUF_THRESH_UNDFLW[4] origin:064-gtp-channel-conf 02_546 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXBUF_THRESH_UNDFLW[5] origin:064-gtp-channel-conf 03_546 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXBUFRESET_TIME[0] origin:064-gtp-channel-conf 01_101 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXBUFRESET_TIME[1] origin:064-gtp-channel-conf 00_102 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXBUFRESET_TIME[2] origin:064-gtp-channel-conf 01_102 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXBUFRESET_TIME[3] origin:064-gtp-channel-conf 00_103 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXBUFRESET_TIME[4] origin:064-gtp-channel-conf 01_103 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[0] origin:064-gtp-channel-conf 02_640 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[1] origin:064-gtp-channel-conf 03_640 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[2] origin:064-gtp-channel-conf 02_641 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[3] origin:064-gtp-channel-conf 03_641 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[4] origin:064-gtp-channel-conf 02_642 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[5] origin:064-gtp-channel-conf 03_642 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[6] origin:064-gtp-channel-conf 02_643 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[7] origin:064-gtp-channel-conf 03_643 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[8] origin:064-gtp-channel-conf 02_644 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[9] origin:064-gtp-channel-conf 03_644 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[10] origin:064-gtp-channel-conf 02_645 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[11] origin:064-gtp-channel-conf 03_645 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[12] origin:064-gtp-channel-conf 02_646 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[13] origin:064-gtp-channel-conf 03_646 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[14] origin:064-gtp-channel-conf 02_647 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[15] origin:064-gtp-channel-conf 03_647 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[16] origin:064-gtp-channel-conf 02_648 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[17] origin:064-gtp-channel-conf 03_648 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[18] origin:064-gtp-channel-conf 02_649 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[19] origin:064-gtp-channel-conf 03_649 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[20] origin:064-gtp-channel-conf 02_650 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[21] origin:064-gtp-channel-conf 03_650 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[22] origin:064-gtp-channel-conf 02_651 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[23] origin:064-gtp-channel-conf 03_651 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[24] origin:064-gtp-channel-conf 02_652 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[25] origin:064-gtp-channel-conf 03_652 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[26] origin:064-gtp-channel-conf 02_653 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[27] origin:064-gtp-channel-conf 03_653 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[28] origin:064-gtp-channel-conf 02_654 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[29] origin:064-gtp-channel-conf 03_654 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[30] origin:064-gtp-channel-conf 02_655 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[31] origin:064-gtp-channel-conf 03_655 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[32] origin:064-gtp-channel-conf 02_656 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[33] origin:064-gtp-channel-conf 03_656 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[34] origin:064-gtp-channel-conf 02_657 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[35] origin:064-gtp-channel-conf 03_657 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[36] origin:064-gtp-channel-conf 02_658 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[37] origin:064-gtp-channel-conf 03_658 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[38] origin:064-gtp-channel-conf 02_659 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[39] origin:064-gtp-channel-conf 03_659 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[40] origin:064-gtp-channel-conf 02_660 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[41] origin:064-gtp-channel-conf 03_660 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[42] origin:064-gtp-channel-conf 02_661 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[43] origin:064-gtp-channel-conf 03_661 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[44] origin:064-gtp-channel-conf 02_662 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[45] origin:064-gtp-channel-conf 03_662 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[46] origin:064-gtp-channel-conf 02_663 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[47] origin:064-gtp-channel-conf 03_663 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[48] origin:064-gtp-channel-conf 02_664 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[49] origin:064-gtp-channel-conf 03_664 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[50] origin:064-gtp-channel-conf 02_665 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[51] origin:064-gtp-channel-conf 03_665 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[52] origin:064-gtp-channel-conf 02_666 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[53] origin:064-gtp-channel-conf 03_666 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[54] origin:064-gtp-channel-conf 02_667 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[55] origin:064-gtp-channel-conf 03_667 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[56] origin:064-gtp-channel-conf 02_668 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[57] origin:064-gtp-channel-conf 03_668 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[58] origin:064-gtp-channel-conf 02_669 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[59] origin:064-gtp-channel-conf 03_669 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[60] origin:064-gtp-channel-conf 02_670 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[61] origin:064-gtp-channel-conf 03_670 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[62] origin:064-gtp-channel-conf 02_671 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[63] origin:064-gtp-channel-conf 03_671 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[64] origin:064-gtp-channel-conf 02_672 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[65] origin:064-gtp-channel-conf 03_672 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[66] origin:064-gtp-channel-conf 02_673 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[67] origin:064-gtp-channel-conf 03_673 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[68] origin:064-gtp-channel-conf 02_674 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[69] origin:064-gtp-channel-conf 03_674 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[70] origin:064-gtp-channel-conf 02_675 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[71] origin:064-gtp-channel-conf 03_675 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[72] origin:064-gtp-channel-conf 02_676 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[73] origin:064-gtp-channel-conf 03_676 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[74] origin:064-gtp-channel-conf 02_677 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[75] origin:064-gtp-channel-conf 03_677 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[76] origin:064-gtp-channel-conf 02_678 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[77] origin:064-gtp-channel-conf 03_678 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[78] origin:064-gtp-channel-conf 02_679 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[79] origin:064-gtp-channel-conf 03_679 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[80] origin:064-gtp-channel-conf 02_680 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[81] origin:064-gtp-channel-conf 03_680 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_CFG[82] origin:064-gtp-channel-conf 02_681 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_FR_RESET_ON_EIDLE[0] origin:064-gtp-channel-conf 02_638 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_HOLD_DURING_EIDLE[0] origin:064-gtp-channel-conf 03_637 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_LOCK_CFG[0] origin:064-gtp-channel-conf 02_632 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_LOCK_CFG[1] origin:064-gtp-channel-conf 03_632 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_LOCK_CFG[2] origin:064-gtp-channel-conf 02_633 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_LOCK_CFG[3] origin:064-gtp-channel-conf 03_633 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_LOCK_CFG[4] origin:064-gtp-channel-conf 02_634 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_LOCK_CFG[5] origin:064-gtp-channel-conf 03_634 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDR_PH_RESET_ON_EIDLE[0] origin:064-gtp-channel-conf 03_638 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDRFREQRESET_TIME[0] origin:064-gtp-channel-conf 01_106 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDRFREQRESET_TIME[1] origin:064-gtp-channel-conf 00_107 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDRFREQRESET_TIME[2] origin:064-gtp-channel-conf 01_107 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDRFREQRESET_TIME[3] origin:064-gtp-channel-conf 00_108 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDRFREQRESET_TIME[4] origin:064-gtp-channel-conf 01_108 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDRPHRESET_TIME[0] origin:064-gtp-channel-conf 00_109 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDRPHRESET_TIME[1] origin:064-gtp-channel-conf 01_109 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDRPHRESET_TIME[2] origin:064-gtp-channel-conf 00_110 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDRPHRESET_TIME[3] origin:064-gtp-channel-conf 01_110 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXCDRPHRESET_TIME[4] origin:064-gtp-channel-conf 00_111 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXDLY_CFG[0] origin:064-gtp-channel-conf 00_680 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXDLY_CFG[1] origin:064-gtp-channel-conf 01_680 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXDLY_CFG[2] origin:064-gtp-channel-conf 00_681 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXDLY_CFG[3] origin:064-gtp-channel-conf 01_681 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXDLY_CFG[4] origin:064-gtp-channel-conf 00_682 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXDLY_CFG[5] origin:064-gtp-channel-conf 01_682 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXDLY_CFG[6] origin:064-gtp-channel-conf 00_683 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXDLY_CFG[7] origin:064-gtp-channel-conf 01_683 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXDLY_CFG[8] origin:064-gtp-channel-conf 00_684 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXDLY_CFG[9] origin:064-gtp-channel-conf 01_684 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXDLY_CFG[10] origin:064-gtp-channel-conf 00_685 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXDLY_CFG[11] origin:064-gtp-channel-conf 01_685 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXDLY_CFG[12] origin:064-gtp-channel-conf 00_686 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXDLY_CFG[13] origin:064-gtp-channel-conf 01_686 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXDLY_CFG[14] origin:064-gtp-channel-conf 00_687 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXDLY_CFG[15] origin:064-gtp-channel-conf 01_687 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXDLY_LCFG[0] origin:064-gtp-channel-conf 02_576 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXDLY_LCFG[1] origin:064-gtp-channel-conf 03_576 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXDLY_LCFG[2] origin:064-gtp-channel-conf 02_577 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXDLY_LCFG[3] origin:064-gtp-channel-conf 03_577 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXDLY_LCFG[4] origin:064-gtp-channel-conf 02_578 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXDLY_LCFG[5] origin:064-gtp-channel-conf 03_578 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXDLY_LCFG[6] origin:064-gtp-channel-conf 02_579 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXDLY_LCFG[7] origin:064-gtp-channel-conf 03_579 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXDLY_LCFG[8] origin:064-gtp-channel-conf 02_580 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXDLY_TAP_CFG[0] origin:064-gtp-channel-conf 00_672 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXDLY_TAP_CFG[1] origin:064-gtp-channel-conf 01_672 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXDLY_TAP_CFG[2] origin:064-gtp-channel-conf 00_673 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXDLY_TAP_CFG[3] origin:064-gtp-channel-conf 01_673 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXDLY_TAP_CFG[4] origin:064-gtp-channel-conf 00_674 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXDLY_TAP_CFG[5] origin:064-gtp-channel-conf 01_674 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXDLY_TAP_CFG[6] origin:064-gtp-channel-conf 00_675 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXDLY_TAP_CFG[7] origin:064-gtp-channel-conf 01_675 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXDLY_TAP_CFG[8] origin:064-gtp-channel-conf 00_676 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXDLY_TAP_CFG[9] origin:064-gtp-channel-conf 01_676 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXDLY_TAP_CFG[10] origin:064-gtp-channel-conf 00_677 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXDLY_TAP_CFG[11] origin:064-gtp-channel-conf 01_677 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXDLY_TAP_CFG[12] origin:064-gtp-channel-conf 00_678 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXDLY_TAP_CFG[13] origin:064-gtp-channel-conf 01_678 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXDLY_TAP_CFG[14] origin:064-gtp-channel-conf 00_679 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXDLY_TAP_CFG[15] origin:064-gtp-channel-conf 01_679 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXGEARBOX_EN origin:064-gtp-channel-conf 01_607 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXISCANRESET_TIME[0] origin:064-gtp-channel-conf 01_123 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXISCANRESET_TIME[1] origin:064-gtp-channel-conf 00_124 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXISCANRESET_TIME[2] origin:064-gtp-channel-conf 01_124 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXISCANRESET_TIME[3] origin:064-gtp-channel-conf 00_125 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXISCANRESET_TIME[4] origin:064-gtp-channel-conf 01_125 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPM_BIAS_STARTUP_DISABLE[0] origin:064-gtp-channel-conf 03_391 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPM_CFG[0] origin:064-gtp-channel-conf 02_328 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPM_CFG[1] origin:064-gtp-channel-conf 03_328 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPM_CFG[2] origin:064-gtp-channel-conf 02_329 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPM_CFG[3] origin:064-gtp-channel-conf 03_329 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPM_CM_CFG[0] origin:064-gtp-channel-conf 02_430 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPM_GC_CFG[0] origin:064-gtp-channel-conf 02_432 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPM_GC_CFG[1] origin:064-gtp-channel-conf 03_432 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPM_GC_CFG[2] origin:064-gtp-channel-conf 02_433 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPM_GC_CFG[3] origin:064-gtp-channel-conf 03_433 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPM_GC_CFG[4] origin:064-gtp-channel-conf 02_434 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPM_GC_CFG[5] origin:064-gtp-channel-conf 03_434 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPM_GC_CFG[6] origin:064-gtp-channel-conf 02_435 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPM_GC_CFG[7] origin:064-gtp-channel-conf 03_435 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPM_GC_CFG[8] origin:064-gtp-channel-conf 02_436 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPM_GC_CFG2[0] origin:064-gtp-channel-conf 03_442 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPM_GC_CFG2[1] origin:064-gtp-channel-conf 02_443 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPM_GC_CFG2[2] origin:064-gtp-channel-conf 03_443 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPM_HF_CFG[0] origin:064-gtp-channel-conf 00_336 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPM_HF_CFG[1] origin:064-gtp-channel-conf 01_336 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPM_HF_CFG[2] origin:064-gtp-channel-conf 00_337 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPM_HF_CFG[3] origin:064-gtp-channel-conf 01_337 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPM_HF_CFG[4] origin:064-gtp-channel-conf 00_338 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPM_HF_CFG[5] origin:064-gtp-channel-conf 01_338 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPM_HF_CFG[6] origin:064-gtp-channel-conf 00_339 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPM_HF_CFG[7] origin:064-gtp-channel-conf 01_339 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPM_HF_CFG[8] origin:064-gtp-channel-conf 00_340 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPM_HF_CFG[9] origin:064-gtp-channel-conf 01_340 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPM_HF_CFG[10] origin:064-gtp-channel-conf 00_341 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPM_HF_CFG[11] origin:064-gtp-channel-conf 01_341 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPM_HF_CFG[12] origin:064-gtp-channel-conf 00_342 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPM_HF_CFG[13] origin:064-gtp-channel-conf 01_342 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPM_HF_CFG2[0] origin:064-gtp-channel-conf 02_424 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPM_HF_CFG2[1] origin:064-gtp-channel-conf 03_424 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPM_HF_CFG2[2] origin:064-gtp-channel-conf 02_425 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPM_HF_CFG2[3] origin:064-gtp-channel-conf 03_425 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPM_HF_CFG2[4] origin:064-gtp-channel-conf 02_426 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPM_HF_CFG3[0] origin:064-gtp-channel-conf 03_389 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPM_HF_CFG3[1] origin:064-gtp-channel-conf 02_390 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPM_HF_CFG3[2] origin:064-gtp-channel-conf 03_390 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPM_HF_CFG3[3] origin:064-gtp-channel-conf 02_391 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPM_HOLD_DURING_EIDLE[0] origin:064-gtp-channel-conf 00_247 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPM_INCM_CFG[0] origin:064-gtp-channel-conf 02_439 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPM_IPCM_CFG[0] origin:064-gtp-channel-conf 03_439 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPM_LF_CFG[0] origin:064-gtp-channel-conf 00_344 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPM_LF_CFG[1] origin:064-gtp-channel-conf 01_344 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPM_LF_CFG[2] origin:064-gtp-channel-conf 00_345 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPM_LF_CFG[3] origin:064-gtp-channel-conf 01_345 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPM_LF_CFG[4] origin:064-gtp-channel-conf 00_346 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPM_LF_CFG[5] origin:064-gtp-channel-conf 01_346 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPM_LF_CFG[6] origin:064-gtp-channel-conf 00_347 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPM_LF_CFG[7] origin:064-gtp-channel-conf 01_347 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPM_LF_CFG[8] origin:064-gtp-channel-conf 00_348 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPM_LF_CFG[9] origin:064-gtp-channel-conf 01_348 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPM_LF_CFG[10] origin:064-gtp-channel-conf 00_349 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPM_LF_CFG[11] origin:064-gtp-channel-conf 01_349 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPM_LF_CFG[12] origin:064-gtp-channel-conf 00_350 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPM_LF_CFG[13] origin:064-gtp-channel-conf 01_350 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPM_LF_CFG[14] origin:064-gtp-channel-conf 00_351 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPM_LF_CFG[15] origin:064-gtp-channel-conf 01_351 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPM_LF_CFG[16] origin:064-gtp-channel-conf 00_343 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPM_LF_CFG[17] origin:064-gtp-channel-conf 01_343 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPM_LF_CFG2[0] origin:064-gtp-channel-conf 03_426 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPM_LF_CFG2[1] origin:064-gtp-channel-conf 02_427 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPM_LF_CFG2[2] origin:064-gtp-channel-conf 03_427 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPM_LF_CFG2[3] origin:064-gtp-channel-conf 02_428 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPM_LF_CFG2[4] origin:064-gtp-channel-conf 03_428 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPM_OSINT_CFG[0] origin:064-gtp-channel-conf 02_440 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPM_OSINT_CFG[1] origin:064-gtp-channel-conf 03_440 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPM_OSINT_CFG[2] origin:064-gtp-channel-conf 02_441 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPM_CFG1[0] origin:064-gtp-channel-conf 02_330 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPMRESET_TIME[0] origin:064-gtp-channel-conf 00_112 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPMRESET_TIME[1] origin:064-gtp-channel-conf 01_112 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPMRESET_TIME[2] origin:064-gtp-channel-conf 00_113 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPMRESET_TIME[3] origin:064-gtp-channel-conf 01_113 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPMRESET_TIME[4] origin:064-gtp-channel-conf 00_114 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPMRESET_TIME[5] origin:064-gtp-channel-conf 01_114 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXLPMRESET_TIME[6] origin:064-gtp-channel-conf 00_115 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXOOB_CFG[0] origin:064-gtp-channel-conf 00_144 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXOOB_CFG[1] origin:064-gtp-channel-conf 01_144 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXOOB_CFG[2] origin:064-gtp-channel-conf 00_145 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXOOB_CFG[3] origin:064-gtp-channel-conf 01_145 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXOOB_CFG[4] origin:064-gtp-channel-conf 00_146 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXOOB_CFG[5] origin:064-gtp-channel-conf 01_146 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXOOB_CFG[6] origin:064-gtp-channel-conf 00_147 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXOOB_CLK_CFG.FABRIC origin:064-gtp-channel-conf 03_129 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXOSCALRESET_TIME[0] origin:064-gtp-channel-conf 00_187 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXOSCALRESET_TIME[1] origin:064-gtp-channel-conf 01_187 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXOSCALRESET_TIME[2] origin:064-gtp-channel-conf 00_188 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXOSCALRESET_TIME[3] origin:064-gtp-channel-conf 01_188 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXOSCALRESET_TIME[4] origin:064-gtp-channel-conf 00_189 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXOSCALRESET_TIMEOUT[0] origin:064-gtp-channel-conf 01_189 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXOSCALRESET_TIMEOUT[1] origin:064-gtp-channel-conf 00_190 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXOSCALRESET_TIMEOUT[2] origin:064-gtp-channel-conf 01_190 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXOSCALRESET_TIMEOUT[3] origin:064-gtp-channel-conf 00_191 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXOSCALRESET_TIMEOUT[4] origin:064-gtp-channel-conf 01_191 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXOUT_DIV[0] origin:064-gtp-channel-conf 02_384 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXOUT_DIV[1] origin:064-gtp-channel-conf 03_384 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXPCSRESET_TIME[0] origin:064-gtp-channel-conf 01_115 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXPCSRESET_TIME[1] origin:064-gtp-channel-conf 00_116 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXPCSRESET_TIME[2] origin:064-gtp-channel-conf 01_116 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXPCSRESET_TIME[3] origin:064-gtp-channel-conf 00_117 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXPCSRESET_TIME[4] origin:064-gtp-channel-conf 01_117 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXPH_CFG[0] origin:064-gtp-channel-conf 02_584 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXPH_CFG[1] origin:064-gtp-channel-conf 03_584 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXPH_CFG[2] origin:064-gtp-channel-conf 02_585 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXPH_CFG[3] origin:064-gtp-channel-conf 03_585 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXPH_CFG[4] origin:064-gtp-channel-conf 02_586 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXPH_CFG[5] origin:064-gtp-channel-conf 03_586 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXPH_CFG[6] origin:064-gtp-channel-conf 02_587 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXPH_CFG[7] origin:064-gtp-channel-conf 03_587 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXPH_CFG[8] origin:064-gtp-channel-conf 02_588 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXPH_CFG[9] origin:064-gtp-channel-conf 03_588 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXPH_CFG[10] origin:064-gtp-channel-conf 02_589 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXPH_CFG[11] origin:064-gtp-channel-conf 03_589 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXPH_CFG[12] origin:064-gtp-channel-conf 02_590 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXPH_CFG[13] origin:064-gtp-channel-conf 03_590 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXPH_CFG[14] origin:064-gtp-channel-conf 02_591 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXPH_CFG[15] origin:064-gtp-channel-conf 03_591 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXPH_CFG[16] origin:064-gtp-channel-conf 02_592 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXPH_CFG[17] origin:064-gtp-channel-conf 03_592 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXPH_CFG[18] origin:064-gtp-channel-conf 02_593 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXPH_CFG[19] origin:064-gtp-channel-conf 03_593 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXPH_CFG[20] origin:064-gtp-channel-conf 02_594 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXPH_CFG[21] origin:064-gtp-channel-conf 03_594 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXPH_CFG[22] origin:064-gtp-channel-conf 02_595 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXPH_CFG[23] origin:064-gtp-channel-conf 03_595 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXPH_MONITOR_SEL[0] origin:064-gtp-channel-conf 00_700 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXPH_MONITOR_SEL[1] origin:064-gtp-channel-conf 01_700 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXPH_MONITOR_SEL[2] origin:064-gtp-channel-conf 00_701 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXPH_MONITOR_SEL[3] origin:064-gtp-channel-conf 01_701 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXPH_MONITOR_SEL[4] origin:064-gtp-channel-conf 00_702 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXPHDLY_CFG[0] origin:064-gtp-channel-conf 02_600 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXPHDLY_CFG[1] origin:064-gtp-channel-conf 03_600 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXPHDLY_CFG[2] origin:064-gtp-channel-conf 02_601 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXPHDLY_CFG[3] origin:064-gtp-channel-conf 03_601 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXPHDLY_CFG[4] origin:064-gtp-channel-conf 02_602 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXPHDLY_CFG[5] origin:064-gtp-channel-conf 03_602 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXPHDLY_CFG[6] origin:064-gtp-channel-conf 02_603 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXPHDLY_CFG[7] origin:064-gtp-channel-conf 03_603 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXPHDLY_CFG[8] origin:064-gtp-channel-conf 02_604 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXPHDLY_CFG[9] origin:064-gtp-channel-conf 03_604 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXPHDLY_CFG[10] origin:064-gtp-channel-conf 02_605 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXPHDLY_CFG[11] origin:064-gtp-channel-conf 03_605 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXPHDLY_CFG[12] origin:064-gtp-channel-conf 02_606 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXPHDLY_CFG[13] origin:064-gtp-channel-conf 03_606 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXPHDLY_CFG[14] origin:064-gtp-channel-conf 02_607 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXPHDLY_CFG[15] origin:064-gtp-channel-conf 03_607 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXPHDLY_CFG[16] origin:064-gtp-channel-conf 02_608 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXPHDLY_CFG[17] origin:064-gtp-channel-conf 03_608 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXPHDLY_CFG[18] origin:064-gtp-channel-conf 02_609 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXPHDLY_CFG[19] origin:064-gtp-channel-conf 03_609 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXPHDLY_CFG[20] origin:064-gtp-channel-conf 02_610 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXPHDLY_CFG[21] origin:064-gtp-channel-conf 03_610 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXPHDLY_CFG[22] origin:064-gtp-channel-conf 02_611 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXPHDLY_CFG[23] origin:064-gtp-channel-conf 03_611 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXPI_CFG0[0] origin:064-gtp-channel-conf 03_430 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXPI_CFG0[1] origin:064-gtp-channel-conf 02_431 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXPI_CFG0[2] origin:064-gtp-channel-conf 03_431 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXPI_CFG1[0] origin:064-gtp-channel-conf 02_442 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXPI_CFG2[0] origin:064-gtp-channel-conf 03_441 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXPMARESET_TIME[0] origin:064-gtp-channel-conf 00_104 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXPMARESET_TIME[1] origin:064-gtp-channel-conf 01_104 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXPMARESET_TIME[2] origin:064-gtp-channel-conf 00_105 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXPMARESET_TIME[3] origin:064-gtp-channel-conf 01_105 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXPMARESET_TIME[4] origin:064-gtp-channel-conf 00_106 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXPRBS_ERR_LOOPBACK[0] origin:064-gtp-channel-conf 00_136 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXSLIDE_AUTO_WAIT[0] origin:064-gtp-channel-conf 00_520 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXSLIDE_AUTO_WAIT[1] origin:064-gtp-channel-conf 01_520 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXSLIDE_AUTO_WAIT[2] origin:064-gtp-channel-conf 00_521 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXSLIDE_AUTO_WAIT[3] origin:064-gtp-channel-conf 01_521 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXSLIDE_MODE.AUTO origin:064-gtp-channel-conf !01_519 00_519 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXSLIDE_MODE.PCS origin:064-gtp-channel-conf !00_519 01_519 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXSLIDE_MODE.PMA origin:064-gtp-channel-conf 00_519 01_519 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXSYNC_MULTILANE[0] origin:064-gtp-channel-conf 00_133 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXSYNC_OVRD[0] origin:064-gtp-channel-conf 01_135 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.RXSYNC_SKIP_DA[0] origin:064-gtp-channel-conf 01_134 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.SAS_MAX_COM[0] origin:064-gtp-channel-conf 00_171 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.SAS_MAX_COM[1] origin:064-gtp-channel-conf 01_171 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.SAS_MAX_COM[2] origin:064-gtp-channel-conf 00_172 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.SAS_MAX_COM[3] origin:064-gtp-channel-conf 01_172 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.SAS_MAX_COM[4] origin:064-gtp-channel-conf 00_173 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.SAS_MAX_COM[5] origin:064-gtp-channel-conf 01_173 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.SAS_MAX_COM[6] origin:064-gtp-channel-conf 00_174 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.SAS_MIN_COM[0] origin:064-gtp-channel-conf 01_156 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.SAS_MIN_COM[1] origin:064-gtp-channel-conf 00_157 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.SAS_MIN_COM[2] origin:064-gtp-channel-conf 01_157 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.SAS_MIN_COM[3] origin:064-gtp-channel-conf 00_158 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.SAS_MIN_COM[4] origin:064-gtp-channel-conf 01_158 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.SAS_MIN_COM[5] origin:064-gtp-channel-conf 00_159 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.SATA_BURST_SEQ_LEN[0] origin:064-gtp-channel-conf 00_150 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.SATA_BURST_SEQ_LEN[1] origin:064-gtp-channel-conf 01_150 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.SATA_BURST_SEQ_LEN[2] origin:064-gtp-channel-conf 00_151 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.SATA_BURST_SEQ_LEN[3] origin:064-gtp-channel-conf 01_151 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.SATA_BURST_VAL[0] origin:064-gtp-channel-conf 01_147 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.SATA_BURST_VAL[1] origin:064-gtp-channel-conf 00_148 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.SATA_BURST_VAL[2] origin:064-gtp-channel-conf 01_148 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.SATA_EIDLE_VAL[0] origin:064-gtp-channel-conf 00_152 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.SATA_EIDLE_VAL[1] origin:064-gtp-channel-conf 01_152 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.SATA_EIDLE_VAL[2] origin:064-gtp-channel-conf 00_153 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.SATA_MAX_BURST[0] origin:064-gtp-channel-conf 00_168 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.SATA_MAX_BURST[1] origin:064-gtp-channel-conf 01_168 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.SATA_MAX_BURST[2] origin:064-gtp-channel-conf 00_169 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.SATA_MAX_BURST[3] origin:064-gtp-channel-conf 01_169 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.SATA_MAX_BURST[4] origin:064-gtp-channel-conf 00_170 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.SATA_MAX_BURST[5] origin:064-gtp-channel-conf 01_170 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.SATA_MAX_INIT[0] origin:064-gtp-channel-conf 00_176 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.SATA_MAX_INIT[1] origin:064-gtp-channel-conf 01_176 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.SATA_MAX_INIT[2] origin:064-gtp-channel-conf 00_177 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.SATA_MAX_INIT[3] origin:064-gtp-channel-conf 01_177 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.SATA_MAX_INIT[4] origin:064-gtp-channel-conf 00_178 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.SATA_MAX_INIT[5] origin:064-gtp-channel-conf 01_178 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.SATA_MAX_WAKE[0] origin:064-gtp-channel-conf 00_179 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.SATA_MAX_WAKE[1] origin:064-gtp-channel-conf 01_179 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.SATA_MAX_WAKE[2] origin:064-gtp-channel-conf 00_180 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.SATA_MAX_WAKE[3] origin:064-gtp-channel-conf 01_180 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.SATA_MAX_WAKE[4] origin:064-gtp-channel-conf 00_181 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.SATA_MAX_WAKE[5] origin:064-gtp-channel-conf 01_181 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.SATA_MIN_BURST[0] origin:064-gtp-channel-conf 01_153 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.SATA_MIN_BURST[1] origin:064-gtp-channel-conf 00_154 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.SATA_MIN_BURST[2] origin:064-gtp-channel-conf 01_154 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.SATA_MIN_BURST[3] origin:064-gtp-channel-conf 00_155 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.SATA_MIN_BURST[4] origin:064-gtp-channel-conf 01_155 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.SATA_MIN_BURST[5] origin:064-gtp-channel-conf 00_156 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.SATA_MIN_INIT[0] origin:064-gtp-channel-conf 00_160 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.SATA_MIN_INIT[1] origin:064-gtp-channel-conf 01_160 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.SATA_MIN_INIT[2] origin:064-gtp-channel-conf 00_161 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.SATA_MIN_INIT[3] origin:064-gtp-channel-conf 01_161 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.SATA_MIN_INIT[4] origin:064-gtp-channel-conf 00_162 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.SATA_MIN_INIT[5] origin:064-gtp-channel-conf 01_162 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.SATA_MIN_WAKE[0] origin:064-gtp-channel-conf 00_163 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.SATA_MIN_WAKE[1] origin:064-gtp-channel-conf 01_163 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.SATA_MIN_WAKE[2] origin:064-gtp-channel-conf 00_164 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.SATA_MIN_WAKE[3] origin:064-gtp-channel-conf 01_164 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.SATA_MIN_WAKE[4] origin:064-gtp-channel-conf 00_165 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.SATA_MIN_WAKE[5] origin:064-gtp-channel-conf 01_165 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.SATA_PLL_CFG.VCO_1500MHZ origin:064-gtp-channel-conf 02_55 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.SATA_PLL_CFG.VCO_750MHZ origin:064-gtp-channel-conf 03_55 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.SHOW_REALIGN_COMMA origin:064-gtp-channel-conf 01_522 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TERM_RCAL_CFG[0] origin:064-gtp-channel-conf 02_136 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TERM_RCAL_CFG[1] origin:064-gtp-channel-conf 03_136 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TERM_RCAL_CFG[2] origin:064-gtp-channel-conf 02_137 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TERM_RCAL_CFG[3] origin:064-gtp-channel-conf 03_137 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TERM_RCAL_CFG[4] origin:064-gtp-channel-conf 02_138 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TERM_RCAL_CFG[5] origin:064-gtp-channel-conf 03_138 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TERM_RCAL_CFG[6] origin:064-gtp-channel-conf 02_139 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TERM_RCAL_CFG[7] origin:064-gtp-channel-conf 03_139 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TERM_RCAL_CFG[8] origin:064-gtp-channel-conf 02_140 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TERM_RCAL_CFG[9] origin:064-gtp-channel-conf 03_140 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TERM_RCAL_CFG[10] origin:064-gtp-channel-conf 02_141 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TERM_RCAL_CFG[11] origin:064-gtp-channel-conf 03_141 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TERM_RCAL_CFG[12] origin:064-gtp-channel-conf 02_142 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TERM_RCAL_CFG[13] origin:064-gtp-channel-conf 03_142 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TERM_RCAL_CFG[14] origin:064-gtp-channel-conf 02_143 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TERM_RCAL_OVRD[0] origin:064-gtp-channel-conf 03_150 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TERM_RCAL_OVRD[1] origin:064-gtp-channel-conf 02_151 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TERM_RCAL_OVRD[2] origin:064-gtp-channel-conf 03_151 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TRANS_TIME_RATE[0] origin:064-gtp-channel-conf 00_192 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TRANS_TIME_RATE[1] origin:064-gtp-channel-conf 01_192 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TRANS_TIME_RATE[2] origin:064-gtp-channel-conf 00_193 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TRANS_TIME_RATE[3] origin:064-gtp-channel-conf 01_193 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TRANS_TIME_RATE[4] origin:064-gtp-channel-conf 00_194 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TRANS_TIME_RATE[5] origin:064-gtp-channel-conf 01_194 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TRANS_TIME_RATE[6] origin:064-gtp-channel-conf 00_195 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TRANS_TIME_RATE[7] origin:064-gtp-channel-conf 01_195 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TST_RSV[0] origin:064-gtp-channel-conf 02_504 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TST_RSV[1] origin:064-gtp-channel-conf 03_504 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TST_RSV[2] origin:064-gtp-channel-conf 02_505 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TST_RSV[3] origin:064-gtp-channel-conf 03_505 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TST_RSV[4] origin:064-gtp-channel-conf 02_506 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TST_RSV[5] origin:064-gtp-channel-conf 03_506 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TST_RSV[6] origin:064-gtp-channel-conf 02_507 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TST_RSV[7] origin:064-gtp-channel-conf 03_507 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TST_RSV[8] origin:064-gtp-channel-conf 02_508 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TST_RSV[9] origin:064-gtp-channel-conf 03_508 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TST_RSV[10] origin:064-gtp-channel-conf 02_509 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TST_RSV[11] origin:064-gtp-channel-conf 03_509 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TST_RSV[12] origin:064-gtp-channel-conf 02_510 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TST_RSV[13] origin:064-gtp-channel-conf 03_510 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TST_RSV[14] origin:064-gtp-channel-conf 02_511 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TST_RSV[15] origin:064-gtp-channel-conf 03_511 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TST_RSV[16] origin:064-gtp-channel-conf 02_512 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TST_RSV[17] origin:064-gtp-channel-conf 03_512 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TST_RSV[18] origin:064-gtp-channel-conf 02_513 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TST_RSV[19] origin:064-gtp-channel-conf 03_513 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TST_RSV[20] origin:064-gtp-channel-conf 02_514 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TST_RSV[21] origin:064-gtp-channel-conf 03_514 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TST_RSV[22] origin:064-gtp-channel-conf 02_515 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TST_RSV[23] origin:064-gtp-channel-conf 03_515 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TST_RSV[24] origin:064-gtp-channel-conf 02_516 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TST_RSV[25] origin:064-gtp-channel-conf 03_516 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TST_RSV[26] origin:064-gtp-channel-conf 02_517 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TST_RSV[27] origin:064-gtp-channel-conf 03_517 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TST_RSV[28] origin:064-gtp-channel-conf 02_518 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TST_RSV[29] origin:064-gtp-channel-conf 03_518 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TST_RSV[30] origin:064-gtp-channel-conf 02_519 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TST_RSV[31] origin:064-gtp-channel-conf 03_519 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_CLKMUX_EN[0] origin:064-gtp-channel-conf 03_128 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_DATA_WIDTH[0] origin:064-gtp-channel-conf 02_152 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_DATA_WIDTH[1] origin:064-gtp-channel-conf 03_152 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_DATA_WIDTH[2] origin:064-gtp-channel-conf 02_153 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_DRIVE_MODE.PIPE origin:064-gtp-channel-conf 00_200 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_EIDLE_ASSERT_DELAY[0] origin:064-gtp-channel-conf 00_203 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_EIDLE_ASSERT_DELAY[1] origin:064-gtp-channel-conf 01_203 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_EIDLE_ASSERT_DELAY[2] origin:064-gtp-channel-conf 00_204 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_EIDLE_DEASSERT_DELAY[0] origin:064-gtp-channel-conf 01_204 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_EIDLE_DEASSERT_DELAY[1] origin:064-gtp-channel-conf 00_205 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_EIDLE_DEASSERT_DELAY[2] origin:064-gtp-channel-conf 01_205 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_LOOPBACK_DRIVE_HIZ origin:064-gtp-channel-conf 01_202 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_MAINCURSOR_SEL[0] origin:064-gtp-channel-conf 03_289 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_MARGIN_FULL_0[0] origin:064-gtp-channel-conf 02_232 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_MARGIN_FULL_0[1] origin:064-gtp-channel-conf 03_232 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_MARGIN_FULL_0[2] origin:064-gtp-channel-conf 02_233 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_MARGIN_FULL_0[3] origin:064-gtp-channel-conf 03_233 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_MARGIN_FULL_0[4] origin:064-gtp-channel-conf 02_234 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_MARGIN_FULL_0[5] origin:064-gtp-channel-conf 03_234 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_MARGIN_FULL_0[6] origin:064-gtp-channel-conf 02_235 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_MARGIN_FULL_1[0] origin:064-gtp-channel-conf 02_236 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_MARGIN_FULL_1[1] origin:064-gtp-channel-conf 03_236 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_MARGIN_FULL_1[2] origin:064-gtp-channel-conf 02_237 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_MARGIN_FULL_1[3] origin:064-gtp-channel-conf 03_237 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_MARGIN_FULL_1[4] origin:064-gtp-channel-conf 02_238 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_MARGIN_FULL_1[5] origin:064-gtp-channel-conf 03_238 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_MARGIN_FULL_1[6] origin:064-gtp-channel-conf 02_239 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_MARGIN_FULL_2[0] origin:064-gtp-channel-conf 02_240 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_MARGIN_FULL_2[1] origin:064-gtp-channel-conf 03_240 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_MARGIN_FULL_2[2] origin:064-gtp-channel-conf 02_241 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_MARGIN_FULL_2[3] origin:064-gtp-channel-conf 03_241 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_MARGIN_FULL_2[4] origin:064-gtp-channel-conf 02_242 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_MARGIN_FULL_2[5] origin:064-gtp-channel-conf 03_242 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_MARGIN_FULL_2[6] origin:064-gtp-channel-conf 02_243 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_MARGIN_FULL_3[0] origin:064-gtp-channel-conf 02_244 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_MARGIN_FULL_3[1] origin:064-gtp-channel-conf 03_244 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_MARGIN_FULL_3[2] origin:064-gtp-channel-conf 02_245 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_MARGIN_FULL_3[3] origin:064-gtp-channel-conf 03_245 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_MARGIN_FULL_3[4] origin:064-gtp-channel-conf 02_246 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_MARGIN_FULL_3[5] origin:064-gtp-channel-conf 03_246 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_MARGIN_FULL_3[6] origin:064-gtp-channel-conf 02_247 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_MARGIN_FULL_4[0] origin:064-gtp-channel-conf 02_248 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_MARGIN_FULL_4[1] origin:064-gtp-channel-conf 03_248 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_MARGIN_FULL_4[2] origin:064-gtp-channel-conf 02_249 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_MARGIN_FULL_4[3] origin:064-gtp-channel-conf 03_249 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_MARGIN_FULL_4[4] origin:064-gtp-channel-conf 02_250 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_MARGIN_FULL_4[5] origin:064-gtp-channel-conf 03_250 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_MARGIN_FULL_4[6] origin:064-gtp-channel-conf 02_251 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_MARGIN_LOW_0[0] origin:064-gtp-channel-conf 02_252 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_MARGIN_LOW_0[1] origin:064-gtp-channel-conf 03_252 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_MARGIN_LOW_0[2] origin:064-gtp-channel-conf 02_253 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_MARGIN_LOW_0[3] origin:064-gtp-channel-conf 03_253 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_MARGIN_LOW_0[4] origin:064-gtp-channel-conf 02_254 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_MARGIN_LOW_0[5] origin:064-gtp-channel-conf 03_254 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_MARGIN_LOW_0[6] origin:064-gtp-channel-conf 02_255 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_MARGIN_LOW_1[0] origin:064-gtp-channel-conf 02_256 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_MARGIN_LOW_1[1] origin:064-gtp-channel-conf 03_256 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_MARGIN_LOW_1[2] origin:064-gtp-channel-conf 02_257 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_MARGIN_LOW_1[3] origin:064-gtp-channel-conf 03_257 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_MARGIN_LOW_1[4] origin:064-gtp-channel-conf 02_258 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_MARGIN_LOW_1[5] origin:064-gtp-channel-conf 03_258 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_MARGIN_LOW_1[6] origin:064-gtp-channel-conf 02_259 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_MARGIN_LOW_2[0] origin:064-gtp-channel-conf 02_260 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_MARGIN_LOW_2[1] origin:064-gtp-channel-conf 03_260 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_MARGIN_LOW_2[2] origin:064-gtp-channel-conf 02_261 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_MARGIN_LOW_2[3] origin:064-gtp-channel-conf 03_261 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_MARGIN_LOW_2[4] origin:064-gtp-channel-conf 02_262 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_MARGIN_LOW_2[5] origin:064-gtp-channel-conf 03_262 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_MARGIN_LOW_2[6] origin:064-gtp-channel-conf 02_263 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_MARGIN_LOW_3[0] origin:064-gtp-channel-conf 02_264 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_MARGIN_LOW_3[1] origin:064-gtp-channel-conf 03_264 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_MARGIN_LOW_3[2] origin:064-gtp-channel-conf 02_265 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_MARGIN_LOW_3[3] origin:064-gtp-channel-conf 03_265 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_MARGIN_LOW_3[4] origin:064-gtp-channel-conf 02_266 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_MARGIN_LOW_3[5] origin:064-gtp-channel-conf 03_266 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_MARGIN_LOW_3[6] origin:064-gtp-channel-conf 02_267 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_MARGIN_LOW_4[0] origin:064-gtp-channel-conf 02_268 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_MARGIN_LOW_4[1] origin:064-gtp-channel-conf 03_268 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_MARGIN_LOW_4[2] origin:064-gtp-channel-conf 02_269 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_MARGIN_LOW_4[3] origin:064-gtp-channel-conf 03_269 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_MARGIN_LOW_4[4] origin:064-gtp-channel-conf 02_270 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_MARGIN_LOW_4[5] origin:064-gtp-channel-conf 03_270 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_MARGIN_LOW_4[6] origin:064-gtp-channel-conf 02_271 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_PREDRIVER_MODE[0] origin:064-gtp-channel-conf 00_206 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_RXDETECT_CFG[0] origin:064-gtp-channel-conf 02_296 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_RXDETECT_CFG[1] origin:064-gtp-channel-conf 03_296 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_RXDETECT_CFG[2] origin:064-gtp-channel-conf 02_297 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_RXDETECT_CFG[3] origin:064-gtp-channel-conf 03_297 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_RXDETECT_CFG[4] origin:064-gtp-channel-conf 02_298 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_RXDETECT_CFG[5] origin:064-gtp-channel-conf 03_298 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_RXDETECT_CFG[6] origin:064-gtp-channel-conf 02_299 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_RXDETECT_CFG[7] origin:064-gtp-channel-conf 03_299 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_RXDETECT_CFG[8] origin:064-gtp-channel-conf 02_300 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_RXDETECT_CFG[9] origin:064-gtp-channel-conf 03_300 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_RXDETECT_CFG[10] origin:064-gtp-channel-conf 02_301 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_RXDETECT_CFG[11] origin:064-gtp-channel-conf 03_301 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_RXDETECT_CFG[12] origin:064-gtp-channel-conf 02_302 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_RXDETECT_CFG[13] origin:064-gtp-channel-conf 03_302 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_RXDETECT_REF[0] origin:064-gtp-channel-conf 02_292 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_RXDETECT_REF[1] origin:064-gtp-channel-conf 03_292 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_RXDETECT_REF[2] origin:064-gtp-channel-conf 02_293 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_XCLK_SEL.TXUSR origin:064-gtp-channel-conf 03_11 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_CLK25_DIV[0] origin:064-gtp-channel-conf 02_144 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_CLK25_DIV[1] origin:064-gtp-channel-conf 03_144 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_CLK25_DIV[2] origin:064-gtp-channel-conf 02_145 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_CLK25_DIV[3] origin:064-gtp-channel-conf 03_145 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_CLK25_DIV[4] origin:064-gtp-channel-conf 02_146 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_DEEMPH0[0] origin:064-gtp-channel-conf 02_272 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_DEEMPH0[1] origin:064-gtp-channel-conf 03_272 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_DEEMPH0[2] origin:064-gtp-channel-conf 02_273 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_DEEMPH0[3] origin:064-gtp-channel-conf 03_273 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_DEEMPH0[4] origin:064-gtp-channel-conf 02_274 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_DEEMPH0[5] origin:064-gtp-channel-conf 03_274 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_DEEMPH1[0] origin:064-gtp-channel-conf 02_276 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_DEEMPH1[1] origin:064-gtp-channel-conf 03_276 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_DEEMPH1[2] origin:064-gtp-channel-conf 02_277 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_DEEMPH1[3] origin:064-gtp-channel-conf 03_277 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_DEEMPH1[4] origin:064-gtp-channel-conf 02_278 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TX_DEEMPH1[5] origin:064-gtp-channel-conf 03_278 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXBUF_EN origin:064-gtp-channel-conf 00_231 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXBUF_RESET_ON_RATE_CHANGE origin:064-gtp-channel-conf 01_231 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXDLY_CFG[0] origin:064-gtp-channel-conf 02_80 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXDLY_CFG[1] origin:064-gtp-channel-conf 03_80 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXDLY_CFG[2] origin:064-gtp-channel-conf 02_81 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXDLY_CFG[3] origin:064-gtp-channel-conf 03_81 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXDLY_CFG[4] origin:064-gtp-channel-conf 02_82 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXDLY_CFG[5] origin:064-gtp-channel-conf 03_82 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXDLY_CFG[6] origin:064-gtp-channel-conf 02_83 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXDLY_CFG[7] origin:064-gtp-channel-conf 03_83 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXDLY_CFG[8] origin:064-gtp-channel-conf 02_84 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXDLY_CFG[9] origin:064-gtp-channel-conf 03_84 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXDLY_CFG[10] origin:064-gtp-channel-conf 02_85 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXDLY_CFG[11] origin:064-gtp-channel-conf 03_85 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXDLY_CFG[12] origin:064-gtp-channel-conf 02_86 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXDLY_CFG[13] origin:064-gtp-channel-conf 03_86 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXDLY_CFG[14] origin:064-gtp-channel-conf 02_87 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXDLY_CFG[15] origin:064-gtp-channel-conf 03_87 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXDLY_LCFG[0] origin:064-gtp-channel-conf 02_568 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXDLY_LCFG[1] origin:064-gtp-channel-conf 03_568 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXDLY_LCFG[2] origin:064-gtp-channel-conf 02_569 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXDLY_LCFG[3] origin:064-gtp-channel-conf 03_569 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXDLY_LCFG[4] origin:064-gtp-channel-conf 02_570 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXDLY_LCFG[5] origin:064-gtp-channel-conf 03_570 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXDLY_LCFG[6] origin:064-gtp-channel-conf 02_571 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXDLY_LCFG[7] origin:064-gtp-channel-conf 03_571 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXDLY_LCFG[8] origin:064-gtp-channel-conf 02_572 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXDLY_TAP_CFG[0] origin:064-gtp-channel-conf 02_88 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXDLY_TAP_CFG[1] origin:064-gtp-channel-conf 03_88 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXDLY_TAP_CFG[2] origin:064-gtp-channel-conf 02_89 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXDLY_TAP_CFG[3] origin:064-gtp-channel-conf 03_89 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXDLY_TAP_CFG[4] origin:064-gtp-channel-conf 02_90 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXDLY_TAP_CFG[5] origin:064-gtp-channel-conf 03_90 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXDLY_TAP_CFG[6] origin:064-gtp-channel-conf 02_91 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXDLY_TAP_CFG[7] origin:064-gtp-channel-conf 03_91 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXDLY_TAP_CFG[8] origin:064-gtp-channel-conf 02_92 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXDLY_TAP_CFG[9] origin:064-gtp-channel-conf 03_92 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXDLY_TAP_CFG[10] origin:064-gtp-channel-conf 02_93 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXDLY_TAP_CFG[11] origin:064-gtp-channel-conf 03_93 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXDLY_TAP_CFG[12] origin:064-gtp-channel-conf 02_94 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXDLY_TAP_CFG[13] origin:064-gtp-channel-conf 03_94 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXDLY_TAP_CFG[14] origin:064-gtp-channel-conf 02_95 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXDLY_TAP_CFG[15] origin:064-gtp-channel-conf 03_95 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXGEARBOX_EN origin:064-gtp-channel-conf 01_226 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXOOB_CFG[0] origin:064-gtp-channel-conf 03_20 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXOUT_DIV[0] origin:064-gtp-channel-conf 02_386 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXOUT_DIV[1] origin:064-gtp-channel-conf 03_386 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPCSRESET_TIME[0] origin:064-gtp-channel-conf 01_130 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPCSRESET_TIME[1] origin:064-gtp-channel-conf 00_131 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPCSRESET_TIME[2] origin:064-gtp-channel-conf 01_131 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPCSRESET_TIME[3] origin:064-gtp-channel-conf 00_132 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPCSRESET_TIME[4] origin:064-gtp-channel-conf 01_132 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPH_CFG[0] origin:064-gtp-channel-conf 02_96 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPH_CFG[1] origin:064-gtp-channel-conf 03_96 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPH_CFG[2] origin:064-gtp-channel-conf 02_97 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPH_CFG[3] origin:064-gtp-channel-conf 03_97 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPH_CFG[4] origin:064-gtp-channel-conf 02_98 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPH_CFG[5] origin:064-gtp-channel-conf 03_98 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPH_CFG[6] origin:064-gtp-channel-conf 02_99 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPH_CFG[7] origin:064-gtp-channel-conf 03_99 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPH_CFG[8] origin:064-gtp-channel-conf 02_100 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPH_CFG[9] origin:064-gtp-channel-conf 03_100 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPH_CFG[10] origin:064-gtp-channel-conf 02_101 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPH_CFG[11] origin:064-gtp-channel-conf 03_101 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPH_CFG[12] origin:064-gtp-channel-conf 02_102 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPH_CFG[13] origin:064-gtp-channel-conf 03_102 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPH_CFG[14] origin:064-gtp-channel-conf 02_103 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPH_CFG[15] origin:064-gtp-channel-conf 03_103 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPH_MONITOR_SEL[0] origin:064-gtp-channel-conf 02_108 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPH_MONITOR_SEL[1] origin:064-gtp-channel-conf 03_108 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPH_MONITOR_SEL[2] origin:064-gtp-channel-conf 02_109 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPH_MONITOR_SEL[3] origin:064-gtp-channel-conf 03_109 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPH_MONITOR_SEL[4] origin:064-gtp-channel-conf 02_110 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPHDLY_CFG[0] origin:064-gtp-channel-conf 02_64 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPHDLY_CFG[1] origin:064-gtp-channel-conf 03_64 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPHDLY_CFG[2] origin:064-gtp-channel-conf 02_65 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPHDLY_CFG[3] origin:064-gtp-channel-conf 03_65 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPHDLY_CFG[4] origin:064-gtp-channel-conf 02_66 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPHDLY_CFG[5] origin:064-gtp-channel-conf 03_66 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPHDLY_CFG[6] origin:064-gtp-channel-conf 02_67 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPHDLY_CFG[7] origin:064-gtp-channel-conf 03_67 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPHDLY_CFG[8] origin:064-gtp-channel-conf 02_68 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPHDLY_CFG[9] origin:064-gtp-channel-conf 03_68 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPHDLY_CFG[10] origin:064-gtp-channel-conf 02_69 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPHDLY_CFG[11] origin:064-gtp-channel-conf 03_69 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPHDLY_CFG[12] origin:064-gtp-channel-conf 02_70 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPHDLY_CFG[13] origin:064-gtp-channel-conf 03_70 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPHDLY_CFG[14] origin:064-gtp-channel-conf 02_71 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPHDLY_CFG[15] origin:064-gtp-channel-conf 03_71 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPHDLY_CFG[16] origin:064-gtp-channel-conf 02_72 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPHDLY_CFG[17] origin:064-gtp-channel-conf 03_72 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPHDLY_CFG[18] origin:064-gtp-channel-conf 02_73 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPHDLY_CFG[19] origin:064-gtp-channel-conf 03_73 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPHDLY_CFG[20] origin:064-gtp-channel-conf 02_74 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPHDLY_CFG[21] origin:064-gtp-channel-conf 03_74 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPHDLY_CFG[22] origin:064-gtp-channel-conf 02_75 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPHDLY_CFG[23] origin:064-gtp-channel-conf 03_75 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPI_GREY_SEL[0] origin:064-gtp-channel-conf 03_498 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPI_INVSTROBE_SEL[0] origin:064-gtp-channel-conf 02_498 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPI_PPM_CFG[0] origin:064-gtp-channel-conf 02_488 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPI_PPM_CFG[1] origin:064-gtp-channel-conf 03_488 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPI_PPM_CFG[2] origin:064-gtp-channel-conf 02_489 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPI_PPM_CFG[3] origin:064-gtp-channel-conf 03_489 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPI_PPM_CFG[4] origin:064-gtp-channel-conf 02_490 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPI_PPM_CFG[5] origin:064-gtp-channel-conf 03_490 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPI_PPM_CFG[6] origin:064-gtp-channel-conf 02_491 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPI_PPM_CFG[7] origin:064-gtp-channel-conf 03_491 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPI_PPMCLK_SEL.TXUSRCLK2 origin:064-gtp-channel-conf 03_497 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPI_SYNFREQ_PPM[0] origin:064-gtp-channel-conf 02_496 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPI_SYNFREQ_PPM[1] origin:064-gtp-channel-conf 03_496 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPI_SYNFREQ_PPM[2] origin:064-gtp-channel-conf 02_497 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPI_CFG0[0] origin:064-gtp-channel-conf 02_40 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPI_CFG0[1] origin:064-gtp-channel-conf 03_40 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPI_CFG1[0] origin:064-gtp-channel-conf 02_41 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPI_CFG1[1] origin:064-gtp-channel-conf 03_41 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPI_CFG2[0] origin:064-gtp-channel-conf 02_42 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPI_CFG2[1] origin:064-gtp-channel-conf 03_42 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPI_CFG3[0] origin:064-gtp-channel-conf 02_43 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPI_CFG4[0] origin:064-gtp-channel-conf 03_43 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPI_CFG5[0] origin:064-gtp-channel-conf 02_44 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPI_CFG5[1] origin:064-gtp-channel-conf 03_44 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPI_CFG5[2] origin:064-gtp-channel-conf 02_45 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPMARESET_TIME[0] origin:064-gtp-channel-conf 00_128 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPMARESET_TIME[1] origin:064-gtp-channel-conf 01_128 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPMARESET_TIME[2] origin:064-gtp-channel-conf 00_129 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPMARESET_TIME[3] origin:064-gtp-channel-conf 01_129 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXPMARESET_TIME[4] origin:064-gtp-channel-conf 00_130 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXSYNC_MULTILANE[0] origin:064-gtp-channel-conf 01_133 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXSYNC_OVRD[0] origin:064-gtp-channel-conf 00_135 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.TXSYNC_SKIP_DA[0] origin:064-gtp-channel-conf 00_134 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.UCODEER_CLR[0] origin:064-gtp-channel-conf 01_00 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.USE_PCS_CLK_PHASE_SEL[0] origin:064-gtp-channel-conf 02_463 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ZINV_DMONITORCLK origin:064-gtp-channel-conf 02_13 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ZINV_DRPCLK origin:064-gtp-channel-conf 02_00 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ZINV_RXUSRCLK origin:064-gtp-channel-conf 03_01 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ZINV_SIGVALIDCLK origin:064-gtp-channel-conf 03_13 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ZINV_TXPHDLYTSTCLK origin:064-gtp-channel-conf 02_03 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ZINV_TXUSRCLK origin:064-gtp-channel-conf 03_04 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ZINV_CLKRSVD0 origin:064-gtp-channel-conf 02_23 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ZINV_CLKRSVD1 origin:064-gtp-channel-conf 03_23 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ZINV_RXUSRCLK2 origin:064-gtp-channel-conf 02_02 -GTP_CHANNEL_0_MID_RIGHT.GTPE2.ZINV_TXUSRCLK2 origin:064-gtp-channel-conf 02_05 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ACJTAG_DEBUG_MODE[0] origin:064-gtp-channel-conf 00_07 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ACJTAG_MODE[0] origin:064-gtp-channel-conf 01_06 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ACJTAG_RESET[0] origin:064-gtp-channel-conf 01_07 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[0] origin:064-gtp-channel-conf 02_464 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[1] origin:064-gtp-channel-conf 03_464 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[2] origin:064-gtp-channel-conf 02_465 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[3] origin:064-gtp-channel-conf 03_465 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[4] origin:064-gtp-channel-conf 02_466 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[5] origin:064-gtp-channel-conf 03_466 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[6] origin:064-gtp-channel-conf 02_467 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[7] origin:064-gtp-channel-conf 03_467 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[8] origin:064-gtp-channel-conf 02_468 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[9] origin:064-gtp-channel-conf 03_468 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[10] origin:064-gtp-channel-conf 02_469 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[11] origin:064-gtp-channel-conf 03_469 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[12] origin:064-gtp-channel-conf 02_470 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[13] origin:064-gtp-channel-conf 03_470 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[14] origin:064-gtp-channel-conf 02_471 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[15] origin:064-gtp-channel-conf 03_471 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[16] origin:064-gtp-channel-conf 02_472 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[17] origin:064-gtp-channel-conf 03_472 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[18] origin:064-gtp-channel-conf 02_473 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[19] origin:064-gtp-channel-conf 03_473 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ALIGN_COMMA_DOUBLE origin:064-gtp-channel-conf 00_522 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[0] origin:064-gtp-channel-conf 00_496 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[1] origin:064-gtp-channel-conf 01_496 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[2] origin:064-gtp-channel-conf 00_497 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[3] origin:064-gtp-channel-conf 01_497 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[4] origin:064-gtp-channel-conf 00_498 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[5] origin:064-gtp-channel-conf 01_498 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[6] origin:064-gtp-channel-conf 00_499 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[7] origin:064-gtp-channel-conf 01_499 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[8] origin:064-gtp-channel-conf 00_500 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[9] origin:064-gtp-channel-conf 01_500 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ALIGN_COMMA_WORD[0] origin:064-gtp-channel-conf 01_526 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ALIGN_COMMA_WORD[1] origin:064-gtp-channel-conf 00_527 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ALIGN_MCOMMA_DET origin:064-gtp-channel-conf 00_523 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[0] origin:064-gtp-channel-conf 00_504 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[1] origin:064-gtp-channel-conf 01_504 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[2] origin:064-gtp-channel-conf 00_505 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[3] origin:064-gtp-channel-conf 01_505 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[4] origin:064-gtp-channel-conf 00_506 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[5] origin:064-gtp-channel-conf 01_506 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[6] origin:064-gtp-channel-conf 00_507 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[7] origin:064-gtp-channel-conf 01_507 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[8] origin:064-gtp-channel-conf 00_508 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[9] origin:064-gtp-channel-conf 01_508 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ALIGN_PCOMMA_DET origin:064-gtp-channel-conf 01_523 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[0] origin:064-gtp-channel-conf 00_512 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[1] origin:064-gtp-channel-conf 01_512 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[2] origin:064-gtp-channel-conf 00_513 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[3] origin:064-gtp-channel-conf 01_513 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[4] origin:064-gtp-channel-conf 00_514 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[5] origin:064-gtp-channel-conf 01_514 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[6] origin:064-gtp-channel-conf 00_515 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[7] origin:064-gtp-channel-conf 01_515 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[8] origin:064-gtp-channel-conf 00_516 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[9] origin:064-gtp-channel-conf 01_516 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CBCC_DATA_SOURCE_SEL.DECODED origin:064-gtp-channel-conf 01_661 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[0] origin:064-gtp-channel-conf 02_392 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[1] origin:064-gtp-channel-conf 03_392 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[2] origin:064-gtp-channel-conf 02_393 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[3] origin:064-gtp-channel-conf 03_393 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[4] origin:064-gtp-channel-conf 02_394 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[5] origin:064-gtp-channel-conf 03_394 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[6] origin:064-gtp-channel-conf 02_395 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[7] origin:064-gtp-channel-conf 03_395 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[8] origin:064-gtp-channel-conf 02_396 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[9] origin:064-gtp-channel-conf 03_396 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[10] origin:064-gtp-channel-conf 02_397 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[11] origin:064-gtp-channel-conf 03_397 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[12] origin:064-gtp-channel-conf 02_398 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[13] origin:064-gtp-channel-conf 03_398 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[14] origin:064-gtp-channel-conf 02_399 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[15] origin:064-gtp-channel-conf 03_399 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[16] origin:064-gtp-channel-conf 02_400 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[17] origin:064-gtp-channel-conf 03_400 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[18] origin:064-gtp-channel-conf 02_401 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[19] origin:064-gtp-channel-conf 03_401 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[20] origin:064-gtp-channel-conf 02_402 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[21] origin:064-gtp-channel-conf 03_402 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[22] origin:064-gtp-channel-conf 02_403 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[23] origin:064-gtp-channel-conf 03_403 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[24] origin:064-gtp-channel-conf 02_404 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[25] origin:064-gtp-channel-conf 03_404 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[26] origin:064-gtp-channel-conf 02_405 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[27] origin:064-gtp-channel-conf 03_405 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[28] origin:064-gtp-channel-conf 02_406 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[29] origin:064-gtp-channel-conf 03_406 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[30] origin:064-gtp-channel-conf 02_407 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[31] origin:064-gtp-channel-conf 03_407 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[32] origin:064-gtp-channel-conf 02_408 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[33] origin:064-gtp-channel-conf 03_408 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[34] origin:064-gtp-channel-conf 02_409 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[35] origin:064-gtp-channel-conf 03_409 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[36] origin:064-gtp-channel-conf 02_410 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[37] origin:064-gtp-channel-conf 03_410 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[38] origin:064-gtp-channel-conf 02_411 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[39] origin:064-gtp-channel-conf 03_411 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[40] origin:064-gtp-channel-conf 02_412 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[41] origin:064-gtp-channel-conf 03_412 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[42] origin:064-gtp-channel-conf 02_413 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG2[0] origin:064-gtp-channel-conf 02_459 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG2[1] origin:064-gtp-channel-conf 03_459 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG2[2] origin:064-gtp-channel-conf 02_460 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG2[3] origin:064-gtp-channel-conf 03_460 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG2[4] origin:064-gtp-channel-conf 02_461 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG2[5] origin:064-gtp-channel-conf 03_461 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG2[6] origin:064-gtp-channel-conf 02_462 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG3[0] origin:064-gtp-channel-conf 02_416 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG3[1] origin:064-gtp-channel-conf 03_416 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG3[2] origin:064-gtp-channel-conf 02_417 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG3[3] origin:064-gtp-channel-conf 03_417 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG3[4] origin:064-gtp-channel-conf 02_418 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG3[5] origin:064-gtp-channel-conf 03_418 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG3[6] origin:064-gtp-channel-conf 02_419 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG4[0] origin:064-gtp-channel-conf 03_438 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG5[0] origin:064-gtp-channel-conf 02_429 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG5[1] origin:064-gtp-channel-conf 03_429 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG6[0] origin:064-gtp-channel-conf 03_436 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG6[1] origin:064-gtp-channel-conf 02_437 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG6[2] origin:064-gtp-channel-conf 03_437 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG6[3] origin:064-gtp-channel-conf 02_438 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_KEEP_ALIGN origin:064-gtp-channel-conf 01_631 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_MAX_SKEW[0] origin:064-gtp-channel-conf 00_670 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_MAX_SKEW[1] origin:064-gtp-channel-conf 01_670 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_MAX_SKEW[2] origin:064-gtp-channel-conf 00_671 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_MAX_SKEW[3] origin:064-gtp-channel-conf 01_671 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[0] origin:064-gtp-channel-conf 00_608 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[1] origin:064-gtp-channel-conf 01_608 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[2] origin:064-gtp-channel-conf 00_609 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[3] origin:064-gtp-channel-conf 01_609 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[4] origin:064-gtp-channel-conf 00_610 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[5] origin:064-gtp-channel-conf 01_610 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[6] origin:064-gtp-channel-conf 00_611 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[7] origin:064-gtp-channel-conf 01_611 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[8] origin:064-gtp-channel-conf 00_612 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[9] origin:064-gtp-channel-conf 01_612 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[0] origin:064-gtp-channel-conf 00_616 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[1] origin:064-gtp-channel-conf 01_616 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[2] origin:064-gtp-channel-conf 00_617 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[3] origin:064-gtp-channel-conf 01_617 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[4] origin:064-gtp-channel-conf 00_618 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[5] origin:064-gtp-channel-conf 01_618 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[6] origin:064-gtp-channel-conf 00_619 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[7] origin:064-gtp-channel-conf 01_619 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[8] origin:064-gtp-channel-conf 00_620 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[9] origin:064-gtp-channel-conf 01_620 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[0] origin:064-gtp-channel-conf 00_624 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[1] origin:064-gtp-channel-conf 01_624 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[2] origin:064-gtp-channel-conf 00_625 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[3] origin:064-gtp-channel-conf 01_625 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[4] origin:064-gtp-channel-conf 00_626 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[5] origin:064-gtp-channel-conf 01_626 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[6] origin:064-gtp-channel-conf 00_627 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[7] origin:064-gtp-channel-conf 01_627 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[8] origin:064-gtp-channel-conf 00_628 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[9] origin:064-gtp-channel-conf 01_628 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[0] origin:064-gtp-channel-conf 00_632 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[1] origin:064-gtp-channel-conf 01_632 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[2] origin:064-gtp-channel-conf 00_633 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[3] origin:064-gtp-channel-conf 01_633 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[4] origin:064-gtp-channel-conf 00_634 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[5] origin:064-gtp-channel-conf 01_634 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[6] origin:064-gtp-channel-conf 00_635 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[7] origin:064-gtp-channel-conf 01_635 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[8] origin:064-gtp-channel-conf 00_636 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[9] origin:064-gtp-channel-conf 01_636 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_ENABLE[0] origin:064-gtp-channel-conf 00_614 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_ENABLE[1] origin:064-gtp-channel-conf 01_614 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_ENABLE[2] origin:064-gtp-channel-conf 00_615 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_ENABLE[3] origin:064-gtp-channel-conf 01_615 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[0] origin:064-gtp-channel-conf 00_640 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[1] origin:064-gtp-channel-conf 01_640 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[2] origin:064-gtp-channel-conf 00_641 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[3] origin:064-gtp-channel-conf 01_641 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[4] origin:064-gtp-channel-conf 00_642 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[5] origin:064-gtp-channel-conf 01_642 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[6] origin:064-gtp-channel-conf 00_643 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[7] origin:064-gtp-channel-conf 01_643 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[8] origin:064-gtp-channel-conf 00_644 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[9] origin:064-gtp-channel-conf 01_644 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[0] origin:064-gtp-channel-conf 00_648 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[1] origin:064-gtp-channel-conf 01_648 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[2] origin:064-gtp-channel-conf 00_649 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[3] origin:064-gtp-channel-conf 01_649 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[4] origin:064-gtp-channel-conf 00_650 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[5] origin:064-gtp-channel-conf 01_650 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[6] origin:064-gtp-channel-conf 00_651 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[7] origin:064-gtp-channel-conf 01_651 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[8] origin:064-gtp-channel-conf 00_652 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[9] origin:064-gtp-channel-conf 01_652 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[0] origin:064-gtp-channel-conf 00_656 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[1] origin:064-gtp-channel-conf 01_656 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[2] origin:064-gtp-channel-conf 00_657 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[3] origin:064-gtp-channel-conf 01_657 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[4] origin:064-gtp-channel-conf 00_658 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[5] origin:064-gtp-channel-conf 01_658 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[6] origin:064-gtp-channel-conf 00_659 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[7] origin:064-gtp-channel-conf 01_659 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[8] origin:064-gtp-channel-conf 00_660 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[9] origin:064-gtp-channel-conf 01_660 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[0] origin:064-gtp-channel-conf 00_664 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[1] origin:064-gtp-channel-conf 01_664 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[2] origin:064-gtp-channel-conf 00_665 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[3] origin:064-gtp-channel-conf 01_665 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[4] origin:064-gtp-channel-conf 00_666 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[5] origin:064-gtp-channel-conf 01_666 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[6] origin:064-gtp-channel-conf 00_667 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[7] origin:064-gtp-channel-conf 01_667 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[8] origin:064-gtp-channel-conf 00_668 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[9] origin:064-gtp-channel-conf 01_668 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_ENABLE[0] origin:064-gtp-channel-conf 00_646 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_ENABLE[1] origin:064-gtp-channel-conf 01_646 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_ENABLE[2] origin:064-gtp-channel-conf 00_647 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_ENABLE[3] origin:064-gtp-channel-conf 01_647 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_USE origin:064-gtp-channel-conf 01_645 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_LEN[0] origin:064-gtp-channel-conf 00_623 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_LEN[1] origin:064-gtp-channel-conf 01_623 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COMMON_SWING[0] origin:064-gtp-channel-conf 03_311 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_KEEP_IDLE origin:064-gtp-channel-conf 00_591 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_MAX_LAT[0] origin:064-gtp-channel-conf 00_557 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_MAX_LAT[1] origin:064-gtp-channel-conf 01_557 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_MAX_LAT[2] origin:064-gtp-channel-conf 00_558 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_MAX_LAT[3] origin:064-gtp-channel-conf 01_558 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_MAX_LAT[4] origin:064-gtp-channel-conf 00_559 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_MAX_LAT[5] origin:064-gtp-channel-conf 01_559 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_MIN_LAT[0] origin:064-gtp-channel-conf 00_565 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_MIN_LAT[1] origin:064-gtp-channel-conf 01_565 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_MIN_LAT[2] origin:064-gtp-channel-conf 00_566 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_MIN_LAT[3] origin:064-gtp-channel-conf 01_566 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_MIN_LAT[4] origin:064-gtp-channel-conf 00_567 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_MIN_LAT[5] origin:064-gtp-channel-conf 01_567 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_PRECEDENCE origin:064-gtp-channel-conf 00_590 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_REPEAT_WAIT[0] origin:064-gtp-channel-conf 00_573 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_REPEAT_WAIT[1] origin:064-gtp-channel-conf 01_573 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_REPEAT_WAIT[2] origin:064-gtp-channel-conf 00_574 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_REPEAT_WAIT[3] origin:064-gtp-channel-conf 01_574 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_REPEAT_WAIT[4] origin:064-gtp-channel-conf 00_575 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[0] origin:064-gtp-channel-conf 00_544 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[1] origin:064-gtp-channel-conf 01_544 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[2] origin:064-gtp-channel-conf 00_545 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[3] origin:064-gtp-channel-conf 01_545 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[4] origin:064-gtp-channel-conf 00_546 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[5] origin:064-gtp-channel-conf 01_546 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[6] origin:064-gtp-channel-conf 00_547 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[7] origin:064-gtp-channel-conf 01_547 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[8] origin:064-gtp-channel-conf 00_548 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[9] origin:064-gtp-channel-conf 01_548 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[0] origin:064-gtp-channel-conf 00_552 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[1] origin:064-gtp-channel-conf 01_552 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[2] origin:064-gtp-channel-conf 00_553 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[3] origin:064-gtp-channel-conf 01_553 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[4] origin:064-gtp-channel-conf 00_554 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[5] origin:064-gtp-channel-conf 01_554 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[6] origin:064-gtp-channel-conf 00_555 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[7] origin:064-gtp-channel-conf 01_555 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[8] origin:064-gtp-channel-conf 00_556 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[9] origin:064-gtp-channel-conf 01_556 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[0] origin:064-gtp-channel-conf 00_560 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[1] origin:064-gtp-channel-conf 01_560 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[2] origin:064-gtp-channel-conf 00_561 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[3] origin:064-gtp-channel-conf 01_561 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[4] origin:064-gtp-channel-conf 00_562 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[5] origin:064-gtp-channel-conf 01_562 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[6] origin:064-gtp-channel-conf 00_563 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[7] origin:064-gtp-channel-conf 01_563 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[8] origin:064-gtp-channel-conf 00_564 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[9] origin:064-gtp-channel-conf 01_564 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[0] origin:064-gtp-channel-conf 00_568 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[1] origin:064-gtp-channel-conf 01_568 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[2] origin:064-gtp-channel-conf 00_569 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[3] origin:064-gtp-channel-conf 01_569 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[4] origin:064-gtp-channel-conf 00_570 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[5] origin:064-gtp-channel-conf 01_570 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[6] origin:064-gtp-channel-conf 00_571 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[7] origin:064-gtp-channel-conf 01_571 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[8] origin:064-gtp-channel-conf 00_572 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[9] origin:064-gtp-channel-conf 01_572 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_ENABLE[0] origin:064-gtp-channel-conf 00_549 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_ENABLE[1] origin:064-gtp-channel-conf 01_549 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_ENABLE[2] origin:064-gtp-channel-conf 00_550 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_ENABLE[3] origin:064-gtp-channel-conf 01_550 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[0] origin:064-gtp-channel-conf 00_576 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[1] origin:064-gtp-channel-conf 01_576 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[2] origin:064-gtp-channel-conf 00_577 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[3] origin:064-gtp-channel-conf 01_577 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[4] origin:064-gtp-channel-conf 00_578 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[5] origin:064-gtp-channel-conf 01_578 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[6] origin:064-gtp-channel-conf 00_579 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[7] origin:064-gtp-channel-conf 01_579 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[8] origin:064-gtp-channel-conf 00_580 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[9] origin:064-gtp-channel-conf 01_580 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[0] origin:064-gtp-channel-conf 00_584 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[1] origin:064-gtp-channel-conf 01_584 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[2] origin:064-gtp-channel-conf 00_585 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[3] origin:064-gtp-channel-conf 01_585 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[4] origin:064-gtp-channel-conf 00_586 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[5] origin:064-gtp-channel-conf 01_586 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[6] origin:064-gtp-channel-conf 00_587 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[7] origin:064-gtp-channel-conf 01_587 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[8] origin:064-gtp-channel-conf 00_588 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[9] origin:064-gtp-channel-conf 01_588 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[0] origin:064-gtp-channel-conf 00_592 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[1] origin:064-gtp-channel-conf 01_592 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[2] origin:064-gtp-channel-conf 00_593 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[3] origin:064-gtp-channel-conf 01_593 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[4] origin:064-gtp-channel-conf 00_594 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[5] origin:064-gtp-channel-conf 01_594 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[6] origin:064-gtp-channel-conf 00_595 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[7] origin:064-gtp-channel-conf 01_595 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[8] origin:064-gtp-channel-conf 00_596 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[9] origin:064-gtp-channel-conf 01_596 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[0] origin:064-gtp-channel-conf 00_600 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[1] origin:064-gtp-channel-conf 01_600 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[2] origin:064-gtp-channel-conf 00_601 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[3] origin:064-gtp-channel-conf 01_601 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[4] origin:064-gtp-channel-conf 00_602 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[5] origin:064-gtp-channel-conf 01_602 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[6] origin:064-gtp-channel-conf 00_603 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[7] origin:064-gtp-channel-conf 01_603 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[8] origin:064-gtp-channel-conf 00_604 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[9] origin:064-gtp-channel-conf 01_604 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_ENABLE[0] origin:064-gtp-channel-conf 00_581 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_ENABLE[1] origin:064-gtp-channel-conf 01_581 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_ENABLE[2] origin:064-gtp-channel-conf 00_582 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_ENABLE[3] origin:064-gtp-channel-conf 01_582 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_USE origin:064-gtp-channel-conf 00_583 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_LEN[0] origin:064-gtp-channel-conf 00_589 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_LEN[1] origin:064-gtp-channel-conf 01_589 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.CLK_CORRECT_USE origin:064-gtp-channel-conf 00_551 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.DEC_MCOMMA_DETECT origin:064-gtp-channel-conf 01_494 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.DEC_PCOMMA_DETECT origin:064-gtp-channel-conf 00_495 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.DEC_VALID_COMMA_ONLY origin:064-gtp-channel-conf 00_494 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[0] origin:064-gtp-channel-conf 02_368 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[1] origin:064-gtp-channel-conf 03_368 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[2] origin:064-gtp-channel-conf 02_369 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[3] origin:064-gtp-channel-conf 03_369 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[4] origin:064-gtp-channel-conf 02_370 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[5] origin:064-gtp-channel-conf 03_370 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[6] origin:064-gtp-channel-conf 02_371 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[7] origin:064-gtp-channel-conf 03_371 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[8] origin:064-gtp-channel-conf 02_372 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[9] origin:064-gtp-channel-conf 03_372 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[10] origin:064-gtp-channel-conf 02_373 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[11] origin:064-gtp-channel-conf 03_373 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[12] origin:064-gtp-channel-conf 02_374 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[13] origin:064-gtp-channel-conf 03_374 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[14] origin:064-gtp-channel-conf 02_375 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[15] origin:064-gtp-channel-conf 03_375 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[16] origin:064-gtp-channel-conf 02_376 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[17] origin:064-gtp-channel-conf 03_376 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[18] origin:064-gtp-channel-conf 02_377 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[19] origin:064-gtp-channel-conf 03_377 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[20] origin:064-gtp-channel-conf 02_378 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[21] origin:064-gtp-channel-conf 03_378 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[22] origin:064-gtp-channel-conf 02_379 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[23] origin:064-gtp-channel-conf 03_379 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_CLK_PHASE_SEL[0] origin:064-gtp-channel-conf 03_463 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_CONTROL[0] origin:064-gtp-channel-conf 00_488 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_CONTROL[1] origin:064-gtp-channel-conf 01_488 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_CONTROL[2] origin:064-gtp-channel-conf 00_489 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_CONTROL[3] origin:064-gtp-channel-conf 01_489 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_CONTROL[4] origin:064-gtp-channel-conf 00_490 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_CONTROL[5] origin:064-gtp-channel-conf 01_490 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_ERRDET_EN origin:064-gtp-channel-conf 01_492 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_EYE_SCAN_EN origin:064-gtp-channel-conf 00_492 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_HORZ_OFFSET[0] origin:064-gtp-channel-conf 00_480 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_HORZ_OFFSET[1] origin:064-gtp-channel-conf 01_480 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_HORZ_OFFSET[2] origin:064-gtp-channel-conf 00_481 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_HORZ_OFFSET[3] origin:064-gtp-channel-conf 01_481 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_HORZ_OFFSET[4] origin:064-gtp-channel-conf 00_482 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_HORZ_OFFSET[5] origin:064-gtp-channel-conf 01_482 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_HORZ_OFFSET[6] origin:064-gtp-channel-conf 00_483 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_HORZ_OFFSET[7] origin:064-gtp-channel-conf 01_483 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_HORZ_OFFSET[8] origin:064-gtp-channel-conf 00_484 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_HORZ_OFFSET[9] origin:064-gtp-channel-conf 01_484 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_HORZ_OFFSET[10] origin:064-gtp-channel-conf 00_485 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_HORZ_OFFSET[11] origin:064-gtp-channel-conf 01_485 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_PMA_CFG[0] origin:064-gtp-channel-conf 02_624 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_PMA_CFG[1] origin:064-gtp-channel-conf 03_624 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_PMA_CFG[2] origin:064-gtp-channel-conf 02_625 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_PMA_CFG[3] origin:064-gtp-channel-conf 03_625 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_PMA_CFG[4] origin:064-gtp-channel-conf 02_626 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_PMA_CFG[5] origin:064-gtp-channel-conf 03_626 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_PMA_CFG[6] origin:064-gtp-channel-conf 02_627 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_PMA_CFG[7] origin:064-gtp-channel-conf 03_627 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_PMA_CFG[8] origin:064-gtp-channel-conf 02_628 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_PMA_CFG[9] origin:064-gtp-channel-conf 03_628 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_PRESCALE[0] origin:064-gtp-channel-conf 01_477 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_PRESCALE[1] origin:064-gtp-channel-conf 00_478 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_PRESCALE[2] origin:064-gtp-channel-conf 01_478 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_PRESCALE[3] origin:064-gtp-channel-conf 00_479 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_PRESCALE[4] origin:064-gtp-channel-conf 01_479 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[0] origin:064-gtp-channel-conf 00_392 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[1] origin:064-gtp-channel-conf 01_392 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[2] origin:064-gtp-channel-conf 00_393 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[3] origin:064-gtp-channel-conf 01_393 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[4] origin:064-gtp-channel-conf 00_394 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[5] origin:064-gtp-channel-conf 01_394 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[6] origin:064-gtp-channel-conf 00_395 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[7] origin:064-gtp-channel-conf 01_395 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[8] origin:064-gtp-channel-conf 00_396 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[9] origin:064-gtp-channel-conf 01_396 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[10] origin:064-gtp-channel-conf 00_397 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[11] origin:064-gtp-channel-conf 01_397 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[12] origin:064-gtp-channel-conf 00_398 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[13] origin:064-gtp-channel-conf 01_398 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[14] origin:064-gtp-channel-conf 00_399 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[15] origin:064-gtp-channel-conf 01_399 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[16] origin:064-gtp-channel-conf 00_400 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[17] origin:064-gtp-channel-conf 01_400 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[18] origin:064-gtp-channel-conf 00_401 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[19] origin:064-gtp-channel-conf 01_401 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[20] origin:064-gtp-channel-conf 00_402 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[21] origin:064-gtp-channel-conf 01_402 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[22] origin:064-gtp-channel-conf 00_403 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[23] origin:064-gtp-channel-conf 01_403 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[24] origin:064-gtp-channel-conf 00_404 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[25] origin:064-gtp-channel-conf 01_404 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[26] origin:064-gtp-channel-conf 00_405 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[27] origin:064-gtp-channel-conf 01_405 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[28] origin:064-gtp-channel-conf 00_406 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[29] origin:064-gtp-channel-conf 01_406 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[30] origin:064-gtp-channel-conf 00_407 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[31] origin:064-gtp-channel-conf 01_407 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[32] origin:064-gtp-channel-conf 00_408 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[33] origin:064-gtp-channel-conf 01_408 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[34] origin:064-gtp-channel-conf 00_409 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[35] origin:064-gtp-channel-conf 01_409 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[36] origin:064-gtp-channel-conf 00_410 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[37] origin:064-gtp-channel-conf 01_410 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[38] origin:064-gtp-channel-conf 00_411 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[39] origin:064-gtp-channel-conf 01_411 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[40] origin:064-gtp-channel-conf 00_412 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[41] origin:064-gtp-channel-conf 01_412 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[42] origin:064-gtp-channel-conf 00_413 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[43] origin:064-gtp-channel-conf 01_413 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[44] origin:064-gtp-channel-conf 00_414 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[45] origin:064-gtp-channel-conf 01_414 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[46] origin:064-gtp-channel-conf 00_415 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[47] origin:064-gtp-channel-conf 01_415 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[48] origin:064-gtp-channel-conf 00_416 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[49] origin:064-gtp-channel-conf 01_416 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[50] origin:064-gtp-channel-conf 00_417 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[51] origin:064-gtp-channel-conf 01_417 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[52] origin:064-gtp-channel-conf 00_418 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[53] origin:064-gtp-channel-conf 01_418 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[54] origin:064-gtp-channel-conf 00_419 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[55] origin:064-gtp-channel-conf 01_419 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[56] origin:064-gtp-channel-conf 00_420 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[57] origin:064-gtp-channel-conf 01_420 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[58] origin:064-gtp-channel-conf 00_421 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[59] origin:064-gtp-channel-conf 01_421 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[60] origin:064-gtp-channel-conf 00_422 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[61] origin:064-gtp-channel-conf 01_422 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[62] origin:064-gtp-channel-conf 00_423 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[63] origin:064-gtp-channel-conf 01_423 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[64] origin:064-gtp-channel-conf 00_424 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[65] origin:064-gtp-channel-conf 01_424 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[66] origin:064-gtp-channel-conf 00_425 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[67] origin:064-gtp-channel-conf 01_425 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[68] origin:064-gtp-channel-conf 00_426 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[69] origin:064-gtp-channel-conf 01_426 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[70] origin:064-gtp-channel-conf 00_427 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[71] origin:064-gtp-channel-conf 01_427 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[72] origin:064-gtp-channel-conf 00_428 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[73] origin:064-gtp-channel-conf 01_428 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[74] origin:064-gtp-channel-conf 00_429 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[75] origin:064-gtp-channel-conf 01_429 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[76] origin:064-gtp-channel-conf 00_430 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[77] origin:064-gtp-channel-conf 01_430 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[78] origin:064-gtp-channel-conf 00_431 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[79] origin:064-gtp-channel-conf 01_431 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[0] origin:064-gtp-channel-conf 00_352 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[1] origin:064-gtp-channel-conf 01_352 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[2] origin:064-gtp-channel-conf 00_353 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[3] origin:064-gtp-channel-conf 01_353 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[4] origin:064-gtp-channel-conf 00_354 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[5] origin:064-gtp-channel-conf 01_354 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[6] origin:064-gtp-channel-conf 00_355 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[7] origin:064-gtp-channel-conf 01_355 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[8] origin:064-gtp-channel-conf 00_356 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[9] origin:064-gtp-channel-conf 01_356 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[10] origin:064-gtp-channel-conf 00_357 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[11] origin:064-gtp-channel-conf 01_357 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[12] origin:064-gtp-channel-conf 00_358 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[13] origin:064-gtp-channel-conf 01_358 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[14] origin:064-gtp-channel-conf 00_359 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[15] origin:064-gtp-channel-conf 01_359 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[16] origin:064-gtp-channel-conf 00_360 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[17] origin:064-gtp-channel-conf 01_360 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[18] origin:064-gtp-channel-conf 00_361 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[19] origin:064-gtp-channel-conf 01_361 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[20] origin:064-gtp-channel-conf 00_362 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[21] origin:064-gtp-channel-conf 01_362 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[22] origin:064-gtp-channel-conf 00_363 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[23] origin:064-gtp-channel-conf 01_363 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[24] origin:064-gtp-channel-conf 00_364 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[25] origin:064-gtp-channel-conf 01_364 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[26] origin:064-gtp-channel-conf 00_365 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[27] origin:064-gtp-channel-conf 01_365 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[28] origin:064-gtp-channel-conf 00_366 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[29] origin:064-gtp-channel-conf 01_366 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[30] origin:064-gtp-channel-conf 00_367 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[31] origin:064-gtp-channel-conf 01_367 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[32] origin:064-gtp-channel-conf 00_368 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[33] origin:064-gtp-channel-conf 01_368 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[34] origin:064-gtp-channel-conf 00_369 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[35] origin:064-gtp-channel-conf 01_369 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[36] origin:064-gtp-channel-conf 00_370 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[37] origin:064-gtp-channel-conf 01_370 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[38] origin:064-gtp-channel-conf 00_371 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[39] origin:064-gtp-channel-conf 01_371 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[40] origin:064-gtp-channel-conf 00_372 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[41] origin:064-gtp-channel-conf 01_372 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[42] origin:064-gtp-channel-conf 00_373 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[43] origin:064-gtp-channel-conf 01_373 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[44] origin:064-gtp-channel-conf 00_374 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[45] origin:064-gtp-channel-conf 01_374 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[46] origin:064-gtp-channel-conf 00_375 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[47] origin:064-gtp-channel-conf 01_375 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[48] origin:064-gtp-channel-conf 00_376 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[49] origin:064-gtp-channel-conf 01_376 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[50] origin:064-gtp-channel-conf 00_377 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[51] origin:064-gtp-channel-conf 01_377 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[52] origin:064-gtp-channel-conf 00_378 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[53] origin:064-gtp-channel-conf 01_378 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[54] origin:064-gtp-channel-conf 00_379 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[55] origin:064-gtp-channel-conf 01_379 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[56] origin:064-gtp-channel-conf 00_380 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[57] origin:064-gtp-channel-conf 01_380 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[58] origin:064-gtp-channel-conf 00_381 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[59] origin:064-gtp-channel-conf 01_381 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[60] origin:064-gtp-channel-conf 00_382 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[61] origin:064-gtp-channel-conf 01_382 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[62] origin:064-gtp-channel-conf 00_383 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[63] origin:064-gtp-channel-conf 01_383 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[64] origin:064-gtp-channel-conf 00_384 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[65] origin:064-gtp-channel-conf 01_384 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[66] origin:064-gtp-channel-conf 00_385 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[67] origin:064-gtp-channel-conf 01_385 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[68] origin:064-gtp-channel-conf 00_386 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[69] origin:064-gtp-channel-conf 01_386 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[70] origin:064-gtp-channel-conf 00_387 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[71] origin:064-gtp-channel-conf 01_387 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[72] origin:064-gtp-channel-conf 00_388 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[73] origin:064-gtp-channel-conf 01_388 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[74] origin:064-gtp-channel-conf 00_389 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[75] origin:064-gtp-channel-conf 01_389 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[76] origin:064-gtp-channel-conf 00_390 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[77] origin:064-gtp-channel-conf 01_390 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[78] origin:064-gtp-channel-conf 00_391 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[79] origin:064-gtp-channel-conf 01_391 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[0] origin:064-gtp-channel-conf 00_432 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[1] origin:064-gtp-channel-conf 01_432 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[2] origin:064-gtp-channel-conf 00_433 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[3] origin:064-gtp-channel-conf 01_433 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[4] origin:064-gtp-channel-conf 00_434 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[5] origin:064-gtp-channel-conf 01_434 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[6] origin:064-gtp-channel-conf 00_435 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[7] origin:064-gtp-channel-conf 01_435 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[8] origin:064-gtp-channel-conf 00_436 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[9] origin:064-gtp-channel-conf 01_436 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[10] origin:064-gtp-channel-conf 00_437 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[11] origin:064-gtp-channel-conf 01_437 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[12] origin:064-gtp-channel-conf 00_438 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[13] origin:064-gtp-channel-conf 01_438 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[14] origin:064-gtp-channel-conf 00_439 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[15] origin:064-gtp-channel-conf 01_439 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[16] origin:064-gtp-channel-conf 00_440 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[17] origin:064-gtp-channel-conf 01_440 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[18] origin:064-gtp-channel-conf 00_441 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[19] origin:064-gtp-channel-conf 01_441 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[20] origin:064-gtp-channel-conf 00_442 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[21] origin:064-gtp-channel-conf 01_442 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[22] origin:064-gtp-channel-conf 00_443 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[23] origin:064-gtp-channel-conf 01_443 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[24] origin:064-gtp-channel-conf 00_444 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[25] origin:064-gtp-channel-conf 01_444 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[26] origin:064-gtp-channel-conf 00_445 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[27] origin:064-gtp-channel-conf 01_445 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[28] origin:064-gtp-channel-conf 00_446 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[29] origin:064-gtp-channel-conf 01_446 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[30] origin:064-gtp-channel-conf 00_447 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[31] origin:064-gtp-channel-conf 01_447 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[32] origin:064-gtp-channel-conf 00_448 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[33] origin:064-gtp-channel-conf 01_448 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[34] origin:064-gtp-channel-conf 00_449 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[35] origin:064-gtp-channel-conf 01_449 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[36] origin:064-gtp-channel-conf 00_450 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[37] origin:064-gtp-channel-conf 01_450 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[38] origin:064-gtp-channel-conf 00_451 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[39] origin:064-gtp-channel-conf 01_451 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[40] origin:064-gtp-channel-conf 00_452 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[41] origin:064-gtp-channel-conf 01_452 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[42] origin:064-gtp-channel-conf 00_453 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[43] origin:064-gtp-channel-conf 01_453 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[44] origin:064-gtp-channel-conf 00_454 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[45] origin:064-gtp-channel-conf 01_454 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[46] origin:064-gtp-channel-conf 00_455 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[47] origin:064-gtp-channel-conf 01_455 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[48] origin:064-gtp-channel-conf 00_456 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[49] origin:064-gtp-channel-conf 01_456 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[50] origin:064-gtp-channel-conf 00_457 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[51] origin:064-gtp-channel-conf 01_457 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[52] origin:064-gtp-channel-conf 00_458 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[53] origin:064-gtp-channel-conf 01_458 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[54] origin:064-gtp-channel-conf 00_459 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[55] origin:064-gtp-channel-conf 01_459 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[56] origin:064-gtp-channel-conf 00_460 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[57] origin:064-gtp-channel-conf 01_460 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[58] origin:064-gtp-channel-conf 00_461 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[59] origin:064-gtp-channel-conf 01_461 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[60] origin:064-gtp-channel-conf 00_462 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[61] origin:064-gtp-channel-conf 01_462 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[62] origin:064-gtp-channel-conf 00_463 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[63] origin:064-gtp-channel-conf 01_463 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[64] origin:064-gtp-channel-conf 00_464 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[65] origin:064-gtp-channel-conf 01_464 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[66] origin:064-gtp-channel-conf 00_465 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[67] origin:064-gtp-channel-conf 01_465 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[68] origin:064-gtp-channel-conf 00_466 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[69] origin:064-gtp-channel-conf 01_466 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[70] origin:064-gtp-channel-conf 00_467 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[71] origin:064-gtp-channel-conf 01_467 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[72] origin:064-gtp-channel-conf 00_468 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[73] origin:064-gtp-channel-conf 01_468 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[74] origin:064-gtp-channel-conf 00_469 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[75] origin:064-gtp-channel-conf 01_469 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[76] origin:064-gtp-channel-conf 00_470 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[77] origin:064-gtp-channel-conf 01_470 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[78] origin:064-gtp-channel-conf 00_471 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[79] origin:064-gtp-channel-conf 01_471 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_VERT_OFFSET[0] origin:064-gtp-channel-conf 00_472 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_VERT_OFFSET[1] origin:064-gtp-channel-conf 01_472 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_VERT_OFFSET[2] origin:064-gtp-channel-conf 00_473 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_VERT_OFFSET[3] origin:064-gtp-channel-conf 01_473 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_VERT_OFFSET[4] origin:064-gtp-channel-conf 00_474 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_VERT_OFFSET[5] origin:064-gtp-channel-conf 01_474 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_VERT_OFFSET[6] origin:064-gtp-channel-conf 00_475 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_VERT_OFFSET[7] origin:064-gtp-channel-conf 01_475 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.ES_VERT_OFFSET[8] origin:064-gtp-channel-conf 00_476 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.FTS_DESKEW_SEQ_ENABLE[0] origin:064-gtp-channel-conf 00_662 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.FTS_DESKEW_SEQ_ENABLE[1] origin:064-gtp-channel-conf 01_662 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.FTS_DESKEW_SEQ_ENABLE[2] origin:064-gtp-channel-conf 00_663 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.FTS_DESKEW_SEQ_ENABLE[3] origin:064-gtp-channel-conf 01_663 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.FTS_LANE_DESKEW_CFG[0] origin:064-gtp-channel-conf 00_654 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.FTS_LANE_DESKEW_CFG[1] origin:064-gtp-channel-conf 01_654 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.FTS_LANE_DESKEW_CFG[2] origin:064-gtp-channel-conf 00_655 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.FTS_LANE_DESKEW_CFG[3] origin:064-gtp-channel-conf 01_655 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.FTS_LANE_DESKEW_EN origin:064-gtp-channel-conf 01_653 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.GEARBOX_MODE[0] origin:064-gtp-channel-conf 00_224 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.GEARBOX_MODE[1] origin:064-gtp-channel-conf 01_224 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.GEARBOX_MODE[2] origin:064-gtp-channel-conf 00_225 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.IN_USE origin:064-gtp-channel-conf 00_00 00_01 00_47 00_52 00_53 00_65 01_01 01_47 02_129 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.INV_DMONITORCLK origin:064-gtp-channel-conf 02_13 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.INV_DRPCLK origin:064-gtp-channel-conf 02_00 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.INV_RXUSRCLK origin:064-gtp-channel-conf 03_01 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.INV_SIGVALIDCLK origin:064-gtp-channel-conf 03_13 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.INV_TXPHDLYTSTCLK origin:064-gtp-channel-conf 02_03 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.INV_TXUSRCLK origin:064-gtp-channel-conf 03_04 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.INV_CLKRSVD0 origin:064-gtp-channel-conf 02_23 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.INV_CLKRSVD1 origin:064-gtp-channel-conf 03_23 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.INV_RXUSRCLK2 origin:064-gtp-channel-conf 02_02 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.INV_TXUSRCLK2 origin:064-gtp-channel-conf 02_05 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.LOOPBACK_CFG[0] origin:064-gtp-channel-conf 02_20 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.OUTREFCLK_SEL_INV[0] origin:064-gtp-channel-conf 00_149 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.OUTREFCLK_SEL_INV[1] origin:064-gtp-channel-conf 01_149 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PCS_PCIE_EN origin:064-gtp-channel-conf 00_216 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[0] origin:064-gtp-channel-conf 02_184 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[1] origin:064-gtp-channel-conf 03_184 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[2] origin:064-gtp-channel-conf 02_185 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[3] origin:064-gtp-channel-conf 03_185 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[4] origin:064-gtp-channel-conf 02_186 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[5] origin:064-gtp-channel-conf 03_186 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[6] origin:064-gtp-channel-conf 02_187 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[7] origin:064-gtp-channel-conf 03_187 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[8] origin:064-gtp-channel-conf 02_188 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[9] origin:064-gtp-channel-conf 03_188 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[10] origin:064-gtp-channel-conf 02_189 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[11] origin:064-gtp-channel-conf 03_189 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[12] origin:064-gtp-channel-conf 02_190 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[13] origin:064-gtp-channel-conf 03_190 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[14] origin:064-gtp-channel-conf 02_191 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[15] origin:064-gtp-channel-conf 03_191 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[16] origin:064-gtp-channel-conf 02_192 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[17] origin:064-gtp-channel-conf 03_192 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[18] origin:064-gtp-channel-conf 02_193 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[19] origin:064-gtp-channel-conf 03_193 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[20] origin:064-gtp-channel-conf 02_194 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[21] origin:064-gtp-channel-conf 03_194 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[22] origin:064-gtp-channel-conf 02_195 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[23] origin:064-gtp-channel-conf 03_195 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[24] origin:064-gtp-channel-conf 02_196 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[25] origin:064-gtp-channel-conf 03_196 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[26] origin:064-gtp-channel-conf 02_197 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[27] origin:064-gtp-channel-conf 03_197 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[28] origin:064-gtp-channel-conf 02_198 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[29] origin:064-gtp-channel-conf 03_198 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[30] origin:064-gtp-channel-conf 02_199 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[31] origin:064-gtp-channel-conf 03_199 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[32] origin:064-gtp-channel-conf 02_200 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[33] origin:064-gtp-channel-conf 03_200 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[34] origin:064-gtp-channel-conf 02_201 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[35] origin:064-gtp-channel-conf 03_201 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[36] origin:064-gtp-channel-conf 02_202 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[37] origin:064-gtp-channel-conf 03_202 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[38] origin:064-gtp-channel-conf 02_203 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[39] origin:064-gtp-channel-conf 03_203 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[40] origin:064-gtp-channel-conf 02_204 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[41] origin:064-gtp-channel-conf 03_204 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[42] origin:064-gtp-channel-conf 02_205 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[43] origin:064-gtp-channel-conf 03_205 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[44] origin:064-gtp-channel-conf 02_206 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[45] origin:064-gtp-channel-conf 03_206 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[46] origin:064-gtp-channel-conf 02_207 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[47] origin:064-gtp-channel-conf 03_207 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[0] origin:064-gtp-channel-conf 01_216 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[1] origin:064-gtp-channel-conf 00_217 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[2] origin:064-gtp-channel-conf 01_217 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[3] origin:064-gtp-channel-conf 00_218 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[4] origin:064-gtp-channel-conf 01_218 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[5] origin:064-gtp-channel-conf 00_219 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[6] origin:064-gtp-channel-conf 01_219 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[7] origin:064-gtp-channel-conf 00_220 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[8] origin:064-gtp-channel-conf 01_220 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[9] origin:064-gtp-channel-conf 00_221 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[10] origin:064-gtp-channel-conf 01_221 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[11] origin:064-gtp-channel-conf 00_222 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[0] origin:064-gtp-channel-conf 00_208 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[1] origin:064-gtp-channel-conf 01_208 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[2] origin:064-gtp-channel-conf 00_209 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[3] origin:064-gtp-channel-conf 01_209 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[4] origin:064-gtp-channel-conf 00_210 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[5] origin:064-gtp-channel-conf 01_210 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[6] origin:064-gtp-channel-conf 00_211 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[7] origin:064-gtp-channel-conf 01_211 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[0] origin:064-gtp-channel-conf 00_212 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[1] origin:064-gtp-channel-conf 01_212 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[2] origin:064-gtp-channel-conf 00_213 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[3] origin:064-gtp-channel-conf 01_213 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[4] origin:064-gtp-channel-conf 00_214 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[5] origin:064-gtp-channel-conf 01_214 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[6] origin:064-gtp-channel-conf 00_215 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[7] origin:064-gtp-channel-conf 01_215 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PMA_LOOPBACK_CFG[0] origin:064-gtp-channel-conf 01_207 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[0] origin:064-gtp-channel-conf 02_520 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[1] origin:064-gtp-channel-conf 03_520 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[2] origin:064-gtp-channel-conf 02_521 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[3] origin:064-gtp-channel-conf 03_521 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[4] origin:064-gtp-channel-conf 02_522 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[5] origin:064-gtp-channel-conf 03_522 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[6] origin:064-gtp-channel-conf 02_523 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[7] origin:064-gtp-channel-conf 03_523 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[8] origin:064-gtp-channel-conf 02_524 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[9] origin:064-gtp-channel-conf 03_524 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[10] origin:064-gtp-channel-conf 02_525 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[11] origin:064-gtp-channel-conf 03_525 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[12] origin:064-gtp-channel-conf 02_526 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[13] origin:064-gtp-channel-conf 03_526 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[14] origin:064-gtp-channel-conf 02_527 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[15] origin:064-gtp-channel-conf 03_527 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[16] origin:064-gtp-channel-conf 02_528 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[17] origin:064-gtp-channel-conf 03_528 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[18] origin:064-gtp-channel-conf 02_529 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[19] origin:064-gtp-channel-conf 03_529 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[20] origin:064-gtp-channel-conf 02_530 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[21] origin:064-gtp-channel-conf 03_530 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[22] origin:064-gtp-channel-conf 02_531 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[23] origin:064-gtp-channel-conf 03_531 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[24] origin:064-gtp-channel-conf 02_532 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[25] origin:064-gtp-channel-conf 03_532 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[26] origin:064-gtp-channel-conf 02_533 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[27] origin:064-gtp-channel-conf 03_533 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[28] origin:064-gtp-channel-conf 02_534 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[29] origin:064-gtp-channel-conf 03_534 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[30] origin:064-gtp-channel-conf 02_535 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[31] origin:064-gtp-channel-conf 03_535 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[0] origin:064-gtp-channel-conf 02_336 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[1] origin:064-gtp-channel-conf 03_336 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[2] origin:064-gtp-channel-conf 02_337 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[3] origin:064-gtp-channel-conf 03_337 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[4] origin:064-gtp-channel-conf 02_338 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[5] origin:064-gtp-channel-conf 03_338 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[6] origin:064-gtp-channel-conf 02_339 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[7] origin:064-gtp-channel-conf 03_339 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[8] origin:064-gtp-channel-conf 02_340 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[9] origin:064-gtp-channel-conf 03_340 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[10] origin:064-gtp-channel-conf 02_341 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[11] origin:064-gtp-channel-conf 03_341 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[12] origin:064-gtp-channel-conf 02_342 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[13] origin:064-gtp-channel-conf 03_342 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[14] origin:064-gtp-channel-conf 02_343 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[15] origin:064-gtp-channel-conf 03_343 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[16] origin:064-gtp-channel-conf 02_344 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[17] origin:064-gtp-channel-conf 03_344 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[18] origin:064-gtp-channel-conf 02_345 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[19] origin:064-gtp-channel-conf 03_345 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[20] origin:064-gtp-channel-conf 02_346 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[21] origin:064-gtp-channel-conf 03_346 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[22] origin:064-gtp-channel-conf 02_347 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[23] origin:064-gtp-channel-conf 03_347 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[24] origin:064-gtp-channel-conf 02_348 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[25] origin:064-gtp-channel-conf 03_348 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[26] origin:064-gtp-channel-conf 02_349 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[27] origin:064-gtp-channel-conf 03_349 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[28] origin:064-gtp-channel-conf 02_350 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[29] origin:064-gtp-channel-conf 03_350 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[30] origin:064-gtp-channel-conf 02_351 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[31] origin:064-gtp-channel-conf 03_351 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV3[0] origin:064-gtp-channel-conf 02_288 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV3[1] origin:064-gtp-channel-conf 03_288 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV4[0] origin:064-gtp-channel-conf 02_156 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV4[1] origin:064-gtp-channel-conf 03_156 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV4[2] origin:064-gtp-channel-conf 02_157 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV4[3] origin:064-gtp-channel-conf 03_157 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV5[0] origin:064-gtp-channel-conf 03_159 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV6[0] origin:064-gtp-channel-conf 02_303 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV7[0] origin:064-gtp-channel-conf 03_303 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_BIAS_CFG[0] origin:064-gtp-channel-conf 02_112 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_BIAS_CFG[1] origin:064-gtp-channel-conf 03_112 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_BIAS_CFG[2] origin:064-gtp-channel-conf 02_113 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_BIAS_CFG[3] origin:064-gtp-channel-conf 03_113 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_BIAS_CFG[4] origin:064-gtp-channel-conf 02_114 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_BIAS_CFG[5] origin:064-gtp-channel-conf 03_114 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_BIAS_CFG[6] origin:064-gtp-channel-conf 02_115 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_BIAS_CFG[7] origin:064-gtp-channel-conf 03_115 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_BIAS_CFG[8] origin:064-gtp-channel-conf 02_116 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_BIAS_CFG[9] origin:064-gtp-channel-conf 03_116 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_BIAS_CFG[10] origin:064-gtp-channel-conf 02_117 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_BIAS_CFG[11] origin:064-gtp-channel-conf 03_117 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_BIAS_CFG[12] origin:064-gtp-channel-conf 02_118 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_BIAS_CFG[13] origin:064-gtp-channel-conf 03_118 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_BIAS_CFG[14] origin:064-gtp-channel-conf 02_119 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_BIAS_CFG[15] origin:064-gtp-channel-conf 03_119 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_BUFFER_CFG[0] origin:064-gtp-channel-conf 02_536 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_BUFFER_CFG[1] origin:064-gtp-channel-conf 03_536 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_BUFFER_CFG[2] origin:064-gtp-channel-conf 02_537 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_BUFFER_CFG[3] origin:064-gtp-channel-conf 03_537 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_BUFFER_CFG[4] origin:064-gtp-channel-conf 02_538 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_BUFFER_CFG[5] origin:064-gtp-channel-conf 03_538 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_CLKMUX_EN[0] origin:064-gtp-channel-conf 02_128 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_CM_SEL[0] origin:064-gtp-channel-conf 00_138 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_CM_SEL[1] origin:064-gtp-channel-conf 01_138 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_CM_TRIM[0] origin:064-gtp-channel-conf 02_304 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_CM_TRIM[1] origin:064-gtp-channel-conf 03_304 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_CM_TRIM[2] origin:064-gtp-channel-conf 02_305 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_CM_TRIM[3] origin:064-gtp-channel-conf 03_305 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_DATA_WIDTH[0] origin:064-gtp-channel-conf 01_141 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_DATA_WIDTH[1] origin:064-gtp-channel-conf 00_142 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_DATA_WIDTH[2] origin:064-gtp-channel-conf 01_142 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_DDI_SEL[0] origin:064-gtp-channel-conf 00_696 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_DDI_SEL[1] origin:064-gtp-channel-conf 01_696 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_DDI_SEL[2] origin:064-gtp-channel-conf 00_697 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_DDI_SEL[3] origin:064-gtp-channel-conf 01_697 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_DDI_SEL[4] origin:064-gtp-channel-conf 00_698 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_DDI_SEL[5] origin:064-gtp-channel-conf 01_698 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_DEBUG_CFG[0] origin:064-gtp-channel-conf 02_616 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_DEBUG_CFG[1] origin:064-gtp-channel-conf 03_616 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_DEBUG_CFG[2] origin:064-gtp-channel-conf 02_617 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_DEBUG_CFG[3] origin:064-gtp-channel-conf 03_617 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_DEBUG_CFG[4] origin:064-gtp-channel-conf 02_618 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_DEBUG_CFG[5] origin:064-gtp-channel-conf 03_618 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_DEBUG_CFG[6] origin:064-gtp-channel-conf 02_619 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_DEBUG_CFG[7] origin:064-gtp-channel-conf 03_619 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_DEBUG_CFG[8] origin:064-gtp-channel-conf 02_620 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_DEBUG_CFG[9] origin:064-gtp-channel-conf 03_620 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_DEBUG_CFG[10] origin:064-gtp-channel-conf 02_621 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_DEBUG_CFG[11] origin:064-gtp-channel-conf 03_621 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_DEBUG_CFG[12] origin:064-gtp-channel-conf 02_622 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_DEBUG_CFG[13] origin:064-gtp-channel-conf 03_622 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_DEFER_RESET_BUF_EN origin:064-gtp-channel-conf 02_552 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_DISPERR_SEQ_MATCH origin:064-gtp-channel-conf 01_495 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_OS_CFG[0] origin:064-gtp-channel-conf 00_288 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_OS_CFG[1] origin:064-gtp-channel-conf 01_288 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_OS_CFG[2] origin:064-gtp-channel-conf 00_289 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_OS_CFG[3] origin:064-gtp-channel-conf 01_289 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_OS_CFG[4] origin:064-gtp-channel-conf 00_290 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_OS_CFG[5] origin:064-gtp-channel-conf 01_290 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_OS_CFG[6] origin:064-gtp-channel-conf 00_291 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_OS_CFG[7] origin:064-gtp-channel-conf 01_291 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_OS_CFG[8] origin:064-gtp-channel-conf 00_292 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_OS_CFG[9] origin:064-gtp-channel-conf 01_292 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_OS_CFG[10] origin:064-gtp-channel-conf 00_293 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_OS_CFG[11] origin:064-gtp-channel-conf 01_293 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_OS_CFG[12] origin:064-gtp-channel-conf 00_294 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_SIG_VALID_DLY[0] origin:064-gtp-channel-conf 00_524 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_SIG_VALID_DLY[1] origin:064-gtp-channel-conf 01_524 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_SIG_VALID_DLY[2] origin:064-gtp-channel-conf 00_525 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_SIG_VALID_DLY[3] origin:064-gtp-channel-conf 01_525 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_SIG_VALID_DLY[4] origin:064-gtp-channel-conf 00_526 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_XCLK_SEL.RXUSR origin:064-gtp-channel-conf 00_143 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_CLK25_DIV[0] origin:064-gtp-channel-conf 00_139 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_CLK25_DIV[1] origin:064-gtp-channel-conf 01_139 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_CLK25_DIV[2] origin:064-gtp-channel-conf 00_140 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_CLK25_DIV[3] origin:064-gtp-channel-conf 01_140 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RX_CLK25_DIV[4] origin:064-gtp-channel-conf 00_141 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXBUF_ADDR_MODE.FAST origin:064-gtp-channel-conf 03_555 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXBUF_EIDLE_HI_CNT[0] origin:064-gtp-channel-conf 02_558 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXBUF_EIDLE_HI_CNT[1] origin:064-gtp-channel-conf 03_558 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXBUF_EIDLE_HI_CNT[2] origin:064-gtp-channel-conf 02_559 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXBUF_EIDLE_HI_CNT[3] origin:064-gtp-channel-conf 03_559 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXBUF_EIDLE_LO_CNT[0] origin:064-gtp-channel-conf 02_556 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXBUF_EIDLE_LO_CNT[1] origin:064-gtp-channel-conf 03_556 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXBUF_EIDLE_LO_CNT[2] origin:064-gtp-channel-conf 02_557 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXBUF_EIDLE_LO_CNT[3] origin:064-gtp-channel-conf 03_557 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXBUF_EN origin:064-gtp-channel-conf 02_11 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXBUF_RESET_ON_CB_CHANGE origin:064-gtp-channel-conf 02_560 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXBUF_RESET_ON_COMMAALIGN origin:064-gtp-channel-conf 02_561 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXBUF_RESET_ON_EIDLE origin:064-gtp-channel-conf 02_547 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXBUF_RESET_ON_RATE_CHANGE origin:064-gtp-channel-conf 03_560 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXBUF_THRESH_OVFLW[0] origin:064-gtp-channel-conf 03_552 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXBUF_THRESH_OVFLW[1] origin:064-gtp-channel-conf 02_553 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXBUF_THRESH_OVFLW[2] origin:064-gtp-channel-conf 03_553 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXBUF_THRESH_OVFLW[3] origin:064-gtp-channel-conf 02_554 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXBUF_THRESH_OVFLW[4] origin:064-gtp-channel-conf 03_554 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXBUF_THRESH_OVFLW[5] origin:064-gtp-channel-conf 02_555 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXBUF_THRESH_OVRD origin:064-gtp-channel-conf 02_548 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXBUF_THRESH_UNDFLW[0] origin:064-gtp-channel-conf 02_544 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXBUF_THRESH_UNDFLW[1] origin:064-gtp-channel-conf 03_544 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXBUF_THRESH_UNDFLW[2] origin:064-gtp-channel-conf 02_545 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXBUF_THRESH_UNDFLW[3] origin:064-gtp-channel-conf 03_545 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXBUF_THRESH_UNDFLW[4] origin:064-gtp-channel-conf 02_546 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXBUF_THRESH_UNDFLW[5] origin:064-gtp-channel-conf 03_546 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXBUFRESET_TIME[0] origin:064-gtp-channel-conf 01_101 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXBUFRESET_TIME[1] origin:064-gtp-channel-conf 00_102 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXBUFRESET_TIME[2] origin:064-gtp-channel-conf 01_102 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXBUFRESET_TIME[3] origin:064-gtp-channel-conf 00_103 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXBUFRESET_TIME[4] origin:064-gtp-channel-conf 01_103 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[0] origin:064-gtp-channel-conf 02_640 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[1] origin:064-gtp-channel-conf 03_640 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[2] origin:064-gtp-channel-conf 02_641 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[3] origin:064-gtp-channel-conf 03_641 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[4] origin:064-gtp-channel-conf 02_642 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[5] origin:064-gtp-channel-conf 03_642 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[6] origin:064-gtp-channel-conf 02_643 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[7] origin:064-gtp-channel-conf 03_643 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[8] origin:064-gtp-channel-conf 02_644 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[9] origin:064-gtp-channel-conf 03_644 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[10] origin:064-gtp-channel-conf 02_645 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[11] origin:064-gtp-channel-conf 03_645 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[12] origin:064-gtp-channel-conf 02_646 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[13] origin:064-gtp-channel-conf 03_646 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[14] origin:064-gtp-channel-conf 02_647 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[15] origin:064-gtp-channel-conf 03_647 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[16] origin:064-gtp-channel-conf 02_648 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[17] origin:064-gtp-channel-conf 03_648 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[18] origin:064-gtp-channel-conf 02_649 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[19] origin:064-gtp-channel-conf 03_649 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[20] origin:064-gtp-channel-conf 02_650 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[21] origin:064-gtp-channel-conf 03_650 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[22] origin:064-gtp-channel-conf 02_651 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[23] origin:064-gtp-channel-conf 03_651 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[24] origin:064-gtp-channel-conf 02_652 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[25] origin:064-gtp-channel-conf 03_652 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[26] origin:064-gtp-channel-conf 02_653 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[27] origin:064-gtp-channel-conf 03_653 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[28] origin:064-gtp-channel-conf 02_654 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[29] origin:064-gtp-channel-conf 03_654 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[30] origin:064-gtp-channel-conf 02_655 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[31] origin:064-gtp-channel-conf 03_655 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[32] origin:064-gtp-channel-conf 02_656 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[33] origin:064-gtp-channel-conf 03_656 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[34] origin:064-gtp-channel-conf 02_657 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[35] origin:064-gtp-channel-conf 03_657 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[36] origin:064-gtp-channel-conf 02_658 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[37] origin:064-gtp-channel-conf 03_658 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[38] origin:064-gtp-channel-conf 02_659 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[39] origin:064-gtp-channel-conf 03_659 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[40] origin:064-gtp-channel-conf 02_660 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[41] origin:064-gtp-channel-conf 03_660 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[42] origin:064-gtp-channel-conf 02_661 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[43] origin:064-gtp-channel-conf 03_661 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[44] origin:064-gtp-channel-conf 02_662 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[45] origin:064-gtp-channel-conf 03_662 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[46] origin:064-gtp-channel-conf 02_663 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[47] origin:064-gtp-channel-conf 03_663 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[48] origin:064-gtp-channel-conf 02_664 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[49] origin:064-gtp-channel-conf 03_664 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[50] origin:064-gtp-channel-conf 02_665 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[51] origin:064-gtp-channel-conf 03_665 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[52] origin:064-gtp-channel-conf 02_666 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[53] origin:064-gtp-channel-conf 03_666 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[54] origin:064-gtp-channel-conf 02_667 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[55] origin:064-gtp-channel-conf 03_667 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[56] origin:064-gtp-channel-conf 02_668 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[57] origin:064-gtp-channel-conf 03_668 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[58] origin:064-gtp-channel-conf 02_669 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[59] origin:064-gtp-channel-conf 03_669 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[60] origin:064-gtp-channel-conf 02_670 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[61] origin:064-gtp-channel-conf 03_670 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[62] origin:064-gtp-channel-conf 02_671 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[63] origin:064-gtp-channel-conf 03_671 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[64] origin:064-gtp-channel-conf 02_672 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[65] origin:064-gtp-channel-conf 03_672 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[66] origin:064-gtp-channel-conf 02_673 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[67] origin:064-gtp-channel-conf 03_673 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[68] origin:064-gtp-channel-conf 02_674 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[69] origin:064-gtp-channel-conf 03_674 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[70] origin:064-gtp-channel-conf 02_675 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[71] origin:064-gtp-channel-conf 03_675 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[72] origin:064-gtp-channel-conf 02_676 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[73] origin:064-gtp-channel-conf 03_676 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[74] origin:064-gtp-channel-conf 02_677 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[75] origin:064-gtp-channel-conf 03_677 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[76] origin:064-gtp-channel-conf 02_678 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[77] origin:064-gtp-channel-conf 03_678 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[78] origin:064-gtp-channel-conf 02_679 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[79] origin:064-gtp-channel-conf 03_679 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[80] origin:064-gtp-channel-conf 02_680 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[81] origin:064-gtp-channel-conf 03_680 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[82] origin:064-gtp-channel-conf 02_681 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_FR_RESET_ON_EIDLE[0] origin:064-gtp-channel-conf 02_638 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_HOLD_DURING_EIDLE[0] origin:064-gtp-channel-conf 03_637 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_LOCK_CFG[0] origin:064-gtp-channel-conf 02_632 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_LOCK_CFG[1] origin:064-gtp-channel-conf 03_632 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_LOCK_CFG[2] origin:064-gtp-channel-conf 02_633 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_LOCK_CFG[3] origin:064-gtp-channel-conf 03_633 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_LOCK_CFG[4] origin:064-gtp-channel-conf 02_634 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_LOCK_CFG[5] origin:064-gtp-channel-conf 03_634 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDR_PH_RESET_ON_EIDLE[0] origin:064-gtp-channel-conf 03_638 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDRFREQRESET_TIME[0] origin:064-gtp-channel-conf 01_106 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDRFREQRESET_TIME[1] origin:064-gtp-channel-conf 00_107 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDRFREQRESET_TIME[2] origin:064-gtp-channel-conf 01_107 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDRFREQRESET_TIME[3] origin:064-gtp-channel-conf 00_108 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDRFREQRESET_TIME[4] origin:064-gtp-channel-conf 01_108 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDRPHRESET_TIME[0] origin:064-gtp-channel-conf 00_109 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDRPHRESET_TIME[1] origin:064-gtp-channel-conf 01_109 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDRPHRESET_TIME[2] origin:064-gtp-channel-conf 00_110 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDRPHRESET_TIME[3] origin:064-gtp-channel-conf 01_110 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXCDRPHRESET_TIME[4] origin:064-gtp-channel-conf 00_111 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXDLY_CFG[0] origin:064-gtp-channel-conf 00_680 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXDLY_CFG[1] origin:064-gtp-channel-conf 01_680 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXDLY_CFG[2] origin:064-gtp-channel-conf 00_681 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXDLY_CFG[3] origin:064-gtp-channel-conf 01_681 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXDLY_CFG[4] origin:064-gtp-channel-conf 00_682 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXDLY_CFG[5] origin:064-gtp-channel-conf 01_682 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXDLY_CFG[6] origin:064-gtp-channel-conf 00_683 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXDLY_CFG[7] origin:064-gtp-channel-conf 01_683 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXDLY_CFG[8] origin:064-gtp-channel-conf 00_684 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXDLY_CFG[9] origin:064-gtp-channel-conf 01_684 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXDLY_CFG[10] origin:064-gtp-channel-conf 00_685 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXDLY_CFG[11] origin:064-gtp-channel-conf 01_685 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXDLY_CFG[12] origin:064-gtp-channel-conf 00_686 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXDLY_CFG[13] origin:064-gtp-channel-conf 01_686 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXDLY_CFG[14] origin:064-gtp-channel-conf 00_687 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXDLY_CFG[15] origin:064-gtp-channel-conf 01_687 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXDLY_LCFG[0] origin:064-gtp-channel-conf 02_576 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXDLY_LCFG[1] origin:064-gtp-channel-conf 03_576 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXDLY_LCFG[2] origin:064-gtp-channel-conf 02_577 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXDLY_LCFG[3] origin:064-gtp-channel-conf 03_577 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXDLY_LCFG[4] origin:064-gtp-channel-conf 02_578 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXDLY_LCFG[5] origin:064-gtp-channel-conf 03_578 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXDLY_LCFG[6] origin:064-gtp-channel-conf 02_579 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXDLY_LCFG[7] origin:064-gtp-channel-conf 03_579 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXDLY_LCFG[8] origin:064-gtp-channel-conf 02_580 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXDLY_TAP_CFG[0] origin:064-gtp-channel-conf 00_672 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXDLY_TAP_CFG[1] origin:064-gtp-channel-conf 01_672 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXDLY_TAP_CFG[2] origin:064-gtp-channel-conf 00_673 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXDLY_TAP_CFG[3] origin:064-gtp-channel-conf 01_673 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXDLY_TAP_CFG[4] origin:064-gtp-channel-conf 00_674 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXDLY_TAP_CFG[5] origin:064-gtp-channel-conf 01_674 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXDLY_TAP_CFG[6] origin:064-gtp-channel-conf 00_675 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXDLY_TAP_CFG[7] origin:064-gtp-channel-conf 01_675 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXDLY_TAP_CFG[8] origin:064-gtp-channel-conf 00_676 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXDLY_TAP_CFG[9] origin:064-gtp-channel-conf 01_676 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXDLY_TAP_CFG[10] origin:064-gtp-channel-conf 00_677 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXDLY_TAP_CFG[11] origin:064-gtp-channel-conf 01_677 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXDLY_TAP_CFG[12] origin:064-gtp-channel-conf 00_678 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXDLY_TAP_CFG[13] origin:064-gtp-channel-conf 01_678 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXDLY_TAP_CFG[14] origin:064-gtp-channel-conf 00_679 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXDLY_TAP_CFG[15] origin:064-gtp-channel-conf 01_679 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXGEARBOX_EN origin:064-gtp-channel-conf 01_607 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXISCANRESET_TIME[0] origin:064-gtp-channel-conf 01_123 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXISCANRESET_TIME[1] origin:064-gtp-channel-conf 00_124 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXISCANRESET_TIME[2] origin:064-gtp-channel-conf 01_124 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXISCANRESET_TIME[3] origin:064-gtp-channel-conf 00_125 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXISCANRESET_TIME[4] origin:064-gtp-channel-conf 01_125 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPM_BIAS_STARTUP_DISABLE[0] origin:064-gtp-channel-conf 03_391 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPM_CFG[0] origin:064-gtp-channel-conf 02_328 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPM_CFG[1] origin:064-gtp-channel-conf 03_328 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPM_CFG[2] origin:064-gtp-channel-conf 02_329 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPM_CFG[3] origin:064-gtp-channel-conf 03_329 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPM_CM_CFG[0] origin:064-gtp-channel-conf 02_430 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPM_GC_CFG[0] origin:064-gtp-channel-conf 02_432 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPM_GC_CFG[1] origin:064-gtp-channel-conf 03_432 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPM_GC_CFG[2] origin:064-gtp-channel-conf 02_433 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPM_GC_CFG[3] origin:064-gtp-channel-conf 03_433 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPM_GC_CFG[4] origin:064-gtp-channel-conf 02_434 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPM_GC_CFG[5] origin:064-gtp-channel-conf 03_434 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPM_GC_CFG[6] origin:064-gtp-channel-conf 02_435 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPM_GC_CFG[7] origin:064-gtp-channel-conf 03_435 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPM_GC_CFG[8] origin:064-gtp-channel-conf 02_436 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPM_GC_CFG2[0] origin:064-gtp-channel-conf 03_442 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPM_GC_CFG2[1] origin:064-gtp-channel-conf 02_443 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPM_GC_CFG2[2] origin:064-gtp-channel-conf 03_443 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG[0] origin:064-gtp-channel-conf 00_336 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG[1] origin:064-gtp-channel-conf 01_336 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG[2] origin:064-gtp-channel-conf 00_337 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG[3] origin:064-gtp-channel-conf 01_337 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG[4] origin:064-gtp-channel-conf 00_338 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG[5] origin:064-gtp-channel-conf 01_338 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG[6] origin:064-gtp-channel-conf 00_339 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG[7] origin:064-gtp-channel-conf 01_339 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG[8] origin:064-gtp-channel-conf 00_340 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG[9] origin:064-gtp-channel-conf 01_340 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG[10] origin:064-gtp-channel-conf 00_341 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG[11] origin:064-gtp-channel-conf 01_341 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG[12] origin:064-gtp-channel-conf 00_342 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG[13] origin:064-gtp-channel-conf 01_342 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG2[0] origin:064-gtp-channel-conf 02_424 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG2[1] origin:064-gtp-channel-conf 03_424 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG2[2] origin:064-gtp-channel-conf 02_425 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG2[3] origin:064-gtp-channel-conf 03_425 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG2[4] origin:064-gtp-channel-conf 02_426 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG3[0] origin:064-gtp-channel-conf 03_389 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG3[1] origin:064-gtp-channel-conf 02_390 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG3[2] origin:064-gtp-channel-conf 03_390 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG3[3] origin:064-gtp-channel-conf 02_391 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HOLD_DURING_EIDLE[0] origin:064-gtp-channel-conf 00_247 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPM_INCM_CFG[0] origin:064-gtp-channel-conf 02_439 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPM_IPCM_CFG[0] origin:064-gtp-channel-conf 03_439 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG[0] origin:064-gtp-channel-conf 00_344 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG[1] origin:064-gtp-channel-conf 01_344 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG[2] origin:064-gtp-channel-conf 00_345 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG[3] origin:064-gtp-channel-conf 01_345 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG[4] origin:064-gtp-channel-conf 00_346 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG[5] origin:064-gtp-channel-conf 01_346 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG[6] origin:064-gtp-channel-conf 00_347 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG[7] origin:064-gtp-channel-conf 01_347 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG[8] origin:064-gtp-channel-conf 00_348 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG[9] origin:064-gtp-channel-conf 01_348 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG[10] origin:064-gtp-channel-conf 00_349 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG[11] origin:064-gtp-channel-conf 01_349 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG[12] origin:064-gtp-channel-conf 00_350 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG[13] origin:064-gtp-channel-conf 01_350 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG[14] origin:064-gtp-channel-conf 00_351 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG[15] origin:064-gtp-channel-conf 01_351 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG[16] origin:064-gtp-channel-conf 00_343 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG[17] origin:064-gtp-channel-conf 01_343 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG2[0] origin:064-gtp-channel-conf 03_426 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG2[1] origin:064-gtp-channel-conf 02_427 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG2[2] origin:064-gtp-channel-conf 03_427 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG2[3] origin:064-gtp-channel-conf 02_428 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG2[4] origin:064-gtp-channel-conf 03_428 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPM_OSINT_CFG[0] origin:064-gtp-channel-conf 02_440 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPM_OSINT_CFG[1] origin:064-gtp-channel-conf 03_440 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPM_OSINT_CFG[2] origin:064-gtp-channel-conf 02_441 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPM_CFG1[0] origin:064-gtp-channel-conf 02_330 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPMRESET_TIME[0] origin:064-gtp-channel-conf 00_112 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPMRESET_TIME[1] origin:064-gtp-channel-conf 01_112 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPMRESET_TIME[2] origin:064-gtp-channel-conf 00_113 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPMRESET_TIME[3] origin:064-gtp-channel-conf 01_113 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPMRESET_TIME[4] origin:064-gtp-channel-conf 00_114 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPMRESET_TIME[5] origin:064-gtp-channel-conf 01_114 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXLPMRESET_TIME[6] origin:064-gtp-channel-conf 00_115 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXOOB_CFG[0] origin:064-gtp-channel-conf 00_144 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXOOB_CFG[1] origin:064-gtp-channel-conf 01_144 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXOOB_CFG[2] origin:064-gtp-channel-conf 00_145 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXOOB_CFG[3] origin:064-gtp-channel-conf 01_145 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXOOB_CFG[4] origin:064-gtp-channel-conf 00_146 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXOOB_CFG[5] origin:064-gtp-channel-conf 01_146 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXOOB_CFG[6] origin:064-gtp-channel-conf 00_147 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXOOB_CLK_CFG.FABRIC origin:064-gtp-channel-conf 03_129 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXOSCALRESET_TIME[0] origin:064-gtp-channel-conf 00_187 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXOSCALRESET_TIME[1] origin:064-gtp-channel-conf 01_187 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXOSCALRESET_TIME[2] origin:064-gtp-channel-conf 00_188 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXOSCALRESET_TIME[3] origin:064-gtp-channel-conf 01_188 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXOSCALRESET_TIME[4] origin:064-gtp-channel-conf 00_189 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXOSCALRESET_TIMEOUT[0] origin:064-gtp-channel-conf 01_189 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXOSCALRESET_TIMEOUT[1] origin:064-gtp-channel-conf 00_190 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXOSCALRESET_TIMEOUT[2] origin:064-gtp-channel-conf 01_190 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXOSCALRESET_TIMEOUT[3] origin:064-gtp-channel-conf 00_191 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXOSCALRESET_TIMEOUT[4] origin:064-gtp-channel-conf 01_191 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXOUT_DIV[0] origin:064-gtp-channel-conf 02_384 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXOUT_DIV[1] origin:064-gtp-channel-conf 03_384 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXPCSRESET_TIME[0] origin:064-gtp-channel-conf 01_115 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXPCSRESET_TIME[1] origin:064-gtp-channel-conf 00_116 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXPCSRESET_TIME[2] origin:064-gtp-channel-conf 01_116 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXPCSRESET_TIME[3] origin:064-gtp-channel-conf 00_117 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXPCSRESET_TIME[4] origin:064-gtp-channel-conf 01_117 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[0] origin:064-gtp-channel-conf 02_584 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[1] origin:064-gtp-channel-conf 03_584 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[2] origin:064-gtp-channel-conf 02_585 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[3] origin:064-gtp-channel-conf 03_585 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[4] origin:064-gtp-channel-conf 02_586 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[5] origin:064-gtp-channel-conf 03_586 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[6] origin:064-gtp-channel-conf 02_587 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[7] origin:064-gtp-channel-conf 03_587 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[8] origin:064-gtp-channel-conf 02_588 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[9] origin:064-gtp-channel-conf 03_588 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[10] origin:064-gtp-channel-conf 02_589 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[11] origin:064-gtp-channel-conf 03_589 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[12] origin:064-gtp-channel-conf 02_590 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[13] origin:064-gtp-channel-conf 03_590 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[14] origin:064-gtp-channel-conf 02_591 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[15] origin:064-gtp-channel-conf 03_591 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[16] origin:064-gtp-channel-conf 02_592 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[17] origin:064-gtp-channel-conf 03_592 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[18] origin:064-gtp-channel-conf 02_593 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[19] origin:064-gtp-channel-conf 03_593 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[20] origin:064-gtp-channel-conf 02_594 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[21] origin:064-gtp-channel-conf 03_594 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[22] origin:064-gtp-channel-conf 02_595 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[23] origin:064-gtp-channel-conf 03_595 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXPH_MONITOR_SEL[0] origin:064-gtp-channel-conf 00_700 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXPH_MONITOR_SEL[1] origin:064-gtp-channel-conf 01_700 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXPH_MONITOR_SEL[2] origin:064-gtp-channel-conf 00_701 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXPH_MONITOR_SEL[3] origin:064-gtp-channel-conf 01_701 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXPH_MONITOR_SEL[4] origin:064-gtp-channel-conf 00_702 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[0] origin:064-gtp-channel-conf 02_600 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[1] origin:064-gtp-channel-conf 03_600 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[2] origin:064-gtp-channel-conf 02_601 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[3] origin:064-gtp-channel-conf 03_601 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[4] origin:064-gtp-channel-conf 02_602 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[5] origin:064-gtp-channel-conf 03_602 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[6] origin:064-gtp-channel-conf 02_603 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[7] origin:064-gtp-channel-conf 03_603 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[8] origin:064-gtp-channel-conf 02_604 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[9] origin:064-gtp-channel-conf 03_604 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[10] origin:064-gtp-channel-conf 02_605 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[11] origin:064-gtp-channel-conf 03_605 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[12] origin:064-gtp-channel-conf 02_606 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[13] origin:064-gtp-channel-conf 03_606 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[14] origin:064-gtp-channel-conf 02_607 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[15] origin:064-gtp-channel-conf 03_607 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[16] origin:064-gtp-channel-conf 02_608 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[17] origin:064-gtp-channel-conf 03_608 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[18] origin:064-gtp-channel-conf 02_609 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[19] origin:064-gtp-channel-conf 03_609 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[20] origin:064-gtp-channel-conf 02_610 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[21] origin:064-gtp-channel-conf 03_610 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[22] origin:064-gtp-channel-conf 02_611 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[23] origin:064-gtp-channel-conf 03_611 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXPI_CFG0[0] origin:064-gtp-channel-conf 03_430 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXPI_CFG0[1] origin:064-gtp-channel-conf 02_431 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXPI_CFG0[2] origin:064-gtp-channel-conf 03_431 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXPI_CFG1[0] origin:064-gtp-channel-conf 02_442 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXPI_CFG2[0] origin:064-gtp-channel-conf 03_441 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXPMARESET_TIME[0] origin:064-gtp-channel-conf 00_104 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXPMARESET_TIME[1] origin:064-gtp-channel-conf 01_104 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXPMARESET_TIME[2] origin:064-gtp-channel-conf 00_105 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXPMARESET_TIME[3] origin:064-gtp-channel-conf 01_105 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXPMARESET_TIME[4] origin:064-gtp-channel-conf 00_106 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXPRBS_ERR_LOOPBACK[0] origin:064-gtp-channel-conf 00_136 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXSLIDE_AUTO_WAIT[0] origin:064-gtp-channel-conf 00_520 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXSLIDE_AUTO_WAIT[1] origin:064-gtp-channel-conf 01_520 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXSLIDE_AUTO_WAIT[2] origin:064-gtp-channel-conf 00_521 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXSLIDE_AUTO_WAIT[3] origin:064-gtp-channel-conf 01_521 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXSLIDE_MODE.AUTO origin:064-gtp-channel-conf !01_519 00_519 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXSLIDE_MODE.PCS origin:064-gtp-channel-conf !00_519 01_519 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXSLIDE_MODE.PMA origin:064-gtp-channel-conf 00_519 01_519 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXSYNC_MULTILANE[0] origin:064-gtp-channel-conf 00_133 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXSYNC_OVRD[0] origin:064-gtp-channel-conf 01_135 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.RXSYNC_SKIP_DA[0] origin:064-gtp-channel-conf 01_134 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.SAS_MAX_COM[0] origin:064-gtp-channel-conf 00_171 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.SAS_MAX_COM[1] origin:064-gtp-channel-conf 01_171 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.SAS_MAX_COM[2] origin:064-gtp-channel-conf 00_172 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.SAS_MAX_COM[3] origin:064-gtp-channel-conf 01_172 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.SAS_MAX_COM[4] origin:064-gtp-channel-conf 00_173 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.SAS_MAX_COM[5] origin:064-gtp-channel-conf 01_173 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.SAS_MAX_COM[6] origin:064-gtp-channel-conf 00_174 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.SAS_MIN_COM[0] origin:064-gtp-channel-conf 01_156 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.SAS_MIN_COM[1] origin:064-gtp-channel-conf 00_157 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.SAS_MIN_COM[2] origin:064-gtp-channel-conf 01_157 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.SAS_MIN_COM[3] origin:064-gtp-channel-conf 00_158 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.SAS_MIN_COM[4] origin:064-gtp-channel-conf 01_158 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.SAS_MIN_COM[5] origin:064-gtp-channel-conf 00_159 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.SATA_BURST_SEQ_LEN[0] origin:064-gtp-channel-conf 00_150 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.SATA_BURST_SEQ_LEN[1] origin:064-gtp-channel-conf 01_150 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.SATA_BURST_SEQ_LEN[2] origin:064-gtp-channel-conf 00_151 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.SATA_BURST_SEQ_LEN[3] origin:064-gtp-channel-conf 01_151 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.SATA_BURST_VAL[0] origin:064-gtp-channel-conf 01_147 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.SATA_BURST_VAL[1] origin:064-gtp-channel-conf 00_148 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.SATA_BURST_VAL[2] origin:064-gtp-channel-conf 01_148 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.SATA_EIDLE_VAL[0] origin:064-gtp-channel-conf 00_152 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.SATA_EIDLE_VAL[1] origin:064-gtp-channel-conf 01_152 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.SATA_EIDLE_VAL[2] origin:064-gtp-channel-conf 00_153 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.SATA_MAX_BURST[0] origin:064-gtp-channel-conf 00_168 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.SATA_MAX_BURST[1] origin:064-gtp-channel-conf 01_168 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.SATA_MAX_BURST[2] origin:064-gtp-channel-conf 00_169 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.SATA_MAX_BURST[3] origin:064-gtp-channel-conf 01_169 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.SATA_MAX_BURST[4] origin:064-gtp-channel-conf 00_170 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.SATA_MAX_BURST[5] origin:064-gtp-channel-conf 01_170 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.SATA_MAX_INIT[0] origin:064-gtp-channel-conf 00_176 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.SATA_MAX_INIT[1] origin:064-gtp-channel-conf 01_176 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.SATA_MAX_INIT[2] origin:064-gtp-channel-conf 00_177 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.SATA_MAX_INIT[3] origin:064-gtp-channel-conf 01_177 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.SATA_MAX_INIT[4] origin:064-gtp-channel-conf 00_178 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.SATA_MAX_INIT[5] origin:064-gtp-channel-conf 01_178 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.SATA_MAX_WAKE[0] origin:064-gtp-channel-conf 00_179 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.SATA_MAX_WAKE[1] origin:064-gtp-channel-conf 01_179 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.SATA_MAX_WAKE[2] origin:064-gtp-channel-conf 00_180 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.SATA_MAX_WAKE[3] origin:064-gtp-channel-conf 01_180 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.SATA_MAX_WAKE[4] origin:064-gtp-channel-conf 00_181 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.SATA_MAX_WAKE[5] origin:064-gtp-channel-conf 01_181 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.SATA_MIN_BURST[0] origin:064-gtp-channel-conf 01_153 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.SATA_MIN_BURST[1] origin:064-gtp-channel-conf 00_154 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.SATA_MIN_BURST[2] origin:064-gtp-channel-conf 01_154 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.SATA_MIN_BURST[3] origin:064-gtp-channel-conf 00_155 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.SATA_MIN_BURST[4] origin:064-gtp-channel-conf 01_155 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.SATA_MIN_BURST[5] origin:064-gtp-channel-conf 00_156 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.SATA_MIN_INIT[0] origin:064-gtp-channel-conf 00_160 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.SATA_MIN_INIT[1] origin:064-gtp-channel-conf 01_160 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.SATA_MIN_INIT[2] origin:064-gtp-channel-conf 00_161 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.SATA_MIN_INIT[3] origin:064-gtp-channel-conf 01_161 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.SATA_MIN_INIT[4] origin:064-gtp-channel-conf 00_162 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.SATA_MIN_INIT[5] origin:064-gtp-channel-conf 01_162 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.SATA_MIN_WAKE[0] origin:064-gtp-channel-conf 00_163 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.SATA_MIN_WAKE[1] origin:064-gtp-channel-conf 01_163 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.SATA_MIN_WAKE[2] origin:064-gtp-channel-conf 00_164 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.SATA_MIN_WAKE[3] origin:064-gtp-channel-conf 01_164 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.SATA_MIN_WAKE[4] origin:064-gtp-channel-conf 00_165 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.SATA_MIN_WAKE[5] origin:064-gtp-channel-conf 01_165 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.SATA_PLL_CFG.VCO_1500MHZ origin:064-gtp-channel-conf 02_55 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.SATA_PLL_CFG.VCO_750MHZ origin:064-gtp-channel-conf 03_55 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.SHOW_REALIGN_COMMA origin:064-gtp-channel-conf 01_522 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TERM_RCAL_CFG[0] origin:064-gtp-channel-conf 02_136 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TERM_RCAL_CFG[1] origin:064-gtp-channel-conf 03_136 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TERM_RCAL_CFG[2] origin:064-gtp-channel-conf 02_137 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TERM_RCAL_CFG[3] origin:064-gtp-channel-conf 03_137 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TERM_RCAL_CFG[4] origin:064-gtp-channel-conf 02_138 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TERM_RCAL_CFG[5] origin:064-gtp-channel-conf 03_138 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TERM_RCAL_CFG[6] origin:064-gtp-channel-conf 02_139 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TERM_RCAL_CFG[7] origin:064-gtp-channel-conf 03_139 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TERM_RCAL_CFG[8] origin:064-gtp-channel-conf 02_140 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TERM_RCAL_CFG[9] origin:064-gtp-channel-conf 03_140 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TERM_RCAL_CFG[10] origin:064-gtp-channel-conf 02_141 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TERM_RCAL_CFG[11] origin:064-gtp-channel-conf 03_141 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TERM_RCAL_CFG[12] origin:064-gtp-channel-conf 02_142 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TERM_RCAL_CFG[13] origin:064-gtp-channel-conf 03_142 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TERM_RCAL_CFG[14] origin:064-gtp-channel-conf 02_143 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TERM_RCAL_OVRD[0] origin:064-gtp-channel-conf 03_150 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TERM_RCAL_OVRD[1] origin:064-gtp-channel-conf 02_151 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TERM_RCAL_OVRD[2] origin:064-gtp-channel-conf 03_151 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TRANS_TIME_RATE[0] origin:064-gtp-channel-conf 00_192 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TRANS_TIME_RATE[1] origin:064-gtp-channel-conf 01_192 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TRANS_TIME_RATE[2] origin:064-gtp-channel-conf 00_193 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TRANS_TIME_RATE[3] origin:064-gtp-channel-conf 01_193 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TRANS_TIME_RATE[4] origin:064-gtp-channel-conf 00_194 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TRANS_TIME_RATE[5] origin:064-gtp-channel-conf 01_194 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TRANS_TIME_RATE[6] origin:064-gtp-channel-conf 00_195 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TRANS_TIME_RATE[7] origin:064-gtp-channel-conf 01_195 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[0] origin:064-gtp-channel-conf 02_504 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[1] origin:064-gtp-channel-conf 03_504 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[2] origin:064-gtp-channel-conf 02_505 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[3] origin:064-gtp-channel-conf 03_505 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[4] origin:064-gtp-channel-conf 02_506 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[5] origin:064-gtp-channel-conf 03_506 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[6] origin:064-gtp-channel-conf 02_507 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[7] origin:064-gtp-channel-conf 03_507 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[8] origin:064-gtp-channel-conf 02_508 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[9] origin:064-gtp-channel-conf 03_508 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[10] origin:064-gtp-channel-conf 02_509 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[11] origin:064-gtp-channel-conf 03_509 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[12] origin:064-gtp-channel-conf 02_510 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[13] origin:064-gtp-channel-conf 03_510 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[14] origin:064-gtp-channel-conf 02_511 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[15] origin:064-gtp-channel-conf 03_511 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[16] origin:064-gtp-channel-conf 02_512 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[17] origin:064-gtp-channel-conf 03_512 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[18] origin:064-gtp-channel-conf 02_513 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[19] origin:064-gtp-channel-conf 03_513 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[20] origin:064-gtp-channel-conf 02_514 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[21] origin:064-gtp-channel-conf 03_514 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[22] origin:064-gtp-channel-conf 02_515 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[23] origin:064-gtp-channel-conf 03_515 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[24] origin:064-gtp-channel-conf 02_516 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[25] origin:064-gtp-channel-conf 03_516 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[26] origin:064-gtp-channel-conf 02_517 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[27] origin:064-gtp-channel-conf 03_517 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[28] origin:064-gtp-channel-conf 02_518 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[29] origin:064-gtp-channel-conf 03_518 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[30] origin:064-gtp-channel-conf 02_519 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[31] origin:064-gtp-channel-conf 03_519 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_CLKMUX_EN[0] origin:064-gtp-channel-conf 03_128 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_DATA_WIDTH[0] origin:064-gtp-channel-conf 02_152 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_DATA_WIDTH[1] origin:064-gtp-channel-conf 03_152 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_DATA_WIDTH[2] origin:064-gtp-channel-conf 02_153 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_DRIVE_MODE.PIPE origin:064-gtp-channel-conf 00_200 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_EIDLE_ASSERT_DELAY[0] origin:064-gtp-channel-conf 00_203 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_EIDLE_ASSERT_DELAY[1] origin:064-gtp-channel-conf 01_203 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_EIDLE_ASSERT_DELAY[2] origin:064-gtp-channel-conf 00_204 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_EIDLE_DEASSERT_DELAY[0] origin:064-gtp-channel-conf 01_204 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_EIDLE_DEASSERT_DELAY[1] origin:064-gtp-channel-conf 00_205 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_EIDLE_DEASSERT_DELAY[2] origin:064-gtp-channel-conf 01_205 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_LOOPBACK_DRIVE_HIZ origin:064-gtp-channel-conf 01_202 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_MAINCURSOR_SEL[0] origin:064-gtp-channel-conf 03_289 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_0[0] origin:064-gtp-channel-conf 02_232 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_0[1] origin:064-gtp-channel-conf 03_232 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_0[2] origin:064-gtp-channel-conf 02_233 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_0[3] origin:064-gtp-channel-conf 03_233 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_0[4] origin:064-gtp-channel-conf 02_234 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_0[5] origin:064-gtp-channel-conf 03_234 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_0[6] origin:064-gtp-channel-conf 02_235 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_1[0] origin:064-gtp-channel-conf 02_236 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_1[1] origin:064-gtp-channel-conf 03_236 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_1[2] origin:064-gtp-channel-conf 02_237 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_1[3] origin:064-gtp-channel-conf 03_237 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_1[4] origin:064-gtp-channel-conf 02_238 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_1[5] origin:064-gtp-channel-conf 03_238 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_1[6] origin:064-gtp-channel-conf 02_239 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_2[0] origin:064-gtp-channel-conf 02_240 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_2[1] origin:064-gtp-channel-conf 03_240 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_2[2] origin:064-gtp-channel-conf 02_241 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_2[3] origin:064-gtp-channel-conf 03_241 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_2[4] origin:064-gtp-channel-conf 02_242 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_2[5] origin:064-gtp-channel-conf 03_242 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_2[6] origin:064-gtp-channel-conf 02_243 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_3[0] origin:064-gtp-channel-conf 02_244 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_3[1] origin:064-gtp-channel-conf 03_244 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_3[2] origin:064-gtp-channel-conf 02_245 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_3[3] origin:064-gtp-channel-conf 03_245 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_3[4] origin:064-gtp-channel-conf 02_246 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_3[5] origin:064-gtp-channel-conf 03_246 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_3[6] origin:064-gtp-channel-conf 02_247 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_4[0] origin:064-gtp-channel-conf 02_248 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_4[1] origin:064-gtp-channel-conf 03_248 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_4[2] origin:064-gtp-channel-conf 02_249 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_4[3] origin:064-gtp-channel-conf 03_249 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_4[4] origin:064-gtp-channel-conf 02_250 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_4[5] origin:064-gtp-channel-conf 03_250 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_4[6] origin:064-gtp-channel-conf 02_251 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_0[0] origin:064-gtp-channel-conf 02_252 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_0[1] origin:064-gtp-channel-conf 03_252 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_0[2] origin:064-gtp-channel-conf 02_253 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_0[3] origin:064-gtp-channel-conf 03_253 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_0[4] origin:064-gtp-channel-conf 02_254 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_0[5] origin:064-gtp-channel-conf 03_254 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_0[6] origin:064-gtp-channel-conf 02_255 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_1[0] origin:064-gtp-channel-conf 02_256 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_1[1] origin:064-gtp-channel-conf 03_256 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_1[2] origin:064-gtp-channel-conf 02_257 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_1[3] origin:064-gtp-channel-conf 03_257 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_1[4] origin:064-gtp-channel-conf 02_258 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_1[5] origin:064-gtp-channel-conf 03_258 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_1[6] origin:064-gtp-channel-conf 02_259 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_2[0] origin:064-gtp-channel-conf 02_260 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_2[1] origin:064-gtp-channel-conf 03_260 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_2[2] origin:064-gtp-channel-conf 02_261 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_2[3] origin:064-gtp-channel-conf 03_261 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_2[4] origin:064-gtp-channel-conf 02_262 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_2[5] origin:064-gtp-channel-conf 03_262 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_2[6] origin:064-gtp-channel-conf 02_263 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_3[0] origin:064-gtp-channel-conf 02_264 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_3[1] origin:064-gtp-channel-conf 03_264 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_3[2] origin:064-gtp-channel-conf 02_265 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_3[3] origin:064-gtp-channel-conf 03_265 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_3[4] origin:064-gtp-channel-conf 02_266 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_3[5] origin:064-gtp-channel-conf 03_266 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_3[6] origin:064-gtp-channel-conf 02_267 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_4[0] origin:064-gtp-channel-conf 02_268 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_4[1] origin:064-gtp-channel-conf 03_268 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_4[2] origin:064-gtp-channel-conf 02_269 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_4[3] origin:064-gtp-channel-conf 03_269 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_4[4] origin:064-gtp-channel-conf 02_270 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_4[5] origin:064-gtp-channel-conf 03_270 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_4[6] origin:064-gtp-channel-conf 02_271 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_PREDRIVER_MODE[0] origin:064-gtp-channel-conf 00_206 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_RXDETECT_CFG[0] origin:064-gtp-channel-conf 02_296 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_RXDETECT_CFG[1] origin:064-gtp-channel-conf 03_296 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_RXDETECT_CFG[2] origin:064-gtp-channel-conf 02_297 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_RXDETECT_CFG[3] origin:064-gtp-channel-conf 03_297 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_RXDETECT_CFG[4] origin:064-gtp-channel-conf 02_298 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_RXDETECT_CFG[5] origin:064-gtp-channel-conf 03_298 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_RXDETECT_CFG[6] origin:064-gtp-channel-conf 02_299 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_RXDETECT_CFG[7] origin:064-gtp-channel-conf 03_299 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_RXDETECT_CFG[8] origin:064-gtp-channel-conf 02_300 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_RXDETECT_CFG[9] origin:064-gtp-channel-conf 03_300 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_RXDETECT_CFG[10] origin:064-gtp-channel-conf 02_301 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_RXDETECT_CFG[11] origin:064-gtp-channel-conf 03_301 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_RXDETECT_CFG[12] origin:064-gtp-channel-conf 02_302 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_RXDETECT_CFG[13] origin:064-gtp-channel-conf 03_302 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_RXDETECT_REF[0] origin:064-gtp-channel-conf 02_292 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_RXDETECT_REF[1] origin:064-gtp-channel-conf 03_292 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_RXDETECT_REF[2] origin:064-gtp-channel-conf 02_293 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_XCLK_SEL.TXUSR origin:064-gtp-channel-conf 03_11 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_CLK25_DIV[0] origin:064-gtp-channel-conf 02_144 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_CLK25_DIV[1] origin:064-gtp-channel-conf 03_144 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_CLK25_DIV[2] origin:064-gtp-channel-conf 02_145 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_CLK25_DIV[3] origin:064-gtp-channel-conf 03_145 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_CLK25_DIV[4] origin:064-gtp-channel-conf 02_146 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_DEEMPH0[0] origin:064-gtp-channel-conf 02_272 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_DEEMPH0[1] origin:064-gtp-channel-conf 03_272 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_DEEMPH0[2] origin:064-gtp-channel-conf 02_273 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_DEEMPH0[3] origin:064-gtp-channel-conf 03_273 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_DEEMPH0[4] origin:064-gtp-channel-conf 02_274 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_DEEMPH0[5] origin:064-gtp-channel-conf 03_274 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_DEEMPH1[0] origin:064-gtp-channel-conf 02_276 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_DEEMPH1[1] origin:064-gtp-channel-conf 03_276 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_DEEMPH1[2] origin:064-gtp-channel-conf 02_277 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_DEEMPH1[3] origin:064-gtp-channel-conf 03_277 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_DEEMPH1[4] origin:064-gtp-channel-conf 02_278 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TX_DEEMPH1[5] origin:064-gtp-channel-conf 03_278 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXBUF_EN origin:064-gtp-channel-conf 00_231 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXBUF_RESET_ON_RATE_CHANGE origin:064-gtp-channel-conf 01_231 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXDLY_CFG[0] origin:064-gtp-channel-conf 02_80 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXDLY_CFG[1] origin:064-gtp-channel-conf 03_80 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXDLY_CFG[2] origin:064-gtp-channel-conf 02_81 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXDLY_CFG[3] origin:064-gtp-channel-conf 03_81 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXDLY_CFG[4] origin:064-gtp-channel-conf 02_82 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXDLY_CFG[5] origin:064-gtp-channel-conf 03_82 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXDLY_CFG[6] origin:064-gtp-channel-conf 02_83 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXDLY_CFG[7] origin:064-gtp-channel-conf 03_83 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXDLY_CFG[8] origin:064-gtp-channel-conf 02_84 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXDLY_CFG[9] origin:064-gtp-channel-conf 03_84 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXDLY_CFG[10] origin:064-gtp-channel-conf 02_85 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXDLY_CFG[11] origin:064-gtp-channel-conf 03_85 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXDLY_CFG[12] origin:064-gtp-channel-conf 02_86 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXDLY_CFG[13] origin:064-gtp-channel-conf 03_86 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXDLY_CFG[14] origin:064-gtp-channel-conf 02_87 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXDLY_CFG[15] origin:064-gtp-channel-conf 03_87 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXDLY_LCFG[0] origin:064-gtp-channel-conf 02_568 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXDLY_LCFG[1] origin:064-gtp-channel-conf 03_568 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXDLY_LCFG[2] origin:064-gtp-channel-conf 02_569 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXDLY_LCFG[3] origin:064-gtp-channel-conf 03_569 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXDLY_LCFG[4] origin:064-gtp-channel-conf 02_570 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXDLY_LCFG[5] origin:064-gtp-channel-conf 03_570 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXDLY_LCFG[6] origin:064-gtp-channel-conf 02_571 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXDLY_LCFG[7] origin:064-gtp-channel-conf 03_571 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXDLY_LCFG[8] origin:064-gtp-channel-conf 02_572 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXDLY_TAP_CFG[0] origin:064-gtp-channel-conf 02_88 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXDLY_TAP_CFG[1] origin:064-gtp-channel-conf 03_88 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXDLY_TAP_CFG[2] origin:064-gtp-channel-conf 02_89 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXDLY_TAP_CFG[3] origin:064-gtp-channel-conf 03_89 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXDLY_TAP_CFG[4] origin:064-gtp-channel-conf 02_90 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXDLY_TAP_CFG[5] origin:064-gtp-channel-conf 03_90 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXDLY_TAP_CFG[6] origin:064-gtp-channel-conf 02_91 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXDLY_TAP_CFG[7] origin:064-gtp-channel-conf 03_91 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXDLY_TAP_CFG[8] origin:064-gtp-channel-conf 02_92 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXDLY_TAP_CFG[9] origin:064-gtp-channel-conf 03_92 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXDLY_TAP_CFG[10] origin:064-gtp-channel-conf 02_93 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXDLY_TAP_CFG[11] origin:064-gtp-channel-conf 03_93 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXDLY_TAP_CFG[12] origin:064-gtp-channel-conf 02_94 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXDLY_TAP_CFG[13] origin:064-gtp-channel-conf 03_94 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXDLY_TAP_CFG[14] origin:064-gtp-channel-conf 02_95 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXDLY_TAP_CFG[15] origin:064-gtp-channel-conf 03_95 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXGEARBOX_EN origin:064-gtp-channel-conf 01_226 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXOOB_CFG[0] origin:064-gtp-channel-conf 03_20 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXOUT_DIV[0] origin:064-gtp-channel-conf 02_386 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXOUT_DIV[1] origin:064-gtp-channel-conf 03_386 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPCSRESET_TIME[0] origin:064-gtp-channel-conf 01_130 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPCSRESET_TIME[1] origin:064-gtp-channel-conf 00_131 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPCSRESET_TIME[2] origin:064-gtp-channel-conf 01_131 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPCSRESET_TIME[3] origin:064-gtp-channel-conf 00_132 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPCSRESET_TIME[4] origin:064-gtp-channel-conf 01_132 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPH_CFG[0] origin:064-gtp-channel-conf 02_96 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPH_CFG[1] origin:064-gtp-channel-conf 03_96 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPH_CFG[2] origin:064-gtp-channel-conf 02_97 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPH_CFG[3] origin:064-gtp-channel-conf 03_97 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPH_CFG[4] origin:064-gtp-channel-conf 02_98 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPH_CFG[5] origin:064-gtp-channel-conf 03_98 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPH_CFG[6] origin:064-gtp-channel-conf 02_99 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPH_CFG[7] origin:064-gtp-channel-conf 03_99 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPH_CFG[8] origin:064-gtp-channel-conf 02_100 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPH_CFG[9] origin:064-gtp-channel-conf 03_100 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPH_CFG[10] origin:064-gtp-channel-conf 02_101 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPH_CFG[11] origin:064-gtp-channel-conf 03_101 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPH_CFG[12] origin:064-gtp-channel-conf 02_102 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPH_CFG[13] origin:064-gtp-channel-conf 03_102 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPH_CFG[14] origin:064-gtp-channel-conf 02_103 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPH_CFG[15] origin:064-gtp-channel-conf 03_103 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPH_MONITOR_SEL[0] origin:064-gtp-channel-conf 02_108 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPH_MONITOR_SEL[1] origin:064-gtp-channel-conf 03_108 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPH_MONITOR_SEL[2] origin:064-gtp-channel-conf 02_109 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPH_MONITOR_SEL[3] origin:064-gtp-channel-conf 03_109 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPH_MONITOR_SEL[4] origin:064-gtp-channel-conf 02_110 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[0] origin:064-gtp-channel-conf 02_64 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[1] origin:064-gtp-channel-conf 03_64 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[2] origin:064-gtp-channel-conf 02_65 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[3] origin:064-gtp-channel-conf 03_65 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[4] origin:064-gtp-channel-conf 02_66 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[5] origin:064-gtp-channel-conf 03_66 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[6] origin:064-gtp-channel-conf 02_67 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[7] origin:064-gtp-channel-conf 03_67 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[8] origin:064-gtp-channel-conf 02_68 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[9] origin:064-gtp-channel-conf 03_68 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[10] origin:064-gtp-channel-conf 02_69 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[11] origin:064-gtp-channel-conf 03_69 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[12] origin:064-gtp-channel-conf 02_70 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[13] origin:064-gtp-channel-conf 03_70 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[14] origin:064-gtp-channel-conf 02_71 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[15] origin:064-gtp-channel-conf 03_71 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[16] origin:064-gtp-channel-conf 02_72 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[17] origin:064-gtp-channel-conf 03_72 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[18] origin:064-gtp-channel-conf 02_73 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[19] origin:064-gtp-channel-conf 03_73 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[20] origin:064-gtp-channel-conf 02_74 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[21] origin:064-gtp-channel-conf 03_74 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[22] origin:064-gtp-channel-conf 02_75 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[23] origin:064-gtp-channel-conf 03_75 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPI_GREY_SEL[0] origin:064-gtp-channel-conf 03_498 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPI_INVSTROBE_SEL[0] origin:064-gtp-channel-conf 02_498 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPI_PPM_CFG[0] origin:064-gtp-channel-conf 02_488 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPI_PPM_CFG[1] origin:064-gtp-channel-conf 03_488 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPI_PPM_CFG[2] origin:064-gtp-channel-conf 02_489 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPI_PPM_CFG[3] origin:064-gtp-channel-conf 03_489 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPI_PPM_CFG[4] origin:064-gtp-channel-conf 02_490 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPI_PPM_CFG[5] origin:064-gtp-channel-conf 03_490 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPI_PPM_CFG[6] origin:064-gtp-channel-conf 02_491 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPI_PPM_CFG[7] origin:064-gtp-channel-conf 03_491 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPI_PPMCLK_SEL.TXUSRCLK2 origin:064-gtp-channel-conf 03_497 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPI_SYNFREQ_PPM[0] origin:064-gtp-channel-conf 02_496 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPI_SYNFREQ_PPM[1] origin:064-gtp-channel-conf 03_496 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPI_SYNFREQ_PPM[2] origin:064-gtp-channel-conf 02_497 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPI_CFG0[0] origin:064-gtp-channel-conf 02_40 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPI_CFG0[1] origin:064-gtp-channel-conf 03_40 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPI_CFG1[0] origin:064-gtp-channel-conf 02_41 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPI_CFG1[1] origin:064-gtp-channel-conf 03_41 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPI_CFG2[0] origin:064-gtp-channel-conf 02_42 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPI_CFG2[1] origin:064-gtp-channel-conf 03_42 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPI_CFG3[0] origin:064-gtp-channel-conf 02_43 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPI_CFG4[0] origin:064-gtp-channel-conf 03_43 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPI_CFG5[0] origin:064-gtp-channel-conf 02_44 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPI_CFG5[1] origin:064-gtp-channel-conf 03_44 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPI_CFG5[2] origin:064-gtp-channel-conf 02_45 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPMARESET_TIME[0] origin:064-gtp-channel-conf 00_128 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPMARESET_TIME[1] origin:064-gtp-channel-conf 01_128 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPMARESET_TIME[2] origin:064-gtp-channel-conf 00_129 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPMARESET_TIME[3] origin:064-gtp-channel-conf 01_129 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXPMARESET_TIME[4] origin:064-gtp-channel-conf 00_130 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXSYNC_MULTILANE[0] origin:064-gtp-channel-conf 01_133 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXSYNC_OVRD[0] origin:064-gtp-channel-conf 00_135 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.TXSYNC_SKIP_DA[0] origin:064-gtp-channel-conf 00_134 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.UCODEER_CLR[0] origin:064-gtp-channel-conf 01_00 +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL.USE_PCS_CLK_PHASE_SEL[0] origin:064-gtp-channel-conf 02_463 diff --git a/artix7/segbits_gtp_channel_1.db b/artix7/segbits_gtp_channel_1.db index cfdeff1..337a625 100644 --- a/artix7/segbits_gtp_channel_1.db +++ b/artix7/segbits_gtp_channel_1.db @@ -1,1627 +1,1627 @@ -GTP_CHANNEL_1.GTPE2.ACJTAG_DEBUG_MODE[0] 28_07 -GTP_CHANNEL_1.GTPE2.ACJTAG_MODE[0] 29_06 -GTP_CHANNEL_1.GTPE2.ACJTAG_RESET[0] 29_07 -GTP_CHANNEL_1.GTPE2.ADAPT_CFG0[0] 30_464 -GTP_CHANNEL_1.GTPE2.ADAPT_CFG0[1] 31_464 -GTP_CHANNEL_1.GTPE2.ADAPT_CFG0[2] 30_465 -GTP_CHANNEL_1.GTPE2.ADAPT_CFG0[3] 31_465 -GTP_CHANNEL_1.GTPE2.ADAPT_CFG0[4] 30_466 -GTP_CHANNEL_1.GTPE2.ADAPT_CFG0[5] 31_466 -GTP_CHANNEL_1.GTPE2.ADAPT_CFG0[6] 30_467 -GTP_CHANNEL_1.GTPE2.ADAPT_CFG0[7] 31_467 -GTP_CHANNEL_1.GTPE2.ADAPT_CFG0[8] 30_468 -GTP_CHANNEL_1.GTPE2.ADAPT_CFG0[9] 31_468 -GTP_CHANNEL_1.GTPE2.ADAPT_CFG0[10] 30_469 -GTP_CHANNEL_1.GTPE2.ADAPT_CFG0[11] 31_469 -GTP_CHANNEL_1.GTPE2.ADAPT_CFG0[12] 30_470 -GTP_CHANNEL_1.GTPE2.ADAPT_CFG0[13] 31_470 -GTP_CHANNEL_1.GTPE2.ADAPT_CFG0[14] 30_471 -GTP_CHANNEL_1.GTPE2.ADAPT_CFG0[15] 31_471 -GTP_CHANNEL_1.GTPE2.ADAPT_CFG0[16] 30_472 -GTP_CHANNEL_1.GTPE2.ADAPT_CFG0[17] 31_472 -GTP_CHANNEL_1.GTPE2.ADAPT_CFG0[18] 30_473 -GTP_CHANNEL_1.GTPE2.ADAPT_CFG0[19] 31_473 -GTP_CHANNEL_1.GTPE2.ALIGN_COMMA_DOUBLE 28_522 -GTP_CHANNEL_1.GTPE2.ALIGN_COMMA_ENABLE[0] 28_496 -GTP_CHANNEL_1.GTPE2.ALIGN_COMMA_ENABLE[1] 29_496 -GTP_CHANNEL_1.GTPE2.ALIGN_COMMA_ENABLE[2] 28_497 -GTP_CHANNEL_1.GTPE2.ALIGN_COMMA_ENABLE[3] 29_497 -GTP_CHANNEL_1.GTPE2.ALIGN_COMMA_ENABLE[4] 28_498 -GTP_CHANNEL_1.GTPE2.ALIGN_COMMA_ENABLE[5] 29_498 -GTP_CHANNEL_1.GTPE2.ALIGN_COMMA_ENABLE[6] 28_499 -GTP_CHANNEL_1.GTPE2.ALIGN_COMMA_ENABLE[7] 29_499 -GTP_CHANNEL_1.GTPE2.ALIGN_COMMA_ENABLE[8] 28_500 -GTP_CHANNEL_1.GTPE2.ALIGN_COMMA_ENABLE[9] 29_500 -GTP_CHANNEL_1.GTPE2.ALIGN_COMMA_WORD[0] 29_526 -GTP_CHANNEL_1.GTPE2.ALIGN_COMMA_WORD[1] 28_527 -GTP_CHANNEL_1.GTPE2.ALIGN_MCOMMA_DET 28_523 -GTP_CHANNEL_1.GTPE2.ALIGN_MCOMMA_VALUE[0] 28_504 -GTP_CHANNEL_1.GTPE2.ALIGN_MCOMMA_VALUE[1] 29_504 -GTP_CHANNEL_1.GTPE2.ALIGN_MCOMMA_VALUE[2] 28_505 -GTP_CHANNEL_1.GTPE2.ALIGN_MCOMMA_VALUE[3] 29_505 -GTP_CHANNEL_1.GTPE2.ALIGN_MCOMMA_VALUE[4] 28_506 -GTP_CHANNEL_1.GTPE2.ALIGN_MCOMMA_VALUE[5] 29_506 -GTP_CHANNEL_1.GTPE2.ALIGN_MCOMMA_VALUE[6] 28_507 -GTP_CHANNEL_1.GTPE2.ALIGN_MCOMMA_VALUE[7] 29_507 -GTP_CHANNEL_1.GTPE2.ALIGN_MCOMMA_VALUE[8] 28_508 -GTP_CHANNEL_1.GTPE2.ALIGN_MCOMMA_VALUE[9] 29_508 -GTP_CHANNEL_1.GTPE2.ALIGN_PCOMMA_DET 29_523 -GTP_CHANNEL_1.GTPE2.ALIGN_PCOMMA_VALUE[0] 28_512 -GTP_CHANNEL_1.GTPE2.ALIGN_PCOMMA_VALUE[1] 29_512 -GTP_CHANNEL_1.GTPE2.ALIGN_PCOMMA_VALUE[2] 28_513 -GTP_CHANNEL_1.GTPE2.ALIGN_PCOMMA_VALUE[3] 29_513 -GTP_CHANNEL_1.GTPE2.ALIGN_PCOMMA_VALUE[4] 28_514 -GTP_CHANNEL_1.GTPE2.ALIGN_PCOMMA_VALUE[5] 29_514 -GTP_CHANNEL_1.GTPE2.ALIGN_PCOMMA_VALUE[6] 28_515 -GTP_CHANNEL_1.GTPE2.ALIGN_PCOMMA_VALUE[7] 29_515 -GTP_CHANNEL_1.GTPE2.ALIGN_PCOMMA_VALUE[8] 28_516 -GTP_CHANNEL_1.GTPE2.ALIGN_PCOMMA_VALUE[9] 29_516 -GTP_CHANNEL_1.GTPE2.CBCC_DATA_SOURCE_SEL.DECODED 29_661 -GTP_CHANNEL_1.GTPE2.CFOK_CFG[0] 30_392 -GTP_CHANNEL_1.GTPE2.CFOK_CFG[1] 31_392 -GTP_CHANNEL_1.GTPE2.CFOK_CFG[2] 30_393 -GTP_CHANNEL_1.GTPE2.CFOK_CFG[3] 31_393 -GTP_CHANNEL_1.GTPE2.CFOK_CFG[4] 30_394 -GTP_CHANNEL_1.GTPE2.CFOK_CFG[5] 31_394 -GTP_CHANNEL_1.GTPE2.CFOK_CFG[6] 30_395 -GTP_CHANNEL_1.GTPE2.CFOK_CFG[7] 31_395 -GTP_CHANNEL_1.GTPE2.CFOK_CFG[8] 30_396 -GTP_CHANNEL_1.GTPE2.CFOK_CFG[9] 31_396 -GTP_CHANNEL_1.GTPE2.CFOK_CFG[10] 30_397 -GTP_CHANNEL_1.GTPE2.CFOK_CFG[11] 31_397 -GTP_CHANNEL_1.GTPE2.CFOK_CFG[12] 30_398 -GTP_CHANNEL_1.GTPE2.CFOK_CFG[13] 31_398 -GTP_CHANNEL_1.GTPE2.CFOK_CFG[14] 30_399 -GTP_CHANNEL_1.GTPE2.CFOK_CFG[15] 31_399 -GTP_CHANNEL_1.GTPE2.CFOK_CFG[16] 30_400 -GTP_CHANNEL_1.GTPE2.CFOK_CFG[17] 31_400 -GTP_CHANNEL_1.GTPE2.CFOK_CFG[18] 30_401 -GTP_CHANNEL_1.GTPE2.CFOK_CFG[19] 31_401 -GTP_CHANNEL_1.GTPE2.CFOK_CFG[20] 30_402 -GTP_CHANNEL_1.GTPE2.CFOK_CFG[21] 31_402 -GTP_CHANNEL_1.GTPE2.CFOK_CFG[22] 30_403 -GTP_CHANNEL_1.GTPE2.CFOK_CFG[23] 31_403 -GTP_CHANNEL_1.GTPE2.CFOK_CFG[24] 30_404 -GTP_CHANNEL_1.GTPE2.CFOK_CFG[25] 31_404 -GTP_CHANNEL_1.GTPE2.CFOK_CFG[26] 30_405 -GTP_CHANNEL_1.GTPE2.CFOK_CFG[27] 31_405 -GTP_CHANNEL_1.GTPE2.CFOK_CFG[28] 30_406 -GTP_CHANNEL_1.GTPE2.CFOK_CFG[29] 31_406 -GTP_CHANNEL_1.GTPE2.CFOK_CFG[30] 30_407 -GTP_CHANNEL_1.GTPE2.CFOK_CFG[31] 31_407 -GTP_CHANNEL_1.GTPE2.CFOK_CFG[32] 30_408 -GTP_CHANNEL_1.GTPE2.CFOK_CFG[33] 31_408 -GTP_CHANNEL_1.GTPE2.CFOK_CFG[34] 30_409 -GTP_CHANNEL_1.GTPE2.CFOK_CFG[35] 31_409 -GTP_CHANNEL_1.GTPE2.CFOK_CFG[36] 30_410 -GTP_CHANNEL_1.GTPE2.CFOK_CFG[37] 31_410 -GTP_CHANNEL_1.GTPE2.CFOK_CFG[38] 30_411 -GTP_CHANNEL_1.GTPE2.CFOK_CFG[39] 31_411 -GTP_CHANNEL_1.GTPE2.CFOK_CFG[40] 30_412 -GTP_CHANNEL_1.GTPE2.CFOK_CFG[41] 31_412 -GTP_CHANNEL_1.GTPE2.CFOK_CFG[42] 30_413 -GTP_CHANNEL_1.GTPE2.CFOK_CFG2[0] 30_459 -GTP_CHANNEL_1.GTPE2.CFOK_CFG2[1] 31_459 -GTP_CHANNEL_1.GTPE2.CFOK_CFG2[2] 30_460 -GTP_CHANNEL_1.GTPE2.CFOK_CFG2[3] 31_460 -GTP_CHANNEL_1.GTPE2.CFOK_CFG2[4] 30_461 -GTP_CHANNEL_1.GTPE2.CFOK_CFG2[5] 31_461 -GTP_CHANNEL_1.GTPE2.CFOK_CFG2[6] 30_462 -GTP_CHANNEL_1.GTPE2.CFOK_CFG3[0] 30_416 -GTP_CHANNEL_1.GTPE2.CFOK_CFG3[1] 31_416 -GTP_CHANNEL_1.GTPE2.CFOK_CFG3[2] 30_417 -GTP_CHANNEL_1.GTPE2.CFOK_CFG3[3] 31_417 -GTP_CHANNEL_1.GTPE2.CFOK_CFG3[4] 30_418 -GTP_CHANNEL_1.GTPE2.CFOK_CFG3[5] 31_418 -GTP_CHANNEL_1.GTPE2.CFOK_CFG3[6] 30_419 -GTP_CHANNEL_1.GTPE2.CFOK_CFG4[0] 31_438 -GTP_CHANNEL_1.GTPE2.CFOK_CFG5[0] 30_429 -GTP_CHANNEL_1.GTPE2.CFOK_CFG5[1] 31_429 -GTP_CHANNEL_1.GTPE2.CFOK_CFG6[0] 31_436 -GTP_CHANNEL_1.GTPE2.CFOK_CFG6[1] 30_437 -GTP_CHANNEL_1.GTPE2.CFOK_CFG6[2] 31_437 -GTP_CHANNEL_1.GTPE2.CFOK_CFG6[3] 30_438 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_KEEP_ALIGN 29_631 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_MAX_SKEW[0] 28_670 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_MAX_SKEW[1] 29_670 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_MAX_SKEW[2] 28_671 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_MAX_SKEW[3] 29_671 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_1_1[0] 28_608 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_1_1[1] 29_608 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_1_1[2] 28_609 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_1_1[3] 29_609 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_1_1[4] 28_610 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_1_1[5] 29_610 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_1_1[6] 28_611 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_1_1[7] 29_611 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_1_1[8] 28_612 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_1_1[9] 29_612 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_1_2[0] 28_616 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_1_2[1] 29_616 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_1_2[2] 28_617 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_1_2[3] 29_617 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_1_2[4] 28_618 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_1_2[5] 29_618 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_1_2[6] 28_619 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_1_2[7] 29_619 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_1_2[8] 28_620 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_1_2[9] 29_620 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_1_3[0] 28_624 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_1_3[1] 29_624 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_1_3[2] 28_625 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_1_3[3] 29_625 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_1_3[4] 28_626 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_1_3[5] 29_626 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_1_3[6] 28_627 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_1_3[7] 29_627 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_1_3[8] 28_628 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_1_3[9] 29_628 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_1_4[0] 28_632 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_1_4[1] 29_632 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_1_4[2] 28_633 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_1_4[3] 29_633 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_1_4[4] 28_634 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_1_4[5] 29_634 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_1_4[6] 28_635 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_1_4[7] 29_635 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_1_4[8] 28_636 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_1_4[9] 29_636 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_1_ENABLE[0] 28_614 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_1_ENABLE[1] 29_614 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_1_ENABLE[2] 28_615 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_1_ENABLE[3] 29_615 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_2_1[0] 28_640 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_2_1[1] 29_640 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_2_1[2] 28_641 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_2_1[3] 29_641 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_2_1[4] 28_642 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_2_1[5] 29_642 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_2_1[6] 28_643 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_2_1[7] 29_643 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_2_1[8] 28_644 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_2_1[9] 29_644 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_2_2[0] 28_648 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_2_2[1] 29_648 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_2_2[2] 28_649 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_2_2[3] 29_649 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_2_2[4] 28_650 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_2_2[5] 29_650 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_2_2[6] 28_651 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_2_2[7] 29_651 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_2_2[8] 28_652 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_2_2[9] 29_652 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_2_3[0] 28_656 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_2_3[1] 29_656 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_2_3[2] 28_657 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_2_3[3] 29_657 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_2_3[4] 28_658 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_2_3[5] 29_658 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_2_3[6] 28_659 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_2_3[7] 29_659 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_2_3[8] 28_660 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_2_3[9] 29_660 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_2_4[0] 28_664 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_2_4[1] 29_664 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_2_4[2] 28_665 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_2_4[3] 29_665 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_2_4[4] 28_666 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_2_4[5] 29_666 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_2_4[6] 28_667 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_2_4[7] 29_667 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_2_4[8] 28_668 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_2_4[9] 29_668 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_2_ENABLE[0] 28_646 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_2_ENABLE[1] 29_646 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_2_ENABLE[2] 28_647 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_2_ENABLE[3] 29_647 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_2_USE 29_645 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_LEN[0] 28_623 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_LEN[1] 29_623 -GTP_CHANNEL_1.GTPE2.CLK_COMMON_SWING[0] 31_311 -GTP_CHANNEL_1.GTPE2.CLK_COR_KEEP_IDLE 28_591 -GTP_CHANNEL_1.GTPE2.CLK_COR_MAX_LAT[0] 28_557 -GTP_CHANNEL_1.GTPE2.CLK_COR_MAX_LAT[1] 29_557 -GTP_CHANNEL_1.GTPE2.CLK_COR_MAX_LAT[2] 28_558 -GTP_CHANNEL_1.GTPE2.CLK_COR_MAX_LAT[3] 29_558 -GTP_CHANNEL_1.GTPE2.CLK_COR_MAX_LAT[4] 28_559 -GTP_CHANNEL_1.GTPE2.CLK_COR_MAX_LAT[5] 29_559 -GTP_CHANNEL_1.GTPE2.CLK_COR_MIN_LAT[0] 28_565 -GTP_CHANNEL_1.GTPE2.CLK_COR_MIN_LAT[1] 29_565 -GTP_CHANNEL_1.GTPE2.CLK_COR_MIN_LAT[2] 28_566 -GTP_CHANNEL_1.GTPE2.CLK_COR_MIN_LAT[3] 29_566 -GTP_CHANNEL_1.GTPE2.CLK_COR_MIN_LAT[4] 28_567 -GTP_CHANNEL_1.GTPE2.CLK_COR_MIN_LAT[5] 29_567 -GTP_CHANNEL_1.GTPE2.CLK_COR_PRECEDENCE 28_590 -GTP_CHANNEL_1.GTPE2.CLK_COR_REPEAT_WAIT[0] 28_573 -GTP_CHANNEL_1.GTPE2.CLK_COR_REPEAT_WAIT[1] 29_573 -GTP_CHANNEL_1.GTPE2.CLK_COR_REPEAT_WAIT[2] 28_574 -GTP_CHANNEL_1.GTPE2.CLK_COR_REPEAT_WAIT[3] 29_574 -GTP_CHANNEL_1.GTPE2.CLK_COR_REPEAT_WAIT[4] 28_575 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_1_1[0] 28_544 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_1_1[1] 29_544 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_1_1[2] 28_545 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_1_1[3] 29_545 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_1_1[4] 28_546 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_1_1[5] 29_546 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_1_1[6] 28_547 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_1_1[7] 29_547 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_1_1[8] 28_548 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_1_1[9] 29_548 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_1_2[0] 28_552 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_1_2[1] 29_552 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_1_2[2] 28_553 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_1_2[3] 29_553 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_1_2[4] 28_554 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_1_2[5] 29_554 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_1_2[6] 28_555 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_1_2[7] 29_555 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_1_2[8] 28_556 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_1_2[9] 29_556 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_1_3[0] 28_560 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_1_3[1] 29_560 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_1_3[2] 28_561 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_1_3[3] 29_561 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_1_3[4] 28_562 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_1_3[5] 29_562 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_1_3[6] 28_563 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_1_3[7] 29_563 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_1_3[8] 28_564 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_1_3[9] 29_564 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_1_4[0] 28_568 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_1_4[1] 29_568 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_1_4[2] 28_569 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_1_4[3] 29_569 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_1_4[4] 28_570 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_1_4[5] 29_570 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_1_4[6] 28_571 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_1_4[7] 29_571 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_1_4[8] 28_572 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_1_4[9] 29_572 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_1_ENABLE[0] 28_549 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_1_ENABLE[1] 29_549 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_1_ENABLE[2] 28_550 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_1_ENABLE[3] 29_550 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_2_1[0] 28_576 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_2_1[1] 29_576 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_2_1[2] 28_577 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_2_1[3] 29_577 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_2_1[4] 28_578 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_2_1[5] 29_578 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_2_1[6] 28_579 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_2_1[7] 29_579 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_2_1[8] 28_580 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_2_1[9] 29_580 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_2_2[0] 28_584 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_2_2[1] 29_584 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_2_2[2] 28_585 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_2_2[3] 29_585 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_2_2[4] 28_586 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_2_2[5] 29_586 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_2_2[6] 28_587 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_2_2[7] 29_587 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_2_2[8] 28_588 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_2_2[9] 29_588 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_2_3[0] 28_592 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_2_3[1] 29_592 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_2_3[2] 28_593 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_2_3[3] 29_593 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_2_3[4] 28_594 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_2_3[5] 29_594 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_2_3[6] 28_595 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_2_3[7] 29_595 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_2_3[8] 28_596 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_2_3[9] 29_596 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_2_4[0] 28_600 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_2_4[1] 29_600 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_2_4[2] 28_601 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_2_4[3] 29_601 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_2_4[4] 28_602 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_2_4[5] 29_602 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_2_4[6] 28_603 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_2_4[7] 29_603 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_2_4[8] 28_604 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_2_4[9] 29_604 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_2_ENABLE[0] 28_581 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_2_ENABLE[1] 29_581 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_2_ENABLE[2] 28_582 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_2_ENABLE[3] 29_582 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_2_USE 28_583 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_LEN[0] 28_589 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_LEN[1] 29_589 -GTP_CHANNEL_1.GTPE2.CLK_CORRECT_USE 28_551 -GTP_CHANNEL_1.GTPE2.DEC_MCOMMA_DETECT 29_494 -GTP_CHANNEL_1.GTPE2.DEC_PCOMMA_DETECT 28_495 -GTP_CHANNEL_1.GTPE2.DEC_VALID_COMMA_ONLY 28_494 -GTP_CHANNEL_1.GTPE2.DMONITOR_CFG[0] 30_368 -GTP_CHANNEL_1.GTPE2.DMONITOR_CFG[1] 31_368 -GTP_CHANNEL_1.GTPE2.DMONITOR_CFG[2] 30_369 -GTP_CHANNEL_1.GTPE2.DMONITOR_CFG[3] 31_369 -GTP_CHANNEL_1.GTPE2.DMONITOR_CFG[4] 30_370 -GTP_CHANNEL_1.GTPE2.DMONITOR_CFG[5] 31_370 -GTP_CHANNEL_1.GTPE2.DMONITOR_CFG[6] 30_371 -GTP_CHANNEL_1.GTPE2.DMONITOR_CFG[7] 31_371 -GTP_CHANNEL_1.GTPE2.DMONITOR_CFG[8] 30_372 -GTP_CHANNEL_1.GTPE2.DMONITOR_CFG[9] 31_372 -GTP_CHANNEL_1.GTPE2.DMONITOR_CFG[10] 30_373 -GTP_CHANNEL_1.GTPE2.DMONITOR_CFG[11] 31_373 -GTP_CHANNEL_1.GTPE2.DMONITOR_CFG[12] 30_374 -GTP_CHANNEL_1.GTPE2.DMONITOR_CFG[13] 31_374 -GTP_CHANNEL_1.GTPE2.DMONITOR_CFG[14] 30_375 -GTP_CHANNEL_1.GTPE2.DMONITOR_CFG[15] 31_375 -GTP_CHANNEL_1.GTPE2.DMONITOR_CFG[16] 30_376 -GTP_CHANNEL_1.GTPE2.DMONITOR_CFG[17] 31_376 -GTP_CHANNEL_1.GTPE2.DMONITOR_CFG[18] 30_377 -GTP_CHANNEL_1.GTPE2.DMONITOR_CFG[19] 31_377 -GTP_CHANNEL_1.GTPE2.DMONITOR_CFG[20] 30_378 -GTP_CHANNEL_1.GTPE2.DMONITOR_CFG[21] 31_378 -GTP_CHANNEL_1.GTPE2.DMONITOR_CFG[22] 30_379 -GTP_CHANNEL_1.GTPE2.DMONITOR_CFG[23] 31_379 -GTP_CHANNEL_1.GTPE2.ES_CLK_PHASE_SEL[0] 31_463 -GTP_CHANNEL_1.GTPE2.ES_CONTROL[0] 28_488 -GTP_CHANNEL_1.GTPE2.ES_CONTROL[1] 29_488 -GTP_CHANNEL_1.GTPE2.ES_CONTROL[2] 28_489 -GTP_CHANNEL_1.GTPE2.ES_CONTROL[3] 29_489 -GTP_CHANNEL_1.GTPE2.ES_CONTROL[4] 28_490 -GTP_CHANNEL_1.GTPE2.ES_CONTROL[5] 29_490 -GTP_CHANNEL_1.GTPE2.ES_ERRDET_EN 29_492 -GTP_CHANNEL_1.GTPE2.ES_EYE_SCAN_EN 28_492 -GTP_CHANNEL_1.GTPE2.ES_HORZ_OFFSET[0] 28_480 -GTP_CHANNEL_1.GTPE2.ES_HORZ_OFFSET[1] 29_480 -GTP_CHANNEL_1.GTPE2.ES_HORZ_OFFSET[2] 28_481 -GTP_CHANNEL_1.GTPE2.ES_HORZ_OFFSET[3] 29_481 -GTP_CHANNEL_1.GTPE2.ES_HORZ_OFFSET[4] 28_482 -GTP_CHANNEL_1.GTPE2.ES_HORZ_OFFSET[5] 29_482 -GTP_CHANNEL_1.GTPE2.ES_HORZ_OFFSET[6] 28_483 -GTP_CHANNEL_1.GTPE2.ES_HORZ_OFFSET[7] 29_483 -GTP_CHANNEL_1.GTPE2.ES_HORZ_OFFSET[8] 28_484 -GTP_CHANNEL_1.GTPE2.ES_HORZ_OFFSET[9] 29_484 -GTP_CHANNEL_1.GTPE2.ES_HORZ_OFFSET[10] 28_485 -GTP_CHANNEL_1.GTPE2.ES_HORZ_OFFSET[11] 29_485 -GTP_CHANNEL_1.GTPE2.ES_PMA_CFG[0] 30_624 -GTP_CHANNEL_1.GTPE2.ES_PMA_CFG[1] 31_624 -GTP_CHANNEL_1.GTPE2.ES_PMA_CFG[2] 30_625 -GTP_CHANNEL_1.GTPE2.ES_PMA_CFG[3] 31_625 -GTP_CHANNEL_1.GTPE2.ES_PMA_CFG[4] 30_626 -GTP_CHANNEL_1.GTPE2.ES_PMA_CFG[5] 31_626 -GTP_CHANNEL_1.GTPE2.ES_PMA_CFG[6] 30_627 -GTP_CHANNEL_1.GTPE2.ES_PMA_CFG[7] 31_627 -GTP_CHANNEL_1.GTPE2.ES_PMA_CFG[8] 30_628 -GTP_CHANNEL_1.GTPE2.ES_PMA_CFG[9] 31_628 -GTP_CHANNEL_1.GTPE2.ES_PRESCALE[0] 29_477 -GTP_CHANNEL_1.GTPE2.ES_PRESCALE[1] 28_478 -GTP_CHANNEL_1.GTPE2.ES_PRESCALE[2] 29_478 -GTP_CHANNEL_1.GTPE2.ES_PRESCALE[3] 28_479 -GTP_CHANNEL_1.GTPE2.ES_PRESCALE[4] 29_479 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[0] 28_392 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[1] 29_392 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[2] 28_393 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[3] 29_393 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[4] 28_394 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[5] 29_394 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[6] 28_395 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[7] 29_395 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[8] 28_396 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[9] 29_396 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[10] 28_397 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[11] 29_397 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[12] 28_398 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[13] 29_398 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[14] 28_399 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[15] 29_399 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[16] 28_400 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[17] 29_400 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[18] 28_401 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[19] 29_401 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[20] 28_402 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[21] 29_402 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[22] 28_403 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[23] 29_403 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[24] 28_404 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[25] 29_404 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[26] 28_405 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[27] 29_405 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[28] 28_406 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[29] 29_406 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[30] 28_407 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[31] 29_407 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[32] 28_408 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[33] 29_408 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[34] 28_409 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[35] 29_409 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[36] 28_410 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[37] 29_410 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[38] 28_411 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[39] 29_411 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[40] 28_412 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[41] 29_412 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[42] 28_413 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[43] 29_413 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[44] 28_414 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[45] 29_414 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[46] 28_415 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[47] 29_415 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[48] 28_416 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[49] 29_416 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[50] 28_417 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[51] 29_417 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[52] 28_418 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[53] 29_418 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[54] 28_419 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[55] 29_419 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[56] 28_420 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[57] 29_420 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[58] 28_421 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[59] 29_421 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[60] 28_422 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[61] 29_422 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[62] 28_423 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[63] 29_423 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[64] 28_424 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[65] 29_424 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[66] 28_425 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[67] 29_425 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[68] 28_426 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[69] 29_426 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[70] 28_427 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[71] 29_427 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[72] 28_428 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[73] 29_428 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[74] 28_429 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[75] 29_429 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[76] 28_430 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[77] 29_430 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[78] 28_431 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[79] 29_431 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[0] 28_352 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[1] 29_352 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[2] 28_353 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[3] 29_353 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[4] 28_354 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[5] 29_354 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[6] 28_355 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[7] 29_355 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[8] 28_356 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[9] 29_356 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[10] 28_357 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[11] 29_357 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[12] 28_358 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[13] 29_358 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[14] 28_359 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[15] 29_359 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[16] 28_360 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[17] 29_360 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[18] 28_361 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[19] 29_361 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[20] 28_362 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[21] 29_362 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[22] 28_363 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[23] 29_363 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[24] 28_364 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[25] 29_364 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[26] 28_365 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[27] 29_365 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[28] 28_366 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[29] 29_366 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[30] 28_367 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[31] 29_367 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[32] 28_368 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[33] 29_368 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[34] 28_369 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[35] 29_369 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[36] 28_370 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[37] 29_370 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[38] 28_371 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[39] 29_371 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[40] 28_372 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[41] 29_372 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[42] 28_373 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[43] 29_373 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[44] 28_374 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[45] 29_374 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[46] 28_375 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[47] 29_375 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[48] 28_376 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[49] 29_376 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[50] 28_377 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[51] 29_377 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[52] 28_378 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[53] 29_378 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[54] 28_379 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[55] 29_379 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[56] 28_380 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[57] 29_380 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[58] 28_381 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[59] 29_381 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[60] 28_382 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[61] 29_382 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[62] 28_383 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[63] 29_383 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[64] 28_384 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[65] 29_384 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[66] 28_385 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[67] 29_385 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[68] 28_386 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[69] 29_386 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[70] 28_387 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[71] 29_387 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[72] 28_388 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[73] 29_388 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[74] 28_389 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[75] 29_389 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[76] 28_390 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[77] 29_390 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[78] 28_391 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[79] 29_391 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[0] 28_432 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[1] 29_432 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[2] 28_433 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[3] 29_433 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[4] 28_434 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[5] 29_434 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[6] 28_435 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[7] 29_435 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[8] 28_436 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[9] 29_436 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[10] 28_437 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[11] 29_437 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[12] 28_438 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[13] 29_438 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[14] 28_439 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[15] 29_439 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[16] 28_440 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[17] 29_440 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[18] 28_441 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[19] 29_441 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[20] 28_442 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[21] 29_442 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[22] 28_443 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[23] 29_443 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[24] 28_444 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[25] 29_444 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[26] 28_445 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[27] 29_445 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[28] 28_446 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[29] 29_446 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[30] 28_447 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[31] 29_447 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[32] 28_448 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[33] 29_448 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[34] 28_449 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[35] 29_449 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[36] 28_450 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[37] 29_450 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[38] 28_451 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[39] 29_451 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[40] 28_452 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[41] 29_452 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[42] 28_453 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[43] 29_453 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[44] 28_454 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[45] 29_454 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[46] 28_455 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[47] 29_455 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[48] 28_456 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[49] 29_456 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[50] 28_457 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[51] 29_457 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[52] 28_458 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[53] 29_458 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[54] 28_459 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[55] 29_459 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[56] 28_460 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[57] 29_460 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[58] 28_461 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[59] 29_461 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[60] 28_462 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[61] 29_462 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[62] 28_463 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[63] 29_463 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[64] 28_464 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[65] 29_464 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[66] 28_465 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[67] 29_465 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[68] 28_466 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[69] 29_466 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[70] 28_467 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[71] 29_467 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[72] 28_468 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[73] 29_468 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[74] 28_469 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[75] 29_469 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[76] 28_470 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[77] 29_470 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[78] 28_471 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[79] 29_471 -GTP_CHANNEL_1.GTPE2.ES_VERT_OFFSET[0] 28_472 -GTP_CHANNEL_1.GTPE2.ES_VERT_OFFSET[1] 29_472 -GTP_CHANNEL_1.GTPE2.ES_VERT_OFFSET[2] 28_473 -GTP_CHANNEL_1.GTPE2.ES_VERT_OFFSET[3] 29_473 -GTP_CHANNEL_1.GTPE2.ES_VERT_OFFSET[4] 28_474 -GTP_CHANNEL_1.GTPE2.ES_VERT_OFFSET[5] 29_474 -GTP_CHANNEL_1.GTPE2.ES_VERT_OFFSET[6] 28_475 -GTP_CHANNEL_1.GTPE2.ES_VERT_OFFSET[7] 29_475 -GTP_CHANNEL_1.GTPE2.ES_VERT_OFFSET[8] 28_476 -GTP_CHANNEL_1.GTPE2.FTS_DESKEW_SEQ_ENABLE[0] 28_662 -GTP_CHANNEL_1.GTPE2.FTS_DESKEW_SEQ_ENABLE[1] 29_662 -GTP_CHANNEL_1.GTPE2.FTS_DESKEW_SEQ_ENABLE[2] 28_663 -GTP_CHANNEL_1.GTPE2.FTS_DESKEW_SEQ_ENABLE[3] 29_663 -GTP_CHANNEL_1.GTPE2.FTS_LANE_DESKEW_CFG[0] 28_654 -GTP_CHANNEL_1.GTPE2.FTS_LANE_DESKEW_CFG[1] 29_654 -GTP_CHANNEL_1.GTPE2.FTS_LANE_DESKEW_CFG[2] 28_655 -GTP_CHANNEL_1.GTPE2.FTS_LANE_DESKEW_CFG[3] 29_655 -GTP_CHANNEL_1.GTPE2.FTS_LANE_DESKEW_EN 29_653 -GTP_CHANNEL_1.GTPE2.GEARBOX_MODE[0] 28_224 -GTP_CHANNEL_1.GTPE2.GEARBOX_MODE[1] 29_224 -GTP_CHANNEL_1.GTPE2.GEARBOX_MODE[2] 28_225 -GTP_CHANNEL_1.GTPE2.IN_USE 28_00 28_01 28_47 28_52 28_53 28_65 29_01 29_47 30_129 -GTP_CHANNEL_1.GTPE2.LOOPBACK_CFG[0] 30_20 -GTP_CHANNEL_1.GTPE2.OUTREFCLK_SEL_INV[0] 28_149 -GTP_CHANNEL_1.GTPE2.OUTREFCLK_SEL_INV[1] 29_149 -GTP_CHANNEL_1.GTPE2.PCS_PCIE_EN 28_216 -GTP_CHANNEL_1.GTPE2.PCS_RSVD_ATTR[0] 30_184 -GTP_CHANNEL_1.GTPE2.PCS_RSVD_ATTR[1] 31_184 -GTP_CHANNEL_1.GTPE2.PCS_RSVD_ATTR[2] 30_185 -GTP_CHANNEL_1.GTPE2.PCS_RSVD_ATTR[3] 31_185 -GTP_CHANNEL_1.GTPE2.PCS_RSVD_ATTR[4] 30_186 -GTP_CHANNEL_1.GTPE2.PCS_RSVD_ATTR[5] 31_186 -GTP_CHANNEL_1.GTPE2.PCS_RSVD_ATTR[6] 30_187 -GTP_CHANNEL_1.GTPE2.PCS_RSVD_ATTR[7] 31_187 -GTP_CHANNEL_1.GTPE2.PCS_RSVD_ATTR[8] 30_188 -GTP_CHANNEL_1.GTPE2.PCS_RSVD_ATTR[9] 31_188 -GTP_CHANNEL_1.GTPE2.PCS_RSVD_ATTR[10] 30_189 -GTP_CHANNEL_1.GTPE2.PCS_RSVD_ATTR[11] 31_189 -GTP_CHANNEL_1.GTPE2.PCS_RSVD_ATTR[12] 30_190 -GTP_CHANNEL_1.GTPE2.PCS_RSVD_ATTR[13] 31_190 -GTP_CHANNEL_1.GTPE2.PCS_RSVD_ATTR[14] 30_191 -GTP_CHANNEL_1.GTPE2.PCS_RSVD_ATTR[15] 31_191 -GTP_CHANNEL_1.GTPE2.PCS_RSVD_ATTR[16] 30_192 -GTP_CHANNEL_1.GTPE2.PCS_RSVD_ATTR[17] 31_192 -GTP_CHANNEL_1.GTPE2.PCS_RSVD_ATTR[18] 30_193 -GTP_CHANNEL_1.GTPE2.PCS_RSVD_ATTR[19] 31_193 -GTP_CHANNEL_1.GTPE2.PCS_RSVD_ATTR[20] 30_194 -GTP_CHANNEL_1.GTPE2.PCS_RSVD_ATTR[21] 31_194 -GTP_CHANNEL_1.GTPE2.PCS_RSVD_ATTR[22] 30_195 -GTP_CHANNEL_1.GTPE2.PCS_RSVD_ATTR[23] 31_195 -GTP_CHANNEL_1.GTPE2.PCS_RSVD_ATTR[24] 30_196 -GTP_CHANNEL_1.GTPE2.PCS_RSVD_ATTR[25] 31_196 -GTP_CHANNEL_1.GTPE2.PCS_RSVD_ATTR[26] 30_197 -GTP_CHANNEL_1.GTPE2.PCS_RSVD_ATTR[27] 31_197 -GTP_CHANNEL_1.GTPE2.PCS_RSVD_ATTR[28] 30_198 -GTP_CHANNEL_1.GTPE2.PCS_RSVD_ATTR[29] 31_198 -GTP_CHANNEL_1.GTPE2.PCS_RSVD_ATTR[30] 30_199 -GTP_CHANNEL_1.GTPE2.PCS_RSVD_ATTR[31] 31_199 -GTP_CHANNEL_1.GTPE2.PCS_RSVD_ATTR[32] 30_200 -GTP_CHANNEL_1.GTPE2.PCS_RSVD_ATTR[33] 31_200 -GTP_CHANNEL_1.GTPE2.PCS_RSVD_ATTR[34] 30_201 -GTP_CHANNEL_1.GTPE2.PCS_RSVD_ATTR[35] 31_201 -GTP_CHANNEL_1.GTPE2.PCS_RSVD_ATTR[36] 30_202 -GTP_CHANNEL_1.GTPE2.PCS_RSVD_ATTR[37] 31_202 -GTP_CHANNEL_1.GTPE2.PCS_RSVD_ATTR[38] 30_203 -GTP_CHANNEL_1.GTPE2.PCS_RSVD_ATTR[39] 31_203 -GTP_CHANNEL_1.GTPE2.PCS_RSVD_ATTR[40] 30_204 -GTP_CHANNEL_1.GTPE2.PCS_RSVD_ATTR[41] 31_204 -GTP_CHANNEL_1.GTPE2.PCS_RSVD_ATTR[42] 30_205 -GTP_CHANNEL_1.GTPE2.PCS_RSVD_ATTR[43] 31_205 -GTP_CHANNEL_1.GTPE2.PCS_RSVD_ATTR[44] 30_206 -GTP_CHANNEL_1.GTPE2.PCS_RSVD_ATTR[45] 31_206 -GTP_CHANNEL_1.GTPE2.PCS_RSVD_ATTR[46] 30_207 -GTP_CHANNEL_1.GTPE2.PCS_RSVD_ATTR[47] 31_207 -GTP_CHANNEL_1.GTPE2.PD_TRANS_TIME_FROM_P2[0] 29_216 -GTP_CHANNEL_1.GTPE2.PD_TRANS_TIME_FROM_P2[1] 28_217 -GTP_CHANNEL_1.GTPE2.PD_TRANS_TIME_FROM_P2[2] 29_217 -GTP_CHANNEL_1.GTPE2.PD_TRANS_TIME_FROM_P2[3] 28_218 -GTP_CHANNEL_1.GTPE2.PD_TRANS_TIME_FROM_P2[4] 29_218 -GTP_CHANNEL_1.GTPE2.PD_TRANS_TIME_FROM_P2[5] 28_219 -GTP_CHANNEL_1.GTPE2.PD_TRANS_TIME_FROM_P2[6] 29_219 -GTP_CHANNEL_1.GTPE2.PD_TRANS_TIME_FROM_P2[7] 28_220 -GTP_CHANNEL_1.GTPE2.PD_TRANS_TIME_FROM_P2[8] 29_220 -GTP_CHANNEL_1.GTPE2.PD_TRANS_TIME_FROM_P2[9] 28_221 -GTP_CHANNEL_1.GTPE2.PD_TRANS_TIME_FROM_P2[10] 29_221 -GTP_CHANNEL_1.GTPE2.PD_TRANS_TIME_FROM_P2[11] 28_222 -GTP_CHANNEL_1.GTPE2.PD_TRANS_TIME_NONE_P2[0] 28_208 -GTP_CHANNEL_1.GTPE2.PD_TRANS_TIME_NONE_P2[1] 29_208 -GTP_CHANNEL_1.GTPE2.PD_TRANS_TIME_NONE_P2[2] 28_209 -GTP_CHANNEL_1.GTPE2.PD_TRANS_TIME_NONE_P2[3] 29_209 -GTP_CHANNEL_1.GTPE2.PD_TRANS_TIME_NONE_P2[4] 28_210 -GTP_CHANNEL_1.GTPE2.PD_TRANS_TIME_NONE_P2[5] 29_210 -GTP_CHANNEL_1.GTPE2.PD_TRANS_TIME_NONE_P2[6] 28_211 -GTP_CHANNEL_1.GTPE2.PD_TRANS_TIME_NONE_P2[7] 29_211 -GTP_CHANNEL_1.GTPE2.PD_TRANS_TIME_TO_P2[0] 28_212 -GTP_CHANNEL_1.GTPE2.PD_TRANS_TIME_TO_P2[1] 29_212 -GTP_CHANNEL_1.GTPE2.PD_TRANS_TIME_TO_P2[2] 28_213 -GTP_CHANNEL_1.GTPE2.PD_TRANS_TIME_TO_P2[3] 29_213 -GTP_CHANNEL_1.GTPE2.PD_TRANS_TIME_TO_P2[4] 28_214 -GTP_CHANNEL_1.GTPE2.PD_TRANS_TIME_TO_P2[5] 29_214 -GTP_CHANNEL_1.GTPE2.PD_TRANS_TIME_TO_P2[6] 28_215 -GTP_CHANNEL_1.GTPE2.PD_TRANS_TIME_TO_P2[7] 29_215 -GTP_CHANNEL_1.GTPE2.PMA_LOOPBACK_CFG[0] 29_207 -GTP_CHANNEL_1.GTPE2.PMA_RSV[0] 30_520 -GTP_CHANNEL_1.GTPE2.PMA_RSV[1] 31_520 -GTP_CHANNEL_1.GTPE2.PMA_RSV[2] 30_521 -GTP_CHANNEL_1.GTPE2.PMA_RSV[3] 31_521 -GTP_CHANNEL_1.GTPE2.PMA_RSV[4] 30_522 -GTP_CHANNEL_1.GTPE2.PMA_RSV[5] 31_522 -GTP_CHANNEL_1.GTPE2.PMA_RSV[6] 30_523 -GTP_CHANNEL_1.GTPE2.PMA_RSV[7] 31_523 -GTP_CHANNEL_1.GTPE2.PMA_RSV[8] 30_524 -GTP_CHANNEL_1.GTPE2.PMA_RSV[9] 31_524 -GTP_CHANNEL_1.GTPE2.PMA_RSV[10] 30_525 -GTP_CHANNEL_1.GTPE2.PMA_RSV[11] 31_525 -GTP_CHANNEL_1.GTPE2.PMA_RSV[12] 30_526 -GTP_CHANNEL_1.GTPE2.PMA_RSV[13] 31_526 -GTP_CHANNEL_1.GTPE2.PMA_RSV[14] 30_527 -GTP_CHANNEL_1.GTPE2.PMA_RSV[15] 31_527 -GTP_CHANNEL_1.GTPE2.PMA_RSV[16] 30_528 -GTP_CHANNEL_1.GTPE2.PMA_RSV[17] 31_528 -GTP_CHANNEL_1.GTPE2.PMA_RSV[18] 30_529 -GTP_CHANNEL_1.GTPE2.PMA_RSV[19] 31_529 -GTP_CHANNEL_1.GTPE2.PMA_RSV[20] 30_530 -GTP_CHANNEL_1.GTPE2.PMA_RSV[21] 31_530 -GTP_CHANNEL_1.GTPE2.PMA_RSV[22] 30_531 -GTP_CHANNEL_1.GTPE2.PMA_RSV[23] 31_531 -GTP_CHANNEL_1.GTPE2.PMA_RSV[24] 30_532 -GTP_CHANNEL_1.GTPE2.PMA_RSV[25] 31_532 -GTP_CHANNEL_1.GTPE2.PMA_RSV[26] 30_533 -GTP_CHANNEL_1.GTPE2.PMA_RSV[27] 31_533 -GTP_CHANNEL_1.GTPE2.PMA_RSV[28] 30_534 -GTP_CHANNEL_1.GTPE2.PMA_RSV[29] 31_534 -GTP_CHANNEL_1.GTPE2.PMA_RSV[30] 30_535 -GTP_CHANNEL_1.GTPE2.PMA_RSV[31] 31_535 -GTP_CHANNEL_1.GTPE2.PMA_RSV2[0] 30_336 -GTP_CHANNEL_1.GTPE2.PMA_RSV2[1] 31_336 -GTP_CHANNEL_1.GTPE2.PMA_RSV2[2] 30_337 -GTP_CHANNEL_1.GTPE2.PMA_RSV2[3] 31_337 -GTP_CHANNEL_1.GTPE2.PMA_RSV2[4] 30_338 -GTP_CHANNEL_1.GTPE2.PMA_RSV2[5] 31_338 -GTP_CHANNEL_1.GTPE2.PMA_RSV2[6] 30_339 -GTP_CHANNEL_1.GTPE2.PMA_RSV2[7] 31_339 -GTP_CHANNEL_1.GTPE2.PMA_RSV2[8] 30_340 -GTP_CHANNEL_1.GTPE2.PMA_RSV2[9] 31_340 -GTP_CHANNEL_1.GTPE2.PMA_RSV2[10] 30_341 -GTP_CHANNEL_1.GTPE2.PMA_RSV2[11] 31_341 -GTP_CHANNEL_1.GTPE2.PMA_RSV2[12] 30_342 -GTP_CHANNEL_1.GTPE2.PMA_RSV2[13] 31_342 -GTP_CHANNEL_1.GTPE2.PMA_RSV2[14] 30_343 -GTP_CHANNEL_1.GTPE2.PMA_RSV2[15] 31_343 -GTP_CHANNEL_1.GTPE2.PMA_RSV2[16] 30_344 -GTP_CHANNEL_1.GTPE2.PMA_RSV2[17] 31_344 -GTP_CHANNEL_1.GTPE2.PMA_RSV2[18] 30_345 -GTP_CHANNEL_1.GTPE2.PMA_RSV2[19] 31_345 -GTP_CHANNEL_1.GTPE2.PMA_RSV2[20] 30_346 -GTP_CHANNEL_1.GTPE2.PMA_RSV2[21] 31_346 -GTP_CHANNEL_1.GTPE2.PMA_RSV2[22] 30_347 -GTP_CHANNEL_1.GTPE2.PMA_RSV2[23] 31_347 -GTP_CHANNEL_1.GTPE2.PMA_RSV2[24] 30_348 -GTP_CHANNEL_1.GTPE2.PMA_RSV2[25] 31_348 -GTP_CHANNEL_1.GTPE2.PMA_RSV2[26] 30_349 -GTP_CHANNEL_1.GTPE2.PMA_RSV2[27] 31_349 -GTP_CHANNEL_1.GTPE2.PMA_RSV2[28] 30_350 -GTP_CHANNEL_1.GTPE2.PMA_RSV2[29] 31_350 -GTP_CHANNEL_1.GTPE2.PMA_RSV2[30] 30_351 -GTP_CHANNEL_1.GTPE2.PMA_RSV2[31] 31_351 -GTP_CHANNEL_1.GTPE2.PMA_RSV3[0] 30_288 -GTP_CHANNEL_1.GTPE2.PMA_RSV3[1] 31_288 -GTP_CHANNEL_1.GTPE2.PMA_RSV4[0] 30_156 -GTP_CHANNEL_1.GTPE2.PMA_RSV4[1] 31_156 -GTP_CHANNEL_1.GTPE2.PMA_RSV4[2] 30_157 -GTP_CHANNEL_1.GTPE2.PMA_RSV4[3] 31_157 -GTP_CHANNEL_1.GTPE2.PMA_RSV5[0] 31_159 -GTP_CHANNEL_1.GTPE2.PMA_RSV6[0] 30_303 -GTP_CHANNEL_1.GTPE2.PMA_RSV7[0] 31_303 -GTP_CHANNEL_1.GTPE2.RX_BIAS_CFG[0] 30_112 -GTP_CHANNEL_1.GTPE2.RX_BIAS_CFG[1] 31_112 -GTP_CHANNEL_1.GTPE2.RX_BIAS_CFG[2] 30_113 -GTP_CHANNEL_1.GTPE2.RX_BIAS_CFG[3] 31_113 -GTP_CHANNEL_1.GTPE2.RX_BIAS_CFG[4] 30_114 -GTP_CHANNEL_1.GTPE2.RX_BIAS_CFG[5] 31_114 -GTP_CHANNEL_1.GTPE2.RX_BIAS_CFG[6] 30_115 -GTP_CHANNEL_1.GTPE2.RX_BIAS_CFG[7] 31_115 -GTP_CHANNEL_1.GTPE2.RX_BIAS_CFG[8] 30_116 -GTP_CHANNEL_1.GTPE2.RX_BIAS_CFG[9] 31_116 -GTP_CHANNEL_1.GTPE2.RX_BIAS_CFG[10] 30_117 -GTP_CHANNEL_1.GTPE2.RX_BIAS_CFG[11] 31_117 -GTP_CHANNEL_1.GTPE2.RX_BIAS_CFG[12] 30_118 -GTP_CHANNEL_1.GTPE2.RX_BIAS_CFG[13] 31_118 -GTP_CHANNEL_1.GTPE2.RX_BIAS_CFG[14] 30_119 -GTP_CHANNEL_1.GTPE2.RX_BIAS_CFG[15] 31_119 -GTP_CHANNEL_1.GTPE2.RX_BUFFER_CFG[0] 30_536 -GTP_CHANNEL_1.GTPE2.RX_BUFFER_CFG[1] 31_536 -GTP_CHANNEL_1.GTPE2.RX_BUFFER_CFG[2] 30_537 -GTP_CHANNEL_1.GTPE2.RX_BUFFER_CFG[3] 31_537 -GTP_CHANNEL_1.GTPE2.RX_BUFFER_CFG[4] 30_538 -GTP_CHANNEL_1.GTPE2.RX_BUFFER_CFG[5] 31_538 -GTP_CHANNEL_1.GTPE2.RX_CLKMUX_EN[0] 30_128 -GTP_CHANNEL_1.GTPE2.RX_CM_SEL[0] 28_138 -GTP_CHANNEL_1.GTPE2.RX_CM_SEL[1] 29_138 -GTP_CHANNEL_1.GTPE2.RX_CM_TRIM[0] 30_304 -GTP_CHANNEL_1.GTPE2.RX_CM_TRIM[1] 31_304 -GTP_CHANNEL_1.GTPE2.RX_CM_TRIM[2] 30_305 -GTP_CHANNEL_1.GTPE2.RX_CM_TRIM[3] 31_305 -GTP_CHANNEL_1.GTPE2.RX_DATA_WIDTH[0] 29_141 -GTP_CHANNEL_1.GTPE2.RX_DATA_WIDTH[1] 28_142 -GTP_CHANNEL_1.GTPE2.RX_DATA_WIDTH[2] 29_142 -GTP_CHANNEL_1.GTPE2.RX_DDI_SEL[0] 28_696 -GTP_CHANNEL_1.GTPE2.RX_DDI_SEL[1] 29_696 -GTP_CHANNEL_1.GTPE2.RX_DDI_SEL[2] 28_697 -GTP_CHANNEL_1.GTPE2.RX_DDI_SEL[3] 29_697 -GTP_CHANNEL_1.GTPE2.RX_DDI_SEL[4] 28_698 -GTP_CHANNEL_1.GTPE2.RX_DDI_SEL[5] 29_698 -GTP_CHANNEL_1.GTPE2.RX_DEBUG_CFG[0] 30_616 -GTP_CHANNEL_1.GTPE2.RX_DEBUG_CFG[1] 31_616 -GTP_CHANNEL_1.GTPE2.RX_DEBUG_CFG[2] 30_617 -GTP_CHANNEL_1.GTPE2.RX_DEBUG_CFG[3] 31_617 -GTP_CHANNEL_1.GTPE2.RX_DEBUG_CFG[4] 30_618 -GTP_CHANNEL_1.GTPE2.RX_DEBUG_CFG[5] 31_618 -GTP_CHANNEL_1.GTPE2.RX_DEBUG_CFG[6] 30_619 -GTP_CHANNEL_1.GTPE2.RX_DEBUG_CFG[7] 31_619 -GTP_CHANNEL_1.GTPE2.RX_DEBUG_CFG[8] 30_620 -GTP_CHANNEL_1.GTPE2.RX_DEBUG_CFG[9] 31_620 -GTP_CHANNEL_1.GTPE2.RX_DEBUG_CFG[10] 30_621 -GTP_CHANNEL_1.GTPE2.RX_DEBUG_CFG[11] 31_621 -GTP_CHANNEL_1.GTPE2.RX_DEBUG_CFG[12] 30_622 -GTP_CHANNEL_1.GTPE2.RX_DEBUG_CFG[13] 31_622 -GTP_CHANNEL_1.GTPE2.RX_DEFER_RESET_BUF_EN 30_552 -GTP_CHANNEL_1.GTPE2.RX_DISPERR_SEQ_MATCH 29_495 -GTP_CHANNEL_1.GTPE2.RX_OS_CFG[0] 28_288 -GTP_CHANNEL_1.GTPE2.RX_OS_CFG[1] 29_288 -GTP_CHANNEL_1.GTPE2.RX_OS_CFG[2] 28_289 -GTP_CHANNEL_1.GTPE2.RX_OS_CFG[3] 29_289 -GTP_CHANNEL_1.GTPE2.RX_OS_CFG[4] 28_290 -GTP_CHANNEL_1.GTPE2.RX_OS_CFG[5] 29_290 -GTP_CHANNEL_1.GTPE2.RX_OS_CFG[6] 28_291 -GTP_CHANNEL_1.GTPE2.RX_OS_CFG[7] 29_291 -GTP_CHANNEL_1.GTPE2.RX_OS_CFG[8] 28_292 -GTP_CHANNEL_1.GTPE2.RX_OS_CFG[9] 29_292 -GTP_CHANNEL_1.GTPE2.RX_OS_CFG[10] 28_293 -GTP_CHANNEL_1.GTPE2.RX_OS_CFG[11] 29_293 -GTP_CHANNEL_1.GTPE2.RX_OS_CFG[12] 28_294 -GTP_CHANNEL_1.GTPE2.RX_SIG_VALID_DLY[0] 28_524 -GTP_CHANNEL_1.GTPE2.RX_SIG_VALID_DLY[1] 29_524 -GTP_CHANNEL_1.GTPE2.RX_SIG_VALID_DLY[2] 28_525 -GTP_CHANNEL_1.GTPE2.RX_SIG_VALID_DLY[3] 29_525 -GTP_CHANNEL_1.GTPE2.RX_SIG_VALID_DLY[4] 28_526 -GTP_CHANNEL_1.GTPE2.RX_XCLK_SEL.RXUSR 28_143 -GTP_CHANNEL_1.GTPE2.RX_CLK25_DIV[0] 28_139 -GTP_CHANNEL_1.GTPE2.RX_CLK25_DIV[1] 29_139 -GTP_CHANNEL_1.GTPE2.RX_CLK25_DIV[2] 28_140 -GTP_CHANNEL_1.GTPE2.RX_CLK25_DIV[3] 29_140 -GTP_CHANNEL_1.GTPE2.RX_CLK25_DIV[4] 28_141 -GTP_CHANNEL_1.GTPE2.RXBUF_ADDR_MODE.FAST 31_555 -GTP_CHANNEL_1.GTPE2.RXBUF_EIDLE_HI_CNT[0] 30_558 -GTP_CHANNEL_1.GTPE2.RXBUF_EIDLE_HI_CNT[1] 31_558 -GTP_CHANNEL_1.GTPE2.RXBUF_EIDLE_HI_CNT[2] 30_559 -GTP_CHANNEL_1.GTPE2.RXBUF_EIDLE_HI_CNT[3] 31_559 -GTP_CHANNEL_1.GTPE2.RXBUF_EIDLE_LO_CNT[0] 30_556 -GTP_CHANNEL_1.GTPE2.RXBUF_EIDLE_LO_CNT[1] 31_556 -GTP_CHANNEL_1.GTPE2.RXBUF_EIDLE_LO_CNT[2] 30_557 -GTP_CHANNEL_1.GTPE2.RXBUF_EIDLE_LO_CNT[3] 31_557 -GTP_CHANNEL_1.GTPE2.RXBUF_EN 30_11 -GTP_CHANNEL_1.GTPE2.RXBUF_RESET_ON_CB_CHANGE 30_560 -GTP_CHANNEL_1.GTPE2.RXBUF_RESET_ON_COMMAALIGN 30_561 -GTP_CHANNEL_1.GTPE2.RXBUF_RESET_ON_EIDLE 30_547 -GTP_CHANNEL_1.GTPE2.RXBUF_RESET_ON_RATE_CHANGE 31_560 -GTP_CHANNEL_1.GTPE2.RXBUF_THRESH_OVFLW[0] 31_552 -GTP_CHANNEL_1.GTPE2.RXBUF_THRESH_OVFLW[1] 30_553 -GTP_CHANNEL_1.GTPE2.RXBUF_THRESH_OVFLW[2] 31_553 -GTP_CHANNEL_1.GTPE2.RXBUF_THRESH_OVFLW[3] 30_554 -GTP_CHANNEL_1.GTPE2.RXBUF_THRESH_OVFLW[4] 31_554 -GTP_CHANNEL_1.GTPE2.RXBUF_THRESH_OVFLW[5] 30_555 -GTP_CHANNEL_1.GTPE2.RXBUF_THRESH_OVRD 30_548 -GTP_CHANNEL_1.GTPE2.RXBUF_THRESH_UNDFLW[0] 30_544 -GTP_CHANNEL_1.GTPE2.RXBUF_THRESH_UNDFLW[1] 31_544 -GTP_CHANNEL_1.GTPE2.RXBUF_THRESH_UNDFLW[2] 30_545 -GTP_CHANNEL_1.GTPE2.RXBUF_THRESH_UNDFLW[3] 31_545 -GTP_CHANNEL_1.GTPE2.RXBUF_THRESH_UNDFLW[4] 30_546 -GTP_CHANNEL_1.GTPE2.RXBUF_THRESH_UNDFLW[5] 31_546 -GTP_CHANNEL_1.GTPE2.RXBUFRESET_TIME[0] 29_101 -GTP_CHANNEL_1.GTPE2.RXBUFRESET_TIME[1] 28_102 -GTP_CHANNEL_1.GTPE2.RXBUFRESET_TIME[2] 29_102 -GTP_CHANNEL_1.GTPE2.RXBUFRESET_TIME[3] 28_103 -GTP_CHANNEL_1.GTPE2.RXBUFRESET_TIME[4] 29_103 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[0] 30_640 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[1] 31_640 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[2] 30_641 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[3] 31_641 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[4] 30_642 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[5] 31_642 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[6] 30_643 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[7] 31_643 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[8] 30_644 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[9] 31_644 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[10] 30_645 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[11] 31_645 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[12] 30_646 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[13] 31_646 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[14] 30_647 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[15] 31_647 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[16] 30_648 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[17] 31_648 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[18] 30_649 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[19] 31_649 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[20] 30_650 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[21] 31_650 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[22] 30_651 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[23] 31_651 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[24] 30_652 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[25] 31_652 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[26] 30_653 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[27] 31_653 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[28] 30_654 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[29] 31_654 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[30] 30_655 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[31] 31_655 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[32] 30_656 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[33] 31_656 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[34] 30_657 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[35] 31_657 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[36] 30_658 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[37] 31_658 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[38] 30_659 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[39] 31_659 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[40] 30_660 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[41] 31_660 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[42] 30_661 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[43] 31_661 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[44] 30_662 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[45] 31_662 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[46] 30_663 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[47] 31_663 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[48] 30_664 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[49] 31_664 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[50] 30_665 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[51] 31_665 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[52] 30_666 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[53] 31_666 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[54] 30_667 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[55] 31_667 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[56] 30_668 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[57] 31_668 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[58] 30_669 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[59] 31_669 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[60] 30_670 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[61] 31_670 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[62] 30_671 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[63] 31_671 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[64] 30_672 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[65] 31_672 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[66] 30_673 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[67] 31_673 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[68] 30_674 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[69] 31_674 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[70] 30_675 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[71] 31_675 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[72] 30_676 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[73] 31_676 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[74] 30_677 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[75] 31_677 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[76] 30_678 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[77] 31_678 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[78] 30_679 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[79] 31_679 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[80] 30_680 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[81] 31_680 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[82] 30_681 -GTP_CHANNEL_1.GTPE2.RXCDR_FR_RESET_ON_EIDLE[0] 30_638 -GTP_CHANNEL_1.GTPE2.RXCDR_HOLD_DURING_EIDLE[0] 31_637 -GTP_CHANNEL_1.GTPE2.RXCDR_LOCK_CFG[0] 30_632 -GTP_CHANNEL_1.GTPE2.RXCDR_LOCK_CFG[1] 31_632 -GTP_CHANNEL_1.GTPE2.RXCDR_LOCK_CFG[2] 30_633 -GTP_CHANNEL_1.GTPE2.RXCDR_LOCK_CFG[3] 31_633 -GTP_CHANNEL_1.GTPE2.RXCDR_LOCK_CFG[4] 30_634 -GTP_CHANNEL_1.GTPE2.RXCDR_LOCK_CFG[5] 31_634 -GTP_CHANNEL_1.GTPE2.RXCDR_PH_RESET_ON_EIDLE[0] 31_638 -GTP_CHANNEL_1.GTPE2.RXCDRFREQRESET_TIME[0] 29_106 -GTP_CHANNEL_1.GTPE2.RXCDRFREQRESET_TIME[1] 28_107 -GTP_CHANNEL_1.GTPE2.RXCDRFREQRESET_TIME[2] 29_107 -GTP_CHANNEL_1.GTPE2.RXCDRFREQRESET_TIME[3] 28_108 -GTP_CHANNEL_1.GTPE2.RXCDRFREQRESET_TIME[4] 29_108 -GTP_CHANNEL_1.GTPE2.RXCDRPHRESET_TIME[0] 28_109 -GTP_CHANNEL_1.GTPE2.RXCDRPHRESET_TIME[1] 29_109 -GTP_CHANNEL_1.GTPE2.RXCDRPHRESET_TIME[2] 28_110 -GTP_CHANNEL_1.GTPE2.RXCDRPHRESET_TIME[3] 29_110 -GTP_CHANNEL_1.GTPE2.RXCDRPHRESET_TIME[4] 28_111 -GTP_CHANNEL_1.GTPE2.RXDLY_CFG[0] 28_680 -GTP_CHANNEL_1.GTPE2.RXDLY_CFG[1] 29_680 -GTP_CHANNEL_1.GTPE2.RXDLY_CFG[2] 28_681 -GTP_CHANNEL_1.GTPE2.RXDLY_CFG[3] 29_681 -GTP_CHANNEL_1.GTPE2.RXDLY_CFG[4] 28_682 -GTP_CHANNEL_1.GTPE2.RXDLY_CFG[5] 29_682 -GTP_CHANNEL_1.GTPE2.RXDLY_CFG[6] 28_683 -GTP_CHANNEL_1.GTPE2.RXDLY_CFG[7] 29_683 -GTP_CHANNEL_1.GTPE2.RXDLY_CFG[8] 28_684 -GTP_CHANNEL_1.GTPE2.RXDLY_CFG[9] 29_684 -GTP_CHANNEL_1.GTPE2.RXDLY_CFG[10] 28_685 -GTP_CHANNEL_1.GTPE2.RXDLY_CFG[11] 29_685 -GTP_CHANNEL_1.GTPE2.RXDLY_CFG[12] 28_686 -GTP_CHANNEL_1.GTPE2.RXDLY_CFG[13] 29_686 -GTP_CHANNEL_1.GTPE2.RXDLY_CFG[14] 28_687 -GTP_CHANNEL_1.GTPE2.RXDLY_CFG[15] 29_687 -GTP_CHANNEL_1.GTPE2.RXDLY_LCFG[0] 30_576 -GTP_CHANNEL_1.GTPE2.RXDLY_LCFG[1] 31_576 -GTP_CHANNEL_1.GTPE2.RXDLY_LCFG[2] 30_577 -GTP_CHANNEL_1.GTPE2.RXDLY_LCFG[3] 31_577 -GTP_CHANNEL_1.GTPE2.RXDLY_LCFG[4] 30_578 -GTP_CHANNEL_1.GTPE2.RXDLY_LCFG[5] 31_578 -GTP_CHANNEL_1.GTPE2.RXDLY_LCFG[6] 30_579 -GTP_CHANNEL_1.GTPE2.RXDLY_LCFG[7] 31_579 -GTP_CHANNEL_1.GTPE2.RXDLY_LCFG[8] 30_580 -GTP_CHANNEL_1.GTPE2.RXDLY_TAP_CFG[0] 28_672 -GTP_CHANNEL_1.GTPE2.RXDLY_TAP_CFG[1] 29_672 -GTP_CHANNEL_1.GTPE2.RXDLY_TAP_CFG[2] 28_673 -GTP_CHANNEL_1.GTPE2.RXDLY_TAP_CFG[3] 29_673 -GTP_CHANNEL_1.GTPE2.RXDLY_TAP_CFG[4] 28_674 -GTP_CHANNEL_1.GTPE2.RXDLY_TAP_CFG[5] 29_674 -GTP_CHANNEL_1.GTPE2.RXDLY_TAP_CFG[6] 28_675 -GTP_CHANNEL_1.GTPE2.RXDLY_TAP_CFG[7] 29_675 -GTP_CHANNEL_1.GTPE2.RXDLY_TAP_CFG[8] 28_676 -GTP_CHANNEL_1.GTPE2.RXDLY_TAP_CFG[9] 29_676 -GTP_CHANNEL_1.GTPE2.RXDLY_TAP_CFG[10] 28_677 -GTP_CHANNEL_1.GTPE2.RXDLY_TAP_CFG[11] 29_677 -GTP_CHANNEL_1.GTPE2.RXDLY_TAP_CFG[12] 28_678 -GTP_CHANNEL_1.GTPE2.RXDLY_TAP_CFG[13] 29_678 -GTP_CHANNEL_1.GTPE2.RXDLY_TAP_CFG[14] 28_679 -GTP_CHANNEL_1.GTPE2.RXDLY_TAP_CFG[15] 29_679 -GTP_CHANNEL_1.GTPE2.RXGEARBOX_EN 29_607 -GTP_CHANNEL_1.GTPE2.RXISCANRESET_TIME[0] 29_123 -GTP_CHANNEL_1.GTPE2.RXISCANRESET_TIME[1] 28_124 -GTP_CHANNEL_1.GTPE2.RXISCANRESET_TIME[2] 29_124 -GTP_CHANNEL_1.GTPE2.RXISCANRESET_TIME[3] 28_125 -GTP_CHANNEL_1.GTPE2.RXISCANRESET_TIME[4] 29_125 -GTP_CHANNEL_1.GTPE2.RXLPM_BIAS_STARTUP_DISABLE[0] 31_391 -GTP_CHANNEL_1.GTPE2.RXLPM_CFG[0] 30_328 -GTP_CHANNEL_1.GTPE2.RXLPM_CFG[1] 31_328 -GTP_CHANNEL_1.GTPE2.RXLPM_CFG[2] 30_329 -GTP_CHANNEL_1.GTPE2.RXLPM_CFG[3] 31_329 -GTP_CHANNEL_1.GTPE2.RXLPM_CM_CFG[0] 30_430 -GTP_CHANNEL_1.GTPE2.RXLPM_GC_CFG[0] 30_432 -GTP_CHANNEL_1.GTPE2.RXLPM_GC_CFG[1] 31_432 -GTP_CHANNEL_1.GTPE2.RXLPM_GC_CFG[2] 30_433 -GTP_CHANNEL_1.GTPE2.RXLPM_GC_CFG[3] 31_433 -GTP_CHANNEL_1.GTPE2.RXLPM_GC_CFG[4] 30_434 -GTP_CHANNEL_1.GTPE2.RXLPM_GC_CFG[5] 31_434 -GTP_CHANNEL_1.GTPE2.RXLPM_GC_CFG[6] 30_435 -GTP_CHANNEL_1.GTPE2.RXLPM_GC_CFG[7] 31_435 -GTP_CHANNEL_1.GTPE2.RXLPM_GC_CFG[8] 30_436 -GTP_CHANNEL_1.GTPE2.RXLPM_GC_CFG2[0] 31_442 -GTP_CHANNEL_1.GTPE2.RXLPM_GC_CFG2[1] 30_443 -GTP_CHANNEL_1.GTPE2.RXLPM_GC_CFG2[2] 31_443 -GTP_CHANNEL_1.GTPE2.RXLPM_HF_CFG[0] 28_336 -GTP_CHANNEL_1.GTPE2.RXLPM_HF_CFG[1] 29_336 -GTP_CHANNEL_1.GTPE2.RXLPM_HF_CFG[2] 28_337 -GTP_CHANNEL_1.GTPE2.RXLPM_HF_CFG[3] 29_337 -GTP_CHANNEL_1.GTPE2.RXLPM_HF_CFG[4] 28_338 -GTP_CHANNEL_1.GTPE2.RXLPM_HF_CFG[5] 29_338 -GTP_CHANNEL_1.GTPE2.RXLPM_HF_CFG[6] 28_339 -GTP_CHANNEL_1.GTPE2.RXLPM_HF_CFG[7] 29_339 -GTP_CHANNEL_1.GTPE2.RXLPM_HF_CFG[8] 28_340 -GTP_CHANNEL_1.GTPE2.RXLPM_HF_CFG[9] 29_340 -GTP_CHANNEL_1.GTPE2.RXLPM_HF_CFG[10] 28_341 -GTP_CHANNEL_1.GTPE2.RXLPM_HF_CFG[11] 29_341 -GTP_CHANNEL_1.GTPE2.RXLPM_HF_CFG[12] 28_342 -GTP_CHANNEL_1.GTPE2.RXLPM_HF_CFG[13] 29_342 -GTP_CHANNEL_1.GTPE2.RXLPM_HF_CFG2[0] 30_424 -GTP_CHANNEL_1.GTPE2.RXLPM_HF_CFG2[1] 31_424 -GTP_CHANNEL_1.GTPE2.RXLPM_HF_CFG2[2] 30_425 -GTP_CHANNEL_1.GTPE2.RXLPM_HF_CFG2[3] 31_425 -GTP_CHANNEL_1.GTPE2.RXLPM_HF_CFG2[4] 30_426 -GTP_CHANNEL_1.GTPE2.RXLPM_HF_CFG3[0] 31_389 -GTP_CHANNEL_1.GTPE2.RXLPM_HF_CFG3[1] 30_390 -GTP_CHANNEL_1.GTPE2.RXLPM_HF_CFG3[2] 31_390 -GTP_CHANNEL_1.GTPE2.RXLPM_HF_CFG3[3] 30_391 -GTP_CHANNEL_1.GTPE2.RXLPM_HOLD_DURING_EIDLE[0] 28_247 -GTP_CHANNEL_1.GTPE2.RXLPM_INCM_CFG[0] 30_439 -GTP_CHANNEL_1.GTPE2.RXLPM_IPCM_CFG[0] 31_439 -GTP_CHANNEL_1.GTPE2.RXLPM_LF_CFG[0] 28_344 -GTP_CHANNEL_1.GTPE2.RXLPM_LF_CFG[1] 29_344 -GTP_CHANNEL_1.GTPE2.RXLPM_LF_CFG[2] 28_345 -GTP_CHANNEL_1.GTPE2.RXLPM_LF_CFG[3] 29_345 -GTP_CHANNEL_1.GTPE2.RXLPM_LF_CFG[4] 28_346 -GTP_CHANNEL_1.GTPE2.RXLPM_LF_CFG[5] 29_346 -GTP_CHANNEL_1.GTPE2.RXLPM_LF_CFG[6] 28_347 -GTP_CHANNEL_1.GTPE2.RXLPM_LF_CFG[7] 29_347 -GTP_CHANNEL_1.GTPE2.RXLPM_LF_CFG[8] 28_348 -GTP_CHANNEL_1.GTPE2.RXLPM_LF_CFG[9] 29_348 -GTP_CHANNEL_1.GTPE2.RXLPM_LF_CFG[10] 28_349 -GTP_CHANNEL_1.GTPE2.RXLPM_LF_CFG[11] 29_349 -GTP_CHANNEL_1.GTPE2.RXLPM_LF_CFG[12] 28_350 -GTP_CHANNEL_1.GTPE2.RXLPM_LF_CFG[13] 29_350 -GTP_CHANNEL_1.GTPE2.RXLPM_LF_CFG[14] 28_351 -GTP_CHANNEL_1.GTPE2.RXLPM_LF_CFG[15] 29_351 -GTP_CHANNEL_1.GTPE2.RXLPM_LF_CFG[16] 28_343 -GTP_CHANNEL_1.GTPE2.RXLPM_LF_CFG[17] 29_343 -GTP_CHANNEL_1.GTPE2.RXLPM_LF_CFG2[0] 31_426 -GTP_CHANNEL_1.GTPE2.RXLPM_LF_CFG2[1] 30_427 -GTP_CHANNEL_1.GTPE2.RXLPM_LF_CFG2[2] 31_427 -GTP_CHANNEL_1.GTPE2.RXLPM_LF_CFG2[3] 30_428 -GTP_CHANNEL_1.GTPE2.RXLPM_LF_CFG2[4] 31_428 -GTP_CHANNEL_1.GTPE2.RXLPM_OSINT_CFG[0] 30_440 -GTP_CHANNEL_1.GTPE2.RXLPM_OSINT_CFG[1] 31_440 -GTP_CHANNEL_1.GTPE2.RXLPM_OSINT_CFG[2] 30_441 -GTP_CHANNEL_1.GTPE2.RXLPM_CFG1[0] 30_330 -GTP_CHANNEL_1.GTPE2.RXLPMRESET_TIME[0] 28_112 -GTP_CHANNEL_1.GTPE2.RXLPMRESET_TIME[1] 29_112 -GTP_CHANNEL_1.GTPE2.RXLPMRESET_TIME[2] 28_113 -GTP_CHANNEL_1.GTPE2.RXLPMRESET_TIME[3] 29_113 -GTP_CHANNEL_1.GTPE2.RXLPMRESET_TIME[4] 28_114 -GTP_CHANNEL_1.GTPE2.RXLPMRESET_TIME[5] 29_114 -GTP_CHANNEL_1.GTPE2.RXLPMRESET_TIME[6] 28_115 -GTP_CHANNEL_1.GTPE2.RXOOB_CFG[0] 28_144 -GTP_CHANNEL_1.GTPE2.RXOOB_CFG[1] 29_144 -GTP_CHANNEL_1.GTPE2.RXOOB_CFG[2] 28_145 -GTP_CHANNEL_1.GTPE2.RXOOB_CFG[3] 29_145 -GTP_CHANNEL_1.GTPE2.RXOOB_CFG[4] 28_146 -GTP_CHANNEL_1.GTPE2.RXOOB_CFG[5] 29_146 -GTP_CHANNEL_1.GTPE2.RXOOB_CFG[6] 28_147 -GTP_CHANNEL_1.GTPE2.RXOOB_CLK_CFG.FABRIC 31_129 -GTP_CHANNEL_1.GTPE2.RXOSCALRESET_TIME[0] 28_187 -GTP_CHANNEL_1.GTPE2.RXOSCALRESET_TIME[1] 29_187 -GTP_CHANNEL_1.GTPE2.RXOSCALRESET_TIME[2] 28_188 -GTP_CHANNEL_1.GTPE2.RXOSCALRESET_TIME[3] 29_188 -GTP_CHANNEL_1.GTPE2.RXOSCALRESET_TIME[4] 28_189 -GTP_CHANNEL_1.GTPE2.RXOSCALRESET_TIMEOUT[0] 29_189 -GTP_CHANNEL_1.GTPE2.RXOSCALRESET_TIMEOUT[1] 28_190 -GTP_CHANNEL_1.GTPE2.RXOSCALRESET_TIMEOUT[2] 29_190 -GTP_CHANNEL_1.GTPE2.RXOSCALRESET_TIMEOUT[3] 28_191 -GTP_CHANNEL_1.GTPE2.RXOSCALRESET_TIMEOUT[4] 29_191 -GTP_CHANNEL_1.GTPE2.RXOUT_DIV[0] 30_384 -GTP_CHANNEL_1.GTPE2.RXOUT_DIV[1] 31_384 -GTP_CHANNEL_1.GTPE2.RXPCSRESET_TIME[0] 29_115 -GTP_CHANNEL_1.GTPE2.RXPCSRESET_TIME[1] 28_116 -GTP_CHANNEL_1.GTPE2.RXPCSRESET_TIME[2] 29_116 -GTP_CHANNEL_1.GTPE2.RXPCSRESET_TIME[3] 28_117 -GTP_CHANNEL_1.GTPE2.RXPCSRESET_TIME[4] 29_117 -GTP_CHANNEL_1.GTPE2.RXPH_CFG[0] 30_584 -GTP_CHANNEL_1.GTPE2.RXPH_CFG[1] 31_584 -GTP_CHANNEL_1.GTPE2.RXPH_CFG[2] 30_585 -GTP_CHANNEL_1.GTPE2.RXPH_CFG[3] 31_585 -GTP_CHANNEL_1.GTPE2.RXPH_CFG[4] 30_586 -GTP_CHANNEL_1.GTPE2.RXPH_CFG[5] 31_586 -GTP_CHANNEL_1.GTPE2.RXPH_CFG[6] 30_587 -GTP_CHANNEL_1.GTPE2.RXPH_CFG[7] 31_587 -GTP_CHANNEL_1.GTPE2.RXPH_CFG[8] 30_588 -GTP_CHANNEL_1.GTPE2.RXPH_CFG[9] 31_588 -GTP_CHANNEL_1.GTPE2.RXPH_CFG[10] 30_589 -GTP_CHANNEL_1.GTPE2.RXPH_CFG[11] 31_589 -GTP_CHANNEL_1.GTPE2.RXPH_CFG[12] 30_590 -GTP_CHANNEL_1.GTPE2.RXPH_CFG[13] 31_590 -GTP_CHANNEL_1.GTPE2.RXPH_CFG[14] 30_591 -GTP_CHANNEL_1.GTPE2.RXPH_CFG[15] 31_591 -GTP_CHANNEL_1.GTPE2.RXPH_CFG[16] 30_592 -GTP_CHANNEL_1.GTPE2.RXPH_CFG[17] 31_592 -GTP_CHANNEL_1.GTPE2.RXPH_CFG[18] 30_593 -GTP_CHANNEL_1.GTPE2.RXPH_CFG[19] 31_593 -GTP_CHANNEL_1.GTPE2.RXPH_CFG[20] 30_594 -GTP_CHANNEL_1.GTPE2.RXPH_CFG[21] 31_594 -GTP_CHANNEL_1.GTPE2.RXPH_CFG[22] 30_595 -GTP_CHANNEL_1.GTPE2.RXPH_CFG[23] 31_595 -GTP_CHANNEL_1.GTPE2.RXPH_MONITOR_SEL[0] 28_700 -GTP_CHANNEL_1.GTPE2.RXPH_MONITOR_SEL[1] 29_700 -GTP_CHANNEL_1.GTPE2.RXPH_MONITOR_SEL[2] 28_701 -GTP_CHANNEL_1.GTPE2.RXPH_MONITOR_SEL[3] 29_701 -GTP_CHANNEL_1.GTPE2.RXPH_MONITOR_SEL[4] 28_702 -GTP_CHANNEL_1.GTPE2.RXPHDLY_CFG[0] 30_600 -GTP_CHANNEL_1.GTPE2.RXPHDLY_CFG[1] 31_600 -GTP_CHANNEL_1.GTPE2.RXPHDLY_CFG[2] 30_601 -GTP_CHANNEL_1.GTPE2.RXPHDLY_CFG[3] 31_601 -GTP_CHANNEL_1.GTPE2.RXPHDLY_CFG[4] 30_602 -GTP_CHANNEL_1.GTPE2.RXPHDLY_CFG[5] 31_602 -GTP_CHANNEL_1.GTPE2.RXPHDLY_CFG[6] 30_603 -GTP_CHANNEL_1.GTPE2.RXPHDLY_CFG[7] 31_603 -GTP_CHANNEL_1.GTPE2.RXPHDLY_CFG[8] 30_604 -GTP_CHANNEL_1.GTPE2.RXPHDLY_CFG[9] 31_604 -GTP_CHANNEL_1.GTPE2.RXPHDLY_CFG[10] 30_605 -GTP_CHANNEL_1.GTPE2.RXPHDLY_CFG[11] 31_605 -GTP_CHANNEL_1.GTPE2.RXPHDLY_CFG[12] 30_606 -GTP_CHANNEL_1.GTPE2.RXPHDLY_CFG[13] 31_606 -GTP_CHANNEL_1.GTPE2.RXPHDLY_CFG[14] 30_607 -GTP_CHANNEL_1.GTPE2.RXPHDLY_CFG[15] 31_607 -GTP_CHANNEL_1.GTPE2.RXPHDLY_CFG[16] 30_608 -GTP_CHANNEL_1.GTPE2.RXPHDLY_CFG[17] 31_608 -GTP_CHANNEL_1.GTPE2.RXPHDLY_CFG[18] 30_609 -GTP_CHANNEL_1.GTPE2.RXPHDLY_CFG[19] 31_609 -GTP_CHANNEL_1.GTPE2.RXPHDLY_CFG[20] 30_610 -GTP_CHANNEL_1.GTPE2.RXPHDLY_CFG[21] 31_610 -GTP_CHANNEL_1.GTPE2.RXPHDLY_CFG[22] 30_611 -GTP_CHANNEL_1.GTPE2.RXPHDLY_CFG[23] 31_611 -GTP_CHANNEL_1.GTPE2.RXPI_CFG0[0] 31_430 -GTP_CHANNEL_1.GTPE2.RXPI_CFG0[1] 30_431 -GTP_CHANNEL_1.GTPE2.RXPI_CFG0[2] 31_431 -GTP_CHANNEL_1.GTPE2.RXPI_CFG1[0] 30_442 -GTP_CHANNEL_1.GTPE2.RXPI_CFG2[0] 31_441 -GTP_CHANNEL_1.GTPE2.RXPMARESET_TIME[0] 28_104 -GTP_CHANNEL_1.GTPE2.RXPMARESET_TIME[1] 29_104 -GTP_CHANNEL_1.GTPE2.RXPMARESET_TIME[2] 28_105 -GTP_CHANNEL_1.GTPE2.RXPMARESET_TIME[3] 29_105 -GTP_CHANNEL_1.GTPE2.RXPMARESET_TIME[4] 28_106 -GTP_CHANNEL_1.GTPE2.RXPRBS_ERR_LOOPBACK[0] 28_136 -GTP_CHANNEL_1.GTPE2.RXSLIDE_AUTO_WAIT[0] 28_520 -GTP_CHANNEL_1.GTPE2.RXSLIDE_AUTO_WAIT[1] 29_520 -GTP_CHANNEL_1.GTPE2.RXSLIDE_AUTO_WAIT[2] 28_521 -GTP_CHANNEL_1.GTPE2.RXSLIDE_AUTO_WAIT[3] 29_521 -GTP_CHANNEL_1.GTPE2.RXSLIDE_MODE.AUTO 28_519 !29_519 -GTP_CHANNEL_1.GTPE2.RXSLIDE_MODE.PCS !28_519 29_519 -GTP_CHANNEL_1.GTPE2.RXSLIDE_MODE.PMA 28_519 29_519 -GTP_CHANNEL_1.GTPE2.RXSYNC_MULTILANE[0] 28_133 -GTP_CHANNEL_1.GTPE2.RXSYNC_OVRD[0] 29_135 -GTP_CHANNEL_1.GTPE2.RXSYNC_SKIP_DA[0] 29_134 -GTP_CHANNEL_1.GTPE2.SAS_MAX_COM[0] 28_171 -GTP_CHANNEL_1.GTPE2.SAS_MAX_COM[1] 29_171 -GTP_CHANNEL_1.GTPE2.SAS_MAX_COM[2] 28_172 -GTP_CHANNEL_1.GTPE2.SAS_MAX_COM[3] 29_172 -GTP_CHANNEL_1.GTPE2.SAS_MAX_COM[4] 28_173 -GTP_CHANNEL_1.GTPE2.SAS_MAX_COM[5] 29_173 -GTP_CHANNEL_1.GTPE2.SAS_MAX_COM[6] 28_174 -GTP_CHANNEL_1.GTPE2.SAS_MIN_COM[0] 29_156 -GTP_CHANNEL_1.GTPE2.SAS_MIN_COM[1] 28_157 -GTP_CHANNEL_1.GTPE2.SAS_MIN_COM[2] 29_157 -GTP_CHANNEL_1.GTPE2.SAS_MIN_COM[3] 28_158 -GTP_CHANNEL_1.GTPE2.SAS_MIN_COM[4] 29_158 -GTP_CHANNEL_1.GTPE2.SAS_MIN_COM[5] 28_159 -GTP_CHANNEL_1.GTPE2.SATA_BURST_SEQ_LEN[0] 28_150 -GTP_CHANNEL_1.GTPE2.SATA_BURST_SEQ_LEN[1] 29_150 -GTP_CHANNEL_1.GTPE2.SATA_BURST_SEQ_LEN[2] 28_151 -GTP_CHANNEL_1.GTPE2.SATA_BURST_SEQ_LEN[3] 29_151 -GTP_CHANNEL_1.GTPE2.SATA_BURST_VAL[0] 29_147 -GTP_CHANNEL_1.GTPE2.SATA_BURST_VAL[1] 28_148 -GTP_CHANNEL_1.GTPE2.SATA_BURST_VAL[2] 29_148 -GTP_CHANNEL_1.GTPE2.SATA_EIDLE_VAL[0] 28_152 -GTP_CHANNEL_1.GTPE2.SATA_EIDLE_VAL[1] 29_152 -GTP_CHANNEL_1.GTPE2.SATA_EIDLE_VAL[2] 28_153 -GTP_CHANNEL_1.GTPE2.SATA_MAX_BURST[0] 28_168 -GTP_CHANNEL_1.GTPE2.SATA_MAX_BURST[1] 29_168 -GTP_CHANNEL_1.GTPE2.SATA_MAX_BURST[2] 28_169 -GTP_CHANNEL_1.GTPE2.SATA_MAX_BURST[3] 29_169 -GTP_CHANNEL_1.GTPE2.SATA_MAX_BURST[4] 28_170 -GTP_CHANNEL_1.GTPE2.SATA_MAX_BURST[5] 29_170 -GTP_CHANNEL_1.GTPE2.SATA_MAX_INIT[0] 28_176 -GTP_CHANNEL_1.GTPE2.SATA_MAX_INIT[1] 29_176 -GTP_CHANNEL_1.GTPE2.SATA_MAX_INIT[2] 28_177 -GTP_CHANNEL_1.GTPE2.SATA_MAX_INIT[3] 29_177 -GTP_CHANNEL_1.GTPE2.SATA_MAX_INIT[4] 28_178 -GTP_CHANNEL_1.GTPE2.SATA_MAX_INIT[5] 29_178 -GTP_CHANNEL_1.GTPE2.SATA_MAX_WAKE[0] 28_179 -GTP_CHANNEL_1.GTPE2.SATA_MAX_WAKE[1] 29_179 -GTP_CHANNEL_1.GTPE2.SATA_MAX_WAKE[2] 28_180 -GTP_CHANNEL_1.GTPE2.SATA_MAX_WAKE[3] 29_180 -GTP_CHANNEL_1.GTPE2.SATA_MAX_WAKE[4] 28_181 -GTP_CHANNEL_1.GTPE2.SATA_MAX_WAKE[5] 29_181 -GTP_CHANNEL_1.GTPE2.SATA_MIN_BURST[0] 29_153 -GTP_CHANNEL_1.GTPE2.SATA_MIN_BURST[1] 28_154 -GTP_CHANNEL_1.GTPE2.SATA_MIN_BURST[2] 29_154 -GTP_CHANNEL_1.GTPE2.SATA_MIN_BURST[3] 28_155 -GTP_CHANNEL_1.GTPE2.SATA_MIN_BURST[4] 29_155 -GTP_CHANNEL_1.GTPE2.SATA_MIN_BURST[5] 28_156 -GTP_CHANNEL_1.GTPE2.SATA_MIN_INIT[0] 28_160 -GTP_CHANNEL_1.GTPE2.SATA_MIN_INIT[1] 29_160 -GTP_CHANNEL_1.GTPE2.SATA_MIN_INIT[2] 28_161 -GTP_CHANNEL_1.GTPE2.SATA_MIN_INIT[3] 29_161 -GTP_CHANNEL_1.GTPE2.SATA_MIN_INIT[4] 28_162 -GTP_CHANNEL_1.GTPE2.SATA_MIN_INIT[5] 29_162 -GTP_CHANNEL_1.GTPE2.SATA_MIN_WAKE[0] 28_163 -GTP_CHANNEL_1.GTPE2.SATA_MIN_WAKE[1] 29_163 -GTP_CHANNEL_1.GTPE2.SATA_MIN_WAKE[2] 28_164 -GTP_CHANNEL_1.GTPE2.SATA_MIN_WAKE[3] 29_164 -GTP_CHANNEL_1.GTPE2.SATA_MIN_WAKE[4] 28_165 -GTP_CHANNEL_1.GTPE2.SATA_MIN_WAKE[5] 29_165 -GTP_CHANNEL_1.GTPE2.SATA_PLL_CFG.VCO_1500MHZ 30_55 -GTP_CHANNEL_1.GTPE2.SATA_PLL_CFG.VCO_750MHZ 31_55 -GTP_CHANNEL_1.GTPE2.SHOW_REALIGN_COMMA 29_522 -GTP_CHANNEL_1.GTPE2.TERM_RCAL_CFG[0] 30_136 -GTP_CHANNEL_1.GTPE2.TERM_RCAL_CFG[1] 31_136 -GTP_CHANNEL_1.GTPE2.TERM_RCAL_CFG[2] 30_137 -GTP_CHANNEL_1.GTPE2.TERM_RCAL_CFG[3] 31_137 -GTP_CHANNEL_1.GTPE2.TERM_RCAL_CFG[4] 30_138 -GTP_CHANNEL_1.GTPE2.TERM_RCAL_CFG[5] 31_138 -GTP_CHANNEL_1.GTPE2.TERM_RCAL_CFG[6] 30_139 -GTP_CHANNEL_1.GTPE2.TERM_RCAL_CFG[7] 31_139 -GTP_CHANNEL_1.GTPE2.TERM_RCAL_CFG[8] 30_140 -GTP_CHANNEL_1.GTPE2.TERM_RCAL_CFG[9] 31_140 -GTP_CHANNEL_1.GTPE2.TERM_RCAL_CFG[10] 30_141 -GTP_CHANNEL_1.GTPE2.TERM_RCAL_CFG[11] 31_141 -GTP_CHANNEL_1.GTPE2.TERM_RCAL_CFG[12] 30_142 -GTP_CHANNEL_1.GTPE2.TERM_RCAL_CFG[13] 31_142 -GTP_CHANNEL_1.GTPE2.TERM_RCAL_CFG[14] 30_143 -GTP_CHANNEL_1.GTPE2.TERM_RCAL_OVRD[0] 31_150 -GTP_CHANNEL_1.GTPE2.TERM_RCAL_OVRD[1] 30_151 -GTP_CHANNEL_1.GTPE2.TERM_RCAL_OVRD[2] 31_151 -GTP_CHANNEL_1.GTPE2.TRANS_TIME_RATE[0] 28_192 -GTP_CHANNEL_1.GTPE2.TRANS_TIME_RATE[1] 29_192 -GTP_CHANNEL_1.GTPE2.TRANS_TIME_RATE[2] 28_193 -GTP_CHANNEL_1.GTPE2.TRANS_TIME_RATE[3] 29_193 -GTP_CHANNEL_1.GTPE2.TRANS_TIME_RATE[4] 28_194 -GTP_CHANNEL_1.GTPE2.TRANS_TIME_RATE[5] 29_194 -GTP_CHANNEL_1.GTPE2.TRANS_TIME_RATE[6] 28_195 -GTP_CHANNEL_1.GTPE2.TRANS_TIME_RATE[7] 29_195 -GTP_CHANNEL_1.GTPE2.TST_RSV[0] 30_504 -GTP_CHANNEL_1.GTPE2.TST_RSV[1] 31_504 -GTP_CHANNEL_1.GTPE2.TST_RSV[2] 30_505 -GTP_CHANNEL_1.GTPE2.TST_RSV[3] 31_505 -GTP_CHANNEL_1.GTPE2.TST_RSV[4] 30_506 -GTP_CHANNEL_1.GTPE2.TST_RSV[5] 31_506 -GTP_CHANNEL_1.GTPE2.TST_RSV[6] 30_507 -GTP_CHANNEL_1.GTPE2.TST_RSV[7] 31_507 -GTP_CHANNEL_1.GTPE2.TST_RSV[8] 30_508 -GTP_CHANNEL_1.GTPE2.TST_RSV[9] 31_508 -GTP_CHANNEL_1.GTPE2.TST_RSV[10] 30_509 -GTP_CHANNEL_1.GTPE2.TST_RSV[11] 31_509 -GTP_CHANNEL_1.GTPE2.TST_RSV[12] 30_510 -GTP_CHANNEL_1.GTPE2.TST_RSV[13] 31_510 -GTP_CHANNEL_1.GTPE2.TST_RSV[14] 30_511 -GTP_CHANNEL_1.GTPE2.TST_RSV[15] 31_511 -GTP_CHANNEL_1.GTPE2.TST_RSV[16] 30_512 -GTP_CHANNEL_1.GTPE2.TST_RSV[17] 31_512 -GTP_CHANNEL_1.GTPE2.TST_RSV[18] 30_513 -GTP_CHANNEL_1.GTPE2.TST_RSV[19] 31_513 -GTP_CHANNEL_1.GTPE2.TST_RSV[20] 30_514 -GTP_CHANNEL_1.GTPE2.TST_RSV[21] 31_514 -GTP_CHANNEL_1.GTPE2.TST_RSV[22] 30_515 -GTP_CHANNEL_1.GTPE2.TST_RSV[23] 31_515 -GTP_CHANNEL_1.GTPE2.TST_RSV[24] 30_516 -GTP_CHANNEL_1.GTPE2.TST_RSV[25] 31_516 -GTP_CHANNEL_1.GTPE2.TST_RSV[26] 30_517 -GTP_CHANNEL_1.GTPE2.TST_RSV[27] 31_517 -GTP_CHANNEL_1.GTPE2.TST_RSV[28] 30_518 -GTP_CHANNEL_1.GTPE2.TST_RSV[29] 31_518 -GTP_CHANNEL_1.GTPE2.TST_RSV[30] 30_519 -GTP_CHANNEL_1.GTPE2.TST_RSV[31] 31_519 -GTP_CHANNEL_1.GTPE2.TX_CLKMUX_EN[0] 31_128 -GTP_CHANNEL_1.GTPE2.TX_DATA_WIDTH[0] 30_152 -GTP_CHANNEL_1.GTPE2.TX_DATA_WIDTH[1] 31_152 -GTP_CHANNEL_1.GTPE2.TX_DATA_WIDTH[2] 30_153 -GTP_CHANNEL_1.GTPE2.TX_DRIVE_MODE.PIPE 28_200 -GTP_CHANNEL_1.GTPE2.TX_EIDLE_ASSERT_DELAY[0] 28_203 -GTP_CHANNEL_1.GTPE2.TX_EIDLE_ASSERT_DELAY[1] 29_203 -GTP_CHANNEL_1.GTPE2.TX_EIDLE_ASSERT_DELAY[2] 28_204 -GTP_CHANNEL_1.GTPE2.TX_EIDLE_DEASSERT_DELAY[0] 29_204 -GTP_CHANNEL_1.GTPE2.TX_EIDLE_DEASSERT_DELAY[1] 28_205 -GTP_CHANNEL_1.GTPE2.TX_EIDLE_DEASSERT_DELAY[2] 29_205 -GTP_CHANNEL_1.GTPE2.TX_LOOPBACK_DRIVE_HIZ 29_202 -GTP_CHANNEL_1.GTPE2.TX_MAINCURSOR_SEL[0] 31_289 -GTP_CHANNEL_1.GTPE2.TX_MARGIN_FULL_0[0] 30_232 -GTP_CHANNEL_1.GTPE2.TX_MARGIN_FULL_0[1] 31_232 -GTP_CHANNEL_1.GTPE2.TX_MARGIN_FULL_0[2] 30_233 -GTP_CHANNEL_1.GTPE2.TX_MARGIN_FULL_0[3] 31_233 -GTP_CHANNEL_1.GTPE2.TX_MARGIN_FULL_0[4] 30_234 -GTP_CHANNEL_1.GTPE2.TX_MARGIN_FULL_0[5] 31_234 -GTP_CHANNEL_1.GTPE2.TX_MARGIN_FULL_0[6] 30_235 -GTP_CHANNEL_1.GTPE2.TX_MARGIN_FULL_1[0] 30_236 -GTP_CHANNEL_1.GTPE2.TX_MARGIN_FULL_1[1] 31_236 -GTP_CHANNEL_1.GTPE2.TX_MARGIN_FULL_1[2] 30_237 -GTP_CHANNEL_1.GTPE2.TX_MARGIN_FULL_1[3] 31_237 -GTP_CHANNEL_1.GTPE2.TX_MARGIN_FULL_1[4] 30_238 -GTP_CHANNEL_1.GTPE2.TX_MARGIN_FULL_1[5] 31_238 -GTP_CHANNEL_1.GTPE2.TX_MARGIN_FULL_1[6] 30_239 -GTP_CHANNEL_1.GTPE2.TX_MARGIN_FULL_2[0] 30_240 -GTP_CHANNEL_1.GTPE2.TX_MARGIN_FULL_2[1] 31_240 -GTP_CHANNEL_1.GTPE2.TX_MARGIN_FULL_2[2] 30_241 -GTP_CHANNEL_1.GTPE2.TX_MARGIN_FULL_2[3] 31_241 -GTP_CHANNEL_1.GTPE2.TX_MARGIN_FULL_2[4] 30_242 -GTP_CHANNEL_1.GTPE2.TX_MARGIN_FULL_2[5] 31_242 -GTP_CHANNEL_1.GTPE2.TX_MARGIN_FULL_2[6] 30_243 -GTP_CHANNEL_1.GTPE2.TX_MARGIN_FULL_3[0] 30_244 -GTP_CHANNEL_1.GTPE2.TX_MARGIN_FULL_3[1] 31_244 -GTP_CHANNEL_1.GTPE2.TX_MARGIN_FULL_3[2] 30_245 -GTP_CHANNEL_1.GTPE2.TX_MARGIN_FULL_3[3] 31_245 -GTP_CHANNEL_1.GTPE2.TX_MARGIN_FULL_3[4] 30_246 -GTP_CHANNEL_1.GTPE2.TX_MARGIN_FULL_3[5] 31_246 -GTP_CHANNEL_1.GTPE2.TX_MARGIN_FULL_3[6] 30_247 -GTP_CHANNEL_1.GTPE2.TX_MARGIN_FULL_4[0] 30_248 -GTP_CHANNEL_1.GTPE2.TX_MARGIN_FULL_4[1] 31_248 -GTP_CHANNEL_1.GTPE2.TX_MARGIN_FULL_4[2] 30_249 -GTP_CHANNEL_1.GTPE2.TX_MARGIN_FULL_4[3] 31_249 -GTP_CHANNEL_1.GTPE2.TX_MARGIN_FULL_4[4] 30_250 -GTP_CHANNEL_1.GTPE2.TX_MARGIN_FULL_4[5] 31_250 -GTP_CHANNEL_1.GTPE2.TX_MARGIN_FULL_4[6] 30_251 -GTP_CHANNEL_1.GTPE2.TX_MARGIN_LOW_0[0] 30_252 -GTP_CHANNEL_1.GTPE2.TX_MARGIN_LOW_0[1] 31_252 -GTP_CHANNEL_1.GTPE2.TX_MARGIN_LOW_0[2] 30_253 -GTP_CHANNEL_1.GTPE2.TX_MARGIN_LOW_0[3] 31_253 -GTP_CHANNEL_1.GTPE2.TX_MARGIN_LOW_0[4] 30_254 -GTP_CHANNEL_1.GTPE2.TX_MARGIN_LOW_0[5] 31_254 -GTP_CHANNEL_1.GTPE2.TX_MARGIN_LOW_0[6] 30_255 -GTP_CHANNEL_1.GTPE2.TX_MARGIN_LOW_1[0] 30_256 -GTP_CHANNEL_1.GTPE2.TX_MARGIN_LOW_1[1] 31_256 -GTP_CHANNEL_1.GTPE2.TX_MARGIN_LOW_1[2] 30_257 -GTP_CHANNEL_1.GTPE2.TX_MARGIN_LOW_1[3] 31_257 -GTP_CHANNEL_1.GTPE2.TX_MARGIN_LOW_1[4] 30_258 -GTP_CHANNEL_1.GTPE2.TX_MARGIN_LOW_1[5] 31_258 -GTP_CHANNEL_1.GTPE2.TX_MARGIN_LOW_1[6] 30_259 -GTP_CHANNEL_1.GTPE2.TX_MARGIN_LOW_2[0] 30_260 -GTP_CHANNEL_1.GTPE2.TX_MARGIN_LOW_2[1] 31_260 -GTP_CHANNEL_1.GTPE2.TX_MARGIN_LOW_2[2] 30_261 -GTP_CHANNEL_1.GTPE2.TX_MARGIN_LOW_2[3] 31_261 -GTP_CHANNEL_1.GTPE2.TX_MARGIN_LOW_2[4] 30_262 -GTP_CHANNEL_1.GTPE2.TX_MARGIN_LOW_2[5] 31_262 -GTP_CHANNEL_1.GTPE2.TX_MARGIN_LOW_2[6] 30_263 -GTP_CHANNEL_1.GTPE2.TX_MARGIN_LOW_3[0] 30_264 -GTP_CHANNEL_1.GTPE2.TX_MARGIN_LOW_3[1] 31_264 -GTP_CHANNEL_1.GTPE2.TX_MARGIN_LOW_3[2] 30_265 -GTP_CHANNEL_1.GTPE2.TX_MARGIN_LOW_3[3] 31_265 -GTP_CHANNEL_1.GTPE2.TX_MARGIN_LOW_3[4] 30_266 -GTP_CHANNEL_1.GTPE2.TX_MARGIN_LOW_3[5] 31_266 -GTP_CHANNEL_1.GTPE2.TX_MARGIN_LOW_3[6] 30_267 -GTP_CHANNEL_1.GTPE2.TX_MARGIN_LOW_4[0] 30_268 -GTP_CHANNEL_1.GTPE2.TX_MARGIN_LOW_4[1] 31_268 -GTP_CHANNEL_1.GTPE2.TX_MARGIN_LOW_4[2] 30_269 -GTP_CHANNEL_1.GTPE2.TX_MARGIN_LOW_4[3] 31_269 -GTP_CHANNEL_1.GTPE2.TX_MARGIN_LOW_4[4] 30_270 -GTP_CHANNEL_1.GTPE2.TX_MARGIN_LOW_4[5] 31_270 -GTP_CHANNEL_1.GTPE2.TX_MARGIN_LOW_4[6] 30_271 -GTP_CHANNEL_1.GTPE2.TX_PREDRIVER_MODE[0] 28_206 -GTP_CHANNEL_1.GTPE2.TX_RXDETECT_CFG[0] 30_296 -GTP_CHANNEL_1.GTPE2.TX_RXDETECT_CFG[1] 31_296 -GTP_CHANNEL_1.GTPE2.TX_RXDETECT_CFG[2] 30_297 -GTP_CHANNEL_1.GTPE2.TX_RXDETECT_CFG[3] 31_297 -GTP_CHANNEL_1.GTPE2.TX_RXDETECT_CFG[4] 30_298 -GTP_CHANNEL_1.GTPE2.TX_RXDETECT_CFG[5] 31_298 -GTP_CHANNEL_1.GTPE2.TX_RXDETECT_CFG[6] 30_299 -GTP_CHANNEL_1.GTPE2.TX_RXDETECT_CFG[7] 31_299 -GTP_CHANNEL_1.GTPE2.TX_RXDETECT_CFG[8] 30_300 -GTP_CHANNEL_1.GTPE2.TX_RXDETECT_CFG[9] 31_300 -GTP_CHANNEL_1.GTPE2.TX_RXDETECT_CFG[10] 30_301 -GTP_CHANNEL_1.GTPE2.TX_RXDETECT_CFG[11] 31_301 -GTP_CHANNEL_1.GTPE2.TX_RXDETECT_CFG[12] 30_302 -GTP_CHANNEL_1.GTPE2.TX_RXDETECT_CFG[13] 31_302 -GTP_CHANNEL_1.GTPE2.TX_RXDETECT_REF[0] 30_292 -GTP_CHANNEL_1.GTPE2.TX_RXDETECT_REF[1] 31_292 -GTP_CHANNEL_1.GTPE2.TX_RXDETECT_REF[2] 30_293 -GTP_CHANNEL_1.GTPE2.TX_XCLK_SEL.TXUSR 31_11 -GTP_CHANNEL_1.GTPE2.TX_CLK25_DIV[0] 30_144 -GTP_CHANNEL_1.GTPE2.TX_CLK25_DIV[1] 31_144 -GTP_CHANNEL_1.GTPE2.TX_CLK25_DIV[2] 30_145 -GTP_CHANNEL_1.GTPE2.TX_CLK25_DIV[3] 31_145 -GTP_CHANNEL_1.GTPE2.TX_CLK25_DIV[4] 30_146 -GTP_CHANNEL_1.GTPE2.TX_DEEMPH0[0] 30_272 -GTP_CHANNEL_1.GTPE2.TX_DEEMPH0[1] 31_272 -GTP_CHANNEL_1.GTPE2.TX_DEEMPH0[2] 30_273 -GTP_CHANNEL_1.GTPE2.TX_DEEMPH0[3] 31_273 -GTP_CHANNEL_1.GTPE2.TX_DEEMPH0[4] 30_274 -GTP_CHANNEL_1.GTPE2.TX_DEEMPH0[5] 31_274 -GTP_CHANNEL_1.GTPE2.TX_DEEMPH1[0] 30_276 -GTP_CHANNEL_1.GTPE2.TX_DEEMPH1[1] 31_276 -GTP_CHANNEL_1.GTPE2.TX_DEEMPH1[2] 30_277 -GTP_CHANNEL_1.GTPE2.TX_DEEMPH1[3] 31_277 -GTP_CHANNEL_1.GTPE2.TX_DEEMPH1[4] 30_278 -GTP_CHANNEL_1.GTPE2.TX_DEEMPH1[5] 31_278 -GTP_CHANNEL_1.GTPE2.TXBUF_EN 28_231 -GTP_CHANNEL_1.GTPE2.TXBUF_RESET_ON_RATE_CHANGE 29_231 -GTP_CHANNEL_1.GTPE2.TXDLY_CFG[0] 30_80 -GTP_CHANNEL_1.GTPE2.TXDLY_CFG[1] 31_80 -GTP_CHANNEL_1.GTPE2.TXDLY_CFG[2] 30_81 -GTP_CHANNEL_1.GTPE2.TXDLY_CFG[3] 31_81 -GTP_CHANNEL_1.GTPE2.TXDLY_CFG[4] 30_82 -GTP_CHANNEL_1.GTPE2.TXDLY_CFG[5] 31_82 -GTP_CHANNEL_1.GTPE2.TXDLY_CFG[6] 30_83 -GTP_CHANNEL_1.GTPE2.TXDLY_CFG[7] 31_83 -GTP_CHANNEL_1.GTPE2.TXDLY_CFG[8] 30_84 -GTP_CHANNEL_1.GTPE2.TXDLY_CFG[9] 31_84 -GTP_CHANNEL_1.GTPE2.TXDLY_CFG[10] 30_85 -GTP_CHANNEL_1.GTPE2.TXDLY_CFG[11] 31_85 -GTP_CHANNEL_1.GTPE2.TXDLY_CFG[12] 30_86 -GTP_CHANNEL_1.GTPE2.TXDLY_CFG[13] 31_86 -GTP_CHANNEL_1.GTPE2.TXDLY_CFG[14] 30_87 -GTP_CHANNEL_1.GTPE2.TXDLY_CFG[15] 31_87 -GTP_CHANNEL_1.GTPE2.TXDLY_LCFG[0] 30_568 -GTP_CHANNEL_1.GTPE2.TXDLY_LCFG[1] 31_568 -GTP_CHANNEL_1.GTPE2.TXDLY_LCFG[2] 30_569 -GTP_CHANNEL_1.GTPE2.TXDLY_LCFG[3] 31_569 -GTP_CHANNEL_1.GTPE2.TXDLY_LCFG[4] 30_570 -GTP_CHANNEL_1.GTPE2.TXDLY_LCFG[5] 31_570 -GTP_CHANNEL_1.GTPE2.TXDLY_LCFG[6] 30_571 -GTP_CHANNEL_1.GTPE2.TXDLY_LCFG[7] 31_571 -GTP_CHANNEL_1.GTPE2.TXDLY_LCFG[8] 30_572 -GTP_CHANNEL_1.GTPE2.TXDLY_TAP_CFG[0] 30_88 -GTP_CHANNEL_1.GTPE2.TXDLY_TAP_CFG[1] 31_88 -GTP_CHANNEL_1.GTPE2.TXDLY_TAP_CFG[2] 30_89 -GTP_CHANNEL_1.GTPE2.TXDLY_TAP_CFG[3] 31_89 -GTP_CHANNEL_1.GTPE2.TXDLY_TAP_CFG[4] 30_90 -GTP_CHANNEL_1.GTPE2.TXDLY_TAP_CFG[5] 31_90 -GTP_CHANNEL_1.GTPE2.TXDLY_TAP_CFG[6] 30_91 -GTP_CHANNEL_1.GTPE2.TXDLY_TAP_CFG[7] 31_91 -GTP_CHANNEL_1.GTPE2.TXDLY_TAP_CFG[8] 30_92 -GTP_CHANNEL_1.GTPE2.TXDLY_TAP_CFG[9] 31_92 -GTP_CHANNEL_1.GTPE2.TXDLY_TAP_CFG[10] 30_93 -GTP_CHANNEL_1.GTPE2.TXDLY_TAP_CFG[11] 31_93 -GTP_CHANNEL_1.GTPE2.TXDLY_TAP_CFG[12] 30_94 -GTP_CHANNEL_1.GTPE2.TXDLY_TAP_CFG[13] 31_94 -GTP_CHANNEL_1.GTPE2.TXDLY_TAP_CFG[14] 30_95 -GTP_CHANNEL_1.GTPE2.TXDLY_TAP_CFG[15] 31_95 -GTP_CHANNEL_1.GTPE2.TXGEARBOX_EN 29_226 -GTP_CHANNEL_1.GTPE2.TXOOB_CFG[0] 31_20 -GTP_CHANNEL_1.GTPE2.TXOUT_DIV[0] 30_386 -GTP_CHANNEL_1.GTPE2.TXOUT_DIV[1] 31_386 -GTP_CHANNEL_1.GTPE2.TXPCSRESET_TIME[0] 29_130 -GTP_CHANNEL_1.GTPE2.TXPCSRESET_TIME[1] 28_131 -GTP_CHANNEL_1.GTPE2.TXPCSRESET_TIME[2] 29_131 -GTP_CHANNEL_1.GTPE2.TXPCSRESET_TIME[3] 28_132 -GTP_CHANNEL_1.GTPE2.TXPCSRESET_TIME[4] 29_132 -GTP_CHANNEL_1.GTPE2.TXPH_CFG[0] 30_96 -GTP_CHANNEL_1.GTPE2.TXPH_CFG[1] 31_96 -GTP_CHANNEL_1.GTPE2.TXPH_CFG[2] 30_97 -GTP_CHANNEL_1.GTPE2.TXPH_CFG[3] 31_97 -GTP_CHANNEL_1.GTPE2.TXPH_CFG[4] 30_98 -GTP_CHANNEL_1.GTPE2.TXPH_CFG[5] 31_98 -GTP_CHANNEL_1.GTPE2.TXPH_CFG[6] 30_99 -GTP_CHANNEL_1.GTPE2.TXPH_CFG[7] 31_99 -GTP_CHANNEL_1.GTPE2.TXPH_CFG[8] 30_100 -GTP_CHANNEL_1.GTPE2.TXPH_CFG[9] 31_100 -GTP_CHANNEL_1.GTPE2.TXPH_CFG[10] 30_101 -GTP_CHANNEL_1.GTPE2.TXPH_CFG[11] 31_101 -GTP_CHANNEL_1.GTPE2.TXPH_CFG[12] 30_102 -GTP_CHANNEL_1.GTPE2.TXPH_CFG[13] 31_102 -GTP_CHANNEL_1.GTPE2.TXPH_CFG[14] 30_103 -GTP_CHANNEL_1.GTPE2.TXPH_CFG[15] 31_103 -GTP_CHANNEL_1.GTPE2.TXPH_MONITOR_SEL[0] 30_108 -GTP_CHANNEL_1.GTPE2.TXPH_MONITOR_SEL[1] 31_108 -GTP_CHANNEL_1.GTPE2.TXPH_MONITOR_SEL[2] 30_109 -GTP_CHANNEL_1.GTPE2.TXPH_MONITOR_SEL[3] 31_109 -GTP_CHANNEL_1.GTPE2.TXPH_MONITOR_SEL[4] 30_110 -GTP_CHANNEL_1.GTPE2.TXPHDLY_CFG[0] 30_64 -GTP_CHANNEL_1.GTPE2.TXPHDLY_CFG[1] 31_64 -GTP_CHANNEL_1.GTPE2.TXPHDLY_CFG[2] 30_65 -GTP_CHANNEL_1.GTPE2.TXPHDLY_CFG[3] 31_65 -GTP_CHANNEL_1.GTPE2.TXPHDLY_CFG[4] 30_66 -GTP_CHANNEL_1.GTPE2.TXPHDLY_CFG[5] 31_66 -GTP_CHANNEL_1.GTPE2.TXPHDLY_CFG[6] 30_67 -GTP_CHANNEL_1.GTPE2.TXPHDLY_CFG[7] 31_67 -GTP_CHANNEL_1.GTPE2.TXPHDLY_CFG[8] 30_68 -GTP_CHANNEL_1.GTPE2.TXPHDLY_CFG[9] 31_68 -GTP_CHANNEL_1.GTPE2.TXPHDLY_CFG[10] 30_69 -GTP_CHANNEL_1.GTPE2.TXPHDLY_CFG[11] 31_69 -GTP_CHANNEL_1.GTPE2.TXPHDLY_CFG[12] 30_70 -GTP_CHANNEL_1.GTPE2.TXPHDLY_CFG[13] 31_70 -GTP_CHANNEL_1.GTPE2.TXPHDLY_CFG[14] 30_71 -GTP_CHANNEL_1.GTPE2.TXPHDLY_CFG[15] 31_71 -GTP_CHANNEL_1.GTPE2.TXPHDLY_CFG[16] 30_72 -GTP_CHANNEL_1.GTPE2.TXPHDLY_CFG[17] 31_72 -GTP_CHANNEL_1.GTPE2.TXPHDLY_CFG[18] 30_73 -GTP_CHANNEL_1.GTPE2.TXPHDLY_CFG[19] 31_73 -GTP_CHANNEL_1.GTPE2.TXPHDLY_CFG[20] 30_74 -GTP_CHANNEL_1.GTPE2.TXPHDLY_CFG[21] 31_74 -GTP_CHANNEL_1.GTPE2.TXPHDLY_CFG[22] 30_75 -GTP_CHANNEL_1.GTPE2.TXPHDLY_CFG[23] 31_75 -GTP_CHANNEL_1.GTPE2.TXPI_GREY_SEL[0] 31_498 -GTP_CHANNEL_1.GTPE2.TXPI_INVSTROBE_SEL[0] 30_498 -GTP_CHANNEL_1.GTPE2.TXPI_PPM_CFG[0] 30_488 -GTP_CHANNEL_1.GTPE2.TXPI_PPM_CFG[1] 31_488 -GTP_CHANNEL_1.GTPE2.TXPI_PPM_CFG[2] 30_489 -GTP_CHANNEL_1.GTPE2.TXPI_PPM_CFG[3] 31_489 -GTP_CHANNEL_1.GTPE2.TXPI_PPM_CFG[4] 30_490 -GTP_CHANNEL_1.GTPE2.TXPI_PPM_CFG[5] 31_490 -GTP_CHANNEL_1.GTPE2.TXPI_PPM_CFG[6] 30_491 -GTP_CHANNEL_1.GTPE2.TXPI_PPM_CFG[7] 31_491 -GTP_CHANNEL_1.GTPE2.TXPI_PPMCLK_SEL.TXUSRCLK2 31_497 -GTP_CHANNEL_1.GTPE2.TXPI_SYNFREQ_PPM[0] 30_496 -GTP_CHANNEL_1.GTPE2.TXPI_SYNFREQ_PPM[1] 31_496 -GTP_CHANNEL_1.GTPE2.TXPI_SYNFREQ_PPM[2] 30_497 -GTP_CHANNEL_1.GTPE2.TXPI_CFG0[0] 30_40 -GTP_CHANNEL_1.GTPE2.TXPI_CFG0[1] 31_40 -GTP_CHANNEL_1.GTPE2.TXPI_CFG1[0] 30_41 -GTP_CHANNEL_1.GTPE2.TXPI_CFG1[1] 31_41 -GTP_CHANNEL_1.GTPE2.TXPI_CFG2[0] 30_42 -GTP_CHANNEL_1.GTPE2.TXPI_CFG2[1] 31_42 -GTP_CHANNEL_1.GTPE2.TXPI_CFG3[0] 30_43 -GTP_CHANNEL_1.GTPE2.TXPI_CFG4[0] 31_43 -GTP_CHANNEL_1.GTPE2.TXPI_CFG5[0] 30_44 -GTP_CHANNEL_1.GTPE2.TXPI_CFG5[1] 31_44 -GTP_CHANNEL_1.GTPE2.TXPI_CFG5[2] 30_45 -GTP_CHANNEL_1.GTPE2.TXPMARESET_TIME[0] 28_128 -GTP_CHANNEL_1.GTPE2.TXPMARESET_TIME[1] 29_128 -GTP_CHANNEL_1.GTPE2.TXPMARESET_TIME[2] 28_129 -GTP_CHANNEL_1.GTPE2.TXPMARESET_TIME[3] 29_129 -GTP_CHANNEL_1.GTPE2.TXPMARESET_TIME[4] 28_130 -GTP_CHANNEL_1.GTPE2.TXSYNC_MULTILANE[0] 29_133 -GTP_CHANNEL_1.GTPE2.TXSYNC_OVRD[0] 28_135 -GTP_CHANNEL_1.GTPE2.TXSYNC_SKIP_DA[0] 28_134 -GTP_CHANNEL_1.GTPE2.UCODEER_CLR[0] 29_00 -GTP_CHANNEL_1.GTPE2.USE_PCS_CLK_PHASE_SEL[0] 30_463 -GTP_CHANNEL_1.GTPE2.ZINV_DMONITORCLK 30_13 -GTP_CHANNEL_1.GTPE2.ZINV_DRPCLK 30_00 -GTP_CHANNEL_1.GTPE2.ZINV_RXUSRCLK 31_01 -GTP_CHANNEL_1.GTPE2.ZINV_SIGVALIDCLK 31_13 -GTP_CHANNEL_1.GTPE2.ZINV_TXPHDLYTSTCLK 30_03 -GTP_CHANNEL_1.GTPE2.ZINV_TXUSRCLK 31_04 -GTP_CHANNEL_1.GTPE2.ZINV_CLKRSVD0 30_23 -GTP_CHANNEL_1.GTPE2.ZINV_CLKRSVD1 31_23 -GTP_CHANNEL_1.GTPE2.ZINV_RXUSRCLK2 30_02 -GTP_CHANNEL_1.GTPE2.ZINV_TXUSRCLK2 30_05 +GTP_CHANNEL_1.GTPE2_CHANNEL.ACJTAG_DEBUG_MODE[0] 28_07 +GTP_CHANNEL_1.GTPE2_CHANNEL.ACJTAG_MODE[0] 29_06 +GTP_CHANNEL_1.GTPE2_CHANNEL.ACJTAG_RESET[0] 29_07 +GTP_CHANNEL_1.GTPE2_CHANNEL.ADAPT_CFG0[0] 30_464 +GTP_CHANNEL_1.GTPE2_CHANNEL.ADAPT_CFG0[1] 31_464 +GTP_CHANNEL_1.GTPE2_CHANNEL.ADAPT_CFG0[2] 30_465 +GTP_CHANNEL_1.GTPE2_CHANNEL.ADAPT_CFG0[3] 31_465 +GTP_CHANNEL_1.GTPE2_CHANNEL.ADAPT_CFG0[4] 30_466 +GTP_CHANNEL_1.GTPE2_CHANNEL.ADAPT_CFG0[5] 31_466 +GTP_CHANNEL_1.GTPE2_CHANNEL.ADAPT_CFG0[6] 30_467 +GTP_CHANNEL_1.GTPE2_CHANNEL.ADAPT_CFG0[7] 31_467 +GTP_CHANNEL_1.GTPE2_CHANNEL.ADAPT_CFG0[8] 30_468 +GTP_CHANNEL_1.GTPE2_CHANNEL.ADAPT_CFG0[9] 31_468 +GTP_CHANNEL_1.GTPE2_CHANNEL.ADAPT_CFG0[10] 30_469 +GTP_CHANNEL_1.GTPE2_CHANNEL.ADAPT_CFG0[11] 31_469 +GTP_CHANNEL_1.GTPE2_CHANNEL.ADAPT_CFG0[12] 30_470 +GTP_CHANNEL_1.GTPE2_CHANNEL.ADAPT_CFG0[13] 31_470 +GTP_CHANNEL_1.GTPE2_CHANNEL.ADAPT_CFG0[14] 30_471 +GTP_CHANNEL_1.GTPE2_CHANNEL.ADAPT_CFG0[15] 31_471 +GTP_CHANNEL_1.GTPE2_CHANNEL.ADAPT_CFG0[16] 30_472 +GTP_CHANNEL_1.GTPE2_CHANNEL.ADAPT_CFG0[17] 31_472 +GTP_CHANNEL_1.GTPE2_CHANNEL.ADAPT_CFG0[18] 30_473 +GTP_CHANNEL_1.GTPE2_CHANNEL.ADAPT_CFG0[19] 31_473 +GTP_CHANNEL_1.GTPE2_CHANNEL.ALIGN_COMMA_DOUBLE 28_522 +GTP_CHANNEL_1.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[0] 28_496 +GTP_CHANNEL_1.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[1] 29_496 +GTP_CHANNEL_1.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[2] 28_497 +GTP_CHANNEL_1.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[3] 29_497 +GTP_CHANNEL_1.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[4] 28_498 +GTP_CHANNEL_1.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[5] 29_498 +GTP_CHANNEL_1.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[6] 28_499 +GTP_CHANNEL_1.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[7] 29_499 +GTP_CHANNEL_1.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[8] 28_500 +GTP_CHANNEL_1.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[9] 29_500 +GTP_CHANNEL_1.GTPE2_CHANNEL.ALIGN_COMMA_WORD[0] 29_526 +GTP_CHANNEL_1.GTPE2_CHANNEL.ALIGN_COMMA_WORD[1] 28_527 +GTP_CHANNEL_1.GTPE2_CHANNEL.ALIGN_MCOMMA_DET 28_523 +GTP_CHANNEL_1.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[0] 28_504 +GTP_CHANNEL_1.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[1] 29_504 +GTP_CHANNEL_1.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[2] 28_505 +GTP_CHANNEL_1.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[3] 29_505 +GTP_CHANNEL_1.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[4] 28_506 +GTP_CHANNEL_1.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[5] 29_506 +GTP_CHANNEL_1.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[6] 28_507 +GTP_CHANNEL_1.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[7] 29_507 +GTP_CHANNEL_1.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[8] 28_508 +GTP_CHANNEL_1.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[9] 29_508 +GTP_CHANNEL_1.GTPE2_CHANNEL.ALIGN_PCOMMA_DET 29_523 +GTP_CHANNEL_1.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[0] 28_512 +GTP_CHANNEL_1.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[1] 29_512 +GTP_CHANNEL_1.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[2] 28_513 +GTP_CHANNEL_1.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[3] 29_513 +GTP_CHANNEL_1.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[4] 28_514 +GTP_CHANNEL_1.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[5] 29_514 +GTP_CHANNEL_1.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[6] 28_515 +GTP_CHANNEL_1.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[7] 29_515 +GTP_CHANNEL_1.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[8] 28_516 +GTP_CHANNEL_1.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[9] 29_516 +GTP_CHANNEL_1.GTPE2_CHANNEL.CBCC_DATA_SOURCE_SEL.DECODED 29_661 +GTP_CHANNEL_1.GTPE2_CHANNEL.CFOK_CFG[0] 30_392 +GTP_CHANNEL_1.GTPE2_CHANNEL.CFOK_CFG[1] 31_392 +GTP_CHANNEL_1.GTPE2_CHANNEL.CFOK_CFG[2] 30_393 +GTP_CHANNEL_1.GTPE2_CHANNEL.CFOK_CFG[3] 31_393 +GTP_CHANNEL_1.GTPE2_CHANNEL.CFOK_CFG[4] 30_394 +GTP_CHANNEL_1.GTPE2_CHANNEL.CFOK_CFG[5] 31_394 +GTP_CHANNEL_1.GTPE2_CHANNEL.CFOK_CFG[6] 30_395 +GTP_CHANNEL_1.GTPE2_CHANNEL.CFOK_CFG[7] 31_395 +GTP_CHANNEL_1.GTPE2_CHANNEL.CFOK_CFG[8] 30_396 +GTP_CHANNEL_1.GTPE2_CHANNEL.CFOK_CFG[9] 31_396 +GTP_CHANNEL_1.GTPE2_CHANNEL.CFOK_CFG[10] 30_397 +GTP_CHANNEL_1.GTPE2_CHANNEL.CFOK_CFG[11] 31_397 +GTP_CHANNEL_1.GTPE2_CHANNEL.CFOK_CFG[12] 30_398 +GTP_CHANNEL_1.GTPE2_CHANNEL.CFOK_CFG[13] 31_398 +GTP_CHANNEL_1.GTPE2_CHANNEL.CFOK_CFG[14] 30_399 +GTP_CHANNEL_1.GTPE2_CHANNEL.CFOK_CFG[15] 31_399 +GTP_CHANNEL_1.GTPE2_CHANNEL.CFOK_CFG[16] 30_400 +GTP_CHANNEL_1.GTPE2_CHANNEL.CFOK_CFG[17] 31_400 +GTP_CHANNEL_1.GTPE2_CHANNEL.CFOK_CFG[18] 30_401 +GTP_CHANNEL_1.GTPE2_CHANNEL.CFOK_CFG[19] 31_401 +GTP_CHANNEL_1.GTPE2_CHANNEL.CFOK_CFG[20] 30_402 +GTP_CHANNEL_1.GTPE2_CHANNEL.CFOK_CFG[21] 31_402 +GTP_CHANNEL_1.GTPE2_CHANNEL.CFOK_CFG[22] 30_403 +GTP_CHANNEL_1.GTPE2_CHANNEL.CFOK_CFG[23] 31_403 +GTP_CHANNEL_1.GTPE2_CHANNEL.CFOK_CFG[24] 30_404 +GTP_CHANNEL_1.GTPE2_CHANNEL.CFOK_CFG[25] 31_404 +GTP_CHANNEL_1.GTPE2_CHANNEL.CFOK_CFG[26] 30_405 +GTP_CHANNEL_1.GTPE2_CHANNEL.CFOK_CFG[27] 31_405 +GTP_CHANNEL_1.GTPE2_CHANNEL.CFOK_CFG[28] 30_406 +GTP_CHANNEL_1.GTPE2_CHANNEL.CFOK_CFG[29] 31_406 +GTP_CHANNEL_1.GTPE2_CHANNEL.CFOK_CFG[30] 30_407 +GTP_CHANNEL_1.GTPE2_CHANNEL.CFOK_CFG[31] 31_407 +GTP_CHANNEL_1.GTPE2_CHANNEL.CFOK_CFG[32] 30_408 +GTP_CHANNEL_1.GTPE2_CHANNEL.CFOK_CFG[33] 31_408 +GTP_CHANNEL_1.GTPE2_CHANNEL.CFOK_CFG[34] 30_409 +GTP_CHANNEL_1.GTPE2_CHANNEL.CFOK_CFG[35] 31_409 +GTP_CHANNEL_1.GTPE2_CHANNEL.CFOK_CFG[36] 30_410 +GTP_CHANNEL_1.GTPE2_CHANNEL.CFOK_CFG[37] 31_410 +GTP_CHANNEL_1.GTPE2_CHANNEL.CFOK_CFG[38] 30_411 +GTP_CHANNEL_1.GTPE2_CHANNEL.CFOK_CFG[39] 31_411 +GTP_CHANNEL_1.GTPE2_CHANNEL.CFOK_CFG[40] 30_412 +GTP_CHANNEL_1.GTPE2_CHANNEL.CFOK_CFG[41] 31_412 +GTP_CHANNEL_1.GTPE2_CHANNEL.CFOK_CFG[42] 30_413 +GTP_CHANNEL_1.GTPE2_CHANNEL.CFOK_CFG2[0] 30_459 +GTP_CHANNEL_1.GTPE2_CHANNEL.CFOK_CFG2[1] 31_459 +GTP_CHANNEL_1.GTPE2_CHANNEL.CFOK_CFG2[2] 30_460 +GTP_CHANNEL_1.GTPE2_CHANNEL.CFOK_CFG2[3] 31_460 +GTP_CHANNEL_1.GTPE2_CHANNEL.CFOK_CFG2[4] 30_461 +GTP_CHANNEL_1.GTPE2_CHANNEL.CFOK_CFG2[5] 31_461 +GTP_CHANNEL_1.GTPE2_CHANNEL.CFOK_CFG2[6] 30_462 +GTP_CHANNEL_1.GTPE2_CHANNEL.CFOK_CFG3[0] 30_416 +GTP_CHANNEL_1.GTPE2_CHANNEL.CFOK_CFG3[1] 31_416 +GTP_CHANNEL_1.GTPE2_CHANNEL.CFOK_CFG3[2] 30_417 +GTP_CHANNEL_1.GTPE2_CHANNEL.CFOK_CFG3[3] 31_417 +GTP_CHANNEL_1.GTPE2_CHANNEL.CFOK_CFG3[4] 30_418 +GTP_CHANNEL_1.GTPE2_CHANNEL.CFOK_CFG3[5] 31_418 +GTP_CHANNEL_1.GTPE2_CHANNEL.CFOK_CFG3[6] 30_419 +GTP_CHANNEL_1.GTPE2_CHANNEL.CFOK_CFG4[0] 31_438 +GTP_CHANNEL_1.GTPE2_CHANNEL.CFOK_CFG5[0] 30_429 +GTP_CHANNEL_1.GTPE2_CHANNEL.CFOK_CFG5[1] 31_429 +GTP_CHANNEL_1.GTPE2_CHANNEL.CFOK_CFG6[0] 31_436 +GTP_CHANNEL_1.GTPE2_CHANNEL.CFOK_CFG6[1] 30_437 +GTP_CHANNEL_1.GTPE2_CHANNEL.CFOK_CFG6[2] 31_437 +GTP_CHANNEL_1.GTPE2_CHANNEL.CFOK_CFG6[3] 30_438 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_KEEP_ALIGN 29_631 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_MAX_SKEW[0] 28_670 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_MAX_SKEW[1] 29_670 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_MAX_SKEW[2] 28_671 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_MAX_SKEW[3] 29_671 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[0] 28_608 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[1] 29_608 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[2] 28_609 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[3] 29_609 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[4] 28_610 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[5] 29_610 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[6] 28_611 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[7] 29_611 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[8] 28_612 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[9] 29_612 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[0] 28_616 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[1] 29_616 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[2] 28_617 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[3] 29_617 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[4] 28_618 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[5] 29_618 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[6] 28_619 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[7] 29_619 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[8] 28_620 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[9] 29_620 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[0] 28_624 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[1] 29_624 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[2] 28_625 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[3] 29_625 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[4] 28_626 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[5] 29_626 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[6] 28_627 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[7] 29_627 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[8] 28_628 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[9] 29_628 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[0] 28_632 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[1] 29_632 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[2] 28_633 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[3] 29_633 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[4] 28_634 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[5] 29_634 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[6] 28_635 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[7] 29_635 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[8] 28_636 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[9] 29_636 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_ENABLE[0] 28_614 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_ENABLE[1] 29_614 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_ENABLE[2] 28_615 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_ENABLE[3] 29_615 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[0] 28_640 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[1] 29_640 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[2] 28_641 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[3] 29_641 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[4] 28_642 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[5] 29_642 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[6] 28_643 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[7] 29_643 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[8] 28_644 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[9] 29_644 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[0] 28_648 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[1] 29_648 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[2] 28_649 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[3] 29_649 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[4] 28_650 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[5] 29_650 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[6] 28_651 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[7] 29_651 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[8] 28_652 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[9] 29_652 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[0] 28_656 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[1] 29_656 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[2] 28_657 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[3] 29_657 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[4] 28_658 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[5] 29_658 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[6] 28_659 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[7] 29_659 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[8] 28_660 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[9] 29_660 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[0] 28_664 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[1] 29_664 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[2] 28_665 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[3] 29_665 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[4] 28_666 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[5] 29_666 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[6] 28_667 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[7] 29_667 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[8] 28_668 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[9] 29_668 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_ENABLE[0] 28_646 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_ENABLE[1] 29_646 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_ENABLE[2] 28_647 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_ENABLE[3] 29_647 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_USE 29_645 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_LEN[0] 28_623 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_LEN[1] 29_623 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COMMON_SWING[0] 31_311 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_KEEP_IDLE 28_591 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_MAX_LAT[0] 28_557 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_MAX_LAT[1] 29_557 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_MAX_LAT[2] 28_558 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_MAX_LAT[3] 29_558 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_MAX_LAT[4] 28_559 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_MAX_LAT[5] 29_559 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_MIN_LAT[0] 28_565 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_MIN_LAT[1] 29_565 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_MIN_LAT[2] 28_566 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_MIN_LAT[3] 29_566 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_MIN_LAT[4] 28_567 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_MIN_LAT[5] 29_567 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_PRECEDENCE 28_590 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_REPEAT_WAIT[0] 28_573 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_REPEAT_WAIT[1] 29_573 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_REPEAT_WAIT[2] 28_574 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_REPEAT_WAIT[3] 29_574 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_REPEAT_WAIT[4] 28_575 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[0] 28_544 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[1] 29_544 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[2] 28_545 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[3] 29_545 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[4] 28_546 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[5] 29_546 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[6] 28_547 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[7] 29_547 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[8] 28_548 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[9] 29_548 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[0] 28_552 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[1] 29_552 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[2] 28_553 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[3] 29_553 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[4] 28_554 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[5] 29_554 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[6] 28_555 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[7] 29_555 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[8] 28_556 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[9] 29_556 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[0] 28_560 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[1] 29_560 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[2] 28_561 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[3] 29_561 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[4] 28_562 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[5] 29_562 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[6] 28_563 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[7] 29_563 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[8] 28_564 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[9] 29_564 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[0] 28_568 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[1] 29_568 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[2] 28_569 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[3] 29_569 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[4] 28_570 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[5] 29_570 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[6] 28_571 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[7] 29_571 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[8] 28_572 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[9] 29_572 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_1_ENABLE[0] 28_549 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_1_ENABLE[1] 29_549 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_1_ENABLE[2] 28_550 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_1_ENABLE[3] 29_550 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[0] 28_576 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[1] 29_576 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[2] 28_577 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[3] 29_577 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[4] 28_578 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[5] 29_578 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[6] 28_579 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[7] 29_579 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[8] 28_580 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[9] 29_580 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[0] 28_584 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[1] 29_584 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[2] 28_585 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[3] 29_585 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[4] 28_586 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[5] 29_586 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[6] 28_587 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[7] 29_587 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[8] 28_588 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[9] 29_588 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[0] 28_592 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[1] 29_592 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[2] 28_593 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[3] 29_593 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[4] 28_594 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[5] 29_594 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[6] 28_595 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[7] 29_595 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[8] 28_596 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[9] 29_596 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[0] 28_600 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[1] 29_600 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[2] 28_601 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[3] 29_601 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[4] 28_602 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[5] 29_602 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[6] 28_603 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[7] 29_603 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[8] 28_604 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[9] 29_604 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_2_ENABLE[0] 28_581 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_2_ENABLE[1] 29_581 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_2_ENABLE[2] 28_582 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_2_ENABLE[3] 29_582 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_2_USE 28_583 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_LEN[0] 28_589 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_LEN[1] 29_589 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_CORRECT_USE 28_551 +GTP_CHANNEL_1.GTPE2_CHANNEL.DEC_MCOMMA_DETECT 29_494 +GTP_CHANNEL_1.GTPE2_CHANNEL.DEC_PCOMMA_DETECT 28_495 +GTP_CHANNEL_1.GTPE2_CHANNEL.DEC_VALID_COMMA_ONLY 28_494 +GTP_CHANNEL_1.GTPE2_CHANNEL.DMONITOR_CFG[0] 30_368 +GTP_CHANNEL_1.GTPE2_CHANNEL.DMONITOR_CFG[1] 31_368 +GTP_CHANNEL_1.GTPE2_CHANNEL.DMONITOR_CFG[2] 30_369 +GTP_CHANNEL_1.GTPE2_CHANNEL.DMONITOR_CFG[3] 31_369 +GTP_CHANNEL_1.GTPE2_CHANNEL.DMONITOR_CFG[4] 30_370 +GTP_CHANNEL_1.GTPE2_CHANNEL.DMONITOR_CFG[5] 31_370 +GTP_CHANNEL_1.GTPE2_CHANNEL.DMONITOR_CFG[6] 30_371 +GTP_CHANNEL_1.GTPE2_CHANNEL.DMONITOR_CFG[7] 31_371 +GTP_CHANNEL_1.GTPE2_CHANNEL.DMONITOR_CFG[8] 30_372 +GTP_CHANNEL_1.GTPE2_CHANNEL.DMONITOR_CFG[9] 31_372 +GTP_CHANNEL_1.GTPE2_CHANNEL.DMONITOR_CFG[10] 30_373 +GTP_CHANNEL_1.GTPE2_CHANNEL.DMONITOR_CFG[11] 31_373 +GTP_CHANNEL_1.GTPE2_CHANNEL.DMONITOR_CFG[12] 30_374 +GTP_CHANNEL_1.GTPE2_CHANNEL.DMONITOR_CFG[13] 31_374 +GTP_CHANNEL_1.GTPE2_CHANNEL.DMONITOR_CFG[14] 30_375 +GTP_CHANNEL_1.GTPE2_CHANNEL.DMONITOR_CFG[15] 31_375 +GTP_CHANNEL_1.GTPE2_CHANNEL.DMONITOR_CFG[16] 30_376 +GTP_CHANNEL_1.GTPE2_CHANNEL.DMONITOR_CFG[17] 31_376 +GTP_CHANNEL_1.GTPE2_CHANNEL.DMONITOR_CFG[18] 30_377 +GTP_CHANNEL_1.GTPE2_CHANNEL.DMONITOR_CFG[19] 31_377 +GTP_CHANNEL_1.GTPE2_CHANNEL.DMONITOR_CFG[20] 30_378 +GTP_CHANNEL_1.GTPE2_CHANNEL.DMONITOR_CFG[21] 31_378 +GTP_CHANNEL_1.GTPE2_CHANNEL.DMONITOR_CFG[22] 30_379 +GTP_CHANNEL_1.GTPE2_CHANNEL.DMONITOR_CFG[23] 31_379 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_CLK_PHASE_SEL[0] 31_463 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_CONTROL[0] 28_488 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_CONTROL[1] 29_488 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_CONTROL[2] 28_489 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_CONTROL[3] 29_489 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_CONTROL[4] 28_490 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_CONTROL[5] 29_490 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_ERRDET_EN 29_492 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_EYE_SCAN_EN 28_492 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_HORZ_OFFSET[0] 28_480 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_HORZ_OFFSET[1] 29_480 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_HORZ_OFFSET[2] 28_481 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_HORZ_OFFSET[3] 29_481 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_HORZ_OFFSET[4] 28_482 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_HORZ_OFFSET[5] 29_482 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_HORZ_OFFSET[6] 28_483 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_HORZ_OFFSET[7] 29_483 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_HORZ_OFFSET[8] 28_484 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_HORZ_OFFSET[9] 29_484 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_HORZ_OFFSET[10] 28_485 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_HORZ_OFFSET[11] 29_485 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_PMA_CFG[0] 30_624 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_PMA_CFG[1] 31_624 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_PMA_CFG[2] 30_625 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_PMA_CFG[3] 31_625 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_PMA_CFG[4] 30_626 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_PMA_CFG[5] 31_626 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_PMA_CFG[6] 30_627 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_PMA_CFG[7] 31_627 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_PMA_CFG[8] 30_628 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_PMA_CFG[9] 31_628 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_PRESCALE[0] 29_477 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_PRESCALE[1] 28_478 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_PRESCALE[2] 29_478 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_PRESCALE[3] 28_479 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_PRESCALE[4] 29_479 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[0] 28_392 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[1] 29_392 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[2] 28_393 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[3] 29_393 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[4] 28_394 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[5] 29_394 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[6] 28_395 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[7] 29_395 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[8] 28_396 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[9] 29_396 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[10] 28_397 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[11] 29_397 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[12] 28_398 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[13] 29_398 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[14] 28_399 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[15] 29_399 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[16] 28_400 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[17] 29_400 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[18] 28_401 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[19] 29_401 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[20] 28_402 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[21] 29_402 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[22] 28_403 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[23] 29_403 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[24] 28_404 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[25] 29_404 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[26] 28_405 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[27] 29_405 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[28] 28_406 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[29] 29_406 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[30] 28_407 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[31] 29_407 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[32] 28_408 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[33] 29_408 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[34] 28_409 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[35] 29_409 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[36] 28_410 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[37] 29_410 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[38] 28_411 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[39] 29_411 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[40] 28_412 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[41] 29_412 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[42] 28_413 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[43] 29_413 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[44] 28_414 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[45] 29_414 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[46] 28_415 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[47] 29_415 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[48] 28_416 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[49] 29_416 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[50] 28_417 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[51] 29_417 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[52] 28_418 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[53] 29_418 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[54] 28_419 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[55] 29_419 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[56] 28_420 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[57] 29_420 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[58] 28_421 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[59] 29_421 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[60] 28_422 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[61] 29_422 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[62] 28_423 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[63] 29_423 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[64] 28_424 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[65] 29_424 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[66] 28_425 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[67] 29_425 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[68] 28_426 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[69] 29_426 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[70] 28_427 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[71] 29_427 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[72] 28_428 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[73] 29_428 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[74] 28_429 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[75] 29_429 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[76] 28_430 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[77] 29_430 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[78] 28_431 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[79] 29_431 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[0] 28_352 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[1] 29_352 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[2] 28_353 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[3] 29_353 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[4] 28_354 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[5] 29_354 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[6] 28_355 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[7] 29_355 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[8] 28_356 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[9] 29_356 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[10] 28_357 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[11] 29_357 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[12] 28_358 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[13] 29_358 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[14] 28_359 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[15] 29_359 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[16] 28_360 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[17] 29_360 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[18] 28_361 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[19] 29_361 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[20] 28_362 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[21] 29_362 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[22] 28_363 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[23] 29_363 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[24] 28_364 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[25] 29_364 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[26] 28_365 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[27] 29_365 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[28] 28_366 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[29] 29_366 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[30] 28_367 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[31] 29_367 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[32] 28_368 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[33] 29_368 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[34] 28_369 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[35] 29_369 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[36] 28_370 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[37] 29_370 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[38] 28_371 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[39] 29_371 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[40] 28_372 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[41] 29_372 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[42] 28_373 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[43] 29_373 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[44] 28_374 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[45] 29_374 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[46] 28_375 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[47] 29_375 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[48] 28_376 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[49] 29_376 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[50] 28_377 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[51] 29_377 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[52] 28_378 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[53] 29_378 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[54] 28_379 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[55] 29_379 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[56] 28_380 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[57] 29_380 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[58] 28_381 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[59] 29_381 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[60] 28_382 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[61] 29_382 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[62] 28_383 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[63] 29_383 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[64] 28_384 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[65] 29_384 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[66] 28_385 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[67] 29_385 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[68] 28_386 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[69] 29_386 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[70] 28_387 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[71] 29_387 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[72] 28_388 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[73] 29_388 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[74] 28_389 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[75] 29_389 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[76] 28_390 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[77] 29_390 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[78] 28_391 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[79] 29_391 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[0] 28_432 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[1] 29_432 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[2] 28_433 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[3] 29_433 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[4] 28_434 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[5] 29_434 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[6] 28_435 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[7] 29_435 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[8] 28_436 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[9] 29_436 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[10] 28_437 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[11] 29_437 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[12] 28_438 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[13] 29_438 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[14] 28_439 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[15] 29_439 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[16] 28_440 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[17] 29_440 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[18] 28_441 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[19] 29_441 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[20] 28_442 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[21] 29_442 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[22] 28_443 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[23] 29_443 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[24] 28_444 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[25] 29_444 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[26] 28_445 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[27] 29_445 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[28] 28_446 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[29] 29_446 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[30] 28_447 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[31] 29_447 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[32] 28_448 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[33] 29_448 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[34] 28_449 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[35] 29_449 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[36] 28_450 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[37] 29_450 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[38] 28_451 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[39] 29_451 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[40] 28_452 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[41] 29_452 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[42] 28_453 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[43] 29_453 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[44] 28_454 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[45] 29_454 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[46] 28_455 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[47] 29_455 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[48] 28_456 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[49] 29_456 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[50] 28_457 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[51] 29_457 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[52] 28_458 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[53] 29_458 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[54] 28_459 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[55] 29_459 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[56] 28_460 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[57] 29_460 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[58] 28_461 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[59] 29_461 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[60] 28_462 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[61] 29_462 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[62] 28_463 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[63] 29_463 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[64] 28_464 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[65] 29_464 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[66] 28_465 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[67] 29_465 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[68] 28_466 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[69] 29_466 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[70] 28_467 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[71] 29_467 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[72] 28_468 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[73] 29_468 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[74] 28_469 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[75] 29_469 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[76] 28_470 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[77] 29_470 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[78] 28_471 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[79] 29_471 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_VERT_OFFSET[0] 28_472 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_VERT_OFFSET[1] 29_472 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_VERT_OFFSET[2] 28_473 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_VERT_OFFSET[3] 29_473 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_VERT_OFFSET[4] 28_474 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_VERT_OFFSET[5] 29_474 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_VERT_OFFSET[6] 28_475 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_VERT_OFFSET[7] 29_475 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_VERT_OFFSET[8] 28_476 +GTP_CHANNEL_1.GTPE2_CHANNEL.FTS_DESKEW_SEQ_ENABLE[0] 28_662 +GTP_CHANNEL_1.GTPE2_CHANNEL.FTS_DESKEW_SEQ_ENABLE[1] 29_662 +GTP_CHANNEL_1.GTPE2_CHANNEL.FTS_DESKEW_SEQ_ENABLE[2] 28_663 +GTP_CHANNEL_1.GTPE2_CHANNEL.FTS_DESKEW_SEQ_ENABLE[3] 29_663 +GTP_CHANNEL_1.GTPE2_CHANNEL.FTS_LANE_DESKEW_CFG[0] 28_654 +GTP_CHANNEL_1.GTPE2_CHANNEL.FTS_LANE_DESKEW_CFG[1] 29_654 +GTP_CHANNEL_1.GTPE2_CHANNEL.FTS_LANE_DESKEW_CFG[2] 28_655 +GTP_CHANNEL_1.GTPE2_CHANNEL.FTS_LANE_DESKEW_CFG[3] 29_655 +GTP_CHANNEL_1.GTPE2_CHANNEL.FTS_LANE_DESKEW_EN 29_653 +GTP_CHANNEL_1.GTPE2_CHANNEL.GEARBOX_MODE[0] 28_224 +GTP_CHANNEL_1.GTPE2_CHANNEL.GEARBOX_MODE[1] 29_224 +GTP_CHANNEL_1.GTPE2_CHANNEL.GEARBOX_MODE[2] 28_225 +GTP_CHANNEL_1.GTPE2_CHANNEL.IN_USE 28_00 28_01 28_47 28_52 28_53 28_65 29_01 29_47 30_129 +GTP_CHANNEL_1.GTPE2_CHANNEL.INV_DMONITORCLK 30_13 +GTP_CHANNEL_1.GTPE2_CHANNEL.INV_DRPCLK 30_00 +GTP_CHANNEL_1.GTPE2_CHANNEL.INV_RXUSRCLK 31_01 +GTP_CHANNEL_1.GTPE2_CHANNEL.INV_SIGVALIDCLK 31_13 +GTP_CHANNEL_1.GTPE2_CHANNEL.INV_TXPHDLYTSTCLK 30_03 +GTP_CHANNEL_1.GTPE2_CHANNEL.INV_TXUSRCLK 31_04 +GTP_CHANNEL_1.GTPE2_CHANNEL.INV_CLKRSVD0 30_23 +GTP_CHANNEL_1.GTPE2_CHANNEL.INV_CLKRSVD1 31_23 +GTP_CHANNEL_1.GTPE2_CHANNEL.INV_RXUSRCLK2 30_02 +GTP_CHANNEL_1.GTPE2_CHANNEL.INV_TXUSRCLK2 30_05 +GTP_CHANNEL_1.GTPE2_CHANNEL.LOOPBACK_CFG[0] 30_20 +GTP_CHANNEL_1.GTPE2_CHANNEL.OUTREFCLK_SEL_INV[0] 28_149 +GTP_CHANNEL_1.GTPE2_CHANNEL.OUTREFCLK_SEL_INV[1] 29_149 +GTP_CHANNEL_1.GTPE2_CHANNEL.PCS_PCIE_EN 28_216 +GTP_CHANNEL_1.GTPE2_CHANNEL.PCS_RSVD_ATTR[0] 30_184 +GTP_CHANNEL_1.GTPE2_CHANNEL.PCS_RSVD_ATTR[1] 31_184 +GTP_CHANNEL_1.GTPE2_CHANNEL.PCS_RSVD_ATTR[2] 30_185 +GTP_CHANNEL_1.GTPE2_CHANNEL.PCS_RSVD_ATTR[3] 31_185 +GTP_CHANNEL_1.GTPE2_CHANNEL.PCS_RSVD_ATTR[4] 30_186 +GTP_CHANNEL_1.GTPE2_CHANNEL.PCS_RSVD_ATTR[5] 31_186 +GTP_CHANNEL_1.GTPE2_CHANNEL.PCS_RSVD_ATTR[6] 30_187 +GTP_CHANNEL_1.GTPE2_CHANNEL.PCS_RSVD_ATTR[7] 31_187 +GTP_CHANNEL_1.GTPE2_CHANNEL.PCS_RSVD_ATTR[8] 30_188 +GTP_CHANNEL_1.GTPE2_CHANNEL.PCS_RSVD_ATTR[9] 31_188 +GTP_CHANNEL_1.GTPE2_CHANNEL.PCS_RSVD_ATTR[10] 30_189 +GTP_CHANNEL_1.GTPE2_CHANNEL.PCS_RSVD_ATTR[11] 31_189 +GTP_CHANNEL_1.GTPE2_CHANNEL.PCS_RSVD_ATTR[12] 30_190 +GTP_CHANNEL_1.GTPE2_CHANNEL.PCS_RSVD_ATTR[13] 31_190 +GTP_CHANNEL_1.GTPE2_CHANNEL.PCS_RSVD_ATTR[14] 30_191 +GTP_CHANNEL_1.GTPE2_CHANNEL.PCS_RSVD_ATTR[15] 31_191 +GTP_CHANNEL_1.GTPE2_CHANNEL.PCS_RSVD_ATTR[16] 30_192 +GTP_CHANNEL_1.GTPE2_CHANNEL.PCS_RSVD_ATTR[17] 31_192 +GTP_CHANNEL_1.GTPE2_CHANNEL.PCS_RSVD_ATTR[18] 30_193 +GTP_CHANNEL_1.GTPE2_CHANNEL.PCS_RSVD_ATTR[19] 31_193 +GTP_CHANNEL_1.GTPE2_CHANNEL.PCS_RSVD_ATTR[20] 30_194 +GTP_CHANNEL_1.GTPE2_CHANNEL.PCS_RSVD_ATTR[21] 31_194 +GTP_CHANNEL_1.GTPE2_CHANNEL.PCS_RSVD_ATTR[22] 30_195 +GTP_CHANNEL_1.GTPE2_CHANNEL.PCS_RSVD_ATTR[23] 31_195 +GTP_CHANNEL_1.GTPE2_CHANNEL.PCS_RSVD_ATTR[24] 30_196 +GTP_CHANNEL_1.GTPE2_CHANNEL.PCS_RSVD_ATTR[25] 31_196 +GTP_CHANNEL_1.GTPE2_CHANNEL.PCS_RSVD_ATTR[26] 30_197 +GTP_CHANNEL_1.GTPE2_CHANNEL.PCS_RSVD_ATTR[27] 31_197 +GTP_CHANNEL_1.GTPE2_CHANNEL.PCS_RSVD_ATTR[28] 30_198 +GTP_CHANNEL_1.GTPE2_CHANNEL.PCS_RSVD_ATTR[29] 31_198 +GTP_CHANNEL_1.GTPE2_CHANNEL.PCS_RSVD_ATTR[30] 30_199 +GTP_CHANNEL_1.GTPE2_CHANNEL.PCS_RSVD_ATTR[31] 31_199 +GTP_CHANNEL_1.GTPE2_CHANNEL.PCS_RSVD_ATTR[32] 30_200 +GTP_CHANNEL_1.GTPE2_CHANNEL.PCS_RSVD_ATTR[33] 31_200 +GTP_CHANNEL_1.GTPE2_CHANNEL.PCS_RSVD_ATTR[34] 30_201 +GTP_CHANNEL_1.GTPE2_CHANNEL.PCS_RSVD_ATTR[35] 31_201 +GTP_CHANNEL_1.GTPE2_CHANNEL.PCS_RSVD_ATTR[36] 30_202 +GTP_CHANNEL_1.GTPE2_CHANNEL.PCS_RSVD_ATTR[37] 31_202 +GTP_CHANNEL_1.GTPE2_CHANNEL.PCS_RSVD_ATTR[38] 30_203 +GTP_CHANNEL_1.GTPE2_CHANNEL.PCS_RSVD_ATTR[39] 31_203 +GTP_CHANNEL_1.GTPE2_CHANNEL.PCS_RSVD_ATTR[40] 30_204 +GTP_CHANNEL_1.GTPE2_CHANNEL.PCS_RSVD_ATTR[41] 31_204 +GTP_CHANNEL_1.GTPE2_CHANNEL.PCS_RSVD_ATTR[42] 30_205 +GTP_CHANNEL_1.GTPE2_CHANNEL.PCS_RSVD_ATTR[43] 31_205 +GTP_CHANNEL_1.GTPE2_CHANNEL.PCS_RSVD_ATTR[44] 30_206 +GTP_CHANNEL_1.GTPE2_CHANNEL.PCS_RSVD_ATTR[45] 31_206 +GTP_CHANNEL_1.GTPE2_CHANNEL.PCS_RSVD_ATTR[46] 30_207 +GTP_CHANNEL_1.GTPE2_CHANNEL.PCS_RSVD_ATTR[47] 31_207 +GTP_CHANNEL_1.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[0] 29_216 +GTP_CHANNEL_1.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[1] 28_217 +GTP_CHANNEL_1.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[2] 29_217 +GTP_CHANNEL_1.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[3] 28_218 +GTP_CHANNEL_1.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[4] 29_218 +GTP_CHANNEL_1.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[5] 28_219 +GTP_CHANNEL_1.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[6] 29_219 +GTP_CHANNEL_1.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[7] 28_220 +GTP_CHANNEL_1.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[8] 29_220 +GTP_CHANNEL_1.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[9] 28_221 +GTP_CHANNEL_1.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[10] 29_221 +GTP_CHANNEL_1.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[11] 28_222 +GTP_CHANNEL_1.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[0] 28_208 +GTP_CHANNEL_1.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[1] 29_208 +GTP_CHANNEL_1.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[2] 28_209 +GTP_CHANNEL_1.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[3] 29_209 +GTP_CHANNEL_1.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[4] 28_210 +GTP_CHANNEL_1.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[5] 29_210 +GTP_CHANNEL_1.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[6] 28_211 +GTP_CHANNEL_1.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[7] 29_211 +GTP_CHANNEL_1.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[0] 28_212 +GTP_CHANNEL_1.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[1] 29_212 +GTP_CHANNEL_1.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[2] 28_213 +GTP_CHANNEL_1.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[3] 29_213 +GTP_CHANNEL_1.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[4] 28_214 +GTP_CHANNEL_1.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[5] 29_214 +GTP_CHANNEL_1.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[6] 28_215 +GTP_CHANNEL_1.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[7] 29_215 +GTP_CHANNEL_1.GTPE2_CHANNEL.PMA_LOOPBACK_CFG[0] 29_207 +GTP_CHANNEL_1.GTPE2_CHANNEL.PMA_RSV[0] 30_520 +GTP_CHANNEL_1.GTPE2_CHANNEL.PMA_RSV[1] 31_520 +GTP_CHANNEL_1.GTPE2_CHANNEL.PMA_RSV[2] 30_521 +GTP_CHANNEL_1.GTPE2_CHANNEL.PMA_RSV[3] 31_521 +GTP_CHANNEL_1.GTPE2_CHANNEL.PMA_RSV[4] 30_522 +GTP_CHANNEL_1.GTPE2_CHANNEL.PMA_RSV[5] 31_522 +GTP_CHANNEL_1.GTPE2_CHANNEL.PMA_RSV[6] 30_523 +GTP_CHANNEL_1.GTPE2_CHANNEL.PMA_RSV[7] 31_523 +GTP_CHANNEL_1.GTPE2_CHANNEL.PMA_RSV[8] 30_524 +GTP_CHANNEL_1.GTPE2_CHANNEL.PMA_RSV[9] 31_524 +GTP_CHANNEL_1.GTPE2_CHANNEL.PMA_RSV[10] 30_525 +GTP_CHANNEL_1.GTPE2_CHANNEL.PMA_RSV[11] 31_525 +GTP_CHANNEL_1.GTPE2_CHANNEL.PMA_RSV[12] 30_526 +GTP_CHANNEL_1.GTPE2_CHANNEL.PMA_RSV[13] 31_526 +GTP_CHANNEL_1.GTPE2_CHANNEL.PMA_RSV[14] 30_527 +GTP_CHANNEL_1.GTPE2_CHANNEL.PMA_RSV[15] 31_527 +GTP_CHANNEL_1.GTPE2_CHANNEL.PMA_RSV[16] 30_528 +GTP_CHANNEL_1.GTPE2_CHANNEL.PMA_RSV[17] 31_528 +GTP_CHANNEL_1.GTPE2_CHANNEL.PMA_RSV[18] 30_529 +GTP_CHANNEL_1.GTPE2_CHANNEL.PMA_RSV[19] 31_529 +GTP_CHANNEL_1.GTPE2_CHANNEL.PMA_RSV[20] 30_530 +GTP_CHANNEL_1.GTPE2_CHANNEL.PMA_RSV[21] 31_530 +GTP_CHANNEL_1.GTPE2_CHANNEL.PMA_RSV[22] 30_531 +GTP_CHANNEL_1.GTPE2_CHANNEL.PMA_RSV[23] 31_531 +GTP_CHANNEL_1.GTPE2_CHANNEL.PMA_RSV[24] 30_532 +GTP_CHANNEL_1.GTPE2_CHANNEL.PMA_RSV[25] 31_532 +GTP_CHANNEL_1.GTPE2_CHANNEL.PMA_RSV[26] 30_533 +GTP_CHANNEL_1.GTPE2_CHANNEL.PMA_RSV[27] 31_533 +GTP_CHANNEL_1.GTPE2_CHANNEL.PMA_RSV[28] 30_534 +GTP_CHANNEL_1.GTPE2_CHANNEL.PMA_RSV[29] 31_534 +GTP_CHANNEL_1.GTPE2_CHANNEL.PMA_RSV[30] 30_535 +GTP_CHANNEL_1.GTPE2_CHANNEL.PMA_RSV[31] 31_535 +GTP_CHANNEL_1.GTPE2_CHANNEL.PMA_RSV2[0] 30_336 +GTP_CHANNEL_1.GTPE2_CHANNEL.PMA_RSV2[1] 31_336 +GTP_CHANNEL_1.GTPE2_CHANNEL.PMA_RSV2[2] 30_337 +GTP_CHANNEL_1.GTPE2_CHANNEL.PMA_RSV2[3] 31_337 +GTP_CHANNEL_1.GTPE2_CHANNEL.PMA_RSV2[4] 30_338 +GTP_CHANNEL_1.GTPE2_CHANNEL.PMA_RSV2[5] 31_338 +GTP_CHANNEL_1.GTPE2_CHANNEL.PMA_RSV2[6] 30_339 +GTP_CHANNEL_1.GTPE2_CHANNEL.PMA_RSV2[7] 31_339 +GTP_CHANNEL_1.GTPE2_CHANNEL.PMA_RSV2[8] 30_340 +GTP_CHANNEL_1.GTPE2_CHANNEL.PMA_RSV2[9] 31_340 +GTP_CHANNEL_1.GTPE2_CHANNEL.PMA_RSV2[10] 30_341 +GTP_CHANNEL_1.GTPE2_CHANNEL.PMA_RSV2[11] 31_341 +GTP_CHANNEL_1.GTPE2_CHANNEL.PMA_RSV2[12] 30_342 +GTP_CHANNEL_1.GTPE2_CHANNEL.PMA_RSV2[13] 31_342 +GTP_CHANNEL_1.GTPE2_CHANNEL.PMA_RSV2[14] 30_343 +GTP_CHANNEL_1.GTPE2_CHANNEL.PMA_RSV2[15] 31_343 +GTP_CHANNEL_1.GTPE2_CHANNEL.PMA_RSV2[16] 30_344 +GTP_CHANNEL_1.GTPE2_CHANNEL.PMA_RSV2[17] 31_344 +GTP_CHANNEL_1.GTPE2_CHANNEL.PMA_RSV2[18] 30_345 +GTP_CHANNEL_1.GTPE2_CHANNEL.PMA_RSV2[19] 31_345 +GTP_CHANNEL_1.GTPE2_CHANNEL.PMA_RSV2[20] 30_346 +GTP_CHANNEL_1.GTPE2_CHANNEL.PMA_RSV2[21] 31_346 +GTP_CHANNEL_1.GTPE2_CHANNEL.PMA_RSV2[22] 30_347 +GTP_CHANNEL_1.GTPE2_CHANNEL.PMA_RSV2[23] 31_347 +GTP_CHANNEL_1.GTPE2_CHANNEL.PMA_RSV2[24] 30_348 +GTP_CHANNEL_1.GTPE2_CHANNEL.PMA_RSV2[25] 31_348 +GTP_CHANNEL_1.GTPE2_CHANNEL.PMA_RSV2[26] 30_349 +GTP_CHANNEL_1.GTPE2_CHANNEL.PMA_RSV2[27] 31_349 +GTP_CHANNEL_1.GTPE2_CHANNEL.PMA_RSV2[28] 30_350 +GTP_CHANNEL_1.GTPE2_CHANNEL.PMA_RSV2[29] 31_350 +GTP_CHANNEL_1.GTPE2_CHANNEL.PMA_RSV2[30] 30_351 +GTP_CHANNEL_1.GTPE2_CHANNEL.PMA_RSV2[31] 31_351 +GTP_CHANNEL_1.GTPE2_CHANNEL.PMA_RSV3[0] 30_288 +GTP_CHANNEL_1.GTPE2_CHANNEL.PMA_RSV3[1] 31_288 +GTP_CHANNEL_1.GTPE2_CHANNEL.PMA_RSV4[0] 30_156 +GTP_CHANNEL_1.GTPE2_CHANNEL.PMA_RSV4[1] 31_156 +GTP_CHANNEL_1.GTPE2_CHANNEL.PMA_RSV4[2] 30_157 +GTP_CHANNEL_1.GTPE2_CHANNEL.PMA_RSV4[3] 31_157 +GTP_CHANNEL_1.GTPE2_CHANNEL.PMA_RSV5[0] 31_159 +GTP_CHANNEL_1.GTPE2_CHANNEL.PMA_RSV6[0] 30_303 +GTP_CHANNEL_1.GTPE2_CHANNEL.PMA_RSV7[0] 31_303 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_BIAS_CFG[0] 30_112 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_BIAS_CFG[1] 31_112 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_BIAS_CFG[2] 30_113 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_BIAS_CFG[3] 31_113 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_BIAS_CFG[4] 30_114 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_BIAS_CFG[5] 31_114 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_BIAS_CFG[6] 30_115 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_BIAS_CFG[7] 31_115 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_BIAS_CFG[8] 30_116 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_BIAS_CFG[9] 31_116 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_BIAS_CFG[10] 30_117 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_BIAS_CFG[11] 31_117 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_BIAS_CFG[12] 30_118 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_BIAS_CFG[13] 31_118 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_BIAS_CFG[14] 30_119 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_BIAS_CFG[15] 31_119 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_BUFFER_CFG[0] 30_536 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_BUFFER_CFG[1] 31_536 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_BUFFER_CFG[2] 30_537 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_BUFFER_CFG[3] 31_537 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_BUFFER_CFG[4] 30_538 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_BUFFER_CFG[5] 31_538 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_CLKMUX_EN[0] 30_128 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_CM_SEL[0] 28_138 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_CM_SEL[1] 29_138 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_CM_TRIM[0] 30_304 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_CM_TRIM[1] 31_304 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_CM_TRIM[2] 30_305 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_CM_TRIM[3] 31_305 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_DATA_WIDTH[0] 29_141 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_DATA_WIDTH[1] 28_142 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_DATA_WIDTH[2] 29_142 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_DDI_SEL[0] 28_696 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_DDI_SEL[1] 29_696 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_DDI_SEL[2] 28_697 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_DDI_SEL[3] 29_697 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_DDI_SEL[4] 28_698 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_DDI_SEL[5] 29_698 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_DEBUG_CFG[0] 30_616 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_DEBUG_CFG[1] 31_616 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_DEBUG_CFG[2] 30_617 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_DEBUG_CFG[3] 31_617 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_DEBUG_CFG[4] 30_618 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_DEBUG_CFG[5] 31_618 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_DEBUG_CFG[6] 30_619 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_DEBUG_CFG[7] 31_619 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_DEBUG_CFG[8] 30_620 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_DEBUG_CFG[9] 31_620 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_DEBUG_CFG[10] 30_621 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_DEBUG_CFG[11] 31_621 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_DEBUG_CFG[12] 30_622 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_DEBUG_CFG[13] 31_622 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_DEFER_RESET_BUF_EN 30_552 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_DISPERR_SEQ_MATCH 29_495 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_OS_CFG[0] 28_288 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_OS_CFG[1] 29_288 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_OS_CFG[2] 28_289 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_OS_CFG[3] 29_289 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_OS_CFG[4] 28_290 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_OS_CFG[5] 29_290 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_OS_CFG[6] 28_291 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_OS_CFG[7] 29_291 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_OS_CFG[8] 28_292 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_OS_CFG[9] 29_292 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_OS_CFG[10] 28_293 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_OS_CFG[11] 29_293 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_OS_CFG[12] 28_294 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_SIG_VALID_DLY[0] 28_524 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_SIG_VALID_DLY[1] 29_524 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_SIG_VALID_DLY[2] 28_525 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_SIG_VALID_DLY[3] 29_525 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_SIG_VALID_DLY[4] 28_526 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_XCLK_SEL.RXUSR 28_143 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_CLK25_DIV[0] 28_139 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_CLK25_DIV[1] 29_139 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_CLK25_DIV[2] 28_140 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_CLK25_DIV[3] 29_140 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_CLK25_DIV[4] 28_141 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXBUF_ADDR_MODE.FAST 31_555 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXBUF_EIDLE_HI_CNT[0] 30_558 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXBUF_EIDLE_HI_CNT[1] 31_558 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXBUF_EIDLE_HI_CNT[2] 30_559 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXBUF_EIDLE_HI_CNT[3] 31_559 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXBUF_EIDLE_LO_CNT[0] 30_556 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXBUF_EIDLE_LO_CNT[1] 31_556 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXBUF_EIDLE_LO_CNT[2] 30_557 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXBUF_EIDLE_LO_CNT[3] 31_557 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXBUF_EN 30_11 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXBUF_RESET_ON_CB_CHANGE 30_560 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXBUF_RESET_ON_COMMAALIGN 30_561 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXBUF_RESET_ON_EIDLE 30_547 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXBUF_RESET_ON_RATE_CHANGE 31_560 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXBUF_THRESH_OVFLW[0] 31_552 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXBUF_THRESH_OVFLW[1] 30_553 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXBUF_THRESH_OVFLW[2] 31_553 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXBUF_THRESH_OVFLW[3] 30_554 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXBUF_THRESH_OVFLW[4] 31_554 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXBUF_THRESH_OVFLW[5] 30_555 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXBUF_THRESH_OVRD 30_548 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXBUF_THRESH_UNDFLW[0] 30_544 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXBUF_THRESH_UNDFLW[1] 31_544 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXBUF_THRESH_UNDFLW[2] 30_545 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXBUF_THRESH_UNDFLW[3] 31_545 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXBUF_THRESH_UNDFLW[4] 30_546 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXBUF_THRESH_UNDFLW[5] 31_546 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXBUFRESET_TIME[0] 29_101 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXBUFRESET_TIME[1] 28_102 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXBUFRESET_TIME[2] 29_102 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXBUFRESET_TIME[3] 28_103 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXBUFRESET_TIME[4] 29_103 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[0] 30_640 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[1] 31_640 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[2] 30_641 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[3] 31_641 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[4] 30_642 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[5] 31_642 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[6] 30_643 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[7] 31_643 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[8] 30_644 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[9] 31_644 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[10] 30_645 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[11] 31_645 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[12] 30_646 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[13] 31_646 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[14] 30_647 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[15] 31_647 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[16] 30_648 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[17] 31_648 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[18] 30_649 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[19] 31_649 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[20] 30_650 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[21] 31_650 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[22] 30_651 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[23] 31_651 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[24] 30_652 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[25] 31_652 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[26] 30_653 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[27] 31_653 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[28] 30_654 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[29] 31_654 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[30] 30_655 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[31] 31_655 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[32] 30_656 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[33] 31_656 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[34] 30_657 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[35] 31_657 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[36] 30_658 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[37] 31_658 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[38] 30_659 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[39] 31_659 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[40] 30_660 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[41] 31_660 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[42] 30_661 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[43] 31_661 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[44] 30_662 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[45] 31_662 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[46] 30_663 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[47] 31_663 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[48] 30_664 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[49] 31_664 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[50] 30_665 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[51] 31_665 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[52] 30_666 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[53] 31_666 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[54] 30_667 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[55] 31_667 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[56] 30_668 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[57] 31_668 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[58] 30_669 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[59] 31_669 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[60] 30_670 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[61] 31_670 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[62] 30_671 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[63] 31_671 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[64] 30_672 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[65] 31_672 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[66] 30_673 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[67] 31_673 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[68] 30_674 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[69] 31_674 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[70] 30_675 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[71] 31_675 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[72] 30_676 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[73] 31_676 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[74] 30_677 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[75] 31_677 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[76] 30_678 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[77] 31_678 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[78] 30_679 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[79] 31_679 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[80] 30_680 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[81] 31_680 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[82] 30_681 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_FR_RESET_ON_EIDLE[0] 30_638 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_HOLD_DURING_EIDLE[0] 31_637 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_LOCK_CFG[0] 30_632 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_LOCK_CFG[1] 31_632 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_LOCK_CFG[2] 30_633 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_LOCK_CFG[3] 31_633 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_LOCK_CFG[4] 30_634 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_LOCK_CFG[5] 31_634 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_PH_RESET_ON_EIDLE[0] 31_638 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDRFREQRESET_TIME[0] 29_106 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDRFREQRESET_TIME[1] 28_107 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDRFREQRESET_TIME[2] 29_107 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDRFREQRESET_TIME[3] 28_108 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDRFREQRESET_TIME[4] 29_108 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDRPHRESET_TIME[0] 28_109 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDRPHRESET_TIME[1] 29_109 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDRPHRESET_TIME[2] 28_110 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDRPHRESET_TIME[3] 29_110 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDRPHRESET_TIME[4] 28_111 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXDLY_CFG[0] 28_680 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXDLY_CFG[1] 29_680 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXDLY_CFG[2] 28_681 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXDLY_CFG[3] 29_681 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXDLY_CFG[4] 28_682 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXDLY_CFG[5] 29_682 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXDLY_CFG[6] 28_683 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXDLY_CFG[7] 29_683 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXDLY_CFG[8] 28_684 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXDLY_CFG[9] 29_684 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXDLY_CFG[10] 28_685 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXDLY_CFG[11] 29_685 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXDLY_CFG[12] 28_686 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXDLY_CFG[13] 29_686 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXDLY_CFG[14] 28_687 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXDLY_CFG[15] 29_687 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXDLY_LCFG[0] 30_576 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXDLY_LCFG[1] 31_576 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXDLY_LCFG[2] 30_577 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXDLY_LCFG[3] 31_577 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXDLY_LCFG[4] 30_578 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXDLY_LCFG[5] 31_578 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXDLY_LCFG[6] 30_579 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXDLY_LCFG[7] 31_579 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXDLY_LCFG[8] 30_580 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXDLY_TAP_CFG[0] 28_672 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXDLY_TAP_CFG[1] 29_672 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXDLY_TAP_CFG[2] 28_673 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXDLY_TAP_CFG[3] 29_673 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXDLY_TAP_CFG[4] 28_674 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXDLY_TAP_CFG[5] 29_674 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXDLY_TAP_CFG[6] 28_675 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXDLY_TAP_CFG[7] 29_675 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXDLY_TAP_CFG[8] 28_676 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXDLY_TAP_CFG[9] 29_676 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXDLY_TAP_CFG[10] 28_677 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXDLY_TAP_CFG[11] 29_677 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXDLY_TAP_CFG[12] 28_678 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXDLY_TAP_CFG[13] 29_678 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXDLY_TAP_CFG[14] 28_679 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXDLY_TAP_CFG[15] 29_679 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXGEARBOX_EN 29_607 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXISCANRESET_TIME[0] 29_123 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXISCANRESET_TIME[1] 28_124 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXISCANRESET_TIME[2] 29_124 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXISCANRESET_TIME[3] 28_125 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXISCANRESET_TIME[4] 29_125 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPM_BIAS_STARTUP_DISABLE[0] 31_391 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPM_CFG[0] 30_328 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPM_CFG[1] 31_328 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPM_CFG[2] 30_329 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPM_CFG[3] 31_329 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPM_CM_CFG[0] 30_430 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPM_GC_CFG[0] 30_432 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPM_GC_CFG[1] 31_432 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPM_GC_CFG[2] 30_433 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPM_GC_CFG[3] 31_433 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPM_GC_CFG[4] 30_434 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPM_GC_CFG[5] 31_434 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPM_GC_CFG[6] 30_435 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPM_GC_CFG[7] 31_435 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPM_GC_CFG[8] 30_436 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPM_GC_CFG2[0] 31_442 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPM_GC_CFG2[1] 30_443 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPM_GC_CFG2[2] 31_443 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPM_HF_CFG[0] 28_336 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPM_HF_CFG[1] 29_336 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPM_HF_CFG[2] 28_337 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPM_HF_CFG[3] 29_337 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPM_HF_CFG[4] 28_338 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPM_HF_CFG[5] 29_338 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPM_HF_CFG[6] 28_339 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPM_HF_CFG[7] 29_339 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPM_HF_CFG[8] 28_340 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPM_HF_CFG[9] 29_340 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPM_HF_CFG[10] 28_341 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPM_HF_CFG[11] 29_341 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPM_HF_CFG[12] 28_342 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPM_HF_CFG[13] 29_342 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPM_HF_CFG2[0] 30_424 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPM_HF_CFG2[1] 31_424 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPM_HF_CFG2[2] 30_425 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPM_HF_CFG2[3] 31_425 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPM_HF_CFG2[4] 30_426 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPM_HF_CFG3[0] 31_389 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPM_HF_CFG3[1] 30_390 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPM_HF_CFG3[2] 31_390 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPM_HF_CFG3[3] 30_391 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPM_HOLD_DURING_EIDLE[0] 28_247 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPM_INCM_CFG[0] 30_439 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPM_IPCM_CFG[0] 31_439 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPM_LF_CFG[0] 28_344 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPM_LF_CFG[1] 29_344 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPM_LF_CFG[2] 28_345 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPM_LF_CFG[3] 29_345 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPM_LF_CFG[4] 28_346 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPM_LF_CFG[5] 29_346 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPM_LF_CFG[6] 28_347 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPM_LF_CFG[7] 29_347 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPM_LF_CFG[8] 28_348 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPM_LF_CFG[9] 29_348 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPM_LF_CFG[10] 28_349 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPM_LF_CFG[11] 29_349 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPM_LF_CFG[12] 28_350 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPM_LF_CFG[13] 29_350 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPM_LF_CFG[14] 28_351 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPM_LF_CFG[15] 29_351 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPM_LF_CFG[16] 28_343 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPM_LF_CFG[17] 29_343 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPM_LF_CFG2[0] 31_426 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPM_LF_CFG2[1] 30_427 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPM_LF_CFG2[2] 31_427 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPM_LF_CFG2[3] 30_428 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPM_LF_CFG2[4] 31_428 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPM_OSINT_CFG[0] 30_440 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPM_OSINT_CFG[1] 31_440 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPM_OSINT_CFG[2] 30_441 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPM_CFG1[0] 30_330 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPMRESET_TIME[0] 28_112 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPMRESET_TIME[1] 29_112 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPMRESET_TIME[2] 28_113 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPMRESET_TIME[3] 29_113 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPMRESET_TIME[4] 28_114 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPMRESET_TIME[5] 29_114 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPMRESET_TIME[6] 28_115 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXOOB_CFG[0] 28_144 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXOOB_CFG[1] 29_144 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXOOB_CFG[2] 28_145 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXOOB_CFG[3] 29_145 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXOOB_CFG[4] 28_146 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXOOB_CFG[5] 29_146 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXOOB_CFG[6] 28_147 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXOOB_CLK_CFG.FABRIC 31_129 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXOSCALRESET_TIME[0] 28_187 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXOSCALRESET_TIME[1] 29_187 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXOSCALRESET_TIME[2] 28_188 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXOSCALRESET_TIME[3] 29_188 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXOSCALRESET_TIME[4] 28_189 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXOSCALRESET_TIMEOUT[0] 29_189 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXOSCALRESET_TIMEOUT[1] 28_190 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXOSCALRESET_TIMEOUT[2] 29_190 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXOSCALRESET_TIMEOUT[3] 28_191 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXOSCALRESET_TIMEOUT[4] 29_191 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXOUT_DIV[0] 30_384 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXOUT_DIV[1] 31_384 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXPCSRESET_TIME[0] 29_115 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXPCSRESET_TIME[1] 28_116 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXPCSRESET_TIME[2] 29_116 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXPCSRESET_TIME[3] 28_117 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXPCSRESET_TIME[4] 29_117 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXPH_CFG[0] 30_584 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXPH_CFG[1] 31_584 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXPH_CFG[2] 30_585 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXPH_CFG[3] 31_585 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXPH_CFG[4] 30_586 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXPH_CFG[5] 31_586 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXPH_CFG[6] 30_587 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXPH_CFG[7] 31_587 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXPH_CFG[8] 30_588 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXPH_CFG[9] 31_588 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXPH_CFG[10] 30_589 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXPH_CFG[11] 31_589 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXPH_CFG[12] 30_590 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXPH_CFG[13] 31_590 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXPH_CFG[14] 30_591 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXPH_CFG[15] 31_591 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXPH_CFG[16] 30_592 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXPH_CFG[17] 31_592 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXPH_CFG[18] 30_593 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXPH_CFG[19] 31_593 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXPH_CFG[20] 30_594 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXPH_CFG[21] 31_594 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXPH_CFG[22] 30_595 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXPH_CFG[23] 31_595 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXPH_MONITOR_SEL[0] 28_700 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXPH_MONITOR_SEL[1] 29_700 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXPH_MONITOR_SEL[2] 28_701 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXPH_MONITOR_SEL[3] 29_701 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXPH_MONITOR_SEL[4] 28_702 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXPHDLY_CFG[0] 30_600 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXPHDLY_CFG[1] 31_600 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXPHDLY_CFG[2] 30_601 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXPHDLY_CFG[3] 31_601 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXPHDLY_CFG[4] 30_602 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXPHDLY_CFG[5] 31_602 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXPHDLY_CFG[6] 30_603 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXPHDLY_CFG[7] 31_603 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXPHDLY_CFG[8] 30_604 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXPHDLY_CFG[9] 31_604 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXPHDLY_CFG[10] 30_605 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXPHDLY_CFG[11] 31_605 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXPHDLY_CFG[12] 30_606 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXPHDLY_CFG[13] 31_606 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXPHDLY_CFG[14] 30_607 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXPHDLY_CFG[15] 31_607 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXPHDLY_CFG[16] 30_608 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXPHDLY_CFG[17] 31_608 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXPHDLY_CFG[18] 30_609 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXPHDLY_CFG[19] 31_609 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXPHDLY_CFG[20] 30_610 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXPHDLY_CFG[21] 31_610 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXPHDLY_CFG[22] 30_611 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXPHDLY_CFG[23] 31_611 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXPI_CFG0[0] 31_430 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXPI_CFG0[1] 30_431 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXPI_CFG0[2] 31_431 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXPI_CFG1[0] 30_442 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXPI_CFG2[0] 31_441 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXPMARESET_TIME[0] 28_104 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXPMARESET_TIME[1] 29_104 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXPMARESET_TIME[2] 28_105 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXPMARESET_TIME[3] 29_105 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXPMARESET_TIME[4] 28_106 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXPRBS_ERR_LOOPBACK[0] 28_136 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXSLIDE_AUTO_WAIT[0] 28_520 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXSLIDE_AUTO_WAIT[1] 29_520 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXSLIDE_AUTO_WAIT[2] 28_521 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXSLIDE_AUTO_WAIT[3] 29_521 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXSLIDE_MODE.AUTO 28_519 !29_519 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXSLIDE_MODE.PCS !28_519 29_519 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXSLIDE_MODE.PMA 28_519 29_519 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXSYNC_MULTILANE[0] 28_133 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXSYNC_OVRD[0] 29_135 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXSYNC_SKIP_DA[0] 29_134 +GTP_CHANNEL_1.GTPE2_CHANNEL.SAS_MAX_COM[0] 28_171 +GTP_CHANNEL_1.GTPE2_CHANNEL.SAS_MAX_COM[1] 29_171 +GTP_CHANNEL_1.GTPE2_CHANNEL.SAS_MAX_COM[2] 28_172 +GTP_CHANNEL_1.GTPE2_CHANNEL.SAS_MAX_COM[3] 29_172 +GTP_CHANNEL_1.GTPE2_CHANNEL.SAS_MAX_COM[4] 28_173 +GTP_CHANNEL_1.GTPE2_CHANNEL.SAS_MAX_COM[5] 29_173 +GTP_CHANNEL_1.GTPE2_CHANNEL.SAS_MAX_COM[6] 28_174 +GTP_CHANNEL_1.GTPE2_CHANNEL.SAS_MIN_COM[0] 29_156 +GTP_CHANNEL_1.GTPE2_CHANNEL.SAS_MIN_COM[1] 28_157 +GTP_CHANNEL_1.GTPE2_CHANNEL.SAS_MIN_COM[2] 29_157 +GTP_CHANNEL_1.GTPE2_CHANNEL.SAS_MIN_COM[3] 28_158 +GTP_CHANNEL_1.GTPE2_CHANNEL.SAS_MIN_COM[4] 29_158 +GTP_CHANNEL_1.GTPE2_CHANNEL.SAS_MIN_COM[5] 28_159 +GTP_CHANNEL_1.GTPE2_CHANNEL.SATA_BURST_SEQ_LEN[0] 28_150 +GTP_CHANNEL_1.GTPE2_CHANNEL.SATA_BURST_SEQ_LEN[1] 29_150 +GTP_CHANNEL_1.GTPE2_CHANNEL.SATA_BURST_SEQ_LEN[2] 28_151 +GTP_CHANNEL_1.GTPE2_CHANNEL.SATA_BURST_SEQ_LEN[3] 29_151 +GTP_CHANNEL_1.GTPE2_CHANNEL.SATA_BURST_VAL[0] 29_147 +GTP_CHANNEL_1.GTPE2_CHANNEL.SATA_BURST_VAL[1] 28_148 +GTP_CHANNEL_1.GTPE2_CHANNEL.SATA_BURST_VAL[2] 29_148 +GTP_CHANNEL_1.GTPE2_CHANNEL.SATA_EIDLE_VAL[0] 28_152 +GTP_CHANNEL_1.GTPE2_CHANNEL.SATA_EIDLE_VAL[1] 29_152 +GTP_CHANNEL_1.GTPE2_CHANNEL.SATA_EIDLE_VAL[2] 28_153 +GTP_CHANNEL_1.GTPE2_CHANNEL.SATA_MAX_BURST[0] 28_168 +GTP_CHANNEL_1.GTPE2_CHANNEL.SATA_MAX_BURST[1] 29_168 +GTP_CHANNEL_1.GTPE2_CHANNEL.SATA_MAX_BURST[2] 28_169 +GTP_CHANNEL_1.GTPE2_CHANNEL.SATA_MAX_BURST[3] 29_169 +GTP_CHANNEL_1.GTPE2_CHANNEL.SATA_MAX_BURST[4] 28_170 +GTP_CHANNEL_1.GTPE2_CHANNEL.SATA_MAX_BURST[5] 29_170 +GTP_CHANNEL_1.GTPE2_CHANNEL.SATA_MAX_INIT[0] 28_176 +GTP_CHANNEL_1.GTPE2_CHANNEL.SATA_MAX_INIT[1] 29_176 +GTP_CHANNEL_1.GTPE2_CHANNEL.SATA_MAX_INIT[2] 28_177 +GTP_CHANNEL_1.GTPE2_CHANNEL.SATA_MAX_INIT[3] 29_177 +GTP_CHANNEL_1.GTPE2_CHANNEL.SATA_MAX_INIT[4] 28_178 +GTP_CHANNEL_1.GTPE2_CHANNEL.SATA_MAX_INIT[5] 29_178 +GTP_CHANNEL_1.GTPE2_CHANNEL.SATA_MAX_WAKE[0] 28_179 +GTP_CHANNEL_1.GTPE2_CHANNEL.SATA_MAX_WAKE[1] 29_179 +GTP_CHANNEL_1.GTPE2_CHANNEL.SATA_MAX_WAKE[2] 28_180 +GTP_CHANNEL_1.GTPE2_CHANNEL.SATA_MAX_WAKE[3] 29_180 +GTP_CHANNEL_1.GTPE2_CHANNEL.SATA_MAX_WAKE[4] 28_181 +GTP_CHANNEL_1.GTPE2_CHANNEL.SATA_MAX_WAKE[5] 29_181 +GTP_CHANNEL_1.GTPE2_CHANNEL.SATA_MIN_BURST[0] 29_153 +GTP_CHANNEL_1.GTPE2_CHANNEL.SATA_MIN_BURST[1] 28_154 +GTP_CHANNEL_1.GTPE2_CHANNEL.SATA_MIN_BURST[2] 29_154 +GTP_CHANNEL_1.GTPE2_CHANNEL.SATA_MIN_BURST[3] 28_155 +GTP_CHANNEL_1.GTPE2_CHANNEL.SATA_MIN_BURST[4] 29_155 +GTP_CHANNEL_1.GTPE2_CHANNEL.SATA_MIN_BURST[5] 28_156 +GTP_CHANNEL_1.GTPE2_CHANNEL.SATA_MIN_INIT[0] 28_160 +GTP_CHANNEL_1.GTPE2_CHANNEL.SATA_MIN_INIT[1] 29_160 +GTP_CHANNEL_1.GTPE2_CHANNEL.SATA_MIN_INIT[2] 28_161 +GTP_CHANNEL_1.GTPE2_CHANNEL.SATA_MIN_INIT[3] 29_161 +GTP_CHANNEL_1.GTPE2_CHANNEL.SATA_MIN_INIT[4] 28_162 +GTP_CHANNEL_1.GTPE2_CHANNEL.SATA_MIN_INIT[5] 29_162 +GTP_CHANNEL_1.GTPE2_CHANNEL.SATA_MIN_WAKE[0] 28_163 +GTP_CHANNEL_1.GTPE2_CHANNEL.SATA_MIN_WAKE[1] 29_163 +GTP_CHANNEL_1.GTPE2_CHANNEL.SATA_MIN_WAKE[2] 28_164 +GTP_CHANNEL_1.GTPE2_CHANNEL.SATA_MIN_WAKE[3] 29_164 +GTP_CHANNEL_1.GTPE2_CHANNEL.SATA_MIN_WAKE[4] 28_165 +GTP_CHANNEL_1.GTPE2_CHANNEL.SATA_MIN_WAKE[5] 29_165 +GTP_CHANNEL_1.GTPE2_CHANNEL.SATA_PLL_CFG.VCO_1500MHZ 30_55 +GTP_CHANNEL_1.GTPE2_CHANNEL.SATA_PLL_CFG.VCO_750MHZ 31_55 +GTP_CHANNEL_1.GTPE2_CHANNEL.SHOW_REALIGN_COMMA 29_522 +GTP_CHANNEL_1.GTPE2_CHANNEL.TERM_RCAL_CFG[0] 30_136 +GTP_CHANNEL_1.GTPE2_CHANNEL.TERM_RCAL_CFG[1] 31_136 +GTP_CHANNEL_1.GTPE2_CHANNEL.TERM_RCAL_CFG[2] 30_137 +GTP_CHANNEL_1.GTPE2_CHANNEL.TERM_RCAL_CFG[3] 31_137 +GTP_CHANNEL_1.GTPE2_CHANNEL.TERM_RCAL_CFG[4] 30_138 +GTP_CHANNEL_1.GTPE2_CHANNEL.TERM_RCAL_CFG[5] 31_138 +GTP_CHANNEL_1.GTPE2_CHANNEL.TERM_RCAL_CFG[6] 30_139 +GTP_CHANNEL_1.GTPE2_CHANNEL.TERM_RCAL_CFG[7] 31_139 +GTP_CHANNEL_1.GTPE2_CHANNEL.TERM_RCAL_CFG[8] 30_140 +GTP_CHANNEL_1.GTPE2_CHANNEL.TERM_RCAL_CFG[9] 31_140 +GTP_CHANNEL_1.GTPE2_CHANNEL.TERM_RCAL_CFG[10] 30_141 +GTP_CHANNEL_1.GTPE2_CHANNEL.TERM_RCAL_CFG[11] 31_141 +GTP_CHANNEL_1.GTPE2_CHANNEL.TERM_RCAL_CFG[12] 30_142 +GTP_CHANNEL_1.GTPE2_CHANNEL.TERM_RCAL_CFG[13] 31_142 +GTP_CHANNEL_1.GTPE2_CHANNEL.TERM_RCAL_CFG[14] 30_143 +GTP_CHANNEL_1.GTPE2_CHANNEL.TERM_RCAL_OVRD[0] 31_150 +GTP_CHANNEL_1.GTPE2_CHANNEL.TERM_RCAL_OVRD[1] 30_151 +GTP_CHANNEL_1.GTPE2_CHANNEL.TERM_RCAL_OVRD[2] 31_151 +GTP_CHANNEL_1.GTPE2_CHANNEL.TRANS_TIME_RATE[0] 28_192 +GTP_CHANNEL_1.GTPE2_CHANNEL.TRANS_TIME_RATE[1] 29_192 +GTP_CHANNEL_1.GTPE2_CHANNEL.TRANS_TIME_RATE[2] 28_193 +GTP_CHANNEL_1.GTPE2_CHANNEL.TRANS_TIME_RATE[3] 29_193 +GTP_CHANNEL_1.GTPE2_CHANNEL.TRANS_TIME_RATE[4] 28_194 +GTP_CHANNEL_1.GTPE2_CHANNEL.TRANS_TIME_RATE[5] 29_194 +GTP_CHANNEL_1.GTPE2_CHANNEL.TRANS_TIME_RATE[6] 28_195 +GTP_CHANNEL_1.GTPE2_CHANNEL.TRANS_TIME_RATE[7] 29_195 +GTP_CHANNEL_1.GTPE2_CHANNEL.TST_RSV[0] 30_504 +GTP_CHANNEL_1.GTPE2_CHANNEL.TST_RSV[1] 31_504 +GTP_CHANNEL_1.GTPE2_CHANNEL.TST_RSV[2] 30_505 +GTP_CHANNEL_1.GTPE2_CHANNEL.TST_RSV[3] 31_505 +GTP_CHANNEL_1.GTPE2_CHANNEL.TST_RSV[4] 30_506 +GTP_CHANNEL_1.GTPE2_CHANNEL.TST_RSV[5] 31_506 +GTP_CHANNEL_1.GTPE2_CHANNEL.TST_RSV[6] 30_507 +GTP_CHANNEL_1.GTPE2_CHANNEL.TST_RSV[7] 31_507 +GTP_CHANNEL_1.GTPE2_CHANNEL.TST_RSV[8] 30_508 +GTP_CHANNEL_1.GTPE2_CHANNEL.TST_RSV[9] 31_508 +GTP_CHANNEL_1.GTPE2_CHANNEL.TST_RSV[10] 30_509 +GTP_CHANNEL_1.GTPE2_CHANNEL.TST_RSV[11] 31_509 +GTP_CHANNEL_1.GTPE2_CHANNEL.TST_RSV[12] 30_510 +GTP_CHANNEL_1.GTPE2_CHANNEL.TST_RSV[13] 31_510 +GTP_CHANNEL_1.GTPE2_CHANNEL.TST_RSV[14] 30_511 +GTP_CHANNEL_1.GTPE2_CHANNEL.TST_RSV[15] 31_511 +GTP_CHANNEL_1.GTPE2_CHANNEL.TST_RSV[16] 30_512 +GTP_CHANNEL_1.GTPE2_CHANNEL.TST_RSV[17] 31_512 +GTP_CHANNEL_1.GTPE2_CHANNEL.TST_RSV[18] 30_513 +GTP_CHANNEL_1.GTPE2_CHANNEL.TST_RSV[19] 31_513 +GTP_CHANNEL_1.GTPE2_CHANNEL.TST_RSV[20] 30_514 +GTP_CHANNEL_1.GTPE2_CHANNEL.TST_RSV[21] 31_514 +GTP_CHANNEL_1.GTPE2_CHANNEL.TST_RSV[22] 30_515 +GTP_CHANNEL_1.GTPE2_CHANNEL.TST_RSV[23] 31_515 +GTP_CHANNEL_1.GTPE2_CHANNEL.TST_RSV[24] 30_516 +GTP_CHANNEL_1.GTPE2_CHANNEL.TST_RSV[25] 31_516 +GTP_CHANNEL_1.GTPE2_CHANNEL.TST_RSV[26] 30_517 +GTP_CHANNEL_1.GTPE2_CHANNEL.TST_RSV[27] 31_517 +GTP_CHANNEL_1.GTPE2_CHANNEL.TST_RSV[28] 30_518 +GTP_CHANNEL_1.GTPE2_CHANNEL.TST_RSV[29] 31_518 +GTP_CHANNEL_1.GTPE2_CHANNEL.TST_RSV[30] 30_519 +GTP_CHANNEL_1.GTPE2_CHANNEL.TST_RSV[31] 31_519 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_CLKMUX_EN[0] 31_128 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_DATA_WIDTH[0] 30_152 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_DATA_WIDTH[1] 31_152 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_DATA_WIDTH[2] 30_153 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_DRIVE_MODE.PIPE 28_200 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_EIDLE_ASSERT_DELAY[0] 28_203 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_EIDLE_ASSERT_DELAY[1] 29_203 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_EIDLE_ASSERT_DELAY[2] 28_204 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_EIDLE_DEASSERT_DELAY[0] 29_204 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_EIDLE_DEASSERT_DELAY[1] 28_205 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_EIDLE_DEASSERT_DELAY[2] 29_205 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_LOOPBACK_DRIVE_HIZ 29_202 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_MAINCURSOR_SEL[0] 31_289 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_MARGIN_FULL_0[0] 30_232 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_MARGIN_FULL_0[1] 31_232 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_MARGIN_FULL_0[2] 30_233 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_MARGIN_FULL_0[3] 31_233 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_MARGIN_FULL_0[4] 30_234 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_MARGIN_FULL_0[5] 31_234 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_MARGIN_FULL_0[6] 30_235 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_MARGIN_FULL_1[0] 30_236 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_MARGIN_FULL_1[1] 31_236 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_MARGIN_FULL_1[2] 30_237 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_MARGIN_FULL_1[3] 31_237 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_MARGIN_FULL_1[4] 30_238 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_MARGIN_FULL_1[5] 31_238 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_MARGIN_FULL_1[6] 30_239 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_MARGIN_FULL_2[0] 30_240 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_MARGIN_FULL_2[1] 31_240 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_MARGIN_FULL_2[2] 30_241 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_MARGIN_FULL_2[3] 31_241 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_MARGIN_FULL_2[4] 30_242 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_MARGIN_FULL_2[5] 31_242 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_MARGIN_FULL_2[6] 30_243 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_MARGIN_FULL_3[0] 30_244 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_MARGIN_FULL_3[1] 31_244 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_MARGIN_FULL_3[2] 30_245 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_MARGIN_FULL_3[3] 31_245 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_MARGIN_FULL_3[4] 30_246 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_MARGIN_FULL_3[5] 31_246 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_MARGIN_FULL_3[6] 30_247 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_MARGIN_FULL_4[0] 30_248 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_MARGIN_FULL_4[1] 31_248 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_MARGIN_FULL_4[2] 30_249 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_MARGIN_FULL_4[3] 31_249 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_MARGIN_FULL_4[4] 30_250 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_MARGIN_FULL_4[5] 31_250 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_MARGIN_FULL_4[6] 30_251 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_MARGIN_LOW_0[0] 30_252 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_MARGIN_LOW_0[1] 31_252 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_MARGIN_LOW_0[2] 30_253 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_MARGIN_LOW_0[3] 31_253 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_MARGIN_LOW_0[4] 30_254 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_MARGIN_LOW_0[5] 31_254 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_MARGIN_LOW_0[6] 30_255 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_MARGIN_LOW_1[0] 30_256 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_MARGIN_LOW_1[1] 31_256 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_MARGIN_LOW_1[2] 30_257 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_MARGIN_LOW_1[3] 31_257 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_MARGIN_LOW_1[4] 30_258 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_MARGIN_LOW_1[5] 31_258 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_MARGIN_LOW_1[6] 30_259 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_MARGIN_LOW_2[0] 30_260 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_MARGIN_LOW_2[1] 31_260 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_MARGIN_LOW_2[2] 30_261 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_MARGIN_LOW_2[3] 31_261 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_MARGIN_LOW_2[4] 30_262 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_MARGIN_LOW_2[5] 31_262 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_MARGIN_LOW_2[6] 30_263 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_MARGIN_LOW_3[0] 30_264 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_MARGIN_LOW_3[1] 31_264 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_MARGIN_LOW_3[2] 30_265 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_MARGIN_LOW_3[3] 31_265 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_MARGIN_LOW_3[4] 30_266 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_MARGIN_LOW_3[5] 31_266 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_MARGIN_LOW_3[6] 30_267 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_MARGIN_LOW_4[0] 30_268 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_MARGIN_LOW_4[1] 31_268 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_MARGIN_LOW_4[2] 30_269 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_MARGIN_LOW_4[3] 31_269 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_MARGIN_LOW_4[4] 30_270 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_MARGIN_LOW_4[5] 31_270 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_MARGIN_LOW_4[6] 30_271 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_PREDRIVER_MODE[0] 28_206 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_RXDETECT_CFG[0] 30_296 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_RXDETECT_CFG[1] 31_296 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_RXDETECT_CFG[2] 30_297 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_RXDETECT_CFG[3] 31_297 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_RXDETECT_CFG[4] 30_298 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_RXDETECT_CFG[5] 31_298 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_RXDETECT_CFG[6] 30_299 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_RXDETECT_CFG[7] 31_299 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_RXDETECT_CFG[8] 30_300 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_RXDETECT_CFG[9] 31_300 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_RXDETECT_CFG[10] 30_301 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_RXDETECT_CFG[11] 31_301 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_RXDETECT_CFG[12] 30_302 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_RXDETECT_CFG[13] 31_302 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_RXDETECT_REF[0] 30_292 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_RXDETECT_REF[1] 31_292 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_RXDETECT_REF[2] 30_293 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_XCLK_SEL.TXUSR 31_11 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_CLK25_DIV[0] 30_144 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_CLK25_DIV[1] 31_144 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_CLK25_DIV[2] 30_145 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_CLK25_DIV[3] 31_145 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_CLK25_DIV[4] 30_146 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_DEEMPH0[0] 30_272 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_DEEMPH0[1] 31_272 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_DEEMPH0[2] 30_273 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_DEEMPH0[3] 31_273 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_DEEMPH0[4] 30_274 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_DEEMPH0[5] 31_274 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_DEEMPH1[0] 30_276 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_DEEMPH1[1] 31_276 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_DEEMPH1[2] 30_277 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_DEEMPH1[3] 31_277 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_DEEMPH1[4] 30_278 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_DEEMPH1[5] 31_278 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXBUF_EN 28_231 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXBUF_RESET_ON_RATE_CHANGE 29_231 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXDLY_CFG[0] 30_80 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXDLY_CFG[1] 31_80 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXDLY_CFG[2] 30_81 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXDLY_CFG[3] 31_81 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXDLY_CFG[4] 30_82 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXDLY_CFG[5] 31_82 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXDLY_CFG[6] 30_83 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXDLY_CFG[7] 31_83 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXDLY_CFG[8] 30_84 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXDLY_CFG[9] 31_84 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXDLY_CFG[10] 30_85 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXDLY_CFG[11] 31_85 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXDLY_CFG[12] 30_86 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXDLY_CFG[13] 31_86 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXDLY_CFG[14] 30_87 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXDLY_CFG[15] 31_87 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXDLY_LCFG[0] 30_568 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXDLY_LCFG[1] 31_568 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXDLY_LCFG[2] 30_569 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXDLY_LCFG[3] 31_569 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXDLY_LCFG[4] 30_570 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXDLY_LCFG[5] 31_570 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXDLY_LCFG[6] 30_571 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXDLY_LCFG[7] 31_571 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXDLY_LCFG[8] 30_572 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXDLY_TAP_CFG[0] 30_88 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXDLY_TAP_CFG[1] 31_88 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXDLY_TAP_CFG[2] 30_89 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXDLY_TAP_CFG[3] 31_89 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXDLY_TAP_CFG[4] 30_90 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXDLY_TAP_CFG[5] 31_90 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXDLY_TAP_CFG[6] 30_91 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXDLY_TAP_CFG[7] 31_91 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXDLY_TAP_CFG[8] 30_92 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXDLY_TAP_CFG[9] 31_92 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXDLY_TAP_CFG[10] 30_93 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXDLY_TAP_CFG[11] 31_93 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXDLY_TAP_CFG[12] 30_94 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXDLY_TAP_CFG[13] 31_94 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXDLY_TAP_CFG[14] 30_95 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXDLY_TAP_CFG[15] 31_95 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXGEARBOX_EN 29_226 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXOOB_CFG[0] 31_20 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXOUT_DIV[0] 30_386 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXOUT_DIV[1] 31_386 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPCSRESET_TIME[0] 29_130 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPCSRESET_TIME[1] 28_131 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPCSRESET_TIME[2] 29_131 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPCSRESET_TIME[3] 28_132 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPCSRESET_TIME[4] 29_132 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPH_CFG[0] 30_96 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPH_CFG[1] 31_96 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPH_CFG[2] 30_97 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPH_CFG[3] 31_97 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPH_CFG[4] 30_98 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPH_CFG[5] 31_98 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPH_CFG[6] 30_99 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPH_CFG[7] 31_99 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPH_CFG[8] 30_100 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPH_CFG[9] 31_100 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPH_CFG[10] 30_101 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPH_CFG[11] 31_101 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPH_CFG[12] 30_102 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPH_CFG[13] 31_102 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPH_CFG[14] 30_103 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPH_CFG[15] 31_103 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPH_MONITOR_SEL[0] 30_108 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPH_MONITOR_SEL[1] 31_108 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPH_MONITOR_SEL[2] 30_109 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPH_MONITOR_SEL[3] 31_109 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPH_MONITOR_SEL[4] 30_110 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPHDLY_CFG[0] 30_64 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPHDLY_CFG[1] 31_64 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPHDLY_CFG[2] 30_65 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPHDLY_CFG[3] 31_65 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPHDLY_CFG[4] 30_66 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPHDLY_CFG[5] 31_66 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPHDLY_CFG[6] 30_67 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPHDLY_CFG[7] 31_67 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPHDLY_CFG[8] 30_68 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPHDLY_CFG[9] 31_68 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPHDLY_CFG[10] 30_69 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPHDLY_CFG[11] 31_69 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPHDLY_CFG[12] 30_70 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPHDLY_CFG[13] 31_70 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPHDLY_CFG[14] 30_71 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPHDLY_CFG[15] 31_71 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPHDLY_CFG[16] 30_72 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPHDLY_CFG[17] 31_72 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPHDLY_CFG[18] 30_73 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPHDLY_CFG[19] 31_73 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPHDLY_CFG[20] 30_74 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPHDLY_CFG[21] 31_74 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPHDLY_CFG[22] 30_75 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPHDLY_CFG[23] 31_75 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPI_GREY_SEL[0] 31_498 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPI_INVSTROBE_SEL[0] 30_498 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPI_PPM_CFG[0] 30_488 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPI_PPM_CFG[1] 31_488 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPI_PPM_CFG[2] 30_489 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPI_PPM_CFG[3] 31_489 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPI_PPM_CFG[4] 30_490 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPI_PPM_CFG[5] 31_490 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPI_PPM_CFG[6] 30_491 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPI_PPM_CFG[7] 31_491 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPI_PPMCLK_SEL.TXUSRCLK2 31_497 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPI_SYNFREQ_PPM[0] 30_496 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPI_SYNFREQ_PPM[1] 31_496 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPI_SYNFREQ_PPM[2] 30_497 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPI_CFG0[0] 30_40 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPI_CFG0[1] 31_40 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPI_CFG1[0] 30_41 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPI_CFG1[1] 31_41 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPI_CFG2[0] 30_42 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPI_CFG2[1] 31_42 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPI_CFG3[0] 30_43 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPI_CFG4[0] 31_43 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPI_CFG5[0] 30_44 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPI_CFG5[1] 31_44 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPI_CFG5[2] 30_45 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPMARESET_TIME[0] 28_128 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPMARESET_TIME[1] 29_128 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPMARESET_TIME[2] 28_129 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPMARESET_TIME[3] 29_129 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPMARESET_TIME[4] 28_130 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXSYNC_MULTILANE[0] 29_133 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXSYNC_OVRD[0] 28_135 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXSYNC_SKIP_DA[0] 28_134 +GTP_CHANNEL_1.GTPE2_CHANNEL.UCODEER_CLR[0] 29_00 +GTP_CHANNEL_1.GTPE2_CHANNEL.USE_PCS_CLK_PHASE_SEL[0] 30_463 diff --git a/artix7/segbits_gtp_channel_1.origin_info.db b/artix7/segbits_gtp_channel_1.origin_info.db index 4316de2..7e3ac20 100644 --- a/artix7/segbits_gtp_channel_1.origin_info.db +++ b/artix7/segbits_gtp_channel_1.origin_info.db @@ -1,1627 +1,1627 @@ -GTP_CHANNEL_1.GTPE2.ACJTAG_DEBUG_MODE[0] origin:064-gtp-channel-conf 28_07 -GTP_CHANNEL_1.GTPE2.ACJTAG_MODE[0] origin:064-gtp-channel-conf 29_06 -GTP_CHANNEL_1.GTPE2.ACJTAG_RESET[0] origin:064-gtp-channel-conf 29_07 -GTP_CHANNEL_1.GTPE2.ADAPT_CFG0[0] origin:064-gtp-channel-conf 30_464 -GTP_CHANNEL_1.GTPE2.ADAPT_CFG0[1] origin:064-gtp-channel-conf 31_464 -GTP_CHANNEL_1.GTPE2.ADAPT_CFG0[2] origin:064-gtp-channel-conf 30_465 -GTP_CHANNEL_1.GTPE2.ADAPT_CFG0[3] origin:064-gtp-channel-conf 31_465 -GTP_CHANNEL_1.GTPE2.ADAPT_CFG0[4] origin:064-gtp-channel-conf 30_466 -GTP_CHANNEL_1.GTPE2.ADAPT_CFG0[5] origin:064-gtp-channel-conf 31_466 -GTP_CHANNEL_1.GTPE2.ADAPT_CFG0[6] origin:064-gtp-channel-conf 30_467 -GTP_CHANNEL_1.GTPE2.ADAPT_CFG0[7] origin:064-gtp-channel-conf 31_467 -GTP_CHANNEL_1.GTPE2.ADAPT_CFG0[8] origin:064-gtp-channel-conf 30_468 -GTP_CHANNEL_1.GTPE2.ADAPT_CFG0[9] origin:064-gtp-channel-conf 31_468 -GTP_CHANNEL_1.GTPE2.ADAPT_CFG0[10] origin:064-gtp-channel-conf 30_469 -GTP_CHANNEL_1.GTPE2.ADAPT_CFG0[11] origin:064-gtp-channel-conf 31_469 -GTP_CHANNEL_1.GTPE2.ADAPT_CFG0[12] origin:064-gtp-channel-conf 30_470 -GTP_CHANNEL_1.GTPE2.ADAPT_CFG0[13] origin:064-gtp-channel-conf 31_470 -GTP_CHANNEL_1.GTPE2.ADAPT_CFG0[14] origin:064-gtp-channel-conf 30_471 -GTP_CHANNEL_1.GTPE2.ADAPT_CFG0[15] origin:064-gtp-channel-conf 31_471 -GTP_CHANNEL_1.GTPE2.ADAPT_CFG0[16] origin:064-gtp-channel-conf 30_472 -GTP_CHANNEL_1.GTPE2.ADAPT_CFG0[17] origin:064-gtp-channel-conf 31_472 -GTP_CHANNEL_1.GTPE2.ADAPT_CFG0[18] origin:064-gtp-channel-conf 30_473 -GTP_CHANNEL_1.GTPE2.ADAPT_CFG0[19] origin:064-gtp-channel-conf 31_473 -GTP_CHANNEL_1.GTPE2.ALIGN_COMMA_DOUBLE origin:064-gtp-channel-conf 28_522 -GTP_CHANNEL_1.GTPE2.ALIGN_COMMA_ENABLE[0] origin:064-gtp-channel-conf 28_496 -GTP_CHANNEL_1.GTPE2.ALIGN_COMMA_ENABLE[1] origin:064-gtp-channel-conf 29_496 -GTP_CHANNEL_1.GTPE2.ALIGN_COMMA_ENABLE[2] origin:064-gtp-channel-conf 28_497 -GTP_CHANNEL_1.GTPE2.ALIGN_COMMA_ENABLE[3] origin:064-gtp-channel-conf 29_497 -GTP_CHANNEL_1.GTPE2.ALIGN_COMMA_ENABLE[4] origin:064-gtp-channel-conf 28_498 -GTP_CHANNEL_1.GTPE2.ALIGN_COMMA_ENABLE[5] origin:064-gtp-channel-conf 29_498 -GTP_CHANNEL_1.GTPE2.ALIGN_COMMA_ENABLE[6] origin:064-gtp-channel-conf 28_499 -GTP_CHANNEL_1.GTPE2.ALIGN_COMMA_ENABLE[7] origin:064-gtp-channel-conf 29_499 -GTP_CHANNEL_1.GTPE2.ALIGN_COMMA_ENABLE[8] origin:064-gtp-channel-conf 28_500 -GTP_CHANNEL_1.GTPE2.ALIGN_COMMA_ENABLE[9] origin:064-gtp-channel-conf 29_500 -GTP_CHANNEL_1.GTPE2.ALIGN_COMMA_WORD[0] origin:064-gtp-channel-conf 29_526 -GTP_CHANNEL_1.GTPE2.ALIGN_COMMA_WORD[1] origin:064-gtp-channel-conf 28_527 -GTP_CHANNEL_1.GTPE2.ALIGN_MCOMMA_DET origin:064-gtp-channel-conf 28_523 -GTP_CHANNEL_1.GTPE2.ALIGN_MCOMMA_VALUE[0] origin:064-gtp-channel-conf 28_504 -GTP_CHANNEL_1.GTPE2.ALIGN_MCOMMA_VALUE[1] origin:064-gtp-channel-conf 29_504 -GTP_CHANNEL_1.GTPE2.ALIGN_MCOMMA_VALUE[2] origin:064-gtp-channel-conf 28_505 -GTP_CHANNEL_1.GTPE2.ALIGN_MCOMMA_VALUE[3] origin:064-gtp-channel-conf 29_505 -GTP_CHANNEL_1.GTPE2.ALIGN_MCOMMA_VALUE[4] origin:064-gtp-channel-conf 28_506 -GTP_CHANNEL_1.GTPE2.ALIGN_MCOMMA_VALUE[5] origin:064-gtp-channel-conf 29_506 -GTP_CHANNEL_1.GTPE2.ALIGN_MCOMMA_VALUE[6] origin:064-gtp-channel-conf 28_507 -GTP_CHANNEL_1.GTPE2.ALIGN_MCOMMA_VALUE[7] origin:064-gtp-channel-conf 29_507 -GTP_CHANNEL_1.GTPE2.ALIGN_MCOMMA_VALUE[8] origin:064-gtp-channel-conf 28_508 -GTP_CHANNEL_1.GTPE2.ALIGN_MCOMMA_VALUE[9] origin:064-gtp-channel-conf 29_508 -GTP_CHANNEL_1.GTPE2.ALIGN_PCOMMA_DET origin:064-gtp-channel-conf 29_523 -GTP_CHANNEL_1.GTPE2.ALIGN_PCOMMA_VALUE[0] origin:064-gtp-channel-conf 28_512 -GTP_CHANNEL_1.GTPE2.ALIGN_PCOMMA_VALUE[1] origin:064-gtp-channel-conf 29_512 -GTP_CHANNEL_1.GTPE2.ALIGN_PCOMMA_VALUE[2] origin:064-gtp-channel-conf 28_513 -GTP_CHANNEL_1.GTPE2.ALIGN_PCOMMA_VALUE[3] origin:064-gtp-channel-conf 29_513 -GTP_CHANNEL_1.GTPE2.ALIGN_PCOMMA_VALUE[4] origin:064-gtp-channel-conf 28_514 -GTP_CHANNEL_1.GTPE2.ALIGN_PCOMMA_VALUE[5] origin:064-gtp-channel-conf 29_514 -GTP_CHANNEL_1.GTPE2.ALIGN_PCOMMA_VALUE[6] origin:064-gtp-channel-conf 28_515 -GTP_CHANNEL_1.GTPE2.ALIGN_PCOMMA_VALUE[7] origin:064-gtp-channel-conf 29_515 -GTP_CHANNEL_1.GTPE2.ALIGN_PCOMMA_VALUE[8] origin:064-gtp-channel-conf 28_516 -GTP_CHANNEL_1.GTPE2.ALIGN_PCOMMA_VALUE[9] origin:064-gtp-channel-conf 29_516 -GTP_CHANNEL_1.GTPE2.CBCC_DATA_SOURCE_SEL.DECODED origin:064-gtp-channel-conf 29_661 -GTP_CHANNEL_1.GTPE2.CFOK_CFG[0] origin:064-gtp-channel-conf 30_392 -GTP_CHANNEL_1.GTPE2.CFOK_CFG[1] origin:064-gtp-channel-conf 31_392 -GTP_CHANNEL_1.GTPE2.CFOK_CFG[2] origin:064-gtp-channel-conf 30_393 -GTP_CHANNEL_1.GTPE2.CFOK_CFG[3] origin:064-gtp-channel-conf 31_393 -GTP_CHANNEL_1.GTPE2.CFOK_CFG[4] origin:064-gtp-channel-conf 30_394 -GTP_CHANNEL_1.GTPE2.CFOK_CFG[5] origin:064-gtp-channel-conf 31_394 -GTP_CHANNEL_1.GTPE2.CFOK_CFG[6] origin:064-gtp-channel-conf 30_395 -GTP_CHANNEL_1.GTPE2.CFOK_CFG[7] origin:064-gtp-channel-conf 31_395 -GTP_CHANNEL_1.GTPE2.CFOK_CFG[8] origin:064-gtp-channel-conf 30_396 -GTP_CHANNEL_1.GTPE2.CFOK_CFG[9] origin:064-gtp-channel-conf 31_396 -GTP_CHANNEL_1.GTPE2.CFOK_CFG[10] origin:064-gtp-channel-conf 30_397 -GTP_CHANNEL_1.GTPE2.CFOK_CFG[11] origin:064-gtp-channel-conf 31_397 -GTP_CHANNEL_1.GTPE2.CFOK_CFG[12] origin:064-gtp-channel-conf 30_398 -GTP_CHANNEL_1.GTPE2.CFOK_CFG[13] origin:064-gtp-channel-conf 31_398 -GTP_CHANNEL_1.GTPE2.CFOK_CFG[14] origin:064-gtp-channel-conf 30_399 -GTP_CHANNEL_1.GTPE2.CFOK_CFG[15] origin:064-gtp-channel-conf 31_399 -GTP_CHANNEL_1.GTPE2.CFOK_CFG[16] origin:064-gtp-channel-conf 30_400 -GTP_CHANNEL_1.GTPE2.CFOK_CFG[17] origin:064-gtp-channel-conf 31_400 -GTP_CHANNEL_1.GTPE2.CFOK_CFG[18] origin:064-gtp-channel-conf 30_401 -GTP_CHANNEL_1.GTPE2.CFOK_CFG[19] origin:064-gtp-channel-conf 31_401 -GTP_CHANNEL_1.GTPE2.CFOK_CFG[20] origin:064-gtp-channel-conf 30_402 -GTP_CHANNEL_1.GTPE2.CFOK_CFG[21] origin:064-gtp-channel-conf 31_402 -GTP_CHANNEL_1.GTPE2.CFOK_CFG[22] origin:064-gtp-channel-conf 30_403 -GTP_CHANNEL_1.GTPE2.CFOK_CFG[23] origin:064-gtp-channel-conf 31_403 -GTP_CHANNEL_1.GTPE2.CFOK_CFG[24] origin:064-gtp-channel-conf 30_404 -GTP_CHANNEL_1.GTPE2.CFOK_CFG[25] origin:064-gtp-channel-conf 31_404 -GTP_CHANNEL_1.GTPE2.CFOK_CFG[26] origin:064-gtp-channel-conf 30_405 -GTP_CHANNEL_1.GTPE2.CFOK_CFG[27] origin:064-gtp-channel-conf 31_405 -GTP_CHANNEL_1.GTPE2.CFOK_CFG[28] origin:064-gtp-channel-conf 30_406 -GTP_CHANNEL_1.GTPE2.CFOK_CFG[29] origin:064-gtp-channel-conf 31_406 -GTP_CHANNEL_1.GTPE2.CFOK_CFG[30] origin:064-gtp-channel-conf 30_407 -GTP_CHANNEL_1.GTPE2.CFOK_CFG[31] origin:064-gtp-channel-conf 31_407 -GTP_CHANNEL_1.GTPE2.CFOK_CFG[32] origin:064-gtp-channel-conf 30_408 -GTP_CHANNEL_1.GTPE2.CFOK_CFG[33] origin:064-gtp-channel-conf 31_408 -GTP_CHANNEL_1.GTPE2.CFOK_CFG[34] origin:064-gtp-channel-conf 30_409 -GTP_CHANNEL_1.GTPE2.CFOK_CFG[35] origin:064-gtp-channel-conf 31_409 -GTP_CHANNEL_1.GTPE2.CFOK_CFG[36] origin:064-gtp-channel-conf 30_410 -GTP_CHANNEL_1.GTPE2.CFOK_CFG[37] origin:064-gtp-channel-conf 31_410 -GTP_CHANNEL_1.GTPE2.CFOK_CFG[38] origin:064-gtp-channel-conf 30_411 -GTP_CHANNEL_1.GTPE2.CFOK_CFG[39] origin:064-gtp-channel-conf 31_411 -GTP_CHANNEL_1.GTPE2.CFOK_CFG[40] origin:064-gtp-channel-conf 30_412 -GTP_CHANNEL_1.GTPE2.CFOK_CFG[41] origin:064-gtp-channel-conf 31_412 -GTP_CHANNEL_1.GTPE2.CFOK_CFG[42] origin:064-gtp-channel-conf 30_413 -GTP_CHANNEL_1.GTPE2.CFOK_CFG2[0] origin:064-gtp-channel-conf 30_459 -GTP_CHANNEL_1.GTPE2.CFOK_CFG2[1] origin:064-gtp-channel-conf 31_459 -GTP_CHANNEL_1.GTPE2.CFOK_CFG2[2] origin:064-gtp-channel-conf 30_460 -GTP_CHANNEL_1.GTPE2.CFOK_CFG2[3] origin:064-gtp-channel-conf 31_460 -GTP_CHANNEL_1.GTPE2.CFOK_CFG2[4] origin:064-gtp-channel-conf 30_461 -GTP_CHANNEL_1.GTPE2.CFOK_CFG2[5] origin:064-gtp-channel-conf 31_461 -GTP_CHANNEL_1.GTPE2.CFOK_CFG2[6] origin:064-gtp-channel-conf 30_462 -GTP_CHANNEL_1.GTPE2.CFOK_CFG3[0] origin:064-gtp-channel-conf 30_416 -GTP_CHANNEL_1.GTPE2.CFOK_CFG3[1] origin:064-gtp-channel-conf 31_416 -GTP_CHANNEL_1.GTPE2.CFOK_CFG3[2] origin:064-gtp-channel-conf 30_417 -GTP_CHANNEL_1.GTPE2.CFOK_CFG3[3] origin:064-gtp-channel-conf 31_417 -GTP_CHANNEL_1.GTPE2.CFOK_CFG3[4] origin:064-gtp-channel-conf 30_418 -GTP_CHANNEL_1.GTPE2.CFOK_CFG3[5] origin:064-gtp-channel-conf 31_418 -GTP_CHANNEL_1.GTPE2.CFOK_CFG3[6] origin:064-gtp-channel-conf 30_419 -GTP_CHANNEL_1.GTPE2.CFOK_CFG4[0] origin:064-gtp-channel-conf 31_438 -GTP_CHANNEL_1.GTPE2.CFOK_CFG5[0] origin:064-gtp-channel-conf 30_429 -GTP_CHANNEL_1.GTPE2.CFOK_CFG5[1] origin:064-gtp-channel-conf 31_429 -GTP_CHANNEL_1.GTPE2.CFOK_CFG6[0] origin:064-gtp-channel-conf 31_436 -GTP_CHANNEL_1.GTPE2.CFOK_CFG6[1] origin:064-gtp-channel-conf 30_437 -GTP_CHANNEL_1.GTPE2.CFOK_CFG6[2] origin:064-gtp-channel-conf 31_437 -GTP_CHANNEL_1.GTPE2.CFOK_CFG6[3] origin:064-gtp-channel-conf 30_438 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_KEEP_ALIGN origin:064-gtp-channel-conf 29_631 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_MAX_SKEW[0] origin:064-gtp-channel-conf 28_670 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_MAX_SKEW[1] origin:064-gtp-channel-conf 29_670 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_MAX_SKEW[2] origin:064-gtp-channel-conf 28_671 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_MAX_SKEW[3] origin:064-gtp-channel-conf 29_671 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_1_1[0] origin:064-gtp-channel-conf 28_608 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_1_1[1] origin:064-gtp-channel-conf 29_608 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_1_1[2] origin:064-gtp-channel-conf 28_609 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_1_1[3] origin:064-gtp-channel-conf 29_609 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_1_1[4] origin:064-gtp-channel-conf 28_610 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_1_1[5] origin:064-gtp-channel-conf 29_610 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_1_1[6] origin:064-gtp-channel-conf 28_611 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_1_1[7] origin:064-gtp-channel-conf 29_611 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_1_1[8] origin:064-gtp-channel-conf 28_612 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_1_1[9] origin:064-gtp-channel-conf 29_612 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_1_2[0] origin:064-gtp-channel-conf 28_616 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_1_2[1] origin:064-gtp-channel-conf 29_616 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_1_2[2] origin:064-gtp-channel-conf 28_617 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_1_2[3] origin:064-gtp-channel-conf 29_617 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_1_2[4] origin:064-gtp-channel-conf 28_618 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_1_2[5] origin:064-gtp-channel-conf 29_618 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_1_2[6] origin:064-gtp-channel-conf 28_619 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_1_2[7] origin:064-gtp-channel-conf 29_619 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_1_2[8] origin:064-gtp-channel-conf 28_620 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_1_2[9] origin:064-gtp-channel-conf 29_620 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_1_3[0] origin:064-gtp-channel-conf 28_624 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_1_3[1] origin:064-gtp-channel-conf 29_624 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_1_3[2] origin:064-gtp-channel-conf 28_625 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_1_3[3] origin:064-gtp-channel-conf 29_625 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_1_3[4] origin:064-gtp-channel-conf 28_626 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_1_3[5] origin:064-gtp-channel-conf 29_626 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_1_3[6] origin:064-gtp-channel-conf 28_627 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_1_3[7] origin:064-gtp-channel-conf 29_627 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_1_3[8] origin:064-gtp-channel-conf 28_628 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_1_3[9] origin:064-gtp-channel-conf 29_628 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_1_4[0] origin:064-gtp-channel-conf 28_632 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_1_4[1] origin:064-gtp-channel-conf 29_632 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_1_4[2] origin:064-gtp-channel-conf 28_633 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_1_4[3] origin:064-gtp-channel-conf 29_633 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_1_4[4] origin:064-gtp-channel-conf 28_634 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_1_4[5] origin:064-gtp-channel-conf 29_634 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_1_4[6] origin:064-gtp-channel-conf 28_635 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_1_4[7] origin:064-gtp-channel-conf 29_635 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_1_4[8] origin:064-gtp-channel-conf 28_636 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_1_4[9] origin:064-gtp-channel-conf 29_636 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_1_ENABLE[0] origin:064-gtp-channel-conf 28_614 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_1_ENABLE[1] origin:064-gtp-channel-conf 29_614 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_1_ENABLE[2] origin:064-gtp-channel-conf 28_615 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_1_ENABLE[3] origin:064-gtp-channel-conf 29_615 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_2_1[0] origin:064-gtp-channel-conf 28_640 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_2_1[1] origin:064-gtp-channel-conf 29_640 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_2_1[2] origin:064-gtp-channel-conf 28_641 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_2_1[3] origin:064-gtp-channel-conf 29_641 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_2_1[4] origin:064-gtp-channel-conf 28_642 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_2_1[5] origin:064-gtp-channel-conf 29_642 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_2_1[6] origin:064-gtp-channel-conf 28_643 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_2_1[7] origin:064-gtp-channel-conf 29_643 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_2_1[8] origin:064-gtp-channel-conf 28_644 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_2_1[9] origin:064-gtp-channel-conf 29_644 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_2_2[0] origin:064-gtp-channel-conf 28_648 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_2_2[1] origin:064-gtp-channel-conf 29_648 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_2_2[2] origin:064-gtp-channel-conf 28_649 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_2_2[3] origin:064-gtp-channel-conf 29_649 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_2_2[4] origin:064-gtp-channel-conf 28_650 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_2_2[5] origin:064-gtp-channel-conf 29_650 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_2_2[6] origin:064-gtp-channel-conf 28_651 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_2_2[7] origin:064-gtp-channel-conf 29_651 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_2_2[8] origin:064-gtp-channel-conf 28_652 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_2_2[9] origin:064-gtp-channel-conf 29_652 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_2_3[0] origin:064-gtp-channel-conf 28_656 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_2_3[1] origin:064-gtp-channel-conf 29_656 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_2_3[2] origin:064-gtp-channel-conf 28_657 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_2_3[3] origin:064-gtp-channel-conf 29_657 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_2_3[4] origin:064-gtp-channel-conf 28_658 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_2_3[5] origin:064-gtp-channel-conf 29_658 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_2_3[6] origin:064-gtp-channel-conf 28_659 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_2_3[7] origin:064-gtp-channel-conf 29_659 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_2_3[8] origin:064-gtp-channel-conf 28_660 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_2_3[9] origin:064-gtp-channel-conf 29_660 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_2_4[0] origin:064-gtp-channel-conf 28_664 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_2_4[1] origin:064-gtp-channel-conf 29_664 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_2_4[2] origin:064-gtp-channel-conf 28_665 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_2_4[3] origin:064-gtp-channel-conf 29_665 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_2_4[4] origin:064-gtp-channel-conf 28_666 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_2_4[5] origin:064-gtp-channel-conf 29_666 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_2_4[6] origin:064-gtp-channel-conf 28_667 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_2_4[7] origin:064-gtp-channel-conf 29_667 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_2_4[8] origin:064-gtp-channel-conf 28_668 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_2_4[9] origin:064-gtp-channel-conf 29_668 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_2_ENABLE[0] origin:064-gtp-channel-conf 28_646 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_2_ENABLE[1] origin:064-gtp-channel-conf 29_646 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_2_ENABLE[2] origin:064-gtp-channel-conf 28_647 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_2_ENABLE[3] origin:064-gtp-channel-conf 29_647 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_2_USE origin:064-gtp-channel-conf 29_645 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_LEN[0] origin:064-gtp-channel-conf 28_623 -GTP_CHANNEL_1.GTPE2.CHAN_BOND_SEQ_LEN[1] origin:064-gtp-channel-conf 29_623 -GTP_CHANNEL_1.GTPE2.CLK_COMMON_SWING[0] origin:064-gtp-channel-conf 31_311 -GTP_CHANNEL_1.GTPE2.CLK_COR_KEEP_IDLE origin:064-gtp-channel-conf 28_591 -GTP_CHANNEL_1.GTPE2.CLK_COR_MAX_LAT[0] origin:064-gtp-channel-conf 28_557 -GTP_CHANNEL_1.GTPE2.CLK_COR_MAX_LAT[1] origin:064-gtp-channel-conf 29_557 -GTP_CHANNEL_1.GTPE2.CLK_COR_MAX_LAT[2] origin:064-gtp-channel-conf 28_558 -GTP_CHANNEL_1.GTPE2.CLK_COR_MAX_LAT[3] origin:064-gtp-channel-conf 29_558 -GTP_CHANNEL_1.GTPE2.CLK_COR_MAX_LAT[4] origin:064-gtp-channel-conf 28_559 -GTP_CHANNEL_1.GTPE2.CLK_COR_MAX_LAT[5] origin:064-gtp-channel-conf 29_559 -GTP_CHANNEL_1.GTPE2.CLK_COR_MIN_LAT[0] origin:064-gtp-channel-conf 28_565 -GTP_CHANNEL_1.GTPE2.CLK_COR_MIN_LAT[1] origin:064-gtp-channel-conf 29_565 -GTP_CHANNEL_1.GTPE2.CLK_COR_MIN_LAT[2] origin:064-gtp-channel-conf 28_566 -GTP_CHANNEL_1.GTPE2.CLK_COR_MIN_LAT[3] origin:064-gtp-channel-conf 29_566 -GTP_CHANNEL_1.GTPE2.CLK_COR_MIN_LAT[4] origin:064-gtp-channel-conf 28_567 -GTP_CHANNEL_1.GTPE2.CLK_COR_MIN_LAT[5] origin:064-gtp-channel-conf 29_567 -GTP_CHANNEL_1.GTPE2.CLK_COR_PRECEDENCE origin:064-gtp-channel-conf 28_590 -GTP_CHANNEL_1.GTPE2.CLK_COR_REPEAT_WAIT[0] origin:064-gtp-channel-conf 28_573 -GTP_CHANNEL_1.GTPE2.CLK_COR_REPEAT_WAIT[1] origin:064-gtp-channel-conf 29_573 -GTP_CHANNEL_1.GTPE2.CLK_COR_REPEAT_WAIT[2] origin:064-gtp-channel-conf 28_574 -GTP_CHANNEL_1.GTPE2.CLK_COR_REPEAT_WAIT[3] origin:064-gtp-channel-conf 29_574 -GTP_CHANNEL_1.GTPE2.CLK_COR_REPEAT_WAIT[4] origin:064-gtp-channel-conf 28_575 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_1_1[0] origin:064-gtp-channel-conf 28_544 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_1_1[1] origin:064-gtp-channel-conf 29_544 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_1_1[2] origin:064-gtp-channel-conf 28_545 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_1_1[3] origin:064-gtp-channel-conf 29_545 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_1_1[4] origin:064-gtp-channel-conf 28_546 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_1_1[5] origin:064-gtp-channel-conf 29_546 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_1_1[6] origin:064-gtp-channel-conf 28_547 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_1_1[7] origin:064-gtp-channel-conf 29_547 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_1_1[8] origin:064-gtp-channel-conf 28_548 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_1_1[9] origin:064-gtp-channel-conf 29_548 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_1_2[0] origin:064-gtp-channel-conf 28_552 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_1_2[1] origin:064-gtp-channel-conf 29_552 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_1_2[2] origin:064-gtp-channel-conf 28_553 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_1_2[3] origin:064-gtp-channel-conf 29_553 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_1_2[4] origin:064-gtp-channel-conf 28_554 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_1_2[5] origin:064-gtp-channel-conf 29_554 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_1_2[6] origin:064-gtp-channel-conf 28_555 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_1_2[7] origin:064-gtp-channel-conf 29_555 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_1_2[8] origin:064-gtp-channel-conf 28_556 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_1_2[9] origin:064-gtp-channel-conf 29_556 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_1_3[0] origin:064-gtp-channel-conf 28_560 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_1_3[1] origin:064-gtp-channel-conf 29_560 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_1_3[2] origin:064-gtp-channel-conf 28_561 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_1_3[3] origin:064-gtp-channel-conf 29_561 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_1_3[4] origin:064-gtp-channel-conf 28_562 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_1_3[5] origin:064-gtp-channel-conf 29_562 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_1_3[6] origin:064-gtp-channel-conf 28_563 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_1_3[7] origin:064-gtp-channel-conf 29_563 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_1_3[8] origin:064-gtp-channel-conf 28_564 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_1_3[9] origin:064-gtp-channel-conf 29_564 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_1_4[0] origin:064-gtp-channel-conf 28_568 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_1_4[1] origin:064-gtp-channel-conf 29_568 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_1_4[2] origin:064-gtp-channel-conf 28_569 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_1_4[3] origin:064-gtp-channel-conf 29_569 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_1_4[4] origin:064-gtp-channel-conf 28_570 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_1_4[5] origin:064-gtp-channel-conf 29_570 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_1_4[6] origin:064-gtp-channel-conf 28_571 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_1_4[7] origin:064-gtp-channel-conf 29_571 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_1_4[8] origin:064-gtp-channel-conf 28_572 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_1_4[9] origin:064-gtp-channel-conf 29_572 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_1_ENABLE[0] origin:064-gtp-channel-conf 28_549 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_1_ENABLE[1] origin:064-gtp-channel-conf 29_549 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_1_ENABLE[2] origin:064-gtp-channel-conf 28_550 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_1_ENABLE[3] origin:064-gtp-channel-conf 29_550 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_2_1[0] origin:064-gtp-channel-conf 28_576 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_2_1[1] origin:064-gtp-channel-conf 29_576 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_2_1[2] origin:064-gtp-channel-conf 28_577 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_2_1[3] origin:064-gtp-channel-conf 29_577 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_2_1[4] origin:064-gtp-channel-conf 28_578 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_2_1[5] origin:064-gtp-channel-conf 29_578 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_2_1[6] origin:064-gtp-channel-conf 28_579 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_2_1[7] origin:064-gtp-channel-conf 29_579 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_2_1[8] origin:064-gtp-channel-conf 28_580 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_2_1[9] origin:064-gtp-channel-conf 29_580 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_2_2[0] origin:064-gtp-channel-conf 28_584 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_2_2[1] origin:064-gtp-channel-conf 29_584 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_2_2[2] origin:064-gtp-channel-conf 28_585 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_2_2[3] origin:064-gtp-channel-conf 29_585 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_2_2[4] origin:064-gtp-channel-conf 28_586 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_2_2[5] origin:064-gtp-channel-conf 29_586 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_2_2[6] origin:064-gtp-channel-conf 28_587 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_2_2[7] origin:064-gtp-channel-conf 29_587 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_2_2[8] origin:064-gtp-channel-conf 28_588 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_2_2[9] origin:064-gtp-channel-conf 29_588 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_2_3[0] origin:064-gtp-channel-conf 28_592 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_2_3[1] origin:064-gtp-channel-conf 29_592 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_2_3[2] origin:064-gtp-channel-conf 28_593 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_2_3[3] origin:064-gtp-channel-conf 29_593 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_2_3[4] origin:064-gtp-channel-conf 28_594 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_2_3[5] origin:064-gtp-channel-conf 29_594 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_2_3[6] origin:064-gtp-channel-conf 28_595 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_2_3[7] origin:064-gtp-channel-conf 29_595 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_2_3[8] origin:064-gtp-channel-conf 28_596 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_2_3[9] origin:064-gtp-channel-conf 29_596 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_2_4[0] origin:064-gtp-channel-conf 28_600 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_2_4[1] origin:064-gtp-channel-conf 29_600 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_2_4[2] origin:064-gtp-channel-conf 28_601 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_2_4[3] origin:064-gtp-channel-conf 29_601 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_2_4[4] origin:064-gtp-channel-conf 28_602 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_2_4[5] origin:064-gtp-channel-conf 29_602 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_2_4[6] origin:064-gtp-channel-conf 28_603 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_2_4[7] origin:064-gtp-channel-conf 29_603 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_2_4[8] origin:064-gtp-channel-conf 28_604 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_2_4[9] origin:064-gtp-channel-conf 29_604 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_2_ENABLE[0] origin:064-gtp-channel-conf 28_581 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_2_ENABLE[1] origin:064-gtp-channel-conf 29_581 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_2_ENABLE[2] origin:064-gtp-channel-conf 28_582 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_2_ENABLE[3] origin:064-gtp-channel-conf 29_582 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_2_USE origin:064-gtp-channel-conf 28_583 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_LEN[0] origin:064-gtp-channel-conf 28_589 -GTP_CHANNEL_1.GTPE2.CLK_COR_SEQ_LEN[1] origin:064-gtp-channel-conf 29_589 -GTP_CHANNEL_1.GTPE2.CLK_CORRECT_USE origin:064-gtp-channel-conf 28_551 -GTP_CHANNEL_1.GTPE2.DEC_MCOMMA_DETECT origin:064-gtp-channel-conf 29_494 -GTP_CHANNEL_1.GTPE2.DEC_PCOMMA_DETECT origin:064-gtp-channel-conf 28_495 -GTP_CHANNEL_1.GTPE2.DEC_VALID_COMMA_ONLY origin:064-gtp-channel-conf 28_494 -GTP_CHANNEL_1.GTPE2.DMONITOR_CFG[0] origin:064-gtp-channel-conf 30_368 -GTP_CHANNEL_1.GTPE2.DMONITOR_CFG[1] origin:064-gtp-channel-conf 31_368 -GTP_CHANNEL_1.GTPE2.DMONITOR_CFG[2] origin:064-gtp-channel-conf 30_369 -GTP_CHANNEL_1.GTPE2.DMONITOR_CFG[3] origin:064-gtp-channel-conf 31_369 -GTP_CHANNEL_1.GTPE2.DMONITOR_CFG[4] origin:064-gtp-channel-conf 30_370 -GTP_CHANNEL_1.GTPE2.DMONITOR_CFG[5] origin:064-gtp-channel-conf 31_370 -GTP_CHANNEL_1.GTPE2.DMONITOR_CFG[6] origin:064-gtp-channel-conf 30_371 -GTP_CHANNEL_1.GTPE2.DMONITOR_CFG[7] origin:064-gtp-channel-conf 31_371 -GTP_CHANNEL_1.GTPE2.DMONITOR_CFG[8] origin:064-gtp-channel-conf 30_372 -GTP_CHANNEL_1.GTPE2.DMONITOR_CFG[9] origin:064-gtp-channel-conf 31_372 -GTP_CHANNEL_1.GTPE2.DMONITOR_CFG[10] origin:064-gtp-channel-conf 30_373 -GTP_CHANNEL_1.GTPE2.DMONITOR_CFG[11] origin:064-gtp-channel-conf 31_373 -GTP_CHANNEL_1.GTPE2.DMONITOR_CFG[12] origin:064-gtp-channel-conf 30_374 -GTP_CHANNEL_1.GTPE2.DMONITOR_CFG[13] origin:064-gtp-channel-conf 31_374 -GTP_CHANNEL_1.GTPE2.DMONITOR_CFG[14] origin:064-gtp-channel-conf 30_375 -GTP_CHANNEL_1.GTPE2.DMONITOR_CFG[15] origin:064-gtp-channel-conf 31_375 -GTP_CHANNEL_1.GTPE2.DMONITOR_CFG[16] origin:064-gtp-channel-conf 30_376 -GTP_CHANNEL_1.GTPE2.DMONITOR_CFG[17] origin:064-gtp-channel-conf 31_376 -GTP_CHANNEL_1.GTPE2.DMONITOR_CFG[18] origin:064-gtp-channel-conf 30_377 -GTP_CHANNEL_1.GTPE2.DMONITOR_CFG[19] origin:064-gtp-channel-conf 31_377 -GTP_CHANNEL_1.GTPE2.DMONITOR_CFG[20] origin:064-gtp-channel-conf 30_378 -GTP_CHANNEL_1.GTPE2.DMONITOR_CFG[21] origin:064-gtp-channel-conf 31_378 -GTP_CHANNEL_1.GTPE2.DMONITOR_CFG[22] origin:064-gtp-channel-conf 30_379 -GTP_CHANNEL_1.GTPE2.DMONITOR_CFG[23] origin:064-gtp-channel-conf 31_379 -GTP_CHANNEL_1.GTPE2.ES_CLK_PHASE_SEL[0] origin:064-gtp-channel-conf 31_463 -GTP_CHANNEL_1.GTPE2.ES_CONTROL[0] origin:064-gtp-channel-conf 28_488 -GTP_CHANNEL_1.GTPE2.ES_CONTROL[1] origin:064-gtp-channel-conf 29_488 -GTP_CHANNEL_1.GTPE2.ES_CONTROL[2] origin:064-gtp-channel-conf 28_489 -GTP_CHANNEL_1.GTPE2.ES_CONTROL[3] origin:064-gtp-channel-conf 29_489 -GTP_CHANNEL_1.GTPE2.ES_CONTROL[4] origin:064-gtp-channel-conf 28_490 -GTP_CHANNEL_1.GTPE2.ES_CONTROL[5] origin:064-gtp-channel-conf 29_490 -GTP_CHANNEL_1.GTPE2.ES_ERRDET_EN origin:064-gtp-channel-conf 29_492 -GTP_CHANNEL_1.GTPE2.ES_EYE_SCAN_EN origin:064-gtp-channel-conf 28_492 -GTP_CHANNEL_1.GTPE2.ES_HORZ_OFFSET[0] origin:064-gtp-channel-conf 28_480 -GTP_CHANNEL_1.GTPE2.ES_HORZ_OFFSET[1] origin:064-gtp-channel-conf 29_480 -GTP_CHANNEL_1.GTPE2.ES_HORZ_OFFSET[2] origin:064-gtp-channel-conf 28_481 -GTP_CHANNEL_1.GTPE2.ES_HORZ_OFFSET[3] origin:064-gtp-channel-conf 29_481 -GTP_CHANNEL_1.GTPE2.ES_HORZ_OFFSET[4] origin:064-gtp-channel-conf 28_482 -GTP_CHANNEL_1.GTPE2.ES_HORZ_OFFSET[5] origin:064-gtp-channel-conf 29_482 -GTP_CHANNEL_1.GTPE2.ES_HORZ_OFFSET[6] origin:064-gtp-channel-conf 28_483 -GTP_CHANNEL_1.GTPE2.ES_HORZ_OFFSET[7] origin:064-gtp-channel-conf 29_483 -GTP_CHANNEL_1.GTPE2.ES_HORZ_OFFSET[8] origin:064-gtp-channel-conf 28_484 -GTP_CHANNEL_1.GTPE2.ES_HORZ_OFFSET[9] origin:064-gtp-channel-conf 29_484 -GTP_CHANNEL_1.GTPE2.ES_HORZ_OFFSET[10] origin:064-gtp-channel-conf 28_485 -GTP_CHANNEL_1.GTPE2.ES_HORZ_OFFSET[11] origin:064-gtp-channel-conf 29_485 -GTP_CHANNEL_1.GTPE2.ES_PMA_CFG[0] origin:064-gtp-channel-conf 30_624 -GTP_CHANNEL_1.GTPE2.ES_PMA_CFG[1] origin:064-gtp-channel-conf 31_624 -GTP_CHANNEL_1.GTPE2.ES_PMA_CFG[2] origin:064-gtp-channel-conf 30_625 -GTP_CHANNEL_1.GTPE2.ES_PMA_CFG[3] origin:064-gtp-channel-conf 31_625 -GTP_CHANNEL_1.GTPE2.ES_PMA_CFG[4] origin:064-gtp-channel-conf 30_626 -GTP_CHANNEL_1.GTPE2.ES_PMA_CFG[5] origin:064-gtp-channel-conf 31_626 -GTP_CHANNEL_1.GTPE2.ES_PMA_CFG[6] origin:064-gtp-channel-conf 30_627 -GTP_CHANNEL_1.GTPE2.ES_PMA_CFG[7] origin:064-gtp-channel-conf 31_627 -GTP_CHANNEL_1.GTPE2.ES_PMA_CFG[8] origin:064-gtp-channel-conf 30_628 -GTP_CHANNEL_1.GTPE2.ES_PMA_CFG[9] origin:064-gtp-channel-conf 31_628 -GTP_CHANNEL_1.GTPE2.ES_PRESCALE[0] origin:064-gtp-channel-conf 29_477 -GTP_CHANNEL_1.GTPE2.ES_PRESCALE[1] origin:064-gtp-channel-conf 28_478 -GTP_CHANNEL_1.GTPE2.ES_PRESCALE[2] origin:064-gtp-channel-conf 29_478 -GTP_CHANNEL_1.GTPE2.ES_PRESCALE[3] origin:064-gtp-channel-conf 28_479 -GTP_CHANNEL_1.GTPE2.ES_PRESCALE[4] origin:064-gtp-channel-conf 29_479 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[0] origin:064-gtp-channel-conf 28_392 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[1] origin:064-gtp-channel-conf 29_392 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[2] origin:064-gtp-channel-conf 28_393 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[3] origin:064-gtp-channel-conf 29_393 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[4] origin:064-gtp-channel-conf 28_394 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[5] origin:064-gtp-channel-conf 29_394 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[6] origin:064-gtp-channel-conf 28_395 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[7] origin:064-gtp-channel-conf 29_395 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[8] origin:064-gtp-channel-conf 28_396 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[9] origin:064-gtp-channel-conf 29_396 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[10] origin:064-gtp-channel-conf 28_397 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[11] origin:064-gtp-channel-conf 29_397 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[12] origin:064-gtp-channel-conf 28_398 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[13] origin:064-gtp-channel-conf 29_398 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[14] origin:064-gtp-channel-conf 28_399 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[15] origin:064-gtp-channel-conf 29_399 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[16] origin:064-gtp-channel-conf 28_400 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[17] origin:064-gtp-channel-conf 29_400 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[18] origin:064-gtp-channel-conf 28_401 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[19] origin:064-gtp-channel-conf 29_401 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[20] origin:064-gtp-channel-conf 28_402 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[21] origin:064-gtp-channel-conf 29_402 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[22] origin:064-gtp-channel-conf 28_403 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[23] origin:064-gtp-channel-conf 29_403 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[24] origin:064-gtp-channel-conf 28_404 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[25] origin:064-gtp-channel-conf 29_404 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[26] origin:064-gtp-channel-conf 28_405 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[27] origin:064-gtp-channel-conf 29_405 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[28] origin:064-gtp-channel-conf 28_406 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[29] origin:064-gtp-channel-conf 29_406 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[30] origin:064-gtp-channel-conf 28_407 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[31] origin:064-gtp-channel-conf 29_407 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[32] origin:064-gtp-channel-conf 28_408 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[33] origin:064-gtp-channel-conf 29_408 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[34] origin:064-gtp-channel-conf 28_409 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[35] origin:064-gtp-channel-conf 29_409 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[36] origin:064-gtp-channel-conf 28_410 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[37] origin:064-gtp-channel-conf 29_410 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[38] origin:064-gtp-channel-conf 28_411 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[39] origin:064-gtp-channel-conf 29_411 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[40] origin:064-gtp-channel-conf 28_412 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[41] origin:064-gtp-channel-conf 29_412 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[42] origin:064-gtp-channel-conf 28_413 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[43] origin:064-gtp-channel-conf 29_413 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[44] origin:064-gtp-channel-conf 28_414 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[45] origin:064-gtp-channel-conf 29_414 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[46] origin:064-gtp-channel-conf 28_415 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[47] origin:064-gtp-channel-conf 29_415 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[48] origin:064-gtp-channel-conf 28_416 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[49] origin:064-gtp-channel-conf 29_416 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[50] origin:064-gtp-channel-conf 28_417 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[51] origin:064-gtp-channel-conf 29_417 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[52] origin:064-gtp-channel-conf 28_418 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[53] origin:064-gtp-channel-conf 29_418 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[54] origin:064-gtp-channel-conf 28_419 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[55] origin:064-gtp-channel-conf 29_419 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[56] origin:064-gtp-channel-conf 28_420 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[57] origin:064-gtp-channel-conf 29_420 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[58] origin:064-gtp-channel-conf 28_421 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[59] origin:064-gtp-channel-conf 29_421 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[60] origin:064-gtp-channel-conf 28_422 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[61] origin:064-gtp-channel-conf 29_422 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[62] origin:064-gtp-channel-conf 28_423 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[63] origin:064-gtp-channel-conf 29_423 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[64] origin:064-gtp-channel-conf 28_424 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[65] origin:064-gtp-channel-conf 29_424 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[66] origin:064-gtp-channel-conf 28_425 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[67] origin:064-gtp-channel-conf 29_425 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[68] origin:064-gtp-channel-conf 28_426 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[69] origin:064-gtp-channel-conf 29_426 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[70] origin:064-gtp-channel-conf 28_427 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[71] origin:064-gtp-channel-conf 29_427 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[72] origin:064-gtp-channel-conf 28_428 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[73] origin:064-gtp-channel-conf 29_428 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[74] origin:064-gtp-channel-conf 28_429 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[75] origin:064-gtp-channel-conf 29_429 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[76] origin:064-gtp-channel-conf 28_430 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[77] origin:064-gtp-channel-conf 29_430 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[78] origin:064-gtp-channel-conf 28_431 -GTP_CHANNEL_1.GTPE2.ES_QUAL_MASK[79] origin:064-gtp-channel-conf 29_431 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[0] origin:064-gtp-channel-conf 28_352 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[1] origin:064-gtp-channel-conf 29_352 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[2] origin:064-gtp-channel-conf 28_353 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[3] origin:064-gtp-channel-conf 29_353 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[4] origin:064-gtp-channel-conf 28_354 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[5] origin:064-gtp-channel-conf 29_354 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[6] origin:064-gtp-channel-conf 28_355 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[7] origin:064-gtp-channel-conf 29_355 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[8] origin:064-gtp-channel-conf 28_356 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[9] origin:064-gtp-channel-conf 29_356 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[10] origin:064-gtp-channel-conf 28_357 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[11] origin:064-gtp-channel-conf 29_357 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[12] origin:064-gtp-channel-conf 28_358 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[13] origin:064-gtp-channel-conf 29_358 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[14] origin:064-gtp-channel-conf 28_359 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[15] origin:064-gtp-channel-conf 29_359 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[16] origin:064-gtp-channel-conf 28_360 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[17] origin:064-gtp-channel-conf 29_360 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[18] origin:064-gtp-channel-conf 28_361 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[19] origin:064-gtp-channel-conf 29_361 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[20] origin:064-gtp-channel-conf 28_362 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[21] origin:064-gtp-channel-conf 29_362 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[22] origin:064-gtp-channel-conf 28_363 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[23] origin:064-gtp-channel-conf 29_363 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[24] origin:064-gtp-channel-conf 28_364 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[25] origin:064-gtp-channel-conf 29_364 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[26] origin:064-gtp-channel-conf 28_365 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[27] origin:064-gtp-channel-conf 29_365 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[28] origin:064-gtp-channel-conf 28_366 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[29] origin:064-gtp-channel-conf 29_366 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[30] origin:064-gtp-channel-conf 28_367 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[31] origin:064-gtp-channel-conf 29_367 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[32] origin:064-gtp-channel-conf 28_368 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[33] origin:064-gtp-channel-conf 29_368 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[34] origin:064-gtp-channel-conf 28_369 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[35] origin:064-gtp-channel-conf 29_369 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[36] origin:064-gtp-channel-conf 28_370 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[37] origin:064-gtp-channel-conf 29_370 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[38] origin:064-gtp-channel-conf 28_371 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[39] origin:064-gtp-channel-conf 29_371 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[40] origin:064-gtp-channel-conf 28_372 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[41] origin:064-gtp-channel-conf 29_372 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[42] origin:064-gtp-channel-conf 28_373 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[43] origin:064-gtp-channel-conf 29_373 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[44] origin:064-gtp-channel-conf 28_374 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[45] origin:064-gtp-channel-conf 29_374 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[46] origin:064-gtp-channel-conf 28_375 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[47] origin:064-gtp-channel-conf 29_375 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[48] origin:064-gtp-channel-conf 28_376 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[49] origin:064-gtp-channel-conf 29_376 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[50] origin:064-gtp-channel-conf 28_377 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[51] origin:064-gtp-channel-conf 29_377 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[52] origin:064-gtp-channel-conf 28_378 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[53] origin:064-gtp-channel-conf 29_378 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[54] origin:064-gtp-channel-conf 28_379 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[55] origin:064-gtp-channel-conf 29_379 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[56] origin:064-gtp-channel-conf 28_380 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[57] origin:064-gtp-channel-conf 29_380 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[58] origin:064-gtp-channel-conf 28_381 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[59] origin:064-gtp-channel-conf 29_381 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[60] origin:064-gtp-channel-conf 28_382 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[61] origin:064-gtp-channel-conf 29_382 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[62] origin:064-gtp-channel-conf 28_383 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[63] origin:064-gtp-channel-conf 29_383 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[64] origin:064-gtp-channel-conf 28_384 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[65] origin:064-gtp-channel-conf 29_384 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[66] origin:064-gtp-channel-conf 28_385 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[67] origin:064-gtp-channel-conf 29_385 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[68] origin:064-gtp-channel-conf 28_386 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[69] origin:064-gtp-channel-conf 29_386 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[70] origin:064-gtp-channel-conf 28_387 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[71] origin:064-gtp-channel-conf 29_387 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[72] origin:064-gtp-channel-conf 28_388 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[73] origin:064-gtp-channel-conf 29_388 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[74] origin:064-gtp-channel-conf 28_389 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[75] origin:064-gtp-channel-conf 29_389 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[76] origin:064-gtp-channel-conf 28_390 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[77] origin:064-gtp-channel-conf 29_390 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[78] origin:064-gtp-channel-conf 28_391 -GTP_CHANNEL_1.GTPE2.ES_QUALIFIER[79] origin:064-gtp-channel-conf 29_391 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[0] origin:064-gtp-channel-conf 28_432 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[1] origin:064-gtp-channel-conf 29_432 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[2] origin:064-gtp-channel-conf 28_433 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[3] origin:064-gtp-channel-conf 29_433 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[4] origin:064-gtp-channel-conf 28_434 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[5] origin:064-gtp-channel-conf 29_434 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[6] origin:064-gtp-channel-conf 28_435 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[7] origin:064-gtp-channel-conf 29_435 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[8] origin:064-gtp-channel-conf 28_436 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[9] origin:064-gtp-channel-conf 29_436 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[10] origin:064-gtp-channel-conf 28_437 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[11] origin:064-gtp-channel-conf 29_437 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[12] origin:064-gtp-channel-conf 28_438 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[13] origin:064-gtp-channel-conf 29_438 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[14] origin:064-gtp-channel-conf 28_439 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[15] origin:064-gtp-channel-conf 29_439 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[16] origin:064-gtp-channel-conf 28_440 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[17] origin:064-gtp-channel-conf 29_440 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[18] origin:064-gtp-channel-conf 28_441 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[19] origin:064-gtp-channel-conf 29_441 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[20] origin:064-gtp-channel-conf 28_442 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[21] origin:064-gtp-channel-conf 29_442 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[22] origin:064-gtp-channel-conf 28_443 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[23] origin:064-gtp-channel-conf 29_443 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[24] origin:064-gtp-channel-conf 28_444 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[25] origin:064-gtp-channel-conf 29_444 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[26] origin:064-gtp-channel-conf 28_445 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[27] origin:064-gtp-channel-conf 29_445 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[28] origin:064-gtp-channel-conf 28_446 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[29] origin:064-gtp-channel-conf 29_446 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[30] origin:064-gtp-channel-conf 28_447 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[31] origin:064-gtp-channel-conf 29_447 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[32] origin:064-gtp-channel-conf 28_448 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[33] origin:064-gtp-channel-conf 29_448 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[34] origin:064-gtp-channel-conf 28_449 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[35] origin:064-gtp-channel-conf 29_449 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[36] origin:064-gtp-channel-conf 28_450 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[37] origin:064-gtp-channel-conf 29_450 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[38] origin:064-gtp-channel-conf 28_451 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[39] origin:064-gtp-channel-conf 29_451 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[40] origin:064-gtp-channel-conf 28_452 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[41] origin:064-gtp-channel-conf 29_452 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[42] origin:064-gtp-channel-conf 28_453 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[43] origin:064-gtp-channel-conf 29_453 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[44] origin:064-gtp-channel-conf 28_454 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[45] origin:064-gtp-channel-conf 29_454 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[46] origin:064-gtp-channel-conf 28_455 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[47] origin:064-gtp-channel-conf 29_455 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[48] origin:064-gtp-channel-conf 28_456 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[49] origin:064-gtp-channel-conf 29_456 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[50] origin:064-gtp-channel-conf 28_457 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[51] origin:064-gtp-channel-conf 29_457 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[52] origin:064-gtp-channel-conf 28_458 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[53] origin:064-gtp-channel-conf 29_458 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[54] origin:064-gtp-channel-conf 28_459 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[55] origin:064-gtp-channel-conf 29_459 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[56] origin:064-gtp-channel-conf 28_460 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[57] origin:064-gtp-channel-conf 29_460 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[58] origin:064-gtp-channel-conf 28_461 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[59] origin:064-gtp-channel-conf 29_461 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[60] origin:064-gtp-channel-conf 28_462 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[61] origin:064-gtp-channel-conf 29_462 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[62] origin:064-gtp-channel-conf 28_463 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[63] origin:064-gtp-channel-conf 29_463 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[64] origin:064-gtp-channel-conf 28_464 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[65] origin:064-gtp-channel-conf 29_464 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[66] origin:064-gtp-channel-conf 28_465 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[67] origin:064-gtp-channel-conf 29_465 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[68] origin:064-gtp-channel-conf 28_466 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[69] origin:064-gtp-channel-conf 29_466 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[70] origin:064-gtp-channel-conf 28_467 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[71] origin:064-gtp-channel-conf 29_467 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[72] origin:064-gtp-channel-conf 28_468 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[73] origin:064-gtp-channel-conf 29_468 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[74] origin:064-gtp-channel-conf 28_469 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[75] origin:064-gtp-channel-conf 29_469 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[76] origin:064-gtp-channel-conf 28_470 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[77] origin:064-gtp-channel-conf 29_470 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[78] origin:064-gtp-channel-conf 28_471 -GTP_CHANNEL_1.GTPE2.ES_SDATA_MASK[79] origin:064-gtp-channel-conf 29_471 -GTP_CHANNEL_1.GTPE2.ES_VERT_OFFSET[0] origin:064-gtp-channel-conf 28_472 -GTP_CHANNEL_1.GTPE2.ES_VERT_OFFSET[1] origin:064-gtp-channel-conf 29_472 -GTP_CHANNEL_1.GTPE2.ES_VERT_OFFSET[2] origin:064-gtp-channel-conf 28_473 -GTP_CHANNEL_1.GTPE2.ES_VERT_OFFSET[3] origin:064-gtp-channel-conf 29_473 -GTP_CHANNEL_1.GTPE2.ES_VERT_OFFSET[4] origin:064-gtp-channel-conf 28_474 -GTP_CHANNEL_1.GTPE2.ES_VERT_OFFSET[5] origin:064-gtp-channel-conf 29_474 -GTP_CHANNEL_1.GTPE2.ES_VERT_OFFSET[6] origin:064-gtp-channel-conf 28_475 -GTP_CHANNEL_1.GTPE2.ES_VERT_OFFSET[7] origin:064-gtp-channel-conf 29_475 -GTP_CHANNEL_1.GTPE2.ES_VERT_OFFSET[8] origin:064-gtp-channel-conf 28_476 -GTP_CHANNEL_1.GTPE2.FTS_DESKEW_SEQ_ENABLE[0] origin:064-gtp-channel-conf 28_662 -GTP_CHANNEL_1.GTPE2.FTS_DESKEW_SEQ_ENABLE[1] origin:064-gtp-channel-conf 29_662 -GTP_CHANNEL_1.GTPE2.FTS_DESKEW_SEQ_ENABLE[2] origin:064-gtp-channel-conf 28_663 -GTP_CHANNEL_1.GTPE2.FTS_DESKEW_SEQ_ENABLE[3] origin:064-gtp-channel-conf 29_663 -GTP_CHANNEL_1.GTPE2.FTS_LANE_DESKEW_CFG[0] origin:064-gtp-channel-conf 28_654 -GTP_CHANNEL_1.GTPE2.FTS_LANE_DESKEW_CFG[1] origin:064-gtp-channel-conf 29_654 -GTP_CHANNEL_1.GTPE2.FTS_LANE_DESKEW_CFG[2] origin:064-gtp-channel-conf 28_655 -GTP_CHANNEL_1.GTPE2.FTS_LANE_DESKEW_CFG[3] origin:064-gtp-channel-conf 29_655 -GTP_CHANNEL_1.GTPE2.FTS_LANE_DESKEW_EN origin:064-gtp-channel-conf 29_653 -GTP_CHANNEL_1.GTPE2.GEARBOX_MODE[0] origin:064-gtp-channel-conf 28_224 -GTP_CHANNEL_1.GTPE2.GEARBOX_MODE[1] origin:064-gtp-channel-conf 29_224 -GTP_CHANNEL_1.GTPE2.GEARBOX_MODE[2] origin:064-gtp-channel-conf 28_225 -GTP_CHANNEL_1.GTPE2.IN_USE origin:064-gtp-channel-conf 28_00 28_01 28_47 28_52 28_53 28_65 29_01 29_47 30_129 -GTP_CHANNEL_1.GTPE2.LOOPBACK_CFG[0] origin:064-gtp-channel-conf 30_20 -GTP_CHANNEL_1.GTPE2.OUTREFCLK_SEL_INV[0] origin:064-gtp-channel-conf 28_149 -GTP_CHANNEL_1.GTPE2.OUTREFCLK_SEL_INV[1] origin:064-gtp-channel-conf 29_149 -GTP_CHANNEL_1.GTPE2.PCS_PCIE_EN origin:064-gtp-channel-conf 28_216 -GTP_CHANNEL_1.GTPE2.PCS_RSVD_ATTR[0] origin:064-gtp-channel-conf 30_184 -GTP_CHANNEL_1.GTPE2.PCS_RSVD_ATTR[1] origin:064-gtp-channel-conf 31_184 -GTP_CHANNEL_1.GTPE2.PCS_RSVD_ATTR[2] origin:064-gtp-channel-conf 30_185 -GTP_CHANNEL_1.GTPE2.PCS_RSVD_ATTR[3] origin:064-gtp-channel-conf 31_185 -GTP_CHANNEL_1.GTPE2.PCS_RSVD_ATTR[4] origin:064-gtp-channel-conf 30_186 -GTP_CHANNEL_1.GTPE2.PCS_RSVD_ATTR[5] origin:064-gtp-channel-conf 31_186 -GTP_CHANNEL_1.GTPE2.PCS_RSVD_ATTR[6] origin:064-gtp-channel-conf 30_187 -GTP_CHANNEL_1.GTPE2.PCS_RSVD_ATTR[7] origin:064-gtp-channel-conf 31_187 -GTP_CHANNEL_1.GTPE2.PCS_RSVD_ATTR[8] origin:064-gtp-channel-conf 30_188 -GTP_CHANNEL_1.GTPE2.PCS_RSVD_ATTR[9] origin:064-gtp-channel-conf 31_188 -GTP_CHANNEL_1.GTPE2.PCS_RSVD_ATTR[10] origin:064-gtp-channel-conf 30_189 -GTP_CHANNEL_1.GTPE2.PCS_RSVD_ATTR[11] origin:064-gtp-channel-conf 31_189 -GTP_CHANNEL_1.GTPE2.PCS_RSVD_ATTR[12] origin:064-gtp-channel-conf 30_190 -GTP_CHANNEL_1.GTPE2.PCS_RSVD_ATTR[13] origin:064-gtp-channel-conf 31_190 -GTP_CHANNEL_1.GTPE2.PCS_RSVD_ATTR[14] origin:064-gtp-channel-conf 30_191 -GTP_CHANNEL_1.GTPE2.PCS_RSVD_ATTR[15] origin:064-gtp-channel-conf 31_191 -GTP_CHANNEL_1.GTPE2.PCS_RSVD_ATTR[16] origin:064-gtp-channel-conf 30_192 -GTP_CHANNEL_1.GTPE2.PCS_RSVD_ATTR[17] origin:064-gtp-channel-conf 31_192 -GTP_CHANNEL_1.GTPE2.PCS_RSVD_ATTR[18] origin:064-gtp-channel-conf 30_193 -GTP_CHANNEL_1.GTPE2.PCS_RSVD_ATTR[19] origin:064-gtp-channel-conf 31_193 -GTP_CHANNEL_1.GTPE2.PCS_RSVD_ATTR[20] origin:064-gtp-channel-conf 30_194 -GTP_CHANNEL_1.GTPE2.PCS_RSVD_ATTR[21] origin:064-gtp-channel-conf 31_194 -GTP_CHANNEL_1.GTPE2.PCS_RSVD_ATTR[22] origin:064-gtp-channel-conf 30_195 -GTP_CHANNEL_1.GTPE2.PCS_RSVD_ATTR[23] origin:064-gtp-channel-conf 31_195 -GTP_CHANNEL_1.GTPE2.PCS_RSVD_ATTR[24] origin:064-gtp-channel-conf 30_196 -GTP_CHANNEL_1.GTPE2.PCS_RSVD_ATTR[25] origin:064-gtp-channel-conf 31_196 -GTP_CHANNEL_1.GTPE2.PCS_RSVD_ATTR[26] origin:064-gtp-channel-conf 30_197 -GTP_CHANNEL_1.GTPE2.PCS_RSVD_ATTR[27] origin:064-gtp-channel-conf 31_197 -GTP_CHANNEL_1.GTPE2.PCS_RSVD_ATTR[28] origin:064-gtp-channel-conf 30_198 -GTP_CHANNEL_1.GTPE2.PCS_RSVD_ATTR[29] origin:064-gtp-channel-conf 31_198 -GTP_CHANNEL_1.GTPE2.PCS_RSVD_ATTR[30] origin:064-gtp-channel-conf 30_199 -GTP_CHANNEL_1.GTPE2.PCS_RSVD_ATTR[31] origin:064-gtp-channel-conf 31_199 -GTP_CHANNEL_1.GTPE2.PCS_RSVD_ATTR[32] origin:064-gtp-channel-conf 30_200 -GTP_CHANNEL_1.GTPE2.PCS_RSVD_ATTR[33] origin:064-gtp-channel-conf 31_200 -GTP_CHANNEL_1.GTPE2.PCS_RSVD_ATTR[34] origin:064-gtp-channel-conf 30_201 -GTP_CHANNEL_1.GTPE2.PCS_RSVD_ATTR[35] origin:064-gtp-channel-conf 31_201 -GTP_CHANNEL_1.GTPE2.PCS_RSVD_ATTR[36] origin:064-gtp-channel-conf 30_202 -GTP_CHANNEL_1.GTPE2.PCS_RSVD_ATTR[37] origin:064-gtp-channel-conf 31_202 -GTP_CHANNEL_1.GTPE2.PCS_RSVD_ATTR[38] origin:064-gtp-channel-conf 30_203 -GTP_CHANNEL_1.GTPE2.PCS_RSVD_ATTR[39] origin:064-gtp-channel-conf 31_203 -GTP_CHANNEL_1.GTPE2.PCS_RSVD_ATTR[40] origin:064-gtp-channel-conf 30_204 -GTP_CHANNEL_1.GTPE2.PCS_RSVD_ATTR[41] origin:064-gtp-channel-conf 31_204 -GTP_CHANNEL_1.GTPE2.PCS_RSVD_ATTR[42] origin:064-gtp-channel-conf 30_205 -GTP_CHANNEL_1.GTPE2.PCS_RSVD_ATTR[43] origin:064-gtp-channel-conf 31_205 -GTP_CHANNEL_1.GTPE2.PCS_RSVD_ATTR[44] origin:064-gtp-channel-conf 30_206 -GTP_CHANNEL_1.GTPE2.PCS_RSVD_ATTR[45] origin:064-gtp-channel-conf 31_206 -GTP_CHANNEL_1.GTPE2.PCS_RSVD_ATTR[46] origin:064-gtp-channel-conf 30_207 -GTP_CHANNEL_1.GTPE2.PCS_RSVD_ATTR[47] origin:064-gtp-channel-conf 31_207 -GTP_CHANNEL_1.GTPE2.PD_TRANS_TIME_FROM_P2[0] origin:064-gtp-channel-conf 29_216 -GTP_CHANNEL_1.GTPE2.PD_TRANS_TIME_FROM_P2[1] origin:064-gtp-channel-conf 28_217 -GTP_CHANNEL_1.GTPE2.PD_TRANS_TIME_FROM_P2[2] origin:064-gtp-channel-conf 29_217 -GTP_CHANNEL_1.GTPE2.PD_TRANS_TIME_FROM_P2[3] origin:064-gtp-channel-conf 28_218 -GTP_CHANNEL_1.GTPE2.PD_TRANS_TIME_FROM_P2[4] origin:064-gtp-channel-conf 29_218 -GTP_CHANNEL_1.GTPE2.PD_TRANS_TIME_FROM_P2[5] origin:064-gtp-channel-conf 28_219 -GTP_CHANNEL_1.GTPE2.PD_TRANS_TIME_FROM_P2[6] origin:064-gtp-channel-conf 29_219 -GTP_CHANNEL_1.GTPE2.PD_TRANS_TIME_FROM_P2[7] origin:064-gtp-channel-conf 28_220 -GTP_CHANNEL_1.GTPE2.PD_TRANS_TIME_FROM_P2[8] origin:064-gtp-channel-conf 29_220 -GTP_CHANNEL_1.GTPE2.PD_TRANS_TIME_FROM_P2[9] origin:064-gtp-channel-conf 28_221 -GTP_CHANNEL_1.GTPE2.PD_TRANS_TIME_FROM_P2[10] origin:064-gtp-channel-conf 29_221 -GTP_CHANNEL_1.GTPE2.PD_TRANS_TIME_FROM_P2[11] origin:064-gtp-channel-conf 28_222 -GTP_CHANNEL_1.GTPE2.PD_TRANS_TIME_NONE_P2[0] origin:064-gtp-channel-conf 28_208 -GTP_CHANNEL_1.GTPE2.PD_TRANS_TIME_NONE_P2[1] origin:064-gtp-channel-conf 29_208 -GTP_CHANNEL_1.GTPE2.PD_TRANS_TIME_NONE_P2[2] origin:064-gtp-channel-conf 28_209 -GTP_CHANNEL_1.GTPE2.PD_TRANS_TIME_NONE_P2[3] origin:064-gtp-channel-conf 29_209 -GTP_CHANNEL_1.GTPE2.PD_TRANS_TIME_NONE_P2[4] origin:064-gtp-channel-conf 28_210 -GTP_CHANNEL_1.GTPE2.PD_TRANS_TIME_NONE_P2[5] origin:064-gtp-channel-conf 29_210 -GTP_CHANNEL_1.GTPE2.PD_TRANS_TIME_NONE_P2[6] origin:064-gtp-channel-conf 28_211 -GTP_CHANNEL_1.GTPE2.PD_TRANS_TIME_NONE_P2[7] origin:064-gtp-channel-conf 29_211 -GTP_CHANNEL_1.GTPE2.PD_TRANS_TIME_TO_P2[0] origin:064-gtp-channel-conf 28_212 -GTP_CHANNEL_1.GTPE2.PD_TRANS_TIME_TO_P2[1] origin:064-gtp-channel-conf 29_212 -GTP_CHANNEL_1.GTPE2.PD_TRANS_TIME_TO_P2[2] origin:064-gtp-channel-conf 28_213 -GTP_CHANNEL_1.GTPE2.PD_TRANS_TIME_TO_P2[3] origin:064-gtp-channel-conf 29_213 -GTP_CHANNEL_1.GTPE2.PD_TRANS_TIME_TO_P2[4] origin:064-gtp-channel-conf 28_214 -GTP_CHANNEL_1.GTPE2.PD_TRANS_TIME_TO_P2[5] origin:064-gtp-channel-conf 29_214 -GTP_CHANNEL_1.GTPE2.PD_TRANS_TIME_TO_P2[6] origin:064-gtp-channel-conf 28_215 -GTP_CHANNEL_1.GTPE2.PD_TRANS_TIME_TO_P2[7] origin:064-gtp-channel-conf 29_215 -GTP_CHANNEL_1.GTPE2.PMA_LOOPBACK_CFG[0] origin:064-gtp-channel-conf 29_207 -GTP_CHANNEL_1.GTPE2.PMA_RSV[0] origin:064-gtp-channel-conf 30_520 -GTP_CHANNEL_1.GTPE2.PMA_RSV[1] origin:064-gtp-channel-conf 31_520 -GTP_CHANNEL_1.GTPE2.PMA_RSV[2] origin:064-gtp-channel-conf 30_521 -GTP_CHANNEL_1.GTPE2.PMA_RSV[3] origin:064-gtp-channel-conf 31_521 -GTP_CHANNEL_1.GTPE2.PMA_RSV[4] origin:064-gtp-channel-conf 30_522 -GTP_CHANNEL_1.GTPE2.PMA_RSV[5] origin:064-gtp-channel-conf 31_522 -GTP_CHANNEL_1.GTPE2.PMA_RSV[6] origin:064-gtp-channel-conf 30_523 -GTP_CHANNEL_1.GTPE2.PMA_RSV[7] origin:064-gtp-channel-conf 31_523 -GTP_CHANNEL_1.GTPE2.PMA_RSV[8] origin:064-gtp-channel-conf 30_524 -GTP_CHANNEL_1.GTPE2.PMA_RSV[9] origin:064-gtp-channel-conf 31_524 -GTP_CHANNEL_1.GTPE2.PMA_RSV[10] origin:064-gtp-channel-conf 30_525 -GTP_CHANNEL_1.GTPE2.PMA_RSV[11] origin:064-gtp-channel-conf 31_525 -GTP_CHANNEL_1.GTPE2.PMA_RSV[12] origin:064-gtp-channel-conf 30_526 -GTP_CHANNEL_1.GTPE2.PMA_RSV[13] origin:064-gtp-channel-conf 31_526 -GTP_CHANNEL_1.GTPE2.PMA_RSV[14] origin:064-gtp-channel-conf 30_527 -GTP_CHANNEL_1.GTPE2.PMA_RSV[15] origin:064-gtp-channel-conf 31_527 -GTP_CHANNEL_1.GTPE2.PMA_RSV[16] origin:064-gtp-channel-conf 30_528 -GTP_CHANNEL_1.GTPE2.PMA_RSV[17] origin:064-gtp-channel-conf 31_528 -GTP_CHANNEL_1.GTPE2.PMA_RSV[18] origin:064-gtp-channel-conf 30_529 -GTP_CHANNEL_1.GTPE2.PMA_RSV[19] origin:064-gtp-channel-conf 31_529 -GTP_CHANNEL_1.GTPE2.PMA_RSV[20] origin:064-gtp-channel-conf 30_530 -GTP_CHANNEL_1.GTPE2.PMA_RSV[21] origin:064-gtp-channel-conf 31_530 -GTP_CHANNEL_1.GTPE2.PMA_RSV[22] origin:064-gtp-channel-conf 30_531 -GTP_CHANNEL_1.GTPE2.PMA_RSV[23] origin:064-gtp-channel-conf 31_531 -GTP_CHANNEL_1.GTPE2.PMA_RSV[24] origin:064-gtp-channel-conf 30_532 -GTP_CHANNEL_1.GTPE2.PMA_RSV[25] origin:064-gtp-channel-conf 31_532 -GTP_CHANNEL_1.GTPE2.PMA_RSV[26] origin:064-gtp-channel-conf 30_533 -GTP_CHANNEL_1.GTPE2.PMA_RSV[27] origin:064-gtp-channel-conf 31_533 -GTP_CHANNEL_1.GTPE2.PMA_RSV[28] origin:064-gtp-channel-conf 30_534 -GTP_CHANNEL_1.GTPE2.PMA_RSV[29] origin:064-gtp-channel-conf 31_534 -GTP_CHANNEL_1.GTPE2.PMA_RSV[30] origin:064-gtp-channel-conf 30_535 -GTP_CHANNEL_1.GTPE2.PMA_RSV[31] origin:064-gtp-channel-conf 31_535 -GTP_CHANNEL_1.GTPE2.PMA_RSV2[0] origin:064-gtp-channel-conf 30_336 -GTP_CHANNEL_1.GTPE2.PMA_RSV2[1] origin:064-gtp-channel-conf 31_336 -GTP_CHANNEL_1.GTPE2.PMA_RSV2[2] origin:064-gtp-channel-conf 30_337 -GTP_CHANNEL_1.GTPE2.PMA_RSV2[3] origin:064-gtp-channel-conf 31_337 -GTP_CHANNEL_1.GTPE2.PMA_RSV2[4] origin:064-gtp-channel-conf 30_338 -GTP_CHANNEL_1.GTPE2.PMA_RSV2[5] origin:064-gtp-channel-conf 31_338 -GTP_CHANNEL_1.GTPE2.PMA_RSV2[6] origin:064-gtp-channel-conf 30_339 -GTP_CHANNEL_1.GTPE2.PMA_RSV2[7] origin:064-gtp-channel-conf 31_339 -GTP_CHANNEL_1.GTPE2.PMA_RSV2[8] origin:064-gtp-channel-conf 30_340 -GTP_CHANNEL_1.GTPE2.PMA_RSV2[9] origin:064-gtp-channel-conf 31_340 -GTP_CHANNEL_1.GTPE2.PMA_RSV2[10] origin:064-gtp-channel-conf 30_341 -GTP_CHANNEL_1.GTPE2.PMA_RSV2[11] origin:064-gtp-channel-conf 31_341 -GTP_CHANNEL_1.GTPE2.PMA_RSV2[12] origin:064-gtp-channel-conf 30_342 -GTP_CHANNEL_1.GTPE2.PMA_RSV2[13] origin:064-gtp-channel-conf 31_342 -GTP_CHANNEL_1.GTPE2.PMA_RSV2[14] origin:064-gtp-channel-conf 30_343 -GTP_CHANNEL_1.GTPE2.PMA_RSV2[15] origin:064-gtp-channel-conf 31_343 -GTP_CHANNEL_1.GTPE2.PMA_RSV2[16] origin:064-gtp-channel-conf 30_344 -GTP_CHANNEL_1.GTPE2.PMA_RSV2[17] origin:064-gtp-channel-conf 31_344 -GTP_CHANNEL_1.GTPE2.PMA_RSV2[18] origin:064-gtp-channel-conf 30_345 -GTP_CHANNEL_1.GTPE2.PMA_RSV2[19] origin:064-gtp-channel-conf 31_345 -GTP_CHANNEL_1.GTPE2.PMA_RSV2[20] origin:064-gtp-channel-conf 30_346 -GTP_CHANNEL_1.GTPE2.PMA_RSV2[21] origin:064-gtp-channel-conf 31_346 -GTP_CHANNEL_1.GTPE2.PMA_RSV2[22] origin:064-gtp-channel-conf 30_347 -GTP_CHANNEL_1.GTPE2.PMA_RSV2[23] origin:064-gtp-channel-conf 31_347 -GTP_CHANNEL_1.GTPE2.PMA_RSV2[24] origin:064-gtp-channel-conf 30_348 -GTP_CHANNEL_1.GTPE2.PMA_RSV2[25] origin:064-gtp-channel-conf 31_348 -GTP_CHANNEL_1.GTPE2.PMA_RSV2[26] origin:064-gtp-channel-conf 30_349 -GTP_CHANNEL_1.GTPE2.PMA_RSV2[27] origin:064-gtp-channel-conf 31_349 -GTP_CHANNEL_1.GTPE2.PMA_RSV2[28] origin:064-gtp-channel-conf 30_350 -GTP_CHANNEL_1.GTPE2.PMA_RSV2[29] origin:064-gtp-channel-conf 31_350 -GTP_CHANNEL_1.GTPE2.PMA_RSV2[30] origin:064-gtp-channel-conf 30_351 -GTP_CHANNEL_1.GTPE2.PMA_RSV2[31] origin:064-gtp-channel-conf 31_351 -GTP_CHANNEL_1.GTPE2.PMA_RSV3[0] origin:064-gtp-channel-conf 30_288 -GTP_CHANNEL_1.GTPE2.PMA_RSV3[1] origin:064-gtp-channel-conf 31_288 -GTP_CHANNEL_1.GTPE2.PMA_RSV4[0] origin:064-gtp-channel-conf 30_156 -GTP_CHANNEL_1.GTPE2.PMA_RSV4[1] origin:064-gtp-channel-conf 31_156 -GTP_CHANNEL_1.GTPE2.PMA_RSV4[2] origin:064-gtp-channel-conf 30_157 -GTP_CHANNEL_1.GTPE2.PMA_RSV4[3] origin:064-gtp-channel-conf 31_157 -GTP_CHANNEL_1.GTPE2.PMA_RSV5[0] origin:064-gtp-channel-conf 31_159 -GTP_CHANNEL_1.GTPE2.PMA_RSV6[0] origin:064-gtp-channel-conf 30_303 -GTP_CHANNEL_1.GTPE2.PMA_RSV7[0] origin:064-gtp-channel-conf 31_303 -GTP_CHANNEL_1.GTPE2.RX_BIAS_CFG[0] origin:064-gtp-channel-conf 30_112 -GTP_CHANNEL_1.GTPE2.RX_BIAS_CFG[1] origin:064-gtp-channel-conf 31_112 -GTP_CHANNEL_1.GTPE2.RX_BIAS_CFG[2] origin:064-gtp-channel-conf 30_113 -GTP_CHANNEL_1.GTPE2.RX_BIAS_CFG[3] origin:064-gtp-channel-conf 31_113 -GTP_CHANNEL_1.GTPE2.RX_BIAS_CFG[4] origin:064-gtp-channel-conf 30_114 -GTP_CHANNEL_1.GTPE2.RX_BIAS_CFG[5] origin:064-gtp-channel-conf 31_114 -GTP_CHANNEL_1.GTPE2.RX_BIAS_CFG[6] origin:064-gtp-channel-conf 30_115 -GTP_CHANNEL_1.GTPE2.RX_BIAS_CFG[7] origin:064-gtp-channel-conf 31_115 -GTP_CHANNEL_1.GTPE2.RX_BIAS_CFG[8] origin:064-gtp-channel-conf 30_116 -GTP_CHANNEL_1.GTPE2.RX_BIAS_CFG[9] origin:064-gtp-channel-conf 31_116 -GTP_CHANNEL_1.GTPE2.RX_BIAS_CFG[10] origin:064-gtp-channel-conf 30_117 -GTP_CHANNEL_1.GTPE2.RX_BIAS_CFG[11] origin:064-gtp-channel-conf 31_117 -GTP_CHANNEL_1.GTPE2.RX_BIAS_CFG[12] origin:064-gtp-channel-conf 30_118 -GTP_CHANNEL_1.GTPE2.RX_BIAS_CFG[13] origin:064-gtp-channel-conf 31_118 -GTP_CHANNEL_1.GTPE2.RX_BIAS_CFG[14] origin:064-gtp-channel-conf 30_119 -GTP_CHANNEL_1.GTPE2.RX_BIAS_CFG[15] origin:064-gtp-channel-conf 31_119 -GTP_CHANNEL_1.GTPE2.RX_BUFFER_CFG[0] origin:064-gtp-channel-conf 30_536 -GTP_CHANNEL_1.GTPE2.RX_BUFFER_CFG[1] origin:064-gtp-channel-conf 31_536 -GTP_CHANNEL_1.GTPE2.RX_BUFFER_CFG[2] origin:064-gtp-channel-conf 30_537 -GTP_CHANNEL_1.GTPE2.RX_BUFFER_CFG[3] origin:064-gtp-channel-conf 31_537 -GTP_CHANNEL_1.GTPE2.RX_BUFFER_CFG[4] origin:064-gtp-channel-conf 30_538 -GTP_CHANNEL_1.GTPE2.RX_BUFFER_CFG[5] origin:064-gtp-channel-conf 31_538 -GTP_CHANNEL_1.GTPE2.RX_CLKMUX_EN[0] origin:064-gtp-channel-conf 30_128 -GTP_CHANNEL_1.GTPE2.RX_CM_SEL[0] origin:064-gtp-channel-conf 28_138 -GTP_CHANNEL_1.GTPE2.RX_CM_SEL[1] origin:064-gtp-channel-conf 29_138 -GTP_CHANNEL_1.GTPE2.RX_CM_TRIM[0] origin:064-gtp-channel-conf 30_304 -GTP_CHANNEL_1.GTPE2.RX_CM_TRIM[1] origin:064-gtp-channel-conf 31_304 -GTP_CHANNEL_1.GTPE2.RX_CM_TRIM[2] origin:064-gtp-channel-conf 30_305 -GTP_CHANNEL_1.GTPE2.RX_CM_TRIM[3] origin:064-gtp-channel-conf 31_305 -GTP_CHANNEL_1.GTPE2.RX_DATA_WIDTH[0] origin:064-gtp-channel-conf 29_141 -GTP_CHANNEL_1.GTPE2.RX_DATA_WIDTH[1] origin:064-gtp-channel-conf 28_142 -GTP_CHANNEL_1.GTPE2.RX_DATA_WIDTH[2] origin:064-gtp-channel-conf 29_142 -GTP_CHANNEL_1.GTPE2.RX_DDI_SEL[0] origin:064-gtp-channel-conf 28_696 -GTP_CHANNEL_1.GTPE2.RX_DDI_SEL[1] origin:064-gtp-channel-conf 29_696 -GTP_CHANNEL_1.GTPE2.RX_DDI_SEL[2] origin:064-gtp-channel-conf 28_697 -GTP_CHANNEL_1.GTPE2.RX_DDI_SEL[3] origin:064-gtp-channel-conf 29_697 -GTP_CHANNEL_1.GTPE2.RX_DDI_SEL[4] origin:064-gtp-channel-conf 28_698 -GTP_CHANNEL_1.GTPE2.RX_DDI_SEL[5] origin:064-gtp-channel-conf 29_698 -GTP_CHANNEL_1.GTPE2.RX_DEBUG_CFG[0] origin:064-gtp-channel-conf 30_616 -GTP_CHANNEL_1.GTPE2.RX_DEBUG_CFG[1] origin:064-gtp-channel-conf 31_616 -GTP_CHANNEL_1.GTPE2.RX_DEBUG_CFG[2] origin:064-gtp-channel-conf 30_617 -GTP_CHANNEL_1.GTPE2.RX_DEBUG_CFG[3] origin:064-gtp-channel-conf 31_617 -GTP_CHANNEL_1.GTPE2.RX_DEBUG_CFG[4] origin:064-gtp-channel-conf 30_618 -GTP_CHANNEL_1.GTPE2.RX_DEBUG_CFG[5] origin:064-gtp-channel-conf 31_618 -GTP_CHANNEL_1.GTPE2.RX_DEBUG_CFG[6] origin:064-gtp-channel-conf 30_619 -GTP_CHANNEL_1.GTPE2.RX_DEBUG_CFG[7] origin:064-gtp-channel-conf 31_619 -GTP_CHANNEL_1.GTPE2.RX_DEBUG_CFG[8] origin:064-gtp-channel-conf 30_620 -GTP_CHANNEL_1.GTPE2.RX_DEBUG_CFG[9] origin:064-gtp-channel-conf 31_620 -GTP_CHANNEL_1.GTPE2.RX_DEBUG_CFG[10] origin:064-gtp-channel-conf 30_621 -GTP_CHANNEL_1.GTPE2.RX_DEBUG_CFG[11] origin:064-gtp-channel-conf 31_621 -GTP_CHANNEL_1.GTPE2.RX_DEBUG_CFG[12] origin:064-gtp-channel-conf 30_622 -GTP_CHANNEL_1.GTPE2.RX_DEBUG_CFG[13] origin:064-gtp-channel-conf 31_622 -GTP_CHANNEL_1.GTPE2.RX_DEFER_RESET_BUF_EN origin:064-gtp-channel-conf 30_552 -GTP_CHANNEL_1.GTPE2.RX_DISPERR_SEQ_MATCH origin:064-gtp-channel-conf 29_495 -GTP_CHANNEL_1.GTPE2.RX_OS_CFG[0] origin:064-gtp-channel-conf 28_288 -GTP_CHANNEL_1.GTPE2.RX_OS_CFG[1] origin:064-gtp-channel-conf 29_288 -GTP_CHANNEL_1.GTPE2.RX_OS_CFG[2] origin:064-gtp-channel-conf 28_289 -GTP_CHANNEL_1.GTPE2.RX_OS_CFG[3] origin:064-gtp-channel-conf 29_289 -GTP_CHANNEL_1.GTPE2.RX_OS_CFG[4] origin:064-gtp-channel-conf 28_290 -GTP_CHANNEL_1.GTPE2.RX_OS_CFG[5] origin:064-gtp-channel-conf 29_290 -GTP_CHANNEL_1.GTPE2.RX_OS_CFG[6] origin:064-gtp-channel-conf 28_291 -GTP_CHANNEL_1.GTPE2.RX_OS_CFG[7] origin:064-gtp-channel-conf 29_291 -GTP_CHANNEL_1.GTPE2.RX_OS_CFG[8] origin:064-gtp-channel-conf 28_292 -GTP_CHANNEL_1.GTPE2.RX_OS_CFG[9] origin:064-gtp-channel-conf 29_292 -GTP_CHANNEL_1.GTPE2.RX_OS_CFG[10] origin:064-gtp-channel-conf 28_293 -GTP_CHANNEL_1.GTPE2.RX_OS_CFG[11] origin:064-gtp-channel-conf 29_293 -GTP_CHANNEL_1.GTPE2.RX_OS_CFG[12] origin:064-gtp-channel-conf 28_294 -GTP_CHANNEL_1.GTPE2.RX_SIG_VALID_DLY[0] origin:064-gtp-channel-conf 28_524 -GTP_CHANNEL_1.GTPE2.RX_SIG_VALID_DLY[1] origin:064-gtp-channel-conf 29_524 -GTP_CHANNEL_1.GTPE2.RX_SIG_VALID_DLY[2] origin:064-gtp-channel-conf 28_525 -GTP_CHANNEL_1.GTPE2.RX_SIG_VALID_DLY[3] origin:064-gtp-channel-conf 29_525 -GTP_CHANNEL_1.GTPE2.RX_SIG_VALID_DLY[4] origin:064-gtp-channel-conf 28_526 -GTP_CHANNEL_1.GTPE2.RX_XCLK_SEL.RXUSR origin:064-gtp-channel-conf 28_143 -GTP_CHANNEL_1.GTPE2.RX_CLK25_DIV[0] origin:064-gtp-channel-conf 28_139 -GTP_CHANNEL_1.GTPE2.RX_CLK25_DIV[1] origin:064-gtp-channel-conf 29_139 -GTP_CHANNEL_1.GTPE2.RX_CLK25_DIV[2] origin:064-gtp-channel-conf 28_140 -GTP_CHANNEL_1.GTPE2.RX_CLK25_DIV[3] origin:064-gtp-channel-conf 29_140 -GTP_CHANNEL_1.GTPE2.RX_CLK25_DIV[4] origin:064-gtp-channel-conf 28_141 -GTP_CHANNEL_1.GTPE2.RXBUF_ADDR_MODE.FAST origin:064-gtp-channel-conf 31_555 -GTP_CHANNEL_1.GTPE2.RXBUF_EIDLE_HI_CNT[0] origin:064-gtp-channel-conf 30_558 -GTP_CHANNEL_1.GTPE2.RXBUF_EIDLE_HI_CNT[1] origin:064-gtp-channel-conf 31_558 -GTP_CHANNEL_1.GTPE2.RXBUF_EIDLE_HI_CNT[2] origin:064-gtp-channel-conf 30_559 -GTP_CHANNEL_1.GTPE2.RXBUF_EIDLE_HI_CNT[3] origin:064-gtp-channel-conf 31_559 -GTP_CHANNEL_1.GTPE2.RXBUF_EIDLE_LO_CNT[0] origin:064-gtp-channel-conf 30_556 -GTP_CHANNEL_1.GTPE2.RXBUF_EIDLE_LO_CNT[1] origin:064-gtp-channel-conf 31_556 -GTP_CHANNEL_1.GTPE2.RXBUF_EIDLE_LO_CNT[2] origin:064-gtp-channel-conf 30_557 -GTP_CHANNEL_1.GTPE2.RXBUF_EIDLE_LO_CNT[3] origin:064-gtp-channel-conf 31_557 -GTP_CHANNEL_1.GTPE2.RXBUF_EN origin:064-gtp-channel-conf 30_11 -GTP_CHANNEL_1.GTPE2.RXBUF_RESET_ON_CB_CHANGE origin:064-gtp-channel-conf 30_560 -GTP_CHANNEL_1.GTPE2.RXBUF_RESET_ON_COMMAALIGN origin:064-gtp-channel-conf 30_561 -GTP_CHANNEL_1.GTPE2.RXBUF_RESET_ON_EIDLE origin:064-gtp-channel-conf 30_547 -GTP_CHANNEL_1.GTPE2.RXBUF_RESET_ON_RATE_CHANGE origin:064-gtp-channel-conf 31_560 -GTP_CHANNEL_1.GTPE2.RXBUF_THRESH_OVFLW[0] origin:064-gtp-channel-conf 31_552 -GTP_CHANNEL_1.GTPE2.RXBUF_THRESH_OVFLW[1] origin:064-gtp-channel-conf 30_553 -GTP_CHANNEL_1.GTPE2.RXBUF_THRESH_OVFLW[2] origin:064-gtp-channel-conf 31_553 -GTP_CHANNEL_1.GTPE2.RXBUF_THRESH_OVFLW[3] origin:064-gtp-channel-conf 30_554 -GTP_CHANNEL_1.GTPE2.RXBUF_THRESH_OVFLW[4] origin:064-gtp-channel-conf 31_554 -GTP_CHANNEL_1.GTPE2.RXBUF_THRESH_OVFLW[5] origin:064-gtp-channel-conf 30_555 -GTP_CHANNEL_1.GTPE2.RXBUF_THRESH_OVRD origin:064-gtp-channel-conf 30_548 -GTP_CHANNEL_1.GTPE2.RXBUF_THRESH_UNDFLW[0] origin:064-gtp-channel-conf 30_544 -GTP_CHANNEL_1.GTPE2.RXBUF_THRESH_UNDFLW[1] origin:064-gtp-channel-conf 31_544 -GTP_CHANNEL_1.GTPE2.RXBUF_THRESH_UNDFLW[2] origin:064-gtp-channel-conf 30_545 -GTP_CHANNEL_1.GTPE2.RXBUF_THRESH_UNDFLW[3] origin:064-gtp-channel-conf 31_545 -GTP_CHANNEL_1.GTPE2.RXBUF_THRESH_UNDFLW[4] origin:064-gtp-channel-conf 30_546 -GTP_CHANNEL_1.GTPE2.RXBUF_THRESH_UNDFLW[5] origin:064-gtp-channel-conf 31_546 -GTP_CHANNEL_1.GTPE2.RXBUFRESET_TIME[0] origin:064-gtp-channel-conf 29_101 -GTP_CHANNEL_1.GTPE2.RXBUFRESET_TIME[1] origin:064-gtp-channel-conf 28_102 -GTP_CHANNEL_1.GTPE2.RXBUFRESET_TIME[2] origin:064-gtp-channel-conf 29_102 -GTP_CHANNEL_1.GTPE2.RXBUFRESET_TIME[3] origin:064-gtp-channel-conf 28_103 -GTP_CHANNEL_1.GTPE2.RXBUFRESET_TIME[4] origin:064-gtp-channel-conf 29_103 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[0] origin:064-gtp-channel-conf 30_640 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[1] origin:064-gtp-channel-conf 31_640 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[2] origin:064-gtp-channel-conf 30_641 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[3] origin:064-gtp-channel-conf 31_641 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[4] origin:064-gtp-channel-conf 30_642 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[5] origin:064-gtp-channel-conf 31_642 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[6] origin:064-gtp-channel-conf 30_643 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[7] origin:064-gtp-channel-conf 31_643 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[8] origin:064-gtp-channel-conf 30_644 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[9] origin:064-gtp-channel-conf 31_644 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[10] origin:064-gtp-channel-conf 30_645 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[11] origin:064-gtp-channel-conf 31_645 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[12] origin:064-gtp-channel-conf 30_646 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[13] origin:064-gtp-channel-conf 31_646 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[14] origin:064-gtp-channel-conf 30_647 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[15] origin:064-gtp-channel-conf 31_647 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[16] origin:064-gtp-channel-conf 30_648 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[17] origin:064-gtp-channel-conf 31_648 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[18] origin:064-gtp-channel-conf 30_649 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[19] origin:064-gtp-channel-conf 31_649 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[20] origin:064-gtp-channel-conf 30_650 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[21] origin:064-gtp-channel-conf 31_650 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[22] origin:064-gtp-channel-conf 30_651 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[23] origin:064-gtp-channel-conf 31_651 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[24] origin:064-gtp-channel-conf 30_652 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[25] origin:064-gtp-channel-conf 31_652 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[26] origin:064-gtp-channel-conf 30_653 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[27] origin:064-gtp-channel-conf 31_653 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[28] origin:064-gtp-channel-conf 30_654 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[29] origin:064-gtp-channel-conf 31_654 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[30] origin:064-gtp-channel-conf 30_655 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[31] origin:064-gtp-channel-conf 31_655 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[32] origin:064-gtp-channel-conf 30_656 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[33] origin:064-gtp-channel-conf 31_656 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[34] origin:064-gtp-channel-conf 30_657 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[35] origin:064-gtp-channel-conf 31_657 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[36] origin:064-gtp-channel-conf 30_658 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[37] origin:064-gtp-channel-conf 31_658 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[38] origin:064-gtp-channel-conf 30_659 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[39] origin:064-gtp-channel-conf 31_659 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[40] origin:064-gtp-channel-conf 30_660 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[41] origin:064-gtp-channel-conf 31_660 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[42] origin:064-gtp-channel-conf 30_661 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[43] origin:064-gtp-channel-conf 31_661 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[44] origin:064-gtp-channel-conf 30_662 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[45] origin:064-gtp-channel-conf 31_662 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[46] origin:064-gtp-channel-conf 30_663 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[47] origin:064-gtp-channel-conf 31_663 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[48] origin:064-gtp-channel-conf 30_664 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[49] origin:064-gtp-channel-conf 31_664 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[50] origin:064-gtp-channel-conf 30_665 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[51] origin:064-gtp-channel-conf 31_665 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[52] origin:064-gtp-channel-conf 30_666 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[53] origin:064-gtp-channel-conf 31_666 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[54] origin:064-gtp-channel-conf 30_667 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[55] origin:064-gtp-channel-conf 31_667 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[56] origin:064-gtp-channel-conf 30_668 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[57] origin:064-gtp-channel-conf 31_668 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[58] origin:064-gtp-channel-conf 30_669 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[59] origin:064-gtp-channel-conf 31_669 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[60] origin:064-gtp-channel-conf 30_670 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[61] origin:064-gtp-channel-conf 31_670 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[62] origin:064-gtp-channel-conf 30_671 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[63] origin:064-gtp-channel-conf 31_671 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[64] origin:064-gtp-channel-conf 30_672 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[65] origin:064-gtp-channel-conf 31_672 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[66] origin:064-gtp-channel-conf 30_673 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[67] origin:064-gtp-channel-conf 31_673 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[68] origin:064-gtp-channel-conf 30_674 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[69] origin:064-gtp-channel-conf 31_674 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[70] origin:064-gtp-channel-conf 30_675 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[71] origin:064-gtp-channel-conf 31_675 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[72] origin:064-gtp-channel-conf 30_676 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[73] origin:064-gtp-channel-conf 31_676 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[74] origin:064-gtp-channel-conf 30_677 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[75] origin:064-gtp-channel-conf 31_677 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[76] origin:064-gtp-channel-conf 30_678 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[77] origin:064-gtp-channel-conf 31_678 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[78] origin:064-gtp-channel-conf 30_679 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[79] origin:064-gtp-channel-conf 31_679 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[80] origin:064-gtp-channel-conf 30_680 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[81] origin:064-gtp-channel-conf 31_680 -GTP_CHANNEL_1.GTPE2.RXCDR_CFG[82] origin:064-gtp-channel-conf 30_681 -GTP_CHANNEL_1.GTPE2.RXCDR_FR_RESET_ON_EIDLE[0] origin:064-gtp-channel-conf 30_638 -GTP_CHANNEL_1.GTPE2.RXCDR_HOLD_DURING_EIDLE[0] origin:064-gtp-channel-conf 31_637 -GTP_CHANNEL_1.GTPE2.RXCDR_LOCK_CFG[0] origin:064-gtp-channel-conf 30_632 -GTP_CHANNEL_1.GTPE2.RXCDR_LOCK_CFG[1] origin:064-gtp-channel-conf 31_632 -GTP_CHANNEL_1.GTPE2.RXCDR_LOCK_CFG[2] origin:064-gtp-channel-conf 30_633 -GTP_CHANNEL_1.GTPE2.RXCDR_LOCK_CFG[3] origin:064-gtp-channel-conf 31_633 -GTP_CHANNEL_1.GTPE2.RXCDR_LOCK_CFG[4] origin:064-gtp-channel-conf 30_634 -GTP_CHANNEL_1.GTPE2.RXCDR_LOCK_CFG[5] origin:064-gtp-channel-conf 31_634 -GTP_CHANNEL_1.GTPE2.RXCDR_PH_RESET_ON_EIDLE[0] origin:064-gtp-channel-conf 31_638 -GTP_CHANNEL_1.GTPE2.RXCDRFREQRESET_TIME[0] origin:064-gtp-channel-conf 29_106 -GTP_CHANNEL_1.GTPE2.RXCDRFREQRESET_TIME[1] origin:064-gtp-channel-conf 28_107 -GTP_CHANNEL_1.GTPE2.RXCDRFREQRESET_TIME[2] origin:064-gtp-channel-conf 29_107 -GTP_CHANNEL_1.GTPE2.RXCDRFREQRESET_TIME[3] origin:064-gtp-channel-conf 28_108 -GTP_CHANNEL_1.GTPE2.RXCDRFREQRESET_TIME[4] origin:064-gtp-channel-conf 29_108 -GTP_CHANNEL_1.GTPE2.RXCDRPHRESET_TIME[0] origin:064-gtp-channel-conf 28_109 -GTP_CHANNEL_1.GTPE2.RXCDRPHRESET_TIME[1] origin:064-gtp-channel-conf 29_109 -GTP_CHANNEL_1.GTPE2.RXCDRPHRESET_TIME[2] origin:064-gtp-channel-conf 28_110 -GTP_CHANNEL_1.GTPE2.RXCDRPHRESET_TIME[3] origin:064-gtp-channel-conf 29_110 -GTP_CHANNEL_1.GTPE2.RXCDRPHRESET_TIME[4] origin:064-gtp-channel-conf 28_111 -GTP_CHANNEL_1.GTPE2.RXDLY_CFG[0] origin:064-gtp-channel-conf 28_680 -GTP_CHANNEL_1.GTPE2.RXDLY_CFG[1] origin:064-gtp-channel-conf 29_680 -GTP_CHANNEL_1.GTPE2.RXDLY_CFG[2] origin:064-gtp-channel-conf 28_681 -GTP_CHANNEL_1.GTPE2.RXDLY_CFG[3] origin:064-gtp-channel-conf 29_681 -GTP_CHANNEL_1.GTPE2.RXDLY_CFG[4] origin:064-gtp-channel-conf 28_682 -GTP_CHANNEL_1.GTPE2.RXDLY_CFG[5] origin:064-gtp-channel-conf 29_682 -GTP_CHANNEL_1.GTPE2.RXDLY_CFG[6] origin:064-gtp-channel-conf 28_683 -GTP_CHANNEL_1.GTPE2.RXDLY_CFG[7] origin:064-gtp-channel-conf 29_683 -GTP_CHANNEL_1.GTPE2.RXDLY_CFG[8] origin:064-gtp-channel-conf 28_684 -GTP_CHANNEL_1.GTPE2.RXDLY_CFG[9] origin:064-gtp-channel-conf 29_684 -GTP_CHANNEL_1.GTPE2.RXDLY_CFG[10] origin:064-gtp-channel-conf 28_685 -GTP_CHANNEL_1.GTPE2.RXDLY_CFG[11] origin:064-gtp-channel-conf 29_685 -GTP_CHANNEL_1.GTPE2.RXDLY_CFG[12] origin:064-gtp-channel-conf 28_686 -GTP_CHANNEL_1.GTPE2.RXDLY_CFG[13] origin:064-gtp-channel-conf 29_686 -GTP_CHANNEL_1.GTPE2.RXDLY_CFG[14] origin:064-gtp-channel-conf 28_687 -GTP_CHANNEL_1.GTPE2.RXDLY_CFG[15] origin:064-gtp-channel-conf 29_687 -GTP_CHANNEL_1.GTPE2.RXDLY_LCFG[0] origin:064-gtp-channel-conf 30_576 -GTP_CHANNEL_1.GTPE2.RXDLY_LCFG[1] origin:064-gtp-channel-conf 31_576 -GTP_CHANNEL_1.GTPE2.RXDLY_LCFG[2] origin:064-gtp-channel-conf 30_577 -GTP_CHANNEL_1.GTPE2.RXDLY_LCFG[3] origin:064-gtp-channel-conf 31_577 -GTP_CHANNEL_1.GTPE2.RXDLY_LCFG[4] origin:064-gtp-channel-conf 30_578 -GTP_CHANNEL_1.GTPE2.RXDLY_LCFG[5] origin:064-gtp-channel-conf 31_578 -GTP_CHANNEL_1.GTPE2.RXDLY_LCFG[6] origin:064-gtp-channel-conf 30_579 -GTP_CHANNEL_1.GTPE2.RXDLY_LCFG[7] origin:064-gtp-channel-conf 31_579 -GTP_CHANNEL_1.GTPE2.RXDLY_LCFG[8] origin:064-gtp-channel-conf 30_580 -GTP_CHANNEL_1.GTPE2.RXDLY_TAP_CFG[0] origin:064-gtp-channel-conf 28_672 -GTP_CHANNEL_1.GTPE2.RXDLY_TAP_CFG[1] origin:064-gtp-channel-conf 29_672 -GTP_CHANNEL_1.GTPE2.RXDLY_TAP_CFG[2] origin:064-gtp-channel-conf 28_673 -GTP_CHANNEL_1.GTPE2.RXDLY_TAP_CFG[3] origin:064-gtp-channel-conf 29_673 -GTP_CHANNEL_1.GTPE2.RXDLY_TAP_CFG[4] origin:064-gtp-channel-conf 28_674 -GTP_CHANNEL_1.GTPE2.RXDLY_TAP_CFG[5] origin:064-gtp-channel-conf 29_674 -GTP_CHANNEL_1.GTPE2.RXDLY_TAP_CFG[6] origin:064-gtp-channel-conf 28_675 -GTP_CHANNEL_1.GTPE2.RXDLY_TAP_CFG[7] origin:064-gtp-channel-conf 29_675 -GTP_CHANNEL_1.GTPE2.RXDLY_TAP_CFG[8] origin:064-gtp-channel-conf 28_676 -GTP_CHANNEL_1.GTPE2.RXDLY_TAP_CFG[9] origin:064-gtp-channel-conf 29_676 -GTP_CHANNEL_1.GTPE2.RXDLY_TAP_CFG[10] origin:064-gtp-channel-conf 28_677 -GTP_CHANNEL_1.GTPE2.RXDLY_TAP_CFG[11] origin:064-gtp-channel-conf 29_677 -GTP_CHANNEL_1.GTPE2.RXDLY_TAP_CFG[12] origin:064-gtp-channel-conf 28_678 -GTP_CHANNEL_1.GTPE2.RXDLY_TAP_CFG[13] origin:064-gtp-channel-conf 29_678 -GTP_CHANNEL_1.GTPE2.RXDLY_TAP_CFG[14] origin:064-gtp-channel-conf 28_679 -GTP_CHANNEL_1.GTPE2.RXDLY_TAP_CFG[15] origin:064-gtp-channel-conf 29_679 -GTP_CHANNEL_1.GTPE2.RXGEARBOX_EN origin:064-gtp-channel-conf 29_607 -GTP_CHANNEL_1.GTPE2.RXISCANRESET_TIME[0] origin:064-gtp-channel-conf 29_123 -GTP_CHANNEL_1.GTPE2.RXISCANRESET_TIME[1] origin:064-gtp-channel-conf 28_124 -GTP_CHANNEL_1.GTPE2.RXISCANRESET_TIME[2] origin:064-gtp-channel-conf 29_124 -GTP_CHANNEL_1.GTPE2.RXISCANRESET_TIME[3] origin:064-gtp-channel-conf 28_125 -GTP_CHANNEL_1.GTPE2.RXISCANRESET_TIME[4] origin:064-gtp-channel-conf 29_125 -GTP_CHANNEL_1.GTPE2.RXLPM_BIAS_STARTUP_DISABLE[0] origin:064-gtp-channel-conf 31_391 -GTP_CHANNEL_1.GTPE2.RXLPM_CFG[0] origin:064-gtp-channel-conf 30_328 -GTP_CHANNEL_1.GTPE2.RXLPM_CFG[1] origin:064-gtp-channel-conf 31_328 -GTP_CHANNEL_1.GTPE2.RXLPM_CFG[2] origin:064-gtp-channel-conf 30_329 -GTP_CHANNEL_1.GTPE2.RXLPM_CFG[3] origin:064-gtp-channel-conf 31_329 -GTP_CHANNEL_1.GTPE2.RXLPM_CM_CFG[0] origin:064-gtp-channel-conf 30_430 -GTP_CHANNEL_1.GTPE2.RXLPM_GC_CFG[0] origin:064-gtp-channel-conf 30_432 -GTP_CHANNEL_1.GTPE2.RXLPM_GC_CFG[1] origin:064-gtp-channel-conf 31_432 -GTP_CHANNEL_1.GTPE2.RXLPM_GC_CFG[2] origin:064-gtp-channel-conf 30_433 -GTP_CHANNEL_1.GTPE2.RXLPM_GC_CFG[3] origin:064-gtp-channel-conf 31_433 -GTP_CHANNEL_1.GTPE2.RXLPM_GC_CFG[4] origin:064-gtp-channel-conf 30_434 -GTP_CHANNEL_1.GTPE2.RXLPM_GC_CFG[5] origin:064-gtp-channel-conf 31_434 -GTP_CHANNEL_1.GTPE2.RXLPM_GC_CFG[6] origin:064-gtp-channel-conf 30_435 -GTP_CHANNEL_1.GTPE2.RXLPM_GC_CFG[7] origin:064-gtp-channel-conf 31_435 -GTP_CHANNEL_1.GTPE2.RXLPM_GC_CFG[8] origin:064-gtp-channel-conf 30_436 -GTP_CHANNEL_1.GTPE2.RXLPM_GC_CFG2[0] origin:064-gtp-channel-conf 31_442 -GTP_CHANNEL_1.GTPE2.RXLPM_GC_CFG2[1] origin:064-gtp-channel-conf 30_443 -GTP_CHANNEL_1.GTPE2.RXLPM_GC_CFG2[2] origin:064-gtp-channel-conf 31_443 -GTP_CHANNEL_1.GTPE2.RXLPM_HF_CFG[0] origin:064-gtp-channel-conf 28_336 -GTP_CHANNEL_1.GTPE2.RXLPM_HF_CFG[1] origin:064-gtp-channel-conf 29_336 -GTP_CHANNEL_1.GTPE2.RXLPM_HF_CFG[2] origin:064-gtp-channel-conf 28_337 -GTP_CHANNEL_1.GTPE2.RXLPM_HF_CFG[3] origin:064-gtp-channel-conf 29_337 -GTP_CHANNEL_1.GTPE2.RXLPM_HF_CFG[4] origin:064-gtp-channel-conf 28_338 -GTP_CHANNEL_1.GTPE2.RXLPM_HF_CFG[5] origin:064-gtp-channel-conf 29_338 -GTP_CHANNEL_1.GTPE2.RXLPM_HF_CFG[6] origin:064-gtp-channel-conf 28_339 -GTP_CHANNEL_1.GTPE2.RXLPM_HF_CFG[7] origin:064-gtp-channel-conf 29_339 -GTP_CHANNEL_1.GTPE2.RXLPM_HF_CFG[8] origin:064-gtp-channel-conf 28_340 -GTP_CHANNEL_1.GTPE2.RXLPM_HF_CFG[9] origin:064-gtp-channel-conf 29_340 -GTP_CHANNEL_1.GTPE2.RXLPM_HF_CFG[10] origin:064-gtp-channel-conf 28_341 -GTP_CHANNEL_1.GTPE2.RXLPM_HF_CFG[11] origin:064-gtp-channel-conf 29_341 -GTP_CHANNEL_1.GTPE2.RXLPM_HF_CFG[12] origin:064-gtp-channel-conf 28_342 -GTP_CHANNEL_1.GTPE2.RXLPM_HF_CFG[13] origin:064-gtp-channel-conf 29_342 -GTP_CHANNEL_1.GTPE2.RXLPM_HF_CFG2[0] origin:064-gtp-channel-conf 30_424 -GTP_CHANNEL_1.GTPE2.RXLPM_HF_CFG2[1] origin:064-gtp-channel-conf 31_424 -GTP_CHANNEL_1.GTPE2.RXLPM_HF_CFG2[2] origin:064-gtp-channel-conf 30_425 -GTP_CHANNEL_1.GTPE2.RXLPM_HF_CFG2[3] origin:064-gtp-channel-conf 31_425 -GTP_CHANNEL_1.GTPE2.RXLPM_HF_CFG2[4] origin:064-gtp-channel-conf 30_426 -GTP_CHANNEL_1.GTPE2.RXLPM_HF_CFG3[0] origin:064-gtp-channel-conf 31_389 -GTP_CHANNEL_1.GTPE2.RXLPM_HF_CFG3[1] origin:064-gtp-channel-conf 30_390 -GTP_CHANNEL_1.GTPE2.RXLPM_HF_CFG3[2] origin:064-gtp-channel-conf 31_390 -GTP_CHANNEL_1.GTPE2.RXLPM_HF_CFG3[3] origin:064-gtp-channel-conf 30_391 -GTP_CHANNEL_1.GTPE2.RXLPM_HOLD_DURING_EIDLE[0] origin:064-gtp-channel-conf 28_247 -GTP_CHANNEL_1.GTPE2.RXLPM_INCM_CFG[0] origin:064-gtp-channel-conf 30_439 -GTP_CHANNEL_1.GTPE2.RXLPM_IPCM_CFG[0] origin:064-gtp-channel-conf 31_439 -GTP_CHANNEL_1.GTPE2.RXLPM_LF_CFG[0] origin:064-gtp-channel-conf 28_344 -GTP_CHANNEL_1.GTPE2.RXLPM_LF_CFG[1] origin:064-gtp-channel-conf 29_344 -GTP_CHANNEL_1.GTPE2.RXLPM_LF_CFG[2] origin:064-gtp-channel-conf 28_345 -GTP_CHANNEL_1.GTPE2.RXLPM_LF_CFG[3] origin:064-gtp-channel-conf 29_345 -GTP_CHANNEL_1.GTPE2.RXLPM_LF_CFG[4] origin:064-gtp-channel-conf 28_346 -GTP_CHANNEL_1.GTPE2.RXLPM_LF_CFG[5] origin:064-gtp-channel-conf 29_346 -GTP_CHANNEL_1.GTPE2.RXLPM_LF_CFG[6] origin:064-gtp-channel-conf 28_347 -GTP_CHANNEL_1.GTPE2.RXLPM_LF_CFG[7] origin:064-gtp-channel-conf 29_347 -GTP_CHANNEL_1.GTPE2.RXLPM_LF_CFG[8] origin:064-gtp-channel-conf 28_348 -GTP_CHANNEL_1.GTPE2.RXLPM_LF_CFG[9] origin:064-gtp-channel-conf 29_348 -GTP_CHANNEL_1.GTPE2.RXLPM_LF_CFG[10] origin:064-gtp-channel-conf 28_349 -GTP_CHANNEL_1.GTPE2.RXLPM_LF_CFG[11] origin:064-gtp-channel-conf 29_349 -GTP_CHANNEL_1.GTPE2.RXLPM_LF_CFG[12] origin:064-gtp-channel-conf 28_350 -GTP_CHANNEL_1.GTPE2.RXLPM_LF_CFG[13] origin:064-gtp-channel-conf 29_350 -GTP_CHANNEL_1.GTPE2.RXLPM_LF_CFG[14] origin:064-gtp-channel-conf 28_351 -GTP_CHANNEL_1.GTPE2.RXLPM_LF_CFG[15] origin:064-gtp-channel-conf 29_351 -GTP_CHANNEL_1.GTPE2.RXLPM_LF_CFG[16] origin:064-gtp-channel-conf 28_343 -GTP_CHANNEL_1.GTPE2.RXLPM_LF_CFG[17] origin:064-gtp-channel-conf 29_343 -GTP_CHANNEL_1.GTPE2.RXLPM_LF_CFG2[0] origin:064-gtp-channel-conf 31_426 -GTP_CHANNEL_1.GTPE2.RXLPM_LF_CFG2[1] origin:064-gtp-channel-conf 30_427 -GTP_CHANNEL_1.GTPE2.RXLPM_LF_CFG2[2] origin:064-gtp-channel-conf 31_427 -GTP_CHANNEL_1.GTPE2.RXLPM_LF_CFG2[3] origin:064-gtp-channel-conf 30_428 -GTP_CHANNEL_1.GTPE2.RXLPM_LF_CFG2[4] origin:064-gtp-channel-conf 31_428 -GTP_CHANNEL_1.GTPE2.RXLPM_OSINT_CFG[0] origin:064-gtp-channel-conf 30_440 -GTP_CHANNEL_1.GTPE2.RXLPM_OSINT_CFG[1] origin:064-gtp-channel-conf 31_440 -GTP_CHANNEL_1.GTPE2.RXLPM_OSINT_CFG[2] origin:064-gtp-channel-conf 30_441 -GTP_CHANNEL_1.GTPE2.RXLPM_CFG1[0] origin:064-gtp-channel-conf 30_330 -GTP_CHANNEL_1.GTPE2.RXLPMRESET_TIME[0] origin:064-gtp-channel-conf 28_112 -GTP_CHANNEL_1.GTPE2.RXLPMRESET_TIME[1] origin:064-gtp-channel-conf 29_112 -GTP_CHANNEL_1.GTPE2.RXLPMRESET_TIME[2] origin:064-gtp-channel-conf 28_113 -GTP_CHANNEL_1.GTPE2.RXLPMRESET_TIME[3] origin:064-gtp-channel-conf 29_113 -GTP_CHANNEL_1.GTPE2.RXLPMRESET_TIME[4] origin:064-gtp-channel-conf 28_114 -GTP_CHANNEL_1.GTPE2.RXLPMRESET_TIME[5] origin:064-gtp-channel-conf 29_114 -GTP_CHANNEL_1.GTPE2.RXLPMRESET_TIME[6] origin:064-gtp-channel-conf 28_115 -GTP_CHANNEL_1.GTPE2.RXOOB_CFG[0] origin:064-gtp-channel-conf 28_144 -GTP_CHANNEL_1.GTPE2.RXOOB_CFG[1] origin:064-gtp-channel-conf 29_144 -GTP_CHANNEL_1.GTPE2.RXOOB_CFG[2] origin:064-gtp-channel-conf 28_145 -GTP_CHANNEL_1.GTPE2.RXOOB_CFG[3] origin:064-gtp-channel-conf 29_145 -GTP_CHANNEL_1.GTPE2.RXOOB_CFG[4] origin:064-gtp-channel-conf 28_146 -GTP_CHANNEL_1.GTPE2.RXOOB_CFG[5] origin:064-gtp-channel-conf 29_146 -GTP_CHANNEL_1.GTPE2.RXOOB_CFG[6] origin:064-gtp-channel-conf 28_147 -GTP_CHANNEL_1.GTPE2.RXOOB_CLK_CFG.FABRIC origin:064-gtp-channel-conf 31_129 -GTP_CHANNEL_1.GTPE2.RXOSCALRESET_TIME[0] origin:064-gtp-channel-conf 28_187 -GTP_CHANNEL_1.GTPE2.RXOSCALRESET_TIME[1] origin:064-gtp-channel-conf 29_187 -GTP_CHANNEL_1.GTPE2.RXOSCALRESET_TIME[2] origin:064-gtp-channel-conf 28_188 -GTP_CHANNEL_1.GTPE2.RXOSCALRESET_TIME[3] origin:064-gtp-channel-conf 29_188 -GTP_CHANNEL_1.GTPE2.RXOSCALRESET_TIME[4] origin:064-gtp-channel-conf 28_189 -GTP_CHANNEL_1.GTPE2.RXOSCALRESET_TIMEOUT[0] origin:064-gtp-channel-conf 29_189 -GTP_CHANNEL_1.GTPE2.RXOSCALRESET_TIMEOUT[1] origin:064-gtp-channel-conf 28_190 -GTP_CHANNEL_1.GTPE2.RXOSCALRESET_TIMEOUT[2] origin:064-gtp-channel-conf 29_190 -GTP_CHANNEL_1.GTPE2.RXOSCALRESET_TIMEOUT[3] origin:064-gtp-channel-conf 28_191 -GTP_CHANNEL_1.GTPE2.RXOSCALRESET_TIMEOUT[4] origin:064-gtp-channel-conf 29_191 -GTP_CHANNEL_1.GTPE2.RXOUT_DIV[0] origin:064-gtp-channel-conf 30_384 -GTP_CHANNEL_1.GTPE2.RXOUT_DIV[1] origin:064-gtp-channel-conf 31_384 -GTP_CHANNEL_1.GTPE2.RXPCSRESET_TIME[0] origin:064-gtp-channel-conf 29_115 -GTP_CHANNEL_1.GTPE2.RXPCSRESET_TIME[1] origin:064-gtp-channel-conf 28_116 -GTP_CHANNEL_1.GTPE2.RXPCSRESET_TIME[2] origin:064-gtp-channel-conf 29_116 -GTP_CHANNEL_1.GTPE2.RXPCSRESET_TIME[3] origin:064-gtp-channel-conf 28_117 -GTP_CHANNEL_1.GTPE2.RXPCSRESET_TIME[4] origin:064-gtp-channel-conf 29_117 -GTP_CHANNEL_1.GTPE2.RXPH_CFG[0] origin:064-gtp-channel-conf 30_584 -GTP_CHANNEL_1.GTPE2.RXPH_CFG[1] origin:064-gtp-channel-conf 31_584 -GTP_CHANNEL_1.GTPE2.RXPH_CFG[2] origin:064-gtp-channel-conf 30_585 -GTP_CHANNEL_1.GTPE2.RXPH_CFG[3] origin:064-gtp-channel-conf 31_585 -GTP_CHANNEL_1.GTPE2.RXPH_CFG[4] origin:064-gtp-channel-conf 30_586 -GTP_CHANNEL_1.GTPE2.RXPH_CFG[5] origin:064-gtp-channel-conf 31_586 -GTP_CHANNEL_1.GTPE2.RXPH_CFG[6] origin:064-gtp-channel-conf 30_587 -GTP_CHANNEL_1.GTPE2.RXPH_CFG[7] origin:064-gtp-channel-conf 31_587 -GTP_CHANNEL_1.GTPE2.RXPH_CFG[8] origin:064-gtp-channel-conf 30_588 -GTP_CHANNEL_1.GTPE2.RXPH_CFG[9] origin:064-gtp-channel-conf 31_588 -GTP_CHANNEL_1.GTPE2.RXPH_CFG[10] origin:064-gtp-channel-conf 30_589 -GTP_CHANNEL_1.GTPE2.RXPH_CFG[11] origin:064-gtp-channel-conf 31_589 -GTP_CHANNEL_1.GTPE2.RXPH_CFG[12] origin:064-gtp-channel-conf 30_590 -GTP_CHANNEL_1.GTPE2.RXPH_CFG[13] origin:064-gtp-channel-conf 31_590 -GTP_CHANNEL_1.GTPE2.RXPH_CFG[14] origin:064-gtp-channel-conf 30_591 -GTP_CHANNEL_1.GTPE2.RXPH_CFG[15] origin:064-gtp-channel-conf 31_591 -GTP_CHANNEL_1.GTPE2.RXPH_CFG[16] origin:064-gtp-channel-conf 30_592 -GTP_CHANNEL_1.GTPE2.RXPH_CFG[17] origin:064-gtp-channel-conf 31_592 -GTP_CHANNEL_1.GTPE2.RXPH_CFG[18] origin:064-gtp-channel-conf 30_593 -GTP_CHANNEL_1.GTPE2.RXPH_CFG[19] origin:064-gtp-channel-conf 31_593 -GTP_CHANNEL_1.GTPE2.RXPH_CFG[20] origin:064-gtp-channel-conf 30_594 -GTP_CHANNEL_1.GTPE2.RXPH_CFG[21] origin:064-gtp-channel-conf 31_594 -GTP_CHANNEL_1.GTPE2.RXPH_CFG[22] origin:064-gtp-channel-conf 30_595 -GTP_CHANNEL_1.GTPE2.RXPH_CFG[23] origin:064-gtp-channel-conf 31_595 -GTP_CHANNEL_1.GTPE2.RXPH_MONITOR_SEL[0] origin:064-gtp-channel-conf 28_700 -GTP_CHANNEL_1.GTPE2.RXPH_MONITOR_SEL[1] origin:064-gtp-channel-conf 29_700 -GTP_CHANNEL_1.GTPE2.RXPH_MONITOR_SEL[2] origin:064-gtp-channel-conf 28_701 -GTP_CHANNEL_1.GTPE2.RXPH_MONITOR_SEL[3] origin:064-gtp-channel-conf 29_701 -GTP_CHANNEL_1.GTPE2.RXPH_MONITOR_SEL[4] origin:064-gtp-channel-conf 28_702 -GTP_CHANNEL_1.GTPE2.RXPHDLY_CFG[0] origin:064-gtp-channel-conf 30_600 -GTP_CHANNEL_1.GTPE2.RXPHDLY_CFG[1] origin:064-gtp-channel-conf 31_600 -GTP_CHANNEL_1.GTPE2.RXPHDLY_CFG[2] origin:064-gtp-channel-conf 30_601 -GTP_CHANNEL_1.GTPE2.RXPHDLY_CFG[3] origin:064-gtp-channel-conf 31_601 -GTP_CHANNEL_1.GTPE2.RXPHDLY_CFG[4] origin:064-gtp-channel-conf 30_602 -GTP_CHANNEL_1.GTPE2.RXPHDLY_CFG[5] origin:064-gtp-channel-conf 31_602 -GTP_CHANNEL_1.GTPE2.RXPHDLY_CFG[6] origin:064-gtp-channel-conf 30_603 -GTP_CHANNEL_1.GTPE2.RXPHDLY_CFG[7] origin:064-gtp-channel-conf 31_603 -GTP_CHANNEL_1.GTPE2.RXPHDLY_CFG[8] origin:064-gtp-channel-conf 30_604 -GTP_CHANNEL_1.GTPE2.RXPHDLY_CFG[9] origin:064-gtp-channel-conf 31_604 -GTP_CHANNEL_1.GTPE2.RXPHDLY_CFG[10] origin:064-gtp-channel-conf 30_605 -GTP_CHANNEL_1.GTPE2.RXPHDLY_CFG[11] origin:064-gtp-channel-conf 31_605 -GTP_CHANNEL_1.GTPE2.RXPHDLY_CFG[12] origin:064-gtp-channel-conf 30_606 -GTP_CHANNEL_1.GTPE2.RXPHDLY_CFG[13] origin:064-gtp-channel-conf 31_606 -GTP_CHANNEL_1.GTPE2.RXPHDLY_CFG[14] origin:064-gtp-channel-conf 30_607 -GTP_CHANNEL_1.GTPE2.RXPHDLY_CFG[15] origin:064-gtp-channel-conf 31_607 -GTP_CHANNEL_1.GTPE2.RXPHDLY_CFG[16] origin:064-gtp-channel-conf 30_608 -GTP_CHANNEL_1.GTPE2.RXPHDLY_CFG[17] origin:064-gtp-channel-conf 31_608 -GTP_CHANNEL_1.GTPE2.RXPHDLY_CFG[18] origin:064-gtp-channel-conf 30_609 -GTP_CHANNEL_1.GTPE2.RXPHDLY_CFG[19] origin:064-gtp-channel-conf 31_609 -GTP_CHANNEL_1.GTPE2.RXPHDLY_CFG[20] origin:064-gtp-channel-conf 30_610 -GTP_CHANNEL_1.GTPE2.RXPHDLY_CFG[21] origin:064-gtp-channel-conf 31_610 -GTP_CHANNEL_1.GTPE2.RXPHDLY_CFG[22] origin:064-gtp-channel-conf 30_611 -GTP_CHANNEL_1.GTPE2.RXPHDLY_CFG[23] origin:064-gtp-channel-conf 31_611 -GTP_CHANNEL_1.GTPE2.RXPI_CFG0[0] origin:064-gtp-channel-conf 31_430 -GTP_CHANNEL_1.GTPE2.RXPI_CFG0[1] origin:064-gtp-channel-conf 30_431 -GTP_CHANNEL_1.GTPE2.RXPI_CFG0[2] origin:064-gtp-channel-conf 31_431 -GTP_CHANNEL_1.GTPE2.RXPI_CFG1[0] origin:064-gtp-channel-conf 30_442 -GTP_CHANNEL_1.GTPE2.RXPI_CFG2[0] origin:064-gtp-channel-conf 31_441 -GTP_CHANNEL_1.GTPE2.RXPMARESET_TIME[0] origin:064-gtp-channel-conf 28_104 -GTP_CHANNEL_1.GTPE2.RXPMARESET_TIME[1] origin:064-gtp-channel-conf 29_104 -GTP_CHANNEL_1.GTPE2.RXPMARESET_TIME[2] origin:064-gtp-channel-conf 28_105 -GTP_CHANNEL_1.GTPE2.RXPMARESET_TIME[3] origin:064-gtp-channel-conf 29_105 -GTP_CHANNEL_1.GTPE2.RXPMARESET_TIME[4] origin:064-gtp-channel-conf 28_106 -GTP_CHANNEL_1.GTPE2.RXPRBS_ERR_LOOPBACK[0] origin:064-gtp-channel-conf 28_136 -GTP_CHANNEL_1.GTPE2.RXSLIDE_AUTO_WAIT[0] origin:064-gtp-channel-conf 28_520 -GTP_CHANNEL_1.GTPE2.RXSLIDE_AUTO_WAIT[1] origin:064-gtp-channel-conf 29_520 -GTP_CHANNEL_1.GTPE2.RXSLIDE_AUTO_WAIT[2] origin:064-gtp-channel-conf 28_521 -GTP_CHANNEL_1.GTPE2.RXSLIDE_AUTO_WAIT[3] origin:064-gtp-channel-conf 29_521 -GTP_CHANNEL_1.GTPE2.RXSLIDE_MODE.AUTO origin:064-gtp-channel-conf !29_519 28_519 -GTP_CHANNEL_1.GTPE2.RXSLIDE_MODE.PCS origin:064-gtp-channel-conf !28_519 29_519 -GTP_CHANNEL_1.GTPE2.RXSLIDE_MODE.PMA origin:064-gtp-channel-conf 28_519 29_519 -GTP_CHANNEL_1.GTPE2.RXSYNC_MULTILANE[0] origin:064-gtp-channel-conf 28_133 -GTP_CHANNEL_1.GTPE2.RXSYNC_OVRD[0] origin:064-gtp-channel-conf 29_135 -GTP_CHANNEL_1.GTPE2.RXSYNC_SKIP_DA[0] origin:064-gtp-channel-conf 29_134 -GTP_CHANNEL_1.GTPE2.SAS_MAX_COM[0] origin:064-gtp-channel-conf 28_171 -GTP_CHANNEL_1.GTPE2.SAS_MAX_COM[1] origin:064-gtp-channel-conf 29_171 -GTP_CHANNEL_1.GTPE2.SAS_MAX_COM[2] origin:064-gtp-channel-conf 28_172 -GTP_CHANNEL_1.GTPE2.SAS_MAX_COM[3] origin:064-gtp-channel-conf 29_172 -GTP_CHANNEL_1.GTPE2.SAS_MAX_COM[4] origin:064-gtp-channel-conf 28_173 -GTP_CHANNEL_1.GTPE2.SAS_MAX_COM[5] origin:064-gtp-channel-conf 29_173 -GTP_CHANNEL_1.GTPE2.SAS_MAX_COM[6] origin:064-gtp-channel-conf 28_174 -GTP_CHANNEL_1.GTPE2.SAS_MIN_COM[0] origin:064-gtp-channel-conf 29_156 -GTP_CHANNEL_1.GTPE2.SAS_MIN_COM[1] origin:064-gtp-channel-conf 28_157 -GTP_CHANNEL_1.GTPE2.SAS_MIN_COM[2] origin:064-gtp-channel-conf 29_157 -GTP_CHANNEL_1.GTPE2.SAS_MIN_COM[3] origin:064-gtp-channel-conf 28_158 -GTP_CHANNEL_1.GTPE2.SAS_MIN_COM[4] origin:064-gtp-channel-conf 29_158 -GTP_CHANNEL_1.GTPE2.SAS_MIN_COM[5] origin:064-gtp-channel-conf 28_159 -GTP_CHANNEL_1.GTPE2.SATA_BURST_SEQ_LEN[0] origin:064-gtp-channel-conf 28_150 -GTP_CHANNEL_1.GTPE2.SATA_BURST_SEQ_LEN[1] origin:064-gtp-channel-conf 29_150 -GTP_CHANNEL_1.GTPE2.SATA_BURST_SEQ_LEN[2] origin:064-gtp-channel-conf 28_151 -GTP_CHANNEL_1.GTPE2.SATA_BURST_SEQ_LEN[3] origin:064-gtp-channel-conf 29_151 -GTP_CHANNEL_1.GTPE2.SATA_BURST_VAL[0] origin:064-gtp-channel-conf 29_147 -GTP_CHANNEL_1.GTPE2.SATA_BURST_VAL[1] origin:064-gtp-channel-conf 28_148 -GTP_CHANNEL_1.GTPE2.SATA_BURST_VAL[2] origin:064-gtp-channel-conf 29_148 -GTP_CHANNEL_1.GTPE2.SATA_EIDLE_VAL[0] origin:064-gtp-channel-conf 28_152 -GTP_CHANNEL_1.GTPE2.SATA_EIDLE_VAL[1] origin:064-gtp-channel-conf 29_152 -GTP_CHANNEL_1.GTPE2.SATA_EIDLE_VAL[2] origin:064-gtp-channel-conf 28_153 -GTP_CHANNEL_1.GTPE2.SATA_MAX_BURST[0] origin:064-gtp-channel-conf 28_168 -GTP_CHANNEL_1.GTPE2.SATA_MAX_BURST[1] origin:064-gtp-channel-conf 29_168 -GTP_CHANNEL_1.GTPE2.SATA_MAX_BURST[2] origin:064-gtp-channel-conf 28_169 -GTP_CHANNEL_1.GTPE2.SATA_MAX_BURST[3] origin:064-gtp-channel-conf 29_169 -GTP_CHANNEL_1.GTPE2.SATA_MAX_BURST[4] origin:064-gtp-channel-conf 28_170 -GTP_CHANNEL_1.GTPE2.SATA_MAX_BURST[5] origin:064-gtp-channel-conf 29_170 -GTP_CHANNEL_1.GTPE2.SATA_MAX_INIT[0] origin:064-gtp-channel-conf 28_176 -GTP_CHANNEL_1.GTPE2.SATA_MAX_INIT[1] origin:064-gtp-channel-conf 29_176 -GTP_CHANNEL_1.GTPE2.SATA_MAX_INIT[2] origin:064-gtp-channel-conf 28_177 -GTP_CHANNEL_1.GTPE2.SATA_MAX_INIT[3] origin:064-gtp-channel-conf 29_177 -GTP_CHANNEL_1.GTPE2.SATA_MAX_INIT[4] origin:064-gtp-channel-conf 28_178 -GTP_CHANNEL_1.GTPE2.SATA_MAX_INIT[5] origin:064-gtp-channel-conf 29_178 -GTP_CHANNEL_1.GTPE2.SATA_MAX_WAKE[0] origin:064-gtp-channel-conf 28_179 -GTP_CHANNEL_1.GTPE2.SATA_MAX_WAKE[1] origin:064-gtp-channel-conf 29_179 -GTP_CHANNEL_1.GTPE2.SATA_MAX_WAKE[2] origin:064-gtp-channel-conf 28_180 -GTP_CHANNEL_1.GTPE2.SATA_MAX_WAKE[3] origin:064-gtp-channel-conf 29_180 -GTP_CHANNEL_1.GTPE2.SATA_MAX_WAKE[4] origin:064-gtp-channel-conf 28_181 -GTP_CHANNEL_1.GTPE2.SATA_MAX_WAKE[5] origin:064-gtp-channel-conf 29_181 -GTP_CHANNEL_1.GTPE2.SATA_MIN_BURST[0] origin:064-gtp-channel-conf 29_153 -GTP_CHANNEL_1.GTPE2.SATA_MIN_BURST[1] origin:064-gtp-channel-conf 28_154 -GTP_CHANNEL_1.GTPE2.SATA_MIN_BURST[2] origin:064-gtp-channel-conf 29_154 -GTP_CHANNEL_1.GTPE2.SATA_MIN_BURST[3] origin:064-gtp-channel-conf 28_155 -GTP_CHANNEL_1.GTPE2.SATA_MIN_BURST[4] origin:064-gtp-channel-conf 29_155 -GTP_CHANNEL_1.GTPE2.SATA_MIN_BURST[5] origin:064-gtp-channel-conf 28_156 -GTP_CHANNEL_1.GTPE2.SATA_MIN_INIT[0] origin:064-gtp-channel-conf 28_160 -GTP_CHANNEL_1.GTPE2.SATA_MIN_INIT[1] origin:064-gtp-channel-conf 29_160 -GTP_CHANNEL_1.GTPE2.SATA_MIN_INIT[2] origin:064-gtp-channel-conf 28_161 -GTP_CHANNEL_1.GTPE2.SATA_MIN_INIT[3] origin:064-gtp-channel-conf 29_161 -GTP_CHANNEL_1.GTPE2.SATA_MIN_INIT[4] origin:064-gtp-channel-conf 28_162 -GTP_CHANNEL_1.GTPE2.SATA_MIN_INIT[5] origin:064-gtp-channel-conf 29_162 -GTP_CHANNEL_1.GTPE2.SATA_MIN_WAKE[0] origin:064-gtp-channel-conf 28_163 -GTP_CHANNEL_1.GTPE2.SATA_MIN_WAKE[1] origin:064-gtp-channel-conf 29_163 -GTP_CHANNEL_1.GTPE2.SATA_MIN_WAKE[2] origin:064-gtp-channel-conf 28_164 -GTP_CHANNEL_1.GTPE2.SATA_MIN_WAKE[3] origin:064-gtp-channel-conf 29_164 -GTP_CHANNEL_1.GTPE2.SATA_MIN_WAKE[4] origin:064-gtp-channel-conf 28_165 -GTP_CHANNEL_1.GTPE2.SATA_MIN_WAKE[5] origin:064-gtp-channel-conf 29_165 -GTP_CHANNEL_1.GTPE2.SATA_PLL_CFG.VCO_1500MHZ origin:064-gtp-channel-conf 30_55 -GTP_CHANNEL_1.GTPE2.SATA_PLL_CFG.VCO_750MHZ origin:064-gtp-channel-conf 31_55 -GTP_CHANNEL_1.GTPE2.SHOW_REALIGN_COMMA origin:064-gtp-channel-conf 29_522 -GTP_CHANNEL_1.GTPE2.TERM_RCAL_CFG[0] origin:064-gtp-channel-conf 30_136 -GTP_CHANNEL_1.GTPE2.TERM_RCAL_CFG[1] origin:064-gtp-channel-conf 31_136 -GTP_CHANNEL_1.GTPE2.TERM_RCAL_CFG[2] origin:064-gtp-channel-conf 30_137 -GTP_CHANNEL_1.GTPE2.TERM_RCAL_CFG[3] origin:064-gtp-channel-conf 31_137 -GTP_CHANNEL_1.GTPE2.TERM_RCAL_CFG[4] origin:064-gtp-channel-conf 30_138 -GTP_CHANNEL_1.GTPE2.TERM_RCAL_CFG[5] origin:064-gtp-channel-conf 31_138 -GTP_CHANNEL_1.GTPE2.TERM_RCAL_CFG[6] origin:064-gtp-channel-conf 30_139 -GTP_CHANNEL_1.GTPE2.TERM_RCAL_CFG[7] origin:064-gtp-channel-conf 31_139 -GTP_CHANNEL_1.GTPE2.TERM_RCAL_CFG[8] origin:064-gtp-channel-conf 30_140 -GTP_CHANNEL_1.GTPE2.TERM_RCAL_CFG[9] origin:064-gtp-channel-conf 31_140 -GTP_CHANNEL_1.GTPE2.TERM_RCAL_CFG[10] origin:064-gtp-channel-conf 30_141 -GTP_CHANNEL_1.GTPE2.TERM_RCAL_CFG[11] origin:064-gtp-channel-conf 31_141 -GTP_CHANNEL_1.GTPE2.TERM_RCAL_CFG[12] origin:064-gtp-channel-conf 30_142 -GTP_CHANNEL_1.GTPE2.TERM_RCAL_CFG[13] origin:064-gtp-channel-conf 31_142 -GTP_CHANNEL_1.GTPE2.TERM_RCAL_CFG[14] origin:064-gtp-channel-conf 30_143 -GTP_CHANNEL_1.GTPE2.TERM_RCAL_OVRD[0] origin:064-gtp-channel-conf 31_150 -GTP_CHANNEL_1.GTPE2.TERM_RCAL_OVRD[1] origin:064-gtp-channel-conf 30_151 -GTP_CHANNEL_1.GTPE2.TERM_RCAL_OVRD[2] origin:064-gtp-channel-conf 31_151 -GTP_CHANNEL_1.GTPE2.TRANS_TIME_RATE[0] origin:064-gtp-channel-conf 28_192 -GTP_CHANNEL_1.GTPE2.TRANS_TIME_RATE[1] origin:064-gtp-channel-conf 29_192 -GTP_CHANNEL_1.GTPE2.TRANS_TIME_RATE[2] origin:064-gtp-channel-conf 28_193 -GTP_CHANNEL_1.GTPE2.TRANS_TIME_RATE[3] origin:064-gtp-channel-conf 29_193 -GTP_CHANNEL_1.GTPE2.TRANS_TIME_RATE[4] origin:064-gtp-channel-conf 28_194 -GTP_CHANNEL_1.GTPE2.TRANS_TIME_RATE[5] origin:064-gtp-channel-conf 29_194 -GTP_CHANNEL_1.GTPE2.TRANS_TIME_RATE[6] origin:064-gtp-channel-conf 28_195 -GTP_CHANNEL_1.GTPE2.TRANS_TIME_RATE[7] origin:064-gtp-channel-conf 29_195 -GTP_CHANNEL_1.GTPE2.TST_RSV[0] origin:064-gtp-channel-conf 30_504 -GTP_CHANNEL_1.GTPE2.TST_RSV[1] origin:064-gtp-channel-conf 31_504 -GTP_CHANNEL_1.GTPE2.TST_RSV[2] origin:064-gtp-channel-conf 30_505 -GTP_CHANNEL_1.GTPE2.TST_RSV[3] origin:064-gtp-channel-conf 31_505 -GTP_CHANNEL_1.GTPE2.TST_RSV[4] origin:064-gtp-channel-conf 30_506 -GTP_CHANNEL_1.GTPE2.TST_RSV[5] origin:064-gtp-channel-conf 31_506 -GTP_CHANNEL_1.GTPE2.TST_RSV[6] origin:064-gtp-channel-conf 30_507 -GTP_CHANNEL_1.GTPE2.TST_RSV[7] origin:064-gtp-channel-conf 31_507 -GTP_CHANNEL_1.GTPE2.TST_RSV[8] origin:064-gtp-channel-conf 30_508 -GTP_CHANNEL_1.GTPE2.TST_RSV[9] origin:064-gtp-channel-conf 31_508 -GTP_CHANNEL_1.GTPE2.TST_RSV[10] origin:064-gtp-channel-conf 30_509 -GTP_CHANNEL_1.GTPE2.TST_RSV[11] origin:064-gtp-channel-conf 31_509 -GTP_CHANNEL_1.GTPE2.TST_RSV[12] origin:064-gtp-channel-conf 30_510 -GTP_CHANNEL_1.GTPE2.TST_RSV[13] origin:064-gtp-channel-conf 31_510 -GTP_CHANNEL_1.GTPE2.TST_RSV[14] origin:064-gtp-channel-conf 30_511 -GTP_CHANNEL_1.GTPE2.TST_RSV[15] origin:064-gtp-channel-conf 31_511 -GTP_CHANNEL_1.GTPE2.TST_RSV[16] origin:064-gtp-channel-conf 30_512 -GTP_CHANNEL_1.GTPE2.TST_RSV[17] origin:064-gtp-channel-conf 31_512 -GTP_CHANNEL_1.GTPE2.TST_RSV[18] origin:064-gtp-channel-conf 30_513 -GTP_CHANNEL_1.GTPE2.TST_RSV[19] origin:064-gtp-channel-conf 31_513 -GTP_CHANNEL_1.GTPE2.TST_RSV[20] origin:064-gtp-channel-conf 30_514 -GTP_CHANNEL_1.GTPE2.TST_RSV[21] origin:064-gtp-channel-conf 31_514 -GTP_CHANNEL_1.GTPE2.TST_RSV[22] origin:064-gtp-channel-conf 30_515 -GTP_CHANNEL_1.GTPE2.TST_RSV[23] origin:064-gtp-channel-conf 31_515 -GTP_CHANNEL_1.GTPE2.TST_RSV[24] origin:064-gtp-channel-conf 30_516 -GTP_CHANNEL_1.GTPE2.TST_RSV[25] origin:064-gtp-channel-conf 31_516 -GTP_CHANNEL_1.GTPE2.TST_RSV[26] origin:064-gtp-channel-conf 30_517 -GTP_CHANNEL_1.GTPE2.TST_RSV[27] origin:064-gtp-channel-conf 31_517 -GTP_CHANNEL_1.GTPE2.TST_RSV[28] origin:064-gtp-channel-conf 30_518 -GTP_CHANNEL_1.GTPE2.TST_RSV[29] origin:064-gtp-channel-conf 31_518 -GTP_CHANNEL_1.GTPE2.TST_RSV[30] origin:064-gtp-channel-conf 30_519 -GTP_CHANNEL_1.GTPE2.TST_RSV[31] origin:064-gtp-channel-conf 31_519 -GTP_CHANNEL_1.GTPE2.TX_CLKMUX_EN[0] origin:064-gtp-channel-conf 31_128 -GTP_CHANNEL_1.GTPE2.TX_DATA_WIDTH[0] origin:064-gtp-channel-conf 30_152 -GTP_CHANNEL_1.GTPE2.TX_DATA_WIDTH[1] origin:064-gtp-channel-conf 31_152 -GTP_CHANNEL_1.GTPE2.TX_DATA_WIDTH[2] origin:064-gtp-channel-conf 30_153 -GTP_CHANNEL_1.GTPE2.TX_DRIVE_MODE.PIPE origin:064-gtp-channel-conf 28_200 -GTP_CHANNEL_1.GTPE2.TX_EIDLE_ASSERT_DELAY[0] origin:064-gtp-channel-conf 28_203 -GTP_CHANNEL_1.GTPE2.TX_EIDLE_ASSERT_DELAY[1] origin:064-gtp-channel-conf 29_203 -GTP_CHANNEL_1.GTPE2.TX_EIDLE_ASSERT_DELAY[2] origin:064-gtp-channel-conf 28_204 -GTP_CHANNEL_1.GTPE2.TX_EIDLE_DEASSERT_DELAY[0] origin:064-gtp-channel-conf 29_204 -GTP_CHANNEL_1.GTPE2.TX_EIDLE_DEASSERT_DELAY[1] origin:064-gtp-channel-conf 28_205 -GTP_CHANNEL_1.GTPE2.TX_EIDLE_DEASSERT_DELAY[2] origin:064-gtp-channel-conf 29_205 -GTP_CHANNEL_1.GTPE2.TX_LOOPBACK_DRIVE_HIZ origin:064-gtp-channel-conf 29_202 -GTP_CHANNEL_1.GTPE2.TX_MAINCURSOR_SEL[0] origin:064-gtp-channel-conf 31_289 -GTP_CHANNEL_1.GTPE2.TX_MARGIN_FULL_0[0] origin:064-gtp-channel-conf 30_232 -GTP_CHANNEL_1.GTPE2.TX_MARGIN_FULL_0[1] origin:064-gtp-channel-conf 31_232 -GTP_CHANNEL_1.GTPE2.TX_MARGIN_FULL_0[2] origin:064-gtp-channel-conf 30_233 -GTP_CHANNEL_1.GTPE2.TX_MARGIN_FULL_0[3] origin:064-gtp-channel-conf 31_233 -GTP_CHANNEL_1.GTPE2.TX_MARGIN_FULL_0[4] origin:064-gtp-channel-conf 30_234 -GTP_CHANNEL_1.GTPE2.TX_MARGIN_FULL_0[5] origin:064-gtp-channel-conf 31_234 -GTP_CHANNEL_1.GTPE2.TX_MARGIN_FULL_0[6] origin:064-gtp-channel-conf 30_235 -GTP_CHANNEL_1.GTPE2.TX_MARGIN_FULL_1[0] origin:064-gtp-channel-conf 30_236 -GTP_CHANNEL_1.GTPE2.TX_MARGIN_FULL_1[1] origin:064-gtp-channel-conf 31_236 -GTP_CHANNEL_1.GTPE2.TX_MARGIN_FULL_1[2] origin:064-gtp-channel-conf 30_237 -GTP_CHANNEL_1.GTPE2.TX_MARGIN_FULL_1[3] origin:064-gtp-channel-conf 31_237 -GTP_CHANNEL_1.GTPE2.TX_MARGIN_FULL_1[4] origin:064-gtp-channel-conf 30_238 -GTP_CHANNEL_1.GTPE2.TX_MARGIN_FULL_1[5] origin:064-gtp-channel-conf 31_238 -GTP_CHANNEL_1.GTPE2.TX_MARGIN_FULL_1[6] origin:064-gtp-channel-conf 30_239 -GTP_CHANNEL_1.GTPE2.TX_MARGIN_FULL_2[0] origin:064-gtp-channel-conf 30_240 -GTP_CHANNEL_1.GTPE2.TX_MARGIN_FULL_2[1] origin:064-gtp-channel-conf 31_240 -GTP_CHANNEL_1.GTPE2.TX_MARGIN_FULL_2[2] origin:064-gtp-channel-conf 30_241 -GTP_CHANNEL_1.GTPE2.TX_MARGIN_FULL_2[3] origin:064-gtp-channel-conf 31_241 -GTP_CHANNEL_1.GTPE2.TX_MARGIN_FULL_2[4] origin:064-gtp-channel-conf 30_242 -GTP_CHANNEL_1.GTPE2.TX_MARGIN_FULL_2[5] origin:064-gtp-channel-conf 31_242 -GTP_CHANNEL_1.GTPE2.TX_MARGIN_FULL_2[6] origin:064-gtp-channel-conf 30_243 -GTP_CHANNEL_1.GTPE2.TX_MARGIN_FULL_3[0] origin:064-gtp-channel-conf 30_244 -GTP_CHANNEL_1.GTPE2.TX_MARGIN_FULL_3[1] origin:064-gtp-channel-conf 31_244 -GTP_CHANNEL_1.GTPE2.TX_MARGIN_FULL_3[2] origin:064-gtp-channel-conf 30_245 -GTP_CHANNEL_1.GTPE2.TX_MARGIN_FULL_3[3] origin:064-gtp-channel-conf 31_245 -GTP_CHANNEL_1.GTPE2.TX_MARGIN_FULL_3[4] origin:064-gtp-channel-conf 30_246 -GTP_CHANNEL_1.GTPE2.TX_MARGIN_FULL_3[5] origin:064-gtp-channel-conf 31_246 -GTP_CHANNEL_1.GTPE2.TX_MARGIN_FULL_3[6] origin:064-gtp-channel-conf 30_247 -GTP_CHANNEL_1.GTPE2.TX_MARGIN_FULL_4[0] origin:064-gtp-channel-conf 30_248 -GTP_CHANNEL_1.GTPE2.TX_MARGIN_FULL_4[1] origin:064-gtp-channel-conf 31_248 -GTP_CHANNEL_1.GTPE2.TX_MARGIN_FULL_4[2] origin:064-gtp-channel-conf 30_249 -GTP_CHANNEL_1.GTPE2.TX_MARGIN_FULL_4[3] origin:064-gtp-channel-conf 31_249 -GTP_CHANNEL_1.GTPE2.TX_MARGIN_FULL_4[4] origin:064-gtp-channel-conf 30_250 -GTP_CHANNEL_1.GTPE2.TX_MARGIN_FULL_4[5] origin:064-gtp-channel-conf 31_250 -GTP_CHANNEL_1.GTPE2.TX_MARGIN_FULL_4[6] origin:064-gtp-channel-conf 30_251 -GTP_CHANNEL_1.GTPE2.TX_MARGIN_LOW_0[0] origin:064-gtp-channel-conf 30_252 -GTP_CHANNEL_1.GTPE2.TX_MARGIN_LOW_0[1] origin:064-gtp-channel-conf 31_252 -GTP_CHANNEL_1.GTPE2.TX_MARGIN_LOW_0[2] origin:064-gtp-channel-conf 30_253 -GTP_CHANNEL_1.GTPE2.TX_MARGIN_LOW_0[3] origin:064-gtp-channel-conf 31_253 -GTP_CHANNEL_1.GTPE2.TX_MARGIN_LOW_0[4] origin:064-gtp-channel-conf 30_254 -GTP_CHANNEL_1.GTPE2.TX_MARGIN_LOW_0[5] origin:064-gtp-channel-conf 31_254 -GTP_CHANNEL_1.GTPE2.TX_MARGIN_LOW_0[6] origin:064-gtp-channel-conf 30_255 -GTP_CHANNEL_1.GTPE2.TX_MARGIN_LOW_1[0] origin:064-gtp-channel-conf 30_256 -GTP_CHANNEL_1.GTPE2.TX_MARGIN_LOW_1[1] origin:064-gtp-channel-conf 31_256 -GTP_CHANNEL_1.GTPE2.TX_MARGIN_LOW_1[2] origin:064-gtp-channel-conf 30_257 -GTP_CHANNEL_1.GTPE2.TX_MARGIN_LOW_1[3] origin:064-gtp-channel-conf 31_257 -GTP_CHANNEL_1.GTPE2.TX_MARGIN_LOW_1[4] origin:064-gtp-channel-conf 30_258 -GTP_CHANNEL_1.GTPE2.TX_MARGIN_LOW_1[5] origin:064-gtp-channel-conf 31_258 -GTP_CHANNEL_1.GTPE2.TX_MARGIN_LOW_1[6] origin:064-gtp-channel-conf 30_259 -GTP_CHANNEL_1.GTPE2.TX_MARGIN_LOW_2[0] origin:064-gtp-channel-conf 30_260 -GTP_CHANNEL_1.GTPE2.TX_MARGIN_LOW_2[1] origin:064-gtp-channel-conf 31_260 -GTP_CHANNEL_1.GTPE2.TX_MARGIN_LOW_2[2] origin:064-gtp-channel-conf 30_261 -GTP_CHANNEL_1.GTPE2.TX_MARGIN_LOW_2[3] origin:064-gtp-channel-conf 31_261 -GTP_CHANNEL_1.GTPE2.TX_MARGIN_LOW_2[4] origin:064-gtp-channel-conf 30_262 -GTP_CHANNEL_1.GTPE2.TX_MARGIN_LOW_2[5] origin:064-gtp-channel-conf 31_262 -GTP_CHANNEL_1.GTPE2.TX_MARGIN_LOW_2[6] origin:064-gtp-channel-conf 30_263 -GTP_CHANNEL_1.GTPE2.TX_MARGIN_LOW_3[0] origin:064-gtp-channel-conf 30_264 -GTP_CHANNEL_1.GTPE2.TX_MARGIN_LOW_3[1] origin:064-gtp-channel-conf 31_264 -GTP_CHANNEL_1.GTPE2.TX_MARGIN_LOW_3[2] origin:064-gtp-channel-conf 30_265 -GTP_CHANNEL_1.GTPE2.TX_MARGIN_LOW_3[3] origin:064-gtp-channel-conf 31_265 -GTP_CHANNEL_1.GTPE2.TX_MARGIN_LOW_3[4] origin:064-gtp-channel-conf 30_266 -GTP_CHANNEL_1.GTPE2.TX_MARGIN_LOW_3[5] origin:064-gtp-channel-conf 31_266 -GTP_CHANNEL_1.GTPE2.TX_MARGIN_LOW_3[6] origin:064-gtp-channel-conf 30_267 -GTP_CHANNEL_1.GTPE2.TX_MARGIN_LOW_4[0] origin:064-gtp-channel-conf 30_268 -GTP_CHANNEL_1.GTPE2.TX_MARGIN_LOW_4[1] origin:064-gtp-channel-conf 31_268 -GTP_CHANNEL_1.GTPE2.TX_MARGIN_LOW_4[2] origin:064-gtp-channel-conf 30_269 -GTP_CHANNEL_1.GTPE2.TX_MARGIN_LOW_4[3] origin:064-gtp-channel-conf 31_269 -GTP_CHANNEL_1.GTPE2.TX_MARGIN_LOW_4[4] origin:064-gtp-channel-conf 30_270 -GTP_CHANNEL_1.GTPE2.TX_MARGIN_LOW_4[5] origin:064-gtp-channel-conf 31_270 -GTP_CHANNEL_1.GTPE2.TX_MARGIN_LOW_4[6] origin:064-gtp-channel-conf 30_271 -GTP_CHANNEL_1.GTPE2.TX_PREDRIVER_MODE[0] origin:064-gtp-channel-conf 28_206 -GTP_CHANNEL_1.GTPE2.TX_RXDETECT_CFG[0] origin:064-gtp-channel-conf 30_296 -GTP_CHANNEL_1.GTPE2.TX_RXDETECT_CFG[1] origin:064-gtp-channel-conf 31_296 -GTP_CHANNEL_1.GTPE2.TX_RXDETECT_CFG[2] origin:064-gtp-channel-conf 30_297 -GTP_CHANNEL_1.GTPE2.TX_RXDETECT_CFG[3] origin:064-gtp-channel-conf 31_297 -GTP_CHANNEL_1.GTPE2.TX_RXDETECT_CFG[4] origin:064-gtp-channel-conf 30_298 -GTP_CHANNEL_1.GTPE2.TX_RXDETECT_CFG[5] origin:064-gtp-channel-conf 31_298 -GTP_CHANNEL_1.GTPE2.TX_RXDETECT_CFG[6] origin:064-gtp-channel-conf 30_299 -GTP_CHANNEL_1.GTPE2.TX_RXDETECT_CFG[7] origin:064-gtp-channel-conf 31_299 -GTP_CHANNEL_1.GTPE2.TX_RXDETECT_CFG[8] origin:064-gtp-channel-conf 30_300 -GTP_CHANNEL_1.GTPE2.TX_RXDETECT_CFG[9] origin:064-gtp-channel-conf 31_300 -GTP_CHANNEL_1.GTPE2.TX_RXDETECT_CFG[10] origin:064-gtp-channel-conf 30_301 -GTP_CHANNEL_1.GTPE2.TX_RXDETECT_CFG[11] origin:064-gtp-channel-conf 31_301 -GTP_CHANNEL_1.GTPE2.TX_RXDETECT_CFG[12] origin:064-gtp-channel-conf 30_302 -GTP_CHANNEL_1.GTPE2.TX_RXDETECT_CFG[13] origin:064-gtp-channel-conf 31_302 -GTP_CHANNEL_1.GTPE2.TX_RXDETECT_REF[0] origin:064-gtp-channel-conf 30_292 -GTP_CHANNEL_1.GTPE2.TX_RXDETECT_REF[1] origin:064-gtp-channel-conf 31_292 -GTP_CHANNEL_1.GTPE2.TX_RXDETECT_REF[2] origin:064-gtp-channel-conf 30_293 -GTP_CHANNEL_1.GTPE2.TX_XCLK_SEL.TXUSR origin:064-gtp-channel-conf 31_11 -GTP_CHANNEL_1.GTPE2.TX_CLK25_DIV[0] origin:064-gtp-channel-conf 30_144 -GTP_CHANNEL_1.GTPE2.TX_CLK25_DIV[1] origin:064-gtp-channel-conf 31_144 -GTP_CHANNEL_1.GTPE2.TX_CLK25_DIV[2] origin:064-gtp-channel-conf 30_145 -GTP_CHANNEL_1.GTPE2.TX_CLK25_DIV[3] origin:064-gtp-channel-conf 31_145 -GTP_CHANNEL_1.GTPE2.TX_CLK25_DIV[4] origin:064-gtp-channel-conf 30_146 -GTP_CHANNEL_1.GTPE2.TX_DEEMPH0[0] origin:064-gtp-channel-conf 30_272 -GTP_CHANNEL_1.GTPE2.TX_DEEMPH0[1] origin:064-gtp-channel-conf 31_272 -GTP_CHANNEL_1.GTPE2.TX_DEEMPH0[2] origin:064-gtp-channel-conf 30_273 -GTP_CHANNEL_1.GTPE2.TX_DEEMPH0[3] origin:064-gtp-channel-conf 31_273 -GTP_CHANNEL_1.GTPE2.TX_DEEMPH0[4] origin:064-gtp-channel-conf 30_274 -GTP_CHANNEL_1.GTPE2.TX_DEEMPH0[5] origin:064-gtp-channel-conf 31_274 -GTP_CHANNEL_1.GTPE2.TX_DEEMPH1[0] origin:064-gtp-channel-conf 30_276 -GTP_CHANNEL_1.GTPE2.TX_DEEMPH1[1] origin:064-gtp-channel-conf 31_276 -GTP_CHANNEL_1.GTPE2.TX_DEEMPH1[2] origin:064-gtp-channel-conf 30_277 -GTP_CHANNEL_1.GTPE2.TX_DEEMPH1[3] origin:064-gtp-channel-conf 31_277 -GTP_CHANNEL_1.GTPE2.TX_DEEMPH1[4] origin:064-gtp-channel-conf 30_278 -GTP_CHANNEL_1.GTPE2.TX_DEEMPH1[5] origin:064-gtp-channel-conf 31_278 -GTP_CHANNEL_1.GTPE2.TXBUF_EN origin:064-gtp-channel-conf 28_231 -GTP_CHANNEL_1.GTPE2.TXBUF_RESET_ON_RATE_CHANGE origin:064-gtp-channel-conf 29_231 -GTP_CHANNEL_1.GTPE2.TXDLY_CFG[0] origin:064-gtp-channel-conf 30_80 -GTP_CHANNEL_1.GTPE2.TXDLY_CFG[1] origin:064-gtp-channel-conf 31_80 -GTP_CHANNEL_1.GTPE2.TXDLY_CFG[2] origin:064-gtp-channel-conf 30_81 -GTP_CHANNEL_1.GTPE2.TXDLY_CFG[3] origin:064-gtp-channel-conf 31_81 -GTP_CHANNEL_1.GTPE2.TXDLY_CFG[4] origin:064-gtp-channel-conf 30_82 -GTP_CHANNEL_1.GTPE2.TXDLY_CFG[5] origin:064-gtp-channel-conf 31_82 -GTP_CHANNEL_1.GTPE2.TXDLY_CFG[6] origin:064-gtp-channel-conf 30_83 -GTP_CHANNEL_1.GTPE2.TXDLY_CFG[7] origin:064-gtp-channel-conf 31_83 -GTP_CHANNEL_1.GTPE2.TXDLY_CFG[8] origin:064-gtp-channel-conf 30_84 -GTP_CHANNEL_1.GTPE2.TXDLY_CFG[9] origin:064-gtp-channel-conf 31_84 -GTP_CHANNEL_1.GTPE2.TXDLY_CFG[10] origin:064-gtp-channel-conf 30_85 -GTP_CHANNEL_1.GTPE2.TXDLY_CFG[11] origin:064-gtp-channel-conf 31_85 -GTP_CHANNEL_1.GTPE2.TXDLY_CFG[12] origin:064-gtp-channel-conf 30_86 -GTP_CHANNEL_1.GTPE2.TXDLY_CFG[13] origin:064-gtp-channel-conf 31_86 -GTP_CHANNEL_1.GTPE2.TXDLY_CFG[14] origin:064-gtp-channel-conf 30_87 -GTP_CHANNEL_1.GTPE2.TXDLY_CFG[15] origin:064-gtp-channel-conf 31_87 -GTP_CHANNEL_1.GTPE2.TXDLY_LCFG[0] origin:064-gtp-channel-conf 30_568 -GTP_CHANNEL_1.GTPE2.TXDLY_LCFG[1] origin:064-gtp-channel-conf 31_568 -GTP_CHANNEL_1.GTPE2.TXDLY_LCFG[2] origin:064-gtp-channel-conf 30_569 -GTP_CHANNEL_1.GTPE2.TXDLY_LCFG[3] origin:064-gtp-channel-conf 31_569 -GTP_CHANNEL_1.GTPE2.TXDLY_LCFG[4] origin:064-gtp-channel-conf 30_570 -GTP_CHANNEL_1.GTPE2.TXDLY_LCFG[5] origin:064-gtp-channel-conf 31_570 -GTP_CHANNEL_1.GTPE2.TXDLY_LCFG[6] origin:064-gtp-channel-conf 30_571 -GTP_CHANNEL_1.GTPE2.TXDLY_LCFG[7] origin:064-gtp-channel-conf 31_571 -GTP_CHANNEL_1.GTPE2.TXDLY_LCFG[8] origin:064-gtp-channel-conf 30_572 -GTP_CHANNEL_1.GTPE2.TXDLY_TAP_CFG[0] origin:064-gtp-channel-conf 30_88 -GTP_CHANNEL_1.GTPE2.TXDLY_TAP_CFG[1] origin:064-gtp-channel-conf 31_88 -GTP_CHANNEL_1.GTPE2.TXDLY_TAP_CFG[2] origin:064-gtp-channel-conf 30_89 -GTP_CHANNEL_1.GTPE2.TXDLY_TAP_CFG[3] origin:064-gtp-channel-conf 31_89 -GTP_CHANNEL_1.GTPE2.TXDLY_TAP_CFG[4] origin:064-gtp-channel-conf 30_90 -GTP_CHANNEL_1.GTPE2.TXDLY_TAP_CFG[5] origin:064-gtp-channel-conf 31_90 -GTP_CHANNEL_1.GTPE2.TXDLY_TAP_CFG[6] origin:064-gtp-channel-conf 30_91 -GTP_CHANNEL_1.GTPE2.TXDLY_TAP_CFG[7] origin:064-gtp-channel-conf 31_91 -GTP_CHANNEL_1.GTPE2.TXDLY_TAP_CFG[8] origin:064-gtp-channel-conf 30_92 -GTP_CHANNEL_1.GTPE2.TXDLY_TAP_CFG[9] origin:064-gtp-channel-conf 31_92 -GTP_CHANNEL_1.GTPE2.TXDLY_TAP_CFG[10] origin:064-gtp-channel-conf 30_93 -GTP_CHANNEL_1.GTPE2.TXDLY_TAP_CFG[11] origin:064-gtp-channel-conf 31_93 -GTP_CHANNEL_1.GTPE2.TXDLY_TAP_CFG[12] origin:064-gtp-channel-conf 30_94 -GTP_CHANNEL_1.GTPE2.TXDLY_TAP_CFG[13] origin:064-gtp-channel-conf 31_94 -GTP_CHANNEL_1.GTPE2.TXDLY_TAP_CFG[14] origin:064-gtp-channel-conf 30_95 -GTP_CHANNEL_1.GTPE2.TXDLY_TAP_CFG[15] origin:064-gtp-channel-conf 31_95 -GTP_CHANNEL_1.GTPE2.TXGEARBOX_EN origin:064-gtp-channel-conf 29_226 -GTP_CHANNEL_1.GTPE2.TXOOB_CFG[0] origin:064-gtp-channel-conf 31_20 -GTP_CHANNEL_1.GTPE2.TXOUT_DIV[0] origin:064-gtp-channel-conf 30_386 -GTP_CHANNEL_1.GTPE2.TXOUT_DIV[1] origin:064-gtp-channel-conf 31_386 -GTP_CHANNEL_1.GTPE2.TXPCSRESET_TIME[0] origin:064-gtp-channel-conf 29_130 -GTP_CHANNEL_1.GTPE2.TXPCSRESET_TIME[1] origin:064-gtp-channel-conf 28_131 -GTP_CHANNEL_1.GTPE2.TXPCSRESET_TIME[2] origin:064-gtp-channel-conf 29_131 -GTP_CHANNEL_1.GTPE2.TXPCSRESET_TIME[3] origin:064-gtp-channel-conf 28_132 -GTP_CHANNEL_1.GTPE2.TXPCSRESET_TIME[4] origin:064-gtp-channel-conf 29_132 -GTP_CHANNEL_1.GTPE2.TXPH_CFG[0] origin:064-gtp-channel-conf 30_96 -GTP_CHANNEL_1.GTPE2.TXPH_CFG[1] origin:064-gtp-channel-conf 31_96 -GTP_CHANNEL_1.GTPE2.TXPH_CFG[2] origin:064-gtp-channel-conf 30_97 -GTP_CHANNEL_1.GTPE2.TXPH_CFG[3] origin:064-gtp-channel-conf 31_97 -GTP_CHANNEL_1.GTPE2.TXPH_CFG[4] origin:064-gtp-channel-conf 30_98 -GTP_CHANNEL_1.GTPE2.TXPH_CFG[5] origin:064-gtp-channel-conf 31_98 -GTP_CHANNEL_1.GTPE2.TXPH_CFG[6] origin:064-gtp-channel-conf 30_99 -GTP_CHANNEL_1.GTPE2.TXPH_CFG[7] origin:064-gtp-channel-conf 31_99 -GTP_CHANNEL_1.GTPE2.TXPH_CFG[8] origin:064-gtp-channel-conf 30_100 -GTP_CHANNEL_1.GTPE2.TXPH_CFG[9] origin:064-gtp-channel-conf 31_100 -GTP_CHANNEL_1.GTPE2.TXPH_CFG[10] origin:064-gtp-channel-conf 30_101 -GTP_CHANNEL_1.GTPE2.TXPH_CFG[11] origin:064-gtp-channel-conf 31_101 -GTP_CHANNEL_1.GTPE2.TXPH_CFG[12] origin:064-gtp-channel-conf 30_102 -GTP_CHANNEL_1.GTPE2.TXPH_CFG[13] origin:064-gtp-channel-conf 31_102 -GTP_CHANNEL_1.GTPE2.TXPH_CFG[14] origin:064-gtp-channel-conf 30_103 -GTP_CHANNEL_1.GTPE2.TXPH_CFG[15] origin:064-gtp-channel-conf 31_103 -GTP_CHANNEL_1.GTPE2.TXPH_MONITOR_SEL[0] origin:064-gtp-channel-conf 30_108 -GTP_CHANNEL_1.GTPE2.TXPH_MONITOR_SEL[1] origin:064-gtp-channel-conf 31_108 -GTP_CHANNEL_1.GTPE2.TXPH_MONITOR_SEL[2] origin:064-gtp-channel-conf 30_109 -GTP_CHANNEL_1.GTPE2.TXPH_MONITOR_SEL[3] origin:064-gtp-channel-conf 31_109 -GTP_CHANNEL_1.GTPE2.TXPH_MONITOR_SEL[4] origin:064-gtp-channel-conf 30_110 -GTP_CHANNEL_1.GTPE2.TXPHDLY_CFG[0] origin:064-gtp-channel-conf 30_64 -GTP_CHANNEL_1.GTPE2.TXPHDLY_CFG[1] origin:064-gtp-channel-conf 31_64 -GTP_CHANNEL_1.GTPE2.TXPHDLY_CFG[2] origin:064-gtp-channel-conf 30_65 -GTP_CHANNEL_1.GTPE2.TXPHDLY_CFG[3] origin:064-gtp-channel-conf 31_65 -GTP_CHANNEL_1.GTPE2.TXPHDLY_CFG[4] origin:064-gtp-channel-conf 30_66 -GTP_CHANNEL_1.GTPE2.TXPHDLY_CFG[5] origin:064-gtp-channel-conf 31_66 -GTP_CHANNEL_1.GTPE2.TXPHDLY_CFG[6] origin:064-gtp-channel-conf 30_67 -GTP_CHANNEL_1.GTPE2.TXPHDLY_CFG[7] origin:064-gtp-channel-conf 31_67 -GTP_CHANNEL_1.GTPE2.TXPHDLY_CFG[8] origin:064-gtp-channel-conf 30_68 -GTP_CHANNEL_1.GTPE2.TXPHDLY_CFG[9] origin:064-gtp-channel-conf 31_68 -GTP_CHANNEL_1.GTPE2.TXPHDLY_CFG[10] origin:064-gtp-channel-conf 30_69 -GTP_CHANNEL_1.GTPE2.TXPHDLY_CFG[11] origin:064-gtp-channel-conf 31_69 -GTP_CHANNEL_1.GTPE2.TXPHDLY_CFG[12] origin:064-gtp-channel-conf 30_70 -GTP_CHANNEL_1.GTPE2.TXPHDLY_CFG[13] origin:064-gtp-channel-conf 31_70 -GTP_CHANNEL_1.GTPE2.TXPHDLY_CFG[14] origin:064-gtp-channel-conf 30_71 -GTP_CHANNEL_1.GTPE2.TXPHDLY_CFG[15] origin:064-gtp-channel-conf 31_71 -GTP_CHANNEL_1.GTPE2.TXPHDLY_CFG[16] origin:064-gtp-channel-conf 30_72 -GTP_CHANNEL_1.GTPE2.TXPHDLY_CFG[17] origin:064-gtp-channel-conf 31_72 -GTP_CHANNEL_1.GTPE2.TXPHDLY_CFG[18] origin:064-gtp-channel-conf 30_73 -GTP_CHANNEL_1.GTPE2.TXPHDLY_CFG[19] origin:064-gtp-channel-conf 31_73 -GTP_CHANNEL_1.GTPE2.TXPHDLY_CFG[20] origin:064-gtp-channel-conf 30_74 -GTP_CHANNEL_1.GTPE2.TXPHDLY_CFG[21] origin:064-gtp-channel-conf 31_74 -GTP_CHANNEL_1.GTPE2.TXPHDLY_CFG[22] origin:064-gtp-channel-conf 30_75 -GTP_CHANNEL_1.GTPE2.TXPHDLY_CFG[23] origin:064-gtp-channel-conf 31_75 -GTP_CHANNEL_1.GTPE2.TXPI_GREY_SEL[0] origin:064-gtp-channel-conf 31_498 -GTP_CHANNEL_1.GTPE2.TXPI_INVSTROBE_SEL[0] origin:064-gtp-channel-conf 30_498 -GTP_CHANNEL_1.GTPE2.TXPI_PPM_CFG[0] origin:064-gtp-channel-conf 30_488 -GTP_CHANNEL_1.GTPE2.TXPI_PPM_CFG[1] origin:064-gtp-channel-conf 31_488 -GTP_CHANNEL_1.GTPE2.TXPI_PPM_CFG[2] origin:064-gtp-channel-conf 30_489 -GTP_CHANNEL_1.GTPE2.TXPI_PPM_CFG[3] origin:064-gtp-channel-conf 31_489 -GTP_CHANNEL_1.GTPE2.TXPI_PPM_CFG[4] origin:064-gtp-channel-conf 30_490 -GTP_CHANNEL_1.GTPE2.TXPI_PPM_CFG[5] origin:064-gtp-channel-conf 31_490 -GTP_CHANNEL_1.GTPE2.TXPI_PPM_CFG[6] origin:064-gtp-channel-conf 30_491 -GTP_CHANNEL_1.GTPE2.TXPI_PPM_CFG[7] origin:064-gtp-channel-conf 31_491 -GTP_CHANNEL_1.GTPE2.TXPI_PPMCLK_SEL.TXUSRCLK2 origin:064-gtp-channel-conf 31_497 -GTP_CHANNEL_1.GTPE2.TXPI_SYNFREQ_PPM[0] origin:064-gtp-channel-conf 30_496 -GTP_CHANNEL_1.GTPE2.TXPI_SYNFREQ_PPM[1] origin:064-gtp-channel-conf 31_496 -GTP_CHANNEL_1.GTPE2.TXPI_SYNFREQ_PPM[2] origin:064-gtp-channel-conf 30_497 -GTP_CHANNEL_1.GTPE2.TXPI_CFG0[0] origin:064-gtp-channel-conf 30_40 -GTP_CHANNEL_1.GTPE2.TXPI_CFG0[1] origin:064-gtp-channel-conf 31_40 -GTP_CHANNEL_1.GTPE2.TXPI_CFG1[0] origin:064-gtp-channel-conf 30_41 -GTP_CHANNEL_1.GTPE2.TXPI_CFG1[1] origin:064-gtp-channel-conf 31_41 -GTP_CHANNEL_1.GTPE2.TXPI_CFG2[0] origin:064-gtp-channel-conf 30_42 -GTP_CHANNEL_1.GTPE2.TXPI_CFG2[1] origin:064-gtp-channel-conf 31_42 -GTP_CHANNEL_1.GTPE2.TXPI_CFG3[0] origin:064-gtp-channel-conf 30_43 -GTP_CHANNEL_1.GTPE2.TXPI_CFG4[0] origin:064-gtp-channel-conf 31_43 -GTP_CHANNEL_1.GTPE2.TXPI_CFG5[0] origin:064-gtp-channel-conf 30_44 -GTP_CHANNEL_1.GTPE2.TXPI_CFG5[1] origin:064-gtp-channel-conf 31_44 -GTP_CHANNEL_1.GTPE2.TXPI_CFG5[2] origin:064-gtp-channel-conf 30_45 -GTP_CHANNEL_1.GTPE2.TXPMARESET_TIME[0] origin:064-gtp-channel-conf 28_128 -GTP_CHANNEL_1.GTPE2.TXPMARESET_TIME[1] origin:064-gtp-channel-conf 29_128 -GTP_CHANNEL_1.GTPE2.TXPMARESET_TIME[2] origin:064-gtp-channel-conf 28_129 -GTP_CHANNEL_1.GTPE2.TXPMARESET_TIME[3] origin:064-gtp-channel-conf 29_129 -GTP_CHANNEL_1.GTPE2.TXPMARESET_TIME[4] origin:064-gtp-channel-conf 28_130 -GTP_CHANNEL_1.GTPE2.TXSYNC_MULTILANE[0] origin:064-gtp-channel-conf 29_133 -GTP_CHANNEL_1.GTPE2.TXSYNC_OVRD[0] origin:064-gtp-channel-conf 28_135 -GTP_CHANNEL_1.GTPE2.TXSYNC_SKIP_DA[0] origin:064-gtp-channel-conf 28_134 -GTP_CHANNEL_1.GTPE2.UCODEER_CLR[0] origin:064-gtp-channel-conf 29_00 -GTP_CHANNEL_1.GTPE2.USE_PCS_CLK_PHASE_SEL[0] origin:064-gtp-channel-conf 30_463 -GTP_CHANNEL_1.GTPE2.ZINV_DMONITORCLK origin:064-gtp-channel-conf 30_13 -GTP_CHANNEL_1.GTPE2.ZINV_DRPCLK origin:064-gtp-channel-conf 30_00 -GTP_CHANNEL_1.GTPE2.ZINV_RXUSRCLK origin:064-gtp-channel-conf 31_01 -GTP_CHANNEL_1.GTPE2.ZINV_SIGVALIDCLK origin:064-gtp-channel-conf 31_13 -GTP_CHANNEL_1.GTPE2.ZINV_TXPHDLYTSTCLK origin:064-gtp-channel-conf 30_03 -GTP_CHANNEL_1.GTPE2.ZINV_TXUSRCLK origin:064-gtp-channel-conf 31_04 -GTP_CHANNEL_1.GTPE2.ZINV_CLKRSVD0 origin:064-gtp-channel-conf 30_23 -GTP_CHANNEL_1.GTPE2.ZINV_CLKRSVD1 origin:064-gtp-channel-conf 31_23 -GTP_CHANNEL_1.GTPE2.ZINV_RXUSRCLK2 origin:064-gtp-channel-conf 30_02 -GTP_CHANNEL_1.GTPE2.ZINV_TXUSRCLK2 origin:064-gtp-channel-conf 30_05 +GTP_CHANNEL_1.GTPE2_CHANNEL.ACJTAG_DEBUG_MODE[0] origin:064-gtp-channel-conf 28_07 +GTP_CHANNEL_1.GTPE2_CHANNEL.ACJTAG_MODE[0] origin:064-gtp-channel-conf 29_06 +GTP_CHANNEL_1.GTPE2_CHANNEL.ACJTAG_RESET[0] origin:064-gtp-channel-conf 29_07 +GTP_CHANNEL_1.GTPE2_CHANNEL.ADAPT_CFG0[0] origin:064-gtp-channel-conf 30_464 +GTP_CHANNEL_1.GTPE2_CHANNEL.ADAPT_CFG0[1] origin:064-gtp-channel-conf 31_464 +GTP_CHANNEL_1.GTPE2_CHANNEL.ADAPT_CFG0[2] origin:064-gtp-channel-conf 30_465 +GTP_CHANNEL_1.GTPE2_CHANNEL.ADAPT_CFG0[3] origin:064-gtp-channel-conf 31_465 +GTP_CHANNEL_1.GTPE2_CHANNEL.ADAPT_CFG0[4] origin:064-gtp-channel-conf 30_466 +GTP_CHANNEL_1.GTPE2_CHANNEL.ADAPT_CFG0[5] origin:064-gtp-channel-conf 31_466 +GTP_CHANNEL_1.GTPE2_CHANNEL.ADAPT_CFG0[6] origin:064-gtp-channel-conf 30_467 +GTP_CHANNEL_1.GTPE2_CHANNEL.ADAPT_CFG0[7] origin:064-gtp-channel-conf 31_467 +GTP_CHANNEL_1.GTPE2_CHANNEL.ADAPT_CFG0[8] origin:064-gtp-channel-conf 30_468 +GTP_CHANNEL_1.GTPE2_CHANNEL.ADAPT_CFG0[9] origin:064-gtp-channel-conf 31_468 +GTP_CHANNEL_1.GTPE2_CHANNEL.ADAPT_CFG0[10] origin:064-gtp-channel-conf 30_469 +GTP_CHANNEL_1.GTPE2_CHANNEL.ADAPT_CFG0[11] origin:064-gtp-channel-conf 31_469 +GTP_CHANNEL_1.GTPE2_CHANNEL.ADAPT_CFG0[12] origin:064-gtp-channel-conf 30_470 +GTP_CHANNEL_1.GTPE2_CHANNEL.ADAPT_CFG0[13] origin:064-gtp-channel-conf 31_470 +GTP_CHANNEL_1.GTPE2_CHANNEL.ADAPT_CFG0[14] origin:064-gtp-channel-conf 30_471 +GTP_CHANNEL_1.GTPE2_CHANNEL.ADAPT_CFG0[15] origin:064-gtp-channel-conf 31_471 +GTP_CHANNEL_1.GTPE2_CHANNEL.ADAPT_CFG0[16] origin:064-gtp-channel-conf 30_472 +GTP_CHANNEL_1.GTPE2_CHANNEL.ADAPT_CFG0[17] origin:064-gtp-channel-conf 31_472 +GTP_CHANNEL_1.GTPE2_CHANNEL.ADAPT_CFG0[18] origin:064-gtp-channel-conf 30_473 +GTP_CHANNEL_1.GTPE2_CHANNEL.ADAPT_CFG0[19] origin:064-gtp-channel-conf 31_473 +GTP_CHANNEL_1.GTPE2_CHANNEL.ALIGN_COMMA_DOUBLE origin:064-gtp-channel-conf 28_522 +GTP_CHANNEL_1.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[0] origin:064-gtp-channel-conf 28_496 +GTP_CHANNEL_1.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[1] origin:064-gtp-channel-conf 29_496 +GTP_CHANNEL_1.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[2] origin:064-gtp-channel-conf 28_497 +GTP_CHANNEL_1.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[3] origin:064-gtp-channel-conf 29_497 +GTP_CHANNEL_1.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[4] origin:064-gtp-channel-conf 28_498 +GTP_CHANNEL_1.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[5] origin:064-gtp-channel-conf 29_498 +GTP_CHANNEL_1.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[6] origin:064-gtp-channel-conf 28_499 +GTP_CHANNEL_1.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[7] origin:064-gtp-channel-conf 29_499 +GTP_CHANNEL_1.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[8] origin:064-gtp-channel-conf 28_500 +GTP_CHANNEL_1.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[9] origin:064-gtp-channel-conf 29_500 +GTP_CHANNEL_1.GTPE2_CHANNEL.ALIGN_COMMA_WORD[0] origin:064-gtp-channel-conf 29_526 +GTP_CHANNEL_1.GTPE2_CHANNEL.ALIGN_COMMA_WORD[1] origin:064-gtp-channel-conf 28_527 +GTP_CHANNEL_1.GTPE2_CHANNEL.ALIGN_MCOMMA_DET origin:064-gtp-channel-conf 28_523 +GTP_CHANNEL_1.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[0] origin:064-gtp-channel-conf 28_504 +GTP_CHANNEL_1.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[1] origin:064-gtp-channel-conf 29_504 +GTP_CHANNEL_1.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[2] origin:064-gtp-channel-conf 28_505 +GTP_CHANNEL_1.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[3] origin:064-gtp-channel-conf 29_505 +GTP_CHANNEL_1.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[4] origin:064-gtp-channel-conf 28_506 +GTP_CHANNEL_1.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[5] origin:064-gtp-channel-conf 29_506 +GTP_CHANNEL_1.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[6] origin:064-gtp-channel-conf 28_507 +GTP_CHANNEL_1.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[7] origin:064-gtp-channel-conf 29_507 +GTP_CHANNEL_1.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[8] origin:064-gtp-channel-conf 28_508 +GTP_CHANNEL_1.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[9] origin:064-gtp-channel-conf 29_508 +GTP_CHANNEL_1.GTPE2_CHANNEL.ALIGN_PCOMMA_DET origin:064-gtp-channel-conf 29_523 +GTP_CHANNEL_1.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[0] origin:064-gtp-channel-conf 28_512 +GTP_CHANNEL_1.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[1] origin:064-gtp-channel-conf 29_512 +GTP_CHANNEL_1.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[2] origin:064-gtp-channel-conf 28_513 +GTP_CHANNEL_1.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[3] origin:064-gtp-channel-conf 29_513 +GTP_CHANNEL_1.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[4] origin:064-gtp-channel-conf 28_514 +GTP_CHANNEL_1.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[5] origin:064-gtp-channel-conf 29_514 +GTP_CHANNEL_1.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[6] origin:064-gtp-channel-conf 28_515 +GTP_CHANNEL_1.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[7] origin:064-gtp-channel-conf 29_515 +GTP_CHANNEL_1.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[8] origin:064-gtp-channel-conf 28_516 +GTP_CHANNEL_1.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[9] origin:064-gtp-channel-conf 29_516 +GTP_CHANNEL_1.GTPE2_CHANNEL.CBCC_DATA_SOURCE_SEL.DECODED origin:064-gtp-channel-conf 29_661 +GTP_CHANNEL_1.GTPE2_CHANNEL.CFOK_CFG[0] origin:064-gtp-channel-conf 30_392 +GTP_CHANNEL_1.GTPE2_CHANNEL.CFOK_CFG[1] origin:064-gtp-channel-conf 31_392 +GTP_CHANNEL_1.GTPE2_CHANNEL.CFOK_CFG[2] origin:064-gtp-channel-conf 30_393 +GTP_CHANNEL_1.GTPE2_CHANNEL.CFOK_CFG[3] origin:064-gtp-channel-conf 31_393 +GTP_CHANNEL_1.GTPE2_CHANNEL.CFOK_CFG[4] origin:064-gtp-channel-conf 30_394 +GTP_CHANNEL_1.GTPE2_CHANNEL.CFOK_CFG[5] origin:064-gtp-channel-conf 31_394 +GTP_CHANNEL_1.GTPE2_CHANNEL.CFOK_CFG[6] origin:064-gtp-channel-conf 30_395 +GTP_CHANNEL_1.GTPE2_CHANNEL.CFOK_CFG[7] origin:064-gtp-channel-conf 31_395 +GTP_CHANNEL_1.GTPE2_CHANNEL.CFOK_CFG[8] origin:064-gtp-channel-conf 30_396 +GTP_CHANNEL_1.GTPE2_CHANNEL.CFOK_CFG[9] origin:064-gtp-channel-conf 31_396 +GTP_CHANNEL_1.GTPE2_CHANNEL.CFOK_CFG[10] origin:064-gtp-channel-conf 30_397 +GTP_CHANNEL_1.GTPE2_CHANNEL.CFOK_CFG[11] origin:064-gtp-channel-conf 31_397 +GTP_CHANNEL_1.GTPE2_CHANNEL.CFOK_CFG[12] origin:064-gtp-channel-conf 30_398 +GTP_CHANNEL_1.GTPE2_CHANNEL.CFOK_CFG[13] origin:064-gtp-channel-conf 31_398 +GTP_CHANNEL_1.GTPE2_CHANNEL.CFOK_CFG[14] origin:064-gtp-channel-conf 30_399 +GTP_CHANNEL_1.GTPE2_CHANNEL.CFOK_CFG[15] origin:064-gtp-channel-conf 31_399 +GTP_CHANNEL_1.GTPE2_CHANNEL.CFOK_CFG[16] origin:064-gtp-channel-conf 30_400 +GTP_CHANNEL_1.GTPE2_CHANNEL.CFOK_CFG[17] origin:064-gtp-channel-conf 31_400 +GTP_CHANNEL_1.GTPE2_CHANNEL.CFOK_CFG[18] origin:064-gtp-channel-conf 30_401 +GTP_CHANNEL_1.GTPE2_CHANNEL.CFOK_CFG[19] origin:064-gtp-channel-conf 31_401 +GTP_CHANNEL_1.GTPE2_CHANNEL.CFOK_CFG[20] origin:064-gtp-channel-conf 30_402 +GTP_CHANNEL_1.GTPE2_CHANNEL.CFOK_CFG[21] origin:064-gtp-channel-conf 31_402 +GTP_CHANNEL_1.GTPE2_CHANNEL.CFOK_CFG[22] origin:064-gtp-channel-conf 30_403 +GTP_CHANNEL_1.GTPE2_CHANNEL.CFOK_CFG[23] origin:064-gtp-channel-conf 31_403 +GTP_CHANNEL_1.GTPE2_CHANNEL.CFOK_CFG[24] origin:064-gtp-channel-conf 30_404 +GTP_CHANNEL_1.GTPE2_CHANNEL.CFOK_CFG[25] origin:064-gtp-channel-conf 31_404 +GTP_CHANNEL_1.GTPE2_CHANNEL.CFOK_CFG[26] origin:064-gtp-channel-conf 30_405 +GTP_CHANNEL_1.GTPE2_CHANNEL.CFOK_CFG[27] origin:064-gtp-channel-conf 31_405 +GTP_CHANNEL_1.GTPE2_CHANNEL.CFOK_CFG[28] origin:064-gtp-channel-conf 30_406 +GTP_CHANNEL_1.GTPE2_CHANNEL.CFOK_CFG[29] origin:064-gtp-channel-conf 31_406 +GTP_CHANNEL_1.GTPE2_CHANNEL.CFOK_CFG[30] origin:064-gtp-channel-conf 30_407 +GTP_CHANNEL_1.GTPE2_CHANNEL.CFOK_CFG[31] origin:064-gtp-channel-conf 31_407 +GTP_CHANNEL_1.GTPE2_CHANNEL.CFOK_CFG[32] origin:064-gtp-channel-conf 30_408 +GTP_CHANNEL_1.GTPE2_CHANNEL.CFOK_CFG[33] origin:064-gtp-channel-conf 31_408 +GTP_CHANNEL_1.GTPE2_CHANNEL.CFOK_CFG[34] origin:064-gtp-channel-conf 30_409 +GTP_CHANNEL_1.GTPE2_CHANNEL.CFOK_CFG[35] origin:064-gtp-channel-conf 31_409 +GTP_CHANNEL_1.GTPE2_CHANNEL.CFOK_CFG[36] origin:064-gtp-channel-conf 30_410 +GTP_CHANNEL_1.GTPE2_CHANNEL.CFOK_CFG[37] origin:064-gtp-channel-conf 31_410 +GTP_CHANNEL_1.GTPE2_CHANNEL.CFOK_CFG[38] origin:064-gtp-channel-conf 30_411 +GTP_CHANNEL_1.GTPE2_CHANNEL.CFOK_CFG[39] origin:064-gtp-channel-conf 31_411 +GTP_CHANNEL_1.GTPE2_CHANNEL.CFOK_CFG[40] origin:064-gtp-channel-conf 30_412 +GTP_CHANNEL_1.GTPE2_CHANNEL.CFOK_CFG[41] origin:064-gtp-channel-conf 31_412 +GTP_CHANNEL_1.GTPE2_CHANNEL.CFOK_CFG[42] origin:064-gtp-channel-conf 30_413 +GTP_CHANNEL_1.GTPE2_CHANNEL.CFOK_CFG2[0] origin:064-gtp-channel-conf 30_459 +GTP_CHANNEL_1.GTPE2_CHANNEL.CFOK_CFG2[1] origin:064-gtp-channel-conf 31_459 +GTP_CHANNEL_1.GTPE2_CHANNEL.CFOK_CFG2[2] origin:064-gtp-channel-conf 30_460 +GTP_CHANNEL_1.GTPE2_CHANNEL.CFOK_CFG2[3] origin:064-gtp-channel-conf 31_460 +GTP_CHANNEL_1.GTPE2_CHANNEL.CFOK_CFG2[4] origin:064-gtp-channel-conf 30_461 +GTP_CHANNEL_1.GTPE2_CHANNEL.CFOK_CFG2[5] origin:064-gtp-channel-conf 31_461 +GTP_CHANNEL_1.GTPE2_CHANNEL.CFOK_CFG2[6] origin:064-gtp-channel-conf 30_462 +GTP_CHANNEL_1.GTPE2_CHANNEL.CFOK_CFG3[0] origin:064-gtp-channel-conf 30_416 +GTP_CHANNEL_1.GTPE2_CHANNEL.CFOK_CFG3[1] origin:064-gtp-channel-conf 31_416 +GTP_CHANNEL_1.GTPE2_CHANNEL.CFOK_CFG3[2] origin:064-gtp-channel-conf 30_417 +GTP_CHANNEL_1.GTPE2_CHANNEL.CFOK_CFG3[3] origin:064-gtp-channel-conf 31_417 +GTP_CHANNEL_1.GTPE2_CHANNEL.CFOK_CFG3[4] origin:064-gtp-channel-conf 30_418 +GTP_CHANNEL_1.GTPE2_CHANNEL.CFOK_CFG3[5] origin:064-gtp-channel-conf 31_418 +GTP_CHANNEL_1.GTPE2_CHANNEL.CFOK_CFG3[6] origin:064-gtp-channel-conf 30_419 +GTP_CHANNEL_1.GTPE2_CHANNEL.CFOK_CFG4[0] origin:064-gtp-channel-conf 31_438 +GTP_CHANNEL_1.GTPE2_CHANNEL.CFOK_CFG5[0] origin:064-gtp-channel-conf 30_429 +GTP_CHANNEL_1.GTPE2_CHANNEL.CFOK_CFG5[1] origin:064-gtp-channel-conf 31_429 +GTP_CHANNEL_1.GTPE2_CHANNEL.CFOK_CFG6[0] origin:064-gtp-channel-conf 31_436 +GTP_CHANNEL_1.GTPE2_CHANNEL.CFOK_CFG6[1] origin:064-gtp-channel-conf 30_437 +GTP_CHANNEL_1.GTPE2_CHANNEL.CFOK_CFG6[2] origin:064-gtp-channel-conf 31_437 +GTP_CHANNEL_1.GTPE2_CHANNEL.CFOK_CFG6[3] origin:064-gtp-channel-conf 30_438 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_KEEP_ALIGN origin:064-gtp-channel-conf 29_631 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_MAX_SKEW[0] origin:064-gtp-channel-conf 28_670 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_MAX_SKEW[1] origin:064-gtp-channel-conf 29_670 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_MAX_SKEW[2] origin:064-gtp-channel-conf 28_671 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_MAX_SKEW[3] origin:064-gtp-channel-conf 29_671 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[0] origin:064-gtp-channel-conf 28_608 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[1] origin:064-gtp-channel-conf 29_608 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[2] origin:064-gtp-channel-conf 28_609 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[3] origin:064-gtp-channel-conf 29_609 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[4] origin:064-gtp-channel-conf 28_610 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[5] origin:064-gtp-channel-conf 29_610 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[6] origin:064-gtp-channel-conf 28_611 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[7] origin:064-gtp-channel-conf 29_611 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[8] origin:064-gtp-channel-conf 28_612 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[9] origin:064-gtp-channel-conf 29_612 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[0] origin:064-gtp-channel-conf 28_616 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[1] origin:064-gtp-channel-conf 29_616 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[2] origin:064-gtp-channel-conf 28_617 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[3] origin:064-gtp-channel-conf 29_617 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[4] origin:064-gtp-channel-conf 28_618 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[5] origin:064-gtp-channel-conf 29_618 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[6] origin:064-gtp-channel-conf 28_619 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[7] origin:064-gtp-channel-conf 29_619 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[8] origin:064-gtp-channel-conf 28_620 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[9] origin:064-gtp-channel-conf 29_620 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[0] origin:064-gtp-channel-conf 28_624 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[1] origin:064-gtp-channel-conf 29_624 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[2] origin:064-gtp-channel-conf 28_625 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[3] origin:064-gtp-channel-conf 29_625 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[4] origin:064-gtp-channel-conf 28_626 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[5] origin:064-gtp-channel-conf 29_626 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[6] origin:064-gtp-channel-conf 28_627 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[7] origin:064-gtp-channel-conf 29_627 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[8] origin:064-gtp-channel-conf 28_628 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[9] origin:064-gtp-channel-conf 29_628 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[0] origin:064-gtp-channel-conf 28_632 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[1] origin:064-gtp-channel-conf 29_632 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[2] origin:064-gtp-channel-conf 28_633 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[3] origin:064-gtp-channel-conf 29_633 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[4] origin:064-gtp-channel-conf 28_634 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[5] origin:064-gtp-channel-conf 29_634 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[6] origin:064-gtp-channel-conf 28_635 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[7] origin:064-gtp-channel-conf 29_635 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[8] origin:064-gtp-channel-conf 28_636 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[9] origin:064-gtp-channel-conf 29_636 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_ENABLE[0] origin:064-gtp-channel-conf 28_614 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_ENABLE[1] origin:064-gtp-channel-conf 29_614 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_ENABLE[2] origin:064-gtp-channel-conf 28_615 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_ENABLE[3] origin:064-gtp-channel-conf 29_615 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[0] origin:064-gtp-channel-conf 28_640 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[1] origin:064-gtp-channel-conf 29_640 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[2] origin:064-gtp-channel-conf 28_641 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[3] origin:064-gtp-channel-conf 29_641 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[4] origin:064-gtp-channel-conf 28_642 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[5] origin:064-gtp-channel-conf 29_642 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[6] origin:064-gtp-channel-conf 28_643 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[7] origin:064-gtp-channel-conf 29_643 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[8] origin:064-gtp-channel-conf 28_644 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[9] origin:064-gtp-channel-conf 29_644 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[0] origin:064-gtp-channel-conf 28_648 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[1] origin:064-gtp-channel-conf 29_648 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[2] origin:064-gtp-channel-conf 28_649 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[3] origin:064-gtp-channel-conf 29_649 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[4] origin:064-gtp-channel-conf 28_650 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[5] origin:064-gtp-channel-conf 29_650 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[6] origin:064-gtp-channel-conf 28_651 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[7] origin:064-gtp-channel-conf 29_651 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[8] origin:064-gtp-channel-conf 28_652 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[9] origin:064-gtp-channel-conf 29_652 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[0] origin:064-gtp-channel-conf 28_656 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[1] origin:064-gtp-channel-conf 29_656 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[2] origin:064-gtp-channel-conf 28_657 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[3] origin:064-gtp-channel-conf 29_657 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[4] origin:064-gtp-channel-conf 28_658 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[5] origin:064-gtp-channel-conf 29_658 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[6] origin:064-gtp-channel-conf 28_659 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[7] origin:064-gtp-channel-conf 29_659 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[8] origin:064-gtp-channel-conf 28_660 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[9] origin:064-gtp-channel-conf 29_660 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[0] origin:064-gtp-channel-conf 28_664 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[1] origin:064-gtp-channel-conf 29_664 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[2] origin:064-gtp-channel-conf 28_665 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[3] origin:064-gtp-channel-conf 29_665 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[4] origin:064-gtp-channel-conf 28_666 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[5] origin:064-gtp-channel-conf 29_666 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[6] origin:064-gtp-channel-conf 28_667 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[7] origin:064-gtp-channel-conf 29_667 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[8] origin:064-gtp-channel-conf 28_668 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[9] origin:064-gtp-channel-conf 29_668 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_ENABLE[0] origin:064-gtp-channel-conf 28_646 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_ENABLE[1] origin:064-gtp-channel-conf 29_646 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_ENABLE[2] origin:064-gtp-channel-conf 28_647 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_ENABLE[3] origin:064-gtp-channel-conf 29_647 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_USE origin:064-gtp-channel-conf 29_645 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_LEN[0] origin:064-gtp-channel-conf 28_623 +GTP_CHANNEL_1.GTPE2_CHANNEL.CHAN_BOND_SEQ_LEN[1] origin:064-gtp-channel-conf 29_623 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COMMON_SWING[0] origin:064-gtp-channel-conf 31_311 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_KEEP_IDLE origin:064-gtp-channel-conf 28_591 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_MAX_LAT[0] origin:064-gtp-channel-conf 28_557 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_MAX_LAT[1] origin:064-gtp-channel-conf 29_557 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_MAX_LAT[2] origin:064-gtp-channel-conf 28_558 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_MAX_LAT[3] origin:064-gtp-channel-conf 29_558 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_MAX_LAT[4] origin:064-gtp-channel-conf 28_559 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_MAX_LAT[5] origin:064-gtp-channel-conf 29_559 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_MIN_LAT[0] origin:064-gtp-channel-conf 28_565 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_MIN_LAT[1] origin:064-gtp-channel-conf 29_565 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_MIN_LAT[2] origin:064-gtp-channel-conf 28_566 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_MIN_LAT[3] origin:064-gtp-channel-conf 29_566 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_MIN_LAT[4] origin:064-gtp-channel-conf 28_567 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_MIN_LAT[5] origin:064-gtp-channel-conf 29_567 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_PRECEDENCE origin:064-gtp-channel-conf 28_590 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_REPEAT_WAIT[0] origin:064-gtp-channel-conf 28_573 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_REPEAT_WAIT[1] origin:064-gtp-channel-conf 29_573 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_REPEAT_WAIT[2] origin:064-gtp-channel-conf 28_574 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_REPEAT_WAIT[3] origin:064-gtp-channel-conf 29_574 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_REPEAT_WAIT[4] origin:064-gtp-channel-conf 28_575 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[0] origin:064-gtp-channel-conf 28_544 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[1] origin:064-gtp-channel-conf 29_544 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[2] origin:064-gtp-channel-conf 28_545 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[3] origin:064-gtp-channel-conf 29_545 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[4] origin:064-gtp-channel-conf 28_546 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[5] origin:064-gtp-channel-conf 29_546 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[6] origin:064-gtp-channel-conf 28_547 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[7] origin:064-gtp-channel-conf 29_547 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[8] origin:064-gtp-channel-conf 28_548 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[9] origin:064-gtp-channel-conf 29_548 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[0] origin:064-gtp-channel-conf 28_552 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[1] origin:064-gtp-channel-conf 29_552 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[2] origin:064-gtp-channel-conf 28_553 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[3] origin:064-gtp-channel-conf 29_553 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[4] origin:064-gtp-channel-conf 28_554 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[5] origin:064-gtp-channel-conf 29_554 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[6] origin:064-gtp-channel-conf 28_555 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[7] origin:064-gtp-channel-conf 29_555 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[8] origin:064-gtp-channel-conf 28_556 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[9] origin:064-gtp-channel-conf 29_556 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[0] origin:064-gtp-channel-conf 28_560 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[1] origin:064-gtp-channel-conf 29_560 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[2] origin:064-gtp-channel-conf 28_561 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[3] origin:064-gtp-channel-conf 29_561 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[4] origin:064-gtp-channel-conf 28_562 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[5] origin:064-gtp-channel-conf 29_562 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[6] origin:064-gtp-channel-conf 28_563 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[7] origin:064-gtp-channel-conf 29_563 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[8] origin:064-gtp-channel-conf 28_564 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[9] origin:064-gtp-channel-conf 29_564 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[0] origin:064-gtp-channel-conf 28_568 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[1] origin:064-gtp-channel-conf 29_568 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[2] origin:064-gtp-channel-conf 28_569 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[3] origin:064-gtp-channel-conf 29_569 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[4] origin:064-gtp-channel-conf 28_570 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[5] origin:064-gtp-channel-conf 29_570 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[6] origin:064-gtp-channel-conf 28_571 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[7] origin:064-gtp-channel-conf 29_571 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[8] origin:064-gtp-channel-conf 28_572 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[9] origin:064-gtp-channel-conf 29_572 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_1_ENABLE[0] origin:064-gtp-channel-conf 28_549 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_1_ENABLE[1] origin:064-gtp-channel-conf 29_549 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_1_ENABLE[2] origin:064-gtp-channel-conf 28_550 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_1_ENABLE[3] origin:064-gtp-channel-conf 29_550 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[0] origin:064-gtp-channel-conf 28_576 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[1] origin:064-gtp-channel-conf 29_576 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[2] origin:064-gtp-channel-conf 28_577 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[3] origin:064-gtp-channel-conf 29_577 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[4] origin:064-gtp-channel-conf 28_578 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[5] origin:064-gtp-channel-conf 29_578 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[6] origin:064-gtp-channel-conf 28_579 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[7] origin:064-gtp-channel-conf 29_579 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[8] origin:064-gtp-channel-conf 28_580 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[9] origin:064-gtp-channel-conf 29_580 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[0] origin:064-gtp-channel-conf 28_584 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[1] origin:064-gtp-channel-conf 29_584 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[2] origin:064-gtp-channel-conf 28_585 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[3] origin:064-gtp-channel-conf 29_585 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[4] origin:064-gtp-channel-conf 28_586 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[5] origin:064-gtp-channel-conf 29_586 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[6] origin:064-gtp-channel-conf 28_587 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[7] origin:064-gtp-channel-conf 29_587 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[8] origin:064-gtp-channel-conf 28_588 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[9] origin:064-gtp-channel-conf 29_588 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[0] origin:064-gtp-channel-conf 28_592 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[1] origin:064-gtp-channel-conf 29_592 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[2] origin:064-gtp-channel-conf 28_593 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[3] origin:064-gtp-channel-conf 29_593 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[4] origin:064-gtp-channel-conf 28_594 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[5] origin:064-gtp-channel-conf 29_594 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[6] origin:064-gtp-channel-conf 28_595 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[7] origin:064-gtp-channel-conf 29_595 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[8] origin:064-gtp-channel-conf 28_596 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[9] origin:064-gtp-channel-conf 29_596 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[0] origin:064-gtp-channel-conf 28_600 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[1] origin:064-gtp-channel-conf 29_600 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[2] origin:064-gtp-channel-conf 28_601 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[3] origin:064-gtp-channel-conf 29_601 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[4] origin:064-gtp-channel-conf 28_602 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[5] origin:064-gtp-channel-conf 29_602 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[6] origin:064-gtp-channel-conf 28_603 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[7] origin:064-gtp-channel-conf 29_603 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[8] origin:064-gtp-channel-conf 28_604 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[9] origin:064-gtp-channel-conf 29_604 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_2_ENABLE[0] origin:064-gtp-channel-conf 28_581 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_2_ENABLE[1] origin:064-gtp-channel-conf 29_581 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_2_ENABLE[2] origin:064-gtp-channel-conf 28_582 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_2_ENABLE[3] origin:064-gtp-channel-conf 29_582 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_2_USE origin:064-gtp-channel-conf 28_583 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_LEN[0] origin:064-gtp-channel-conf 28_589 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_COR_SEQ_LEN[1] origin:064-gtp-channel-conf 29_589 +GTP_CHANNEL_1.GTPE2_CHANNEL.CLK_CORRECT_USE origin:064-gtp-channel-conf 28_551 +GTP_CHANNEL_1.GTPE2_CHANNEL.DEC_MCOMMA_DETECT origin:064-gtp-channel-conf 29_494 +GTP_CHANNEL_1.GTPE2_CHANNEL.DEC_PCOMMA_DETECT origin:064-gtp-channel-conf 28_495 +GTP_CHANNEL_1.GTPE2_CHANNEL.DEC_VALID_COMMA_ONLY origin:064-gtp-channel-conf 28_494 +GTP_CHANNEL_1.GTPE2_CHANNEL.DMONITOR_CFG[0] origin:064-gtp-channel-conf 30_368 +GTP_CHANNEL_1.GTPE2_CHANNEL.DMONITOR_CFG[1] origin:064-gtp-channel-conf 31_368 +GTP_CHANNEL_1.GTPE2_CHANNEL.DMONITOR_CFG[2] origin:064-gtp-channel-conf 30_369 +GTP_CHANNEL_1.GTPE2_CHANNEL.DMONITOR_CFG[3] origin:064-gtp-channel-conf 31_369 +GTP_CHANNEL_1.GTPE2_CHANNEL.DMONITOR_CFG[4] origin:064-gtp-channel-conf 30_370 +GTP_CHANNEL_1.GTPE2_CHANNEL.DMONITOR_CFG[5] origin:064-gtp-channel-conf 31_370 +GTP_CHANNEL_1.GTPE2_CHANNEL.DMONITOR_CFG[6] origin:064-gtp-channel-conf 30_371 +GTP_CHANNEL_1.GTPE2_CHANNEL.DMONITOR_CFG[7] origin:064-gtp-channel-conf 31_371 +GTP_CHANNEL_1.GTPE2_CHANNEL.DMONITOR_CFG[8] origin:064-gtp-channel-conf 30_372 +GTP_CHANNEL_1.GTPE2_CHANNEL.DMONITOR_CFG[9] origin:064-gtp-channel-conf 31_372 +GTP_CHANNEL_1.GTPE2_CHANNEL.DMONITOR_CFG[10] origin:064-gtp-channel-conf 30_373 +GTP_CHANNEL_1.GTPE2_CHANNEL.DMONITOR_CFG[11] origin:064-gtp-channel-conf 31_373 +GTP_CHANNEL_1.GTPE2_CHANNEL.DMONITOR_CFG[12] origin:064-gtp-channel-conf 30_374 +GTP_CHANNEL_1.GTPE2_CHANNEL.DMONITOR_CFG[13] origin:064-gtp-channel-conf 31_374 +GTP_CHANNEL_1.GTPE2_CHANNEL.DMONITOR_CFG[14] origin:064-gtp-channel-conf 30_375 +GTP_CHANNEL_1.GTPE2_CHANNEL.DMONITOR_CFG[15] origin:064-gtp-channel-conf 31_375 +GTP_CHANNEL_1.GTPE2_CHANNEL.DMONITOR_CFG[16] origin:064-gtp-channel-conf 30_376 +GTP_CHANNEL_1.GTPE2_CHANNEL.DMONITOR_CFG[17] origin:064-gtp-channel-conf 31_376 +GTP_CHANNEL_1.GTPE2_CHANNEL.DMONITOR_CFG[18] origin:064-gtp-channel-conf 30_377 +GTP_CHANNEL_1.GTPE2_CHANNEL.DMONITOR_CFG[19] origin:064-gtp-channel-conf 31_377 +GTP_CHANNEL_1.GTPE2_CHANNEL.DMONITOR_CFG[20] origin:064-gtp-channel-conf 30_378 +GTP_CHANNEL_1.GTPE2_CHANNEL.DMONITOR_CFG[21] origin:064-gtp-channel-conf 31_378 +GTP_CHANNEL_1.GTPE2_CHANNEL.DMONITOR_CFG[22] origin:064-gtp-channel-conf 30_379 +GTP_CHANNEL_1.GTPE2_CHANNEL.DMONITOR_CFG[23] origin:064-gtp-channel-conf 31_379 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_CLK_PHASE_SEL[0] origin:064-gtp-channel-conf 31_463 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_CONTROL[0] origin:064-gtp-channel-conf 28_488 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_CONTROL[1] origin:064-gtp-channel-conf 29_488 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_CONTROL[2] origin:064-gtp-channel-conf 28_489 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_CONTROL[3] origin:064-gtp-channel-conf 29_489 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_CONTROL[4] origin:064-gtp-channel-conf 28_490 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_CONTROL[5] origin:064-gtp-channel-conf 29_490 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_ERRDET_EN origin:064-gtp-channel-conf 29_492 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_EYE_SCAN_EN origin:064-gtp-channel-conf 28_492 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_HORZ_OFFSET[0] origin:064-gtp-channel-conf 28_480 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_HORZ_OFFSET[1] origin:064-gtp-channel-conf 29_480 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_HORZ_OFFSET[2] origin:064-gtp-channel-conf 28_481 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_HORZ_OFFSET[3] origin:064-gtp-channel-conf 29_481 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_HORZ_OFFSET[4] origin:064-gtp-channel-conf 28_482 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_HORZ_OFFSET[5] origin:064-gtp-channel-conf 29_482 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_HORZ_OFFSET[6] origin:064-gtp-channel-conf 28_483 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_HORZ_OFFSET[7] origin:064-gtp-channel-conf 29_483 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_HORZ_OFFSET[8] origin:064-gtp-channel-conf 28_484 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_HORZ_OFFSET[9] origin:064-gtp-channel-conf 29_484 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_HORZ_OFFSET[10] origin:064-gtp-channel-conf 28_485 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_HORZ_OFFSET[11] origin:064-gtp-channel-conf 29_485 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_PMA_CFG[0] origin:064-gtp-channel-conf 30_624 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_PMA_CFG[1] origin:064-gtp-channel-conf 31_624 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_PMA_CFG[2] origin:064-gtp-channel-conf 30_625 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_PMA_CFG[3] origin:064-gtp-channel-conf 31_625 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_PMA_CFG[4] origin:064-gtp-channel-conf 30_626 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_PMA_CFG[5] origin:064-gtp-channel-conf 31_626 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_PMA_CFG[6] origin:064-gtp-channel-conf 30_627 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_PMA_CFG[7] origin:064-gtp-channel-conf 31_627 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_PMA_CFG[8] origin:064-gtp-channel-conf 30_628 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_PMA_CFG[9] origin:064-gtp-channel-conf 31_628 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_PRESCALE[0] origin:064-gtp-channel-conf 29_477 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_PRESCALE[1] origin:064-gtp-channel-conf 28_478 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_PRESCALE[2] origin:064-gtp-channel-conf 29_478 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_PRESCALE[3] origin:064-gtp-channel-conf 28_479 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_PRESCALE[4] origin:064-gtp-channel-conf 29_479 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[0] origin:064-gtp-channel-conf 28_392 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[1] origin:064-gtp-channel-conf 29_392 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[2] origin:064-gtp-channel-conf 28_393 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[3] origin:064-gtp-channel-conf 29_393 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[4] origin:064-gtp-channel-conf 28_394 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[5] origin:064-gtp-channel-conf 29_394 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[6] origin:064-gtp-channel-conf 28_395 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[7] origin:064-gtp-channel-conf 29_395 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[8] origin:064-gtp-channel-conf 28_396 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[9] origin:064-gtp-channel-conf 29_396 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[10] origin:064-gtp-channel-conf 28_397 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[11] origin:064-gtp-channel-conf 29_397 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[12] origin:064-gtp-channel-conf 28_398 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[13] origin:064-gtp-channel-conf 29_398 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[14] origin:064-gtp-channel-conf 28_399 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[15] origin:064-gtp-channel-conf 29_399 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[16] origin:064-gtp-channel-conf 28_400 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[17] origin:064-gtp-channel-conf 29_400 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[18] origin:064-gtp-channel-conf 28_401 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[19] origin:064-gtp-channel-conf 29_401 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[20] origin:064-gtp-channel-conf 28_402 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[21] origin:064-gtp-channel-conf 29_402 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[22] origin:064-gtp-channel-conf 28_403 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[23] origin:064-gtp-channel-conf 29_403 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[24] origin:064-gtp-channel-conf 28_404 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[25] origin:064-gtp-channel-conf 29_404 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[26] origin:064-gtp-channel-conf 28_405 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[27] origin:064-gtp-channel-conf 29_405 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[28] origin:064-gtp-channel-conf 28_406 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[29] origin:064-gtp-channel-conf 29_406 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[30] origin:064-gtp-channel-conf 28_407 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[31] origin:064-gtp-channel-conf 29_407 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[32] origin:064-gtp-channel-conf 28_408 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[33] origin:064-gtp-channel-conf 29_408 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[34] origin:064-gtp-channel-conf 28_409 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[35] origin:064-gtp-channel-conf 29_409 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[36] origin:064-gtp-channel-conf 28_410 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[37] origin:064-gtp-channel-conf 29_410 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[38] origin:064-gtp-channel-conf 28_411 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[39] origin:064-gtp-channel-conf 29_411 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[40] origin:064-gtp-channel-conf 28_412 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[41] origin:064-gtp-channel-conf 29_412 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[42] origin:064-gtp-channel-conf 28_413 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[43] origin:064-gtp-channel-conf 29_413 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[44] origin:064-gtp-channel-conf 28_414 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[45] origin:064-gtp-channel-conf 29_414 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[46] origin:064-gtp-channel-conf 28_415 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[47] origin:064-gtp-channel-conf 29_415 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[48] origin:064-gtp-channel-conf 28_416 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[49] origin:064-gtp-channel-conf 29_416 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[50] origin:064-gtp-channel-conf 28_417 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[51] origin:064-gtp-channel-conf 29_417 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[52] origin:064-gtp-channel-conf 28_418 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[53] origin:064-gtp-channel-conf 29_418 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[54] origin:064-gtp-channel-conf 28_419 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[55] origin:064-gtp-channel-conf 29_419 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[56] origin:064-gtp-channel-conf 28_420 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[57] origin:064-gtp-channel-conf 29_420 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[58] origin:064-gtp-channel-conf 28_421 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[59] origin:064-gtp-channel-conf 29_421 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[60] origin:064-gtp-channel-conf 28_422 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[61] origin:064-gtp-channel-conf 29_422 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[62] origin:064-gtp-channel-conf 28_423 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[63] origin:064-gtp-channel-conf 29_423 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[64] origin:064-gtp-channel-conf 28_424 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[65] origin:064-gtp-channel-conf 29_424 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[66] origin:064-gtp-channel-conf 28_425 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[67] origin:064-gtp-channel-conf 29_425 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[68] origin:064-gtp-channel-conf 28_426 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[69] origin:064-gtp-channel-conf 29_426 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[70] origin:064-gtp-channel-conf 28_427 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[71] origin:064-gtp-channel-conf 29_427 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[72] origin:064-gtp-channel-conf 28_428 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[73] origin:064-gtp-channel-conf 29_428 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[74] origin:064-gtp-channel-conf 28_429 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[75] origin:064-gtp-channel-conf 29_429 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[76] origin:064-gtp-channel-conf 28_430 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[77] origin:064-gtp-channel-conf 29_430 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[78] origin:064-gtp-channel-conf 28_431 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUAL_MASK[79] origin:064-gtp-channel-conf 29_431 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[0] origin:064-gtp-channel-conf 28_352 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[1] origin:064-gtp-channel-conf 29_352 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[2] origin:064-gtp-channel-conf 28_353 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[3] origin:064-gtp-channel-conf 29_353 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[4] origin:064-gtp-channel-conf 28_354 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[5] origin:064-gtp-channel-conf 29_354 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[6] origin:064-gtp-channel-conf 28_355 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[7] origin:064-gtp-channel-conf 29_355 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[8] origin:064-gtp-channel-conf 28_356 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[9] origin:064-gtp-channel-conf 29_356 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[10] origin:064-gtp-channel-conf 28_357 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[11] origin:064-gtp-channel-conf 29_357 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[12] origin:064-gtp-channel-conf 28_358 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[13] origin:064-gtp-channel-conf 29_358 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[14] origin:064-gtp-channel-conf 28_359 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[15] origin:064-gtp-channel-conf 29_359 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[16] origin:064-gtp-channel-conf 28_360 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[17] origin:064-gtp-channel-conf 29_360 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[18] origin:064-gtp-channel-conf 28_361 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[19] origin:064-gtp-channel-conf 29_361 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[20] origin:064-gtp-channel-conf 28_362 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[21] origin:064-gtp-channel-conf 29_362 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[22] origin:064-gtp-channel-conf 28_363 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[23] origin:064-gtp-channel-conf 29_363 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[24] origin:064-gtp-channel-conf 28_364 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[25] origin:064-gtp-channel-conf 29_364 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[26] origin:064-gtp-channel-conf 28_365 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[27] origin:064-gtp-channel-conf 29_365 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[28] origin:064-gtp-channel-conf 28_366 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[29] origin:064-gtp-channel-conf 29_366 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[30] origin:064-gtp-channel-conf 28_367 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[31] origin:064-gtp-channel-conf 29_367 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[32] origin:064-gtp-channel-conf 28_368 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[33] origin:064-gtp-channel-conf 29_368 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[34] origin:064-gtp-channel-conf 28_369 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[35] origin:064-gtp-channel-conf 29_369 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[36] origin:064-gtp-channel-conf 28_370 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[37] origin:064-gtp-channel-conf 29_370 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[38] origin:064-gtp-channel-conf 28_371 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[39] origin:064-gtp-channel-conf 29_371 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[40] origin:064-gtp-channel-conf 28_372 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[41] origin:064-gtp-channel-conf 29_372 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[42] origin:064-gtp-channel-conf 28_373 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[43] origin:064-gtp-channel-conf 29_373 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[44] origin:064-gtp-channel-conf 28_374 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[45] origin:064-gtp-channel-conf 29_374 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[46] origin:064-gtp-channel-conf 28_375 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[47] origin:064-gtp-channel-conf 29_375 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[48] origin:064-gtp-channel-conf 28_376 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[49] origin:064-gtp-channel-conf 29_376 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[50] origin:064-gtp-channel-conf 28_377 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[51] origin:064-gtp-channel-conf 29_377 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[52] origin:064-gtp-channel-conf 28_378 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[53] origin:064-gtp-channel-conf 29_378 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[54] origin:064-gtp-channel-conf 28_379 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[55] origin:064-gtp-channel-conf 29_379 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[56] origin:064-gtp-channel-conf 28_380 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[57] origin:064-gtp-channel-conf 29_380 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[58] origin:064-gtp-channel-conf 28_381 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[59] origin:064-gtp-channel-conf 29_381 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[60] origin:064-gtp-channel-conf 28_382 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[61] origin:064-gtp-channel-conf 29_382 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[62] origin:064-gtp-channel-conf 28_383 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[63] origin:064-gtp-channel-conf 29_383 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[64] origin:064-gtp-channel-conf 28_384 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[65] origin:064-gtp-channel-conf 29_384 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[66] origin:064-gtp-channel-conf 28_385 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[67] origin:064-gtp-channel-conf 29_385 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[68] origin:064-gtp-channel-conf 28_386 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[69] origin:064-gtp-channel-conf 29_386 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[70] origin:064-gtp-channel-conf 28_387 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[71] origin:064-gtp-channel-conf 29_387 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[72] origin:064-gtp-channel-conf 28_388 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[73] origin:064-gtp-channel-conf 29_388 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[74] origin:064-gtp-channel-conf 28_389 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[75] origin:064-gtp-channel-conf 29_389 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[76] origin:064-gtp-channel-conf 28_390 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[77] origin:064-gtp-channel-conf 29_390 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[78] origin:064-gtp-channel-conf 28_391 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_QUALIFIER[79] origin:064-gtp-channel-conf 29_391 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[0] origin:064-gtp-channel-conf 28_432 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[1] origin:064-gtp-channel-conf 29_432 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[2] origin:064-gtp-channel-conf 28_433 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[3] origin:064-gtp-channel-conf 29_433 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[4] origin:064-gtp-channel-conf 28_434 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[5] origin:064-gtp-channel-conf 29_434 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[6] origin:064-gtp-channel-conf 28_435 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[7] origin:064-gtp-channel-conf 29_435 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[8] origin:064-gtp-channel-conf 28_436 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[9] origin:064-gtp-channel-conf 29_436 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[10] origin:064-gtp-channel-conf 28_437 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[11] origin:064-gtp-channel-conf 29_437 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[12] origin:064-gtp-channel-conf 28_438 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[13] origin:064-gtp-channel-conf 29_438 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[14] origin:064-gtp-channel-conf 28_439 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[15] origin:064-gtp-channel-conf 29_439 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[16] origin:064-gtp-channel-conf 28_440 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[17] origin:064-gtp-channel-conf 29_440 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[18] origin:064-gtp-channel-conf 28_441 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[19] origin:064-gtp-channel-conf 29_441 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[20] origin:064-gtp-channel-conf 28_442 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[21] origin:064-gtp-channel-conf 29_442 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[22] origin:064-gtp-channel-conf 28_443 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[23] origin:064-gtp-channel-conf 29_443 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[24] origin:064-gtp-channel-conf 28_444 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[25] origin:064-gtp-channel-conf 29_444 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[26] origin:064-gtp-channel-conf 28_445 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[27] origin:064-gtp-channel-conf 29_445 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[28] origin:064-gtp-channel-conf 28_446 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[29] origin:064-gtp-channel-conf 29_446 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[30] origin:064-gtp-channel-conf 28_447 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[31] origin:064-gtp-channel-conf 29_447 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[32] origin:064-gtp-channel-conf 28_448 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[33] origin:064-gtp-channel-conf 29_448 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[34] origin:064-gtp-channel-conf 28_449 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[35] origin:064-gtp-channel-conf 29_449 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[36] origin:064-gtp-channel-conf 28_450 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[37] origin:064-gtp-channel-conf 29_450 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[38] origin:064-gtp-channel-conf 28_451 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[39] origin:064-gtp-channel-conf 29_451 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[40] origin:064-gtp-channel-conf 28_452 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[41] origin:064-gtp-channel-conf 29_452 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[42] origin:064-gtp-channel-conf 28_453 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[43] origin:064-gtp-channel-conf 29_453 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[44] origin:064-gtp-channel-conf 28_454 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[45] origin:064-gtp-channel-conf 29_454 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[46] origin:064-gtp-channel-conf 28_455 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[47] origin:064-gtp-channel-conf 29_455 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[48] origin:064-gtp-channel-conf 28_456 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[49] origin:064-gtp-channel-conf 29_456 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[50] origin:064-gtp-channel-conf 28_457 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[51] origin:064-gtp-channel-conf 29_457 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[52] origin:064-gtp-channel-conf 28_458 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[53] origin:064-gtp-channel-conf 29_458 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[54] origin:064-gtp-channel-conf 28_459 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[55] origin:064-gtp-channel-conf 29_459 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[56] origin:064-gtp-channel-conf 28_460 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[57] origin:064-gtp-channel-conf 29_460 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[58] origin:064-gtp-channel-conf 28_461 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[59] origin:064-gtp-channel-conf 29_461 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[60] origin:064-gtp-channel-conf 28_462 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[61] origin:064-gtp-channel-conf 29_462 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[62] origin:064-gtp-channel-conf 28_463 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[63] origin:064-gtp-channel-conf 29_463 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[64] origin:064-gtp-channel-conf 28_464 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[65] origin:064-gtp-channel-conf 29_464 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[66] origin:064-gtp-channel-conf 28_465 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[67] origin:064-gtp-channel-conf 29_465 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[68] origin:064-gtp-channel-conf 28_466 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[69] origin:064-gtp-channel-conf 29_466 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[70] origin:064-gtp-channel-conf 28_467 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[71] origin:064-gtp-channel-conf 29_467 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[72] origin:064-gtp-channel-conf 28_468 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[73] origin:064-gtp-channel-conf 29_468 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[74] origin:064-gtp-channel-conf 28_469 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[75] origin:064-gtp-channel-conf 29_469 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[76] origin:064-gtp-channel-conf 28_470 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[77] origin:064-gtp-channel-conf 29_470 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[78] origin:064-gtp-channel-conf 28_471 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_SDATA_MASK[79] origin:064-gtp-channel-conf 29_471 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_VERT_OFFSET[0] origin:064-gtp-channel-conf 28_472 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_VERT_OFFSET[1] origin:064-gtp-channel-conf 29_472 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_VERT_OFFSET[2] origin:064-gtp-channel-conf 28_473 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_VERT_OFFSET[3] origin:064-gtp-channel-conf 29_473 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_VERT_OFFSET[4] origin:064-gtp-channel-conf 28_474 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_VERT_OFFSET[5] origin:064-gtp-channel-conf 29_474 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_VERT_OFFSET[6] origin:064-gtp-channel-conf 28_475 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_VERT_OFFSET[7] origin:064-gtp-channel-conf 29_475 +GTP_CHANNEL_1.GTPE2_CHANNEL.ES_VERT_OFFSET[8] origin:064-gtp-channel-conf 28_476 +GTP_CHANNEL_1.GTPE2_CHANNEL.FTS_DESKEW_SEQ_ENABLE[0] origin:064-gtp-channel-conf 28_662 +GTP_CHANNEL_1.GTPE2_CHANNEL.FTS_DESKEW_SEQ_ENABLE[1] origin:064-gtp-channel-conf 29_662 +GTP_CHANNEL_1.GTPE2_CHANNEL.FTS_DESKEW_SEQ_ENABLE[2] origin:064-gtp-channel-conf 28_663 +GTP_CHANNEL_1.GTPE2_CHANNEL.FTS_DESKEW_SEQ_ENABLE[3] origin:064-gtp-channel-conf 29_663 +GTP_CHANNEL_1.GTPE2_CHANNEL.FTS_LANE_DESKEW_CFG[0] origin:064-gtp-channel-conf 28_654 +GTP_CHANNEL_1.GTPE2_CHANNEL.FTS_LANE_DESKEW_CFG[1] origin:064-gtp-channel-conf 29_654 +GTP_CHANNEL_1.GTPE2_CHANNEL.FTS_LANE_DESKEW_CFG[2] origin:064-gtp-channel-conf 28_655 +GTP_CHANNEL_1.GTPE2_CHANNEL.FTS_LANE_DESKEW_CFG[3] origin:064-gtp-channel-conf 29_655 +GTP_CHANNEL_1.GTPE2_CHANNEL.FTS_LANE_DESKEW_EN origin:064-gtp-channel-conf 29_653 +GTP_CHANNEL_1.GTPE2_CHANNEL.GEARBOX_MODE[0] origin:064-gtp-channel-conf 28_224 +GTP_CHANNEL_1.GTPE2_CHANNEL.GEARBOX_MODE[1] origin:064-gtp-channel-conf 29_224 +GTP_CHANNEL_1.GTPE2_CHANNEL.GEARBOX_MODE[2] origin:064-gtp-channel-conf 28_225 +GTP_CHANNEL_1.GTPE2_CHANNEL.IN_USE origin:064-gtp-channel-conf 28_00 28_01 28_47 28_52 28_53 28_65 29_01 29_47 30_129 +GTP_CHANNEL_1.GTPE2_CHANNEL.INV_DMONITORCLK origin:064-gtp-channel-conf 30_13 +GTP_CHANNEL_1.GTPE2_CHANNEL.INV_DRPCLK origin:064-gtp-channel-conf 30_00 +GTP_CHANNEL_1.GTPE2_CHANNEL.INV_RXUSRCLK origin:064-gtp-channel-conf 31_01 +GTP_CHANNEL_1.GTPE2_CHANNEL.INV_SIGVALIDCLK origin:064-gtp-channel-conf 31_13 +GTP_CHANNEL_1.GTPE2_CHANNEL.INV_TXPHDLYTSTCLK origin:064-gtp-channel-conf 30_03 +GTP_CHANNEL_1.GTPE2_CHANNEL.INV_TXUSRCLK origin:064-gtp-channel-conf 31_04 +GTP_CHANNEL_1.GTPE2_CHANNEL.INV_CLKRSVD0 origin:064-gtp-channel-conf 30_23 +GTP_CHANNEL_1.GTPE2_CHANNEL.INV_CLKRSVD1 origin:064-gtp-channel-conf 31_23 +GTP_CHANNEL_1.GTPE2_CHANNEL.INV_RXUSRCLK2 origin:064-gtp-channel-conf 30_02 +GTP_CHANNEL_1.GTPE2_CHANNEL.INV_TXUSRCLK2 origin:064-gtp-channel-conf 30_05 +GTP_CHANNEL_1.GTPE2_CHANNEL.LOOPBACK_CFG[0] origin:064-gtp-channel-conf 30_20 +GTP_CHANNEL_1.GTPE2_CHANNEL.OUTREFCLK_SEL_INV[0] origin:064-gtp-channel-conf 28_149 +GTP_CHANNEL_1.GTPE2_CHANNEL.OUTREFCLK_SEL_INV[1] origin:064-gtp-channel-conf 29_149 +GTP_CHANNEL_1.GTPE2_CHANNEL.PCS_PCIE_EN origin:064-gtp-channel-conf 28_216 +GTP_CHANNEL_1.GTPE2_CHANNEL.PCS_RSVD_ATTR[0] origin:064-gtp-channel-conf 30_184 +GTP_CHANNEL_1.GTPE2_CHANNEL.PCS_RSVD_ATTR[1] origin:064-gtp-channel-conf 31_184 +GTP_CHANNEL_1.GTPE2_CHANNEL.PCS_RSVD_ATTR[2] origin:064-gtp-channel-conf 30_185 +GTP_CHANNEL_1.GTPE2_CHANNEL.PCS_RSVD_ATTR[3] origin:064-gtp-channel-conf 31_185 +GTP_CHANNEL_1.GTPE2_CHANNEL.PCS_RSVD_ATTR[4] origin:064-gtp-channel-conf 30_186 +GTP_CHANNEL_1.GTPE2_CHANNEL.PCS_RSVD_ATTR[5] origin:064-gtp-channel-conf 31_186 +GTP_CHANNEL_1.GTPE2_CHANNEL.PCS_RSVD_ATTR[6] origin:064-gtp-channel-conf 30_187 +GTP_CHANNEL_1.GTPE2_CHANNEL.PCS_RSVD_ATTR[7] origin:064-gtp-channel-conf 31_187 +GTP_CHANNEL_1.GTPE2_CHANNEL.PCS_RSVD_ATTR[8] origin:064-gtp-channel-conf 30_188 +GTP_CHANNEL_1.GTPE2_CHANNEL.PCS_RSVD_ATTR[9] origin:064-gtp-channel-conf 31_188 +GTP_CHANNEL_1.GTPE2_CHANNEL.PCS_RSVD_ATTR[10] origin:064-gtp-channel-conf 30_189 +GTP_CHANNEL_1.GTPE2_CHANNEL.PCS_RSVD_ATTR[11] origin:064-gtp-channel-conf 31_189 +GTP_CHANNEL_1.GTPE2_CHANNEL.PCS_RSVD_ATTR[12] origin:064-gtp-channel-conf 30_190 +GTP_CHANNEL_1.GTPE2_CHANNEL.PCS_RSVD_ATTR[13] origin:064-gtp-channel-conf 31_190 +GTP_CHANNEL_1.GTPE2_CHANNEL.PCS_RSVD_ATTR[14] origin:064-gtp-channel-conf 30_191 +GTP_CHANNEL_1.GTPE2_CHANNEL.PCS_RSVD_ATTR[15] origin:064-gtp-channel-conf 31_191 +GTP_CHANNEL_1.GTPE2_CHANNEL.PCS_RSVD_ATTR[16] origin:064-gtp-channel-conf 30_192 +GTP_CHANNEL_1.GTPE2_CHANNEL.PCS_RSVD_ATTR[17] origin:064-gtp-channel-conf 31_192 +GTP_CHANNEL_1.GTPE2_CHANNEL.PCS_RSVD_ATTR[18] origin:064-gtp-channel-conf 30_193 +GTP_CHANNEL_1.GTPE2_CHANNEL.PCS_RSVD_ATTR[19] origin:064-gtp-channel-conf 31_193 +GTP_CHANNEL_1.GTPE2_CHANNEL.PCS_RSVD_ATTR[20] origin:064-gtp-channel-conf 30_194 +GTP_CHANNEL_1.GTPE2_CHANNEL.PCS_RSVD_ATTR[21] origin:064-gtp-channel-conf 31_194 +GTP_CHANNEL_1.GTPE2_CHANNEL.PCS_RSVD_ATTR[22] origin:064-gtp-channel-conf 30_195 +GTP_CHANNEL_1.GTPE2_CHANNEL.PCS_RSVD_ATTR[23] origin:064-gtp-channel-conf 31_195 +GTP_CHANNEL_1.GTPE2_CHANNEL.PCS_RSVD_ATTR[24] origin:064-gtp-channel-conf 30_196 +GTP_CHANNEL_1.GTPE2_CHANNEL.PCS_RSVD_ATTR[25] origin:064-gtp-channel-conf 31_196 +GTP_CHANNEL_1.GTPE2_CHANNEL.PCS_RSVD_ATTR[26] origin:064-gtp-channel-conf 30_197 +GTP_CHANNEL_1.GTPE2_CHANNEL.PCS_RSVD_ATTR[27] origin:064-gtp-channel-conf 31_197 +GTP_CHANNEL_1.GTPE2_CHANNEL.PCS_RSVD_ATTR[28] origin:064-gtp-channel-conf 30_198 +GTP_CHANNEL_1.GTPE2_CHANNEL.PCS_RSVD_ATTR[29] origin:064-gtp-channel-conf 31_198 +GTP_CHANNEL_1.GTPE2_CHANNEL.PCS_RSVD_ATTR[30] origin:064-gtp-channel-conf 30_199 +GTP_CHANNEL_1.GTPE2_CHANNEL.PCS_RSVD_ATTR[31] origin:064-gtp-channel-conf 31_199 +GTP_CHANNEL_1.GTPE2_CHANNEL.PCS_RSVD_ATTR[32] origin:064-gtp-channel-conf 30_200 +GTP_CHANNEL_1.GTPE2_CHANNEL.PCS_RSVD_ATTR[33] origin:064-gtp-channel-conf 31_200 +GTP_CHANNEL_1.GTPE2_CHANNEL.PCS_RSVD_ATTR[34] origin:064-gtp-channel-conf 30_201 +GTP_CHANNEL_1.GTPE2_CHANNEL.PCS_RSVD_ATTR[35] origin:064-gtp-channel-conf 31_201 +GTP_CHANNEL_1.GTPE2_CHANNEL.PCS_RSVD_ATTR[36] origin:064-gtp-channel-conf 30_202 +GTP_CHANNEL_1.GTPE2_CHANNEL.PCS_RSVD_ATTR[37] origin:064-gtp-channel-conf 31_202 +GTP_CHANNEL_1.GTPE2_CHANNEL.PCS_RSVD_ATTR[38] origin:064-gtp-channel-conf 30_203 +GTP_CHANNEL_1.GTPE2_CHANNEL.PCS_RSVD_ATTR[39] origin:064-gtp-channel-conf 31_203 +GTP_CHANNEL_1.GTPE2_CHANNEL.PCS_RSVD_ATTR[40] origin:064-gtp-channel-conf 30_204 +GTP_CHANNEL_1.GTPE2_CHANNEL.PCS_RSVD_ATTR[41] origin:064-gtp-channel-conf 31_204 +GTP_CHANNEL_1.GTPE2_CHANNEL.PCS_RSVD_ATTR[42] origin:064-gtp-channel-conf 30_205 +GTP_CHANNEL_1.GTPE2_CHANNEL.PCS_RSVD_ATTR[43] origin:064-gtp-channel-conf 31_205 +GTP_CHANNEL_1.GTPE2_CHANNEL.PCS_RSVD_ATTR[44] origin:064-gtp-channel-conf 30_206 +GTP_CHANNEL_1.GTPE2_CHANNEL.PCS_RSVD_ATTR[45] origin:064-gtp-channel-conf 31_206 +GTP_CHANNEL_1.GTPE2_CHANNEL.PCS_RSVD_ATTR[46] origin:064-gtp-channel-conf 30_207 +GTP_CHANNEL_1.GTPE2_CHANNEL.PCS_RSVD_ATTR[47] origin:064-gtp-channel-conf 31_207 +GTP_CHANNEL_1.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[0] origin:064-gtp-channel-conf 29_216 +GTP_CHANNEL_1.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[1] origin:064-gtp-channel-conf 28_217 +GTP_CHANNEL_1.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[2] origin:064-gtp-channel-conf 29_217 +GTP_CHANNEL_1.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[3] origin:064-gtp-channel-conf 28_218 +GTP_CHANNEL_1.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[4] origin:064-gtp-channel-conf 29_218 +GTP_CHANNEL_1.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[5] origin:064-gtp-channel-conf 28_219 +GTP_CHANNEL_1.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[6] origin:064-gtp-channel-conf 29_219 +GTP_CHANNEL_1.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[7] origin:064-gtp-channel-conf 28_220 +GTP_CHANNEL_1.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[8] origin:064-gtp-channel-conf 29_220 +GTP_CHANNEL_1.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[9] origin:064-gtp-channel-conf 28_221 +GTP_CHANNEL_1.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[10] origin:064-gtp-channel-conf 29_221 +GTP_CHANNEL_1.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[11] origin:064-gtp-channel-conf 28_222 +GTP_CHANNEL_1.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[0] origin:064-gtp-channel-conf 28_208 +GTP_CHANNEL_1.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[1] origin:064-gtp-channel-conf 29_208 +GTP_CHANNEL_1.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[2] origin:064-gtp-channel-conf 28_209 +GTP_CHANNEL_1.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[3] origin:064-gtp-channel-conf 29_209 +GTP_CHANNEL_1.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[4] origin:064-gtp-channel-conf 28_210 +GTP_CHANNEL_1.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[5] origin:064-gtp-channel-conf 29_210 +GTP_CHANNEL_1.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[6] origin:064-gtp-channel-conf 28_211 +GTP_CHANNEL_1.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[7] origin:064-gtp-channel-conf 29_211 +GTP_CHANNEL_1.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[0] origin:064-gtp-channel-conf 28_212 +GTP_CHANNEL_1.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[1] origin:064-gtp-channel-conf 29_212 +GTP_CHANNEL_1.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[2] origin:064-gtp-channel-conf 28_213 +GTP_CHANNEL_1.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[3] origin:064-gtp-channel-conf 29_213 +GTP_CHANNEL_1.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[4] origin:064-gtp-channel-conf 28_214 +GTP_CHANNEL_1.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[5] origin:064-gtp-channel-conf 29_214 +GTP_CHANNEL_1.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[6] origin:064-gtp-channel-conf 28_215 +GTP_CHANNEL_1.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[7] origin:064-gtp-channel-conf 29_215 +GTP_CHANNEL_1.GTPE2_CHANNEL.PMA_LOOPBACK_CFG[0] origin:064-gtp-channel-conf 29_207 +GTP_CHANNEL_1.GTPE2_CHANNEL.PMA_RSV[0] origin:064-gtp-channel-conf 30_520 +GTP_CHANNEL_1.GTPE2_CHANNEL.PMA_RSV[1] origin:064-gtp-channel-conf 31_520 +GTP_CHANNEL_1.GTPE2_CHANNEL.PMA_RSV[2] origin:064-gtp-channel-conf 30_521 +GTP_CHANNEL_1.GTPE2_CHANNEL.PMA_RSV[3] origin:064-gtp-channel-conf 31_521 +GTP_CHANNEL_1.GTPE2_CHANNEL.PMA_RSV[4] origin:064-gtp-channel-conf 30_522 +GTP_CHANNEL_1.GTPE2_CHANNEL.PMA_RSV[5] origin:064-gtp-channel-conf 31_522 +GTP_CHANNEL_1.GTPE2_CHANNEL.PMA_RSV[6] origin:064-gtp-channel-conf 30_523 +GTP_CHANNEL_1.GTPE2_CHANNEL.PMA_RSV[7] origin:064-gtp-channel-conf 31_523 +GTP_CHANNEL_1.GTPE2_CHANNEL.PMA_RSV[8] origin:064-gtp-channel-conf 30_524 +GTP_CHANNEL_1.GTPE2_CHANNEL.PMA_RSV[9] origin:064-gtp-channel-conf 31_524 +GTP_CHANNEL_1.GTPE2_CHANNEL.PMA_RSV[10] origin:064-gtp-channel-conf 30_525 +GTP_CHANNEL_1.GTPE2_CHANNEL.PMA_RSV[11] origin:064-gtp-channel-conf 31_525 +GTP_CHANNEL_1.GTPE2_CHANNEL.PMA_RSV[12] origin:064-gtp-channel-conf 30_526 +GTP_CHANNEL_1.GTPE2_CHANNEL.PMA_RSV[13] origin:064-gtp-channel-conf 31_526 +GTP_CHANNEL_1.GTPE2_CHANNEL.PMA_RSV[14] origin:064-gtp-channel-conf 30_527 +GTP_CHANNEL_1.GTPE2_CHANNEL.PMA_RSV[15] origin:064-gtp-channel-conf 31_527 +GTP_CHANNEL_1.GTPE2_CHANNEL.PMA_RSV[16] origin:064-gtp-channel-conf 30_528 +GTP_CHANNEL_1.GTPE2_CHANNEL.PMA_RSV[17] origin:064-gtp-channel-conf 31_528 +GTP_CHANNEL_1.GTPE2_CHANNEL.PMA_RSV[18] origin:064-gtp-channel-conf 30_529 +GTP_CHANNEL_1.GTPE2_CHANNEL.PMA_RSV[19] origin:064-gtp-channel-conf 31_529 +GTP_CHANNEL_1.GTPE2_CHANNEL.PMA_RSV[20] origin:064-gtp-channel-conf 30_530 +GTP_CHANNEL_1.GTPE2_CHANNEL.PMA_RSV[21] origin:064-gtp-channel-conf 31_530 +GTP_CHANNEL_1.GTPE2_CHANNEL.PMA_RSV[22] origin:064-gtp-channel-conf 30_531 +GTP_CHANNEL_1.GTPE2_CHANNEL.PMA_RSV[23] origin:064-gtp-channel-conf 31_531 +GTP_CHANNEL_1.GTPE2_CHANNEL.PMA_RSV[24] origin:064-gtp-channel-conf 30_532 +GTP_CHANNEL_1.GTPE2_CHANNEL.PMA_RSV[25] origin:064-gtp-channel-conf 31_532 +GTP_CHANNEL_1.GTPE2_CHANNEL.PMA_RSV[26] origin:064-gtp-channel-conf 30_533 +GTP_CHANNEL_1.GTPE2_CHANNEL.PMA_RSV[27] origin:064-gtp-channel-conf 31_533 +GTP_CHANNEL_1.GTPE2_CHANNEL.PMA_RSV[28] origin:064-gtp-channel-conf 30_534 +GTP_CHANNEL_1.GTPE2_CHANNEL.PMA_RSV[29] origin:064-gtp-channel-conf 31_534 +GTP_CHANNEL_1.GTPE2_CHANNEL.PMA_RSV[30] origin:064-gtp-channel-conf 30_535 +GTP_CHANNEL_1.GTPE2_CHANNEL.PMA_RSV[31] origin:064-gtp-channel-conf 31_535 +GTP_CHANNEL_1.GTPE2_CHANNEL.PMA_RSV2[0] origin:064-gtp-channel-conf 30_336 +GTP_CHANNEL_1.GTPE2_CHANNEL.PMA_RSV2[1] origin:064-gtp-channel-conf 31_336 +GTP_CHANNEL_1.GTPE2_CHANNEL.PMA_RSV2[2] origin:064-gtp-channel-conf 30_337 +GTP_CHANNEL_1.GTPE2_CHANNEL.PMA_RSV2[3] origin:064-gtp-channel-conf 31_337 +GTP_CHANNEL_1.GTPE2_CHANNEL.PMA_RSV2[4] origin:064-gtp-channel-conf 30_338 +GTP_CHANNEL_1.GTPE2_CHANNEL.PMA_RSV2[5] origin:064-gtp-channel-conf 31_338 +GTP_CHANNEL_1.GTPE2_CHANNEL.PMA_RSV2[6] origin:064-gtp-channel-conf 30_339 +GTP_CHANNEL_1.GTPE2_CHANNEL.PMA_RSV2[7] origin:064-gtp-channel-conf 31_339 +GTP_CHANNEL_1.GTPE2_CHANNEL.PMA_RSV2[8] origin:064-gtp-channel-conf 30_340 +GTP_CHANNEL_1.GTPE2_CHANNEL.PMA_RSV2[9] origin:064-gtp-channel-conf 31_340 +GTP_CHANNEL_1.GTPE2_CHANNEL.PMA_RSV2[10] origin:064-gtp-channel-conf 30_341 +GTP_CHANNEL_1.GTPE2_CHANNEL.PMA_RSV2[11] origin:064-gtp-channel-conf 31_341 +GTP_CHANNEL_1.GTPE2_CHANNEL.PMA_RSV2[12] origin:064-gtp-channel-conf 30_342 +GTP_CHANNEL_1.GTPE2_CHANNEL.PMA_RSV2[13] origin:064-gtp-channel-conf 31_342 +GTP_CHANNEL_1.GTPE2_CHANNEL.PMA_RSV2[14] origin:064-gtp-channel-conf 30_343 +GTP_CHANNEL_1.GTPE2_CHANNEL.PMA_RSV2[15] origin:064-gtp-channel-conf 31_343 +GTP_CHANNEL_1.GTPE2_CHANNEL.PMA_RSV2[16] origin:064-gtp-channel-conf 30_344 +GTP_CHANNEL_1.GTPE2_CHANNEL.PMA_RSV2[17] origin:064-gtp-channel-conf 31_344 +GTP_CHANNEL_1.GTPE2_CHANNEL.PMA_RSV2[18] origin:064-gtp-channel-conf 30_345 +GTP_CHANNEL_1.GTPE2_CHANNEL.PMA_RSV2[19] origin:064-gtp-channel-conf 31_345 +GTP_CHANNEL_1.GTPE2_CHANNEL.PMA_RSV2[20] origin:064-gtp-channel-conf 30_346 +GTP_CHANNEL_1.GTPE2_CHANNEL.PMA_RSV2[21] origin:064-gtp-channel-conf 31_346 +GTP_CHANNEL_1.GTPE2_CHANNEL.PMA_RSV2[22] origin:064-gtp-channel-conf 30_347 +GTP_CHANNEL_1.GTPE2_CHANNEL.PMA_RSV2[23] origin:064-gtp-channel-conf 31_347 +GTP_CHANNEL_1.GTPE2_CHANNEL.PMA_RSV2[24] origin:064-gtp-channel-conf 30_348 +GTP_CHANNEL_1.GTPE2_CHANNEL.PMA_RSV2[25] origin:064-gtp-channel-conf 31_348 +GTP_CHANNEL_1.GTPE2_CHANNEL.PMA_RSV2[26] origin:064-gtp-channel-conf 30_349 +GTP_CHANNEL_1.GTPE2_CHANNEL.PMA_RSV2[27] origin:064-gtp-channel-conf 31_349 +GTP_CHANNEL_1.GTPE2_CHANNEL.PMA_RSV2[28] origin:064-gtp-channel-conf 30_350 +GTP_CHANNEL_1.GTPE2_CHANNEL.PMA_RSV2[29] origin:064-gtp-channel-conf 31_350 +GTP_CHANNEL_1.GTPE2_CHANNEL.PMA_RSV2[30] origin:064-gtp-channel-conf 30_351 +GTP_CHANNEL_1.GTPE2_CHANNEL.PMA_RSV2[31] origin:064-gtp-channel-conf 31_351 +GTP_CHANNEL_1.GTPE2_CHANNEL.PMA_RSV3[0] origin:064-gtp-channel-conf 30_288 +GTP_CHANNEL_1.GTPE2_CHANNEL.PMA_RSV3[1] origin:064-gtp-channel-conf 31_288 +GTP_CHANNEL_1.GTPE2_CHANNEL.PMA_RSV4[0] origin:064-gtp-channel-conf 30_156 +GTP_CHANNEL_1.GTPE2_CHANNEL.PMA_RSV4[1] origin:064-gtp-channel-conf 31_156 +GTP_CHANNEL_1.GTPE2_CHANNEL.PMA_RSV4[2] origin:064-gtp-channel-conf 30_157 +GTP_CHANNEL_1.GTPE2_CHANNEL.PMA_RSV4[3] origin:064-gtp-channel-conf 31_157 +GTP_CHANNEL_1.GTPE2_CHANNEL.PMA_RSV5[0] origin:064-gtp-channel-conf 31_159 +GTP_CHANNEL_1.GTPE2_CHANNEL.PMA_RSV6[0] origin:064-gtp-channel-conf 30_303 +GTP_CHANNEL_1.GTPE2_CHANNEL.PMA_RSV7[0] origin:064-gtp-channel-conf 31_303 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_BIAS_CFG[0] origin:064-gtp-channel-conf 30_112 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_BIAS_CFG[1] origin:064-gtp-channel-conf 31_112 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_BIAS_CFG[2] origin:064-gtp-channel-conf 30_113 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_BIAS_CFG[3] origin:064-gtp-channel-conf 31_113 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_BIAS_CFG[4] origin:064-gtp-channel-conf 30_114 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_BIAS_CFG[5] origin:064-gtp-channel-conf 31_114 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_BIAS_CFG[6] origin:064-gtp-channel-conf 30_115 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_BIAS_CFG[7] origin:064-gtp-channel-conf 31_115 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_BIAS_CFG[8] origin:064-gtp-channel-conf 30_116 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_BIAS_CFG[9] origin:064-gtp-channel-conf 31_116 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_BIAS_CFG[10] origin:064-gtp-channel-conf 30_117 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_BIAS_CFG[11] origin:064-gtp-channel-conf 31_117 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_BIAS_CFG[12] origin:064-gtp-channel-conf 30_118 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_BIAS_CFG[13] origin:064-gtp-channel-conf 31_118 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_BIAS_CFG[14] origin:064-gtp-channel-conf 30_119 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_BIAS_CFG[15] origin:064-gtp-channel-conf 31_119 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_BUFFER_CFG[0] origin:064-gtp-channel-conf 30_536 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_BUFFER_CFG[1] origin:064-gtp-channel-conf 31_536 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_BUFFER_CFG[2] origin:064-gtp-channel-conf 30_537 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_BUFFER_CFG[3] origin:064-gtp-channel-conf 31_537 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_BUFFER_CFG[4] origin:064-gtp-channel-conf 30_538 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_BUFFER_CFG[5] origin:064-gtp-channel-conf 31_538 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_CLKMUX_EN[0] origin:064-gtp-channel-conf 30_128 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_CM_SEL[0] origin:064-gtp-channel-conf 28_138 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_CM_SEL[1] origin:064-gtp-channel-conf 29_138 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_CM_TRIM[0] origin:064-gtp-channel-conf 30_304 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_CM_TRIM[1] origin:064-gtp-channel-conf 31_304 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_CM_TRIM[2] origin:064-gtp-channel-conf 30_305 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_CM_TRIM[3] origin:064-gtp-channel-conf 31_305 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_DATA_WIDTH[0] origin:064-gtp-channel-conf 29_141 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_DATA_WIDTH[1] origin:064-gtp-channel-conf 28_142 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_DATA_WIDTH[2] origin:064-gtp-channel-conf 29_142 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_DDI_SEL[0] origin:064-gtp-channel-conf 28_696 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_DDI_SEL[1] origin:064-gtp-channel-conf 29_696 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_DDI_SEL[2] origin:064-gtp-channel-conf 28_697 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_DDI_SEL[3] origin:064-gtp-channel-conf 29_697 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_DDI_SEL[4] origin:064-gtp-channel-conf 28_698 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_DDI_SEL[5] origin:064-gtp-channel-conf 29_698 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_DEBUG_CFG[0] origin:064-gtp-channel-conf 30_616 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_DEBUG_CFG[1] origin:064-gtp-channel-conf 31_616 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_DEBUG_CFG[2] origin:064-gtp-channel-conf 30_617 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_DEBUG_CFG[3] origin:064-gtp-channel-conf 31_617 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_DEBUG_CFG[4] origin:064-gtp-channel-conf 30_618 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_DEBUG_CFG[5] origin:064-gtp-channel-conf 31_618 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_DEBUG_CFG[6] origin:064-gtp-channel-conf 30_619 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_DEBUG_CFG[7] origin:064-gtp-channel-conf 31_619 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_DEBUG_CFG[8] origin:064-gtp-channel-conf 30_620 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_DEBUG_CFG[9] origin:064-gtp-channel-conf 31_620 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_DEBUG_CFG[10] origin:064-gtp-channel-conf 30_621 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_DEBUG_CFG[11] origin:064-gtp-channel-conf 31_621 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_DEBUG_CFG[12] origin:064-gtp-channel-conf 30_622 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_DEBUG_CFG[13] origin:064-gtp-channel-conf 31_622 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_DEFER_RESET_BUF_EN origin:064-gtp-channel-conf 30_552 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_DISPERR_SEQ_MATCH origin:064-gtp-channel-conf 29_495 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_OS_CFG[0] origin:064-gtp-channel-conf 28_288 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_OS_CFG[1] origin:064-gtp-channel-conf 29_288 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_OS_CFG[2] origin:064-gtp-channel-conf 28_289 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_OS_CFG[3] origin:064-gtp-channel-conf 29_289 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_OS_CFG[4] origin:064-gtp-channel-conf 28_290 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_OS_CFG[5] origin:064-gtp-channel-conf 29_290 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_OS_CFG[6] origin:064-gtp-channel-conf 28_291 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_OS_CFG[7] origin:064-gtp-channel-conf 29_291 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_OS_CFG[8] origin:064-gtp-channel-conf 28_292 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_OS_CFG[9] origin:064-gtp-channel-conf 29_292 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_OS_CFG[10] origin:064-gtp-channel-conf 28_293 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_OS_CFG[11] origin:064-gtp-channel-conf 29_293 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_OS_CFG[12] origin:064-gtp-channel-conf 28_294 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_SIG_VALID_DLY[0] origin:064-gtp-channel-conf 28_524 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_SIG_VALID_DLY[1] origin:064-gtp-channel-conf 29_524 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_SIG_VALID_DLY[2] origin:064-gtp-channel-conf 28_525 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_SIG_VALID_DLY[3] origin:064-gtp-channel-conf 29_525 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_SIG_VALID_DLY[4] origin:064-gtp-channel-conf 28_526 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_XCLK_SEL.RXUSR origin:064-gtp-channel-conf 28_143 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_CLK25_DIV[0] origin:064-gtp-channel-conf 28_139 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_CLK25_DIV[1] origin:064-gtp-channel-conf 29_139 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_CLK25_DIV[2] origin:064-gtp-channel-conf 28_140 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_CLK25_DIV[3] origin:064-gtp-channel-conf 29_140 +GTP_CHANNEL_1.GTPE2_CHANNEL.RX_CLK25_DIV[4] origin:064-gtp-channel-conf 28_141 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXBUF_ADDR_MODE.FAST origin:064-gtp-channel-conf 31_555 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXBUF_EIDLE_HI_CNT[0] origin:064-gtp-channel-conf 30_558 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXBUF_EIDLE_HI_CNT[1] origin:064-gtp-channel-conf 31_558 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXBUF_EIDLE_HI_CNT[2] origin:064-gtp-channel-conf 30_559 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXBUF_EIDLE_HI_CNT[3] origin:064-gtp-channel-conf 31_559 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXBUF_EIDLE_LO_CNT[0] origin:064-gtp-channel-conf 30_556 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXBUF_EIDLE_LO_CNT[1] origin:064-gtp-channel-conf 31_556 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXBUF_EIDLE_LO_CNT[2] origin:064-gtp-channel-conf 30_557 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXBUF_EIDLE_LO_CNT[3] origin:064-gtp-channel-conf 31_557 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXBUF_EN origin:064-gtp-channel-conf 30_11 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXBUF_RESET_ON_CB_CHANGE origin:064-gtp-channel-conf 30_560 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXBUF_RESET_ON_COMMAALIGN origin:064-gtp-channel-conf 30_561 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXBUF_RESET_ON_EIDLE origin:064-gtp-channel-conf 30_547 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXBUF_RESET_ON_RATE_CHANGE origin:064-gtp-channel-conf 31_560 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXBUF_THRESH_OVFLW[0] origin:064-gtp-channel-conf 31_552 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXBUF_THRESH_OVFLW[1] origin:064-gtp-channel-conf 30_553 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXBUF_THRESH_OVFLW[2] origin:064-gtp-channel-conf 31_553 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXBUF_THRESH_OVFLW[3] origin:064-gtp-channel-conf 30_554 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXBUF_THRESH_OVFLW[4] origin:064-gtp-channel-conf 31_554 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXBUF_THRESH_OVFLW[5] origin:064-gtp-channel-conf 30_555 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXBUF_THRESH_OVRD origin:064-gtp-channel-conf 30_548 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXBUF_THRESH_UNDFLW[0] origin:064-gtp-channel-conf 30_544 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXBUF_THRESH_UNDFLW[1] origin:064-gtp-channel-conf 31_544 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXBUF_THRESH_UNDFLW[2] origin:064-gtp-channel-conf 30_545 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXBUF_THRESH_UNDFLW[3] origin:064-gtp-channel-conf 31_545 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXBUF_THRESH_UNDFLW[4] origin:064-gtp-channel-conf 30_546 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXBUF_THRESH_UNDFLW[5] origin:064-gtp-channel-conf 31_546 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXBUFRESET_TIME[0] origin:064-gtp-channel-conf 29_101 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXBUFRESET_TIME[1] origin:064-gtp-channel-conf 28_102 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXBUFRESET_TIME[2] origin:064-gtp-channel-conf 29_102 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXBUFRESET_TIME[3] origin:064-gtp-channel-conf 28_103 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXBUFRESET_TIME[4] origin:064-gtp-channel-conf 29_103 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[0] origin:064-gtp-channel-conf 30_640 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[1] origin:064-gtp-channel-conf 31_640 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[2] origin:064-gtp-channel-conf 30_641 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[3] origin:064-gtp-channel-conf 31_641 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[4] origin:064-gtp-channel-conf 30_642 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[5] origin:064-gtp-channel-conf 31_642 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[6] origin:064-gtp-channel-conf 30_643 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[7] origin:064-gtp-channel-conf 31_643 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[8] origin:064-gtp-channel-conf 30_644 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[9] origin:064-gtp-channel-conf 31_644 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[10] origin:064-gtp-channel-conf 30_645 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[11] origin:064-gtp-channel-conf 31_645 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[12] origin:064-gtp-channel-conf 30_646 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[13] origin:064-gtp-channel-conf 31_646 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[14] origin:064-gtp-channel-conf 30_647 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[15] origin:064-gtp-channel-conf 31_647 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[16] origin:064-gtp-channel-conf 30_648 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[17] origin:064-gtp-channel-conf 31_648 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[18] origin:064-gtp-channel-conf 30_649 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[19] origin:064-gtp-channel-conf 31_649 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[20] origin:064-gtp-channel-conf 30_650 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[21] origin:064-gtp-channel-conf 31_650 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[22] origin:064-gtp-channel-conf 30_651 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[23] origin:064-gtp-channel-conf 31_651 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[24] origin:064-gtp-channel-conf 30_652 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[25] origin:064-gtp-channel-conf 31_652 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[26] origin:064-gtp-channel-conf 30_653 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[27] origin:064-gtp-channel-conf 31_653 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[28] origin:064-gtp-channel-conf 30_654 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[29] origin:064-gtp-channel-conf 31_654 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[30] origin:064-gtp-channel-conf 30_655 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[31] origin:064-gtp-channel-conf 31_655 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[32] origin:064-gtp-channel-conf 30_656 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[33] origin:064-gtp-channel-conf 31_656 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[34] origin:064-gtp-channel-conf 30_657 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[35] origin:064-gtp-channel-conf 31_657 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[36] origin:064-gtp-channel-conf 30_658 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[37] origin:064-gtp-channel-conf 31_658 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[38] origin:064-gtp-channel-conf 30_659 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[39] origin:064-gtp-channel-conf 31_659 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[40] origin:064-gtp-channel-conf 30_660 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[41] origin:064-gtp-channel-conf 31_660 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[42] origin:064-gtp-channel-conf 30_661 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[43] origin:064-gtp-channel-conf 31_661 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[44] origin:064-gtp-channel-conf 30_662 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[45] origin:064-gtp-channel-conf 31_662 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[46] origin:064-gtp-channel-conf 30_663 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[47] origin:064-gtp-channel-conf 31_663 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[48] origin:064-gtp-channel-conf 30_664 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[49] origin:064-gtp-channel-conf 31_664 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[50] origin:064-gtp-channel-conf 30_665 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[51] origin:064-gtp-channel-conf 31_665 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[52] origin:064-gtp-channel-conf 30_666 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[53] origin:064-gtp-channel-conf 31_666 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[54] origin:064-gtp-channel-conf 30_667 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[55] origin:064-gtp-channel-conf 31_667 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[56] origin:064-gtp-channel-conf 30_668 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[57] origin:064-gtp-channel-conf 31_668 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[58] origin:064-gtp-channel-conf 30_669 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[59] origin:064-gtp-channel-conf 31_669 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[60] origin:064-gtp-channel-conf 30_670 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[61] origin:064-gtp-channel-conf 31_670 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[62] origin:064-gtp-channel-conf 30_671 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[63] origin:064-gtp-channel-conf 31_671 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[64] origin:064-gtp-channel-conf 30_672 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[65] origin:064-gtp-channel-conf 31_672 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[66] origin:064-gtp-channel-conf 30_673 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[67] origin:064-gtp-channel-conf 31_673 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[68] origin:064-gtp-channel-conf 30_674 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[69] origin:064-gtp-channel-conf 31_674 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[70] origin:064-gtp-channel-conf 30_675 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[71] origin:064-gtp-channel-conf 31_675 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[72] origin:064-gtp-channel-conf 30_676 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[73] origin:064-gtp-channel-conf 31_676 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[74] origin:064-gtp-channel-conf 30_677 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[75] origin:064-gtp-channel-conf 31_677 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[76] origin:064-gtp-channel-conf 30_678 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[77] origin:064-gtp-channel-conf 31_678 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[78] origin:064-gtp-channel-conf 30_679 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[79] origin:064-gtp-channel-conf 31_679 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[80] origin:064-gtp-channel-conf 30_680 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[81] origin:064-gtp-channel-conf 31_680 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_CFG[82] origin:064-gtp-channel-conf 30_681 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_FR_RESET_ON_EIDLE[0] origin:064-gtp-channel-conf 30_638 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_HOLD_DURING_EIDLE[0] origin:064-gtp-channel-conf 31_637 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_LOCK_CFG[0] origin:064-gtp-channel-conf 30_632 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_LOCK_CFG[1] origin:064-gtp-channel-conf 31_632 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_LOCK_CFG[2] origin:064-gtp-channel-conf 30_633 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_LOCK_CFG[3] origin:064-gtp-channel-conf 31_633 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_LOCK_CFG[4] origin:064-gtp-channel-conf 30_634 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_LOCK_CFG[5] origin:064-gtp-channel-conf 31_634 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDR_PH_RESET_ON_EIDLE[0] origin:064-gtp-channel-conf 31_638 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDRFREQRESET_TIME[0] origin:064-gtp-channel-conf 29_106 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDRFREQRESET_TIME[1] origin:064-gtp-channel-conf 28_107 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDRFREQRESET_TIME[2] origin:064-gtp-channel-conf 29_107 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDRFREQRESET_TIME[3] origin:064-gtp-channel-conf 28_108 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDRFREQRESET_TIME[4] origin:064-gtp-channel-conf 29_108 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDRPHRESET_TIME[0] origin:064-gtp-channel-conf 28_109 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDRPHRESET_TIME[1] origin:064-gtp-channel-conf 29_109 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDRPHRESET_TIME[2] origin:064-gtp-channel-conf 28_110 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDRPHRESET_TIME[3] origin:064-gtp-channel-conf 29_110 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXCDRPHRESET_TIME[4] origin:064-gtp-channel-conf 28_111 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXDLY_CFG[0] origin:064-gtp-channel-conf 28_680 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXDLY_CFG[1] origin:064-gtp-channel-conf 29_680 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXDLY_CFG[2] origin:064-gtp-channel-conf 28_681 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXDLY_CFG[3] origin:064-gtp-channel-conf 29_681 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXDLY_CFG[4] origin:064-gtp-channel-conf 28_682 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXDLY_CFG[5] origin:064-gtp-channel-conf 29_682 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXDLY_CFG[6] origin:064-gtp-channel-conf 28_683 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXDLY_CFG[7] origin:064-gtp-channel-conf 29_683 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXDLY_CFG[8] origin:064-gtp-channel-conf 28_684 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXDLY_CFG[9] origin:064-gtp-channel-conf 29_684 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXDLY_CFG[10] origin:064-gtp-channel-conf 28_685 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXDLY_CFG[11] origin:064-gtp-channel-conf 29_685 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXDLY_CFG[12] origin:064-gtp-channel-conf 28_686 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXDLY_CFG[13] origin:064-gtp-channel-conf 29_686 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXDLY_CFG[14] origin:064-gtp-channel-conf 28_687 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXDLY_CFG[15] origin:064-gtp-channel-conf 29_687 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXDLY_LCFG[0] origin:064-gtp-channel-conf 30_576 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXDLY_LCFG[1] origin:064-gtp-channel-conf 31_576 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXDLY_LCFG[2] origin:064-gtp-channel-conf 30_577 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXDLY_LCFG[3] origin:064-gtp-channel-conf 31_577 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXDLY_LCFG[4] origin:064-gtp-channel-conf 30_578 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXDLY_LCFG[5] origin:064-gtp-channel-conf 31_578 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXDLY_LCFG[6] origin:064-gtp-channel-conf 30_579 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXDLY_LCFG[7] origin:064-gtp-channel-conf 31_579 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXDLY_LCFG[8] origin:064-gtp-channel-conf 30_580 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXDLY_TAP_CFG[0] origin:064-gtp-channel-conf 28_672 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXDLY_TAP_CFG[1] origin:064-gtp-channel-conf 29_672 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXDLY_TAP_CFG[2] origin:064-gtp-channel-conf 28_673 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXDLY_TAP_CFG[3] origin:064-gtp-channel-conf 29_673 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXDLY_TAP_CFG[4] origin:064-gtp-channel-conf 28_674 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXDLY_TAP_CFG[5] origin:064-gtp-channel-conf 29_674 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXDLY_TAP_CFG[6] origin:064-gtp-channel-conf 28_675 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXDLY_TAP_CFG[7] origin:064-gtp-channel-conf 29_675 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXDLY_TAP_CFG[8] origin:064-gtp-channel-conf 28_676 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXDLY_TAP_CFG[9] origin:064-gtp-channel-conf 29_676 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXDLY_TAP_CFG[10] origin:064-gtp-channel-conf 28_677 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXDLY_TAP_CFG[11] origin:064-gtp-channel-conf 29_677 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXDLY_TAP_CFG[12] origin:064-gtp-channel-conf 28_678 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXDLY_TAP_CFG[13] origin:064-gtp-channel-conf 29_678 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXDLY_TAP_CFG[14] origin:064-gtp-channel-conf 28_679 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXDLY_TAP_CFG[15] origin:064-gtp-channel-conf 29_679 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXGEARBOX_EN origin:064-gtp-channel-conf 29_607 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXISCANRESET_TIME[0] origin:064-gtp-channel-conf 29_123 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXISCANRESET_TIME[1] origin:064-gtp-channel-conf 28_124 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXISCANRESET_TIME[2] origin:064-gtp-channel-conf 29_124 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXISCANRESET_TIME[3] origin:064-gtp-channel-conf 28_125 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXISCANRESET_TIME[4] origin:064-gtp-channel-conf 29_125 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPM_BIAS_STARTUP_DISABLE[0] origin:064-gtp-channel-conf 31_391 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPM_CFG[0] origin:064-gtp-channel-conf 30_328 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPM_CFG[1] origin:064-gtp-channel-conf 31_328 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPM_CFG[2] origin:064-gtp-channel-conf 30_329 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPM_CFG[3] origin:064-gtp-channel-conf 31_329 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPM_CM_CFG[0] origin:064-gtp-channel-conf 30_430 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPM_GC_CFG[0] origin:064-gtp-channel-conf 30_432 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPM_GC_CFG[1] origin:064-gtp-channel-conf 31_432 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPM_GC_CFG[2] origin:064-gtp-channel-conf 30_433 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPM_GC_CFG[3] origin:064-gtp-channel-conf 31_433 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPM_GC_CFG[4] origin:064-gtp-channel-conf 30_434 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPM_GC_CFG[5] origin:064-gtp-channel-conf 31_434 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPM_GC_CFG[6] origin:064-gtp-channel-conf 30_435 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPM_GC_CFG[7] origin:064-gtp-channel-conf 31_435 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPM_GC_CFG[8] origin:064-gtp-channel-conf 30_436 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPM_GC_CFG2[0] origin:064-gtp-channel-conf 31_442 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPM_GC_CFG2[1] origin:064-gtp-channel-conf 30_443 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPM_GC_CFG2[2] origin:064-gtp-channel-conf 31_443 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPM_HF_CFG[0] origin:064-gtp-channel-conf 28_336 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPM_HF_CFG[1] origin:064-gtp-channel-conf 29_336 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPM_HF_CFG[2] origin:064-gtp-channel-conf 28_337 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPM_HF_CFG[3] origin:064-gtp-channel-conf 29_337 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPM_HF_CFG[4] origin:064-gtp-channel-conf 28_338 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPM_HF_CFG[5] origin:064-gtp-channel-conf 29_338 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPM_HF_CFG[6] origin:064-gtp-channel-conf 28_339 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPM_HF_CFG[7] origin:064-gtp-channel-conf 29_339 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPM_HF_CFG[8] origin:064-gtp-channel-conf 28_340 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPM_HF_CFG[9] origin:064-gtp-channel-conf 29_340 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPM_HF_CFG[10] origin:064-gtp-channel-conf 28_341 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPM_HF_CFG[11] origin:064-gtp-channel-conf 29_341 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPM_HF_CFG[12] origin:064-gtp-channel-conf 28_342 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPM_HF_CFG[13] origin:064-gtp-channel-conf 29_342 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPM_HF_CFG2[0] origin:064-gtp-channel-conf 30_424 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPM_HF_CFG2[1] origin:064-gtp-channel-conf 31_424 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPM_HF_CFG2[2] origin:064-gtp-channel-conf 30_425 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPM_HF_CFG2[3] origin:064-gtp-channel-conf 31_425 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPM_HF_CFG2[4] origin:064-gtp-channel-conf 30_426 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPM_HF_CFG3[0] origin:064-gtp-channel-conf 31_389 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPM_HF_CFG3[1] origin:064-gtp-channel-conf 30_390 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPM_HF_CFG3[2] origin:064-gtp-channel-conf 31_390 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPM_HF_CFG3[3] origin:064-gtp-channel-conf 30_391 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPM_HOLD_DURING_EIDLE[0] origin:064-gtp-channel-conf 28_247 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPM_INCM_CFG[0] origin:064-gtp-channel-conf 30_439 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPM_IPCM_CFG[0] origin:064-gtp-channel-conf 31_439 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPM_LF_CFG[0] origin:064-gtp-channel-conf 28_344 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPM_LF_CFG[1] origin:064-gtp-channel-conf 29_344 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPM_LF_CFG[2] origin:064-gtp-channel-conf 28_345 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPM_LF_CFG[3] origin:064-gtp-channel-conf 29_345 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPM_LF_CFG[4] origin:064-gtp-channel-conf 28_346 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPM_LF_CFG[5] origin:064-gtp-channel-conf 29_346 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPM_LF_CFG[6] origin:064-gtp-channel-conf 28_347 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPM_LF_CFG[7] origin:064-gtp-channel-conf 29_347 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPM_LF_CFG[8] origin:064-gtp-channel-conf 28_348 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPM_LF_CFG[9] origin:064-gtp-channel-conf 29_348 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPM_LF_CFG[10] origin:064-gtp-channel-conf 28_349 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPM_LF_CFG[11] origin:064-gtp-channel-conf 29_349 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPM_LF_CFG[12] origin:064-gtp-channel-conf 28_350 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPM_LF_CFG[13] origin:064-gtp-channel-conf 29_350 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPM_LF_CFG[14] origin:064-gtp-channel-conf 28_351 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPM_LF_CFG[15] origin:064-gtp-channel-conf 29_351 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPM_LF_CFG[16] origin:064-gtp-channel-conf 28_343 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPM_LF_CFG[17] origin:064-gtp-channel-conf 29_343 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPM_LF_CFG2[0] origin:064-gtp-channel-conf 31_426 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPM_LF_CFG2[1] origin:064-gtp-channel-conf 30_427 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPM_LF_CFG2[2] origin:064-gtp-channel-conf 31_427 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPM_LF_CFG2[3] origin:064-gtp-channel-conf 30_428 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPM_LF_CFG2[4] origin:064-gtp-channel-conf 31_428 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPM_OSINT_CFG[0] origin:064-gtp-channel-conf 30_440 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPM_OSINT_CFG[1] origin:064-gtp-channel-conf 31_440 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPM_OSINT_CFG[2] origin:064-gtp-channel-conf 30_441 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPM_CFG1[0] origin:064-gtp-channel-conf 30_330 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPMRESET_TIME[0] origin:064-gtp-channel-conf 28_112 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPMRESET_TIME[1] origin:064-gtp-channel-conf 29_112 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPMRESET_TIME[2] origin:064-gtp-channel-conf 28_113 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPMRESET_TIME[3] origin:064-gtp-channel-conf 29_113 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPMRESET_TIME[4] origin:064-gtp-channel-conf 28_114 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPMRESET_TIME[5] origin:064-gtp-channel-conf 29_114 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXLPMRESET_TIME[6] origin:064-gtp-channel-conf 28_115 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXOOB_CFG[0] origin:064-gtp-channel-conf 28_144 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXOOB_CFG[1] origin:064-gtp-channel-conf 29_144 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXOOB_CFG[2] origin:064-gtp-channel-conf 28_145 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXOOB_CFG[3] origin:064-gtp-channel-conf 29_145 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXOOB_CFG[4] origin:064-gtp-channel-conf 28_146 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXOOB_CFG[5] origin:064-gtp-channel-conf 29_146 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXOOB_CFG[6] origin:064-gtp-channel-conf 28_147 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXOOB_CLK_CFG.FABRIC origin:064-gtp-channel-conf 31_129 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXOSCALRESET_TIME[0] origin:064-gtp-channel-conf 28_187 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXOSCALRESET_TIME[1] origin:064-gtp-channel-conf 29_187 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXOSCALRESET_TIME[2] origin:064-gtp-channel-conf 28_188 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXOSCALRESET_TIME[3] origin:064-gtp-channel-conf 29_188 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXOSCALRESET_TIME[4] origin:064-gtp-channel-conf 28_189 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXOSCALRESET_TIMEOUT[0] origin:064-gtp-channel-conf 29_189 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXOSCALRESET_TIMEOUT[1] origin:064-gtp-channel-conf 28_190 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXOSCALRESET_TIMEOUT[2] origin:064-gtp-channel-conf 29_190 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXOSCALRESET_TIMEOUT[3] origin:064-gtp-channel-conf 28_191 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXOSCALRESET_TIMEOUT[4] origin:064-gtp-channel-conf 29_191 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXOUT_DIV[0] origin:064-gtp-channel-conf 30_384 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXOUT_DIV[1] origin:064-gtp-channel-conf 31_384 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXPCSRESET_TIME[0] origin:064-gtp-channel-conf 29_115 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXPCSRESET_TIME[1] origin:064-gtp-channel-conf 28_116 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXPCSRESET_TIME[2] origin:064-gtp-channel-conf 29_116 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXPCSRESET_TIME[3] origin:064-gtp-channel-conf 28_117 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXPCSRESET_TIME[4] origin:064-gtp-channel-conf 29_117 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXPH_CFG[0] origin:064-gtp-channel-conf 30_584 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXPH_CFG[1] origin:064-gtp-channel-conf 31_584 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXPH_CFG[2] origin:064-gtp-channel-conf 30_585 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXPH_CFG[3] origin:064-gtp-channel-conf 31_585 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXPH_CFG[4] origin:064-gtp-channel-conf 30_586 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXPH_CFG[5] origin:064-gtp-channel-conf 31_586 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXPH_CFG[6] origin:064-gtp-channel-conf 30_587 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXPH_CFG[7] origin:064-gtp-channel-conf 31_587 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXPH_CFG[8] origin:064-gtp-channel-conf 30_588 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXPH_CFG[9] origin:064-gtp-channel-conf 31_588 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXPH_CFG[10] origin:064-gtp-channel-conf 30_589 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXPH_CFG[11] origin:064-gtp-channel-conf 31_589 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXPH_CFG[12] origin:064-gtp-channel-conf 30_590 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXPH_CFG[13] origin:064-gtp-channel-conf 31_590 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXPH_CFG[14] origin:064-gtp-channel-conf 30_591 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXPH_CFG[15] origin:064-gtp-channel-conf 31_591 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXPH_CFG[16] origin:064-gtp-channel-conf 30_592 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXPH_CFG[17] origin:064-gtp-channel-conf 31_592 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXPH_CFG[18] origin:064-gtp-channel-conf 30_593 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXPH_CFG[19] origin:064-gtp-channel-conf 31_593 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXPH_CFG[20] origin:064-gtp-channel-conf 30_594 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXPH_CFG[21] origin:064-gtp-channel-conf 31_594 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXPH_CFG[22] origin:064-gtp-channel-conf 30_595 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXPH_CFG[23] origin:064-gtp-channel-conf 31_595 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXPH_MONITOR_SEL[0] origin:064-gtp-channel-conf 28_700 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXPH_MONITOR_SEL[1] origin:064-gtp-channel-conf 29_700 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXPH_MONITOR_SEL[2] origin:064-gtp-channel-conf 28_701 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXPH_MONITOR_SEL[3] origin:064-gtp-channel-conf 29_701 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXPH_MONITOR_SEL[4] origin:064-gtp-channel-conf 28_702 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXPHDLY_CFG[0] origin:064-gtp-channel-conf 30_600 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXPHDLY_CFG[1] origin:064-gtp-channel-conf 31_600 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXPHDLY_CFG[2] origin:064-gtp-channel-conf 30_601 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXPHDLY_CFG[3] origin:064-gtp-channel-conf 31_601 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXPHDLY_CFG[4] origin:064-gtp-channel-conf 30_602 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXPHDLY_CFG[5] origin:064-gtp-channel-conf 31_602 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXPHDLY_CFG[6] origin:064-gtp-channel-conf 30_603 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXPHDLY_CFG[7] origin:064-gtp-channel-conf 31_603 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXPHDLY_CFG[8] origin:064-gtp-channel-conf 30_604 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXPHDLY_CFG[9] origin:064-gtp-channel-conf 31_604 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXPHDLY_CFG[10] origin:064-gtp-channel-conf 30_605 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXPHDLY_CFG[11] origin:064-gtp-channel-conf 31_605 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXPHDLY_CFG[12] origin:064-gtp-channel-conf 30_606 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXPHDLY_CFG[13] origin:064-gtp-channel-conf 31_606 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXPHDLY_CFG[14] origin:064-gtp-channel-conf 30_607 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXPHDLY_CFG[15] origin:064-gtp-channel-conf 31_607 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXPHDLY_CFG[16] origin:064-gtp-channel-conf 30_608 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXPHDLY_CFG[17] origin:064-gtp-channel-conf 31_608 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXPHDLY_CFG[18] origin:064-gtp-channel-conf 30_609 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXPHDLY_CFG[19] origin:064-gtp-channel-conf 31_609 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXPHDLY_CFG[20] origin:064-gtp-channel-conf 30_610 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXPHDLY_CFG[21] origin:064-gtp-channel-conf 31_610 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXPHDLY_CFG[22] origin:064-gtp-channel-conf 30_611 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXPHDLY_CFG[23] origin:064-gtp-channel-conf 31_611 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXPI_CFG0[0] origin:064-gtp-channel-conf 31_430 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXPI_CFG0[1] origin:064-gtp-channel-conf 30_431 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXPI_CFG0[2] origin:064-gtp-channel-conf 31_431 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXPI_CFG1[0] origin:064-gtp-channel-conf 30_442 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXPI_CFG2[0] origin:064-gtp-channel-conf 31_441 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXPMARESET_TIME[0] origin:064-gtp-channel-conf 28_104 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXPMARESET_TIME[1] origin:064-gtp-channel-conf 29_104 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXPMARESET_TIME[2] origin:064-gtp-channel-conf 28_105 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXPMARESET_TIME[3] origin:064-gtp-channel-conf 29_105 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXPMARESET_TIME[4] origin:064-gtp-channel-conf 28_106 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXPRBS_ERR_LOOPBACK[0] origin:064-gtp-channel-conf 28_136 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXSLIDE_AUTO_WAIT[0] origin:064-gtp-channel-conf 28_520 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXSLIDE_AUTO_WAIT[1] origin:064-gtp-channel-conf 29_520 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXSLIDE_AUTO_WAIT[2] origin:064-gtp-channel-conf 28_521 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXSLIDE_AUTO_WAIT[3] origin:064-gtp-channel-conf 29_521 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXSLIDE_MODE.AUTO origin:064-gtp-channel-conf !29_519 28_519 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXSLIDE_MODE.PCS origin:064-gtp-channel-conf !28_519 29_519 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXSLIDE_MODE.PMA origin:064-gtp-channel-conf 28_519 29_519 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXSYNC_MULTILANE[0] origin:064-gtp-channel-conf 28_133 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXSYNC_OVRD[0] origin:064-gtp-channel-conf 29_135 +GTP_CHANNEL_1.GTPE2_CHANNEL.RXSYNC_SKIP_DA[0] origin:064-gtp-channel-conf 29_134 +GTP_CHANNEL_1.GTPE2_CHANNEL.SAS_MAX_COM[0] origin:064-gtp-channel-conf 28_171 +GTP_CHANNEL_1.GTPE2_CHANNEL.SAS_MAX_COM[1] origin:064-gtp-channel-conf 29_171 +GTP_CHANNEL_1.GTPE2_CHANNEL.SAS_MAX_COM[2] origin:064-gtp-channel-conf 28_172 +GTP_CHANNEL_1.GTPE2_CHANNEL.SAS_MAX_COM[3] origin:064-gtp-channel-conf 29_172 +GTP_CHANNEL_1.GTPE2_CHANNEL.SAS_MAX_COM[4] origin:064-gtp-channel-conf 28_173 +GTP_CHANNEL_1.GTPE2_CHANNEL.SAS_MAX_COM[5] origin:064-gtp-channel-conf 29_173 +GTP_CHANNEL_1.GTPE2_CHANNEL.SAS_MAX_COM[6] origin:064-gtp-channel-conf 28_174 +GTP_CHANNEL_1.GTPE2_CHANNEL.SAS_MIN_COM[0] origin:064-gtp-channel-conf 29_156 +GTP_CHANNEL_1.GTPE2_CHANNEL.SAS_MIN_COM[1] origin:064-gtp-channel-conf 28_157 +GTP_CHANNEL_1.GTPE2_CHANNEL.SAS_MIN_COM[2] origin:064-gtp-channel-conf 29_157 +GTP_CHANNEL_1.GTPE2_CHANNEL.SAS_MIN_COM[3] origin:064-gtp-channel-conf 28_158 +GTP_CHANNEL_1.GTPE2_CHANNEL.SAS_MIN_COM[4] origin:064-gtp-channel-conf 29_158 +GTP_CHANNEL_1.GTPE2_CHANNEL.SAS_MIN_COM[5] origin:064-gtp-channel-conf 28_159 +GTP_CHANNEL_1.GTPE2_CHANNEL.SATA_BURST_SEQ_LEN[0] origin:064-gtp-channel-conf 28_150 +GTP_CHANNEL_1.GTPE2_CHANNEL.SATA_BURST_SEQ_LEN[1] origin:064-gtp-channel-conf 29_150 +GTP_CHANNEL_1.GTPE2_CHANNEL.SATA_BURST_SEQ_LEN[2] origin:064-gtp-channel-conf 28_151 +GTP_CHANNEL_1.GTPE2_CHANNEL.SATA_BURST_SEQ_LEN[3] origin:064-gtp-channel-conf 29_151 +GTP_CHANNEL_1.GTPE2_CHANNEL.SATA_BURST_VAL[0] origin:064-gtp-channel-conf 29_147 +GTP_CHANNEL_1.GTPE2_CHANNEL.SATA_BURST_VAL[1] origin:064-gtp-channel-conf 28_148 +GTP_CHANNEL_1.GTPE2_CHANNEL.SATA_BURST_VAL[2] origin:064-gtp-channel-conf 29_148 +GTP_CHANNEL_1.GTPE2_CHANNEL.SATA_EIDLE_VAL[0] origin:064-gtp-channel-conf 28_152 +GTP_CHANNEL_1.GTPE2_CHANNEL.SATA_EIDLE_VAL[1] origin:064-gtp-channel-conf 29_152 +GTP_CHANNEL_1.GTPE2_CHANNEL.SATA_EIDLE_VAL[2] origin:064-gtp-channel-conf 28_153 +GTP_CHANNEL_1.GTPE2_CHANNEL.SATA_MAX_BURST[0] origin:064-gtp-channel-conf 28_168 +GTP_CHANNEL_1.GTPE2_CHANNEL.SATA_MAX_BURST[1] origin:064-gtp-channel-conf 29_168 +GTP_CHANNEL_1.GTPE2_CHANNEL.SATA_MAX_BURST[2] origin:064-gtp-channel-conf 28_169 +GTP_CHANNEL_1.GTPE2_CHANNEL.SATA_MAX_BURST[3] origin:064-gtp-channel-conf 29_169 +GTP_CHANNEL_1.GTPE2_CHANNEL.SATA_MAX_BURST[4] origin:064-gtp-channel-conf 28_170 +GTP_CHANNEL_1.GTPE2_CHANNEL.SATA_MAX_BURST[5] origin:064-gtp-channel-conf 29_170 +GTP_CHANNEL_1.GTPE2_CHANNEL.SATA_MAX_INIT[0] origin:064-gtp-channel-conf 28_176 +GTP_CHANNEL_1.GTPE2_CHANNEL.SATA_MAX_INIT[1] origin:064-gtp-channel-conf 29_176 +GTP_CHANNEL_1.GTPE2_CHANNEL.SATA_MAX_INIT[2] origin:064-gtp-channel-conf 28_177 +GTP_CHANNEL_1.GTPE2_CHANNEL.SATA_MAX_INIT[3] origin:064-gtp-channel-conf 29_177 +GTP_CHANNEL_1.GTPE2_CHANNEL.SATA_MAX_INIT[4] origin:064-gtp-channel-conf 28_178 +GTP_CHANNEL_1.GTPE2_CHANNEL.SATA_MAX_INIT[5] origin:064-gtp-channel-conf 29_178 +GTP_CHANNEL_1.GTPE2_CHANNEL.SATA_MAX_WAKE[0] origin:064-gtp-channel-conf 28_179 +GTP_CHANNEL_1.GTPE2_CHANNEL.SATA_MAX_WAKE[1] origin:064-gtp-channel-conf 29_179 +GTP_CHANNEL_1.GTPE2_CHANNEL.SATA_MAX_WAKE[2] origin:064-gtp-channel-conf 28_180 +GTP_CHANNEL_1.GTPE2_CHANNEL.SATA_MAX_WAKE[3] origin:064-gtp-channel-conf 29_180 +GTP_CHANNEL_1.GTPE2_CHANNEL.SATA_MAX_WAKE[4] origin:064-gtp-channel-conf 28_181 +GTP_CHANNEL_1.GTPE2_CHANNEL.SATA_MAX_WAKE[5] origin:064-gtp-channel-conf 29_181 +GTP_CHANNEL_1.GTPE2_CHANNEL.SATA_MIN_BURST[0] origin:064-gtp-channel-conf 29_153 +GTP_CHANNEL_1.GTPE2_CHANNEL.SATA_MIN_BURST[1] origin:064-gtp-channel-conf 28_154 +GTP_CHANNEL_1.GTPE2_CHANNEL.SATA_MIN_BURST[2] origin:064-gtp-channel-conf 29_154 +GTP_CHANNEL_1.GTPE2_CHANNEL.SATA_MIN_BURST[3] origin:064-gtp-channel-conf 28_155 +GTP_CHANNEL_1.GTPE2_CHANNEL.SATA_MIN_BURST[4] origin:064-gtp-channel-conf 29_155 +GTP_CHANNEL_1.GTPE2_CHANNEL.SATA_MIN_BURST[5] origin:064-gtp-channel-conf 28_156 +GTP_CHANNEL_1.GTPE2_CHANNEL.SATA_MIN_INIT[0] origin:064-gtp-channel-conf 28_160 +GTP_CHANNEL_1.GTPE2_CHANNEL.SATA_MIN_INIT[1] origin:064-gtp-channel-conf 29_160 +GTP_CHANNEL_1.GTPE2_CHANNEL.SATA_MIN_INIT[2] origin:064-gtp-channel-conf 28_161 +GTP_CHANNEL_1.GTPE2_CHANNEL.SATA_MIN_INIT[3] origin:064-gtp-channel-conf 29_161 +GTP_CHANNEL_1.GTPE2_CHANNEL.SATA_MIN_INIT[4] origin:064-gtp-channel-conf 28_162 +GTP_CHANNEL_1.GTPE2_CHANNEL.SATA_MIN_INIT[5] origin:064-gtp-channel-conf 29_162 +GTP_CHANNEL_1.GTPE2_CHANNEL.SATA_MIN_WAKE[0] origin:064-gtp-channel-conf 28_163 +GTP_CHANNEL_1.GTPE2_CHANNEL.SATA_MIN_WAKE[1] origin:064-gtp-channel-conf 29_163 +GTP_CHANNEL_1.GTPE2_CHANNEL.SATA_MIN_WAKE[2] origin:064-gtp-channel-conf 28_164 +GTP_CHANNEL_1.GTPE2_CHANNEL.SATA_MIN_WAKE[3] origin:064-gtp-channel-conf 29_164 +GTP_CHANNEL_1.GTPE2_CHANNEL.SATA_MIN_WAKE[4] origin:064-gtp-channel-conf 28_165 +GTP_CHANNEL_1.GTPE2_CHANNEL.SATA_MIN_WAKE[5] origin:064-gtp-channel-conf 29_165 +GTP_CHANNEL_1.GTPE2_CHANNEL.SATA_PLL_CFG.VCO_1500MHZ origin:064-gtp-channel-conf 30_55 +GTP_CHANNEL_1.GTPE2_CHANNEL.SATA_PLL_CFG.VCO_750MHZ origin:064-gtp-channel-conf 31_55 +GTP_CHANNEL_1.GTPE2_CHANNEL.SHOW_REALIGN_COMMA origin:064-gtp-channel-conf 29_522 +GTP_CHANNEL_1.GTPE2_CHANNEL.TERM_RCAL_CFG[0] origin:064-gtp-channel-conf 30_136 +GTP_CHANNEL_1.GTPE2_CHANNEL.TERM_RCAL_CFG[1] origin:064-gtp-channel-conf 31_136 +GTP_CHANNEL_1.GTPE2_CHANNEL.TERM_RCAL_CFG[2] origin:064-gtp-channel-conf 30_137 +GTP_CHANNEL_1.GTPE2_CHANNEL.TERM_RCAL_CFG[3] origin:064-gtp-channel-conf 31_137 +GTP_CHANNEL_1.GTPE2_CHANNEL.TERM_RCAL_CFG[4] origin:064-gtp-channel-conf 30_138 +GTP_CHANNEL_1.GTPE2_CHANNEL.TERM_RCAL_CFG[5] origin:064-gtp-channel-conf 31_138 +GTP_CHANNEL_1.GTPE2_CHANNEL.TERM_RCAL_CFG[6] origin:064-gtp-channel-conf 30_139 +GTP_CHANNEL_1.GTPE2_CHANNEL.TERM_RCAL_CFG[7] origin:064-gtp-channel-conf 31_139 +GTP_CHANNEL_1.GTPE2_CHANNEL.TERM_RCAL_CFG[8] origin:064-gtp-channel-conf 30_140 +GTP_CHANNEL_1.GTPE2_CHANNEL.TERM_RCAL_CFG[9] origin:064-gtp-channel-conf 31_140 +GTP_CHANNEL_1.GTPE2_CHANNEL.TERM_RCAL_CFG[10] origin:064-gtp-channel-conf 30_141 +GTP_CHANNEL_1.GTPE2_CHANNEL.TERM_RCAL_CFG[11] origin:064-gtp-channel-conf 31_141 +GTP_CHANNEL_1.GTPE2_CHANNEL.TERM_RCAL_CFG[12] origin:064-gtp-channel-conf 30_142 +GTP_CHANNEL_1.GTPE2_CHANNEL.TERM_RCAL_CFG[13] origin:064-gtp-channel-conf 31_142 +GTP_CHANNEL_1.GTPE2_CHANNEL.TERM_RCAL_CFG[14] origin:064-gtp-channel-conf 30_143 +GTP_CHANNEL_1.GTPE2_CHANNEL.TERM_RCAL_OVRD[0] origin:064-gtp-channel-conf 31_150 +GTP_CHANNEL_1.GTPE2_CHANNEL.TERM_RCAL_OVRD[1] origin:064-gtp-channel-conf 30_151 +GTP_CHANNEL_1.GTPE2_CHANNEL.TERM_RCAL_OVRD[2] origin:064-gtp-channel-conf 31_151 +GTP_CHANNEL_1.GTPE2_CHANNEL.TRANS_TIME_RATE[0] origin:064-gtp-channel-conf 28_192 +GTP_CHANNEL_1.GTPE2_CHANNEL.TRANS_TIME_RATE[1] origin:064-gtp-channel-conf 29_192 +GTP_CHANNEL_1.GTPE2_CHANNEL.TRANS_TIME_RATE[2] origin:064-gtp-channel-conf 28_193 +GTP_CHANNEL_1.GTPE2_CHANNEL.TRANS_TIME_RATE[3] origin:064-gtp-channel-conf 29_193 +GTP_CHANNEL_1.GTPE2_CHANNEL.TRANS_TIME_RATE[4] origin:064-gtp-channel-conf 28_194 +GTP_CHANNEL_1.GTPE2_CHANNEL.TRANS_TIME_RATE[5] origin:064-gtp-channel-conf 29_194 +GTP_CHANNEL_1.GTPE2_CHANNEL.TRANS_TIME_RATE[6] origin:064-gtp-channel-conf 28_195 +GTP_CHANNEL_1.GTPE2_CHANNEL.TRANS_TIME_RATE[7] origin:064-gtp-channel-conf 29_195 +GTP_CHANNEL_1.GTPE2_CHANNEL.TST_RSV[0] origin:064-gtp-channel-conf 30_504 +GTP_CHANNEL_1.GTPE2_CHANNEL.TST_RSV[1] origin:064-gtp-channel-conf 31_504 +GTP_CHANNEL_1.GTPE2_CHANNEL.TST_RSV[2] origin:064-gtp-channel-conf 30_505 +GTP_CHANNEL_1.GTPE2_CHANNEL.TST_RSV[3] origin:064-gtp-channel-conf 31_505 +GTP_CHANNEL_1.GTPE2_CHANNEL.TST_RSV[4] origin:064-gtp-channel-conf 30_506 +GTP_CHANNEL_1.GTPE2_CHANNEL.TST_RSV[5] origin:064-gtp-channel-conf 31_506 +GTP_CHANNEL_1.GTPE2_CHANNEL.TST_RSV[6] origin:064-gtp-channel-conf 30_507 +GTP_CHANNEL_1.GTPE2_CHANNEL.TST_RSV[7] origin:064-gtp-channel-conf 31_507 +GTP_CHANNEL_1.GTPE2_CHANNEL.TST_RSV[8] origin:064-gtp-channel-conf 30_508 +GTP_CHANNEL_1.GTPE2_CHANNEL.TST_RSV[9] origin:064-gtp-channel-conf 31_508 +GTP_CHANNEL_1.GTPE2_CHANNEL.TST_RSV[10] origin:064-gtp-channel-conf 30_509 +GTP_CHANNEL_1.GTPE2_CHANNEL.TST_RSV[11] origin:064-gtp-channel-conf 31_509 +GTP_CHANNEL_1.GTPE2_CHANNEL.TST_RSV[12] origin:064-gtp-channel-conf 30_510 +GTP_CHANNEL_1.GTPE2_CHANNEL.TST_RSV[13] origin:064-gtp-channel-conf 31_510 +GTP_CHANNEL_1.GTPE2_CHANNEL.TST_RSV[14] origin:064-gtp-channel-conf 30_511 +GTP_CHANNEL_1.GTPE2_CHANNEL.TST_RSV[15] origin:064-gtp-channel-conf 31_511 +GTP_CHANNEL_1.GTPE2_CHANNEL.TST_RSV[16] origin:064-gtp-channel-conf 30_512 +GTP_CHANNEL_1.GTPE2_CHANNEL.TST_RSV[17] origin:064-gtp-channel-conf 31_512 +GTP_CHANNEL_1.GTPE2_CHANNEL.TST_RSV[18] origin:064-gtp-channel-conf 30_513 +GTP_CHANNEL_1.GTPE2_CHANNEL.TST_RSV[19] origin:064-gtp-channel-conf 31_513 +GTP_CHANNEL_1.GTPE2_CHANNEL.TST_RSV[20] origin:064-gtp-channel-conf 30_514 +GTP_CHANNEL_1.GTPE2_CHANNEL.TST_RSV[21] origin:064-gtp-channel-conf 31_514 +GTP_CHANNEL_1.GTPE2_CHANNEL.TST_RSV[22] origin:064-gtp-channel-conf 30_515 +GTP_CHANNEL_1.GTPE2_CHANNEL.TST_RSV[23] origin:064-gtp-channel-conf 31_515 +GTP_CHANNEL_1.GTPE2_CHANNEL.TST_RSV[24] origin:064-gtp-channel-conf 30_516 +GTP_CHANNEL_1.GTPE2_CHANNEL.TST_RSV[25] origin:064-gtp-channel-conf 31_516 +GTP_CHANNEL_1.GTPE2_CHANNEL.TST_RSV[26] origin:064-gtp-channel-conf 30_517 +GTP_CHANNEL_1.GTPE2_CHANNEL.TST_RSV[27] origin:064-gtp-channel-conf 31_517 +GTP_CHANNEL_1.GTPE2_CHANNEL.TST_RSV[28] origin:064-gtp-channel-conf 30_518 +GTP_CHANNEL_1.GTPE2_CHANNEL.TST_RSV[29] origin:064-gtp-channel-conf 31_518 +GTP_CHANNEL_1.GTPE2_CHANNEL.TST_RSV[30] origin:064-gtp-channel-conf 30_519 +GTP_CHANNEL_1.GTPE2_CHANNEL.TST_RSV[31] origin:064-gtp-channel-conf 31_519 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_CLKMUX_EN[0] origin:064-gtp-channel-conf 31_128 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_DATA_WIDTH[0] origin:064-gtp-channel-conf 30_152 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_DATA_WIDTH[1] origin:064-gtp-channel-conf 31_152 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_DATA_WIDTH[2] origin:064-gtp-channel-conf 30_153 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_DRIVE_MODE.PIPE origin:064-gtp-channel-conf 28_200 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_EIDLE_ASSERT_DELAY[0] origin:064-gtp-channel-conf 28_203 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_EIDLE_ASSERT_DELAY[1] origin:064-gtp-channel-conf 29_203 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_EIDLE_ASSERT_DELAY[2] origin:064-gtp-channel-conf 28_204 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_EIDLE_DEASSERT_DELAY[0] origin:064-gtp-channel-conf 29_204 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_EIDLE_DEASSERT_DELAY[1] origin:064-gtp-channel-conf 28_205 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_EIDLE_DEASSERT_DELAY[2] origin:064-gtp-channel-conf 29_205 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_LOOPBACK_DRIVE_HIZ origin:064-gtp-channel-conf 29_202 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_MAINCURSOR_SEL[0] origin:064-gtp-channel-conf 31_289 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_MARGIN_FULL_0[0] origin:064-gtp-channel-conf 30_232 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_MARGIN_FULL_0[1] origin:064-gtp-channel-conf 31_232 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_MARGIN_FULL_0[2] origin:064-gtp-channel-conf 30_233 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_MARGIN_FULL_0[3] origin:064-gtp-channel-conf 31_233 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_MARGIN_FULL_0[4] origin:064-gtp-channel-conf 30_234 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_MARGIN_FULL_0[5] origin:064-gtp-channel-conf 31_234 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_MARGIN_FULL_0[6] origin:064-gtp-channel-conf 30_235 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_MARGIN_FULL_1[0] origin:064-gtp-channel-conf 30_236 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_MARGIN_FULL_1[1] origin:064-gtp-channel-conf 31_236 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_MARGIN_FULL_1[2] origin:064-gtp-channel-conf 30_237 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_MARGIN_FULL_1[3] origin:064-gtp-channel-conf 31_237 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_MARGIN_FULL_1[4] origin:064-gtp-channel-conf 30_238 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_MARGIN_FULL_1[5] origin:064-gtp-channel-conf 31_238 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_MARGIN_FULL_1[6] origin:064-gtp-channel-conf 30_239 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_MARGIN_FULL_2[0] origin:064-gtp-channel-conf 30_240 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_MARGIN_FULL_2[1] origin:064-gtp-channel-conf 31_240 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_MARGIN_FULL_2[2] origin:064-gtp-channel-conf 30_241 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_MARGIN_FULL_2[3] origin:064-gtp-channel-conf 31_241 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_MARGIN_FULL_2[4] origin:064-gtp-channel-conf 30_242 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_MARGIN_FULL_2[5] origin:064-gtp-channel-conf 31_242 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_MARGIN_FULL_2[6] origin:064-gtp-channel-conf 30_243 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_MARGIN_FULL_3[0] origin:064-gtp-channel-conf 30_244 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_MARGIN_FULL_3[1] origin:064-gtp-channel-conf 31_244 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_MARGIN_FULL_3[2] origin:064-gtp-channel-conf 30_245 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_MARGIN_FULL_3[3] origin:064-gtp-channel-conf 31_245 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_MARGIN_FULL_3[4] origin:064-gtp-channel-conf 30_246 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_MARGIN_FULL_3[5] origin:064-gtp-channel-conf 31_246 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_MARGIN_FULL_3[6] origin:064-gtp-channel-conf 30_247 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_MARGIN_FULL_4[0] origin:064-gtp-channel-conf 30_248 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_MARGIN_FULL_4[1] origin:064-gtp-channel-conf 31_248 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_MARGIN_FULL_4[2] origin:064-gtp-channel-conf 30_249 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_MARGIN_FULL_4[3] origin:064-gtp-channel-conf 31_249 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_MARGIN_FULL_4[4] origin:064-gtp-channel-conf 30_250 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_MARGIN_FULL_4[5] origin:064-gtp-channel-conf 31_250 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_MARGIN_FULL_4[6] origin:064-gtp-channel-conf 30_251 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_MARGIN_LOW_0[0] origin:064-gtp-channel-conf 30_252 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_MARGIN_LOW_0[1] origin:064-gtp-channel-conf 31_252 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_MARGIN_LOW_0[2] origin:064-gtp-channel-conf 30_253 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_MARGIN_LOW_0[3] origin:064-gtp-channel-conf 31_253 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_MARGIN_LOW_0[4] origin:064-gtp-channel-conf 30_254 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_MARGIN_LOW_0[5] origin:064-gtp-channel-conf 31_254 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_MARGIN_LOW_0[6] origin:064-gtp-channel-conf 30_255 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_MARGIN_LOW_1[0] origin:064-gtp-channel-conf 30_256 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_MARGIN_LOW_1[1] origin:064-gtp-channel-conf 31_256 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_MARGIN_LOW_1[2] origin:064-gtp-channel-conf 30_257 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_MARGIN_LOW_1[3] origin:064-gtp-channel-conf 31_257 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_MARGIN_LOW_1[4] origin:064-gtp-channel-conf 30_258 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_MARGIN_LOW_1[5] origin:064-gtp-channel-conf 31_258 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_MARGIN_LOW_1[6] origin:064-gtp-channel-conf 30_259 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_MARGIN_LOW_2[0] origin:064-gtp-channel-conf 30_260 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_MARGIN_LOW_2[1] origin:064-gtp-channel-conf 31_260 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_MARGIN_LOW_2[2] origin:064-gtp-channel-conf 30_261 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_MARGIN_LOW_2[3] origin:064-gtp-channel-conf 31_261 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_MARGIN_LOW_2[4] origin:064-gtp-channel-conf 30_262 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_MARGIN_LOW_2[5] origin:064-gtp-channel-conf 31_262 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_MARGIN_LOW_2[6] origin:064-gtp-channel-conf 30_263 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_MARGIN_LOW_3[0] origin:064-gtp-channel-conf 30_264 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_MARGIN_LOW_3[1] origin:064-gtp-channel-conf 31_264 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_MARGIN_LOW_3[2] origin:064-gtp-channel-conf 30_265 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_MARGIN_LOW_3[3] origin:064-gtp-channel-conf 31_265 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_MARGIN_LOW_3[4] origin:064-gtp-channel-conf 30_266 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_MARGIN_LOW_3[5] origin:064-gtp-channel-conf 31_266 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_MARGIN_LOW_3[6] origin:064-gtp-channel-conf 30_267 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_MARGIN_LOW_4[0] origin:064-gtp-channel-conf 30_268 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_MARGIN_LOW_4[1] origin:064-gtp-channel-conf 31_268 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_MARGIN_LOW_4[2] origin:064-gtp-channel-conf 30_269 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_MARGIN_LOW_4[3] origin:064-gtp-channel-conf 31_269 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_MARGIN_LOW_4[4] origin:064-gtp-channel-conf 30_270 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_MARGIN_LOW_4[5] origin:064-gtp-channel-conf 31_270 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_MARGIN_LOW_4[6] origin:064-gtp-channel-conf 30_271 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_PREDRIVER_MODE[0] origin:064-gtp-channel-conf 28_206 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_RXDETECT_CFG[0] origin:064-gtp-channel-conf 30_296 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_RXDETECT_CFG[1] origin:064-gtp-channel-conf 31_296 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_RXDETECT_CFG[2] origin:064-gtp-channel-conf 30_297 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_RXDETECT_CFG[3] origin:064-gtp-channel-conf 31_297 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_RXDETECT_CFG[4] origin:064-gtp-channel-conf 30_298 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_RXDETECT_CFG[5] origin:064-gtp-channel-conf 31_298 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_RXDETECT_CFG[6] origin:064-gtp-channel-conf 30_299 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_RXDETECT_CFG[7] origin:064-gtp-channel-conf 31_299 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_RXDETECT_CFG[8] origin:064-gtp-channel-conf 30_300 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_RXDETECT_CFG[9] origin:064-gtp-channel-conf 31_300 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_RXDETECT_CFG[10] origin:064-gtp-channel-conf 30_301 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_RXDETECT_CFG[11] origin:064-gtp-channel-conf 31_301 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_RXDETECT_CFG[12] origin:064-gtp-channel-conf 30_302 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_RXDETECT_CFG[13] origin:064-gtp-channel-conf 31_302 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_RXDETECT_REF[0] origin:064-gtp-channel-conf 30_292 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_RXDETECT_REF[1] origin:064-gtp-channel-conf 31_292 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_RXDETECT_REF[2] origin:064-gtp-channel-conf 30_293 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_XCLK_SEL.TXUSR origin:064-gtp-channel-conf 31_11 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_CLK25_DIV[0] origin:064-gtp-channel-conf 30_144 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_CLK25_DIV[1] origin:064-gtp-channel-conf 31_144 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_CLK25_DIV[2] origin:064-gtp-channel-conf 30_145 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_CLK25_DIV[3] origin:064-gtp-channel-conf 31_145 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_CLK25_DIV[4] origin:064-gtp-channel-conf 30_146 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_DEEMPH0[0] origin:064-gtp-channel-conf 30_272 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_DEEMPH0[1] origin:064-gtp-channel-conf 31_272 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_DEEMPH0[2] origin:064-gtp-channel-conf 30_273 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_DEEMPH0[3] origin:064-gtp-channel-conf 31_273 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_DEEMPH0[4] origin:064-gtp-channel-conf 30_274 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_DEEMPH0[5] origin:064-gtp-channel-conf 31_274 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_DEEMPH1[0] origin:064-gtp-channel-conf 30_276 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_DEEMPH1[1] origin:064-gtp-channel-conf 31_276 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_DEEMPH1[2] origin:064-gtp-channel-conf 30_277 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_DEEMPH1[3] origin:064-gtp-channel-conf 31_277 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_DEEMPH1[4] origin:064-gtp-channel-conf 30_278 +GTP_CHANNEL_1.GTPE2_CHANNEL.TX_DEEMPH1[5] origin:064-gtp-channel-conf 31_278 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXBUF_EN origin:064-gtp-channel-conf 28_231 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXBUF_RESET_ON_RATE_CHANGE origin:064-gtp-channel-conf 29_231 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXDLY_CFG[0] origin:064-gtp-channel-conf 30_80 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXDLY_CFG[1] origin:064-gtp-channel-conf 31_80 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXDLY_CFG[2] origin:064-gtp-channel-conf 30_81 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXDLY_CFG[3] origin:064-gtp-channel-conf 31_81 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXDLY_CFG[4] origin:064-gtp-channel-conf 30_82 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXDLY_CFG[5] origin:064-gtp-channel-conf 31_82 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXDLY_CFG[6] origin:064-gtp-channel-conf 30_83 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXDLY_CFG[7] origin:064-gtp-channel-conf 31_83 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXDLY_CFG[8] origin:064-gtp-channel-conf 30_84 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXDLY_CFG[9] origin:064-gtp-channel-conf 31_84 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXDLY_CFG[10] origin:064-gtp-channel-conf 30_85 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXDLY_CFG[11] origin:064-gtp-channel-conf 31_85 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXDLY_CFG[12] origin:064-gtp-channel-conf 30_86 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXDLY_CFG[13] origin:064-gtp-channel-conf 31_86 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXDLY_CFG[14] origin:064-gtp-channel-conf 30_87 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXDLY_CFG[15] origin:064-gtp-channel-conf 31_87 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXDLY_LCFG[0] origin:064-gtp-channel-conf 30_568 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXDLY_LCFG[1] origin:064-gtp-channel-conf 31_568 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXDLY_LCFG[2] origin:064-gtp-channel-conf 30_569 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXDLY_LCFG[3] origin:064-gtp-channel-conf 31_569 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXDLY_LCFG[4] origin:064-gtp-channel-conf 30_570 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXDLY_LCFG[5] origin:064-gtp-channel-conf 31_570 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXDLY_LCFG[6] origin:064-gtp-channel-conf 30_571 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXDLY_LCFG[7] origin:064-gtp-channel-conf 31_571 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXDLY_LCFG[8] origin:064-gtp-channel-conf 30_572 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXDLY_TAP_CFG[0] origin:064-gtp-channel-conf 30_88 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXDLY_TAP_CFG[1] origin:064-gtp-channel-conf 31_88 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXDLY_TAP_CFG[2] origin:064-gtp-channel-conf 30_89 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXDLY_TAP_CFG[3] origin:064-gtp-channel-conf 31_89 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXDLY_TAP_CFG[4] origin:064-gtp-channel-conf 30_90 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXDLY_TAP_CFG[5] origin:064-gtp-channel-conf 31_90 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXDLY_TAP_CFG[6] origin:064-gtp-channel-conf 30_91 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXDLY_TAP_CFG[7] origin:064-gtp-channel-conf 31_91 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXDLY_TAP_CFG[8] origin:064-gtp-channel-conf 30_92 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXDLY_TAP_CFG[9] origin:064-gtp-channel-conf 31_92 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXDLY_TAP_CFG[10] origin:064-gtp-channel-conf 30_93 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXDLY_TAP_CFG[11] origin:064-gtp-channel-conf 31_93 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXDLY_TAP_CFG[12] origin:064-gtp-channel-conf 30_94 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXDLY_TAP_CFG[13] origin:064-gtp-channel-conf 31_94 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXDLY_TAP_CFG[14] origin:064-gtp-channel-conf 30_95 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXDLY_TAP_CFG[15] origin:064-gtp-channel-conf 31_95 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXGEARBOX_EN origin:064-gtp-channel-conf 29_226 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXOOB_CFG[0] origin:064-gtp-channel-conf 31_20 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXOUT_DIV[0] origin:064-gtp-channel-conf 30_386 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXOUT_DIV[1] origin:064-gtp-channel-conf 31_386 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPCSRESET_TIME[0] origin:064-gtp-channel-conf 29_130 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPCSRESET_TIME[1] origin:064-gtp-channel-conf 28_131 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPCSRESET_TIME[2] origin:064-gtp-channel-conf 29_131 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPCSRESET_TIME[3] origin:064-gtp-channel-conf 28_132 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPCSRESET_TIME[4] origin:064-gtp-channel-conf 29_132 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPH_CFG[0] origin:064-gtp-channel-conf 30_96 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPH_CFG[1] origin:064-gtp-channel-conf 31_96 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPH_CFG[2] origin:064-gtp-channel-conf 30_97 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPH_CFG[3] origin:064-gtp-channel-conf 31_97 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPH_CFG[4] origin:064-gtp-channel-conf 30_98 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPH_CFG[5] origin:064-gtp-channel-conf 31_98 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPH_CFG[6] origin:064-gtp-channel-conf 30_99 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPH_CFG[7] origin:064-gtp-channel-conf 31_99 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPH_CFG[8] origin:064-gtp-channel-conf 30_100 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPH_CFG[9] origin:064-gtp-channel-conf 31_100 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPH_CFG[10] origin:064-gtp-channel-conf 30_101 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPH_CFG[11] origin:064-gtp-channel-conf 31_101 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPH_CFG[12] origin:064-gtp-channel-conf 30_102 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPH_CFG[13] origin:064-gtp-channel-conf 31_102 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPH_CFG[14] origin:064-gtp-channel-conf 30_103 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPH_CFG[15] origin:064-gtp-channel-conf 31_103 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPH_MONITOR_SEL[0] origin:064-gtp-channel-conf 30_108 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPH_MONITOR_SEL[1] origin:064-gtp-channel-conf 31_108 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPH_MONITOR_SEL[2] origin:064-gtp-channel-conf 30_109 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPH_MONITOR_SEL[3] origin:064-gtp-channel-conf 31_109 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPH_MONITOR_SEL[4] origin:064-gtp-channel-conf 30_110 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPHDLY_CFG[0] origin:064-gtp-channel-conf 30_64 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPHDLY_CFG[1] origin:064-gtp-channel-conf 31_64 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPHDLY_CFG[2] origin:064-gtp-channel-conf 30_65 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPHDLY_CFG[3] origin:064-gtp-channel-conf 31_65 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPHDLY_CFG[4] origin:064-gtp-channel-conf 30_66 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPHDLY_CFG[5] origin:064-gtp-channel-conf 31_66 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPHDLY_CFG[6] origin:064-gtp-channel-conf 30_67 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPHDLY_CFG[7] origin:064-gtp-channel-conf 31_67 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPHDLY_CFG[8] origin:064-gtp-channel-conf 30_68 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPHDLY_CFG[9] origin:064-gtp-channel-conf 31_68 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPHDLY_CFG[10] origin:064-gtp-channel-conf 30_69 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPHDLY_CFG[11] origin:064-gtp-channel-conf 31_69 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPHDLY_CFG[12] origin:064-gtp-channel-conf 30_70 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPHDLY_CFG[13] origin:064-gtp-channel-conf 31_70 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPHDLY_CFG[14] origin:064-gtp-channel-conf 30_71 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPHDLY_CFG[15] origin:064-gtp-channel-conf 31_71 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPHDLY_CFG[16] origin:064-gtp-channel-conf 30_72 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPHDLY_CFG[17] origin:064-gtp-channel-conf 31_72 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPHDLY_CFG[18] origin:064-gtp-channel-conf 30_73 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPHDLY_CFG[19] origin:064-gtp-channel-conf 31_73 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPHDLY_CFG[20] origin:064-gtp-channel-conf 30_74 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPHDLY_CFG[21] origin:064-gtp-channel-conf 31_74 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPHDLY_CFG[22] origin:064-gtp-channel-conf 30_75 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPHDLY_CFG[23] origin:064-gtp-channel-conf 31_75 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPI_GREY_SEL[0] origin:064-gtp-channel-conf 31_498 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPI_INVSTROBE_SEL[0] origin:064-gtp-channel-conf 30_498 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPI_PPM_CFG[0] origin:064-gtp-channel-conf 30_488 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPI_PPM_CFG[1] origin:064-gtp-channel-conf 31_488 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPI_PPM_CFG[2] origin:064-gtp-channel-conf 30_489 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPI_PPM_CFG[3] origin:064-gtp-channel-conf 31_489 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPI_PPM_CFG[4] origin:064-gtp-channel-conf 30_490 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPI_PPM_CFG[5] origin:064-gtp-channel-conf 31_490 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPI_PPM_CFG[6] origin:064-gtp-channel-conf 30_491 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPI_PPM_CFG[7] origin:064-gtp-channel-conf 31_491 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPI_PPMCLK_SEL.TXUSRCLK2 origin:064-gtp-channel-conf 31_497 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPI_SYNFREQ_PPM[0] origin:064-gtp-channel-conf 30_496 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPI_SYNFREQ_PPM[1] origin:064-gtp-channel-conf 31_496 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPI_SYNFREQ_PPM[2] origin:064-gtp-channel-conf 30_497 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPI_CFG0[0] origin:064-gtp-channel-conf 30_40 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPI_CFG0[1] origin:064-gtp-channel-conf 31_40 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPI_CFG1[0] origin:064-gtp-channel-conf 30_41 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPI_CFG1[1] origin:064-gtp-channel-conf 31_41 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPI_CFG2[0] origin:064-gtp-channel-conf 30_42 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPI_CFG2[1] origin:064-gtp-channel-conf 31_42 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPI_CFG3[0] origin:064-gtp-channel-conf 30_43 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPI_CFG4[0] origin:064-gtp-channel-conf 31_43 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPI_CFG5[0] origin:064-gtp-channel-conf 30_44 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPI_CFG5[1] origin:064-gtp-channel-conf 31_44 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPI_CFG5[2] origin:064-gtp-channel-conf 30_45 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPMARESET_TIME[0] origin:064-gtp-channel-conf 28_128 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPMARESET_TIME[1] origin:064-gtp-channel-conf 29_128 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPMARESET_TIME[2] origin:064-gtp-channel-conf 28_129 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPMARESET_TIME[3] origin:064-gtp-channel-conf 29_129 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXPMARESET_TIME[4] origin:064-gtp-channel-conf 28_130 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXSYNC_MULTILANE[0] origin:064-gtp-channel-conf 29_133 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXSYNC_OVRD[0] origin:064-gtp-channel-conf 28_135 +GTP_CHANNEL_1.GTPE2_CHANNEL.TXSYNC_SKIP_DA[0] origin:064-gtp-channel-conf 28_134 +GTP_CHANNEL_1.GTPE2_CHANNEL.UCODEER_CLR[0] origin:064-gtp-channel-conf 29_00 +GTP_CHANNEL_1.GTPE2_CHANNEL.USE_PCS_CLK_PHASE_SEL[0] origin:064-gtp-channel-conf 30_463 diff --git a/artix7/segbits_gtp_channel_1_mid_left.db b/artix7/segbits_gtp_channel_1_mid_left.db index d4dbd36..67ab3a2 100644 --- a/artix7/segbits_gtp_channel_1_mid_left.db +++ b/artix7/segbits_gtp_channel_1_mid_left.db @@ -1,1627 +1,1627 @@ -GTP_CHANNEL_1_MID_LEFT.GTPE2.ACJTAG_DEBUG_MODE[0] 00_07 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ACJTAG_MODE[0] 01_06 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ACJTAG_RESET[0] 01_07 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ADAPT_CFG0[0] 02_464 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ADAPT_CFG0[1] 03_464 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ADAPT_CFG0[2] 02_465 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ADAPT_CFG0[3] 03_465 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ADAPT_CFG0[4] 02_466 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ADAPT_CFG0[5] 03_466 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ADAPT_CFG0[6] 02_467 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ADAPT_CFG0[7] 03_467 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ADAPT_CFG0[8] 02_468 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ADAPT_CFG0[9] 03_468 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ADAPT_CFG0[10] 02_469 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ADAPT_CFG0[11] 03_469 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ADAPT_CFG0[12] 02_470 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ADAPT_CFG0[13] 03_470 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ADAPT_CFG0[14] 02_471 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ADAPT_CFG0[15] 03_471 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ADAPT_CFG0[16] 02_472 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ADAPT_CFG0[17] 03_472 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ADAPT_CFG0[18] 02_473 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ADAPT_CFG0[19] 03_473 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ALIGN_COMMA_DOUBLE 00_522 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ALIGN_COMMA_ENABLE[0] 00_496 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ALIGN_COMMA_ENABLE[1] 01_496 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ALIGN_COMMA_ENABLE[2] 00_497 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ALIGN_COMMA_ENABLE[3] 01_497 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ALIGN_COMMA_ENABLE[4] 00_498 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ALIGN_COMMA_ENABLE[5] 01_498 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ALIGN_COMMA_ENABLE[6] 00_499 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ALIGN_COMMA_ENABLE[7] 01_499 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ALIGN_COMMA_ENABLE[8] 00_500 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ALIGN_COMMA_ENABLE[9] 01_500 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ALIGN_COMMA_WORD[0] 01_526 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ALIGN_COMMA_WORD[1] 00_527 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ALIGN_MCOMMA_DET 00_523 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ALIGN_MCOMMA_VALUE[0] 00_504 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ALIGN_MCOMMA_VALUE[1] 01_504 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ALIGN_MCOMMA_VALUE[2] 00_505 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ALIGN_MCOMMA_VALUE[3] 01_505 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ALIGN_MCOMMA_VALUE[4] 00_506 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ALIGN_MCOMMA_VALUE[5] 01_506 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ALIGN_MCOMMA_VALUE[6] 00_507 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ALIGN_MCOMMA_VALUE[7] 01_507 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ALIGN_MCOMMA_VALUE[8] 00_508 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ALIGN_MCOMMA_VALUE[9] 01_508 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ALIGN_PCOMMA_DET 01_523 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ALIGN_PCOMMA_VALUE[0] 00_512 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ALIGN_PCOMMA_VALUE[1] 01_512 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ALIGN_PCOMMA_VALUE[2] 00_513 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ALIGN_PCOMMA_VALUE[3] 01_513 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ALIGN_PCOMMA_VALUE[4] 00_514 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ALIGN_PCOMMA_VALUE[5] 01_514 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ALIGN_PCOMMA_VALUE[6] 00_515 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ALIGN_PCOMMA_VALUE[7] 01_515 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ALIGN_PCOMMA_VALUE[8] 00_516 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ALIGN_PCOMMA_VALUE[9] 01_516 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CBCC_DATA_SOURCE_SEL.DECODED 01_661 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CFOK_CFG[0] 02_392 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CFOK_CFG[1] 03_392 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CFOK_CFG[2] 02_393 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CFOK_CFG[3] 03_393 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CFOK_CFG[4] 02_394 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CFOK_CFG[5] 03_394 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CFOK_CFG[6] 02_395 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CFOK_CFG[7] 03_395 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CFOK_CFG[8] 02_396 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CFOK_CFG[9] 03_396 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CFOK_CFG[10] 02_397 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CFOK_CFG[11] 03_397 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CFOK_CFG[12] 02_398 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CFOK_CFG[13] 03_398 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CFOK_CFG[14] 02_399 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CFOK_CFG[15] 03_399 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CFOK_CFG[16] 02_400 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CFOK_CFG[17] 03_400 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CFOK_CFG[18] 02_401 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CFOK_CFG[19] 03_401 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CFOK_CFG[20] 02_402 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CFOK_CFG[21] 03_402 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CFOK_CFG[22] 02_403 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CFOK_CFG[23] 03_403 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CFOK_CFG[24] 02_404 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CFOK_CFG[25] 03_404 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CFOK_CFG[26] 02_405 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CFOK_CFG[27] 03_405 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CFOK_CFG[28] 02_406 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CFOK_CFG[29] 03_406 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CFOK_CFG[30] 02_407 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CFOK_CFG[31] 03_407 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CFOK_CFG[32] 02_408 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CFOK_CFG[33] 03_408 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CFOK_CFG[34] 02_409 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CFOK_CFG[35] 03_409 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CFOK_CFG[36] 02_410 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CFOK_CFG[37] 03_410 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CFOK_CFG[38] 02_411 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CFOK_CFG[39] 03_411 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CFOK_CFG[40] 02_412 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CFOK_CFG[41] 03_412 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CFOK_CFG[42] 02_413 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CFOK_CFG2[0] 02_459 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CFOK_CFG2[1] 03_459 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CFOK_CFG2[2] 02_460 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CFOK_CFG2[3] 03_460 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CFOK_CFG2[4] 02_461 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CFOK_CFG2[5] 03_461 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CFOK_CFG2[6] 02_462 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CFOK_CFG3[0] 02_416 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CFOK_CFG3[1] 03_416 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CFOK_CFG3[2] 02_417 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CFOK_CFG3[3] 03_417 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CFOK_CFG3[4] 02_418 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CFOK_CFG3[5] 03_418 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CFOK_CFG3[6] 02_419 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CFOK_CFG4[0] 03_438 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CFOK_CFG5[0] 02_429 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CFOK_CFG5[1] 03_429 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CFOK_CFG6[0] 03_436 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CFOK_CFG6[1] 02_437 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CFOK_CFG6[2] 03_437 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CFOK_CFG6[3] 02_438 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_KEEP_ALIGN 01_631 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_MAX_SKEW[0] 00_670 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_MAX_SKEW[1] 01_670 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_MAX_SKEW[2] 00_671 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_MAX_SKEW[3] 01_671 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_1[0] 00_608 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_1[1] 01_608 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_1[2] 00_609 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_1[3] 01_609 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_1[4] 00_610 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_1[5] 01_610 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_1[6] 00_611 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_1[7] 01_611 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_1[8] 00_612 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_1[9] 01_612 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_2[0] 00_616 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_2[1] 01_616 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_2[2] 00_617 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_2[3] 01_617 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_2[4] 00_618 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_2[5] 01_618 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_2[6] 00_619 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_2[7] 01_619 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_2[8] 00_620 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_2[9] 01_620 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_3[0] 00_624 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_3[1] 01_624 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_3[2] 00_625 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_3[3] 01_625 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_3[4] 00_626 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_3[5] 01_626 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_3[6] 00_627 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_3[7] 01_627 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_3[8] 00_628 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_3[9] 01_628 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_4[0] 00_632 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_4[1] 01_632 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_4[2] 00_633 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_4[3] 01_633 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_4[4] 00_634 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_4[5] 01_634 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_4[6] 00_635 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_4[7] 01_635 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_4[8] 00_636 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_4[9] 01_636 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_ENABLE[0] 00_614 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_ENABLE[1] 01_614 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_ENABLE[2] 00_615 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_ENABLE[3] 01_615 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_1[0] 00_640 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_1[1] 01_640 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_1[2] 00_641 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_1[3] 01_641 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_1[4] 00_642 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_1[5] 01_642 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_1[6] 00_643 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_1[7] 01_643 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_1[8] 00_644 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_1[9] 01_644 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_2[0] 00_648 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_2[1] 01_648 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_2[2] 00_649 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_2[3] 01_649 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_2[4] 00_650 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_2[5] 01_650 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_2[6] 00_651 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_2[7] 01_651 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_2[8] 00_652 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_2[9] 01_652 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_3[0] 00_656 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_3[1] 01_656 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_3[2] 00_657 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_3[3] 01_657 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_3[4] 00_658 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_3[5] 01_658 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_3[6] 00_659 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_3[7] 01_659 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_3[8] 00_660 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_3[9] 01_660 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_4[0] 00_664 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_4[1] 01_664 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_4[2] 00_665 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_4[3] 01_665 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_4[4] 00_666 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_4[5] 01_666 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_4[6] 00_667 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_4[7] 01_667 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_4[8] 00_668 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_4[9] 01_668 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_ENABLE[0] 00_646 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_ENABLE[1] 01_646 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_ENABLE[2] 00_647 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_ENABLE[3] 01_647 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_USE 01_645 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_LEN[0] 00_623 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_LEN[1] 01_623 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COMMON_SWING[0] 03_311 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_KEEP_IDLE 00_591 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_MAX_LAT[0] 00_557 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_MAX_LAT[1] 01_557 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_MAX_LAT[2] 00_558 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_MAX_LAT[3] 01_558 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_MAX_LAT[4] 00_559 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_MAX_LAT[5] 01_559 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_MIN_LAT[0] 00_565 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_MIN_LAT[1] 01_565 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_MIN_LAT[2] 00_566 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_MIN_LAT[3] 01_566 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_MIN_LAT[4] 00_567 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_MIN_LAT[5] 01_567 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_PRECEDENCE 00_590 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_REPEAT_WAIT[0] 00_573 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_REPEAT_WAIT[1] 01_573 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_REPEAT_WAIT[2] 00_574 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_REPEAT_WAIT[3] 01_574 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_REPEAT_WAIT[4] 00_575 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_1_1[0] 00_544 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_1_1[1] 01_544 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_1_1[2] 00_545 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_1_1[3] 01_545 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_1_1[4] 00_546 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_1_1[5] 01_546 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_1_1[6] 00_547 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_1_1[7] 01_547 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_1_1[8] 00_548 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_1_1[9] 01_548 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_1_2[0] 00_552 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_1_2[1] 01_552 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_1_2[2] 00_553 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_1_2[3] 01_553 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_1_2[4] 00_554 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_1_2[5] 01_554 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_1_2[6] 00_555 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_1_2[7] 01_555 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_1_2[8] 00_556 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_1_2[9] 01_556 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_1_3[0] 00_560 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_1_3[1] 01_560 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_1_3[2] 00_561 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_1_3[3] 01_561 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_1_3[4] 00_562 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_1_3[5] 01_562 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_1_3[6] 00_563 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_1_3[7] 01_563 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_1_3[8] 00_564 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_1_3[9] 01_564 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_1_4[0] 00_568 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_1_4[1] 01_568 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_1_4[2] 00_569 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_1_4[3] 01_569 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_1_4[4] 00_570 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_1_4[5] 01_570 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_1_4[6] 00_571 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_1_4[7] 01_571 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_1_4[8] 00_572 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_1_4[9] 01_572 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_1_ENABLE[0] 00_549 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_1_ENABLE[1] 01_549 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_1_ENABLE[2] 00_550 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_1_ENABLE[3] 01_550 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_2_1[0] 00_576 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_2_1[1] 01_576 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_2_1[2] 00_577 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_2_1[3] 01_577 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_2_1[4] 00_578 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_2_1[5] 01_578 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_2_1[6] 00_579 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_2_1[7] 01_579 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_2_1[8] 00_580 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_2_1[9] 01_580 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_2_2[0] 00_584 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_2_2[1] 01_584 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_2_2[2] 00_585 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_2_2[3] 01_585 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_2_2[4] 00_586 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_2_2[5] 01_586 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_2_2[6] 00_587 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_2_2[7] 01_587 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_2_2[8] 00_588 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_2_2[9] 01_588 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_2_3[0] 00_592 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_2_3[1] 01_592 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_2_3[2] 00_593 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_2_3[3] 01_593 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_2_3[4] 00_594 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_2_3[5] 01_594 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_2_3[6] 00_595 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_2_3[7] 01_595 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_2_3[8] 00_596 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_2_3[9] 01_596 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_2_4[0] 00_600 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_2_4[1] 01_600 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_2_4[2] 00_601 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_2_4[3] 01_601 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_2_4[4] 00_602 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_2_4[5] 01_602 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_2_4[6] 00_603 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_2_4[7] 01_603 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_2_4[8] 00_604 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_2_4[9] 01_604 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_2_ENABLE[0] 00_581 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_2_ENABLE[1] 01_581 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_2_ENABLE[2] 00_582 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_2_ENABLE[3] 01_582 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_2_USE 00_583 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_LEN[0] 00_589 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_LEN[1] 01_589 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_CORRECT_USE 00_551 -GTP_CHANNEL_1_MID_LEFT.GTPE2.DEC_MCOMMA_DETECT 01_494 -GTP_CHANNEL_1_MID_LEFT.GTPE2.DEC_PCOMMA_DETECT 00_495 -GTP_CHANNEL_1_MID_LEFT.GTPE2.DEC_VALID_COMMA_ONLY 00_494 -GTP_CHANNEL_1_MID_LEFT.GTPE2.DMONITOR_CFG[0] 02_368 -GTP_CHANNEL_1_MID_LEFT.GTPE2.DMONITOR_CFG[1] 03_368 -GTP_CHANNEL_1_MID_LEFT.GTPE2.DMONITOR_CFG[2] 02_369 -GTP_CHANNEL_1_MID_LEFT.GTPE2.DMONITOR_CFG[3] 03_369 -GTP_CHANNEL_1_MID_LEFT.GTPE2.DMONITOR_CFG[4] 02_370 -GTP_CHANNEL_1_MID_LEFT.GTPE2.DMONITOR_CFG[5] 03_370 -GTP_CHANNEL_1_MID_LEFT.GTPE2.DMONITOR_CFG[6] 02_371 -GTP_CHANNEL_1_MID_LEFT.GTPE2.DMONITOR_CFG[7] 03_371 -GTP_CHANNEL_1_MID_LEFT.GTPE2.DMONITOR_CFG[8] 02_372 -GTP_CHANNEL_1_MID_LEFT.GTPE2.DMONITOR_CFG[9] 03_372 -GTP_CHANNEL_1_MID_LEFT.GTPE2.DMONITOR_CFG[10] 02_373 -GTP_CHANNEL_1_MID_LEFT.GTPE2.DMONITOR_CFG[11] 03_373 -GTP_CHANNEL_1_MID_LEFT.GTPE2.DMONITOR_CFG[12] 02_374 -GTP_CHANNEL_1_MID_LEFT.GTPE2.DMONITOR_CFG[13] 03_374 -GTP_CHANNEL_1_MID_LEFT.GTPE2.DMONITOR_CFG[14] 02_375 -GTP_CHANNEL_1_MID_LEFT.GTPE2.DMONITOR_CFG[15] 03_375 -GTP_CHANNEL_1_MID_LEFT.GTPE2.DMONITOR_CFG[16] 02_376 -GTP_CHANNEL_1_MID_LEFT.GTPE2.DMONITOR_CFG[17] 03_376 -GTP_CHANNEL_1_MID_LEFT.GTPE2.DMONITOR_CFG[18] 02_377 -GTP_CHANNEL_1_MID_LEFT.GTPE2.DMONITOR_CFG[19] 03_377 -GTP_CHANNEL_1_MID_LEFT.GTPE2.DMONITOR_CFG[20] 02_378 -GTP_CHANNEL_1_MID_LEFT.GTPE2.DMONITOR_CFG[21] 03_378 -GTP_CHANNEL_1_MID_LEFT.GTPE2.DMONITOR_CFG[22] 02_379 -GTP_CHANNEL_1_MID_LEFT.GTPE2.DMONITOR_CFG[23] 03_379 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_CLK_PHASE_SEL[0] 03_463 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_CONTROL[0] 00_488 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_CONTROL[1] 01_488 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_CONTROL[2] 00_489 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_CONTROL[3] 01_489 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_CONTROL[4] 00_490 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_CONTROL[5] 01_490 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_ERRDET_EN 01_492 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_EYE_SCAN_EN 00_492 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_HORZ_OFFSET[0] 00_480 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_HORZ_OFFSET[1] 01_480 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_HORZ_OFFSET[2] 00_481 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_HORZ_OFFSET[3] 01_481 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_HORZ_OFFSET[4] 00_482 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_HORZ_OFFSET[5] 01_482 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_HORZ_OFFSET[6] 00_483 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_HORZ_OFFSET[7] 01_483 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_HORZ_OFFSET[8] 00_484 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_HORZ_OFFSET[9] 01_484 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_HORZ_OFFSET[10] 00_485 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_HORZ_OFFSET[11] 01_485 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_PMA_CFG[0] 02_624 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_PMA_CFG[1] 03_624 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_PMA_CFG[2] 02_625 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_PMA_CFG[3] 03_625 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_PMA_CFG[4] 02_626 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_PMA_CFG[5] 03_626 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_PMA_CFG[6] 02_627 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_PMA_CFG[7] 03_627 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_PMA_CFG[8] 02_628 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_PMA_CFG[9] 03_628 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_PRESCALE[0] 01_477 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_PRESCALE[1] 00_478 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_PRESCALE[2] 01_478 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_PRESCALE[3] 00_479 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_PRESCALE[4] 01_479 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[0] 00_392 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[1] 01_392 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[2] 00_393 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[3] 01_393 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[4] 00_394 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[5] 01_394 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[6] 00_395 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[7] 01_395 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[8] 00_396 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[9] 01_396 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[10] 00_397 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[11] 01_397 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[12] 00_398 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[13] 01_398 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[14] 00_399 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[15] 01_399 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[16] 00_400 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[17] 01_400 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[18] 00_401 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[19] 01_401 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[20] 00_402 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[21] 01_402 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[22] 00_403 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[23] 01_403 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[24] 00_404 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[25] 01_404 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[26] 00_405 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[27] 01_405 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[28] 00_406 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[29] 01_406 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[30] 00_407 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[31] 01_407 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[32] 00_408 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[33] 01_408 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[34] 00_409 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[35] 01_409 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[36] 00_410 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[37] 01_410 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[38] 00_411 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[39] 01_411 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[40] 00_412 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[41] 01_412 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[42] 00_413 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[43] 01_413 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[44] 00_414 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[45] 01_414 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[46] 00_415 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[47] 01_415 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[48] 00_416 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[49] 01_416 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[50] 00_417 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[51] 01_417 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[52] 00_418 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[53] 01_418 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[54] 00_419 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[55] 01_419 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[56] 00_420 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[57] 01_420 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[58] 00_421 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[59] 01_421 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[60] 00_422 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[61] 01_422 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[62] 00_423 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[63] 01_423 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[64] 00_424 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[65] 01_424 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[66] 00_425 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[67] 01_425 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[68] 00_426 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[69] 01_426 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[70] 00_427 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[71] 01_427 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[72] 00_428 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[73] 01_428 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[74] 00_429 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[75] 01_429 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[76] 00_430 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[77] 01_430 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[78] 00_431 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[79] 01_431 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[0] 00_352 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[1] 01_352 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[2] 00_353 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[3] 01_353 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[4] 00_354 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[5] 01_354 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[6] 00_355 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[7] 01_355 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[8] 00_356 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[9] 01_356 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[10] 00_357 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[11] 01_357 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[12] 00_358 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[13] 01_358 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[14] 00_359 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[15] 01_359 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[16] 00_360 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[17] 01_360 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[18] 00_361 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[19] 01_361 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[20] 00_362 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[21] 01_362 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[22] 00_363 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[23] 01_363 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[24] 00_364 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[25] 01_364 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[26] 00_365 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[27] 01_365 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[28] 00_366 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[29] 01_366 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[30] 00_367 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[31] 01_367 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[32] 00_368 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[33] 01_368 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[34] 00_369 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[35] 01_369 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[36] 00_370 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[37] 01_370 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[38] 00_371 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[39] 01_371 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[40] 00_372 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[41] 01_372 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[42] 00_373 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[43] 01_373 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[44] 00_374 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[45] 01_374 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[46] 00_375 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[47] 01_375 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[48] 00_376 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[49] 01_376 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[50] 00_377 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[51] 01_377 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[52] 00_378 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[53] 01_378 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[54] 00_379 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[55] 01_379 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[56] 00_380 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[57] 01_380 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[58] 00_381 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[59] 01_381 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[60] 00_382 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[61] 01_382 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[62] 00_383 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[63] 01_383 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[64] 00_384 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[65] 01_384 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[66] 00_385 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[67] 01_385 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[68] 00_386 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[69] 01_386 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[70] 00_387 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[71] 01_387 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[72] 00_388 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[73] 01_388 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[74] 00_389 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[75] 01_389 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[76] 00_390 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[77] 01_390 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[78] 00_391 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[79] 01_391 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[0] 00_432 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[1] 01_432 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[2] 00_433 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[3] 01_433 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[4] 00_434 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[5] 01_434 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[6] 00_435 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[7] 01_435 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[8] 00_436 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[9] 01_436 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[10] 00_437 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[11] 01_437 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[12] 00_438 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[13] 01_438 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[14] 00_439 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[15] 01_439 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[16] 00_440 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[17] 01_440 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[18] 00_441 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[19] 01_441 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[20] 00_442 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[21] 01_442 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[22] 00_443 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[23] 01_443 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[24] 00_444 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[25] 01_444 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[26] 00_445 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[27] 01_445 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[28] 00_446 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[29] 01_446 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[30] 00_447 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[31] 01_447 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[32] 00_448 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[33] 01_448 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[34] 00_449 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[35] 01_449 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[36] 00_450 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[37] 01_450 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[38] 00_451 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[39] 01_451 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[40] 00_452 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[41] 01_452 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[42] 00_453 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[43] 01_453 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[44] 00_454 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[45] 01_454 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[46] 00_455 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[47] 01_455 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[48] 00_456 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[49] 01_456 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[50] 00_457 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[51] 01_457 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[52] 00_458 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[53] 01_458 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[54] 00_459 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[55] 01_459 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[56] 00_460 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[57] 01_460 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[58] 00_461 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[59] 01_461 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[60] 00_462 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[61] 01_462 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[62] 00_463 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[63] 01_463 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[64] 00_464 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[65] 01_464 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[66] 00_465 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[67] 01_465 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[68] 00_466 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[69] 01_466 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[70] 00_467 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[71] 01_467 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[72] 00_468 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[73] 01_468 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[74] 00_469 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[75] 01_469 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[76] 00_470 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[77] 01_470 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[78] 00_471 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[79] 01_471 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_VERT_OFFSET[0] 00_472 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_VERT_OFFSET[1] 01_472 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_VERT_OFFSET[2] 00_473 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_VERT_OFFSET[3] 01_473 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_VERT_OFFSET[4] 00_474 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_VERT_OFFSET[5] 01_474 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_VERT_OFFSET[6] 00_475 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_VERT_OFFSET[7] 01_475 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_VERT_OFFSET[8] 00_476 -GTP_CHANNEL_1_MID_LEFT.GTPE2.FTS_DESKEW_SEQ_ENABLE[0] 00_662 -GTP_CHANNEL_1_MID_LEFT.GTPE2.FTS_DESKEW_SEQ_ENABLE[1] 01_662 -GTP_CHANNEL_1_MID_LEFT.GTPE2.FTS_DESKEW_SEQ_ENABLE[2] 00_663 -GTP_CHANNEL_1_MID_LEFT.GTPE2.FTS_DESKEW_SEQ_ENABLE[3] 01_663 -GTP_CHANNEL_1_MID_LEFT.GTPE2.FTS_LANE_DESKEW_CFG[0] 00_654 -GTP_CHANNEL_1_MID_LEFT.GTPE2.FTS_LANE_DESKEW_CFG[1] 01_654 -GTP_CHANNEL_1_MID_LEFT.GTPE2.FTS_LANE_DESKEW_CFG[2] 00_655 -GTP_CHANNEL_1_MID_LEFT.GTPE2.FTS_LANE_DESKEW_CFG[3] 01_655 -GTP_CHANNEL_1_MID_LEFT.GTPE2.FTS_LANE_DESKEW_EN 01_653 -GTP_CHANNEL_1_MID_LEFT.GTPE2.GEARBOX_MODE[0] 00_224 -GTP_CHANNEL_1_MID_LEFT.GTPE2.GEARBOX_MODE[1] 01_224 -GTP_CHANNEL_1_MID_LEFT.GTPE2.GEARBOX_MODE[2] 00_225 -GTP_CHANNEL_1_MID_LEFT.GTPE2.IN_USE 00_00 00_01 00_47 00_52 00_53 00_65 01_01 01_47 02_129 -GTP_CHANNEL_1_MID_LEFT.GTPE2.LOOPBACK_CFG[0] 02_20 -GTP_CHANNEL_1_MID_LEFT.GTPE2.OUTREFCLK_SEL_INV[0] 00_149 -GTP_CHANNEL_1_MID_LEFT.GTPE2.OUTREFCLK_SEL_INV[1] 01_149 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PCS_PCIE_EN 00_216 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PCS_RSVD_ATTR[0] 02_184 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PCS_RSVD_ATTR[1] 03_184 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PCS_RSVD_ATTR[2] 02_185 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PCS_RSVD_ATTR[3] 03_185 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PCS_RSVD_ATTR[4] 02_186 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PCS_RSVD_ATTR[5] 03_186 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PCS_RSVD_ATTR[6] 02_187 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PCS_RSVD_ATTR[7] 03_187 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PCS_RSVD_ATTR[8] 02_188 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PCS_RSVD_ATTR[9] 03_188 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PCS_RSVD_ATTR[10] 02_189 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PCS_RSVD_ATTR[11] 03_189 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PCS_RSVD_ATTR[12] 02_190 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PCS_RSVD_ATTR[13] 03_190 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PCS_RSVD_ATTR[14] 02_191 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PCS_RSVD_ATTR[15] 03_191 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PCS_RSVD_ATTR[16] 02_192 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PCS_RSVD_ATTR[17] 03_192 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PCS_RSVD_ATTR[18] 02_193 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PCS_RSVD_ATTR[19] 03_193 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PCS_RSVD_ATTR[20] 02_194 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PCS_RSVD_ATTR[21] 03_194 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PCS_RSVD_ATTR[22] 02_195 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PCS_RSVD_ATTR[23] 03_195 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PCS_RSVD_ATTR[24] 02_196 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PCS_RSVD_ATTR[25] 03_196 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PCS_RSVD_ATTR[26] 02_197 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PCS_RSVD_ATTR[27] 03_197 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PCS_RSVD_ATTR[28] 02_198 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PCS_RSVD_ATTR[29] 03_198 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PCS_RSVD_ATTR[30] 02_199 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PCS_RSVD_ATTR[31] 03_199 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PCS_RSVD_ATTR[32] 02_200 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PCS_RSVD_ATTR[33] 03_200 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PCS_RSVD_ATTR[34] 02_201 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PCS_RSVD_ATTR[35] 03_201 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PCS_RSVD_ATTR[36] 02_202 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PCS_RSVD_ATTR[37] 03_202 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PCS_RSVD_ATTR[38] 02_203 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PCS_RSVD_ATTR[39] 03_203 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PCS_RSVD_ATTR[40] 02_204 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PCS_RSVD_ATTR[41] 03_204 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PCS_RSVD_ATTR[42] 02_205 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PCS_RSVD_ATTR[43] 03_205 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PCS_RSVD_ATTR[44] 02_206 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PCS_RSVD_ATTR[45] 03_206 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PCS_RSVD_ATTR[46] 02_207 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PCS_RSVD_ATTR[47] 03_207 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PD_TRANS_TIME_FROM_P2[0] 01_216 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PD_TRANS_TIME_FROM_P2[1] 00_217 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PD_TRANS_TIME_FROM_P2[2] 01_217 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PD_TRANS_TIME_FROM_P2[3] 00_218 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PD_TRANS_TIME_FROM_P2[4] 01_218 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PD_TRANS_TIME_FROM_P2[5] 00_219 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PD_TRANS_TIME_FROM_P2[6] 01_219 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PD_TRANS_TIME_FROM_P2[7] 00_220 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PD_TRANS_TIME_FROM_P2[8] 01_220 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PD_TRANS_TIME_FROM_P2[9] 00_221 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PD_TRANS_TIME_FROM_P2[10] 01_221 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PD_TRANS_TIME_FROM_P2[11] 00_222 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PD_TRANS_TIME_NONE_P2[0] 00_208 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PD_TRANS_TIME_NONE_P2[1] 01_208 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PD_TRANS_TIME_NONE_P2[2] 00_209 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PD_TRANS_TIME_NONE_P2[3] 01_209 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PD_TRANS_TIME_NONE_P2[4] 00_210 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PD_TRANS_TIME_NONE_P2[5] 01_210 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PD_TRANS_TIME_NONE_P2[6] 00_211 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PD_TRANS_TIME_NONE_P2[7] 01_211 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PD_TRANS_TIME_TO_P2[0] 00_212 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PD_TRANS_TIME_TO_P2[1] 01_212 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PD_TRANS_TIME_TO_P2[2] 00_213 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PD_TRANS_TIME_TO_P2[3] 01_213 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PD_TRANS_TIME_TO_P2[4] 00_214 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PD_TRANS_TIME_TO_P2[5] 01_214 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PD_TRANS_TIME_TO_P2[6] 00_215 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PD_TRANS_TIME_TO_P2[7] 01_215 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PMA_LOOPBACK_CFG[0] 01_207 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PMA_RSV[0] 02_520 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PMA_RSV[1] 03_520 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PMA_RSV[2] 02_521 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PMA_RSV[3] 03_521 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PMA_RSV[4] 02_522 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PMA_RSV[5] 03_522 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PMA_RSV[6] 02_523 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PMA_RSV[7] 03_523 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PMA_RSV[8] 02_524 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PMA_RSV[9] 03_524 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PMA_RSV[10] 02_525 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PMA_RSV[11] 03_525 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PMA_RSV[12] 02_526 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PMA_RSV[13] 03_526 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PMA_RSV[14] 02_527 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PMA_RSV[15] 03_527 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PMA_RSV[16] 02_528 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PMA_RSV[17] 03_528 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PMA_RSV[18] 02_529 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PMA_RSV[19] 03_529 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PMA_RSV[20] 02_530 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PMA_RSV[21] 03_530 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PMA_RSV[22] 02_531 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PMA_RSV[23] 03_531 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PMA_RSV[24] 02_532 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PMA_RSV[25] 03_532 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PMA_RSV[26] 02_533 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PMA_RSV[27] 03_533 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PMA_RSV[28] 02_534 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PMA_RSV[29] 03_534 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PMA_RSV[30] 02_535 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PMA_RSV[31] 03_535 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PMA_RSV2[0] 02_336 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PMA_RSV2[1] 03_336 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PMA_RSV2[2] 02_337 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PMA_RSV2[3] 03_337 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PMA_RSV2[4] 02_338 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PMA_RSV2[5] 03_338 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PMA_RSV2[6] 02_339 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PMA_RSV2[7] 03_339 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PMA_RSV2[8] 02_340 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PMA_RSV2[9] 03_340 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PMA_RSV2[10] 02_341 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PMA_RSV2[11] 03_341 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PMA_RSV2[12] 02_342 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PMA_RSV2[13] 03_342 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PMA_RSV2[14] 02_343 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PMA_RSV2[15] 03_343 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PMA_RSV2[16] 02_344 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PMA_RSV2[17] 03_344 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PMA_RSV2[18] 02_345 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PMA_RSV2[19] 03_345 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PMA_RSV2[20] 02_346 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PMA_RSV2[21] 03_346 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PMA_RSV2[22] 02_347 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PMA_RSV2[23] 03_347 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PMA_RSV2[24] 02_348 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PMA_RSV2[25] 03_348 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PMA_RSV2[26] 02_349 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PMA_RSV2[27] 03_349 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PMA_RSV2[28] 02_350 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PMA_RSV2[29] 03_350 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PMA_RSV2[30] 02_351 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PMA_RSV2[31] 03_351 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PMA_RSV3[0] 02_288 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PMA_RSV3[1] 03_288 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PMA_RSV4[0] 02_156 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PMA_RSV4[1] 03_156 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PMA_RSV4[2] 02_157 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PMA_RSV4[3] 03_157 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PMA_RSV5[0] 03_159 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PMA_RSV6[0] 02_303 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PMA_RSV7[0] 03_303 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_BIAS_CFG[0] 02_112 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_BIAS_CFG[1] 03_112 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_BIAS_CFG[2] 02_113 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_BIAS_CFG[3] 03_113 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_BIAS_CFG[4] 02_114 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_BIAS_CFG[5] 03_114 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_BIAS_CFG[6] 02_115 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_BIAS_CFG[7] 03_115 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_BIAS_CFG[8] 02_116 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_BIAS_CFG[9] 03_116 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_BIAS_CFG[10] 02_117 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_BIAS_CFG[11] 03_117 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_BIAS_CFG[12] 02_118 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_BIAS_CFG[13] 03_118 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_BIAS_CFG[14] 02_119 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_BIAS_CFG[15] 03_119 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_BUFFER_CFG[0] 02_536 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_BUFFER_CFG[1] 03_536 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_BUFFER_CFG[2] 02_537 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_BUFFER_CFG[3] 03_537 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_BUFFER_CFG[4] 02_538 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_BUFFER_CFG[5] 03_538 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_CLKMUX_EN[0] 02_128 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_CM_SEL[0] 00_138 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_CM_SEL[1] 01_138 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_CM_TRIM[0] 02_304 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_CM_TRIM[1] 03_304 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_CM_TRIM[2] 02_305 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_CM_TRIM[3] 03_305 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_DATA_WIDTH[0] 01_141 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_DATA_WIDTH[1] 00_142 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_DATA_WIDTH[2] 01_142 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_DDI_SEL[0] 00_696 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_DDI_SEL[1] 01_696 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_DDI_SEL[2] 00_697 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_DDI_SEL[3] 01_697 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_DDI_SEL[4] 00_698 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_DDI_SEL[5] 01_698 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_DEBUG_CFG[0] 02_616 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_DEBUG_CFG[1] 03_616 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_DEBUG_CFG[2] 02_617 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_DEBUG_CFG[3] 03_617 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_DEBUG_CFG[4] 02_618 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_DEBUG_CFG[5] 03_618 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_DEBUG_CFG[6] 02_619 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_DEBUG_CFG[7] 03_619 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_DEBUG_CFG[8] 02_620 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_DEBUG_CFG[9] 03_620 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_DEBUG_CFG[10] 02_621 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_DEBUG_CFG[11] 03_621 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_DEBUG_CFG[12] 02_622 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_DEBUG_CFG[13] 03_622 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_DEFER_RESET_BUF_EN 02_552 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_DISPERR_SEQ_MATCH 01_495 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_OS_CFG[0] 00_288 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_OS_CFG[1] 01_288 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_OS_CFG[2] 00_289 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_OS_CFG[3] 01_289 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_OS_CFG[4] 00_290 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_OS_CFG[5] 01_290 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_OS_CFG[6] 00_291 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_OS_CFG[7] 01_291 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_OS_CFG[8] 00_292 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_OS_CFG[9] 01_292 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_OS_CFG[10] 00_293 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_OS_CFG[11] 01_293 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_OS_CFG[12] 00_294 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_SIG_VALID_DLY[0] 00_524 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_SIG_VALID_DLY[1] 01_524 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_SIG_VALID_DLY[2] 00_525 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_SIG_VALID_DLY[3] 01_525 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_SIG_VALID_DLY[4] 00_526 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_XCLK_SEL.RXUSR 00_143 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_CLK25_DIV[0] 00_139 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_CLK25_DIV[1] 01_139 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_CLK25_DIV[2] 00_140 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_CLK25_DIV[3] 01_140 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_CLK25_DIV[4] 00_141 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXBUF_ADDR_MODE.FAST 03_555 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXBUF_EIDLE_HI_CNT[0] 02_558 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXBUF_EIDLE_HI_CNT[1] 03_558 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXBUF_EIDLE_HI_CNT[2] 02_559 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXBUF_EIDLE_HI_CNT[3] 03_559 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXBUF_EIDLE_LO_CNT[0] 02_556 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXBUF_EIDLE_LO_CNT[1] 03_556 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXBUF_EIDLE_LO_CNT[2] 02_557 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXBUF_EIDLE_LO_CNT[3] 03_557 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXBUF_EN 02_11 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXBUF_RESET_ON_CB_CHANGE 02_560 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXBUF_RESET_ON_COMMAALIGN 02_561 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXBUF_RESET_ON_EIDLE 02_547 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXBUF_RESET_ON_RATE_CHANGE 03_560 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXBUF_THRESH_OVFLW[0] 03_552 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXBUF_THRESH_OVFLW[1] 02_553 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXBUF_THRESH_OVFLW[2] 03_553 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXBUF_THRESH_OVFLW[3] 02_554 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXBUF_THRESH_OVFLW[4] 03_554 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXBUF_THRESH_OVFLW[5] 02_555 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXBUF_THRESH_OVRD 02_548 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXBUF_THRESH_UNDFLW[0] 02_544 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXBUF_THRESH_UNDFLW[1] 03_544 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXBUF_THRESH_UNDFLW[2] 02_545 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXBUF_THRESH_UNDFLW[3] 03_545 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXBUF_THRESH_UNDFLW[4] 02_546 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXBUF_THRESH_UNDFLW[5] 03_546 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXBUFRESET_TIME[0] 01_101 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXBUFRESET_TIME[1] 00_102 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXBUFRESET_TIME[2] 01_102 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXBUFRESET_TIME[3] 00_103 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXBUFRESET_TIME[4] 01_103 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[0] 02_640 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[1] 03_640 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[2] 02_641 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[3] 03_641 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[4] 02_642 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[5] 03_642 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[6] 02_643 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[7] 03_643 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[8] 02_644 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[9] 03_644 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[10] 02_645 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[11] 03_645 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[12] 02_646 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[13] 03_646 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[14] 02_647 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[15] 03_647 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[16] 02_648 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[17] 03_648 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[18] 02_649 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[19] 03_649 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[20] 02_650 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[21] 03_650 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[22] 02_651 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[23] 03_651 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[24] 02_652 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[25] 03_652 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[26] 02_653 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[27] 03_653 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[28] 02_654 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[29] 03_654 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[30] 02_655 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[31] 03_655 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[32] 02_656 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[33] 03_656 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[34] 02_657 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[35] 03_657 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[36] 02_658 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[37] 03_658 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[38] 02_659 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[39] 03_659 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[40] 02_660 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[41] 03_660 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[42] 02_661 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[43] 03_661 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[44] 02_662 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[45] 03_662 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[46] 02_663 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[47] 03_663 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[48] 02_664 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[49] 03_664 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[50] 02_665 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[51] 03_665 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[52] 02_666 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[53] 03_666 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[54] 02_667 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[55] 03_667 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[56] 02_668 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[57] 03_668 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[58] 02_669 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[59] 03_669 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[60] 02_670 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[61] 03_670 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[62] 02_671 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[63] 03_671 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[64] 02_672 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[65] 03_672 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[66] 02_673 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[67] 03_673 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[68] 02_674 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[69] 03_674 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[70] 02_675 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[71] 03_675 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[72] 02_676 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[73] 03_676 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[74] 02_677 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[75] 03_677 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[76] 02_678 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[77] 03_678 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[78] 02_679 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[79] 03_679 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[80] 02_680 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[81] 03_680 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[82] 02_681 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_FR_RESET_ON_EIDLE[0] 02_638 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_HOLD_DURING_EIDLE[0] 03_637 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_LOCK_CFG[0] 02_632 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_LOCK_CFG[1] 03_632 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_LOCK_CFG[2] 02_633 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_LOCK_CFG[3] 03_633 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_LOCK_CFG[4] 02_634 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_LOCK_CFG[5] 03_634 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_PH_RESET_ON_EIDLE[0] 03_638 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDRFREQRESET_TIME[0] 01_106 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDRFREQRESET_TIME[1] 00_107 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDRFREQRESET_TIME[2] 01_107 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDRFREQRESET_TIME[3] 00_108 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDRFREQRESET_TIME[4] 01_108 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDRPHRESET_TIME[0] 00_109 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDRPHRESET_TIME[1] 01_109 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDRPHRESET_TIME[2] 00_110 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDRPHRESET_TIME[3] 01_110 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDRPHRESET_TIME[4] 00_111 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXDLY_CFG[0] 00_680 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXDLY_CFG[1] 01_680 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXDLY_CFG[2] 00_681 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXDLY_CFG[3] 01_681 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXDLY_CFG[4] 00_682 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXDLY_CFG[5] 01_682 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXDLY_CFG[6] 00_683 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXDLY_CFG[7] 01_683 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXDLY_CFG[8] 00_684 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXDLY_CFG[9] 01_684 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXDLY_CFG[10] 00_685 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXDLY_CFG[11] 01_685 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXDLY_CFG[12] 00_686 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXDLY_CFG[13] 01_686 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXDLY_CFG[14] 00_687 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXDLY_CFG[15] 01_687 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXDLY_LCFG[0] 02_576 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXDLY_LCFG[1] 03_576 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXDLY_LCFG[2] 02_577 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXDLY_LCFG[3] 03_577 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXDLY_LCFG[4] 02_578 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXDLY_LCFG[5] 03_578 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXDLY_LCFG[6] 02_579 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXDLY_LCFG[7] 03_579 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXDLY_LCFG[8] 02_580 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXDLY_TAP_CFG[0] 00_672 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXDLY_TAP_CFG[1] 01_672 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXDLY_TAP_CFG[2] 00_673 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXDLY_TAP_CFG[3] 01_673 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXDLY_TAP_CFG[4] 00_674 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXDLY_TAP_CFG[5] 01_674 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXDLY_TAP_CFG[6] 00_675 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXDLY_TAP_CFG[7] 01_675 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXDLY_TAP_CFG[8] 00_676 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXDLY_TAP_CFG[9] 01_676 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXDLY_TAP_CFG[10] 00_677 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXDLY_TAP_CFG[11] 01_677 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXDLY_TAP_CFG[12] 00_678 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXDLY_TAP_CFG[13] 01_678 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXDLY_TAP_CFG[14] 00_679 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXDLY_TAP_CFG[15] 01_679 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXGEARBOX_EN 01_607 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXISCANRESET_TIME[0] 01_123 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXISCANRESET_TIME[1] 00_124 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXISCANRESET_TIME[2] 01_124 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXISCANRESET_TIME[3] 00_125 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXISCANRESET_TIME[4] 01_125 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPM_BIAS_STARTUP_DISABLE[0] 03_391 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPM_CFG[0] 02_328 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPM_CFG[1] 03_328 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPM_CFG[2] 02_329 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPM_CFG[3] 03_329 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPM_CM_CFG[0] 02_430 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPM_GC_CFG[0] 02_432 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPM_GC_CFG[1] 03_432 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPM_GC_CFG[2] 02_433 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPM_GC_CFG[3] 03_433 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPM_GC_CFG[4] 02_434 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPM_GC_CFG[5] 03_434 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPM_GC_CFG[6] 02_435 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPM_GC_CFG[7] 03_435 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPM_GC_CFG[8] 02_436 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPM_GC_CFG2[0] 03_442 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPM_GC_CFG2[1] 02_443 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPM_GC_CFG2[2] 03_443 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPM_HF_CFG[0] 00_336 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPM_HF_CFG[1] 01_336 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPM_HF_CFG[2] 00_337 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPM_HF_CFG[3] 01_337 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPM_HF_CFG[4] 00_338 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPM_HF_CFG[5] 01_338 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPM_HF_CFG[6] 00_339 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPM_HF_CFG[7] 01_339 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPM_HF_CFG[8] 00_340 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPM_HF_CFG[9] 01_340 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPM_HF_CFG[10] 00_341 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPM_HF_CFG[11] 01_341 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPM_HF_CFG[12] 00_342 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPM_HF_CFG[13] 01_342 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPM_HF_CFG2[0] 02_424 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPM_HF_CFG2[1] 03_424 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPM_HF_CFG2[2] 02_425 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPM_HF_CFG2[3] 03_425 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPM_HF_CFG2[4] 02_426 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPM_HF_CFG3[0] 03_389 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPM_HF_CFG3[1] 02_390 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPM_HF_CFG3[2] 03_390 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPM_HF_CFG3[3] 02_391 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPM_HOLD_DURING_EIDLE[0] 00_247 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPM_INCM_CFG[0] 02_439 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPM_IPCM_CFG[0] 03_439 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPM_LF_CFG[0] 00_344 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPM_LF_CFG[1] 01_344 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPM_LF_CFG[2] 00_345 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPM_LF_CFG[3] 01_345 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPM_LF_CFG[4] 00_346 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPM_LF_CFG[5] 01_346 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPM_LF_CFG[6] 00_347 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPM_LF_CFG[7] 01_347 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPM_LF_CFG[8] 00_348 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPM_LF_CFG[9] 01_348 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPM_LF_CFG[10] 00_349 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPM_LF_CFG[11] 01_349 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPM_LF_CFG[12] 00_350 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPM_LF_CFG[13] 01_350 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPM_LF_CFG[14] 00_351 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPM_LF_CFG[15] 01_351 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPM_LF_CFG[16] 00_343 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPM_LF_CFG[17] 01_343 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPM_LF_CFG2[0] 03_426 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPM_LF_CFG2[1] 02_427 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPM_LF_CFG2[2] 03_427 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPM_LF_CFG2[3] 02_428 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPM_LF_CFG2[4] 03_428 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPM_OSINT_CFG[0] 02_440 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPM_OSINT_CFG[1] 03_440 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPM_OSINT_CFG[2] 02_441 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPM_CFG1[0] 02_330 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPMRESET_TIME[0] 00_112 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPMRESET_TIME[1] 01_112 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPMRESET_TIME[2] 00_113 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPMRESET_TIME[3] 01_113 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPMRESET_TIME[4] 00_114 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPMRESET_TIME[5] 01_114 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPMRESET_TIME[6] 00_115 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXOOB_CFG[0] 00_144 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXOOB_CFG[1] 01_144 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXOOB_CFG[2] 00_145 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXOOB_CFG[3] 01_145 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXOOB_CFG[4] 00_146 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXOOB_CFG[5] 01_146 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXOOB_CFG[6] 00_147 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXOOB_CLK_CFG.FABRIC 03_129 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXOSCALRESET_TIME[0] 00_187 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXOSCALRESET_TIME[1] 01_187 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXOSCALRESET_TIME[2] 00_188 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXOSCALRESET_TIME[3] 01_188 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXOSCALRESET_TIME[4] 00_189 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXOSCALRESET_TIMEOUT[0] 01_189 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXOSCALRESET_TIMEOUT[1] 00_190 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXOSCALRESET_TIMEOUT[2] 01_190 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXOSCALRESET_TIMEOUT[3] 00_191 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXOSCALRESET_TIMEOUT[4] 01_191 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXOUT_DIV[0] 02_384 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXOUT_DIV[1] 03_384 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXPCSRESET_TIME[0] 01_115 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXPCSRESET_TIME[1] 00_116 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXPCSRESET_TIME[2] 01_116 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXPCSRESET_TIME[3] 00_117 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXPCSRESET_TIME[4] 01_117 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXPH_CFG[0] 02_584 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXPH_CFG[1] 03_584 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXPH_CFG[2] 02_585 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXPH_CFG[3] 03_585 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXPH_CFG[4] 02_586 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXPH_CFG[5] 03_586 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXPH_CFG[6] 02_587 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXPH_CFG[7] 03_587 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXPH_CFG[8] 02_588 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXPH_CFG[9] 03_588 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXPH_CFG[10] 02_589 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXPH_CFG[11] 03_589 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXPH_CFG[12] 02_590 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXPH_CFG[13] 03_590 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXPH_CFG[14] 02_591 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXPH_CFG[15] 03_591 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXPH_CFG[16] 02_592 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXPH_CFG[17] 03_592 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXPH_CFG[18] 02_593 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXPH_CFG[19] 03_593 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXPH_CFG[20] 02_594 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXPH_CFG[21] 03_594 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXPH_CFG[22] 02_595 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXPH_CFG[23] 03_595 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXPH_MONITOR_SEL[0] 00_700 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXPH_MONITOR_SEL[1] 01_700 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXPH_MONITOR_SEL[2] 00_701 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXPH_MONITOR_SEL[3] 01_701 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXPH_MONITOR_SEL[4] 00_702 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXPHDLY_CFG[0] 02_600 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXPHDLY_CFG[1] 03_600 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXPHDLY_CFG[2] 02_601 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXPHDLY_CFG[3] 03_601 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXPHDLY_CFG[4] 02_602 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXPHDLY_CFG[5] 03_602 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXPHDLY_CFG[6] 02_603 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXPHDLY_CFG[7] 03_603 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXPHDLY_CFG[8] 02_604 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXPHDLY_CFG[9] 03_604 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXPHDLY_CFG[10] 02_605 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXPHDLY_CFG[11] 03_605 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXPHDLY_CFG[12] 02_606 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXPHDLY_CFG[13] 03_606 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXPHDLY_CFG[14] 02_607 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXPHDLY_CFG[15] 03_607 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXPHDLY_CFG[16] 02_608 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXPHDLY_CFG[17] 03_608 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXPHDLY_CFG[18] 02_609 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXPHDLY_CFG[19] 03_609 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXPHDLY_CFG[20] 02_610 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXPHDLY_CFG[21] 03_610 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXPHDLY_CFG[22] 02_611 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXPHDLY_CFG[23] 03_611 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXPI_CFG0[0] 03_430 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXPI_CFG0[1] 02_431 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXPI_CFG0[2] 03_431 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXPI_CFG1[0] 02_442 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXPI_CFG2[0] 03_441 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXPMARESET_TIME[0] 00_104 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXPMARESET_TIME[1] 01_104 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXPMARESET_TIME[2] 00_105 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXPMARESET_TIME[3] 01_105 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXPMARESET_TIME[4] 00_106 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXPRBS_ERR_LOOPBACK[0] 00_136 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXSLIDE_AUTO_WAIT[0] 00_520 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXSLIDE_AUTO_WAIT[1] 01_520 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXSLIDE_AUTO_WAIT[2] 00_521 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXSLIDE_AUTO_WAIT[3] 01_521 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXSLIDE_MODE.AUTO 00_519 !01_519 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXSLIDE_MODE.PCS !00_519 01_519 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXSLIDE_MODE.PMA 00_519 01_519 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXSYNC_MULTILANE[0] 00_133 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXSYNC_OVRD[0] 01_135 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXSYNC_SKIP_DA[0] 01_134 -GTP_CHANNEL_1_MID_LEFT.GTPE2.SAS_MAX_COM[0] 00_171 -GTP_CHANNEL_1_MID_LEFT.GTPE2.SAS_MAX_COM[1] 01_171 -GTP_CHANNEL_1_MID_LEFT.GTPE2.SAS_MAX_COM[2] 00_172 -GTP_CHANNEL_1_MID_LEFT.GTPE2.SAS_MAX_COM[3] 01_172 -GTP_CHANNEL_1_MID_LEFT.GTPE2.SAS_MAX_COM[4] 00_173 -GTP_CHANNEL_1_MID_LEFT.GTPE2.SAS_MAX_COM[5] 01_173 -GTP_CHANNEL_1_MID_LEFT.GTPE2.SAS_MAX_COM[6] 00_174 -GTP_CHANNEL_1_MID_LEFT.GTPE2.SAS_MIN_COM[0] 01_156 -GTP_CHANNEL_1_MID_LEFT.GTPE2.SAS_MIN_COM[1] 00_157 -GTP_CHANNEL_1_MID_LEFT.GTPE2.SAS_MIN_COM[2] 01_157 -GTP_CHANNEL_1_MID_LEFT.GTPE2.SAS_MIN_COM[3] 00_158 -GTP_CHANNEL_1_MID_LEFT.GTPE2.SAS_MIN_COM[4] 01_158 -GTP_CHANNEL_1_MID_LEFT.GTPE2.SAS_MIN_COM[5] 00_159 -GTP_CHANNEL_1_MID_LEFT.GTPE2.SATA_BURST_SEQ_LEN[0] 00_150 -GTP_CHANNEL_1_MID_LEFT.GTPE2.SATA_BURST_SEQ_LEN[1] 01_150 -GTP_CHANNEL_1_MID_LEFT.GTPE2.SATA_BURST_SEQ_LEN[2] 00_151 -GTP_CHANNEL_1_MID_LEFT.GTPE2.SATA_BURST_SEQ_LEN[3] 01_151 -GTP_CHANNEL_1_MID_LEFT.GTPE2.SATA_BURST_VAL[0] 01_147 -GTP_CHANNEL_1_MID_LEFT.GTPE2.SATA_BURST_VAL[1] 00_148 -GTP_CHANNEL_1_MID_LEFT.GTPE2.SATA_BURST_VAL[2] 01_148 -GTP_CHANNEL_1_MID_LEFT.GTPE2.SATA_EIDLE_VAL[0] 00_152 -GTP_CHANNEL_1_MID_LEFT.GTPE2.SATA_EIDLE_VAL[1] 01_152 -GTP_CHANNEL_1_MID_LEFT.GTPE2.SATA_EIDLE_VAL[2] 00_153 -GTP_CHANNEL_1_MID_LEFT.GTPE2.SATA_MAX_BURST[0] 00_168 -GTP_CHANNEL_1_MID_LEFT.GTPE2.SATA_MAX_BURST[1] 01_168 -GTP_CHANNEL_1_MID_LEFT.GTPE2.SATA_MAX_BURST[2] 00_169 -GTP_CHANNEL_1_MID_LEFT.GTPE2.SATA_MAX_BURST[3] 01_169 -GTP_CHANNEL_1_MID_LEFT.GTPE2.SATA_MAX_BURST[4] 00_170 -GTP_CHANNEL_1_MID_LEFT.GTPE2.SATA_MAX_BURST[5] 01_170 -GTP_CHANNEL_1_MID_LEFT.GTPE2.SATA_MAX_INIT[0] 00_176 -GTP_CHANNEL_1_MID_LEFT.GTPE2.SATA_MAX_INIT[1] 01_176 -GTP_CHANNEL_1_MID_LEFT.GTPE2.SATA_MAX_INIT[2] 00_177 -GTP_CHANNEL_1_MID_LEFT.GTPE2.SATA_MAX_INIT[3] 01_177 -GTP_CHANNEL_1_MID_LEFT.GTPE2.SATA_MAX_INIT[4] 00_178 -GTP_CHANNEL_1_MID_LEFT.GTPE2.SATA_MAX_INIT[5] 01_178 -GTP_CHANNEL_1_MID_LEFT.GTPE2.SATA_MAX_WAKE[0] 00_179 -GTP_CHANNEL_1_MID_LEFT.GTPE2.SATA_MAX_WAKE[1] 01_179 -GTP_CHANNEL_1_MID_LEFT.GTPE2.SATA_MAX_WAKE[2] 00_180 -GTP_CHANNEL_1_MID_LEFT.GTPE2.SATA_MAX_WAKE[3] 01_180 -GTP_CHANNEL_1_MID_LEFT.GTPE2.SATA_MAX_WAKE[4] 00_181 -GTP_CHANNEL_1_MID_LEFT.GTPE2.SATA_MAX_WAKE[5] 01_181 -GTP_CHANNEL_1_MID_LEFT.GTPE2.SATA_MIN_BURST[0] 01_153 -GTP_CHANNEL_1_MID_LEFT.GTPE2.SATA_MIN_BURST[1] 00_154 -GTP_CHANNEL_1_MID_LEFT.GTPE2.SATA_MIN_BURST[2] 01_154 -GTP_CHANNEL_1_MID_LEFT.GTPE2.SATA_MIN_BURST[3] 00_155 -GTP_CHANNEL_1_MID_LEFT.GTPE2.SATA_MIN_BURST[4] 01_155 -GTP_CHANNEL_1_MID_LEFT.GTPE2.SATA_MIN_BURST[5] 00_156 -GTP_CHANNEL_1_MID_LEFT.GTPE2.SATA_MIN_INIT[0] 00_160 -GTP_CHANNEL_1_MID_LEFT.GTPE2.SATA_MIN_INIT[1] 01_160 -GTP_CHANNEL_1_MID_LEFT.GTPE2.SATA_MIN_INIT[2] 00_161 -GTP_CHANNEL_1_MID_LEFT.GTPE2.SATA_MIN_INIT[3] 01_161 -GTP_CHANNEL_1_MID_LEFT.GTPE2.SATA_MIN_INIT[4] 00_162 -GTP_CHANNEL_1_MID_LEFT.GTPE2.SATA_MIN_INIT[5] 01_162 -GTP_CHANNEL_1_MID_LEFT.GTPE2.SATA_MIN_WAKE[0] 00_163 -GTP_CHANNEL_1_MID_LEFT.GTPE2.SATA_MIN_WAKE[1] 01_163 -GTP_CHANNEL_1_MID_LEFT.GTPE2.SATA_MIN_WAKE[2] 00_164 -GTP_CHANNEL_1_MID_LEFT.GTPE2.SATA_MIN_WAKE[3] 01_164 -GTP_CHANNEL_1_MID_LEFT.GTPE2.SATA_MIN_WAKE[4] 00_165 -GTP_CHANNEL_1_MID_LEFT.GTPE2.SATA_MIN_WAKE[5] 01_165 -GTP_CHANNEL_1_MID_LEFT.GTPE2.SATA_PLL_CFG.VCO_1500MHZ 02_55 -GTP_CHANNEL_1_MID_LEFT.GTPE2.SATA_PLL_CFG.VCO_750MHZ 03_55 -GTP_CHANNEL_1_MID_LEFT.GTPE2.SHOW_REALIGN_COMMA 01_522 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TERM_RCAL_CFG[0] 02_136 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TERM_RCAL_CFG[1] 03_136 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TERM_RCAL_CFG[2] 02_137 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TERM_RCAL_CFG[3] 03_137 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TERM_RCAL_CFG[4] 02_138 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TERM_RCAL_CFG[5] 03_138 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TERM_RCAL_CFG[6] 02_139 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TERM_RCAL_CFG[7] 03_139 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TERM_RCAL_CFG[8] 02_140 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TERM_RCAL_CFG[9] 03_140 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TERM_RCAL_CFG[10] 02_141 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TERM_RCAL_CFG[11] 03_141 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TERM_RCAL_CFG[12] 02_142 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TERM_RCAL_CFG[13] 03_142 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TERM_RCAL_CFG[14] 02_143 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TERM_RCAL_OVRD[0] 03_150 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TERM_RCAL_OVRD[1] 02_151 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TERM_RCAL_OVRD[2] 03_151 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TRANS_TIME_RATE[0] 00_192 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TRANS_TIME_RATE[1] 01_192 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TRANS_TIME_RATE[2] 00_193 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TRANS_TIME_RATE[3] 01_193 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TRANS_TIME_RATE[4] 00_194 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TRANS_TIME_RATE[5] 01_194 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TRANS_TIME_RATE[6] 00_195 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TRANS_TIME_RATE[7] 01_195 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TST_RSV[0] 02_504 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TST_RSV[1] 03_504 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TST_RSV[2] 02_505 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TST_RSV[3] 03_505 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TST_RSV[4] 02_506 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TST_RSV[5] 03_506 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TST_RSV[6] 02_507 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TST_RSV[7] 03_507 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TST_RSV[8] 02_508 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TST_RSV[9] 03_508 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TST_RSV[10] 02_509 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TST_RSV[11] 03_509 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TST_RSV[12] 02_510 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TST_RSV[13] 03_510 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TST_RSV[14] 02_511 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TST_RSV[15] 03_511 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TST_RSV[16] 02_512 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TST_RSV[17] 03_512 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TST_RSV[18] 02_513 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TST_RSV[19] 03_513 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TST_RSV[20] 02_514 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TST_RSV[21] 03_514 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TST_RSV[22] 02_515 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TST_RSV[23] 03_515 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TST_RSV[24] 02_516 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TST_RSV[25] 03_516 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TST_RSV[26] 02_517 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TST_RSV[27] 03_517 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TST_RSV[28] 02_518 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TST_RSV[29] 03_518 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TST_RSV[30] 02_519 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TST_RSV[31] 03_519 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_CLKMUX_EN[0] 03_128 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_DATA_WIDTH[0] 02_152 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_DATA_WIDTH[1] 03_152 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_DATA_WIDTH[2] 02_153 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_DRIVE_MODE.PIPE 00_200 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_EIDLE_ASSERT_DELAY[0] 00_203 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_EIDLE_ASSERT_DELAY[1] 01_203 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_EIDLE_ASSERT_DELAY[2] 00_204 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_EIDLE_DEASSERT_DELAY[0] 01_204 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_EIDLE_DEASSERT_DELAY[1] 00_205 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_EIDLE_DEASSERT_DELAY[2] 01_205 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_LOOPBACK_DRIVE_HIZ 01_202 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_MAINCURSOR_SEL[0] 03_289 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_MARGIN_FULL_0[0] 02_232 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_MARGIN_FULL_0[1] 03_232 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_MARGIN_FULL_0[2] 02_233 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_MARGIN_FULL_0[3] 03_233 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_MARGIN_FULL_0[4] 02_234 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_MARGIN_FULL_0[5] 03_234 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_MARGIN_FULL_0[6] 02_235 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_MARGIN_FULL_1[0] 02_236 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_MARGIN_FULL_1[1] 03_236 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_MARGIN_FULL_1[2] 02_237 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_MARGIN_FULL_1[3] 03_237 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_MARGIN_FULL_1[4] 02_238 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_MARGIN_FULL_1[5] 03_238 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_MARGIN_FULL_1[6] 02_239 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_MARGIN_FULL_2[0] 02_240 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_MARGIN_FULL_2[1] 03_240 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_MARGIN_FULL_2[2] 02_241 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_MARGIN_FULL_2[3] 03_241 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_MARGIN_FULL_2[4] 02_242 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_MARGIN_FULL_2[5] 03_242 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_MARGIN_FULL_2[6] 02_243 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_MARGIN_FULL_3[0] 02_244 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_MARGIN_FULL_3[1] 03_244 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_MARGIN_FULL_3[2] 02_245 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_MARGIN_FULL_3[3] 03_245 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_MARGIN_FULL_3[4] 02_246 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_MARGIN_FULL_3[5] 03_246 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_MARGIN_FULL_3[6] 02_247 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_MARGIN_FULL_4[0] 02_248 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_MARGIN_FULL_4[1] 03_248 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_MARGIN_FULL_4[2] 02_249 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_MARGIN_FULL_4[3] 03_249 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_MARGIN_FULL_4[4] 02_250 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_MARGIN_FULL_4[5] 03_250 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_MARGIN_FULL_4[6] 02_251 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_MARGIN_LOW_0[0] 02_252 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_MARGIN_LOW_0[1] 03_252 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_MARGIN_LOW_0[2] 02_253 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_MARGIN_LOW_0[3] 03_253 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_MARGIN_LOW_0[4] 02_254 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_MARGIN_LOW_0[5] 03_254 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_MARGIN_LOW_0[6] 02_255 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_MARGIN_LOW_1[0] 02_256 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_MARGIN_LOW_1[1] 03_256 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_MARGIN_LOW_1[2] 02_257 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_MARGIN_LOW_1[3] 03_257 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_MARGIN_LOW_1[4] 02_258 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_MARGIN_LOW_1[5] 03_258 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_MARGIN_LOW_1[6] 02_259 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_MARGIN_LOW_2[0] 02_260 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_MARGIN_LOW_2[1] 03_260 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_MARGIN_LOW_2[2] 02_261 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_MARGIN_LOW_2[3] 03_261 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_MARGIN_LOW_2[4] 02_262 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_MARGIN_LOW_2[5] 03_262 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_MARGIN_LOW_2[6] 02_263 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_MARGIN_LOW_3[0] 02_264 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_MARGIN_LOW_3[1] 03_264 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_MARGIN_LOW_3[2] 02_265 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_MARGIN_LOW_3[3] 03_265 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_MARGIN_LOW_3[4] 02_266 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_MARGIN_LOW_3[5] 03_266 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_MARGIN_LOW_3[6] 02_267 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_MARGIN_LOW_4[0] 02_268 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_MARGIN_LOW_4[1] 03_268 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_MARGIN_LOW_4[2] 02_269 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_MARGIN_LOW_4[3] 03_269 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_MARGIN_LOW_4[4] 02_270 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_MARGIN_LOW_4[5] 03_270 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_MARGIN_LOW_4[6] 02_271 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_PREDRIVER_MODE[0] 00_206 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_RXDETECT_CFG[0] 02_296 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_RXDETECT_CFG[1] 03_296 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_RXDETECT_CFG[2] 02_297 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_RXDETECT_CFG[3] 03_297 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_RXDETECT_CFG[4] 02_298 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_RXDETECT_CFG[5] 03_298 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_RXDETECT_CFG[6] 02_299 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_RXDETECT_CFG[7] 03_299 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_RXDETECT_CFG[8] 02_300 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_RXDETECT_CFG[9] 03_300 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_RXDETECT_CFG[10] 02_301 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_RXDETECT_CFG[11] 03_301 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_RXDETECT_CFG[12] 02_302 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_RXDETECT_CFG[13] 03_302 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_RXDETECT_REF[0] 02_292 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_RXDETECT_REF[1] 03_292 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_RXDETECT_REF[2] 02_293 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_XCLK_SEL.TXUSR 03_11 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_CLK25_DIV[0] 02_144 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_CLK25_DIV[1] 03_144 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_CLK25_DIV[2] 02_145 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_CLK25_DIV[3] 03_145 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_CLK25_DIV[4] 02_146 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_DEEMPH0[0] 02_272 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_DEEMPH0[1] 03_272 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_DEEMPH0[2] 02_273 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_DEEMPH0[3] 03_273 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_DEEMPH0[4] 02_274 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_DEEMPH0[5] 03_274 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_DEEMPH1[0] 02_276 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_DEEMPH1[1] 03_276 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_DEEMPH1[2] 02_277 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_DEEMPH1[3] 03_277 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_DEEMPH1[4] 02_278 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_DEEMPH1[5] 03_278 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXBUF_EN 00_231 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXBUF_RESET_ON_RATE_CHANGE 01_231 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXDLY_CFG[0] 02_80 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXDLY_CFG[1] 03_80 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXDLY_CFG[2] 02_81 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXDLY_CFG[3] 03_81 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXDLY_CFG[4] 02_82 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXDLY_CFG[5] 03_82 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXDLY_CFG[6] 02_83 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXDLY_CFG[7] 03_83 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXDLY_CFG[8] 02_84 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXDLY_CFG[9] 03_84 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXDLY_CFG[10] 02_85 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXDLY_CFG[11] 03_85 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXDLY_CFG[12] 02_86 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXDLY_CFG[13] 03_86 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXDLY_CFG[14] 02_87 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXDLY_CFG[15] 03_87 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXDLY_LCFG[0] 02_568 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXDLY_LCFG[1] 03_568 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXDLY_LCFG[2] 02_569 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXDLY_LCFG[3] 03_569 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXDLY_LCFG[4] 02_570 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXDLY_LCFG[5] 03_570 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXDLY_LCFG[6] 02_571 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXDLY_LCFG[7] 03_571 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXDLY_LCFG[8] 02_572 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXDLY_TAP_CFG[0] 02_88 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXDLY_TAP_CFG[1] 03_88 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXDLY_TAP_CFG[2] 02_89 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXDLY_TAP_CFG[3] 03_89 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXDLY_TAP_CFG[4] 02_90 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXDLY_TAP_CFG[5] 03_90 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXDLY_TAP_CFG[6] 02_91 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXDLY_TAP_CFG[7] 03_91 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXDLY_TAP_CFG[8] 02_92 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXDLY_TAP_CFG[9] 03_92 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXDLY_TAP_CFG[10] 02_93 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXDLY_TAP_CFG[11] 03_93 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXDLY_TAP_CFG[12] 02_94 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXDLY_TAP_CFG[13] 03_94 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXDLY_TAP_CFG[14] 02_95 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXDLY_TAP_CFG[15] 03_95 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXGEARBOX_EN 01_226 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXOOB_CFG[0] 03_20 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXOUT_DIV[0] 02_386 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXOUT_DIV[1] 03_386 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPCSRESET_TIME[0] 01_130 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPCSRESET_TIME[1] 00_131 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPCSRESET_TIME[2] 01_131 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPCSRESET_TIME[3] 00_132 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPCSRESET_TIME[4] 01_132 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPH_CFG[0] 02_96 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPH_CFG[1] 03_96 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPH_CFG[2] 02_97 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPH_CFG[3] 03_97 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPH_CFG[4] 02_98 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPH_CFG[5] 03_98 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPH_CFG[6] 02_99 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPH_CFG[7] 03_99 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPH_CFG[8] 02_100 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPH_CFG[9] 03_100 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPH_CFG[10] 02_101 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPH_CFG[11] 03_101 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPH_CFG[12] 02_102 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPH_CFG[13] 03_102 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPH_CFG[14] 02_103 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPH_CFG[15] 03_103 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPH_MONITOR_SEL[0] 02_108 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPH_MONITOR_SEL[1] 03_108 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPH_MONITOR_SEL[2] 02_109 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPH_MONITOR_SEL[3] 03_109 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPH_MONITOR_SEL[4] 02_110 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPHDLY_CFG[0] 02_64 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPHDLY_CFG[1] 03_64 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPHDLY_CFG[2] 02_65 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPHDLY_CFG[3] 03_65 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPHDLY_CFG[4] 02_66 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPHDLY_CFG[5] 03_66 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPHDLY_CFG[6] 02_67 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPHDLY_CFG[7] 03_67 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPHDLY_CFG[8] 02_68 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPHDLY_CFG[9] 03_68 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPHDLY_CFG[10] 02_69 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPHDLY_CFG[11] 03_69 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPHDLY_CFG[12] 02_70 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPHDLY_CFG[13] 03_70 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPHDLY_CFG[14] 02_71 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPHDLY_CFG[15] 03_71 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPHDLY_CFG[16] 02_72 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPHDLY_CFG[17] 03_72 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPHDLY_CFG[18] 02_73 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPHDLY_CFG[19] 03_73 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPHDLY_CFG[20] 02_74 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPHDLY_CFG[21] 03_74 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPHDLY_CFG[22] 02_75 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPHDLY_CFG[23] 03_75 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPI_GREY_SEL[0] 03_498 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPI_INVSTROBE_SEL[0] 02_498 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPI_PPM_CFG[0] 02_488 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPI_PPM_CFG[1] 03_488 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPI_PPM_CFG[2] 02_489 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPI_PPM_CFG[3] 03_489 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPI_PPM_CFG[4] 02_490 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPI_PPM_CFG[5] 03_490 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPI_PPM_CFG[6] 02_491 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPI_PPM_CFG[7] 03_491 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPI_PPMCLK_SEL.TXUSRCLK2 03_497 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPI_SYNFREQ_PPM[0] 02_496 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPI_SYNFREQ_PPM[1] 03_496 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPI_SYNFREQ_PPM[2] 02_497 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPI_CFG0[0] 02_40 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPI_CFG0[1] 03_40 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPI_CFG1[0] 02_41 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPI_CFG1[1] 03_41 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPI_CFG2[0] 02_42 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPI_CFG2[1] 03_42 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPI_CFG3[0] 02_43 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPI_CFG4[0] 03_43 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPI_CFG5[0] 02_44 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPI_CFG5[1] 03_44 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPI_CFG5[2] 02_45 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPMARESET_TIME[0] 00_128 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPMARESET_TIME[1] 01_128 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPMARESET_TIME[2] 00_129 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPMARESET_TIME[3] 01_129 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPMARESET_TIME[4] 00_130 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXSYNC_MULTILANE[0] 01_133 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXSYNC_OVRD[0] 00_135 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXSYNC_SKIP_DA[0] 00_134 -GTP_CHANNEL_1_MID_LEFT.GTPE2.UCODEER_CLR[0] 01_00 -GTP_CHANNEL_1_MID_LEFT.GTPE2.USE_PCS_CLK_PHASE_SEL[0] 02_463 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ZINV_DMONITORCLK 02_13 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ZINV_DRPCLK 02_00 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ZINV_RXUSRCLK 03_01 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ZINV_SIGVALIDCLK 03_13 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ZINV_TXPHDLYTSTCLK 02_03 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ZINV_TXUSRCLK 03_04 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ZINV_CLKRSVD0 02_23 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ZINV_CLKRSVD1 03_23 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ZINV_RXUSRCLK2 02_02 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ZINV_TXUSRCLK2 02_05 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ACJTAG_DEBUG_MODE[0] 00_07 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ACJTAG_MODE[0] 01_06 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ACJTAG_RESET[0] 01_07 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[0] 02_464 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[1] 03_464 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[2] 02_465 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[3] 03_465 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[4] 02_466 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[5] 03_466 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[6] 02_467 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[7] 03_467 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[8] 02_468 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[9] 03_468 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[10] 02_469 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[11] 03_469 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[12] 02_470 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[13] 03_470 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[14] 02_471 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[15] 03_471 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[16] 02_472 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[17] 03_472 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[18] 02_473 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[19] 03_473 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ALIGN_COMMA_DOUBLE 00_522 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[0] 00_496 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[1] 01_496 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[2] 00_497 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[3] 01_497 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[4] 00_498 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[5] 01_498 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[6] 00_499 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[7] 01_499 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[8] 00_500 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[9] 01_500 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ALIGN_COMMA_WORD[0] 01_526 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ALIGN_COMMA_WORD[1] 00_527 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ALIGN_MCOMMA_DET 00_523 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[0] 00_504 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[1] 01_504 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[2] 00_505 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[3] 01_505 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[4] 00_506 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[5] 01_506 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[6] 00_507 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[7] 01_507 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[8] 00_508 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[9] 01_508 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ALIGN_PCOMMA_DET 01_523 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[0] 00_512 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[1] 01_512 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[2] 00_513 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[3] 01_513 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[4] 00_514 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[5] 01_514 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[6] 00_515 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[7] 01_515 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[8] 00_516 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[9] 01_516 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CBCC_DATA_SOURCE_SEL.DECODED 01_661 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[0] 02_392 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[1] 03_392 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[2] 02_393 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[3] 03_393 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[4] 02_394 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[5] 03_394 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[6] 02_395 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[7] 03_395 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[8] 02_396 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[9] 03_396 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[10] 02_397 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[11] 03_397 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[12] 02_398 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[13] 03_398 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[14] 02_399 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[15] 03_399 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[16] 02_400 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[17] 03_400 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[18] 02_401 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[19] 03_401 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[20] 02_402 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[21] 03_402 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[22] 02_403 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[23] 03_403 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[24] 02_404 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[25] 03_404 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[26] 02_405 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[27] 03_405 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[28] 02_406 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[29] 03_406 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[30] 02_407 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[31] 03_407 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[32] 02_408 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[33] 03_408 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[34] 02_409 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[35] 03_409 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[36] 02_410 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[37] 03_410 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[38] 02_411 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[39] 03_411 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[40] 02_412 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[41] 03_412 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[42] 02_413 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG2[0] 02_459 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG2[1] 03_459 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG2[2] 02_460 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG2[3] 03_460 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG2[4] 02_461 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG2[5] 03_461 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG2[6] 02_462 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG3[0] 02_416 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG3[1] 03_416 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG3[2] 02_417 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG3[3] 03_417 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG3[4] 02_418 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG3[5] 03_418 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG3[6] 02_419 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG4[0] 03_438 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG5[0] 02_429 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG5[1] 03_429 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG6[0] 03_436 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG6[1] 02_437 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG6[2] 03_437 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG6[3] 02_438 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_KEEP_ALIGN 01_631 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_MAX_SKEW[0] 00_670 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_MAX_SKEW[1] 01_670 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_MAX_SKEW[2] 00_671 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_MAX_SKEW[3] 01_671 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[0] 00_608 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[1] 01_608 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[2] 00_609 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[3] 01_609 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[4] 00_610 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[5] 01_610 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[6] 00_611 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[7] 01_611 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[8] 00_612 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[9] 01_612 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[0] 00_616 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[1] 01_616 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[2] 00_617 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[3] 01_617 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[4] 00_618 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[5] 01_618 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[6] 00_619 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[7] 01_619 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[8] 00_620 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[9] 01_620 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[0] 00_624 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[1] 01_624 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[2] 00_625 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[3] 01_625 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[4] 00_626 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[5] 01_626 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[6] 00_627 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[7] 01_627 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[8] 00_628 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[9] 01_628 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[0] 00_632 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[1] 01_632 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[2] 00_633 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[3] 01_633 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[4] 00_634 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[5] 01_634 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[6] 00_635 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[7] 01_635 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[8] 00_636 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[9] 01_636 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_ENABLE[0] 00_614 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_ENABLE[1] 01_614 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_ENABLE[2] 00_615 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_ENABLE[3] 01_615 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[0] 00_640 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[1] 01_640 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[2] 00_641 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[3] 01_641 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[4] 00_642 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[5] 01_642 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[6] 00_643 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[7] 01_643 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[8] 00_644 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[9] 01_644 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[0] 00_648 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[1] 01_648 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[2] 00_649 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[3] 01_649 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[4] 00_650 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[5] 01_650 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[6] 00_651 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[7] 01_651 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[8] 00_652 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[9] 01_652 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[0] 00_656 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[1] 01_656 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[2] 00_657 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[3] 01_657 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[4] 00_658 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[5] 01_658 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[6] 00_659 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[7] 01_659 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[8] 00_660 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[9] 01_660 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[0] 00_664 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[1] 01_664 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[2] 00_665 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[3] 01_665 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[4] 00_666 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[5] 01_666 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[6] 00_667 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[7] 01_667 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[8] 00_668 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[9] 01_668 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_ENABLE[0] 00_646 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_ENABLE[1] 01_646 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_ENABLE[2] 00_647 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_ENABLE[3] 01_647 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_USE 01_645 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_LEN[0] 00_623 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_LEN[1] 01_623 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COMMON_SWING[0] 03_311 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_KEEP_IDLE 00_591 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_MAX_LAT[0] 00_557 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_MAX_LAT[1] 01_557 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_MAX_LAT[2] 00_558 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_MAX_LAT[3] 01_558 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_MAX_LAT[4] 00_559 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_MAX_LAT[5] 01_559 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_MIN_LAT[0] 00_565 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_MIN_LAT[1] 01_565 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_MIN_LAT[2] 00_566 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_MIN_LAT[3] 01_566 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_MIN_LAT[4] 00_567 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_MIN_LAT[5] 01_567 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_PRECEDENCE 00_590 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_REPEAT_WAIT[0] 00_573 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_REPEAT_WAIT[1] 01_573 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_REPEAT_WAIT[2] 00_574 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_REPEAT_WAIT[3] 01_574 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_REPEAT_WAIT[4] 00_575 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[0] 00_544 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[1] 01_544 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[2] 00_545 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[3] 01_545 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[4] 00_546 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[5] 01_546 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[6] 00_547 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[7] 01_547 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[8] 00_548 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[9] 01_548 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[0] 00_552 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[1] 01_552 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[2] 00_553 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[3] 01_553 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[4] 00_554 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[5] 01_554 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[6] 00_555 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[7] 01_555 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[8] 00_556 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[9] 01_556 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[0] 00_560 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[1] 01_560 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[2] 00_561 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[3] 01_561 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[4] 00_562 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[5] 01_562 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[6] 00_563 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[7] 01_563 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[8] 00_564 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[9] 01_564 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[0] 00_568 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[1] 01_568 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[2] 00_569 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[3] 01_569 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[4] 00_570 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[5] 01_570 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[6] 00_571 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[7] 01_571 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[8] 00_572 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[9] 01_572 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_ENABLE[0] 00_549 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_ENABLE[1] 01_549 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_ENABLE[2] 00_550 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_ENABLE[3] 01_550 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[0] 00_576 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[1] 01_576 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[2] 00_577 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[3] 01_577 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[4] 00_578 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[5] 01_578 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[6] 00_579 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[7] 01_579 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[8] 00_580 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[9] 01_580 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[0] 00_584 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[1] 01_584 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[2] 00_585 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[3] 01_585 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[4] 00_586 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[5] 01_586 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[6] 00_587 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[7] 01_587 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[8] 00_588 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[9] 01_588 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[0] 00_592 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[1] 01_592 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[2] 00_593 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[3] 01_593 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[4] 00_594 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[5] 01_594 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[6] 00_595 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[7] 01_595 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[8] 00_596 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[9] 01_596 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[0] 00_600 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[1] 01_600 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[2] 00_601 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[3] 01_601 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[4] 00_602 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[5] 01_602 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[6] 00_603 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[7] 01_603 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[8] 00_604 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[9] 01_604 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_ENABLE[0] 00_581 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_ENABLE[1] 01_581 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_ENABLE[2] 00_582 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_ENABLE[3] 01_582 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_USE 00_583 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_LEN[0] 00_589 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_LEN[1] 01_589 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_CORRECT_USE 00_551 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.DEC_MCOMMA_DETECT 01_494 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.DEC_PCOMMA_DETECT 00_495 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.DEC_VALID_COMMA_ONLY 00_494 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[0] 02_368 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[1] 03_368 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[2] 02_369 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[3] 03_369 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[4] 02_370 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[5] 03_370 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[6] 02_371 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[7] 03_371 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[8] 02_372 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[9] 03_372 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[10] 02_373 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[11] 03_373 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[12] 02_374 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[13] 03_374 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[14] 02_375 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[15] 03_375 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[16] 02_376 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[17] 03_376 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[18] 02_377 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[19] 03_377 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[20] 02_378 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[21] 03_378 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[22] 02_379 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[23] 03_379 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_CLK_PHASE_SEL[0] 03_463 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_CONTROL[0] 00_488 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_CONTROL[1] 01_488 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_CONTROL[2] 00_489 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_CONTROL[3] 01_489 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_CONTROL[4] 00_490 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_CONTROL[5] 01_490 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_ERRDET_EN 01_492 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_EYE_SCAN_EN 00_492 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_HORZ_OFFSET[0] 00_480 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_HORZ_OFFSET[1] 01_480 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_HORZ_OFFSET[2] 00_481 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_HORZ_OFFSET[3] 01_481 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_HORZ_OFFSET[4] 00_482 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_HORZ_OFFSET[5] 01_482 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_HORZ_OFFSET[6] 00_483 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_HORZ_OFFSET[7] 01_483 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_HORZ_OFFSET[8] 00_484 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_HORZ_OFFSET[9] 01_484 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_HORZ_OFFSET[10] 00_485 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_HORZ_OFFSET[11] 01_485 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_PMA_CFG[0] 02_624 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_PMA_CFG[1] 03_624 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_PMA_CFG[2] 02_625 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_PMA_CFG[3] 03_625 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_PMA_CFG[4] 02_626 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_PMA_CFG[5] 03_626 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_PMA_CFG[6] 02_627 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_PMA_CFG[7] 03_627 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_PMA_CFG[8] 02_628 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_PMA_CFG[9] 03_628 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_PRESCALE[0] 01_477 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_PRESCALE[1] 00_478 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_PRESCALE[2] 01_478 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_PRESCALE[3] 00_479 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_PRESCALE[4] 01_479 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[0] 00_392 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[1] 01_392 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[2] 00_393 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[3] 01_393 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[4] 00_394 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[5] 01_394 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[6] 00_395 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[7] 01_395 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[8] 00_396 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[9] 01_396 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[10] 00_397 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[11] 01_397 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[12] 00_398 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[13] 01_398 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[14] 00_399 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[15] 01_399 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[16] 00_400 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[17] 01_400 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[18] 00_401 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[19] 01_401 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[20] 00_402 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[21] 01_402 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[22] 00_403 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[23] 01_403 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[24] 00_404 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[25] 01_404 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[26] 00_405 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[27] 01_405 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[28] 00_406 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[29] 01_406 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[30] 00_407 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[31] 01_407 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[32] 00_408 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[33] 01_408 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[34] 00_409 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[35] 01_409 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[36] 00_410 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[37] 01_410 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[38] 00_411 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[39] 01_411 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[40] 00_412 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[41] 01_412 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[42] 00_413 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[43] 01_413 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[44] 00_414 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[45] 01_414 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[46] 00_415 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[47] 01_415 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[48] 00_416 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[49] 01_416 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[50] 00_417 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[51] 01_417 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[52] 00_418 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[53] 01_418 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[54] 00_419 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[55] 01_419 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[56] 00_420 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[57] 01_420 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[58] 00_421 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[59] 01_421 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[60] 00_422 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[61] 01_422 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[62] 00_423 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[63] 01_423 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[64] 00_424 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[65] 01_424 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[66] 00_425 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[67] 01_425 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[68] 00_426 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[69] 01_426 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[70] 00_427 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[71] 01_427 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[72] 00_428 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[73] 01_428 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[74] 00_429 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[75] 01_429 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[76] 00_430 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[77] 01_430 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[78] 00_431 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[79] 01_431 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[0] 00_352 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[1] 01_352 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[2] 00_353 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[3] 01_353 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[4] 00_354 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[5] 01_354 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[6] 00_355 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[7] 01_355 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[8] 00_356 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[9] 01_356 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[10] 00_357 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[11] 01_357 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[12] 00_358 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[13] 01_358 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[14] 00_359 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[15] 01_359 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[16] 00_360 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[17] 01_360 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[18] 00_361 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[19] 01_361 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[20] 00_362 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[21] 01_362 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[22] 00_363 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[23] 01_363 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[24] 00_364 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[25] 01_364 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[26] 00_365 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[27] 01_365 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[28] 00_366 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[29] 01_366 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[30] 00_367 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[31] 01_367 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[32] 00_368 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[33] 01_368 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[34] 00_369 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[35] 01_369 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[36] 00_370 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[37] 01_370 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[38] 00_371 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[39] 01_371 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[40] 00_372 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[41] 01_372 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[42] 00_373 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[43] 01_373 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[44] 00_374 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[45] 01_374 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[46] 00_375 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[47] 01_375 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[48] 00_376 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[49] 01_376 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[50] 00_377 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[51] 01_377 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[52] 00_378 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[53] 01_378 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[54] 00_379 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[55] 01_379 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[56] 00_380 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[57] 01_380 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[58] 00_381 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[59] 01_381 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[60] 00_382 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[61] 01_382 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[62] 00_383 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[63] 01_383 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[64] 00_384 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[65] 01_384 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[66] 00_385 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[67] 01_385 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[68] 00_386 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[69] 01_386 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[70] 00_387 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[71] 01_387 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[72] 00_388 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[73] 01_388 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[74] 00_389 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[75] 01_389 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[76] 00_390 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[77] 01_390 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[78] 00_391 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[79] 01_391 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[0] 00_432 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[1] 01_432 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[2] 00_433 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[3] 01_433 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[4] 00_434 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[5] 01_434 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[6] 00_435 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[7] 01_435 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[8] 00_436 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[9] 01_436 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[10] 00_437 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[11] 01_437 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[12] 00_438 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[13] 01_438 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[14] 00_439 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[15] 01_439 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[16] 00_440 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[17] 01_440 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[18] 00_441 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[19] 01_441 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[20] 00_442 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[21] 01_442 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[22] 00_443 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[23] 01_443 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[24] 00_444 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[25] 01_444 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[26] 00_445 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[27] 01_445 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[28] 00_446 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[29] 01_446 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[30] 00_447 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[31] 01_447 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[32] 00_448 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[33] 01_448 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[34] 00_449 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[35] 01_449 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[36] 00_450 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[37] 01_450 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[38] 00_451 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[39] 01_451 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[40] 00_452 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[41] 01_452 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[42] 00_453 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[43] 01_453 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[44] 00_454 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[45] 01_454 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[46] 00_455 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[47] 01_455 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[48] 00_456 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[49] 01_456 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[50] 00_457 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[51] 01_457 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[52] 00_458 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[53] 01_458 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[54] 00_459 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[55] 01_459 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[56] 00_460 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[57] 01_460 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[58] 00_461 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[59] 01_461 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[60] 00_462 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[61] 01_462 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[62] 00_463 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[63] 01_463 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[64] 00_464 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[65] 01_464 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[66] 00_465 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[67] 01_465 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[68] 00_466 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[69] 01_466 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[70] 00_467 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[71] 01_467 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[72] 00_468 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[73] 01_468 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[74] 00_469 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[75] 01_469 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[76] 00_470 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[77] 01_470 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[78] 00_471 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[79] 01_471 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_VERT_OFFSET[0] 00_472 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_VERT_OFFSET[1] 01_472 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_VERT_OFFSET[2] 00_473 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_VERT_OFFSET[3] 01_473 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_VERT_OFFSET[4] 00_474 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_VERT_OFFSET[5] 01_474 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_VERT_OFFSET[6] 00_475 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_VERT_OFFSET[7] 01_475 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_VERT_OFFSET[8] 00_476 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.FTS_DESKEW_SEQ_ENABLE[0] 00_662 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.FTS_DESKEW_SEQ_ENABLE[1] 01_662 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.FTS_DESKEW_SEQ_ENABLE[2] 00_663 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.FTS_DESKEW_SEQ_ENABLE[3] 01_663 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.FTS_LANE_DESKEW_CFG[0] 00_654 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.FTS_LANE_DESKEW_CFG[1] 01_654 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.FTS_LANE_DESKEW_CFG[2] 00_655 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.FTS_LANE_DESKEW_CFG[3] 01_655 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.FTS_LANE_DESKEW_EN 01_653 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.GEARBOX_MODE[0] 00_224 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.GEARBOX_MODE[1] 01_224 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.GEARBOX_MODE[2] 00_225 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.IN_USE 00_00 00_01 00_47 00_52 00_53 00_65 01_01 01_47 02_129 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.INV_DMONITORCLK 02_13 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.INV_DRPCLK 02_00 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.INV_RXUSRCLK 03_01 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.INV_SIGVALIDCLK 03_13 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.INV_TXPHDLYTSTCLK 02_03 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.INV_TXUSRCLK 03_04 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.INV_CLKRSVD0 02_23 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.INV_CLKRSVD1 03_23 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.INV_RXUSRCLK2 02_02 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.INV_TXUSRCLK2 02_05 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.LOOPBACK_CFG[0] 02_20 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.OUTREFCLK_SEL_INV[0] 00_149 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.OUTREFCLK_SEL_INV[1] 01_149 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PCS_PCIE_EN 00_216 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[0] 02_184 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[1] 03_184 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[2] 02_185 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[3] 03_185 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[4] 02_186 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[5] 03_186 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[6] 02_187 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[7] 03_187 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[8] 02_188 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[9] 03_188 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[10] 02_189 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[11] 03_189 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[12] 02_190 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[13] 03_190 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[14] 02_191 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[15] 03_191 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[16] 02_192 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[17] 03_192 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[18] 02_193 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[19] 03_193 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[20] 02_194 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[21] 03_194 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[22] 02_195 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[23] 03_195 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[24] 02_196 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[25] 03_196 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[26] 02_197 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[27] 03_197 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[28] 02_198 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[29] 03_198 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[30] 02_199 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[31] 03_199 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[32] 02_200 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[33] 03_200 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[34] 02_201 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[35] 03_201 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[36] 02_202 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[37] 03_202 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[38] 02_203 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[39] 03_203 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[40] 02_204 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[41] 03_204 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[42] 02_205 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[43] 03_205 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[44] 02_206 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[45] 03_206 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[46] 02_207 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[47] 03_207 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[0] 01_216 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[1] 00_217 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[2] 01_217 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[3] 00_218 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[4] 01_218 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[5] 00_219 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[6] 01_219 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[7] 00_220 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[8] 01_220 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[9] 00_221 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[10] 01_221 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[11] 00_222 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[0] 00_208 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[1] 01_208 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[2] 00_209 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[3] 01_209 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[4] 00_210 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[5] 01_210 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[6] 00_211 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[7] 01_211 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[0] 00_212 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[1] 01_212 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[2] 00_213 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[3] 01_213 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[4] 00_214 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[5] 01_214 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[6] 00_215 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[7] 01_215 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PMA_LOOPBACK_CFG[0] 01_207 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[0] 02_520 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[1] 03_520 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[2] 02_521 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[3] 03_521 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[4] 02_522 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[5] 03_522 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[6] 02_523 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[7] 03_523 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[8] 02_524 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[9] 03_524 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[10] 02_525 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[11] 03_525 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[12] 02_526 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[13] 03_526 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[14] 02_527 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[15] 03_527 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[16] 02_528 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[17] 03_528 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[18] 02_529 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[19] 03_529 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[20] 02_530 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[21] 03_530 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[22] 02_531 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[23] 03_531 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[24] 02_532 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[25] 03_532 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[26] 02_533 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[27] 03_533 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[28] 02_534 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[29] 03_534 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[30] 02_535 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[31] 03_535 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[0] 02_336 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[1] 03_336 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[2] 02_337 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[3] 03_337 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[4] 02_338 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[5] 03_338 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[6] 02_339 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[7] 03_339 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[8] 02_340 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[9] 03_340 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[10] 02_341 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[11] 03_341 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[12] 02_342 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[13] 03_342 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[14] 02_343 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[15] 03_343 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[16] 02_344 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[17] 03_344 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[18] 02_345 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[19] 03_345 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[20] 02_346 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[21] 03_346 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[22] 02_347 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[23] 03_347 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[24] 02_348 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[25] 03_348 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[26] 02_349 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[27] 03_349 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[28] 02_350 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[29] 03_350 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[30] 02_351 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[31] 03_351 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PMA_RSV3[0] 02_288 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PMA_RSV3[1] 03_288 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PMA_RSV4[0] 02_156 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PMA_RSV4[1] 03_156 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PMA_RSV4[2] 02_157 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PMA_RSV4[3] 03_157 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PMA_RSV5[0] 03_159 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PMA_RSV6[0] 02_303 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PMA_RSV7[0] 03_303 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_BIAS_CFG[0] 02_112 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_BIAS_CFG[1] 03_112 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_BIAS_CFG[2] 02_113 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_BIAS_CFG[3] 03_113 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_BIAS_CFG[4] 02_114 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_BIAS_CFG[5] 03_114 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_BIAS_CFG[6] 02_115 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_BIAS_CFG[7] 03_115 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_BIAS_CFG[8] 02_116 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_BIAS_CFG[9] 03_116 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_BIAS_CFG[10] 02_117 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_BIAS_CFG[11] 03_117 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_BIAS_CFG[12] 02_118 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_BIAS_CFG[13] 03_118 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_BIAS_CFG[14] 02_119 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_BIAS_CFG[15] 03_119 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_BUFFER_CFG[0] 02_536 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_BUFFER_CFG[1] 03_536 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_BUFFER_CFG[2] 02_537 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_BUFFER_CFG[3] 03_537 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_BUFFER_CFG[4] 02_538 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_BUFFER_CFG[5] 03_538 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_CLKMUX_EN[0] 02_128 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_CM_SEL[0] 00_138 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_CM_SEL[1] 01_138 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_CM_TRIM[0] 02_304 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_CM_TRIM[1] 03_304 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_CM_TRIM[2] 02_305 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_CM_TRIM[3] 03_305 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_DATA_WIDTH[0] 01_141 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_DATA_WIDTH[1] 00_142 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_DATA_WIDTH[2] 01_142 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_DDI_SEL[0] 00_696 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_DDI_SEL[1] 01_696 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_DDI_SEL[2] 00_697 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_DDI_SEL[3] 01_697 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_DDI_SEL[4] 00_698 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_DDI_SEL[5] 01_698 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_DEBUG_CFG[0] 02_616 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_DEBUG_CFG[1] 03_616 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_DEBUG_CFG[2] 02_617 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_DEBUG_CFG[3] 03_617 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_DEBUG_CFG[4] 02_618 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_DEBUG_CFG[5] 03_618 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_DEBUG_CFG[6] 02_619 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_DEBUG_CFG[7] 03_619 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_DEBUG_CFG[8] 02_620 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_DEBUG_CFG[9] 03_620 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_DEBUG_CFG[10] 02_621 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_DEBUG_CFG[11] 03_621 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_DEBUG_CFG[12] 02_622 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_DEBUG_CFG[13] 03_622 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_DEFER_RESET_BUF_EN 02_552 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_DISPERR_SEQ_MATCH 01_495 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_OS_CFG[0] 00_288 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_OS_CFG[1] 01_288 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_OS_CFG[2] 00_289 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_OS_CFG[3] 01_289 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_OS_CFG[4] 00_290 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_OS_CFG[5] 01_290 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_OS_CFG[6] 00_291 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_OS_CFG[7] 01_291 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_OS_CFG[8] 00_292 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_OS_CFG[9] 01_292 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_OS_CFG[10] 00_293 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_OS_CFG[11] 01_293 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_OS_CFG[12] 00_294 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_SIG_VALID_DLY[0] 00_524 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_SIG_VALID_DLY[1] 01_524 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_SIG_VALID_DLY[2] 00_525 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_SIG_VALID_DLY[3] 01_525 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_SIG_VALID_DLY[4] 00_526 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_XCLK_SEL.RXUSR 00_143 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_CLK25_DIV[0] 00_139 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_CLK25_DIV[1] 01_139 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_CLK25_DIV[2] 00_140 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_CLK25_DIV[3] 01_140 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_CLK25_DIV[4] 00_141 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXBUF_ADDR_MODE.FAST 03_555 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXBUF_EIDLE_HI_CNT[0] 02_558 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXBUF_EIDLE_HI_CNT[1] 03_558 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXBUF_EIDLE_HI_CNT[2] 02_559 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXBUF_EIDLE_HI_CNT[3] 03_559 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXBUF_EIDLE_LO_CNT[0] 02_556 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXBUF_EIDLE_LO_CNT[1] 03_556 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXBUF_EIDLE_LO_CNT[2] 02_557 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXBUF_EIDLE_LO_CNT[3] 03_557 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXBUF_EN 02_11 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXBUF_RESET_ON_CB_CHANGE 02_560 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXBUF_RESET_ON_COMMAALIGN 02_561 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXBUF_RESET_ON_EIDLE 02_547 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXBUF_RESET_ON_RATE_CHANGE 03_560 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXBUF_THRESH_OVFLW[0] 03_552 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXBUF_THRESH_OVFLW[1] 02_553 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXBUF_THRESH_OVFLW[2] 03_553 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXBUF_THRESH_OVFLW[3] 02_554 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXBUF_THRESH_OVFLW[4] 03_554 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXBUF_THRESH_OVFLW[5] 02_555 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXBUF_THRESH_OVRD 02_548 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXBUF_THRESH_UNDFLW[0] 02_544 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXBUF_THRESH_UNDFLW[1] 03_544 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXBUF_THRESH_UNDFLW[2] 02_545 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXBUF_THRESH_UNDFLW[3] 03_545 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXBUF_THRESH_UNDFLW[4] 02_546 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXBUF_THRESH_UNDFLW[5] 03_546 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXBUFRESET_TIME[0] 01_101 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXBUFRESET_TIME[1] 00_102 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXBUFRESET_TIME[2] 01_102 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXBUFRESET_TIME[3] 00_103 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXBUFRESET_TIME[4] 01_103 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[0] 02_640 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[1] 03_640 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[2] 02_641 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[3] 03_641 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[4] 02_642 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[5] 03_642 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[6] 02_643 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[7] 03_643 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[8] 02_644 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[9] 03_644 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[10] 02_645 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[11] 03_645 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[12] 02_646 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[13] 03_646 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[14] 02_647 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[15] 03_647 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[16] 02_648 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[17] 03_648 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[18] 02_649 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[19] 03_649 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[20] 02_650 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[21] 03_650 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[22] 02_651 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[23] 03_651 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[24] 02_652 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[25] 03_652 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[26] 02_653 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[27] 03_653 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[28] 02_654 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[29] 03_654 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[30] 02_655 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[31] 03_655 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[32] 02_656 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[33] 03_656 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[34] 02_657 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[35] 03_657 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[36] 02_658 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[37] 03_658 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[38] 02_659 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[39] 03_659 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[40] 02_660 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[41] 03_660 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[42] 02_661 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[43] 03_661 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[44] 02_662 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[45] 03_662 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[46] 02_663 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[47] 03_663 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[48] 02_664 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[49] 03_664 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[50] 02_665 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[51] 03_665 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[52] 02_666 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[53] 03_666 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[54] 02_667 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[55] 03_667 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[56] 02_668 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[57] 03_668 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[58] 02_669 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[59] 03_669 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[60] 02_670 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[61] 03_670 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[62] 02_671 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[63] 03_671 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[64] 02_672 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[65] 03_672 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[66] 02_673 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[67] 03_673 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[68] 02_674 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[69] 03_674 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[70] 02_675 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[71] 03_675 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[72] 02_676 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[73] 03_676 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[74] 02_677 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[75] 03_677 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[76] 02_678 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[77] 03_678 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[78] 02_679 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[79] 03_679 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[80] 02_680 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[81] 03_680 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[82] 02_681 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_FR_RESET_ON_EIDLE[0] 02_638 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_HOLD_DURING_EIDLE[0] 03_637 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_LOCK_CFG[0] 02_632 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_LOCK_CFG[1] 03_632 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_LOCK_CFG[2] 02_633 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_LOCK_CFG[3] 03_633 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_LOCK_CFG[4] 02_634 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_LOCK_CFG[5] 03_634 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_PH_RESET_ON_EIDLE[0] 03_638 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDRFREQRESET_TIME[0] 01_106 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDRFREQRESET_TIME[1] 00_107 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDRFREQRESET_TIME[2] 01_107 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDRFREQRESET_TIME[3] 00_108 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDRFREQRESET_TIME[4] 01_108 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDRPHRESET_TIME[0] 00_109 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDRPHRESET_TIME[1] 01_109 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDRPHRESET_TIME[2] 00_110 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDRPHRESET_TIME[3] 01_110 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDRPHRESET_TIME[4] 00_111 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXDLY_CFG[0] 00_680 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXDLY_CFG[1] 01_680 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXDLY_CFG[2] 00_681 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXDLY_CFG[3] 01_681 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXDLY_CFG[4] 00_682 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXDLY_CFG[5] 01_682 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXDLY_CFG[6] 00_683 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXDLY_CFG[7] 01_683 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXDLY_CFG[8] 00_684 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXDLY_CFG[9] 01_684 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXDLY_CFG[10] 00_685 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXDLY_CFG[11] 01_685 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXDLY_CFG[12] 00_686 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXDLY_CFG[13] 01_686 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXDLY_CFG[14] 00_687 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXDLY_CFG[15] 01_687 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXDLY_LCFG[0] 02_576 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXDLY_LCFG[1] 03_576 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXDLY_LCFG[2] 02_577 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXDLY_LCFG[3] 03_577 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXDLY_LCFG[4] 02_578 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXDLY_LCFG[5] 03_578 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXDLY_LCFG[6] 02_579 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXDLY_LCFG[7] 03_579 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXDLY_LCFG[8] 02_580 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXDLY_TAP_CFG[0] 00_672 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXDLY_TAP_CFG[1] 01_672 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXDLY_TAP_CFG[2] 00_673 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXDLY_TAP_CFG[3] 01_673 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXDLY_TAP_CFG[4] 00_674 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXDLY_TAP_CFG[5] 01_674 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXDLY_TAP_CFG[6] 00_675 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXDLY_TAP_CFG[7] 01_675 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXDLY_TAP_CFG[8] 00_676 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXDLY_TAP_CFG[9] 01_676 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXDLY_TAP_CFG[10] 00_677 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXDLY_TAP_CFG[11] 01_677 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXDLY_TAP_CFG[12] 00_678 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXDLY_TAP_CFG[13] 01_678 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXDLY_TAP_CFG[14] 00_679 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXDLY_TAP_CFG[15] 01_679 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXGEARBOX_EN 01_607 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXISCANRESET_TIME[0] 01_123 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXISCANRESET_TIME[1] 00_124 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXISCANRESET_TIME[2] 01_124 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXISCANRESET_TIME[3] 00_125 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXISCANRESET_TIME[4] 01_125 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPM_BIAS_STARTUP_DISABLE[0] 03_391 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPM_CFG[0] 02_328 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPM_CFG[1] 03_328 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPM_CFG[2] 02_329 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPM_CFG[3] 03_329 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPM_CM_CFG[0] 02_430 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPM_GC_CFG[0] 02_432 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPM_GC_CFG[1] 03_432 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPM_GC_CFG[2] 02_433 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPM_GC_CFG[3] 03_433 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPM_GC_CFG[4] 02_434 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPM_GC_CFG[5] 03_434 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPM_GC_CFG[6] 02_435 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPM_GC_CFG[7] 03_435 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPM_GC_CFG[8] 02_436 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPM_GC_CFG2[0] 03_442 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPM_GC_CFG2[1] 02_443 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPM_GC_CFG2[2] 03_443 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG[0] 00_336 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG[1] 01_336 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG[2] 00_337 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG[3] 01_337 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG[4] 00_338 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG[5] 01_338 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG[6] 00_339 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG[7] 01_339 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG[8] 00_340 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG[9] 01_340 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG[10] 00_341 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG[11] 01_341 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG[12] 00_342 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG[13] 01_342 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG2[0] 02_424 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG2[1] 03_424 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG2[2] 02_425 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG2[3] 03_425 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG2[4] 02_426 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG3[0] 03_389 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG3[1] 02_390 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG3[2] 03_390 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG3[3] 02_391 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPM_HOLD_DURING_EIDLE[0] 00_247 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPM_INCM_CFG[0] 02_439 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPM_IPCM_CFG[0] 03_439 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG[0] 00_344 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG[1] 01_344 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG[2] 00_345 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG[3] 01_345 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG[4] 00_346 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG[5] 01_346 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG[6] 00_347 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG[7] 01_347 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG[8] 00_348 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG[9] 01_348 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG[10] 00_349 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG[11] 01_349 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG[12] 00_350 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG[13] 01_350 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG[14] 00_351 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG[15] 01_351 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG[16] 00_343 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG[17] 01_343 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG2[0] 03_426 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG2[1] 02_427 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG2[2] 03_427 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG2[3] 02_428 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG2[4] 03_428 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPM_OSINT_CFG[0] 02_440 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPM_OSINT_CFG[1] 03_440 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPM_OSINT_CFG[2] 02_441 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPM_CFG1[0] 02_330 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPMRESET_TIME[0] 00_112 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPMRESET_TIME[1] 01_112 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPMRESET_TIME[2] 00_113 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPMRESET_TIME[3] 01_113 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPMRESET_TIME[4] 00_114 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPMRESET_TIME[5] 01_114 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPMRESET_TIME[6] 00_115 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXOOB_CFG[0] 00_144 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXOOB_CFG[1] 01_144 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXOOB_CFG[2] 00_145 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXOOB_CFG[3] 01_145 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXOOB_CFG[4] 00_146 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXOOB_CFG[5] 01_146 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXOOB_CFG[6] 00_147 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXOOB_CLK_CFG.FABRIC 03_129 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXOSCALRESET_TIME[0] 00_187 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXOSCALRESET_TIME[1] 01_187 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXOSCALRESET_TIME[2] 00_188 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXOSCALRESET_TIME[3] 01_188 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXOSCALRESET_TIME[4] 00_189 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXOSCALRESET_TIMEOUT[0] 01_189 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXOSCALRESET_TIMEOUT[1] 00_190 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXOSCALRESET_TIMEOUT[2] 01_190 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXOSCALRESET_TIMEOUT[3] 00_191 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXOSCALRESET_TIMEOUT[4] 01_191 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXOUT_DIV[0] 02_384 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXOUT_DIV[1] 03_384 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXPCSRESET_TIME[0] 01_115 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXPCSRESET_TIME[1] 00_116 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXPCSRESET_TIME[2] 01_116 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXPCSRESET_TIME[3] 00_117 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXPCSRESET_TIME[4] 01_117 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[0] 02_584 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[1] 03_584 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[2] 02_585 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[3] 03_585 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[4] 02_586 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[5] 03_586 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[6] 02_587 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[7] 03_587 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[8] 02_588 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[9] 03_588 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[10] 02_589 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[11] 03_589 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[12] 02_590 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[13] 03_590 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[14] 02_591 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[15] 03_591 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[16] 02_592 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[17] 03_592 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[18] 02_593 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[19] 03_593 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[20] 02_594 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[21] 03_594 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[22] 02_595 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[23] 03_595 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXPH_MONITOR_SEL[0] 00_700 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXPH_MONITOR_SEL[1] 01_700 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXPH_MONITOR_SEL[2] 00_701 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXPH_MONITOR_SEL[3] 01_701 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXPH_MONITOR_SEL[4] 00_702 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[0] 02_600 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[1] 03_600 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[2] 02_601 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[3] 03_601 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[4] 02_602 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[5] 03_602 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[6] 02_603 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[7] 03_603 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[8] 02_604 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[9] 03_604 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[10] 02_605 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[11] 03_605 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[12] 02_606 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[13] 03_606 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[14] 02_607 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[15] 03_607 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[16] 02_608 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[17] 03_608 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[18] 02_609 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[19] 03_609 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[20] 02_610 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[21] 03_610 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[22] 02_611 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[23] 03_611 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXPI_CFG0[0] 03_430 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXPI_CFG0[1] 02_431 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXPI_CFG0[2] 03_431 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXPI_CFG1[0] 02_442 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXPI_CFG2[0] 03_441 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXPMARESET_TIME[0] 00_104 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXPMARESET_TIME[1] 01_104 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXPMARESET_TIME[2] 00_105 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXPMARESET_TIME[3] 01_105 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXPMARESET_TIME[4] 00_106 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXPRBS_ERR_LOOPBACK[0] 00_136 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXSLIDE_AUTO_WAIT[0] 00_520 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXSLIDE_AUTO_WAIT[1] 01_520 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXSLIDE_AUTO_WAIT[2] 00_521 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXSLIDE_AUTO_WAIT[3] 01_521 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXSLIDE_MODE.AUTO 00_519 !01_519 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXSLIDE_MODE.PCS !00_519 01_519 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXSLIDE_MODE.PMA 00_519 01_519 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXSYNC_MULTILANE[0] 00_133 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXSYNC_OVRD[0] 01_135 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXSYNC_SKIP_DA[0] 01_134 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.SAS_MAX_COM[0] 00_171 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.SAS_MAX_COM[1] 01_171 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.SAS_MAX_COM[2] 00_172 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.SAS_MAX_COM[3] 01_172 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.SAS_MAX_COM[4] 00_173 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.SAS_MAX_COM[5] 01_173 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.SAS_MAX_COM[6] 00_174 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.SAS_MIN_COM[0] 01_156 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.SAS_MIN_COM[1] 00_157 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.SAS_MIN_COM[2] 01_157 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.SAS_MIN_COM[3] 00_158 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.SAS_MIN_COM[4] 01_158 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.SAS_MIN_COM[5] 00_159 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.SATA_BURST_SEQ_LEN[0] 00_150 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.SATA_BURST_SEQ_LEN[1] 01_150 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.SATA_BURST_SEQ_LEN[2] 00_151 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.SATA_BURST_SEQ_LEN[3] 01_151 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.SATA_BURST_VAL[0] 01_147 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.SATA_BURST_VAL[1] 00_148 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.SATA_BURST_VAL[2] 01_148 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.SATA_EIDLE_VAL[0] 00_152 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.SATA_EIDLE_VAL[1] 01_152 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.SATA_EIDLE_VAL[2] 00_153 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.SATA_MAX_BURST[0] 00_168 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.SATA_MAX_BURST[1] 01_168 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.SATA_MAX_BURST[2] 00_169 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.SATA_MAX_BURST[3] 01_169 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.SATA_MAX_BURST[4] 00_170 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.SATA_MAX_BURST[5] 01_170 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.SATA_MAX_INIT[0] 00_176 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.SATA_MAX_INIT[1] 01_176 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.SATA_MAX_INIT[2] 00_177 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.SATA_MAX_INIT[3] 01_177 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.SATA_MAX_INIT[4] 00_178 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.SATA_MAX_INIT[5] 01_178 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.SATA_MAX_WAKE[0] 00_179 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.SATA_MAX_WAKE[1] 01_179 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.SATA_MAX_WAKE[2] 00_180 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.SATA_MAX_WAKE[3] 01_180 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.SATA_MAX_WAKE[4] 00_181 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.SATA_MAX_WAKE[5] 01_181 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.SATA_MIN_BURST[0] 01_153 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.SATA_MIN_BURST[1] 00_154 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.SATA_MIN_BURST[2] 01_154 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.SATA_MIN_BURST[3] 00_155 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.SATA_MIN_BURST[4] 01_155 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.SATA_MIN_BURST[5] 00_156 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.SATA_MIN_INIT[0] 00_160 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.SATA_MIN_INIT[1] 01_160 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.SATA_MIN_INIT[2] 00_161 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.SATA_MIN_INIT[3] 01_161 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.SATA_MIN_INIT[4] 00_162 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.SATA_MIN_INIT[5] 01_162 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.SATA_MIN_WAKE[0] 00_163 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.SATA_MIN_WAKE[1] 01_163 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.SATA_MIN_WAKE[2] 00_164 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.SATA_MIN_WAKE[3] 01_164 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.SATA_MIN_WAKE[4] 00_165 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.SATA_MIN_WAKE[5] 01_165 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.SATA_PLL_CFG.VCO_1500MHZ 02_55 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.SATA_PLL_CFG.VCO_750MHZ 03_55 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.SHOW_REALIGN_COMMA 01_522 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TERM_RCAL_CFG[0] 02_136 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TERM_RCAL_CFG[1] 03_136 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TERM_RCAL_CFG[2] 02_137 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TERM_RCAL_CFG[3] 03_137 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TERM_RCAL_CFG[4] 02_138 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TERM_RCAL_CFG[5] 03_138 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TERM_RCAL_CFG[6] 02_139 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TERM_RCAL_CFG[7] 03_139 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TERM_RCAL_CFG[8] 02_140 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TERM_RCAL_CFG[9] 03_140 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TERM_RCAL_CFG[10] 02_141 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TERM_RCAL_CFG[11] 03_141 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TERM_RCAL_CFG[12] 02_142 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TERM_RCAL_CFG[13] 03_142 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TERM_RCAL_CFG[14] 02_143 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TERM_RCAL_OVRD[0] 03_150 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TERM_RCAL_OVRD[1] 02_151 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TERM_RCAL_OVRD[2] 03_151 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TRANS_TIME_RATE[0] 00_192 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TRANS_TIME_RATE[1] 01_192 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TRANS_TIME_RATE[2] 00_193 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TRANS_TIME_RATE[3] 01_193 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TRANS_TIME_RATE[4] 00_194 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TRANS_TIME_RATE[5] 01_194 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TRANS_TIME_RATE[6] 00_195 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TRANS_TIME_RATE[7] 01_195 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TST_RSV[0] 02_504 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TST_RSV[1] 03_504 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TST_RSV[2] 02_505 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TST_RSV[3] 03_505 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TST_RSV[4] 02_506 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TST_RSV[5] 03_506 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TST_RSV[6] 02_507 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TST_RSV[7] 03_507 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TST_RSV[8] 02_508 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TST_RSV[9] 03_508 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TST_RSV[10] 02_509 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TST_RSV[11] 03_509 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TST_RSV[12] 02_510 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TST_RSV[13] 03_510 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TST_RSV[14] 02_511 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TST_RSV[15] 03_511 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TST_RSV[16] 02_512 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TST_RSV[17] 03_512 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TST_RSV[18] 02_513 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TST_RSV[19] 03_513 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TST_RSV[20] 02_514 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TST_RSV[21] 03_514 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TST_RSV[22] 02_515 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TST_RSV[23] 03_515 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TST_RSV[24] 02_516 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TST_RSV[25] 03_516 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TST_RSV[26] 02_517 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TST_RSV[27] 03_517 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TST_RSV[28] 02_518 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TST_RSV[29] 03_518 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TST_RSV[30] 02_519 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TST_RSV[31] 03_519 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_CLKMUX_EN[0] 03_128 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_DATA_WIDTH[0] 02_152 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_DATA_WIDTH[1] 03_152 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_DATA_WIDTH[2] 02_153 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_DRIVE_MODE.PIPE 00_200 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_EIDLE_ASSERT_DELAY[0] 00_203 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_EIDLE_ASSERT_DELAY[1] 01_203 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_EIDLE_ASSERT_DELAY[2] 00_204 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_EIDLE_DEASSERT_DELAY[0] 01_204 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_EIDLE_DEASSERT_DELAY[1] 00_205 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_EIDLE_DEASSERT_DELAY[2] 01_205 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_LOOPBACK_DRIVE_HIZ 01_202 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_MAINCURSOR_SEL[0] 03_289 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_0[0] 02_232 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_0[1] 03_232 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_0[2] 02_233 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_0[3] 03_233 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_0[4] 02_234 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_0[5] 03_234 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_0[6] 02_235 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_1[0] 02_236 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_1[1] 03_236 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_1[2] 02_237 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_1[3] 03_237 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_1[4] 02_238 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_1[5] 03_238 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_1[6] 02_239 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_2[0] 02_240 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_2[1] 03_240 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_2[2] 02_241 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_2[3] 03_241 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_2[4] 02_242 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_2[5] 03_242 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_2[6] 02_243 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_3[0] 02_244 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_3[1] 03_244 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_3[2] 02_245 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_3[3] 03_245 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_3[4] 02_246 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_3[5] 03_246 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_3[6] 02_247 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_4[0] 02_248 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_4[1] 03_248 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_4[2] 02_249 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_4[3] 03_249 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_4[4] 02_250 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_4[5] 03_250 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_4[6] 02_251 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_0[0] 02_252 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_0[1] 03_252 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_0[2] 02_253 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_0[3] 03_253 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_0[4] 02_254 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_0[5] 03_254 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_0[6] 02_255 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_1[0] 02_256 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_1[1] 03_256 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_1[2] 02_257 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_1[3] 03_257 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_1[4] 02_258 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_1[5] 03_258 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_1[6] 02_259 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_2[0] 02_260 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_2[1] 03_260 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_2[2] 02_261 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_2[3] 03_261 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_2[4] 02_262 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_2[5] 03_262 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_2[6] 02_263 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_3[0] 02_264 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_3[1] 03_264 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_3[2] 02_265 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_3[3] 03_265 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_3[4] 02_266 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_3[5] 03_266 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_3[6] 02_267 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_4[0] 02_268 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_4[1] 03_268 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_4[2] 02_269 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_4[3] 03_269 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_4[4] 02_270 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_4[5] 03_270 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_4[6] 02_271 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_PREDRIVER_MODE[0] 00_206 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_RXDETECT_CFG[0] 02_296 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_RXDETECT_CFG[1] 03_296 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_RXDETECT_CFG[2] 02_297 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_RXDETECT_CFG[3] 03_297 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_RXDETECT_CFG[4] 02_298 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_RXDETECT_CFG[5] 03_298 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_RXDETECT_CFG[6] 02_299 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_RXDETECT_CFG[7] 03_299 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_RXDETECT_CFG[8] 02_300 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_RXDETECT_CFG[9] 03_300 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_RXDETECT_CFG[10] 02_301 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_RXDETECT_CFG[11] 03_301 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_RXDETECT_CFG[12] 02_302 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_RXDETECT_CFG[13] 03_302 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_RXDETECT_REF[0] 02_292 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_RXDETECT_REF[1] 03_292 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_RXDETECT_REF[2] 02_293 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_XCLK_SEL.TXUSR 03_11 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_CLK25_DIV[0] 02_144 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_CLK25_DIV[1] 03_144 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_CLK25_DIV[2] 02_145 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_CLK25_DIV[3] 03_145 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_CLK25_DIV[4] 02_146 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_DEEMPH0[0] 02_272 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_DEEMPH0[1] 03_272 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_DEEMPH0[2] 02_273 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_DEEMPH0[3] 03_273 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_DEEMPH0[4] 02_274 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_DEEMPH0[5] 03_274 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_DEEMPH1[0] 02_276 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_DEEMPH1[1] 03_276 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_DEEMPH1[2] 02_277 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_DEEMPH1[3] 03_277 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_DEEMPH1[4] 02_278 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_DEEMPH1[5] 03_278 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXBUF_EN 00_231 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXBUF_RESET_ON_RATE_CHANGE 01_231 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXDLY_CFG[0] 02_80 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXDLY_CFG[1] 03_80 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXDLY_CFG[2] 02_81 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXDLY_CFG[3] 03_81 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXDLY_CFG[4] 02_82 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXDLY_CFG[5] 03_82 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXDLY_CFG[6] 02_83 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXDLY_CFG[7] 03_83 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXDLY_CFG[8] 02_84 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXDLY_CFG[9] 03_84 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXDLY_CFG[10] 02_85 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXDLY_CFG[11] 03_85 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXDLY_CFG[12] 02_86 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXDLY_CFG[13] 03_86 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXDLY_CFG[14] 02_87 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXDLY_CFG[15] 03_87 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXDLY_LCFG[0] 02_568 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXDLY_LCFG[1] 03_568 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXDLY_LCFG[2] 02_569 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXDLY_LCFG[3] 03_569 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXDLY_LCFG[4] 02_570 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXDLY_LCFG[5] 03_570 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXDLY_LCFG[6] 02_571 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXDLY_LCFG[7] 03_571 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXDLY_LCFG[8] 02_572 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXDLY_TAP_CFG[0] 02_88 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXDLY_TAP_CFG[1] 03_88 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXDLY_TAP_CFG[2] 02_89 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXDLY_TAP_CFG[3] 03_89 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXDLY_TAP_CFG[4] 02_90 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXDLY_TAP_CFG[5] 03_90 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXDLY_TAP_CFG[6] 02_91 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXDLY_TAP_CFG[7] 03_91 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXDLY_TAP_CFG[8] 02_92 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXDLY_TAP_CFG[9] 03_92 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXDLY_TAP_CFG[10] 02_93 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXDLY_TAP_CFG[11] 03_93 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXDLY_TAP_CFG[12] 02_94 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXDLY_TAP_CFG[13] 03_94 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXDLY_TAP_CFG[14] 02_95 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXDLY_TAP_CFG[15] 03_95 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXGEARBOX_EN 01_226 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXOOB_CFG[0] 03_20 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXOUT_DIV[0] 02_386 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXOUT_DIV[1] 03_386 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPCSRESET_TIME[0] 01_130 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPCSRESET_TIME[1] 00_131 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPCSRESET_TIME[2] 01_131 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPCSRESET_TIME[3] 00_132 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPCSRESET_TIME[4] 01_132 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPH_CFG[0] 02_96 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPH_CFG[1] 03_96 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPH_CFG[2] 02_97 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPH_CFG[3] 03_97 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPH_CFG[4] 02_98 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPH_CFG[5] 03_98 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPH_CFG[6] 02_99 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPH_CFG[7] 03_99 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPH_CFG[8] 02_100 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPH_CFG[9] 03_100 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPH_CFG[10] 02_101 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPH_CFG[11] 03_101 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPH_CFG[12] 02_102 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPH_CFG[13] 03_102 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPH_CFG[14] 02_103 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPH_CFG[15] 03_103 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPH_MONITOR_SEL[0] 02_108 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPH_MONITOR_SEL[1] 03_108 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPH_MONITOR_SEL[2] 02_109 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPH_MONITOR_SEL[3] 03_109 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPH_MONITOR_SEL[4] 02_110 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[0] 02_64 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[1] 03_64 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[2] 02_65 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[3] 03_65 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[4] 02_66 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[5] 03_66 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[6] 02_67 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[7] 03_67 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[8] 02_68 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[9] 03_68 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[10] 02_69 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[11] 03_69 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[12] 02_70 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[13] 03_70 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[14] 02_71 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[15] 03_71 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[16] 02_72 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[17] 03_72 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[18] 02_73 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[19] 03_73 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[20] 02_74 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[21] 03_74 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[22] 02_75 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[23] 03_75 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPI_GREY_SEL[0] 03_498 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPI_INVSTROBE_SEL[0] 02_498 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPI_PPM_CFG[0] 02_488 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPI_PPM_CFG[1] 03_488 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPI_PPM_CFG[2] 02_489 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPI_PPM_CFG[3] 03_489 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPI_PPM_CFG[4] 02_490 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPI_PPM_CFG[5] 03_490 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPI_PPM_CFG[6] 02_491 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPI_PPM_CFG[7] 03_491 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPI_PPMCLK_SEL.TXUSRCLK2 03_497 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPI_SYNFREQ_PPM[0] 02_496 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPI_SYNFREQ_PPM[1] 03_496 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPI_SYNFREQ_PPM[2] 02_497 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPI_CFG0[0] 02_40 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPI_CFG0[1] 03_40 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPI_CFG1[0] 02_41 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPI_CFG1[1] 03_41 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPI_CFG2[0] 02_42 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPI_CFG2[1] 03_42 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPI_CFG3[0] 02_43 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPI_CFG4[0] 03_43 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPI_CFG5[0] 02_44 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPI_CFG5[1] 03_44 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPI_CFG5[2] 02_45 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPMARESET_TIME[0] 00_128 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPMARESET_TIME[1] 01_128 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPMARESET_TIME[2] 00_129 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPMARESET_TIME[3] 01_129 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPMARESET_TIME[4] 00_130 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXSYNC_MULTILANE[0] 01_133 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXSYNC_OVRD[0] 00_135 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXSYNC_SKIP_DA[0] 00_134 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.UCODEER_CLR[0] 01_00 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.USE_PCS_CLK_PHASE_SEL[0] 02_463 diff --git a/artix7/segbits_gtp_channel_1_mid_left.origin_info.db b/artix7/segbits_gtp_channel_1_mid_left.origin_info.db index 705bf23..a0e5ec2 100644 --- a/artix7/segbits_gtp_channel_1_mid_left.origin_info.db +++ b/artix7/segbits_gtp_channel_1_mid_left.origin_info.db @@ -1,1627 +1,1627 @@ -GTP_CHANNEL_1_MID_LEFT.GTPE2.ACJTAG_DEBUG_MODE[0] origin:064-gtp-channel-conf 00_07 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ACJTAG_MODE[0] origin:064-gtp-channel-conf 01_06 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ACJTAG_RESET[0] origin:064-gtp-channel-conf 01_07 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ADAPT_CFG0[0] origin:064-gtp-channel-conf 02_464 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ADAPT_CFG0[1] origin:064-gtp-channel-conf 03_464 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ADAPT_CFG0[2] origin:064-gtp-channel-conf 02_465 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ADAPT_CFG0[3] origin:064-gtp-channel-conf 03_465 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ADAPT_CFG0[4] origin:064-gtp-channel-conf 02_466 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ADAPT_CFG0[5] origin:064-gtp-channel-conf 03_466 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ADAPT_CFG0[6] origin:064-gtp-channel-conf 02_467 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ADAPT_CFG0[7] origin:064-gtp-channel-conf 03_467 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ADAPT_CFG0[8] origin:064-gtp-channel-conf 02_468 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ADAPT_CFG0[9] origin:064-gtp-channel-conf 03_468 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ADAPT_CFG0[10] origin:064-gtp-channel-conf 02_469 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ADAPT_CFG0[11] origin:064-gtp-channel-conf 03_469 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ADAPT_CFG0[12] origin:064-gtp-channel-conf 02_470 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ADAPT_CFG0[13] origin:064-gtp-channel-conf 03_470 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ADAPT_CFG0[14] origin:064-gtp-channel-conf 02_471 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ADAPT_CFG0[15] origin:064-gtp-channel-conf 03_471 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ADAPT_CFG0[16] origin:064-gtp-channel-conf 02_472 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ADAPT_CFG0[17] origin:064-gtp-channel-conf 03_472 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ADAPT_CFG0[18] origin:064-gtp-channel-conf 02_473 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ADAPT_CFG0[19] origin:064-gtp-channel-conf 03_473 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ALIGN_COMMA_DOUBLE origin:064-gtp-channel-conf 00_522 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ALIGN_COMMA_ENABLE[0] origin:064-gtp-channel-conf 00_496 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ALIGN_COMMA_ENABLE[1] origin:064-gtp-channel-conf 01_496 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ALIGN_COMMA_ENABLE[2] origin:064-gtp-channel-conf 00_497 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ALIGN_COMMA_ENABLE[3] origin:064-gtp-channel-conf 01_497 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ALIGN_COMMA_ENABLE[4] origin:064-gtp-channel-conf 00_498 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ALIGN_COMMA_ENABLE[5] origin:064-gtp-channel-conf 01_498 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ALIGN_COMMA_ENABLE[6] origin:064-gtp-channel-conf 00_499 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ALIGN_COMMA_ENABLE[7] origin:064-gtp-channel-conf 01_499 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ALIGN_COMMA_ENABLE[8] origin:064-gtp-channel-conf 00_500 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ALIGN_COMMA_ENABLE[9] origin:064-gtp-channel-conf 01_500 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ALIGN_COMMA_WORD[0] origin:064-gtp-channel-conf 01_526 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ALIGN_COMMA_WORD[1] origin:064-gtp-channel-conf 00_527 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ALIGN_MCOMMA_DET origin:064-gtp-channel-conf 00_523 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ALIGN_MCOMMA_VALUE[0] origin:064-gtp-channel-conf 00_504 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ALIGN_MCOMMA_VALUE[1] origin:064-gtp-channel-conf 01_504 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ALIGN_MCOMMA_VALUE[2] origin:064-gtp-channel-conf 00_505 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ALIGN_MCOMMA_VALUE[3] origin:064-gtp-channel-conf 01_505 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ALIGN_MCOMMA_VALUE[4] origin:064-gtp-channel-conf 00_506 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ALIGN_MCOMMA_VALUE[5] origin:064-gtp-channel-conf 01_506 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ALIGN_MCOMMA_VALUE[6] origin:064-gtp-channel-conf 00_507 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ALIGN_MCOMMA_VALUE[7] origin:064-gtp-channel-conf 01_507 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ALIGN_MCOMMA_VALUE[8] origin:064-gtp-channel-conf 00_508 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ALIGN_MCOMMA_VALUE[9] origin:064-gtp-channel-conf 01_508 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ALIGN_PCOMMA_DET origin:064-gtp-channel-conf 01_523 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ALIGN_PCOMMA_VALUE[0] origin:064-gtp-channel-conf 00_512 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ALIGN_PCOMMA_VALUE[1] origin:064-gtp-channel-conf 01_512 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ALIGN_PCOMMA_VALUE[2] origin:064-gtp-channel-conf 00_513 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ALIGN_PCOMMA_VALUE[3] origin:064-gtp-channel-conf 01_513 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ALIGN_PCOMMA_VALUE[4] origin:064-gtp-channel-conf 00_514 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ALIGN_PCOMMA_VALUE[5] origin:064-gtp-channel-conf 01_514 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ALIGN_PCOMMA_VALUE[6] origin:064-gtp-channel-conf 00_515 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ALIGN_PCOMMA_VALUE[7] origin:064-gtp-channel-conf 01_515 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ALIGN_PCOMMA_VALUE[8] origin:064-gtp-channel-conf 00_516 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ALIGN_PCOMMA_VALUE[9] origin:064-gtp-channel-conf 01_516 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CBCC_DATA_SOURCE_SEL.DECODED origin:064-gtp-channel-conf 01_661 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CFOK_CFG[0] origin:064-gtp-channel-conf 02_392 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CFOK_CFG[1] origin:064-gtp-channel-conf 03_392 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CFOK_CFG[2] origin:064-gtp-channel-conf 02_393 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CFOK_CFG[3] origin:064-gtp-channel-conf 03_393 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CFOK_CFG[4] origin:064-gtp-channel-conf 02_394 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CFOK_CFG[5] origin:064-gtp-channel-conf 03_394 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CFOK_CFG[6] origin:064-gtp-channel-conf 02_395 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CFOK_CFG[7] origin:064-gtp-channel-conf 03_395 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CFOK_CFG[8] origin:064-gtp-channel-conf 02_396 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CFOK_CFG[9] origin:064-gtp-channel-conf 03_396 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CFOK_CFG[10] origin:064-gtp-channel-conf 02_397 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CFOK_CFG[11] origin:064-gtp-channel-conf 03_397 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CFOK_CFG[12] origin:064-gtp-channel-conf 02_398 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CFOK_CFG[13] origin:064-gtp-channel-conf 03_398 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CFOK_CFG[14] origin:064-gtp-channel-conf 02_399 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CFOK_CFG[15] origin:064-gtp-channel-conf 03_399 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CFOK_CFG[16] origin:064-gtp-channel-conf 02_400 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CFOK_CFG[17] origin:064-gtp-channel-conf 03_400 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CFOK_CFG[18] origin:064-gtp-channel-conf 02_401 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CFOK_CFG[19] origin:064-gtp-channel-conf 03_401 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CFOK_CFG[20] origin:064-gtp-channel-conf 02_402 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CFOK_CFG[21] origin:064-gtp-channel-conf 03_402 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CFOK_CFG[22] origin:064-gtp-channel-conf 02_403 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CFOK_CFG[23] origin:064-gtp-channel-conf 03_403 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CFOK_CFG[24] origin:064-gtp-channel-conf 02_404 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CFOK_CFG[25] origin:064-gtp-channel-conf 03_404 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CFOK_CFG[26] origin:064-gtp-channel-conf 02_405 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CFOK_CFG[27] origin:064-gtp-channel-conf 03_405 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CFOK_CFG[28] origin:064-gtp-channel-conf 02_406 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CFOK_CFG[29] origin:064-gtp-channel-conf 03_406 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CFOK_CFG[30] origin:064-gtp-channel-conf 02_407 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CFOK_CFG[31] origin:064-gtp-channel-conf 03_407 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CFOK_CFG[32] origin:064-gtp-channel-conf 02_408 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CFOK_CFG[33] origin:064-gtp-channel-conf 03_408 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CFOK_CFG[34] origin:064-gtp-channel-conf 02_409 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CFOK_CFG[35] origin:064-gtp-channel-conf 03_409 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CFOK_CFG[36] origin:064-gtp-channel-conf 02_410 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CFOK_CFG[37] origin:064-gtp-channel-conf 03_410 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CFOK_CFG[38] origin:064-gtp-channel-conf 02_411 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CFOK_CFG[39] origin:064-gtp-channel-conf 03_411 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CFOK_CFG[40] origin:064-gtp-channel-conf 02_412 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CFOK_CFG[41] origin:064-gtp-channel-conf 03_412 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CFOK_CFG[42] origin:064-gtp-channel-conf 02_413 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CFOK_CFG2[0] origin:064-gtp-channel-conf 02_459 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CFOK_CFG2[1] origin:064-gtp-channel-conf 03_459 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CFOK_CFG2[2] origin:064-gtp-channel-conf 02_460 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CFOK_CFG2[3] origin:064-gtp-channel-conf 03_460 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CFOK_CFG2[4] origin:064-gtp-channel-conf 02_461 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CFOK_CFG2[5] origin:064-gtp-channel-conf 03_461 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CFOK_CFG2[6] origin:064-gtp-channel-conf 02_462 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CFOK_CFG3[0] origin:064-gtp-channel-conf 02_416 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CFOK_CFG3[1] origin:064-gtp-channel-conf 03_416 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CFOK_CFG3[2] origin:064-gtp-channel-conf 02_417 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CFOK_CFG3[3] origin:064-gtp-channel-conf 03_417 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CFOK_CFG3[4] origin:064-gtp-channel-conf 02_418 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CFOK_CFG3[5] origin:064-gtp-channel-conf 03_418 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CFOK_CFG3[6] origin:064-gtp-channel-conf 02_419 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CFOK_CFG4[0] origin:064-gtp-channel-conf 03_438 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CFOK_CFG5[0] origin:064-gtp-channel-conf 02_429 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CFOK_CFG5[1] origin:064-gtp-channel-conf 03_429 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CFOK_CFG6[0] origin:064-gtp-channel-conf 03_436 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CFOK_CFG6[1] origin:064-gtp-channel-conf 02_437 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CFOK_CFG6[2] origin:064-gtp-channel-conf 03_437 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CFOK_CFG6[3] origin:064-gtp-channel-conf 02_438 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_KEEP_ALIGN origin:064-gtp-channel-conf 01_631 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_MAX_SKEW[0] origin:064-gtp-channel-conf 00_670 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_MAX_SKEW[1] origin:064-gtp-channel-conf 01_670 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_MAX_SKEW[2] origin:064-gtp-channel-conf 00_671 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_MAX_SKEW[3] origin:064-gtp-channel-conf 01_671 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_1[0] origin:064-gtp-channel-conf 00_608 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_1[1] origin:064-gtp-channel-conf 01_608 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_1[2] origin:064-gtp-channel-conf 00_609 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_1[3] origin:064-gtp-channel-conf 01_609 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_1[4] origin:064-gtp-channel-conf 00_610 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_1[5] origin:064-gtp-channel-conf 01_610 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_1[6] origin:064-gtp-channel-conf 00_611 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_1[7] origin:064-gtp-channel-conf 01_611 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_1[8] origin:064-gtp-channel-conf 00_612 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_1[9] origin:064-gtp-channel-conf 01_612 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_2[0] origin:064-gtp-channel-conf 00_616 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_2[1] origin:064-gtp-channel-conf 01_616 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_2[2] origin:064-gtp-channel-conf 00_617 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_2[3] origin:064-gtp-channel-conf 01_617 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_2[4] origin:064-gtp-channel-conf 00_618 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_2[5] origin:064-gtp-channel-conf 01_618 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_2[6] origin:064-gtp-channel-conf 00_619 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_2[7] origin:064-gtp-channel-conf 01_619 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_2[8] origin:064-gtp-channel-conf 00_620 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_2[9] origin:064-gtp-channel-conf 01_620 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_3[0] origin:064-gtp-channel-conf 00_624 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_3[1] origin:064-gtp-channel-conf 01_624 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_3[2] origin:064-gtp-channel-conf 00_625 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_3[3] origin:064-gtp-channel-conf 01_625 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_3[4] origin:064-gtp-channel-conf 00_626 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_3[5] origin:064-gtp-channel-conf 01_626 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_3[6] origin:064-gtp-channel-conf 00_627 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_3[7] origin:064-gtp-channel-conf 01_627 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_3[8] origin:064-gtp-channel-conf 00_628 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_3[9] origin:064-gtp-channel-conf 01_628 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_4[0] origin:064-gtp-channel-conf 00_632 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_4[1] origin:064-gtp-channel-conf 01_632 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_4[2] origin:064-gtp-channel-conf 00_633 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_4[3] origin:064-gtp-channel-conf 01_633 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_4[4] origin:064-gtp-channel-conf 00_634 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_4[5] origin:064-gtp-channel-conf 01_634 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_4[6] origin:064-gtp-channel-conf 00_635 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_4[7] origin:064-gtp-channel-conf 01_635 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_4[8] origin:064-gtp-channel-conf 00_636 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_4[9] origin:064-gtp-channel-conf 01_636 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_ENABLE[0] origin:064-gtp-channel-conf 00_614 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_ENABLE[1] origin:064-gtp-channel-conf 01_614 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_ENABLE[2] origin:064-gtp-channel-conf 00_615 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_ENABLE[3] origin:064-gtp-channel-conf 01_615 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_1[0] origin:064-gtp-channel-conf 00_640 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_1[1] origin:064-gtp-channel-conf 01_640 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_1[2] origin:064-gtp-channel-conf 00_641 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_1[3] origin:064-gtp-channel-conf 01_641 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_1[4] origin:064-gtp-channel-conf 00_642 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_1[5] origin:064-gtp-channel-conf 01_642 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_1[6] origin:064-gtp-channel-conf 00_643 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_1[7] origin:064-gtp-channel-conf 01_643 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_1[8] origin:064-gtp-channel-conf 00_644 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_1[9] origin:064-gtp-channel-conf 01_644 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_2[0] origin:064-gtp-channel-conf 00_648 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_2[1] origin:064-gtp-channel-conf 01_648 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_2[2] origin:064-gtp-channel-conf 00_649 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_2[3] origin:064-gtp-channel-conf 01_649 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_2[4] origin:064-gtp-channel-conf 00_650 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_2[5] origin:064-gtp-channel-conf 01_650 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_2[6] origin:064-gtp-channel-conf 00_651 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_2[7] origin:064-gtp-channel-conf 01_651 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_2[8] origin:064-gtp-channel-conf 00_652 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_2[9] origin:064-gtp-channel-conf 01_652 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_3[0] origin:064-gtp-channel-conf 00_656 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_3[1] origin:064-gtp-channel-conf 01_656 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_3[2] origin:064-gtp-channel-conf 00_657 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_3[3] origin:064-gtp-channel-conf 01_657 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_3[4] origin:064-gtp-channel-conf 00_658 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_3[5] origin:064-gtp-channel-conf 01_658 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_3[6] origin:064-gtp-channel-conf 00_659 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_3[7] origin:064-gtp-channel-conf 01_659 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_3[8] origin:064-gtp-channel-conf 00_660 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_3[9] origin:064-gtp-channel-conf 01_660 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_4[0] origin:064-gtp-channel-conf 00_664 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_4[1] origin:064-gtp-channel-conf 01_664 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_4[2] origin:064-gtp-channel-conf 00_665 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_4[3] origin:064-gtp-channel-conf 01_665 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_4[4] origin:064-gtp-channel-conf 00_666 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_4[5] origin:064-gtp-channel-conf 01_666 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_4[6] origin:064-gtp-channel-conf 00_667 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_4[7] origin:064-gtp-channel-conf 01_667 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_4[8] origin:064-gtp-channel-conf 00_668 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_4[9] origin:064-gtp-channel-conf 01_668 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_ENABLE[0] origin:064-gtp-channel-conf 00_646 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_ENABLE[1] origin:064-gtp-channel-conf 01_646 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_ENABLE[2] origin:064-gtp-channel-conf 00_647 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_ENABLE[3] origin:064-gtp-channel-conf 01_647 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_USE origin:064-gtp-channel-conf 01_645 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_LEN[0] origin:064-gtp-channel-conf 00_623 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CHAN_BOND_SEQ_LEN[1] origin:064-gtp-channel-conf 01_623 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COMMON_SWING[0] origin:064-gtp-channel-conf 03_311 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_KEEP_IDLE origin:064-gtp-channel-conf 00_591 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_MAX_LAT[0] origin:064-gtp-channel-conf 00_557 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_MAX_LAT[1] origin:064-gtp-channel-conf 01_557 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_MAX_LAT[2] origin:064-gtp-channel-conf 00_558 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_MAX_LAT[3] origin:064-gtp-channel-conf 01_558 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_MAX_LAT[4] origin:064-gtp-channel-conf 00_559 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_MAX_LAT[5] origin:064-gtp-channel-conf 01_559 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_MIN_LAT[0] origin:064-gtp-channel-conf 00_565 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_MIN_LAT[1] origin:064-gtp-channel-conf 01_565 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_MIN_LAT[2] origin:064-gtp-channel-conf 00_566 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_MIN_LAT[3] origin:064-gtp-channel-conf 01_566 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_MIN_LAT[4] origin:064-gtp-channel-conf 00_567 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_MIN_LAT[5] origin:064-gtp-channel-conf 01_567 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_PRECEDENCE origin:064-gtp-channel-conf 00_590 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_REPEAT_WAIT[0] origin:064-gtp-channel-conf 00_573 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_REPEAT_WAIT[1] origin:064-gtp-channel-conf 01_573 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_REPEAT_WAIT[2] origin:064-gtp-channel-conf 00_574 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_REPEAT_WAIT[3] origin:064-gtp-channel-conf 01_574 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_REPEAT_WAIT[4] origin:064-gtp-channel-conf 00_575 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_1_1[0] origin:064-gtp-channel-conf 00_544 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_1_1[1] origin:064-gtp-channel-conf 01_544 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_1_1[2] origin:064-gtp-channel-conf 00_545 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_1_1[3] origin:064-gtp-channel-conf 01_545 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_1_1[4] origin:064-gtp-channel-conf 00_546 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_1_1[5] origin:064-gtp-channel-conf 01_546 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_1_1[6] origin:064-gtp-channel-conf 00_547 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_1_1[7] origin:064-gtp-channel-conf 01_547 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_1_1[8] origin:064-gtp-channel-conf 00_548 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_1_1[9] origin:064-gtp-channel-conf 01_548 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_1_2[0] origin:064-gtp-channel-conf 00_552 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_1_2[1] origin:064-gtp-channel-conf 01_552 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_1_2[2] origin:064-gtp-channel-conf 00_553 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_1_2[3] origin:064-gtp-channel-conf 01_553 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_1_2[4] origin:064-gtp-channel-conf 00_554 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_1_2[5] origin:064-gtp-channel-conf 01_554 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_1_2[6] origin:064-gtp-channel-conf 00_555 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_1_2[7] origin:064-gtp-channel-conf 01_555 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_1_2[8] origin:064-gtp-channel-conf 00_556 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_1_2[9] origin:064-gtp-channel-conf 01_556 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_1_3[0] origin:064-gtp-channel-conf 00_560 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_1_3[1] origin:064-gtp-channel-conf 01_560 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_1_3[2] origin:064-gtp-channel-conf 00_561 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_1_3[3] origin:064-gtp-channel-conf 01_561 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_1_3[4] origin:064-gtp-channel-conf 00_562 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_1_3[5] origin:064-gtp-channel-conf 01_562 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_1_3[6] origin:064-gtp-channel-conf 00_563 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_1_3[7] origin:064-gtp-channel-conf 01_563 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_1_3[8] origin:064-gtp-channel-conf 00_564 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_1_3[9] origin:064-gtp-channel-conf 01_564 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_1_4[0] origin:064-gtp-channel-conf 00_568 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_1_4[1] origin:064-gtp-channel-conf 01_568 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_1_4[2] origin:064-gtp-channel-conf 00_569 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_1_4[3] origin:064-gtp-channel-conf 01_569 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_1_4[4] origin:064-gtp-channel-conf 00_570 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_1_4[5] origin:064-gtp-channel-conf 01_570 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_1_4[6] origin:064-gtp-channel-conf 00_571 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_1_4[7] origin:064-gtp-channel-conf 01_571 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_1_4[8] origin:064-gtp-channel-conf 00_572 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_1_4[9] origin:064-gtp-channel-conf 01_572 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_1_ENABLE[0] origin:064-gtp-channel-conf 00_549 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_1_ENABLE[1] origin:064-gtp-channel-conf 01_549 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_1_ENABLE[2] origin:064-gtp-channel-conf 00_550 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_1_ENABLE[3] origin:064-gtp-channel-conf 01_550 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_2_1[0] origin:064-gtp-channel-conf 00_576 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_2_1[1] origin:064-gtp-channel-conf 01_576 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_2_1[2] origin:064-gtp-channel-conf 00_577 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_2_1[3] origin:064-gtp-channel-conf 01_577 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_2_1[4] origin:064-gtp-channel-conf 00_578 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_2_1[5] origin:064-gtp-channel-conf 01_578 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_2_1[6] origin:064-gtp-channel-conf 00_579 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_2_1[7] origin:064-gtp-channel-conf 01_579 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_2_1[8] origin:064-gtp-channel-conf 00_580 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_2_1[9] origin:064-gtp-channel-conf 01_580 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_2_2[0] origin:064-gtp-channel-conf 00_584 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_2_2[1] origin:064-gtp-channel-conf 01_584 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_2_2[2] origin:064-gtp-channel-conf 00_585 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_2_2[3] origin:064-gtp-channel-conf 01_585 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_2_2[4] origin:064-gtp-channel-conf 00_586 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_2_2[5] origin:064-gtp-channel-conf 01_586 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_2_2[6] origin:064-gtp-channel-conf 00_587 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_2_2[7] origin:064-gtp-channel-conf 01_587 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_2_2[8] origin:064-gtp-channel-conf 00_588 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_2_2[9] origin:064-gtp-channel-conf 01_588 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_2_3[0] origin:064-gtp-channel-conf 00_592 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_2_3[1] origin:064-gtp-channel-conf 01_592 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_2_3[2] origin:064-gtp-channel-conf 00_593 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_2_3[3] origin:064-gtp-channel-conf 01_593 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_2_3[4] origin:064-gtp-channel-conf 00_594 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_2_3[5] origin:064-gtp-channel-conf 01_594 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_2_3[6] origin:064-gtp-channel-conf 00_595 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_2_3[7] origin:064-gtp-channel-conf 01_595 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_2_3[8] origin:064-gtp-channel-conf 00_596 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_2_3[9] origin:064-gtp-channel-conf 01_596 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_2_4[0] origin:064-gtp-channel-conf 00_600 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_2_4[1] origin:064-gtp-channel-conf 01_600 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_2_4[2] origin:064-gtp-channel-conf 00_601 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_2_4[3] origin:064-gtp-channel-conf 01_601 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_2_4[4] origin:064-gtp-channel-conf 00_602 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_2_4[5] origin:064-gtp-channel-conf 01_602 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_2_4[6] origin:064-gtp-channel-conf 00_603 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_2_4[7] origin:064-gtp-channel-conf 01_603 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_2_4[8] origin:064-gtp-channel-conf 00_604 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_2_4[9] origin:064-gtp-channel-conf 01_604 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_2_ENABLE[0] origin:064-gtp-channel-conf 00_581 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_2_ENABLE[1] origin:064-gtp-channel-conf 01_581 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_2_ENABLE[2] origin:064-gtp-channel-conf 00_582 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_2_ENABLE[3] origin:064-gtp-channel-conf 01_582 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_2_USE origin:064-gtp-channel-conf 00_583 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_LEN[0] origin:064-gtp-channel-conf 00_589 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_COR_SEQ_LEN[1] origin:064-gtp-channel-conf 01_589 -GTP_CHANNEL_1_MID_LEFT.GTPE2.CLK_CORRECT_USE origin:064-gtp-channel-conf 00_551 -GTP_CHANNEL_1_MID_LEFT.GTPE2.DEC_MCOMMA_DETECT origin:064-gtp-channel-conf 01_494 -GTP_CHANNEL_1_MID_LEFT.GTPE2.DEC_PCOMMA_DETECT origin:064-gtp-channel-conf 00_495 -GTP_CHANNEL_1_MID_LEFT.GTPE2.DEC_VALID_COMMA_ONLY origin:064-gtp-channel-conf 00_494 -GTP_CHANNEL_1_MID_LEFT.GTPE2.DMONITOR_CFG[0] origin:064-gtp-channel-conf 02_368 -GTP_CHANNEL_1_MID_LEFT.GTPE2.DMONITOR_CFG[1] origin:064-gtp-channel-conf 03_368 -GTP_CHANNEL_1_MID_LEFT.GTPE2.DMONITOR_CFG[2] origin:064-gtp-channel-conf 02_369 -GTP_CHANNEL_1_MID_LEFT.GTPE2.DMONITOR_CFG[3] origin:064-gtp-channel-conf 03_369 -GTP_CHANNEL_1_MID_LEFT.GTPE2.DMONITOR_CFG[4] origin:064-gtp-channel-conf 02_370 -GTP_CHANNEL_1_MID_LEFT.GTPE2.DMONITOR_CFG[5] origin:064-gtp-channel-conf 03_370 -GTP_CHANNEL_1_MID_LEFT.GTPE2.DMONITOR_CFG[6] origin:064-gtp-channel-conf 02_371 -GTP_CHANNEL_1_MID_LEFT.GTPE2.DMONITOR_CFG[7] origin:064-gtp-channel-conf 03_371 -GTP_CHANNEL_1_MID_LEFT.GTPE2.DMONITOR_CFG[8] origin:064-gtp-channel-conf 02_372 -GTP_CHANNEL_1_MID_LEFT.GTPE2.DMONITOR_CFG[9] origin:064-gtp-channel-conf 03_372 -GTP_CHANNEL_1_MID_LEFT.GTPE2.DMONITOR_CFG[10] origin:064-gtp-channel-conf 02_373 -GTP_CHANNEL_1_MID_LEFT.GTPE2.DMONITOR_CFG[11] origin:064-gtp-channel-conf 03_373 -GTP_CHANNEL_1_MID_LEFT.GTPE2.DMONITOR_CFG[12] origin:064-gtp-channel-conf 02_374 -GTP_CHANNEL_1_MID_LEFT.GTPE2.DMONITOR_CFG[13] origin:064-gtp-channel-conf 03_374 -GTP_CHANNEL_1_MID_LEFT.GTPE2.DMONITOR_CFG[14] origin:064-gtp-channel-conf 02_375 -GTP_CHANNEL_1_MID_LEFT.GTPE2.DMONITOR_CFG[15] origin:064-gtp-channel-conf 03_375 -GTP_CHANNEL_1_MID_LEFT.GTPE2.DMONITOR_CFG[16] origin:064-gtp-channel-conf 02_376 -GTP_CHANNEL_1_MID_LEFT.GTPE2.DMONITOR_CFG[17] origin:064-gtp-channel-conf 03_376 -GTP_CHANNEL_1_MID_LEFT.GTPE2.DMONITOR_CFG[18] origin:064-gtp-channel-conf 02_377 -GTP_CHANNEL_1_MID_LEFT.GTPE2.DMONITOR_CFG[19] origin:064-gtp-channel-conf 03_377 -GTP_CHANNEL_1_MID_LEFT.GTPE2.DMONITOR_CFG[20] origin:064-gtp-channel-conf 02_378 -GTP_CHANNEL_1_MID_LEFT.GTPE2.DMONITOR_CFG[21] origin:064-gtp-channel-conf 03_378 -GTP_CHANNEL_1_MID_LEFT.GTPE2.DMONITOR_CFG[22] origin:064-gtp-channel-conf 02_379 -GTP_CHANNEL_1_MID_LEFT.GTPE2.DMONITOR_CFG[23] origin:064-gtp-channel-conf 03_379 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_CLK_PHASE_SEL[0] origin:064-gtp-channel-conf 03_463 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_CONTROL[0] origin:064-gtp-channel-conf 00_488 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_CONTROL[1] origin:064-gtp-channel-conf 01_488 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_CONTROL[2] origin:064-gtp-channel-conf 00_489 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_CONTROL[3] origin:064-gtp-channel-conf 01_489 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_CONTROL[4] origin:064-gtp-channel-conf 00_490 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_CONTROL[5] origin:064-gtp-channel-conf 01_490 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_ERRDET_EN origin:064-gtp-channel-conf 01_492 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_EYE_SCAN_EN origin:064-gtp-channel-conf 00_492 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_HORZ_OFFSET[0] origin:064-gtp-channel-conf 00_480 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_HORZ_OFFSET[1] origin:064-gtp-channel-conf 01_480 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_HORZ_OFFSET[2] origin:064-gtp-channel-conf 00_481 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_HORZ_OFFSET[3] origin:064-gtp-channel-conf 01_481 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_HORZ_OFFSET[4] origin:064-gtp-channel-conf 00_482 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_HORZ_OFFSET[5] origin:064-gtp-channel-conf 01_482 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_HORZ_OFFSET[6] origin:064-gtp-channel-conf 00_483 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_HORZ_OFFSET[7] origin:064-gtp-channel-conf 01_483 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_HORZ_OFFSET[8] origin:064-gtp-channel-conf 00_484 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_HORZ_OFFSET[9] origin:064-gtp-channel-conf 01_484 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_HORZ_OFFSET[10] origin:064-gtp-channel-conf 00_485 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_HORZ_OFFSET[11] origin:064-gtp-channel-conf 01_485 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_PMA_CFG[0] origin:064-gtp-channel-conf 02_624 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_PMA_CFG[1] origin:064-gtp-channel-conf 03_624 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_PMA_CFG[2] origin:064-gtp-channel-conf 02_625 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_PMA_CFG[3] origin:064-gtp-channel-conf 03_625 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_PMA_CFG[4] origin:064-gtp-channel-conf 02_626 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_PMA_CFG[5] origin:064-gtp-channel-conf 03_626 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_PMA_CFG[6] origin:064-gtp-channel-conf 02_627 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_PMA_CFG[7] origin:064-gtp-channel-conf 03_627 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_PMA_CFG[8] origin:064-gtp-channel-conf 02_628 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_PMA_CFG[9] origin:064-gtp-channel-conf 03_628 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_PRESCALE[0] origin:064-gtp-channel-conf 01_477 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_PRESCALE[1] origin:064-gtp-channel-conf 00_478 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_PRESCALE[2] origin:064-gtp-channel-conf 01_478 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_PRESCALE[3] origin:064-gtp-channel-conf 00_479 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_PRESCALE[4] origin:064-gtp-channel-conf 01_479 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[0] origin:064-gtp-channel-conf 00_392 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[1] origin:064-gtp-channel-conf 01_392 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[2] origin:064-gtp-channel-conf 00_393 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[3] origin:064-gtp-channel-conf 01_393 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[4] origin:064-gtp-channel-conf 00_394 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[5] origin:064-gtp-channel-conf 01_394 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[6] origin:064-gtp-channel-conf 00_395 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[7] origin:064-gtp-channel-conf 01_395 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[8] origin:064-gtp-channel-conf 00_396 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[9] origin:064-gtp-channel-conf 01_396 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[10] origin:064-gtp-channel-conf 00_397 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[11] origin:064-gtp-channel-conf 01_397 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[12] origin:064-gtp-channel-conf 00_398 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[13] origin:064-gtp-channel-conf 01_398 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[14] origin:064-gtp-channel-conf 00_399 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[15] origin:064-gtp-channel-conf 01_399 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[16] origin:064-gtp-channel-conf 00_400 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[17] origin:064-gtp-channel-conf 01_400 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[18] origin:064-gtp-channel-conf 00_401 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[19] origin:064-gtp-channel-conf 01_401 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[20] origin:064-gtp-channel-conf 00_402 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[21] origin:064-gtp-channel-conf 01_402 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[22] origin:064-gtp-channel-conf 00_403 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[23] origin:064-gtp-channel-conf 01_403 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[24] origin:064-gtp-channel-conf 00_404 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[25] origin:064-gtp-channel-conf 01_404 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[26] origin:064-gtp-channel-conf 00_405 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[27] origin:064-gtp-channel-conf 01_405 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[28] origin:064-gtp-channel-conf 00_406 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[29] origin:064-gtp-channel-conf 01_406 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[30] origin:064-gtp-channel-conf 00_407 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[31] origin:064-gtp-channel-conf 01_407 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[32] origin:064-gtp-channel-conf 00_408 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[33] origin:064-gtp-channel-conf 01_408 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[34] origin:064-gtp-channel-conf 00_409 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[35] origin:064-gtp-channel-conf 01_409 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[36] origin:064-gtp-channel-conf 00_410 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[37] origin:064-gtp-channel-conf 01_410 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[38] origin:064-gtp-channel-conf 00_411 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[39] origin:064-gtp-channel-conf 01_411 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[40] origin:064-gtp-channel-conf 00_412 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[41] origin:064-gtp-channel-conf 01_412 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[42] origin:064-gtp-channel-conf 00_413 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[43] origin:064-gtp-channel-conf 01_413 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[44] origin:064-gtp-channel-conf 00_414 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[45] origin:064-gtp-channel-conf 01_414 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[46] origin:064-gtp-channel-conf 00_415 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[47] origin:064-gtp-channel-conf 01_415 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[48] origin:064-gtp-channel-conf 00_416 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[49] origin:064-gtp-channel-conf 01_416 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[50] origin:064-gtp-channel-conf 00_417 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[51] origin:064-gtp-channel-conf 01_417 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[52] origin:064-gtp-channel-conf 00_418 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[53] origin:064-gtp-channel-conf 01_418 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[54] origin:064-gtp-channel-conf 00_419 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[55] origin:064-gtp-channel-conf 01_419 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[56] origin:064-gtp-channel-conf 00_420 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[57] origin:064-gtp-channel-conf 01_420 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[58] origin:064-gtp-channel-conf 00_421 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[59] origin:064-gtp-channel-conf 01_421 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[60] origin:064-gtp-channel-conf 00_422 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[61] origin:064-gtp-channel-conf 01_422 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[62] origin:064-gtp-channel-conf 00_423 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[63] origin:064-gtp-channel-conf 01_423 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[64] origin:064-gtp-channel-conf 00_424 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[65] origin:064-gtp-channel-conf 01_424 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[66] origin:064-gtp-channel-conf 00_425 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[67] origin:064-gtp-channel-conf 01_425 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[68] origin:064-gtp-channel-conf 00_426 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[69] origin:064-gtp-channel-conf 01_426 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[70] origin:064-gtp-channel-conf 00_427 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[71] origin:064-gtp-channel-conf 01_427 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[72] origin:064-gtp-channel-conf 00_428 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[73] origin:064-gtp-channel-conf 01_428 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[74] origin:064-gtp-channel-conf 00_429 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[75] origin:064-gtp-channel-conf 01_429 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[76] origin:064-gtp-channel-conf 00_430 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[77] origin:064-gtp-channel-conf 01_430 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[78] origin:064-gtp-channel-conf 00_431 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUAL_MASK[79] origin:064-gtp-channel-conf 01_431 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[0] origin:064-gtp-channel-conf 00_352 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[1] origin:064-gtp-channel-conf 01_352 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[2] origin:064-gtp-channel-conf 00_353 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[3] origin:064-gtp-channel-conf 01_353 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[4] origin:064-gtp-channel-conf 00_354 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[5] origin:064-gtp-channel-conf 01_354 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[6] origin:064-gtp-channel-conf 00_355 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[7] origin:064-gtp-channel-conf 01_355 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[8] origin:064-gtp-channel-conf 00_356 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[9] origin:064-gtp-channel-conf 01_356 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[10] origin:064-gtp-channel-conf 00_357 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[11] origin:064-gtp-channel-conf 01_357 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[12] origin:064-gtp-channel-conf 00_358 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[13] origin:064-gtp-channel-conf 01_358 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[14] origin:064-gtp-channel-conf 00_359 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[15] origin:064-gtp-channel-conf 01_359 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[16] origin:064-gtp-channel-conf 00_360 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[17] origin:064-gtp-channel-conf 01_360 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[18] origin:064-gtp-channel-conf 00_361 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[19] origin:064-gtp-channel-conf 01_361 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[20] origin:064-gtp-channel-conf 00_362 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[21] origin:064-gtp-channel-conf 01_362 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[22] origin:064-gtp-channel-conf 00_363 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[23] origin:064-gtp-channel-conf 01_363 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[24] origin:064-gtp-channel-conf 00_364 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[25] origin:064-gtp-channel-conf 01_364 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[26] origin:064-gtp-channel-conf 00_365 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[27] origin:064-gtp-channel-conf 01_365 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[28] origin:064-gtp-channel-conf 00_366 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[29] origin:064-gtp-channel-conf 01_366 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[30] origin:064-gtp-channel-conf 00_367 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[31] origin:064-gtp-channel-conf 01_367 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[32] origin:064-gtp-channel-conf 00_368 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[33] origin:064-gtp-channel-conf 01_368 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[34] origin:064-gtp-channel-conf 00_369 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[35] origin:064-gtp-channel-conf 01_369 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[36] origin:064-gtp-channel-conf 00_370 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[37] origin:064-gtp-channel-conf 01_370 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[38] origin:064-gtp-channel-conf 00_371 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[39] origin:064-gtp-channel-conf 01_371 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[40] origin:064-gtp-channel-conf 00_372 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[41] origin:064-gtp-channel-conf 01_372 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[42] origin:064-gtp-channel-conf 00_373 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[43] origin:064-gtp-channel-conf 01_373 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[44] origin:064-gtp-channel-conf 00_374 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[45] origin:064-gtp-channel-conf 01_374 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[46] origin:064-gtp-channel-conf 00_375 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[47] origin:064-gtp-channel-conf 01_375 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[48] origin:064-gtp-channel-conf 00_376 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[49] origin:064-gtp-channel-conf 01_376 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[50] origin:064-gtp-channel-conf 00_377 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[51] origin:064-gtp-channel-conf 01_377 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[52] origin:064-gtp-channel-conf 00_378 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[53] origin:064-gtp-channel-conf 01_378 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[54] origin:064-gtp-channel-conf 00_379 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[55] origin:064-gtp-channel-conf 01_379 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[56] origin:064-gtp-channel-conf 00_380 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[57] origin:064-gtp-channel-conf 01_380 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[58] origin:064-gtp-channel-conf 00_381 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[59] origin:064-gtp-channel-conf 01_381 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[60] origin:064-gtp-channel-conf 00_382 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[61] origin:064-gtp-channel-conf 01_382 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[62] origin:064-gtp-channel-conf 00_383 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[63] origin:064-gtp-channel-conf 01_383 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[64] origin:064-gtp-channel-conf 00_384 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[65] origin:064-gtp-channel-conf 01_384 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[66] origin:064-gtp-channel-conf 00_385 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[67] origin:064-gtp-channel-conf 01_385 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[68] origin:064-gtp-channel-conf 00_386 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[69] origin:064-gtp-channel-conf 01_386 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[70] origin:064-gtp-channel-conf 00_387 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[71] origin:064-gtp-channel-conf 01_387 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[72] origin:064-gtp-channel-conf 00_388 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[73] origin:064-gtp-channel-conf 01_388 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[74] origin:064-gtp-channel-conf 00_389 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[75] origin:064-gtp-channel-conf 01_389 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[76] origin:064-gtp-channel-conf 00_390 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[77] origin:064-gtp-channel-conf 01_390 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[78] origin:064-gtp-channel-conf 00_391 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_QUALIFIER[79] origin:064-gtp-channel-conf 01_391 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[0] origin:064-gtp-channel-conf 00_432 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[1] origin:064-gtp-channel-conf 01_432 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[2] origin:064-gtp-channel-conf 00_433 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[3] origin:064-gtp-channel-conf 01_433 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[4] origin:064-gtp-channel-conf 00_434 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[5] origin:064-gtp-channel-conf 01_434 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[6] origin:064-gtp-channel-conf 00_435 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[7] origin:064-gtp-channel-conf 01_435 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[8] origin:064-gtp-channel-conf 00_436 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[9] origin:064-gtp-channel-conf 01_436 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[10] origin:064-gtp-channel-conf 00_437 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[11] origin:064-gtp-channel-conf 01_437 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[12] origin:064-gtp-channel-conf 00_438 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[13] origin:064-gtp-channel-conf 01_438 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[14] origin:064-gtp-channel-conf 00_439 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[15] origin:064-gtp-channel-conf 01_439 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[16] origin:064-gtp-channel-conf 00_440 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[17] origin:064-gtp-channel-conf 01_440 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[18] origin:064-gtp-channel-conf 00_441 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[19] origin:064-gtp-channel-conf 01_441 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[20] origin:064-gtp-channel-conf 00_442 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[21] origin:064-gtp-channel-conf 01_442 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[22] origin:064-gtp-channel-conf 00_443 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[23] origin:064-gtp-channel-conf 01_443 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[24] origin:064-gtp-channel-conf 00_444 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[25] origin:064-gtp-channel-conf 01_444 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[26] origin:064-gtp-channel-conf 00_445 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[27] origin:064-gtp-channel-conf 01_445 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[28] origin:064-gtp-channel-conf 00_446 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[29] origin:064-gtp-channel-conf 01_446 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[30] origin:064-gtp-channel-conf 00_447 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[31] origin:064-gtp-channel-conf 01_447 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[32] origin:064-gtp-channel-conf 00_448 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[33] origin:064-gtp-channel-conf 01_448 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[34] origin:064-gtp-channel-conf 00_449 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[35] origin:064-gtp-channel-conf 01_449 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[36] origin:064-gtp-channel-conf 00_450 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[37] origin:064-gtp-channel-conf 01_450 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[38] origin:064-gtp-channel-conf 00_451 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[39] origin:064-gtp-channel-conf 01_451 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[40] origin:064-gtp-channel-conf 00_452 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[41] origin:064-gtp-channel-conf 01_452 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[42] origin:064-gtp-channel-conf 00_453 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[43] origin:064-gtp-channel-conf 01_453 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[44] origin:064-gtp-channel-conf 00_454 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[45] origin:064-gtp-channel-conf 01_454 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[46] origin:064-gtp-channel-conf 00_455 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[47] origin:064-gtp-channel-conf 01_455 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[48] origin:064-gtp-channel-conf 00_456 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[49] origin:064-gtp-channel-conf 01_456 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[50] origin:064-gtp-channel-conf 00_457 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[51] origin:064-gtp-channel-conf 01_457 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[52] origin:064-gtp-channel-conf 00_458 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[53] origin:064-gtp-channel-conf 01_458 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[54] origin:064-gtp-channel-conf 00_459 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[55] origin:064-gtp-channel-conf 01_459 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[56] origin:064-gtp-channel-conf 00_460 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[57] origin:064-gtp-channel-conf 01_460 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[58] origin:064-gtp-channel-conf 00_461 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[59] origin:064-gtp-channel-conf 01_461 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[60] origin:064-gtp-channel-conf 00_462 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[61] origin:064-gtp-channel-conf 01_462 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[62] origin:064-gtp-channel-conf 00_463 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[63] origin:064-gtp-channel-conf 01_463 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[64] origin:064-gtp-channel-conf 00_464 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[65] origin:064-gtp-channel-conf 01_464 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[66] origin:064-gtp-channel-conf 00_465 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[67] origin:064-gtp-channel-conf 01_465 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[68] origin:064-gtp-channel-conf 00_466 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[69] origin:064-gtp-channel-conf 01_466 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[70] origin:064-gtp-channel-conf 00_467 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[71] origin:064-gtp-channel-conf 01_467 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[72] origin:064-gtp-channel-conf 00_468 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[73] origin:064-gtp-channel-conf 01_468 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[74] origin:064-gtp-channel-conf 00_469 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[75] origin:064-gtp-channel-conf 01_469 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[76] origin:064-gtp-channel-conf 00_470 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[77] origin:064-gtp-channel-conf 01_470 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[78] origin:064-gtp-channel-conf 00_471 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_SDATA_MASK[79] origin:064-gtp-channel-conf 01_471 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_VERT_OFFSET[0] origin:064-gtp-channel-conf 00_472 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_VERT_OFFSET[1] origin:064-gtp-channel-conf 01_472 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_VERT_OFFSET[2] origin:064-gtp-channel-conf 00_473 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_VERT_OFFSET[3] origin:064-gtp-channel-conf 01_473 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_VERT_OFFSET[4] origin:064-gtp-channel-conf 00_474 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_VERT_OFFSET[5] origin:064-gtp-channel-conf 01_474 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_VERT_OFFSET[6] origin:064-gtp-channel-conf 00_475 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_VERT_OFFSET[7] origin:064-gtp-channel-conf 01_475 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ES_VERT_OFFSET[8] origin:064-gtp-channel-conf 00_476 -GTP_CHANNEL_1_MID_LEFT.GTPE2.FTS_DESKEW_SEQ_ENABLE[0] origin:064-gtp-channel-conf 00_662 -GTP_CHANNEL_1_MID_LEFT.GTPE2.FTS_DESKEW_SEQ_ENABLE[1] origin:064-gtp-channel-conf 01_662 -GTP_CHANNEL_1_MID_LEFT.GTPE2.FTS_DESKEW_SEQ_ENABLE[2] origin:064-gtp-channel-conf 00_663 -GTP_CHANNEL_1_MID_LEFT.GTPE2.FTS_DESKEW_SEQ_ENABLE[3] origin:064-gtp-channel-conf 01_663 -GTP_CHANNEL_1_MID_LEFT.GTPE2.FTS_LANE_DESKEW_CFG[0] origin:064-gtp-channel-conf 00_654 -GTP_CHANNEL_1_MID_LEFT.GTPE2.FTS_LANE_DESKEW_CFG[1] origin:064-gtp-channel-conf 01_654 -GTP_CHANNEL_1_MID_LEFT.GTPE2.FTS_LANE_DESKEW_CFG[2] origin:064-gtp-channel-conf 00_655 -GTP_CHANNEL_1_MID_LEFT.GTPE2.FTS_LANE_DESKEW_CFG[3] origin:064-gtp-channel-conf 01_655 -GTP_CHANNEL_1_MID_LEFT.GTPE2.FTS_LANE_DESKEW_EN origin:064-gtp-channel-conf 01_653 -GTP_CHANNEL_1_MID_LEFT.GTPE2.GEARBOX_MODE[0] origin:064-gtp-channel-conf 00_224 -GTP_CHANNEL_1_MID_LEFT.GTPE2.GEARBOX_MODE[1] origin:064-gtp-channel-conf 01_224 -GTP_CHANNEL_1_MID_LEFT.GTPE2.GEARBOX_MODE[2] origin:064-gtp-channel-conf 00_225 -GTP_CHANNEL_1_MID_LEFT.GTPE2.IN_USE origin:064-gtp-channel-conf 00_00 00_01 00_47 00_52 00_53 00_65 01_01 01_47 02_129 -GTP_CHANNEL_1_MID_LEFT.GTPE2.LOOPBACK_CFG[0] origin:064-gtp-channel-conf 02_20 -GTP_CHANNEL_1_MID_LEFT.GTPE2.OUTREFCLK_SEL_INV[0] origin:064-gtp-channel-conf 00_149 -GTP_CHANNEL_1_MID_LEFT.GTPE2.OUTREFCLK_SEL_INV[1] origin:064-gtp-channel-conf 01_149 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PCS_PCIE_EN origin:064-gtp-channel-conf 00_216 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PCS_RSVD_ATTR[0] origin:064-gtp-channel-conf 02_184 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PCS_RSVD_ATTR[1] origin:064-gtp-channel-conf 03_184 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PCS_RSVD_ATTR[2] origin:064-gtp-channel-conf 02_185 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PCS_RSVD_ATTR[3] origin:064-gtp-channel-conf 03_185 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PCS_RSVD_ATTR[4] origin:064-gtp-channel-conf 02_186 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PCS_RSVD_ATTR[5] origin:064-gtp-channel-conf 03_186 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PCS_RSVD_ATTR[6] origin:064-gtp-channel-conf 02_187 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PCS_RSVD_ATTR[7] origin:064-gtp-channel-conf 03_187 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PCS_RSVD_ATTR[8] origin:064-gtp-channel-conf 02_188 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PCS_RSVD_ATTR[9] origin:064-gtp-channel-conf 03_188 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PCS_RSVD_ATTR[10] origin:064-gtp-channel-conf 02_189 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PCS_RSVD_ATTR[11] origin:064-gtp-channel-conf 03_189 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PCS_RSVD_ATTR[12] origin:064-gtp-channel-conf 02_190 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PCS_RSVD_ATTR[13] origin:064-gtp-channel-conf 03_190 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PCS_RSVD_ATTR[14] origin:064-gtp-channel-conf 02_191 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PCS_RSVD_ATTR[15] origin:064-gtp-channel-conf 03_191 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PCS_RSVD_ATTR[16] origin:064-gtp-channel-conf 02_192 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PCS_RSVD_ATTR[17] origin:064-gtp-channel-conf 03_192 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PCS_RSVD_ATTR[18] origin:064-gtp-channel-conf 02_193 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PCS_RSVD_ATTR[19] origin:064-gtp-channel-conf 03_193 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PCS_RSVD_ATTR[20] origin:064-gtp-channel-conf 02_194 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PCS_RSVD_ATTR[21] origin:064-gtp-channel-conf 03_194 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PCS_RSVD_ATTR[22] origin:064-gtp-channel-conf 02_195 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PCS_RSVD_ATTR[23] origin:064-gtp-channel-conf 03_195 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PCS_RSVD_ATTR[24] origin:064-gtp-channel-conf 02_196 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PCS_RSVD_ATTR[25] origin:064-gtp-channel-conf 03_196 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PCS_RSVD_ATTR[26] origin:064-gtp-channel-conf 02_197 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PCS_RSVD_ATTR[27] origin:064-gtp-channel-conf 03_197 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PCS_RSVD_ATTR[28] origin:064-gtp-channel-conf 02_198 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PCS_RSVD_ATTR[29] origin:064-gtp-channel-conf 03_198 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PCS_RSVD_ATTR[30] origin:064-gtp-channel-conf 02_199 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PCS_RSVD_ATTR[31] origin:064-gtp-channel-conf 03_199 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PCS_RSVD_ATTR[32] origin:064-gtp-channel-conf 02_200 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PCS_RSVD_ATTR[33] origin:064-gtp-channel-conf 03_200 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PCS_RSVD_ATTR[34] origin:064-gtp-channel-conf 02_201 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PCS_RSVD_ATTR[35] origin:064-gtp-channel-conf 03_201 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PCS_RSVD_ATTR[36] origin:064-gtp-channel-conf 02_202 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PCS_RSVD_ATTR[37] origin:064-gtp-channel-conf 03_202 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PCS_RSVD_ATTR[38] origin:064-gtp-channel-conf 02_203 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PCS_RSVD_ATTR[39] origin:064-gtp-channel-conf 03_203 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PCS_RSVD_ATTR[40] origin:064-gtp-channel-conf 02_204 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PCS_RSVD_ATTR[41] origin:064-gtp-channel-conf 03_204 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PCS_RSVD_ATTR[42] origin:064-gtp-channel-conf 02_205 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PCS_RSVD_ATTR[43] origin:064-gtp-channel-conf 03_205 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PCS_RSVD_ATTR[44] origin:064-gtp-channel-conf 02_206 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PCS_RSVD_ATTR[45] origin:064-gtp-channel-conf 03_206 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PCS_RSVD_ATTR[46] origin:064-gtp-channel-conf 02_207 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PCS_RSVD_ATTR[47] origin:064-gtp-channel-conf 03_207 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PD_TRANS_TIME_FROM_P2[0] origin:064-gtp-channel-conf 01_216 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PD_TRANS_TIME_FROM_P2[1] origin:064-gtp-channel-conf 00_217 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PD_TRANS_TIME_FROM_P2[2] origin:064-gtp-channel-conf 01_217 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PD_TRANS_TIME_FROM_P2[3] origin:064-gtp-channel-conf 00_218 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PD_TRANS_TIME_FROM_P2[4] origin:064-gtp-channel-conf 01_218 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PD_TRANS_TIME_FROM_P2[5] origin:064-gtp-channel-conf 00_219 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PD_TRANS_TIME_FROM_P2[6] origin:064-gtp-channel-conf 01_219 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PD_TRANS_TIME_FROM_P2[7] origin:064-gtp-channel-conf 00_220 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PD_TRANS_TIME_FROM_P2[8] origin:064-gtp-channel-conf 01_220 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PD_TRANS_TIME_FROM_P2[9] origin:064-gtp-channel-conf 00_221 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PD_TRANS_TIME_FROM_P2[10] origin:064-gtp-channel-conf 01_221 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PD_TRANS_TIME_FROM_P2[11] origin:064-gtp-channel-conf 00_222 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PD_TRANS_TIME_NONE_P2[0] origin:064-gtp-channel-conf 00_208 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PD_TRANS_TIME_NONE_P2[1] origin:064-gtp-channel-conf 01_208 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PD_TRANS_TIME_NONE_P2[2] origin:064-gtp-channel-conf 00_209 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PD_TRANS_TIME_NONE_P2[3] origin:064-gtp-channel-conf 01_209 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PD_TRANS_TIME_NONE_P2[4] origin:064-gtp-channel-conf 00_210 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PD_TRANS_TIME_NONE_P2[5] origin:064-gtp-channel-conf 01_210 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PD_TRANS_TIME_NONE_P2[6] origin:064-gtp-channel-conf 00_211 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PD_TRANS_TIME_NONE_P2[7] origin:064-gtp-channel-conf 01_211 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PD_TRANS_TIME_TO_P2[0] origin:064-gtp-channel-conf 00_212 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PD_TRANS_TIME_TO_P2[1] origin:064-gtp-channel-conf 01_212 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PD_TRANS_TIME_TO_P2[2] origin:064-gtp-channel-conf 00_213 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PD_TRANS_TIME_TO_P2[3] origin:064-gtp-channel-conf 01_213 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PD_TRANS_TIME_TO_P2[4] origin:064-gtp-channel-conf 00_214 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PD_TRANS_TIME_TO_P2[5] origin:064-gtp-channel-conf 01_214 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PD_TRANS_TIME_TO_P2[6] origin:064-gtp-channel-conf 00_215 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PD_TRANS_TIME_TO_P2[7] origin:064-gtp-channel-conf 01_215 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PMA_LOOPBACK_CFG[0] origin:064-gtp-channel-conf 01_207 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PMA_RSV[0] origin:064-gtp-channel-conf 02_520 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PMA_RSV[1] origin:064-gtp-channel-conf 03_520 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PMA_RSV[2] origin:064-gtp-channel-conf 02_521 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PMA_RSV[3] origin:064-gtp-channel-conf 03_521 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PMA_RSV[4] origin:064-gtp-channel-conf 02_522 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PMA_RSV[5] origin:064-gtp-channel-conf 03_522 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PMA_RSV[6] origin:064-gtp-channel-conf 02_523 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PMA_RSV[7] origin:064-gtp-channel-conf 03_523 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PMA_RSV[8] origin:064-gtp-channel-conf 02_524 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PMA_RSV[9] origin:064-gtp-channel-conf 03_524 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PMA_RSV[10] origin:064-gtp-channel-conf 02_525 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PMA_RSV[11] origin:064-gtp-channel-conf 03_525 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PMA_RSV[12] origin:064-gtp-channel-conf 02_526 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PMA_RSV[13] origin:064-gtp-channel-conf 03_526 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PMA_RSV[14] origin:064-gtp-channel-conf 02_527 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PMA_RSV[15] origin:064-gtp-channel-conf 03_527 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PMA_RSV[16] origin:064-gtp-channel-conf 02_528 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PMA_RSV[17] origin:064-gtp-channel-conf 03_528 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PMA_RSV[18] origin:064-gtp-channel-conf 02_529 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PMA_RSV[19] origin:064-gtp-channel-conf 03_529 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PMA_RSV[20] origin:064-gtp-channel-conf 02_530 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PMA_RSV[21] origin:064-gtp-channel-conf 03_530 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PMA_RSV[22] origin:064-gtp-channel-conf 02_531 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PMA_RSV[23] origin:064-gtp-channel-conf 03_531 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PMA_RSV[24] origin:064-gtp-channel-conf 02_532 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PMA_RSV[25] origin:064-gtp-channel-conf 03_532 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PMA_RSV[26] origin:064-gtp-channel-conf 02_533 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PMA_RSV[27] origin:064-gtp-channel-conf 03_533 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PMA_RSV[28] origin:064-gtp-channel-conf 02_534 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PMA_RSV[29] origin:064-gtp-channel-conf 03_534 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PMA_RSV[30] origin:064-gtp-channel-conf 02_535 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PMA_RSV[31] origin:064-gtp-channel-conf 03_535 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PMA_RSV2[0] origin:064-gtp-channel-conf 02_336 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PMA_RSV2[1] origin:064-gtp-channel-conf 03_336 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PMA_RSV2[2] origin:064-gtp-channel-conf 02_337 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PMA_RSV2[3] origin:064-gtp-channel-conf 03_337 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PMA_RSV2[4] origin:064-gtp-channel-conf 02_338 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PMA_RSV2[5] origin:064-gtp-channel-conf 03_338 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PMA_RSV2[6] origin:064-gtp-channel-conf 02_339 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PMA_RSV2[7] origin:064-gtp-channel-conf 03_339 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PMA_RSV2[8] origin:064-gtp-channel-conf 02_340 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PMA_RSV2[9] origin:064-gtp-channel-conf 03_340 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PMA_RSV2[10] origin:064-gtp-channel-conf 02_341 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PMA_RSV2[11] origin:064-gtp-channel-conf 03_341 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PMA_RSV2[12] origin:064-gtp-channel-conf 02_342 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PMA_RSV2[13] origin:064-gtp-channel-conf 03_342 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PMA_RSV2[14] origin:064-gtp-channel-conf 02_343 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PMA_RSV2[15] origin:064-gtp-channel-conf 03_343 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PMA_RSV2[16] origin:064-gtp-channel-conf 02_344 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PMA_RSV2[17] origin:064-gtp-channel-conf 03_344 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PMA_RSV2[18] origin:064-gtp-channel-conf 02_345 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PMA_RSV2[19] origin:064-gtp-channel-conf 03_345 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PMA_RSV2[20] origin:064-gtp-channel-conf 02_346 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PMA_RSV2[21] origin:064-gtp-channel-conf 03_346 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PMA_RSV2[22] origin:064-gtp-channel-conf 02_347 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PMA_RSV2[23] origin:064-gtp-channel-conf 03_347 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PMA_RSV2[24] origin:064-gtp-channel-conf 02_348 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PMA_RSV2[25] origin:064-gtp-channel-conf 03_348 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PMA_RSV2[26] origin:064-gtp-channel-conf 02_349 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PMA_RSV2[27] origin:064-gtp-channel-conf 03_349 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PMA_RSV2[28] origin:064-gtp-channel-conf 02_350 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PMA_RSV2[29] origin:064-gtp-channel-conf 03_350 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PMA_RSV2[30] origin:064-gtp-channel-conf 02_351 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PMA_RSV2[31] origin:064-gtp-channel-conf 03_351 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PMA_RSV3[0] origin:064-gtp-channel-conf 02_288 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PMA_RSV3[1] origin:064-gtp-channel-conf 03_288 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PMA_RSV4[0] origin:064-gtp-channel-conf 02_156 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PMA_RSV4[1] origin:064-gtp-channel-conf 03_156 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PMA_RSV4[2] origin:064-gtp-channel-conf 02_157 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PMA_RSV4[3] origin:064-gtp-channel-conf 03_157 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PMA_RSV5[0] origin:064-gtp-channel-conf 03_159 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PMA_RSV6[0] origin:064-gtp-channel-conf 02_303 -GTP_CHANNEL_1_MID_LEFT.GTPE2.PMA_RSV7[0] origin:064-gtp-channel-conf 03_303 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_BIAS_CFG[0] origin:064-gtp-channel-conf 02_112 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_BIAS_CFG[1] origin:064-gtp-channel-conf 03_112 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_BIAS_CFG[2] origin:064-gtp-channel-conf 02_113 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_BIAS_CFG[3] origin:064-gtp-channel-conf 03_113 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_BIAS_CFG[4] origin:064-gtp-channel-conf 02_114 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_BIAS_CFG[5] origin:064-gtp-channel-conf 03_114 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_BIAS_CFG[6] origin:064-gtp-channel-conf 02_115 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_BIAS_CFG[7] origin:064-gtp-channel-conf 03_115 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_BIAS_CFG[8] origin:064-gtp-channel-conf 02_116 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_BIAS_CFG[9] origin:064-gtp-channel-conf 03_116 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_BIAS_CFG[10] origin:064-gtp-channel-conf 02_117 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_BIAS_CFG[11] origin:064-gtp-channel-conf 03_117 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_BIAS_CFG[12] origin:064-gtp-channel-conf 02_118 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_BIAS_CFG[13] origin:064-gtp-channel-conf 03_118 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_BIAS_CFG[14] origin:064-gtp-channel-conf 02_119 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_BIAS_CFG[15] origin:064-gtp-channel-conf 03_119 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_BUFFER_CFG[0] origin:064-gtp-channel-conf 02_536 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_BUFFER_CFG[1] origin:064-gtp-channel-conf 03_536 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_BUFFER_CFG[2] origin:064-gtp-channel-conf 02_537 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_BUFFER_CFG[3] origin:064-gtp-channel-conf 03_537 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_BUFFER_CFG[4] origin:064-gtp-channel-conf 02_538 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_BUFFER_CFG[5] origin:064-gtp-channel-conf 03_538 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_CLKMUX_EN[0] origin:064-gtp-channel-conf 02_128 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_CM_SEL[0] origin:064-gtp-channel-conf 00_138 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_CM_SEL[1] origin:064-gtp-channel-conf 01_138 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_CM_TRIM[0] origin:064-gtp-channel-conf 02_304 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_CM_TRIM[1] origin:064-gtp-channel-conf 03_304 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_CM_TRIM[2] origin:064-gtp-channel-conf 02_305 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_CM_TRIM[3] origin:064-gtp-channel-conf 03_305 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_DATA_WIDTH[0] origin:064-gtp-channel-conf 01_141 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_DATA_WIDTH[1] origin:064-gtp-channel-conf 00_142 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_DATA_WIDTH[2] origin:064-gtp-channel-conf 01_142 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_DDI_SEL[0] origin:064-gtp-channel-conf 00_696 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_DDI_SEL[1] origin:064-gtp-channel-conf 01_696 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_DDI_SEL[2] origin:064-gtp-channel-conf 00_697 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_DDI_SEL[3] origin:064-gtp-channel-conf 01_697 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_DDI_SEL[4] origin:064-gtp-channel-conf 00_698 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_DDI_SEL[5] origin:064-gtp-channel-conf 01_698 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_DEBUG_CFG[0] origin:064-gtp-channel-conf 02_616 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_DEBUG_CFG[1] origin:064-gtp-channel-conf 03_616 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_DEBUG_CFG[2] origin:064-gtp-channel-conf 02_617 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_DEBUG_CFG[3] origin:064-gtp-channel-conf 03_617 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_DEBUG_CFG[4] origin:064-gtp-channel-conf 02_618 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_DEBUG_CFG[5] origin:064-gtp-channel-conf 03_618 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_DEBUG_CFG[6] origin:064-gtp-channel-conf 02_619 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_DEBUG_CFG[7] origin:064-gtp-channel-conf 03_619 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_DEBUG_CFG[8] origin:064-gtp-channel-conf 02_620 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_DEBUG_CFG[9] origin:064-gtp-channel-conf 03_620 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_DEBUG_CFG[10] origin:064-gtp-channel-conf 02_621 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_DEBUG_CFG[11] origin:064-gtp-channel-conf 03_621 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_DEBUG_CFG[12] origin:064-gtp-channel-conf 02_622 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_DEBUG_CFG[13] origin:064-gtp-channel-conf 03_622 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_DEFER_RESET_BUF_EN origin:064-gtp-channel-conf 02_552 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_DISPERR_SEQ_MATCH origin:064-gtp-channel-conf 01_495 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_OS_CFG[0] origin:064-gtp-channel-conf 00_288 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_OS_CFG[1] origin:064-gtp-channel-conf 01_288 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_OS_CFG[2] origin:064-gtp-channel-conf 00_289 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_OS_CFG[3] origin:064-gtp-channel-conf 01_289 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_OS_CFG[4] origin:064-gtp-channel-conf 00_290 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_OS_CFG[5] origin:064-gtp-channel-conf 01_290 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_OS_CFG[6] origin:064-gtp-channel-conf 00_291 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_OS_CFG[7] origin:064-gtp-channel-conf 01_291 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_OS_CFG[8] origin:064-gtp-channel-conf 00_292 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_OS_CFG[9] origin:064-gtp-channel-conf 01_292 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_OS_CFG[10] origin:064-gtp-channel-conf 00_293 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_OS_CFG[11] origin:064-gtp-channel-conf 01_293 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_OS_CFG[12] origin:064-gtp-channel-conf 00_294 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_SIG_VALID_DLY[0] origin:064-gtp-channel-conf 00_524 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_SIG_VALID_DLY[1] origin:064-gtp-channel-conf 01_524 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_SIG_VALID_DLY[2] origin:064-gtp-channel-conf 00_525 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_SIG_VALID_DLY[3] origin:064-gtp-channel-conf 01_525 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_SIG_VALID_DLY[4] origin:064-gtp-channel-conf 00_526 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_XCLK_SEL.RXUSR origin:064-gtp-channel-conf 00_143 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_CLK25_DIV[0] origin:064-gtp-channel-conf 00_139 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_CLK25_DIV[1] origin:064-gtp-channel-conf 01_139 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_CLK25_DIV[2] origin:064-gtp-channel-conf 00_140 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_CLK25_DIV[3] origin:064-gtp-channel-conf 01_140 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RX_CLK25_DIV[4] origin:064-gtp-channel-conf 00_141 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXBUF_ADDR_MODE.FAST origin:064-gtp-channel-conf 03_555 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXBUF_EIDLE_HI_CNT[0] origin:064-gtp-channel-conf 02_558 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXBUF_EIDLE_HI_CNT[1] origin:064-gtp-channel-conf 03_558 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXBUF_EIDLE_HI_CNT[2] origin:064-gtp-channel-conf 02_559 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXBUF_EIDLE_HI_CNT[3] origin:064-gtp-channel-conf 03_559 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXBUF_EIDLE_LO_CNT[0] origin:064-gtp-channel-conf 02_556 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXBUF_EIDLE_LO_CNT[1] origin:064-gtp-channel-conf 03_556 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXBUF_EIDLE_LO_CNT[2] origin:064-gtp-channel-conf 02_557 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXBUF_EIDLE_LO_CNT[3] origin:064-gtp-channel-conf 03_557 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXBUF_EN origin:064-gtp-channel-conf 02_11 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXBUF_RESET_ON_CB_CHANGE origin:064-gtp-channel-conf 02_560 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXBUF_RESET_ON_COMMAALIGN origin:064-gtp-channel-conf 02_561 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXBUF_RESET_ON_EIDLE origin:064-gtp-channel-conf 02_547 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXBUF_RESET_ON_RATE_CHANGE origin:064-gtp-channel-conf 03_560 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXBUF_THRESH_OVFLW[0] origin:064-gtp-channel-conf 03_552 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXBUF_THRESH_OVFLW[1] origin:064-gtp-channel-conf 02_553 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXBUF_THRESH_OVFLW[2] origin:064-gtp-channel-conf 03_553 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXBUF_THRESH_OVFLW[3] origin:064-gtp-channel-conf 02_554 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXBUF_THRESH_OVFLW[4] origin:064-gtp-channel-conf 03_554 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXBUF_THRESH_OVFLW[5] origin:064-gtp-channel-conf 02_555 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXBUF_THRESH_OVRD origin:064-gtp-channel-conf 02_548 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXBUF_THRESH_UNDFLW[0] origin:064-gtp-channel-conf 02_544 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXBUF_THRESH_UNDFLW[1] origin:064-gtp-channel-conf 03_544 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXBUF_THRESH_UNDFLW[2] origin:064-gtp-channel-conf 02_545 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXBUF_THRESH_UNDFLW[3] origin:064-gtp-channel-conf 03_545 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXBUF_THRESH_UNDFLW[4] origin:064-gtp-channel-conf 02_546 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXBUF_THRESH_UNDFLW[5] origin:064-gtp-channel-conf 03_546 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXBUFRESET_TIME[0] origin:064-gtp-channel-conf 01_101 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXBUFRESET_TIME[1] origin:064-gtp-channel-conf 00_102 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXBUFRESET_TIME[2] origin:064-gtp-channel-conf 01_102 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXBUFRESET_TIME[3] origin:064-gtp-channel-conf 00_103 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXBUFRESET_TIME[4] origin:064-gtp-channel-conf 01_103 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[0] origin:064-gtp-channel-conf 02_640 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[1] origin:064-gtp-channel-conf 03_640 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[2] origin:064-gtp-channel-conf 02_641 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[3] origin:064-gtp-channel-conf 03_641 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[4] origin:064-gtp-channel-conf 02_642 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[5] origin:064-gtp-channel-conf 03_642 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[6] origin:064-gtp-channel-conf 02_643 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[7] origin:064-gtp-channel-conf 03_643 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[8] origin:064-gtp-channel-conf 02_644 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[9] origin:064-gtp-channel-conf 03_644 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[10] origin:064-gtp-channel-conf 02_645 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[11] origin:064-gtp-channel-conf 03_645 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[12] origin:064-gtp-channel-conf 02_646 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[13] origin:064-gtp-channel-conf 03_646 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[14] origin:064-gtp-channel-conf 02_647 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[15] origin:064-gtp-channel-conf 03_647 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[16] origin:064-gtp-channel-conf 02_648 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[17] origin:064-gtp-channel-conf 03_648 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[18] origin:064-gtp-channel-conf 02_649 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[19] origin:064-gtp-channel-conf 03_649 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[20] origin:064-gtp-channel-conf 02_650 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[21] origin:064-gtp-channel-conf 03_650 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[22] origin:064-gtp-channel-conf 02_651 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[23] origin:064-gtp-channel-conf 03_651 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[24] origin:064-gtp-channel-conf 02_652 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[25] origin:064-gtp-channel-conf 03_652 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[26] origin:064-gtp-channel-conf 02_653 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[27] origin:064-gtp-channel-conf 03_653 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[28] origin:064-gtp-channel-conf 02_654 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[29] origin:064-gtp-channel-conf 03_654 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[30] origin:064-gtp-channel-conf 02_655 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[31] origin:064-gtp-channel-conf 03_655 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[32] origin:064-gtp-channel-conf 02_656 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[33] origin:064-gtp-channel-conf 03_656 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[34] origin:064-gtp-channel-conf 02_657 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[35] origin:064-gtp-channel-conf 03_657 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[36] origin:064-gtp-channel-conf 02_658 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[37] origin:064-gtp-channel-conf 03_658 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[38] origin:064-gtp-channel-conf 02_659 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[39] origin:064-gtp-channel-conf 03_659 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[40] origin:064-gtp-channel-conf 02_660 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[41] origin:064-gtp-channel-conf 03_660 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[42] origin:064-gtp-channel-conf 02_661 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[43] origin:064-gtp-channel-conf 03_661 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[44] origin:064-gtp-channel-conf 02_662 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[45] origin:064-gtp-channel-conf 03_662 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[46] origin:064-gtp-channel-conf 02_663 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[47] origin:064-gtp-channel-conf 03_663 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[48] origin:064-gtp-channel-conf 02_664 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[49] origin:064-gtp-channel-conf 03_664 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[50] origin:064-gtp-channel-conf 02_665 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[51] origin:064-gtp-channel-conf 03_665 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[52] origin:064-gtp-channel-conf 02_666 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[53] origin:064-gtp-channel-conf 03_666 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[54] origin:064-gtp-channel-conf 02_667 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[55] origin:064-gtp-channel-conf 03_667 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[56] origin:064-gtp-channel-conf 02_668 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[57] origin:064-gtp-channel-conf 03_668 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[58] origin:064-gtp-channel-conf 02_669 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[59] origin:064-gtp-channel-conf 03_669 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[60] origin:064-gtp-channel-conf 02_670 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[61] origin:064-gtp-channel-conf 03_670 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[62] origin:064-gtp-channel-conf 02_671 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[63] origin:064-gtp-channel-conf 03_671 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[64] origin:064-gtp-channel-conf 02_672 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[65] origin:064-gtp-channel-conf 03_672 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[66] origin:064-gtp-channel-conf 02_673 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[67] origin:064-gtp-channel-conf 03_673 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[68] origin:064-gtp-channel-conf 02_674 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[69] origin:064-gtp-channel-conf 03_674 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[70] origin:064-gtp-channel-conf 02_675 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[71] origin:064-gtp-channel-conf 03_675 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[72] origin:064-gtp-channel-conf 02_676 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[73] origin:064-gtp-channel-conf 03_676 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[74] origin:064-gtp-channel-conf 02_677 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[75] origin:064-gtp-channel-conf 03_677 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[76] origin:064-gtp-channel-conf 02_678 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[77] origin:064-gtp-channel-conf 03_678 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[78] origin:064-gtp-channel-conf 02_679 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[79] origin:064-gtp-channel-conf 03_679 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[80] origin:064-gtp-channel-conf 02_680 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[81] origin:064-gtp-channel-conf 03_680 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_CFG[82] origin:064-gtp-channel-conf 02_681 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_FR_RESET_ON_EIDLE[0] origin:064-gtp-channel-conf 02_638 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_HOLD_DURING_EIDLE[0] origin:064-gtp-channel-conf 03_637 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_LOCK_CFG[0] origin:064-gtp-channel-conf 02_632 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_LOCK_CFG[1] origin:064-gtp-channel-conf 03_632 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_LOCK_CFG[2] origin:064-gtp-channel-conf 02_633 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_LOCK_CFG[3] origin:064-gtp-channel-conf 03_633 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_LOCK_CFG[4] origin:064-gtp-channel-conf 02_634 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_LOCK_CFG[5] origin:064-gtp-channel-conf 03_634 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDR_PH_RESET_ON_EIDLE[0] origin:064-gtp-channel-conf 03_638 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDRFREQRESET_TIME[0] origin:064-gtp-channel-conf 01_106 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDRFREQRESET_TIME[1] origin:064-gtp-channel-conf 00_107 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDRFREQRESET_TIME[2] origin:064-gtp-channel-conf 01_107 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDRFREQRESET_TIME[3] origin:064-gtp-channel-conf 00_108 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDRFREQRESET_TIME[4] origin:064-gtp-channel-conf 01_108 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDRPHRESET_TIME[0] origin:064-gtp-channel-conf 00_109 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDRPHRESET_TIME[1] origin:064-gtp-channel-conf 01_109 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDRPHRESET_TIME[2] origin:064-gtp-channel-conf 00_110 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDRPHRESET_TIME[3] origin:064-gtp-channel-conf 01_110 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXCDRPHRESET_TIME[4] origin:064-gtp-channel-conf 00_111 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXDLY_CFG[0] origin:064-gtp-channel-conf 00_680 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXDLY_CFG[1] origin:064-gtp-channel-conf 01_680 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXDLY_CFG[2] origin:064-gtp-channel-conf 00_681 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXDLY_CFG[3] origin:064-gtp-channel-conf 01_681 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXDLY_CFG[4] origin:064-gtp-channel-conf 00_682 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXDLY_CFG[5] origin:064-gtp-channel-conf 01_682 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXDLY_CFG[6] origin:064-gtp-channel-conf 00_683 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXDLY_CFG[7] origin:064-gtp-channel-conf 01_683 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXDLY_CFG[8] origin:064-gtp-channel-conf 00_684 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXDLY_CFG[9] origin:064-gtp-channel-conf 01_684 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXDLY_CFG[10] origin:064-gtp-channel-conf 00_685 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXDLY_CFG[11] origin:064-gtp-channel-conf 01_685 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXDLY_CFG[12] origin:064-gtp-channel-conf 00_686 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXDLY_CFG[13] origin:064-gtp-channel-conf 01_686 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXDLY_CFG[14] origin:064-gtp-channel-conf 00_687 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXDLY_CFG[15] origin:064-gtp-channel-conf 01_687 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXDLY_LCFG[0] origin:064-gtp-channel-conf 02_576 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXDLY_LCFG[1] origin:064-gtp-channel-conf 03_576 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXDLY_LCFG[2] origin:064-gtp-channel-conf 02_577 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXDLY_LCFG[3] origin:064-gtp-channel-conf 03_577 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXDLY_LCFG[4] origin:064-gtp-channel-conf 02_578 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXDLY_LCFG[5] origin:064-gtp-channel-conf 03_578 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXDLY_LCFG[6] origin:064-gtp-channel-conf 02_579 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXDLY_LCFG[7] origin:064-gtp-channel-conf 03_579 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXDLY_LCFG[8] origin:064-gtp-channel-conf 02_580 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXDLY_TAP_CFG[0] origin:064-gtp-channel-conf 00_672 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXDLY_TAP_CFG[1] origin:064-gtp-channel-conf 01_672 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXDLY_TAP_CFG[2] origin:064-gtp-channel-conf 00_673 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXDLY_TAP_CFG[3] origin:064-gtp-channel-conf 01_673 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXDLY_TAP_CFG[4] origin:064-gtp-channel-conf 00_674 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXDLY_TAP_CFG[5] origin:064-gtp-channel-conf 01_674 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXDLY_TAP_CFG[6] origin:064-gtp-channel-conf 00_675 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXDLY_TAP_CFG[7] origin:064-gtp-channel-conf 01_675 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXDLY_TAP_CFG[8] origin:064-gtp-channel-conf 00_676 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXDLY_TAP_CFG[9] origin:064-gtp-channel-conf 01_676 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXDLY_TAP_CFG[10] origin:064-gtp-channel-conf 00_677 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXDLY_TAP_CFG[11] origin:064-gtp-channel-conf 01_677 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXDLY_TAP_CFG[12] origin:064-gtp-channel-conf 00_678 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXDLY_TAP_CFG[13] origin:064-gtp-channel-conf 01_678 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXDLY_TAP_CFG[14] origin:064-gtp-channel-conf 00_679 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXDLY_TAP_CFG[15] origin:064-gtp-channel-conf 01_679 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXGEARBOX_EN origin:064-gtp-channel-conf 01_607 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXISCANRESET_TIME[0] origin:064-gtp-channel-conf 01_123 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXISCANRESET_TIME[1] origin:064-gtp-channel-conf 00_124 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXISCANRESET_TIME[2] origin:064-gtp-channel-conf 01_124 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXISCANRESET_TIME[3] origin:064-gtp-channel-conf 00_125 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXISCANRESET_TIME[4] origin:064-gtp-channel-conf 01_125 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPM_BIAS_STARTUP_DISABLE[0] origin:064-gtp-channel-conf 03_391 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPM_CFG[0] origin:064-gtp-channel-conf 02_328 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPM_CFG[1] origin:064-gtp-channel-conf 03_328 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPM_CFG[2] origin:064-gtp-channel-conf 02_329 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPM_CFG[3] origin:064-gtp-channel-conf 03_329 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPM_CM_CFG[0] origin:064-gtp-channel-conf 02_430 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPM_GC_CFG[0] origin:064-gtp-channel-conf 02_432 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPM_GC_CFG[1] origin:064-gtp-channel-conf 03_432 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPM_GC_CFG[2] origin:064-gtp-channel-conf 02_433 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPM_GC_CFG[3] origin:064-gtp-channel-conf 03_433 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPM_GC_CFG[4] origin:064-gtp-channel-conf 02_434 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPM_GC_CFG[5] origin:064-gtp-channel-conf 03_434 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPM_GC_CFG[6] origin:064-gtp-channel-conf 02_435 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPM_GC_CFG[7] origin:064-gtp-channel-conf 03_435 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPM_GC_CFG[8] origin:064-gtp-channel-conf 02_436 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPM_GC_CFG2[0] origin:064-gtp-channel-conf 03_442 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPM_GC_CFG2[1] origin:064-gtp-channel-conf 02_443 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPM_GC_CFG2[2] origin:064-gtp-channel-conf 03_443 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPM_HF_CFG[0] origin:064-gtp-channel-conf 00_336 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPM_HF_CFG[1] origin:064-gtp-channel-conf 01_336 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPM_HF_CFG[2] origin:064-gtp-channel-conf 00_337 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPM_HF_CFG[3] origin:064-gtp-channel-conf 01_337 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPM_HF_CFG[4] origin:064-gtp-channel-conf 00_338 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPM_HF_CFG[5] origin:064-gtp-channel-conf 01_338 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPM_HF_CFG[6] origin:064-gtp-channel-conf 00_339 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPM_HF_CFG[7] origin:064-gtp-channel-conf 01_339 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPM_HF_CFG[8] origin:064-gtp-channel-conf 00_340 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPM_HF_CFG[9] origin:064-gtp-channel-conf 01_340 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPM_HF_CFG[10] origin:064-gtp-channel-conf 00_341 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPM_HF_CFG[11] origin:064-gtp-channel-conf 01_341 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPM_HF_CFG[12] origin:064-gtp-channel-conf 00_342 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPM_HF_CFG[13] origin:064-gtp-channel-conf 01_342 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPM_HF_CFG2[0] origin:064-gtp-channel-conf 02_424 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPM_HF_CFG2[1] origin:064-gtp-channel-conf 03_424 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPM_HF_CFG2[2] origin:064-gtp-channel-conf 02_425 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPM_HF_CFG2[3] origin:064-gtp-channel-conf 03_425 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPM_HF_CFG2[4] origin:064-gtp-channel-conf 02_426 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPM_HF_CFG3[0] origin:064-gtp-channel-conf 03_389 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPM_HF_CFG3[1] origin:064-gtp-channel-conf 02_390 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPM_HF_CFG3[2] origin:064-gtp-channel-conf 03_390 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPM_HF_CFG3[3] origin:064-gtp-channel-conf 02_391 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPM_HOLD_DURING_EIDLE[0] origin:064-gtp-channel-conf 00_247 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPM_INCM_CFG[0] origin:064-gtp-channel-conf 02_439 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPM_IPCM_CFG[0] origin:064-gtp-channel-conf 03_439 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPM_LF_CFG[0] origin:064-gtp-channel-conf 00_344 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPM_LF_CFG[1] origin:064-gtp-channel-conf 01_344 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPM_LF_CFG[2] origin:064-gtp-channel-conf 00_345 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPM_LF_CFG[3] origin:064-gtp-channel-conf 01_345 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPM_LF_CFG[4] origin:064-gtp-channel-conf 00_346 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPM_LF_CFG[5] origin:064-gtp-channel-conf 01_346 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPM_LF_CFG[6] origin:064-gtp-channel-conf 00_347 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPM_LF_CFG[7] origin:064-gtp-channel-conf 01_347 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPM_LF_CFG[8] origin:064-gtp-channel-conf 00_348 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPM_LF_CFG[9] origin:064-gtp-channel-conf 01_348 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPM_LF_CFG[10] origin:064-gtp-channel-conf 00_349 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPM_LF_CFG[11] origin:064-gtp-channel-conf 01_349 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPM_LF_CFG[12] origin:064-gtp-channel-conf 00_350 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPM_LF_CFG[13] origin:064-gtp-channel-conf 01_350 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPM_LF_CFG[14] origin:064-gtp-channel-conf 00_351 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPM_LF_CFG[15] origin:064-gtp-channel-conf 01_351 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPM_LF_CFG[16] origin:064-gtp-channel-conf 00_343 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPM_LF_CFG[17] origin:064-gtp-channel-conf 01_343 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPM_LF_CFG2[0] origin:064-gtp-channel-conf 03_426 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPM_LF_CFG2[1] origin:064-gtp-channel-conf 02_427 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPM_LF_CFG2[2] origin:064-gtp-channel-conf 03_427 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPM_LF_CFG2[3] origin:064-gtp-channel-conf 02_428 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPM_LF_CFG2[4] origin:064-gtp-channel-conf 03_428 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPM_OSINT_CFG[0] origin:064-gtp-channel-conf 02_440 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPM_OSINT_CFG[1] origin:064-gtp-channel-conf 03_440 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPM_OSINT_CFG[2] origin:064-gtp-channel-conf 02_441 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPM_CFG1[0] origin:064-gtp-channel-conf 02_330 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPMRESET_TIME[0] origin:064-gtp-channel-conf 00_112 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPMRESET_TIME[1] origin:064-gtp-channel-conf 01_112 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPMRESET_TIME[2] origin:064-gtp-channel-conf 00_113 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPMRESET_TIME[3] origin:064-gtp-channel-conf 01_113 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPMRESET_TIME[4] origin:064-gtp-channel-conf 00_114 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPMRESET_TIME[5] origin:064-gtp-channel-conf 01_114 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXLPMRESET_TIME[6] origin:064-gtp-channel-conf 00_115 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXOOB_CFG[0] origin:064-gtp-channel-conf 00_144 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXOOB_CFG[1] origin:064-gtp-channel-conf 01_144 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXOOB_CFG[2] origin:064-gtp-channel-conf 00_145 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXOOB_CFG[3] origin:064-gtp-channel-conf 01_145 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXOOB_CFG[4] origin:064-gtp-channel-conf 00_146 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXOOB_CFG[5] origin:064-gtp-channel-conf 01_146 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXOOB_CFG[6] origin:064-gtp-channel-conf 00_147 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXOOB_CLK_CFG.FABRIC origin:064-gtp-channel-conf 03_129 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXOSCALRESET_TIME[0] origin:064-gtp-channel-conf 00_187 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXOSCALRESET_TIME[1] origin:064-gtp-channel-conf 01_187 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXOSCALRESET_TIME[2] origin:064-gtp-channel-conf 00_188 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXOSCALRESET_TIME[3] origin:064-gtp-channel-conf 01_188 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXOSCALRESET_TIME[4] origin:064-gtp-channel-conf 00_189 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXOSCALRESET_TIMEOUT[0] origin:064-gtp-channel-conf 01_189 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXOSCALRESET_TIMEOUT[1] origin:064-gtp-channel-conf 00_190 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXOSCALRESET_TIMEOUT[2] origin:064-gtp-channel-conf 01_190 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXOSCALRESET_TIMEOUT[3] origin:064-gtp-channel-conf 00_191 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXOSCALRESET_TIMEOUT[4] origin:064-gtp-channel-conf 01_191 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXOUT_DIV[0] origin:064-gtp-channel-conf 02_384 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXOUT_DIV[1] origin:064-gtp-channel-conf 03_384 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXPCSRESET_TIME[0] origin:064-gtp-channel-conf 01_115 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXPCSRESET_TIME[1] origin:064-gtp-channel-conf 00_116 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXPCSRESET_TIME[2] origin:064-gtp-channel-conf 01_116 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXPCSRESET_TIME[3] origin:064-gtp-channel-conf 00_117 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXPCSRESET_TIME[4] origin:064-gtp-channel-conf 01_117 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXPH_CFG[0] origin:064-gtp-channel-conf 02_584 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXPH_CFG[1] origin:064-gtp-channel-conf 03_584 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXPH_CFG[2] origin:064-gtp-channel-conf 02_585 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXPH_CFG[3] origin:064-gtp-channel-conf 03_585 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXPH_CFG[4] origin:064-gtp-channel-conf 02_586 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXPH_CFG[5] origin:064-gtp-channel-conf 03_586 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXPH_CFG[6] origin:064-gtp-channel-conf 02_587 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXPH_CFG[7] origin:064-gtp-channel-conf 03_587 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXPH_CFG[8] origin:064-gtp-channel-conf 02_588 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXPH_CFG[9] origin:064-gtp-channel-conf 03_588 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXPH_CFG[10] origin:064-gtp-channel-conf 02_589 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXPH_CFG[11] origin:064-gtp-channel-conf 03_589 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXPH_CFG[12] origin:064-gtp-channel-conf 02_590 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXPH_CFG[13] origin:064-gtp-channel-conf 03_590 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXPH_CFG[14] origin:064-gtp-channel-conf 02_591 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXPH_CFG[15] origin:064-gtp-channel-conf 03_591 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXPH_CFG[16] origin:064-gtp-channel-conf 02_592 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXPH_CFG[17] origin:064-gtp-channel-conf 03_592 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXPH_CFG[18] origin:064-gtp-channel-conf 02_593 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXPH_CFG[19] origin:064-gtp-channel-conf 03_593 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXPH_CFG[20] origin:064-gtp-channel-conf 02_594 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXPH_CFG[21] origin:064-gtp-channel-conf 03_594 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXPH_CFG[22] origin:064-gtp-channel-conf 02_595 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXPH_CFG[23] origin:064-gtp-channel-conf 03_595 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXPH_MONITOR_SEL[0] origin:064-gtp-channel-conf 00_700 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXPH_MONITOR_SEL[1] origin:064-gtp-channel-conf 01_700 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXPH_MONITOR_SEL[2] origin:064-gtp-channel-conf 00_701 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXPH_MONITOR_SEL[3] origin:064-gtp-channel-conf 01_701 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXPH_MONITOR_SEL[4] origin:064-gtp-channel-conf 00_702 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXPHDLY_CFG[0] origin:064-gtp-channel-conf 02_600 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXPHDLY_CFG[1] origin:064-gtp-channel-conf 03_600 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXPHDLY_CFG[2] origin:064-gtp-channel-conf 02_601 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXPHDLY_CFG[3] origin:064-gtp-channel-conf 03_601 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXPHDLY_CFG[4] origin:064-gtp-channel-conf 02_602 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXPHDLY_CFG[5] origin:064-gtp-channel-conf 03_602 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXPHDLY_CFG[6] origin:064-gtp-channel-conf 02_603 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXPHDLY_CFG[7] origin:064-gtp-channel-conf 03_603 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXPHDLY_CFG[8] origin:064-gtp-channel-conf 02_604 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXPHDLY_CFG[9] origin:064-gtp-channel-conf 03_604 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXPHDLY_CFG[10] origin:064-gtp-channel-conf 02_605 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXPHDLY_CFG[11] origin:064-gtp-channel-conf 03_605 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXPHDLY_CFG[12] origin:064-gtp-channel-conf 02_606 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXPHDLY_CFG[13] origin:064-gtp-channel-conf 03_606 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXPHDLY_CFG[14] origin:064-gtp-channel-conf 02_607 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXPHDLY_CFG[15] origin:064-gtp-channel-conf 03_607 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXPHDLY_CFG[16] origin:064-gtp-channel-conf 02_608 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXPHDLY_CFG[17] origin:064-gtp-channel-conf 03_608 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXPHDLY_CFG[18] origin:064-gtp-channel-conf 02_609 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXPHDLY_CFG[19] origin:064-gtp-channel-conf 03_609 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXPHDLY_CFG[20] origin:064-gtp-channel-conf 02_610 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXPHDLY_CFG[21] origin:064-gtp-channel-conf 03_610 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXPHDLY_CFG[22] origin:064-gtp-channel-conf 02_611 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXPHDLY_CFG[23] origin:064-gtp-channel-conf 03_611 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXPI_CFG0[0] origin:064-gtp-channel-conf 03_430 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXPI_CFG0[1] origin:064-gtp-channel-conf 02_431 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXPI_CFG0[2] origin:064-gtp-channel-conf 03_431 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXPI_CFG1[0] origin:064-gtp-channel-conf 02_442 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXPI_CFG2[0] origin:064-gtp-channel-conf 03_441 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXPMARESET_TIME[0] origin:064-gtp-channel-conf 00_104 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXPMARESET_TIME[1] origin:064-gtp-channel-conf 01_104 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXPMARESET_TIME[2] origin:064-gtp-channel-conf 00_105 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXPMARESET_TIME[3] origin:064-gtp-channel-conf 01_105 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXPMARESET_TIME[4] origin:064-gtp-channel-conf 00_106 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXPRBS_ERR_LOOPBACK[0] origin:064-gtp-channel-conf 00_136 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXSLIDE_AUTO_WAIT[0] origin:064-gtp-channel-conf 00_520 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXSLIDE_AUTO_WAIT[1] origin:064-gtp-channel-conf 01_520 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXSLIDE_AUTO_WAIT[2] origin:064-gtp-channel-conf 00_521 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXSLIDE_AUTO_WAIT[3] origin:064-gtp-channel-conf 01_521 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXSLIDE_MODE.AUTO origin:064-gtp-channel-conf !01_519 00_519 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXSLIDE_MODE.PCS origin:064-gtp-channel-conf !00_519 01_519 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXSLIDE_MODE.PMA origin:064-gtp-channel-conf 00_519 01_519 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXSYNC_MULTILANE[0] origin:064-gtp-channel-conf 00_133 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXSYNC_OVRD[0] origin:064-gtp-channel-conf 01_135 -GTP_CHANNEL_1_MID_LEFT.GTPE2.RXSYNC_SKIP_DA[0] origin:064-gtp-channel-conf 01_134 -GTP_CHANNEL_1_MID_LEFT.GTPE2.SAS_MAX_COM[0] origin:064-gtp-channel-conf 00_171 -GTP_CHANNEL_1_MID_LEFT.GTPE2.SAS_MAX_COM[1] origin:064-gtp-channel-conf 01_171 -GTP_CHANNEL_1_MID_LEFT.GTPE2.SAS_MAX_COM[2] origin:064-gtp-channel-conf 00_172 -GTP_CHANNEL_1_MID_LEFT.GTPE2.SAS_MAX_COM[3] origin:064-gtp-channel-conf 01_172 -GTP_CHANNEL_1_MID_LEFT.GTPE2.SAS_MAX_COM[4] origin:064-gtp-channel-conf 00_173 -GTP_CHANNEL_1_MID_LEFT.GTPE2.SAS_MAX_COM[5] origin:064-gtp-channel-conf 01_173 -GTP_CHANNEL_1_MID_LEFT.GTPE2.SAS_MAX_COM[6] origin:064-gtp-channel-conf 00_174 -GTP_CHANNEL_1_MID_LEFT.GTPE2.SAS_MIN_COM[0] origin:064-gtp-channel-conf 01_156 -GTP_CHANNEL_1_MID_LEFT.GTPE2.SAS_MIN_COM[1] origin:064-gtp-channel-conf 00_157 -GTP_CHANNEL_1_MID_LEFT.GTPE2.SAS_MIN_COM[2] origin:064-gtp-channel-conf 01_157 -GTP_CHANNEL_1_MID_LEFT.GTPE2.SAS_MIN_COM[3] origin:064-gtp-channel-conf 00_158 -GTP_CHANNEL_1_MID_LEFT.GTPE2.SAS_MIN_COM[4] origin:064-gtp-channel-conf 01_158 -GTP_CHANNEL_1_MID_LEFT.GTPE2.SAS_MIN_COM[5] origin:064-gtp-channel-conf 00_159 -GTP_CHANNEL_1_MID_LEFT.GTPE2.SATA_BURST_SEQ_LEN[0] origin:064-gtp-channel-conf 00_150 -GTP_CHANNEL_1_MID_LEFT.GTPE2.SATA_BURST_SEQ_LEN[1] origin:064-gtp-channel-conf 01_150 -GTP_CHANNEL_1_MID_LEFT.GTPE2.SATA_BURST_SEQ_LEN[2] origin:064-gtp-channel-conf 00_151 -GTP_CHANNEL_1_MID_LEFT.GTPE2.SATA_BURST_SEQ_LEN[3] origin:064-gtp-channel-conf 01_151 -GTP_CHANNEL_1_MID_LEFT.GTPE2.SATA_BURST_VAL[0] origin:064-gtp-channel-conf 01_147 -GTP_CHANNEL_1_MID_LEFT.GTPE2.SATA_BURST_VAL[1] origin:064-gtp-channel-conf 00_148 -GTP_CHANNEL_1_MID_LEFT.GTPE2.SATA_BURST_VAL[2] origin:064-gtp-channel-conf 01_148 -GTP_CHANNEL_1_MID_LEFT.GTPE2.SATA_EIDLE_VAL[0] origin:064-gtp-channel-conf 00_152 -GTP_CHANNEL_1_MID_LEFT.GTPE2.SATA_EIDLE_VAL[1] origin:064-gtp-channel-conf 01_152 -GTP_CHANNEL_1_MID_LEFT.GTPE2.SATA_EIDLE_VAL[2] origin:064-gtp-channel-conf 00_153 -GTP_CHANNEL_1_MID_LEFT.GTPE2.SATA_MAX_BURST[0] origin:064-gtp-channel-conf 00_168 -GTP_CHANNEL_1_MID_LEFT.GTPE2.SATA_MAX_BURST[1] origin:064-gtp-channel-conf 01_168 -GTP_CHANNEL_1_MID_LEFT.GTPE2.SATA_MAX_BURST[2] origin:064-gtp-channel-conf 00_169 -GTP_CHANNEL_1_MID_LEFT.GTPE2.SATA_MAX_BURST[3] origin:064-gtp-channel-conf 01_169 -GTP_CHANNEL_1_MID_LEFT.GTPE2.SATA_MAX_BURST[4] origin:064-gtp-channel-conf 00_170 -GTP_CHANNEL_1_MID_LEFT.GTPE2.SATA_MAX_BURST[5] origin:064-gtp-channel-conf 01_170 -GTP_CHANNEL_1_MID_LEFT.GTPE2.SATA_MAX_INIT[0] origin:064-gtp-channel-conf 00_176 -GTP_CHANNEL_1_MID_LEFT.GTPE2.SATA_MAX_INIT[1] origin:064-gtp-channel-conf 01_176 -GTP_CHANNEL_1_MID_LEFT.GTPE2.SATA_MAX_INIT[2] origin:064-gtp-channel-conf 00_177 -GTP_CHANNEL_1_MID_LEFT.GTPE2.SATA_MAX_INIT[3] origin:064-gtp-channel-conf 01_177 -GTP_CHANNEL_1_MID_LEFT.GTPE2.SATA_MAX_INIT[4] origin:064-gtp-channel-conf 00_178 -GTP_CHANNEL_1_MID_LEFT.GTPE2.SATA_MAX_INIT[5] origin:064-gtp-channel-conf 01_178 -GTP_CHANNEL_1_MID_LEFT.GTPE2.SATA_MAX_WAKE[0] origin:064-gtp-channel-conf 00_179 -GTP_CHANNEL_1_MID_LEFT.GTPE2.SATA_MAX_WAKE[1] origin:064-gtp-channel-conf 01_179 -GTP_CHANNEL_1_MID_LEFT.GTPE2.SATA_MAX_WAKE[2] origin:064-gtp-channel-conf 00_180 -GTP_CHANNEL_1_MID_LEFT.GTPE2.SATA_MAX_WAKE[3] origin:064-gtp-channel-conf 01_180 -GTP_CHANNEL_1_MID_LEFT.GTPE2.SATA_MAX_WAKE[4] origin:064-gtp-channel-conf 00_181 -GTP_CHANNEL_1_MID_LEFT.GTPE2.SATA_MAX_WAKE[5] origin:064-gtp-channel-conf 01_181 -GTP_CHANNEL_1_MID_LEFT.GTPE2.SATA_MIN_BURST[0] origin:064-gtp-channel-conf 01_153 -GTP_CHANNEL_1_MID_LEFT.GTPE2.SATA_MIN_BURST[1] origin:064-gtp-channel-conf 00_154 -GTP_CHANNEL_1_MID_LEFT.GTPE2.SATA_MIN_BURST[2] origin:064-gtp-channel-conf 01_154 -GTP_CHANNEL_1_MID_LEFT.GTPE2.SATA_MIN_BURST[3] origin:064-gtp-channel-conf 00_155 -GTP_CHANNEL_1_MID_LEFT.GTPE2.SATA_MIN_BURST[4] origin:064-gtp-channel-conf 01_155 -GTP_CHANNEL_1_MID_LEFT.GTPE2.SATA_MIN_BURST[5] origin:064-gtp-channel-conf 00_156 -GTP_CHANNEL_1_MID_LEFT.GTPE2.SATA_MIN_INIT[0] origin:064-gtp-channel-conf 00_160 -GTP_CHANNEL_1_MID_LEFT.GTPE2.SATA_MIN_INIT[1] origin:064-gtp-channel-conf 01_160 -GTP_CHANNEL_1_MID_LEFT.GTPE2.SATA_MIN_INIT[2] origin:064-gtp-channel-conf 00_161 -GTP_CHANNEL_1_MID_LEFT.GTPE2.SATA_MIN_INIT[3] origin:064-gtp-channel-conf 01_161 -GTP_CHANNEL_1_MID_LEFT.GTPE2.SATA_MIN_INIT[4] origin:064-gtp-channel-conf 00_162 -GTP_CHANNEL_1_MID_LEFT.GTPE2.SATA_MIN_INIT[5] origin:064-gtp-channel-conf 01_162 -GTP_CHANNEL_1_MID_LEFT.GTPE2.SATA_MIN_WAKE[0] origin:064-gtp-channel-conf 00_163 -GTP_CHANNEL_1_MID_LEFT.GTPE2.SATA_MIN_WAKE[1] origin:064-gtp-channel-conf 01_163 -GTP_CHANNEL_1_MID_LEFT.GTPE2.SATA_MIN_WAKE[2] origin:064-gtp-channel-conf 00_164 -GTP_CHANNEL_1_MID_LEFT.GTPE2.SATA_MIN_WAKE[3] origin:064-gtp-channel-conf 01_164 -GTP_CHANNEL_1_MID_LEFT.GTPE2.SATA_MIN_WAKE[4] origin:064-gtp-channel-conf 00_165 -GTP_CHANNEL_1_MID_LEFT.GTPE2.SATA_MIN_WAKE[5] origin:064-gtp-channel-conf 01_165 -GTP_CHANNEL_1_MID_LEFT.GTPE2.SATA_PLL_CFG.VCO_1500MHZ origin:064-gtp-channel-conf 02_55 -GTP_CHANNEL_1_MID_LEFT.GTPE2.SATA_PLL_CFG.VCO_750MHZ origin:064-gtp-channel-conf 03_55 -GTP_CHANNEL_1_MID_LEFT.GTPE2.SHOW_REALIGN_COMMA origin:064-gtp-channel-conf 01_522 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TERM_RCAL_CFG[0] origin:064-gtp-channel-conf 02_136 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TERM_RCAL_CFG[1] origin:064-gtp-channel-conf 03_136 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TERM_RCAL_CFG[2] origin:064-gtp-channel-conf 02_137 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TERM_RCAL_CFG[3] origin:064-gtp-channel-conf 03_137 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TERM_RCAL_CFG[4] origin:064-gtp-channel-conf 02_138 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TERM_RCAL_CFG[5] origin:064-gtp-channel-conf 03_138 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TERM_RCAL_CFG[6] origin:064-gtp-channel-conf 02_139 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TERM_RCAL_CFG[7] origin:064-gtp-channel-conf 03_139 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TERM_RCAL_CFG[8] origin:064-gtp-channel-conf 02_140 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TERM_RCAL_CFG[9] origin:064-gtp-channel-conf 03_140 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TERM_RCAL_CFG[10] origin:064-gtp-channel-conf 02_141 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TERM_RCAL_CFG[11] origin:064-gtp-channel-conf 03_141 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TERM_RCAL_CFG[12] origin:064-gtp-channel-conf 02_142 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TERM_RCAL_CFG[13] origin:064-gtp-channel-conf 03_142 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TERM_RCAL_CFG[14] origin:064-gtp-channel-conf 02_143 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TERM_RCAL_OVRD[0] origin:064-gtp-channel-conf 03_150 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TERM_RCAL_OVRD[1] origin:064-gtp-channel-conf 02_151 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TERM_RCAL_OVRD[2] origin:064-gtp-channel-conf 03_151 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TRANS_TIME_RATE[0] origin:064-gtp-channel-conf 00_192 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TRANS_TIME_RATE[1] origin:064-gtp-channel-conf 01_192 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TRANS_TIME_RATE[2] origin:064-gtp-channel-conf 00_193 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TRANS_TIME_RATE[3] origin:064-gtp-channel-conf 01_193 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TRANS_TIME_RATE[4] origin:064-gtp-channel-conf 00_194 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TRANS_TIME_RATE[5] origin:064-gtp-channel-conf 01_194 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TRANS_TIME_RATE[6] origin:064-gtp-channel-conf 00_195 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TRANS_TIME_RATE[7] origin:064-gtp-channel-conf 01_195 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TST_RSV[0] origin:064-gtp-channel-conf 02_504 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TST_RSV[1] origin:064-gtp-channel-conf 03_504 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TST_RSV[2] origin:064-gtp-channel-conf 02_505 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TST_RSV[3] origin:064-gtp-channel-conf 03_505 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TST_RSV[4] origin:064-gtp-channel-conf 02_506 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TST_RSV[5] origin:064-gtp-channel-conf 03_506 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TST_RSV[6] origin:064-gtp-channel-conf 02_507 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TST_RSV[7] origin:064-gtp-channel-conf 03_507 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TST_RSV[8] origin:064-gtp-channel-conf 02_508 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TST_RSV[9] origin:064-gtp-channel-conf 03_508 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TST_RSV[10] origin:064-gtp-channel-conf 02_509 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TST_RSV[11] origin:064-gtp-channel-conf 03_509 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TST_RSV[12] origin:064-gtp-channel-conf 02_510 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TST_RSV[13] origin:064-gtp-channel-conf 03_510 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TST_RSV[14] origin:064-gtp-channel-conf 02_511 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TST_RSV[15] origin:064-gtp-channel-conf 03_511 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TST_RSV[16] origin:064-gtp-channel-conf 02_512 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TST_RSV[17] origin:064-gtp-channel-conf 03_512 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TST_RSV[18] origin:064-gtp-channel-conf 02_513 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TST_RSV[19] origin:064-gtp-channel-conf 03_513 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TST_RSV[20] origin:064-gtp-channel-conf 02_514 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TST_RSV[21] origin:064-gtp-channel-conf 03_514 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TST_RSV[22] origin:064-gtp-channel-conf 02_515 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TST_RSV[23] origin:064-gtp-channel-conf 03_515 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TST_RSV[24] origin:064-gtp-channel-conf 02_516 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TST_RSV[25] origin:064-gtp-channel-conf 03_516 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TST_RSV[26] origin:064-gtp-channel-conf 02_517 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TST_RSV[27] origin:064-gtp-channel-conf 03_517 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TST_RSV[28] origin:064-gtp-channel-conf 02_518 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TST_RSV[29] origin:064-gtp-channel-conf 03_518 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TST_RSV[30] origin:064-gtp-channel-conf 02_519 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TST_RSV[31] origin:064-gtp-channel-conf 03_519 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_CLKMUX_EN[0] origin:064-gtp-channel-conf 03_128 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_DATA_WIDTH[0] origin:064-gtp-channel-conf 02_152 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_DATA_WIDTH[1] origin:064-gtp-channel-conf 03_152 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_DATA_WIDTH[2] origin:064-gtp-channel-conf 02_153 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_DRIVE_MODE.PIPE origin:064-gtp-channel-conf 00_200 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_EIDLE_ASSERT_DELAY[0] origin:064-gtp-channel-conf 00_203 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_EIDLE_ASSERT_DELAY[1] origin:064-gtp-channel-conf 01_203 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_EIDLE_ASSERT_DELAY[2] origin:064-gtp-channel-conf 00_204 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_EIDLE_DEASSERT_DELAY[0] origin:064-gtp-channel-conf 01_204 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_EIDLE_DEASSERT_DELAY[1] origin:064-gtp-channel-conf 00_205 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_EIDLE_DEASSERT_DELAY[2] origin:064-gtp-channel-conf 01_205 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_LOOPBACK_DRIVE_HIZ origin:064-gtp-channel-conf 01_202 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_MAINCURSOR_SEL[0] origin:064-gtp-channel-conf 03_289 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_MARGIN_FULL_0[0] origin:064-gtp-channel-conf 02_232 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_MARGIN_FULL_0[1] origin:064-gtp-channel-conf 03_232 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_MARGIN_FULL_0[2] origin:064-gtp-channel-conf 02_233 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_MARGIN_FULL_0[3] origin:064-gtp-channel-conf 03_233 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_MARGIN_FULL_0[4] origin:064-gtp-channel-conf 02_234 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_MARGIN_FULL_0[5] origin:064-gtp-channel-conf 03_234 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_MARGIN_FULL_0[6] origin:064-gtp-channel-conf 02_235 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_MARGIN_FULL_1[0] origin:064-gtp-channel-conf 02_236 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_MARGIN_FULL_1[1] origin:064-gtp-channel-conf 03_236 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_MARGIN_FULL_1[2] origin:064-gtp-channel-conf 02_237 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_MARGIN_FULL_1[3] origin:064-gtp-channel-conf 03_237 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_MARGIN_FULL_1[4] origin:064-gtp-channel-conf 02_238 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_MARGIN_FULL_1[5] origin:064-gtp-channel-conf 03_238 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_MARGIN_FULL_1[6] origin:064-gtp-channel-conf 02_239 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_MARGIN_FULL_2[0] origin:064-gtp-channel-conf 02_240 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_MARGIN_FULL_2[1] origin:064-gtp-channel-conf 03_240 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_MARGIN_FULL_2[2] origin:064-gtp-channel-conf 02_241 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_MARGIN_FULL_2[3] origin:064-gtp-channel-conf 03_241 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_MARGIN_FULL_2[4] origin:064-gtp-channel-conf 02_242 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_MARGIN_FULL_2[5] origin:064-gtp-channel-conf 03_242 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_MARGIN_FULL_2[6] origin:064-gtp-channel-conf 02_243 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_MARGIN_FULL_3[0] origin:064-gtp-channel-conf 02_244 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_MARGIN_FULL_3[1] origin:064-gtp-channel-conf 03_244 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_MARGIN_FULL_3[2] origin:064-gtp-channel-conf 02_245 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_MARGIN_FULL_3[3] origin:064-gtp-channel-conf 03_245 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_MARGIN_FULL_3[4] origin:064-gtp-channel-conf 02_246 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_MARGIN_FULL_3[5] origin:064-gtp-channel-conf 03_246 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_MARGIN_FULL_3[6] origin:064-gtp-channel-conf 02_247 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_MARGIN_FULL_4[0] origin:064-gtp-channel-conf 02_248 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_MARGIN_FULL_4[1] origin:064-gtp-channel-conf 03_248 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_MARGIN_FULL_4[2] origin:064-gtp-channel-conf 02_249 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_MARGIN_FULL_4[3] origin:064-gtp-channel-conf 03_249 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_MARGIN_FULL_4[4] origin:064-gtp-channel-conf 02_250 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_MARGIN_FULL_4[5] origin:064-gtp-channel-conf 03_250 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_MARGIN_FULL_4[6] origin:064-gtp-channel-conf 02_251 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_MARGIN_LOW_0[0] origin:064-gtp-channel-conf 02_252 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_MARGIN_LOW_0[1] origin:064-gtp-channel-conf 03_252 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_MARGIN_LOW_0[2] origin:064-gtp-channel-conf 02_253 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_MARGIN_LOW_0[3] origin:064-gtp-channel-conf 03_253 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_MARGIN_LOW_0[4] origin:064-gtp-channel-conf 02_254 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_MARGIN_LOW_0[5] origin:064-gtp-channel-conf 03_254 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_MARGIN_LOW_0[6] origin:064-gtp-channel-conf 02_255 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_MARGIN_LOW_1[0] origin:064-gtp-channel-conf 02_256 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_MARGIN_LOW_1[1] origin:064-gtp-channel-conf 03_256 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_MARGIN_LOW_1[2] origin:064-gtp-channel-conf 02_257 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_MARGIN_LOW_1[3] origin:064-gtp-channel-conf 03_257 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_MARGIN_LOW_1[4] origin:064-gtp-channel-conf 02_258 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_MARGIN_LOW_1[5] origin:064-gtp-channel-conf 03_258 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_MARGIN_LOW_1[6] origin:064-gtp-channel-conf 02_259 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_MARGIN_LOW_2[0] origin:064-gtp-channel-conf 02_260 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_MARGIN_LOW_2[1] origin:064-gtp-channel-conf 03_260 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_MARGIN_LOW_2[2] origin:064-gtp-channel-conf 02_261 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_MARGIN_LOW_2[3] origin:064-gtp-channel-conf 03_261 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_MARGIN_LOW_2[4] origin:064-gtp-channel-conf 02_262 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_MARGIN_LOW_2[5] origin:064-gtp-channel-conf 03_262 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_MARGIN_LOW_2[6] origin:064-gtp-channel-conf 02_263 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_MARGIN_LOW_3[0] origin:064-gtp-channel-conf 02_264 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_MARGIN_LOW_3[1] origin:064-gtp-channel-conf 03_264 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_MARGIN_LOW_3[2] origin:064-gtp-channel-conf 02_265 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_MARGIN_LOW_3[3] origin:064-gtp-channel-conf 03_265 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_MARGIN_LOW_3[4] origin:064-gtp-channel-conf 02_266 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_MARGIN_LOW_3[5] origin:064-gtp-channel-conf 03_266 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_MARGIN_LOW_3[6] origin:064-gtp-channel-conf 02_267 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_MARGIN_LOW_4[0] origin:064-gtp-channel-conf 02_268 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_MARGIN_LOW_4[1] origin:064-gtp-channel-conf 03_268 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_MARGIN_LOW_4[2] origin:064-gtp-channel-conf 02_269 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_MARGIN_LOW_4[3] origin:064-gtp-channel-conf 03_269 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_MARGIN_LOW_4[4] origin:064-gtp-channel-conf 02_270 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_MARGIN_LOW_4[5] origin:064-gtp-channel-conf 03_270 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_MARGIN_LOW_4[6] origin:064-gtp-channel-conf 02_271 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_PREDRIVER_MODE[0] origin:064-gtp-channel-conf 00_206 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_RXDETECT_CFG[0] origin:064-gtp-channel-conf 02_296 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_RXDETECT_CFG[1] origin:064-gtp-channel-conf 03_296 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_RXDETECT_CFG[2] origin:064-gtp-channel-conf 02_297 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_RXDETECT_CFG[3] origin:064-gtp-channel-conf 03_297 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_RXDETECT_CFG[4] origin:064-gtp-channel-conf 02_298 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_RXDETECT_CFG[5] origin:064-gtp-channel-conf 03_298 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_RXDETECT_CFG[6] origin:064-gtp-channel-conf 02_299 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_RXDETECT_CFG[7] origin:064-gtp-channel-conf 03_299 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_RXDETECT_CFG[8] origin:064-gtp-channel-conf 02_300 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_RXDETECT_CFG[9] origin:064-gtp-channel-conf 03_300 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_RXDETECT_CFG[10] origin:064-gtp-channel-conf 02_301 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_RXDETECT_CFG[11] origin:064-gtp-channel-conf 03_301 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_RXDETECT_CFG[12] origin:064-gtp-channel-conf 02_302 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_RXDETECT_CFG[13] origin:064-gtp-channel-conf 03_302 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_RXDETECT_REF[0] origin:064-gtp-channel-conf 02_292 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_RXDETECT_REF[1] origin:064-gtp-channel-conf 03_292 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_RXDETECT_REF[2] origin:064-gtp-channel-conf 02_293 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_XCLK_SEL.TXUSR origin:064-gtp-channel-conf 03_11 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_CLK25_DIV[0] origin:064-gtp-channel-conf 02_144 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_CLK25_DIV[1] origin:064-gtp-channel-conf 03_144 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_CLK25_DIV[2] origin:064-gtp-channel-conf 02_145 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_CLK25_DIV[3] origin:064-gtp-channel-conf 03_145 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_CLK25_DIV[4] origin:064-gtp-channel-conf 02_146 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_DEEMPH0[0] origin:064-gtp-channel-conf 02_272 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_DEEMPH0[1] origin:064-gtp-channel-conf 03_272 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_DEEMPH0[2] origin:064-gtp-channel-conf 02_273 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_DEEMPH0[3] origin:064-gtp-channel-conf 03_273 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_DEEMPH0[4] origin:064-gtp-channel-conf 02_274 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_DEEMPH0[5] origin:064-gtp-channel-conf 03_274 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_DEEMPH1[0] origin:064-gtp-channel-conf 02_276 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_DEEMPH1[1] origin:064-gtp-channel-conf 03_276 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_DEEMPH1[2] origin:064-gtp-channel-conf 02_277 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_DEEMPH1[3] origin:064-gtp-channel-conf 03_277 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_DEEMPH1[4] origin:064-gtp-channel-conf 02_278 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TX_DEEMPH1[5] origin:064-gtp-channel-conf 03_278 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXBUF_EN origin:064-gtp-channel-conf 00_231 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXBUF_RESET_ON_RATE_CHANGE origin:064-gtp-channel-conf 01_231 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXDLY_CFG[0] origin:064-gtp-channel-conf 02_80 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXDLY_CFG[1] origin:064-gtp-channel-conf 03_80 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXDLY_CFG[2] origin:064-gtp-channel-conf 02_81 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXDLY_CFG[3] origin:064-gtp-channel-conf 03_81 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXDLY_CFG[4] origin:064-gtp-channel-conf 02_82 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXDLY_CFG[5] origin:064-gtp-channel-conf 03_82 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXDLY_CFG[6] origin:064-gtp-channel-conf 02_83 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXDLY_CFG[7] origin:064-gtp-channel-conf 03_83 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXDLY_CFG[8] origin:064-gtp-channel-conf 02_84 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXDLY_CFG[9] origin:064-gtp-channel-conf 03_84 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXDLY_CFG[10] origin:064-gtp-channel-conf 02_85 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXDLY_CFG[11] origin:064-gtp-channel-conf 03_85 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXDLY_CFG[12] origin:064-gtp-channel-conf 02_86 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXDLY_CFG[13] origin:064-gtp-channel-conf 03_86 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXDLY_CFG[14] origin:064-gtp-channel-conf 02_87 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXDLY_CFG[15] origin:064-gtp-channel-conf 03_87 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXDLY_LCFG[0] origin:064-gtp-channel-conf 02_568 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXDLY_LCFG[1] origin:064-gtp-channel-conf 03_568 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXDLY_LCFG[2] origin:064-gtp-channel-conf 02_569 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXDLY_LCFG[3] origin:064-gtp-channel-conf 03_569 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXDLY_LCFG[4] origin:064-gtp-channel-conf 02_570 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXDLY_LCFG[5] origin:064-gtp-channel-conf 03_570 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXDLY_LCFG[6] origin:064-gtp-channel-conf 02_571 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXDLY_LCFG[7] origin:064-gtp-channel-conf 03_571 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXDLY_LCFG[8] origin:064-gtp-channel-conf 02_572 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXDLY_TAP_CFG[0] origin:064-gtp-channel-conf 02_88 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXDLY_TAP_CFG[1] origin:064-gtp-channel-conf 03_88 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXDLY_TAP_CFG[2] origin:064-gtp-channel-conf 02_89 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXDLY_TAP_CFG[3] origin:064-gtp-channel-conf 03_89 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXDLY_TAP_CFG[4] origin:064-gtp-channel-conf 02_90 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXDLY_TAP_CFG[5] origin:064-gtp-channel-conf 03_90 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXDLY_TAP_CFG[6] origin:064-gtp-channel-conf 02_91 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXDLY_TAP_CFG[7] origin:064-gtp-channel-conf 03_91 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXDLY_TAP_CFG[8] origin:064-gtp-channel-conf 02_92 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXDLY_TAP_CFG[9] origin:064-gtp-channel-conf 03_92 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXDLY_TAP_CFG[10] origin:064-gtp-channel-conf 02_93 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXDLY_TAP_CFG[11] origin:064-gtp-channel-conf 03_93 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXDLY_TAP_CFG[12] origin:064-gtp-channel-conf 02_94 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXDLY_TAP_CFG[13] origin:064-gtp-channel-conf 03_94 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXDLY_TAP_CFG[14] origin:064-gtp-channel-conf 02_95 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXDLY_TAP_CFG[15] origin:064-gtp-channel-conf 03_95 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXGEARBOX_EN origin:064-gtp-channel-conf 01_226 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXOOB_CFG[0] origin:064-gtp-channel-conf 03_20 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXOUT_DIV[0] origin:064-gtp-channel-conf 02_386 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXOUT_DIV[1] origin:064-gtp-channel-conf 03_386 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPCSRESET_TIME[0] origin:064-gtp-channel-conf 01_130 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPCSRESET_TIME[1] origin:064-gtp-channel-conf 00_131 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPCSRESET_TIME[2] origin:064-gtp-channel-conf 01_131 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPCSRESET_TIME[3] origin:064-gtp-channel-conf 00_132 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPCSRESET_TIME[4] origin:064-gtp-channel-conf 01_132 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPH_CFG[0] origin:064-gtp-channel-conf 02_96 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPH_CFG[1] origin:064-gtp-channel-conf 03_96 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPH_CFG[2] origin:064-gtp-channel-conf 02_97 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPH_CFG[3] origin:064-gtp-channel-conf 03_97 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPH_CFG[4] origin:064-gtp-channel-conf 02_98 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPH_CFG[5] origin:064-gtp-channel-conf 03_98 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPH_CFG[6] origin:064-gtp-channel-conf 02_99 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPH_CFG[7] origin:064-gtp-channel-conf 03_99 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPH_CFG[8] origin:064-gtp-channel-conf 02_100 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPH_CFG[9] origin:064-gtp-channel-conf 03_100 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPH_CFG[10] origin:064-gtp-channel-conf 02_101 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPH_CFG[11] origin:064-gtp-channel-conf 03_101 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPH_CFG[12] origin:064-gtp-channel-conf 02_102 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPH_CFG[13] origin:064-gtp-channel-conf 03_102 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPH_CFG[14] origin:064-gtp-channel-conf 02_103 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPH_CFG[15] origin:064-gtp-channel-conf 03_103 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPH_MONITOR_SEL[0] origin:064-gtp-channel-conf 02_108 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPH_MONITOR_SEL[1] origin:064-gtp-channel-conf 03_108 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPH_MONITOR_SEL[2] origin:064-gtp-channel-conf 02_109 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPH_MONITOR_SEL[3] origin:064-gtp-channel-conf 03_109 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPH_MONITOR_SEL[4] origin:064-gtp-channel-conf 02_110 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPHDLY_CFG[0] origin:064-gtp-channel-conf 02_64 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPHDLY_CFG[1] origin:064-gtp-channel-conf 03_64 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPHDLY_CFG[2] origin:064-gtp-channel-conf 02_65 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPHDLY_CFG[3] origin:064-gtp-channel-conf 03_65 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPHDLY_CFG[4] origin:064-gtp-channel-conf 02_66 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPHDLY_CFG[5] origin:064-gtp-channel-conf 03_66 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPHDLY_CFG[6] origin:064-gtp-channel-conf 02_67 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPHDLY_CFG[7] origin:064-gtp-channel-conf 03_67 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPHDLY_CFG[8] origin:064-gtp-channel-conf 02_68 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPHDLY_CFG[9] origin:064-gtp-channel-conf 03_68 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPHDLY_CFG[10] origin:064-gtp-channel-conf 02_69 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPHDLY_CFG[11] origin:064-gtp-channel-conf 03_69 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPHDLY_CFG[12] origin:064-gtp-channel-conf 02_70 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPHDLY_CFG[13] origin:064-gtp-channel-conf 03_70 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPHDLY_CFG[14] origin:064-gtp-channel-conf 02_71 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPHDLY_CFG[15] origin:064-gtp-channel-conf 03_71 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPHDLY_CFG[16] origin:064-gtp-channel-conf 02_72 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPHDLY_CFG[17] origin:064-gtp-channel-conf 03_72 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPHDLY_CFG[18] origin:064-gtp-channel-conf 02_73 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPHDLY_CFG[19] origin:064-gtp-channel-conf 03_73 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPHDLY_CFG[20] origin:064-gtp-channel-conf 02_74 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPHDLY_CFG[21] origin:064-gtp-channel-conf 03_74 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPHDLY_CFG[22] origin:064-gtp-channel-conf 02_75 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPHDLY_CFG[23] origin:064-gtp-channel-conf 03_75 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPI_GREY_SEL[0] origin:064-gtp-channel-conf 03_498 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPI_INVSTROBE_SEL[0] origin:064-gtp-channel-conf 02_498 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPI_PPM_CFG[0] origin:064-gtp-channel-conf 02_488 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPI_PPM_CFG[1] origin:064-gtp-channel-conf 03_488 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPI_PPM_CFG[2] origin:064-gtp-channel-conf 02_489 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPI_PPM_CFG[3] origin:064-gtp-channel-conf 03_489 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPI_PPM_CFG[4] origin:064-gtp-channel-conf 02_490 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPI_PPM_CFG[5] origin:064-gtp-channel-conf 03_490 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPI_PPM_CFG[6] origin:064-gtp-channel-conf 02_491 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPI_PPM_CFG[7] origin:064-gtp-channel-conf 03_491 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPI_PPMCLK_SEL.TXUSRCLK2 origin:064-gtp-channel-conf 03_497 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPI_SYNFREQ_PPM[0] origin:064-gtp-channel-conf 02_496 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPI_SYNFREQ_PPM[1] origin:064-gtp-channel-conf 03_496 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPI_SYNFREQ_PPM[2] origin:064-gtp-channel-conf 02_497 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPI_CFG0[0] origin:064-gtp-channel-conf 02_40 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPI_CFG0[1] origin:064-gtp-channel-conf 03_40 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPI_CFG1[0] origin:064-gtp-channel-conf 02_41 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPI_CFG1[1] origin:064-gtp-channel-conf 03_41 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPI_CFG2[0] origin:064-gtp-channel-conf 02_42 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPI_CFG2[1] origin:064-gtp-channel-conf 03_42 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPI_CFG3[0] origin:064-gtp-channel-conf 02_43 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPI_CFG4[0] origin:064-gtp-channel-conf 03_43 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPI_CFG5[0] origin:064-gtp-channel-conf 02_44 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPI_CFG5[1] origin:064-gtp-channel-conf 03_44 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPI_CFG5[2] origin:064-gtp-channel-conf 02_45 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPMARESET_TIME[0] origin:064-gtp-channel-conf 00_128 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPMARESET_TIME[1] origin:064-gtp-channel-conf 01_128 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPMARESET_TIME[2] origin:064-gtp-channel-conf 00_129 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPMARESET_TIME[3] origin:064-gtp-channel-conf 01_129 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXPMARESET_TIME[4] origin:064-gtp-channel-conf 00_130 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXSYNC_MULTILANE[0] origin:064-gtp-channel-conf 01_133 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXSYNC_OVRD[0] origin:064-gtp-channel-conf 00_135 -GTP_CHANNEL_1_MID_LEFT.GTPE2.TXSYNC_SKIP_DA[0] origin:064-gtp-channel-conf 00_134 -GTP_CHANNEL_1_MID_LEFT.GTPE2.UCODEER_CLR[0] origin:064-gtp-channel-conf 01_00 -GTP_CHANNEL_1_MID_LEFT.GTPE2.USE_PCS_CLK_PHASE_SEL[0] origin:064-gtp-channel-conf 02_463 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ZINV_DMONITORCLK origin:064-gtp-channel-conf 02_13 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ZINV_DRPCLK origin:064-gtp-channel-conf 02_00 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ZINV_RXUSRCLK origin:064-gtp-channel-conf 03_01 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ZINV_SIGVALIDCLK origin:064-gtp-channel-conf 03_13 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ZINV_TXPHDLYTSTCLK origin:064-gtp-channel-conf 02_03 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ZINV_TXUSRCLK origin:064-gtp-channel-conf 03_04 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ZINV_CLKRSVD0 origin:064-gtp-channel-conf 02_23 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ZINV_CLKRSVD1 origin:064-gtp-channel-conf 03_23 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ZINV_RXUSRCLK2 origin:064-gtp-channel-conf 02_02 -GTP_CHANNEL_1_MID_LEFT.GTPE2.ZINV_TXUSRCLK2 origin:064-gtp-channel-conf 02_05 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ACJTAG_DEBUG_MODE[0] origin:064-gtp-channel-conf 00_07 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ACJTAG_MODE[0] origin:064-gtp-channel-conf 01_06 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ACJTAG_RESET[0] origin:064-gtp-channel-conf 01_07 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[0] origin:064-gtp-channel-conf 02_464 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[1] origin:064-gtp-channel-conf 03_464 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[2] origin:064-gtp-channel-conf 02_465 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[3] origin:064-gtp-channel-conf 03_465 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[4] origin:064-gtp-channel-conf 02_466 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[5] origin:064-gtp-channel-conf 03_466 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[6] origin:064-gtp-channel-conf 02_467 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[7] origin:064-gtp-channel-conf 03_467 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[8] origin:064-gtp-channel-conf 02_468 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[9] origin:064-gtp-channel-conf 03_468 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[10] origin:064-gtp-channel-conf 02_469 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[11] origin:064-gtp-channel-conf 03_469 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[12] origin:064-gtp-channel-conf 02_470 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[13] origin:064-gtp-channel-conf 03_470 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[14] origin:064-gtp-channel-conf 02_471 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[15] origin:064-gtp-channel-conf 03_471 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[16] origin:064-gtp-channel-conf 02_472 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[17] origin:064-gtp-channel-conf 03_472 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[18] origin:064-gtp-channel-conf 02_473 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[19] origin:064-gtp-channel-conf 03_473 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ALIGN_COMMA_DOUBLE origin:064-gtp-channel-conf 00_522 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[0] origin:064-gtp-channel-conf 00_496 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[1] origin:064-gtp-channel-conf 01_496 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[2] origin:064-gtp-channel-conf 00_497 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[3] origin:064-gtp-channel-conf 01_497 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[4] origin:064-gtp-channel-conf 00_498 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[5] origin:064-gtp-channel-conf 01_498 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[6] origin:064-gtp-channel-conf 00_499 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[7] origin:064-gtp-channel-conf 01_499 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[8] origin:064-gtp-channel-conf 00_500 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[9] origin:064-gtp-channel-conf 01_500 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ALIGN_COMMA_WORD[0] origin:064-gtp-channel-conf 01_526 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ALIGN_COMMA_WORD[1] origin:064-gtp-channel-conf 00_527 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ALIGN_MCOMMA_DET origin:064-gtp-channel-conf 00_523 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[0] origin:064-gtp-channel-conf 00_504 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[1] origin:064-gtp-channel-conf 01_504 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[2] origin:064-gtp-channel-conf 00_505 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[3] origin:064-gtp-channel-conf 01_505 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[4] origin:064-gtp-channel-conf 00_506 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[5] origin:064-gtp-channel-conf 01_506 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[6] origin:064-gtp-channel-conf 00_507 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[7] origin:064-gtp-channel-conf 01_507 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[8] origin:064-gtp-channel-conf 00_508 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[9] origin:064-gtp-channel-conf 01_508 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ALIGN_PCOMMA_DET origin:064-gtp-channel-conf 01_523 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[0] origin:064-gtp-channel-conf 00_512 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[1] origin:064-gtp-channel-conf 01_512 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[2] origin:064-gtp-channel-conf 00_513 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[3] origin:064-gtp-channel-conf 01_513 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[4] origin:064-gtp-channel-conf 00_514 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[5] origin:064-gtp-channel-conf 01_514 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[6] origin:064-gtp-channel-conf 00_515 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[7] origin:064-gtp-channel-conf 01_515 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[8] origin:064-gtp-channel-conf 00_516 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[9] origin:064-gtp-channel-conf 01_516 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CBCC_DATA_SOURCE_SEL.DECODED origin:064-gtp-channel-conf 01_661 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[0] origin:064-gtp-channel-conf 02_392 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[1] origin:064-gtp-channel-conf 03_392 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[2] origin:064-gtp-channel-conf 02_393 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[3] origin:064-gtp-channel-conf 03_393 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[4] origin:064-gtp-channel-conf 02_394 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[5] origin:064-gtp-channel-conf 03_394 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[6] origin:064-gtp-channel-conf 02_395 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[7] origin:064-gtp-channel-conf 03_395 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[8] origin:064-gtp-channel-conf 02_396 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[9] origin:064-gtp-channel-conf 03_396 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[10] origin:064-gtp-channel-conf 02_397 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[11] origin:064-gtp-channel-conf 03_397 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[12] origin:064-gtp-channel-conf 02_398 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[13] origin:064-gtp-channel-conf 03_398 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[14] origin:064-gtp-channel-conf 02_399 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[15] origin:064-gtp-channel-conf 03_399 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[16] origin:064-gtp-channel-conf 02_400 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[17] origin:064-gtp-channel-conf 03_400 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[18] origin:064-gtp-channel-conf 02_401 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[19] origin:064-gtp-channel-conf 03_401 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[20] origin:064-gtp-channel-conf 02_402 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[21] origin:064-gtp-channel-conf 03_402 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[22] origin:064-gtp-channel-conf 02_403 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[23] origin:064-gtp-channel-conf 03_403 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[24] origin:064-gtp-channel-conf 02_404 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[25] origin:064-gtp-channel-conf 03_404 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[26] origin:064-gtp-channel-conf 02_405 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[27] origin:064-gtp-channel-conf 03_405 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[28] origin:064-gtp-channel-conf 02_406 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[29] origin:064-gtp-channel-conf 03_406 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[30] origin:064-gtp-channel-conf 02_407 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[31] origin:064-gtp-channel-conf 03_407 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[32] origin:064-gtp-channel-conf 02_408 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[33] origin:064-gtp-channel-conf 03_408 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[34] origin:064-gtp-channel-conf 02_409 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[35] origin:064-gtp-channel-conf 03_409 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[36] origin:064-gtp-channel-conf 02_410 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[37] origin:064-gtp-channel-conf 03_410 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[38] origin:064-gtp-channel-conf 02_411 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[39] origin:064-gtp-channel-conf 03_411 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[40] origin:064-gtp-channel-conf 02_412 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[41] origin:064-gtp-channel-conf 03_412 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[42] origin:064-gtp-channel-conf 02_413 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG2[0] origin:064-gtp-channel-conf 02_459 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG2[1] origin:064-gtp-channel-conf 03_459 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG2[2] origin:064-gtp-channel-conf 02_460 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG2[3] origin:064-gtp-channel-conf 03_460 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG2[4] origin:064-gtp-channel-conf 02_461 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG2[5] origin:064-gtp-channel-conf 03_461 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG2[6] origin:064-gtp-channel-conf 02_462 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG3[0] origin:064-gtp-channel-conf 02_416 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG3[1] origin:064-gtp-channel-conf 03_416 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG3[2] origin:064-gtp-channel-conf 02_417 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG3[3] origin:064-gtp-channel-conf 03_417 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG3[4] origin:064-gtp-channel-conf 02_418 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG3[5] origin:064-gtp-channel-conf 03_418 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG3[6] origin:064-gtp-channel-conf 02_419 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG4[0] origin:064-gtp-channel-conf 03_438 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG5[0] origin:064-gtp-channel-conf 02_429 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG5[1] origin:064-gtp-channel-conf 03_429 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG6[0] origin:064-gtp-channel-conf 03_436 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG6[1] origin:064-gtp-channel-conf 02_437 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG6[2] origin:064-gtp-channel-conf 03_437 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG6[3] origin:064-gtp-channel-conf 02_438 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_KEEP_ALIGN origin:064-gtp-channel-conf 01_631 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_MAX_SKEW[0] origin:064-gtp-channel-conf 00_670 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_MAX_SKEW[1] origin:064-gtp-channel-conf 01_670 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_MAX_SKEW[2] origin:064-gtp-channel-conf 00_671 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_MAX_SKEW[3] origin:064-gtp-channel-conf 01_671 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[0] origin:064-gtp-channel-conf 00_608 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[1] origin:064-gtp-channel-conf 01_608 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[2] origin:064-gtp-channel-conf 00_609 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[3] origin:064-gtp-channel-conf 01_609 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[4] origin:064-gtp-channel-conf 00_610 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[5] origin:064-gtp-channel-conf 01_610 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[6] origin:064-gtp-channel-conf 00_611 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[7] origin:064-gtp-channel-conf 01_611 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[8] origin:064-gtp-channel-conf 00_612 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[9] origin:064-gtp-channel-conf 01_612 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[0] origin:064-gtp-channel-conf 00_616 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[1] origin:064-gtp-channel-conf 01_616 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[2] origin:064-gtp-channel-conf 00_617 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[3] origin:064-gtp-channel-conf 01_617 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[4] origin:064-gtp-channel-conf 00_618 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[5] origin:064-gtp-channel-conf 01_618 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[6] origin:064-gtp-channel-conf 00_619 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[7] origin:064-gtp-channel-conf 01_619 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[8] origin:064-gtp-channel-conf 00_620 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[9] origin:064-gtp-channel-conf 01_620 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[0] origin:064-gtp-channel-conf 00_624 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[1] origin:064-gtp-channel-conf 01_624 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[2] origin:064-gtp-channel-conf 00_625 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[3] origin:064-gtp-channel-conf 01_625 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[4] origin:064-gtp-channel-conf 00_626 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[5] origin:064-gtp-channel-conf 01_626 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[6] origin:064-gtp-channel-conf 00_627 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[7] origin:064-gtp-channel-conf 01_627 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[8] origin:064-gtp-channel-conf 00_628 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[9] origin:064-gtp-channel-conf 01_628 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[0] origin:064-gtp-channel-conf 00_632 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[1] origin:064-gtp-channel-conf 01_632 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[2] origin:064-gtp-channel-conf 00_633 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[3] origin:064-gtp-channel-conf 01_633 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[4] origin:064-gtp-channel-conf 00_634 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[5] origin:064-gtp-channel-conf 01_634 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[6] origin:064-gtp-channel-conf 00_635 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[7] origin:064-gtp-channel-conf 01_635 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[8] origin:064-gtp-channel-conf 00_636 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[9] origin:064-gtp-channel-conf 01_636 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_ENABLE[0] origin:064-gtp-channel-conf 00_614 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_ENABLE[1] origin:064-gtp-channel-conf 01_614 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_ENABLE[2] origin:064-gtp-channel-conf 00_615 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_ENABLE[3] origin:064-gtp-channel-conf 01_615 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[0] origin:064-gtp-channel-conf 00_640 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[1] origin:064-gtp-channel-conf 01_640 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[2] origin:064-gtp-channel-conf 00_641 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[3] origin:064-gtp-channel-conf 01_641 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[4] origin:064-gtp-channel-conf 00_642 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[5] origin:064-gtp-channel-conf 01_642 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[6] origin:064-gtp-channel-conf 00_643 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[7] origin:064-gtp-channel-conf 01_643 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[8] origin:064-gtp-channel-conf 00_644 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[9] origin:064-gtp-channel-conf 01_644 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[0] origin:064-gtp-channel-conf 00_648 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[1] origin:064-gtp-channel-conf 01_648 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[2] origin:064-gtp-channel-conf 00_649 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[3] origin:064-gtp-channel-conf 01_649 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[4] origin:064-gtp-channel-conf 00_650 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[5] origin:064-gtp-channel-conf 01_650 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[6] origin:064-gtp-channel-conf 00_651 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[7] origin:064-gtp-channel-conf 01_651 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[8] origin:064-gtp-channel-conf 00_652 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[9] origin:064-gtp-channel-conf 01_652 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[0] origin:064-gtp-channel-conf 00_656 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[1] origin:064-gtp-channel-conf 01_656 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[2] origin:064-gtp-channel-conf 00_657 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[3] origin:064-gtp-channel-conf 01_657 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[4] origin:064-gtp-channel-conf 00_658 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[5] origin:064-gtp-channel-conf 01_658 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[6] origin:064-gtp-channel-conf 00_659 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[7] origin:064-gtp-channel-conf 01_659 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[8] origin:064-gtp-channel-conf 00_660 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[9] origin:064-gtp-channel-conf 01_660 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[0] origin:064-gtp-channel-conf 00_664 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[1] origin:064-gtp-channel-conf 01_664 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[2] origin:064-gtp-channel-conf 00_665 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[3] origin:064-gtp-channel-conf 01_665 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[4] origin:064-gtp-channel-conf 00_666 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[5] origin:064-gtp-channel-conf 01_666 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[6] origin:064-gtp-channel-conf 00_667 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[7] origin:064-gtp-channel-conf 01_667 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[8] origin:064-gtp-channel-conf 00_668 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[9] origin:064-gtp-channel-conf 01_668 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_ENABLE[0] origin:064-gtp-channel-conf 00_646 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_ENABLE[1] origin:064-gtp-channel-conf 01_646 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_ENABLE[2] origin:064-gtp-channel-conf 00_647 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_ENABLE[3] origin:064-gtp-channel-conf 01_647 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_USE origin:064-gtp-channel-conf 01_645 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_LEN[0] origin:064-gtp-channel-conf 00_623 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_LEN[1] origin:064-gtp-channel-conf 01_623 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COMMON_SWING[0] origin:064-gtp-channel-conf 03_311 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_KEEP_IDLE origin:064-gtp-channel-conf 00_591 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_MAX_LAT[0] origin:064-gtp-channel-conf 00_557 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_MAX_LAT[1] origin:064-gtp-channel-conf 01_557 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_MAX_LAT[2] origin:064-gtp-channel-conf 00_558 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_MAX_LAT[3] origin:064-gtp-channel-conf 01_558 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_MAX_LAT[4] origin:064-gtp-channel-conf 00_559 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_MAX_LAT[5] origin:064-gtp-channel-conf 01_559 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_MIN_LAT[0] origin:064-gtp-channel-conf 00_565 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_MIN_LAT[1] origin:064-gtp-channel-conf 01_565 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_MIN_LAT[2] origin:064-gtp-channel-conf 00_566 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_MIN_LAT[3] origin:064-gtp-channel-conf 01_566 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_MIN_LAT[4] origin:064-gtp-channel-conf 00_567 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_MIN_LAT[5] origin:064-gtp-channel-conf 01_567 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_PRECEDENCE origin:064-gtp-channel-conf 00_590 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_REPEAT_WAIT[0] origin:064-gtp-channel-conf 00_573 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_REPEAT_WAIT[1] origin:064-gtp-channel-conf 01_573 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_REPEAT_WAIT[2] origin:064-gtp-channel-conf 00_574 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_REPEAT_WAIT[3] origin:064-gtp-channel-conf 01_574 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_REPEAT_WAIT[4] origin:064-gtp-channel-conf 00_575 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[0] origin:064-gtp-channel-conf 00_544 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[1] origin:064-gtp-channel-conf 01_544 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[2] origin:064-gtp-channel-conf 00_545 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[3] origin:064-gtp-channel-conf 01_545 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[4] origin:064-gtp-channel-conf 00_546 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[5] origin:064-gtp-channel-conf 01_546 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[6] origin:064-gtp-channel-conf 00_547 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[7] origin:064-gtp-channel-conf 01_547 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[8] origin:064-gtp-channel-conf 00_548 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[9] origin:064-gtp-channel-conf 01_548 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[0] origin:064-gtp-channel-conf 00_552 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[1] origin:064-gtp-channel-conf 01_552 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[2] origin:064-gtp-channel-conf 00_553 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[3] origin:064-gtp-channel-conf 01_553 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[4] origin:064-gtp-channel-conf 00_554 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[5] origin:064-gtp-channel-conf 01_554 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[6] origin:064-gtp-channel-conf 00_555 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[7] origin:064-gtp-channel-conf 01_555 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[8] origin:064-gtp-channel-conf 00_556 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[9] origin:064-gtp-channel-conf 01_556 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[0] origin:064-gtp-channel-conf 00_560 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[1] origin:064-gtp-channel-conf 01_560 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[2] origin:064-gtp-channel-conf 00_561 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[3] origin:064-gtp-channel-conf 01_561 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[4] origin:064-gtp-channel-conf 00_562 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[5] origin:064-gtp-channel-conf 01_562 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[6] origin:064-gtp-channel-conf 00_563 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[7] origin:064-gtp-channel-conf 01_563 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[8] origin:064-gtp-channel-conf 00_564 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[9] origin:064-gtp-channel-conf 01_564 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[0] origin:064-gtp-channel-conf 00_568 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[1] origin:064-gtp-channel-conf 01_568 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[2] origin:064-gtp-channel-conf 00_569 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[3] origin:064-gtp-channel-conf 01_569 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[4] origin:064-gtp-channel-conf 00_570 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[5] origin:064-gtp-channel-conf 01_570 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[6] origin:064-gtp-channel-conf 00_571 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[7] origin:064-gtp-channel-conf 01_571 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[8] origin:064-gtp-channel-conf 00_572 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[9] origin:064-gtp-channel-conf 01_572 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_ENABLE[0] origin:064-gtp-channel-conf 00_549 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_ENABLE[1] origin:064-gtp-channel-conf 01_549 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_ENABLE[2] origin:064-gtp-channel-conf 00_550 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_ENABLE[3] origin:064-gtp-channel-conf 01_550 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[0] origin:064-gtp-channel-conf 00_576 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[1] origin:064-gtp-channel-conf 01_576 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[2] origin:064-gtp-channel-conf 00_577 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[3] origin:064-gtp-channel-conf 01_577 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[4] origin:064-gtp-channel-conf 00_578 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[5] origin:064-gtp-channel-conf 01_578 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[6] origin:064-gtp-channel-conf 00_579 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[7] origin:064-gtp-channel-conf 01_579 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[8] origin:064-gtp-channel-conf 00_580 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[9] origin:064-gtp-channel-conf 01_580 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[0] origin:064-gtp-channel-conf 00_584 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[1] origin:064-gtp-channel-conf 01_584 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[2] origin:064-gtp-channel-conf 00_585 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[3] origin:064-gtp-channel-conf 01_585 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[4] origin:064-gtp-channel-conf 00_586 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[5] origin:064-gtp-channel-conf 01_586 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[6] origin:064-gtp-channel-conf 00_587 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[7] origin:064-gtp-channel-conf 01_587 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[8] origin:064-gtp-channel-conf 00_588 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[9] origin:064-gtp-channel-conf 01_588 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[0] origin:064-gtp-channel-conf 00_592 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[1] origin:064-gtp-channel-conf 01_592 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[2] origin:064-gtp-channel-conf 00_593 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[3] origin:064-gtp-channel-conf 01_593 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[4] origin:064-gtp-channel-conf 00_594 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[5] origin:064-gtp-channel-conf 01_594 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[6] origin:064-gtp-channel-conf 00_595 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[7] origin:064-gtp-channel-conf 01_595 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[8] origin:064-gtp-channel-conf 00_596 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[9] origin:064-gtp-channel-conf 01_596 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[0] origin:064-gtp-channel-conf 00_600 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[1] origin:064-gtp-channel-conf 01_600 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[2] origin:064-gtp-channel-conf 00_601 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[3] origin:064-gtp-channel-conf 01_601 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[4] origin:064-gtp-channel-conf 00_602 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[5] origin:064-gtp-channel-conf 01_602 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[6] origin:064-gtp-channel-conf 00_603 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[7] origin:064-gtp-channel-conf 01_603 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[8] origin:064-gtp-channel-conf 00_604 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[9] origin:064-gtp-channel-conf 01_604 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_ENABLE[0] origin:064-gtp-channel-conf 00_581 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_ENABLE[1] origin:064-gtp-channel-conf 01_581 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_ENABLE[2] origin:064-gtp-channel-conf 00_582 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_ENABLE[3] origin:064-gtp-channel-conf 01_582 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_USE origin:064-gtp-channel-conf 00_583 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_LEN[0] origin:064-gtp-channel-conf 00_589 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_LEN[1] origin:064-gtp-channel-conf 01_589 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.CLK_CORRECT_USE origin:064-gtp-channel-conf 00_551 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.DEC_MCOMMA_DETECT origin:064-gtp-channel-conf 01_494 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.DEC_PCOMMA_DETECT origin:064-gtp-channel-conf 00_495 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.DEC_VALID_COMMA_ONLY origin:064-gtp-channel-conf 00_494 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[0] origin:064-gtp-channel-conf 02_368 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[1] origin:064-gtp-channel-conf 03_368 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[2] origin:064-gtp-channel-conf 02_369 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[3] origin:064-gtp-channel-conf 03_369 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[4] origin:064-gtp-channel-conf 02_370 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[5] origin:064-gtp-channel-conf 03_370 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[6] origin:064-gtp-channel-conf 02_371 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[7] origin:064-gtp-channel-conf 03_371 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[8] origin:064-gtp-channel-conf 02_372 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[9] origin:064-gtp-channel-conf 03_372 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[10] origin:064-gtp-channel-conf 02_373 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[11] origin:064-gtp-channel-conf 03_373 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[12] origin:064-gtp-channel-conf 02_374 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[13] origin:064-gtp-channel-conf 03_374 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[14] origin:064-gtp-channel-conf 02_375 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[15] origin:064-gtp-channel-conf 03_375 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[16] origin:064-gtp-channel-conf 02_376 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[17] origin:064-gtp-channel-conf 03_376 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[18] origin:064-gtp-channel-conf 02_377 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[19] origin:064-gtp-channel-conf 03_377 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[20] origin:064-gtp-channel-conf 02_378 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[21] origin:064-gtp-channel-conf 03_378 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[22] origin:064-gtp-channel-conf 02_379 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[23] origin:064-gtp-channel-conf 03_379 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_CLK_PHASE_SEL[0] origin:064-gtp-channel-conf 03_463 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_CONTROL[0] origin:064-gtp-channel-conf 00_488 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_CONTROL[1] origin:064-gtp-channel-conf 01_488 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_CONTROL[2] origin:064-gtp-channel-conf 00_489 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_CONTROL[3] origin:064-gtp-channel-conf 01_489 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_CONTROL[4] origin:064-gtp-channel-conf 00_490 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_CONTROL[5] origin:064-gtp-channel-conf 01_490 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_ERRDET_EN origin:064-gtp-channel-conf 01_492 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_EYE_SCAN_EN origin:064-gtp-channel-conf 00_492 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_HORZ_OFFSET[0] origin:064-gtp-channel-conf 00_480 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_HORZ_OFFSET[1] origin:064-gtp-channel-conf 01_480 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_HORZ_OFFSET[2] origin:064-gtp-channel-conf 00_481 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_HORZ_OFFSET[3] origin:064-gtp-channel-conf 01_481 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_HORZ_OFFSET[4] origin:064-gtp-channel-conf 00_482 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_HORZ_OFFSET[5] origin:064-gtp-channel-conf 01_482 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_HORZ_OFFSET[6] origin:064-gtp-channel-conf 00_483 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_HORZ_OFFSET[7] origin:064-gtp-channel-conf 01_483 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_HORZ_OFFSET[8] origin:064-gtp-channel-conf 00_484 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_HORZ_OFFSET[9] origin:064-gtp-channel-conf 01_484 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_HORZ_OFFSET[10] origin:064-gtp-channel-conf 00_485 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_HORZ_OFFSET[11] origin:064-gtp-channel-conf 01_485 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_PMA_CFG[0] origin:064-gtp-channel-conf 02_624 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_PMA_CFG[1] origin:064-gtp-channel-conf 03_624 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_PMA_CFG[2] origin:064-gtp-channel-conf 02_625 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_PMA_CFG[3] origin:064-gtp-channel-conf 03_625 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_PMA_CFG[4] origin:064-gtp-channel-conf 02_626 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_PMA_CFG[5] origin:064-gtp-channel-conf 03_626 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_PMA_CFG[6] origin:064-gtp-channel-conf 02_627 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_PMA_CFG[7] origin:064-gtp-channel-conf 03_627 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_PMA_CFG[8] origin:064-gtp-channel-conf 02_628 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_PMA_CFG[9] origin:064-gtp-channel-conf 03_628 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_PRESCALE[0] origin:064-gtp-channel-conf 01_477 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_PRESCALE[1] origin:064-gtp-channel-conf 00_478 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_PRESCALE[2] origin:064-gtp-channel-conf 01_478 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_PRESCALE[3] origin:064-gtp-channel-conf 00_479 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_PRESCALE[4] origin:064-gtp-channel-conf 01_479 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[0] origin:064-gtp-channel-conf 00_392 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[1] origin:064-gtp-channel-conf 01_392 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[2] origin:064-gtp-channel-conf 00_393 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[3] origin:064-gtp-channel-conf 01_393 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[4] origin:064-gtp-channel-conf 00_394 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[5] origin:064-gtp-channel-conf 01_394 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[6] origin:064-gtp-channel-conf 00_395 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[7] origin:064-gtp-channel-conf 01_395 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[8] origin:064-gtp-channel-conf 00_396 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[9] origin:064-gtp-channel-conf 01_396 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[10] origin:064-gtp-channel-conf 00_397 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[11] origin:064-gtp-channel-conf 01_397 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[12] origin:064-gtp-channel-conf 00_398 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[13] origin:064-gtp-channel-conf 01_398 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[14] origin:064-gtp-channel-conf 00_399 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[15] origin:064-gtp-channel-conf 01_399 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[16] origin:064-gtp-channel-conf 00_400 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[17] origin:064-gtp-channel-conf 01_400 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[18] origin:064-gtp-channel-conf 00_401 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[19] origin:064-gtp-channel-conf 01_401 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[20] origin:064-gtp-channel-conf 00_402 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[21] origin:064-gtp-channel-conf 01_402 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[22] origin:064-gtp-channel-conf 00_403 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[23] origin:064-gtp-channel-conf 01_403 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[24] origin:064-gtp-channel-conf 00_404 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[25] origin:064-gtp-channel-conf 01_404 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[26] origin:064-gtp-channel-conf 00_405 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[27] origin:064-gtp-channel-conf 01_405 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[28] origin:064-gtp-channel-conf 00_406 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[29] origin:064-gtp-channel-conf 01_406 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[30] origin:064-gtp-channel-conf 00_407 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[31] origin:064-gtp-channel-conf 01_407 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[32] origin:064-gtp-channel-conf 00_408 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[33] origin:064-gtp-channel-conf 01_408 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[34] origin:064-gtp-channel-conf 00_409 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[35] origin:064-gtp-channel-conf 01_409 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[36] origin:064-gtp-channel-conf 00_410 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[37] origin:064-gtp-channel-conf 01_410 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[38] origin:064-gtp-channel-conf 00_411 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[39] origin:064-gtp-channel-conf 01_411 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[40] origin:064-gtp-channel-conf 00_412 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[41] origin:064-gtp-channel-conf 01_412 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[42] origin:064-gtp-channel-conf 00_413 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[43] origin:064-gtp-channel-conf 01_413 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[44] origin:064-gtp-channel-conf 00_414 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[45] origin:064-gtp-channel-conf 01_414 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[46] origin:064-gtp-channel-conf 00_415 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[47] origin:064-gtp-channel-conf 01_415 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[48] origin:064-gtp-channel-conf 00_416 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[49] origin:064-gtp-channel-conf 01_416 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[50] origin:064-gtp-channel-conf 00_417 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[51] origin:064-gtp-channel-conf 01_417 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[52] origin:064-gtp-channel-conf 00_418 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[53] origin:064-gtp-channel-conf 01_418 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[54] origin:064-gtp-channel-conf 00_419 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[55] origin:064-gtp-channel-conf 01_419 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[56] origin:064-gtp-channel-conf 00_420 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[57] origin:064-gtp-channel-conf 01_420 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[58] origin:064-gtp-channel-conf 00_421 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[59] origin:064-gtp-channel-conf 01_421 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[60] origin:064-gtp-channel-conf 00_422 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[61] origin:064-gtp-channel-conf 01_422 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[62] origin:064-gtp-channel-conf 00_423 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[63] origin:064-gtp-channel-conf 01_423 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[64] origin:064-gtp-channel-conf 00_424 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[65] origin:064-gtp-channel-conf 01_424 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[66] origin:064-gtp-channel-conf 00_425 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[67] origin:064-gtp-channel-conf 01_425 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[68] origin:064-gtp-channel-conf 00_426 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[69] origin:064-gtp-channel-conf 01_426 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[70] origin:064-gtp-channel-conf 00_427 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[71] origin:064-gtp-channel-conf 01_427 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[72] origin:064-gtp-channel-conf 00_428 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[73] origin:064-gtp-channel-conf 01_428 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[74] origin:064-gtp-channel-conf 00_429 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[75] origin:064-gtp-channel-conf 01_429 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[76] origin:064-gtp-channel-conf 00_430 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[77] origin:064-gtp-channel-conf 01_430 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[78] origin:064-gtp-channel-conf 00_431 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[79] origin:064-gtp-channel-conf 01_431 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[0] origin:064-gtp-channel-conf 00_352 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[1] origin:064-gtp-channel-conf 01_352 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[2] origin:064-gtp-channel-conf 00_353 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[3] origin:064-gtp-channel-conf 01_353 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[4] origin:064-gtp-channel-conf 00_354 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[5] origin:064-gtp-channel-conf 01_354 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[6] origin:064-gtp-channel-conf 00_355 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[7] origin:064-gtp-channel-conf 01_355 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[8] origin:064-gtp-channel-conf 00_356 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[9] origin:064-gtp-channel-conf 01_356 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[10] origin:064-gtp-channel-conf 00_357 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[11] origin:064-gtp-channel-conf 01_357 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[12] origin:064-gtp-channel-conf 00_358 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[13] origin:064-gtp-channel-conf 01_358 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[14] origin:064-gtp-channel-conf 00_359 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[15] origin:064-gtp-channel-conf 01_359 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[16] origin:064-gtp-channel-conf 00_360 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[17] origin:064-gtp-channel-conf 01_360 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[18] origin:064-gtp-channel-conf 00_361 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[19] origin:064-gtp-channel-conf 01_361 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[20] origin:064-gtp-channel-conf 00_362 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[21] origin:064-gtp-channel-conf 01_362 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[22] origin:064-gtp-channel-conf 00_363 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[23] origin:064-gtp-channel-conf 01_363 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[24] origin:064-gtp-channel-conf 00_364 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[25] origin:064-gtp-channel-conf 01_364 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[26] origin:064-gtp-channel-conf 00_365 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[27] origin:064-gtp-channel-conf 01_365 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[28] origin:064-gtp-channel-conf 00_366 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[29] origin:064-gtp-channel-conf 01_366 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[30] origin:064-gtp-channel-conf 00_367 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[31] origin:064-gtp-channel-conf 01_367 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[32] origin:064-gtp-channel-conf 00_368 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[33] origin:064-gtp-channel-conf 01_368 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[34] origin:064-gtp-channel-conf 00_369 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[35] origin:064-gtp-channel-conf 01_369 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[36] origin:064-gtp-channel-conf 00_370 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[37] origin:064-gtp-channel-conf 01_370 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[38] origin:064-gtp-channel-conf 00_371 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[39] origin:064-gtp-channel-conf 01_371 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[40] origin:064-gtp-channel-conf 00_372 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[41] origin:064-gtp-channel-conf 01_372 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[42] origin:064-gtp-channel-conf 00_373 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[43] origin:064-gtp-channel-conf 01_373 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[44] origin:064-gtp-channel-conf 00_374 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[45] origin:064-gtp-channel-conf 01_374 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[46] origin:064-gtp-channel-conf 00_375 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[47] origin:064-gtp-channel-conf 01_375 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[48] origin:064-gtp-channel-conf 00_376 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[49] origin:064-gtp-channel-conf 01_376 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[50] origin:064-gtp-channel-conf 00_377 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[51] origin:064-gtp-channel-conf 01_377 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[52] origin:064-gtp-channel-conf 00_378 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[53] origin:064-gtp-channel-conf 01_378 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[54] origin:064-gtp-channel-conf 00_379 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[55] origin:064-gtp-channel-conf 01_379 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[56] origin:064-gtp-channel-conf 00_380 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[57] origin:064-gtp-channel-conf 01_380 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[58] origin:064-gtp-channel-conf 00_381 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[59] origin:064-gtp-channel-conf 01_381 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[60] origin:064-gtp-channel-conf 00_382 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[61] origin:064-gtp-channel-conf 01_382 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[62] origin:064-gtp-channel-conf 00_383 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[63] origin:064-gtp-channel-conf 01_383 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[64] origin:064-gtp-channel-conf 00_384 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[65] origin:064-gtp-channel-conf 01_384 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[66] origin:064-gtp-channel-conf 00_385 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[67] origin:064-gtp-channel-conf 01_385 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[68] origin:064-gtp-channel-conf 00_386 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[69] origin:064-gtp-channel-conf 01_386 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[70] origin:064-gtp-channel-conf 00_387 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[71] origin:064-gtp-channel-conf 01_387 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[72] origin:064-gtp-channel-conf 00_388 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[73] origin:064-gtp-channel-conf 01_388 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[74] origin:064-gtp-channel-conf 00_389 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[75] origin:064-gtp-channel-conf 01_389 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[76] origin:064-gtp-channel-conf 00_390 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[77] origin:064-gtp-channel-conf 01_390 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[78] origin:064-gtp-channel-conf 00_391 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[79] origin:064-gtp-channel-conf 01_391 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[0] origin:064-gtp-channel-conf 00_432 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[1] origin:064-gtp-channel-conf 01_432 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[2] origin:064-gtp-channel-conf 00_433 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[3] origin:064-gtp-channel-conf 01_433 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[4] origin:064-gtp-channel-conf 00_434 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[5] origin:064-gtp-channel-conf 01_434 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[6] origin:064-gtp-channel-conf 00_435 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[7] origin:064-gtp-channel-conf 01_435 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[8] origin:064-gtp-channel-conf 00_436 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[9] origin:064-gtp-channel-conf 01_436 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[10] origin:064-gtp-channel-conf 00_437 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[11] origin:064-gtp-channel-conf 01_437 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[12] origin:064-gtp-channel-conf 00_438 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[13] origin:064-gtp-channel-conf 01_438 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[14] origin:064-gtp-channel-conf 00_439 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[15] origin:064-gtp-channel-conf 01_439 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[16] origin:064-gtp-channel-conf 00_440 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[17] origin:064-gtp-channel-conf 01_440 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[18] origin:064-gtp-channel-conf 00_441 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[19] origin:064-gtp-channel-conf 01_441 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[20] origin:064-gtp-channel-conf 00_442 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[21] origin:064-gtp-channel-conf 01_442 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[22] origin:064-gtp-channel-conf 00_443 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[23] origin:064-gtp-channel-conf 01_443 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[24] origin:064-gtp-channel-conf 00_444 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[25] origin:064-gtp-channel-conf 01_444 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[26] origin:064-gtp-channel-conf 00_445 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[27] origin:064-gtp-channel-conf 01_445 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[28] origin:064-gtp-channel-conf 00_446 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[29] origin:064-gtp-channel-conf 01_446 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[30] origin:064-gtp-channel-conf 00_447 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[31] origin:064-gtp-channel-conf 01_447 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[32] origin:064-gtp-channel-conf 00_448 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[33] origin:064-gtp-channel-conf 01_448 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[34] origin:064-gtp-channel-conf 00_449 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[35] origin:064-gtp-channel-conf 01_449 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[36] origin:064-gtp-channel-conf 00_450 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[37] origin:064-gtp-channel-conf 01_450 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[38] origin:064-gtp-channel-conf 00_451 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[39] origin:064-gtp-channel-conf 01_451 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[40] origin:064-gtp-channel-conf 00_452 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[41] origin:064-gtp-channel-conf 01_452 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[42] origin:064-gtp-channel-conf 00_453 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[43] origin:064-gtp-channel-conf 01_453 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[44] origin:064-gtp-channel-conf 00_454 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[45] origin:064-gtp-channel-conf 01_454 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[46] origin:064-gtp-channel-conf 00_455 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[47] origin:064-gtp-channel-conf 01_455 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[48] origin:064-gtp-channel-conf 00_456 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[49] origin:064-gtp-channel-conf 01_456 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[50] origin:064-gtp-channel-conf 00_457 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[51] origin:064-gtp-channel-conf 01_457 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[52] origin:064-gtp-channel-conf 00_458 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[53] origin:064-gtp-channel-conf 01_458 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[54] origin:064-gtp-channel-conf 00_459 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[55] origin:064-gtp-channel-conf 01_459 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[56] origin:064-gtp-channel-conf 00_460 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[57] origin:064-gtp-channel-conf 01_460 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[58] origin:064-gtp-channel-conf 00_461 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[59] origin:064-gtp-channel-conf 01_461 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[60] origin:064-gtp-channel-conf 00_462 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[61] origin:064-gtp-channel-conf 01_462 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[62] origin:064-gtp-channel-conf 00_463 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[63] origin:064-gtp-channel-conf 01_463 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[64] origin:064-gtp-channel-conf 00_464 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[65] origin:064-gtp-channel-conf 01_464 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[66] origin:064-gtp-channel-conf 00_465 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[67] origin:064-gtp-channel-conf 01_465 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[68] origin:064-gtp-channel-conf 00_466 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[69] origin:064-gtp-channel-conf 01_466 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[70] origin:064-gtp-channel-conf 00_467 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[71] origin:064-gtp-channel-conf 01_467 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[72] origin:064-gtp-channel-conf 00_468 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[73] origin:064-gtp-channel-conf 01_468 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[74] origin:064-gtp-channel-conf 00_469 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[75] origin:064-gtp-channel-conf 01_469 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[76] origin:064-gtp-channel-conf 00_470 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[77] origin:064-gtp-channel-conf 01_470 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[78] origin:064-gtp-channel-conf 00_471 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[79] origin:064-gtp-channel-conf 01_471 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_VERT_OFFSET[0] origin:064-gtp-channel-conf 00_472 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_VERT_OFFSET[1] origin:064-gtp-channel-conf 01_472 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_VERT_OFFSET[2] origin:064-gtp-channel-conf 00_473 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_VERT_OFFSET[3] origin:064-gtp-channel-conf 01_473 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_VERT_OFFSET[4] origin:064-gtp-channel-conf 00_474 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_VERT_OFFSET[5] origin:064-gtp-channel-conf 01_474 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_VERT_OFFSET[6] origin:064-gtp-channel-conf 00_475 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_VERT_OFFSET[7] origin:064-gtp-channel-conf 01_475 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.ES_VERT_OFFSET[8] origin:064-gtp-channel-conf 00_476 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.FTS_DESKEW_SEQ_ENABLE[0] origin:064-gtp-channel-conf 00_662 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.FTS_DESKEW_SEQ_ENABLE[1] origin:064-gtp-channel-conf 01_662 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.FTS_DESKEW_SEQ_ENABLE[2] origin:064-gtp-channel-conf 00_663 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.FTS_DESKEW_SEQ_ENABLE[3] origin:064-gtp-channel-conf 01_663 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.FTS_LANE_DESKEW_CFG[0] origin:064-gtp-channel-conf 00_654 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.FTS_LANE_DESKEW_CFG[1] origin:064-gtp-channel-conf 01_654 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.FTS_LANE_DESKEW_CFG[2] origin:064-gtp-channel-conf 00_655 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.FTS_LANE_DESKEW_CFG[3] origin:064-gtp-channel-conf 01_655 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.FTS_LANE_DESKEW_EN origin:064-gtp-channel-conf 01_653 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.GEARBOX_MODE[0] origin:064-gtp-channel-conf 00_224 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.GEARBOX_MODE[1] origin:064-gtp-channel-conf 01_224 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.GEARBOX_MODE[2] origin:064-gtp-channel-conf 00_225 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.IN_USE origin:064-gtp-channel-conf 00_00 00_01 00_47 00_52 00_53 00_65 01_01 01_47 02_129 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.INV_DMONITORCLK origin:064-gtp-channel-conf 02_13 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.INV_DRPCLK origin:064-gtp-channel-conf 02_00 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.INV_RXUSRCLK origin:064-gtp-channel-conf 03_01 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.INV_SIGVALIDCLK origin:064-gtp-channel-conf 03_13 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.INV_TXPHDLYTSTCLK origin:064-gtp-channel-conf 02_03 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.INV_TXUSRCLK origin:064-gtp-channel-conf 03_04 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.INV_CLKRSVD0 origin:064-gtp-channel-conf 02_23 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.INV_CLKRSVD1 origin:064-gtp-channel-conf 03_23 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.INV_RXUSRCLK2 origin:064-gtp-channel-conf 02_02 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.INV_TXUSRCLK2 origin:064-gtp-channel-conf 02_05 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.LOOPBACK_CFG[0] origin:064-gtp-channel-conf 02_20 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.OUTREFCLK_SEL_INV[0] origin:064-gtp-channel-conf 00_149 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.OUTREFCLK_SEL_INV[1] origin:064-gtp-channel-conf 01_149 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PCS_PCIE_EN origin:064-gtp-channel-conf 00_216 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[0] origin:064-gtp-channel-conf 02_184 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[1] origin:064-gtp-channel-conf 03_184 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[2] origin:064-gtp-channel-conf 02_185 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[3] origin:064-gtp-channel-conf 03_185 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[4] origin:064-gtp-channel-conf 02_186 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[5] origin:064-gtp-channel-conf 03_186 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[6] origin:064-gtp-channel-conf 02_187 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[7] origin:064-gtp-channel-conf 03_187 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[8] origin:064-gtp-channel-conf 02_188 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[9] origin:064-gtp-channel-conf 03_188 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[10] origin:064-gtp-channel-conf 02_189 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[11] origin:064-gtp-channel-conf 03_189 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[12] origin:064-gtp-channel-conf 02_190 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[13] origin:064-gtp-channel-conf 03_190 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[14] origin:064-gtp-channel-conf 02_191 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[15] origin:064-gtp-channel-conf 03_191 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[16] origin:064-gtp-channel-conf 02_192 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[17] origin:064-gtp-channel-conf 03_192 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[18] origin:064-gtp-channel-conf 02_193 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[19] origin:064-gtp-channel-conf 03_193 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[20] origin:064-gtp-channel-conf 02_194 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[21] origin:064-gtp-channel-conf 03_194 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[22] origin:064-gtp-channel-conf 02_195 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[23] origin:064-gtp-channel-conf 03_195 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[24] origin:064-gtp-channel-conf 02_196 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[25] origin:064-gtp-channel-conf 03_196 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[26] origin:064-gtp-channel-conf 02_197 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[27] origin:064-gtp-channel-conf 03_197 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[28] origin:064-gtp-channel-conf 02_198 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[29] origin:064-gtp-channel-conf 03_198 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[30] origin:064-gtp-channel-conf 02_199 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[31] origin:064-gtp-channel-conf 03_199 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[32] origin:064-gtp-channel-conf 02_200 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[33] origin:064-gtp-channel-conf 03_200 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[34] origin:064-gtp-channel-conf 02_201 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[35] origin:064-gtp-channel-conf 03_201 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[36] origin:064-gtp-channel-conf 02_202 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[37] origin:064-gtp-channel-conf 03_202 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[38] origin:064-gtp-channel-conf 02_203 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[39] origin:064-gtp-channel-conf 03_203 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[40] origin:064-gtp-channel-conf 02_204 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[41] origin:064-gtp-channel-conf 03_204 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[42] origin:064-gtp-channel-conf 02_205 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[43] origin:064-gtp-channel-conf 03_205 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[44] origin:064-gtp-channel-conf 02_206 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[45] origin:064-gtp-channel-conf 03_206 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[46] origin:064-gtp-channel-conf 02_207 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[47] origin:064-gtp-channel-conf 03_207 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[0] origin:064-gtp-channel-conf 01_216 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[1] origin:064-gtp-channel-conf 00_217 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[2] origin:064-gtp-channel-conf 01_217 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[3] origin:064-gtp-channel-conf 00_218 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[4] origin:064-gtp-channel-conf 01_218 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[5] origin:064-gtp-channel-conf 00_219 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[6] origin:064-gtp-channel-conf 01_219 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[7] origin:064-gtp-channel-conf 00_220 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[8] origin:064-gtp-channel-conf 01_220 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[9] origin:064-gtp-channel-conf 00_221 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[10] origin:064-gtp-channel-conf 01_221 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[11] origin:064-gtp-channel-conf 00_222 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[0] origin:064-gtp-channel-conf 00_208 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[1] origin:064-gtp-channel-conf 01_208 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[2] origin:064-gtp-channel-conf 00_209 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[3] origin:064-gtp-channel-conf 01_209 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[4] origin:064-gtp-channel-conf 00_210 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[5] origin:064-gtp-channel-conf 01_210 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[6] origin:064-gtp-channel-conf 00_211 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[7] origin:064-gtp-channel-conf 01_211 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[0] origin:064-gtp-channel-conf 00_212 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[1] origin:064-gtp-channel-conf 01_212 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[2] origin:064-gtp-channel-conf 00_213 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[3] origin:064-gtp-channel-conf 01_213 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[4] origin:064-gtp-channel-conf 00_214 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[5] origin:064-gtp-channel-conf 01_214 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[6] origin:064-gtp-channel-conf 00_215 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[7] origin:064-gtp-channel-conf 01_215 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PMA_LOOPBACK_CFG[0] origin:064-gtp-channel-conf 01_207 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[0] origin:064-gtp-channel-conf 02_520 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[1] origin:064-gtp-channel-conf 03_520 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[2] origin:064-gtp-channel-conf 02_521 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[3] origin:064-gtp-channel-conf 03_521 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[4] origin:064-gtp-channel-conf 02_522 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[5] origin:064-gtp-channel-conf 03_522 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[6] origin:064-gtp-channel-conf 02_523 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[7] origin:064-gtp-channel-conf 03_523 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[8] origin:064-gtp-channel-conf 02_524 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[9] origin:064-gtp-channel-conf 03_524 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[10] origin:064-gtp-channel-conf 02_525 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[11] origin:064-gtp-channel-conf 03_525 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[12] origin:064-gtp-channel-conf 02_526 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[13] origin:064-gtp-channel-conf 03_526 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[14] origin:064-gtp-channel-conf 02_527 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[15] origin:064-gtp-channel-conf 03_527 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[16] origin:064-gtp-channel-conf 02_528 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[17] origin:064-gtp-channel-conf 03_528 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[18] origin:064-gtp-channel-conf 02_529 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[19] origin:064-gtp-channel-conf 03_529 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[20] origin:064-gtp-channel-conf 02_530 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[21] origin:064-gtp-channel-conf 03_530 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[22] origin:064-gtp-channel-conf 02_531 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[23] origin:064-gtp-channel-conf 03_531 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[24] origin:064-gtp-channel-conf 02_532 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[25] origin:064-gtp-channel-conf 03_532 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[26] origin:064-gtp-channel-conf 02_533 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[27] origin:064-gtp-channel-conf 03_533 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[28] origin:064-gtp-channel-conf 02_534 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[29] origin:064-gtp-channel-conf 03_534 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[30] origin:064-gtp-channel-conf 02_535 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[31] origin:064-gtp-channel-conf 03_535 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[0] origin:064-gtp-channel-conf 02_336 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[1] origin:064-gtp-channel-conf 03_336 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[2] origin:064-gtp-channel-conf 02_337 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[3] origin:064-gtp-channel-conf 03_337 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[4] origin:064-gtp-channel-conf 02_338 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[5] origin:064-gtp-channel-conf 03_338 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[6] origin:064-gtp-channel-conf 02_339 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[7] origin:064-gtp-channel-conf 03_339 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[8] origin:064-gtp-channel-conf 02_340 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[9] origin:064-gtp-channel-conf 03_340 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[10] origin:064-gtp-channel-conf 02_341 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[11] origin:064-gtp-channel-conf 03_341 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[12] origin:064-gtp-channel-conf 02_342 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[13] origin:064-gtp-channel-conf 03_342 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[14] origin:064-gtp-channel-conf 02_343 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[15] origin:064-gtp-channel-conf 03_343 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[16] origin:064-gtp-channel-conf 02_344 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[17] origin:064-gtp-channel-conf 03_344 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[18] origin:064-gtp-channel-conf 02_345 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[19] origin:064-gtp-channel-conf 03_345 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[20] origin:064-gtp-channel-conf 02_346 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[21] origin:064-gtp-channel-conf 03_346 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[22] origin:064-gtp-channel-conf 02_347 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[23] origin:064-gtp-channel-conf 03_347 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[24] origin:064-gtp-channel-conf 02_348 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[25] origin:064-gtp-channel-conf 03_348 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[26] origin:064-gtp-channel-conf 02_349 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[27] origin:064-gtp-channel-conf 03_349 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[28] origin:064-gtp-channel-conf 02_350 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[29] origin:064-gtp-channel-conf 03_350 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[30] origin:064-gtp-channel-conf 02_351 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[31] origin:064-gtp-channel-conf 03_351 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PMA_RSV3[0] origin:064-gtp-channel-conf 02_288 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PMA_RSV3[1] origin:064-gtp-channel-conf 03_288 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PMA_RSV4[0] origin:064-gtp-channel-conf 02_156 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PMA_RSV4[1] origin:064-gtp-channel-conf 03_156 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PMA_RSV4[2] origin:064-gtp-channel-conf 02_157 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PMA_RSV4[3] origin:064-gtp-channel-conf 03_157 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PMA_RSV5[0] origin:064-gtp-channel-conf 03_159 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PMA_RSV6[0] origin:064-gtp-channel-conf 02_303 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.PMA_RSV7[0] origin:064-gtp-channel-conf 03_303 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_BIAS_CFG[0] origin:064-gtp-channel-conf 02_112 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_BIAS_CFG[1] origin:064-gtp-channel-conf 03_112 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_BIAS_CFG[2] origin:064-gtp-channel-conf 02_113 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_BIAS_CFG[3] origin:064-gtp-channel-conf 03_113 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_BIAS_CFG[4] origin:064-gtp-channel-conf 02_114 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_BIAS_CFG[5] origin:064-gtp-channel-conf 03_114 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_BIAS_CFG[6] origin:064-gtp-channel-conf 02_115 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_BIAS_CFG[7] origin:064-gtp-channel-conf 03_115 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_BIAS_CFG[8] origin:064-gtp-channel-conf 02_116 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_BIAS_CFG[9] origin:064-gtp-channel-conf 03_116 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_BIAS_CFG[10] origin:064-gtp-channel-conf 02_117 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_BIAS_CFG[11] origin:064-gtp-channel-conf 03_117 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_BIAS_CFG[12] origin:064-gtp-channel-conf 02_118 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_BIAS_CFG[13] origin:064-gtp-channel-conf 03_118 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_BIAS_CFG[14] origin:064-gtp-channel-conf 02_119 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_BIAS_CFG[15] origin:064-gtp-channel-conf 03_119 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_BUFFER_CFG[0] origin:064-gtp-channel-conf 02_536 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_BUFFER_CFG[1] origin:064-gtp-channel-conf 03_536 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_BUFFER_CFG[2] origin:064-gtp-channel-conf 02_537 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_BUFFER_CFG[3] origin:064-gtp-channel-conf 03_537 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_BUFFER_CFG[4] origin:064-gtp-channel-conf 02_538 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_BUFFER_CFG[5] origin:064-gtp-channel-conf 03_538 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_CLKMUX_EN[0] origin:064-gtp-channel-conf 02_128 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_CM_SEL[0] origin:064-gtp-channel-conf 00_138 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_CM_SEL[1] origin:064-gtp-channel-conf 01_138 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_CM_TRIM[0] origin:064-gtp-channel-conf 02_304 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_CM_TRIM[1] origin:064-gtp-channel-conf 03_304 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_CM_TRIM[2] origin:064-gtp-channel-conf 02_305 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_CM_TRIM[3] origin:064-gtp-channel-conf 03_305 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_DATA_WIDTH[0] origin:064-gtp-channel-conf 01_141 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_DATA_WIDTH[1] origin:064-gtp-channel-conf 00_142 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_DATA_WIDTH[2] origin:064-gtp-channel-conf 01_142 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_DDI_SEL[0] origin:064-gtp-channel-conf 00_696 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_DDI_SEL[1] origin:064-gtp-channel-conf 01_696 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_DDI_SEL[2] origin:064-gtp-channel-conf 00_697 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_DDI_SEL[3] origin:064-gtp-channel-conf 01_697 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_DDI_SEL[4] origin:064-gtp-channel-conf 00_698 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_DDI_SEL[5] origin:064-gtp-channel-conf 01_698 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_DEBUG_CFG[0] origin:064-gtp-channel-conf 02_616 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_DEBUG_CFG[1] origin:064-gtp-channel-conf 03_616 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_DEBUG_CFG[2] origin:064-gtp-channel-conf 02_617 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_DEBUG_CFG[3] origin:064-gtp-channel-conf 03_617 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_DEBUG_CFG[4] origin:064-gtp-channel-conf 02_618 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_DEBUG_CFG[5] origin:064-gtp-channel-conf 03_618 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_DEBUG_CFG[6] origin:064-gtp-channel-conf 02_619 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_DEBUG_CFG[7] origin:064-gtp-channel-conf 03_619 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_DEBUG_CFG[8] origin:064-gtp-channel-conf 02_620 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_DEBUG_CFG[9] origin:064-gtp-channel-conf 03_620 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_DEBUG_CFG[10] origin:064-gtp-channel-conf 02_621 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_DEBUG_CFG[11] origin:064-gtp-channel-conf 03_621 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_DEBUG_CFG[12] origin:064-gtp-channel-conf 02_622 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_DEBUG_CFG[13] origin:064-gtp-channel-conf 03_622 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_DEFER_RESET_BUF_EN origin:064-gtp-channel-conf 02_552 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_DISPERR_SEQ_MATCH origin:064-gtp-channel-conf 01_495 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_OS_CFG[0] origin:064-gtp-channel-conf 00_288 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_OS_CFG[1] origin:064-gtp-channel-conf 01_288 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_OS_CFG[2] origin:064-gtp-channel-conf 00_289 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_OS_CFG[3] origin:064-gtp-channel-conf 01_289 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_OS_CFG[4] origin:064-gtp-channel-conf 00_290 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_OS_CFG[5] origin:064-gtp-channel-conf 01_290 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_OS_CFG[6] origin:064-gtp-channel-conf 00_291 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_OS_CFG[7] origin:064-gtp-channel-conf 01_291 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_OS_CFG[8] origin:064-gtp-channel-conf 00_292 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_OS_CFG[9] origin:064-gtp-channel-conf 01_292 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_OS_CFG[10] origin:064-gtp-channel-conf 00_293 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_OS_CFG[11] origin:064-gtp-channel-conf 01_293 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_OS_CFG[12] origin:064-gtp-channel-conf 00_294 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_SIG_VALID_DLY[0] origin:064-gtp-channel-conf 00_524 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_SIG_VALID_DLY[1] origin:064-gtp-channel-conf 01_524 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_SIG_VALID_DLY[2] origin:064-gtp-channel-conf 00_525 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_SIG_VALID_DLY[3] origin:064-gtp-channel-conf 01_525 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_SIG_VALID_DLY[4] origin:064-gtp-channel-conf 00_526 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_XCLK_SEL.RXUSR origin:064-gtp-channel-conf 00_143 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_CLK25_DIV[0] origin:064-gtp-channel-conf 00_139 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_CLK25_DIV[1] origin:064-gtp-channel-conf 01_139 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_CLK25_DIV[2] origin:064-gtp-channel-conf 00_140 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_CLK25_DIV[3] origin:064-gtp-channel-conf 01_140 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RX_CLK25_DIV[4] origin:064-gtp-channel-conf 00_141 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXBUF_ADDR_MODE.FAST origin:064-gtp-channel-conf 03_555 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXBUF_EIDLE_HI_CNT[0] origin:064-gtp-channel-conf 02_558 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXBUF_EIDLE_HI_CNT[1] origin:064-gtp-channel-conf 03_558 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXBUF_EIDLE_HI_CNT[2] origin:064-gtp-channel-conf 02_559 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXBUF_EIDLE_HI_CNT[3] origin:064-gtp-channel-conf 03_559 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXBUF_EIDLE_LO_CNT[0] origin:064-gtp-channel-conf 02_556 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXBUF_EIDLE_LO_CNT[1] origin:064-gtp-channel-conf 03_556 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXBUF_EIDLE_LO_CNT[2] origin:064-gtp-channel-conf 02_557 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXBUF_EIDLE_LO_CNT[3] origin:064-gtp-channel-conf 03_557 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXBUF_EN origin:064-gtp-channel-conf 02_11 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXBUF_RESET_ON_CB_CHANGE origin:064-gtp-channel-conf 02_560 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXBUF_RESET_ON_COMMAALIGN origin:064-gtp-channel-conf 02_561 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXBUF_RESET_ON_EIDLE origin:064-gtp-channel-conf 02_547 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXBUF_RESET_ON_RATE_CHANGE origin:064-gtp-channel-conf 03_560 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXBUF_THRESH_OVFLW[0] origin:064-gtp-channel-conf 03_552 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXBUF_THRESH_OVFLW[1] origin:064-gtp-channel-conf 02_553 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXBUF_THRESH_OVFLW[2] origin:064-gtp-channel-conf 03_553 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXBUF_THRESH_OVFLW[3] origin:064-gtp-channel-conf 02_554 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXBUF_THRESH_OVFLW[4] origin:064-gtp-channel-conf 03_554 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXBUF_THRESH_OVFLW[5] origin:064-gtp-channel-conf 02_555 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXBUF_THRESH_OVRD origin:064-gtp-channel-conf 02_548 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXBUF_THRESH_UNDFLW[0] origin:064-gtp-channel-conf 02_544 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXBUF_THRESH_UNDFLW[1] origin:064-gtp-channel-conf 03_544 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXBUF_THRESH_UNDFLW[2] origin:064-gtp-channel-conf 02_545 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXBUF_THRESH_UNDFLW[3] origin:064-gtp-channel-conf 03_545 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXBUF_THRESH_UNDFLW[4] origin:064-gtp-channel-conf 02_546 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXBUF_THRESH_UNDFLW[5] origin:064-gtp-channel-conf 03_546 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXBUFRESET_TIME[0] origin:064-gtp-channel-conf 01_101 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXBUFRESET_TIME[1] origin:064-gtp-channel-conf 00_102 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXBUFRESET_TIME[2] origin:064-gtp-channel-conf 01_102 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXBUFRESET_TIME[3] origin:064-gtp-channel-conf 00_103 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXBUFRESET_TIME[4] origin:064-gtp-channel-conf 01_103 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[0] origin:064-gtp-channel-conf 02_640 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[1] origin:064-gtp-channel-conf 03_640 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[2] origin:064-gtp-channel-conf 02_641 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[3] origin:064-gtp-channel-conf 03_641 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[4] origin:064-gtp-channel-conf 02_642 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[5] origin:064-gtp-channel-conf 03_642 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[6] origin:064-gtp-channel-conf 02_643 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[7] origin:064-gtp-channel-conf 03_643 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[8] origin:064-gtp-channel-conf 02_644 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[9] origin:064-gtp-channel-conf 03_644 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[10] origin:064-gtp-channel-conf 02_645 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[11] origin:064-gtp-channel-conf 03_645 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[12] origin:064-gtp-channel-conf 02_646 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[13] origin:064-gtp-channel-conf 03_646 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[14] origin:064-gtp-channel-conf 02_647 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[15] origin:064-gtp-channel-conf 03_647 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[16] origin:064-gtp-channel-conf 02_648 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[17] origin:064-gtp-channel-conf 03_648 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[18] origin:064-gtp-channel-conf 02_649 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[19] origin:064-gtp-channel-conf 03_649 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[20] origin:064-gtp-channel-conf 02_650 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[21] origin:064-gtp-channel-conf 03_650 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[22] origin:064-gtp-channel-conf 02_651 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[23] origin:064-gtp-channel-conf 03_651 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[24] origin:064-gtp-channel-conf 02_652 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[25] origin:064-gtp-channel-conf 03_652 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[26] origin:064-gtp-channel-conf 02_653 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[27] origin:064-gtp-channel-conf 03_653 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[28] origin:064-gtp-channel-conf 02_654 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[29] origin:064-gtp-channel-conf 03_654 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[30] origin:064-gtp-channel-conf 02_655 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[31] origin:064-gtp-channel-conf 03_655 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[32] origin:064-gtp-channel-conf 02_656 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[33] origin:064-gtp-channel-conf 03_656 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[34] origin:064-gtp-channel-conf 02_657 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[35] origin:064-gtp-channel-conf 03_657 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[36] origin:064-gtp-channel-conf 02_658 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[37] origin:064-gtp-channel-conf 03_658 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[38] origin:064-gtp-channel-conf 02_659 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[39] origin:064-gtp-channel-conf 03_659 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[40] origin:064-gtp-channel-conf 02_660 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[41] origin:064-gtp-channel-conf 03_660 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[42] origin:064-gtp-channel-conf 02_661 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[43] origin:064-gtp-channel-conf 03_661 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[44] origin:064-gtp-channel-conf 02_662 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[45] origin:064-gtp-channel-conf 03_662 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[46] origin:064-gtp-channel-conf 02_663 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[47] origin:064-gtp-channel-conf 03_663 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[48] origin:064-gtp-channel-conf 02_664 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[49] origin:064-gtp-channel-conf 03_664 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[50] origin:064-gtp-channel-conf 02_665 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[51] origin:064-gtp-channel-conf 03_665 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[52] origin:064-gtp-channel-conf 02_666 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[53] origin:064-gtp-channel-conf 03_666 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[54] origin:064-gtp-channel-conf 02_667 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[55] origin:064-gtp-channel-conf 03_667 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[56] origin:064-gtp-channel-conf 02_668 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[57] origin:064-gtp-channel-conf 03_668 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[58] origin:064-gtp-channel-conf 02_669 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[59] origin:064-gtp-channel-conf 03_669 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[60] origin:064-gtp-channel-conf 02_670 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[61] origin:064-gtp-channel-conf 03_670 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[62] origin:064-gtp-channel-conf 02_671 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[63] origin:064-gtp-channel-conf 03_671 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[64] origin:064-gtp-channel-conf 02_672 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[65] origin:064-gtp-channel-conf 03_672 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[66] origin:064-gtp-channel-conf 02_673 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[67] origin:064-gtp-channel-conf 03_673 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[68] origin:064-gtp-channel-conf 02_674 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[69] origin:064-gtp-channel-conf 03_674 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[70] origin:064-gtp-channel-conf 02_675 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[71] origin:064-gtp-channel-conf 03_675 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[72] origin:064-gtp-channel-conf 02_676 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[73] origin:064-gtp-channel-conf 03_676 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[74] origin:064-gtp-channel-conf 02_677 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[75] origin:064-gtp-channel-conf 03_677 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[76] origin:064-gtp-channel-conf 02_678 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[77] origin:064-gtp-channel-conf 03_678 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[78] origin:064-gtp-channel-conf 02_679 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[79] origin:064-gtp-channel-conf 03_679 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[80] origin:064-gtp-channel-conf 02_680 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[81] origin:064-gtp-channel-conf 03_680 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[82] origin:064-gtp-channel-conf 02_681 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_FR_RESET_ON_EIDLE[0] origin:064-gtp-channel-conf 02_638 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_HOLD_DURING_EIDLE[0] origin:064-gtp-channel-conf 03_637 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_LOCK_CFG[0] origin:064-gtp-channel-conf 02_632 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_LOCK_CFG[1] origin:064-gtp-channel-conf 03_632 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_LOCK_CFG[2] origin:064-gtp-channel-conf 02_633 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_LOCK_CFG[3] origin:064-gtp-channel-conf 03_633 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_LOCK_CFG[4] origin:064-gtp-channel-conf 02_634 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_LOCK_CFG[5] origin:064-gtp-channel-conf 03_634 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDR_PH_RESET_ON_EIDLE[0] origin:064-gtp-channel-conf 03_638 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDRFREQRESET_TIME[0] origin:064-gtp-channel-conf 01_106 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDRFREQRESET_TIME[1] origin:064-gtp-channel-conf 00_107 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDRFREQRESET_TIME[2] origin:064-gtp-channel-conf 01_107 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDRFREQRESET_TIME[3] origin:064-gtp-channel-conf 00_108 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDRFREQRESET_TIME[4] origin:064-gtp-channel-conf 01_108 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDRPHRESET_TIME[0] origin:064-gtp-channel-conf 00_109 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDRPHRESET_TIME[1] origin:064-gtp-channel-conf 01_109 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDRPHRESET_TIME[2] origin:064-gtp-channel-conf 00_110 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDRPHRESET_TIME[3] origin:064-gtp-channel-conf 01_110 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXCDRPHRESET_TIME[4] origin:064-gtp-channel-conf 00_111 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXDLY_CFG[0] origin:064-gtp-channel-conf 00_680 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXDLY_CFG[1] origin:064-gtp-channel-conf 01_680 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXDLY_CFG[2] origin:064-gtp-channel-conf 00_681 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXDLY_CFG[3] origin:064-gtp-channel-conf 01_681 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXDLY_CFG[4] origin:064-gtp-channel-conf 00_682 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXDLY_CFG[5] origin:064-gtp-channel-conf 01_682 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXDLY_CFG[6] origin:064-gtp-channel-conf 00_683 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXDLY_CFG[7] origin:064-gtp-channel-conf 01_683 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXDLY_CFG[8] origin:064-gtp-channel-conf 00_684 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXDLY_CFG[9] origin:064-gtp-channel-conf 01_684 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXDLY_CFG[10] origin:064-gtp-channel-conf 00_685 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXDLY_CFG[11] origin:064-gtp-channel-conf 01_685 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXDLY_CFG[12] origin:064-gtp-channel-conf 00_686 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXDLY_CFG[13] origin:064-gtp-channel-conf 01_686 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXDLY_CFG[14] origin:064-gtp-channel-conf 00_687 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXDLY_CFG[15] origin:064-gtp-channel-conf 01_687 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXDLY_LCFG[0] origin:064-gtp-channel-conf 02_576 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXDLY_LCFG[1] origin:064-gtp-channel-conf 03_576 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXDLY_LCFG[2] origin:064-gtp-channel-conf 02_577 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXDLY_LCFG[3] origin:064-gtp-channel-conf 03_577 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXDLY_LCFG[4] origin:064-gtp-channel-conf 02_578 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXDLY_LCFG[5] origin:064-gtp-channel-conf 03_578 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXDLY_LCFG[6] origin:064-gtp-channel-conf 02_579 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXDLY_LCFG[7] origin:064-gtp-channel-conf 03_579 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXDLY_LCFG[8] origin:064-gtp-channel-conf 02_580 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXDLY_TAP_CFG[0] origin:064-gtp-channel-conf 00_672 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXDLY_TAP_CFG[1] origin:064-gtp-channel-conf 01_672 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXDLY_TAP_CFG[2] origin:064-gtp-channel-conf 00_673 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXDLY_TAP_CFG[3] origin:064-gtp-channel-conf 01_673 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXDLY_TAP_CFG[4] origin:064-gtp-channel-conf 00_674 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXDLY_TAP_CFG[5] origin:064-gtp-channel-conf 01_674 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXDLY_TAP_CFG[6] origin:064-gtp-channel-conf 00_675 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXDLY_TAP_CFG[7] origin:064-gtp-channel-conf 01_675 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXDLY_TAP_CFG[8] origin:064-gtp-channel-conf 00_676 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXDLY_TAP_CFG[9] origin:064-gtp-channel-conf 01_676 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXDLY_TAP_CFG[10] origin:064-gtp-channel-conf 00_677 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXDLY_TAP_CFG[11] origin:064-gtp-channel-conf 01_677 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXDLY_TAP_CFG[12] origin:064-gtp-channel-conf 00_678 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXDLY_TAP_CFG[13] origin:064-gtp-channel-conf 01_678 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXDLY_TAP_CFG[14] origin:064-gtp-channel-conf 00_679 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXDLY_TAP_CFG[15] origin:064-gtp-channel-conf 01_679 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXGEARBOX_EN origin:064-gtp-channel-conf 01_607 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXISCANRESET_TIME[0] origin:064-gtp-channel-conf 01_123 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXISCANRESET_TIME[1] origin:064-gtp-channel-conf 00_124 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXISCANRESET_TIME[2] origin:064-gtp-channel-conf 01_124 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXISCANRESET_TIME[3] origin:064-gtp-channel-conf 00_125 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXISCANRESET_TIME[4] origin:064-gtp-channel-conf 01_125 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPM_BIAS_STARTUP_DISABLE[0] origin:064-gtp-channel-conf 03_391 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPM_CFG[0] origin:064-gtp-channel-conf 02_328 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPM_CFG[1] origin:064-gtp-channel-conf 03_328 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPM_CFG[2] origin:064-gtp-channel-conf 02_329 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPM_CFG[3] origin:064-gtp-channel-conf 03_329 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPM_CM_CFG[0] origin:064-gtp-channel-conf 02_430 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPM_GC_CFG[0] origin:064-gtp-channel-conf 02_432 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPM_GC_CFG[1] origin:064-gtp-channel-conf 03_432 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPM_GC_CFG[2] origin:064-gtp-channel-conf 02_433 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPM_GC_CFG[3] origin:064-gtp-channel-conf 03_433 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPM_GC_CFG[4] origin:064-gtp-channel-conf 02_434 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPM_GC_CFG[5] origin:064-gtp-channel-conf 03_434 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPM_GC_CFG[6] origin:064-gtp-channel-conf 02_435 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPM_GC_CFG[7] origin:064-gtp-channel-conf 03_435 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPM_GC_CFG[8] origin:064-gtp-channel-conf 02_436 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPM_GC_CFG2[0] origin:064-gtp-channel-conf 03_442 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPM_GC_CFG2[1] origin:064-gtp-channel-conf 02_443 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPM_GC_CFG2[2] origin:064-gtp-channel-conf 03_443 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG[0] origin:064-gtp-channel-conf 00_336 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG[1] origin:064-gtp-channel-conf 01_336 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG[2] origin:064-gtp-channel-conf 00_337 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG[3] origin:064-gtp-channel-conf 01_337 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG[4] origin:064-gtp-channel-conf 00_338 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG[5] origin:064-gtp-channel-conf 01_338 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG[6] origin:064-gtp-channel-conf 00_339 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG[7] origin:064-gtp-channel-conf 01_339 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG[8] origin:064-gtp-channel-conf 00_340 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG[9] origin:064-gtp-channel-conf 01_340 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG[10] origin:064-gtp-channel-conf 00_341 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG[11] origin:064-gtp-channel-conf 01_341 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG[12] origin:064-gtp-channel-conf 00_342 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG[13] origin:064-gtp-channel-conf 01_342 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG2[0] origin:064-gtp-channel-conf 02_424 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG2[1] origin:064-gtp-channel-conf 03_424 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG2[2] origin:064-gtp-channel-conf 02_425 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG2[3] origin:064-gtp-channel-conf 03_425 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG2[4] origin:064-gtp-channel-conf 02_426 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG3[0] origin:064-gtp-channel-conf 03_389 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG3[1] origin:064-gtp-channel-conf 02_390 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG3[2] origin:064-gtp-channel-conf 03_390 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG3[3] origin:064-gtp-channel-conf 02_391 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPM_HOLD_DURING_EIDLE[0] origin:064-gtp-channel-conf 00_247 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPM_INCM_CFG[0] origin:064-gtp-channel-conf 02_439 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPM_IPCM_CFG[0] origin:064-gtp-channel-conf 03_439 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG[0] origin:064-gtp-channel-conf 00_344 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG[1] origin:064-gtp-channel-conf 01_344 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG[2] origin:064-gtp-channel-conf 00_345 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG[3] origin:064-gtp-channel-conf 01_345 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG[4] origin:064-gtp-channel-conf 00_346 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG[5] origin:064-gtp-channel-conf 01_346 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG[6] origin:064-gtp-channel-conf 00_347 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG[7] origin:064-gtp-channel-conf 01_347 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG[8] origin:064-gtp-channel-conf 00_348 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG[9] origin:064-gtp-channel-conf 01_348 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG[10] origin:064-gtp-channel-conf 00_349 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG[11] origin:064-gtp-channel-conf 01_349 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG[12] origin:064-gtp-channel-conf 00_350 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG[13] origin:064-gtp-channel-conf 01_350 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG[14] origin:064-gtp-channel-conf 00_351 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG[15] origin:064-gtp-channel-conf 01_351 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG[16] origin:064-gtp-channel-conf 00_343 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG[17] origin:064-gtp-channel-conf 01_343 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG2[0] origin:064-gtp-channel-conf 03_426 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG2[1] origin:064-gtp-channel-conf 02_427 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG2[2] origin:064-gtp-channel-conf 03_427 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG2[3] origin:064-gtp-channel-conf 02_428 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG2[4] origin:064-gtp-channel-conf 03_428 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPM_OSINT_CFG[0] origin:064-gtp-channel-conf 02_440 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPM_OSINT_CFG[1] origin:064-gtp-channel-conf 03_440 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPM_OSINT_CFG[2] origin:064-gtp-channel-conf 02_441 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPM_CFG1[0] origin:064-gtp-channel-conf 02_330 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPMRESET_TIME[0] origin:064-gtp-channel-conf 00_112 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPMRESET_TIME[1] origin:064-gtp-channel-conf 01_112 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPMRESET_TIME[2] origin:064-gtp-channel-conf 00_113 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPMRESET_TIME[3] origin:064-gtp-channel-conf 01_113 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPMRESET_TIME[4] origin:064-gtp-channel-conf 00_114 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPMRESET_TIME[5] origin:064-gtp-channel-conf 01_114 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXLPMRESET_TIME[6] origin:064-gtp-channel-conf 00_115 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXOOB_CFG[0] origin:064-gtp-channel-conf 00_144 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXOOB_CFG[1] origin:064-gtp-channel-conf 01_144 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXOOB_CFG[2] origin:064-gtp-channel-conf 00_145 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXOOB_CFG[3] origin:064-gtp-channel-conf 01_145 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXOOB_CFG[4] origin:064-gtp-channel-conf 00_146 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXOOB_CFG[5] origin:064-gtp-channel-conf 01_146 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXOOB_CFG[6] origin:064-gtp-channel-conf 00_147 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXOOB_CLK_CFG.FABRIC origin:064-gtp-channel-conf 03_129 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXOSCALRESET_TIME[0] origin:064-gtp-channel-conf 00_187 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXOSCALRESET_TIME[1] origin:064-gtp-channel-conf 01_187 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXOSCALRESET_TIME[2] origin:064-gtp-channel-conf 00_188 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXOSCALRESET_TIME[3] origin:064-gtp-channel-conf 01_188 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXOSCALRESET_TIME[4] origin:064-gtp-channel-conf 00_189 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXOSCALRESET_TIMEOUT[0] origin:064-gtp-channel-conf 01_189 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXOSCALRESET_TIMEOUT[1] origin:064-gtp-channel-conf 00_190 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXOSCALRESET_TIMEOUT[2] origin:064-gtp-channel-conf 01_190 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXOSCALRESET_TIMEOUT[3] origin:064-gtp-channel-conf 00_191 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXOSCALRESET_TIMEOUT[4] origin:064-gtp-channel-conf 01_191 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXOUT_DIV[0] origin:064-gtp-channel-conf 02_384 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXOUT_DIV[1] origin:064-gtp-channel-conf 03_384 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXPCSRESET_TIME[0] origin:064-gtp-channel-conf 01_115 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXPCSRESET_TIME[1] origin:064-gtp-channel-conf 00_116 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXPCSRESET_TIME[2] origin:064-gtp-channel-conf 01_116 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXPCSRESET_TIME[3] origin:064-gtp-channel-conf 00_117 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXPCSRESET_TIME[4] origin:064-gtp-channel-conf 01_117 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[0] origin:064-gtp-channel-conf 02_584 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[1] origin:064-gtp-channel-conf 03_584 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[2] origin:064-gtp-channel-conf 02_585 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[3] origin:064-gtp-channel-conf 03_585 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[4] origin:064-gtp-channel-conf 02_586 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[5] origin:064-gtp-channel-conf 03_586 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[6] origin:064-gtp-channel-conf 02_587 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[7] origin:064-gtp-channel-conf 03_587 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[8] origin:064-gtp-channel-conf 02_588 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[9] origin:064-gtp-channel-conf 03_588 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[10] origin:064-gtp-channel-conf 02_589 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[11] origin:064-gtp-channel-conf 03_589 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[12] origin:064-gtp-channel-conf 02_590 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[13] origin:064-gtp-channel-conf 03_590 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[14] origin:064-gtp-channel-conf 02_591 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[15] origin:064-gtp-channel-conf 03_591 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[16] origin:064-gtp-channel-conf 02_592 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[17] origin:064-gtp-channel-conf 03_592 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[18] origin:064-gtp-channel-conf 02_593 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[19] origin:064-gtp-channel-conf 03_593 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[20] origin:064-gtp-channel-conf 02_594 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[21] origin:064-gtp-channel-conf 03_594 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[22] origin:064-gtp-channel-conf 02_595 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[23] origin:064-gtp-channel-conf 03_595 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXPH_MONITOR_SEL[0] origin:064-gtp-channel-conf 00_700 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXPH_MONITOR_SEL[1] origin:064-gtp-channel-conf 01_700 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXPH_MONITOR_SEL[2] origin:064-gtp-channel-conf 00_701 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXPH_MONITOR_SEL[3] origin:064-gtp-channel-conf 01_701 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXPH_MONITOR_SEL[4] origin:064-gtp-channel-conf 00_702 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[0] origin:064-gtp-channel-conf 02_600 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[1] origin:064-gtp-channel-conf 03_600 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[2] origin:064-gtp-channel-conf 02_601 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[3] origin:064-gtp-channel-conf 03_601 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[4] origin:064-gtp-channel-conf 02_602 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[5] origin:064-gtp-channel-conf 03_602 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[6] origin:064-gtp-channel-conf 02_603 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[7] origin:064-gtp-channel-conf 03_603 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[8] origin:064-gtp-channel-conf 02_604 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[9] origin:064-gtp-channel-conf 03_604 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[10] origin:064-gtp-channel-conf 02_605 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[11] origin:064-gtp-channel-conf 03_605 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[12] origin:064-gtp-channel-conf 02_606 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[13] origin:064-gtp-channel-conf 03_606 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[14] origin:064-gtp-channel-conf 02_607 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[15] origin:064-gtp-channel-conf 03_607 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[16] origin:064-gtp-channel-conf 02_608 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[17] origin:064-gtp-channel-conf 03_608 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[18] origin:064-gtp-channel-conf 02_609 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[19] origin:064-gtp-channel-conf 03_609 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[20] origin:064-gtp-channel-conf 02_610 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[21] origin:064-gtp-channel-conf 03_610 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[22] origin:064-gtp-channel-conf 02_611 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[23] origin:064-gtp-channel-conf 03_611 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXPI_CFG0[0] origin:064-gtp-channel-conf 03_430 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXPI_CFG0[1] origin:064-gtp-channel-conf 02_431 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXPI_CFG0[2] origin:064-gtp-channel-conf 03_431 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXPI_CFG1[0] origin:064-gtp-channel-conf 02_442 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXPI_CFG2[0] origin:064-gtp-channel-conf 03_441 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXPMARESET_TIME[0] origin:064-gtp-channel-conf 00_104 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXPMARESET_TIME[1] origin:064-gtp-channel-conf 01_104 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXPMARESET_TIME[2] origin:064-gtp-channel-conf 00_105 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXPMARESET_TIME[3] origin:064-gtp-channel-conf 01_105 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXPMARESET_TIME[4] origin:064-gtp-channel-conf 00_106 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXPRBS_ERR_LOOPBACK[0] origin:064-gtp-channel-conf 00_136 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXSLIDE_AUTO_WAIT[0] origin:064-gtp-channel-conf 00_520 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXSLIDE_AUTO_WAIT[1] origin:064-gtp-channel-conf 01_520 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXSLIDE_AUTO_WAIT[2] origin:064-gtp-channel-conf 00_521 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXSLIDE_AUTO_WAIT[3] origin:064-gtp-channel-conf 01_521 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXSLIDE_MODE.AUTO origin:064-gtp-channel-conf !01_519 00_519 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXSLIDE_MODE.PCS origin:064-gtp-channel-conf !00_519 01_519 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXSLIDE_MODE.PMA origin:064-gtp-channel-conf 00_519 01_519 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXSYNC_MULTILANE[0] origin:064-gtp-channel-conf 00_133 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXSYNC_OVRD[0] origin:064-gtp-channel-conf 01_135 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.RXSYNC_SKIP_DA[0] origin:064-gtp-channel-conf 01_134 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.SAS_MAX_COM[0] origin:064-gtp-channel-conf 00_171 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.SAS_MAX_COM[1] origin:064-gtp-channel-conf 01_171 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.SAS_MAX_COM[2] origin:064-gtp-channel-conf 00_172 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.SAS_MAX_COM[3] origin:064-gtp-channel-conf 01_172 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.SAS_MAX_COM[4] origin:064-gtp-channel-conf 00_173 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.SAS_MAX_COM[5] origin:064-gtp-channel-conf 01_173 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.SAS_MAX_COM[6] origin:064-gtp-channel-conf 00_174 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.SAS_MIN_COM[0] origin:064-gtp-channel-conf 01_156 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.SAS_MIN_COM[1] origin:064-gtp-channel-conf 00_157 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.SAS_MIN_COM[2] origin:064-gtp-channel-conf 01_157 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.SAS_MIN_COM[3] origin:064-gtp-channel-conf 00_158 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.SAS_MIN_COM[4] origin:064-gtp-channel-conf 01_158 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.SAS_MIN_COM[5] origin:064-gtp-channel-conf 00_159 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.SATA_BURST_SEQ_LEN[0] origin:064-gtp-channel-conf 00_150 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.SATA_BURST_SEQ_LEN[1] origin:064-gtp-channel-conf 01_150 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.SATA_BURST_SEQ_LEN[2] origin:064-gtp-channel-conf 00_151 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.SATA_BURST_SEQ_LEN[3] origin:064-gtp-channel-conf 01_151 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.SATA_BURST_VAL[0] origin:064-gtp-channel-conf 01_147 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.SATA_BURST_VAL[1] origin:064-gtp-channel-conf 00_148 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.SATA_BURST_VAL[2] origin:064-gtp-channel-conf 01_148 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.SATA_EIDLE_VAL[0] origin:064-gtp-channel-conf 00_152 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.SATA_EIDLE_VAL[1] origin:064-gtp-channel-conf 01_152 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.SATA_EIDLE_VAL[2] origin:064-gtp-channel-conf 00_153 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.SATA_MAX_BURST[0] origin:064-gtp-channel-conf 00_168 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.SATA_MAX_BURST[1] origin:064-gtp-channel-conf 01_168 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.SATA_MAX_BURST[2] origin:064-gtp-channel-conf 00_169 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.SATA_MAX_BURST[3] origin:064-gtp-channel-conf 01_169 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.SATA_MAX_BURST[4] origin:064-gtp-channel-conf 00_170 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.SATA_MAX_BURST[5] origin:064-gtp-channel-conf 01_170 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.SATA_MAX_INIT[0] origin:064-gtp-channel-conf 00_176 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.SATA_MAX_INIT[1] origin:064-gtp-channel-conf 01_176 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.SATA_MAX_INIT[2] origin:064-gtp-channel-conf 00_177 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.SATA_MAX_INIT[3] origin:064-gtp-channel-conf 01_177 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.SATA_MAX_INIT[4] origin:064-gtp-channel-conf 00_178 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.SATA_MAX_INIT[5] origin:064-gtp-channel-conf 01_178 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.SATA_MAX_WAKE[0] origin:064-gtp-channel-conf 00_179 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.SATA_MAX_WAKE[1] origin:064-gtp-channel-conf 01_179 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.SATA_MAX_WAKE[2] origin:064-gtp-channel-conf 00_180 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.SATA_MAX_WAKE[3] origin:064-gtp-channel-conf 01_180 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.SATA_MAX_WAKE[4] origin:064-gtp-channel-conf 00_181 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.SATA_MAX_WAKE[5] origin:064-gtp-channel-conf 01_181 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.SATA_MIN_BURST[0] origin:064-gtp-channel-conf 01_153 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.SATA_MIN_BURST[1] origin:064-gtp-channel-conf 00_154 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.SATA_MIN_BURST[2] origin:064-gtp-channel-conf 01_154 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.SATA_MIN_BURST[3] origin:064-gtp-channel-conf 00_155 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.SATA_MIN_BURST[4] origin:064-gtp-channel-conf 01_155 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.SATA_MIN_BURST[5] origin:064-gtp-channel-conf 00_156 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.SATA_MIN_INIT[0] origin:064-gtp-channel-conf 00_160 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.SATA_MIN_INIT[1] origin:064-gtp-channel-conf 01_160 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.SATA_MIN_INIT[2] origin:064-gtp-channel-conf 00_161 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.SATA_MIN_INIT[3] origin:064-gtp-channel-conf 01_161 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.SATA_MIN_INIT[4] origin:064-gtp-channel-conf 00_162 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.SATA_MIN_INIT[5] origin:064-gtp-channel-conf 01_162 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.SATA_MIN_WAKE[0] origin:064-gtp-channel-conf 00_163 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.SATA_MIN_WAKE[1] origin:064-gtp-channel-conf 01_163 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.SATA_MIN_WAKE[2] origin:064-gtp-channel-conf 00_164 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.SATA_MIN_WAKE[3] origin:064-gtp-channel-conf 01_164 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.SATA_MIN_WAKE[4] origin:064-gtp-channel-conf 00_165 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.SATA_MIN_WAKE[5] origin:064-gtp-channel-conf 01_165 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.SATA_PLL_CFG.VCO_1500MHZ origin:064-gtp-channel-conf 02_55 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.SATA_PLL_CFG.VCO_750MHZ origin:064-gtp-channel-conf 03_55 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.SHOW_REALIGN_COMMA origin:064-gtp-channel-conf 01_522 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TERM_RCAL_CFG[0] origin:064-gtp-channel-conf 02_136 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TERM_RCAL_CFG[1] origin:064-gtp-channel-conf 03_136 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TERM_RCAL_CFG[2] origin:064-gtp-channel-conf 02_137 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TERM_RCAL_CFG[3] origin:064-gtp-channel-conf 03_137 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TERM_RCAL_CFG[4] origin:064-gtp-channel-conf 02_138 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TERM_RCAL_CFG[5] origin:064-gtp-channel-conf 03_138 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TERM_RCAL_CFG[6] origin:064-gtp-channel-conf 02_139 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TERM_RCAL_CFG[7] origin:064-gtp-channel-conf 03_139 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TERM_RCAL_CFG[8] origin:064-gtp-channel-conf 02_140 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TERM_RCAL_CFG[9] origin:064-gtp-channel-conf 03_140 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TERM_RCAL_CFG[10] origin:064-gtp-channel-conf 02_141 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TERM_RCAL_CFG[11] origin:064-gtp-channel-conf 03_141 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TERM_RCAL_CFG[12] origin:064-gtp-channel-conf 02_142 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TERM_RCAL_CFG[13] origin:064-gtp-channel-conf 03_142 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TERM_RCAL_CFG[14] origin:064-gtp-channel-conf 02_143 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TERM_RCAL_OVRD[0] origin:064-gtp-channel-conf 03_150 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TERM_RCAL_OVRD[1] origin:064-gtp-channel-conf 02_151 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TERM_RCAL_OVRD[2] origin:064-gtp-channel-conf 03_151 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TRANS_TIME_RATE[0] origin:064-gtp-channel-conf 00_192 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TRANS_TIME_RATE[1] origin:064-gtp-channel-conf 01_192 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TRANS_TIME_RATE[2] origin:064-gtp-channel-conf 00_193 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TRANS_TIME_RATE[3] origin:064-gtp-channel-conf 01_193 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TRANS_TIME_RATE[4] origin:064-gtp-channel-conf 00_194 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TRANS_TIME_RATE[5] origin:064-gtp-channel-conf 01_194 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TRANS_TIME_RATE[6] origin:064-gtp-channel-conf 00_195 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TRANS_TIME_RATE[7] origin:064-gtp-channel-conf 01_195 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TST_RSV[0] origin:064-gtp-channel-conf 02_504 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TST_RSV[1] origin:064-gtp-channel-conf 03_504 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TST_RSV[2] origin:064-gtp-channel-conf 02_505 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TST_RSV[3] origin:064-gtp-channel-conf 03_505 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TST_RSV[4] origin:064-gtp-channel-conf 02_506 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TST_RSV[5] origin:064-gtp-channel-conf 03_506 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TST_RSV[6] origin:064-gtp-channel-conf 02_507 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TST_RSV[7] origin:064-gtp-channel-conf 03_507 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TST_RSV[8] origin:064-gtp-channel-conf 02_508 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TST_RSV[9] origin:064-gtp-channel-conf 03_508 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TST_RSV[10] origin:064-gtp-channel-conf 02_509 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TST_RSV[11] origin:064-gtp-channel-conf 03_509 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TST_RSV[12] origin:064-gtp-channel-conf 02_510 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TST_RSV[13] origin:064-gtp-channel-conf 03_510 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TST_RSV[14] origin:064-gtp-channel-conf 02_511 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TST_RSV[15] origin:064-gtp-channel-conf 03_511 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TST_RSV[16] origin:064-gtp-channel-conf 02_512 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TST_RSV[17] origin:064-gtp-channel-conf 03_512 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TST_RSV[18] origin:064-gtp-channel-conf 02_513 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TST_RSV[19] origin:064-gtp-channel-conf 03_513 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TST_RSV[20] origin:064-gtp-channel-conf 02_514 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TST_RSV[21] origin:064-gtp-channel-conf 03_514 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TST_RSV[22] origin:064-gtp-channel-conf 02_515 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TST_RSV[23] origin:064-gtp-channel-conf 03_515 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TST_RSV[24] origin:064-gtp-channel-conf 02_516 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TST_RSV[25] origin:064-gtp-channel-conf 03_516 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TST_RSV[26] origin:064-gtp-channel-conf 02_517 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TST_RSV[27] origin:064-gtp-channel-conf 03_517 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TST_RSV[28] origin:064-gtp-channel-conf 02_518 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TST_RSV[29] origin:064-gtp-channel-conf 03_518 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TST_RSV[30] origin:064-gtp-channel-conf 02_519 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TST_RSV[31] origin:064-gtp-channel-conf 03_519 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_CLKMUX_EN[0] origin:064-gtp-channel-conf 03_128 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_DATA_WIDTH[0] origin:064-gtp-channel-conf 02_152 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_DATA_WIDTH[1] origin:064-gtp-channel-conf 03_152 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_DATA_WIDTH[2] origin:064-gtp-channel-conf 02_153 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_DRIVE_MODE.PIPE origin:064-gtp-channel-conf 00_200 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_EIDLE_ASSERT_DELAY[0] origin:064-gtp-channel-conf 00_203 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_EIDLE_ASSERT_DELAY[1] origin:064-gtp-channel-conf 01_203 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_EIDLE_ASSERT_DELAY[2] origin:064-gtp-channel-conf 00_204 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_EIDLE_DEASSERT_DELAY[0] origin:064-gtp-channel-conf 01_204 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_EIDLE_DEASSERT_DELAY[1] origin:064-gtp-channel-conf 00_205 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_EIDLE_DEASSERT_DELAY[2] origin:064-gtp-channel-conf 01_205 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_LOOPBACK_DRIVE_HIZ origin:064-gtp-channel-conf 01_202 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_MAINCURSOR_SEL[0] origin:064-gtp-channel-conf 03_289 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_0[0] origin:064-gtp-channel-conf 02_232 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_0[1] origin:064-gtp-channel-conf 03_232 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_0[2] origin:064-gtp-channel-conf 02_233 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_0[3] origin:064-gtp-channel-conf 03_233 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_0[4] origin:064-gtp-channel-conf 02_234 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_0[5] origin:064-gtp-channel-conf 03_234 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_0[6] origin:064-gtp-channel-conf 02_235 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_1[0] origin:064-gtp-channel-conf 02_236 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_1[1] origin:064-gtp-channel-conf 03_236 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_1[2] origin:064-gtp-channel-conf 02_237 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_1[3] origin:064-gtp-channel-conf 03_237 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_1[4] origin:064-gtp-channel-conf 02_238 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_1[5] origin:064-gtp-channel-conf 03_238 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_1[6] origin:064-gtp-channel-conf 02_239 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_2[0] origin:064-gtp-channel-conf 02_240 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_2[1] origin:064-gtp-channel-conf 03_240 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_2[2] origin:064-gtp-channel-conf 02_241 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_2[3] origin:064-gtp-channel-conf 03_241 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_2[4] origin:064-gtp-channel-conf 02_242 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_2[5] origin:064-gtp-channel-conf 03_242 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_2[6] origin:064-gtp-channel-conf 02_243 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_3[0] origin:064-gtp-channel-conf 02_244 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_3[1] origin:064-gtp-channel-conf 03_244 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_3[2] origin:064-gtp-channel-conf 02_245 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_3[3] origin:064-gtp-channel-conf 03_245 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_3[4] origin:064-gtp-channel-conf 02_246 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_3[5] origin:064-gtp-channel-conf 03_246 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_3[6] origin:064-gtp-channel-conf 02_247 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_4[0] origin:064-gtp-channel-conf 02_248 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_4[1] origin:064-gtp-channel-conf 03_248 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_4[2] origin:064-gtp-channel-conf 02_249 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_4[3] origin:064-gtp-channel-conf 03_249 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_4[4] origin:064-gtp-channel-conf 02_250 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_4[5] origin:064-gtp-channel-conf 03_250 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_4[6] origin:064-gtp-channel-conf 02_251 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_0[0] origin:064-gtp-channel-conf 02_252 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_0[1] origin:064-gtp-channel-conf 03_252 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_0[2] origin:064-gtp-channel-conf 02_253 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_0[3] origin:064-gtp-channel-conf 03_253 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_0[4] origin:064-gtp-channel-conf 02_254 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_0[5] origin:064-gtp-channel-conf 03_254 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_0[6] origin:064-gtp-channel-conf 02_255 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_1[0] origin:064-gtp-channel-conf 02_256 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_1[1] origin:064-gtp-channel-conf 03_256 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_1[2] origin:064-gtp-channel-conf 02_257 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_1[3] origin:064-gtp-channel-conf 03_257 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_1[4] origin:064-gtp-channel-conf 02_258 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_1[5] origin:064-gtp-channel-conf 03_258 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_1[6] origin:064-gtp-channel-conf 02_259 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_2[0] origin:064-gtp-channel-conf 02_260 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_2[1] origin:064-gtp-channel-conf 03_260 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_2[2] origin:064-gtp-channel-conf 02_261 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_2[3] origin:064-gtp-channel-conf 03_261 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_2[4] origin:064-gtp-channel-conf 02_262 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_2[5] origin:064-gtp-channel-conf 03_262 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_2[6] origin:064-gtp-channel-conf 02_263 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_3[0] origin:064-gtp-channel-conf 02_264 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_3[1] origin:064-gtp-channel-conf 03_264 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_3[2] origin:064-gtp-channel-conf 02_265 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_3[3] origin:064-gtp-channel-conf 03_265 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_3[4] origin:064-gtp-channel-conf 02_266 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_3[5] origin:064-gtp-channel-conf 03_266 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_3[6] origin:064-gtp-channel-conf 02_267 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_4[0] origin:064-gtp-channel-conf 02_268 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_4[1] origin:064-gtp-channel-conf 03_268 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_4[2] origin:064-gtp-channel-conf 02_269 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_4[3] origin:064-gtp-channel-conf 03_269 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_4[4] origin:064-gtp-channel-conf 02_270 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_4[5] origin:064-gtp-channel-conf 03_270 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_4[6] origin:064-gtp-channel-conf 02_271 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_PREDRIVER_MODE[0] origin:064-gtp-channel-conf 00_206 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_RXDETECT_CFG[0] origin:064-gtp-channel-conf 02_296 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_RXDETECT_CFG[1] origin:064-gtp-channel-conf 03_296 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_RXDETECT_CFG[2] origin:064-gtp-channel-conf 02_297 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_RXDETECT_CFG[3] origin:064-gtp-channel-conf 03_297 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_RXDETECT_CFG[4] origin:064-gtp-channel-conf 02_298 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_RXDETECT_CFG[5] origin:064-gtp-channel-conf 03_298 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_RXDETECT_CFG[6] origin:064-gtp-channel-conf 02_299 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_RXDETECT_CFG[7] origin:064-gtp-channel-conf 03_299 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_RXDETECT_CFG[8] origin:064-gtp-channel-conf 02_300 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_RXDETECT_CFG[9] origin:064-gtp-channel-conf 03_300 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_RXDETECT_CFG[10] origin:064-gtp-channel-conf 02_301 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_RXDETECT_CFG[11] origin:064-gtp-channel-conf 03_301 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_RXDETECT_CFG[12] origin:064-gtp-channel-conf 02_302 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_RXDETECT_CFG[13] origin:064-gtp-channel-conf 03_302 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_RXDETECT_REF[0] origin:064-gtp-channel-conf 02_292 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_RXDETECT_REF[1] origin:064-gtp-channel-conf 03_292 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_RXDETECT_REF[2] origin:064-gtp-channel-conf 02_293 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_XCLK_SEL.TXUSR origin:064-gtp-channel-conf 03_11 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_CLK25_DIV[0] origin:064-gtp-channel-conf 02_144 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_CLK25_DIV[1] origin:064-gtp-channel-conf 03_144 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_CLK25_DIV[2] origin:064-gtp-channel-conf 02_145 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_CLK25_DIV[3] origin:064-gtp-channel-conf 03_145 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_CLK25_DIV[4] origin:064-gtp-channel-conf 02_146 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_DEEMPH0[0] origin:064-gtp-channel-conf 02_272 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_DEEMPH0[1] origin:064-gtp-channel-conf 03_272 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_DEEMPH0[2] origin:064-gtp-channel-conf 02_273 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_DEEMPH0[3] origin:064-gtp-channel-conf 03_273 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_DEEMPH0[4] origin:064-gtp-channel-conf 02_274 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_DEEMPH0[5] origin:064-gtp-channel-conf 03_274 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_DEEMPH1[0] origin:064-gtp-channel-conf 02_276 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_DEEMPH1[1] origin:064-gtp-channel-conf 03_276 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_DEEMPH1[2] origin:064-gtp-channel-conf 02_277 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_DEEMPH1[3] origin:064-gtp-channel-conf 03_277 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_DEEMPH1[4] origin:064-gtp-channel-conf 02_278 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TX_DEEMPH1[5] origin:064-gtp-channel-conf 03_278 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXBUF_EN origin:064-gtp-channel-conf 00_231 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXBUF_RESET_ON_RATE_CHANGE origin:064-gtp-channel-conf 01_231 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXDLY_CFG[0] origin:064-gtp-channel-conf 02_80 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXDLY_CFG[1] origin:064-gtp-channel-conf 03_80 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXDLY_CFG[2] origin:064-gtp-channel-conf 02_81 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXDLY_CFG[3] origin:064-gtp-channel-conf 03_81 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXDLY_CFG[4] origin:064-gtp-channel-conf 02_82 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXDLY_CFG[5] origin:064-gtp-channel-conf 03_82 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXDLY_CFG[6] origin:064-gtp-channel-conf 02_83 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXDLY_CFG[7] origin:064-gtp-channel-conf 03_83 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXDLY_CFG[8] origin:064-gtp-channel-conf 02_84 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXDLY_CFG[9] origin:064-gtp-channel-conf 03_84 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXDLY_CFG[10] origin:064-gtp-channel-conf 02_85 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXDLY_CFG[11] origin:064-gtp-channel-conf 03_85 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXDLY_CFG[12] origin:064-gtp-channel-conf 02_86 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXDLY_CFG[13] origin:064-gtp-channel-conf 03_86 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXDLY_CFG[14] origin:064-gtp-channel-conf 02_87 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXDLY_CFG[15] origin:064-gtp-channel-conf 03_87 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXDLY_LCFG[0] origin:064-gtp-channel-conf 02_568 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXDLY_LCFG[1] origin:064-gtp-channel-conf 03_568 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXDLY_LCFG[2] origin:064-gtp-channel-conf 02_569 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXDLY_LCFG[3] origin:064-gtp-channel-conf 03_569 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXDLY_LCFG[4] origin:064-gtp-channel-conf 02_570 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXDLY_LCFG[5] origin:064-gtp-channel-conf 03_570 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXDLY_LCFG[6] origin:064-gtp-channel-conf 02_571 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXDLY_LCFG[7] origin:064-gtp-channel-conf 03_571 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXDLY_LCFG[8] origin:064-gtp-channel-conf 02_572 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXDLY_TAP_CFG[0] origin:064-gtp-channel-conf 02_88 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXDLY_TAP_CFG[1] origin:064-gtp-channel-conf 03_88 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXDLY_TAP_CFG[2] origin:064-gtp-channel-conf 02_89 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXDLY_TAP_CFG[3] origin:064-gtp-channel-conf 03_89 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXDLY_TAP_CFG[4] origin:064-gtp-channel-conf 02_90 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXDLY_TAP_CFG[5] origin:064-gtp-channel-conf 03_90 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXDLY_TAP_CFG[6] origin:064-gtp-channel-conf 02_91 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXDLY_TAP_CFG[7] origin:064-gtp-channel-conf 03_91 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXDLY_TAP_CFG[8] origin:064-gtp-channel-conf 02_92 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXDLY_TAP_CFG[9] origin:064-gtp-channel-conf 03_92 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXDLY_TAP_CFG[10] origin:064-gtp-channel-conf 02_93 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXDLY_TAP_CFG[11] origin:064-gtp-channel-conf 03_93 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXDLY_TAP_CFG[12] origin:064-gtp-channel-conf 02_94 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXDLY_TAP_CFG[13] origin:064-gtp-channel-conf 03_94 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXDLY_TAP_CFG[14] origin:064-gtp-channel-conf 02_95 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXDLY_TAP_CFG[15] origin:064-gtp-channel-conf 03_95 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXGEARBOX_EN origin:064-gtp-channel-conf 01_226 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXOOB_CFG[0] origin:064-gtp-channel-conf 03_20 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXOUT_DIV[0] origin:064-gtp-channel-conf 02_386 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXOUT_DIV[1] origin:064-gtp-channel-conf 03_386 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPCSRESET_TIME[0] origin:064-gtp-channel-conf 01_130 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPCSRESET_TIME[1] origin:064-gtp-channel-conf 00_131 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPCSRESET_TIME[2] origin:064-gtp-channel-conf 01_131 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPCSRESET_TIME[3] origin:064-gtp-channel-conf 00_132 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPCSRESET_TIME[4] origin:064-gtp-channel-conf 01_132 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPH_CFG[0] origin:064-gtp-channel-conf 02_96 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPH_CFG[1] origin:064-gtp-channel-conf 03_96 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPH_CFG[2] origin:064-gtp-channel-conf 02_97 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPH_CFG[3] origin:064-gtp-channel-conf 03_97 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPH_CFG[4] origin:064-gtp-channel-conf 02_98 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPH_CFG[5] origin:064-gtp-channel-conf 03_98 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPH_CFG[6] origin:064-gtp-channel-conf 02_99 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPH_CFG[7] origin:064-gtp-channel-conf 03_99 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPH_CFG[8] origin:064-gtp-channel-conf 02_100 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPH_CFG[9] origin:064-gtp-channel-conf 03_100 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPH_CFG[10] origin:064-gtp-channel-conf 02_101 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPH_CFG[11] origin:064-gtp-channel-conf 03_101 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPH_CFG[12] origin:064-gtp-channel-conf 02_102 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPH_CFG[13] origin:064-gtp-channel-conf 03_102 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPH_CFG[14] origin:064-gtp-channel-conf 02_103 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPH_CFG[15] origin:064-gtp-channel-conf 03_103 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPH_MONITOR_SEL[0] origin:064-gtp-channel-conf 02_108 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPH_MONITOR_SEL[1] origin:064-gtp-channel-conf 03_108 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPH_MONITOR_SEL[2] origin:064-gtp-channel-conf 02_109 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPH_MONITOR_SEL[3] origin:064-gtp-channel-conf 03_109 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPH_MONITOR_SEL[4] origin:064-gtp-channel-conf 02_110 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[0] origin:064-gtp-channel-conf 02_64 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[1] origin:064-gtp-channel-conf 03_64 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[2] origin:064-gtp-channel-conf 02_65 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[3] origin:064-gtp-channel-conf 03_65 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[4] origin:064-gtp-channel-conf 02_66 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[5] origin:064-gtp-channel-conf 03_66 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[6] origin:064-gtp-channel-conf 02_67 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[7] origin:064-gtp-channel-conf 03_67 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[8] origin:064-gtp-channel-conf 02_68 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[9] origin:064-gtp-channel-conf 03_68 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[10] origin:064-gtp-channel-conf 02_69 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[11] origin:064-gtp-channel-conf 03_69 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[12] origin:064-gtp-channel-conf 02_70 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[13] origin:064-gtp-channel-conf 03_70 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[14] origin:064-gtp-channel-conf 02_71 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[15] origin:064-gtp-channel-conf 03_71 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[16] origin:064-gtp-channel-conf 02_72 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[17] origin:064-gtp-channel-conf 03_72 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[18] origin:064-gtp-channel-conf 02_73 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[19] origin:064-gtp-channel-conf 03_73 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[20] origin:064-gtp-channel-conf 02_74 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[21] origin:064-gtp-channel-conf 03_74 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[22] origin:064-gtp-channel-conf 02_75 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[23] origin:064-gtp-channel-conf 03_75 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPI_GREY_SEL[0] origin:064-gtp-channel-conf 03_498 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPI_INVSTROBE_SEL[0] origin:064-gtp-channel-conf 02_498 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPI_PPM_CFG[0] origin:064-gtp-channel-conf 02_488 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPI_PPM_CFG[1] origin:064-gtp-channel-conf 03_488 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPI_PPM_CFG[2] origin:064-gtp-channel-conf 02_489 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPI_PPM_CFG[3] origin:064-gtp-channel-conf 03_489 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPI_PPM_CFG[4] origin:064-gtp-channel-conf 02_490 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPI_PPM_CFG[5] origin:064-gtp-channel-conf 03_490 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPI_PPM_CFG[6] origin:064-gtp-channel-conf 02_491 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPI_PPM_CFG[7] origin:064-gtp-channel-conf 03_491 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPI_PPMCLK_SEL.TXUSRCLK2 origin:064-gtp-channel-conf 03_497 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPI_SYNFREQ_PPM[0] origin:064-gtp-channel-conf 02_496 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPI_SYNFREQ_PPM[1] origin:064-gtp-channel-conf 03_496 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPI_SYNFREQ_PPM[2] origin:064-gtp-channel-conf 02_497 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPI_CFG0[0] origin:064-gtp-channel-conf 02_40 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPI_CFG0[1] origin:064-gtp-channel-conf 03_40 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPI_CFG1[0] origin:064-gtp-channel-conf 02_41 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPI_CFG1[1] origin:064-gtp-channel-conf 03_41 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPI_CFG2[0] origin:064-gtp-channel-conf 02_42 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPI_CFG2[1] origin:064-gtp-channel-conf 03_42 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPI_CFG3[0] origin:064-gtp-channel-conf 02_43 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPI_CFG4[0] origin:064-gtp-channel-conf 03_43 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPI_CFG5[0] origin:064-gtp-channel-conf 02_44 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPI_CFG5[1] origin:064-gtp-channel-conf 03_44 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPI_CFG5[2] origin:064-gtp-channel-conf 02_45 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPMARESET_TIME[0] origin:064-gtp-channel-conf 00_128 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPMARESET_TIME[1] origin:064-gtp-channel-conf 01_128 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPMARESET_TIME[2] origin:064-gtp-channel-conf 00_129 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPMARESET_TIME[3] origin:064-gtp-channel-conf 01_129 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXPMARESET_TIME[4] origin:064-gtp-channel-conf 00_130 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXSYNC_MULTILANE[0] origin:064-gtp-channel-conf 01_133 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXSYNC_OVRD[0] origin:064-gtp-channel-conf 00_135 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.TXSYNC_SKIP_DA[0] origin:064-gtp-channel-conf 00_134 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.UCODEER_CLR[0] origin:064-gtp-channel-conf 01_00 +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL.USE_PCS_CLK_PHASE_SEL[0] origin:064-gtp-channel-conf 02_463 diff --git a/artix7/segbits_gtp_channel_1_mid_right.db b/artix7/segbits_gtp_channel_1_mid_right.db index 8802798..6414f66 100644 --- a/artix7/segbits_gtp_channel_1_mid_right.db +++ b/artix7/segbits_gtp_channel_1_mid_right.db @@ -1,1627 +1,1627 @@ -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ACJTAG_DEBUG_MODE[0] 00_07 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ACJTAG_MODE[0] 01_06 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ACJTAG_RESET[0] 01_07 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ADAPT_CFG0[0] 02_464 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ADAPT_CFG0[1] 03_464 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ADAPT_CFG0[2] 02_465 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ADAPT_CFG0[3] 03_465 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ADAPT_CFG0[4] 02_466 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ADAPT_CFG0[5] 03_466 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ADAPT_CFG0[6] 02_467 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ADAPT_CFG0[7] 03_467 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ADAPT_CFG0[8] 02_468 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ADAPT_CFG0[9] 03_468 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ADAPT_CFG0[10] 02_469 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ADAPT_CFG0[11] 03_469 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ADAPT_CFG0[12] 02_470 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ADAPT_CFG0[13] 03_470 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ADAPT_CFG0[14] 02_471 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ADAPT_CFG0[15] 03_471 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ADAPT_CFG0[16] 02_472 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ADAPT_CFG0[17] 03_472 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ADAPT_CFG0[18] 02_473 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ADAPT_CFG0[19] 03_473 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ALIGN_COMMA_DOUBLE 00_522 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ALIGN_COMMA_ENABLE[0] 00_496 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ALIGN_COMMA_ENABLE[1] 01_496 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ALIGN_COMMA_ENABLE[2] 00_497 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ALIGN_COMMA_ENABLE[3] 01_497 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ALIGN_COMMA_ENABLE[4] 00_498 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ALIGN_COMMA_ENABLE[5] 01_498 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ALIGN_COMMA_ENABLE[6] 00_499 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ALIGN_COMMA_ENABLE[7] 01_499 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ALIGN_COMMA_ENABLE[8] 00_500 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ALIGN_COMMA_ENABLE[9] 01_500 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ALIGN_COMMA_WORD[0] 01_526 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ALIGN_COMMA_WORD[1] 00_527 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ALIGN_MCOMMA_DET 00_523 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ALIGN_MCOMMA_VALUE[0] 00_504 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ALIGN_MCOMMA_VALUE[1] 01_504 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ALIGN_MCOMMA_VALUE[2] 00_505 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ALIGN_MCOMMA_VALUE[3] 01_505 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ALIGN_MCOMMA_VALUE[4] 00_506 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ALIGN_MCOMMA_VALUE[5] 01_506 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ALIGN_MCOMMA_VALUE[6] 00_507 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ALIGN_MCOMMA_VALUE[7] 01_507 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ALIGN_MCOMMA_VALUE[8] 00_508 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ALIGN_MCOMMA_VALUE[9] 01_508 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ALIGN_PCOMMA_DET 01_523 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ALIGN_PCOMMA_VALUE[0] 00_512 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ALIGN_PCOMMA_VALUE[1] 01_512 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ALIGN_PCOMMA_VALUE[2] 00_513 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ALIGN_PCOMMA_VALUE[3] 01_513 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ALIGN_PCOMMA_VALUE[4] 00_514 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ALIGN_PCOMMA_VALUE[5] 01_514 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ALIGN_PCOMMA_VALUE[6] 00_515 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ALIGN_PCOMMA_VALUE[7] 01_515 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ALIGN_PCOMMA_VALUE[8] 00_516 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ALIGN_PCOMMA_VALUE[9] 01_516 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CBCC_DATA_SOURCE_SEL.DECODED 01_661 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CFOK_CFG[0] 02_392 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CFOK_CFG[1] 03_392 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CFOK_CFG[2] 02_393 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CFOK_CFG[3] 03_393 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CFOK_CFG[4] 02_394 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CFOK_CFG[5] 03_394 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CFOK_CFG[6] 02_395 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CFOK_CFG[7] 03_395 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CFOK_CFG[8] 02_396 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CFOK_CFG[9] 03_396 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CFOK_CFG[10] 02_397 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CFOK_CFG[11] 03_397 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CFOK_CFG[12] 02_398 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CFOK_CFG[13] 03_398 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CFOK_CFG[14] 02_399 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CFOK_CFG[15] 03_399 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CFOK_CFG[16] 02_400 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CFOK_CFG[17] 03_400 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CFOK_CFG[18] 02_401 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CFOK_CFG[19] 03_401 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CFOK_CFG[20] 02_402 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CFOK_CFG[21] 03_402 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CFOK_CFG[22] 02_403 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CFOK_CFG[23] 03_403 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CFOK_CFG[24] 02_404 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CFOK_CFG[25] 03_404 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CFOK_CFG[26] 02_405 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CFOK_CFG[27] 03_405 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CFOK_CFG[28] 02_406 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CFOK_CFG[29] 03_406 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CFOK_CFG[30] 02_407 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CFOK_CFG[31] 03_407 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CFOK_CFG[32] 02_408 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CFOK_CFG[33] 03_408 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CFOK_CFG[34] 02_409 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CFOK_CFG[35] 03_409 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CFOK_CFG[36] 02_410 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CFOK_CFG[37] 03_410 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CFOK_CFG[38] 02_411 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CFOK_CFG[39] 03_411 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CFOK_CFG[40] 02_412 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CFOK_CFG[41] 03_412 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CFOK_CFG[42] 02_413 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CFOK_CFG2[0] 02_459 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CFOK_CFG2[1] 03_459 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CFOK_CFG2[2] 02_460 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CFOK_CFG2[3] 03_460 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CFOK_CFG2[4] 02_461 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CFOK_CFG2[5] 03_461 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CFOK_CFG2[6] 02_462 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CFOK_CFG3[0] 02_416 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CFOK_CFG3[1] 03_416 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CFOK_CFG3[2] 02_417 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CFOK_CFG3[3] 03_417 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CFOK_CFG3[4] 02_418 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CFOK_CFG3[5] 03_418 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CFOK_CFG3[6] 02_419 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CFOK_CFG4[0] 03_438 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CFOK_CFG5[0] 02_429 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CFOK_CFG5[1] 03_429 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CFOK_CFG6[0] 03_436 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CFOK_CFG6[1] 02_437 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CFOK_CFG6[2] 03_437 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CFOK_CFG6[3] 02_438 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_KEEP_ALIGN 01_631 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_MAX_SKEW[0] 00_670 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_MAX_SKEW[1] 01_670 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_MAX_SKEW[2] 00_671 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_MAX_SKEW[3] 01_671 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_1[0] 00_608 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_1[1] 01_608 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_1[2] 00_609 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_1[3] 01_609 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_1[4] 00_610 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_1[5] 01_610 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_1[6] 00_611 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_1[7] 01_611 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_1[8] 00_612 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_1[9] 01_612 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_2[0] 00_616 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_2[1] 01_616 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_2[2] 00_617 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_2[3] 01_617 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_2[4] 00_618 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_2[5] 01_618 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_2[6] 00_619 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_2[7] 01_619 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_2[8] 00_620 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_2[9] 01_620 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_3[0] 00_624 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_3[1] 01_624 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_3[2] 00_625 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_3[3] 01_625 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_3[4] 00_626 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_3[5] 01_626 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_3[6] 00_627 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_3[7] 01_627 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_3[8] 00_628 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_3[9] 01_628 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_4[0] 00_632 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_4[1] 01_632 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_4[2] 00_633 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_4[3] 01_633 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_4[4] 00_634 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_4[5] 01_634 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_4[6] 00_635 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_4[7] 01_635 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_4[8] 00_636 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_4[9] 01_636 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_ENABLE[0] 00_614 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_ENABLE[1] 01_614 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_ENABLE[2] 00_615 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_ENABLE[3] 01_615 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_1[0] 00_640 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_1[1] 01_640 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_1[2] 00_641 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_1[3] 01_641 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_1[4] 00_642 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_1[5] 01_642 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_1[6] 00_643 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_1[7] 01_643 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_1[8] 00_644 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_1[9] 01_644 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_2[0] 00_648 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_2[1] 01_648 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_2[2] 00_649 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_2[3] 01_649 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_2[4] 00_650 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_2[5] 01_650 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_2[6] 00_651 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_2[7] 01_651 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_2[8] 00_652 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_2[9] 01_652 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_3[0] 00_656 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_3[1] 01_656 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_3[2] 00_657 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_3[3] 01_657 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_3[4] 00_658 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_3[5] 01_658 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_3[6] 00_659 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_3[7] 01_659 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_3[8] 00_660 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_3[9] 01_660 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_4[0] 00_664 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_4[1] 01_664 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_4[2] 00_665 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_4[3] 01_665 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_4[4] 00_666 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_4[5] 01_666 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_4[6] 00_667 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_4[7] 01_667 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_4[8] 00_668 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_4[9] 01_668 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_ENABLE[0] 00_646 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_ENABLE[1] 01_646 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_ENABLE[2] 00_647 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_ENABLE[3] 01_647 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_USE 01_645 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_LEN[0] 00_623 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_LEN[1] 01_623 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COMMON_SWING[0] 03_311 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_KEEP_IDLE 00_591 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_MAX_LAT[0] 00_557 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_MAX_LAT[1] 01_557 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_MAX_LAT[2] 00_558 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_MAX_LAT[3] 01_558 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_MAX_LAT[4] 00_559 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_MAX_LAT[5] 01_559 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_MIN_LAT[0] 00_565 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_MIN_LAT[1] 01_565 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_MIN_LAT[2] 00_566 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_MIN_LAT[3] 01_566 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_MIN_LAT[4] 00_567 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_MIN_LAT[5] 01_567 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_PRECEDENCE 00_590 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_REPEAT_WAIT[0] 00_573 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_REPEAT_WAIT[1] 01_573 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_REPEAT_WAIT[2] 00_574 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_REPEAT_WAIT[3] 01_574 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_REPEAT_WAIT[4] 00_575 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_1[0] 00_544 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_1[1] 01_544 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_1[2] 00_545 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_1[3] 01_545 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_1[4] 00_546 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_1[5] 01_546 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_1[6] 00_547 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_1[7] 01_547 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_1[8] 00_548 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_1[9] 01_548 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_2[0] 00_552 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_2[1] 01_552 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_2[2] 00_553 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_2[3] 01_553 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_2[4] 00_554 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_2[5] 01_554 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_2[6] 00_555 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_2[7] 01_555 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_2[8] 00_556 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_2[9] 01_556 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_3[0] 00_560 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_3[1] 01_560 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_3[2] 00_561 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_3[3] 01_561 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_3[4] 00_562 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_3[5] 01_562 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_3[6] 00_563 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_3[7] 01_563 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_3[8] 00_564 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_3[9] 01_564 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_4[0] 00_568 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_4[1] 01_568 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_4[2] 00_569 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_4[3] 01_569 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_4[4] 00_570 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_4[5] 01_570 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_4[6] 00_571 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_4[7] 01_571 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_4[8] 00_572 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_4[9] 01_572 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_ENABLE[0] 00_549 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_ENABLE[1] 01_549 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_ENABLE[2] 00_550 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_ENABLE[3] 01_550 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_1[0] 00_576 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_1[1] 01_576 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_1[2] 00_577 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_1[3] 01_577 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_1[4] 00_578 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_1[5] 01_578 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_1[6] 00_579 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_1[7] 01_579 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_1[8] 00_580 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_1[9] 01_580 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_2[0] 00_584 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_2[1] 01_584 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_2[2] 00_585 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_2[3] 01_585 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_2[4] 00_586 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_2[5] 01_586 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_2[6] 00_587 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_2[7] 01_587 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_2[8] 00_588 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_2[9] 01_588 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_3[0] 00_592 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_3[1] 01_592 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_3[2] 00_593 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_3[3] 01_593 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_3[4] 00_594 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_3[5] 01_594 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_3[6] 00_595 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_3[7] 01_595 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_3[8] 00_596 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_3[9] 01_596 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_4[0] 00_600 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_4[1] 01_600 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_4[2] 00_601 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_4[3] 01_601 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_4[4] 00_602 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_4[5] 01_602 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_4[6] 00_603 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_4[7] 01_603 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_4[8] 00_604 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_4[9] 01_604 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_ENABLE[0] 00_581 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_ENABLE[1] 01_581 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_ENABLE[2] 00_582 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_ENABLE[3] 01_582 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_USE 00_583 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_LEN[0] 00_589 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_LEN[1] 01_589 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_CORRECT_USE 00_551 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.DEC_MCOMMA_DETECT 01_494 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.DEC_PCOMMA_DETECT 00_495 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.DEC_VALID_COMMA_ONLY 00_494 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.DMONITOR_CFG[0] 02_368 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.DMONITOR_CFG[1] 03_368 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.DMONITOR_CFG[2] 02_369 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.DMONITOR_CFG[3] 03_369 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.DMONITOR_CFG[4] 02_370 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.DMONITOR_CFG[5] 03_370 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.DMONITOR_CFG[6] 02_371 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.DMONITOR_CFG[7] 03_371 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.DMONITOR_CFG[8] 02_372 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.DMONITOR_CFG[9] 03_372 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.DMONITOR_CFG[10] 02_373 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.DMONITOR_CFG[11] 03_373 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.DMONITOR_CFG[12] 02_374 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.DMONITOR_CFG[13] 03_374 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.DMONITOR_CFG[14] 02_375 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.DMONITOR_CFG[15] 03_375 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.DMONITOR_CFG[16] 02_376 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.DMONITOR_CFG[17] 03_376 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.DMONITOR_CFG[18] 02_377 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.DMONITOR_CFG[19] 03_377 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.DMONITOR_CFG[20] 02_378 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.DMONITOR_CFG[21] 03_378 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.DMONITOR_CFG[22] 02_379 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.DMONITOR_CFG[23] 03_379 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_CLK_PHASE_SEL[0] 03_463 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_CONTROL[0] 00_488 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_CONTROL[1] 01_488 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_CONTROL[2] 00_489 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_CONTROL[3] 01_489 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_CONTROL[4] 00_490 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_CONTROL[5] 01_490 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_ERRDET_EN 01_492 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_EYE_SCAN_EN 00_492 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_HORZ_OFFSET[0] 00_480 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_HORZ_OFFSET[1] 01_480 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_HORZ_OFFSET[2] 00_481 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_HORZ_OFFSET[3] 01_481 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_HORZ_OFFSET[4] 00_482 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_HORZ_OFFSET[5] 01_482 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_HORZ_OFFSET[6] 00_483 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_HORZ_OFFSET[7] 01_483 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_HORZ_OFFSET[8] 00_484 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_HORZ_OFFSET[9] 01_484 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_HORZ_OFFSET[10] 00_485 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_HORZ_OFFSET[11] 01_485 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_PMA_CFG[0] 02_624 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_PMA_CFG[1] 03_624 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_PMA_CFG[2] 02_625 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_PMA_CFG[3] 03_625 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_PMA_CFG[4] 02_626 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_PMA_CFG[5] 03_626 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_PMA_CFG[6] 02_627 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_PMA_CFG[7] 03_627 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_PMA_CFG[8] 02_628 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_PMA_CFG[9] 03_628 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_PRESCALE[0] 01_477 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_PRESCALE[1] 00_478 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_PRESCALE[2] 01_478 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_PRESCALE[3] 00_479 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_PRESCALE[4] 01_479 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[0] 00_392 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[1] 01_392 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[2] 00_393 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[3] 01_393 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[4] 00_394 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[5] 01_394 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[6] 00_395 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[7] 01_395 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[8] 00_396 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[9] 01_396 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[10] 00_397 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[11] 01_397 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[12] 00_398 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[13] 01_398 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[14] 00_399 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[15] 01_399 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[16] 00_400 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[17] 01_400 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[18] 00_401 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[19] 01_401 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[20] 00_402 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[21] 01_402 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[22] 00_403 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[23] 01_403 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[24] 00_404 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[25] 01_404 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[26] 00_405 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[27] 01_405 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[28] 00_406 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[29] 01_406 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[30] 00_407 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[31] 01_407 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[32] 00_408 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[33] 01_408 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[34] 00_409 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[35] 01_409 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[36] 00_410 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[37] 01_410 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[38] 00_411 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[39] 01_411 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[40] 00_412 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[41] 01_412 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[42] 00_413 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[43] 01_413 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[44] 00_414 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[45] 01_414 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[46] 00_415 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[47] 01_415 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[48] 00_416 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[49] 01_416 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[50] 00_417 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[51] 01_417 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[52] 00_418 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[53] 01_418 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[54] 00_419 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[55] 01_419 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[56] 00_420 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[57] 01_420 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[58] 00_421 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[59] 01_421 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[60] 00_422 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[61] 01_422 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[62] 00_423 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[63] 01_423 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[64] 00_424 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[65] 01_424 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[66] 00_425 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[67] 01_425 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[68] 00_426 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[69] 01_426 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[70] 00_427 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[71] 01_427 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[72] 00_428 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[73] 01_428 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[74] 00_429 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[75] 01_429 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[76] 00_430 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[77] 01_430 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[78] 00_431 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[79] 01_431 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[0] 00_352 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[1] 01_352 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[2] 00_353 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[3] 01_353 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[4] 00_354 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[5] 01_354 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[6] 00_355 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[7] 01_355 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[8] 00_356 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[9] 01_356 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[10] 00_357 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[11] 01_357 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[12] 00_358 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[13] 01_358 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[14] 00_359 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[15] 01_359 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[16] 00_360 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[17] 01_360 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[18] 00_361 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[19] 01_361 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[20] 00_362 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[21] 01_362 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[22] 00_363 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[23] 01_363 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[24] 00_364 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[25] 01_364 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[26] 00_365 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[27] 01_365 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[28] 00_366 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[29] 01_366 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[30] 00_367 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[31] 01_367 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[32] 00_368 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[33] 01_368 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[34] 00_369 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[35] 01_369 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[36] 00_370 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[37] 01_370 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[38] 00_371 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[39] 01_371 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[40] 00_372 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[41] 01_372 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[42] 00_373 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[43] 01_373 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[44] 00_374 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[45] 01_374 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[46] 00_375 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[47] 01_375 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[48] 00_376 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[49] 01_376 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[50] 00_377 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[51] 01_377 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[52] 00_378 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[53] 01_378 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[54] 00_379 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[55] 01_379 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[56] 00_380 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[57] 01_380 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[58] 00_381 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[59] 01_381 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[60] 00_382 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[61] 01_382 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[62] 00_383 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[63] 01_383 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[64] 00_384 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[65] 01_384 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[66] 00_385 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[67] 01_385 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[68] 00_386 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[69] 01_386 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[70] 00_387 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[71] 01_387 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[72] 00_388 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[73] 01_388 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[74] 00_389 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[75] 01_389 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[76] 00_390 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[77] 01_390 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[78] 00_391 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[79] 01_391 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[0] 00_432 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[1] 01_432 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[2] 00_433 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[3] 01_433 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[4] 00_434 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[5] 01_434 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[6] 00_435 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[7] 01_435 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[8] 00_436 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[9] 01_436 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[10] 00_437 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[11] 01_437 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[12] 00_438 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[13] 01_438 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[14] 00_439 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[15] 01_439 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[16] 00_440 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[17] 01_440 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[18] 00_441 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[19] 01_441 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[20] 00_442 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[21] 01_442 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[22] 00_443 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[23] 01_443 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[24] 00_444 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[25] 01_444 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[26] 00_445 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[27] 01_445 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[28] 00_446 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[29] 01_446 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[30] 00_447 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[31] 01_447 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[32] 00_448 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[33] 01_448 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[34] 00_449 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[35] 01_449 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[36] 00_450 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[37] 01_450 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[38] 00_451 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[39] 01_451 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[40] 00_452 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[41] 01_452 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[42] 00_453 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[43] 01_453 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[44] 00_454 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[45] 01_454 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[46] 00_455 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[47] 01_455 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[48] 00_456 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[49] 01_456 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[50] 00_457 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[51] 01_457 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[52] 00_458 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[53] 01_458 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[54] 00_459 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[55] 01_459 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[56] 00_460 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[57] 01_460 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[58] 00_461 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[59] 01_461 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[60] 00_462 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[61] 01_462 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[62] 00_463 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[63] 01_463 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[64] 00_464 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[65] 01_464 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[66] 00_465 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[67] 01_465 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[68] 00_466 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[69] 01_466 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[70] 00_467 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[71] 01_467 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[72] 00_468 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[73] 01_468 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[74] 00_469 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[75] 01_469 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[76] 00_470 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[77] 01_470 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[78] 00_471 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[79] 01_471 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_VERT_OFFSET[0] 00_472 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_VERT_OFFSET[1] 01_472 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_VERT_OFFSET[2] 00_473 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_VERT_OFFSET[3] 01_473 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_VERT_OFFSET[4] 00_474 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_VERT_OFFSET[5] 01_474 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_VERT_OFFSET[6] 00_475 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_VERT_OFFSET[7] 01_475 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_VERT_OFFSET[8] 00_476 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.FTS_DESKEW_SEQ_ENABLE[0] 00_662 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.FTS_DESKEW_SEQ_ENABLE[1] 01_662 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.FTS_DESKEW_SEQ_ENABLE[2] 00_663 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.FTS_DESKEW_SEQ_ENABLE[3] 01_663 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.FTS_LANE_DESKEW_CFG[0] 00_654 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.FTS_LANE_DESKEW_CFG[1] 01_654 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.FTS_LANE_DESKEW_CFG[2] 00_655 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.FTS_LANE_DESKEW_CFG[3] 01_655 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.FTS_LANE_DESKEW_EN 01_653 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.GEARBOX_MODE[0] 00_224 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.GEARBOX_MODE[1] 01_224 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.GEARBOX_MODE[2] 00_225 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.IN_USE 00_00 00_01 00_47 00_52 00_53 00_65 01_01 01_47 02_129 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.LOOPBACK_CFG[0] 02_20 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.OUTREFCLK_SEL_INV[0] 00_149 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.OUTREFCLK_SEL_INV[1] 01_149 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PCS_PCIE_EN 00_216 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[0] 02_184 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[1] 03_184 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[2] 02_185 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[3] 03_185 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[4] 02_186 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[5] 03_186 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[6] 02_187 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[7] 03_187 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[8] 02_188 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[9] 03_188 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[10] 02_189 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[11] 03_189 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[12] 02_190 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[13] 03_190 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[14] 02_191 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[15] 03_191 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[16] 02_192 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[17] 03_192 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[18] 02_193 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[19] 03_193 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[20] 02_194 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[21] 03_194 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[22] 02_195 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[23] 03_195 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[24] 02_196 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[25] 03_196 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[26] 02_197 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[27] 03_197 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[28] 02_198 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[29] 03_198 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[30] 02_199 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[31] 03_199 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[32] 02_200 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[33] 03_200 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[34] 02_201 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[35] 03_201 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[36] 02_202 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[37] 03_202 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[38] 02_203 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[39] 03_203 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[40] 02_204 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[41] 03_204 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[42] 02_205 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[43] 03_205 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[44] 02_206 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[45] 03_206 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[46] 02_207 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[47] 03_207 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PD_TRANS_TIME_FROM_P2[0] 01_216 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PD_TRANS_TIME_FROM_P2[1] 00_217 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PD_TRANS_TIME_FROM_P2[2] 01_217 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PD_TRANS_TIME_FROM_P2[3] 00_218 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PD_TRANS_TIME_FROM_P2[4] 01_218 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PD_TRANS_TIME_FROM_P2[5] 00_219 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PD_TRANS_TIME_FROM_P2[6] 01_219 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PD_TRANS_TIME_FROM_P2[7] 00_220 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PD_TRANS_TIME_FROM_P2[8] 01_220 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PD_TRANS_TIME_FROM_P2[9] 00_221 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PD_TRANS_TIME_FROM_P2[10] 01_221 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PD_TRANS_TIME_FROM_P2[11] 00_222 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PD_TRANS_TIME_NONE_P2[0] 00_208 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PD_TRANS_TIME_NONE_P2[1] 01_208 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PD_TRANS_TIME_NONE_P2[2] 00_209 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PD_TRANS_TIME_NONE_P2[3] 01_209 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PD_TRANS_TIME_NONE_P2[4] 00_210 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PD_TRANS_TIME_NONE_P2[5] 01_210 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PD_TRANS_TIME_NONE_P2[6] 00_211 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PD_TRANS_TIME_NONE_P2[7] 01_211 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PD_TRANS_TIME_TO_P2[0] 00_212 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PD_TRANS_TIME_TO_P2[1] 01_212 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PD_TRANS_TIME_TO_P2[2] 00_213 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PD_TRANS_TIME_TO_P2[3] 01_213 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PD_TRANS_TIME_TO_P2[4] 00_214 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PD_TRANS_TIME_TO_P2[5] 01_214 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PD_TRANS_TIME_TO_P2[6] 00_215 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PD_TRANS_TIME_TO_P2[7] 01_215 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PMA_LOOPBACK_CFG[0] 01_207 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PMA_RSV[0] 02_520 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PMA_RSV[1] 03_520 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PMA_RSV[2] 02_521 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PMA_RSV[3] 03_521 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PMA_RSV[4] 02_522 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PMA_RSV[5] 03_522 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PMA_RSV[6] 02_523 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PMA_RSV[7] 03_523 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PMA_RSV[8] 02_524 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PMA_RSV[9] 03_524 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PMA_RSV[10] 02_525 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PMA_RSV[11] 03_525 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PMA_RSV[12] 02_526 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PMA_RSV[13] 03_526 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PMA_RSV[14] 02_527 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PMA_RSV[15] 03_527 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PMA_RSV[16] 02_528 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PMA_RSV[17] 03_528 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PMA_RSV[18] 02_529 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PMA_RSV[19] 03_529 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PMA_RSV[20] 02_530 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PMA_RSV[21] 03_530 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PMA_RSV[22] 02_531 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PMA_RSV[23] 03_531 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PMA_RSV[24] 02_532 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PMA_RSV[25] 03_532 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PMA_RSV[26] 02_533 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PMA_RSV[27] 03_533 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PMA_RSV[28] 02_534 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PMA_RSV[29] 03_534 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PMA_RSV[30] 02_535 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PMA_RSV[31] 03_535 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PMA_RSV2[0] 02_336 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PMA_RSV2[1] 03_336 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PMA_RSV2[2] 02_337 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PMA_RSV2[3] 03_337 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PMA_RSV2[4] 02_338 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PMA_RSV2[5] 03_338 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PMA_RSV2[6] 02_339 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PMA_RSV2[7] 03_339 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PMA_RSV2[8] 02_340 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PMA_RSV2[9] 03_340 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PMA_RSV2[10] 02_341 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PMA_RSV2[11] 03_341 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PMA_RSV2[12] 02_342 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PMA_RSV2[13] 03_342 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PMA_RSV2[14] 02_343 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PMA_RSV2[15] 03_343 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PMA_RSV2[16] 02_344 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PMA_RSV2[17] 03_344 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PMA_RSV2[18] 02_345 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PMA_RSV2[19] 03_345 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PMA_RSV2[20] 02_346 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PMA_RSV2[21] 03_346 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PMA_RSV2[22] 02_347 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PMA_RSV2[23] 03_347 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PMA_RSV2[24] 02_348 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PMA_RSV2[25] 03_348 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PMA_RSV2[26] 02_349 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PMA_RSV2[27] 03_349 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PMA_RSV2[28] 02_350 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PMA_RSV2[29] 03_350 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PMA_RSV2[30] 02_351 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PMA_RSV2[31] 03_351 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PMA_RSV3[0] 02_288 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PMA_RSV3[1] 03_288 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PMA_RSV4[0] 02_156 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PMA_RSV4[1] 03_156 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PMA_RSV4[2] 02_157 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PMA_RSV4[3] 03_157 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PMA_RSV5[0] 03_159 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PMA_RSV6[0] 02_303 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PMA_RSV7[0] 03_303 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_BIAS_CFG[0] 02_112 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_BIAS_CFG[1] 03_112 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_BIAS_CFG[2] 02_113 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_BIAS_CFG[3] 03_113 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_BIAS_CFG[4] 02_114 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_BIAS_CFG[5] 03_114 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_BIAS_CFG[6] 02_115 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_BIAS_CFG[7] 03_115 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_BIAS_CFG[8] 02_116 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_BIAS_CFG[9] 03_116 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_BIAS_CFG[10] 02_117 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_BIAS_CFG[11] 03_117 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_BIAS_CFG[12] 02_118 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_BIAS_CFG[13] 03_118 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_BIAS_CFG[14] 02_119 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_BIAS_CFG[15] 03_119 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_BUFFER_CFG[0] 02_536 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_BUFFER_CFG[1] 03_536 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_BUFFER_CFG[2] 02_537 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_BUFFER_CFG[3] 03_537 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_BUFFER_CFG[4] 02_538 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_BUFFER_CFG[5] 03_538 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_CLKMUX_EN[0] 02_128 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_CM_SEL[0] 00_138 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_CM_SEL[1] 01_138 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_CM_TRIM[0] 02_304 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_CM_TRIM[1] 03_304 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_CM_TRIM[2] 02_305 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_CM_TRIM[3] 03_305 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_DATA_WIDTH[0] 01_141 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_DATA_WIDTH[1] 00_142 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_DATA_WIDTH[2] 01_142 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_DDI_SEL[0] 00_696 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_DDI_SEL[1] 01_696 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_DDI_SEL[2] 00_697 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_DDI_SEL[3] 01_697 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_DDI_SEL[4] 00_698 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_DDI_SEL[5] 01_698 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_DEBUG_CFG[0] 02_616 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_DEBUG_CFG[1] 03_616 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_DEBUG_CFG[2] 02_617 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_DEBUG_CFG[3] 03_617 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_DEBUG_CFG[4] 02_618 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_DEBUG_CFG[5] 03_618 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_DEBUG_CFG[6] 02_619 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_DEBUG_CFG[7] 03_619 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_DEBUG_CFG[8] 02_620 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_DEBUG_CFG[9] 03_620 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_DEBUG_CFG[10] 02_621 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_DEBUG_CFG[11] 03_621 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_DEBUG_CFG[12] 02_622 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_DEBUG_CFG[13] 03_622 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_DEFER_RESET_BUF_EN 02_552 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_DISPERR_SEQ_MATCH 01_495 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_OS_CFG[0] 00_288 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_OS_CFG[1] 01_288 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_OS_CFG[2] 00_289 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_OS_CFG[3] 01_289 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_OS_CFG[4] 00_290 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_OS_CFG[5] 01_290 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_OS_CFG[6] 00_291 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_OS_CFG[7] 01_291 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_OS_CFG[8] 00_292 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_OS_CFG[9] 01_292 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_OS_CFG[10] 00_293 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_OS_CFG[11] 01_293 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_OS_CFG[12] 00_294 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_SIG_VALID_DLY[0] 00_524 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_SIG_VALID_DLY[1] 01_524 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_SIG_VALID_DLY[2] 00_525 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_SIG_VALID_DLY[3] 01_525 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_SIG_VALID_DLY[4] 00_526 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_XCLK_SEL.RXUSR 00_143 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_CLK25_DIV[0] 00_139 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_CLK25_DIV[1] 01_139 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_CLK25_DIV[2] 00_140 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_CLK25_DIV[3] 01_140 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_CLK25_DIV[4] 00_141 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXBUF_ADDR_MODE.FAST 03_555 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXBUF_EIDLE_HI_CNT[0] 02_558 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXBUF_EIDLE_HI_CNT[1] 03_558 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXBUF_EIDLE_HI_CNT[2] 02_559 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXBUF_EIDLE_HI_CNT[3] 03_559 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXBUF_EIDLE_LO_CNT[0] 02_556 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXBUF_EIDLE_LO_CNT[1] 03_556 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXBUF_EIDLE_LO_CNT[2] 02_557 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXBUF_EIDLE_LO_CNT[3] 03_557 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXBUF_EN 02_11 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXBUF_RESET_ON_CB_CHANGE 02_560 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXBUF_RESET_ON_COMMAALIGN 02_561 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXBUF_RESET_ON_EIDLE 02_547 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXBUF_RESET_ON_RATE_CHANGE 03_560 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXBUF_THRESH_OVFLW[0] 03_552 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXBUF_THRESH_OVFLW[1] 02_553 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXBUF_THRESH_OVFLW[2] 03_553 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXBUF_THRESH_OVFLW[3] 02_554 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXBUF_THRESH_OVFLW[4] 03_554 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXBUF_THRESH_OVFLW[5] 02_555 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXBUF_THRESH_OVRD 02_548 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXBUF_THRESH_UNDFLW[0] 02_544 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXBUF_THRESH_UNDFLW[1] 03_544 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXBUF_THRESH_UNDFLW[2] 02_545 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXBUF_THRESH_UNDFLW[3] 03_545 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXBUF_THRESH_UNDFLW[4] 02_546 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXBUF_THRESH_UNDFLW[5] 03_546 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXBUFRESET_TIME[0] 01_101 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXBUFRESET_TIME[1] 00_102 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXBUFRESET_TIME[2] 01_102 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXBUFRESET_TIME[3] 00_103 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXBUFRESET_TIME[4] 01_103 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[0] 02_640 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[1] 03_640 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[2] 02_641 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[3] 03_641 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[4] 02_642 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[5] 03_642 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[6] 02_643 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[7] 03_643 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[8] 02_644 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[9] 03_644 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[10] 02_645 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[11] 03_645 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[12] 02_646 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[13] 03_646 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[14] 02_647 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[15] 03_647 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[16] 02_648 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[17] 03_648 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[18] 02_649 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[19] 03_649 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[20] 02_650 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[21] 03_650 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[22] 02_651 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[23] 03_651 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[24] 02_652 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[25] 03_652 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[26] 02_653 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[27] 03_653 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[28] 02_654 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[29] 03_654 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[30] 02_655 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[31] 03_655 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[32] 02_656 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[33] 03_656 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[34] 02_657 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[35] 03_657 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[36] 02_658 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[37] 03_658 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[38] 02_659 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[39] 03_659 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[40] 02_660 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[41] 03_660 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[42] 02_661 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[43] 03_661 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[44] 02_662 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[45] 03_662 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[46] 02_663 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[47] 03_663 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[48] 02_664 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[49] 03_664 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[50] 02_665 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[51] 03_665 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[52] 02_666 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[53] 03_666 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[54] 02_667 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[55] 03_667 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[56] 02_668 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[57] 03_668 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[58] 02_669 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[59] 03_669 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[60] 02_670 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[61] 03_670 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[62] 02_671 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[63] 03_671 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[64] 02_672 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[65] 03_672 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[66] 02_673 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[67] 03_673 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[68] 02_674 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[69] 03_674 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[70] 02_675 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[71] 03_675 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[72] 02_676 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[73] 03_676 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[74] 02_677 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[75] 03_677 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[76] 02_678 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[77] 03_678 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[78] 02_679 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[79] 03_679 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[80] 02_680 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[81] 03_680 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[82] 02_681 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_FR_RESET_ON_EIDLE[0] 02_638 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_HOLD_DURING_EIDLE[0] 03_637 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_LOCK_CFG[0] 02_632 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_LOCK_CFG[1] 03_632 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_LOCK_CFG[2] 02_633 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_LOCK_CFG[3] 03_633 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_LOCK_CFG[4] 02_634 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_LOCK_CFG[5] 03_634 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_PH_RESET_ON_EIDLE[0] 03_638 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDRFREQRESET_TIME[0] 01_106 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDRFREQRESET_TIME[1] 00_107 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDRFREQRESET_TIME[2] 01_107 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDRFREQRESET_TIME[3] 00_108 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDRFREQRESET_TIME[4] 01_108 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDRPHRESET_TIME[0] 00_109 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDRPHRESET_TIME[1] 01_109 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDRPHRESET_TIME[2] 00_110 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDRPHRESET_TIME[3] 01_110 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDRPHRESET_TIME[4] 00_111 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXDLY_CFG[0] 00_680 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXDLY_CFG[1] 01_680 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXDLY_CFG[2] 00_681 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXDLY_CFG[3] 01_681 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXDLY_CFG[4] 00_682 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXDLY_CFG[5] 01_682 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXDLY_CFG[6] 00_683 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXDLY_CFG[7] 01_683 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXDLY_CFG[8] 00_684 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXDLY_CFG[9] 01_684 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXDLY_CFG[10] 00_685 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXDLY_CFG[11] 01_685 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXDLY_CFG[12] 00_686 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXDLY_CFG[13] 01_686 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXDLY_CFG[14] 00_687 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXDLY_CFG[15] 01_687 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXDLY_LCFG[0] 02_576 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXDLY_LCFG[1] 03_576 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXDLY_LCFG[2] 02_577 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXDLY_LCFG[3] 03_577 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXDLY_LCFG[4] 02_578 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXDLY_LCFG[5] 03_578 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXDLY_LCFG[6] 02_579 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXDLY_LCFG[7] 03_579 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXDLY_LCFG[8] 02_580 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXDLY_TAP_CFG[0] 00_672 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXDLY_TAP_CFG[1] 01_672 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXDLY_TAP_CFG[2] 00_673 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXDLY_TAP_CFG[3] 01_673 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXDLY_TAP_CFG[4] 00_674 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXDLY_TAP_CFG[5] 01_674 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXDLY_TAP_CFG[6] 00_675 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXDLY_TAP_CFG[7] 01_675 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXDLY_TAP_CFG[8] 00_676 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXDLY_TAP_CFG[9] 01_676 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXDLY_TAP_CFG[10] 00_677 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXDLY_TAP_CFG[11] 01_677 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXDLY_TAP_CFG[12] 00_678 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXDLY_TAP_CFG[13] 01_678 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXDLY_TAP_CFG[14] 00_679 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXDLY_TAP_CFG[15] 01_679 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXGEARBOX_EN 01_607 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXISCANRESET_TIME[0] 01_123 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXISCANRESET_TIME[1] 00_124 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXISCANRESET_TIME[2] 01_124 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXISCANRESET_TIME[3] 00_125 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXISCANRESET_TIME[4] 01_125 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPM_BIAS_STARTUP_DISABLE[0] 03_391 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPM_CFG[0] 02_328 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPM_CFG[1] 03_328 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPM_CFG[2] 02_329 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPM_CFG[3] 03_329 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPM_CM_CFG[0] 02_430 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPM_GC_CFG[0] 02_432 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPM_GC_CFG[1] 03_432 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPM_GC_CFG[2] 02_433 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPM_GC_CFG[3] 03_433 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPM_GC_CFG[4] 02_434 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPM_GC_CFG[5] 03_434 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPM_GC_CFG[6] 02_435 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPM_GC_CFG[7] 03_435 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPM_GC_CFG[8] 02_436 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPM_GC_CFG2[0] 03_442 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPM_GC_CFG2[1] 02_443 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPM_GC_CFG2[2] 03_443 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPM_HF_CFG[0] 00_336 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPM_HF_CFG[1] 01_336 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPM_HF_CFG[2] 00_337 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPM_HF_CFG[3] 01_337 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPM_HF_CFG[4] 00_338 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPM_HF_CFG[5] 01_338 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPM_HF_CFG[6] 00_339 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPM_HF_CFG[7] 01_339 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPM_HF_CFG[8] 00_340 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPM_HF_CFG[9] 01_340 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPM_HF_CFG[10] 00_341 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPM_HF_CFG[11] 01_341 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPM_HF_CFG[12] 00_342 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPM_HF_CFG[13] 01_342 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPM_HF_CFG2[0] 02_424 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPM_HF_CFG2[1] 03_424 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPM_HF_CFG2[2] 02_425 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPM_HF_CFG2[3] 03_425 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPM_HF_CFG2[4] 02_426 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPM_HF_CFG3[0] 03_389 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPM_HF_CFG3[1] 02_390 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPM_HF_CFG3[2] 03_390 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPM_HF_CFG3[3] 02_391 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPM_HOLD_DURING_EIDLE[0] 00_247 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPM_INCM_CFG[0] 02_439 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPM_IPCM_CFG[0] 03_439 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPM_LF_CFG[0] 00_344 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPM_LF_CFG[1] 01_344 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPM_LF_CFG[2] 00_345 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPM_LF_CFG[3] 01_345 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPM_LF_CFG[4] 00_346 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPM_LF_CFG[5] 01_346 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPM_LF_CFG[6] 00_347 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPM_LF_CFG[7] 01_347 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPM_LF_CFG[8] 00_348 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPM_LF_CFG[9] 01_348 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPM_LF_CFG[10] 00_349 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPM_LF_CFG[11] 01_349 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPM_LF_CFG[12] 00_350 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPM_LF_CFG[13] 01_350 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPM_LF_CFG[14] 00_351 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPM_LF_CFG[15] 01_351 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPM_LF_CFG[16] 00_343 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPM_LF_CFG[17] 01_343 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPM_LF_CFG2[0] 03_426 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPM_LF_CFG2[1] 02_427 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPM_LF_CFG2[2] 03_427 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPM_LF_CFG2[3] 02_428 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPM_LF_CFG2[4] 03_428 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPM_OSINT_CFG[0] 02_440 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPM_OSINT_CFG[1] 03_440 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPM_OSINT_CFG[2] 02_441 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPM_CFG1[0] 02_330 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPMRESET_TIME[0] 00_112 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPMRESET_TIME[1] 01_112 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPMRESET_TIME[2] 00_113 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPMRESET_TIME[3] 01_113 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPMRESET_TIME[4] 00_114 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPMRESET_TIME[5] 01_114 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPMRESET_TIME[6] 00_115 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXOOB_CFG[0] 00_144 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXOOB_CFG[1] 01_144 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXOOB_CFG[2] 00_145 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXOOB_CFG[3] 01_145 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXOOB_CFG[4] 00_146 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXOOB_CFG[5] 01_146 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXOOB_CFG[6] 00_147 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXOOB_CLK_CFG.FABRIC 03_129 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXOSCALRESET_TIME[0] 00_187 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXOSCALRESET_TIME[1] 01_187 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXOSCALRESET_TIME[2] 00_188 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXOSCALRESET_TIME[3] 01_188 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXOSCALRESET_TIME[4] 00_189 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXOSCALRESET_TIMEOUT[0] 01_189 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXOSCALRESET_TIMEOUT[1] 00_190 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXOSCALRESET_TIMEOUT[2] 01_190 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXOSCALRESET_TIMEOUT[3] 00_191 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXOSCALRESET_TIMEOUT[4] 01_191 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXOUT_DIV[0] 02_384 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXOUT_DIV[1] 03_384 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXPCSRESET_TIME[0] 01_115 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXPCSRESET_TIME[1] 00_116 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXPCSRESET_TIME[2] 01_116 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXPCSRESET_TIME[3] 00_117 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXPCSRESET_TIME[4] 01_117 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXPH_CFG[0] 02_584 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXPH_CFG[1] 03_584 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXPH_CFG[2] 02_585 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXPH_CFG[3] 03_585 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXPH_CFG[4] 02_586 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXPH_CFG[5] 03_586 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXPH_CFG[6] 02_587 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXPH_CFG[7] 03_587 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXPH_CFG[8] 02_588 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXPH_CFG[9] 03_588 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXPH_CFG[10] 02_589 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXPH_CFG[11] 03_589 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXPH_CFG[12] 02_590 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXPH_CFG[13] 03_590 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXPH_CFG[14] 02_591 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXPH_CFG[15] 03_591 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXPH_CFG[16] 02_592 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXPH_CFG[17] 03_592 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXPH_CFG[18] 02_593 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXPH_CFG[19] 03_593 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXPH_CFG[20] 02_594 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXPH_CFG[21] 03_594 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXPH_CFG[22] 02_595 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXPH_CFG[23] 03_595 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXPH_MONITOR_SEL[0] 00_700 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXPH_MONITOR_SEL[1] 01_700 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXPH_MONITOR_SEL[2] 00_701 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXPH_MONITOR_SEL[3] 01_701 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXPH_MONITOR_SEL[4] 00_702 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXPHDLY_CFG[0] 02_600 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXPHDLY_CFG[1] 03_600 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXPHDLY_CFG[2] 02_601 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXPHDLY_CFG[3] 03_601 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXPHDLY_CFG[4] 02_602 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXPHDLY_CFG[5] 03_602 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXPHDLY_CFG[6] 02_603 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXPHDLY_CFG[7] 03_603 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXPHDLY_CFG[8] 02_604 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXPHDLY_CFG[9] 03_604 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXPHDLY_CFG[10] 02_605 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXPHDLY_CFG[11] 03_605 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXPHDLY_CFG[12] 02_606 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXPHDLY_CFG[13] 03_606 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXPHDLY_CFG[14] 02_607 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXPHDLY_CFG[15] 03_607 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXPHDLY_CFG[16] 02_608 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXPHDLY_CFG[17] 03_608 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXPHDLY_CFG[18] 02_609 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXPHDLY_CFG[19] 03_609 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXPHDLY_CFG[20] 02_610 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXPHDLY_CFG[21] 03_610 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXPHDLY_CFG[22] 02_611 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXPHDLY_CFG[23] 03_611 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXPI_CFG0[0] 03_430 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXPI_CFG0[1] 02_431 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXPI_CFG0[2] 03_431 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXPI_CFG1[0] 02_442 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXPI_CFG2[0] 03_441 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXPMARESET_TIME[0] 00_104 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXPMARESET_TIME[1] 01_104 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXPMARESET_TIME[2] 00_105 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXPMARESET_TIME[3] 01_105 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXPMARESET_TIME[4] 00_106 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXPRBS_ERR_LOOPBACK[0] 00_136 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXSLIDE_AUTO_WAIT[0] 00_520 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXSLIDE_AUTO_WAIT[1] 01_520 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXSLIDE_AUTO_WAIT[2] 00_521 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXSLIDE_AUTO_WAIT[3] 01_521 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXSLIDE_MODE.AUTO 00_519 !01_519 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXSLIDE_MODE.PCS !00_519 01_519 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXSLIDE_MODE.PMA 00_519 01_519 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXSYNC_MULTILANE[0] 00_133 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXSYNC_OVRD[0] 01_135 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXSYNC_SKIP_DA[0] 01_134 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.SAS_MAX_COM[0] 00_171 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.SAS_MAX_COM[1] 01_171 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.SAS_MAX_COM[2] 00_172 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.SAS_MAX_COM[3] 01_172 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.SAS_MAX_COM[4] 00_173 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.SAS_MAX_COM[5] 01_173 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.SAS_MAX_COM[6] 00_174 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.SAS_MIN_COM[0] 01_156 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.SAS_MIN_COM[1] 00_157 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.SAS_MIN_COM[2] 01_157 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.SAS_MIN_COM[3] 00_158 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.SAS_MIN_COM[4] 01_158 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.SAS_MIN_COM[5] 00_159 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.SATA_BURST_SEQ_LEN[0] 00_150 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.SATA_BURST_SEQ_LEN[1] 01_150 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.SATA_BURST_SEQ_LEN[2] 00_151 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.SATA_BURST_SEQ_LEN[3] 01_151 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.SATA_BURST_VAL[0] 01_147 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.SATA_BURST_VAL[1] 00_148 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.SATA_BURST_VAL[2] 01_148 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.SATA_EIDLE_VAL[0] 00_152 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.SATA_EIDLE_VAL[1] 01_152 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.SATA_EIDLE_VAL[2] 00_153 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.SATA_MAX_BURST[0] 00_168 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.SATA_MAX_BURST[1] 01_168 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.SATA_MAX_BURST[2] 00_169 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.SATA_MAX_BURST[3] 01_169 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.SATA_MAX_BURST[4] 00_170 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.SATA_MAX_BURST[5] 01_170 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.SATA_MAX_INIT[0] 00_176 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.SATA_MAX_INIT[1] 01_176 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.SATA_MAX_INIT[2] 00_177 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.SATA_MAX_INIT[3] 01_177 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.SATA_MAX_INIT[4] 00_178 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.SATA_MAX_INIT[5] 01_178 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.SATA_MAX_WAKE[0] 00_179 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.SATA_MAX_WAKE[1] 01_179 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.SATA_MAX_WAKE[2] 00_180 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.SATA_MAX_WAKE[3] 01_180 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.SATA_MAX_WAKE[4] 00_181 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.SATA_MAX_WAKE[5] 01_181 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.SATA_MIN_BURST[0] 01_153 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.SATA_MIN_BURST[1] 00_154 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.SATA_MIN_BURST[2] 01_154 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.SATA_MIN_BURST[3] 00_155 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.SATA_MIN_BURST[4] 01_155 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.SATA_MIN_BURST[5] 00_156 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.SATA_MIN_INIT[0] 00_160 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.SATA_MIN_INIT[1] 01_160 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.SATA_MIN_INIT[2] 00_161 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.SATA_MIN_INIT[3] 01_161 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.SATA_MIN_INIT[4] 00_162 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.SATA_MIN_INIT[5] 01_162 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.SATA_MIN_WAKE[0] 00_163 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.SATA_MIN_WAKE[1] 01_163 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.SATA_MIN_WAKE[2] 00_164 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.SATA_MIN_WAKE[3] 01_164 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.SATA_MIN_WAKE[4] 00_165 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.SATA_MIN_WAKE[5] 01_165 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.SATA_PLL_CFG.VCO_1500MHZ 02_55 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.SATA_PLL_CFG.VCO_750MHZ 03_55 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.SHOW_REALIGN_COMMA 01_522 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TERM_RCAL_CFG[0] 02_136 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TERM_RCAL_CFG[1] 03_136 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TERM_RCAL_CFG[2] 02_137 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TERM_RCAL_CFG[3] 03_137 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TERM_RCAL_CFG[4] 02_138 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TERM_RCAL_CFG[5] 03_138 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TERM_RCAL_CFG[6] 02_139 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TERM_RCAL_CFG[7] 03_139 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TERM_RCAL_CFG[8] 02_140 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TERM_RCAL_CFG[9] 03_140 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TERM_RCAL_CFG[10] 02_141 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TERM_RCAL_CFG[11] 03_141 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TERM_RCAL_CFG[12] 02_142 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TERM_RCAL_CFG[13] 03_142 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TERM_RCAL_CFG[14] 02_143 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TERM_RCAL_OVRD[0] 03_150 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TERM_RCAL_OVRD[1] 02_151 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TERM_RCAL_OVRD[2] 03_151 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TRANS_TIME_RATE[0] 00_192 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TRANS_TIME_RATE[1] 01_192 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TRANS_TIME_RATE[2] 00_193 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TRANS_TIME_RATE[3] 01_193 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TRANS_TIME_RATE[4] 00_194 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TRANS_TIME_RATE[5] 01_194 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TRANS_TIME_RATE[6] 00_195 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TRANS_TIME_RATE[7] 01_195 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TST_RSV[0] 02_504 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TST_RSV[1] 03_504 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TST_RSV[2] 02_505 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TST_RSV[3] 03_505 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TST_RSV[4] 02_506 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TST_RSV[5] 03_506 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TST_RSV[6] 02_507 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TST_RSV[7] 03_507 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TST_RSV[8] 02_508 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TST_RSV[9] 03_508 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TST_RSV[10] 02_509 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TST_RSV[11] 03_509 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TST_RSV[12] 02_510 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TST_RSV[13] 03_510 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TST_RSV[14] 02_511 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TST_RSV[15] 03_511 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TST_RSV[16] 02_512 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TST_RSV[17] 03_512 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TST_RSV[18] 02_513 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TST_RSV[19] 03_513 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TST_RSV[20] 02_514 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TST_RSV[21] 03_514 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TST_RSV[22] 02_515 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TST_RSV[23] 03_515 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TST_RSV[24] 02_516 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TST_RSV[25] 03_516 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TST_RSV[26] 02_517 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TST_RSV[27] 03_517 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TST_RSV[28] 02_518 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TST_RSV[29] 03_518 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TST_RSV[30] 02_519 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TST_RSV[31] 03_519 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_CLKMUX_EN[0] 03_128 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_DATA_WIDTH[0] 02_152 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_DATA_WIDTH[1] 03_152 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_DATA_WIDTH[2] 02_153 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_DRIVE_MODE.PIPE 00_200 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_EIDLE_ASSERT_DELAY[0] 00_203 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_EIDLE_ASSERT_DELAY[1] 01_203 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_EIDLE_ASSERT_DELAY[2] 00_204 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_EIDLE_DEASSERT_DELAY[0] 01_204 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_EIDLE_DEASSERT_DELAY[1] 00_205 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_EIDLE_DEASSERT_DELAY[2] 01_205 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_LOOPBACK_DRIVE_HIZ 01_202 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_MAINCURSOR_SEL[0] 03_289 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_MARGIN_FULL_0[0] 02_232 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_MARGIN_FULL_0[1] 03_232 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_MARGIN_FULL_0[2] 02_233 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_MARGIN_FULL_0[3] 03_233 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_MARGIN_FULL_0[4] 02_234 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_MARGIN_FULL_0[5] 03_234 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_MARGIN_FULL_0[6] 02_235 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_MARGIN_FULL_1[0] 02_236 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_MARGIN_FULL_1[1] 03_236 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_MARGIN_FULL_1[2] 02_237 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_MARGIN_FULL_1[3] 03_237 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_MARGIN_FULL_1[4] 02_238 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_MARGIN_FULL_1[5] 03_238 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_MARGIN_FULL_1[6] 02_239 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_MARGIN_FULL_2[0] 02_240 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_MARGIN_FULL_2[1] 03_240 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_MARGIN_FULL_2[2] 02_241 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_MARGIN_FULL_2[3] 03_241 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_MARGIN_FULL_2[4] 02_242 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_MARGIN_FULL_2[5] 03_242 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_MARGIN_FULL_2[6] 02_243 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_MARGIN_FULL_3[0] 02_244 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_MARGIN_FULL_3[1] 03_244 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_MARGIN_FULL_3[2] 02_245 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_MARGIN_FULL_3[3] 03_245 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_MARGIN_FULL_3[4] 02_246 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_MARGIN_FULL_3[5] 03_246 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_MARGIN_FULL_3[6] 02_247 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_MARGIN_FULL_4[0] 02_248 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_MARGIN_FULL_4[1] 03_248 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_MARGIN_FULL_4[2] 02_249 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_MARGIN_FULL_4[3] 03_249 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_MARGIN_FULL_4[4] 02_250 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_MARGIN_FULL_4[5] 03_250 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_MARGIN_FULL_4[6] 02_251 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_MARGIN_LOW_0[0] 02_252 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_MARGIN_LOW_0[1] 03_252 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_MARGIN_LOW_0[2] 02_253 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_MARGIN_LOW_0[3] 03_253 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_MARGIN_LOW_0[4] 02_254 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_MARGIN_LOW_0[5] 03_254 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_MARGIN_LOW_0[6] 02_255 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_MARGIN_LOW_1[0] 02_256 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_MARGIN_LOW_1[1] 03_256 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_MARGIN_LOW_1[2] 02_257 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_MARGIN_LOW_1[3] 03_257 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_MARGIN_LOW_1[4] 02_258 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_MARGIN_LOW_1[5] 03_258 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_MARGIN_LOW_1[6] 02_259 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_MARGIN_LOW_2[0] 02_260 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_MARGIN_LOW_2[1] 03_260 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_MARGIN_LOW_2[2] 02_261 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_MARGIN_LOW_2[3] 03_261 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_MARGIN_LOW_2[4] 02_262 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_MARGIN_LOW_2[5] 03_262 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_MARGIN_LOW_2[6] 02_263 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_MARGIN_LOW_3[0] 02_264 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_MARGIN_LOW_3[1] 03_264 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_MARGIN_LOW_3[2] 02_265 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_MARGIN_LOW_3[3] 03_265 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_MARGIN_LOW_3[4] 02_266 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_MARGIN_LOW_3[5] 03_266 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_MARGIN_LOW_3[6] 02_267 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_MARGIN_LOW_4[0] 02_268 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_MARGIN_LOW_4[1] 03_268 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_MARGIN_LOW_4[2] 02_269 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_MARGIN_LOW_4[3] 03_269 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_MARGIN_LOW_4[4] 02_270 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_MARGIN_LOW_4[5] 03_270 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_MARGIN_LOW_4[6] 02_271 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_PREDRIVER_MODE[0] 00_206 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_RXDETECT_CFG[0] 02_296 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_RXDETECT_CFG[1] 03_296 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_RXDETECT_CFG[2] 02_297 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_RXDETECT_CFG[3] 03_297 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_RXDETECT_CFG[4] 02_298 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_RXDETECT_CFG[5] 03_298 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_RXDETECT_CFG[6] 02_299 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_RXDETECT_CFG[7] 03_299 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_RXDETECT_CFG[8] 02_300 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_RXDETECT_CFG[9] 03_300 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_RXDETECT_CFG[10] 02_301 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_RXDETECT_CFG[11] 03_301 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_RXDETECT_CFG[12] 02_302 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_RXDETECT_CFG[13] 03_302 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_RXDETECT_REF[0] 02_292 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_RXDETECT_REF[1] 03_292 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_RXDETECT_REF[2] 02_293 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_XCLK_SEL.TXUSR 03_11 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_CLK25_DIV[0] 02_144 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_CLK25_DIV[1] 03_144 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_CLK25_DIV[2] 02_145 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_CLK25_DIV[3] 03_145 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_CLK25_DIV[4] 02_146 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_DEEMPH0[0] 02_272 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_DEEMPH0[1] 03_272 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_DEEMPH0[2] 02_273 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_DEEMPH0[3] 03_273 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_DEEMPH0[4] 02_274 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_DEEMPH0[5] 03_274 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_DEEMPH1[0] 02_276 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_DEEMPH1[1] 03_276 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_DEEMPH1[2] 02_277 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_DEEMPH1[3] 03_277 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_DEEMPH1[4] 02_278 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_DEEMPH1[5] 03_278 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXBUF_EN 00_231 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXBUF_RESET_ON_RATE_CHANGE 01_231 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXDLY_CFG[0] 02_80 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXDLY_CFG[1] 03_80 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXDLY_CFG[2] 02_81 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXDLY_CFG[3] 03_81 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXDLY_CFG[4] 02_82 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXDLY_CFG[5] 03_82 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXDLY_CFG[6] 02_83 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXDLY_CFG[7] 03_83 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXDLY_CFG[8] 02_84 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXDLY_CFG[9] 03_84 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXDLY_CFG[10] 02_85 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXDLY_CFG[11] 03_85 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXDLY_CFG[12] 02_86 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXDLY_CFG[13] 03_86 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXDLY_CFG[14] 02_87 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXDLY_CFG[15] 03_87 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXDLY_LCFG[0] 02_568 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXDLY_LCFG[1] 03_568 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXDLY_LCFG[2] 02_569 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXDLY_LCFG[3] 03_569 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXDLY_LCFG[4] 02_570 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXDLY_LCFG[5] 03_570 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXDLY_LCFG[6] 02_571 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXDLY_LCFG[7] 03_571 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXDLY_LCFG[8] 02_572 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXDLY_TAP_CFG[0] 02_88 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXDLY_TAP_CFG[1] 03_88 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXDLY_TAP_CFG[2] 02_89 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXDLY_TAP_CFG[3] 03_89 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXDLY_TAP_CFG[4] 02_90 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXDLY_TAP_CFG[5] 03_90 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXDLY_TAP_CFG[6] 02_91 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXDLY_TAP_CFG[7] 03_91 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXDLY_TAP_CFG[8] 02_92 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXDLY_TAP_CFG[9] 03_92 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXDLY_TAP_CFG[10] 02_93 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXDLY_TAP_CFG[11] 03_93 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXDLY_TAP_CFG[12] 02_94 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXDLY_TAP_CFG[13] 03_94 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXDLY_TAP_CFG[14] 02_95 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXDLY_TAP_CFG[15] 03_95 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXGEARBOX_EN 01_226 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXOOB_CFG[0] 03_20 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXOUT_DIV[0] 02_386 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXOUT_DIV[1] 03_386 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPCSRESET_TIME[0] 01_130 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPCSRESET_TIME[1] 00_131 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPCSRESET_TIME[2] 01_131 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPCSRESET_TIME[3] 00_132 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPCSRESET_TIME[4] 01_132 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPH_CFG[0] 02_96 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPH_CFG[1] 03_96 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPH_CFG[2] 02_97 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPH_CFG[3] 03_97 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPH_CFG[4] 02_98 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPH_CFG[5] 03_98 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPH_CFG[6] 02_99 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPH_CFG[7] 03_99 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPH_CFG[8] 02_100 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPH_CFG[9] 03_100 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPH_CFG[10] 02_101 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPH_CFG[11] 03_101 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPH_CFG[12] 02_102 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPH_CFG[13] 03_102 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPH_CFG[14] 02_103 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPH_CFG[15] 03_103 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPH_MONITOR_SEL[0] 02_108 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPH_MONITOR_SEL[1] 03_108 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPH_MONITOR_SEL[2] 02_109 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPH_MONITOR_SEL[3] 03_109 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPH_MONITOR_SEL[4] 02_110 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPHDLY_CFG[0] 02_64 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPHDLY_CFG[1] 03_64 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPHDLY_CFG[2] 02_65 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPHDLY_CFG[3] 03_65 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPHDLY_CFG[4] 02_66 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPHDLY_CFG[5] 03_66 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPHDLY_CFG[6] 02_67 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPHDLY_CFG[7] 03_67 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPHDLY_CFG[8] 02_68 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPHDLY_CFG[9] 03_68 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPHDLY_CFG[10] 02_69 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPHDLY_CFG[11] 03_69 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPHDLY_CFG[12] 02_70 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPHDLY_CFG[13] 03_70 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPHDLY_CFG[14] 02_71 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPHDLY_CFG[15] 03_71 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPHDLY_CFG[16] 02_72 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPHDLY_CFG[17] 03_72 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPHDLY_CFG[18] 02_73 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPHDLY_CFG[19] 03_73 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPHDLY_CFG[20] 02_74 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPHDLY_CFG[21] 03_74 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPHDLY_CFG[22] 02_75 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPHDLY_CFG[23] 03_75 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPI_GREY_SEL[0] 03_498 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPI_INVSTROBE_SEL[0] 02_498 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPI_PPM_CFG[0] 02_488 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPI_PPM_CFG[1] 03_488 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPI_PPM_CFG[2] 02_489 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPI_PPM_CFG[3] 03_489 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPI_PPM_CFG[4] 02_490 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPI_PPM_CFG[5] 03_490 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPI_PPM_CFG[6] 02_491 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPI_PPM_CFG[7] 03_491 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPI_PPMCLK_SEL.TXUSRCLK2 03_497 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPI_SYNFREQ_PPM[0] 02_496 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPI_SYNFREQ_PPM[1] 03_496 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPI_SYNFREQ_PPM[2] 02_497 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPI_CFG0[0] 02_40 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPI_CFG0[1] 03_40 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPI_CFG1[0] 02_41 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPI_CFG1[1] 03_41 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPI_CFG2[0] 02_42 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPI_CFG2[1] 03_42 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPI_CFG3[0] 02_43 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPI_CFG4[0] 03_43 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPI_CFG5[0] 02_44 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPI_CFG5[1] 03_44 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPI_CFG5[2] 02_45 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPMARESET_TIME[0] 00_128 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPMARESET_TIME[1] 01_128 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPMARESET_TIME[2] 00_129 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPMARESET_TIME[3] 01_129 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPMARESET_TIME[4] 00_130 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXSYNC_MULTILANE[0] 01_133 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXSYNC_OVRD[0] 00_135 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXSYNC_SKIP_DA[0] 00_134 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.UCODEER_CLR[0] 01_00 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.USE_PCS_CLK_PHASE_SEL[0] 02_463 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ZINV_DMONITORCLK 02_13 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ZINV_DRPCLK 02_00 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ZINV_RXUSRCLK 03_01 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ZINV_SIGVALIDCLK 03_13 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ZINV_TXPHDLYTSTCLK 02_03 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ZINV_TXUSRCLK 03_04 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ZINV_CLKRSVD0 02_23 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ZINV_CLKRSVD1 03_23 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ZINV_RXUSRCLK2 02_02 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ZINV_TXUSRCLK2 02_05 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ACJTAG_DEBUG_MODE[0] 00_07 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ACJTAG_MODE[0] 01_06 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ACJTAG_RESET[0] 01_07 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[0] 02_464 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[1] 03_464 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[2] 02_465 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[3] 03_465 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[4] 02_466 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[5] 03_466 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[6] 02_467 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[7] 03_467 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[8] 02_468 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[9] 03_468 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[10] 02_469 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[11] 03_469 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[12] 02_470 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[13] 03_470 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[14] 02_471 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[15] 03_471 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[16] 02_472 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[17] 03_472 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[18] 02_473 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[19] 03_473 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ALIGN_COMMA_DOUBLE 00_522 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[0] 00_496 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[1] 01_496 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[2] 00_497 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[3] 01_497 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[4] 00_498 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[5] 01_498 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[6] 00_499 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[7] 01_499 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[8] 00_500 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[9] 01_500 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ALIGN_COMMA_WORD[0] 01_526 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ALIGN_COMMA_WORD[1] 00_527 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ALIGN_MCOMMA_DET 00_523 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[0] 00_504 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[1] 01_504 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[2] 00_505 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[3] 01_505 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[4] 00_506 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[5] 01_506 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[6] 00_507 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[7] 01_507 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[8] 00_508 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[9] 01_508 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ALIGN_PCOMMA_DET 01_523 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[0] 00_512 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[1] 01_512 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[2] 00_513 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[3] 01_513 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[4] 00_514 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[5] 01_514 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[6] 00_515 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[7] 01_515 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[8] 00_516 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[9] 01_516 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CBCC_DATA_SOURCE_SEL.DECODED 01_661 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[0] 02_392 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[1] 03_392 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[2] 02_393 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[3] 03_393 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[4] 02_394 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[5] 03_394 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[6] 02_395 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[7] 03_395 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[8] 02_396 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[9] 03_396 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[10] 02_397 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[11] 03_397 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[12] 02_398 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[13] 03_398 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[14] 02_399 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[15] 03_399 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[16] 02_400 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[17] 03_400 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[18] 02_401 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[19] 03_401 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[20] 02_402 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[21] 03_402 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[22] 02_403 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[23] 03_403 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[24] 02_404 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[25] 03_404 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[26] 02_405 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[27] 03_405 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[28] 02_406 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[29] 03_406 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[30] 02_407 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[31] 03_407 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[32] 02_408 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[33] 03_408 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[34] 02_409 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[35] 03_409 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[36] 02_410 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[37] 03_410 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[38] 02_411 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[39] 03_411 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[40] 02_412 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[41] 03_412 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[42] 02_413 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG2[0] 02_459 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG2[1] 03_459 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG2[2] 02_460 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG2[3] 03_460 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG2[4] 02_461 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG2[5] 03_461 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG2[6] 02_462 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG3[0] 02_416 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG3[1] 03_416 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG3[2] 02_417 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG3[3] 03_417 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG3[4] 02_418 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG3[5] 03_418 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG3[6] 02_419 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG4[0] 03_438 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG5[0] 02_429 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG5[1] 03_429 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG6[0] 03_436 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG6[1] 02_437 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG6[2] 03_437 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG6[3] 02_438 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_KEEP_ALIGN 01_631 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_MAX_SKEW[0] 00_670 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_MAX_SKEW[1] 01_670 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_MAX_SKEW[2] 00_671 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_MAX_SKEW[3] 01_671 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[0] 00_608 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[1] 01_608 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[2] 00_609 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[3] 01_609 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[4] 00_610 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[5] 01_610 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[6] 00_611 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[7] 01_611 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[8] 00_612 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[9] 01_612 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[0] 00_616 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[1] 01_616 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[2] 00_617 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[3] 01_617 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[4] 00_618 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[5] 01_618 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[6] 00_619 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[7] 01_619 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[8] 00_620 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[9] 01_620 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[0] 00_624 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[1] 01_624 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[2] 00_625 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[3] 01_625 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[4] 00_626 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[5] 01_626 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[6] 00_627 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[7] 01_627 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[8] 00_628 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[9] 01_628 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[0] 00_632 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[1] 01_632 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[2] 00_633 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[3] 01_633 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[4] 00_634 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[5] 01_634 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[6] 00_635 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[7] 01_635 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[8] 00_636 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[9] 01_636 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_ENABLE[0] 00_614 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_ENABLE[1] 01_614 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_ENABLE[2] 00_615 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_ENABLE[3] 01_615 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[0] 00_640 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[1] 01_640 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[2] 00_641 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[3] 01_641 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[4] 00_642 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[5] 01_642 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[6] 00_643 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[7] 01_643 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[8] 00_644 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[9] 01_644 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[0] 00_648 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[1] 01_648 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[2] 00_649 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[3] 01_649 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[4] 00_650 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[5] 01_650 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[6] 00_651 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[7] 01_651 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[8] 00_652 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[9] 01_652 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[0] 00_656 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[1] 01_656 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[2] 00_657 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[3] 01_657 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[4] 00_658 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[5] 01_658 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[6] 00_659 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[7] 01_659 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[8] 00_660 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[9] 01_660 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[0] 00_664 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[1] 01_664 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[2] 00_665 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[3] 01_665 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[4] 00_666 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[5] 01_666 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[6] 00_667 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[7] 01_667 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[8] 00_668 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[9] 01_668 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_ENABLE[0] 00_646 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_ENABLE[1] 01_646 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_ENABLE[2] 00_647 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_ENABLE[3] 01_647 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_USE 01_645 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_LEN[0] 00_623 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_LEN[1] 01_623 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COMMON_SWING[0] 03_311 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_KEEP_IDLE 00_591 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_MAX_LAT[0] 00_557 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_MAX_LAT[1] 01_557 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_MAX_LAT[2] 00_558 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_MAX_LAT[3] 01_558 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_MAX_LAT[4] 00_559 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_MAX_LAT[5] 01_559 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_MIN_LAT[0] 00_565 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_MIN_LAT[1] 01_565 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_MIN_LAT[2] 00_566 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_MIN_LAT[3] 01_566 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_MIN_LAT[4] 00_567 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_MIN_LAT[5] 01_567 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_PRECEDENCE 00_590 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_REPEAT_WAIT[0] 00_573 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_REPEAT_WAIT[1] 01_573 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_REPEAT_WAIT[2] 00_574 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_REPEAT_WAIT[3] 01_574 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_REPEAT_WAIT[4] 00_575 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[0] 00_544 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[1] 01_544 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[2] 00_545 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[3] 01_545 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[4] 00_546 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[5] 01_546 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[6] 00_547 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[7] 01_547 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[8] 00_548 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[9] 01_548 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[0] 00_552 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[1] 01_552 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[2] 00_553 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[3] 01_553 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[4] 00_554 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[5] 01_554 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[6] 00_555 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[7] 01_555 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[8] 00_556 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[9] 01_556 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[0] 00_560 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[1] 01_560 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[2] 00_561 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[3] 01_561 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[4] 00_562 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[5] 01_562 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[6] 00_563 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[7] 01_563 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[8] 00_564 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[9] 01_564 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[0] 00_568 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[1] 01_568 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[2] 00_569 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[3] 01_569 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[4] 00_570 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[5] 01_570 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[6] 00_571 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[7] 01_571 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[8] 00_572 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[9] 01_572 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_ENABLE[0] 00_549 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_ENABLE[1] 01_549 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_ENABLE[2] 00_550 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_ENABLE[3] 01_550 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[0] 00_576 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[1] 01_576 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[2] 00_577 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[3] 01_577 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[4] 00_578 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[5] 01_578 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[6] 00_579 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[7] 01_579 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[8] 00_580 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[9] 01_580 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[0] 00_584 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[1] 01_584 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[2] 00_585 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[3] 01_585 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[4] 00_586 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[5] 01_586 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[6] 00_587 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[7] 01_587 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[8] 00_588 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[9] 01_588 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[0] 00_592 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[1] 01_592 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[2] 00_593 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[3] 01_593 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[4] 00_594 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[5] 01_594 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[6] 00_595 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[7] 01_595 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[8] 00_596 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[9] 01_596 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[0] 00_600 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[1] 01_600 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[2] 00_601 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[3] 01_601 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[4] 00_602 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[5] 01_602 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[6] 00_603 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[7] 01_603 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[8] 00_604 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[9] 01_604 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_ENABLE[0] 00_581 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_ENABLE[1] 01_581 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_ENABLE[2] 00_582 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_ENABLE[3] 01_582 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_USE 00_583 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_LEN[0] 00_589 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_LEN[1] 01_589 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_CORRECT_USE 00_551 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.DEC_MCOMMA_DETECT 01_494 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.DEC_PCOMMA_DETECT 00_495 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.DEC_VALID_COMMA_ONLY 00_494 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[0] 02_368 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[1] 03_368 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[2] 02_369 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[3] 03_369 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[4] 02_370 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[5] 03_370 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[6] 02_371 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[7] 03_371 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[8] 02_372 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[9] 03_372 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[10] 02_373 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[11] 03_373 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[12] 02_374 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[13] 03_374 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[14] 02_375 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[15] 03_375 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[16] 02_376 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[17] 03_376 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[18] 02_377 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[19] 03_377 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[20] 02_378 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[21] 03_378 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[22] 02_379 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[23] 03_379 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_CLK_PHASE_SEL[0] 03_463 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_CONTROL[0] 00_488 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_CONTROL[1] 01_488 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_CONTROL[2] 00_489 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_CONTROL[3] 01_489 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_CONTROL[4] 00_490 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_CONTROL[5] 01_490 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_ERRDET_EN 01_492 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_EYE_SCAN_EN 00_492 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_HORZ_OFFSET[0] 00_480 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_HORZ_OFFSET[1] 01_480 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_HORZ_OFFSET[2] 00_481 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_HORZ_OFFSET[3] 01_481 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_HORZ_OFFSET[4] 00_482 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_HORZ_OFFSET[5] 01_482 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_HORZ_OFFSET[6] 00_483 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_HORZ_OFFSET[7] 01_483 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_HORZ_OFFSET[8] 00_484 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_HORZ_OFFSET[9] 01_484 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_HORZ_OFFSET[10] 00_485 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_HORZ_OFFSET[11] 01_485 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_PMA_CFG[0] 02_624 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_PMA_CFG[1] 03_624 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_PMA_CFG[2] 02_625 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_PMA_CFG[3] 03_625 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_PMA_CFG[4] 02_626 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_PMA_CFG[5] 03_626 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_PMA_CFG[6] 02_627 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_PMA_CFG[7] 03_627 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_PMA_CFG[8] 02_628 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_PMA_CFG[9] 03_628 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_PRESCALE[0] 01_477 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_PRESCALE[1] 00_478 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_PRESCALE[2] 01_478 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_PRESCALE[3] 00_479 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_PRESCALE[4] 01_479 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[0] 00_392 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[1] 01_392 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[2] 00_393 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[3] 01_393 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[4] 00_394 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[5] 01_394 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[6] 00_395 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[7] 01_395 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[8] 00_396 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[9] 01_396 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[10] 00_397 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[11] 01_397 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[12] 00_398 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[13] 01_398 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[14] 00_399 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[15] 01_399 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[16] 00_400 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[17] 01_400 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[18] 00_401 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[19] 01_401 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[20] 00_402 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[21] 01_402 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[22] 00_403 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[23] 01_403 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[24] 00_404 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[25] 01_404 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[26] 00_405 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[27] 01_405 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[28] 00_406 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[29] 01_406 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[30] 00_407 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[31] 01_407 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[32] 00_408 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[33] 01_408 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[34] 00_409 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[35] 01_409 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[36] 00_410 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[37] 01_410 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[38] 00_411 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[39] 01_411 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[40] 00_412 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[41] 01_412 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[42] 00_413 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[43] 01_413 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[44] 00_414 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[45] 01_414 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[46] 00_415 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[47] 01_415 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[48] 00_416 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[49] 01_416 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[50] 00_417 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[51] 01_417 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[52] 00_418 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[53] 01_418 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[54] 00_419 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[55] 01_419 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[56] 00_420 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[57] 01_420 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[58] 00_421 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[59] 01_421 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[60] 00_422 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[61] 01_422 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[62] 00_423 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[63] 01_423 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[64] 00_424 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[65] 01_424 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[66] 00_425 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[67] 01_425 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[68] 00_426 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[69] 01_426 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[70] 00_427 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[71] 01_427 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[72] 00_428 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[73] 01_428 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[74] 00_429 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[75] 01_429 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[76] 00_430 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[77] 01_430 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[78] 00_431 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[79] 01_431 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[0] 00_352 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[1] 01_352 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[2] 00_353 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[3] 01_353 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[4] 00_354 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[5] 01_354 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[6] 00_355 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[7] 01_355 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[8] 00_356 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[9] 01_356 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[10] 00_357 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[11] 01_357 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[12] 00_358 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[13] 01_358 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[14] 00_359 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[15] 01_359 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[16] 00_360 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[17] 01_360 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[18] 00_361 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[19] 01_361 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[20] 00_362 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[21] 01_362 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[22] 00_363 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[23] 01_363 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[24] 00_364 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[25] 01_364 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[26] 00_365 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[27] 01_365 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[28] 00_366 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[29] 01_366 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[30] 00_367 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[31] 01_367 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[32] 00_368 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[33] 01_368 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[34] 00_369 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[35] 01_369 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[36] 00_370 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[37] 01_370 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[38] 00_371 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[39] 01_371 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[40] 00_372 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[41] 01_372 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[42] 00_373 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[43] 01_373 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[44] 00_374 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[45] 01_374 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[46] 00_375 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[47] 01_375 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[48] 00_376 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[49] 01_376 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[50] 00_377 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[51] 01_377 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[52] 00_378 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[53] 01_378 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[54] 00_379 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[55] 01_379 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[56] 00_380 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[57] 01_380 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[58] 00_381 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[59] 01_381 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[60] 00_382 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[61] 01_382 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[62] 00_383 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[63] 01_383 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[64] 00_384 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[65] 01_384 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[66] 00_385 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[67] 01_385 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[68] 00_386 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[69] 01_386 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[70] 00_387 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[71] 01_387 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[72] 00_388 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[73] 01_388 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[74] 00_389 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[75] 01_389 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[76] 00_390 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[77] 01_390 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[78] 00_391 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[79] 01_391 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[0] 00_432 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[1] 01_432 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[2] 00_433 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[3] 01_433 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[4] 00_434 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[5] 01_434 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[6] 00_435 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[7] 01_435 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[8] 00_436 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[9] 01_436 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[10] 00_437 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[11] 01_437 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[12] 00_438 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[13] 01_438 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[14] 00_439 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[15] 01_439 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[16] 00_440 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[17] 01_440 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[18] 00_441 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[19] 01_441 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[20] 00_442 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[21] 01_442 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[22] 00_443 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[23] 01_443 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[24] 00_444 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[25] 01_444 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[26] 00_445 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[27] 01_445 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[28] 00_446 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[29] 01_446 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[30] 00_447 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[31] 01_447 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[32] 00_448 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[33] 01_448 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[34] 00_449 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[35] 01_449 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[36] 00_450 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[37] 01_450 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[38] 00_451 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[39] 01_451 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[40] 00_452 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[41] 01_452 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[42] 00_453 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[43] 01_453 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[44] 00_454 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[45] 01_454 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[46] 00_455 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[47] 01_455 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[48] 00_456 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[49] 01_456 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[50] 00_457 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[51] 01_457 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[52] 00_458 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[53] 01_458 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[54] 00_459 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[55] 01_459 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[56] 00_460 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[57] 01_460 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[58] 00_461 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[59] 01_461 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[60] 00_462 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[61] 01_462 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[62] 00_463 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[63] 01_463 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[64] 00_464 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[65] 01_464 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[66] 00_465 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[67] 01_465 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[68] 00_466 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[69] 01_466 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[70] 00_467 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[71] 01_467 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[72] 00_468 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[73] 01_468 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[74] 00_469 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[75] 01_469 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[76] 00_470 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[77] 01_470 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[78] 00_471 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[79] 01_471 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_VERT_OFFSET[0] 00_472 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_VERT_OFFSET[1] 01_472 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_VERT_OFFSET[2] 00_473 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_VERT_OFFSET[3] 01_473 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_VERT_OFFSET[4] 00_474 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_VERT_OFFSET[5] 01_474 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_VERT_OFFSET[6] 00_475 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_VERT_OFFSET[7] 01_475 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_VERT_OFFSET[8] 00_476 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.FTS_DESKEW_SEQ_ENABLE[0] 00_662 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.FTS_DESKEW_SEQ_ENABLE[1] 01_662 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.FTS_DESKEW_SEQ_ENABLE[2] 00_663 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.FTS_DESKEW_SEQ_ENABLE[3] 01_663 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.FTS_LANE_DESKEW_CFG[0] 00_654 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.FTS_LANE_DESKEW_CFG[1] 01_654 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.FTS_LANE_DESKEW_CFG[2] 00_655 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.FTS_LANE_DESKEW_CFG[3] 01_655 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.FTS_LANE_DESKEW_EN 01_653 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.GEARBOX_MODE[0] 00_224 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.GEARBOX_MODE[1] 01_224 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.GEARBOX_MODE[2] 00_225 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.IN_USE 00_00 00_01 00_47 00_52 00_53 00_65 01_01 01_47 02_129 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.INV_DMONITORCLK 02_13 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.INV_DRPCLK 02_00 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.INV_RXUSRCLK 03_01 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.INV_SIGVALIDCLK 03_13 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.INV_TXPHDLYTSTCLK 02_03 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.INV_TXUSRCLK 03_04 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.INV_CLKRSVD0 02_23 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.INV_CLKRSVD1 03_23 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.INV_RXUSRCLK2 02_02 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.INV_TXUSRCLK2 02_05 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.LOOPBACK_CFG[0] 02_20 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.OUTREFCLK_SEL_INV[0] 00_149 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.OUTREFCLK_SEL_INV[1] 01_149 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PCS_PCIE_EN 00_216 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[0] 02_184 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[1] 03_184 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[2] 02_185 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[3] 03_185 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[4] 02_186 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[5] 03_186 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[6] 02_187 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[7] 03_187 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[8] 02_188 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[9] 03_188 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[10] 02_189 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[11] 03_189 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[12] 02_190 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[13] 03_190 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[14] 02_191 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[15] 03_191 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[16] 02_192 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[17] 03_192 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[18] 02_193 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[19] 03_193 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[20] 02_194 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[21] 03_194 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[22] 02_195 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[23] 03_195 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[24] 02_196 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[25] 03_196 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[26] 02_197 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[27] 03_197 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[28] 02_198 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[29] 03_198 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[30] 02_199 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[31] 03_199 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[32] 02_200 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[33] 03_200 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[34] 02_201 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[35] 03_201 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[36] 02_202 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[37] 03_202 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[38] 02_203 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[39] 03_203 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[40] 02_204 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[41] 03_204 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[42] 02_205 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[43] 03_205 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[44] 02_206 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[45] 03_206 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[46] 02_207 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[47] 03_207 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[0] 01_216 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[1] 00_217 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[2] 01_217 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[3] 00_218 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[4] 01_218 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[5] 00_219 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[6] 01_219 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[7] 00_220 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[8] 01_220 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[9] 00_221 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[10] 01_221 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[11] 00_222 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[0] 00_208 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[1] 01_208 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[2] 00_209 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[3] 01_209 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[4] 00_210 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[5] 01_210 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[6] 00_211 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[7] 01_211 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[0] 00_212 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[1] 01_212 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[2] 00_213 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[3] 01_213 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[4] 00_214 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[5] 01_214 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[6] 00_215 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[7] 01_215 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PMA_LOOPBACK_CFG[0] 01_207 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[0] 02_520 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[1] 03_520 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[2] 02_521 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[3] 03_521 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[4] 02_522 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[5] 03_522 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[6] 02_523 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[7] 03_523 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[8] 02_524 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[9] 03_524 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[10] 02_525 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[11] 03_525 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[12] 02_526 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[13] 03_526 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[14] 02_527 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[15] 03_527 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[16] 02_528 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[17] 03_528 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[18] 02_529 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[19] 03_529 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[20] 02_530 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[21] 03_530 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[22] 02_531 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[23] 03_531 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[24] 02_532 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[25] 03_532 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[26] 02_533 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[27] 03_533 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[28] 02_534 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[29] 03_534 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[30] 02_535 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[31] 03_535 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[0] 02_336 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[1] 03_336 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[2] 02_337 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[3] 03_337 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[4] 02_338 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[5] 03_338 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[6] 02_339 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[7] 03_339 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[8] 02_340 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[9] 03_340 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[10] 02_341 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[11] 03_341 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[12] 02_342 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[13] 03_342 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[14] 02_343 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[15] 03_343 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[16] 02_344 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[17] 03_344 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[18] 02_345 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[19] 03_345 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[20] 02_346 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[21] 03_346 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[22] 02_347 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[23] 03_347 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[24] 02_348 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[25] 03_348 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[26] 02_349 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[27] 03_349 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[28] 02_350 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[29] 03_350 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[30] 02_351 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[31] 03_351 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV3[0] 02_288 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV3[1] 03_288 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV4[0] 02_156 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV4[1] 03_156 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV4[2] 02_157 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV4[3] 03_157 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV5[0] 03_159 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV6[0] 02_303 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV7[0] 03_303 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_BIAS_CFG[0] 02_112 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_BIAS_CFG[1] 03_112 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_BIAS_CFG[2] 02_113 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_BIAS_CFG[3] 03_113 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_BIAS_CFG[4] 02_114 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_BIAS_CFG[5] 03_114 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_BIAS_CFG[6] 02_115 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_BIAS_CFG[7] 03_115 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_BIAS_CFG[8] 02_116 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_BIAS_CFG[9] 03_116 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_BIAS_CFG[10] 02_117 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_BIAS_CFG[11] 03_117 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_BIAS_CFG[12] 02_118 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_BIAS_CFG[13] 03_118 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_BIAS_CFG[14] 02_119 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_BIAS_CFG[15] 03_119 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_BUFFER_CFG[0] 02_536 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_BUFFER_CFG[1] 03_536 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_BUFFER_CFG[2] 02_537 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_BUFFER_CFG[3] 03_537 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_BUFFER_CFG[4] 02_538 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_BUFFER_CFG[5] 03_538 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_CLKMUX_EN[0] 02_128 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_CM_SEL[0] 00_138 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_CM_SEL[1] 01_138 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_CM_TRIM[0] 02_304 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_CM_TRIM[1] 03_304 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_CM_TRIM[2] 02_305 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_CM_TRIM[3] 03_305 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_DATA_WIDTH[0] 01_141 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_DATA_WIDTH[1] 00_142 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_DATA_WIDTH[2] 01_142 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_DDI_SEL[0] 00_696 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_DDI_SEL[1] 01_696 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_DDI_SEL[2] 00_697 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_DDI_SEL[3] 01_697 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_DDI_SEL[4] 00_698 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_DDI_SEL[5] 01_698 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_DEBUG_CFG[0] 02_616 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_DEBUG_CFG[1] 03_616 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_DEBUG_CFG[2] 02_617 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_DEBUG_CFG[3] 03_617 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_DEBUG_CFG[4] 02_618 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_DEBUG_CFG[5] 03_618 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_DEBUG_CFG[6] 02_619 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_DEBUG_CFG[7] 03_619 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_DEBUG_CFG[8] 02_620 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_DEBUG_CFG[9] 03_620 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_DEBUG_CFG[10] 02_621 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_DEBUG_CFG[11] 03_621 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_DEBUG_CFG[12] 02_622 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_DEBUG_CFG[13] 03_622 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_DEFER_RESET_BUF_EN 02_552 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_DISPERR_SEQ_MATCH 01_495 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_OS_CFG[0] 00_288 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_OS_CFG[1] 01_288 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_OS_CFG[2] 00_289 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_OS_CFG[3] 01_289 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_OS_CFG[4] 00_290 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_OS_CFG[5] 01_290 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_OS_CFG[6] 00_291 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_OS_CFG[7] 01_291 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_OS_CFG[8] 00_292 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_OS_CFG[9] 01_292 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_OS_CFG[10] 00_293 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_OS_CFG[11] 01_293 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_OS_CFG[12] 00_294 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_SIG_VALID_DLY[0] 00_524 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_SIG_VALID_DLY[1] 01_524 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_SIG_VALID_DLY[2] 00_525 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_SIG_VALID_DLY[3] 01_525 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_SIG_VALID_DLY[4] 00_526 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_XCLK_SEL.RXUSR 00_143 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_CLK25_DIV[0] 00_139 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_CLK25_DIV[1] 01_139 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_CLK25_DIV[2] 00_140 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_CLK25_DIV[3] 01_140 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_CLK25_DIV[4] 00_141 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXBUF_ADDR_MODE.FAST 03_555 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXBUF_EIDLE_HI_CNT[0] 02_558 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXBUF_EIDLE_HI_CNT[1] 03_558 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXBUF_EIDLE_HI_CNT[2] 02_559 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXBUF_EIDLE_HI_CNT[3] 03_559 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXBUF_EIDLE_LO_CNT[0] 02_556 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXBUF_EIDLE_LO_CNT[1] 03_556 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXBUF_EIDLE_LO_CNT[2] 02_557 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXBUF_EIDLE_LO_CNT[3] 03_557 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXBUF_EN 02_11 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXBUF_RESET_ON_CB_CHANGE 02_560 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXBUF_RESET_ON_COMMAALIGN 02_561 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXBUF_RESET_ON_EIDLE 02_547 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXBUF_RESET_ON_RATE_CHANGE 03_560 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXBUF_THRESH_OVFLW[0] 03_552 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXBUF_THRESH_OVFLW[1] 02_553 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXBUF_THRESH_OVFLW[2] 03_553 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXBUF_THRESH_OVFLW[3] 02_554 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXBUF_THRESH_OVFLW[4] 03_554 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXBUF_THRESH_OVFLW[5] 02_555 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXBUF_THRESH_OVRD 02_548 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXBUF_THRESH_UNDFLW[0] 02_544 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXBUF_THRESH_UNDFLW[1] 03_544 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXBUF_THRESH_UNDFLW[2] 02_545 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXBUF_THRESH_UNDFLW[3] 03_545 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXBUF_THRESH_UNDFLW[4] 02_546 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXBUF_THRESH_UNDFLW[5] 03_546 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXBUFRESET_TIME[0] 01_101 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXBUFRESET_TIME[1] 00_102 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXBUFRESET_TIME[2] 01_102 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXBUFRESET_TIME[3] 00_103 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXBUFRESET_TIME[4] 01_103 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[0] 02_640 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[1] 03_640 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[2] 02_641 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[3] 03_641 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[4] 02_642 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[5] 03_642 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[6] 02_643 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[7] 03_643 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[8] 02_644 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[9] 03_644 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[10] 02_645 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[11] 03_645 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[12] 02_646 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[13] 03_646 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[14] 02_647 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[15] 03_647 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[16] 02_648 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[17] 03_648 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[18] 02_649 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[19] 03_649 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[20] 02_650 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[21] 03_650 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[22] 02_651 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[23] 03_651 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[24] 02_652 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[25] 03_652 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[26] 02_653 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[27] 03_653 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[28] 02_654 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[29] 03_654 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[30] 02_655 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[31] 03_655 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[32] 02_656 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[33] 03_656 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[34] 02_657 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[35] 03_657 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[36] 02_658 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[37] 03_658 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[38] 02_659 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[39] 03_659 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[40] 02_660 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[41] 03_660 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[42] 02_661 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[43] 03_661 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[44] 02_662 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[45] 03_662 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[46] 02_663 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[47] 03_663 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[48] 02_664 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[49] 03_664 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[50] 02_665 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[51] 03_665 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[52] 02_666 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[53] 03_666 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[54] 02_667 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[55] 03_667 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[56] 02_668 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[57] 03_668 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[58] 02_669 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[59] 03_669 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[60] 02_670 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[61] 03_670 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[62] 02_671 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[63] 03_671 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[64] 02_672 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[65] 03_672 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[66] 02_673 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[67] 03_673 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[68] 02_674 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[69] 03_674 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[70] 02_675 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[71] 03_675 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[72] 02_676 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[73] 03_676 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[74] 02_677 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[75] 03_677 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[76] 02_678 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[77] 03_678 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[78] 02_679 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[79] 03_679 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[80] 02_680 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[81] 03_680 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[82] 02_681 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_FR_RESET_ON_EIDLE[0] 02_638 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_HOLD_DURING_EIDLE[0] 03_637 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_LOCK_CFG[0] 02_632 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_LOCK_CFG[1] 03_632 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_LOCK_CFG[2] 02_633 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_LOCK_CFG[3] 03_633 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_LOCK_CFG[4] 02_634 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_LOCK_CFG[5] 03_634 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_PH_RESET_ON_EIDLE[0] 03_638 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDRFREQRESET_TIME[0] 01_106 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDRFREQRESET_TIME[1] 00_107 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDRFREQRESET_TIME[2] 01_107 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDRFREQRESET_TIME[3] 00_108 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDRFREQRESET_TIME[4] 01_108 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDRPHRESET_TIME[0] 00_109 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDRPHRESET_TIME[1] 01_109 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDRPHRESET_TIME[2] 00_110 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDRPHRESET_TIME[3] 01_110 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDRPHRESET_TIME[4] 00_111 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXDLY_CFG[0] 00_680 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXDLY_CFG[1] 01_680 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXDLY_CFG[2] 00_681 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXDLY_CFG[3] 01_681 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXDLY_CFG[4] 00_682 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXDLY_CFG[5] 01_682 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXDLY_CFG[6] 00_683 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXDLY_CFG[7] 01_683 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXDLY_CFG[8] 00_684 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXDLY_CFG[9] 01_684 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXDLY_CFG[10] 00_685 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXDLY_CFG[11] 01_685 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXDLY_CFG[12] 00_686 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXDLY_CFG[13] 01_686 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXDLY_CFG[14] 00_687 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXDLY_CFG[15] 01_687 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXDLY_LCFG[0] 02_576 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXDLY_LCFG[1] 03_576 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXDLY_LCFG[2] 02_577 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXDLY_LCFG[3] 03_577 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXDLY_LCFG[4] 02_578 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXDLY_LCFG[5] 03_578 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXDLY_LCFG[6] 02_579 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXDLY_LCFG[7] 03_579 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXDLY_LCFG[8] 02_580 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXDLY_TAP_CFG[0] 00_672 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXDLY_TAP_CFG[1] 01_672 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXDLY_TAP_CFG[2] 00_673 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXDLY_TAP_CFG[3] 01_673 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXDLY_TAP_CFG[4] 00_674 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXDLY_TAP_CFG[5] 01_674 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXDLY_TAP_CFG[6] 00_675 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXDLY_TAP_CFG[7] 01_675 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXDLY_TAP_CFG[8] 00_676 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXDLY_TAP_CFG[9] 01_676 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXDLY_TAP_CFG[10] 00_677 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXDLY_TAP_CFG[11] 01_677 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXDLY_TAP_CFG[12] 00_678 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXDLY_TAP_CFG[13] 01_678 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXDLY_TAP_CFG[14] 00_679 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXDLY_TAP_CFG[15] 01_679 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXGEARBOX_EN 01_607 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXISCANRESET_TIME[0] 01_123 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXISCANRESET_TIME[1] 00_124 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXISCANRESET_TIME[2] 01_124 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXISCANRESET_TIME[3] 00_125 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXISCANRESET_TIME[4] 01_125 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPM_BIAS_STARTUP_DISABLE[0] 03_391 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPM_CFG[0] 02_328 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPM_CFG[1] 03_328 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPM_CFG[2] 02_329 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPM_CFG[3] 03_329 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPM_CM_CFG[0] 02_430 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPM_GC_CFG[0] 02_432 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPM_GC_CFG[1] 03_432 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPM_GC_CFG[2] 02_433 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPM_GC_CFG[3] 03_433 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPM_GC_CFG[4] 02_434 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPM_GC_CFG[5] 03_434 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPM_GC_CFG[6] 02_435 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPM_GC_CFG[7] 03_435 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPM_GC_CFG[8] 02_436 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPM_GC_CFG2[0] 03_442 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPM_GC_CFG2[1] 02_443 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPM_GC_CFG2[2] 03_443 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG[0] 00_336 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG[1] 01_336 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG[2] 00_337 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG[3] 01_337 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG[4] 00_338 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG[5] 01_338 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG[6] 00_339 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG[7] 01_339 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG[8] 00_340 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG[9] 01_340 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG[10] 00_341 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG[11] 01_341 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG[12] 00_342 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG[13] 01_342 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG2[0] 02_424 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG2[1] 03_424 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG2[2] 02_425 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG2[3] 03_425 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG2[4] 02_426 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG3[0] 03_389 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG3[1] 02_390 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG3[2] 03_390 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG3[3] 02_391 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HOLD_DURING_EIDLE[0] 00_247 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPM_INCM_CFG[0] 02_439 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPM_IPCM_CFG[0] 03_439 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG[0] 00_344 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG[1] 01_344 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG[2] 00_345 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG[3] 01_345 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG[4] 00_346 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG[5] 01_346 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG[6] 00_347 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG[7] 01_347 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG[8] 00_348 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG[9] 01_348 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG[10] 00_349 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG[11] 01_349 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG[12] 00_350 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG[13] 01_350 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG[14] 00_351 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG[15] 01_351 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG[16] 00_343 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG[17] 01_343 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG2[0] 03_426 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG2[1] 02_427 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG2[2] 03_427 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG2[3] 02_428 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG2[4] 03_428 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPM_OSINT_CFG[0] 02_440 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPM_OSINT_CFG[1] 03_440 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPM_OSINT_CFG[2] 02_441 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPM_CFG1[0] 02_330 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPMRESET_TIME[0] 00_112 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPMRESET_TIME[1] 01_112 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPMRESET_TIME[2] 00_113 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPMRESET_TIME[3] 01_113 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPMRESET_TIME[4] 00_114 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPMRESET_TIME[5] 01_114 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPMRESET_TIME[6] 00_115 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXOOB_CFG[0] 00_144 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXOOB_CFG[1] 01_144 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXOOB_CFG[2] 00_145 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXOOB_CFG[3] 01_145 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXOOB_CFG[4] 00_146 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXOOB_CFG[5] 01_146 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXOOB_CFG[6] 00_147 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXOOB_CLK_CFG.FABRIC 03_129 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXOSCALRESET_TIME[0] 00_187 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXOSCALRESET_TIME[1] 01_187 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXOSCALRESET_TIME[2] 00_188 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXOSCALRESET_TIME[3] 01_188 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXOSCALRESET_TIME[4] 00_189 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXOSCALRESET_TIMEOUT[0] 01_189 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXOSCALRESET_TIMEOUT[1] 00_190 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXOSCALRESET_TIMEOUT[2] 01_190 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXOSCALRESET_TIMEOUT[3] 00_191 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXOSCALRESET_TIMEOUT[4] 01_191 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXOUT_DIV[0] 02_384 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXOUT_DIV[1] 03_384 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXPCSRESET_TIME[0] 01_115 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXPCSRESET_TIME[1] 00_116 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXPCSRESET_TIME[2] 01_116 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXPCSRESET_TIME[3] 00_117 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXPCSRESET_TIME[4] 01_117 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[0] 02_584 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[1] 03_584 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[2] 02_585 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[3] 03_585 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[4] 02_586 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[5] 03_586 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[6] 02_587 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[7] 03_587 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[8] 02_588 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[9] 03_588 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[10] 02_589 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[11] 03_589 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[12] 02_590 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[13] 03_590 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[14] 02_591 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[15] 03_591 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[16] 02_592 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[17] 03_592 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[18] 02_593 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[19] 03_593 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[20] 02_594 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[21] 03_594 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[22] 02_595 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[23] 03_595 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXPH_MONITOR_SEL[0] 00_700 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXPH_MONITOR_SEL[1] 01_700 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXPH_MONITOR_SEL[2] 00_701 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXPH_MONITOR_SEL[3] 01_701 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXPH_MONITOR_SEL[4] 00_702 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[0] 02_600 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[1] 03_600 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[2] 02_601 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[3] 03_601 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[4] 02_602 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[5] 03_602 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[6] 02_603 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[7] 03_603 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[8] 02_604 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[9] 03_604 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[10] 02_605 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[11] 03_605 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[12] 02_606 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[13] 03_606 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[14] 02_607 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[15] 03_607 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[16] 02_608 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[17] 03_608 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[18] 02_609 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[19] 03_609 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[20] 02_610 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[21] 03_610 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[22] 02_611 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[23] 03_611 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXPI_CFG0[0] 03_430 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXPI_CFG0[1] 02_431 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXPI_CFG0[2] 03_431 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXPI_CFG1[0] 02_442 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXPI_CFG2[0] 03_441 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXPMARESET_TIME[0] 00_104 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXPMARESET_TIME[1] 01_104 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXPMARESET_TIME[2] 00_105 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXPMARESET_TIME[3] 01_105 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXPMARESET_TIME[4] 00_106 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXPRBS_ERR_LOOPBACK[0] 00_136 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXSLIDE_AUTO_WAIT[0] 00_520 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXSLIDE_AUTO_WAIT[1] 01_520 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXSLIDE_AUTO_WAIT[2] 00_521 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXSLIDE_AUTO_WAIT[3] 01_521 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXSLIDE_MODE.AUTO 00_519 !01_519 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXSLIDE_MODE.PCS !00_519 01_519 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXSLIDE_MODE.PMA 00_519 01_519 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXSYNC_MULTILANE[0] 00_133 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXSYNC_OVRD[0] 01_135 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXSYNC_SKIP_DA[0] 01_134 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.SAS_MAX_COM[0] 00_171 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.SAS_MAX_COM[1] 01_171 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.SAS_MAX_COM[2] 00_172 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.SAS_MAX_COM[3] 01_172 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.SAS_MAX_COM[4] 00_173 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.SAS_MAX_COM[5] 01_173 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.SAS_MAX_COM[6] 00_174 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.SAS_MIN_COM[0] 01_156 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.SAS_MIN_COM[1] 00_157 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.SAS_MIN_COM[2] 01_157 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.SAS_MIN_COM[3] 00_158 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.SAS_MIN_COM[4] 01_158 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.SAS_MIN_COM[5] 00_159 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.SATA_BURST_SEQ_LEN[0] 00_150 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.SATA_BURST_SEQ_LEN[1] 01_150 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.SATA_BURST_SEQ_LEN[2] 00_151 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.SATA_BURST_SEQ_LEN[3] 01_151 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.SATA_BURST_VAL[0] 01_147 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.SATA_BURST_VAL[1] 00_148 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.SATA_BURST_VAL[2] 01_148 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.SATA_EIDLE_VAL[0] 00_152 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.SATA_EIDLE_VAL[1] 01_152 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.SATA_EIDLE_VAL[2] 00_153 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.SATA_MAX_BURST[0] 00_168 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.SATA_MAX_BURST[1] 01_168 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.SATA_MAX_BURST[2] 00_169 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.SATA_MAX_BURST[3] 01_169 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.SATA_MAX_BURST[4] 00_170 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.SATA_MAX_BURST[5] 01_170 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.SATA_MAX_INIT[0] 00_176 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.SATA_MAX_INIT[1] 01_176 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.SATA_MAX_INIT[2] 00_177 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.SATA_MAX_INIT[3] 01_177 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.SATA_MAX_INIT[4] 00_178 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.SATA_MAX_INIT[5] 01_178 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.SATA_MAX_WAKE[0] 00_179 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.SATA_MAX_WAKE[1] 01_179 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.SATA_MAX_WAKE[2] 00_180 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.SATA_MAX_WAKE[3] 01_180 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.SATA_MAX_WAKE[4] 00_181 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.SATA_MAX_WAKE[5] 01_181 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.SATA_MIN_BURST[0] 01_153 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.SATA_MIN_BURST[1] 00_154 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.SATA_MIN_BURST[2] 01_154 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.SATA_MIN_BURST[3] 00_155 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.SATA_MIN_BURST[4] 01_155 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.SATA_MIN_BURST[5] 00_156 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.SATA_MIN_INIT[0] 00_160 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.SATA_MIN_INIT[1] 01_160 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.SATA_MIN_INIT[2] 00_161 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.SATA_MIN_INIT[3] 01_161 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.SATA_MIN_INIT[4] 00_162 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.SATA_MIN_INIT[5] 01_162 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.SATA_MIN_WAKE[0] 00_163 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.SATA_MIN_WAKE[1] 01_163 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.SATA_MIN_WAKE[2] 00_164 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.SATA_MIN_WAKE[3] 01_164 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.SATA_MIN_WAKE[4] 00_165 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.SATA_MIN_WAKE[5] 01_165 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.SATA_PLL_CFG.VCO_1500MHZ 02_55 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.SATA_PLL_CFG.VCO_750MHZ 03_55 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.SHOW_REALIGN_COMMA 01_522 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TERM_RCAL_CFG[0] 02_136 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TERM_RCAL_CFG[1] 03_136 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TERM_RCAL_CFG[2] 02_137 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TERM_RCAL_CFG[3] 03_137 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TERM_RCAL_CFG[4] 02_138 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TERM_RCAL_CFG[5] 03_138 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TERM_RCAL_CFG[6] 02_139 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TERM_RCAL_CFG[7] 03_139 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TERM_RCAL_CFG[8] 02_140 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TERM_RCAL_CFG[9] 03_140 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TERM_RCAL_CFG[10] 02_141 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TERM_RCAL_CFG[11] 03_141 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TERM_RCAL_CFG[12] 02_142 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TERM_RCAL_CFG[13] 03_142 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TERM_RCAL_CFG[14] 02_143 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TERM_RCAL_OVRD[0] 03_150 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TERM_RCAL_OVRD[1] 02_151 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TERM_RCAL_OVRD[2] 03_151 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TRANS_TIME_RATE[0] 00_192 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TRANS_TIME_RATE[1] 01_192 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TRANS_TIME_RATE[2] 00_193 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TRANS_TIME_RATE[3] 01_193 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TRANS_TIME_RATE[4] 00_194 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TRANS_TIME_RATE[5] 01_194 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TRANS_TIME_RATE[6] 00_195 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TRANS_TIME_RATE[7] 01_195 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[0] 02_504 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[1] 03_504 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[2] 02_505 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[3] 03_505 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[4] 02_506 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[5] 03_506 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[6] 02_507 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[7] 03_507 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[8] 02_508 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[9] 03_508 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[10] 02_509 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[11] 03_509 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[12] 02_510 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[13] 03_510 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[14] 02_511 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[15] 03_511 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[16] 02_512 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[17] 03_512 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[18] 02_513 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[19] 03_513 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[20] 02_514 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[21] 03_514 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[22] 02_515 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[23] 03_515 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[24] 02_516 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[25] 03_516 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[26] 02_517 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[27] 03_517 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[28] 02_518 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[29] 03_518 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[30] 02_519 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[31] 03_519 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_CLKMUX_EN[0] 03_128 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_DATA_WIDTH[0] 02_152 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_DATA_WIDTH[1] 03_152 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_DATA_WIDTH[2] 02_153 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_DRIVE_MODE.PIPE 00_200 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_EIDLE_ASSERT_DELAY[0] 00_203 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_EIDLE_ASSERT_DELAY[1] 01_203 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_EIDLE_ASSERT_DELAY[2] 00_204 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_EIDLE_DEASSERT_DELAY[0] 01_204 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_EIDLE_DEASSERT_DELAY[1] 00_205 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_EIDLE_DEASSERT_DELAY[2] 01_205 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_LOOPBACK_DRIVE_HIZ 01_202 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_MAINCURSOR_SEL[0] 03_289 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_0[0] 02_232 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_0[1] 03_232 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_0[2] 02_233 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_0[3] 03_233 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_0[4] 02_234 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_0[5] 03_234 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_0[6] 02_235 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_1[0] 02_236 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_1[1] 03_236 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_1[2] 02_237 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_1[3] 03_237 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_1[4] 02_238 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_1[5] 03_238 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_1[6] 02_239 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_2[0] 02_240 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_2[1] 03_240 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_2[2] 02_241 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_2[3] 03_241 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_2[4] 02_242 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_2[5] 03_242 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_2[6] 02_243 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_3[0] 02_244 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_3[1] 03_244 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_3[2] 02_245 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_3[3] 03_245 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_3[4] 02_246 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_3[5] 03_246 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_3[6] 02_247 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_4[0] 02_248 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_4[1] 03_248 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_4[2] 02_249 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_4[3] 03_249 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_4[4] 02_250 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_4[5] 03_250 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_4[6] 02_251 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_0[0] 02_252 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_0[1] 03_252 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_0[2] 02_253 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_0[3] 03_253 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_0[4] 02_254 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_0[5] 03_254 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_0[6] 02_255 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_1[0] 02_256 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_1[1] 03_256 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_1[2] 02_257 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_1[3] 03_257 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_1[4] 02_258 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_1[5] 03_258 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_1[6] 02_259 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_2[0] 02_260 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_2[1] 03_260 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_2[2] 02_261 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_2[3] 03_261 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_2[4] 02_262 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_2[5] 03_262 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_2[6] 02_263 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_3[0] 02_264 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_3[1] 03_264 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_3[2] 02_265 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_3[3] 03_265 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_3[4] 02_266 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_3[5] 03_266 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_3[6] 02_267 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_4[0] 02_268 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_4[1] 03_268 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_4[2] 02_269 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_4[3] 03_269 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_4[4] 02_270 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_4[5] 03_270 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_4[6] 02_271 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_PREDRIVER_MODE[0] 00_206 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_RXDETECT_CFG[0] 02_296 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_RXDETECT_CFG[1] 03_296 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_RXDETECT_CFG[2] 02_297 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_RXDETECT_CFG[3] 03_297 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_RXDETECT_CFG[4] 02_298 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_RXDETECT_CFG[5] 03_298 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_RXDETECT_CFG[6] 02_299 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_RXDETECT_CFG[7] 03_299 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_RXDETECT_CFG[8] 02_300 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_RXDETECT_CFG[9] 03_300 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_RXDETECT_CFG[10] 02_301 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_RXDETECT_CFG[11] 03_301 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_RXDETECT_CFG[12] 02_302 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_RXDETECT_CFG[13] 03_302 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_RXDETECT_REF[0] 02_292 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_RXDETECT_REF[1] 03_292 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_RXDETECT_REF[2] 02_293 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_XCLK_SEL.TXUSR 03_11 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_CLK25_DIV[0] 02_144 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_CLK25_DIV[1] 03_144 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_CLK25_DIV[2] 02_145 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_CLK25_DIV[3] 03_145 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_CLK25_DIV[4] 02_146 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_DEEMPH0[0] 02_272 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_DEEMPH0[1] 03_272 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_DEEMPH0[2] 02_273 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_DEEMPH0[3] 03_273 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_DEEMPH0[4] 02_274 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_DEEMPH0[5] 03_274 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_DEEMPH1[0] 02_276 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_DEEMPH1[1] 03_276 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_DEEMPH1[2] 02_277 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_DEEMPH1[3] 03_277 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_DEEMPH1[4] 02_278 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_DEEMPH1[5] 03_278 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXBUF_EN 00_231 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXBUF_RESET_ON_RATE_CHANGE 01_231 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXDLY_CFG[0] 02_80 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXDLY_CFG[1] 03_80 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXDLY_CFG[2] 02_81 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXDLY_CFG[3] 03_81 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXDLY_CFG[4] 02_82 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXDLY_CFG[5] 03_82 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXDLY_CFG[6] 02_83 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXDLY_CFG[7] 03_83 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXDLY_CFG[8] 02_84 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXDLY_CFG[9] 03_84 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXDLY_CFG[10] 02_85 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXDLY_CFG[11] 03_85 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXDLY_CFG[12] 02_86 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXDLY_CFG[13] 03_86 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXDLY_CFG[14] 02_87 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXDLY_CFG[15] 03_87 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXDLY_LCFG[0] 02_568 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXDLY_LCFG[1] 03_568 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXDLY_LCFG[2] 02_569 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXDLY_LCFG[3] 03_569 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXDLY_LCFG[4] 02_570 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXDLY_LCFG[5] 03_570 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXDLY_LCFG[6] 02_571 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXDLY_LCFG[7] 03_571 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXDLY_LCFG[8] 02_572 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXDLY_TAP_CFG[0] 02_88 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXDLY_TAP_CFG[1] 03_88 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXDLY_TAP_CFG[2] 02_89 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXDLY_TAP_CFG[3] 03_89 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXDLY_TAP_CFG[4] 02_90 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXDLY_TAP_CFG[5] 03_90 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXDLY_TAP_CFG[6] 02_91 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXDLY_TAP_CFG[7] 03_91 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXDLY_TAP_CFG[8] 02_92 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXDLY_TAP_CFG[9] 03_92 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXDLY_TAP_CFG[10] 02_93 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXDLY_TAP_CFG[11] 03_93 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXDLY_TAP_CFG[12] 02_94 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXDLY_TAP_CFG[13] 03_94 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXDLY_TAP_CFG[14] 02_95 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXDLY_TAP_CFG[15] 03_95 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXGEARBOX_EN 01_226 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXOOB_CFG[0] 03_20 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXOUT_DIV[0] 02_386 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXOUT_DIV[1] 03_386 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPCSRESET_TIME[0] 01_130 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPCSRESET_TIME[1] 00_131 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPCSRESET_TIME[2] 01_131 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPCSRESET_TIME[3] 00_132 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPCSRESET_TIME[4] 01_132 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPH_CFG[0] 02_96 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPH_CFG[1] 03_96 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPH_CFG[2] 02_97 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPH_CFG[3] 03_97 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPH_CFG[4] 02_98 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPH_CFG[5] 03_98 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPH_CFG[6] 02_99 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPH_CFG[7] 03_99 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPH_CFG[8] 02_100 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPH_CFG[9] 03_100 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPH_CFG[10] 02_101 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPH_CFG[11] 03_101 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPH_CFG[12] 02_102 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPH_CFG[13] 03_102 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPH_CFG[14] 02_103 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPH_CFG[15] 03_103 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPH_MONITOR_SEL[0] 02_108 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPH_MONITOR_SEL[1] 03_108 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPH_MONITOR_SEL[2] 02_109 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPH_MONITOR_SEL[3] 03_109 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPH_MONITOR_SEL[4] 02_110 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[0] 02_64 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[1] 03_64 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[2] 02_65 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[3] 03_65 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[4] 02_66 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[5] 03_66 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[6] 02_67 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[7] 03_67 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[8] 02_68 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[9] 03_68 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[10] 02_69 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[11] 03_69 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[12] 02_70 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[13] 03_70 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[14] 02_71 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[15] 03_71 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[16] 02_72 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[17] 03_72 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[18] 02_73 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[19] 03_73 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[20] 02_74 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[21] 03_74 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[22] 02_75 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[23] 03_75 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPI_GREY_SEL[0] 03_498 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPI_INVSTROBE_SEL[0] 02_498 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPI_PPM_CFG[0] 02_488 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPI_PPM_CFG[1] 03_488 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPI_PPM_CFG[2] 02_489 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPI_PPM_CFG[3] 03_489 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPI_PPM_CFG[4] 02_490 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPI_PPM_CFG[5] 03_490 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPI_PPM_CFG[6] 02_491 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPI_PPM_CFG[7] 03_491 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPI_PPMCLK_SEL.TXUSRCLK2 03_497 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPI_SYNFREQ_PPM[0] 02_496 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPI_SYNFREQ_PPM[1] 03_496 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPI_SYNFREQ_PPM[2] 02_497 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPI_CFG0[0] 02_40 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPI_CFG0[1] 03_40 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPI_CFG1[0] 02_41 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPI_CFG1[1] 03_41 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPI_CFG2[0] 02_42 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPI_CFG2[1] 03_42 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPI_CFG3[0] 02_43 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPI_CFG4[0] 03_43 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPI_CFG5[0] 02_44 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPI_CFG5[1] 03_44 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPI_CFG5[2] 02_45 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPMARESET_TIME[0] 00_128 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPMARESET_TIME[1] 01_128 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPMARESET_TIME[2] 00_129 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPMARESET_TIME[3] 01_129 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPMARESET_TIME[4] 00_130 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXSYNC_MULTILANE[0] 01_133 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXSYNC_OVRD[0] 00_135 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXSYNC_SKIP_DA[0] 00_134 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.UCODEER_CLR[0] 01_00 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.USE_PCS_CLK_PHASE_SEL[0] 02_463 diff --git a/artix7/segbits_gtp_channel_1_mid_right.origin_info.db b/artix7/segbits_gtp_channel_1_mid_right.origin_info.db index 1b4d170..572242d 100644 --- a/artix7/segbits_gtp_channel_1_mid_right.origin_info.db +++ b/artix7/segbits_gtp_channel_1_mid_right.origin_info.db @@ -1,1627 +1,1627 @@ -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ACJTAG_DEBUG_MODE[0] origin:064-gtp-channel-conf 00_07 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ACJTAG_MODE[0] origin:064-gtp-channel-conf 01_06 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ACJTAG_RESET[0] origin:064-gtp-channel-conf 01_07 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ADAPT_CFG0[0] origin:064-gtp-channel-conf 02_464 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ADAPT_CFG0[1] origin:064-gtp-channel-conf 03_464 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ADAPT_CFG0[2] origin:064-gtp-channel-conf 02_465 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ADAPT_CFG0[3] origin:064-gtp-channel-conf 03_465 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ADAPT_CFG0[4] origin:064-gtp-channel-conf 02_466 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ADAPT_CFG0[5] origin:064-gtp-channel-conf 03_466 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ADAPT_CFG0[6] origin:064-gtp-channel-conf 02_467 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ADAPT_CFG0[7] origin:064-gtp-channel-conf 03_467 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ADAPT_CFG0[8] origin:064-gtp-channel-conf 02_468 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ADAPT_CFG0[9] origin:064-gtp-channel-conf 03_468 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ADAPT_CFG0[10] origin:064-gtp-channel-conf 02_469 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ADAPT_CFG0[11] origin:064-gtp-channel-conf 03_469 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ADAPT_CFG0[12] origin:064-gtp-channel-conf 02_470 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ADAPT_CFG0[13] origin:064-gtp-channel-conf 03_470 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ADAPT_CFG0[14] origin:064-gtp-channel-conf 02_471 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ADAPT_CFG0[15] origin:064-gtp-channel-conf 03_471 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ADAPT_CFG0[16] origin:064-gtp-channel-conf 02_472 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ADAPT_CFG0[17] origin:064-gtp-channel-conf 03_472 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ADAPT_CFG0[18] origin:064-gtp-channel-conf 02_473 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ADAPT_CFG0[19] origin:064-gtp-channel-conf 03_473 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ALIGN_COMMA_DOUBLE origin:064-gtp-channel-conf 00_522 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ALIGN_COMMA_ENABLE[0] origin:064-gtp-channel-conf 00_496 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ALIGN_COMMA_ENABLE[1] origin:064-gtp-channel-conf 01_496 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ALIGN_COMMA_ENABLE[2] origin:064-gtp-channel-conf 00_497 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ALIGN_COMMA_ENABLE[3] origin:064-gtp-channel-conf 01_497 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ALIGN_COMMA_ENABLE[4] origin:064-gtp-channel-conf 00_498 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ALIGN_COMMA_ENABLE[5] origin:064-gtp-channel-conf 01_498 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ALIGN_COMMA_ENABLE[6] origin:064-gtp-channel-conf 00_499 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ALIGN_COMMA_ENABLE[7] origin:064-gtp-channel-conf 01_499 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ALIGN_COMMA_ENABLE[8] origin:064-gtp-channel-conf 00_500 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ALIGN_COMMA_ENABLE[9] origin:064-gtp-channel-conf 01_500 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ALIGN_COMMA_WORD[0] origin:064-gtp-channel-conf 01_526 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ALIGN_COMMA_WORD[1] origin:064-gtp-channel-conf 00_527 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ALIGN_MCOMMA_DET origin:064-gtp-channel-conf 00_523 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ALIGN_MCOMMA_VALUE[0] origin:064-gtp-channel-conf 00_504 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ALIGN_MCOMMA_VALUE[1] origin:064-gtp-channel-conf 01_504 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ALIGN_MCOMMA_VALUE[2] origin:064-gtp-channel-conf 00_505 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ALIGN_MCOMMA_VALUE[3] origin:064-gtp-channel-conf 01_505 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ALIGN_MCOMMA_VALUE[4] origin:064-gtp-channel-conf 00_506 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ALIGN_MCOMMA_VALUE[5] origin:064-gtp-channel-conf 01_506 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ALIGN_MCOMMA_VALUE[6] origin:064-gtp-channel-conf 00_507 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ALIGN_MCOMMA_VALUE[7] origin:064-gtp-channel-conf 01_507 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ALIGN_MCOMMA_VALUE[8] origin:064-gtp-channel-conf 00_508 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ALIGN_MCOMMA_VALUE[9] origin:064-gtp-channel-conf 01_508 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ALIGN_PCOMMA_DET origin:064-gtp-channel-conf 01_523 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ALIGN_PCOMMA_VALUE[0] origin:064-gtp-channel-conf 00_512 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ALIGN_PCOMMA_VALUE[1] origin:064-gtp-channel-conf 01_512 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ALIGN_PCOMMA_VALUE[2] origin:064-gtp-channel-conf 00_513 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ALIGN_PCOMMA_VALUE[3] origin:064-gtp-channel-conf 01_513 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ALIGN_PCOMMA_VALUE[4] origin:064-gtp-channel-conf 00_514 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ALIGN_PCOMMA_VALUE[5] origin:064-gtp-channel-conf 01_514 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ALIGN_PCOMMA_VALUE[6] origin:064-gtp-channel-conf 00_515 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ALIGN_PCOMMA_VALUE[7] origin:064-gtp-channel-conf 01_515 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ALIGN_PCOMMA_VALUE[8] origin:064-gtp-channel-conf 00_516 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ALIGN_PCOMMA_VALUE[9] origin:064-gtp-channel-conf 01_516 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CBCC_DATA_SOURCE_SEL.DECODED origin:064-gtp-channel-conf 01_661 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CFOK_CFG[0] origin:064-gtp-channel-conf 02_392 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CFOK_CFG[1] origin:064-gtp-channel-conf 03_392 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CFOK_CFG[2] origin:064-gtp-channel-conf 02_393 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CFOK_CFG[3] origin:064-gtp-channel-conf 03_393 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CFOK_CFG[4] origin:064-gtp-channel-conf 02_394 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CFOK_CFG[5] origin:064-gtp-channel-conf 03_394 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CFOK_CFG[6] origin:064-gtp-channel-conf 02_395 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CFOK_CFG[7] origin:064-gtp-channel-conf 03_395 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CFOK_CFG[8] origin:064-gtp-channel-conf 02_396 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CFOK_CFG[9] origin:064-gtp-channel-conf 03_396 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CFOK_CFG[10] origin:064-gtp-channel-conf 02_397 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CFOK_CFG[11] origin:064-gtp-channel-conf 03_397 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CFOK_CFG[12] origin:064-gtp-channel-conf 02_398 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CFOK_CFG[13] origin:064-gtp-channel-conf 03_398 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CFOK_CFG[14] origin:064-gtp-channel-conf 02_399 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CFOK_CFG[15] origin:064-gtp-channel-conf 03_399 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CFOK_CFG[16] origin:064-gtp-channel-conf 02_400 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CFOK_CFG[17] origin:064-gtp-channel-conf 03_400 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CFOK_CFG[18] origin:064-gtp-channel-conf 02_401 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CFOK_CFG[19] origin:064-gtp-channel-conf 03_401 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CFOK_CFG[20] origin:064-gtp-channel-conf 02_402 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CFOK_CFG[21] origin:064-gtp-channel-conf 03_402 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CFOK_CFG[22] origin:064-gtp-channel-conf 02_403 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CFOK_CFG[23] origin:064-gtp-channel-conf 03_403 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CFOK_CFG[24] origin:064-gtp-channel-conf 02_404 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CFOK_CFG[25] origin:064-gtp-channel-conf 03_404 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CFOK_CFG[26] origin:064-gtp-channel-conf 02_405 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CFOK_CFG[27] origin:064-gtp-channel-conf 03_405 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CFOK_CFG[28] origin:064-gtp-channel-conf 02_406 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CFOK_CFG[29] origin:064-gtp-channel-conf 03_406 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CFOK_CFG[30] origin:064-gtp-channel-conf 02_407 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CFOK_CFG[31] origin:064-gtp-channel-conf 03_407 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CFOK_CFG[32] origin:064-gtp-channel-conf 02_408 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CFOK_CFG[33] origin:064-gtp-channel-conf 03_408 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CFOK_CFG[34] origin:064-gtp-channel-conf 02_409 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CFOK_CFG[35] origin:064-gtp-channel-conf 03_409 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CFOK_CFG[36] origin:064-gtp-channel-conf 02_410 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CFOK_CFG[37] origin:064-gtp-channel-conf 03_410 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CFOK_CFG[38] origin:064-gtp-channel-conf 02_411 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CFOK_CFG[39] origin:064-gtp-channel-conf 03_411 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CFOK_CFG[40] origin:064-gtp-channel-conf 02_412 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CFOK_CFG[41] origin:064-gtp-channel-conf 03_412 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CFOK_CFG[42] origin:064-gtp-channel-conf 02_413 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CFOK_CFG2[0] origin:064-gtp-channel-conf 02_459 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CFOK_CFG2[1] origin:064-gtp-channel-conf 03_459 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CFOK_CFG2[2] origin:064-gtp-channel-conf 02_460 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CFOK_CFG2[3] origin:064-gtp-channel-conf 03_460 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CFOK_CFG2[4] origin:064-gtp-channel-conf 02_461 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CFOK_CFG2[5] origin:064-gtp-channel-conf 03_461 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CFOK_CFG2[6] origin:064-gtp-channel-conf 02_462 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CFOK_CFG3[0] origin:064-gtp-channel-conf 02_416 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CFOK_CFG3[1] origin:064-gtp-channel-conf 03_416 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CFOK_CFG3[2] origin:064-gtp-channel-conf 02_417 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CFOK_CFG3[3] origin:064-gtp-channel-conf 03_417 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CFOK_CFG3[4] origin:064-gtp-channel-conf 02_418 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CFOK_CFG3[5] origin:064-gtp-channel-conf 03_418 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CFOK_CFG3[6] origin:064-gtp-channel-conf 02_419 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CFOK_CFG4[0] origin:064-gtp-channel-conf 03_438 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CFOK_CFG5[0] origin:064-gtp-channel-conf 02_429 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CFOK_CFG5[1] origin:064-gtp-channel-conf 03_429 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CFOK_CFG6[0] origin:064-gtp-channel-conf 03_436 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CFOK_CFG6[1] origin:064-gtp-channel-conf 02_437 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CFOK_CFG6[2] origin:064-gtp-channel-conf 03_437 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CFOK_CFG6[3] origin:064-gtp-channel-conf 02_438 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_KEEP_ALIGN origin:064-gtp-channel-conf 01_631 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_MAX_SKEW[0] origin:064-gtp-channel-conf 00_670 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_MAX_SKEW[1] origin:064-gtp-channel-conf 01_670 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_MAX_SKEW[2] origin:064-gtp-channel-conf 00_671 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_MAX_SKEW[3] origin:064-gtp-channel-conf 01_671 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_1[0] origin:064-gtp-channel-conf 00_608 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_1[1] origin:064-gtp-channel-conf 01_608 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_1[2] origin:064-gtp-channel-conf 00_609 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_1[3] origin:064-gtp-channel-conf 01_609 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_1[4] origin:064-gtp-channel-conf 00_610 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_1[5] origin:064-gtp-channel-conf 01_610 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_1[6] origin:064-gtp-channel-conf 00_611 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_1[7] origin:064-gtp-channel-conf 01_611 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_1[8] origin:064-gtp-channel-conf 00_612 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_1[9] origin:064-gtp-channel-conf 01_612 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_2[0] origin:064-gtp-channel-conf 00_616 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_2[1] origin:064-gtp-channel-conf 01_616 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_2[2] origin:064-gtp-channel-conf 00_617 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_2[3] origin:064-gtp-channel-conf 01_617 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_2[4] origin:064-gtp-channel-conf 00_618 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_2[5] origin:064-gtp-channel-conf 01_618 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_2[6] origin:064-gtp-channel-conf 00_619 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_2[7] origin:064-gtp-channel-conf 01_619 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_2[8] origin:064-gtp-channel-conf 00_620 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_2[9] origin:064-gtp-channel-conf 01_620 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_3[0] origin:064-gtp-channel-conf 00_624 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_3[1] origin:064-gtp-channel-conf 01_624 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_3[2] origin:064-gtp-channel-conf 00_625 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_3[3] origin:064-gtp-channel-conf 01_625 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_3[4] origin:064-gtp-channel-conf 00_626 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_3[5] origin:064-gtp-channel-conf 01_626 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_3[6] origin:064-gtp-channel-conf 00_627 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_3[7] origin:064-gtp-channel-conf 01_627 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_3[8] origin:064-gtp-channel-conf 00_628 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_3[9] origin:064-gtp-channel-conf 01_628 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_4[0] origin:064-gtp-channel-conf 00_632 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_4[1] origin:064-gtp-channel-conf 01_632 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_4[2] origin:064-gtp-channel-conf 00_633 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_4[3] origin:064-gtp-channel-conf 01_633 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_4[4] origin:064-gtp-channel-conf 00_634 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_4[5] origin:064-gtp-channel-conf 01_634 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_4[6] origin:064-gtp-channel-conf 00_635 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_4[7] origin:064-gtp-channel-conf 01_635 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_4[8] origin:064-gtp-channel-conf 00_636 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_4[9] origin:064-gtp-channel-conf 01_636 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_ENABLE[0] origin:064-gtp-channel-conf 00_614 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_ENABLE[1] origin:064-gtp-channel-conf 01_614 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_ENABLE[2] origin:064-gtp-channel-conf 00_615 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_ENABLE[3] origin:064-gtp-channel-conf 01_615 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_1[0] origin:064-gtp-channel-conf 00_640 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_1[1] origin:064-gtp-channel-conf 01_640 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_1[2] origin:064-gtp-channel-conf 00_641 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_1[3] origin:064-gtp-channel-conf 01_641 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_1[4] origin:064-gtp-channel-conf 00_642 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_1[5] origin:064-gtp-channel-conf 01_642 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_1[6] origin:064-gtp-channel-conf 00_643 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_1[7] origin:064-gtp-channel-conf 01_643 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_1[8] origin:064-gtp-channel-conf 00_644 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_1[9] origin:064-gtp-channel-conf 01_644 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_2[0] origin:064-gtp-channel-conf 00_648 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_2[1] origin:064-gtp-channel-conf 01_648 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_2[2] origin:064-gtp-channel-conf 00_649 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_2[3] origin:064-gtp-channel-conf 01_649 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_2[4] origin:064-gtp-channel-conf 00_650 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_2[5] origin:064-gtp-channel-conf 01_650 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_2[6] origin:064-gtp-channel-conf 00_651 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_2[7] origin:064-gtp-channel-conf 01_651 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_2[8] origin:064-gtp-channel-conf 00_652 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_2[9] origin:064-gtp-channel-conf 01_652 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_3[0] origin:064-gtp-channel-conf 00_656 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_3[1] origin:064-gtp-channel-conf 01_656 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_3[2] origin:064-gtp-channel-conf 00_657 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_3[3] origin:064-gtp-channel-conf 01_657 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_3[4] origin:064-gtp-channel-conf 00_658 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_3[5] origin:064-gtp-channel-conf 01_658 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_3[6] origin:064-gtp-channel-conf 00_659 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_3[7] origin:064-gtp-channel-conf 01_659 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_3[8] origin:064-gtp-channel-conf 00_660 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_3[9] origin:064-gtp-channel-conf 01_660 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_4[0] origin:064-gtp-channel-conf 00_664 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_4[1] origin:064-gtp-channel-conf 01_664 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_4[2] origin:064-gtp-channel-conf 00_665 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_4[3] origin:064-gtp-channel-conf 01_665 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_4[4] origin:064-gtp-channel-conf 00_666 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_4[5] origin:064-gtp-channel-conf 01_666 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_4[6] origin:064-gtp-channel-conf 00_667 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_4[7] origin:064-gtp-channel-conf 01_667 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_4[8] origin:064-gtp-channel-conf 00_668 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_4[9] origin:064-gtp-channel-conf 01_668 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_ENABLE[0] origin:064-gtp-channel-conf 00_646 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_ENABLE[1] origin:064-gtp-channel-conf 01_646 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_ENABLE[2] origin:064-gtp-channel-conf 00_647 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_ENABLE[3] origin:064-gtp-channel-conf 01_647 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_USE origin:064-gtp-channel-conf 01_645 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_LEN[0] origin:064-gtp-channel-conf 00_623 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_LEN[1] origin:064-gtp-channel-conf 01_623 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COMMON_SWING[0] origin:064-gtp-channel-conf 03_311 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_KEEP_IDLE origin:064-gtp-channel-conf 00_591 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_MAX_LAT[0] origin:064-gtp-channel-conf 00_557 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_MAX_LAT[1] origin:064-gtp-channel-conf 01_557 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_MAX_LAT[2] origin:064-gtp-channel-conf 00_558 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_MAX_LAT[3] origin:064-gtp-channel-conf 01_558 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_MAX_LAT[4] origin:064-gtp-channel-conf 00_559 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_MAX_LAT[5] origin:064-gtp-channel-conf 01_559 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_MIN_LAT[0] origin:064-gtp-channel-conf 00_565 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_MIN_LAT[1] origin:064-gtp-channel-conf 01_565 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_MIN_LAT[2] origin:064-gtp-channel-conf 00_566 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_MIN_LAT[3] origin:064-gtp-channel-conf 01_566 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_MIN_LAT[4] origin:064-gtp-channel-conf 00_567 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_MIN_LAT[5] origin:064-gtp-channel-conf 01_567 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_PRECEDENCE origin:064-gtp-channel-conf 00_590 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_REPEAT_WAIT[0] origin:064-gtp-channel-conf 00_573 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_REPEAT_WAIT[1] origin:064-gtp-channel-conf 01_573 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_REPEAT_WAIT[2] origin:064-gtp-channel-conf 00_574 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_REPEAT_WAIT[3] origin:064-gtp-channel-conf 01_574 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_REPEAT_WAIT[4] origin:064-gtp-channel-conf 00_575 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_1[0] origin:064-gtp-channel-conf 00_544 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_1[1] origin:064-gtp-channel-conf 01_544 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_1[2] origin:064-gtp-channel-conf 00_545 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_1[3] origin:064-gtp-channel-conf 01_545 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_1[4] origin:064-gtp-channel-conf 00_546 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_1[5] origin:064-gtp-channel-conf 01_546 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_1[6] origin:064-gtp-channel-conf 00_547 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_1[7] origin:064-gtp-channel-conf 01_547 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_1[8] origin:064-gtp-channel-conf 00_548 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_1[9] origin:064-gtp-channel-conf 01_548 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_2[0] origin:064-gtp-channel-conf 00_552 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_2[1] origin:064-gtp-channel-conf 01_552 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_2[2] origin:064-gtp-channel-conf 00_553 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_2[3] origin:064-gtp-channel-conf 01_553 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_2[4] origin:064-gtp-channel-conf 00_554 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_2[5] origin:064-gtp-channel-conf 01_554 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_2[6] origin:064-gtp-channel-conf 00_555 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_2[7] origin:064-gtp-channel-conf 01_555 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_2[8] origin:064-gtp-channel-conf 00_556 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_2[9] origin:064-gtp-channel-conf 01_556 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_3[0] origin:064-gtp-channel-conf 00_560 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_3[1] origin:064-gtp-channel-conf 01_560 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_3[2] origin:064-gtp-channel-conf 00_561 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_3[3] origin:064-gtp-channel-conf 01_561 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_3[4] origin:064-gtp-channel-conf 00_562 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_3[5] origin:064-gtp-channel-conf 01_562 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_3[6] origin:064-gtp-channel-conf 00_563 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_3[7] origin:064-gtp-channel-conf 01_563 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_3[8] origin:064-gtp-channel-conf 00_564 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_3[9] origin:064-gtp-channel-conf 01_564 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_4[0] origin:064-gtp-channel-conf 00_568 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_4[1] origin:064-gtp-channel-conf 01_568 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_4[2] origin:064-gtp-channel-conf 00_569 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_4[3] origin:064-gtp-channel-conf 01_569 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_4[4] origin:064-gtp-channel-conf 00_570 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_4[5] origin:064-gtp-channel-conf 01_570 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_4[6] origin:064-gtp-channel-conf 00_571 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_4[7] origin:064-gtp-channel-conf 01_571 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_4[8] origin:064-gtp-channel-conf 00_572 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_4[9] origin:064-gtp-channel-conf 01_572 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_ENABLE[0] origin:064-gtp-channel-conf 00_549 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_ENABLE[1] origin:064-gtp-channel-conf 01_549 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_ENABLE[2] origin:064-gtp-channel-conf 00_550 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_ENABLE[3] origin:064-gtp-channel-conf 01_550 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_1[0] origin:064-gtp-channel-conf 00_576 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_1[1] origin:064-gtp-channel-conf 01_576 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_1[2] origin:064-gtp-channel-conf 00_577 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_1[3] origin:064-gtp-channel-conf 01_577 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_1[4] origin:064-gtp-channel-conf 00_578 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_1[5] origin:064-gtp-channel-conf 01_578 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_1[6] origin:064-gtp-channel-conf 00_579 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_1[7] origin:064-gtp-channel-conf 01_579 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_1[8] origin:064-gtp-channel-conf 00_580 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_1[9] origin:064-gtp-channel-conf 01_580 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_2[0] origin:064-gtp-channel-conf 00_584 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_2[1] origin:064-gtp-channel-conf 01_584 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_2[2] origin:064-gtp-channel-conf 00_585 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_2[3] origin:064-gtp-channel-conf 01_585 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_2[4] origin:064-gtp-channel-conf 00_586 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_2[5] origin:064-gtp-channel-conf 01_586 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_2[6] origin:064-gtp-channel-conf 00_587 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_2[7] origin:064-gtp-channel-conf 01_587 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_2[8] origin:064-gtp-channel-conf 00_588 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_2[9] origin:064-gtp-channel-conf 01_588 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_3[0] origin:064-gtp-channel-conf 00_592 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_3[1] origin:064-gtp-channel-conf 01_592 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_3[2] origin:064-gtp-channel-conf 00_593 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_3[3] origin:064-gtp-channel-conf 01_593 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_3[4] origin:064-gtp-channel-conf 00_594 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_3[5] origin:064-gtp-channel-conf 01_594 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_3[6] origin:064-gtp-channel-conf 00_595 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_3[7] origin:064-gtp-channel-conf 01_595 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_3[8] origin:064-gtp-channel-conf 00_596 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_3[9] origin:064-gtp-channel-conf 01_596 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_4[0] origin:064-gtp-channel-conf 00_600 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_4[1] origin:064-gtp-channel-conf 01_600 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_4[2] origin:064-gtp-channel-conf 00_601 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_4[3] origin:064-gtp-channel-conf 01_601 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_4[4] origin:064-gtp-channel-conf 00_602 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_4[5] origin:064-gtp-channel-conf 01_602 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_4[6] origin:064-gtp-channel-conf 00_603 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_4[7] origin:064-gtp-channel-conf 01_603 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_4[8] origin:064-gtp-channel-conf 00_604 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_4[9] origin:064-gtp-channel-conf 01_604 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_ENABLE[0] origin:064-gtp-channel-conf 00_581 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_ENABLE[1] origin:064-gtp-channel-conf 01_581 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_ENABLE[2] origin:064-gtp-channel-conf 00_582 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_ENABLE[3] origin:064-gtp-channel-conf 01_582 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_USE origin:064-gtp-channel-conf 00_583 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_LEN[0] origin:064-gtp-channel-conf 00_589 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_COR_SEQ_LEN[1] origin:064-gtp-channel-conf 01_589 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.CLK_CORRECT_USE origin:064-gtp-channel-conf 00_551 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.DEC_MCOMMA_DETECT origin:064-gtp-channel-conf 01_494 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.DEC_PCOMMA_DETECT origin:064-gtp-channel-conf 00_495 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.DEC_VALID_COMMA_ONLY origin:064-gtp-channel-conf 00_494 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.DMONITOR_CFG[0] origin:064-gtp-channel-conf 02_368 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.DMONITOR_CFG[1] origin:064-gtp-channel-conf 03_368 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.DMONITOR_CFG[2] origin:064-gtp-channel-conf 02_369 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.DMONITOR_CFG[3] origin:064-gtp-channel-conf 03_369 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.DMONITOR_CFG[4] origin:064-gtp-channel-conf 02_370 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.DMONITOR_CFG[5] origin:064-gtp-channel-conf 03_370 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.DMONITOR_CFG[6] origin:064-gtp-channel-conf 02_371 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.DMONITOR_CFG[7] origin:064-gtp-channel-conf 03_371 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.DMONITOR_CFG[8] origin:064-gtp-channel-conf 02_372 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.DMONITOR_CFG[9] origin:064-gtp-channel-conf 03_372 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.DMONITOR_CFG[10] origin:064-gtp-channel-conf 02_373 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.DMONITOR_CFG[11] origin:064-gtp-channel-conf 03_373 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.DMONITOR_CFG[12] origin:064-gtp-channel-conf 02_374 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.DMONITOR_CFG[13] origin:064-gtp-channel-conf 03_374 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.DMONITOR_CFG[14] origin:064-gtp-channel-conf 02_375 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.DMONITOR_CFG[15] origin:064-gtp-channel-conf 03_375 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.DMONITOR_CFG[16] origin:064-gtp-channel-conf 02_376 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.DMONITOR_CFG[17] origin:064-gtp-channel-conf 03_376 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.DMONITOR_CFG[18] origin:064-gtp-channel-conf 02_377 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.DMONITOR_CFG[19] origin:064-gtp-channel-conf 03_377 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.DMONITOR_CFG[20] origin:064-gtp-channel-conf 02_378 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.DMONITOR_CFG[21] origin:064-gtp-channel-conf 03_378 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.DMONITOR_CFG[22] origin:064-gtp-channel-conf 02_379 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.DMONITOR_CFG[23] origin:064-gtp-channel-conf 03_379 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_CLK_PHASE_SEL[0] origin:064-gtp-channel-conf 03_463 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_CONTROL[0] origin:064-gtp-channel-conf 00_488 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_CONTROL[1] origin:064-gtp-channel-conf 01_488 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_CONTROL[2] origin:064-gtp-channel-conf 00_489 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_CONTROL[3] origin:064-gtp-channel-conf 01_489 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_CONTROL[4] origin:064-gtp-channel-conf 00_490 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_CONTROL[5] origin:064-gtp-channel-conf 01_490 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_ERRDET_EN origin:064-gtp-channel-conf 01_492 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_EYE_SCAN_EN origin:064-gtp-channel-conf 00_492 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_HORZ_OFFSET[0] origin:064-gtp-channel-conf 00_480 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_HORZ_OFFSET[1] origin:064-gtp-channel-conf 01_480 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_HORZ_OFFSET[2] origin:064-gtp-channel-conf 00_481 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_HORZ_OFFSET[3] origin:064-gtp-channel-conf 01_481 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_HORZ_OFFSET[4] origin:064-gtp-channel-conf 00_482 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_HORZ_OFFSET[5] origin:064-gtp-channel-conf 01_482 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_HORZ_OFFSET[6] origin:064-gtp-channel-conf 00_483 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_HORZ_OFFSET[7] origin:064-gtp-channel-conf 01_483 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_HORZ_OFFSET[8] origin:064-gtp-channel-conf 00_484 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_HORZ_OFFSET[9] origin:064-gtp-channel-conf 01_484 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_HORZ_OFFSET[10] origin:064-gtp-channel-conf 00_485 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_HORZ_OFFSET[11] origin:064-gtp-channel-conf 01_485 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_PMA_CFG[0] origin:064-gtp-channel-conf 02_624 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_PMA_CFG[1] origin:064-gtp-channel-conf 03_624 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_PMA_CFG[2] origin:064-gtp-channel-conf 02_625 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_PMA_CFG[3] origin:064-gtp-channel-conf 03_625 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_PMA_CFG[4] origin:064-gtp-channel-conf 02_626 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_PMA_CFG[5] origin:064-gtp-channel-conf 03_626 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_PMA_CFG[6] origin:064-gtp-channel-conf 02_627 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_PMA_CFG[7] origin:064-gtp-channel-conf 03_627 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_PMA_CFG[8] origin:064-gtp-channel-conf 02_628 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_PMA_CFG[9] origin:064-gtp-channel-conf 03_628 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_PRESCALE[0] origin:064-gtp-channel-conf 01_477 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_PRESCALE[1] origin:064-gtp-channel-conf 00_478 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_PRESCALE[2] origin:064-gtp-channel-conf 01_478 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_PRESCALE[3] origin:064-gtp-channel-conf 00_479 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_PRESCALE[4] origin:064-gtp-channel-conf 01_479 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[0] origin:064-gtp-channel-conf 00_392 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[1] origin:064-gtp-channel-conf 01_392 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[2] origin:064-gtp-channel-conf 00_393 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[3] origin:064-gtp-channel-conf 01_393 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[4] origin:064-gtp-channel-conf 00_394 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[5] origin:064-gtp-channel-conf 01_394 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[6] origin:064-gtp-channel-conf 00_395 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[7] origin:064-gtp-channel-conf 01_395 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[8] origin:064-gtp-channel-conf 00_396 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[9] origin:064-gtp-channel-conf 01_396 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[10] origin:064-gtp-channel-conf 00_397 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[11] origin:064-gtp-channel-conf 01_397 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[12] origin:064-gtp-channel-conf 00_398 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[13] origin:064-gtp-channel-conf 01_398 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[14] origin:064-gtp-channel-conf 00_399 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[15] origin:064-gtp-channel-conf 01_399 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[16] origin:064-gtp-channel-conf 00_400 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[17] origin:064-gtp-channel-conf 01_400 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[18] origin:064-gtp-channel-conf 00_401 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[19] origin:064-gtp-channel-conf 01_401 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[20] origin:064-gtp-channel-conf 00_402 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[21] origin:064-gtp-channel-conf 01_402 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[22] origin:064-gtp-channel-conf 00_403 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[23] origin:064-gtp-channel-conf 01_403 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[24] origin:064-gtp-channel-conf 00_404 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[25] origin:064-gtp-channel-conf 01_404 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[26] origin:064-gtp-channel-conf 00_405 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[27] origin:064-gtp-channel-conf 01_405 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[28] origin:064-gtp-channel-conf 00_406 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[29] origin:064-gtp-channel-conf 01_406 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[30] origin:064-gtp-channel-conf 00_407 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[31] origin:064-gtp-channel-conf 01_407 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[32] origin:064-gtp-channel-conf 00_408 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[33] origin:064-gtp-channel-conf 01_408 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[34] origin:064-gtp-channel-conf 00_409 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[35] origin:064-gtp-channel-conf 01_409 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[36] origin:064-gtp-channel-conf 00_410 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[37] origin:064-gtp-channel-conf 01_410 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[38] origin:064-gtp-channel-conf 00_411 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[39] origin:064-gtp-channel-conf 01_411 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[40] origin:064-gtp-channel-conf 00_412 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[41] origin:064-gtp-channel-conf 01_412 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[42] origin:064-gtp-channel-conf 00_413 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[43] origin:064-gtp-channel-conf 01_413 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[44] origin:064-gtp-channel-conf 00_414 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[45] origin:064-gtp-channel-conf 01_414 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[46] origin:064-gtp-channel-conf 00_415 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[47] origin:064-gtp-channel-conf 01_415 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[48] origin:064-gtp-channel-conf 00_416 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[49] origin:064-gtp-channel-conf 01_416 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[50] origin:064-gtp-channel-conf 00_417 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[51] origin:064-gtp-channel-conf 01_417 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[52] origin:064-gtp-channel-conf 00_418 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[53] origin:064-gtp-channel-conf 01_418 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[54] origin:064-gtp-channel-conf 00_419 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[55] origin:064-gtp-channel-conf 01_419 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[56] origin:064-gtp-channel-conf 00_420 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[57] origin:064-gtp-channel-conf 01_420 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[58] origin:064-gtp-channel-conf 00_421 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[59] origin:064-gtp-channel-conf 01_421 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[60] origin:064-gtp-channel-conf 00_422 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[61] origin:064-gtp-channel-conf 01_422 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[62] origin:064-gtp-channel-conf 00_423 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[63] origin:064-gtp-channel-conf 01_423 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[64] origin:064-gtp-channel-conf 00_424 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[65] origin:064-gtp-channel-conf 01_424 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[66] origin:064-gtp-channel-conf 00_425 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[67] origin:064-gtp-channel-conf 01_425 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[68] origin:064-gtp-channel-conf 00_426 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[69] origin:064-gtp-channel-conf 01_426 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[70] origin:064-gtp-channel-conf 00_427 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[71] origin:064-gtp-channel-conf 01_427 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[72] origin:064-gtp-channel-conf 00_428 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[73] origin:064-gtp-channel-conf 01_428 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[74] origin:064-gtp-channel-conf 00_429 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[75] origin:064-gtp-channel-conf 01_429 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[76] origin:064-gtp-channel-conf 00_430 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[77] origin:064-gtp-channel-conf 01_430 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[78] origin:064-gtp-channel-conf 00_431 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUAL_MASK[79] origin:064-gtp-channel-conf 01_431 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[0] origin:064-gtp-channel-conf 00_352 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[1] origin:064-gtp-channel-conf 01_352 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[2] origin:064-gtp-channel-conf 00_353 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[3] origin:064-gtp-channel-conf 01_353 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[4] origin:064-gtp-channel-conf 00_354 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[5] origin:064-gtp-channel-conf 01_354 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[6] origin:064-gtp-channel-conf 00_355 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[7] origin:064-gtp-channel-conf 01_355 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[8] origin:064-gtp-channel-conf 00_356 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[9] origin:064-gtp-channel-conf 01_356 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[10] origin:064-gtp-channel-conf 00_357 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[11] origin:064-gtp-channel-conf 01_357 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[12] origin:064-gtp-channel-conf 00_358 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[13] origin:064-gtp-channel-conf 01_358 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[14] origin:064-gtp-channel-conf 00_359 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[15] origin:064-gtp-channel-conf 01_359 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[16] origin:064-gtp-channel-conf 00_360 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[17] origin:064-gtp-channel-conf 01_360 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[18] origin:064-gtp-channel-conf 00_361 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[19] origin:064-gtp-channel-conf 01_361 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[20] origin:064-gtp-channel-conf 00_362 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[21] origin:064-gtp-channel-conf 01_362 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[22] origin:064-gtp-channel-conf 00_363 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[23] origin:064-gtp-channel-conf 01_363 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[24] origin:064-gtp-channel-conf 00_364 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[25] origin:064-gtp-channel-conf 01_364 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[26] origin:064-gtp-channel-conf 00_365 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[27] origin:064-gtp-channel-conf 01_365 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[28] origin:064-gtp-channel-conf 00_366 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[29] origin:064-gtp-channel-conf 01_366 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[30] origin:064-gtp-channel-conf 00_367 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[31] origin:064-gtp-channel-conf 01_367 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[32] origin:064-gtp-channel-conf 00_368 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[33] origin:064-gtp-channel-conf 01_368 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[34] origin:064-gtp-channel-conf 00_369 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[35] origin:064-gtp-channel-conf 01_369 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[36] origin:064-gtp-channel-conf 00_370 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[37] origin:064-gtp-channel-conf 01_370 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[38] origin:064-gtp-channel-conf 00_371 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[39] origin:064-gtp-channel-conf 01_371 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[40] origin:064-gtp-channel-conf 00_372 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[41] origin:064-gtp-channel-conf 01_372 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[42] origin:064-gtp-channel-conf 00_373 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[43] origin:064-gtp-channel-conf 01_373 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[44] origin:064-gtp-channel-conf 00_374 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[45] origin:064-gtp-channel-conf 01_374 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[46] origin:064-gtp-channel-conf 00_375 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[47] origin:064-gtp-channel-conf 01_375 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[48] origin:064-gtp-channel-conf 00_376 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[49] origin:064-gtp-channel-conf 01_376 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[50] origin:064-gtp-channel-conf 00_377 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[51] origin:064-gtp-channel-conf 01_377 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[52] origin:064-gtp-channel-conf 00_378 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[53] origin:064-gtp-channel-conf 01_378 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[54] origin:064-gtp-channel-conf 00_379 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[55] origin:064-gtp-channel-conf 01_379 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[56] origin:064-gtp-channel-conf 00_380 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[57] origin:064-gtp-channel-conf 01_380 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[58] origin:064-gtp-channel-conf 00_381 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[59] origin:064-gtp-channel-conf 01_381 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[60] origin:064-gtp-channel-conf 00_382 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[61] origin:064-gtp-channel-conf 01_382 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[62] origin:064-gtp-channel-conf 00_383 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[63] origin:064-gtp-channel-conf 01_383 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[64] origin:064-gtp-channel-conf 00_384 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[65] origin:064-gtp-channel-conf 01_384 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[66] origin:064-gtp-channel-conf 00_385 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[67] origin:064-gtp-channel-conf 01_385 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[68] origin:064-gtp-channel-conf 00_386 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[69] origin:064-gtp-channel-conf 01_386 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[70] origin:064-gtp-channel-conf 00_387 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[71] origin:064-gtp-channel-conf 01_387 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[72] origin:064-gtp-channel-conf 00_388 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[73] origin:064-gtp-channel-conf 01_388 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[74] origin:064-gtp-channel-conf 00_389 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[75] origin:064-gtp-channel-conf 01_389 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[76] origin:064-gtp-channel-conf 00_390 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[77] origin:064-gtp-channel-conf 01_390 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[78] origin:064-gtp-channel-conf 00_391 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_QUALIFIER[79] origin:064-gtp-channel-conf 01_391 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[0] origin:064-gtp-channel-conf 00_432 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[1] origin:064-gtp-channel-conf 01_432 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[2] origin:064-gtp-channel-conf 00_433 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[3] origin:064-gtp-channel-conf 01_433 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[4] origin:064-gtp-channel-conf 00_434 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[5] origin:064-gtp-channel-conf 01_434 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[6] origin:064-gtp-channel-conf 00_435 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[7] origin:064-gtp-channel-conf 01_435 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[8] origin:064-gtp-channel-conf 00_436 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[9] origin:064-gtp-channel-conf 01_436 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[10] origin:064-gtp-channel-conf 00_437 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[11] origin:064-gtp-channel-conf 01_437 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[12] origin:064-gtp-channel-conf 00_438 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[13] origin:064-gtp-channel-conf 01_438 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[14] origin:064-gtp-channel-conf 00_439 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[15] origin:064-gtp-channel-conf 01_439 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[16] origin:064-gtp-channel-conf 00_440 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[17] origin:064-gtp-channel-conf 01_440 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[18] origin:064-gtp-channel-conf 00_441 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[19] origin:064-gtp-channel-conf 01_441 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[20] origin:064-gtp-channel-conf 00_442 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[21] origin:064-gtp-channel-conf 01_442 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[22] origin:064-gtp-channel-conf 00_443 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[23] origin:064-gtp-channel-conf 01_443 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[24] origin:064-gtp-channel-conf 00_444 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[25] origin:064-gtp-channel-conf 01_444 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[26] origin:064-gtp-channel-conf 00_445 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[27] origin:064-gtp-channel-conf 01_445 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[28] origin:064-gtp-channel-conf 00_446 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[29] origin:064-gtp-channel-conf 01_446 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[30] origin:064-gtp-channel-conf 00_447 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[31] origin:064-gtp-channel-conf 01_447 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[32] origin:064-gtp-channel-conf 00_448 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[33] origin:064-gtp-channel-conf 01_448 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[34] origin:064-gtp-channel-conf 00_449 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[35] origin:064-gtp-channel-conf 01_449 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[36] origin:064-gtp-channel-conf 00_450 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[37] origin:064-gtp-channel-conf 01_450 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[38] origin:064-gtp-channel-conf 00_451 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[39] origin:064-gtp-channel-conf 01_451 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[40] origin:064-gtp-channel-conf 00_452 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[41] origin:064-gtp-channel-conf 01_452 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[42] origin:064-gtp-channel-conf 00_453 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[43] origin:064-gtp-channel-conf 01_453 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[44] origin:064-gtp-channel-conf 00_454 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[45] origin:064-gtp-channel-conf 01_454 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[46] origin:064-gtp-channel-conf 00_455 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[47] origin:064-gtp-channel-conf 01_455 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[48] origin:064-gtp-channel-conf 00_456 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[49] origin:064-gtp-channel-conf 01_456 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[50] origin:064-gtp-channel-conf 00_457 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[51] origin:064-gtp-channel-conf 01_457 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[52] origin:064-gtp-channel-conf 00_458 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[53] origin:064-gtp-channel-conf 01_458 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[54] origin:064-gtp-channel-conf 00_459 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[55] origin:064-gtp-channel-conf 01_459 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[56] origin:064-gtp-channel-conf 00_460 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[57] origin:064-gtp-channel-conf 01_460 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[58] origin:064-gtp-channel-conf 00_461 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[59] origin:064-gtp-channel-conf 01_461 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[60] origin:064-gtp-channel-conf 00_462 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[61] origin:064-gtp-channel-conf 01_462 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[62] origin:064-gtp-channel-conf 00_463 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[63] origin:064-gtp-channel-conf 01_463 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[64] origin:064-gtp-channel-conf 00_464 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[65] origin:064-gtp-channel-conf 01_464 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[66] origin:064-gtp-channel-conf 00_465 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[67] origin:064-gtp-channel-conf 01_465 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[68] origin:064-gtp-channel-conf 00_466 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[69] origin:064-gtp-channel-conf 01_466 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[70] origin:064-gtp-channel-conf 00_467 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[71] origin:064-gtp-channel-conf 01_467 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[72] origin:064-gtp-channel-conf 00_468 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[73] origin:064-gtp-channel-conf 01_468 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[74] origin:064-gtp-channel-conf 00_469 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[75] origin:064-gtp-channel-conf 01_469 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[76] origin:064-gtp-channel-conf 00_470 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[77] origin:064-gtp-channel-conf 01_470 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[78] origin:064-gtp-channel-conf 00_471 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_SDATA_MASK[79] origin:064-gtp-channel-conf 01_471 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_VERT_OFFSET[0] origin:064-gtp-channel-conf 00_472 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_VERT_OFFSET[1] origin:064-gtp-channel-conf 01_472 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_VERT_OFFSET[2] origin:064-gtp-channel-conf 00_473 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_VERT_OFFSET[3] origin:064-gtp-channel-conf 01_473 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_VERT_OFFSET[4] origin:064-gtp-channel-conf 00_474 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_VERT_OFFSET[5] origin:064-gtp-channel-conf 01_474 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_VERT_OFFSET[6] origin:064-gtp-channel-conf 00_475 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_VERT_OFFSET[7] origin:064-gtp-channel-conf 01_475 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ES_VERT_OFFSET[8] origin:064-gtp-channel-conf 00_476 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.FTS_DESKEW_SEQ_ENABLE[0] origin:064-gtp-channel-conf 00_662 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.FTS_DESKEW_SEQ_ENABLE[1] origin:064-gtp-channel-conf 01_662 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.FTS_DESKEW_SEQ_ENABLE[2] origin:064-gtp-channel-conf 00_663 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.FTS_DESKEW_SEQ_ENABLE[3] origin:064-gtp-channel-conf 01_663 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.FTS_LANE_DESKEW_CFG[0] origin:064-gtp-channel-conf 00_654 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.FTS_LANE_DESKEW_CFG[1] origin:064-gtp-channel-conf 01_654 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.FTS_LANE_DESKEW_CFG[2] origin:064-gtp-channel-conf 00_655 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.FTS_LANE_DESKEW_CFG[3] origin:064-gtp-channel-conf 01_655 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.FTS_LANE_DESKEW_EN origin:064-gtp-channel-conf 01_653 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.GEARBOX_MODE[0] origin:064-gtp-channel-conf 00_224 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.GEARBOX_MODE[1] origin:064-gtp-channel-conf 01_224 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.GEARBOX_MODE[2] origin:064-gtp-channel-conf 00_225 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.IN_USE origin:064-gtp-channel-conf 00_00 00_01 00_47 00_52 00_53 00_65 01_01 01_47 02_129 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.LOOPBACK_CFG[0] origin:064-gtp-channel-conf 02_20 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.OUTREFCLK_SEL_INV[0] origin:064-gtp-channel-conf 00_149 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.OUTREFCLK_SEL_INV[1] origin:064-gtp-channel-conf 01_149 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PCS_PCIE_EN origin:064-gtp-channel-conf 00_216 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[0] origin:064-gtp-channel-conf 02_184 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[1] origin:064-gtp-channel-conf 03_184 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[2] origin:064-gtp-channel-conf 02_185 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[3] origin:064-gtp-channel-conf 03_185 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[4] origin:064-gtp-channel-conf 02_186 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[5] origin:064-gtp-channel-conf 03_186 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[6] origin:064-gtp-channel-conf 02_187 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[7] origin:064-gtp-channel-conf 03_187 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[8] origin:064-gtp-channel-conf 02_188 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[9] origin:064-gtp-channel-conf 03_188 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[10] origin:064-gtp-channel-conf 02_189 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[11] origin:064-gtp-channel-conf 03_189 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[12] origin:064-gtp-channel-conf 02_190 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[13] origin:064-gtp-channel-conf 03_190 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[14] origin:064-gtp-channel-conf 02_191 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[15] origin:064-gtp-channel-conf 03_191 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[16] origin:064-gtp-channel-conf 02_192 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[17] origin:064-gtp-channel-conf 03_192 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[18] origin:064-gtp-channel-conf 02_193 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[19] origin:064-gtp-channel-conf 03_193 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[20] origin:064-gtp-channel-conf 02_194 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[21] origin:064-gtp-channel-conf 03_194 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[22] origin:064-gtp-channel-conf 02_195 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[23] origin:064-gtp-channel-conf 03_195 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[24] origin:064-gtp-channel-conf 02_196 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[25] origin:064-gtp-channel-conf 03_196 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[26] origin:064-gtp-channel-conf 02_197 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[27] origin:064-gtp-channel-conf 03_197 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[28] origin:064-gtp-channel-conf 02_198 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[29] origin:064-gtp-channel-conf 03_198 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[30] origin:064-gtp-channel-conf 02_199 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[31] origin:064-gtp-channel-conf 03_199 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[32] origin:064-gtp-channel-conf 02_200 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[33] origin:064-gtp-channel-conf 03_200 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[34] origin:064-gtp-channel-conf 02_201 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[35] origin:064-gtp-channel-conf 03_201 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[36] origin:064-gtp-channel-conf 02_202 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[37] origin:064-gtp-channel-conf 03_202 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[38] origin:064-gtp-channel-conf 02_203 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[39] origin:064-gtp-channel-conf 03_203 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[40] origin:064-gtp-channel-conf 02_204 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[41] origin:064-gtp-channel-conf 03_204 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[42] origin:064-gtp-channel-conf 02_205 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[43] origin:064-gtp-channel-conf 03_205 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[44] origin:064-gtp-channel-conf 02_206 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[45] origin:064-gtp-channel-conf 03_206 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[46] origin:064-gtp-channel-conf 02_207 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[47] origin:064-gtp-channel-conf 03_207 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PD_TRANS_TIME_FROM_P2[0] origin:064-gtp-channel-conf 01_216 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PD_TRANS_TIME_FROM_P2[1] origin:064-gtp-channel-conf 00_217 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PD_TRANS_TIME_FROM_P2[2] origin:064-gtp-channel-conf 01_217 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PD_TRANS_TIME_FROM_P2[3] origin:064-gtp-channel-conf 00_218 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PD_TRANS_TIME_FROM_P2[4] origin:064-gtp-channel-conf 01_218 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PD_TRANS_TIME_FROM_P2[5] origin:064-gtp-channel-conf 00_219 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PD_TRANS_TIME_FROM_P2[6] origin:064-gtp-channel-conf 01_219 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PD_TRANS_TIME_FROM_P2[7] origin:064-gtp-channel-conf 00_220 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PD_TRANS_TIME_FROM_P2[8] origin:064-gtp-channel-conf 01_220 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PD_TRANS_TIME_FROM_P2[9] origin:064-gtp-channel-conf 00_221 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PD_TRANS_TIME_FROM_P2[10] origin:064-gtp-channel-conf 01_221 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PD_TRANS_TIME_FROM_P2[11] origin:064-gtp-channel-conf 00_222 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PD_TRANS_TIME_NONE_P2[0] origin:064-gtp-channel-conf 00_208 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PD_TRANS_TIME_NONE_P2[1] origin:064-gtp-channel-conf 01_208 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PD_TRANS_TIME_NONE_P2[2] origin:064-gtp-channel-conf 00_209 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PD_TRANS_TIME_NONE_P2[3] origin:064-gtp-channel-conf 01_209 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PD_TRANS_TIME_NONE_P2[4] origin:064-gtp-channel-conf 00_210 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PD_TRANS_TIME_NONE_P2[5] origin:064-gtp-channel-conf 01_210 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PD_TRANS_TIME_NONE_P2[6] origin:064-gtp-channel-conf 00_211 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PD_TRANS_TIME_NONE_P2[7] origin:064-gtp-channel-conf 01_211 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PD_TRANS_TIME_TO_P2[0] origin:064-gtp-channel-conf 00_212 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PD_TRANS_TIME_TO_P2[1] origin:064-gtp-channel-conf 01_212 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PD_TRANS_TIME_TO_P2[2] origin:064-gtp-channel-conf 00_213 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PD_TRANS_TIME_TO_P2[3] origin:064-gtp-channel-conf 01_213 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PD_TRANS_TIME_TO_P2[4] origin:064-gtp-channel-conf 00_214 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PD_TRANS_TIME_TO_P2[5] origin:064-gtp-channel-conf 01_214 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PD_TRANS_TIME_TO_P2[6] origin:064-gtp-channel-conf 00_215 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PD_TRANS_TIME_TO_P2[7] origin:064-gtp-channel-conf 01_215 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PMA_LOOPBACK_CFG[0] origin:064-gtp-channel-conf 01_207 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PMA_RSV[0] origin:064-gtp-channel-conf 02_520 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PMA_RSV[1] origin:064-gtp-channel-conf 03_520 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PMA_RSV[2] origin:064-gtp-channel-conf 02_521 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PMA_RSV[3] origin:064-gtp-channel-conf 03_521 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PMA_RSV[4] origin:064-gtp-channel-conf 02_522 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PMA_RSV[5] origin:064-gtp-channel-conf 03_522 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PMA_RSV[6] origin:064-gtp-channel-conf 02_523 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PMA_RSV[7] origin:064-gtp-channel-conf 03_523 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PMA_RSV[8] origin:064-gtp-channel-conf 02_524 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PMA_RSV[9] origin:064-gtp-channel-conf 03_524 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PMA_RSV[10] origin:064-gtp-channel-conf 02_525 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PMA_RSV[11] origin:064-gtp-channel-conf 03_525 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PMA_RSV[12] origin:064-gtp-channel-conf 02_526 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PMA_RSV[13] origin:064-gtp-channel-conf 03_526 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PMA_RSV[14] origin:064-gtp-channel-conf 02_527 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PMA_RSV[15] origin:064-gtp-channel-conf 03_527 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PMA_RSV[16] origin:064-gtp-channel-conf 02_528 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PMA_RSV[17] origin:064-gtp-channel-conf 03_528 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PMA_RSV[18] origin:064-gtp-channel-conf 02_529 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PMA_RSV[19] origin:064-gtp-channel-conf 03_529 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PMA_RSV[20] origin:064-gtp-channel-conf 02_530 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PMA_RSV[21] origin:064-gtp-channel-conf 03_530 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PMA_RSV[22] origin:064-gtp-channel-conf 02_531 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PMA_RSV[23] origin:064-gtp-channel-conf 03_531 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PMA_RSV[24] origin:064-gtp-channel-conf 02_532 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PMA_RSV[25] origin:064-gtp-channel-conf 03_532 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PMA_RSV[26] origin:064-gtp-channel-conf 02_533 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PMA_RSV[27] origin:064-gtp-channel-conf 03_533 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PMA_RSV[28] origin:064-gtp-channel-conf 02_534 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PMA_RSV[29] origin:064-gtp-channel-conf 03_534 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PMA_RSV[30] origin:064-gtp-channel-conf 02_535 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PMA_RSV[31] origin:064-gtp-channel-conf 03_535 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PMA_RSV2[0] origin:064-gtp-channel-conf 02_336 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PMA_RSV2[1] origin:064-gtp-channel-conf 03_336 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PMA_RSV2[2] origin:064-gtp-channel-conf 02_337 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PMA_RSV2[3] origin:064-gtp-channel-conf 03_337 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PMA_RSV2[4] origin:064-gtp-channel-conf 02_338 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PMA_RSV2[5] origin:064-gtp-channel-conf 03_338 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PMA_RSV2[6] origin:064-gtp-channel-conf 02_339 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PMA_RSV2[7] origin:064-gtp-channel-conf 03_339 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PMA_RSV2[8] origin:064-gtp-channel-conf 02_340 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PMA_RSV2[9] origin:064-gtp-channel-conf 03_340 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PMA_RSV2[10] origin:064-gtp-channel-conf 02_341 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PMA_RSV2[11] origin:064-gtp-channel-conf 03_341 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PMA_RSV2[12] origin:064-gtp-channel-conf 02_342 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PMA_RSV2[13] origin:064-gtp-channel-conf 03_342 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PMA_RSV2[14] origin:064-gtp-channel-conf 02_343 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PMA_RSV2[15] origin:064-gtp-channel-conf 03_343 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PMA_RSV2[16] origin:064-gtp-channel-conf 02_344 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PMA_RSV2[17] origin:064-gtp-channel-conf 03_344 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PMA_RSV2[18] origin:064-gtp-channel-conf 02_345 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PMA_RSV2[19] origin:064-gtp-channel-conf 03_345 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PMA_RSV2[20] origin:064-gtp-channel-conf 02_346 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PMA_RSV2[21] origin:064-gtp-channel-conf 03_346 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PMA_RSV2[22] origin:064-gtp-channel-conf 02_347 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PMA_RSV2[23] origin:064-gtp-channel-conf 03_347 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PMA_RSV2[24] origin:064-gtp-channel-conf 02_348 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PMA_RSV2[25] origin:064-gtp-channel-conf 03_348 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PMA_RSV2[26] origin:064-gtp-channel-conf 02_349 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PMA_RSV2[27] origin:064-gtp-channel-conf 03_349 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PMA_RSV2[28] origin:064-gtp-channel-conf 02_350 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PMA_RSV2[29] origin:064-gtp-channel-conf 03_350 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PMA_RSV2[30] origin:064-gtp-channel-conf 02_351 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PMA_RSV2[31] origin:064-gtp-channel-conf 03_351 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PMA_RSV3[0] origin:064-gtp-channel-conf 02_288 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PMA_RSV3[1] origin:064-gtp-channel-conf 03_288 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PMA_RSV4[0] origin:064-gtp-channel-conf 02_156 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PMA_RSV4[1] origin:064-gtp-channel-conf 03_156 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PMA_RSV4[2] origin:064-gtp-channel-conf 02_157 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PMA_RSV4[3] origin:064-gtp-channel-conf 03_157 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PMA_RSV5[0] origin:064-gtp-channel-conf 03_159 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PMA_RSV6[0] origin:064-gtp-channel-conf 02_303 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.PMA_RSV7[0] origin:064-gtp-channel-conf 03_303 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_BIAS_CFG[0] origin:064-gtp-channel-conf 02_112 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_BIAS_CFG[1] origin:064-gtp-channel-conf 03_112 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_BIAS_CFG[2] origin:064-gtp-channel-conf 02_113 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_BIAS_CFG[3] origin:064-gtp-channel-conf 03_113 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_BIAS_CFG[4] origin:064-gtp-channel-conf 02_114 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_BIAS_CFG[5] origin:064-gtp-channel-conf 03_114 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_BIAS_CFG[6] origin:064-gtp-channel-conf 02_115 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_BIAS_CFG[7] origin:064-gtp-channel-conf 03_115 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_BIAS_CFG[8] origin:064-gtp-channel-conf 02_116 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_BIAS_CFG[9] origin:064-gtp-channel-conf 03_116 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_BIAS_CFG[10] origin:064-gtp-channel-conf 02_117 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_BIAS_CFG[11] origin:064-gtp-channel-conf 03_117 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_BIAS_CFG[12] origin:064-gtp-channel-conf 02_118 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_BIAS_CFG[13] origin:064-gtp-channel-conf 03_118 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_BIAS_CFG[14] origin:064-gtp-channel-conf 02_119 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_BIAS_CFG[15] origin:064-gtp-channel-conf 03_119 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_BUFFER_CFG[0] origin:064-gtp-channel-conf 02_536 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_BUFFER_CFG[1] origin:064-gtp-channel-conf 03_536 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_BUFFER_CFG[2] origin:064-gtp-channel-conf 02_537 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_BUFFER_CFG[3] origin:064-gtp-channel-conf 03_537 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_BUFFER_CFG[4] origin:064-gtp-channel-conf 02_538 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_BUFFER_CFG[5] origin:064-gtp-channel-conf 03_538 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_CLKMUX_EN[0] origin:064-gtp-channel-conf 02_128 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_CM_SEL[0] origin:064-gtp-channel-conf 00_138 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_CM_SEL[1] origin:064-gtp-channel-conf 01_138 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_CM_TRIM[0] origin:064-gtp-channel-conf 02_304 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_CM_TRIM[1] origin:064-gtp-channel-conf 03_304 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_CM_TRIM[2] origin:064-gtp-channel-conf 02_305 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_CM_TRIM[3] origin:064-gtp-channel-conf 03_305 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_DATA_WIDTH[0] origin:064-gtp-channel-conf 01_141 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_DATA_WIDTH[1] origin:064-gtp-channel-conf 00_142 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_DATA_WIDTH[2] origin:064-gtp-channel-conf 01_142 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_DDI_SEL[0] origin:064-gtp-channel-conf 00_696 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_DDI_SEL[1] origin:064-gtp-channel-conf 01_696 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_DDI_SEL[2] origin:064-gtp-channel-conf 00_697 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_DDI_SEL[3] origin:064-gtp-channel-conf 01_697 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_DDI_SEL[4] origin:064-gtp-channel-conf 00_698 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_DDI_SEL[5] origin:064-gtp-channel-conf 01_698 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_DEBUG_CFG[0] origin:064-gtp-channel-conf 02_616 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_DEBUG_CFG[1] origin:064-gtp-channel-conf 03_616 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_DEBUG_CFG[2] origin:064-gtp-channel-conf 02_617 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_DEBUG_CFG[3] origin:064-gtp-channel-conf 03_617 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_DEBUG_CFG[4] origin:064-gtp-channel-conf 02_618 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_DEBUG_CFG[5] origin:064-gtp-channel-conf 03_618 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_DEBUG_CFG[6] origin:064-gtp-channel-conf 02_619 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_DEBUG_CFG[7] origin:064-gtp-channel-conf 03_619 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_DEBUG_CFG[8] origin:064-gtp-channel-conf 02_620 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_DEBUG_CFG[9] origin:064-gtp-channel-conf 03_620 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_DEBUG_CFG[10] origin:064-gtp-channel-conf 02_621 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_DEBUG_CFG[11] origin:064-gtp-channel-conf 03_621 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_DEBUG_CFG[12] origin:064-gtp-channel-conf 02_622 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_DEBUG_CFG[13] origin:064-gtp-channel-conf 03_622 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_DEFER_RESET_BUF_EN origin:064-gtp-channel-conf 02_552 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_DISPERR_SEQ_MATCH origin:064-gtp-channel-conf 01_495 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_OS_CFG[0] origin:064-gtp-channel-conf 00_288 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_OS_CFG[1] origin:064-gtp-channel-conf 01_288 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_OS_CFG[2] origin:064-gtp-channel-conf 00_289 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_OS_CFG[3] origin:064-gtp-channel-conf 01_289 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_OS_CFG[4] origin:064-gtp-channel-conf 00_290 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_OS_CFG[5] origin:064-gtp-channel-conf 01_290 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_OS_CFG[6] origin:064-gtp-channel-conf 00_291 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_OS_CFG[7] origin:064-gtp-channel-conf 01_291 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_OS_CFG[8] origin:064-gtp-channel-conf 00_292 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_OS_CFG[9] origin:064-gtp-channel-conf 01_292 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_OS_CFG[10] origin:064-gtp-channel-conf 00_293 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_OS_CFG[11] origin:064-gtp-channel-conf 01_293 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_OS_CFG[12] origin:064-gtp-channel-conf 00_294 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_SIG_VALID_DLY[0] origin:064-gtp-channel-conf 00_524 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_SIG_VALID_DLY[1] origin:064-gtp-channel-conf 01_524 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_SIG_VALID_DLY[2] origin:064-gtp-channel-conf 00_525 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_SIG_VALID_DLY[3] origin:064-gtp-channel-conf 01_525 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_SIG_VALID_DLY[4] origin:064-gtp-channel-conf 00_526 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_XCLK_SEL.RXUSR origin:064-gtp-channel-conf 00_143 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_CLK25_DIV[0] origin:064-gtp-channel-conf 00_139 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_CLK25_DIV[1] origin:064-gtp-channel-conf 01_139 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_CLK25_DIV[2] origin:064-gtp-channel-conf 00_140 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_CLK25_DIV[3] origin:064-gtp-channel-conf 01_140 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RX_CLK25_DIV[4] origin:064-gtp-channel-conf 00_141 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXBUF_ADDR_MODE.FAST origin:064-gtp-channel-conf 03_555 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXBUF_EIDLE_HI_CNT[0] origin:064-gtp-channel-conf 02_558 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXBUF_EIDLE_HI_CNT[1] origin:064-gtp-channel-conf 03_558 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXBUF_EIDLE_HI_CNT[2] origin:064-gtp-channel-conf 02_559 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXBUF_EIDLE_HI_CNT[3] origin:064-gtp-channel-conf 03_559 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXBUF_EIDLE_LO_CNT[0] origin:064-gtp-channel-conf 02_556 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXBUF_EIDLE_LO_CNT[1] origin:064-gtp-channel-conf 03_556 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXBUF_EIDLE_LO_CNT[2] origin:064-gtp-channel-conf 02_557 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXBUF_EIDLE_LO_CNT[3] origin:064-gtp-channel-conf 03_557 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXBUF_EN origin:064-gtp-channel-conf 02_11 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXBUF_RESET_ON_CB_CHANGE origin:064-gtp-channel-conf 02_560 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXBUF_RESET_ON_COMMAALIGN origin:064-gtp-channel-conf 02_561 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXBUF_RESET_ON_EIDLE origin:064-gtp-channel-conf 02_547 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXBUF_RESET_ON_RATE_CHANGE origin:064-gtp-channel-conf 03_560 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXBUF_THRESH_OVFLW[0] origin:064-gtp-channel-conf 03_552 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXBUF_THRESH_OVFLW[1] origin:064-gtp-channel-conf 02_553 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXBUF_THRESH_OVFLW[2] origin:064-gtp-channel-conf 03_553 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXBUF_THRESH_OVFLW[3] origin:064-gtp-channel-conf 02_554 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXBUF_THRESH_OVFLW[4] origin:064-gtp-channel-conf 03_554 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXBUF_THRESH_OVFLW[5] origin:064-gtp-channel-conf 02_555 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXBUF_THRESH_OVRD origin:064-gtp-channel-conf 02_548 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXBUF_THRESH_UNDFLW[0] origin:064-gtp-channel-conf 02_544 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXBUF_THRESH_UNDFLW[1] origin:064-gtp-channel-conf 03_544 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXBUF_THRESH_UNDFLW[2] origin:064-gtp-channel-conf 02_545 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXBUF_THRESH_UNDFLW[3] origin:064-gtp-channel-conf 03_545 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXBUF_THRESH_UNDFLW[4] origin:064-gtp-channel-conf 02_546 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXBUF_THRESH_UNDFLW[5] origin:064-gtp-channel-conf 03_546 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXBUFRESET_TIME[0] origin:064-gtp-channel-conf 01_101 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXBUFRESET_TIME[1] origin:064-gtp-channel-conf 00_102 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXBUFRESET_TIME[2] origin:064-gtp-channel-conf 01_102 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXBUFRESET_TIME[3] origin:064-gtp-channel-conf 00_103 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXBUFRESET_TIME[4] origin:064-gtp-channel-conf 01_103 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[0] origin:064-gtp-channel-conf 02_640 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[1] origin:064-gtp-channel-conf 03_640 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[2] origin:064-gtp-channel-conf 02_641 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[3] origin:064-gtp-channel-conf 03_641 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[4] origin:064-gtp-channel-conf 02_642 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[5] origin:064-gtp-channel-conf 03_642 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[6] origin:064-gtp-channel-conf 02_643 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[7] origin:064-gtp-channel-conf 03_643 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[8] origin:064-gtp-channel-conf 02_644 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[9] origin:064-gtp-channel-conf 03_644 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[10] origin:064-gtp-channel-conf 02_645 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[11] origin:064-gtp-channel-conf 03_645 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[12] origin:064-gtp-channel-conf 02_646 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[13] origin:064-gtp-channel-conf 03_646 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[14] origin:064-gtp-channel-conf 02_647 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[15] origin:064-gtp-channel-conf 03_647 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[16] origin:064-gtp-channel-conf 02_648 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[17] origin:064-gtp-channel-conf 03_648 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[18] origin:064-gtp-channel-conf 02_649 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[19] origin:064-gtp-channel-conf 03_649 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[20] origin:064-gtp-channel-conf 02_650 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[21] origin:064-gtp-channel-conf 03_650 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[22] origin:064-gtp-channel-conf 02_651 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[23] origin:064-gtp-channel-conf 03_651 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[24] origin:064-gtp-channel-conf 02_652 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[25] origin:064-gtp-channel-conf 03_652 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[26] origin:064-gtp-channel-conf 02_653 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[27] origin:064-gtp-channel-conf 03_653 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[28] origin:064-gtp-channel-conf 02_654 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[29] origin:064-gtp-channel-conf 03_654 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[30] origin:064-gtp-channel-conf 02_655 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[31] origin:064-gtp-channel-conf 03_655 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[32] origin:064-gtp-channel-conf 02_656 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[33] origin:064-gtp-channel-conf 03_656 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[34] origin:064-gtp-channel-conf 02_657 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[35] origin:064-gtp-channel-conf 03_657 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[36] origin:064-gtp-channel-conf 02_658 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[37] origin:064-gtp-channel-conf 03_658 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[38] origin:064-gtp-channel-conf 02_659 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[39] origin:064-gtp-channel-conf 03_659 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[40] origin:064-gtp-channel-conf 02_660 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[41] origin:064-gtp-channel-conf 03_660 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[42] origin:064-gtp-channel-conf 02_661 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[43] origin:064-gtp-channel-conf 03_661 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[44] origin:064-gtp-channel-conf 02_662 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[45] origin:064-gtp-channel-conf 03_662 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[46] origin:064-gtp-channel-conf 02_663 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[47] origin:064-gtp-channel-conf 03_663 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[48] origin:064-gtp-channel-conf 02_664 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[49] origin:064-gtp-channel-conf 03_664 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[50] origin:064-gtp-channel-conf 02_665 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[51] origin:064-gtp-channel-conf 03_665 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[52] origin:064-gtp-channel-conf 02_666 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[53] origin:064-gtp-channel-conf 03_666 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[54] origin:064-gtp-channel-conf 02_667 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[55] origin:064-gtp-channel-conf 03_667 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[56] origin:064-gtp-channel-conf 02_668 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[57] origin:064-gtp-channel-conf 03_668 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[58] origin:064-gtp-channel-conf 02_669 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[59] origin:064-gtp-channel-conf 03_669 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[60] origin:064-gtp-channel-conf 02_670 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[61] origin:064-gtp-channel-conf 03_670 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[62] origin:064-gtp-channel-conf 02_671 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[63] origin:064-gtp-channel-conf 03_671 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[64] origin:064-gtp-channel-conf 02_672 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[65] origin:064-gtp-channel-conf 03_672 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[66] origin:064-gtp-channel-conf 02_673 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[67] origin:064-gtp-channel-conf 03_673 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[68] origin:064-gtp-channel-conf 02_674 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[69] origin:064-gtp-channel-conf 03_674 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[70] origin:064-gtp-channel-conf 02_675 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[71] origin:064-gtp-channel-conf 03_675 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[72] origin:064-gtp-channel-conf 02_676 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[73] origin:064-gtp-channel-conf 03_676 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[74] origin:064-gtp-channel-conf 02_677 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[75] origin:064-gtp-channel-conf 03_677 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[76] origin:064-gtp-channel-conf 02_678 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[77] origin:064-gtp-channel-conf 03_678 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[78] origin:064-gtp-channel-conf 02_679 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[79] origin:064-gtp-channel-conf 03_679 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[80] origin:064-gtp-channel-conf 02_680 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[81] origin:064-gtp-channel-conf 03_680 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_CFG[82] origin:064-gtp-channel-conf 02_681 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_FR_RESET_ON_EIDLE[0] origin:064-gtp-channel-conf 02_638 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_HOLD_DURING_EIDLE[0] origin:064-gtp-channel-conf 03_637 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_LOCK_CFG[0] origin:064-gtp-channel-conf 02_632 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_LOCK_CFG[1] origin:064-gtp-channel-conf 03_632 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_LOCK_CFG[2] origin:064-gtp-channel-conf 02_633 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_LOCK_CFG[3] origin:064-gtp-channel-conf 03_633 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_LOCK_CFG[4] origin:064-gtp-channel-conf 02_634 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_LOCK_CFG[5] origin:064-gtp-channel-conf 03_634 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDR_PH_RESET_ON_EIDLE[0] origin:064-gtp-channel-conf 03_638 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDRFREQRESET_TIME[0] origin:064-gtp-channel-conf 01_106 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDRFREQRESET_TIME[1] origin:064-gtp-channel-conf 00_107 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDRFREQRESET_TIME[2] origin:064-gtp-channel-conf 01_107 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDRFREQRESET_TIME[3] origin:064-gtp-channel-conf 00_108 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDRFREQRESET_TIME[4] origin:064-gtp-channel-conf 01_108 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDRPHRESET_TIME[0] origin:064-gtp-channel-conf 00_109 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDRPHRESET_TIME[1] origin:064-gtp-channel-conf 01_109 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDRPHRESET_TIME[2] origin:064-gtp-channel-conf 00_110 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDRPHRESET_TIME[3] origin:064-gtp-channel-conf 01_110 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXCDRPHRESET_TIME[4] origin:064-gtp-channel-conf 00_111 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXDLY_CFG[0] origin:064-gtp-channel-conf 00_680 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXDLY_CFG[1] origin:064-gtp-channel-conf 01_680 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXDLY_CFG[2] origin:064-gtp-channel-conf 00_681 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXDLY_CFG[3] origin:064-gtp-channel-conf 01_681 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXDLY_CFG[4] origin:064-gtp-channel-conf 00_682 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXDLY_CFG[5] origin:064-gtp-channel-conf 01_682 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXDLY_CFG[6] origin:064-gtp-channel-conf 00_683 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXDLY_CFG[7] origin:064-gtp-channel-conf 01_683 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXDLY_CFG[8] origin:064-gtp-channel-conf 00_684 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXDLY_CFG[9] origin:064-gtp-channel-conf 01_684 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXDLY_CFG[10] origin:064-gtp-channel-conf 00_685 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXDLY_CFG[11] origin:064-gtp-channel-conf 01_685 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXDLY_CFG[12] origin:064-gtp-channel-conf 00_686 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXDLY_CFG[13] origin:064-gtp-channel-conf 01_686 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXDLY_CFG[14] origin:064-gtp-channel-conf 00_687 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXDLY_CFG[15] origin:064-gtp-channel-conf 01_687 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXDLY_LCFG[0] origin:064-gtp-channel-conf 02_576 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXDLY_LCFG[1] origin:064-gtp-channel-conf 03_576 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXDLY_LCFG[2] origin:064-gtp-channel-conf 02_577 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXDLY_LCFG[3] origin:064-gtp-channel-conf 03_577 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXDLY_LCFG[4] origin:064-gtp-channel-conf 02_578 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXDLY_LCFG[5] origin:064-gtp-channel-conf 03_578 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXDLY_LCFG[6] origin:064-gtp-channel-conf 02_579 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXDLY_LCFG[7] origin:064-gtp-channel-conf 03_579 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXDLY_LCFG[8] origin:064-gtp-channel-conf 02_580 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXDLY_TAP_CFG[0] origin:064-gtp-channel-conf 00_672 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXDLY_TAP_CFG[1] origin:064-gtp-channel-conf 01_672 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXDLY_TAP_CFG[2] origin:064-gtp-channel-conf 00_673 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXDLY_TAP_CFG[3] origin:064-gtp-channel-conf 01_673 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXDLY_TAP_CFG[4] origin:064-gtp-channel-conf 00_674 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXDLY_TAP_CFG[5] origin:064-gtp-channel-conf 01_674 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXDLY_TAP_CFG[6] origin:064-gtp-channel-conf 00_675 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXDLY_TAP_CFG[7] origin:064-gtp-channel-conf 01_675 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXDLY_TAP_CFG[8] origin:064-gtp-channel-conf 00_676 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXDLY_TAP_CFG[9] origin:064-gtp-channel-conf 01_676 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXDLY_TAP_CFG[10] origin:064-gtp-channel-conf 00_677 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXDLY_TAP_CFG[11] origin:064-gtp-channel-conf 01_677 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXDLY_TAP_CFG[12] origin:064-gtp-channel-conf 00_678 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXDLY_TAP_CFG[13] origin:064-gtp-channel-conf 01_678 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXDLY_TAP_CFG[14] origin:064-gtp-channel-conf 00_679 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXDLY_TAP_CFG[15] origin:064-gtp-channel-conf 01_679 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXGEARBOX_EN origin:064-gtp-channel-conf 01_607 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXISCANRESET_TIME[0] origin:064-gtp-channel-conf 01_123 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXISCANRESET_TIME[1] origin:064-gtp-channel-conf 00_124 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXISCANRESET_TIME[2] origin:064-gtp-channel-conf 01_124 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXISCANRESET_TIME[3] origin:064-gtp-channel-conf 00_125 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXISCANRESET_TIME[4] origin:064-gtp-channel-conf 01_125 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPM_BIAS_STARTUP_DISABLE[0] origin:064-gtp-channel-conf 03_391 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPM_CFG[0] origin:064-gtp-channel-conf 02_328 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPM_CFG[1] origin:064-gtp-channel-conf 03_328 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPM_CFG[2] origin:064-gtp-channel-conf 02_329 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPM_CFG[3] origin:064-gtp-channel-conf 03_329 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPM_CM_CFG[0] origin:064-gtp-channel-conf 02_430 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPM_GC_CFG[0] origin:064-gtp-channel-conf 02_432 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPM_GC_CFG[1] origin:064-gtp-channel-conf 03_432 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPM_GC_CFG[2] origin:064-gtp-channel-conf 02_433 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPM_GC_CFG[3] origin:064-gtp-channel-conf 03_433 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPM_GC_CFG[4] origin:064-gtp-channel-conf 02_434 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPM_GC_CFG[5] origin:064-gtp-channel-conf 03_434 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPM_GC_CFG[6] origin:064-gtp-channel-conf 02_435 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPM_GC_CFG[7] origin:064-gtp-channel-conf 03_435 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPM_GC_CFG[8] origin:064-gtp-channel-conf 02_436 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPM_GC_CFG2[0] origin:064-gtp-channel-conf 03_442 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPM_GC_CFG2[1] origin:064-gtp-channel-conf 02_443 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPM_GC_CFG2[2] origin:064-gtp-channel-conf 03_443 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPM_HF_CFG[0] origin:064-gtp-channel-conf 00_336 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPM_HF_CFG[1] origin:064-gtp-channel-conf 01_336 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPM_HF_CFG[2] origin:064-gtp-channel-conf 00_337 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPM_HF_CFG[3] origin:064-gtp-channel-conf 01_337 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPM_HF_CFG[4] origin:064-gtp-channel-conf 00_338 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPM_HF_CFG[5] origin:064-gtp-channel-conf 01_338 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPM_HF_CFG[6] origin:064-gtp-channel-conf 00_339 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPM_HF_CFG[7] origin:064-gtp-channel-conf 01_339 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPM_HF_CFG[8] origin:064-gtp-channel-conf 00_340 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPM_HF_CFG[9] origin:064-gtp-channel-conf 01_340 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPM_HF_CFG[10] origin:064-gtp-channel-conf 00_341 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPM_HF_CFG[11] origin:064-gtp-channel-conf 01_341 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPM_HF_CFG[12] origin:064-gtp-channel-conf 00_342 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPM_HF_CFG[13] origin:064-gtp-channel-conf 01_342 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPM_HF_CFG2[0] origin:064-gtp-channel-conf 02_424 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPM_HF_CFG2[1] origin:064-gtp-channel-conf 03_424 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPM_HF_CFG2[2] origin:064-gtp-channel-conf 02_425 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPM_HF_CFG2[3] origin:064-gtp-channel-conf 03_425 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPM_HF_CFG2[4] origin:064-gtp-channel-conf 02_426 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPM_HF_CFG3[0] origin:064-gtp-channel-conf 03_389 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPM_HF_CFG3[1] origin:064-gtp-channel-conf 02_390 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPM_HF_CFG3[2] origin:064-gtp-channel-conf 03_390 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPM_HF_CFG3[3] origin:064-gtp-channel-conf 02_391 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPM_HOLD_DURING_EIDLE[0] origin:064-gtp-channel-conf 00_247 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPM_INCM_CFG[0] origin:064-gtp-channel-conf 02_439 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPM_IPCM_CFG[0] origin:064-gtp-channel-conf 03_439 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPM_LF_CFG[0] origin:064-gtp-channel-conf 00_344 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPM_LF_CFG[1] origin:064-gtp-channel-conf 01_344 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPM_LF_CFG[2] origin:064-gtp-channel-conf 00_345 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPM_LF_CFG[3] origin:064-gtp-channel-conf 01_345 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPM_LF_CFG[4] origin:064-gtp-channel-conf 00_346 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPM_LF_CFG[5] origin:064-gtp-channel-conf 01_346 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPM_LF_CFG[6] origin:064-gtp-channel-conf 00_347 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPM_LF_CFG[7] origin:064-gtp-channel-conf 01_347 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPM_LF_CFG[8] origin:064-gtp-channel-conf 00_348 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPM_LF_CFG[9] origin:064-gtp-channel-conf 01_348 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPM_LF_CFG[10] origin:064-gtp-channel-conf 00_349 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPM_LF_CFG[11] origin:064-gtp-channel-conf 01_349 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPM_LF_CFG[12] origin:064-gtp-channel-conf 00_350 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPM_LF_CFG[13] origin:064-gtp-channel-conf 01_350 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPM_LF_CFG[14] origin:064-gtp-channel-conf 00_351 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPM_LF_CFG[15] origin:064-gtp-channel-conf 01_351 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPM_LF_CFG[16] origin:064-gtp-channel-conf 00_343 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPM_LF_CFG[17] origin:064-gtp-channel-conf 01_343 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPM_LF_CFG2[0] origin:064-gtp-channel-conf 03_426 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPM_LF_CFG2[1] origin:064-gtp-channel-conf 02_427 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPM_LF_CFG2[2] origin:064-gtp-channel-conf 03_427 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPM_LF_CFG2[3] origin:064-gtp-channel-conf 02_428 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPM_LF_CFG2[4] origin:064-gtp-channel-conf 03_428 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPM_OSINT_CFG[0] origin:064-gtp-channel-conf 02_440 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPM_OSINT_CFG[1] origin:064-gtp-channel-conf 03_440 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPM_OSINT_CFG[2] origin:064-gtp-channel-conf 02_441 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPM_CFG1[0] origin:064-gtp-channel-conf 02_330 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPMRESET_TIME[0] origin:064-gtp-channel-conf 00_112 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPMRESET_TIME[1] origin:064-gtp-channel-conf 01_112 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPMRESET_TIME[2] origin:064-gtp-channel-conf 00_113 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPMRESET_TIME[3] origin:064-gtp-channel-conf 01_113 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPMRESET_TIME[4] origin:064-gtp-channel-conf 00_114 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPMRESET_TIME[5] origin:064-gtp-channel-conf 01_114 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXLPMRESET_TIME[6] origin:064-gtp-channel-conf 00_115 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXOOB_CFG[0] origin:064-gtp-channel-conf 00_144 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXOOB_CFG[1] origin:064-gtp-channel-conf 01_144 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXOOB_CFG[2] origin:064-gtp-channel-conf 00_145 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXOOB_CFG[3] origin:064-gtp-channel-conf 01_145 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXOOB_CFG[4] origin:064-gtp-channel-conf 00_146 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXOOB_CFG[5] origin:064-gtp-channel-conf 01_146 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXOOB_CFG[6] origin:064-gtp-channel-conf 00_147 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXOOB_CLK_CFG.FABRIC origin:064-gtp-channel-conf 03_129 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXOSCALRESET_TIME[0] origin:064-gtp-channel-conf 00_187 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXOSCALRESET_TIME[1] origin:064-gtp-channel-conf 01_187 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXOSCALRESET_TIME[2] origin:064-gtp-channel-conf 00_188 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXOSCALRESET_TIME[3] origin:064-gtp-channel-conf 01_188 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXOSCALRESET_TIME[4] origin:064-gtp-channel-conf 00_189 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXOSCALRESET_TIMEOUT[0] origin:064-gtp-channel-conf 01_189 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXOSCALRESET_TIMEOUT[1] origin:064-gtp-channel-conf 00_190 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXOSCALRESET_TIMEOUT[2] origin:064-gtp-channel-conf 01_190 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXOSCALRESET_TIMEOUT[3] origin:064-gtp-channel-conf 00_191 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXOSCALRESET_TIMEOUT[4] origin:064-gtp-channel-conf 01_191 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXOUT_DIV[0] origin:064-gtp-channel-conf 02_384 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXOUT_DIV[1] origin:064-gtp-channel-conf 03_384 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXPCSRESET_TIME[0] origin:064-gtp-channel-conf 01_115 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXPCSRESET_TIME[1] origin:064-gtp-channel-conf 00_116 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXPCSRESET_TIME[2] origin:064-gtp-channel-conf 01_116 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXPCSRESET_TIME[3] origin:064-gtp-channel-conf 00_117 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXPCSRESET_TIME[4] origin:064-gtp-channel-conf 01_117 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXPH_CFG[0] origin:064-gtp-channel-conf 02_584 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXPH_CFG[1] origin:064-gtp-channel-conf 03_584 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXPH_CFG[2] origin:064-gtp-channel-conf 02_585 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXPH_CFG[3] origin:064-gtp-channel-conf 03_585 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXPH_CFG[4] origin:064-gtp-channel-conf 02_586 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXPH_CFG[5] origin:064-gtp-channel-conf 03_586 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXPH_CFG[6] origin:064-gtp-channel-conf 02_587 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXPH_CFG[7] origin:064-gtp-channel-conf 03_587 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXPH_CFG[8] origin:064-gtp-channel-conf 02_588 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXPH_CFG[9] origin:064-gtp-channel-conf 03_588 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXPH_CFG[10] origin:064-gtp-channel-conf 02_589 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXPH_CFG[11] origin:064-gtp-channel-conf 03_589 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXPH_CFG[12] origin:064-gtp-channel-conf 02_590 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXPH_CFG[13] origin:064-gtp-channel-conf 03_590 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXPH_CFG[14] origin:064-gtp-channel-conf 02_591 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXPH_CFG[15] origin:064-gtp-channel-conf 03_591 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXPH_CFG[16] origin:064-gtp-channel-conf 02_592 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXPH_CFG[17] origin:064-gtp-channel-conf 03_592 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXPH_CFG[18] origin:064-gtp-channel-conf 02_593 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXPH_CFG[19] origin:064-gtp-channel-conf 03_593 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXPH_CFG[20] origin:064-gtp-channel-conf 02_594 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXPH_CFG[21] origin:064-gtp-channel-conf 03_594 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXPH_CFG[22] origin:064-gtp-channel-conf 02_595 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXPH_CFG[23] origin:064-gtp-channel-conf 03_595 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXPH_MONITOR_SEL[0] origin:064-gtp-channel-conf 00_700 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXPH_MONITOR_SEL[1] origin:064-gtp-channel-conf 01_700 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXPH_MONITOR_SEL[2] origin:064-gtp-channel-conf 00_701 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXPH_MONITOR_SEL[3] origin:064-gtp-channel-conf 01_701 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXPH_MONITOR_SEL[4] origin:064-gtp-channel-conf 00_702 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXPHDLY_CFG[0] origin:064-gtp-channel-conf 02_600 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXPHDLY_CFG[1] origin:064-gtp-channel-conf 03_600 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXPHDLY_CFG[2] origin:064-gtp-channel-conf 02_601 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXPHDLY_CFG[3] origin:064-gtp-channel-conf 03_601 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXPHDLY_CFG[4] origin:064-gtp-channel-conf 02_602 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXPHDLY_CFG[5] origin:064-gtp-channel-conf 03_602 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXPHDLY_CFG[6] origin:064-gtp-channel-conf 02_603 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXPHDLY_CFG[7] origin:064-gtp-channel-conf 03_603 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXPHDLY_CFG[8] origin:064-gtp-channel-conf 02_604 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXPHDLY_CFG[9] origin:064-gtp-channel-conf 03_604 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXPHDLY_CFG[10] origin:064-gtp-channel-conf 02_605 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXPHDLY_CFG[11] origin:064-gtp-channel-conf 03_605 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXPHDLY_CFG[12] origin:064-gtp-channel-conf 02_606 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXPHDLY_CFG[13] origin:064-gtp-channel-conf 03_606 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXPHDLY_CFG[14] origin:064-gtp-channel-conf 02_607 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXPHDLY_CFG[15] origin:064-gtp-channel-conf 03_607 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXPHDLY_CFG[16] origin:064-gtp-channel-conf 02_608 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXPHDLY_CFG[17] origin:064-gtp-channel-conf 03_608 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXPHDLY_CFG[18] origin:064-gtp-channel-conf 02_609 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXPHDLY_CFG[19] origin:064-gtp-channel-conf 03_609 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXPHDLY_CFG[20] origin:064-gtp-channel-conf 02_610 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXPHDLY_CFG[21] origin:064-gtp-channel-conf 03_610 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXPHDLY_CFG[22] origin:064-gtp-channel-conf 02_611 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXPHDLY_CFG[23] origin:064-gtp-channel-conf 03_611 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXPI_CFG0[0] origin:064-gtp-channel-conf 03_430 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXPI_CFG0[1] origin:064-gtp-channel-conf 02_431 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXPI_CFG0[2] origin:064-gtp-channel-conf 03_431 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXPI_CFG1[0] origin:064-gtp-channel-conf 02_442 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXPI_CFG2[0] origin:064-gtp-channel-conf 03_441 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXPMARESET_TIME[0] origin:064-gtp-channel-conf 00_104 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXPMARESET_TIME[1] origin:064-gtp-channel-conf 01_104 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXPMARESET_TIME[2] origin:064-gtp-channel-conf 00_105 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXPMARESET_TIME[3] origin:064-gtp-channel-conf 01_105 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXPMARESET_TIME[4] origin:064-gtp-channel-conf 00_106 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXPRBS_ERR_LOOPBACK[0] origin:064-gtp-channel-conf 00_136 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXSLIDE_AUTO_WAIT[0] origin:064-gtp-channel-conf 00_520 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXSLIDE_AUTO_WAIT[1] origin:064-gtp-channel-conf 01_520 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXSLIDE_AUTO_WAIT[2] origin:064-gtp-channel-conf 00_521 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXSLIDE_AUTO_WAIT[3] origin:064-gtp-channel-conf 01_521 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXSLIDE_MODE.AUTO origin:064-gtp-channel-conf !01_519 00_519 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXSLIDE_MODE.PCS origin:064-gtp-channel-conf !00_519 01_519 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXSLIDE_MODE.PMA origin:064-gtp-channel-conf 00_519 01_519 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXSYNC_MULTILANE[0] origin:064-gtp-channel-conf 00_133 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXSYNC_OVRD[0] origin:064-gtp-channel-conf 01_135 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.RXSYNC_SKIP_DA[0] origin:064-gtp-channel-conf 01_134 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.SAS_MAX_COM[0] origin:064-gtp-channel-conf 00_171 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.SAS_MAX_COM[1] origin:064-gtp-channel-conf 01_171 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.SAS_MAX_COM[2] origin:064-gtp-channel-conf 00_172 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.SAS_MAX_COM[3] origin:064-gtp-channel-conf 01_172 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.SAS_MAX_COM[4] origin:064-gtp-channel-conf 00_173 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.SAS_MAX_COM[5] origin:064-gtp-channel-conf 01_173 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.SAS_MAX_COM[6] origin:064-gtp-channel-conf 00_174 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.SAS_MIN_COM[0] origin:064-gtp-channel-conf 01_156 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.SAS_MIN_COM[1] origin:064-gtp-channel-conf 00_157 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.SAS_MIN_COM[2] origin:064-gtp-channel-conf 01_157 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.SAS_MIN_COM[3] origin:064-gtp-channel-conf 00_158 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.SAS_MIN_COM[4] origin:064-gtp-channel-conf 01_158 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.SAS_MIN_COM[5] origin:064-gtp-channel-conf 00_159 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.SATA_BURST_SEQ_LEN[0] origin:064-gtp-channel-conf 00_150 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.SATA_BURST_SEQ_LEN[1] origin:064-gtp-channel-conf 01_150 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.SATA_BURST_SEQ_LEN[2] origin:064-gtp-channel-conf 00_151 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.SATA_BURST_SEQ_LEN[3] origin:064-gtp-channel-conf 01_151 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.SATA_BURST_VAL[0] origin:064-gtp-channel-conf 01_147 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.SATA_BURST_VAL[1] origin:064-gtp-channel-conf 00_148 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.SATA_BURST_VAL[2] origin:064-gtp-channel-conf 01_148 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.SATA_EIDLE_VAL[0] origin:064-gtp-channel-conf 00_152 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.SATA_EIDLE_VAL[1] origin:064-gtp-channel-conf 01_152 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.SATA_EIDLE_VAL[2] origin:064-gtp-channel-conf 00_153 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.SATA_MAX_BURST[0] origin:064-gtp-channel-conf 00_168 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.SATA_MAX_BURST[1] origin:064-gtp-channel-conf 01_168 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.SATA_MAX_BURST[2] origin:064-gtp-channel-conf 00_169 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.SATA_MAX_BURST[3] origin:064-gtp-channel-conf 01_169 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.SATA_MAX_BURST[4] origin:064-gtp-channel-conf 00_170 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.SATA_MAX_BURST[5] origin:064-gtp-channel-conf 01_170 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.SATA_MAX_INIT[0] origin:064-gtp-channel-conf 00_176 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.SATA_MAX_INIT[1] origin:064-gtp-channel-conf 01_176 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.SATA_MAX_INIT[2] origin:064-gtp-channel-conf 00_177 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.SATA_MAX_INIT[3] origin:064-gtp-channel-conf 01_177 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.SATA_MAX_INIT[4] origin:064-gtp-channel-conf 00_178 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.SATA_MAX_INIT[5] origin:064-gtp-channel-conf 01_178 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.SATA_MAX_WAKE[0] origin:064-gtp-channel-conf 00_179 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.SATA_MAX_WAKE[1] origin:064-gtp-channel-conf 01_179 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.SATA_MAX_WAKE[2] origin:064-gtp-channel-conf 00_180 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.SATA_MAX_WAKE[3] origin:064-gtp-channel-conf 01_180 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.SATA_MAX_WAKE[4] origin:064-gtp-channel-conf 00_181 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.SATA_MAX_WAKE[5] origin:064-gtp-channel-conf 01_181 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.SATA_MIN_BURST[0] origin:064-gtp-channel-conf 01_153 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.SATA_MIN_BURST[1] origin:064-gtp-channel-conf 00_154 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.SATA_MIN_BURST[2] origin:064-gtp-channel-conf 01_154 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.SATA_MIN_BURST[3] origin:064-gtp-channel-conf 00_155 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.SATA_MIN_BURST[4] origin:064-gtp-channel-conf 01_155 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.SATA_MIN_BURST[5] origin:064-gtp-channel-conf 00_156 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.SATA_MIN_INIT[0] origin:064-gtp-channel-conf 00_160 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.SATA_MIN_INIT[1] origin:064-gtp-channel-conf 01_160 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.SATA_MIN_INIT[2] origin:064-gtp-channel-conf 00_161 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.SATA_MIN_INIT[3] origin:064-gtp-channel-conf 01_161 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.SATA_MIN_INIT[4] origin:064-gtp-channel-conf 00_162 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.SATA_MIN_INIT[5] origin:064-gtp-channel-conf 01_162 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.SATA_MIN_WAKE[0] origin:064-gtp-channel-conf 00_163 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.SATA_MIN_WAKE[1] origin:064-gtp-channel-conf 01_163 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.SATA_MIN_WAKE[2] origin:064-gtp-channel-conf 00_164 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.SATA_MIN_WAKE[3] origin:064-gtp-channel-conf 01_164 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.SATA_MIN_WAKE[4] origin:064-gtp-channel-conf 00_165 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.SATA_MIN_WAKE[5] origin:064-gtp-channel-conf 01_165 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.SATA_PLL_CFG.VCO_1500MHZ origin:064-gtp-channel-conf 02_55 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.SATA_PLL_CFG.VCO_750MHZ origin:064-gtp-channel-conf 03_55 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.SHOW_REALIGN_COMMA origin:064-gtp-channel-conf 01_522 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TERM_RCAL_CFG[0] origin:064-gtp-channel-conf 02_136 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TERM_RCAL_CFG[1] origin:064-gtp-channel-conf 03_136 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TERM_RCAL_CFG[2] origin:064-gtp-channel-conf 02_137 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TERM_RCAL_CFG[3] origin:064-gtp-channel-conf 03_137 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TERM_RCAL_CFG[4] origin:064-gtp-channel-conf 02_138 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TERM_RCAL_CFG[5] origin:064-gtp-channel-conf 03_138 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TERM_RCAL_CFG[6] origin:064-gtp-channel-conf 02_139 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TERM_RCAL_CFG[7] origin:064-gtp-channel-conf 03_139 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TERM_RCAL_CFG[8] origin:064-gtp-channel-conf 02_140 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TERM_RCAL_CFG[9] origin:064-gtp-channel-conf 03_140 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TERM_RCAL_CFG[10] origin:064-gtp-channel-conf 02_141 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TERM_RCAL_CFG[11] origin:064-gtp-channel-conf 03_141 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TERM_RCAL_CFG[12] origin:064-gtp-channel-conf 02_142 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TERM_RCAL_CFG[13] origin:064-gtp-channel-conf 03_142 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TERM_RCAL_CFG[14] origin:064-gtp-channel-conf 02_143 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TERM_RCAL_OVRD[0] origin:064-gtp-channel-conf 03_150 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TERM_RCAL_OVRD[1] origin:064-gtp-channel-conf 02_151 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TERM_RCAL_OVRD[2] origin:064-gtp-channel-conf 03_151 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TRANS_TIME_RATE[0] origin:064-gtp-channel-conf 00_192 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TRANS_TIME_RATE[1] origin:064-gtp-channel-conf 01_192 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TRANS_TIME_RATE[2] origin:064-gtp-channel-conf 00_193 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TRANS_TIME_RATE[3] origin:064-gtp-channel-conf 01_193 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TRANS_TIME_RATE[4] origin:064-gtp-channel-conf 00_194 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TRANS_TIME_RATE[5] origin:064-gtp-channel-conf 01_194 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TRANS_TIME_RATE[6] origin:064-gtp-channel-conf 00_195 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TRANS_TIME_RATE[7] origin:064-gtp-channel-conf 01_195 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TST_RSV[0] origin:064-gtp-channel-conf 02_504 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TST_RSV[1] origin:064-gtp-channel-conf 03_504 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TST_RSV[2] origin:064-gtp-channel-conf 02_505 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TST_RSV[3] origin:064-gtp-channel-conf 03_505 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TST_RSV[4] origin:064-gtp-channel-conf 02_506 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TST_RSV[5] origin:064-gtp-channel-conf 03_506 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TST_RSV[6] origin:064-gtp-channel-conf 02_507 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TST_RSV[7] origin:064-gtp-channel-conf 03_507 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TST_RSV[8] origin:064-gtp-channel-conf 02_508 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TST_RSV[9] origin:064-gtp-channel-conf 03_508 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TST_RSV[10] origin:064-gtp-channel-conf 02_509 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TST_RSV[11] origin:064-gtp-channel-conf 03_509 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TST_RSV[12] origin:064-gtp-channel-conf 02_510 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TST_RSV[13] origin:064-gtp-channel-conf 03_510 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TST_RSV[14] origin:064-gtp-channel-conf 02_511 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TST_RSV[15] origin:064-gtp-channel-conf 03_511 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TST_RSV[16] origin:064-gtp-channel-conf 02_512 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TST_RSV[17] origin:064-gtp-channel-conf 03_512 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TST_RSV[18] origin:064-gtp-channel-conf 02_513 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TST_RSV[19] origin:064-gtp-channel-conf 03_513 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TST_RSV[20] origin:064-gtp-channel-conf 02_514 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TST_RSV[21] origin:064-gtp-channel-conf 03_514 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TST_RSV[22] origin:064-gtp-channel-conf 02_515 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TST_RSV[23] origin:064-gtp-channel-conf 03_515 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TST_RSV[24] origin:064-gtp-channel-conf 02_516 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TST_RSV[25] origin:064-gtp-channel-conf 03_516 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TST_RSV[26] origin:064-gtp-channel-conf 02_517 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TST_RSV[27] origin:064-gtp-channel-conf 03_517 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TST_RSV[28] origin:064-gtp-channel-conf 02_518 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TST_RSV[29] origin:064-gtp-channel-conf 03_518 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TST_RSV[30] origin:064-gtp-channel-conf 02_519 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TST_RSV[31] origin:064-gtp-channel-conf 03_519 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_CLKMUX_EN[0] origin:064-gtp-channel-conf 03_128 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_DATA_WIDTH[0] origin:064-gtp-channel-conf 02_152 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_DATA_WIDTH[1] origin:064-gtp-channel-conf 03_152 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_DATA_WIDTH[2] origin:064-gtp-channel-conf 02_153 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_DRIVE_MODE.PIPE origin:064-gtp-channel-conf 00_200 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_EIDLE_ASSERT_DELAY[0] origin:064-gtp-channel-conf 00_203 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_EIDLE_ASSERT_DELAY[1] origin:064-gtp-channel-conf 01_203 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_EIDLE_ASSERT_DELAY[2] origin:064-gtp-channel-conf 00_204 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_EIDLE_DEASSERT_DELAY[0] origin:064-gtp-channel-conf 01_204 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_EIDLE_DEASSERT_DELAY[1] origin:064-gtp-channel-conf 00_205 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_EIDLE_DEASSERT_DELAY[2] origin:064-gtp-channel-conf 01_205 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_LOOPBACK_DRIVE_HIZ origin:064-gtp-channel-conf 01_202 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_MAINCURSOR_SEL[0] origin:064-gtp-channel-conf 03_289 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_MARGIN_FULL_0[0] origin:064-gtp-channel-conf 02_232 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_MARGIN_FULL_0[1] origin:064-gtp-channel-conf 03_232 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_MARGIN_FULL_0[2] origin:064-gtp-channel-conf 02_233 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_MARGIN_FULL_0[3] origin:064-gtp-channel-conf 03_233 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_MARGIN_FULL_0[4] origin:064-gtp-channel-conf 02_234 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_MARGIN_FULL_0[5] origin:064-gtp-channel-conf 03_234 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_MARGIN_FULL_0[6] origin:064-gtp-channel-conf 02_235 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_MARGIN_FULL_1[0] origin:064-gtp-channel-conf 02_236 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_MARGIN_FULL_1[1] origin:064-gtp-channel-conf 03_236 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_MARGIN_FULL_1[2] origin:064-gtp-channel-conf 02_237 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_MARGIN_FULL_1[3] origin:064-gtp-channel-conf 03_237 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_MARGIN_FULL_1[4] origin:064-gtp-channel-conf 02_238 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_MARGIN_FULL_1[5] origin:064-gtp-channel-conf 03_238 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_MARGIN_FULL_1[6] origin:064-gtp-channel-conf 02_239 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_MARGIN_FULL_2[0] origin:064-gtp-channel-conf 02_240 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_MARGIN_FULL_2[1] origin:064-gtp-channel-conf 03_240 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_MARGIN_FULL_2[2] origin:064-gtp-channel-conf 02_241 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_MARGIN_FULL_2[3] origin:064-gtp-channel-conf 03_241 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_MARGIN_FULL_2[4] origin:064-gtp-channel-conf 02_242 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_MARGIN_FULL_2[5] origin:064-gtp-channel-conf 03_242 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_MARGIN_FULL_2[6] origin:064-gtp-channel-conf 02_243 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_MARGIN_FULL_3[0] origin:064-gtp-channel-conf 02_244 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_MARGIN_FULL_3[1] origin:064-gtp-channel-conf 03_244 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_MARGIN_FULL_3[2] origin:064-gtp-channel-conf 02_245 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_MARGIN_FULL_3[3] origin:064-gtp-channel-conf 03_245 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_MARGIN_FULL_3[4] origin:064-gtp-channel-conf 02_246 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_MARGIN_FULL_3[5] origin:064-gtp-channel-conf 03_246 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_MARGIN_FULL_3[6] origin:064-gtp-channel-conf 02_247 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_MARGIN_FULL_4[0] origin:064-gtp-channel-conf 02_248 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_MARGIN_FULL_4[1] origin:064-gtp-channel-conf 03_248 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_MARGIN_FULL_4[2] origin:064-gtp-channel-conf 02_249 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_MARGIN_FULL_4[3] origin:064-gtp-channel-conf 03_249 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_MARGIN_FULL_4[4] origin:064-gtp-channel-conf 02_250 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_MARGIN_FULL_4[5] origin:064-gtp-channel-conf 03_250 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_MARGIN_FULL_4[6] origin:064-gtp-channel-conf 02_251 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_MARGIN_LOW_0[0] origin:064-gtp-channel-conf 02_252 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_MARGIN_LOW_0[1] origin:064-gtp-channel-conf 03_252 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_MARGIN_LOW_0[2] origin:064-gtp-channel-conf 02_253 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_MARGIN_LOW_0[3] origin:064-gtp-channel-conf 03_253 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_MARGIN_LOW_0[4] origin:064-gtp-channel-conf 02_254 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_MARGIN_LOW_0[5] origin:064-gtp-channel-conf 03_254 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_MARGIN_LOW_0[6] origin:064-gtp-channel-conf 02_255 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_MARGIN_LOW_1[0] origin:064-gtp-channel-conf 02_256 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_MARGIN_LOW_1[1] origin:064-gtp-channel-conf 03_256 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_MARGIN_LOW_1[2] origin:064-gtp-channel-conf 02_257 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_MARGIN_LOW_1[3] origin:064-gtp-channel-conf 03_257 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_MARGIN_LOW_1[4] origin:064-gtp-channel-conf 02_258 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_MARGIN_LOW_1[5] origin:064-gtp-channel-conf 03_258 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_MARGIN_LOW_1[6] origin:064-gtp-channel-conf 02_259 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_MARGIN_LOW_2[0] origin:064-gtp-channel-conf 02_260 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_MARGIN_LOW_2[1] origin:064-gtp-channel-conf 03_260 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_MARGIN_LOW_2[2] origin:064-gtp-channel-conf 02_261 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_MARGIN_LOW_2[3] origin:064-gtp-channel-conf 03_261 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_MARGIN_LOW_2[4] origin:064-gtp-channel-conf 02_262 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_MARGIN_LOW_2[5] origin:064-gtp-channel-conf 03_262 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_MARGIN_LOW_2[6] origin:064-gtp-channel-conf 02_263 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_MARGIN_LOW_3[0] origin:064-gtp-channel-conf 02_264 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_MARGIN_LOW_3[1] origin:064-gtp-channel-conf 03_264 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_MARGIN_LOW_3[2] origin:064-gtp-channel-conf 02_265 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_MARGIN_LOW_3[3] origin:064-gtp-channel-conf 03_265 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_MARGIN_LOW_3[4] origin:064-gtp-channel-conf 02_266 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_MARGIN_LOW_3[5] origin:064-gtp-channel-conf 03_266 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_MARGIN_LOW_3[6] origin:064-gtp-channel-conf 02_267 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_MARGIN_LOW_4[0] origin:064-gtp-channel-conf 02_268 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_MARGIN_LOW_4[1] origin:064-gtp-channel-conf 03_268 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_MARGIN_LOW_4[2] origin:064-gtp-channel-conf 02_269 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_MARGIN_LOW_4[3] origin:064-gtp-channel-conf 03_269 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_MARGIN_LOW_4[4] origin:064-gtp-channel-conf 02_270 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_MARGIN_LOW_4[5] origin:064-gtp-channel-conf 03_270 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_MARGIN_LOW_4[6] origin:064-gtp-channel-conf 02_271 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_PREDRIVER_MODE[0] origin:064-gtp-channel-conf 00_206 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_RXDETECT_CFG[0] origin:064-gtp-channel-conf 02_296 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_RXDETECT_CFG[1] origin:064-gtp-channel-conf 03_296 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_RXDETECT_CFG[2] origin:064-gtp-channel-conf 02_297 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_RXDETECT_CFG[3] origin:064-gtp-channel-conf 03_297 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_RXDETECT_CFG[4] origin:064-gtp-channel-conf 02_298 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_RXDETECT_CFG[5] origin:064-gtp-channel-conf 03_298 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_RXDETECT_CFG[6] origin:064-gtp-channel-conf 02_299 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_RXDETECT_CFG[7] origin:064-gtp-channel-conf 03_299 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_RXDETECT_CFG[8] origin:064-gtp-channel-conf 02_300 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_RXDETECT_CFG[9] origin:064-gtp-channel-conf 03_300 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_RXDETECT_CFG[10] origin:064-gtp-channel-conf 02_301 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_RXDETECT_CFG[11] origin:064-gtp-channel-conf 03_301 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_RXDETECT_CFG[12] origin:064-gtp-channel-conf 02_302 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_RXDETECT_CFG[13] origin:064-gtp-channel-conf 03_302 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_RXDETECT_REF[0] origin:064-gtp-channel-conf 02_292 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_RXDETECT_REF[1] origin:064-gtp-channel-conf 03_292 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_RXDETECT_REF[2] origin:064-gtp-channel-conf 02_293 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_XCLK_SEL.TXUSR origin:064-gtp-channel-conf 03_11 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_CLK25_DIV[0] origin:064-gtp-channel-conf 02_144 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_CLK25_DIV[1] origin:064-gtp-channel-conf 03_144 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_CLK25_DIV[2] origin:064-gtp-channel-conf 02_145 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_CLK25_DIV[3] origin:064-gtp-channel-conf 03_145 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_CLK25_DIV[4] origin:064-gtp-channel-conf 02_146 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_DEEMPH0[0] origin:064-gtp-channel-conf 02_272 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_DEEMPH0[1] origin:064-gtp-channel-conf 03_272 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_DEEMPH0[2] origin:064-gtp-channel-conf 02_273 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_DEEMPH0[3] origin:064-gtp-channel-conf 03_273 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_DEEMPH0[4] origin:064-gtp-channel-conf 02_274 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_DEEMPH0[5] origin:064-gtp-channel-conf 03_274 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_DEEMPH1[0] origin:064-gtp-channel-conf 02_276 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_DEEMPH1[1] origin:064-gtp-channel-conf 03_276 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_DEEMPH1[2] origin:064-gtp-channel-conf 02_277 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_DEEMPH1[3] origin:064-gtp-channel-conf 03_277 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_DEEMPH1[4] origin:064-gtp-channel-conf 02_278 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TX_DEEMPH1[5] origin:064-gtp-channel-conf 03_278 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXBUF_EN origin:064-gtp-channel-conf 00_231 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXBUF_RESET_ON_RATE_CHANGE origin:064-gtp-channel-conf 01_231 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXDLY_CFG[0] origin:064-gtp-channel-conf 02_80 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXDLY_CFG[1] origin:064-gtp-channel-conf 03_80 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXDLY_CFG[2] origin:064-gtp-channel-conf 02_81 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXDLY_CFG[3] origin:064-gtp-channel-conf 03_81 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXDLY_CFG[4] origin:064-gtp-channel-conf 02_82 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXDLY_CFG[5] origin:064-gtp-channel-conf 03_82 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXDLY_CFG[6] origin:064-gtp-channel-conf 02_83 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXDLY_CFG[7] origin:064-gtp-channel-conf 03_83 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXDLY_CFG[8] origin:064-gtp-channel-conf 02_84 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXDLY_CFG[9] origin:064-gtp-channel-conf 03_84 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXDLY_CFG[10] origin:064-gtp-channel-conf 02_85 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXDLY_CFG[11] origin:064-gtp-channel-conf 03_85 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXDLY_CFG[12] origin:064-gtp-channel-conf 02_86 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXDLY_CFG[13] origin:064-gtp-channel-conf 03_86 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXDLY_CFG[14] origin:064-gtp-channel-conf 02_87 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXDLY_CFG[15] origin:064-gtp-channel-conf 03_87 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXDLY_LCFG[0] origin:064-gtp-channel-conf 02_568 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXDLY_LCFG[1] origin:064-gtp-channel-conf 03_568 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXDLY_LCFG[2] origin:064-gtp-channel-conf 02_569 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXDLY_LCFG[3] origin:064-gtp-channel-conf 03_569 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXDLY_LCFG[4] origin:064-gtp-channel-conf 02_570 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXDLY_LCFG[5] origin:064-gtp-channel-conf 03_570 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXDLY_LCFG[6] origin:064-gtp-channel-conf 02_571 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXDLY_LCFG[7] origin:064-gtp-channel-conf 03_571 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXDLY_LCFG[8] origin:064-gtp-channel-conf 02_572 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXDLY_TAP_CFG[0] origin:064-gtp-channel-conf 02_88 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXDLY_TAP_CFG[1] origin:064-gtp-channel-conf 03_88 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXDLY_TAP_CFG[2] origin:064-gtp-channel-conf 02_89 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXDLY_TAP_CFG[3] origin:064-gtp-channel-conf 03_89 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXDLY_TAP_CFG[4] origin:064-gtp-channel-conf 02_90 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXDLY_TAP_CFG[5] origin:064-gtp-channel-conf 03_90 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXDLY_TAP_CFG[6] origin:064-gtp-channel-conf 02_91 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXDLY_TAP_CFG[7] origin:064-gtp-channel-conf 03_91 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXDLY_TAP_CFG[8] origin:064-gtp-channel-conf 02_92 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXDLY_TAP_CFG[9] origin:064-gtp-channel-conf 03_92 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXDLY_TAP_CFG[10] origin:064-gtp-channel-conf 02_93 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXDLY_TAP_CFG[11] origin:064-gtp-channel-conf 03_93 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXDLY_TAP_CFG[12] origin:064-gtp-channel-conf 02_94 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXDLY_TAP_CFG[13] origin:064-gtp-channel-conf 03_94 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXDLY_TAP_CFG[14] origin:064-gtp-channel-conf 02_95 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXDLY_TAP_CFG[15] origin:064-gtp-channel-conf 03_95 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXGEARBOX_EN origin:064-gtp-channel-conf 01_226 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXOOB_CFG[0] origin:064-gtp-channel-conf 03_20 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXOUT_DIV[0] origin:064-gtp-channel-conf 02_386 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXOUT_DIV[1] origin:064-gtp-channel-conf 03_386 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPCSRESET_TIME[0] origin:064-gtp-channel-conf 01_130 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPCSRESET_TIME[1] origin:064-gtp-channel-conf 00_131 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPCSRESET_TIME[2] origin:064-gtp-channel-conf 01_131 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPCSRESET_TIME[3] origin:064-gtp-channel-conf 00_132 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPCSRESET_TIME[4] origin:064-gtp-channel-conf 01_132 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPH_CFG[0] origin:064-gtp-channel-conf 02_96 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPH_CFG[1] origin:064-gtp-channel-conf 03_96 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPH_CFG[2] origin:064-gtp-channel-conf 02_97 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPH_CFG[3] origin:064-gtp-channel-conf 03_97 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPH_CFG[4] origin:064-gtp-channel-conf 02_98 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPH_CFG[5] origin:064-gtp-channel-conf 03_98 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPH_CFG[6] origin:064-gtp-channel-conf 02_99 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPH_CFG[7] origin:064-gtp-channel-conf 03_99 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPH_CFG[8] origin:064-gtp-channel-conf 02_100 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPH_CFG[9] origin:064-gtp-channel-conf 03_100 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPH_CFG[10] origin:064-gtp-channel-conf 02_101 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPH_CFG[11] origin:064-gtp-channel-conf 03_101 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPH_CFG[12] origin:064-gtp-channel-conf 02_102 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPH_CFG[13] origin:064-gtp-channel-conf 03_102 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPH_CFG[14] origin:064-gtp-channel-conf 02_103 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPH_CFG[15] origin:064-gtp-channel-conf 03_103 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPH_MONITOR_SEL[0] origin:064-gtp-channel-conf 02_108 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPH_MONITOR_SEL[1] origin:064-gtp-channel-conf 03_108 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPH_MONITOR_SEL[2] origin:064-gtp-channel-conf 02_109 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPH_MONITOR_SEL[3] origin:064-gtp-channel-conf 03_109 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPH_MONITOR_SEL[4] origin:064-gtp-channel-conf 02_110 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPHDLY_CFG[0] origin:064-gtp-channel-conf 02_64 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPHDLY_CFG[1] origin:064-gtp-channel-conf 03_64 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPHDLY_CFG[2] origin:064-gtp-channel-conf 02_65 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPHDLY_CFG[3] origin:064-gtp-channel-conf 03_65 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPHDLY_CFG[4] origin:064-gtp-channel-conf 02_66 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPHDLY_CFG[5] origin:064-gtp-channel-conf 03_66 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPHDLY_CFG[6] origin:064-gtp-channel-conf 02_67 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPHDLY_CFG[7] origin:064-gtp-channel-conf 03_67 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPHDLY_CFG[8] origin:064-gtp-channel-conf 02_68 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPHDLY_CFG[9] origin:064-gtp-channel-conf 03_68 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPHDLY_CFG[10] origin:064-gtp-channel-conf 02_69 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPHDLY_CFG[11] origin:064-gtp-channel-conf 03_69 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPHDLY_CFG[12] origin:064-gtp-channel-conf 02_70 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPHDLY_CFG[13] origin:064-gtp-channel-conf 03_70 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPHDLY_CFG[14] origin:064-gtp-channel-conf 02_71 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPHDLY_CFG[15] origin:064-gtp-channel-conf 03_71 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPHDLY_CFG[16] origin:064-gtp-channel-conf 02_72 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPHDLY_CFG[17] origin:064-gtp-channel-conf 03_72 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPHDLY_CFG[18] origin:064-gtp-channel-conf 02_73 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPHDLY_CFG[19] origin:064-gtp-channel-conf 03_73 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPHDLY_CFG[20] origin:064-gtp-channel-conf 02_74 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPHDLY_CFG[21] origin:064-gtp-channel-conf 03_74 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPHDLY_CFG[22] origin:064-gtp-channel-conf 02_75 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPHDLY_CFG[23] origin:064-gtp-channel-conf 03_75 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPI_GREY_SEL[0] origin:064-gtp-channel-conf 03_498 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPI_INVSTROBE_SEL[0] origin:064-gtp-channel-conf 02_498 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPI_PPM_CFG[0] origin:064-gtp-channel-conf 02_488 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPI_PPM_CFG[1] origin:064-gtp-channel-conf 03_488 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPI_PPM_CFG[2] origin:064-gtp-channel-conf 02_489 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPI_PPM_CFG[3] origin:064-gtp-channel-conf 03_489 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPI_PPM_CFG[4] origin:064-gtp-channel-conf 02_490 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPI_PPM_CFG[5] origin:064-gtp-channel-conf 03_490 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPI_PPM_CFG[6] origin:064-gtp-channel-conf 02_491 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPI_PPM_CFG[7] origin:064-gtp-channel-conf 03_491 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPI_PPMCLK_SEL.TXUSRCLK2 origin:064-gtp-channel-conf 03_497 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPI_SYNFREQ_PPM[0] origin:064-gtp-channel-conf 02_496 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPI_SYNFREQ_PPM[1] origin:064-gtp-channel-conf 03_496 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPI_SYNFREQ_PPM[2] origin:064-gtp-channel-conf 02_497 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPI_CFG0[0] origin:064-gtp-channel-conf 02_40 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPI_CFG0[1] origin:064-gtp-channel-conf 03_40 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPI_CFG1[0] origin:064-gtp-channel-conf 02_41 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPI_CFG1[1] origin:064-gtp-channel-conf 03_41 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPI_CFG2[0] origin:064-gtp-channel-conf 02_42 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPI_CFG2[1] origin:064-gtp-channel-conf 03_42 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPI_CFG3[0] origin:064-gtp-channel-conf 02_43 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPI_CFG4[0] origin:064-gtp-channel-conf 03_43 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPI_CFG5[0] origin:064-gtp-channel-conf 02_44 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPI_CFG5[1] origin:064-gtp-channel-conf 03_44 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPI_CFG5[2] origin:064-gtp-channel-conf 02_45 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPMARESET_TIME[0] origin:064-gtp-channel-conf 00_128 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPMARESET_TIME[1] origin:064-gtp-channel-conf 01_128 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPMARESET_TIME[2] origin:064-gtp-channel-conf 00_129 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPMARESET_TIME[3] origin:064-gtp-channel-conf 01_129 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXPMARESET_TIME[4] origin:064-gtp-channel-conf 00_130 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXSYNC_MULTILANE[0] origin:064-gtp-channel-conf 01_133 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXSYNC_OVRD[0] origin:064-gtp-channel-conf 00_135 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.TXSYNC_SKIP_DA[0] origin:064-gtp-channel-conf 00_134 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.UCODEER_CLR[0] origin:064-gtp-channel-conf 01_00 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.USE_PCS_CLK_PHASE_SEL[0] origin:064-gtp-channel-conf 02_463 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ZINV_DMONITORCLK origin:064-gtp-channel-conf 02_13 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ZINV_DRPCLK origin:064-gtp-channel-conf 02_00 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ZINV_RXUSRCLK origin:064-gtp-channel-conf 03_01 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ZINV_SIGVALIDCLK origin:064-gtp-channel-conf 03_13 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ZINV_TXPHDLYTSTCLK origin:064-gtp-channel-conf 02_03 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ZINV_TXUSRCLK origin:064-gtp-channel-conf 03_04 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ZINV_CLKRSVD0 origin:064-gtp-channel-conf 02_23 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ZINV_CLKRSVD1 origin:064-gtp-channel-conf 03_23 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ZINV_RXUSRCLK2 origin:064-gtp-channel-conf 02_02 -GTP_CHANNEL_1_MID_RIGHT.GTPE2.ZINV_TXUSRCLK2 origin:064-gtp-channel-conf 02_05 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ACJTAG_DEBUG_MODE[0] origin:064-gtp-channel-conf 00_07 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ACJTAG_MODE[0] origin:064-gtp-channel-conf 01_06 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ACJTAG_RESET[0] origin:064-gtp-channel-conf 01_07 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[0] origin:064-gtp-channel-conf 02_464 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[1] origin:064-gtp-channel-conf 03_464 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[2] origin:064-gtp-channel-conf 02_465 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[3] origin:064-gtp-channel-conf 03_465 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[4] origin:064-gtp-channel-conf 02_466 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[5] origin:064-gtp-channel-conf 03_466 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[6] origin:064-gtp-channel-conf 02_467 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[7] origin:064-gtp-channel-conf 03_467 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[8] origin:064-gtp-channel-conf 02_468 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[9] origin:064-gtp-channel-conf 03_468 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[10] origin:064-gtp-channel-conf 02_469 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[11] origin:064-gtp-channel-conf 03_469 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[12] origin:064-gtp-channel-conf 02_470 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[13] origin:064-gtp-channel-conf 03_470 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[14] origin:064-gtp-channel-conf 02_471 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[15] origin:064-gtp-channel-conf 03_471 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[16] origin:064-gtp-channel-conf 02_472 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[17] origin:064-gtp-channel-conf 03_472 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[18] origin:064-gtp-channel-conf 02_473 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[19] origin:064-gtp-channel-conf 03_473 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ALIGN_COMMA_DOUBLE origin:064-gtp-channel-conf 00_522 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[0] origin:064-gtp-channel-conf 00_496 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[1] origin:064-gtp-channel-conf 01_496 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[2] origin:064-gtp-channel-conf 00_497 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[3] origin:064-gtp-channel-conf 01_497 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[4] origin:064-gtp-channel-conf 00_498 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[5] origin:064-gtp-channel-conf 01_498 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[6] origin:064-gtp-channel-conf 00_499 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[7] origin:064-gtp-channel-conf 01_499 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[8] origin:064-gtp-channel-conf 00_500 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[9] origin:064-gtp-channel-conf 01_500 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ALIGN_COMMA_WORD[0] origin:064-gtp-channel-conf 01_526 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ALIGN_COMMA_WORD[1] origin:064-gtp-channel-conf 00_527 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ALIGN_MCOMMA_DET origin:064-gtp-channel-conf 00_523 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[0] origin:064-gtp-channel-conf 00_504 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[1] origin:064-gtp-channel-conf 01_504 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[2] origin:064-gtp-channel-conf 00_505 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[3] origin:064-gtp-channel-conf 01_505 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[4] origin:064-gtp-channel-conf 00_506 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[5] origin:064-gtp-channel-conf 01_506 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[6] origin:064-gtp-channel-conf 00_507 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[7] origin:064-gtp-channel-conf 01_507 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[8] origin:064-gtp-channel-conf 00_508 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[9] origin:064-gtp-channel-conf 01_508 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ALIGN_PCOMMA_DET origin:064-gtp-channel-conf 01_523 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[0] origin:064-gtp-channel-conf 00_512 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[1] origin:064-gtp-channel-conf 01_512 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[2] origin:064-gtp-channel-conf 00_513 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[3] origin:064-gtp-channel-conf 01_513 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[4] origin:064-gtp-channel-conf 00_514 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[5] origin:064-gtp-channel-conf 01_514 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[6] origin:064-gtp-channel-conf 00_515 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[7] origin:064-gtp-channel-conf 01_515 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[8] origin:064-gtp-channel-conf 00_516 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[9] origin:064-gtp-channel-conf 01_516 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CBCC_DATA_SOURCE_SEL.DECODED origin:064-gtp-channel-conf 01_661 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[0] origin:064-gtp-channel-conf 02_392 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[1] origin:064-gtp-channel-conf 03_392 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[2] origin:064-gtp-channel-conf 02_393 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[3] origin:064-gtp-channel-conf 03_393 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[4] origin:064-gtp-channel-conf 02_394 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[5] origin:064-gtp-channel-conf 03_394 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[6] origin:064-gtp-channel-conf 02_395 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[7] origin:064-gtp-channel-conf 03_395 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[8] origin:064-gtp-channel-conf 02_396 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[9] origin:064-gtp-channel-conf 03_396 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[10] origin:064-gtp-channel-conf 02_397 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[11] origin:064-gtp-channel-conf 03_397 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[12] origin:064-gtp-channel-conf 02_398 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[13] origin:064-gtp-channel-conf 03_398 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[14] origin:064-gtp-channel-conf 02_399 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[15] origin:064-gtp-channel-conf 03_399 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[16] origin:064-gtp-channel-conf 02_400 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[17] origin:064-gtp-channel-conf 03_400 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[18] origin:064-gtp-channel-conf 02_401 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[19] origin:064-gtp-channel-conf 03_401 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[20] origin:064-gtp-channel-conf 02_402 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[21] origin:064-gtp-channel-conf 03_402 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[22] origin:064-gtp-channel-conf 02_403 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[23] origin:064-gtp-channel-conf 03_403 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[24] origin:064-gtp-channel-conf 02_404 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[25] origin:064-gtp-channel-conf 03_404 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[26] origin:064-gtp-channel-conf 02_405 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[27] origin:064-gtp-channel-conf 03_405 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[28] origin:064-gtp-channel-conf 02_406 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[29] origin:064-gtp-channel-conf 03_406 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[30] origin:064-gtp-channel-conf 02_407 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[31] origin:064-gtp-channel-conf 03_407 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[32] origin:064-gtp-channel-conf 02_408 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[33] origin:064-gtp-channel-conf 03_408 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[34] origin:064-gtp-channel-conf 02_409 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[35] origin:064-gtp-channel-conf 03_409 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[36] origin:064-gtp-channel-conf 02_410 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[37] origin:064-gtp-channel-conf 03_410 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[38] origin:064-gtp-channel-conf 02_411 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[39] origin:064-gtp-channel-conf 03_411 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[40] origin:064-gtp-channel-conf 02_412 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[41] origin:064-gtp-channel-conf 03_412 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[42] origin:064-gtp-channel-conf 02_413 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG2[0] origin:064-gtp-channel-conf 02_459 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG2[1] origin:064-gtp-channel-conf 03_459 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG2[2] origin:064-gtp-channel-conf 02_460 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG2[3] origin:064-gtp-channel-conf 03_460 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG2[4] origin:064-gtp-channel-conf 02_461 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG2[5] origin:064-gtp-channel-conf 03_461 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG2[6] origin:064-gtp-channel-conf 02_462 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG3[0] origin:064-gtp-channel-conf 02_416 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG3[1] origin:064-gtp-channel-conf 03_416 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG3[2] origin:064-gtp-channel-conf 02_417 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG3[3] origin:064-gtp-channel-conf 03_417 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG3[4] origin:064-gtp-channel-conf 02_418 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG3[5] origin:064-gtp-channel-conf 03_418 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG3[6] origin:064-gtp-channel-conf 02_419 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG4[0] origin:064-gtp-channel-conf 03_438 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG5[0] origin:064-gtp-channel-conf 02_429 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG5[1] origin:064-gtp-channel-conf 03_429 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG6[0] origin:064-gtp-channel-conf 03_436 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG6[1] origin:064-gtp-channel-conf 02_437 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG6[2] origin:064-gtp-channel-conf 03_437 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG6[3] origin:064-gtp-channel-conf 02_438 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_KEEP_ALIGN origin:064-gtp-channel-conf 01_631 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_MAX_SKEW[0] origin:064-gtp-channel-conf 00_670 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_MAX_SKEW[1] origin:064-gtp-channel-conf 01_670 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_MAX_SKEW[2] origin:064-gtp-channel-conf 00_671 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_MAX_SKEW[3] origin:064-gtp-channel-conf 01_671 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[0] origin:064-gtp-channel-conf 00_608 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[1] origin:064-gtp-channel-conf 01_608 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[2] origin:064-gtp-channel-conf 00_609 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[3] origin:064-gtp-channel-conf 01_609 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[4] origin:064-gtp-channel-conf 00_610 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[5] origin:064-gtp-channel-conf 01_610 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[6] origin:064-gtp-channel-conf 00_611 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[7] origin:064-gtp-channel-conf 01_611 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[8] origin:064-gtp-channel-conf 00_612 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[9] origin:064-gtp-channel-conf 01_612 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[0] origin:064-gtp-channel-conf 00_616 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[1] origin:064-gtp-channel-conf 01_616 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[2] origin:064-gtp-channel-conf 00_617 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[3] origin:064-gtp-channel-conf 01_617 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[4] origin:064-gtp-channel-conf 00_618 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[5] origin:064-gtp-channel-conf 01_618 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[6] origin:064-gtp-channel-conf 00_619 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[7] origin:064-gtp-channel-conf 01_619 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[8] origin:064-gtp-channel-conf 00_620 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[9] origin:064-gtp-channel-conf 01_620 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[0] origin:064-gtp-channel-conf 00_624 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[1] origin:064-gtp-channel-conf 01_624 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[2] origin:064-gtp-channel-conf 00_625 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[3] origin:064-gtp-channel-conf 01_625 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[4] origin:064-gtp-channel-conf 00_626 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[5] origin:064-gtp-channel-conf 01_626 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[6] origin:064-gtp-channel-conf 00_627 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[7] origin:064-gtp-channel-conf 01_627 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[8] origin:064-gtp-channel-conf 00_628 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[9] origin:064-gtp-channel-conf 01_628 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[0] origin:064-gtp-channel-conf 00_632 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[1] origin:064-gtp-channel-conf 01_632 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[2] origin:064-gtp-channel-conf 00_633 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[3] origin:064-gtp-channel-conf 01_633 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[4] origin:064-gtp-channel-conf 00_634 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[5] origin:064-gtp-channel-conf 01_634 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[6] origin:064-gtp-channel-conf 00_635 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[7] origin:064-gtp-channel-conf 01_635 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[8] origin:064-gtp-channel-conf 00_636 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[9] origin:064-gtp-channel-conf 01_636 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_ENABLE[0] origin:064-gtp-channel-conf 00_614 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_ENABLE[1] origin:064-gtp-channel-conf 01_614 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_ENABLE[2] origin:064-gtp-channel-conf 00_615 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_ENABLE[3] origin:064-gtp-channel-conf 01_615 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[0] origin:064-gtp-channel-conf 00_640 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[1] origin:064-gtp-channel-conf 01_640 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[2] origin:064-gtp-channel-conf 00_641 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[3] origin:064-gtp-channel-conf 01_641 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[4] origin:064-gtp-channel-conf 00_642 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[5] origin:064-gtp-channel-conf 01_642 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[6] origin:064-gtp-channel-conf 00_643 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[7] origin:064-gtp-channel-conf 01_643 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[8] origin:064-gtp-channel-conf 00_644 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[9] origin:064-gtp-channel-conf 01_644 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[0] origin:064-gtp-channel-conf 00_648 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[1] origin:064-gtp-channel-conf 01_648 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[2] origin:064-gtp-channel-conf 00_649 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[3] origin:064-gtp-channel-conf 01_649 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[4] origin:064-gtp-channel-conf 00_650 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[5] origin:064-gtp-channel-conf 01_650 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[6] origin:064-gtp-channel-conf 00_651 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[7] origin:064-gtp-channel-conf 01_651 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[8] origin:064-gtp-channel-conf 00_652 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[9] origin:064-gtp-channel-conf 01_652 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[0] origin:064-gtp-channel-conf 00_656 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[1] origin:064-gtp-channel-conf 01_656 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[2] origin:064-gtp-channel-conf 00_657 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[3] origin:064-gtp-channel-conf 01_657 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[4] origin:064-gtp-channel-conf 00_658 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[5] origin:064-gtp-channel-conf 01_658 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[6] origin:064-gtp-channel-conf 00_659 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[7] origin:064-gtp-channel-conf 01_659 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[8] origin:064-gtp-channel-conf 00_660 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[9] origin:064-gtp-channel-conf 01_660 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[0] origin:064-gtp-channel-conf 00_664 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[1] origin:064-gtp-channel-conf 01_664 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[2] origin:064-gtp-channel-conf 00_665 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[3] origin:064-gtp-channel-conf 01_665 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[4] origin:064-gtp-channel-conf 00_666 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[5] origin:064-gtp-channel-conf 01_666 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[6] origin:064-gtp-channel-conf 00_667 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[7] origin:064-gtp-channel-conf 01_667 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[8] origin:064-gtp-channel-conf 00_668 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[9] origin:064-gtp-channel-conf 01_668 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_ENABLE[0] origin:064-gtp-channel-conf 00_646 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_ENABLE[1] origin:064-gtp-channel-conf 01_646 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_ENABLE[2] origin:064-gtp-channel-conf 00_647 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_ENABLE[3] origin:064-gtp-channel-conf 01_647 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_USE origin:064-gtp-channel-conf 01_645 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_LEN[0] origin:064-gtp-channel-conf 00_623 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_LEN[1] origin:064-gtp-channel-conf 01_623 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COMMON_SWING[0] origin:064-gtp-channel-conf 03_311 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_KEEP_IDLE origin:064-gtp-channel-conf 00_591 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_MAX_LAT[0] origin:064-gtp-channel-conf 00_557 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_MAX_LAT[1] origin:064-gtp-channel-conf 01_557 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_MAX_LAT[2] origin:064-gtp-channel-conf 00_558 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_MAX_LAT[3] origin:064-gtp-channel-conf 01_558 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_MAX_LAT[4] origin:064-gtp-channel-conf 00_559 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_MAX_LAT[5] origin:064-gtp-channel-conf 01_559 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_MIN_LAT[0] origin:064-gtp-channel-conf 00_565 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_MIN_LAT[1] origin:064-gtp-channel-conf 01_565 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_MIN_LAT[2] origin:064-gtp-channel-conf 00_566 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_MIN_LAT[3] origin:064-gtp-channel-conf 01_566 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_MIN_LAT[4] origin:064-gtp-channel-conf 00_567 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_MIN_LAT[5] origin:064-gtp-channel-conf 01_567 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_PRECEDENCE origin:064-gtp-channel-conf 00_590 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_REPEAT_WAIT[0] origin:064-gtp-channel-conf 00_573 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_REPEAT_WAIT[1] origin:064-gtp-channel-conf 01_573 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_REPEAT_WAIT[2] origin:064-gtp-channel-conf 00_574 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_REPEAT_WAIT[3] origin:064-gtp-channel-conf 01_574 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_REPEAT_WAIT[4] origin:064-gtp-channel-conf 00_575 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[0] origin:064-gtp-channel-conf 00_544 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[1] origin:064-gtp-channel-conf 01_544 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[2] origin:064-gtp-channel-conf 00_545 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[3] origin:064-gtp-channel-conf 01_545 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[4] origin:064-gtp-channel-conf 00_546 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[5] origin:064-gtp-channel-conf 01_546 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[6] origin:064-gtp-channel-conf 00_547 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[7] origin:064-gtp-channel-conf 01_547 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[8] origin:064-gtp-channel-conf 00_548 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[9] origin:064-gtp-channel-conf 01_548 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[0] origin:064-gtp-channel-conf 00_552 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[1] origin:064-gtp-channel-conf 01_552 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[2] origin:064-gtp-channel-conf 00_553 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[3] origin:064-gtp-channel-conf 01_553 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[4] origin:064-gtp-channel-conf 00_554 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[5] origin:064-gtp-channel-conf 01_554 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[6] origin:064-gtp-channel-conf 00_555 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[7] origin:064-gtp-channel-conf 01_555 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[8] origin:064-gtp-channel-conf 00_556 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[9] origin:064-gtp-channel-conf 01_556 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[0] origin:064-gtp-channel-conf 00_560 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[1] origin:064-gtp-channel-conf 01_560 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[2] origin:064-gtp-channel-conf 00_561 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[3] origin:064-gtp-channel-conf 01_561 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[4] origin:064-gtp-channel-conf 00_562 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[5] origin:064-gtp-channel-conf 01_562 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[6] origin:064-gtp-channel-conf 00_563 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[7] origin:064-gtp-channel-conf 01_563 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[8] origin:064-gtp-channel-conf 00_564 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[9] origin:064-gtp-channel-conf 01_564 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[0] origin:064-gtp-channel-conf 00_568 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[1] origin:064-gtp-channel-conf 01_568 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[2] origin:064-gtp-channel-conf 00_569 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[3] origin:064-gtp-channel-conf 01_569 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[4] origin:064-gtp-channel-conf 00_570 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[5] origin:064-gtp-channel-conf 01_570 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[6] origin:064-gtp-channel-conf 00_571 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[7] origin:064-gtp-channel-conf 01_571 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[8] origin:064-gtp-channel-conf 00_572 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[9] origin:064-gtp-channel-conf 01_572 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_ENABLE[0] origin:064-gtp-channel-conf 00_549 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_ENABLE[1] origin:064-gtp-channel-conf 01_549 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_ENABLE[2] origin:064-gtp-channel-conf 00_550 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_ENABLE[3] origin:064-gtp-channel-conf 01_550 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[0] origin:064-gtp-channel-conf 00_576 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[1] origin:064-gtp-channel-conf 01_576 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[2] origin:064-gtp-channel-conf 00_577 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[3] origin:064-gtp-channel-conf 01_577 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[4] origin:064-gtp-channel-conf 00_578 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[5] origin:064-gtp-channel-conf 01_578 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[6] origin:064-gtp-channel-conf 00_579 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[7] origin:064-gtp-channel-conf 01_579 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[8] origin:064-gtp-channel-conf 00_580 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[9] origin:064-gtp-channel-conf 01_580 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[0] origin:064-gtp-channel-conf 00_584 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[1] origin:064-gtp-channel-conf 01_584 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[2] origin:064-gtp-channel-conf 00_585 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[3] origin:064-gtp-channel-conf 01_585 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[4] origin:064-gtp-channel-conf 00_586 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[5] origin:064-gtp-channel-conf 01_586 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[6] origin:064-gtp-channel-conf 00_587 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[7] origin:064-gtp-channel-conf 01_587 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[8] origin:064-gtp-channel-conf 00_588 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[9] origin:064-gtp-channel-conf 01_588 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[0] origin:064-gtp-channel-conf 00_592 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[1] origin:064-gtp-channel-conf 01_592 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[2] origin:064-gtp-channel-conf 00_593 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[3] origin:064-gtp-channel-conf 01_593 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[4] origin:064-gtp-channel-conf 00_594 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[5] origin:064-gtp-channel-conf 01_594 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[6] origin:064-gtp-channel-conf 00_595 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[7] origin:064-gtp-channel-conf 01_595 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[8] origin:064-gtp-channel-conf 00_596 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[9] origin:064-gtp-channel-conf 01_596 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[0] origin:064-gtp-channel-conf 00_600 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[1] origin:064-gtp-channel-conf 01_600 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[2] origin:064-gtp-channel-conf 00_601 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[3] origin:064-gtp-channel-conf 01_601 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[4] origin:064-gtp-channel-conf 00_602 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[5] origin:064-gtp-channel-conf 01_602 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[6] origin:064-gtp-channel-conf 00_603 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[7] origin:064-gtp-channel-conf 01_603 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[8] origin:064-gtp-channel-conf 00_604 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[9] origin:064-gtp-channel-conf 01_604 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_ENABLE[0] origin:064-gtp-channel-conf 00_581 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_ENABLE[1] origin:064-gtp-channel-conf 01_581 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_ENABLE[2] origin:064-gtp-channel-conf 00_582 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_ENABLE[3] origin:064-gtp-channel-conf 01_582 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_USE origin:064-gtp-channel-conf 00_583 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_LEN[0] origin:064-gtp-channel-conf 00_589 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_LEN[1] origin:064-gtp-channel-conf 01_589 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.CLK_CORRECT_USE origin:064-gtp-channel-conf 00_551 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.DEC_MCOMMA_DETECT origin:064-gtp-channel-conf 01_494 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.DEC_PCOMMA_DETECT origin:064-gtp-channel-conf 00_495 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.DEC_VALID_COMMA_ONLY origin:064-gtp-channel-conf 00_494 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[0] origin:064-gtp-channel-conf 02_368 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[1] origin:064-gtp-channel-conf 03_368 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[2] origin:064-gtp-channel-conf 02_369 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[3] origin:064-gtp-channel-conf 03_369 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[4] origin:064-gtp-channel-conf 02_370 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[5] origin:064-gtp-channel-conf 03_370 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[6] origin:064-gtp-channel-conf 02_371 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[7] origin:064-gtp-channel-conf 03_371 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[8] origin:064-gtp-channel-conf 02_372 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[9] origin:064-gtp-channel-conf 03_372 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[10] origin:064-gtp-channel-conf 02_373 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[11] origin:064-gtp-channel-conf 03_373 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[12] origin:064-gtp-channel-conf 02_374 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[13] origin:064-gtp-channel-conf 03_374 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[14] origin:064-gtp-channel-conf 02_375 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[15] origin:064-gtp-channel-conf 03_375 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[16] origin:064-gtp-channel-conf 02_376 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[17] origin:064-gtp-channel-conf 03_376 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[18] origin:064-gtp-channel-conf 02_377 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[19] origin:064-gtp-channel-conf 03_377 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[20] origin:064-gtp-channel-conf 02_378 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[21] origin:064-gtp-channel-conf 03_378 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[22] origin:064-gtp-channel-conf 02_379 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[23] origin:064-gtp-channel-conf 03_379 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_CLK_PHASE_SEL[0] origin:064-gtp-channel-conf 03_463 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_CONTROL[0] origin:064-gtp-channel-conf 00_488 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_CONTROL[1] origin:064-gtp-channel-conf 01_488 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_CONTROL[2] origin:064-gtp-channel-conf 00_489 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_CONTROL[3] origin:064-gtp-channel-conf 01_489 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_CONTROL[4] origin:064-gtp-channel-conf 00_490 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_CONTROL[5] origin:064-gtp-channel-conf 01_490 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_ERRDET_EN origin:064-gtp-channel-conf 01_492 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_EYE_SCAN_EN origin:064-gtp-channel-conf 00_492 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_HORZ_OFFSET[0] origin:064-gtp-channel-conf 00_480 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_HORZ_OFFSET[1] origin:064-gtp-channel-conf 01_480 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_HORZ_OFFSET[2] origin:064-gtp-channel-conf 00_481 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_HORZ_OFFSET[3] origin:064-gtp-channel-conf 01_481 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_HORZ_OFFSET[4] origin:064-gtp-channel-conf 00_482 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_HORZ_OFFSET[5] origin:064-gtp-channel-conf 01_482 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_HORZ_OFFSET[6] origin:064-gtp-channel-conf 00_483 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_HORZ_OFFSET[7] origin:064-gtp-channel-conf 01_483 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_HORZ_OFFSET[8] origin:064-gtp-channel-conf 00_484 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_HORZ_OFFSET[9] origin:064-gtp-channel-conf 01_484 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_HORZ_OFFSET[10] origin:064-gtp-channel-conf 00_485 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_HORZ_OFFSET[11] origin:064-gtp-channel-conf 01_485 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_PMA_CFG[0] origin:064-gtp-channel-conf 02_624 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_PMA_CFG[1] origin:064-gtp-channel-conf 03_624 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_PMA_CFG[2] origin:064-gtp-channel-conf 02_625 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_PMA_CFG[3] origin:064-gtp-channel-conf 03_625 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_PMA_CFG[4] origin:064-gtp-channel-conf 02_626 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_PMA_CFG[5] origin:064-gtp-channel-conf 03_626 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_PMA_CFG[6] origin:064-gtp-channel-conf 02_627 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_PMA_CFG[7] origin:064-gtp-channel-conf 03_627 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_PMA_CFG[8] origin:064-gtp-channel-conf 02_628 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_PMA_CFG[9] origin:064-gtp-channel-conf 03_628 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_PRESCALE[0] origin:064-gtp-channel-conf 01_477 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_PRESCALE[1] origin:064-gtp-channel-conf 00_478 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_PRESCALE[2] origin:064-gtp-channel-conf 01_478 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_PRESCALE[3] origin:064-gtp-channel-conf 00_479 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_PRESCALE[4] origin:064-gtp-channel-conf 01_479 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[0] origin:064-gtp-channel-conf 00_392 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[1] origin:064-gtp-channel-conf 01_392 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[2] origin:064-gtp-channel-conf 00_393 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[3] origin:064-gtp-channel-conf 01_393 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[4] origin:064-gtp-channel-conf 00_394 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[5] origin:064-gtp-channel-conf 01_394 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[6] origin:064-gtp-channel-conf 00_395 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[7] origin:064-gtp-channel-conf 01_395 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[8] origin:064-gtp-channel-conf 00_396 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[9] origin:064-gtp-channel-conf 01_396 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[10] origin:064-gtp-channel-conf 00_397 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[11] origin:064-gtp-channel-conf 01_397 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[12] origin:064-gtp-channel-conf 00_398 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[13] origin:064-gtp-channel-conf 01_398 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[14] origin:064-gtp-channel-conf 00_399 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[15] origin:064-gtp-channel-conf 01_399 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[16] origin:064-gtp-channel-conf 00_400 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[17] origin:064-gtp-channel-conf 01_400 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[18] origin:064-gtp-channel-conf 00_401 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[19] origin:064-gtp-channel-conf 01_401 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[20] origin:064-gtp-channel-conf 00_402 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[21] origin:064-gtp-channel-conf 01_402 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[22] origin:064-gtp-channel-conf 00_403 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[23] origin:064-gtp-channel-conf 01_403 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[24] origin:064-gtp-channel-conf 00_404 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[25] origin:064-gtp-channel-conf 01_404 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[26] origin:064-gtp-channel-conf 00_405 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[27] origin:064-gtp-channel-conf 01_405 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[28] origin:064-gtp-channel-conf 00_406 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[29] origin:064-gtp-channel-conf 01_406 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[30] origin:064-gtp-channel-conf 00_407 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[31] origin:064-gtp-channel-conf 01_407 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[32] origin:064-gtp-channel-conf 00_408 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[33] origin:064-gtp-channel-conf 01_408 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[34] origin:064-gtp-channel-conf 00_409 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[35] origin:064-gtp-channel-conf 01_409 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[36] origin:064-gtp-channel-conf 00_410 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[37] origin:064-gtp-channel-conf 01_410 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[38] origin:064-gtp-channel-conf 00_411 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[39] origin:064-gtp-channel-conf 01_411 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[40] origin:064-gtp-channel-conf 00_412 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[41] origin:064-gtp-channel-conf 01_412 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[42] origin:064-gtp-channel-conf 00_413 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[43] origin:064-gtp-channel-conf 01_413 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[44] origin:064-gtp-channel-conf 00_414 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[45] origin:064-gtp-channel-conf 01_414 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[46] origin:064-gtp-channel-conf 00_415 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[47] origin:064-gtp-channel-conf 01_415 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[48] origin:064-gtp-channel-conf 00_416 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[49] origin:064-gtp-channel-conf 01_416 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[50] origin:064-gtp-channel-conf 00_417 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[51] origin:064-gtp-channel-conf 01_417 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[52] origin:064-gtp-channel-conf 00_418 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[53] origin:064-gtp-channel-conf 01_418 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[54] origin:064-gtp-channel-conf 00_419 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[55] origin:064-gtp-channel-conf 01_419 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[56] origin:064-gtp-channel-conf 00_420 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[57] origin:064-gtp-channel-conf 01_420 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[58] origin:064-gtp-channel-conf 00_421 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[59] origin:064-gtp-channel-conf 01_421 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[60] origin:064-gtp-channel-conf 00_422 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[61] origin:064-gtp-channel-conf 01_422 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[62] origin:064-gtp-channel-conf 00_423 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[63] origin:064-gtp-channel-conf 01_423 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[64] origin:064-gtp-channel-conf 00_424 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[65] origin:064-gtp-channel-conf 01_424 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[66] origin:064-gtp-channel-conf 00_425 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[67] origin:064-gtp-channel-conf 01_425 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[68] origin:064-gtp-channel-conf 00_426 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[69] origin:064-gtp-channel-conf 01_426 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[70] origin:064-gtp-channel-conf 00_427 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[71] origin:064-gtp-channel-conf 01_427 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[72] origin:064-gtp-channel-conf 00_428 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[73] origin:064-gtp-channel-conf 01_428 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[74] origin:064-gtp-channel-conf 00_429 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[75] origin:064-gtp-channel-conf 01_429 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[76] origin:064-gtp-channel-conf 00_430 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[77] origin:064-gtp-channel-conf 01_430 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[78] origin:064-gtp-channel-conf 00_431 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[79] origin:064-gtp-channel-conf 01_431 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[0] origin:064-gtp-channel-conf 00_352 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[1] origin:064-gtp-channel-conf 01_352 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[2] origin:064-gtp-channel-conf 00_353 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[3] origin:064-gtp-channel-conf 01_353 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[4] origin:064-gtp-channel-conf 00_354 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[5] origin:064-gtp-channel-conf 01_354 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[6] origin:064-gtp-channel-conf 00_355 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[7] origin:064-gtp-channel-conf 01_355 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[8] origin:064-gtp-channel-conf 00_356 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[9] origin:064-gtp-channel-conf 01_356 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[10] origin:064-gtp-channel-conf 00_357 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[11] origin:064-gtp-channel-conf 01_357 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[12] origin:064-gtp-channel-conf 00_358 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[13] origin:064-gtp-channel-conf 01_358 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[14] origin:064-gtp-channel-conf 00_359 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[15] origin:064-gtp-channel-conf 01_359 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[16] origin:064-gtp-channel-conf 00_360 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[17] origin:064-gtp-channel-conf 01_360 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[18] origin:064-gtp-channel-conf 00_361 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[19] origin:064-gtp-channel-conf 01_361 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[20] origin:064-gtp-channel-conf 00_362 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[21] origin:064-gtp-channel-conf 01_362 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[22] origin:064-gtp-channel-conf 00_363 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[23] origin:064-gtp-channel-conf 01_363 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[24] origin:064-gtp-channel-conf 00_364 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[25] origin:064-gtp-channel-conf 01_364 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[26] origin:064-gtp-channel-conf 00_365 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[27] origin:064-gtp-channel-conf 01_365 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[28] origin:064-gtp-channel-conf 00_366 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[29] origin:064-gtp-channel-conf 01_366 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[30] origin:064-gtp-channel-conf 00_367 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[31] origin:064-gtp-channel-conf 01_367 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[32] origin:064-gtp-channel-conf 00_368 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[33] origin:064-gtp-channel-conf 01_368 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[34] origin:064-gtp-channel-conf 00_369 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[35] origin:064-gtp-channel-conf 01_369 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[36] origin:064-gtp-channel-conf 00_370 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[37] origin:064-gtp-channel-conf 01_370 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[38] origin:064-gtp-channel-conf 00_371 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[39] origin:064-gtp-channel-conf 01_371 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[40] origin:064-gtp-channel-conf 00_372 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[41] origin:064-gtp-channel-conf 01_372 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[42] origin:064-gtp-channel-conf 00_373 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[43] origin:064-gtp-channel-conf 01_373 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[44] origin:064-gtp-channel-conf 00_374 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[45] origin:064-gtp-channel-conf 01_374 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[46] origin:064-gtp-channel-conf 00_375 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[47] origin:064-gtp-channel-conf 01_375 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[48] origin:064-gtp-channel-conf 00_376 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[49] origin:064-gtp-channel-conf 01_376 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[50] origin:064-gtp-channel-conf 00_377 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[51] origin:064-gtp-channel-conf 01_377 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[52] origin:064-gtp-channel-conf 00_378 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[53] origin:064-gtp-channel-conf 01_378 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[54] origin:064-gtp-channel-conf 00_379 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[55] origin:064-gtp-channel-conf 01_379 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[56] origin:064-gtp-channel-conf 00_380 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[57] origin:064-gtp-channel-conf 01_380 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[58] origin:064-gtp-channel-conf 00_381 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[59] origin:064-gtp-channel-conf 01_381 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[60] origin:064-gtp-channel-conf 00_382 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[61] origin:064-gtp-channel-conf 01_382 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[62] origin:064-gtp-channel-conf 00_383 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[63] origin:064-gtp-channel-conf 01_383 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[64] origin:064-gtp-channel-conf 00_384 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[65] origin:064-gtp-channel-conf 01_384 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[66] origin:064-gtp-channel-conf 00_385 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[67] origin:064-gtp-channel-conf 01_385 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[68] origin:064-gtp-channel-conf 00_386 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[69] origin:064-gtp-channel-conf 01_386 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[70] origin:064-gtp-channel-conf 00_387 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[71] origin:064-gtp-channel-conf 01_387 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[72] origin:064-gtp-channel-conf 00_388 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[73] origin:064-gtp-channel-conf 01_388 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[74] origin:064-gtp-channel-conf 00_389 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[75] origin:064-gtp-channel-conf 01_389 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[76] origin:064-gtp-channel-conf 00_390 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[77] origin:064-gtp-channel-conf 01_390 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[78] origin:064-gtp-channel-conf 00_391 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[79] origin:064-gtp-channel-conf 01_391 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[0] origin:064-gtp-channel-conf 00_432 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[1] origin:064-gtp-channel-conf 01_432 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[2] origin:064-gtp-channel-conf 00_433 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[3] origin:064-gtp-channel-conf 01_433 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[4] origin:064-gtp-channel-conf 00_434 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[5] origin:064-gtp-channel-conf 01_434 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[6] origin:064-gtp-channel-conf 00_435 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[7] origin:064-gtp-channel-conf 01_435 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[8] origin:064-gtp-channel-conf 00_436 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[9] origin:064-gtp-channel-conf 01_436 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[10] origin:064-gtp-channel-conf 00_437 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[11] origin:064-gtp-channel-conf 01_437 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[12] origin:064-gtp-channel-conf 00_438 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[13] origin:064-gtp-channel-conf 01_438 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[14] origin:064-gtp-channel-conf 00_439 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[15] origin:064-gtp-channel-conf 01_439 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[16] origin:064-gtp-channel-conf 00_440 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[17] origin:064-gtp-channel-conf 01_440 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[18] origin:064-gtp-channel-conf 00_441 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[19] origin:064-gtp-channel-conf 01_441 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[20] origin:064-gtp-channel-conf 00_442 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[21] origin:064-gtp-channel-conf 01_442 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[22] origin:064-gtp-channel-conf 00_443 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[23] origin:064-gtp-channel-conf 01_443 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[24] origin:064-gtp-channel-conf 00_444 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[25] origin:064-gtp-channel-conf 01_444 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[26] origin:064-gtp-channel-conf 00_445 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[27] origin:064-gtp-channel-conf 01_445 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[28] origin:064-gtp-channel-conf 00_446 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[29] origin:064-gtp-channel-conf 01_446 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[30] origin:064-gtp-channel-conf 00_447 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[31] origin:064-gtp-channel-conf 01_447 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[32] origin:064-gtp-channel-conf 00_448 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[33] origin:064-gtp-channel-conf 01_448 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[34] origin:064-gtp-channel-conf 00_449 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[35] origin:064-gtp-channel-conf 01_449 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[36] origin:064-gtp-channel-conf 00_450 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[37] origin:064-gtp-channel-conf 01_450 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[38] origin:064-gtp-channel-conf 00_451 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[39] origin:064-gtp-channel-conf 01_451 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[40] origin:064-gtp-channel-conf 00_452 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[41] origin:064-gtp-channel-conf 01_452 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[42] origin:064-gtp-channel-conf 00_453 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[43] origin:064-gtp-channel-conf 01_453 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[44] origin:064-gtp-channel-conf 00_454 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[45] origin:064-gtp-channel-conf 01_454 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[46] origin:064-gtp-channel-conf 00_455 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[47] origin:064-gtp-channel-conf 01_455 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[48] origin:064-gtp-channel-conf 00_456 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[49] origin:064-gtp-channel-conf 01_456 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[50] origin:064-gtp-channel-conf 00_457 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[51] origin:064-gtp-channel-conf 01_457 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[52] origin:064-gtp-channel-conf 00_458 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[53] origin:064-gtp-channel-conf 01_458 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[54] origin:064-gtp-channel-conf 00_459 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[55] origin:064-gtp-channel-conf 01_459 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[56] origin:064-gtp-channel-conf 00_460 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[57] origin:064-gtp-channel-conf 01_460 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[58] origin:064-gtp-channel-conf 00_461 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[59] origin:064-gtp-channel-conf 01_461 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[60] origin:064-gtp-channel-conf 00_462 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[61] origin:064-gtp-channel-conf 01_462 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[62] origin:064-gtp-channel-conf 00_463 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[63] origin:064-gtp-channel-conf 01_463 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[64] origin:064-gtp-channel-conf 00_464 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[65] origin:064-gtp-channel-conf 01_464 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[66] origin:064-gtp-channel-conf 00_465 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[67] origin:064-gtp-channel-conf 01_465 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[68] origin:064-gtp-channel-conf 00_466 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[69] origin:064-gtp-channel-conf 01_466 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[70] origin:064-gtp-channel-conf 00_467 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[71] origin:064-gtp-channel-conf 01_467 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[72] origin:064-gtp-channel-conf 00_468 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[73] origin:064-gtp-channel-conf 01_468 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[74] origin:064-gtp-channel-conf 00_469 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[75] origin:064-gtp-channel-conf 01_469 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[76] origin:064-gtp-channel-conf 00_470 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[77] origin:064-gtp-channel-conf 01_470 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[78] origin:064-gtp-channel-conf 00_471 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[79] origin:064-gtp-channel-conf 01_471 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_VERT_OFFSET[0] origin:064-gtp-channel-conf 00_472 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_VERT_OFFSET[1] origin:064-gtp-channel-conf 01_472 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_VERT_OFFSET[2] origin:064-gtp-channel-conf 00_473 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_VERT_OFFSET[3] origin:064-gtp-channel-conf 01_473 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_VERT_OFFSET[4] origin:064-gtp-channel-conf 00_474 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_VERT_OFFSET[5] origin:064-gtp-channel-conf 01_474 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_VERT_OFFSET[6] origin:064-gtp-channel-conf 00_475 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_VERT_OFFSET[7] origin:064-gtp-channel-conf 01_475 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.ES_VERT_OFFSET[8] origin:064-gtp-channel-conf 00_476 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.FTS_DESKEW_SEQ_ENABLE[0] origin:064-gtp-channel-conf 00_662 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.FTS_DESKEW_SEQ_ENABLE[1] origin:064-gtp-channel-conf 01_662 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.FTS_DESKEW_SEQ_ENABLE[2] origin:064-gtp-channel-conf 00_663 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.FTS_DESKEW_SEQ_ENABLE[3] origin:064-gtp-channel-conf 01_663 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.FTS_LANE_DESKEW_CFG[0] origin:064-gtp-channel-conf 00_654 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.FTS_LANE_DESKEW_CFG[1] origin:064-gtp-channel-conf 01_654 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.FTS_LANE_DESKEW_CFG[2] origin:064-gtp-channel-conf 00_655 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.FTS_LANE_DESKEW_CFG[3] origin:064-gtp-channel-conf 01_655 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.FTS_LANE_DESKEW_EN origin:064-gtp-channel-conf 01_653 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.GEARBOX_MODE[0] origin:064-gtp-channel-conf 00_224 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.GEARBOX_MODE[1] origin:064-gtp-channel-conf 01_224 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.GEARBOX_MODE[2] origin:064-gtp-channel-conf 00_225 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.IN_USE origin:064-gtp-channel-conf 00_00 00_01 00_47 00_52 00_53 00_65 01_01 01_47 02_129 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.INV_DMONITORCLK origin:064-gtp-channel-conf 02_13 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.INV_DRPCLK origin:064-gtp-channel-conf 02_00 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.INV_RXUSRCLK origin:064-gtp-channel-conf 03_01 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.INV_SIGVALIDCLK origin:064-gtp-channel-conf 03_13 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.INV_TXPHDLYTSTCLK origin:064-gtp-channel-conf 02_03 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.INV_TXUSRCLK origin:064-gtp-channel-conf 03_04 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.INV_CLKRSVD0 origin:064-gtp-channel-conf 02_23 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.INV_CLKRSVD1 origin:064-gtp-channel-conf 03_23 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.INV_RXUSRCLK2 origin:064-gtp-channel-conf 02_02 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.INV_TXUSRCLK2 origin:064-gtp-channel-conf 02_05 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.LOOPBACK_CFG[0] origin:064-gtp-channel-conf 02_20 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.OUTREFCLK_SEL_INV[0] origin:064-gtp-channel-conf 00_149 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.OUTREFCLK_SEL_INV[1] origin:064-gtp-channel-conf 01_149 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PCS_PCIE_EN origin:064-gtp-channel-conf 00_216 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[0] origin:064-gtp-channel-conf 02_184 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[1] origin:064-gtp-channel-conf 03_184 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[2] origin:064-gtp-channel-conf 02_185 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[3] origin:064-gtp-channel-conf 03_185 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[4] origin:064-gtp-channel-conf 02_186 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[5] origin:064-gtp-channel-conf 03_186 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[6] origin:064-gtp-channel-conf 02_187 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[7] origin:064-gtp-channel-conf 03_187 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[8] origin:064-gtp-channel-conf 02_188 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[9] origin:064-gtp-channel-conf 03_188 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[10] origin:064-gtp-channel-conf 02_189 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[11] origin:064-gtp-channel-conf 03_189 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[12] origin:064-gtp-channel-conf 02_190 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[13] origin:064-gtp-channel-conf 03_190 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[14] origin:064-gtp-channel-conf 02_191 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[15] origin:064-gtp-channel-conf 03_191 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[16] origin:064-gtp-channel-conf 02_192 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[17] origin:064-gtp-channel-conf 03_192 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[18] origin:064-gtp-channel-conf 02_193 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[19] origin:064-gtp-channel-conf 03_193 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[20] origin:064-gtp-channel-conf 02_194 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[21] origin:064-gtp-channel-conf 03_194 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[22] origin:064-gtp-channel-conf 02_195 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[23] origin:064-gtp-channel-conf 03_195 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[24] origin:064-gtp-channel-conf 02_196 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[25] origin:064-gtp-channel-conf 03_196 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[26] origin:064-gtp-channel-conf 02_197 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[27] origin:064-gtp-channel-conf 03_197 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[28] origin:064-gtp-channel-conf 02_198 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[29] origin:064-gtp-channel-conf 03_198 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[30] origin:064-gtp-channel-conf 02_199 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[31] origin:064-gtp-channel-conf 03_199 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[32] origin:064-gtp-channel-conf 02_200 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[33] origin:064-gtp-channel-conf 03_200 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[34] origin:064-gtp-channel-conf 02_201 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[35] origin:064-gtp-channel-conf 03_201 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[36] origin:064-gtp-channel-conf 02_202 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[37] origin:064-gtp-channel-conf 03_202 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[38] origin:064-gtp-channel-conf 02_203 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[39] origin:064-gtp-channel-conf 03_203 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[40] origin:064-gtp-channel-conf 02_204 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[41] origin:064-gtp-channel-conf 03_204 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[42] origin:064-gtp-channel-conf 02_205 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[43] origin:064-gtp-channel-conf 03_205 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[44] origin:064-gtp-channel-conf 02_206 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[45] origin:064-gtp-channel-conf 03_206 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[46] origin:064-gtp-channel-conf 02_207 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[47] origin:064-gtp-channel-conf 03_207 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[0] origin:064-gtp-channel-conf 01_216 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[1] origin:064-gtp-channel-conf 00_217 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[2] origin:064-gtp-channel-conf 01_217 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[3] origin:064-gtp-channel-conf 00_218 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[4] origin:064-gtp-channel-conf 01_218 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[5] origin:064-gtp-channel-conf 00_219 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[6] origin:064-gtp-channel-conf 01_219 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[7] origin:064-gtp-channel-conf 00_220 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[8] origin:064-gtp-channel-conf 01_220 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[9] origin:064-gtp-channel-conf 00_221 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[10] origin:064-gtp-channel-conf 01_221 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[11] origin:064-gtp-channel-conf 00_222 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[0] origin:064-gtp-channel-conf 00_208 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[1] origin:064-gtp-channel-conf 01_208 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[2] origin:064-gtp-channel-conf 00_209 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[3] origin:064-gtp-channel-conf 01_209 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[4] origin:064-gtp-channel-conf 00_210 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[5] origin:064-gtp-channel-conf 01_210 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[6] origin:064-gtp-channel-conf 00_211 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[7] origin:064-gtp-channel-conf 01_211 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[0] origin:064-gtp-channel-conf 00_212 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[1] origin:064-gtp-channel-conf 01_212 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[2] origin:064-gtp-channel-conf 00_213 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[3] origin:064-gtp-channel-conf 01_213 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[4] origin:064-gtp-channel-conf 00_214 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[5] origin:064-gtp-channel-conf 01_214 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[6] origin:064-gtp-channel-conf 00_215 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[7] origin:064-gtp-channel-conf 01_215 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PMA_LOOPBACK_CFG[0] origin:064-gtp-channel-conf 01_207 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[0] origin:064-gtp-channel-conf 02_520 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[1] origin:064-gtp-channel-conf 03_520 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[2] origin:064-gtp-channel-conf 02_521 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[3] origin:064-gtp-channel-conf 03_521 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[4] origin:064-gtp-channel-conf 02_522 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[5] origin:064-gtp-channel-conf 03_522 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[6] origin:064-gtp-channel-conf 02_523 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[7] origin:064-gtp-channel-conf 03_523 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[8] origin:064-gtp-channel-conf 02_524 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[9] origin:064-gtp-channel-conf 03_524 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[10] origin:064-gtp-channel-conf 02_525 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[11] origin:064-gtp-channel-conf 03_525 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[12] origin:064-gtp-channel-conf 02_526 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[13] origin:064-gtp-channel-conf 03_526 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[14] origin:064-gtp-channel-conf 02_527 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[15] origin:064-gtp-channel-conf 03_527 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[16] origin:064-gtp-channel-conf 02_528 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[17] origin:064-gtp-channel-conf 03_528 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[18] origin:064-gtp-channel-conf 02_529 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[19] origin:064-gtp-channel-conf 03_529 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[20] origin:064-gtp-channel-conf 02_530 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[21] origin:064-gtp-channel-conf 03_530 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[22] origin:064-gtp-channel-conf 02_531 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[23] origin:064-gtp-channel-conf 03_531 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[24] origin:064-gtp-channel-conf 02_532 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[25] origin:064-gtp-channel-conf 03_532 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[26] origin:064-gtp-channel-conf 02_533 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[27] origin:064-gtp-channel-conf 03_533 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[28] origin:064-gtp-channel-conf 02_534 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[29] origin:064-gtp-channel-conf 03_534 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[30] origin:064-gtp-channel-conf 02_535 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[31] origin:064-gtp-channel-conf 03_535 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[0] origin:064-gtp-channel-conf 02_336 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[1] origin:064-gtp-channel-conf 03_336 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[2] origin:064-gtp-channel-conf 02_337 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[3] origin:064-gtp-channel-conf 03_337 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[4] origin:064-gtp-channel-conf 02_338 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[5] origin:064-gtp-channel-conf 03_338 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[6] origin:064-gtp-channel-conf 02_339 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[7] origin:064-gtp-channel-conf 03_339 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[8] origin:064-gtp-channel-conf 02_340 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[9] origin:064-gtp-channel-conf 03_340 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[10] origin:064-gtp-channel-conf 02_341 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[11] origin:064-gtp-channel-conf 03_341 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[12] origin:064-gtp-channel-conf 02_342 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[13] origin:064-gtp-channel-conf 03_342 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[14] origin:064-gtp-channel-conf 02_343 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[15] origin:064-gtp-channel-conf 03_343 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[16] origin:064-gtp-channel-conf 02_344 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[17] origin:064-gtp-channel-conf 03_344 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[18] origin:064-gtp-channel-conf 02_345 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[19] origin:064-gtp-channel-conf 03_345 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[20] origin:064-gtp-channel-conf 02_346 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[21] origin:064-gtp-channel-conf 03_346 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[22] origin:064-gtp-channel-conf 02_347 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[23] origin:064-gtp-channel-conf 03_347 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[24] origin:064-gtp-channel-conf 02_348 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[25] origin:064-gtp-channel-conf 03_348 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[26] origin:064-gtp-channel-conf 02_349 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[27] origin:064-gtp-channel-conf 03_349 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[28] origin:064-gtp-channel-conf 02_350 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[29] origin:064-gtp-channel-conf 03_350 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[30] origin:064-gtp-channel-conf 02_351 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[31] origin:064-gtp-channel-conf 03_351 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV3[0] origin:064-gtp-channel-conf 02_288 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV3[1] origin:064-gtp-channel-conf 03_288 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV4[0] origin:064-gtp-channel-conf 02_156 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV4[1] origin:064-gtp-channel-conf 03_156 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV4[2] origin:064-gtp-channel-conf 02_157 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV4[3] origin:064-gtp-channel-conf 03_157 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV5[0] origin:064-gtp-channel-conf 03_159 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV6[0] origin:064-gtp-channel-conf 02_303 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV7[0] origin:064-gtp-channel-conf 03_303 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_BIAS_CFG[0] origin:064-gtp-channel-conf 02_112 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_BIAS_CFG[1] origin:064-gtp-channel-conf 03_112 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_BIAS_CFG[2] origin:064-gtp-channel-conf 02_113 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_BIAS_CFG[3] origin:064-gtp-channel-conf 03_113 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_BIAS_CFG[4] origin:064-gtp-channel-conf 02_114 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_BIAS_CFG[5] origin:064-gtp-channel-conf 03_114 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_BIAS_CFG[6] origin:064-gtp-channel-conf 02_115 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_BIAS_CFG[7] origin:064-gtp-channel-conf 03_115 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_BIAS_CFG[8] origin:064-gtp-channel-conf 02_116 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_BIAS_CFG[9] origin:064-gtp-channel-conf 03_116 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_BIAS_CFG[10] origin:064-gtp-channel-conf 02_117 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_BIAS_CFG[11] origin:064-gtp-channel-conf 03_117 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_BIAS_CFG[12] origin:064-gtp-channel-conf 02_118 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_BIAS_CFG[13] origin:064-gtp-channel-conf 03_118 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_BIAS_CFG[14] origin:064-gtp-channel-conf 02_119 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_BIAS_CFG[15] origin:064-gtp-channel-conf 03_119 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_BUFFER_CFG[0] origin:064-gtp-channel-conf 02_536 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_BUFFER_CFG[1] origin:064-gtp-channel-conf 03_536 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_BUFFER_CFG[2] origin:064-gtp-channel-conf 02_537 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_BUFFER_CFG[3] origin:064-gtp-channel-conf 03_537 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_BUFFER_CFG[4] origin:064-gtp-channel-conf 02_538 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_BUFFER_CFG[5] origin:064-gtp-channel-conf 03_538 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_CLKMUX_EN[0] origin:064-gtp-channel-conf 02_128 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_CM_SEL[0] origin:064-gtp-channel-conf 00_138 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_CM_SEL[1] origin:064-gtp-channel-conf 01_138 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_CM_TRIM[0] origin:064-gtp-channel-conf 02_304 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_CM_TRIM[1] origin:064-gtp-channel-conf 03_304 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_CM_TRIM[2] origin:064-gtp-channel-conf 02_305 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_CM_TRIM[3] origin:064-gtp-channel-conf 03_305 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_DATA_WIDTH[0] origin:064-gtp-channel-conf 01_141 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_DATA_WIDTH[1] origin:064-gtp-channel-conf 00_142 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_DATA_WIDTH[2] origin:064-gtp-channel-conf 01_142 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_DDI_SEL[0] origin:064-gtp-channel-conf 00_696 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_DDI_SEL[1] origin:064-gtp-channel-conf 01_696 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_DDI_SEL[2] origin:064-gtp-channel-conf 00_697 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_DDI_SEL[3] origin:064-gtp-channel-conf 01_697 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_DDI_SEL[4] origin:064-gtp-channel-conf 00_698 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_DDI_SEL[5] origin:064-gtp-channel-conf 01_698 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_DEBUG_CFG[0] origin:064-gtp-channel-conf 02_616 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_DEBUG_CFG[1] origin:064-gtp-channel-conf 03_616 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_DEBUG_CFG[2] origin:064-gtp-channel-conf 02_617 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_DEBUG_CFG[3] origin:064-gtp-channel-conf 03_617 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_DEBUG_CFG[4] origin:064-gtp-channel-conf 02_618 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_DEBUG_CFG[5] origin:064-gtp-channel-conf 03_618 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_DEBUG_CFG[6] origin:064-gtp-channel-conf 02_619 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_DEBUG_CFG[7] origin:064-gtp-channel-conf 03_619 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_DEBUG_CFG[8] origin:064-gtp-channel-conf 02_620 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_DEBUG_CFG[9] origin:064-gtp-channel-conf 03_620 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_DEBUG_CFG[10] origin:064-gtp-channel-conf 02_621 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_DEBUG_CFG[11] origin:064-gtp-channel-conf 03_621 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_DEBUG_CFG[12] origin:064-gtp-channel-conf 02_622 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_DEBUG_CFG[13] origin:064-gtp-channel-conf 03_622 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_DEFER_RESET_BUF_EN origin:064-gtp-channel-conf 02_552 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_DISPERR_SEQ_MATCH origin:064-gtp-channel-conf 01_495 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_OS_CFG[0] origin:064-gtp-channel-conf 00_288 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_OS_CFG[1] origin:064-gtp-channel-conf 01_288 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_OS_CFG[2] origin:064-gtp-channel-conf 00_289 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_OS_CFG[3] origin:064-gtp-channel-conf 01_289 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_OS_CFG[4] origin:064-gtp-channel-conf 00_290 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_OS_CFG[5] origin:064-gtp-channel-conf 01_290 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_OS_CFG[6] origin:064-gtp-channel-conf 00_291 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_OS_CFG[7] origin:064-gtp-channel-conf 01_291 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_OS_CFG[8] origin:064-gtp-channel-conf 00_292 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_OS_CFG[9] origin:064-gtp-channel-conf 01_292 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_OS_CFG[10] origin:064-gtp-channel-conf 00_293 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_OS_CFG[11] origin:064-gtp-channel-conf 01_293 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_OS_CFG[12] origin:064-gtp-channel-conf 00_294 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_SIG_VALID_DLY[0] origin:064-gtp-channel-conf 00_524 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_SIG_VALID_DLY[1] origin:064-gtp-channel-conf 01_524 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_SIG_VALID_DLY[2] origin:064-gtp-channel-conf 00_525 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_SIG_VALID_DLY[3] origin:064-gtp-channel-conf 01_525 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_SIG_VALID_DLY[4] origin:064-gtp-channel-conf 00_526 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_XCLK_SEL.RXUSR origin:064-gtp-channel-conf 00_143 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_CLK25_DIV[0] origin:064-gtp-channel-conf 00_139 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_CLK25_DIV[1] origin:064-gtp-channel-conf 01_139 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_CLK25_DIV[2] origin:064-gtp-channel-conf 00_140 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_CLK25_DIV[3] origin:064-gtp-channel-conf 01_140 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RX_CLK25_DIV[4] origin:064-gtp-channel-conf 00_141 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXBUF_ADDR_MODE.FAST origin:064-gtp-channel-conf 03_555 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXBUF_EIDLE_HI_CNT[0] origin:064-gtp-channel-conf 02_558 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXBUF_EIDLE_HI_CNT[1] origin:064-gtp-channel-conf 03_558 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXBUF_EIDLE_HI_CNT[2] origin:064-gtp-channel-conf 02_559 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXBUF_EIDLE_HI_CNT[3] origin:064-gtp-channel-conf 03_559 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXBUF_EIDLE_LO_CNT[0] origin:064-gtp-channel-conf 02_556 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXBUF_EIDLE_LO_CNT[1] origin:064-gtp-channel-conf 03_556 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXBUF_EIDLE_LO_CNT[2] origin:064-gtp-channel-conf 02_557 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXBUF_EIDLE_LO_CNT[3] origin:064-gtp-channel-conf 03_557 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXBUF_EN origin:064-gtp-channel-conf 02_11 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXBUF_RESET_ON_CB_CHANGE origin:064-gtp-channel-conf 02_560 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXBUF_RESET_ON_COMMAALIGN origin:064-gtp-channel-conf 02_561 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXBUF_RESET_ON_EIDLE origin:064-gtp-channel-conf 02_547 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXBUF_RESET_ON_RATE_CHANGE origin:064-gtp-channel-conf 03_560 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXBUF_THRESH_OVFLW[0] origin:064-gtp-channel-conf 03_552 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXBUF_THRESH_OVFLW[1] origin:064-gtp-channel-conf 02_553 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXBUF_THRESH_OVFLW[2] origin:064-gtp-channel-conf 03_553 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXBUF_THRESH_OVFLW[3] origin:064-gtp-channel-conf 02_554 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXBUF_THRESH_OVFLW[4] origin:064-gtp-channel-conf 03_554 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXBUF_THRESH_OVFLW[5] origin:064-gtp-channel-conf 02_555 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXBUF_THRESH_OVRD origin:064-gtp-channel-conf 02_548 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXBUF_THRESH_UNDFLW[0] origin:064-gtp-channel-conf 02_544 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXBUF_THRESH_UNDFLW[1] origin:064-gtp-channel-conf 03_544 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXBUF_THRESH_UNDFLW[2] origin:064-gtp-channel-conf 02_545 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXBUF_THRESH_UNDFLW[3] origin:064-gtp-channel-conf 03_545 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXBUF_THRESH_UNDFLW[4] origin:064-gtp-channel-conf 02_546 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXBUF_THRESH_UNDFLW[5] origin:064-gtp-channel-conf 03_546 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXBUFRESET_TIME[0] origin:064-gtp-channel-conf 01_101 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXBUFRESET_TIME[1] origin:064-gtp-channel-conf 00_102 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXBUFRESET_TIME[2] origin:064-gtp-channel-conf 01_102 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXBUFRESET_TIME[3] origin:064-gtp-channel-conf 00_103 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXBUFRESET_TIME[4] origin:064-gtp-channel-conf 01_103 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[0] origin:064-gtp-channel-conf 02_640 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[1] origin:064-gtp-channel-conf 03_640 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[2] origin:064-gtp-channel-conf 02_641 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[3] origin:064-gtp-channel-conf 03_641 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[4] origin:064-gtp-channel-conf 02_642 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[5] origin:064-gtp-channel-conf 03_642 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[6] origin:064-gtp-channel-conf 02_643 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[7] origin:064-gtp-channel-conf 03_643 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[8] origin:064-gtp-channel-conf 02_644 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[9] origin:064-gtp-channel-conf 03_644 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[10] origin:064-gtp-channel-conf 02_645 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[11] origin:064-gtp-channel-conf 03_645 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[12] origin:064-gtp-channel-conf 02_646 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[13] origin:064-gtp-channel-conf 03_646 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[14] origin:064-gtp-channel-conf 02_647 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[15] origin:064-gtp-channel-conf 03_647 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[16] origin:064-gtp-channel-conf 02_648 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[17] origin:064-gtp-channel-conf 03_648 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[18] origin:064-gtp-channel-conf 02_649 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[19] origin:064-gtp-channel-conf 03_649 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[20] origin:064-gtp-channel-conf 02_650 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[21] origin:064-gtp-channel-conf 03_650 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[22] origin:064-gtp-channel-conf 02_651 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[23] origin:064-gtp-channel-conf 03_651 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[24] origin:064-gtp-channel-conf 02_652 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[25] origin:064-gtp-channel-conf 03_652 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[26] origin:064-gtp-channel-conf 02_653 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[27] origin:064-gtp-channel-conf 03_653 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[28] origin:064-gtp-channel-conf 02_654 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[29] origin:064-gtp-channel-conf 03_654 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[30] origin:064-gtp-channel-conf 02_655 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[31] origin:064-gtp-channel-conf 03_655 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[32] origin:064-gtp-channel-conf 02_656 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[33] origin:064-gtp-channel-conf 03_656 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[34] origin:064-gtp-channel-conf 02_657 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[35] origin:064-gtp-channel-conf 03_657 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[36] origin:064-gtp-channel-conf 02_658 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[37] origin:064-gtp-channel-conf 03_658 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[38] origin:064-gtp-channel-conf 02_659 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[39] origin:064-gtp-channel-conf 03_659 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[40] origin:064-gtp-channel-conf 02_660 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[41] origin:064-gtp-channel-conf 03_660 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[42] origin:064-gtp-channel-conf 02_661 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[43] origin:064-gtp-channel-conf 03_661 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[44] origin:064-gtp-channel-conf 02_662 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[45] origin:064-gtp-channel-conf 03_662 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[46] origin:064-gtp-channel-conf 02_663 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[47] origin:064-gtp-channel-conf 03_663 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[48] origin:064-gtp-channel-conf 02_664 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[49] origin:064-gtp-channel-conf 03_664 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[50] origin:064-gtp-channel-conf 02_665 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[51] origin:064-gtp-channel-conf 03_665 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[52] origin:064-gtp-channel-conf 02_666 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[53] origin:064-gtp-channel-conf 03_666 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[54] origin:064-gtp-channel-conf 02_667 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[55] origin:064-gtp-channel-conf 03_667 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[56] origin:064-gtp-channel-conf 02_668 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[57] origin:064-gtp-channel-conf 03_668 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[58] origin:064-gtp-channel-conf 02_669 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[59] origin:064-gtp-channel-conf 03_669 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[60] origin:064-gtp-channel-conf 02_670 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[61] origin:064-gtp-channel-conf 03_670 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[62] origin:064-gtp-channel-conf 02_671 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[63] origin:064-gtp-channel-conf 03_671 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[64] origin:064-gtp-channel-conf 02_672 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[65] origin:064-gtp-channel-conf 03_672 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[66] origin:064-gtp-channel-conf 02_673 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[67] origin:064-gtp-channel-conf 03_673 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[68] origin:064-gtp-channel-conf 02_674 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[69] origin:064-gtp-channel-conf 03_674 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[70] origin:064-gtp-channel-conf 02_675 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[71] origin:064-gtp-channel-conf 03_675 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[72] origin:064-gtp-channel-conf 02_676 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[73] origin:064-gtp-channel-conf 03_676 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[74] origin:064-gtp-channel-conf 02_677 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[75] origin:064-gtp-channel-conf 03_677 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[76] origin:064-gtp-channel-conf 02_678 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[77] origin:064-gtp-channel-conf 03_678 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[78] origin:064-gtp-channel-conf 02_679 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[79] origin:064-gtp-channel-conf 03_679 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[80] origin:064-gtp-channel-conf 02_680 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[81] origin:064-gtp-channel-conf 03_680 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[82] origin:064-gtp-channel-conf 02_681 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_FR_RESET_ON_EIDLE[0] origin:064-gtp-channel-conf 02_638 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_HOLD_DURING_EIDLE[0] origin:064-gtp-channel-conf 03_637 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_LOCK_CFG[0] origin:064-gtp-channel-conf 02_632 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_LOCK_CFG[1] origin:064-gtp-channel-conf 03_632 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_LOCK_CFG[2] origin:064-gtp-channel-conf 02_633 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_LOCK_CFG[3] origin:064-gtp-channel-conf 03_633 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_LOCK_CFG[4] origin:064-gtp-channel-conf 02_634 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_LOCK_CFG[5] origin:064-gtp-channel-conf 03_634 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDR_PH_RESET_ON_EIDLE[0] origin:064-gtp-channel-conf 03_638 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDRFREQRESET_TIME[0] origin:064-gtp-channel-conf 01_106 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDRFREQRESET_TIME[1] origin:064-gtp-channel-conf 00_107 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDRFREQRESET_TIME[2] origin:064-gtp-channel-conf 01_107 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDRFREQRESET_TIME[3] origin:064-gtp-channel-conf 00_108 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDRFREQRESET_TIME[4] origin:064-gtp-channel-conf 01_108 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDRPHRESET_TIME[0] origin:064-gtp-channel-conf 00_109 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDRPHRESET_TIME[1] origin:064-gtp-channel-conf 01_109 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDRPHRESET_TIME[2] origin:064-gtp-channel-conf 00_110 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDRPHRESET_TIME[3] origin:064-gtp-channel-conf 01_110 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXCDRPHRESET_TIME[4] origin:064-gtp-channel-conf 00_111 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXDLY_CFG[0] origin:064-gtp-channel-conf 00_680 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXDLY_CFG[1] origin:064-gtp-channel-conf 01_680 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXDLY_CFG[2] origin:064-gtp-channel-conf 00_681 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXDLY_CFG[3] origin:064-gtp-channel-conf 01_681 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXDLY_CFG[4] origin:064-gtp-channel-conf 00_682 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXDLY_CFG[5] origin:064-gtp-channel-conf 01_682 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXDLY_CFG[6] origin:064-gtp-channel-conf 00_683 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXDLY_CFG[7] origin:064-gtp-channel-conf 01_683 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXDLY_CFG[8] origin:064-gtp-channel-conf 00_684 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXDLY_CFG[9] origin:064-gtp-channel-conf 01_684 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXDLY_CFG[10] origin:064-gtp-channel-conf 00_685 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXDLY_CFG[11] origin:064-gtp-channel-conf 01_685 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXDLY_CFG[12] origin:064-gtp-channel-conf 00_686 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXDLY_CFG[13] origin:064-gtp-channel-conf 01_686 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXDLY_CFG[14] origin:064-gtp-channel-conf 00_687 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXDLY_CFG[15] origin:064-gtp-channel-conf 01_687 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXDLY_LCFG[0] origin:064-gtp-channel-conf 02_576 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXDLY_LCFG[1] origin:064-gtp-channel-conf 03_576 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXDLY_LCFG[2] origin:064-gtp-channel-conf 02_577 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXDLY_LCFG[3] origin:064-gtp-channel-conf 03_577 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXDLY_LCFG[4] origin:064-gtp-channel-conf 02_578 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXDLY_LCFG[5] origin:064-gtp-channel-conf 03_578 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXDLY_LCFG[6] origin:064-gtp-channel-conf 02_579 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXDLY_LCFG[7] origin:064-gtp-channel-conf 03_579 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXDLY_LCFG[8] origin:064-gtp-channel-conf 02_580 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXDLY_TAP_CFG[0] origin:064-gtp-channel-conf 00_672 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXDLY_TAP_CFG[1] origin:064-gtp-channel-conf 01_672 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXDLY_TAP_CFG[2] origin:064-gtp-channel-conf 00_673 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXDLY_TAP_CFG[3] origin:064-gtp-channel-conf 01_673 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXDLY_TAP_CFG[4] origin:064-gtp-channel-conf 00_674 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXDLY_TAP_CFG[5] origin:064-gtp-channel-conf 01_674 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXDLY_TAP_CFG[6] origin:064-gtp-channel-conf 00_675 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXDLY_TAP_CFG[7] origin:064-gtp-channel-conf 01_675 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXDLY_TAP_CFG[8] origin:064-gtp-channel-conf 00_676 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXDLY_TAP_CFG[9] origin:064-gtp-channel-conf 01_676 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXDLY_TAP_CFG[10] origin:064-gtp-channel-conf 00_677 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXDLY_TAP_CFG[11] origin:064-gtp-channel-conf 01_677 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXDLY_TAP_CFG[12] origin:064-gtp-channel-conf 00_678 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXDLY_TAP_CFG[13] origin:064-gtp-channel-conf 01_678 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXDLY_TAP_CFG[14] origin:064-gtp-channel-conf 00_679 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXDLY_TAP_CFG[15] origin:064-gtp-channel-conf 01_679 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXGEARBOX_EN origin:064-gtp-channel-conf 01_607 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXISCANRESET_TIME[0] origin:064-gtp-channel-conf 01_123 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXISCANRESET_TIME[1] origin:064-gtp-channel-conf 00_124 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXISCANRESET_TIME[2] origin:064-gtp-channel-conf 01_124 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXISCANRESET_TIME[3] origin:064-gtp-channel-conf 00_125 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXISCANRESET_TIME[4] origin:064-gtp-channel-conf 01_125 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPM_BIAS_STARTUP_DISABLE[0] origin:064-gtp-channel-conf 03_391 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPM_CFG[0] origin:064-gtp-channel-conf 02_328 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPM_CFG[1] origin:064-gtp-channel-conf 03_328 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPM_CFG[2] origin:064-gtp-channel-conf 02_329 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPM_CFG[3] origin:064-gtp-channel-conf 03_329 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPM_CM_CFG[0] origin:064-gtp-channel-conf 02_430 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPM_GC_CFG[0] origin:064-gtp-channel-conf 02_432 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPM_GC_CFG[1] origin:064-gtp-channel-conf 03_432 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPM_GC_CFG[2] origin:064-gtp-channel-conf 02_433 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPM_GC_CFG[3] origin:064-gtp-channel-conf 03_433 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPM_GC_CFG[4] origin:064-gtp-channel-conf 02_434 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPM_GC_CFG[5] origin:064-gtp-channel-conf 03_434 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPM_GC_CFG[6] origin:064-gtp-channel-conf 02_435 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPM_GC_CFG[7] origin:064-gtp-channel-conf 03_435 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPM_GC_CFG[8] origin:064-gtp-channel-conf 02_436 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPM_GC_CFG2[0] origin:064-gtp-channel-conf 03_442 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPM_GC_CFG2[1] origin:064-gtp-channel-conf 02_443 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPM_GC_CFG2[2] origin:064-gtp-channel-conf 03_443 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG[0] origin:064-gtp-channel-conf 00_336 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG[1] origin:064-gtp-channel-conf 01_336 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG[2] origin:064-gtp-channel-conf 00_337 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG[3] origin:064-gtp-channel-conf 01_337 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG[4] origin:064-gtp-channel-conf 00_338 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG[5] origin:064-gtp-channel-conf 01_338 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG[6] origin:064-gtp-channel-conf 00_339 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG[7] origin:064-gtp-channel-conf 01_339 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG[8] origin:064-gtp-channel-conf 00_340 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG[9] origin:064-gtp-channel-conf 01_340 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG[10] origin:064-gtp-channel-conf 00_341 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG[11] origin:064-gtp-channel-conf 01_341 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG[12] origin:064-gtp-channel-conf 00_342 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG[13] origin:064-gtp-channel-conf 01_342 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG2[0] origin:064-gtp-channel-conf 02_424 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG2[1] origin:064-gtp-channel-conf 03_424 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG2[2] origin:064-gtp-channel-conf 02_425 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG2[3] origin:064-gtp-channel-conf 03_425 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG2[4] origin:064-gtp-channel-conf 02_426 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG3[0] origin:064-gtp-channel-conf 03_389 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG3[1] origin:064-gtp-channel-conf 02_390 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG3[2] origin:064-gtp-channel-conf 03_390 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG3[3] origin:064-gtp-channel-conf 02_391 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HOLD_DURING_EIDLE[0] origin:064-gtp-channel-conf 00_247 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPM_INCM_CFG[0] origin:064-gtp-channel-conf 02_439 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPM_IPCM_CFG[0] origin:064-gtp-channel-conf 03_439 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG[0] origin:064-gtp-channel-conf 00_344 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG[1] origin:064-gtp-channel-conf 01_344 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG[2] origin:064-gtp-channel-conf 00_345 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG[3] origin:064-gtp-channel-conf 01_345 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG[4] origin:064-gtp-channel-conf 00_346 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG[5] origin:064-gtp-channel-conf 01_346 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG[6] origin:064-gtp-channel-conf 00_347 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG[7] origin:064-gtp-channel-conf 01_347 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG[8] origin:064-gtp-channel-conf 00_348 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG[9] origin:064-gtp-channel-conf 01_348 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG[10] origin:064-gtp-channel-conf 00_349 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG[11] origin:064-gtp-channel-conf 01_349 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG[12] origin:064-gtp-channel-conf 00_350 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG[13] origin:064-gtp-channel-conf 01_350 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG[14] origin:064-gtp-channel-conf 00_351 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG[15] origin:064-gtp-channel-conf 01_351 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG[16] origin:064-gtp-channel-conf 00_343 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG[17] origin:064-gtp-channel-conf 01_343 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG2[0] origin:064-gtp-channel-conf 03_426 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG2[1] origin:064-gtp-channel-conf 02_427 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG2[2] origin:064-gtp-channel-conf 03_427 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG2[3] origin:064-gtp-channel-conf 02_428 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG2[4] origin:064-gtp-channel-conf 03_428 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPM_OSINT_CFG[0] origin:064-gtp-channel-conf 02_440 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPM_OSINT_CFG[1] origin:064-gtp-channel-conf 03_440 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPM_OSINT_CFG[2] origin:064-gtp-channel-conf 02_441 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPM_CFG1[0] origin:064-gtp-channel-conf 02_330 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPMRESET_TIME[0] origin:064-gtp-channel-conf 00_112 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPMRESET_TIME[1] origin:064-gtp-channel-conf 01_112 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPMRESET_TIME[2] origin:064-gtp-channel-conf 00_113 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPMRESET_TIME[3] origin:064-gtp-channel-conf 01_113 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPMRESET_TIME[4] origin:064-gtp-channel-conf 00_114 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPMRESET_TIME[5] origin:064-gtp-channel-conf 01_114 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXLPMRESET_TIME[6] origin:064-gtp-channel-conf 00_115 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXOOB_CFG[0] origin:064-gtp-channel-conf 00_144 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXOOB_CFG[1] origin:064-gtp-channel-conf 01_144 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXOOB_CFG[2] origin:064-gtp-channel-conf 00_145 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXOOB_CFG[3] origin:064-gtp-channel-conf 01_145 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXOOB_CFG[4] origin:064-gtp-channel-conf 00_146 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXOOB_CFG[5] origin:064-gtp-channel-conf 01_146 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXOOB_CFG[6] origin:064-gtp-channel-conf 00_147 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXOOB_CLK_CFG.FABRIC origin:064-gtp-channel-conf 03_129 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXOSCALRESET_TIME[0] origin:064-gtp-channel-conf 00_187 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXOSCALRESET_TIME[1] origin:064-gtp-channel-conf 01_187 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXOSCALRESET_TIME[2] origin:064-gtp-channel-conf 00_188 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXOSCALRESET_TIME[3] origin:064-gtp-channel-conf 01_188 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXOSCALRESET_TIME[4] origin:064-gtp-channel-conf 00_189 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXOSCALRESET_TIMEOUT[0] origin:064-gtp-channel-conf 01_189 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXOSCALRESET_TIMEOUT[1] origin:064-gtp-channel-conf 00_190 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXOSCALRESET_TIMEOUT[2] origin:064-gtp-channel-conf 01_190 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXOSCALRESET_TIMEOUT[3] origin:064-gtp-channel-conf 00_191 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXOSCALRESET_TIMEOUT[4] origin:064-gtp-channel-conf 01_191 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXOUT_DIV[0] origin:064-gtp-channel-conf 02_384 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXOUT_DIV[1] origin:064-gtp-channel-conf 03_384 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXPCSRESET_TIME[0] origin:064-gtp-channel-conf 01_115 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXPCSRESET_TIME[1] origin:064-gtp-channel-conf 00_116 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXPCSRESET_TIME[2] origin:064-gtp-channel-conf 01_116 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXPCSRESET_TIME[3] origin:064-gtp-channel-conf 00_117 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXPCSRESET_TIME[4] origin:064-gtp-channel-conf 01_117 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[0] origin:064-gtp-channel-conf 02_584 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[1] origin:064-gtp-channel-conf 03_584 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[2] origin:064-gtp-channel-conf 02_585 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[3] origin:064-gtp-channel-conf 03_585 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[4] origin:064-gtp-channel-conf 02_586 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[5] origin:064-gtp-channel-conf 03_586 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[6] origin:064-gtp-channel-conf 02_587 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[7] origin:064-gtp-channel-conf 03_587 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[8] origin:064-gtp-channel-conf 02_588 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[9] origin:064-gtp-channel-conf 03_588 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[10] origin:064-gtp-channel-conf 02_589 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[11] origin:064-gtp-channel-conf 03_589 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[12] origin:064-gtp-channel-conf 02_590 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[13] origin:064-gtp-channel-conf 03_590 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[14] origin:064-gtp-channel-conf 02_591 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[15] origin:064-gtp-channel-conf 03_591 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[16] origin:064-gtp-channel-conf 02_592 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[17] origin:064-gtp-channel-conf 03_592 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[18] origin:064-gtp-channel-conf 02_593 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[19] origin:064-gtp-channel-conf 03_593 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[20] origin:064-gtp-channel-conf 02_594 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[21] origin:064-gtp-channel-conf 03_594 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[22] origin:064-gtp-channel-conf 02_595 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[23] origin:064-gtp-channel-conf 03_595 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXPH_MONITOR_SEL[0] origin:064-gtp-channel-conf 00_700 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXPH_MONITOR_SEL[1] origin:064-gtp-channel-conf 01_700 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXPH_MONITOR_SEL[2] origin:064-gtp-channel-conf 00_701 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXPH_MONITOR_SEL[3] origin:064-gtp-channel-conf 01_701 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXPH_MONITOR_SEL[4] origin:064-gtp-channel-conf 00_702 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[0] origin:064-gtp-channel-conf 02_600 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[1] origin:064-gtp-channel-conf 03_600 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[2] origin:064-gtp-channel-conf 02_601 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[3] origin:064-gtp-channel-conf 03_601 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[4] origin:064-gtp-channel-conf 02_602 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[5] origin:064-gtp-channel-conf 03_602 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[6] origin:064-gtp-channel-conf 02_603 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[7] origin:064-gtp-channel-conf 03_603 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[8] origin:064-gtp-channel-conf 02_604 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[9] origin:064-gtp-channel-conf 03_604 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[10] origin:064-gtp-channel-conf 02_605 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[11] origin:064-gtp-channel-conf 03_605 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[12] origin:064-gtp-channel-conf 02_606 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[13] origin:064-gtp-channel-conf 03_606 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[14] origin:064-gtp-channel-conf 02_607 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[15] origin:064-gtp-channel-conf 03_607 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[16] origin:064-gtp-channel-conf 02_608 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[17] origin:064-gtp-channel-conf 03_608 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[18] origin:064-gtp-channel-conf 02_609 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[19] origin:064-gtp-channel-conf 03_609 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[20] origin:064-gtp-channel-conf 02_610 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[21] origin:064-gtp-channel-conf 03_610 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[22] origin:064-gtp-channel-conf 02_611 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[23] origin:064-gtp-channel-conf 03_611 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXPI_CFG0[0] origin:064-gtp-channel-conf 03_430 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXPI_CFG0[1] origin:064-gtp-channel-conf 02_431 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXPI_CFG0[2] origin:064-gtp-channel-conf 03_431 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXPI_CFG1[0] origin:064-gtp-channel-conf 02_442 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXPI_CFG2[0] origin:064-gtp-channel-conf 03_441 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXPMARESET_TIME[0] origin:064-gtp-channel-conf 00_104 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXPMARESET_TIME[1] origin:064-gtp-channel-conf 01_104 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXPMARESET_TIME[2] origin:064-gtp-channel-conf 00_105 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXPMARESET_TIME[3] origin:064-gtp-channel-conf 01_105 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXPMARESET_TIME[4] origin:064-gtp-channel-conf 00_106 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXPRBS_ERR_LOOPBACK[0] origin:064-gtp-channel-conf 00_136 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXSLIDE_AUTO_WAIT[0] origin:064-gtp-channel-conf 00_520 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXSLIDE_AUTO_WAIT[1] origin:064-gtp-channel-conf 01_520 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXSLIDE_AUTO_WAIT[2] origin:064-gtp-channel-conf 00_521 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXSLIDE_AUTO_WAIT[3] origin:064-gtp-channel-conf 01_521 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXSLIDE_MODE.AUTO origin:064-gtp-channel-conf !01_519 00_519 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXSLIDE_MODE.PCS origin:064-gtp-channel-conf !00_519 01_519 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXSLIDE_MODE.PMA origin:064-gtp-channel-conf 00_519 01_519 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXSYNC_MULTILANE[0] origin:064-gtp-channel-conf 00_133 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXSYNC_OVRD[0] origin:064-gtp-channel-conf 01_135 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.RXSYNC_SKIP_DA[0] origin:064-gtp-channel-conf 01_134 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.SAS_MAX_COM[0] origin:064-gtp-channel-conf 00_171 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.SAS_MAX_COM[1] origin:064-gtp-channel-conf 01_171 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.SAS_MAX_COM[2] origin:064-gtp-channel-conf 00_172 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.SAS_MAX_COM[3] origin:064-gtp-channel-conf 01_172 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.SAS_MAX_COM[4] origin:064-gtp-channel-conf 00_173 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.SAS_MAX_COM[5] origin:064-gtp-channel-conf 01_173 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.SAS_MAX_COM[6] origin:064-gtp-channel-conf 00_174 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.SAS_MIN_COM[0] origin:064-gtp-channel-conf 01_156 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.SAS_MIN_COM[1] origin:064-gtp-channel-conf 00_157 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.SAS_MIN_COM[2] origin:064-gtp-channel-conf 01_157 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.SAS_MIN_COM[3] origin:064-gtp-channel-conf 00_158 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.SAS_MIN_COM[4] origin:064-gtp-channel-conf 01_158 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.SAS_MIN_COM[5] origin:064-gtp-channel-conf 00_159 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.SATA_BURST_SEQ_LEN[0] origin:064-gtp-channel-conf 00_150 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.SATA_BURST_SEQ_LEN[1] origin:064-gtp-channel-conf 01_150 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.SATA_BURST_SEQ_LEN[2] origin:064-gtp-channel-conf 00_151 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.SATA_BURST_SEQ_LEN[3] origin:064-gtp-channel-conf 01_151 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.SATA_BURST_VAL[0] origin:064-gtp-channel-conf 01_147 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.SATA_BURST_VAL[1] origin:064-gtp-channel-conf 00_148 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.SATA_BURST_VAL[2] origin:064-gtp-channel-conf 01_148 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.SATA_EIDLE_VAL[0] origin:064-gtp-channel-conf 00_152 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.SATA_EIDLE_VAL[1] origin:064-gtp-channel-conf 01_152 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.SATA_EIDLE_VAL[2] origin:064-gtp-channel-conf 00_153 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.SATA_MAX_BURST[0] origin:064-gtp-channel-conf 00_168 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.SATA_MAX_BURST[1] origin:064-gtp-channel-conf 01_168 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.SATA_MAX_BURST[2] origin:064-gtp-channel-conf 00_169 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.SATA_MAX_BURST[3] origin:064-gtp-channel-conf 01_169 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.SATA_MAX_BURST[4] origin:064-gtp-channel-conf 00_170 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.SATA_MAX_BURST[5] origin:064-gtp-channel-conf 01_170 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.SATA_MAX_INIT[0] origin:064-gtp-channel-conf 00_176 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.SATA_MAX_INIT[1] origin:064-gtp-channel-conf 01_176 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.SATA_MAX_INIT[2] origin:064-gtp-channel-conf 00_177 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.SATA_MAX_INIT[3] origin:064-gtp-channel-conf 01_177 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.SATA_MAX_INIT[4] origin:064-gtp-channel-conf 00_178 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.SATA_MAX_INIT[5] origin:064-gtp-channel-conf 01_178 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.SATA_MAX_WAKE[0] origin:064-gtp-channel-conf 00_179 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.SATA_MAX_WAKE[1] origin:064-gtp-channel-conf 01_179 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.SATA_MAX_WAKE[2] origin:064-gtp-channel-conf 00_180 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.SATA_MAX_WAKE[3] origin:064-gtp-channel-conf 01_180 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.SATA_MAX_WAKE[4] origin:064-gtp-channel-conf 00_181 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.SATA_MAX_WAKE[5] origin:064-gtp-channel-conf 01_181 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.SATA_MIN_BURST[0] origin:064-gtp-channel-conf 01_153 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.SATA_MIN_BURST[1] origin:064-gtp-channel-conf 00_154 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.SATA_MIN_BURST[2] origin:064-gtp-channel-conf 01_154 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.SATA_MIN_BURST[3] origin:064-gtp-channel-conf 00_155 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.SATA_MIN_BURST[4] origin:064-gtp-channel-conf 01_155 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.SATA_MIN_BURST[5] origin:064-gtp-channel-conf 00_156 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.SATA_MIN_INIT[0] origin:064-gtp-channel-conf 00_160 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.SATA_MIN_INIT[1] origin:064-gtp-channel-conf 01_160 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.SATA_MIN_INIT[2] origin:064-gtp-channel-conf 00_161 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.SATA_MIN_INIT[3] origin:064-gtp-channel-conf 01_161 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.SATA_MIN_INIT[4] origin:064-gtp-channel-conf 00_162 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.SATA_MIN_INIT[5] origin:064-gtp-channel-conf 01_162 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.SATA_MIN_WAKE[0] origin:064-gtp-channel-conf 00_163 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.SATA_MIN_WAKE[1] origin:064-gtp-channel-conf 01_163 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.SATA_MIN_WAKE[2] origin:064-gtp-channel-conf 00_164 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.SATA_MIN_WAKE[3] origin:064-gtp-channel-conf 01_164 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.SATA_MIN_WAKE[4] origin:064-gtp-channel-conf 00_165 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.SATA_MIN_WAKE[5] origin:064-gtp-channel-conf 01_165 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.SATA_PLL_CFG.VCO_1500MHZ origin:064-gtp-channel-conf 02_55 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.SATA_PLL_CFG.VCO_750MHZ origin:064-gtp-channel-conf 03_55 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.SHOW_REALIGN_COMMA origin:064-gtp-channel-conf 01_522 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TERM_RCAL_CFG[0] origin:064-gtp-channel-conf 02_136 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TERM_RCAL_CFG[1] origin:064-gtp-channel-conf 03_136 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TERM_RCAL_CFG[2] origin:064-gtp-channel-conf 02_137 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TERM_RCAL_CFG[3] origin:064-gtp-channel-conf 03_137 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TERM_RCAL_CFG[4] origin:064-gtp-channel-conf 02_138 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TERM_RCAL_CFG[5] origin:064-gtp-channel-conf 03_138 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TERM_RCAL_CFG[6] origin:064-gtp-channel-conf 02_139 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TERM_RCAL_CFG[7] origin:064-gtp-channel-conf 03_139 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TERM_RCAL_CFG[8] origin:064-gtp-channel-conf 02_140 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TERM_RCAL_CFG[9] origin:064-gtp-channel-conf 03_140 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TERM_RCAL_CFG[10] origin:064-gtp-channel-conf 02_141 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TERM_RCAL_CFG[11] origin:064-gtp-channel-conf 03_141 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TERM_RCAL_CFG[12] origin:064-gtp-channel-conf 02_142 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TERM_RCAL_CFG[13] origin:064-gtp-channel-conf 03_142 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TERM_RCAL_CFG[14] origin:064-gtp-channel-conf 02_143 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TERM_RCAL_OVRD[0] origin:064-gtp-channel-conf 03_150 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TERM_RCAL_OVRD[1] origin:064-gtp-channel-conf 02_151 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TERM_RCAL_OVRD[2] origin:064-gtp-channel-conf 03_151 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TRANS_TIME_RATE[0] origin:064-gtp-channel-conf 00_192 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TRANS_TIME_RATE[1] origin:064-gtp-channel-conf 01_192 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TRANS_TIME_RATE[2] origin:064-gtp-channel-conf 00_193 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TRANS_TIME_RATE[3] origin:064-gtp-channel-conf 01_193 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TRANS_TIME_RATE[4] origin:064-gtp-channel-conf 00_194 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TRANS_TIME_RATE[5] origin:064-gtp-channel-conf 01_194 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TRANS_TIME_RATE[6] origin:064-gtp-channel-conf 00_195 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TRANS_TIME_RATE[7] origin:064-gtp-channel-conf 01_195 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[0] origin:064-gtp-channel-conf 02_504 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[1] origin:064-gtp-channel-conf 03_504 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[2] origin:064-gtp-channel-conf 02_505 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[3] origin:064-gtp-channel-conf 03_505 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[4] origin:064-gtp-channel-conf 02_506 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[5] origin:064-gtp-channel-conf 03_506 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[6] origin:064-gtp-channel-conf 02_507 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[7] origin:064-gtp-channel-conf 03_507 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[8] origin:064-gtp-channel-conf 02_508 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[9] origin:064-gtp-channel-conf 03_508 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[10] origin:064-gtp-channel-conf 02_509 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[11] origin:064-gtp-channel-conf 03_509 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[12] origin:064-gtp-channel-conf 02_510 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[13] origin:064-gtp-channel-conf 03_510 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[14] origin:064-gtp-channel-conf 02_511 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[15] origin:064-gtp-channel-conf 03_511 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[16] origin:064-gtp-channel-conf 02_512 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[17] origin:064-gtp-channel-conf 03_512 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[18] origin:064-gtp-channel-conf 02_513 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[19] origin:064-gtp-channel-conf 03_513 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[20] origin:064-gtp-channel-conf 02_514 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[21] origin:064-gtp-channel-conf 03_514 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[22] origin:064-gtp-channel-conf 02_515 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[23] origin:064-gtp-channel-conf 03_515 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[24] origin:064-gtp-channel-conf 02_516 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[25] origin:064-gtp-channel-conf 03_516 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[26] origin:064-gtp-channel-conf 02_517 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[27] origin:064-gtp-channel-conf 03_517 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[28] origin:064-gtp-channel-conf 02_518 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[29] origin:064-gtp-channel-conf 03_518 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[30] origin:064-gtp-channel-conf 02_519 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[31] origin:064-gtp-channel-conf 03_519 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_CLKMUX_EN[0] origin:064-gtp-channel-conf 03_128 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_DATA_WIDTH[0] origin:064-gtp-channel-conf 02_152 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_DATA_WIDTH[1] origin:064-gtp-channel-conf 03_152 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_DATA_WIDTH[2] origin:064-gtp-channel-conf 02_153 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_DRIVE_MODE.PIPE origin:064-gtp-channel-conf 00_200 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_EIDLE_ASSERT_DELAY[0] origin:064-gtp-channel-conf 00_203 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_EIDLE_ASSERT_DELAY[1] origin:064-gtp-channel-conf 01_203 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_EIDLE_ASSERT_DELAY[2] origin:064-gtp-channel-conf 00_204 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_EIDLE_DEASSERT_DELAY[0] origin:064-gtp-channel-conf 01_204 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_EIDLE_DEASSERT_DELAY[1] origin:064-gtp-channel-conf 00_205 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_EIDLE_DEASSERT_DELAY[2] origin:064-gtp-channel-conf 01_205 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_LOOPBACK_DRIVE_HIZ origin:064-gtp-channel-conf 01_202 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_MAINCURSOR_SEL[0] origin:064-gtp-channel-conf 03_289 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_0[0] origin:064-gtp-channel-conf 02_232 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_0[1] origin:064-gtp-channel-conf 03_232 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_0[2] origin:064-gtp-channel-conf 02_233 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_0[3] origin:064-gtp-channel-conf 03_233 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_0[4] origin:064-gtp-channel-conf 02_234 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_0[5] origin:064-gtp-channel-conf 03_234 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_0[6] origin:064-gtp-channel-conf 02_235 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_1[0] origin:064-gtp-channel-conf 02_236 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_1[1] origin:064-gtp-channel-conf 03_236 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_1[2] origin:064-gtp-channel-conf 02_237 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_1[3] origin:064-gtp-channel-conf 03_237 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_1[4] origin:064-gtp-channel-conf 02_238 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_1[5] origin:064-gtp-channel-conf 03_238 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_1[6] origin:064-gtp-channel-conf 02_239 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_2[0] origin:064-gtp-channel-conf 02_240 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_2[1] origin:064-gtp-channel-conf 03_240 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_2[2] origin:064-gtp-channel-conf 02_241 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_2[3] origin:064-gtp-channel-conf 03_241 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_2[4] origin:064-gtp-channel-conf 02_242 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_2[5] origin:064-gtp-channel-conf 03_242 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_2[6] origin:064-gtp-channel-conf 02_243 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_3[0] origin:064-gtp-channel-conf 02_244 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_3[1] origin:064-gtp-channel-conf 03_244 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_3[2] origin:064-gtp-channel-conf 02_245 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_3[3] origin:064-gtp-channel-conf 03_245 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_3[4] origin:064-gtp-channel-conf 02_246 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_3[5] origin:064-gtp-channel-conf 03_246 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_3[6] origin:064-gtp-channel-conf 02_247 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_4[0] origin:064-gtp-channel-conf 02_248 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_4[1] origin:064-gtp-channel-conf 03_248 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_4[2] origin:064-gtp-channel-conf 02_249 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_4[3] origin:064-gtp-channel-conf 03_249 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_4[4] origin:064-gtp-channel-conf 02_250 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_4[5] origin:064-gtp-channel-conf 03_250 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_4[6] origin:064-gtp-channel-conf 02_251 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_0[0] origin:064-gtp-channel-conf 02_252 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_0[1] origin:064-gtp-channel-conf 03_252 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_0[2] origin:064-gtp-channel-conf 02_253 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_0[3] origin:064-gtp-channel-conf 03_253 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_0[4] origin:064-gtp-channel-conf 02_254 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_0[5] origin:064-gtp-channel-conf 03_254 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_0[6] origin:064-gtp-channel-conf 02_255 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_1[0] origin:064-gtp-channel-conf 02_256 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_1[1] origin:064-gtp-channel-conf 03_256 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_1[2] origin:064-gtp-channel-conf 02_257 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_1[3] origin:064-gtp-channel-conf 03_257 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_1[4] origin:064-gtp-channel-conf 02_258 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_1[5] origin:064-gtp-channel-conf 03_258 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_1[6] origin:064-gtp-channel-conf 02_259 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_2[0] origin:064-gtp-channel-conf 02_260 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_2[1] origin:064-gtp-channel-conf 03_260 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_2[2] origin:064-gtp-channel-conf 02_261 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_2[3] origin:064-gtp-channel-conf 03_261 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_2[4] origin:064-gtp-channel-conf 02_262 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_2[5] origin:064-gtp-channel-conf 03_262 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_2[6] origin:064-gtp-channel-conf 02_263 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_3[0] origin:064-gtp-channel-conf 02_264 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_3[1] origin:064-gtp-channel-conf 03_264 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_3[2] origin:064-gtp-channel-conf 02_265 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_3[3] origin:064-gtp-channel-conf 03_265 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_3[4] origin:064-gtp-channel-conf 02_266 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_3[5] origin:064-gtp-channel-conf 03_266 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_3[6] origin:064-gtp-channel-conf 02_267 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_4[0] origin:064-gtp-channel-conf 02_268 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_4[1] origin:064-gtp-channel-conf 03_268 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_4[2] origin:064-gtp-channel-conf 02_269 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_4[3] origin:064-gtp-channel-conf 03_269 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_4[4] origin:064-gtp-channel-conf 02_270 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_4[5] origin:064-gtp-channel-conf 03_270 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_4[6] origin:064-gtp-channel-conf 02_271 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_PREDRIVER_MODE[0] origin:064-gtp-channel-conf 00_206 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_RXDETECT_CFG[0] origin:064-gtp-channel-conf 02_296 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_RXDETECT_CFG[1] origin:064-gtp-channel-conf 03_296 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_RXDETECT_CFG[2] origin:064-gtp-channel-conf 02_297 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_RXDETECT_CFG[3] origin:064-gtp-channel-conf 03_297 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_RXDETECT_CFG[4] origin:064-gtp-channel-conf 02_298 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_RXDETECT_CFG[5] origin:064-gtp-channel-conf 03_298 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_RXDETECT_CFG[6] origin:064-gtp-channel-conf 02_299 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_RXDETECT_CFG[7] origin:064-gtp-channel-conf 03_299 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_RXDETECT_CFG[8] origin:064-gtp-channel-conf 02_300 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_RXDETECT_CFG[9] origin:064-gtp-channel-conf 03_300 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_RXDETECT_CFG[10] origin:064-gtp-channel-conf 02_301 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_RXDETECT_CFG[11] origin:064-gtp-channel-conf 03_301 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_RXDETECT_CFG[12] origin:064-gtp-channel-conf 02_302 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_RXDETECT_CFG[13] origin:064-gtp-channel-conf 03_302 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_RXDETECT_REF[0] origin:064-gtp-channel-conf 02_292 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_RXDETECT_REF[1] origin:064-gtp-channel-conf 03_292 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_RXDETECT_REF[2] origin:064-gtp-channel-conf 02_293 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_XCLK_SEL.TXUSR origin:064-gtp-channel-conf 03_11 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_CLK25_DIV[0] origin:064-gtp-channel-conf 02_144 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_CLK25_DIV[1] origin:064-gtp-channel-conf 03_144 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_CLK25_DIV[2] origin:064-gtp-channel-conf 02_145 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_CLK25_DIV[3] origin:064-gtp-channel-conf 03_145 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_CLK25_DIV[4] origin:064-gtp-channel-conf 02_146 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_DEEMPH0[0] origin:064-gtp-channel-conf 02_272 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_DEEMPH0[1] origin:064-gtp-channel-conf 03_272 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_DEEMPH0[2] origin:064-gtp-channel-conf 02_273 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_DEEMPH0[3] origin:064-gtp-channel-conf 03_273 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_DEEMPH0[4] origin:064-gtp-channel-conf 02_274 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_DEEMPH0[5] origin:064-gtp-channel-conf 03_274 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_DEEMPH1[0] origin:064-gtp-channel-conf 02_276 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_DEEMPH1[1] origin:064-gtp-channel-conf 03_276 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_DEEMPH1[2] origin:064-gtp-channel-conf 02_277 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_DEEMPH1[3] origin:064-gtp-channel-conf 03_277 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_DEEMPH1[4] origin:064-gtp-channel-conf 02_278 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TX_DEEMPH1[5] origin:064-gtp-channel-conf 03_278 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXBUF_EN origin:064-gtp-channel-conf 00_231 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXBUF_RESET_ON_RATE_CHANGE origin:064-gtp-channel-conf 01_231 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXDLY_CFG[0] origin:064-gtp-channel-conf 02_80 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXDLY_CFG[1] origin:064-gtp-channel-conf 03_80 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXDLY_CFG[2] origin:064-gtp-channel-conf 02_81 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXDLY_CFG[3] origin:064-gtp-channel-conf 03_81 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXDLY_CFG[4] origin:064-gtp-channel-conf 02_82 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXDLY_CFG[5] origin:064-gtp-channel-conf 03_82 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXDLY_CFG[6] origin:064-gtp-channel-conf 02_83 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXDLY_CFG[7] origin:064-gtp-channel-conf 03_83 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXDLY_CFG[8] origin:064-gtp-channel-conf 02_84 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXDLY_CFG[9] origin:064-gtp-channel-conf 03_84 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXDLY_CFG[10] origin:064-gtp-channel-conf 02_85 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXDLY_CFG[11] origin:064-gtp-channel-conf 03_85 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXDLY_CFG[12] origin:064-gtp-channel-conf 02_86 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXDLY_CFG[13] origin:064-gtp-channel-conf 03_86 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXDLY_CFG[14] origin:064-gtp-channel-conf 02_87 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXDLY_CFG[15] origin:064-gtp-channel-conf 03_87 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXDLY_LCFG[0] origin:064-gtp-channel-conf 02_568 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXDLY_LCFG[1] origin:064-gtp-channel-conf 03_568 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXDLY_LCFG[2] origin:064-gtp-channel-conf 02_569 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXDLY_LCFG[3] origin:064-gtp-channel-conf 03_569 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXDLY_LCFG[4] origin:064-gtp-channel-conf 02_570 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXDLY_LCFG[5] origin:064-gtp-channel-conf 03_570 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXDLY_LCFG[6] origin:064-gtp-channel-conf 02_571 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXDLY_LCFG[7] origin:064-gtp-channel-conf 03_571 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXDLY_LCFG[8] origin:064-gtp-channel-conf 02_572 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXDLY_TAP_CFG[0] origin:064-gtp-channel-conf 02_88 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXDLY_TAP_CFG[1] origin:064-gtp-channel-conf 03_88 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXDLY_TAP_CFG[2] origin:064-gtp-channel-conf 02_89 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXDLY_TAP_CFG[3] origin:064-gtp-channel-conf 03_89 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXDLY_TAP_CFG[4] origin:064-gtp-channel-conf 02_90 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXDLY_TAP_CFG[5] origin:064-gtp-channel-conf 03_90 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXDLY_TAP_CFG[6] origin:064-gtp-channel-conf 02_91 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXDLY_TAP_CFG[7] origin:064-gtp-channel-conf 03_91 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXDLY_TAP_CFG[8] origin:064-gtp-channel-conf 02_92 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXDLY_TAP_CFG[9] origin:064-gtp-channel-conf 03_92 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXDLY_TAP_CFG[10] origin:064-gtp-channel-conf 02_93 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXDLY_TAP_CFG[11] origin:064-gtp-channel-conf 03_93 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXDLY_TAP_CFG[12] origin:064-gtp-channel-conf 02_94 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXDLY_TAP_CFG[13] origin:064-gtp-channel-conf 03_94 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXDLY_TAP_CFG[14] origin:064-gtp-channel-conf 02_95 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXDLY_TAP_CFG[15] origin:064-gtp-channel-conf 03_95 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXGEARBOX_EN origin:064-gtp-channel-conf 01_226 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXOOB_CFG[0] origin:064-gtp-channel-conf 03_20 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXOUT_DIV[0] origin:064-gtp-channel-conf 02_386 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXOUT_DIV[1] origin:064-gtp-channel-conf 03_386 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPCSRESET_TIME[0] origin:064-gtp-channel-conf 01_130 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPCSRESET_TIME[1] origin:064-gtp-channel-conf 00_131 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPCSRESET_TIME[2] origin:064-gtp-channel-conf 01_131 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPCSRESET_TIME[3] origin:064-gtp-channel-conf 00_132 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPCSRESET_TIME[4] origin:064-gtp-channel-conf 01_132 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPH_CFG[0] origin:064-gtp-channel-conf 02_96 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPH_CFG[1] origin:064-gtp-channel-conf 03_96 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPH_CFG[2] origin:064-gtp-channel-conf 02_97 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPH_CFG[3] origin:064-gtp-channel-conf 03_97 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPH_CFG[4] origin:064-gtp-channel-conf 02_98 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPH_CFG[5] origin:064-gtp-channel-conf 03_98 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPH_CFG[6] origin:064-gtp-channel-conf 02_99 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPH_CFG[7] origin:064-gtp-channel-conf 03_99 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPH_CFG[8] origin:064-gtp-channel-conf 02_100 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPH_CFG[9] origin:064-gtp-channel-conf 03_100 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPH_CFG[10] origin:064-gtp-channel-conf 02_101 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPH_CFG[11] origin:064-gtp-channel-conf 03_101 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPH_CFG[12] origin:064-gtp-channel-conf 02_102 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPH_CFG[13] origin:064-gtp-channel-conf 03_102 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPH_CFG[14] origin:064-gtp-channel-conf 02_103 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPH_CFG[15] origin:064-gtp-channel-conf 03_103 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPH_MONITOR_SEL[0] origin:064-gtp-channel-conf 02_108 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPH_MONITOR_SEL[1] origin:064-gtp-channel-conf 03_108 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPH_MONITOR_SEL[2] origin:064-gtp-channel-conf 02_109 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPH_MONITOR_SEL[3] origin:064-gtp-channel-conf 03_109 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPH_MONITOR_SEL[4] origin:064-gtp-channel-conf 02_110 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[0] origin:064-gtp-channel-conf 02_64 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[1] origin:064-gtp-channel-conf 03_64 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[2] origin:064-gtp-channel-conf 02_65 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[3] origin:064-gtp-channel-conf 03_65 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[4] origin:064-gtp-channel-conf 02_66 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[5] origin:064-gtp-channel-conf 03_66 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[6] origin:064-gtp-channel-conf 02_67 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[7] origin:064-gtp-channel-conf 03_67 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[8] origin:064-gtp-channel-conf 02_68 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[9] origin:064-gtp-channel-conf 03_68 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[10] origin:064-gtp-channel-conf 02_69 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[11] origin:064-gtp-channel-conf 03_69 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[12] origin:064-gtp-channel-conf 02_70 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[13] origin:064-gtp-channel-conf 03_70 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[14] origin:064-gtp-channel-conf 02_71 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[15] origin:064-gtp-channel-conf 03_71 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[16] origin:064-gtp-channel-conf 02_72 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[17] origin:064-gtp-channel-conf 03_72 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[18] origin:064-gtp-channel-conf 02_73 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[19] origin:064-gtp-channel-conf 03_73 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[20] origin:064-gtp-channel-conf 02_74 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[21] origin:064-gtp-channel-conf 03_74 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[22] origin:064-gtp-channel-conf 02_75 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[23] origin:064-gtp-channel-conf 03_75 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPI_GREY_SEL[0] origin:064-gtp-channel-conf 03_498 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPI_INVSTROBE_SEL[0] origin:064-gtp-channel-conf 02_498 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPI_PPM_CFG[0] origin:064-gtp-channel-conf 02_488 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPI_PPM_CFG[1] origin:064-gtp-channel-conf 03_488 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPI_PPM_CFG[2] origin:064-gtp-channel-conf 02_489 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPI_PPM_CFG[3] origin:064-gtp-channel-conf 03_489 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPI_PPM_CFG[4] origin:064-gtp-channel-conf 02_490 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPI_PPM_CFG[5] origin:064-gtp-channel-conf 03_490 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPI_PPM_CFG[6] origin:064-gtp-channel-conf 02_491 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPI_PPM_CFG[7] origin:064-gtp-channel-conf 03_491 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPI_PPMCLK_SEL.TXUSRCLK2 origin:064-gtp-channel-conf 03_497 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPI_SYNFREQ_PPM[0] origin:064-gtp-channel-conf 02_496 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPI_SYNFREQ_PPM[1] origin:064-gtp-channel-conf 03_496 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPI_SYNFREQ_PPM[2] origin:064-gtp-channel-conf 02_497 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPI_CFG0[0] origin:064-gtp-channel-conf 02_40 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPI_CFG0[1] origin:064-gtp-channel-conf 03_40 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPI_CFG1[0] origin:064-gtp-channel-conf 02_41 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPI_CFG1[1] origin:064-gtp-channel-conf 03_41 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPI_CFG2[0] origin:064-gtp-channel-conf 02_42 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPI_CFG2[1] origin:064-gtp-channel-conf 03_42 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPI_CFG3[0] origin:064-gtp-channel-conf 02_43 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPI_CFG4[0] origin:064-gtp-channel-conf 03_43 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPI_CFG5[0] origin:064-gtp-channel-conf 02_44 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPI_CFG5[1] origin:064-gtp-channel-conf 03_44 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPI_CFG5[2] origin:064-gtp-channel-conf 02_45 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPMARESET_TIME[0] origin:064-gtp-channel-conf 00_128 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPMARESET_TIME[1] origin:064-gtp-channel-conf 01_128 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPMARESET_TIME[2] origin:064-gtp-channel-conf 00_129 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPMARESET_TIME[3] origin:064-gtp-channel-conf 01_129 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXPMARESET_TIME[4] origin:064-gtp-channel-conf 00_130 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXSYNC_MULTILANE[0] origin:064-gtp-channel-conf 01_133 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXSYNC_OVRD[0] origin:064-gtp-channel-conf 00_135 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.TXSYNC_SKIP_DA[0] origin:064-gtp-channel-conf 00_134 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.UCODEER_CLR[0] origin:064-gtp-channel-conf 01_00 +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL.USE_PCS_CLK_PHASE_SEL[0] origin:064-gtp-channel-conf 02_463 diff --git a/artix7/segbits_gtp_channel_2.db b/artix7/segbits_gtp_channel_2.db index d80f2bf..2bfa53f 100644 --- a/artix7/segbits_gtp_channel_2.db +++ b/artix7/segbits_gtp_channel_2.db @@ -1,1627 +1,1627 @@ -GTP_CHANNEL_2.GTPE2.ACJTAG_DEBUG_MODE[0] 28_07 -GTP_CHANNEL_2.GTPE2.ACJTAG_MODE[0] 29_06 -GTP_CHANNEL_2.GTPE2.ACJTAG_RESET[0] 29_07 -GTP_CHANNEL_2.GTPE2.ADAPT_CFG0[0] 30_464 -GTP_CHANNEL_2.GTPE2.ADAPT_CFG0[1] 31_464 -GTP_CHANNEL_2.GTPE2.ADAPT_CFG0[2] 30_465 -GTP_CHANNEL_2.GTPE2.ADAPT_CFG0[3] 31_465 -GTP_CHANNEL_2.GTPE2.ADAPT_CFG0[4] 30_466 -GTP_CHANNEL_2.GTPE2.ADAPT_CFG0[5] 31_466 -GTP_CHANNEL_2.GTPE2.ADAPT_CFG0[6] 30_467 -GTP_CHANNEL_2.GTPE2.ADAPT_CFG0[7] 31_467 -GTP_CHANNEL_2.GTPE2.ADAPT_CFG0[8] 30_468 -GTP_CHANNEL_2.GTPE2.ADAPT_CFG0[9] 31_468 -GTP_CHANNEL_2.GTPE2.ADAPT_CFG0[10] 30_469 -GTP_CHANNEL_2.GTPE2.ADAPT_CFG0[11] 31_469 -GTP_CHANNEL_2.GTPE2.ADAPT_CFG0[12] 30_470 -GTP_CHANNEL_2.GTPE2.ADAPT_CFG0[13] 31_470 -GTP_CHANNEL_2.GTPE2.ADAPT_CFG0[14] 30_471 -GTP_CHANNEL_2.GTPE2.ADAPT_CFG0[15] 31_471 -GTP_CHANNEL_2.GTPE2.ADAPT_CFG0[16] 30_472 -GTP_CHANNEL_2.GTPE2.ADAPT_CFG0[17] 31_472 -GTP_CHANNEL_2.GTPE2.ADAPT_CFG0[18] 30_473 -GTP_CHANNEL_2.GTPE2.ADAPT_CFG0[19] 31_473 -GTP_CHANNEL_2.GTPE2.ALIGN_COMMA_DOUBLE 28_522 -GTP_CHANNEL_2.GTPE2.ALIGN_COMMA_ENABLE[0] 28_496 -GTP_CHANNEL_2.GTPE2.ALIGN_COMMA_ENABLE[1] 29_496 -GTP_CHANNEL_2.GTPE2.ALIGN_COMMA_ENABLE[2] 28_497 -GTP_CHANNEL_2.GTPE2.ALIGN_COMMA_ENABLE[3] 29_497 -GTP_CHANNEL_2.GTPE2.ALIGN_COMMA_ENABLE[4] 28_498 -GTP_CHANNEL_2.GTPE2.ALIGN_COMMA_ENABLE[5] 29_498 -GTP_CHANNEL_2.GTPE2.ALIGN_COMMA_ENABLE[6] 28_499 -GTP_CHANNEL_2.GTPE2.ALIGN_COMMA_ENABLE[7] 29_499 -GTP_CHANNEL_2.GTPE2.ALIGN_COMMA_ENABLE[8] 28_500 -GTP_CHANNEL_2.GTPE2.ALIGN_COMMA_ENABLE[9] 29_500 -GTP_CHANNEL_2.GTPE2.ALIGN_COMMA_WORD[0] 29_526 -GTP_CHANNEL_2.GTPE2.ALIGN_COMMA_WORD[1] 28_527 -GTP_CHANNEL_2.GTPE2.ALIGN_MCOMMA_DET 28_523 -GTP_CHANNEL_2.GTPE2.ALIGN_MCOMMA_VALUE[0] 28_504 -GTP_CHANNEL_2.GTPE2.ALIGN_MCOMMA_VALUE[1] 29_504 -GTP_CHANNEL_2.GTPE2.ALIGN_MCOMMA_VALUE[2] 28_505 -GTP_CHANNEL_2.GTPE2.ALIGN_MCOMMA_VALUE[3] 29_505 -GTP_CHANNEL_2.GTPE2.ALIGN_MCOMMA_VALUE[4] 28_506 -GTP_CHANNEL_2.GTPE2.ALIGN_MCOMMA_VALUE[5] 29_506 -GTP_CHANNEL_2.GTPE2.ALIGN_MCOMMA_VALUE[6] 28_507 -GTP_CHANNEL_2.GTPE2.ALIGN_MCOMMA_VALUE[7] 29_507 -GTP_CHANNEL_2.GTPE2.ALIGN_MCOMMA_VALUE[8] 28_508 -GTP_CHANNEL_2.GTPE2.ALIGN_MCOMMA_VALUE[9] 29_508 -GTP_CHANNEL_2.GTPE2.ALIGN_PCOMMA_DET 29_523 -GTP_CHANNEL_2.GTPE2.ALIGN_PCOMMA_VALUE[0] 28_512 -GTP_CHANNEL_2.GTPE2.ALIGN_PCOMMA_VALUE[1] 29_512 -GTP_CHANNEL_2.GTPE2.ALIGN_PCOMMA_VALUE[2] 28_513 -GTP_CHANNEL_2.GTPE2.ALIGN_PCOMMA_VALUE[3] 29_513 -GTP_CHANNEL_2.GTPE2.ALIGN_PCOMMA_VALUE[4] 28_514 -GTP_CHANNEL_2.GTPE2.ALIGN_PCOMMA_VALUE[5] 29_514 -GTP_CHANNEL_2.GTPE2.ALIGN_PCOMMA_VALUE[6] 28_515 -GTP_CHANNEL_2.GTPE2.ALIGN_PCOMMA_VALUE[7] 29_515 -GTP_CHANNEL_2.GTPE2.ALIGN_PCOMMA_VALUE[8] 28_516 -GTP_CHANNEL_2.GTPE2.ALIGN_PCOMMA_VALUE[9] 29_516 -GTP_CHANNEL_2.GTPE2.CBCC_DATA_SOURCE_SEL.DECODED 29_661 -GTP_CHANNEL_2.GTPE2.CFOK_CFG[0] 30_392 -GTP_CHANNEL_2.GTPE2.CFOK_CFG[1] 31_392 -GTP_CHANNEL_2.GTPE2.CFOK_CFG[2] 30_393 -GTP_CHANNEL_2.GTPE2.CFOK_CFG[3] 31_393 -GTP_CHANNEL_2.GTPE2.CFOK_CFG[4] 30_394 -GTP_CHANNEL_2.GTPE2.CFOK_CFG[5] 31_394 -GTP_CHANNEL_2.GTPE2.CFOK_CFG[6] 30_395 -GTP_CHANNEL_2.GTPE2.CFOK_CFG[7] 31_395 -GTP_CHANNEL_2.GTPE2.CFOK_CFG[8] 30_396 -GTP_CHANNEL_2.GTPE2.CFOK_CFG[9] 31_396 -GTP_CHANNEL_2.GTPE2.CFOK_CFG[10] 30_397 -GTP_CHANNEL_2.GTPE2.CFOK_CFG[11] 31_397 -GTP_CHANNEL_2.GTPE2.CFOK_CFG[12] 30_398 -GTP_CHANNEL_2.GTPE2.CFOK_CFG[13] 31_398 -GTP_CHANNEL_2.GTPE2.CFOK_CFG[14] 30_399 -GTP_CHANNEL_2.GTPE2.CFOK_CFG[15] 31_399 -GTP_CHANNEL_2.GTPE2.CFOK_CFG[16] 30_400 -GTP_CHANNEL_2.GTPE2.CFOK_CFG[17] 31_400 -GTP_CHANNEL_2.GTPE2.CFOK_CFG[18] 30_401 -GTP_CHANNEL_2.GTPE2.CFOK_CFG[19] 31_401 -GTP_CHANNEL_2.GTPE2.CFOK_CFG[20] 30_402 -GTP_CHANNEL_2.GTPE2.CFOK_CFG[21] 31_402 -GTP_CHANNEL_2.GTPE2.CFOK_CFG[22] 30_403 -GTP_CHANNEL_2.GTPE2.CFOK_CFG[23] 31_403 -GTP_CHANNEL_2.GTPE2.CFOK_CFG[24] 30_404 -GTP_CHANNEL_2.GTPE2.CFOK_CFG[25] 31_404 -GTP_CHANNEL_2.GTPE2.CFOK_CFG[26] 30_405 -GTP_CHANNEL_2.GTPE2.CFOK_CFG[27] 31_405 -GTP_CHANNEL_2.GTPE2.CFOK_CFG[28] 30_406 -GTP_CHANNEL_2.GTPE2.CFOK_CFG[29] 31_406 -GTP_CHANNEL_2.GTPE2.CFOK_CFG[30] 30_407 -GTP_CHANNEL_2.GTPE2.CFOK_CFG[31] 31_407 -GTP_CHANNEL_2.GTPE2.CFOK_CFG[32] 30_408 -GTP_CHANNEL_2.GTPE2.CFOK_CFG[33] 31_408 -GTP_CHANNEL_2.GTPE2.CFOK_CFG[34] 30_409 -GTP_CHANNEL_2.GTPE2.CFOK_CFG[35] 31_409 -GTP_CHANNEL_2.GTPE2.CFOK_CFG[36] 30_410 -GTP_CHANNEL_2.GTPE2.CFOK_CFG[37] 31_410 -GTP_CHANNEL_2.GTPE2.CFOK_CFG[38] 30_411 -GTP_CHANNEL_2.GTPE2.CFOK_CFG[39] 31_411 -GTP_CHANNEL_2.GTPE2.CFOK_CFG[40] 30_412 -GTP_CHANNEL_2.GTPE2.CFOK_CFG[41] 31_412 -GTP_CHANNEL_2.GTPE2.CFOK_CFG[42] 30_413 -GTP_CHANNEL_2.GTPE2.CFOK_CFG2[0] 30_459 -GTP_CHANNEL_2.GTPE2.CFOK_CFG2[1] 31_459 -GTP_CHANNEL_2.GTPE2.CFOK_CFG2[2] 30_460 -GTP_CHANNEL_2.GTPE2.CFOK_CFG2[3] 31_460 -GTP_CHANNEL_2.GTPE2.CFOK_CFG2[4] 30_461 -GTP_CHANNEL_2.GTPE2.CFOK_CFG2[5] 31_461 -GTP_CHANNEL_2.GTPE2.CFOK_CFG2[6] 30_462 -GTP_CHANNEL_2.GTPE2.CFOK_CFG3[0] 30_416 -GTP_CHANNEL_2.GTPE2.CFOK_CFG3[1] 31_416 -GTP_CHANNEL_2.GTPE2.CFOK_CFG3[2] 30_417 -GTP_CHANNEL_2.GTPE2.CFOK_CFG3[3] 31_417 -GTP_CHANNEL_2.GTPE2.CFOK_CFG3[4] 30_418 -GTP_CHANNEL_2.GTPE2.CFOK_CFG3[5] 31_418 -GTP_CHANNEL_2.GTPE2.CFOK_CFG3[6] 30_419 -GTP_CHANNEL_2.GTPE2.CFOK_CFG4[0] 31_438 -GTP_CHANNEL_2.GTPE2.CFOK_CFG5[0] 30_429 -GTP_CHANNEL_2.GTPE2.CFOK_CFG5[1] 31_429 -GTP_CHANNEL_2.GTPE2.CFOK_CFG6[0] 31_436 -GTP_CHANNEL_2.GTPE2.CFOK_CFG6[1] 30_437 -GTP_CHANNEL_2.GTPE2.CFOK_CFG6[2] 31_437 -GTP_CHANNEL_2.GTPE2.CFOK_CFG6[3] 30_438 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_KEEP_ALIGN 29_631 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_MAX_SKEW[0] 28_670 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_MAX_SKEW[1] 29_670 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_MAX_SKEW[2] 28_671 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_MAX_SKEW[3] 29_671 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_1_1[0] 28_608 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_1_1[1] 29_608 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_1_1[2] 28_609 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_1_1[3] 29_609 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_1_1[4] 28_610 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_1_1[5] 29_610 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_1_1[6] 28_611 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_1_1[7] 29_611 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_1_1[8] 28_612 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_1_1[9] 29_612 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_1_2[0] 28_616 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_1_2[1] 29_616 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_1_2[2] 28_617 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_1_2[3] 29_617 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_1_2[4] 28_618 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_1_2[5] 29_618 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_1_2[6] 28_619 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_1_2[7] 29_619 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_1_2[8] 28_620 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_1_2[9] 29_620 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_1_3[0] 28_624 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_1_3[1] 29_624 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_1_3[2] 28_625 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_1_3[3] 29_625 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_1_3[4] 28_626 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_1_3[5] 29_626 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_1_3[6] 28_627 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_1_3[7] 29_627 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_1_3[8] 28_628 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_1_3[9] 29_628 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_1_4[0] 28_632 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_1_4[1] 29_632 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_1_4[2] 28_633 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_1_4[3] 29_633 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_1_4[4] 28_634 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_1_4[5] 29_634 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_1_4[6] 28_635 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_1_4[7] 29_635 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_1_4[8] 28_636 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_1_4[9] 29_636 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_1_ENABLE[0] 28_614 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_1_ENABLE[1] 29_614 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_1_ENABLE[2] 28_615 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_1_ENABLE[3] 29_615 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_2_1[0] 28_640 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_2_1[1] 29_640 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_2_1[2] 28_641 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_2_1[3] 29_641 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_2_1[4] 28_642 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_2_1[5] 29_642 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_2_1[6] 28_643 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_2_1[7] 29_643 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_2_1[8] 28_644 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_2_1[9] 29_644 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_2_2[0] 28_648 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_2_2[1] 29_648 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_2_2[2] 28_649 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_2_2[3] 29_649 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_2_2[4] 28_650 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_2_2[5] 29_650 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_2_2[6] 28_651 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_2_2[7] 29_651 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_2_2[8] 28_652 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_2_2[9] 29_652 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_2_3[0] 28_656 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_2_3[1] 29_656 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_2_3[2] 28_657 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_2_3[3] 29_657 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_2_3[4] 28_658 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_2_3[5] 29_658 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_2_3[6] 28_659 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_2_3[7] 29_659 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_2_3[8] 28_660 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_2_3[9] 29_660 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_2_4[0] 28_664 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_2_4[1] 29_664 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_2_4[2] 28_665 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_2_4[3] 29_665 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_2_4[4] 28_666 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_2_4[5] 29_666 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_2_4[6] 28_667 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_2_4[7] 29_667 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_2_4[8] 28_668 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_2_4[9] 29_668 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_2_ENABLE[0] 28_646 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_2_ENABLE[1] 29_646 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_2_ENABLE[2] 28_647 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_2_ENABLE[3] 29_647 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_2_USE 29_645 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_LEN[0] 28_623 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_LEN[1] 29_623 -GTP_CHANNEL_2.GTPE2.CLK_COMMON_SWING[0] 31_311 -GTP_CHANNEL_2.GTPE2.CLK_COR_KEEP_IDLE 28_591 -GTP_CHANNEL_2.GTPE2.CLK_COR_MAX_LAT[0] 28_557 -GTP_CHANNEL_2.GTPE2.CLK_COR_MAX_LAT[1] 29_557 -GTP_CHANNEL_2.GTPE2.CLK_COR_MAX_LAT[2] 28_558 -GTP_CHANNEL_2.GTPE2.CLK_COR_MAX_LAT[3] 29_558 -GTP_CHANNEL_2.GTPE2.CLK_COR_MAX_LAT[4] 28_559 -GTP_CHANNEL_2.GTPE2.CLK_COR_MAX_LAT[5] 29_559 -GTP_CHANNEL_2.GTPE2.CLK_COR_MIN_LAT[0] 28_565 -GTP_CHANNEL_2.GTPE2.CLK_COR_MIN_LAT[1] 29_565 -GTP_CHANNEL_2.GTPE2.CLK_COR_MIN_LAT[2] 28_566 -GTP_CHANNEL_2.GTPE2.CLK_COR_MIN_LAT[3] 29_566 -GTP_CHANNEL_2.GTPE2.CLK_COR_MIN_LAT[4] 28_567 -GTP_CHANNEL_2.GTPE2.CLK_COR_MIN_LAT[5] 29_567 -GTP_CHANNEL_2.GTPE2.CLK_COR_PRECEDENCE 28_590 -GTP_CHANNEL_2.GTPE2.CLK_COR_REPEAT_WAIT[0] 28_573 -GTP_CHANNEL_2.GTPE2.CLK_COR_REPEAT_WAIT[1] 29_573 -GTP_CHANNEL_2.GTPE2.CLK_COR_REPEAT_WAIT[2] 28_574 -GTP_CHANNEL_2.GTPE2.CLK_COR_REPEAT_WAIT[3] 29_574 -GTP_CHANNEL_2.GTPE2.CLK_COR_REPEAT_WAIT[4] 28_575 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_1_1[0] 28_544 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_1_1[1] 29_544 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_1_1[2] 28_545 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_1_1[3] 29_545 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_1_1[4] 28_546 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_1_1[5] 29_546 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_1_1[6] 28_547 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_1_1[7] 29_547 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_1_1[8] 28_548 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_1_1[9] 29_548 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_1_2[0] 28_552 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_1_2[1] 29_552 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_1_2[2] 28_553 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_1_2[3] 29_553 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_1_2[4] 28_554 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_1_2[5] 29_554 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_1_2[6] 28_555 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_1_2[7] 29_555 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_1_2[8] 28_556 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_1_2[9] 29_556 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_1_3[0] 28_560 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_1_3[1] 29_560 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_1_3[2] 28_561 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_1_3[3] 29_561 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_1_3[4] 28_562 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_1_3[5] 29_562 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_1_3[6] 28_563 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_1_3[7] 29_563 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_1_3[8] 28_564 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_1_3[9] 29_564 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_1_4[0] 28_568 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_1_4[1] 29_568 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_1_4[2] 28_569 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_1_4[3] 29_569 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_1_4[4] 28_570 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_1_4[5] 29_570 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_1_4[6] 28_571 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_1_4[7] 29_571 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_1_4[8] 28_572 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_1_4[9] 29_572 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_1_ENABLE[0] 28_549 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_1_ENABLE[1] 29_549 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_1_ENABLE[2] 28_550 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_1_ENABLE[3] 29_550 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_2_1[0] 28_576 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_2_1[1] 29_576 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_2_1[2] 28_577 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_2_1[3] 29_577 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_2_1[4] 28_578 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_2_1[5] 29_578 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_2_1[6] 28_579 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_2_1[7] 29_579 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_2_1[8] 28_580 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_2_1[9] 29_580 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_2_2[0] 28_584 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_2_2[1] 29_584 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_2_2[2] 28_585 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_2_2[3] 29_585 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_2_2[4] 28_586 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_2_2[5] 29_586 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_2_2[6] 28_587 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_2_2[7] 29_587 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_2_2[8] 28_588 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_2_2[9] 29_588 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_2_3[0] 28_592 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_2_3[1] 29_592 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_2_3[2] 28_593 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_2_3[3] 29_593 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_2_3[4] 28_594 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_2_3[5] 29_594 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_2_3[6] 28_595 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_2_3[7] 29_595 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_2_3[8] 28_596 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_2_3[9] 29_596 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_2_4[0] 28_600 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_2_4[1] 29_600 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_2_4[2] 28_601 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_2_4[3] 29_601 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_2_4[4] 28_602 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_2_4[5] 29_602 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_2_4[6] 28_603 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_2_4[7] 29_603 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_2_4[8] 28_604 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_2_4[9] 29_604 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_2_ENABLE[0] 28_581 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_2_ENABLE[1] 29_581 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_2_ENABLE[2] 28_582 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_2_ENABLE[3] 29_582 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_2_USE 28_583 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_LEN[0] 28_589 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_LEN[1] 29_589 -GTP_CHANNEL_2.GTPE2.CLK_CORRECT_USE 28_551 -GTP_CHANNEL_2.GTPE2.DEC_MCOMMA_DETECT 29_494 -GTP_CHANNEL_2.GTPE2.DEC_PCOMMA_DETECT 28_495 -GTP_CHANNEL_2.GTPE2.DEC_VALID_COMMA_ONLY 28_494 -GTP_CHANNEL_2.GTPE2.DMONITOR_CFG[0] 30_368 -GTP_CHANNEL_2.GTPE2.DMONITOR_CFG[1] 31_368 -GTP_CHANNEL_2.GTPE2.DMONITOR_CFG[2] 30_369 -GTP_CHANNEL_2.GTPE2.DMONITOR_CFG[3] 31_369 -GTP_CHANNEL_2.GTPE2.DMONITOR_CFG[4] 30_370 -GTP_CHANNEL_2.GTPE2.DMONITOR_CFG[5] 31_370 -GTP_CHANNEL_2.GTPE2.DMONITOR_CFG[6] 30_371 -GTP_CHANNEL_2.GTPE2.DMONITOR_CFG[7] 31_371 -GTP_CHANNEL_2.GTPE2.DMONITOR_CFG[8] 30_372 -GTP_CHANNEL_2.GTPE2.DMONITOR_CFG[9] 31_372 -GTP_CHANNEL_2.GTPE2.DMONITOR_CFG[10] 30_373 -GTP_CHANNEL_2.GTPE2.DMONITOR_CFG[11] 31_373 -GTP_CHANNEL_2.GTPE2.DMONITOR_CFG[12] 30_374 -GTP_CHANNEL_2.GTPE2.DMONITOR_CFG[13] 31_374 -GTP_CHANNEL_2.GTPE2.DMONITOR_CFG[14] 30_375 -GTP_CHANNEL_2.GTPE2.DMONITOR_CFG[15] 31_375 -GTP_CHANNEL_2.GTPE2.DMONITOR_CFG[16] 30_376 -GTP_CHANNEL_2.GTPE2.DMONITOR_CFG[17] 31_376 -GTP_CHANNEL_2.GTPE2.DMONITOR_CFG[18] 30_377 -GTP_CHANNEL_2.GTPE2.DMONITOR_CFG[19] 31_377 -GTP_CHANNEL_2.GTPE2.DMONITOR_CFG[20] 30_378 -GTP_CHANNEL_2.GTPE2.DMONITOR_CFG[21] 31_378 -GTP_CHANNEL_2.GTPE2.DMONITOR_CFG[22] 30_379 -GTP_CHANNEL_2.GTPE2.DMONITOR_CFG[23] 31_379 -GTP_CHANNEL_2.GTPE2.ES_CLK_PHASE_SEL[0] 31_463 -GTP_CHANNEL_2.GTPE2.ES_CONTROL[0] 28_488 -GTP_CHANNEL_2.GTPE2.ES_CONTROL[1] 29_488 -GTP_CHANNEL_2.GTPE2.ES_CONTROL[2] 28_489 -GTP_CHANNEL_2.GTPE2.ES_CONTROL[3] 29_489 -GTP_CHANNEL_2.GTPE2.ES_CONTROL[4] 28_490 -GTP_CHANNEL_2.GTPE2.ES_CONTROL[5] 29_490 -GTP_CHANNEL_2.GTPE2.ES_ERRDET_EN 29_492 -GTP_CHANNEL_2.GTPE2.ES_EYE_SCAN_EN 28_492 -GTP_CHANNEL_2.GTPE2.ES_HORZ_OFFSET[0] 28_480 -GTP_CHANNEL_2.GTPE2.ES_HORZ_OFFSET[1] 29_480 -GTP_CHANNEL_2.GTPE2.ES_HORZ_OFFSET[2] 28_481 -GTP_CHANNEL_2.GTPE2.ES_HORZ_OFFSET[3] 29_481 -GTP_CHANNEL_2.GTPE2.ES_HORZ_OFFSET[4] 28_482 -GTP_CHANNEL_2.GTPE2.ES_HORZ_OFFSET[5] 29_482 -GTP_CHANNEL_2.GTPE2.ES_HORZ_OFFSET[6] 28_483 -GTP_CHANNEL_2.GTPE2.ES_HORZ_OFFSET[7] 29_483 -GTP_CHANNEL_2.GTPE2.ES_HORZ_OFFSET[8] 28_484 -GTP_CHANNEL_2.GTPE2.ES_HORZ_OFFSET[9] 29_484 -GTP_CHANNEL_2.GTPE2.ES_HORZ_OFFSET[10] 28_485 -GTP_CHANNEL_2.GTPE2.ES_HORZ_OFFSET[11] 29_485 -GTP_CHANNEL_2.GTPE2.ES_PMA_CFG[0] 30_624 -GTP_CHANNEL_2.GTPE2.ES_PMA_CFG[1] 31_624 -GTP_CHANNEL_2.GTPE2.ES_PMA_CFG[2] 30_625 -GTP_CHANNEL_2.GTPE2.ES_PMA_CFG[3] 31_625 -GTP_CHANNEL_2.GTPE2.ES_PMA_CFG[4] 30_626 -GTP_CHANNEL_2.GTPE2.ES_PMA_CFG[5] 31_626 -GTP_CHANNEL_2.GTPE2.ES_PMA_CFG[6] 30_627 -GTP_CHANNEL_2.GTPE2.ES_PMA_CFG[7] 31_627 -GTP_CHANNEL_2.GTPE2.ES_PMA_CFG[8] 30_628 -GTP_CHANNEL_2.GTPE2.ES_PMA_CFG[9] 31_628 -GTP_CHANNEL_2.GTPE2.ES_PRESCALE[0] 29_477 -GTP_CHANNEL_2.GTPE2.ES_PRESCALE[1] 28_478 -GTP_CHANNEL_2.GTPE2.ES_PRESCALE[2] 29_478 -GTP_CHANNEL_2.GTPE2.ES_PRESCALE[3] 28_479 -GTP_CHANNEL_2.GTPE2.ES_PRESCALE[4] 29_479 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[0] 28_392 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[1] 29_392 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[2] 28_393 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[3] 29_393 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[4] 28_394 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[5] 29_394 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[6] 28_395 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[7] 29_395 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[8] 28_396 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[9] 29_396 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[10] 28_397 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[11] 29_397 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[12] 28_398 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[13] 29_398 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[14] 28_399 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[15] 29_399 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[16] 28_400 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[17] 29_400 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[18] 28_401 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[19] 29_401 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[20] 28_402 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[21] 29_402 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[22] 28_403 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[23] 29_403 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[24] 28_404 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[25] 29_404 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[26] 28_405 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[27] 29_405 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[28] 28_406 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[29] 29_406 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[30] 28_407 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[31] 29_407 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[32] 28_408 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[33] 29_408 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[34] 28_409 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[35] 29_409 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[36] 28_410 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[37] 29_410 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[38] 28_411 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[39] 29_411 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[40] 28_412 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[41] 29_412 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[42] 28_413 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[43] 29_413 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[44] 28_414 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[45] 29_414 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[46] 28_415 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[47] 29_415 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[48] 28_416 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[49] 29_416 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[50] 28_417 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[51] 29_417 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[52] 28_418 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[53] 29_418 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[54] 28_419 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[55] 29_419 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[56] 28_420 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[57] 29_420 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[58] 28_421 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[59] 29_421 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[60] 28_422 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[61] 29_422 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[62] 28_423 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[63] 29_423 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[64] 28_424 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[65] 29_424 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[66] 28_425 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[67] 29_425 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[68] 28_426 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[69] 29_426 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[70] 28_427 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[71] 29_427 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[72] 28_428 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[73] 29_428 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[74] 28_429 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[75] 29_429 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[76] 28_430 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[77] 29_430 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[78] 28_431 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[79] 29_431 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[0] 28_352 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[1] 29_352 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[2] 28_353 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[3] 29_353 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[4] 28_354 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[5] 29_354 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[6] 28_355 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[7] 29_355 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[8] 28_356 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[9] 29_356 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[10] 28_357 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[11] 29_357 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[12] 28_358 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[13] 29_358 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[14] 28_359 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[15] 29_359 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[16] 28_360 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[17] 29_360 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[18] 28_361 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[19] 29_361 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[20] 28_362 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[21] 29_362 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[22] 28_363 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[23] 29_363 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[24] 28_364 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[25] 29_364 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[26] 28_365 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[27] 29_365 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[28] 28_366 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[29] 29_366 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[30] 28_367 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[31] 29_367 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[32] 28_368 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[33] 29_368 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[34] 28_369 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[35] 29_369 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[36] 28_370 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[37] 29_370 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[38] 28_371 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[39] 29_371 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[40] 28_372 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[41] 29_372 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[42] 28_373 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[43] 29_373 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[44] 28_374 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[45] 29_374 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[46] 28_375 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[47] 29_375 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[48] 28_376 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[49] 29_376 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[50] 28_377 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[51] 29_377 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[52] 28_378 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[53] 29_378 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[54] 28_379 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[55] 29_379 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[56] 28_380 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[57] 29_380 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[58] 28_381 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[59] 29_381 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[60] 28_382 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[61] 29_382 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[62] 28_383 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[63] 29_383 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[64] 28_384 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[65] 29_384 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[66] 28_385 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[67] 29_385 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[68] 28_386 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[69] 29_386 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[70] 28_387 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[71] 29_387 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[72] 28_388 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[73] 29_388 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[74] 28_389 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[75] 29_389 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[76] 28_390 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[77] 29_390 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[78] 28_391 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[79] 29_391 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[0] 28_432 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[1] 29_432 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[2] 28_433 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[3] 29_433 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[4] 28_434 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[5] 29_434 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[6] 28_435 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[7] 29_435 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[8] 28_436 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[9] 29_436 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[10] 28_437 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[11] 29_437 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[12] 28_438 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[13] 29_438 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[14] 28_439 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[15] 29_439 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[16] 28_440 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[17] 29_440 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[18] 28_441 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[19] 29_441 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[20] 28_442 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[21] 29_442 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[22] 28_443 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[23] 29_443 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[24] 28_444 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[25] 29_444 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[26] 28_445 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[27] 29_445 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[28] 28_446 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[29] 29_446 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[30] 28_447 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[31] 29_447 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[32] 28_448 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[33] 29_448 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[34] 28_449 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[35] 29_449 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[36] 28_450 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[37] 29_450 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[38] 28_451 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[39] 29_451 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[40] 28_452 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[41] 29_452 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[42] 28_453 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[43] 29_453 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[44] 28_454 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[45] 29_454 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[46] 28_455 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[47] 29_455 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[48] 28_456 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[49] 29_456 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[50] 28_457 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[51] 29_457 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[52] 28_458 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[53] 29_458 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[54] 28_459 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[55] 29_459 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[56] 28_460 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[57] 29_460 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[58] 28_461 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[59] 29_461 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[60] 28_462 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[61] 29_462 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[62] 28_463 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[63] 29_463 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[64] 28_464 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[65] 29_464 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[66] 28_465 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[67] 29_465 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[68] 28_466 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[69] 29_466 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[70] 28_467 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[71] 29_467 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[72] 28_468 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[73] 29_468 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[74] 28_469 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[75] 29_469 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[76] 28_470 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[77] 29_470 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[78] 28_471 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[79] 29_471 -GTP_CHANNEL_2.GTPE2.ES_VERT_OFFSET[0] 28_472 -GTP_CHANNEL_2.GTPE2.ES_VERT_OFFSET[1] 29_472 -GTP_CHANNEL_2.GTPE2.ES_VERT_OFFSET[2] 28_473 -GTP_CHANNEL_2.GTPE2.ES_VERT_OFFSET[3] 29_473 -GTP_CHANNEL_2.GTPE2.ES_VERT_OFFSET[4] 28_474 -GTP_CHANNEL_2.GTPE2.ES_VERT_OFFSET[5] 29_474 -GTP_CHANNEL_2.GTPE2.ES_VERT_OFFSET[6] 28_475 -GTP_CHANNEL_2.GTPE2.ES_VERT_OFFSET[7] 29_475 -GTP_CHANNEL_2.GTPE2.ES_VERT_OFFSET[8] 28_476 -GTP_CHANNEL_2.GTPE2.FTS_DESKEW_SEQ_ENABLE[0] 28_662 -GTP_CHANNEL_2.GTPE2.FTS_DESKEW_SEQ_ENABLE[1] 29_662 -GTP_CHANNEL_2.GTPE2.FTS_DESKEW_SEQ_ENABLE[2] 28_663 -GTP_CHANNEL_2.GTPE2.FTS_DESKEW_SEQ_ENABLE[3] 29_663 -GTP_CHANNEL_2.GTPE2.FTS_LANE_DESKEW_CFG[0] 28_654 -GTP_CHANNEL_2.GTPE2.FTS_LANE_DESKEW_CFG[1] 29_654 -GTP_CHANNEL_2.GTPE2.FTS_LANE_DESKEW_CFG[2] 28_655 -GTP_CHANNEL_2.GTPE2.FTS_LANE_DESKEW_CFG[3] 29_655 -GTP_CHANNEL_2.GTPE2.FTS_LANE_DESKEW_EN 29_653 -GTP_CHANNEL_2.GTPE2.GEARBOX_MODE[0] 28_224 -GTP_CHANNEL_2.GTPE2.GEARBOX_MODE[1] 29_224 -GTP_CHANNEL_2.GTPE2.GEARBOX_MODE[2] 28_225 -GTP_CHANNEL_2.GTPE2.IN_USE 28_00 28_01 28_47 28_52 28_53 28_65 29_01 29_47 30_129 -GTP_CHANNEL_2.GTPE2.LOOPBACK_CFG[0] 30_20 -GTP_CHANNEL_2.GTPE2.OUTREFCLK_SEL_INV[0] 28_149 -GTP_CHANNEL_2.GTPE2.OUTREFCLK_SEL_INV[1] 29_149 -GTP_CHANNEL_2.GTPE2.PCS_PCIE_EN 28_216 -GTP_CHANNEL_2.GTPE2.PCS_RSVD_ATTR[0] 30_184 -GTP_CHANNEL_2.GTPE2.PCS_RSVD_ATTR[1] 31_184 -GTP_CHANNEL_2.GTPE2.PCS_RSVD_ATTR[2] 30_185 -GTP_CHANNEL_2.GTPE2.PCS_RSVD_ATTR[3] 31_185 -GTP_CHANNEL_2.GTPE2.PCS_RSVD_ATTR[4] 30_186 -GTP_CHANNEL_2.GTPE2.PCS_RSVD_ATTR[5] 31_186 -GTP_CHANNEL_2.GTPE2.PCS_RSVD_ATTR[6] 30_187 -GTP_CHANNEL_2.GTPE2.PCS_RSVD_ATTR[7] 31_187 -GTP_CHANNEL_2.GTPE2.PCS_RSVD_ATTR[8] 30_188 -GTP_CHANNEL_2.GTPE2.PCS_RSVD_ATTR[9] 31_188 -GTP_CHANNEL_2.GTPE2.PCS_RSVD_ATTR[10] 30_189 -GTP_CHANNEL_2.GTPE2.PCS_RSVD_ATTR[11] 31_189 -GTP_CHANNEL_2.GTPE2.PCS_RSVD_ATTR[12] 30_190 -GTP_CHANNEL_2.GTPE2.PCS_RSVD_ATTR[13] 31_190 -GTP_CHANNEL_2.GTPE2.PCS_RSVD_ATTR[14] 30_191 -GTP_CHANNEL_2.GTPE2.PCS_RSVD_ATTR[15] 31_191 -GTP_CHANNEL_2.GTPE2.PCS_RSVD_ATTR[16] 30_192 -GTP_CHANNEL_2.GTPE2.PCS_RSVD_ATTR[17] 31_192 -GTP_CHANNEL_2.GTPE2.PCS_RSVD_ATTR[18] 30_193 -GTP_CHANNEL_2.GTPE2.PCS_RSVD_ATTR[19] 31_193 -GTP_CHANNEL_2.GTPE2.PCS_RSVD_ATTR[20] 30_194 -GTP_CHANNEL_2.GTPE2.PCS_RSVD_ATTR[21] 31_194 -GTP_CHANNEL_2.GTPE2.PCS_RSVD_ATTR[22] 30_195 -GTP_CHANNEL_2.GTPE2.PCS_RSVD_ATTR[23] 31_195 -GTP_CHANNEL_2.GTPE2.PCS_RSVD_ATTR[24] 30_196 -GTP_CHANNEL_2.GTPE2.PCS_RSVD_ATTR[25] 31_196 -GTP_CHANNEL_2.GTPE2.PCS_RSVD_ATTR[26] 30_197 -GTP_CHANNEL_2.GTPE2.PCS_RSVD_ATTR[27] 31_197 -GTP_CHANNEL_2.GTPE2.PCS_RSVD_ATTR[28] 30_198 -GTP_CHANNEL_2.GTPE2.PCS_RSVD_ATTR[29] 31_198 -GTP_CHANNEL_2.GTPE2.PCS_RSVD_ATTR[30] 30_199 -GTP_CHANNEL_2.GTPE2.PCS_RSVD_ATTR[31] 31_199 -GTP_CHANNEL_2.GTPE2.PCS_RSVD_ATTR[32] 30_200 -GTP_CHANNEL_2.GTPE2.PCS_RSVD_ATTR[33] 31_200 -GTP_CHANNEL_2.GTPE2.PCS_RSVD_ATTR[34] 30_201 -GTP_CHANNEL_2.GTPE2.PCS_RSVD_ATTR[35] 31_201 -GTP_CHANNEL_2.GTPE2.PCS_RSVD_ATTR[36] 30_202 -GTP_CHANNEL_2.GTPE2.PCS_RSVD_ATTR[37] 31_202 -GTP_CHANNEL_2.GTPE2.PCS_RSVD_ATTR[38] 30_203 -GTP_CHANNEL_2.GTPE2.PCS_RSVD_ATTR[39] 31_203 -GTP_CHANNEL_2.GTPE2.PCS_RSVD_ATTR[40] 30_204 -GTP_CHANNEL_2.GTPE2.PCS_RSVD_ATTR[41] 31_204 -GTP_CHANNEL_2.GTPE2.PCS_RSVD_ATTR[42] 30_205 -GTP_CHANNEL_2.GTPE2.PCS_RSVD_ATTR[43] 31_205 -GTP_CHANNEL_2.GTPE2.PCS_RSVD_ATTR[44] 30_206 -GTP_CHANNEL_2.GTPE2.PCS_RSVD_ATTR[45] 31_206 -GTP_CHANNEL_2.GTPE2.PCS_RSVD_ATTR[46] 30_207 -GTP_CHANNEL_2.GTPE2.PCS_RSVD_ATTR[47] 31_207 -GTP_CHANNEL_2.GTPE2.PD_TRANS_TIME_FROM_P2[0] 29_216 -GTP_CHANNEL_2.GTPE2.PD_TRANS_TIME_FROM_P2[1] 28_217 -GTP_CHANNEL_2.GTPE2.PD_TRANS_TIME_FROM_P2[2] 29_217 -GTP_CHANNEL_2.GTPE2.PD_TRANS_TIME_FROM_P2[3] 28_218 -GTP_CHANNEL_2.GTPE2.PD_TRANS_TIME_FROM_P2[4] 29_218 -GTP_CHANNEL_2.GTPE2.PD_TRANS_TIME_FROM_P2[5] 28_219 -GTP_CHANNEL_2.GTPE2.PD_TRANS_TIME_FROM_P2[6] 29_219 -GTP_CHANNEL_2.GTPE2.PD_TRANS_TIME_FROM_P2[7] 28_220 -GTP_CHANNEL_2.GTPE2.PD_TRANS_TIME_FROM_P2[8] 29_220 -GTP_CHANNEL_2.GTPE2.PD_TRANS_TIME_FROM_P2[9] 28_221 -GTP_CHANNEL_2.GTPE2.PD_TRANS_TIME_FROM_P2[10] 29_221 -GTP_CHANNEL_2.GTPE2.PD_TRANS_TIME_FROM_P2[11] 28_222 -GTP_CHANNEL_2.GTPE2.PD_TRANS_TIME_NONE_P2[0] 28_208 -GTP_CHANNEL_2.GTPE2.PD_TRANS_TIME_NONE_P2[1] 29_208 -GTP_CHANNEL_2.GTPE2.PD_TRANS_TIME_NONE_P2[2] 28_209 -GTP_CHANNEL_2.GTPE2.PD_TRANS_TIME_NONE_P2[3] 29_209 -GTP_CHANNEL_2.GTPE2.PD_TRANS_TIME_NONE_P2[4] 28_210 -GTP_CHANNEL_2.GTPE2.PD_TRANS_TIME_NONE_P2[5] 29_210 -GTP_CHANNEL_2.GTPE2.PD_TRANS_TIME_NONE_P2[6] 28_211 -GTP_CHANNEL_2.GTPE2.PD_TRANS_TIME_NONE_P2[7] 29_211 -GTP_CHANNEL_2.GTPE2.PD_TRANS_TIME_TO_P2[0] 28_212 -GTP_CHANNEL_2.GTPE2.PD_TRANS_TIME_TO_P2[1] 29_212 -GTP_CHANNEL_2.GTPE2.PD_TRANS_TIME_TO_P2[2] 28_213 -GTP_CHANNEL_2.GTPE2.PD_TRANS_TIME_TO_P2[3] 29_213 -GTP_CHANNEL_2.GTPE2.PD_TRANS_TIME_TO_P2[4] 28_214 -GTP_CHANNEL_2.GTPE2.PD_TRANS_TIME_TO_P2[5] 29_214 -GTP_CHANNEL_2.GTPE2.PD_TRANS_TIME_TO_P2[6] 28_215 -GTP_CHANNEL_2.GTPE2.PD_TRANS_TIME_TO_P2[7] 29_215 -GTP_CHANNEL_2.GTPE2.PMA_LOOPBACK_CFG[0] 29_207 -GTP_CHANNEL_2.GTPE2.PMA_RSV[0] 30_520 -GTP_CHANNEL_2.GTPE2.PMA_RSV[1] 31_520 -GTP_CHANNEL_2.GTPE2.PMA_RSV[2] 30_521 -GTP_CHANNEL_2.GTPE2.PMA_RSV[3] 31_521 -GTP_CHANNEL_2.GTPE2.PMA_RSV[4] 30_522 -GTP_CHANNEL_2.GTPE2.PMA_RSV[5] 31_522 -GTP_CHANNEL_2.GTPE2.PMA_RSV[6] 30_523 -GTP_CHANNEL_2.GTPE2.PMA_RSV[7] 31_523 -GTP_CHANNEL_2.GTPE2.PMA_RSV[8] 30_524 -GTP_CHANNEL_2.GTPE2.PMA_RSV[9] 31_524 -GTP_CHANNEL_2.GTPE2.PMA_RSV[10] 30_525 -GTP_CHANNEL_2.GTPE2.PMA_RSV[11] 31_525 -GTP_CHANNEL_2.GTPE2.PMA_RSV[12] 30_526 -GTP_CHANNEL_2.GTPE2.PMA_RSV[13] 31_526 -GTP_CHANNEL_2.GTPE2.PMA_RSV[14] 30_527 -GTP_CHANNEL_2.GTPE2.PMA_RSV[15] 31_527 -GTP_CHANNEL_2.GTPE2.PMA_RSV[16] 30_528 -GTP_CHANNEL_2.GTPE2.PMA_RSV[17] 31_528 -GTP_CHANNEL_2.GTPE2.PMA_RSV[18] 30_529 -GTP_CHANNEL_2.GTPE2.PMA_RSV[19] 31_529 -GTP_CHANNEL_2.GTPE2.PMA_RSV[20] 30_530 -GTP_CHANNEL_2.GTPE2.PMA_RSV[21] 31_530 -GTP_CHANNEL_2.GTPE2.PMA_RSV[22] 30_531 -GTP_CHANNEL_2.GTPE2.PMA_RSV[23] 31_531 -GTP_CHANNEL_2.GTPE2.PMA_RSV[24] 30_532 -GTP_CHANNEL_2.GTPE2.PMA_RSV[25] 31_532 -GTP_CHANNEL_2.GTPE2.PMA_RSV[26] 30_533 -GTP_CHANNEL_2.GTPE2.PMA_RSV[27] 31_533 -GTP_CHANNEL_2.GTPE2.PMA_RSV[28] 30_534 -GTP_CHANNEL_2.GTPE2.PMA_RSV[29] 31_534 -GTP_CHANNEL_2.GTPE2.PMA_RSV[30] 30_535 -GTP_CHANNEL_2.GTPE2.PMA_RSV[31] 31_535 -GTP_CHANNEL_2.GTPE2.PMA_RSV2[0] 30_336 -GTP_CHANNEL_2.GTPE2.PMA_RSV2[1] 31_336 -GTP_CHANNEL_2.GTPE2.PMA_RSV2[2] 30_337 -GTP_CHANNEL_2.GTPE2.PMA_RSV2[3] 31_337 -GTP_CHANNEL_2.GTPE2.PMA_RSV2[4] 30_338 -GTP_CHANNEL_2.GTPE2.PMA_RSV2[5] 31_338 -GTP_CHANNEL_2.GTPE2.PMA_RSV2[6] 30_339 -GTP_CHANNEL_2.GTPE2.PMA_RSV2[7] 31_339 -GTP_CHANNEL_2.GTPE2.PMA_RSV2[8] 30_340 -GTP_CHANNEL_2.GTPE2.PMA_RSV2[9] 31_340 -GTP_CHANNEL_2.GTPE2.PMA_RSV2[10] 30_341 -GTP_CHANNEL_2.GTPE2.PMA_RSV2[11] 31_341 -GTP_CHANNEL_2.GTPE2.PMA_RSV2[12] 30_342 -GTP_CHANNEL_2.GTPE2.PMA_RSV2[13] 31_342 -GTP_CHANNEL_2.GTPE2.PMA_RSV2[14] 30_343 -GTP_CHANNEL_2.GTPE2.PMA_RSV2[15] 31_343 -GTP_CHANNEL_2.GTPE2.PMA_RSV2[16] 30_344 -GTP_CHANNEL_2.GTPE2.PMA_RSV2[17] 31_344 -GTP_CHANNEL_2.GTPE2.PMA_RSV2[18] 30_345 -GTP_CHANNEL_2.GTPE2.PMA_RSV2[19] 31_345 -GTP_CHANNEL_2.GTPE2.PMA_RSV2[20] 30_346 -GTP_CHANNEL_2.GTPE2.PMA_RSV2[21] 31_346 -GTP_CHANNEL_2.GTPE2.PMA_RSV2[22] 30_347 -GTP_CHANNEL_2.GTPE2.PMA_RSV2[23] 31_347 -GTP_CHANNEL_2.GTPE2.PMA_RSV2[24] 30_348 -GTP_CHANNEL_2.GTPE2.PMA_RSV2[25] 31_348 -GTP_CHANNEL_2.GTPE2.PMA_RSV2[26] 30_349 -GTP_CHANNEL_2.GTPE2.PMA_RSV2[27] 31_349 -GTP_CHANNEL_2.GTPE2.PMA_RSV2[28] 30_350 -GTP_CHANNEL_2.GTPE2.PMA_RSV2[29] 31_350 -GTP_CHANNEL_2.GTPE2.PMA_RSV2[30] 30_351 -GTP_CHANNEL_2.GTPE2.PMA_RSV2[31] 31_351 -GTP_CHANNEL_2.GTPE2.PMA_RSV3[0] 30_288 -GTP_CHANNEL_2.GTPE2.PMA_RSV3[1] 31_288 -GTP_CHANNEL_2.GTPE2.PMA_RSV4[0] 30_156 -GTP_CHANNEL_2.GTPE2.PMA_RSV4[1] 31_156 -GTP_CHANNEL_2.GTPE2.PMA_RSV4[2] 30_157 -GTP_CHANNEL_2.GTPE2.PMA_RSV4[3] 31_157 -GTP_CHANNEL_2.GTPE2.PMA_RSV5[0] 31_159 -GTP_CHANNEL_2.GTPE2.PMA_RSV6[0] 30_303 -GTP_CHANNEL_2.GTPE2.PMA_RSV7[0] 31_303 -GTP_CHANNEL_2.GTPE2.RX_BIAS_CFG[0] 30_112 -GTP_CHANNEL_2.GTPE2.RX_BIAS_CFG[1] 31_112 -GTP_CHANNEL_2.GTPE2.RX_BIAS_CFG[2] 30_113 -GTP_CHANNEL_2.GTPE2.RX_BIAS_CFG[3] 31_113 -GTP_CHANNEL_2.GTPE2.RX_BIAS_CFG[4] 30_114 -GTP_CHANNEL_2.GTPE2.RX_BIAS_CFG[5] 31_114 -GTP_CHANNEL_2.GTPE2.RX_BIAS_CFG[6] 30_115 -GTP_CHANNEL_2.GTPE2.RX_BIAS_CFG[7] 31_115 -GTP_CHANNEL_2.GTPE2.RX_BIAS_CFG[8] 30_116 -GTP_CHANNEL_2.GTPE2.RX_BIAS_CFG[9] 31_116 -GTP_CHANNEL_2.GTPE2.RX_BIAS_CFG[10] 30_117 -GTP_CHANNEL_2.GTPE2.RX_BIAS_CFG[11] 31_117 -GTP_CHANNEL_2.GTPE2.RX_BIAS_CFG[12] 30_118 -GTP_CHANNEL_2.GTPE2.RX_BIAS_CFG[13] 31_118 -GTP_CHANNEL_2.GTPE2.RX_BIAS_CFG[14] 30_119 -GTP_CHANNEL_2.GTPE2.RX_BIAS_CFG[15] 31_119 -GTP_CHANNEL_2.GTPE2.RX_BUFFER_CFG[0] 30_536 -GTP_CHANNEL_2.GTPE2.RX_BUFFER_CFG[1] 31_536 -GTP_CHANNEL_2.GTPE2.RX_BUFFER_CFG[2] 30_537 -GTP_CHANNEL_2.GTPE2.RX_BUFFER_CFG[3] 31_537 -GTP_CHANNEL_2.GTPE2.RX_BUFFER_CFG[4] 30_538 -GTP_CHANNEL_2.GTPE2.RX_BUFFER_CFG[5] 31_538 -GTP_CHANNEL_2.GTPE2.RX_CLKMUX_EN[0] 30_128 -GTP_CHANNEL_2.GTPE2.RX_CM_SEL[0] 28_138 -GTP_CHANNEL_2.GTPE2.RX_CM_SEL[1] 29_138 -GTP_CHANNEL_2.GTPE2.RX_CM_TRIM[0] 30_304 -GTP_CHANNEL_2.GTPE2.RX_CM_TRIM[1] 31_304 -GTP_CHANNEL_2.GTPE2.RX_CM_TRIM[2] 30_305 -GTP_CHANNEL_2.GTPE2.RX_CM_TRIM[3] 31_305 -GTP_CHANNEL_2.GTPE2.RX_DATA_WIDTH[0] 29_141 -GTP_CHANNEL_2.GTPE2.RX_DATA_WIDTH[1] 28_142 -GTP_CHANNEL_2.GTPE2.RX_DATA_WIDTH[2] 29_142 -GTP_CHANNEL_2.GTPE2.RX_DDI_SEL[0] 28_696 -GTP_CHANNEL_2.GTPE2.RX_DDI_SEL[1] 29_696 -GTP_CHANNEL_2.GTPE2.RX_DDI_SEL[2] 28_697 -GTP_CHANNEL_2.GTPE2.RX_DDI_SEL[3] 29_697 -GTP_CHANNEL_2.GTPE2.RX_DDI_SEL[4] 28_698 -GTP_CHANNEL_2.GTPE2.RX_DDI_SEL[5] 29_698 -GTP_CHANNEL_2.GTPE2.RX_DEBUG_CFG[0] 30_616 -GTP_CHANNEL_2.GTPE2.RX_DEBUG_CFG[1] 31_616 -GTP_CHANNEL_2.GTPE2.RX_DEBUG_CFG[2] 30_617 -GTP_CHANNEL_2.GTPE2.RX_DEBUG_CFG[3] 31_617 -GTP_CHANNEL_2.GTPE2.RX_DEBUG_CFG[4] 30_618 -GTP_CHANNEL_2.GTPE2.RX_DEBUG_CFG[5] 31_618 -GTP_CHANNEL_2.GTPE2.RX_DEBUG_CFG[6] 30_619 -GTP_CHANNEL_2.GTPE2.RX_DEBUG_CFG[7] 31_619 -GTP_CHANNEL_2.GTPE2.RX_DEBUG_CFG[8] 30_620 -GTP_CHANNEL_2.GTPE2.RX_DEBUG_CFG[9] 31_620 -GTP_CHANNEL_2.GTPE2.RX_DEBUG_CFG[10] 30_621 -GTP_CHANNEL_2.GTPE2.RX_DEBUG_CFG[11] 31_621 -GTP_CHANNEL_2.GTPE2.RX_DEBUG_CFG[12] 30_622 -GTP_CHANNEL_2.GTPE2.RX_DEBUG_CFG[13] 31_622 -GTP_CHANNEL_2.GTPE2.RX_DEFER_RESET_BUF_EN 30_552 -GTP_CHANNEL_2.GTPE2.RX_DISPERR_SEQ_MATCH 29_495 -GTP_CHANNEL_2.GTPE2.RX_OS_CFG[0] 28_288 -GTP_CHANNEL_2.GTPE2.RX_OS_CFG[1] 29_288 -GTP_CHANNEL_2.GTPE2.RX_OS_CFG[2] 28_289 -GTP_CHANNEL_2.GTPE2.RX_OS_CFG[3] 29_289 -GTP_CHANNEL_2.GTPE2.RX_OS_CFG[4] 28_290 -GTP_CHANNEL_2.GTPE2.RX_OS_CFG[5] 29_290 -GTP_CHANNEL_2.GTPE2.RX_OS_CFG[6] 28_291 -GTP_CHANNEL_2.GTPE2.RX_OS_CFG[7] 29_291 -GTP_CHANNEL_2.GTPE2.RX_OS_CFG[8] 28_292 -GTP_CHANNEL_2.GTPE2.RX_OS_CFG[9] 29_292 -GTP_CHANNEL_2.GTPE2.RX_OS_CFG[10] 28_293 -GTP_CHANNEL_2.GTPE2.RX_OS_CFG[11] 29_293 -GTP_CHANNEL_2.GTPE2.RX_OS_CFG[12] 28_294 -GTP_CHANNEL_2.GTPE2.RX_SIG_VALID_DLY[0] 28_524 -GTP_CHANNEL_2.GTPE2.RX_SIG_VALID_DLY[1] 29_524 -GTP_CHANNEL_2.GTPE2.RX_SIG_VALID_DLY[2] 28_525 -GTP_CHANNEL_2.GTPE2.RX_SIG_VALID_DLY[3] 29_525 -GTP_CHANNEL_2.GTPE2.RX_SIG_VALID_DLY[4] 28_526 -GTP_CHANNEL_2.GTPE2.RX_XCLK_SEL.RXUSR 28_143 -GTP_CHANNEL_2.GTPE2.RX_CLK25_DIV[0] 28_139 -GTP_CHANNEL_2.GTPE2.RX_CLK25_DIV[1] 29_139 -GTP_CHANNEL_2.GTPE2.RX_CLK25_DIV[2] 28_140 -GTP_CHANNEL_2.GTPE2.RX_CLK25_DIV[3] 29_140 -GTP_CHANNEL_2.GTPE2.RX_CLK25_DIV[4] 28_141 -GTP_CHANNEL_2.GTPE2.RXBUF_ADDR_MODE.FAST 31_555 -GTP_CHANNEL_2.GTPE2.RXBUF_EIDLE_HI_CNT[0] 30_558 -GTP_CHANNEL_2.GTPE2.RXBUF_EIDLE_HI_CNT[1] 31_558 -GTP_CHANNEL_2.GTPE2.RXBUF_EIDLE_HI_CNT[2] 30_559 -GTP_CHANNEL_2.GTPE2.RXBUF_EIDLE_HI_CNT[3] 31_559 -GTP_CHANNEL_2.GTPE2.RXBUF_EIDLE_LO_CNT[0] 30_556 -GTP_CHANNEL_2.GTPE2.RXBUF_EIDLE_LO_CNT[1] 31_556 -GTP_CHANNEL_2.GTPE2.RXBUF_EIDLE_LO_CNT[2] 30_557 -GTP_CHANNEL_2.GTPE2.RXBUF_EIDLE_LO_CNT[3] 31_557 -GTP_CHANNEL_2.GTPE2.RXBUF_EN 30_11 -GTP_CHANNEL_2.GTPE2.RXBUF_RESET_ON_CB_CHANGE 30_560 -GTP_CHANNEL_2.GTPE2.RXBUF_RESET_ON_COMMAALIGN 30_561 -GTP_CHANNEL_2.GTPE2.RXBUF_RESET_ON_EIDLE 30_547 -GTP_CHANNEL_2.GTPE2.RXBUF_RESET_ON_RATE_CHANGE 31_560 -GTP_CHANNEL_2.GTPE2.RXBUF_THRESH_OVFLW[0] 31_552 -GTP_CHANNEL_2.GTPE2.RXBUF_THRESH_OVFLW[1] 30_553 -GTP_CHANNEL_2.GTPE2.RXBUF_THRESH_OVFLW[2] 31_553 -GTP_CHANNEL_2.GTPE2.RXBUF_THRESH_OVFLW[3] 30_554 -GTP_CHANNEL_2.GTPE2.RXBUF_THRESH_OVFLW[4] 31_554 -GTP_CHANNEL_2.GTPE2.RXBUF_THRESH_OVFLW[5] 30_555 -GTP_CHANNEL_2.GTPE2.RXBUF_THRESH_OVRD 30_548 -GTP_CHANNEL_2.GTPE2.RXBUF_THRESH_UNDFLW[0] 30_544 -GTP_CHANNEL_2.GTPE2.RXBUF_THRESH_UNDFLW[1] 31_544 -GTP_CHANNEL_2.GTPE2.RXBUF_THRESH_UNDFLW[2] 30_545 -GTP_CHANNEL_2.GTPE2.RXBUF_THRESH_UNDFLW[3] 31_545 -GTP_CHANNEL_2.GTPE2.RXBUF_THRESH_UNDFLW[4] 30_546 -GTP_CHANNEL_2.GTPE2.RXBUF_THRESH_UNDFLW[5] 31_546 -GTP_CHANNEL_2.GTPE2.RXBUFRESET_TIME[0] 29_101 -GTP_CHANNEL_2.GTPE2.RXBUFRESET_TIME[1] 28_102 -GTP_CHANNEL_2.GTPE2.RXBUFRESET_TIME[2] 29_102 -GTP_CHANNEL_2.GTPE2.RXBUFRESET_TIME[3] 28_103 -GTP_CHANNEL_2.GTPE2.RXBUFRESET_TIME[4] 29_103 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[0] 30_640 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[1] 31_640 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[2] 30_641 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[3] 31_641 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[4] 30_642 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[5] 31_642 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[6] 30_643 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[7] 31_643 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[8] 30_644 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[9] 31_644 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[10] 30_645 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[11] 31_645 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[12] 30_646 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[13] 31_646 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[14] 30_647 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[15] 31_647 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[16] 30_648 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[17] 31_648 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[18] 30_649 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[19] 31_649 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[20] 30_650 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[21] 31_650 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[22] 30_651 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[23] 31_651 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[24] 30_652 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[25] 31_652 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[26] 30_653 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[27] 31_653 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[28] 30_654 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[29] 31_654 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[30] 30_655 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[31] 31_655 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[32] 30_656 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[33] 31_656 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[34] 30_657 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[35] 31_657 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[36] 30_658 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[37] 31_658 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[38] 30_659 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[39] 31_659 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[40] 30_660 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[41] 31_660 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[42] 30_661 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[43] 31_661 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[44] 30_662 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[45] 31_662 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[46] 30_663 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[47] 31_663 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[48] 30_664 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[49] 31_664 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[50] 30_665 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[51] 31_665 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[52] 30_666 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[53] 31_666 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[54] 30_667 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[55] 31_667 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[56] 30_668 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[57] 31_668 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[58] 30_669 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[59] 31_669 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[60] 30_670 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[61] 31_670 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[62] 30_671 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[63] 31_671 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[64] 30_672 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[65] 31_672 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[66] 30_673 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[67] 31_673 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[68] 30_674 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[69] 31_674 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[70] 30_675 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[71] 31_675 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[72] 30_676 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[73] 31_676 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[74] 30_677 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[75] 31_677 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[76] 30_678 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[77] 31_678 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[78] 30_679 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[79] 31_679 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[80] 30_680 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[81] 31_680 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[82] 30_681 -GTP_CHANNEL_2.GTPE2.RXCDR_FR_RESET_ON_EIDLE[0] 30_638 -GTP_CHANNEL_2.GTPE2.RXCDR_HOLD_DURING_EIDLE[0] 31_637 -GTP_CHANNEL_2.GTPE2.RXCDR_LOCK_CFG[0] 30_632 -GTP_CHANNEL_2.GTPE2.RXCDR_LOCK_CFG[1] 31_632 -GTP_CHANNEL_2.GTPE2.RXCDR_LOCK_CFG[2] 30_633 -GTP_CHANNEL_2.GTPE2.RXCDR_LOCK_CFG[3] 31_633 -GTP_CHANNEL_2.GTPE2.RXCDR_LOCK_CFG[4] 30_634 -GTP_CHANNEL_2.GTPE2.RXCDR_LOCK_CFG[5] 31_634 -GTP_CHANNEL_2.GTPE2.RXCDR_PH_RESET_ON_EIDLE[0] 31_638 -GTP_CHANNEL_2.GTPE2.RXCDRFREQRESET_TIME[0] 29_106 -GTP_CHANNEL_2.GTPE2.RXCDRFREQRESET_TIME[1] 28_107 -GTP_CHANNEL_2.GTPE2.RXCDRFREQRESET_TIME[2] 29_107 -GTP_CHANNEL_2.GTPE2.RXCDRFREQRESET_TIME[3] 28_108 -GTP_CHANNEL_2.GTPE2.RXCDRFREQRESET_TIME[4] 29_108 -GTP_CHANNEL_2.GTPE2.RXCDRPHRESET_TIME[0] 28_109 -GTP_CHANNEL_2.GTPE2.RXCDRPHRESET_TIME[1] 29_109 -GTP_CHANNEL_2.GTPE2.RXCDRPHRESET_TIME[2] 28_110 -GTP_CHANNEL_2.GTPE2.RXCDRPHRESET_TIME[3] 29_110 -GTP_CHANNEL_2.GTPE2.RXCDRPHRESET_TIME[4] 28_111 -GTP_CHANNEL_2.GTPE2.RXDLY_CFG[0] 28_680 -GTP_CHANNEL_2.GTPE2.RXDLY_CFG[1] 29_680 -GTP_CHANNEL_2.GTPE2.RXDLY_CFG[2] 28_681 -GTP_CHANNEL_2.GTPE2.RXDLY_CFG[3] 29_681 -GTP_CHANNEL_2.GTPE2.RXDLY_CFG[4] 28_682 -GTP_CHANNEL_2.GTPE2.RXDLY_CFG[5] 29_682 -GTP_CHANNEL_2.GTPE2.RXDLY_CFG[6] 28_683 -GTP_CHANNEL_2.GTPE2.RXDLY_CFG[7] 29_683 -GTP_CHANNEL_2.GTPE2.RXDLY_CFG[8] 28_684 -GTP_CHANNEL_2.GTPE2.RXDLY_CFG[9] 29_684 -GTP_CHANNEL_2.GTPE2.RXDLY_CFG[10] 28_685 -GTP_CHANNEL_2.GTPE2.RXDLY_CFG[11] 29_685 -GTP_CHANNEL_2.GTPE2.RXDLY_CFG[12] 28_686 -GTP_CHANNEL_2.GTPE2.RXDLY_CFG[13] 29_686 -GTP_CHANNEL_2.GTPE2.RXDLY_CFG[14] 28_687 -GTP_CHANNEL_2.GTPE2.RXDLY_CFG[15] 29_687 -GTP_CHANNEL_2.GTPE2.RXDLY_LCFG[0] 30_576 -GTP_CHANNEL_2.GTPE2.RXDLY_LCFG[1] 31_576 -GTP_CHANNEL_2.GTPE2.RXDLY_LCFG[2] 30_577 -GTP_CHANNEL_2.GTPE2.RXDLY_LCFG[3] 31_577 -GTP_CHANNEL_2.GTPE2.RXDLY_LCFG[4] 30_578 -GTP_CHANNEL_2.GTPE2.RXDLY_LCFG[5] 31_578 -GTP_CHANNEL_2.GTPE2.RXDLY_LCFG[6] 30_579 -GTP_CHANNEL_2.GTPE2.RXDLY_LCFG[7] 31_579 -GTP_CHANNEL_2.GTPE2.RXDLY_LCFG[8] 30_580 -GTP_CHANNEL_2.GTPE2.RXDLY_TAP_CFG[0] 28_672 -GTP_CHANNEL_2.GTPE2.RXDLY_TAP_CFG[1] 29_672 -GTP_CHANNEL_2.GTPE2.RXDLY_TAP_CFG[2] 28_673 -GTP_CHANNEL_2.GTPE2.RXDLY_TAP_CFG[3] 29_673 -GTP_CHANNEL_2.GTPE2.RXDLY_TAP_CFG[4] 28_674 -GTP_CHANNEL_2.GTPE2.RXDLY_TAP_CFG[5] 29_674 -GTP_CHANNEL_2.GTPE2.RXDLY_TAP_CFG[6] 28_675 -GTP_CHANNEL_2.GTPE2.RXDLY_TAP_CFG[7] 29_675 -GTP_CHANNEL_2.GTPE2.RXDLY_TAP_CFG[8] 28_676 -GTP_CHANNEL_2.GTPE2.RXDLY_TAP_CFG[9] 29_676 -GTP_CHANNEL_2.GTPE2.RXDLY_TAP_CFG[10] 28_677 -GTP_CHANNEL_2.GTPE2.RXDLY_TAP_CFG[11] 29_677 -GTP_CHANNEL_2.GTPE2.RXDLY_TAP_CFG[12] 28_678 -GTP_CHANNEL_2.GTPE2.RXDLY_TAP_CFG[13] 29_678 -GTP_CHANNEL_2.GTPE2.RXDLY_TAP_CFG[14] 28_679 -GTP_CHANNEL_2.GTPE2.RXDLY_TAP_CFG[15] 29_679 -GTP_CHANNEL_2.GTPE2.RXGEARBOX_EN 29_607 -GTP_CHANNEL_2.GTPE2.RXISCANRESET_TIME[0] 29_123 -GTP_CHANNEL_2.GTPE2.RXISCANRESET_TIME[1] 28_124 -GTP_CHANNEL_2.GTPE2.RXISCANRESET_TIME[2] 29_124 -GTP_CHANNEL_2.GTPE2.RXISCANRESET_TIME[3] 28_125 -GTP_CHANNEL_2.GTPE2.RXISCANRESET_TIME[4] 29_125 -GTP_CHANNEL_2.GTPE2.RXLPM_BIAS_STARTUP_DISABLE[0] 31_391 -GTP_CHANNEL_2.GTPE2.RXLPM_CFG[0] 30_328 -GTP_CHANNEL_2.GTPE2.RXLPM_CFG[1] 31_328 -GTP_CHANNEL_2.GTPE2.RXLPM_CFG[2] 30_329 -GTP_CHANNEL_2.GTPE2.RXLPM_CFG[3] 31_329 -GTP_CHANNEL_2.GTPE2.RXLPM_CM_CFG[0] 30_430 -GTP_CHANNEL_2.GTPE2.RXLPM_GC_CFG[0] 30_432 -GTP_CHANNEL_2.GTPE2.RXLPM_GC_CFG[1] 31_432 -GTP_CHANNEL_2.GTPE2.RXLPM_GC_CFG[2] 30_433 -GTP_CHANNEL_2.GTPE2.RXLPM_GC_CFG[3] 31_433 -GTP_CHANNEL_2.GTPE2.RXLPM_GC_CFG[4] 30_434 -GTP_CHANNEL_2.GTPE2.RXLPM_GC_CFG[5] 31_434 -GTP_CHANNEL_2.GTPE2.RXLPM_GC_CFG[6] 30_435 -GTP_CHANNEL_2.GTPE2.RXLPM_GC_CFG[7] 31_435 -GTP_CHANNEL_2.GTPE2.RXLPM_GC_CFG[8] 30_436 -GTP_CHANNEL_2.GTPE2.RXLPM_GC_CFG2[0] 31_442 -GTP_CHANNEL_2.GTPE2.RXLPM_GC_CFG2[1] 30_443 -GTP_CHANNEL_2.GTPE2.RXLPM_GC_CFG2[2] 31_443 -GTP_CHANNEL_2.GTPE2.RXLPM_HF_CFG[0] 28_336 -GTP_CHANNEL_2.GTPE2.RXLPM_HF_CFG[1] 29_336 -GTP_CHANNEL_2.GTPE2.RXLPM_HF_CFG[2] 28_337 -GTP_CHANNEL_2.GTPE2.RXLPM_HF_CFG[3] 29_337 -GTP_CHANNEL_2.GTPE2.RXLPM_HF_CFG[4] 28_338 -GTP_CHANNEL_2.GTPE2.RXLPM_HF_CFG[5] 29_338 -GTP_CHANNEL_2.GTPE2.RXLPM_HF_CFG[6] 28_339 -GTP_CHANNEL_2.GTPE2.RXLPM_HF_CFG[7] 29_339 -GTP_CHANNEL_2.GTPE2.RXLPM_HF_CFG[8] 28_340 -GTP_CHANNEL_2.GTPE2.RXLPM_HF_CFG[9] 29_340 -GTP_CHANNEL_2.GTPE2.RXLPM_HF_CFG[10] 28_341 -GTP_CHANNEL_2.GTPE2.RXLPM_HF_CFG[11] 29_341 -GTP_CHANNEL_2.GTPE2.RXLPM_HF_CFG[12] 28_342 -GTP_CHANNEL_2.GTPE2.RXLPM_HF_CFG[13] 29_342 -GTP_CHANNEL_2.GTPE2.RXLPM_HF_CFG2[0] 30_424 -GTP_CHANNEL_2.GTPE2.RXLPM_HF_CFG2[1] 31_424 -GTP_CHANNEL_2.GTPE2.RXLPM_HF_CFG2[2] 30_425 -GTP_CHANNEL_2.GTPE2.RXLPM_HF_CFG2[3] 31_425 -GTP_CHANNEL_2.GTPE2.RXLPM_HF_CFG2[4] 30_426 -GTP_CHANNEL_2.GTPE2.RXLPM_HF_CFG3[0] 31_389 -GTP_CHANNEL_2.GTPE2.RXLPM_HF_CFG3[1] 30_390 -GTP_CHANNEL_2.GTPE2.RXLPM_HF_CFG3[2] 31_390 -GTP_CHANNEL_2.GTPE2.RXLPM_HF_CFG3[3] 30_391 -GTP_CHANNEL_2.GTPE2.RXLPM_HOLD_DURING_EIDLE[0] 28_247 -GTP_CHANNEL_2.GTPE2.RXLPM_INCM_CFG[0] 30_439 -GTP_CHANNEL_2.GTPE2.RXLPM_IPCM_CFG[0] 31_439 -GTP_CHANNEL_2.GTPE2.RXLPM_LF_CFG[0] 28_344 -GTP_CHANNEL_2.GTPE2.RXLPM_LF_CFG[1] 29_344 -GTP_CHANNEL_2.GTPE2.RXLPM_LF_CFG[2] 28_345 -GTP_CHANNEL_2.GTPE2.RXLPM_LF_CFG[3] 29_345 -GTP_CHANNEL_2.GTPE2.RXLPM_LF_CFG[4] 28_346 -GTP_CHANNEL_2.GTPE2.RXLPM_LF_CFG[5] 29_346 -GTP_CHANNEL_2.GTPE2.RXLPM_LF_CFG[6] 28_347 -GTP_CHANNEL_2.GTPE2.RXLPM_LF_CFG[7] 29_347 -GTP_CHANNEL_2.GTPE2.RXLPM_LF_CFG[8] 28_348 -GTP_CHANNEL_2.GTPE2.RXLPM_LF_CFG[9] 29_348 -GTP_CHANNEL_2.GTPE2.RXLPM_LF_CFG[10] 28_349 -GTP_CHANNEL_2.GTPE2.RXLPM_LF_CFG[11] 29_349 -GTP_CHANNEL_2.GTPE2.RXLPM_LF_CFG[12] 28_350 -GTP_CHANNEL_2.GTPE2.RXLPM_LF_CFG[13] 29_350 -GTP_CHANNEL_2.GTPE2.RXLPM_LF_CFG[14] 28_351 -GTP_CHANNEL_2.GTPE2.RXLPM_LF_CFG[15] 29_351 -GTP_CHANNEL_2.GTPE2.RXLPM_LF_CFG[16] 28_343 -GTP_CHANNEL_2.GTPE2.RXLPM_LF_CFG[17] 29_343 -GTP_CHANNEL_2.GTPE2.RXLPM_LF_CFG2[0] 31_426 -GTP_CHANNEL_2.GTPE2.RXLPM_LF_CFG2[1] 30_427 -GTP_CHANNEL_2.GTPE2.RXLPM_LF_CFG2[2] 31_427 -GTP_CHANNEL_2.GTPE2.RXLPM_LF_CFG2[3] 30_428 -GTP_CHANNEL_2.GTPE2.RXLPM_LF_CFG2[4] 31_428 -GTP_CHANNEL_2.GTPE2.RXLPM_OSINT_CFG[0] 30_440 -GTP_CHANNEL_2.GTPE2.RXLPM_OSINT_CFG[1] 31_440 -GTP_CHANNEL_2.GTPE2.RXLPM_OSINT_CFG[2] 30_441 -GTP_CHANNEL_2.GTPE2.RXLPM_CFG1[0] 30_330 -GTP_CHANNEL_2.GTPE2.RXLPMRESET_TIME[0] 28_112 -GTP_CHANNEL_2.GTPE2.RXLPMRESET_TIME[1] 29_112 -GTP_CHANNEL_2.GTPE2.RXLPMRESET_TIME[2] 28_113 -GTP_CHANNEL_2.GTPE2.RXLPMRESET_TIME[3] 29_113 -GTP_CHANNEL_2.GTPE2.RXLPMRESET_TIME[4] 28_114 -GTP_CHANNEL_2.GTPE2.RXLPMRESET_TIME[5] 29_114 -GTP_CHANNEL_2.GTPE2.RXLPMRESET_TIME[6] 28_115 -GTP_CHANNEL_2.GTPE2.RXOOB_CFG[0] 28_144 -GTP_CHANNEL_2.GTPE2.RXOOB_CFG[1] 29_144 -GTP_CHANNEL_2.GTPE2.RXOOB_CFG[2] 28_145 -GTP_CHANNEL_2.GTPE2.RXOOB_CFG[3] 29_145 -GTP_CHANNEL_2.GTPE2.RXOOB_CFG[4] 28_146 -GTP_CHANNEL_2.GTPE2.RXOOB_CFG[5] 29_146 -GTP_CHANNEL_2.GTPE2.RXOOB_CFG[6] 28_147 -GTP_CHANNEL_2.GTPE2.RXOOB_CLK_CFG.FABRIC 31_129 -GTP_CHANNEL_2.GTPE2.RXOSCALRESET_TIME[0] 28_187 -GTP_CHANNEL_2.GTPE2.RXOSCALRESET_TIME[1] 29_187 -GTP_CHANNEL_2.GTPE2.RXOSCALRESET_TIME[2] 28_188 -GTP_CHANNEL_2.GTPE2.RXOSCALRESET_TIME[3] 29_188 -GTP_CHANNEL_2.GTPE2.RXOSCALRESET_TIME[4] 28_189 -GTP_CHANNEL_2.GTPE2.RXOSCALRESET_TIMEOUT[0] 29_189 -GTP_CHANNEL_2.GTPE2.RXOSCALRESET_TIMEOUT[1] 28_190 -GTP_CHANNEL_2.GTPE2.RXOSCALRESET_TIMEOUT[2] 29_190 -GTP_CHANNEL_2.GTPE2.RXOSCALRESET_TIMEOUT[3] 28_191 -GTP_CHANNEL_2.GTPE2.RXOSCALRESET_TIMEOUT[4] 29_191 -GTP_CHANNEL_2.GTPE2.RXOUT_DIV[0] 30_384 -GTP_CHANNEL_2.GTPE2.RXOUT_DIV[1] 31_384 -GTP_CHANNEL_2.GTPE2.RXPCSRESET_TIME[0] 29_115 -GTP_CHANNEL_2.GTPE2.RXPCSRESET_TIME[1] 28_116 -GTP_CHANNEL_2.GTPE2.RXPCSRESET_TIME[2] 29_116 -GTP_CHANNEL_2.GTPE2.RXPCSRESET_TIME[3] 28_117 -GTP_CHANNEL_2.GTPE2.RXPCSRESET_TIME[4] 29_117 -GTP_CHANNEL_2.GTPE2.RXPH_CFG[0] 30_584 -GTP_CHANNEL_2.GTPE2.RXPH_CFG[1] 31_584 -GTP_CHANNEL_2.GTPE2.RXPH_CFG[2] 30_585 -GTP_CHANNEL_2.GTPE2.RXPH_CFG[3] 31_585 -GTP_CHANNEL_2.GTPE2.RXPH_CFG[4] 30_586 -GTP_CHANNEL_2.GTPE2.RXPH_CFG[5] 31_586 -GTP_CHANNEL_2.GTPE2.RXPH_CFG[6] 30_587 -GTP_CHANNEL_2.GTPE2.RXPH_CFG[7] 31_587 -GTP_CHANNEL_2.GTPE2.RXPH_CFG[8] 30_588 -GTP_CHANNEL_2.GTPE2.RXPH_CFG[9] 31_588 -GTP_CHANNEL_2.GTPE2.RXPH_CFG[10] 30_589 -GTP_CHANNEL_2.GTPE2.RXPH_CFG[11] 31_589 -GTP_CHANNEL_2.GTPE2.RXPH_CFG[12] 30_590 -GTP_CHANNEL_2.GTPE2.RXPH_CFG[13] 31_590 -GTP_CHANNEL_2.GTPE2.RXPH_CFG[14] 30_591 -GTP_CHANNEL_2.GTPE2.RXPH_CFG[15] 31_591 -GTP_CHANNEL_2.GTPE2.RXPH_CFG[16] 30_592 -GTP_CHANNEL_2.GTPE2.RXPH_CFG[17] 31_592 -GTP_CHANNEL_2.GTPE2.RXPH_CFG[18] 30_593 -GTP_CHANNEL_2.GTPE2.RXPH_CFG[19] 31_593 -GTP_CHANNEL_2.GTPE2.RXPH_CFG[20] 30_594 -GTP_CHANNEL_2.GTPE2.RXPH_CFG[21] 31_594 -GTP_CHANNEL_2.GTPE2.RXPH_CFG[22] 30_595 -GTP_CHANNEL_2.GTPE2.RXPH_CFG[23] 31_595 -GTP_CHANNEL_2.GTPE2.RXPH_MONITOR_SEL[0] 28_700 -GTP_CHANNEL_2.GTPE2.RXPH_MONITOR_SEL[1] 29_700 -GTP_CHANNEL_2.GTPE2.RXPH_MONITOR_SEL[2] 28_701 -GTP_CHANNEL_2.GTPE2.RXPH_MONITOR_SEL[3] 29_701 -GTP_CHANNEL_2.GTPE2.RXPH_MONITOR_SEL[4] 28_702 -GTP_CHANNEL_2.GTPE2.RXPHDLY_CFG[0] 30_600 -GTP_CHANNEL_2.GTPE2.RXPHDLY_CFG[1] 31_600 -GTP_CHANNEL_2.GTPE2.RXPHDLY_CFG[2] 30_601 -GTP_CHANNEL_2.GTPE2.RXPHDLY_CFG[3] 31_601 -GTP_CHANNEL_2.GTPE2.RXPHDLY_CFG[4] 30_602 -GTP_CHANNEL_2.GTPE2.RXPHDLY_CFG[5] 31_602 -GTP_CHANNEL_2.GTPE2.RXPHDLY_CFG[6] 30_603 -GTP_CHANNEL_2.GTPE2.RXPHDLY_CFG[7] 31_603 -GTP_CHANNEL_2.GTPE2.RXPHDLY_CFG[8] 30_604 -GTP_CHANNEL_2.GTPE2.RXPHDLY_CFG[9] 31_604 -GTP_CHANNEL_2.GTPE2.RXPHDLY_CFG[10] 30_605 -GTP_CHANNEL_2.GTPE2.RXPHDLY_CFG[11] 31_605 -GTP_CHANNEL_2.GTPE2.RXPHDLY_CFG[12] 30_606 -GTP_CHANNEL_2.GTPE2.RXPHDLY_CFG[13] 31_606 -GTP_CHANNEL_2.GTPE2.RXPHDLY_CFG[14] 30_607 -GTP_CHANNEL_2.GTPE2.RXPHDLY_CFG[15] 31_607 -GTP_CHANNEL_2.GTPE2.RXPHDLY_CFG[16] 30_608 -GTP_CHANNEL_2.GTPE2.RXPHDLY_CFG[17] 31_608 -GTP_CHANNEL_2.GTPE2.RXPHDLY_CFG[18] 30_609 -GTP_CHANNEL_2.GTPE2.RXPHDLY_CFG[19] 31_609 -GTP_CHANNEL_2.GTPE2.RXPHDLY_CFG[20] 30_610 -GTP_CHANNEL_2.GTPE2.RXPHDLY_CFG[21] 31_610 -GTP_CHANNEL_2.GTPE2.RXPHDLY_CFG[22] 30_611 -GTP_CHANNEL_2.GTPE2.RXPHDLY_CFG[23] 31_611 -GTP_CHANNEL_2.GTPE2.RXPI_CFG0[0] 31_430 -GTP_CHANNEL_2.GTPE2.RXPI_CFG0[1] 30_431 -GTP_CHANNEL_2.GTPE2.RXPI_CFG0[2] 31_431 -GTP_CHANNEL_2.GTPE2.RXPI_CFG1[0] 30_442 -GTP_CHANNEL_2.GTPE2.RXPI_CFG2[0] 31_441 -GTP_CHANNEL_2.GTPE2.RXPMARESET_TIME[0] 28_104 -GTP_CHANNEL_2.GTPE2.RXPMARESET_TIME[1] 29_104 -GTP_CHANNEL_2.GTPE2.RXPMARESET_TIME[2] 28_105 -GTP_CHANNEL_2.GTPE2.RXPMARESET_TIME[3] 29_105 -GTP_CHANNEL_2.GTPE2.RXPMARESET_TIME[4] 28_106 -GTP_CHANNEL_2.GTPE2.RXPRBS_ERR_LOOPBACK[0] 28_136 -GTP_CHANNEL_2.GTPE2.RXSLIDE_AUTO_WAIT[0] 28_520 -GTP_CHANNEL_2.GTPE2.RXSLIDE_AUTO_WAIT[1] 29_520 -GTP_CHANNEL_2.GTPE2.RXSLIDE_AUTO_WAIT[2] 28_521 -GTP_CHANNEL_2.GTPE2.RXSLIDE_AUTO_WAIT[3] 29_521 -GTP_CHANNEL_2.GTPE2.RXSLIDE_MODE.AUTO 28_519 !29_519 -GTP_CHANNEL_2.GTPE2.RXSLIDE_MODE.PCS !28_519 29_519 -GTP_CHANNEL_2.GTPE2.RXSLIDE_MODE.PMA 28_519 29_519 -GTP_CHANNEL_2.GTPE2.RXSYNC_MULTILANE[0] 28_133 -GTP_CHANNEL_2.GTPE2.RXSYNC_OVRD[0] 29_135 -GTP_CHANNEL_2.GTPE2.RXSYNC_SKIP_DA[0] 29_134 -GTP_CHANNEL_2.GTPE2.SAS_MAX_COM[0] 28_171 -GTP_CHANNEL_2.GTPE2.SAS_MAX_COM[1] 29_171 -GTP_CHANNEL_2.GTPE2.SAS_MAX_COM[2] 28_172 -GTP_CHANNEL_2.GTPE2.SAS_MAX_COM[3] 29_172 -GTP_CHANNEL_2.GTPE2.SAS_MAX_COM[4] 28_173 -GTP_CHANNEL_2.GTPE2.SAS_MAX_COM[5] 29_173 -GTP_CHANNEL_2.GTPE2.SAS_MAX_COM[6] 28_174 -GTP_CHANNEL_2.GTPE2.SAS_MIN_COM[0] 29_156 -GTP_CHANNEL_2.GTPE2.SAS_MIN_COM[1] 28_157 -GTP_CHANNEL_2.GTPE2.SAS_MIN_COM[2] 29_157 -GTP_CHANNEL_2.GTPE2.SAS_MIN_COM[3] 28_158 -GTP_CHANNEL_2.GTPE2.SAS_MIN_COM[4] 29_158 -GTP_CHANNEL_2.GTPE2.SAS_MIN_COM[5] 28_159 -GTP_CHANNEL_2.GTPE2.SATA_BURST_SEQ_LEN[0] 28_150 -GTP_CHANNEL_2.GTPE2.SATA_BURST_SEQ_LEN[1] 29_150 -GTP_CHANNEL_2.GTPE2.SATA_BURST_SEQ_LEN[2] 28_151 -GTP_CHANNEL_2.GTPE2.SATA_BURST_SEQ_LEN[3] 29_151 -GTP_CHANNEL_2.GTPE2.SATA_BURST_VAL[0] 29_147 -GTP_CHANNEL_2.GTPE2.SATA_BURST_VAL[1] 28_148 -GTP_CHANNEL_2.GTPE2.SATA_BURST_VAL[2] 29_148 -GTP_CHANNEL_2.GTPE2.SATA_EIDLE_VAL[0] 28_152 -GTP_CHANNEL_2.GTPE2.SATA_EIDLE_VAL[1] 29_152 -GTP_CHANNEL_2.GTPE2.SATA_EIDLE_VAL[2] 28_153 -GTP_CHANNEL_2.GTPE2.SATA_MAX_BURST[0] 28_168 -GTP_CHANNEL_2.GTPE2.SATA_MAX_BURST[1] 29_168 -GTP_CHANNEL_2.GTPE2.SATA_MAX_BURST[2] 28_169 -GTP_CHANNEL_2.GTPE2.SATA_MAX_BURST[3] 29_169 -GTP_CHANNEL_2.GTPE2.SATA_MAX_BURST[4] 28_170 -GTP_CHANNEL_2.GTPE2.SATA_MAX_BURST[5] 29_170 -GTP_CHANNEL_2.GTPE2.SATA_MAX_INIT[0] 28_176 -GTP_CHANNEL_2.GTPE2.SATA_MAX_INIT[1] 29_176 -GTP_CHANNEL_2.GTPE2.SATA_MAX_INIT[2] 28_177 -GTP_CHANNEL_2.GTPE2.SATA_MAX_INIT[3] 29_177 -GTP_CHANNEL_2.GTPE2.SATA_MAX_INIT[4] 28_178 -GTP_CHANNEL_2.GTPE2.SATA_MAX_INIT[5] 29_178 -GTP_CHANNEL_2.GTPE2.SATA_MAX_WAKE[0] 28_179 -GTP_CHANNEL_2.GTPE2.SATA_MAX_WAKE[1] 29_179 -GTP_CHANNEL_2.GTPE2.SATA_MAX_WAKE[2] 28_180 -GTP_CHANNEL_2.GTPE2.SATA_MAX_WAKE[3] 29_180 -GTP_CHANNEL_2.GTPE2.SATA_MAX_WAKE[4] 28_181 -GTP_CHANNEL_2.GTPE2.SATA_MAX_WAKE[5] 29_181 -GTP_CHANNEL_2.GTPE2.SATA_MIN_BURST[0] 29_153 -GTP_CHANNEL_2.GTPE2.SATA_MIN_BURST[1] 28_154 -GTP_CHANNEL_2.GTPE2.SATA_MIN_BURST[2] 29_154 -GTP_CHANNEL_2.GTPE2.SATA_MIN_BURST[3] 28_155 -GTP_CHANNEL_2.GTPE2.SATA_MIN_BURST[4] 29_155 -GTP_CHANNEL_2.GTPE2.SATA_MIN_BURST[5] 28_156 -GTP_CHANNEL_2.GTPE2.SATA_MIN_INIT[0] 28_160 -GTP_CHANNEL_2.GTPE2.SATA_MIN_INIT[1] 29_160 -GTP_CHANNEL_2.GTPE2.SATA_MIN_INIT[2] 28_161 -GTP_CHANNEL_2.GTPE2.SATA_MIN_INIT[3] 29_161 -GTP_CHANNEL_2.GTPE2.SATA_MIN_INIT[4] 28_162 -GTP_CHANNEL_2.GTPE2.SATA_MIN_INIT[5] 29_162 -GTP_CHANNEL_2.GTPE2.SATA_MIN_WAKE[0] 28_163 -GTP_CHANNEL_2.GTPE2.SATA_MIN_WAKE[1] 29_163 -GTP_CHANNEL_2.GTPE2.SATA_MIN_WAKE[2] 28_164 -GTP_CHANNEL_2.GTPE2.SATA_MIN_WAKE[3] 29_164 -GTP_CHANNEL_2.GTPE2.SATA_MIN_WAKE[4] 28_165 -GTP_CHANNEL_2.GTPE2.SATA_MIN_WAKE[5] 29_165 -GTP_CHANNEL_2.GTPE2.SATA_PLL_CFG.VCO_1500MHZ 30_55 -GTP_CHANNEL_2.GTPE2.SATA_PLL_CFG.VCO_750MHZ 31_55 -GTP_CHANNEL_2.GTPE2.SHOW_REALIGN_COMMA 29_522 -GTP_CHANNEL_2.GTPE2.TERM_RCAL_CFG[0] 30_136 -GTP_CHANNEL_2.GTPE2.TERM_RCAL_CFG[1] 31_136 -GTP_CHANNEL_2.GTPE2.TERM_RCAL_CFG[2] 30_137 -GTP_CHANNEL_2.GTPE2.TERM_RCAL_CFG[3] 31_137 -GTP_CHANNEL_2.GTPE2.TERM_RCAL_CFG[4] 30_138 -GTP_CHANNEL_2.GTPE2.TERM_RCAL_CFG[5] 31_138 -GTP_CHANNEL_2.GTPE2.TERM_RCAL_CFG[6] 30_139 -GTP_CHANNEL_2.GTPE2.TERM_RCAL_CFG[7] 31_139 -GTP_CHANNEL_2.GTPE2.TERM_RCAL_CFG[8] 30_140 -GTP_CHANNEL_2.GTPE2.TERM_RCAL_CFG[9] 31_140 -GTP_CHANNEL_2.GTPE2.TERM_RCAL_CFG[10] 30_141 -GTP_CHANNEL_2.GTPE2.TERM_RCAL_CFG[11] 31_141 -GTP_CHANNEL_2.GTPE2.TERM_RCAL_CFG[12] 30_142 -GTP_CHANNEL_2.GTPE2.TERM_RCAL_CFG[13] 31_142 -GTP_CHANNEL_2.GTPE2.TERM_RCAL_CFG[14] 30_143 -GTP_CHANNEL_2.GTPE2.TERM_RCAL_OVRD[0] 31_150 -GTP_CHANNEL_2.GTPE2.TERM_RCAL_OVRD[1] 30_151 -GTP_CHANNEL_2.GTPE2.TERM_RCAL_OVRD[2] 31_151 -GTP_CHANNEL_2.GTPE2.TRANS_TIME_RATE[0] 28_192 -GTP_CHANNEL_2.GTPE2.TRANS_TIME_RATE[1] 29_192 -GTP_CHANNEL_2.GTPE2.TRANS_TIME_RATE[2] 28_193 -GTP_CHANNEL_2.GTPE2.TRANS_TIME_RATE[3] 29_193 -GTP_CHANNEL_2.GTPE2.TRANS_TIME_RATE[4] 28_194 -GTP_CHANNEL_2.GTPE2.TRANS_TIME_RATE[5] 29_194 -GTP_CHANNEL_2.GTPE2.TRANS_TIME_RATE[6] 28_195 -GTP_CHANNEL_2.GTPE2.TRANS_TIME_RATE[7] 29_195 -GTP_CHANNEL_2.GTPE2.TST_RSV[0] 30_504 -GTP_CHANNEL_2.GTPE2.TST_RSV[1] 31_504 -GTP_CHANNEL_2.GTPE2.TST_RSV[2] 30_505 -GTP_CHANNEL_2.GTPE2.TST_RSV[3] 31_505 -GTP_CHANNEL_2.GTPE2.TST_RSV[4] 30_506 -GTP_CHANNEL_2.GTPE2.TST_RSV[5] 31_506 -GTP_CHANNEL_2.GTPE2.TST_RSV[6] 30_507 -GTP_CHANNEL_2.GTPE2.TST_RSV[7] 31_507 -GTP_CHANNEL_2.GTPE2.TST_RSV[8] 30_508 -GTP_CHANNEL_2.GTPE2.TST_RSV[9] 31_508 -GTP_CHANNEL_2.GTPE2.TST_RSV[10] 30_509 -GTP_CHANNEL_2.GTPE2.TST_RSV[11] 31_509 -GTP_CHANNEL_2.GTPE2.TST_RSV[12] 30_510 -GTP_CHANNEL_2.GTPE2.TST_RSV[13] 31_510 -GTP_CHANNEL_2.GTPE2.TST_RSV[14] 30_511 -GTP_CHANNEL_2.GTPE2.TST_RSV[15] 31_511 -GTP_CHANNEL_2.GTPE2.TST_RSV[16] 30_512 -GTP_CHANNEL_2.GTPE2.TST_RSV[17] 31_512 -GTP_CHANNEL_2.GTPE2.TST_RSV[18] 30_513 -GTP_CHANNEL_2.GTPE2.TST_RSV[19] 31_513 -GTP_CHANNEL_2.GTPE2.TST_RSV[20] 30_514 -GTP_CHANNEL_2.GTPE2.TST_RSV[21] 31_514 -GTP_CHANNEL_2.GTPE2.TST_RSV[22] 30_515 -GTP_CHANNEL_2.GTPE2.TST_RSV[23] 31_515 -GTP_CHANNEL_2.GTPE2.TST_RSV[24] 30_516 -GTP_CHANNEL_2.GTPE2.TST_RSV[25] 31_516 -GTP_CHANNEL_2.GTPE2.TST_RSV[26] 30_517 -GTP_CHANNEL_2.GTPE2.TST_RSV[27] 31_517 -GTP_CHANNEL_2.GTPE2.TST_RSV[28] 30_518 -GTP_CHANNEL_2.GTPE2.TST_RSV[29] 31_518 -GTP_CHANNEL_2.GTPE2.TST_RSV[30] 30_519 -GTP_CHANNEL_2.GTPE2.TST_RSV[31] 31_519 -GTP_CHANNEL_2.GTPE2.TX_CLKMUX_EN[0] 31_128 -GTP_CHANNEL_2.GTPE2.TX_DATA_WIDTH[0] 30_152 -GTP_CHANNEL_2.GTPE2.TX_DATA_WIDTH[1] 31_152 -GTP_CHANNEL_2.GTPE2.TX_DATA_WIDTH[2] 30_153 -GTP_CHANNEL_2.GTPE2.TX_DRIVE_MODE.PIPE 28_200 -GTP_CHANNEL_2.GTPE2.TX_EIDLE_ASSERT_DELAY[0] 28_203 -GTP_CHANNEL_2.GTPE2.TX_EIDLE_ASSERT_DELAY[1] 29_203 -GTP_CHANNEL_2.GTPE2.TX_EIDLE_ASSERT_DELAY[2] 28_204 -GTP_CHANNEL_2.GTPE2.TX_EIDLE_DEASSERT_DELAY[0] 29_204 -GTP_CHANNEL_2.GTPE2.TX_EIDLE_DEASSERT_DELAY[1] 28_205 -GTP_CHANNEL_2.GTPE2.TX_EIDLE_DEASSERT_DELAY[2] 29_205 -GTP_CHANNEL_2.GTPE2.TX_LOOPBACK_DRIVE_HIZ 29_202 -GTP_CHANNEL_2.GTPE2.TX_MAINCURSOR_SEL[0] 31_289 -GTP_CHANNEL_2.GTPE2.TX_MARGIN_FULL_0[0] 30_232 -GTP_CHANNEL_2.GTPE2.TX_MARGIN_FULL_0[1] 31_232 -GTP_CHANNEL_2.GTPE2.TX_MARGIN_FULL_0[2] 30_233 -GTP_CHANNEL_2.GTPE2.TX_MARGIN_FULL_0[3] 31_233 -GTP_CHANNEL_2.GTPE2.TX_MARGIN_FULL_0[4] 30_234 -GTP_CHANNEL_2.GTPE2.TX_MARGIN_FULL_0[5] 31_234 -GTP_CHANNEL_2.GTPE2.TX_MARGIN_FULL_0[6] 30_235 -GTP_CHANNEL_2.GTPE2.TX_MARGIN_FULL_1[0] 30_236 -GTP_CHANNEL_2.GTPE2.TX_MARGIN_FULL_1[1] 31_236 -GTP_CHANNEL_2.GTPE2.TX_MARGIN_FULL_1[2] 30_237 -GTP_CHANNEL_2.GTPE2.TX_MARGIN_FULL_1[3] 31_237 -GTP_CHANNEL_2.GTPE2.TX_MARGIN_FULL_1[4] 30_238 -GTP_CHANNEL_2.GTPE2.TX_MARGIN_FULL_1[5] 31_238 -GTP_CHANNEL_2.GTPE2.TX_MARGIN_FULL_1[6] 30_239 -GTP_CHANNEL_2.GTPE2.TX_MARGIN_FULL_2[0] 30_240 -GTP_CHANNEL_2.GTPE2.TX_MARGIN_FULL_2[1] 31_240 -GTP_CHANNEL_2.GTPE2.TX_MARGIN_FULL_2[2] 30_241 -GTP_CHANNEL_2.GTPE2.TX_MARGIN_FULL_2[3] 31_241 -GTP_CHANNEL_2.GTPE2.TX_MARGIN_FULL_2[4] 30_242 -GTP_CHANNEL_2.GTPE2.TX_MARGIN_FULL_2[5] 31_242 -GTP_CHANNEL_2.GTPE2.TX_MARGIN_FULL_2[6] 30_243 -GTP_CHANNEL_2.GTPE2.TX_MARGIN_FULL_3[0] 30_244 -GTP_CHANNEL_2.GTPE2.TX_MARGIN_FULL_3[1] 31_244 -GTP_CHANNEL_2.GTPE2.TX_MARGIN_FULL_3[2] 30_245 -GTP_CHANNEL_2.GTPE2.TX_MARGIN_FULL_3[3] 31_245 -GTP_CHANNEL_2.GTPE2.TX_MARGIN_FULL_3[4] 30_246 -GTP_CHANNEL_2.GTPE2.TX_MARGIN_FULL_3[5] 31_246 -GTP_CHANNEL_2.GTPE2.TX_MARGIN_FULL_3[6] 30_247 -GTP_CHANNEL_2.GTPE2.TX_MARGIN_FULL_4[0] 30_248 -GTP_CHANNEL_2.GTPE2.TX_MARGIN_FULL_4[1] 31_248 -GTP_CHANNEL_2.GTPE2.TX_MARGIN_FULL_4[2] 30_249 -GTP_CHANNEL_2.GTPE2.TX_MARGIN_FULL_4[3] 31_249 -GTP_CHANNEL_2.GTPE2.TX_MARGIN_FULL_4[4] 30_250 -GTP_CHANNEL_2.GTPE2.TX_MARGIN_FULL_4[5] 31_250 -GTP_CHANNEL_2.GTPE2.TX_MARGIN_FULL_4[6] 30_251 -GTP_CHANNEL_2.GTPE2.TX_MARGIN_LOW_0[0] 30_252 -GTP_CHANNEL_2.GTPE2.TX_MARGIN_LOW_0[1] 31_252 -GTP_CHANNEL_2.GTPE2.TX_MARGIN_LOW_0[2] 30_253 -GTP_CHANNEL_2.GTPE2.TX_MARGIN_LOW_0[3] 31_253 -GTP_CHANNEL_2.GTPE2.TX_MARGIN_LOW_0[4] 30_254 -GTP_CHANNEL_2.GTPE2.TX_MARGIN_LOW_0[5] 31_254 -GTP_CHANNEL_2.GTPE2.TX_MARGIN_LOW_0[6] 30_255 -GTP_CHANNEL_2.GTPE2.TX_MARGIN_LOW_1[0] 30_256 -GTP_CHANNEL_2.GTPE2.TX_MARGIN_LOW_1[1] 31_256 -GTP_CHANNEL_2.GTPE2.TX_MARGIN_LOW_1[2] 30_257 -GTP_CHANNEL_2.GTPE2.TX_MARGIN_LOW_1[3] 31_257 -GTP_CHANNEL_2.GTPE2.TX_MARGIN_LOW_1[4] 30_258 -GTP_CHANNEL_2.GTPE2.TX_MARGIN_LOW_1[5] 31_258 -GTP_CHANNEL_2.GTPE2.TX_MARGIN_LOW_1[6] 30_259 -GTP_CHANNEL_2.GTPE2.TX_MARGIN_LOW_2[0] 30_260 -GTP_CHANNEL_2.GTPE2.TX_MARGIN_LOW_2[1] 31_260 -GTP_CHANNEL_2.GTPE2.TX_MARGIN_LOW_2[2] 30_261 -GTP_CHANNEL_2.GTPE2.TX_MARGIN_LOW_2[3] 31_261 -GTP_CHANNEL_2.GTPE2.TX_MARGIN_LOW_2[4] 30_262 -GTP_CHANNEL_2.GTPE2.TX_MARGIN_LOW_2[5] 31_262 -GTP_CHANNEL_2.GTPE2.TX_MARGIN_LOW_2[6] 30_263 -GTP_CHANNEL_2.GTPE2.TX_MARGIN_LOW_3[0] 30_264 -GTP_CHANNEL_2.GTPE2.TX_MARGIN_LOW_3[1] 31_264 -GTP_CHANNEL_2.GTPE2.TX_MARGIN_LOW_3[2] 30_265 -GTP_CHANNEL_2.GTPE2.TX_MARGIN_LOW_3[3] 31_265 -GTP_CHANNEL_2.GTPE2.TX_MARGIN_LOW_3[4] 30_266 -GTP_CHANNEL_2.GTPE2.TX_MARGIN_LOW_3[5] 31_266 -GTP_CHANNEL_2.GTPE2.TX_MARGIN_LOW_3[6] 30_267 -GTP_CHANNEL_2.GTPE2.TX_MARGIN_LOW_4[0] 30_268 -GTP_CHANNEL_2.GTPE2.TX_MARGIN_LOW_4[1] 31_268 -GTP_CHANNEL_2.GTPE2.TX_MARGIN_LOW_4[2] 30_269 -GTP_CHANNEL_2.GTPE2.TX_MARGIN_LOW_4[3] 31_269 -GTP_CHANNEL_2.GTPE2.TX_MARGIN_LOW_4[4] 30_270 -GTP_CHANNEL_2.GTPE2.TX_MARGIN_LOW_4[5] 31_270 -GTP_CHANNEL_2.GTPE2.TX_MARGIN_LOW_4[6] 30_271 -GTP_CHANNEL_2.GTPE2.TX_PREDRIVER_MODE[0] 28_206 -GTP_CHANNEL_2.GTPE2.TX_RXDETECT_CFG[0] 30_296 -GTP_CHANNEL_2.GTPE2.TX_RXDETECT_CFG[1] 31_296 -GTP_CHANNEL_2.GTPE2.TX_RXDETECT_CFG[2] 30_297 -GTP_CHANNEL_2.GTPE2.TX_RXDETECT_CFG[3] 31_297 -GTP_CHANNEL_2.GTPE2.TX_RXDETECT_CFG[4] 30_298 -GTP_CHANNEL_2.GTPE2.TX_RXDETECT_CFG[5] 31_298 -GTP_CHANNEL_2.GTPE2.TX_RXDETECT_CFG[6] 30_299 -GTP_CHANNEL_2.GTPE2.TX_RXDETECT_CFG[7] 31_299 -GTP_CHANNEL_2.GTPE2.TX_RXDETECT_CFG[8] 30_300 -GTP_CHANNEL_2.GTPE2.TX_RXDETECT_CFG[9] 31_300 -GTP_CHANNEL_2.GTPE2.TX_RXDETECT_CFG[10] 30_301 -GTP_CHANNEL_2.GTPE2.TX_RXDETECT_CFG[11] 31_301 -GTP_CHANNEL_2.GTPE2.TX_RXDETECT_CFG[12] 30_302 -GTP_CHANNEL_2.GTPE2.TX_RXDETECT_CFG[13] 31_302 -GTP_CHANNEL_2.GTPE2.TX_RXDETECT_REF[0] 30_292 -GTP_CHANNEL_2.GTPE2.TX_RXDETECT_REF[1] 31_292 -GTP_CHANNEL_2.GTPE2.TX_RXDETECT_REF[2] 30_293 -GTP_CHANNEL_2.GTPE2.TX_XCLK_SEL.TXUSR 31_11 -GTP_CHANNEL_2.GTPE2.TX_CLK25_DIV[0] 30_144 -GTP_CHANNEL_2.GTPE2.TX_CLK25_DIV[1] 31_144 -GTP_CHANNEL_2.GTPE2.TX_CLK25_DIV[2] 30_145 -GTP_CHANNEL_2.GTPE2.TX_CLK25_DIV[3] 31_145 -GTP_CHANNEL_2.GTPE2.TX_CLK25_DIV[4] 30_146 -GTP_CHANNEL_2.GTPE2.TX_DEEMPH0[0] 30_272 -GTP_CHANNEL_2.GTPE2.TX_DEEMPH0[1] 31_272 -GTP_CHANNEL_2.GTPE2.TX_DEEMPH0[2] 30_273 -GTP_CHANNEL_2.GTPE2.TX_DEEMPH0[3] 31_273 -GTP_CHANNEL_2.GTPE2.TX_DEEMPH0[4] 30_274 -GTP_CHANNEL_2.GTPE2.TX_DEEMPH0[5] 31_274 -GTP_CHANNEL_2.GTPE2.TX_DEEMPH1[0] 30_276 -GTP_CHANNEL_2.GTPE2.TX_DEEMPH1[1] 31_276 -GTP_CHANNEL_2.GTPE2.TX_DEEMPH1[2] 30_277 -GTP_CHANNEL_2.GTPE2.TX_DEEMPH1[3] 31_277 -GTP_CHANNEL_2.GTPE2.TX_DEEMPH1[4] 30_278 -GTP_CHANNEL_2.GTPE2.TX_DEEMPH1[5] 31_278 -GTP_CHANNEL_2.GTPE2.TXBUF_EN 28_231 -GTP_CHANNEL_2.GTPE2.TXBUF_RESET_ON_RATE_CHANGE 29_231 -GTP_CHANNEL_2.GTPE2.TXDLY_CFG[0] 30_80 -GTP_CHANNEL_2.GTPE2.TXDLY_CFG[1] 31_80 -GTP_CHANNEL_2.GTPE2.TXDLY_CFG[2] 30_81 -GTP_CHANNEL_2.GTPE2.TXDLY_CFG[3] 31_81 -GTP_CHANNEL_2.GTPE2.TXDLY_CFG[4] 30_82 -GTP_CHANNEL_2.GTPE2.TXDLY_CFG[5] 31_82 -GTP_CHANNEL_2.GTPE2.TXDLY_CFG[6] 30_83 -GTP_CHANNEL_2.GTPE2.TXDLY_CFG[7] 31_83 -GTP_CHANNEL_2.GTPE2.TXDLY_CFG[8] 30_84 -GTP_CHANNEL_2.GTPE2.TXDLY_CFG[9] 31_84 -GTP_CHANNEL_2.GTPE2.TXDLY_CFG[10] 30_85 -GTP_CHANNEL_2.GTPE2.TXDLY_CFG[11] 31_85 -GTP_CHANNEL_2.GTPE2.TXDLY_CFG[12] 30_86 -GTP_CHANNEL_2.GTPE2.TXDLY_CFG[13] 31_86 -GTP_CHANNEL_2.GTPE2.TXDLY_CFG[14] 30_87 -GTP_CHANNEL_2.GTPE2.TXDLY_CFG[15] 31_87 -GTP_CHANNEL_2.GTPE2.TXDLY_LCFG[0] 30_568 -GTP_CHANNEL_2.GTPE2.TXDLY_LCFG[1] 31_568 -GTP_CHANNEL_2.GTPE2.TXDLY_LCFG[2] 30_569 -GTP_CHANNEL_2.GTPE2.TXDLY_LCFG[3] 31_569 -GTP_CHANNEL_2.GTPE2.TXDLY_LCFG[4] 30_570 -GTP_CHANNEL_2.GTPE2.TXDLY_LCFG[5] 31_570 -GTP_CHANNEL_2.GTPE2.TXDLY_LCFG[6] 30_571 -GTP_CHANNEL_2.GTPE2.TXDLY_LCFG[7] 31_571 -GTP_CHANNEL_2.GTPE2.TXDLY_LCFG[8] 30_572 -GTP_CHANNEL_2.GTPE2.TXDLY_TAP_CFG[0] 30_88 -GTP_CHANNEL_2.GTPE2.TXDLY_TAP_CFG[1] 31_88 -GTP_CHANNEL_2.GTPE2.TXDLY_TAP_CFG[2] 30_89 -GTP_CHANNEL_2.GTPE2.TXDLY_TAP_CFG[3] 31_89 -GTP_CHANNEL_2.GTPE2.TXDLY_TAP_CFG[4] 30_90 -GTP_CHANNEL_2.GTPE2.TXDLY_TAP_CFG[5] 31_90 -GTP_CHANNEL_2.GTPE2.TXDLY_TAP_CFG[6] 30_91 -GTP_CHANNEL_2.GTPE2.TXDLY_TAP_CFG[7] 31_91 -GTP_CHANNEL_2.GTPE2.TXDLY_TAP_CFG[8] 30_92 -GTP_CHANNEL_2.GTPE2.TXDLY_TAP_CFG[9] 31_92 -GTP_CHANNEL_2.GTPE2.TXDLY_TAP_CFG[10] 30_93 -GTP_CHANNEL_2.GTPE2.TXDLY_TAP_CFG[11] 31_93 -GTP_CHANNEL_2.GTPE2.TXDLY_TAP_CFG[12] 30_94 -GTP_CHANNEL_2.GTPE2.TXDLY_TAP_CFG[13] 31_94 -GTP_CHANNEL_2.GTPE2.TXDLY_TAP_CFG[14] 30_95 -GTP_CHANNEL_2.GTPE2.TXDLY_TAP_CFG[15] 31_95 -GTP_CHANNEL_2.GTPE2.TXGEARBOX_EN 29_226 -GTP_CHANNEL_2.GTPE2.TXOOB_CFG[0] 31_20 -GTP_CHANNEL_2.GTPE2.TXOUT_DIV[0] 30_386 -GTP_CHANNEL_2.GTPE2.TXOUT_DIV[1] 31_386 -GTP_CHANNEL_2.GTPE2.TXPCSRESET_TIME[0] 29_130 -GTP_CHANNEL_2.GTPE2.TXPCSRESET_TIME[1] 28_131 -GTP_CHANNEL_2.GTPE2.TXPCSRESET_TIME[2] 29_131 -GTP_CHANNEL_2.GTPE2.TXPCSRESET_TIME[3] 28_132 -GTP_CHANNEL_2.GTPE2.TXPCSRESET_TIME[4] 29_132 -GTP_CHANNEL_2.GTPE2.TXPH_CFG[0] 30_96 -GTP_CHANNEL_2.GTPE2.TXPH_CFG[1] 31_96 -GTP_CHANNEL_2.GTPE2.TXPH_CFG[2] 30_97 -GTP_CHANNEL_2.GTPE2.TXPH_CFG[3] 31_97 -GTP_CHANNEL_2.GTPE2.TXPH_CFG[4] 30_98 -GTP_CHANNEL_2.GTPE2.TXPH_CFG[5] 31_98 -GTP_CHANNEL_2.GTPE2.TXPH_CFG[6] 30_99 -GTP_CHANNEL_2.GTPE2.TXPH_CFG[7] 31_99 -GTP_CHANNEL_2.GTPE2.TXPH_CFG[8] 30_100 -GTP_CHANNEL_2.GTPE2.TXPH_CFG[9] 31_100 -GTP_CHANNEL_2.GTPE2.TXPH_CFG[10] 30_101 -GTP_CHANNEL_2.GTPE2.TXPH_CFG[11] 31_101 -GTP_CHANNEL_2.GTPE2.TXPH_CFG[12] 30_102 -GTP_CHANNEL_2.GTPE2.TXPH_CFG[13] 31_102 -GTP_CHANNEL_2.GTPE2.TXPH_CFG[14] 30_103 -GTP_CHANNEL_2.GTPE2.TXPH_CFG[15] 31_103 -GTP_CHANNEL_2.GTPE2.TXPH_MONITOR_SEL[0] 30_108 -GTP_CHANNEL_2.GTPE2.TXPH_MONITOR_SEL[1] 31_108 -GTP_CHANNEL_2.GTPE2.TXPH_MONITOR_SEL[2] 30_109 -GTP_CHANNEL_2.GTPE2.TXPH_MONITOR_SEL[3] 31_109 -GTP_CHANNEL_2.GTPE2.TXPH_MONITOR_SEL[4] 30_110 -GTP_CHANNEL_2.GTPE2.TXPHDLY_CFG[0] 30_64 -GTP_CHANNEL_2.GTPE2.TXPHDLY_CFG[1] 31_64 -GTP_CHANNEL_2.GTPE2.TXPHDLY_CFG[2] 30_65 -GTP_CHANNEL_2.GTPE2.TXPHDLY_CFG[3] 31_65 -GTP_CHANNEL_2.GTPE2.TXPHDLY_CFG[4] 30_66 -GTP_CHANNEL_2.GTPE2.TXPHDLY_CFG[5] 31_66 -GTP_CHANNEL_2.GTPE2.TXPHDLY_CFG[6] 30_67 -GTP_CHANNEL_2.GTPE2.TXPHDLY_CFG[7] 31_67 -GTP_CHANNEL_2.GTPE2.TXPHDLY_CFG[8] 30_68 -GTP_CHANNEL_2.GTPE2.TXPHDLY_CFG[9] 31_68 -GTP_CHANNEL_2.GTPE2.TXPHDLY_CFG[10] 30_69 -GTP_CHANNEL_2.GTPE2.TXPHDLY_CFG[11] 31_69 -GTP_CHANNEL_2.GTPE2.TXPHDLY_CFG[12] 30_70 -GTP_CHANNEL_2.GTPE2.TXPHDLY_CFG[13] 31_70 -GTP_CHANNEL_2.GTPE2.TXPHDLY_CFG[14] 30_71 -GTP_CHANNEL_2.GTPE2.TXPHDLY_CFG[15] 31_71 -GTP_CHANNEL_2.GTPE2.TXPHDLY_CFG[16] 30_72 -GTP_CHANNEL_2.GTPE2.TXPHDLY_CFG[17] 31_72 -GTP_CHANNEL_2.GTPE2.TXPHDLY_CFG[18] 30_73 -GTP_CHANNEL_2.GTPE2.TXPHDLY_CFG[19] 31_73 -GTP_CHANNEL_2.GTPE2.TXPHDLY_CFG[20] 30_74 -GTP_CHANNEL_2.GTPE2.TXPHDLY_CFG[21] 31_74 -GTP_CHANNEL_2.GTPE2.TXPHDLY_CFG[22] 30_75 -GTP_CHANNEL_2.GTPE2.TXPHDLY_CFG[23] 31_75 -GTP_CHANNEL_2.GTPE2.TXPI_GREY_SEL[0] 31_498 -GTP_CHANNEL_2.GTPE2.TXPI_INVSTROBE_SEL[0] 30_498 -GTP_CHANNEL_2.GTPE2.TXPI_PPM_CFG[0] 30_488 -GTP_CHANNEL_2.GTPE2.TXPI_PPM_CFG[1] 31_488 -GTP_CHANNEL_2.GTPE2.TXPI_PPM_CFG[2] 30_489 -GTP_CHANNEL_2.GTPE2.TXPI_PPM_CFG[3] 31_489 -GTP_CHANNEL_2.GTPE2.TXPI_PPM_CFG[4] 30_490 -GTP_CHANNEL_2.GTPE2.TXPI_PPM_CFG[5] 31_490 -GTP_CHANNEL_2.GTPE2.TXPI_PPM_CFG[6] 30_491 -GTP_CHANNEL_2.GTPE2.TXPI_PPM_CFG[7] 31_491 -GTP_CHANNEL_2.GTPE2.TXPI_PPMCLK_SEL.TXUSRCLK2 31_497 -GTP_CHANNEL_2.GTPE2.TXPI_SYNFREQ_PPM[0] 30_496 -GTP_CHANNEL_2.GTPE2.TXPI_SYNFREQ_PPM[1] 31_496 -GTP_CHANNEL_2.GTPE2.TXPI_SYNFREQ_PPM[2] 30_497 -GTP_CHANNEL_2.GTPE2.TXPI_CFG0[0] 30_40 -GTP_CHANNEL_2.GTPE2.TXPI_CFG0[1] 31_40 -GTP_CHANNEL_2.GTPE2.TXPI_CFG1[0] 30_41 -GTP_CHANNEL_2.GTPE2.TXPI_CFG1[1] 31_41 -GTP_CHANNEL_2.GTPE2.TXPI_CFG2[0] 30_42 -GTP_CHANNEL_2.GTPE2.TXPI_CFG2[1] 31_42 -GTP_CHANNEL_2.GTPE2.TXPI_CFG3[0] 30_43 -GTP_CHANNEL_2.GTPE2.TXPI_CFG4[0] 31_43 -GTP_CHANNEL_2.GTPE2.TXPI_CFG5[0] 30_44 -GTP_CHANNEL_2.GTPE2.TXPI_CFG5[1] 31_44 -GTP_CHANNEL_2.GTPE2.TXPI_CFG5[2] 30_45 -GTP_CHANNEL_2.GTPE2.TXPMARESET_TIME[0] 28_128 -GTP_CHANNEL_2.GTPE2.TXPMARESET_TIME[1] 29_128 -GTP_CHANNEL_2.GTPE2.TXPMARESET_TIME[2] 28_129 -GTP_CHANNEL_2.GTPE2.TXPMARESET_TIME[3] 29_129 -GTP_CHANNEL_2.GTPE2.TXPMARESET_TIME[4] 28_130 -GTP_CHANNEL_2.GTPE2.TXSYNC_MULTILANE[0] 29_133 -GTP_CHANNEL_2.GTPE2.TXSYNC_OVRD[0] 28_135 -GTP_CHANNEL_2.GTPE2.TXSYNC_SKIP_DA[0] 28_134 -GTP_CHANNEL_2.GTPE2.UCODEER_CLR[0] 29_00 -GTP_CHANNEL_2.GTPE2.USE_PCS_CLK_PHASE_SEL[0] 30_463 -GTP_CHANNEL_2.GTPE2.ZINV_DMONITORCLK 30_13 -GTP_CHANNEL_2.GTPE2.ZINV_DRPCLK 30_00 -GTP_CHANNEL_2.GTPE2.ZINV_RXUSRCLK 31_01 -GTP_CHANNEL_2.GTPE2.ZINV_SIGVALIDCLK 31_13 -GTP_CHANNEL_2.GTPE2.ZINV_TXPHDLYTSTCLK 30_03 -GTP_CHANNEL_2.GTPE2.ZINV_TXUSRCLK 31_04 -GTP_CHANNEL_2.GTPE2.ZINV_CLKRSVD0 30_23 -GTP_CHANNEL_2.GTPE2.ZINV_CLKRSVD1 31_23 -GTP_CHANNEL_2.GTPE2.ZINV_RXUSRCLK2 30_02 -GTP_CHANNEL_2.GTPE2.ZINV_TXUSRCLK2 30_05 +GTP_CHANNEL_2.GTPE2_CHANNEL.ACJTAG_DEBUG_MODE[0] 28_07 +GTP_CHANNEL_2.GTPE2_CHANNEL.ACJTAG_MODE[0] 29_06 +GTP_CHANNEL_2.GTPE2_CHANNEL.ACJTAG_RESET[0] 29_07 +GTP_CHANNEL_2.GTPE2_CHANNEL.ADAPT_CFG0[0] 30_464 +GTP_CHANNEL_2.GTPE2_CHANNEL.ADAPT_CFG0[1] 31_464 +GTP_CHANNEL_2.GTPE2_CHANNEL.ADAPT_CFG0[2] 30_465 +GTP_CHANNEL_2.GTPE2_CHANNEL.ADAPT_CFG0[3] 31_465 +GTP_CHANNEL_2.GTPE2_CHANNEL.ADAPT_CFG0[4] 30_466 +GTP_CHANNEL_2.GTPE2_CHANNEL.ADAPT_CFG0[5] 31_466 +GTP_CHANNEL_2.GTPE2_CHANNEL.ADAPT_CFG0[6] 30_467 +GTP_CHANNEL_2.GTPE2_CHANNEL.ADAPT_CFG0[7] 31_467 +GTP_CHANNEL_2.GTPE2_CHANNEL.ADAPT_CFG0[8] 30_468 +GTP_CHANNEL_2.GTPE2_CHANNEL.ADAPT_CFG0[9] 31_468 +GTP_CHANNEL_2.GTPE2_CHANNEL.ADAPT_CFG0[10] 30_469 +GTP_CHANNEL_2.GTPE2_CHANNEL.ADAPT_CFG0[11] 31_469 +GTP_CHANNEL_2.GTPE2_CHANNEL.ADAPT_CFG0[12] 30_470 +GTP_CHANNEL_2.GTPE2_CHANNEL.ADAPT_CFG0[13] 31_470 +GTP_CHANNEL_2.GTPE2_CHANNEL.ADAPT_CFG0[14] 30_471 +GTP_CHANNEL_2.GTPE2_CHANNEL.ADAPT_CFG0[15] 31_471 +GTP_CHANNEL_2.GTPE2_CHANNEL.ADAPT_CFG0[16] 30_472 +GTP_CHANNEL_2.GTPE2_CHANNEL.ADAPT_CFG0[17] 31_472 +GTP_CHANNEL_2.GTPE2_CHANNEL.ADAPT_CFG0[18] 30_473 +GTP_CHANNEL_2.GTPE2_CHANNEL.ADAPT_CFG0[19] 31_473 +GTP_CHANNEL_2.GTPE2_CHANNEL.ALIGN_COMMA_DOUBLE 28_522 +GTP_CHANNEL_2.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[0] 28_496 +GTP_CHANNEL_2.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[1] 29_496 +GTP_CHANNEL_2.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[2] 28_497 +GTP_CHANNEL_2.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[3] 29_497 +GTP_CHANNEL_2.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[4] 28_498 +GTP_CHANNEL_2.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[5] 29_498 +GTP_CHANNEL_2.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[6] 28_499 +GTP_CHANNEL_2.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[7] 29_499 +GTP_CHANNEL_2.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[8] 28_500 +GTP_CHANNEL_2.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[9] 29_500 +GTP_CHANNEL_2.GTPE2_CHANNEL.ALIGN_COMMA_WORD[0] 29_526 +GTP_CHANNEL_2.GTPE2_CHANNEL.ALIGN_COMMA_WORD[1] 28_527 +GTP_CHANNEL_2.GTPE2_CHANNEL.ALIGN_MCOMMA_DET 28_523 +GTP_CHANNEL_2.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[0] 28_504 +GTP_CHANNEL_2.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[1] 29_504 +GTP_CHANNEL_2.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[2] 28_505 +GTP_CHANNEL_2.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[3] 29_505 +GTP_CHANNEL_2.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[4] 28_506 +GTP_CHANNEL_2.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[5] 29_506 +GTP_CHANNEL_2.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[6] 28_507 +GTP_CHANNEL_2.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[7] 29_507 +GTP_CHANNEL_2.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[8] 28_508 +GTP_CHANNEL_2.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[9] 29_508 +GTP_CHANNEL_2.GTPE2_CHANNEL.ALIGN_PCOMMA_DET 29_523 +GTP_CHANNEL_2.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[0] 28_512 +GTP_CHANNEL_2.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[1] 29_512 +GTP_CHANNEL_2.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[2] 28_513 +GTP_CHANNEL_2.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[3] 29_513 +GTP_CHANNEL_2.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[4] 28_514 +GTP_CHANNEL_2.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[5] 29_514 +GTP_CHANNEL_2.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[6] 28_515 +GTP_CHANNEL_2.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[7] 29_515 +GTP_CHANNEL_2.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[8] 28_516 +GTP_CHANNEL_2.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[9] 29_516 +GTP_CHANNEL_2.GTPE2_CHANNEL.CBCC_DATA_SOURCE_SEL.DECODED 29_661 +GTP_CHANNEL_2.GTPE2_CHANNEL.CFOK_CFG[0] 30_392 +GTP_CHANNEL_2.GTPE2_CHANNEL.CFOK_CFG[1] 31_392 +GTP_CHANNEL_2.GTPE2_CHANNEL.CFOK_CFG[2] 30_393 +GTP_CHANNEL_2.GTPE2_CHANNEL.CFOK_CFG[3] 31_393 +GTP_CHANNEL_2.GTPE2_CHANNEL.CFOK_CFG[4] 30_394 +GTP_CHANNEL_2.GTPE2_CHANNEL.CFOK_CFG[5] 31_394 +GTP_CHANNEL_2.GTPE2_CHANNEL.CFOK_CFG[6] 30_395 +GTP_CHANNEL_2.GTPE2_CHANNEL.CFOK_CFG[7] 31_395 +GTP_CHANNEL_2.GTPE2_CHANNEL.CFOK_CFG[8] 30_396 +GTP_CHANNEL_2.GTPE2_CHANNEL.CFOK_CFG[9] 31_396 +GTP_CHANNEL_2.GTPE2_CHANNEL.CFOK_CFG[10] 30_397 +GTP_CHANNEL_2.GTPE2_CHANNEL.CFOK_CFG[11] 31_397 +GTP_CHANNEL_2.GTPE2_CHANNEL.CFOK_CFG[12] 30_398 +GTP_CHANNEL_2.GTPE2_CHANNEL.CFOK_CFG[13] 31_398 +GTP_CHANNEL_2.GTPE2_CHANNEL.CFOK_CFG[14] 30_399 +GTP_CHANNEL_2.GTPE2_CHANNEL.CFOK_CFG[15] 31_399 +GTP_CHANNEL_2.GTPE2_CHANNEL.CFOK_CFG[16] 30_400 +GTP_CHANNEL_2.GTPE2_CHANNEL.CFOK_CFG[17] 31_400 +GTP_CHANNEL_2.GTPE2_CHANNEL.CFOK_CFG[18] 30_401 +GTP_CHANNEL_2.GTPE2_CHANNEL.CFOK_CFG[19] 31_401 +GTP_CHANNEL_2.GTPE2_CHANNEL.CFOK_CFG[20] 30_402 +GTP_CHANNEL_2.GTPE2_CHANNEL.CFOK_CFG[21] 31_402 +GTP_CHANNEL_2.GTPE2_CHANNEL.CFOK_CFG[22] 30_403 +GTP_CHANNEL_2.GTPE2_CHANNEL.CFOK_CFG[23] 31_403 +GTP_CHANNEL_2.GTPE2_CHANNEL.CFOK_CFG[24] 30_404 +GTP_CHANNEL_2.GTPE2_CHANNEL.CFOK_CFG[25] 31_404 +GTP_CHANNEL_2.GTPE2_CHANNEL.CFOK_CFG[26] 30_405 +GTP_CHANNEL_2.GTPE2_CHANNEL.CFOK_CFG[27] 31_405 +GTP_CHANNEL_2.GTPE2_CHANNEL.CFOK_CFG[28] 30_406 +GTP_CHANNEL_2.GTPE2_CHANNEL.CFOK_CFG[29] 31_406 +GTP_CHANNEL_2.GTPE2_CHANNEL.CFOK_CFG[30] 30_407 +GTP_CHANNEL_2.GTPE2_CHANNEL.CFOK_CFG[31] 31_407 +GTP_CHANNEL_2.GTPE2_CHANNEL.CFOK_CFG[32] 30_408 +GTP_CHANNEL_2.GTPE2_CHANNEL.CFOK_CFG[33] 31_408 +GTP_CHANNEL_2.GTPE2_CHANNEL.CFOK_CFG[34] 30_409 +GTP_CHANNEL_2.GTPE2_CHANNEL.CFOK_CFG[35] 31_409 +GTP_CHANNEL_2.GTPE2_CHANNEL.CFOK_CFG[36] 30_410 +GTP_CHANNEL_2.GTPE2_CHANNEL.CFOK_CFG[37] 31_410 +GTP_CHANNEL_2.GTPE2_CHANNEL.CFOK_CFG[38] 30_411 +GTP_CHANNEL_2.GTPE2_CHANNEL.CFOK_CFG[39] 31_411 +GTP_CHANNEL_2.GTPE2_CHANNEL.CFOK_CFG[40] 30_412 +GTP_CHANNEL_2.GTPE2_CHANNEL.CFOK_CFG[41] 31_412 +GTP_CHANNEL_2.GTPE2_CHANNEL.CFOK_CFG[42] 30_413 +GTP_CHANNEL_2.GTPE2_CHANNEL.CFOK_CFG2[0] 30_459 +GTP_CHANNEL_2.GTPE2_CHANNEL.CFOK_CFG2[1] 31_459 +GTP_CHANNEL_2.GTPE2_CHANNEL.CFOK_CFG2[2] 30_460 +GTP_CHANNEL_2.GTPE2_CHANNEL.CFOK_CFG2[3] 31_460 +GTP_CHANNEL_2.GTPE2_CHANNEL.CFOK_CFG2[4] 30_461 +GTP_CHANNEL_2.GTPE2_CHANNEL.CFOK_CFG2[5] 31_461 +GTP_CHANNEL_2.GTPE2_CHANNEL.CFOK_CFG2[6] 30_462 +GTP_CHANNEL_2.GTPE2_CHANNEL.CFOK_CFG3[0] 30_416 +GTP_CHANNEL_2.GTPE2_CHANNEL.CFOK_CFG3[1] 31_416 +GTP_CHANNEL_2.GTPE2_CHANNEL.CFOK_CFG3[2] 30_417 +GTP_CHANNEL_2.GTPE2_CHANNEL.CFOK_CFG3[3] 31_417 +GTP_CHANNEL_2.GTPE2_CHANNEL.CFOK_CFG3[4] 30_418 +GTP_CHANNEL_2.GTPE2_CHANNEL.CFOK_CFG3[5] 31_418 +GTP_CHANNEL_2.GTPE2_CHANNEL.CFOK_CFG3[6] 30_419 +GTP_CHANNEL_2.GTPE2_CHANNEL.CFOK_CFG4[0] 31_438 +GTP_CHANNEL_2.GTPE2_CHANNEL.CFOK_CFG5[0] 30_429 +GTP_CHANNEL_2.GTPE2_CHANNEL.CFOK_CFG5[1] 31_429 +GTP_CHANNEL_2.GTPE2_CHANNEL.CFOK_CFG6[0] 31_436 +GTP_CHANNEL_2.GTPE2_CHANNEL.CFOK_CFG6[1] 30_437 +GTP_CHANNEL_2.GTPE2_CHANNEL.CFOK_CFG6[2] 31_437 +GTP_CHANNEL_2.GTPE2_CHANNEL.CFOK_CFG6[3] 30_438 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_KEEP_ALIGN 29_631 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_MAX_SKEW[0] 28_670 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_MAX_SKEW[1] 29_670 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_MAX_SKEW[2] 28_671 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_MAX_SKEW[3] 29_671 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[0] 28_608 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[1] 29_608 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[2] 28_609 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[3] 29_609 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[4] 28_610 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[5] 29_610 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[6] 28_611 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[7] 29_611 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[8] 28_612 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[9] 29_612 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[0] 28_616 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[1] 29_616 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[2] 28_617 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[3] 29_617 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[4] 28_618 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[5] 29_618 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[6] 28_619 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[7] 29_619 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[8] 28_620 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[9] 29_620 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[0] 28_624 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[1] 29_624 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[2] 28_625 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[3] 29_625 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[4] 28_626 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[5] 29_626 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[6] 28_627 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[7] 29_627 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[8] 28_628 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[9] 29_628 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[0] 28_632 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[1] 29_632 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[2] 28_633 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[3] 29_633 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[4] 28_634 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[5] 29_634 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[6] 28_635 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[7] 29_635 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[8] 28_636 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[9] 29_636 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_ENABLE[0] 28_614 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_ENABLE[1] 29_614 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_ENABLE[2] 28_615 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_ENABLE[3] 29_615 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[0] 28_640 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[1] 29_640 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[2] 28_641 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[3] 29_641 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[4] 28_642 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[5] 29_642 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[6] 28_643 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[7] 29_643 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[8] 28_644 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[9] 29_644 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[0] 28_648 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[1] 29_648 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[2] 28_649 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[3] 29_649 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[4] 28_650 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[5] 29_650 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[6] 28_651 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[7] 29_651 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[8] 28_652 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[9] 29_652 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[0] 28_656 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[1] 29_656 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[2] 28_657 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[3] 29_657 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[4] 28_658 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[5] 29_658 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[6] 28_659 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[7] 29_659 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[8] 28_660 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[9] 29_660 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[0] 28_664 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[1] 29_664 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[2] 28_665 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[3] 29_665 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[4] 28_666 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[5] 29_666 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[6] 28_667 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[7] 29_667 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[8] 28_668 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[9] 29_668 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_ENABLE[0] 28_646 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_ENABLE[1] 29_646 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_ENABLE[2] 28_647 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_ENABLE[3] 29_647 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_USE 29_645 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_LEN[0] 28_623 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_LEN[1] 29_623 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COMMON_SWING[0] 31_311 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_KEEP_IDLE 28_591 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_MAX_LAT[0] 28_557 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_MAX_LAT[1] 29_557 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_MAX_LAT[2] 28_558 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_MAX_LAT[3] 29_558 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_MAX_LAT[4] 28_559 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_MAX_LAT[5] 29_559 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_MIN_LAT[0] 28_565 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_MIN_LAT[1] 29_565 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_MIN_LAT[2] 28_566 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_MIN_LAT[3] 29_566 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_MIN_LAT[4] 28_567 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_MIN_LAT[5] 29_567 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_PRECEDENCE 28_590 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_REPEAT_WAIT[0] 28_573 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_REPEAT_WAIT[1] 29_573 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_REPEAT_WAIT[2] 28_574 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_REPEAT_WAIT[3] 29_574 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_REPEAT_WAIT[4] 28_575 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[0] 28_544 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[1] 29_544 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[2] 28_545 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[3] 29_545 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[4] 28_546 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[5] 29_546 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[6] 28_547 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[7] 29_547 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[8] 28_548 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[9] 29_548 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[0] 28_552 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[1] 29_552 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[2] 28_553 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[3] 29_553 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[4] 28_554 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[5] 29_554 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[6] 28_555 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[7] 29_555 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[8] 28_556 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[9] 29_556 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[0] 28_560 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[1] 29_560 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[2] 28_561 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[3] 29_561 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[4] 28_562 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[5] 29_562 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[6] 28_563 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[7] 29_563 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[8] 28_564 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[9] 29_564 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[0] 28_568 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[1] 29_568 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[2] 28_569 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[3] 29_569 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[4] 28_570 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[5] 29_570 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[6] 28_571 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[7] 29_571 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[8] 28_572 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[9] 29_572 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_1_ENABLE[0] 28_549 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_1_ENABLE[1] 29_549 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_1_ENABLE[2] 28_550 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_1_ENABLE[3] 29_550 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[0] 28_576 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[1] 29_576 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[2] 28_577 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[3] 29_577 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[4] 28_578 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[5] 29_578 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[6] 28_579 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[7] 29_579 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[8] 28_580 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[9] 29_580 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[0] 28_584 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[1] 29_584 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[2] 28_585 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[3] 29_585 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[4] 28_586 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[5] 29_586 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[6] 28_587 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[7] 29_587 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[8] 28_588 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[9] 29_588 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[0] 28_592 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[1] 29_592 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[2] 28_593 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[3] 29_593 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[4] 28_594 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[5] 29_594 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[6] 28_595 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[7] 29_595 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[8] 28_596 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[9] 29_596 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[0] 28_600 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[1] 29_600 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[2] 28_601 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[3] 29_601 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[4] 28_602 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[5] 29_602 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[6] 28_603 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[7] 29_603 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[8] 28_604 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[9] 29_604 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_2_ENABLE[0] 28_581 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_2_ENABLE[1] 29_581 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_2_ENABLE[2] 28_582 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_2_ENABLE[3] 29_582 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_2_USE 28_583 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_LEN[0] 28_589 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_LEN[1] 29_589 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_CORRECT_USE 28_551 +GTP_CHANNEL_2.GTPE2_CHANNEL.DEC_MCOMMA_DETECT 29_494 +GTP_CHANNEL_2.GTPE2_CHANNEL.DEC_PCOMMA_DETECT 28_495 +GTP_CHANNEL_2.GTPE2_CHANNEL.DEC_VALID_COMMA_ONLY 28_494 +GTP_CHANNEL_2.GTPE2_CHANNEL.DMONITOR_CFG[0] 30_368 +GTP_CHANNEL_2.GTPE2_CHANNEL.DMONITOR_CFG[1] 31_368 +GTP_CHANNEL_2.GTPE2_CHANNEL.DMONITOR_CFG[2] 30_369 +GTP_CHANNEL_2.GTPE2_CHANNEL.DMONITOR_CFG[3] 31_369 +GTP_CHANNEL_2.GTPE2_CHANNEL.DMONITOR_CFG[4] 30_370 +GTP_CHANNEL_2.GTPE2_CHANNEL.DMONITOR_CFG[5] 31_370 +GTP_CHANNEL_2.GTPE2_CHANNEL.DMONITOR_CFG[6] 30_371 +GTP_CHANNEL_2.GTPE2_CHANNEL.DMONITOR_CFG[7] 31_371 +GTP_CHANNEL_2.GTPE2_CHANNEL.DMONITOR_CFG[8] 30_372 +GTP_CHANNEL_2.GTPE2_CHANNEL.DMONITOR_CFG[9] 31_372 +GTP_CHANNEL_2.GTPE2_CHANNEL.DMONITOR_CFG[10] 30_373 +GTP_CHANNEL_2.GTPE2_CHANNEL.DMONITOR_CFG[11] 31_373 +GTP_CHANNEL_2.GTPE2_CHANNEL.DMONITOR_CFG[12] 30_374 +GTP_CHANNEL_2.GTPE2_CHANNEL.DMONITOR_CFG[13] 31_374 +GTP_CHANNEL_2.GTPE2_CHANNEL.DMONITOR_CFG[14] 30_375 +GTP_CHANNEL_2.GTPE2_CHANNEL.DMONITOR_CFG[15] 31_375 +GTP_CHANNEL_2.GTPE2_CHANNEL.DMONITOR_CFG[16] 30_376 +GTP_CHANNEL_2.GTPE2_CHANNEL.DMONITOR_CFG[17] 31_376 +GTP_CHANNEL_2.GTPE2_CHANNEL.DMONITOR_CFG[18] 30_377 +GTP_CHANNEL_2.GTPE2_CHANNEL.DMONITOR_CFG[19] 31_377 +GTP_CHANNEL_2.GTPE2_CHANNEL.DMONITOR_CFG[20] 30_378 +GTP_CHANNEL_2.GTPE2_CHANNEL.DMONITOR_CFG[21] 31_378 +GTP_CHANNEL_2.GTPE2_CHANNEL.DMONITOR_CFG[22] 30_379 +GTP_CHANNEL_2.GTPE2_CHANNEL.DMONITOR_CFG[23] 31_379 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_CLK_PHASE_SEL[0] 31_463 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_CONTROL[0] 28_488 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_CONTROL[1] 29_488 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_CONTROL[2] 28_489 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_CONTROL[3] 29_489 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_CONTROL[4] 28_490 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_CONTROL[5] 29_490 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_ERRDET_EN 29_492 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_EYE_SCAN_EN 28_492 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_HORZ_OFFSET[0] 28_480 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_HORZ_OFFSET[1] 29_480 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_HORZ_OFFSET[2] 28_481 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_HORZ_OFFSET[3] 29_481 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_HORZ_OFFSET[4] 28_482 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_HORZ_OFFSET[5] 29_482 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_HORZ_OFFSET[6] 28_483 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_HORZ_OFFSET[7] 29_483 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_HORZ_OFFSET[8] 28_484 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_HORZ_OFFSET[9] 29_484 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_HORZ_OFFSET[10] 28_485 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_HORZ_OFFSET[11] 29_485 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_PMA_CFG[0] 30_624 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_PMA_CFG[1] 31_624 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_PMA_CFG[2] 30_625 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_PMA_CFG[3] 31_625 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_PMA_CFG[4] 30_626 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_PMA_CFG[5] 31_626 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_PMA_CFG[6] 30_627 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_PMA_CFG[7] 31_627 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_PMA_CFG[8] 30_628 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_PMA_CFG[9] 31_628 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_PRESCALE[0] 29_477 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_PRESCALE[1] 28_478 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_PRESCALE[2] 29_478 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_PRESCALE[3] 28_479 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_PRESCALE[4] 29_479 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[0] 28_392 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[1] 29_392 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[2] 28_393 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[3] 29_393 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[4] 28_394 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[5] 29_394 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[6] 28_395 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[7] 29_395 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[8] 28_396 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[9] 29_396 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[10] 28_397 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[11] 29_397 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[12] 28_398 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[13] 29_398 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[14] 28_399 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[15] 29_399 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[16] 28_400 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[17] 29_400 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[18] 28_401 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[19] 29_401 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[20] 28_402 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[21] 29_402 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[22] 28_403 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[23] 29_403 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[24] 28_404 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[25] 29_404 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[26] 28_405 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[27] 29_405 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[28] 28_406 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[29] 29_406 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[30] 28_407 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[31] 29_407 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[32] 28_408 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[33] 29_408 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[34] 28_409 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[35] 29_409 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[36] 28_410 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[37] 29_410 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[38] 28_411 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[39] 29_411 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[40] 28_412 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[41] 29_412 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[42] 28_413 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[43] 29_413 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[44] 28_414 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[45] 29_414 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[46] 28_415 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[47] 29_415 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[48] 28_416 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[49] 29_416 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[50] 28_417 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[51] 29_417 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[52] 28_418 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[53] 29_418 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[54] 28_419 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[55] 29_419 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[56] 28_420 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[57] 29_420 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[58] 28_421 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[59] 29_421 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[60] 28_422 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[61] 29_422 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[62] 28_423 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[63] 29_423 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[64] 28_424 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[65] 29_424 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[66] 28_425 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[67] 29_425 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[68] 28_426 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[69] 29_426 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[70] 28_427 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[71] 29_427 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[72] 28_428 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[73] 29_428 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[74] 28_429 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[75] 29_429 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[76] 28_430 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[77] 29_430 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[78] 28_431 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[79] 29_431 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[0] 28_352 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[1] 29_352 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[2] 28_353 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[3] 29_353 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[4] 28_354 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[5] 29_354 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[6] 28_355 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[7] 29_355 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[8] 28_356 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[9] 29_356 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[10] 28_357 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[11] 29_357 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[12] 28_358 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[13] 29_358 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[14] 28_359 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[15] 29_359 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[16] 28_360 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[17] 29_360 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[18] 28_361 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[19] 29_361 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[20] 28_362 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[21] 29_362 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[22] 28_363 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[23] 29_363 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[24] 28_364 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[25] 29_364 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[26] 28_365 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[27] 29_365 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[28] 28_366 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[29] 29_366 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[30] 28_367 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[31] 29_367 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[32] 28_368 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[33] 29_368 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[34] 28_369 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[35] 29_369 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[36] 28_370 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[37] 29_370 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[38] 28_371 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[39] 29_371 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[40] 28_372 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[41] 29_372 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[42] 28_373 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[43] 29_373 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[44] 28_374 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[45] 29_374 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[46] 28_375 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[47] 29_375 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[48] 28_376 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[49] 29_376 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[50] 28_377 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[51] 29_377 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[52] 28_378 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[53] 29_378 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[54] 28_379 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[55] 29_379 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[56] 28_380 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[57] 29_380 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[58] 28_381 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[59] 29_381 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[60] 28_382 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[61] 29_382 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[62] 28_383 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[63] 29_383 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[64] 28_384 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[65] 29_384 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[66] 28_385 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[67] 29_385 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[68] 28_386 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[69] 29_386 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[70] 28_387 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[71] 29_387 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[72] 28_388 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[73] 29_388 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[74] 28_389 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[75] 29_389 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[76] 28_390 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[77] 29_390 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[78] 28_391 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[79] 29_391 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[0] 28_432 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[1] 29_432 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[2] 28_433 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[3] 29_433 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[4] 28_434 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[5] 29_434 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[6] 28_435 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[7] 29_435 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[8] 28_436 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[9] 29_436 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[10] 28_437 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[11] 29_437 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[12] 28_438 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[13] 29_438 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[14] 28_439 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[15] 29_439 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[16] 28_440 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[17] 29_440 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[18] 28_441 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[19] 29_441 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[20] 28_442 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[21] 29_442 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[22] 28_443 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[23] 29_443 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[24] 28_444 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[25] 29_444 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[26] 28_445 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[27] 29_445 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[28] 28_446 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[29] 29_446 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[30] 28_447 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[31] 29_447 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[32] 28_448 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[33] 29_448 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[34] 28_449 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[35] 29_449 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[36] 28_450 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[37] 29_450 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[38] 28_451 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[39] 29_451 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[40] 28_452 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[41] 29_452 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[42] 28_453 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[43] 29_453 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[44] 28_454 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[45] 29_454 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[46] 28_455 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[47] 29_455 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[48] 28_456 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[49] 29_456 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[50] 28_457 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[51] 29_457 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[52] 28_458 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[53] 29_458 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[54] 28_459 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[55] 29_459 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[56] 28_460 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[57] 29_460 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[58] 28_461 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[59] 29_461 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[60] 28_462 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[61] 29_462 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[62] 28_463 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[63] 29_463 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[64] 28_464 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[65] 29_464 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[66] 28_465 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[67] 29_465 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[68] 28_466 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[69] 29_466 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[70] 28_467 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[71] 29_467 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[72] 28_468 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[73] 29_468 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[74] 28_469 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[75] 29_469 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[76] 28_470 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[77] 29_470 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[78] 28_471 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[79] 29_471 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_VERT_OFFSET[0] 28_472 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_VERT_OFFSET[1] 29_472 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_VERT_OFFSET[2] 28_473 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_VERT_OFFSET[3] 29_473 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_VERT_OFFSET[4] 28_474 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_VERT_OFFSET[5] 29_474 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_VERT_OFFSET[6] 28_475 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_VERT_OFFSET[7] 29_475 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_VERT_OFFSET[8] 28_476 +GTP_CHANNEL_2.GTPE2_CHANNEL.FTS_DESKEW_SEQ_ENABLE[0] 28_662 +GTP_CHANNEL_2.GTPE2_CHANNEL.FTS_DESKEW_SEQ_ENABLE[1] 29_662 +GTP_CHANNEL_2.GTPE2_CHANNEL.FTS_DESKEW_SEQ_ENABLE[2] 28_663 +GTP_CHANNEL_2.GTPE2_CHANNEL.FTS_DESKEW_SEQ_ENABLE[3] 29_663 +GTP_CHANNEL_2.GTPE2_CHANNEL.FTS_LANE_DESKEW_CFG[0] 28_654 +GTP_CHANNEL_2.GTPE2_CHANNEL.FTS_LANE_DESKEW_CFG[1] 29_654 +GTP_CHANNEL_2.GTPE2_CHANNEL.FTS_LANE_DESKEW_CFG[2] 28_655 +GTP_CHANNEL_2.GTPE2_CHANNEL.FTS_LANE_DESKEW_CFG[3] 29_655 +GTP_CHANNEL_2.GTPE2_CHANNEL.FTS_LANE_DESKEW_EN 29_653 +GTP_CHANNEL_2.GTPE2_CHANNEL.GEARBOX_MODE[0] 28_224 +GTP_CHANNEL_2.GTPE2_CHANNEL.GEARBOX_MODE[1] 29_224 +GTP_CHANNEL_2.GTPE2_CHANNEL.GEARBOX_MODE[2] 28_225 +GTP_CHANNEL_2.GTPE2_CHANNEL.IN_USE 28_00 28_01 28_47 28_52 28_53 28_65 29_01 29_47 30_129 +GTP_CHANNEL_2.GTPE2_CHANNEL.INV_DMONITORCLK 30_13 +GTP_CHANNEL_2.GTPE2_CHANNEL.INV_DRPCLK 30_00 +GTP_CHANNEL_2.GTPE2_CHANNEL.INV_RXUSRCLK 31_01 +GTP_CHANNEL_2.GTPE2_CHANNEL.INV_SIGVALIDCLK 31_13 +GTP_CHANNEL_2.GTPE2_CHANNEL.INV_TXPHDLYTSTCLK 30_03 +GTP_CHANNEL_2.GTPE2_CHANNEL.INV_TXUSRCLK 31_04 +GTP_CHANNEL_2.GTPE2_CHANNEL.INV_CLKRSVD0 30_23 +GTP_CHANNEL_2.GTPE2_CHANNEL.INV_CLKRSVD1 31_23 +GTP_CHANNEL_2.GTPE2_CHANNEL.INV_RXUSRCLK2 30_02 +GTP_CHANNEL_2.GTPE2_CHANNEL.INV_TXUSRCLK2 30_05 +GTP_CHANNEL_2.GTPE2_CHANNEL.LOOPBACK_CFG[0] 30_20 +GTP_CHANNEL_2.GTPE2_CHANNEL.OUTREFCLK_SEL_INV[0] 28_149 +GTP_CHANNEL_2.GTPE2_CHANNEL.OUTREFCLK_SEL_INV[1] 29_149 +GTP_CHANNEL_2.GTPE2_CHANNEL.PCS_PCIE_EN 28_216 +GTP_CHANNEL_2.GTPE2_CHANNEL.PCS_RSVD_ATTR[0] 30_184 +GTP_CHANNEL_2.GTPE2_CHANNEL.PCS_RSVD_ATTR[1] 31_184 +GTP_CHANNEL_2.GTPE2_CHANNEL.PCS_RSVD_ATTR[2] 30_185 +GTP_CHANNEL_2.GTPE2_CHANNEL.PCS_RSVD_ATTR[3] 31_185 +GTP_CHANNEL_2.GTPE2_CHANNEL.PCS_RSVD_ATTR[4] 30_186 +GTP_CHANNEL_2.GTPE2_CHANNEL.PCS_RSVD_ATTR[5] 31_186 +GTP_CHANNEL_2.GTPE2_CHANNEL.PCS_RSVD_ATTR[6] 30_187 +GTP_CHANNEL_2.GTPE2_CHANNEL.PCS_RSVD_ATTR[7] 31_187 +GTP_CHANNEL_2.GTPE2_CHANNEL.PCS_RSVD_ATTR[8] 30_188 +GTP_CHANNEL_2.GTPE2_CHANNEL.PCS_RSVD_ATTR[9] 31_188 +GTP_CHANNEL_2.GTPE2_CHANNEL.PCS_RSVD_ATTR[10] 30_189 +GTP_CHANNEL_2.GTPE2_CHANNEL.PCS_RSVD_ATTR[11] 31_189 +GTP_CHANNEL_2.GTPE2_CHANNEL.PCS_RSVD_ATTR[12] 30_190 +GTP_CHANNEL_2.GTPE2_CHANNEL.PCS_RSVD_ATTR[13] 31_190 +GTP_CHANNEL_2.GTPE2_CHANNEL.PCS_RSVD_ATTR[14] 30_191 +GTP_CHANNEL_2.GTPE2_CHANNEL.PCS_RSVD_ATTR[15] 31_191 +GTP_CHANNEL_2.GTPE2_CHANNEL.PCS_RSVD_ATTR[16] 30_192 +GTP_CHANNEL_2.GTPE2_CHANNEL.PCS_RSVD_ATTR[17] 31_192 +GTP_CHANNEL_2.GTPE2_CHANNEL.PCS_RSVD_ATTR[18] 30_193 +GTP_CHANNEL_2.GTPE2_CHANNEL.PCS_RSVD_ATTR[19] 31_193 +GTP_CHANNEL_2.GTPE2_CHANNEL.PCS_RSVD_ATTR[20] 30_194 +GTP_CHANNEL_2.GTPE2_CHANNEL.PCS_RSVD_ATTR[21] 31_194 +GTP_CHANNEL_2.GTPE2_CHANNEL.PCS_RSVD_ATTR[22] 30_195 +GTP_CHANNEL_2.GTPE2_CHANNEL.PCS_RSVD_ATTR[23] 31_195 +GTP_CHANNEL_2.GTPE2_CHANNEL.PCS_RSVD_ATTR[24] 30_196 +GTP_CHANNEL_2.GTPE2_CHANNEL.PCS_RSVD_ATTR[25] 31_196 +GTP_CHANNEL_2.GTPE2_CHANNEL.PCS_RSVD_ATTR[26] 30_197 +GTP_CHANNEL_2.GTPE2_CHANNEL.PCS_RSVD_ATTR[27] 31_197 +GTP_CHANNEL_2.GTPE2_CHANNEL.PCS_RSVD_ATTR[28] 30_198 +GTP_CHANNEL_2.GTPE2_CHANNEL.PCS_RSVD_ATTR[29] 31_198 +GTP_CHANNEL_2.GTPE2_CHANNEL.PCS_RSVD_ATTR[30] 30_199 +GTP_CHANNEL_2.GTPE2_CHANNEL.PCS_RSVD_ATTR[31] 31_199 +GTP_CHANNEL_2.GTPE2_CHANNEL.PCS_RSVD_ATTR[32] 30_200 +GTP_CHANNEL_2.GTPE2_CHANNEL.PCS_RSVD_ATTR[33] 31_200 +GTP_CHANNEL_2.GTPE2_CHANNEL.PCS_RSVD_ATTR[34] 30_201 +GTP_CHANNEL_2.GTPE2_CHANNEL.PCS_RSVD_ATTR[35] 31_201 +GTP_CHANNEL_2.GTPE2_CHANNEL.PCS_RSVD_ATTR[36] 30_202 +GTP_CHANNEL_2.GTPE2_CHANNEL.PCS_RSVD_ATTR[37] 31_202 +GTP_CHANNEL_2.GTPE2_CHANNEL.PCS_RSVD_ATTR[38] 30_203 +GTP_CHANNEL_2.GTPE2_CHANNEL.PCS_RSVD_ATTR[39] 31_203 +GTP_CHANNEL_2.GTPE2_CHANNEL.PCS_RSVD_ATTR[40] 30_204 +GTP_CHANNEL_2.GTPE2_CHANNEL.PCS_RSVD_ATTR[41] 31_204 +GTP_CHANNEL_2.GTPE2_CHANNEL.PCS_RSVD_ATTR[42] 30_205 +GTP_CHANNEL_2.GTPE2_CHANNEL.PCS_RSVD_ATTR[43] 31_205 +GTP_CHANNEL_2.GTPE2_CHANNEL.PCS_RSVD_ATTR[44] 30_206 +GTP_CHANNEL_2.GTPE2_CHANNEL.PCS_RSVD_ATTR[45] 31_206 +GTP_CHANNEL_2.GTPE2_CHANNEL.PCS_RSVD_ATTR[46] 30_207 +GTP_CHANNEL_2.GTPE2_CHANNEL.PCS_RSVD_ATTR[47] 31_207 +GTP_CHANNEL_2.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[0] 29_216 +GTP_CHANNEL_2.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[1] 28_217 +GTP_CHANNEL_2.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[2] 29_217 +GTP_CHANNEL_2.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[3] 28_218 +GTP_CHANNEL_2.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[4] 29_218 +GTP_CHANNEL_2.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[5] 28_219 +GTP_CHANNEL_2.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[6] 29_219 +GTP_CHANNEL_2.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[7] 28_220 +GTP_CHANNEL_2.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[8] 29_220 +GTP_CHANNEL_2.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[9] 28_221 +GTP_CHANNEL_2.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[10] 29_221 +GTP_CHANNEL_2.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[11] 28_222 +GTP_CHANNEL_2.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[0] 28_208 +GTP_CHANNEL_2.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[1] 29_208 +GTP_CHANNEL_2.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[2] 28_209 +GTP_CHANNEL_2.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[3] 29_209 +GTP_CHANNEL_2.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[4] 28_210 +GTP_CHANNEL_2.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[5] 29_210 +GTP_CHANNEL_2.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[6] 28_211 +GTP_CHANNEL_2.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[7] 29_211 +GTP_CHANNEL_2.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[0] 28_212 +GTP_CHANNEL_2.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[1] 29_212 +GTP_CHANNEL_2.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[2] 28_213 +GTP_CHANNEL_2.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[3] 29_213 +GTP_CHANNEL_2.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[4] 28_214 +GTP_CHANNEL_2.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[5] 29_214 +GTP_CHANNEL_2.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[6] 28_215 +GTP_CHANNEL_2.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[7] 29_215 +GTP_CHANNEL_2.GTPE2_CHANNEL.PMA_LOOPBACK_CFG[0] 29_207 +GTP_CHANNEL_2.GTPE2_CHANNEL.PMA_RSV[0] 30_520 +GTP_CHANNEL_2.GTPE2_CHANNEL.PMA_RSV[1] 31_520 +GTP_CHANNEL_2.GTPE2_CHANNEL.PMA_RSV[2] 30_521 +GTP_CHANNEL_2.GTPE2_CHANNEL.PMA_RSV[3] 31_521 +GTP_CHANNEL_2.GTPE2_CHANNEL.PMA_RSV[4] 30_522 +GTP_CHANNEL_2.GTPE2_CHANNEL.PMA_RSV[5] 31_522 +GTP_CHANNEL_2.GTPE2_CHANNEL.PMA_RSV[6] 30_523 +GTP_CHANNEL_2.GTPE2_CHANNEL.PMA_RSV[7] 31_523 +GTP_CHANNEL_2.GTPE2_CHANNEL.PMA_RSV[8] 30_524 +GTP_CHANNEL_2.GTPE2_CHANNEL.PMA_RSV[9] 31_524 +GTP_CHANNEL_2.GTPE2_CHANNEL.PMA_RSV[10] 30_525 +GTP_CHANNEL_2.GTPE2_CHANNEL.PMA_RSV[11] 31_525 +GTP_CHANNEL_2.GTPE2_CHANNEL.PMA_RSV[12] 30_526 +GTP_CHANNEL_2.GTPE2_CHANNEL.PMA_RSV[13] 31_526 +GTP_CHANNEL_2.GTPE2_CHANNEL.PMA_RSV[14] 30_527 +GTP_CHANNEL_2.GTPE2_CHANNEL.PMA_RSV[15] 31_527 +GTP_CHANNEL_2.GTPE2_CHANNEL.PMA_RSV[16] 30_528 +GTP_CHANNEL_2.GTPE2_CHANNEL.PMA_RSV[17] 31_528 +GTP_CHANNEL_2.GTPE2_CHANNEL.PMA_RSV[18] 30_529 +GTP_CHANNEL_2.GTPE2_CHANNEL.PMA_RSV[19] 31_529 +GTP_CHANNEL_2.GTPE2_CHANNEL.PMA_RSV[20] 30_530 +GTP_CHANNEL_2.GTPE2_CHANNEL.PMA_RSV[21] 31_530 +GTP_CHANNEL_2.GTPE2_CHANNEL.PMA_RSV[22] 30_531 +GTP_CHANNEL_2.GTPE2_CHANNEL.PMA_RSV[23] 31_531 +GTP_CHANNEL_2.GTPE2_CHANNEL.PMA_RSV[24] 30_532 +GTP_CHANNEL_2.GTPE2_CHANNEL.PMA_RSV[25] 31_532 +GTP_CHANNEL_2.GTPE2_CHANNEL.PMA_RSV[26] 30_533 +GTP_CHANNEL_2.GTPE2_CHANNEL.PMA_RSV[27] 31_533 +GTP_CHANNEL_2.GTPE2_CHANNEL.PMA_RSV[28] 30_534 +GTP_CHANNEL_2.GTPE2_CHANNEL.PMA_RSV[29] 31_534 +GTP_CHANNEL_2.GTPE2_CHANNEL.PMA_RSV[30] 30_535 +GTP_CHANNEL_2.GTPE2_CHANNEL.PMA_RSV[31] 31_535 +GTP_CHANNEL_2.GTPE2_CHANNEL.PMA_RSV2[0] 30_336 +GTP_CHANNEL_2.GTPE2_CHANNEL.PMA_RSV2[1] 31_336 +GTP_CHANNEL_2.GTPE2_CHANNEL.PMA_RSV2[2] 30_337 +GTP_CHANNEL_2.GTPE2_CHANNEL.PMA_RSV2[3] 31_337 +GTP_CHANNEL_2.GTPE2_CHANNEL.PMA_RSV2[4] 30_338 +GTP_CHANNEL_2.GTPE2_CHANNEL.PMA_RSV2[5] 31_338 +GTP_CHANNEL_2.GTPE2_CHANNEL.PMA_RSV2[6] 30_339 +GTP_CHANNEL_2.GTPE2_CHANNEL.PMA_RSV2[7] 31_339 +GTP_CHANNEL_2.GTPE2_CHANNEL.PMA_RSV2[8] 30_340 +GTP_CHANNEL_2.GTPE2_CHANNEL.PMA_RSV2[9] 31_340 +GTP_CHANNEL_2.GTPE2_CHANNEL.PMA_RSV2[10] 30_341 +GTP_CHANNEL_2.GTPE2_CHANNEL.PMA_RSV2[11] 31_341 +GTP_CHANNEL_2.GTPE2_CHANNEL.PMA_RSV2[12] 30_342 +GTP_CHANNEL_2.GTPE2_CHANNEL.PMA_RSV2[13] 31_342 +GTP_CHANNEL_2.GTPE2_CHANNEL.PMA_RSV2[14] 30_343 +GTP_CHANNEL_2.GTPE2_CHANNEL.PMA_RSV2[15] 31_343 +GTP_CHANNEL_2.GTPE2_CHANNEL.PMA_RSV2[16] 30_344 +GTP_CHANNEL_2.GTPE2_CHANNEL.PMA_RSV2[17] 31_344 +GTP_CHANNEL_2.GTPE2_CHANNEL.PMA_RSV2[18] 30_345 +GTP_CHANNEL_2.GTPE2_CHANNEL.PMA_RSV2[19] 31_345 +GTP_CHANNEL_2.GTPE2_CHANNEL.PMA_RSV2[20] 30_346 +GTP_CHANNEL_2.GTPE2_CHANNEL.PMA_RSV2[21] 31_346 +GTP_CHANNEL_2.GTPE2_CHANNEL.PMA_RSV2[22] 30_347 +GTP_CHANNEL_2.GTPE2_CHANNEL.PMA_RSV2[23] 31_347 +GTP_CHANNEL_2.GTPE2_CHANNEL.PMA_RSV2[24] 30_348 +GTP_CHANNEL_2.GTPE2_CHANNEL.PMA_RSV2[25] 31_348 +GTP_CHANNEL_2.GTPE2_CHANNEL.PMA_RSV2[26] 30_349 +GTP_CHANNEL_2.GTPE2_CHANNEL.PMA_RSV2[27] 31_349 +GTP_CHANNEL_2.GTPE2_CHANNEL.PMA_RSV2[28] 30_350 +GTP_CHANNEL_2.GTPE2_CHANNEL.PMA_RSV2[29] 31_350 +GTP_CHANNEL_2.GTPE2_CHANNEL.PMA_RSV2[30] 30_351 +GTP_CHANNEL_2.GTPE2_CHANNEL.PMA_RSV2[31] 31_351 +GTP_CHANNEL_2.GTPE2_CHANNEL.PMA_RSV3[0] 30_288 +GTP_CHANNEL_2.GTPE2_CHANNEL.PMA_RSV3[1] 31_288 +GTP_CHANNEL_2.GTPE2_CHANNEL.PMA_RSV4[0] 30_156 +GTP_CHANNEL_2.GTPE2_CHANNEL.PMA_RSV4[1] 31_156 +GTP_CHANNEL_2.GTPE2_CHANNEL.PMA_RSV4[2] 30_157 +GTP_CHANNEL_2.GTPE2_CHANNEL.PMA_RSV4[3] 31_157 +GTP_CHANNEL_2.GTPE2_CHANNEL.PMA_RSV5[0] 31_159 +GTP_CHANNEL_2.GTPE2_CHANNEL.PMA_RSV6[0] 30_303 +GTP_CHANNEL_2.GTPE2_CHANNEL.PMA_RSV7[0] 31_303 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_BIAS_CFG[0] 30_112 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_BIAS_CFG[1] 31_112 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_BIAS_CFG[2] 30_113 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_BIAS_CFG[3] 31_113 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_BIAS_CFG[4] 30_114 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_BIAS_CFG[5] 31_114 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_BIAS_CFG[6] 30_115 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_BIAS_CFG[7] 31_115 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_BIAS_CFG[8] 30_116 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_BIAS_CFG[9] 31_116 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_BIAS_CFG[10] 30_117 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_BIAS_CFG[11] 31_117 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_BIAS_CFG[12] 30_118 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_BIAS_CFG[13] 31_118 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_BIAS_CFG[14] 30_119 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_BIAS_CFG[15] 31_119 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_BUFFER_CFG[0] 30_536 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_BUFFER_CFG[1] 31_536 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_BUFFER_CFG[2] 30_537 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_BUFFER_CFG[3] 31_537 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_BUFFER_CFG[4] 30_538 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_BUFFER_CFG[5] 31_538 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_CLKMUX_EN[0] 30_128 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_CM_SEL[0] 28_138 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_CM_SEL[1] 29_138 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_CM_TRIM[0] 30_304 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_CM_TRIM[1] 31_304 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_CM_TRIM[2] 30_305 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_CM_TRIM[3] 31_305 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_DATA_WIDTH[0] 29_141 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_DATA_WIDTH[1] 28_142 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_DATA_WIDTH[2] 29_142 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_DDI_SEL[0] 28_696 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_DDI_SEL[1] 29_696 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_DDI_SEL[2] 28_697 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_DDI_SEL[3] 29_697 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_DDI_SEL[4] 28_698 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_DDI_SEL[5] 29_698 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_DEBUG_CFG[0] 30_616 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_DEBUG_CFG[1] 31_616 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_DEBUG_CFG[2] 30_617 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_DEBUG_CFG[3] 31_617 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_DEBUG_CFG[4] 30_618 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_DEBUG_CFG[5] 31_618 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_DEBUG_CFG[6] 30_619 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_DEBUG_CFG[7] 31_619 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_DEBUG_CFG[8] 30_620 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_DEBUG_CFG[9] 31_620 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_DEBUG_CFG[10] 30_621 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_DEBUG_CFG[11] 31_621 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_DEBUG_CFG[12] 30_622 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_DEBUG_CFG[13] 31_622 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_DEFER_RESET_BUF_EN 30_552 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_DISPERR_SEQ_MATCH 29_495 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_OS_CFG[0] 28_288 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_OS_CFG[1] 29_288 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_OS_CFG[2] 28_289 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_OS_CFG[3] 29_289 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_OS_CFG[4] 28_290 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_OS_CFG[5] 29_290 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_OS_CFG[6] 28_291 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_OS_CFG[7] 29_291 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_OS_CFG[8] 28_292 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_OS_CFG[9] 29_292 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_OS_CFG[10] 28_293 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_OS_CFG[11] 29_293 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_OS_CFG[12] 28_294 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_SIG_VALID_DLY[0] 28_524 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_SIG_VALID_DLY[1] 29_524 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_SIG_VALID_DLY[2] 28_525 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_SIG_VALID_DLY[3] 29_525 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_SIG_VALID_DLY[4] 28_526 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_XCLK_SEL.RXUSR 28_143 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_CLK25_DIV[0] 28_139 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_CLK25_DIV[1] 29_139 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_CLK25_DIV[2] 28_140 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_CLK25_DIV[3] 29_140 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_CLK25_DIV[4] 28_141 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXBUF_ADDR_MODE.FAST 31_555 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXBUF_EIDLE_HI_CNT[0] 30_558 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXBUF_EIDLE_HI_CNT[1] 31_558 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXBUF_EIDLE_HI_CNT[2] 30_559 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXBUF_EIDLE_HI_CNT[3] 31_559 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXBUF_EIDLE_LO_CNT[0] 30_556 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXBUF_EIDLE_LO_CNT[1] 31_556 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXBUF_EIDLE_LO_CNT[2] 30_557 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXBUF_EIDLE_LO_CNT[3] 31_557 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXBUF_EN 30_11 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXBUF_RESET_ON_CB_CHANGE 30_560 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXBUF_RESET_ON_COMMAALIGN 30_561 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXBUF_RESET_ON_EIDLE 30_547 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXBUF_RESET_ON_RATE_CHANGE 31_560 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXBUF_THRESH_OVFLW[0] 31_552 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXBUF_THRESH_OVFLW[1] 30_553 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXBUF_THRESH_OVFLW[2] 31_553 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXBUF_THRESH_OVFLW[3] 30_554 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXBUF_THRESH_OVFLW[4] 31_554 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXBUF_THRESH_OVFLW[5] 30_555 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXBUF_THRESH_OVRD 30_548 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXBUF_THRESH_UNDFLW[0] 30_544 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXBUF_THRESH_UNDFLW[1] 31_544 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXBUF_THRESH_UNDFLW[2] 30_545 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXBUF_THRESH_UNDFLW[3] 31_545 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXBUF_THRESH_UNDFLW[4] 30_546 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXBUF_THRESH_UNDFLW[5] 31_546 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXBUFRESET_TIME[0] 29_101 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXBUFRESET_TIME[1] 28_102 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXBUFRESET_TIME[2] 29_102 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXBUFRESET_TIME[3] 28_103 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXBUFRESET_TIME[4] 29_103 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[0] 30_640 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[1] 31_640 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[2] 30_641 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[3] 31_641 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[4] 30_642 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[5] 31_642 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[6] 30_643 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[7] 31_643 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[8] 30_644 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[9] 31_644 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[10] 30_645 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[11] 31_645 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[12] 30_646 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[13] 31_646 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[14] 30_647 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[15] 31_647 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[16] 30_648 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[17] 31_648 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[18] 30_649 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[19] 31_649 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[20] 30_650 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[21] 31_650 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[22] 30_651 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[23] 31_651 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[24] 30_652 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[25] 31_652 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[26] 30_653 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[27] 31_653 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[28] 30_654 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[29] 31_654 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[30] 30_655 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[31] 31_655 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[32] 30_656 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[33] 31_656 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[34] 30_657 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[35] 31_657 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[36] 30_658 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[37] 31_658 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[38] 30_659 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[39] 31_659 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[40] 30_660 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[41] 31_660 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[42] 30_661 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[43] 31_661 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[44] 30_662 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[45] 31_662 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[46] 30_663 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[47] 31_663 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[48] 30_664 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[49] 31_664 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[50] 30_665 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[51] 31_665 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[52] 30_666 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[53] 31_666 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[54] 30_667 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[55] 31_667 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[56] 30_668 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[57] 31_668 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[58] 30_669 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[59] 31_669 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[60] 30_670 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[61] 31_670 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[62] 30_671 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[63] 31_671 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[64] 30_672 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[65] 31_672 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[66] 30_673 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[67] 31_673 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[68] 30_674 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[69] 31_674 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[70] 30_675 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[71] 31_675 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[72] 30_676 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[73] 31_676 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[74] 30_677 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[75] 31_677 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[76] 30_678 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[77] 31_678 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[78] 30_679 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[79] 31_679 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[80] 30_680 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[81] 31_680 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[82] 30_681 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_FR_RESET_ON_EIDLE[0] 30_638 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_HOLD_DURING_EIDLE[0] 31_637 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_LOCK_CFG[0] 30_632 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_LOCK_CFG[1] 31_632 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_LOCK_CFG[2] 30_633 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_LOCK_CFG[3] 31_633 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_LOCK_CFG[4] 30_634 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_LOCK_CFG[5] 31_634 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_PH_RESET_ON_EIDLE[0] 31_638 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDRFREQRESET_TIME[0] 29_106 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDRFREQRESET_TIME[1] 28_107 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDRFREQRESET_TIME[2] 29_107 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDRFREQRESET_TIME[3] 28_108 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDRFREQRESET_TIME[4] 29_108 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDRPHRESET_TIME[0] 28_109 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDRPHRESET_TIME[1] 29_109 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDRPHRESET_TIME[2] 28_110 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDRPHRESET_TIME[3] 29_110 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDRPHRESET_TIME[4] 28_111 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXDLY_CFG[0] 28_680 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXDLY_CFG[1] 29_680 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXDLY_CFG[2] 28_681 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXDLY_CFG[3] 29_681 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXDLY_CFG[4] 28_682 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXDLY_CFG[5] 29_682 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXDLY_CFG[6] 28_683 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXDLY_CFG[7] 29_683 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXDLY_CFG[8] 28_684 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXDLY_CFG[9] 29_684 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXDLY_CFG[10] 28_685 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXDLY_CFG[11] 29_685 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXDLY_CFG[12] 28_686 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXDLY_CFG[13] 29_686 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXDLY_CFG[14] 28_687 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXDLY_CFG[15] 29_687 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXDLY_LCFG[0] 30_576 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXDLY_LCFG[1] 31_576 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXDLY_LCFG[2] 30_577 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXDLY_LCFG[3] 31_577 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXDLY_LCFG[4] 30_578 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXDLY_LCFG[5] 31_578 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXDLY_LCFG[6] 30_579 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXDLY_LCFG[7] 31_579 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXDLY_LCFG[8] 30_580 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXDLY_TAP_CFG[0] 28_672 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXDLY_TAP_CFG[1] 29_672 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXDLY_TAP_CFG[2] 28_673 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXDLY_TAP_CFG[3] 29_673 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXDLY_TAP_CFG[4] 28_674 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXDLY_TAP_CFG[5] 29_674 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXDLY_TAP_CFG[6] 28_675 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXDLY_TAP_CFG[7] 29_675 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXDLY_TAP_CFG[8] 28_676 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXDLY_TAP_CFG[9] 29_676 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXDLY_TAP_CFG[10] 28_677 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXDLY_TAP_CFG[11] 29_677 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXDLY_TAP_CFG[12] 28_678 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXDLY_TAP_CFG[13] 29_678 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXDLY_TAP_CFG[14] 28_679 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXDLY_TAP_CFG[15] 29_679 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXGEARBOX_EN 29_607 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXISCANRESET_TIME[0] 29_123 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXISCANRESET_TIME[1] 28_124 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXISCANRESET_TIME[2] 29_124 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXISCANRESET_TIME[3] 28_125 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXISCANRESET_TIME[4] 29_125 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPM_BIAS_STARTUP_DISABLE[0] 31_391 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPM_CFG[0] 30_328 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPM_CFG[1] 31_328 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPM_CFG[2] 30_329 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPM_CFG[3] 31_329 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPM_CM_CFG[0] 30_430 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPM_GC_CFG[0] 30_432 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPM_GC_CFG[1] 31_432 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPM_GC_CFG[2] 30_433 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPM_GC_CFG[3] 31_433 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPM_GC_CFG[4] 30_434 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPM_GC_CFG[5] 31_434 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPM_GC_CFG[6] 30_435 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPM_GC_CFG[7] 31_435 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPM_GC_CFG[8] 30_436 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPM_GC_CFG2[0] 31_442 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPM_GC_CFG2[1] 30_443 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPM_GC_CFG2[2] 31_443 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPM_HF_CFG[0] 28_336 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPM_HF_CFG[1] 29_336 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPM_HF_CFG[2] 28_337 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPM_HF_CFG[3] 29_337 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPM_HF_CFG[4] 28_338 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPM_HF_CFG[5] 29_338 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPM_HF_CFG[6] 28_339 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPM_HF_CFG[7] 29_339 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPM_HF_CFG[8] 28_340 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPM_HF_CFG[9] 29_340 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPM_HF_CFG[10] 28_341 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPM_HF_CFG[11] 29_341 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPM_HF_CFG[12] 28_342 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPM_HF_CFG[13] 29_342 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPM_HF_CFG2[0] 30_424 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPM_HF_CFG2[1] 31_424 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPM_HF_CFG2[2] 30_425 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPM_HF_CFG2[3] 31_425 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPM_HF_CFG2[4] 30_426 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPM_HF_CFG3[0] 31_389 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPM_HF_CFG3[1] 30_390 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPM_HF_CFG3[2] 31_390 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPM_HF_CFG3[3] 30_391 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPM_HOLD_DURING_EIDLE[0] 28_247 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPM_INCM_CFG[0] 30_439 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPM_IPCM_CFG[0] 31_439 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPM_LF_CFG[0] 28_344 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPM_LF_CFG[1] 29_344 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPM_LF_CFG[2] 28_345 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPM_LF_CFG[3] 29_345 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPM_LF_CFG[4] 28_346 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPM_LF_CFG[5] 29_346 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPM_LF_CFG[6] 28_347 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPM_LF_CFG[7] 29_347 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPM_LF_CFG[8] 28_348 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPM_LF_CFG[9] 29_348 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPM_LF_CFG[10] 28_349 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPM_LF_CFG[11] 29_349 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPM_LF_CFG[12] 28_350 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPM_LF_CFG[13] 29_350 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPM_LF_CFG[14] 28_351 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPM_LF_CFG[15] 29_351 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPM_LF_CFG[16] 28_343 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPM_LF_CFG[17] 29_343 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPM_LF_CFG2[0] 31_426 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPM_LF_CFG2[1] 30_427 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPM_LF_CFG2[2] 31_427 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPM_LF_CFG2[3] 30_428 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPM_LF_CFG2[4] 31_428 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPM_OSINT_CFG[0] 30_440 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPM_OSINT_CFG[1] 31_440 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPM_OSINT_CFG[2] 30_441 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPM_CFG1[0] 30_330 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPMRESET_TIME[0] 28_112 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPMRESET_TIME[1] 29_112 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPMRESET_TIME[2] 28_113 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPMRESET_TIME[3] 29_113 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPMRESET_TIME[4] 28_114 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPMRESET_TIME[5] 29_114 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPMRESET_TIME[6] 28_115 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXOOB_CFG[0] 28_144 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXOOB_CFG[1] 29_144 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXOOB_CFG[2] 28_145 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXOOB_CFG[3] 29_145 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXOOB_CFG[4] 28_146 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXOOB_CFG[5] 29_146 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXOOB_CFG[6] 28_147 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXOOB_CLK_CFG.FABRIC 31_129 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXOSCALRESET_TIME[0] 28_187 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXOSCALRESET_TIME[1] 29_187 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXOSCALRESET_TIME[2] 28_188 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXOSCALRESET_TIME[3] 29_188 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXOSCALRESET_TIME[4] 28_189 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXOSCALRESET_TIMEOUT[0] 29_189 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXOSCALRESET_TIMEOUT[1] 28_190 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXOSCALRESET_TIMEOUT[2] 29_190 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXOSCALRESET_TIMEOUT[3] 28_191 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXOSCALRESET_TIMEOUT[4] 29_191 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXOUT_DIV[0] 30_384 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXOUT_DIV[1] 31_384 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXPCSRESET_TIME[0] 29_115 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXPCSRESET_TIME[1] 28_116 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXPCSRESET_TIME[2] 29_116 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXPCSRESET_TIME[3] 28_117 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXPCSRESET_TIME[4] 29_117 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXPH_CFG[0] 30_584 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXPH_CFG[1] 31_584 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXPH_CFG[2] 30_585 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXPH_CFG[3] 31_585 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXPH_CFG[4] 30_586 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXPH_CFG[5] 31_586 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXPH_CFG[6] 30_587 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXPH_CFG[7] 31_587 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXPH_CFG[8] 30_588 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXPH_CFG[9] 31_588 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXPH_CFG[10] 30_589 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXPH_CFG[11] 31_589 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXPH_CFG[12] 30_590 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXPH_CFG[13] 31_590 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXPH_CFG[14] 30_591 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXPH_CFG[15] 31_591 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXPH_CFG[16] 30_592 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXPH_CFG[17] 31_592 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXPH_CFG[18] 30_593 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXPH_CFG[19] 31_593 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXPH_CFG[20] 30_594 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXPH_CFG[21] 31_594 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXPH_CFG[22] 30_595 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXPH_CFG[23] 31_595 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXPH_MONITOR_SEL[0] 28_700 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXPH_MONITOR_SEL[1] 29_700 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXPH_MONITOR_SEL[2] 28_701 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXPH_MONITOR_SEL[3] 29_701 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXPH_MONITOR_SEL[4] 28_702 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXPHDLY_CFG[0] 30_600 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXPHDLY_CFG[1] 31_600 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXPHDLY_CFG[2] 30_601 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXPHDLY_CFG[3] 31_601 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXPHDLY_CFG[4] 30_602 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXPHDLY_CFG[5] 31_602 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXPHDLY_CFG[6] 30_603 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXPHDLY_CFG[7] 31_603 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXPHDLY_CFG[8] 30_604 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXPHDLY_CFG[9] 31_604 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXPHDLY_CFG[10] 30_605 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXPHDLY_CFG[11] 31_605 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXPHDLY_CFG[12] 30_606 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXPHDLY_CFG[13] 31_606 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXPHDLY_CFG[14] 30_607 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXPHDLY_CFG[15] 31_607 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXPHDLY_CFG[16] 30_608 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXPHDLY_CFG[17] 31_608 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXPHDLY_CFG[18] 30_609 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXPHDLY_CFG[19] 31_609 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXPHDLY_CFG[20] 30_610 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXPHDLY_CFG[21] 31_610 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXPHDLY_CFG[22] 30_611 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXPHDLY_CFG[23] 31_611 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXPI_CFG0[0] 31_430 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXPI_CFG0[1] 30_431 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXPI_CFG0[2] 31_431 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXPI_CFG1[0] 30_442 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXPI_CFG2[0] 31_441 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXPMARESET_TIME[0] 28_104 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXPMARESET_TIME[1] 29_104 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXPMARESET_TIME[2] 28_105 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXPMARESET_TIME[3] 29_105 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXPMARESET_TIME[4] 28_106 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXPRBS_ERR_LOOPBACK[0] 28_136 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXSLIDE_AUTO_WAIT[0] 28_520 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXSLIDE_AUTO_WAIT[1] 29_520 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXSLIDE_AUTO_WAIT[2] 28_521 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXSLIDE_AUTO_WAIT[3] 29_521 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXSLIDE_MODE.AUTO 28_519 !29_519 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXSLIDE_MODE.PCS !28_519 29_519 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXSLIDE_MODE.PMA 28_519 29_519 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXSYNC_MULTILANE[0] 28_133 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXSYNC_OVRD[0] 29_135 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXSYNC_SKIP_DA[0] 29_134 +GTP_CHANNEL_2.GTPE2_CHANNEL.SAS_MAX_COM[0] 28_171 +GTP_CHANNEL_2.GTPE2_CHANNEL.SAS_MAX_COM[1] 29_171 +GTP_CHANNEL_2.GTPE2_CHANNEL.SAS_MAX_COM[2] 28_172 +GTP_CHANNEL_2.GTPE2_CHANNEL.SAS_MAX_COM[3] 29_172 +GTP_CHANNEL_2.GTPE2_CHANNEL.SAS_MAX_COM[4] 28_173 +GTP_CHANNEL_2.GTPE2_CHANNEL.SAS_MAX_COM[5] 29_173 +GTP_CHANNEL_2.GTPE2_CHANNEL.SAS_MAX_COM[6] 28_174 +GTP_CHANNEL_2.GTPE2_CHANNEL.SAS_MIN_COM[0] 29_156 +GTP_CHANNEL_2.GTPE2_CHANNEL.SAS_MIN_COM[1] 28_157 +GTP_CHANNEL_2.GTPE2_CHANNEL.SAS_MIN_COM[2] 29_157 +GTP_CHANNEL_2.GTPE2_CHANNEL.SAS_MIN_COM[3] 28_158 +GTP_CHANNEL_2.GTPE2_CHANNEL.SAS_MIN_COM[4] 29_158 +GTP_CHANNEL_2.GTPE2_CHANNEL.SAS_MIN_COM[5] 28_159 +GTP_CHANNEL_2.GTPE2_CHANNEL.SATA_BURST_SEQ_LEN[0] 28_150 +GTP_CHANNEL_2.GTPE2_CHANNEL.SATA_BURST_SEQ_LEN[1] 29_150 +GTP_CHANNEL_2.GTPE2_CHANNEL.SATA_BURST_SEQ_LEN[2] 28_151 +GTP_CHANNEL_2.GTPE2_CHANNEL.SATA_BURST_SEQ_LEN[3] 29_151 +GTP_CHANNEL_2.GTPE2_CHANNEL.SATA_BURST_VAL[0] 29_147 +GTP_CHANNEL_2.GTPE2_CHANNEL.SATA_BURST_VAL[1] 28_148 +GTP_CHANNEL_2.GTPE2_CHANNEL.SATA_BURST_VAL[2] 29_148 +GTP_CHANNEL_2.GTPE2_CHANNEL.SATA_EIDLE_VAL[0] 28_152 +GTP_CHANNEL_2.GTPE2_CHANNEL.SATA_EIDLE_VAL[1] 29_152 +GTP_CHANNEL_2.GTPE2_CHANNEL.SATA_EIDLE_VAL[2] 28_153 +GTP_CHANNEL_2.GTPE2_CHANNEL.SATA_MAX_BURST[0] 28_168 +GTP_CHANNEL_2.GTPE2_CHANNEL.SATA_MAX_BURST[1] 29_168 +GTP_CHANNEL_2.GTPE2_CHANNEL.SATA_MAX_BURST[2] 28_169 +GTP_CHANNEL_2.GTPE2_CHANNEL.SATA_MAX_BURST[3] 29_169 +GTP_CHANNEL_2.GTPE2_CHANNEL.SATA_MAX_BURST[4] 28_170 +GTP_CHANNEL_2.GTPE2_CHANNEL.SATA_MAX_BURST[5] 29_170 +GTP_CHANNEL_2.GTPE2_CHANNEL.SATA_MAX_INIT[0] 28_176 +GTP_CHANNEL_2.GTPE2_CHANNEL.SATA_MAX_INIT[1] 29_176 +GTP_CHANNEL_2.GTPE2_CHANNEL.SATA_MAX_INIT[2] 28_177 +GTP_CHANNEL_2.GTPE2_CHANNEL.SATA_MAX_INIT[3] 29_177 +GTP_CHANNEL_2.GTPE2_CHANNEL.SATA_MAX_INIT[4] 28_178 +GTP_CHANNEL_2.GTPE2_CHANNEL.SATA_MAX_INIT[5] 29_178 +GTP_CHANNEL_2.GTPE2_CHANNEL.SATA_MAX_WAKE[0] 28_179 +GTP_CHANNEL_2.GTPE2_CHANNEL.SATA_MAX_WAKE[1] 29_179 +GTP_CHANNEL_2.GTPE2_CHANNEL.SATA_MAX_WAKE[2] 28_180 +GTP_CHANNEL_2.GTPE2_CHANNEL.SATA_MAX_WAKE[3] 29_180 +GTP_CHANNEL_2.GTPE2_CHANNEL.SATA_MAX_WAKE[4] 28_181 +GTP_CHANNEL_2.GTPE2_CHANNEL.SATA_MAX_WAKE[5] 29_181 +GTP_CHANNEL_2.GTPE2_CHANNEL.SATA_MIN_BURST[0] 29_153 +GTP_CHANNEL_2.GTPE2_CHANNEL.SATA_MIN_BURST[1] 28_154 +GTP_CHANNEL_2.GTPE2_CHANNEL.SATA_MIN_BURST[2] 29_154 +GTP_CHANNEL_2.GTPE2_CHANNEL.SATA_MIN_BURST[3] 28_155 +GTP_CHANNEL_2.GTPE2_CHANNEL.SATA_MIN_BURST[4] 29_155 +GTP_CHANNEL_2.GTPE2_CHANNEL.SATA_MIN_BURST[5] 28_156 +GTP_CHANNEL_2.GTPE2_CHANNEL.SATA_MIN_INIT[0] 28_160 +GTP_CHANNEL_2.GTPE2_CHANNEL.SATA_MIN_INIT[1] 29_160 +GTP_CHANNEL_2.GTPE2_CHANNEL.SATA_MIN_INIT[2] 28_161 +GTP_CHANNEL_2.GTPE2_CHANNEL.SATA_MIN_INIT[3] 29_161 +GTP_CHANNEL_2.GTPE2_CHANNEL.SATA_MIN_INIT[4] 28_162 +GTP_CHANNEL_2.GTPE2_CHANNEL.SATA_MIN_INIT[5] 29_162 +GTP_CHANNEL_2.GTPE2_CHANNEL.SATA_MIN_WAKE[0] 28_163 +GTP_CHANNEL_2.GTPE2_CHANNEL.SATA_MIN_WAKE[1] 29_163 +GTP_CHANNEL_2.GTPE2_CHANNEL.SATA_MIN_WAKE[2] 28_164 +GTP_CHANNEL_2.GTPE2_CHANNEL.SATA_MIN_WAKE[3] 29_164 +GTP_CHANNEL_2.GTPE2_CHANNEL.SATA_MIN_WAKE[4] 28_165 +GTP_CHANNEL_2.GTPE2_CHANNEL.SATA_MIN_WAKE[5] 29_165 +GTP_CHANNEL_2.GTPE2_CHANNEL.SATA_PLL_CFG.VCO_1500MHZ 30_55 +GTP_CHANNEL_2.GTPE2_CHANNEL.SATA_PLL_CFG.VCO_750MHZ 31_55 +GTP_CHANNEL_2.GTPE2_CHANNEL.SHOW_REALIGN_COMMA 29_522 +GTP_CHANNEL_2.GTPE2_CHANNEL.TERM_RCAL_CFG[0] 30_136 +GTP_CHANNEL_2.GTPE2_CHANNEL.TERM_RCAL_CFG[1] 31_136 +GTP_CHANNEL_2.GTPE2_CHANNEL.TERM_RCAL_CFG[2] 30_137 +GTP_CHANNEL_2.GTPE2_CHANNEL.TERM_RCAL_CFG[3] 31_137 +GTP_CHANNEL_2.GTPE2_CHANNEL.TERM_RCAL_CFG[4] 30_138 +GTP_CHANNEL_2.GTPE2_CHANNEL.TERM_RCAL_CFG[5] 31_138 +GTP_CHANNEL_2.GTPE2_CHANNEL.TERM_RCAL_CFG[6] 30_139 +GTP_CHANNEL_2.GTPE2_CHANNEL.TERM_RCAL_CFG[7] 31_139 +GTP_CHANNEL_2.GTPE2_CHANNEL.TERM_RCAL_CFG[8] 30_140 +GTP_CHANNEL_2.GTPE2_CHANNEL.TERM_RCAL_CFG[9] 31_140 +GTP_CHANNEL_2.GTPE2_CHANNEL.TERM_RCAL_CFG[10] 30_141 +GTP_CHANNEL_2.GTPE2_CHANNEL.TERM_RCAL_CFG[11] 31_141 +GTP_CHANNEL_2.GTPE2_CHANNEL.TERM_RCAL_CFG[12] 30_142 +GTP_CHANNEL_2.GTPE2_CHANNEL.TERM_RCAL_CFG[13] 31_142 +GTP_CHANNEL_2.GTPE2_CHANNEL.TERM_RCAL_CFG[14] 30_143 +GTP_CHANNEL_2.GTPE2_CHANNEL.TERM_RCAL_OVRD[0] 31_150 +GTP_CHANNEL_2.GTPE2_CHANNEL.TERM_RCAL_OVRD[1] 30_151 +GTP_CHANNEL_2.GTPE2_CHANNEL.TERM_RCAL_OVRD[2] 31_151 +GTP_CHANNEL_2.GTPE2_CHANNEL.TRANS_TIME_RATE[0] 28_192 +GTP_CHANNEL_2.GTPE2_CHANNEL.TRANS_TIME_RATE[1] 29_192 +GTP_CHANNEL_2.GTPE2_CHANNEL.TRANS_TIME_RATE[2] 28_193 +GTP_CHANNEL_2.GTPE2_CHANNEL.TRANS_TIME_RATE[3] 29_193 +GTP_CHANNEL_2.GTPE2_CHANNEL.TRANS_TIME_RATE[4] 28_194 +GTP_CHANNEL_2.GTPE2_CHANNEL.TRANS_TIME_RATE[5] 29_194 +GTP_CHANNEL_2.GTPE2_CHANNEL.TRANS_TIME_RATE[6] 28_195 +GTP_CHANNEL_2.GTPE2_CHANNEL.TRANS_TIME_RATE[7] 29_195 +GTP_CHANNEL_2.GTPE2_CHANNEL.TST_RSV[0] 30_504 +GTP_CHANNEL_2.GTPE2_CHANNEL.TST_RSV[1] 31_504 +GTP_CHANNEL_2.GTPE2_CHANNEL.TST_RSV[2] 30_505 +GTP_CHANNEL_2.GTPE2_CHANNEL.TST_RSV[3] 31_505 +GTP_CHANNEL_2.GTPE2_CHANNEL.TST_RSV[4] 30_506 +GTP_CHANNEL_2.GTPE2_CHANNEL.TST_RSV[5] 31_506 +GTP_CHANNEL_2.GTPE2_CHANNEL.TST_RSV[6] 30_507 +GTP_CHANNEL_2.GTPE2_CHANNEL.TST_RSV[7] 31_507 +GTP_CHANNEL_2.GTPE2_CHANNEL.TST_RSV[8] 30_508 +GTP_CHANNEL_2.GTPE2_CHANNEL.TST_RSV[9] 31_508 +GTP_CHANNEL_2.GTPE2_CHANNEL.TST_RSV[10] 30_509 +GTP_CHANNEL_2.GTPE2_CHANNEL.TST_RSV[11] 31_509 +GTP_CHANNEL_2.GTPE2_CHANNEL.TST_RSV[12] 30_510 +GTP_CHANNEL_2.GTPE2_CHANNEL.TST_RSV[13] 31_510 +GTP_CHANNEL_2.GTPE2_CHANNEL.TST_RSV[14] 30_511 +GTP_CHANNEL_2.GTPE2_CHANNEL.TST_RSV[15] 31_511 +GTP_CHANNEL_2.GTPE2_CHANNEL.TST_RSV[16] 30_512 +GTP_CHANNEL_2.GTPE2_CHANNEL.TST_RSV[17] 31_512 +GTP_CHANNEL_2.GTPE2_CHANNEL.TST_RSV[18] 30_513 +GTP_CHANNEL_2.GTPE2_CHANNEL.TST_RSV[19] 31_513 +GTP_CHANNEL_2.GTPE2_CHANNEL.TST_RSV[20] 30_514 +GTP_CHANNEL_2.GTPE2_CHANNEL.TST_RSV[21] 31_514 +GTP_CHANNEL_2.GTPE2_CHANNEL.TST_RSV[22] 30_515 +GTP_CHANNEL_2.GTPE2_CHANNEL.TST_RSV[23] 31_515 +GTP_CHANNEL_2.GTPE2_CHANNEL.TST_RSV[24] 30_516 +GTP_CHANNEL_2.GTPE2_CHANNEL.TST_RSV[25] 31_516 +GTP_CHANNEL_2.GTPE2_CHANNEL.TST_RSV[26] 30_517 +GTP_CHANNEL_2.GTPE2_CHANNEL.TST_RSV[27] 31_517 +GTP_CHANNEL_2.GTPE2_CHANNEL.TST_RSV[28] 30_518 +GTP_CHANNEL_2.GTPE2_CHANNEL.TST_RSV[29] 31_518 +GTP_CHANNEL_2.GTPE2_CHANNEL.TST_RSV[30] 30_519 +GTP_CHANNEL_2.GTPE2_CHANNEL.TST_RSV[31] 31_519 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_CLKMUX_EN[0] 31_128 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_DATA_WIDTH[0] 30_152 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_DATA_WIDTH[1] 31_152 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_DATA_WIDTH[2] 30_153 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_DRIVE_MODE.PIPE 28_200 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_EIDLE_ASSERT_DELAY[0] 28_203 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_EIDLE_ASSERT_DELAY[1] 29_203 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_EIDLE_ASSERT_DELAY[2] 28_204 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_EIDLE_DEASSERT_DELAY[0] 29_204 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_EIDLE_DEASSERT_DELAY[1] 28_205 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_EIDLE_DEASSERT_DELAY[2] 29_205 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_LOOPBACK_DRIVE_HIZ 29_202 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_MAINCURSOR_SEL[0] 31_289 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_MARGIN_FULL_0[0] 30_232 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_MARGIN_FULL_0[1] 31_232 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_MARGIN_FULL_0[2] 30_233 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_MARGIN_FULL_0[3] 31_233 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_MARGIN_FULL_0[4] 30_234 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_MARGIN_FULL_0[5] 31_234 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_MARGIN_FULL_0[6] 30_235 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_MARGIN_FULL_1[0] 30_236 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_MARGIN_FULL_1[1] 31_236 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_MARGIN_FULL_1[2] 30_237 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_MARGIN_FULL_1[3] 31_237 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_MARGIN_FULL_1[4] 30_238 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_MARGIN_FULL_1[5] 31_238 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_MARGIN_FULL_1[6] 30_239 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_MARGIN_FULL_2[0] 30_240 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_MARGIN_FULL_2[1] 31_240 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_MARGIN_FULL_2[2] 30_241 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_MARGIN_FULL_2[3] 31_241 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_MARGIN_FULL_2[4] 30_242 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_MARGIN_FULL_2[5] 31_242 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_MARGIN_FULL_2[6] 30_243 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_MARGIN_FULL_3[0] 30_244 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_MARGIN_FULL_3[1] 31_244 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_MARGIN_FULL_3[2] 30_245 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_MARGIN_FULL_3[3] 31_245 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_MARGIN_FULL_3[4] 30_246 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_MARGIN_FULL_3[5] 31_246 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_MARGIN_FULL_3[6] 30_247 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_MARGIN_FULL_4[0] 30_248 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_MARGIN_FULL_4[1] 31_248 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_MARGIN_FULL_4[2] 30_249 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_MARGIN_FULL_4[3] 31_249 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_MARGIN_FULL_4[4] 30_250 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_MARGIN_FULL_4[5] 31_250 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_MARGIN_FULL_4[6] 30_251 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_MARGIN_LOW_0[0] 30_252 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_MARGIN_LOW_0[1] 31_252 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_MARGIN_LOW_0[2] 30_253 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_MARGIN_LOW_0[3] 31_253 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_MARGIN_LOW_0[4] 30_254 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_MARGIN_LOW_0[5] 31_254 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_MARGIN_LOW_0[6] 30_255 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_MARGIN_LOW_1[0] 30_256 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_MARGIN_LOW_1[1] 31_256 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_MARGIN_LOW_1[2] 30_257 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_MARGIN_LOW_1[3] 31_257 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_MARGIN_LOW_1[4] 30_258 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_MARGIN_LOW_1[5] 31_258 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_MARGIN_LOW_1[6] 30_259 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_MARGIN_LOW_2[0] 30_260 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_MARGIN_LOW_2[1] 31_260 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_MARGIN_LOW_2[2] 30_261 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_MARGIN_LOW_2[3] 31_261 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_MARGIN_LOW_2[4] 30_262 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_MARGIN_LOW_2[5] 31_262 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_MARGIN_LOW_2[6] 30_263 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_MARGIN_LOW_3[0] 30_264 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_MARGIN_LOW_3[1] 31_264 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_MARGIN_LOW_3[2] 30_265 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_MARGIN_LOW_3[3] 31_265 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_MARGIN_LOW_3[4] 30_266 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_MARGIN_LOW_3[5] 31_266 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_MARGIN_LOW_3[6] 30_267 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_MARGIN_LOW_4[0] 30_268 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_MARGIN_LOW_4[1] 31_268 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_MARGIN_LOW_4[2] 30_269 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_MARGIN_LOW_4[3] 31_269 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_MARGIN_LOW_4[4] 30_270 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_MARGIN_LOW_4[5] 31_270 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_MARGIN_LOW_4[6] 30_271 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_PREDRIVER_MODE[0] 28_206 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_RXDETECT_CFG[0] 30_296 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_RXDETECT_CFG[1] 31_296 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_RXDETECT_CFG[2] 30_297 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_RXDETECT_CFG[3] 31_297 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_RXDETECT_CFG[4] 30_298 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_RXDETECT_CFG[5] 31_298 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_RXDETECT_CFG[6] 30_299 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_RXDETECT_CFG[7] 31_299 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_RXDETECT_CFG[8] 30_300 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_RXDETECT_CFG[9] 31_300 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_RXDETECT_CFG[10] 30_301 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_RXDETECT_CFG[11] 31_301 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_RXDETECT_CFG[12] 30_302 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_RXDETECT_CFG[13] 31_302 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_RXDETECT_REF[0] 30_292 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_RXDETECT_REF[1] 31_292 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_RXDETECT_REF[2] 30_293 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_XCLK_SEL.TXUSR 31_11 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_CLK25_DIV[0] 30_144 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_CLK25_DIV[1] 31_144 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_CLK25_DIV[2] 30_145 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_CLK25_DIV[3] 31_145 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_CLK25_DIV[4] 30_146 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_DEEMPH0[0] 30_272 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_DEEMPH0[1] 31_272 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_DEEMPH0[2] 30_273 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_DEEMPH0[3] 31_273 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_DEEMPH0[4] 30_274 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_DEEMPH0[5] 31_274 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_DEEMPH1[0] 30_276 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_DEEMPH1[1] 31_276 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_DEEMPH1[2] 30_277 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_DEEMPH1[3] 31_277 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_DEEMPH1[4] 30_278 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_DEEMPH1[5] 31_278 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXBUF_EN 28_231 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXBUF_RESET_ON_RATE_CHANGE 29_231 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXDLY_CFG[0] 30_80 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXDLY_CFG[1] 31_80 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXDLY_CFG[2] 30_81 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXDLY_CFG[3] 31_81 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXDLY_CFG[4] 30_82 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXDLY_CFG[5] 31_82 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXDLY_CFG[6] 30_83 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXDLY_CFG[7] 31_83 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXDLY_CFG[8] 30_84 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXDLY_CFG[9] 31_84 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXDLY_CFG[10] 30_85 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXDLY_CFG[11] 31_85 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXDLY_CFG[12] 30_86 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXDLY_CFG[13] 31_86 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXDLY_CFG[14] 30_87 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXDLY_CFG[15] 31_87 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXDLY_LCFG[0] 30_568 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXDLY_LCFG[1] 31_568 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXDLY_LCFG[2] 30_569 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXDLY_LCFG[3] 31_569 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXDLY_LCFG[4] 30_570 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXDLY_LCFG[5] 31_570 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXDLY_LCFG[6] 30_571 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXDLY_LCFG[7] 31_571 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXDLY_LCFG[8] 30_572 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXDLY_TAP_CFG[0] 30_88 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXDLY_TAP_CFG[1] 31_88 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXDLY_TAP_CFG[2] 30_89 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXDLY_TAP_CFG[3] 31_89 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXDLY_TAP_CFG[4] 30_90 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXDLY_TAP_CFG[5] 31_90 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXDLY_TAP_CFG[6] 30_91 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXDLY_TAP_CFG[7] 31_91 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXDLY_TAP_CFG[8] 30_92 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXDLY_TAP_CFG[9] 31_92 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXDLY_TAP_CFG[10] 30_93 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXDLY_TAP_CFG[11] 31_93 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXDLY_TAP_CFG[12] 30_94 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXDLY_TAP_CFG[13] 31_94 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXDLY_TAP_CFG[14] 30_95 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXDLY_TAP_CFG[15] 31_95 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXGEARBOX_EN 29_226 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXOOB_CFG[0] 31_20 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXOUT_DIV[0] 30_386 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXOUT_DIV[1] 31_386 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPCSRESET_TIME[0] 29_130 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPCSRESET_TIME[1] 28_131 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPCSRESET_TIME[2] 29_131 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPCSRESET_TIME[3] 28_132 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPCSRESET_TIME[4] 29_132 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPH_CFG[0] 30_96 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPH_CFG[1] 31_96 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPH_CFG[2] 30_97 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPH_CFG[3] 31_97 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPH_CFG[4] 30_98 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPH_CFG[5] 31_98 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPH_CFG[6] 30_99 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPH_CFG[7] 31_99 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPH_CFG[8] 30_100 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPH_CFG[9] 31_100 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPH_CFG[10] 30_101 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPH_CFG[11] 31_101 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPH_CFG[12] 30_102 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPH_CFG[13] 31_102 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPH_CFG[14] 30_103 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPH_CFG[15] 31_103 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPH_MONITOR_SEL[0] 30_108 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPH_MONITOR_SEL[1] 31_108 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPH_MONITOR_SEL[2] 30_109 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPH_MONITOR_SEL[3] 31_109 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPH_MONITOR_SEL[4] 30_110 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPHDLY_CFG[0] 30_64 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPHDLY_CFG[1] 31_64 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPHDLY_CFG[2] 30_65 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPHDLY_CFG[3] 31_65 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPHDLY_CFG[4] 30_66 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPHDLY_CFG[5] 31_66 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPHDLY_CFG[6] 30_67 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPHDLY_CFG[7] 31_67 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPHDLY_CFG[8] 30_68 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPHDLY_CFG[9] 31_68 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPHDLY_CFG[10] 30_69 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPHDLY_CFG[11] 31_69 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPHDLY_CFG[12] 30_70 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPHDLY_CFG[13] 31_70 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPHDLY_CFG[14] 30_71 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPHDLY_CFG[15] 31_71 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPHDLY_CFG[16] 30_72 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPHDLY_CFG[17] 31_72 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPHDLY_CFG[18] 30_73 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPHDLY_CFG[19] 31_73 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPHDLY_CFG[20] 30_74 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPHDLY_CFG[21] 31_74 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPHDLY_CFG[22] 30_75 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPHDLY_CFG[23] 31_75 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPI_GREY_SEL[0] 31_498 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPI_INVSTROBE_SEL[0] 30_498 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPI_PPM_CFG[0] 30_488 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPI_PPM_CFG[1] 31_488 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPI_PPM_CFG[2] 30_489 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPI_PPM_CFG[3] 31_489 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPI_PPM_CFG[4] 30_490 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPI_PPM_CFG[5] 31_490 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPI_PPM_CFG[6] 30_491 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPI_PPM_CFG[7] 31_491 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPI_PPMCLK_SEL.TXUSRCLK2 31_497 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPI_SYNFREQ_PPM[0] 30_496 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPI_SYNFREQ_PPM[1] 31_496 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPI_SYNFREQ_PPM[2] 30_497 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPI_CFG0[0] 30_40 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPI_CFG0[1] 31_40 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPI_CFG1[0] 30_41 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPI_CFG1[1] 31_41 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPI_CFG2[0] 30_42 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPI_CFG2[1] 31_42 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPI_CFG3[0] 30_43 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPI_CFG4[0] 31_43 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPI_CFG5[0] 30_44 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPI_CFG5[1] 31_44 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPI_CFG5[2] 30_45 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPMARESET_TIME[0] 28_128 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPMARESET_TIME[1] 29_128 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPMARESET_TIME[2] 28_129 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPMARESET_TIME[3] 29_129 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPMARESET_TIME[4] 28_130 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXSYNC_MULTILANE[0] 29_133 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXSYNC_OVRD[0] 28_135 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXSYNC_SKIP_DA[0] 28_134 +GTP_CHANNEL_2.GTPE2_CHANNEL.UCODEER_CLR[0] 29_00 +GTP_CHANNEL_2.GTPE2_CHANNEL.USE_PCS_CLK_PHASE_SEL[0] 30_463 diff --git a/artix7/segbits_gtp_channel_2.origin_info.db b/artix7/segbits_gtp_channel_2.origin_info.db index 2822929..2dee1fd 100644 --- a/artix7/segbits_gtp_channel_2.origin_info.db +++ b/artix7/segbits_gtp_channel_2.origin_info.db @@ -1,1627 +1,1627 @@ -GTP_CHANNEL_2.GTPE2.ACJTAG_DEBUG_MODE[0] origin:064-gtp-channel-conf 28_07 -GTP_CHANNEL_2.GTPE2.ACJTAG_MODE[0] origin:064-gtp-channel-conf 29_06 -GTP_CHANNEL_2.GTPE2.ACJTAG_RESET[0] origin:064-gtp-channel-conf 29_07 -GTP_CHANNEL_2.GTPE2.ADAPT_CFG0[0] origin:064-gtp-channel-conf 30_464 -GTP_CHANNEL_2.GTPE2.ADAPT_CFG0[1] origin:064-gtp-channel-conf 31_464 -GTP_CHANNEL_2.GTPE2.ADAPT_CFG0[2] origin:064-gtp-channel-conf 30_465 -GTP_CHANNEL_2.GTPE2.ADAPT_CFG0[3] origin:064-gtp-channel-conf 31_465 -GTP_CHANNEL_2.GTPE2.ADAPT_CFG0[4] origin:064-gtp-channel-conf 30_466 -GTP_CHANNEL_2.GTPE2.ADAPT_CFG0[5] origin:064-gtp-channel-conf 31_466 -GTP_CHANNEL_2.GTPE2.ADAPT_CFG0[6] origin:064-gtp-channel-conf 30_467 -GTP_CHANNEL_2.GTPE2.ADAPT_CFG0[7] origin:064-gtp-channel-conf 31_467 -GTP_CHANNEL_2.GTPE2.ADAPT_CFG0[8] origin:064-gtp-channel-conf 30_468 -GTP_CHANNEL_2.GTPE2.ADAPT_CFG0[9] origin:064-gtp-channel-conf 31_468 -GTP_CHANNEL_2.GTPE2.ADAPT_CFG0[10] origin:064-gtp-channel-conf 30_469 -GTP_CHANNEL_2.GTPE2.ADAPT_CFG0[11] origin:064-gtp-channel-conf 31_469 -GTP_CHANNEL_2.GTPE2.ADAPT_CFG0[12] origin:064-gtp-channel-conf 30_470 -GTP_CHANNEL_2.GTPE2.ADAPT_CFG0[13] origin:064-gtp-channel-conf 31_470 -GTP_CHANNEL_2.GTPE2.ADAPT_CFG0[14] origin:064-gtp-channel-conf 30_471 -GTP_CHANNEL_2.GTPE2.ADAPT_CFG0[15] origin:064-gtp-channel-conf 31_471 -GTP_CHANNEL_2.GTPE2.ADAPT_CFG0[16] origin:064-gtp-channel-conf 30_472 -GTP_CHANNEL_2.GTPE2.ADAPT_CFG0[17] origin:064-gtp-channel-conf 31_472 -GTP_CHANNEL_2.GTPE2.ADAPT_CFG0[18] origin:064-gtp-channel-conf 30_473 -GTP_CHANNEL_2.GTPE2.ADAPT_CFG0[19] origin:064-gtp-channel-conf 31_473 -GTP_CHANNEL_2.GTPE2.ALIGN_COMMA_DOUBLE origin:064-gtp-channel-conf 28_522 -GTP_CHANNEL_2.GTPE2.ALIGN_COMMA_ENABLE[0] origin:064-gtp-channel-conf 28_496 -GTP_CHANNEL_2.GTPE2.ALIGN_COMMA_ENABLE[1] origin:064-gtp-channel-conf 29_496 -GTP_CHANNEL_2.GTPE2.ALIGN_COMMA_ENABLE[2] origin:064-gtp-channel-conf 28_497 -GTP_CHANNEL_2.GTPE2.ALIGN_COMMA_ENABLE[3] origin:064-gtp-channel-conf 29_497 -GTP_CHANNEL_2.GTPE2.ALIGN_COMMA_ENABLE[4] origin:064-gtp-channel-conf 28_498 -GTP_CHANNEL_2.GTPE2.ALIGN_COMMA_ENABLE[5] origin:064-gtp-channel-conf 29_498 -GTP_CHANNEL_2.GTPE2.ALIGN_COMMA_ENABLE[6] origin:064-gtp-channel-conf 28_499 -GTP_CHANNEL_2.GTPE2.ALIGN_COMMA_ENABLE[7] origin:064-gtp-channel-conf 29_499 -GTP_CHANNEL_2.GTPE2.ALIGN_COMMA_ENABLE[8] origin:064-gtp-channel-conf 28_500 -GTP_CHANNEL_2.GTPE2.ALIGN_COMMA_ENABLE[9] origin:064-gtp-channel-conf 29_500 -GTP_CHANNEL_2.GTPE2.ALIGN_COMMA_WORD[0] origin:064-gtp-channel-conf 29_526 -GTP_CHANNEL_2.GTPE2.ALIGN_COMMA_WORD[1] origin:064-gtp-channel-conf 28_527 -GTP_CHANNEL_2.GTPE2.ALIGN_MCOMMA_DET origin:064-gtp-channel-conf 28_523 -GTP_CHANNEL_2.GTPE2.ALIGN_MCOMMA_VALUE[0] origin:064-gtp-channel-conf 28_504 -GTP_CHANNEL_2.GTPE2.ALIGN_MCOMMA_VALUE[1] origin:064-gtp-channel-conf 29_504 -GTP_CHANNEL_2.GTPE2.ALIGN_MCOMMA_VALUE[2] origin:064-gtp-channel-conf 28_505 -GTP_CHANNEL_2.GTPE2.ALIGN_MCOMMA_VALUE[3] origin:064-gtp-channel-conf 29_505 -GTP_CHANNEL_2.GTPE2.ALIGN_MCOMMA_VALUE[4] origin:064-gtp-channel-conf 28_506 -GTP_CHANNEL_2.GTPE2.ALIGN_MCOMMA_VALUE[5] origin:064-gtp-channel-conf 29_506 -GTP_CHANNEL_2.GTPE2.ALIGN_MCOMMA_VALUE[6] origin:064-gtp-channel-conf 28_507 -GTP_CHANNEL_2.GTPE2.ALIGN_MCOMMA_VALUE[7] origin:064-gtp-channel-conf 29_507 -GTP_CHANNEL_2.GTPE2.ALIGN_MCOMMA_VALUE[8] origin:064-gtp-channel-conf 28_508 -GTP_CHANNEL_2.GTPE2.ALIGN_MCOMMA_VALUE[9] origin:064-gtp-channel-conf 29_508 -GTP_CHANNEL_2.GTPE2.ALIGN_PCOMMA_DET origin:064-gtp-channel-conf 29_523 -GTP_CHANNEL_2.GTPE2.ALIGN_PCOMMA_VALUE[0] origin:064-gtp-channel-conf 28_512 -GTP_CHANNEL_2.GTPE2.ALIGN_PCOMMA_VALUE[1] origin:064-gtp-channel-conf 29_512 -GTP_CHANNEL_2.GTPE2.ALIGN_PCOMMA_VALUE[2] origin:064-gtp-channel-conf 28_513 -GTP_CHANNEL_2.GTPE2.ALIGN_PCOMMA_VALUE[3] origin:064-gtp-channel-conf 29_513 -GTP_CHANNEL_2.GTPE2.ALIGN_PCOMMA_VALUE[4] origin:064-gtp-channel-conf 28_514 -GTP_CHANNEL_2.GTPE2.ALIGN_PCOMMA_VALUE[5] origin:064-gtp-channel-conf 29_514 -GTP_CHANNEL_2.GTPE2.ALIGN_PCOMMA_VALUE[6] origin:064-gtp-channel-conf 28_515 -GTP_CHANNEL_2.GTPE2.ALIGN_PCOMMA_VALUE[7] origin:064-gtp-channel-conf 29_515 -GTP_CHANNEL_2.GTPE2.ALIGN_PCOMMA_VALUE[8] origin:064-gtp-channel-conf 28_516 -GTP_CHANNEL_2.GTPE2.ALIGN_PCOMMA_VALUE[9] origin:064-gtp-channel-conf 29_516 -GTP_CHANNEL_2.GTPE2.CBCC_DATA_SOURCE_SEL.DECODED origin:064-gtp-channel-conf 29_661 -GTP_CHANNEL_2.GTPE2.CFOK_CFG[0] origin:064-gtp-channel-conf 30_392 -GTP_CHANNEL_2.GTPE2.CFOK_CFG[1] origin:064-gtp-channel-conf 31_392 -GTP_CHANNEL_2.GTPE2.CFOK_CFG[2] origin:064-gtp-channel-conf 30_393 -GTP_CHANNEL_2.GTPE2.CFOK_CFG[3] origin:064-gtp-channel-conf 31_393 -GTP_CHANNEL_2.GTPE2.CFOK_CFG[4] origin:064-gtp-channel-conf 30_394 -GTP_CHANNEL_2.GTPE2.CFOK_CFG[5] origin:064-gtp-channel-conf 31_394 -GTP_CHANNEL_2.GTPE2.CFOK_CFG[6] origin:064-gtp-channel-conf 30_395 -GTP_CHANNEL_2.GTPE2.CFOK_CFG[7] origin:064-gtp-channel-conf 31_395 -GTP_CHANNEL_2.GTPE2.CFOK_CFG[8] origin:064-gtp-channel-conf 30_396 -GTP_CHANNEL_2.GTPE2.CFOK_CFG[9] origin:064-gtp-channel-conf 31_396 -GTP_CHANNEL_2.GTPE2.CFOK_CFG[10] origin:064-gtp-channel-conf 30_397 -GTP_CHANNEL_2.GTPE2.CFOK_CFG[11] origin:064-gtp-channel-conf 31_397 -GTP_CHANNEL_2.GTPE2.CFOK_CFG[12] origin:064-gtp-channel-conf 30_398 -GTP_CHANNEL_2.GTPE2.CFOK_CFG[13] origin:064-gtp-channel-conf 31_398 -GTP_CHANNEL_2.GTPE2.CFOK_CFG[14] origin:064-gtp-channel-conf 30_399 -GTP_CHANNEL_2.GTPE2.CFOK_CFG[15] origin:064-gtp-channel-conf 31_399 -GTP_CHANNEL_2.GTPE2.CFOK_CFG[16] origin:064-gtp-channel-conf 30_400 -GTP_CHANNEL_2.GTPE2.CFOK_CFG[17] origin:064-gtp-channel-conf 31_400 -GTP_CHANNEL_2.GTPE2.CFOK_CFG[18] origin:064-gtp-channel-conf 30_401 -GTP_CHANNEL_2.GTPE2.CFOK_CFG[19] origin:064-gtp-channel-conf 31_401 -GTP_CHANNEL_2.GTPE2.CFOK_CFG[20] origin:064-gtp-channel-conf 30_402 -GTP_CHANNEL_2.GTPE2.CFOK_CFG[21] origin:064-gtp-channel-conf 31_402 -GTP_CHANNEL_2.GTPE2.CFOK_CFG[22] origin:064-gtp-channel-conf 30_403 -GTP_CHANNEL_2.GTPE2.CFOK_CFG[23] origin:064-gtp-channel-conf 31_403 -GTP_CHANNEL_2.GTPE2.CFOK_CFG[24] origin:064-gtp-channel-conf 30_404 -GTP_CHANNEL_2.GTPE2.CFOK_CFG[25] origin:064-gtp-channel-conf 31_404 -GTP_CHANNEL_2.GTPE2.CFOK_CFG[26] origin:064-gtp-channel-conf 30_405 -GTP_CHANNEL_2.GTPE2.CFOK_CFG[27] origin:064-gtp-channel-conf 31_405 -GTP_CHANNEL_2.GTPE2.CFOK_CFG[28] origin:064-gtp-channel-conf 30_406 -GTP_CHANNEL_2.GTPE2.CFOK_CFG[29] origin:064-gtp-channel-conf 31_406 -GTP_CHANNEL_2.GTPE2.CFOK_CFG[30] origin:064-gtp-channel-conf 30_407 -GTP_CHANNEL_2.GTPE2.CFOK_CFG[31] origin:064-gtp-channel-conf 31_407 -GTP_CHANNEL_2.GTPE2.CFOK_CFG[32] origin:064-gtp-channel-conf 30_408 -GTP_CHANNEL_2.GTPE2.CFOK_CFG[33] origin:064-gtp-channel-conf 31_408 -GTP_CHANNEL_2.GTPE2.CFOK_CFG[34] origin:064-gtp-channel-conf 30_409 -GTP_CHANNEL_2.GTPE2.CFOK_CFG[35] origin:064-gtp-channel-conf 31_409 -GTP_CHANNEL_2.GTPE2.CFOK_CFG[36] origin:064-gtp-channel-conf 30_410 -GTP_CHANNEL_2.GTPE2.CFOK_CFG[37] origin:064-gtp-channel-conf 31_410 -GTP_CHANNEL_2.GTPE2.CFOK_CFG[38] origin:064-gtp-channel-conf 30_411 -GTP_CHANNEL_2.GTPE2.CFOK_CFG[39] origin:064-gtp-channel-conf 31_411 -GTP_CHANNEL_2.GTPE2.CFOK_CFG[40] origin:064-gtp-channel-conf 30_412 -GTP_CHANNEL_2.GTPE2.CFOK_CFG[41] origin:064-gtp-channel-conf 31_412 -GTP_CHANNEL_2.GTPE2.CFOK_CFG[42] origin:064-gtp-channel-conf 30_413 -GTP_CHANNEL_2.GTPE2.CFOK_CFG2[0] origin:064-gtp-channel-conf 30_459 -GTP_CHANNEL_2.GTPE2.CFOK_CFG2[1] origin:064-gtp-channel-conf 31_459 -GTP_CHANNEL_2.GTPE2.CFOK_CFG2[2] origin:064-gtp-channel-conf 30_460 -GTP_CHANNEL_2.GTPE2.CFOK_CFG2[3] origin:064-gtp-channel-conf 31_460 -GTP_CHANNEL_2.GTPE2.CFOK_CFG2[4] origin:064-gtp-channel-conf 30_461 -GTP_CHANNEL_2.GTPE2.CFOK_CFG2[5] origin:064-gtp-channel-conf 31_461 -GTP_CHANNEL_2.GTPE2.CFOK_CFG2[6] origin:064-gtp-channel-conf 30_462 -GTP_CHANNEL_2.GTPE2.CFOK_CFG3[0] origin:064-gtp-channel-conf 30_416 -GTP_CHANNEL_2.GTPE2.CFOK_CFG3[1] origin:064-gtp-channel-conf 31_416 -GTP_CHANNEL_2.GTPE2.CFOK_CFG3[2] origin:064-gtp-channel-conf 30_417 -GTP_CHANNEL_2.GTPE2.CFOK_CFG3[3] origin:064-gtp-channel-conf 31_417 -GTP_CHANNEL_2.GTPE2.CFOK_CFG3[4] origin:064-gtp-channel-conf 30_418 -GTP_CHANNEL_2.GTPE2.CFOK_CFG3[5] origin:064-gtp-channel-conf 31_418 -GTP_CHANNEL_2.GTPE2.CFOK_CFG3[6] origin:064-gtp-channel-conf 30_419 -GTP_CHANNEL_2.GTPE2.CFOK_CFG4[0] origin:064-gtp-channel-conf 31_438 -GTP_CHANNEL_2.GTPE2.CFOK_CFG5[0] origin:064-gtp-channel-conf 30_429 -GTP_CHANNEL_2.GTPE2.CFOK_CFG5[1] origin:064-gtp-channel-conf 31_429 -GTP_CHANNEL_2.GTPE2.CFOK_CFG6[0] origin:064-gtp-channel-conf 31_436 -GTP_CHANNEL_2.GTPE2.CFOK_CFG6[1] origin:064-gtp-channel-conf 30_437 -GTP_CHANNEL_2.GTPE2.CFOK_CFG6[2] origin:064-gtp-channel-conf 31_437 -GTP_CHANNEL_2.GTPE2.CFOK_CFG6[3] origin:064-gtp-channel-conf 30_438 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_KEEP_ALIGN origin:064-gtp-channel-conf 29_631 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_MAX_SKEW[0] origin:064-gtp-channel-conf 28_670 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_MAX_SKEW[1] origin:064-gtp-channel-conf 29_670 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_MAX_SKEW[2] origin:064-gtp-channel-conf 28_671 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_MAX_SKEW[3] origin:064-gtp-channel-conf 29_671 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_1_1[0] origin:064-gtp-channel-conf 28_608 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_1_1[1] origin:064-gtp-channel-conf 29_608 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_1_1[2] origin:064-gtp-channel-conf 28_609 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_1_1[3] origin:064-gtp-channel-conf 29_609 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_1_1[4] origin:064-gtp-channel-conf 28_610 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_1_1[5] origin:064-gtp-channel-conf 29_610 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_1_1[6] origin:064-gtp-channel-conf 28_611 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_1_1[7] origin:064-gtp-channel-conf 29_611 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_1_1[8] origin:064-gtp-channel-conf 28_612 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_1_1[9] origin:064-gtp-channel-conf 29_612 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_1_2[0] origin:064-gtp-channel-conf 28_616 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_1_2[1] origin:064-gtp-channel-conf 29_616 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_1_2[2] origin:064-gtp-channel-conf 28_617 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_1_2[3] origin:064-gtp-channel-conf 29_617 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_1_2[4] origin:064-gtp-channel-conf 28_618 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_1_2[5] origin:064-gtp-channel-conf 29_618 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_1_2[6] origin:064-gtp-channel-conf 28_619 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_1_2[7] origin:064-gtp-channel-conf 29_619 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_1_2[8] origin:064-gtp-channel-conf 28_620 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_1_2[9] origin:064-gtp-channel-conf 29_620 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_1_3[0] origin:064-gtp-channel-conf 28_624 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_1_3[1] origin:064-gtp-channel-conf 29_624 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_1_3[2] origin:064-gtp-channel-conf 28_625 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_1_3[3] origin:064-gtp-channel-conf 29_625 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_1_3[4] origin:064-gtp-channel-conf 28_626 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_1_3[5] origin:064-gtp-channel-conf 29_626 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_1_3[6] origin:064-gtp-channel-conf 28_627 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_1_3[7] origin:064-gtp-channel-conf 29_627 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_1_3[8] origin:064-gtp-channel-conf 28_628 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_1_3[9] origin:064-gtp-channel-conf 29_628 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_1_4[0] origin:064-gtp-channel-conf 28_632 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_1_4[1] origin:064-gtp-channel-conf 29_632 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_1_4[2] origin:064-gtp-channel-conf 28_633 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_1_4[3] origin:064-gtp-channel-conf 29_633 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_1_4[4] origin:064-gtp-channel-conf 28_634 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_1_4[5] origin:064-gtp-channel-conf 29_634 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_1_4[6] origin:064-gtp-channel-conf 28_635 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_1_4[7] origin:064-gtp-channel-conf 29_635 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_1_4[8] origin:064-gtp-channel-conf 28_636 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_1_4[9] origin:064-gtp-channel-conf 29_636 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_1_ENABLE[0] origin:064-gtp-channel-conf 28_614 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_1_ENABLE[1] origin:064-gtp-channel-conf 29_614 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_1_ENABLE[2] origin:064-gtp-channel-conf 28_615 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_1_ENABLE[3] origin:064-gtp-channel-conf 29_615 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_2_1[0] origin:064-gtp-channel-conf 28_640 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_2_1[1] origin:064-gtp-channel-conf 29_640 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_2_1[2] origin:064-gtp-channel-conf 28_641 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_2_1[3] origin:064-gtp-channel-conf 29_641 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_2_1[4] origin:064-gtp-channel-conf 28_642 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_2_1[5] origin:064-gtp-channel-conf 29_642 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_2_1[6] origin:064-gtp-channel-conf 28_643 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_2_1[7] origin:064-gtp-channel-conf 29_643 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_2_1[8] origin:064-gtp-channel-conf 28_644 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_2_1[9] origin:064-gtp-channel-conf 29_644 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_2_2[0] origin:064-gtp-channel-conf 28_648 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_2_2[1] origin:064-gtp-channel-conf 29_648 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_2_2[2] origin:064-gtp-channel-conf 28_649 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_2_2[3] origin:064-gtp-channel-conf 29_649 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_2_2[4] origin:064-gtp-channel-conf 28_650 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_2_2[5] origin:064-gtp-channel-conf 29_650 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_2_2[6] origin:064-gtp-channel-conf 28_651 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_2_2[7] origin:064-gtp-channel-conf 29_651 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_2_2[8] origin:064-gtp-channel-conf 28_652 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_2_2[9] origin:064-gtp-channel-conf 29_652 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_2_3[0] origin:064-gtp-channel-conf 28_656 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_2_3[1] origin:064-gtp-channel-conf 29_656 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_2_3[2] origin:064-gtp-channel-conf 28_657 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_2_3[3] origin:064-gtp-channel-conf 29_657 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_2_3[4] origin:064-gtp-channel-conf 28_658 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_2_3[5] origin:064-gtp-channel-conf 29_658 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_2_3[6] origin:064-gtp-channel-conf 28_659 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_2_3[7] origin:064-gtp-channel-conf 29_659 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_2_3[8] origin:064-gtp-channel-conf 28_660 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_2_3[9] origin:064-gtp-channel-conf 29_660 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_2_4[0] origin:064-gtp-channel-conf 28_664 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_2_4[1] origin:064-gtp-channel-conf 29_664 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_2_4[2] origin:064-gtp-channel-conf 28_665 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_2_4[3] origin:064-gtp-channel-conf 29_665 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_2_4[4] origin:064-gtp-channel-conf 28_666 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_2_4[5] origin:064-gtp-channel-conf 29_666 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_2_4[6] origin:064-gtp-channel-conf 28_667 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_2_4[7] origin:064-gtp-channel-conf 29_667 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_2_4[8] origin:064-gtp-channel-conf 28_668 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_2_4[9] origin:064-gtp-channel-conf 29_668 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_2_ENABLE[0] origin:064-gtp-channel-conf 28_646 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_2_ENABLE[1] origin:064-gtp-channel-conf 29_646 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_2_ENABLE[2] origin:064-gtp-channel-conf 28_647 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_2_ENABLE[3] origin:064-gtp-channel-conf 29_647 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_2_USE origin:064-gtp-channel-conf 29_645 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_LEN[0] origin:064-gtp-channel-conf 28_623 -GTP_CHANNEL_2.GTPE2.CHAN_BOND_SEQ_LEN[1] origin:064-gtp-channel-conf 29_623 -GTP_CHANNEL_2.GTPE2.CLK_COMMON_SWING[0] origin:064-gtp-channel-conf 31_311 -GTP_CHANNEL_2.GTPE2.CLK_COR_KEEP_IDLE origin:064-gtp-channel-conf 28_591 -GTP_CHANNEL_2.GTPE2.CLK_COR_MAX_LAT[0] origin:064-gtp-channel-conf 28_557 -GTP_CHANNEL_2.GTPE2.CLK_COR_MAX_LAT[1] origin:064-gtp-channel-conf 29_557 -GTP_CHANNEL_2.GTPE2.CLK_COR_MAX_LAT[2] origin:064-gtp-channel-conf 28_558 -GTP_CHANNEL_2.GTPE2.CLK_COR_MAX_LAT[3] origin:064-gtp-channel-conf 29_558 -GTP_CHANNEL_2.GTPE2.CLK_COR_MAX_LAT[4] origin:064-gtp-channel-conf 28_559 -GTP_CHANNEL_2.GTPE2.CLK_COR_MAX_LAT[5] origin:064-gtp-channel-conf 29_559 -GTP_CHANNEL_2.GTPE2.CLK_COR_MIN_LAT[0] origin:064-gtp-channel-conf 28_565 -GTP_CHANNEL_2.GTPE2.CLK_COR_MIN_LAT[1] origin:064-gtp-channel-conf 29_565 -GTP_CHANNEL_2.GTPE2.CLK_COR_MIN_LAT[2] origin:064-gtp-channel-conf 28_566 -GTP_CHANNEL_2.GTPE2.CLK_COR_MIN_LAT[3] origin:064-gtp-channel-conf 29_566 -GTP_CHANNEL_2.GTPE2.CLK_COR_MIN_LAT[4] origin:064-gtp-channel-conf 28_567 -GTP_CHANNEL_2.GTPE2.CLK_COR_MIN_LAT[5] origin:064-gtp-channel-conf 29_567 -GTP_CHANNEL_2.GTPE2.CLK_COR_PRECEDENCE origin:064-gtp-channel-conf 28_590 -GTP_CHANNEL_2.GTPE2.CLK_COR_REPEAT_WAIT[0] origin:064-gtp-channel-conf 28_573 -GTP_CHANNEL_2.GTPE2.CLK_COR_REPEAT_WAIT[1] origin:064-gtp-channel-conf 29_573 -GTP_CHANNEL_2.GTPE2.CLK_COR_REPEAT_WAIT[2] origin:064-gtp-channel-conf 28_574 -GTP_CHANNEL_2.GTPE2.CLK_COR_REPEAT_WAIT[3] origin:064-gtp-channel-conf 29_574 -GTP_CHANNEL_2.GTPE2.CLK_COR_REPEAT_WAIT[4] origin:064-gtp-channel-conf 28_575 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_1_1[0] origin:064-gtp-channel-conf 28_544 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_1_1[1] origin:064-gtp-channel-conf 29_544 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_1_1[2] origin:064-gtp-channel-conf 28_545 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_1_1[3] origin:064-gtp-channel-conf 29_545 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_1_1[4] origin:064-gtp-channel-conf 28_546 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_1_1[5] origin:064-gtp-channel-conf 29_546 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_1_1[6] origin:064-gtp-channel-conf 28_547 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_1_1[7] origin:064-gtp-channel-conf 29_547 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_1_1[8] origin:064-gtp-channel-conf 28_548 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_1_1[9] origin:064-gtp-channel-conf 29_548 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_1_2[0] origin:064-gtp-channel-conf 28_552 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_1_2[1] origin:064-gtp-channel-conf 29_552 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_1_2[2] origin:064-gtp-channel-conf 28_553 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_1_2[3] origin:064-gtp-channel-conf 29_553 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_1_2[4] origin:064-gtp-channel-conf 28_554 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_1_2[5] origin:064-gtp-channel-conf 29_554 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_1_2[6] origin:064-gtp-channel-conf 28_555 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_1_2[7] origin:064-gtp-channel-conf 29_555 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_1_2[8] origin:064-gtp-channel-conf 28_556 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_1_2[9] origin:064-gtp-channel-conf 29_556 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_1_3[0] origin:064-gtp-channel-conf 28_560 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_1_3[1] origin:064-gtp-channel-conf 29_560 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_1_3[2] origin:064-gtp-channel-conf 28_561 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_1_3[3] origin:064-gtp-channel-conf 29_561 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_1_3[4] origin:064-gtp-channel-conf 28_562 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_1_3[5] origin:064-gtp-channel-conf 29_562 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_1_3[6] origin:064-gtp-channel-conf 28_563 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_1_3[7] origin:064-gtp-channel-conf 29_563 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_1_3[8] origin:064-gtp-channel-conf 28_564 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_1_3[9] origin:064-gtp-channel-conf 29_564 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_1_4[0] origin:064-gtp-channel-conf 28_568 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_1_4[1] origin:064-gtp-channel-conf 29_568 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_1_4[2] origin:064-gtp-channel-conf 28_569 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_1_4[3] origin:064-gtp-channel-conf 29_569 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_1_4[4] origin:064-gtp-channel-conf 28_570 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_1_4[5] origin:064-gtp-channel-conf 29_570 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_1_4[6] origin:064-gtp-channel-conf 28_571 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_1_4[7] origin:064-gtp-channel-conf 29_571 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_1_4[8] origin:064-gtp-channel-conf 28_572 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_1_4[9] origin:064-gtp-channel-conf 29_572 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_1_ENABLE[0] origin:064-gtp-channel-conf 28_549 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_1_ENABLE[1] origin:064-gtp-channel-conf 29_549 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_1_ENABLE[2] origin:064-gtp-channel-conf 28_550 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_1_ENABLE[3] origin:064-gtp-channel-conf 29_550 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_2_1[0] origin:064-gtp-channel-conf 28_576 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_2_1[1] origin:064-gtp-channel-conf 29_576 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_2_1[2] origin:064-gtp-channel-conf 28_577 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_2_1[3] origin:064-gtp-channel-conf 29_577 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_2_1[4] origin:064-gtp-channel-conf 28_578 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_2_1[5] origin:064-gtp-channel-conf 29_578 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_2_1[6] origin:064-gtp-channel-conf 28_579 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_2_1[7] origin:064-gtp-channel-conf 29_579 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_2_1[8] origin:064-gtp-channel-conf 28_580 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_2_1[9] origin:064-gtp-channel-conf 29_580 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_2_2[0] origin:064-gtp-channel-conf 28_584 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_2_2[1] origin:064-gtp-channel-conf 29_584 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_2_2[2] origin:064-gtp-channel-conf 28_585 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_2_2[3] origin:064-gtp-channel-conf 29_585 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_2_2[4] origin:064-gtp-channel-conf 28_586 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_2_2[5] origin:064-gtp-channel-conf 29_586 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_2_2[6] origin:064-gtp-channel-conf 28_587 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_2_2[7] origin:064-gtp-channel-conf 29_587 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_2_2[8] origin:064-gtp-channel-conf 28_588 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_2_2[9] origin:064-gtp-channel-conf 29_588 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_2_3[0] origin:064-gtp-channel-conf 28_592 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_2_3[1] origin:064-gtp-channel-conf 29_592 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_2_3[2] origin:064-gtp-channel-conf 28_593 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_2_3[3] origin:064-gtp-channel-conf 29_593 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_2_3[4] origin:064-gtp-channel-conf 28_594 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_2_3[5] origin:064-gtp-channel-conf 29_594 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_2_3[6] origin:064-gtp-channel-conf 28_595 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_2_3[7] origin:064-gtp-channel-conf 29_595 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_2_3[8] origin:064-gtp-channel-conf 28_596 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_2_3[9] origin:064-gtp-channel-conf 29_596 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_2_4[0] origin:064-gtp-channel-conf 28_600 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_2_4[1] origin:064-gtp-channel-conf 29_600 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_2_4[2] origin:064-gtp-channel-conf 28_601 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_2_4[3] origin:064-gtp-channel-conf 29_601 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_2_4[4] origin:064-gtp-channel-conf 28_602 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_2_4[5] origin:064-gtp-channel-conf 29_602 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_2_4[6] origin:064-gtp-channel-conf 28_603 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_2_4[7] origin:064-gtp-channel-conf 29_603 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_2_4[8] origin:064-gtp-channel-conf 28_604 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_2_4[9] origin:064-gtp-channel-conf 29_604 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_2_ENABLE[0] origin:064-gtp-channel-conf 28_581 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_2_ENABLE[1] origin:064-gtp-channel-conf 29_581 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_2_ENABLE[2] origin:064-gtp-channel-conf 28_582 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_2_ENABLE[3] origin:064-gtp-channel-conf 29_582 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_2_USE origin:064-gtp-channel-conf 28_583 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_LEN[0] origin:064-gtp-channel-conf 28_589 -GTP_CHANNEL_2.GTPE2.CLK_COR_SEQ_LEN[1] origin:064-gtp-channel-conf 29_589 -GTP_CHANNEL_2.GTPE2.CLK_CORRECT_USE origin:064-gtp-channel-conf 28_551 -GTP_CHANNEL_2.GTPE2.DEC_MCOMMA_DETECT origin:064-gtp-channel-conf 29_494 -GTP_CHANNEL_2.GTPE2.DEC_PCOMMA_DETECT origin:064-gtp-channel-conf 28_495 -GTP_CHANNEL_2.GTPE2.DEC_VALID_COMMA_ONLY origin:064-gtp-channel-conf 28_494 -GTP_CHANNEL_2.GTPE2.DMONITOR_CFG[0] origin:064-gtp-channel-conf 30_368 -GTP_CHANNEL_2.GTPE2.DMONITOR_CFG[1] origin:064-gtp-channel-conf 31_368 -GTP_CHANNEL_2.GTPE2.DMONITOR_CFG[2] origin:064-gtp-channel-conf 30_369 -GTP_CHANNEL_2.GTPE2.DMONITOR_CFG[3] origin:064-gtp-channel-conf 31_369 -GTP_CHANNEL_2.GTPE2.DMONITOR_CFG[4] origin:064-gtp-channel-conf 30_370 -GTP_CHANNEL_2.GTPE2.DMONITOR_CFG[5] origin:064-gtp-channel-conf 31_370 -GTP_CHANNEL_2.GTPE2.DMONITOR_CFG[6] origin:064-gtp-channel-conf 30_371 -GTP_CHANNEL_2.GTPE2.DMONITOR_CFG[7] origin:064-gtp-channel-conf 31_371 -GTP_CHANNEL_2.GTPE2.DMONITOR_CFG[8] origin:064-gtp-channel-conf 30_372 -GTP_CHANNEL_2.GTPE2.DMONITOR_CFG[9] origin:064-gtp-channel-conf 31_372 -GTP_CHANNEL_2.GTPE2.DMONITOR_CFG[10] origin:064-gtp-channel-conf 30_373 -GTP_CHANNEL_2.GTPE2.DMONITOR_CFG[11] origin:064-gtp-channel-conf 31_373 -GTP_CHANNEL_2.GTPE2.DMONITOR_CFG[12] origin:064-gtp-channel-conf 30_374 -GTP_CHANNEL_2.GTPE2.DMONITOR_CFG[13] origin:064-gtp-channel-conf 31_374 -GTP_CHANNEL_2.GTPE2.DMONITOR_CFG[14] origin:064-gtp-channel-conf 30_375 -GTP_CHANNEL_2.GTPE2.DMONITOR_CFG[15] origin:064-gtp-channel-conf 31_375 -GTP_CHANNEL_2.GTPE2.DMONITOR_CFG[16] origin:064-gtp-channel-conf 30_376 -GTP_CHANNEL_2.GTPE2.DMONITOR_CFG[17] origin:064-gtp-channel-conf 31_376 -GTP_CHANNEL_2.GTPE2.DMONITOR_CFG[18] origin:064-gtp-channel-conf 30_377 -GTP_CHANNEL_2.GTPE2.DMONITOR_CFG[19] origin:064-gtp-channel-conf 31_377 -GTP_CHANNEL_2.GTPE2.DMONITOR_CFG[20] origin:064-gtp-channel-conf 30_378 -GTP_CHANNEL_2.GTPE2.DMONITOR_CFG[21] origin:064-gtp-channel-conf 31_378 -GTP_CHANNEL_2.GTPE2.DMONITOR_CFG[22] origin:064-gtp-channel-conf 30_379 -GTP_CHANNEL_2.GTPE2.DMONITOR_CFG[23] origin:064-gtp-channel-conf 31_379 -GTP_CHANNEL_2.GTPE2.ES_CLK_PHASE_SEL[0] origin:064-gtp-channel-conf 31_463 -GTP_CHANNEL_2.GTPE2.ES_CONTROL[0] origin:064-gtp-channel-conf 28_488 -GTP_CHANNEL_2.GTPE2.ES_CONTROL[1] origin:064-gtp-channel-conf 29_488 -GTP_CHANNEL_2.GTPE2.ES_CONTROL[2] origin:064-gtp-channel-conf 28_489 -GTP_CHANNEL_2.GTPE2.ES_CONTROL[3] origin:064-gtp-channel-conf 29_489 -GTP_CHANNEL_2.GTPE2.ES_CONTROL[4] origin:064-gtp-channel-conf 28_490 -GTP_CHANNEL_2.GTPE2.ES_CONTROL[5] origin:064-gtp-channel-conf 29_490 -GTP_CHANNEL_2.GTPE2.ES_ERRDET_EN origin:064-gtp-channel-conf 29_492 -GTP_CHANNEL_2.GTPE2.ES_EYE_SCAN_EN origin:064-gtp-channel-conf 28_492 -GTP_CHANNEL_2.GTPE2.ES_HORZ_OFFSET[0] origin:064-gtp-channel-conf 28_480 -GTP_CHANNEL_2.GTPE2.ES_HORZ_OFFSET[1] origin:064-gtp-channel-conf 29_480 -GTP_CHANNEL_2.GTPE2.ES_HORZ_OFFSET[2] origin:064-gtp-channel-conf 28_481 -GTP_CHANNEL_2.GTPE2.ES_HORZ_OFFSET[3] origin:064-gtp-channel-conf 29_481 -GTP_CHANNEL_2.GTPE2.ES_HORZ_OFFSET[4] origin:064-gtp-channel-conf 28_482 -GTP_CHANNEL_2.GTPE2.ES_HORZ_OFFSET[5] origin:064-gtp-channel-conf 29_482 -GTP_CHANNEL_2.GTPE2.ES_HORZ_OFFSET[6] origin:064-gtp-channel-conf 28_483 -GTP_CHANNEL_2.GTPE2.ES_HORZ_OFFSET[7] origin:064-gtp-channel-conf 29_483 -GTP_CHANNEL_2.GTPE2.ES_HORZ_OFFSET[8] origin:064-gtp-channel-conf 28_484 -GTP_CHANNEL_2.GTPE2.ES_HORZ_OFFSET[9] origin:064-gtp-channel-conf 29_484 -GTP_CHANNEL_2.GTPE2.ES_HORZ_OFFSET[10] origin:064-gtp-channel-conf 28_485 -GTP_CHANNEL_2.GTPE2.ES_HORZ_OFFSET[11] origin:064-gtp-channel-conf 29_485 -GTP_CHANNEL_2.GTPE2.ES_PMA_CFG[0] origin:064-gtp-channel-conf 30_624 -GTP_CHANNEL_2.GTPE2.ES_PMA_CFG[1] origin:064-gtp-channel-conf 31_624 -GTP_CHANNEL_2.GTPE2.ES_PMA_CFG[2] origin:064-gtp-channel-conf 30_625 -GTP_CHANNEL_2.GTPE2.ES_PMA_CFG[3] origin:064-gtp-channel-conf 31_625 -GTP_CHANNEL_2.GTPE2.ES_PMA_CFG[4] origin:064-gtp-channel-conf 30_626 -GTP_CHANNEL_2.GTPE2.ES_PMA_CFG[5] origin:064-gtp-channel-conf 31_626 -GTP_CHANNEL_2.GTPE2.ES_PMA_CFG[6] origin:064-gtp-channel-conf 30_627 -GTP_CHANNEL_2.GTPE2.ES_PMA_CFG[7] origin:064-gtp-channel-conf 31_627 -GTP_CHANNEL_2.GTPE2.ES_PMA_CFG[8] origin:064-gtp-channel-conf 30_628 -GTP_CHANNEL_2.GTPE2.ES_PMA_CFG[9] origin:064-gtp-channel-conf 31_628 -GTP_CHANNEL_2.GTPE2.ES_PRESCALE[0] origin:064-gtp-channel-conf 29_477 -GTP_CHANNEL_2.GTPE2.ES_PRESCALE[1] origin:064-gtp-channel-conf 28_478 -GTP_CHANNEL_2.GTPE2.ES_PRESCALE[2] origin:064-gtp-channel-conf 29_478 -GTP_CHANNEL_2.GTPE2.ES_PRESCALE[3] origin:064-gtp-channel-conf 28_479 -GTP_CHANNEL_2.GTPE2.ES_PRESCALE[4] origin:064-gtp-channel-conf 29_479 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[0] origin:064-gtp-channel-conf 28_392 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[1] origin:064-gtp-channel-conf 29_392 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[2] origin:064-gtp-channel-conf 28_393 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[3] origin:064-gtp-channel-conf 29_393 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[4] origin:064-gtp-channel-conf 28_394 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[5] origin:064-gtp-channel-conf 29_394 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[6] origin:064-gtp-channel-conf 28_395 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[7] origin:064-gtp-channel-conf 29_395 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[8] origin:064-gtp-channel-conf 28_396 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[9] origin:064-gtp-channel-conf 29_396 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[10] origin:064-gtp-channel-conf 28_397 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[11] origin:064-gtp-channel-conf 29_397 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[12] origin:064-gtp-channel-conf 28_398 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[13] origin:064-gtp-channel-conf 29_398 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[14] origin:064-gtp-channel-conf 28_399 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[15] origin:064-gtp-channel-conf 29_399 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[16] origin:064-gtp-channel-conf 28_400 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[17] origin:064-gtp-channel-conf 29_400 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[18] origin:064-gtp-channel-conf 28_401 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[19] origin:064-gtp-channel-conf 29_401 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[20] origin:064-gtp-channel-conf 28_402 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[21] origin:064-gtp-channel-conf 29_402 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[22] origin:064-gtp-channel-conf 28_403 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[23] origin:064-gtp-channel-conf 29_403 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[24] origin:064-gtp-channel-conf 28_404 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[25] origin:064-gtp-channel-conf 29_404 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[26] origin:064-gtp-channel-conf 28_405 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[27] origin:064-gtp-channel-conf 29_405 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[28] origin:064-gtp-channel-conf 28_406 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[29] origin:064-gtp-channel-conf 29_406 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[30] origin:064-gtp-channel-conf 28_407 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[31] origin:064-gtp-channel-conf 29_407 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[32] origin:064-gtp-channel-conf 28_408 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[33] origin:064-gtp-channel-conf 29_408 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[34] origin:064-gtp-channel-conf 28_409 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[35] origin:064-gtp-channel-conf 29_409 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[36] origin:064-gtp-channel-conf 28_410 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[37] origin:064-gtp-channel-conf 29_410 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[38] origin:064-gtp-channel-conf 28_411 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[39] origin:064-gtp-channel-conf 29_411 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[40] origin:064-gtp-channel-conf 28_412 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[41] origin:064-gtp-channel-conf 29_412 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[42] origin:064-gtp-channel-conf 28_413 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[43] origin:064-gtp-channel-conf 29_413 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[44] origin:064-gtp-channel-conf 28_414 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[45] origin:064-gtp-channel-conf 29_414 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[46] origin:064-gtp-channel-conf 28_415 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[47] origin:064-gtp-channel-conf 29_415 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[48] origin:064-gtp-channel-conf 28_416 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[49] origin:064-gtp-channel-conf 29_416 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[50] origin:064-gtp-channel-conf 28_417 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[51] origin:064-gtp-channel-conf 29_417 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[52] origin:064-gtp-channel-conf 28_418 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[53] origin:064-gtp-channel-conf 29_418 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[54] origin:064-gtp-channel-conf 28_419 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[55] origin:064-gtp-channel-conf 29_419 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[56] origin:064-gtp-channel-conf 28_420 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[57] origin:064-gtp-channel-conf 29_420 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[58] origin:064-gtp-channel-conf 28_421 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[59] origin:064-gtp-channel-conf 29_421 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[60] origin:064-gtp-channel-conf 28_422 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[61] origin:064-gtp-channel-conf 29_422 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[62] origin:064-gtp-channel-conf 28_423 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[63] origin:064-gtp-channel-conf 29_423 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[64] origin:064-gtp-channel-conf 28_424 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[65] origin:064-gtp-channel-conf 29_424 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[66] origin:064-gtp-channel-conf 28_425 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[67] origin:064-gtp-channel-conf 29_425 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[68] origin:064-gtp-channel-conf 28_426 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[69] origin:064-gtp-channel-conf 29_426 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[70] origin:064-gtp-channel-conf 28_427 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[71] origin:064-gtp-channel-conf 29_427 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[72] origin:064-gtp-channel-conf 28_428 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[73] origin:064-gtp-channel-conf 29_428 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[74] origin:064-gtp-channel-conf 28_429 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[75] origin:064-gtp-channel-conf 29_429 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[76] origin:064-gtp-channel-conf 28_430 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[77] origin:064-gtp-channel-conf 29_430 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[78] origin:064-gtp-channel-conf 28_431 -GTP_CHANNEL_2.GTPE2.ES_QUAL_MASK[79] origin:064-gtp-channel-conf 29_431 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[0] origin:064-gtp-channel-conf 28_352 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[1] origin:064-gtp-channel-conf 29_352 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[2] origin:064-gtp-channel-conf 28_353 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[3] origin:064-gtp-channel-conf 29_353 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[4] origin:064-gtp-channel-conf 28_354 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[5] origin:064-gtp-channel-conf 29_354 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[6] origin:064-gtp-channel-conf 28_355 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[7] origin:064-gtp-channel-conf 29_355 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[8] origin:064-gtp-channel-conf 28_356 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[9] origin:064-gtp-channel-conf 29_356 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[10] origin:064-gtp-channel-conf 28_357 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[11] origin:064-gtp-channel-conf 29_357 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[12] origin:064-gtp-channel-conf 28_358 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[13] origin:064-gtp-channel-conf 29_358 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[14] origin:064-gtp-channel-conf 28_359 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[15] origin:064-gtp-channel-conf 29_359 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[16] origin:064-gtp-channel-conf 28_360 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[17] origin:064-gtp-channel-conf 29_360 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[18] origin:064-gtp-channel-conf 28_361 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[19] origin:064-gtp-channel-conf 29_361 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[20] origin:064-gtp-channel-conf 28_362 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[21] origin:064-gtp-channel-conf 29_362 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[22] origin:064-gtp-channel-conf 28_363 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[23] origin:064-gtp-channel-conf 29_363 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[24] origin:064-gtp-channel-conf 28_364 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[25] origin:064-gtp-channel-conf 29_364 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[26] origin:064-gtp-channel-conf 28_365 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[27] origin:064-gtp-channel-conf 29_365 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[28] origin:064-gtp-channel-conf 28_366 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[29] origin:064-gtp-channel-conf 29_366 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[30] origin:064-gtp-channel-conf 28_367 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[31] origin:064-gtp-channel-conf 29_367 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[32] origin:064-gtp-channel-conf 28_368 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[33] origin:064-gtp-channel-conf 29_368 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[34] origin:064-gtp-channel-conf 28_369 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[35] origin:064-gtp-channel-conf 29_369 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[36] origin:064-gtp-channel-conf 28_370 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[37] origin:064-gtp-channel-conf 29_370 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[38] origin:064-gtp-channel-conf 28_371 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[39] origin:064-gtp-channel-conf 29_371 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[40] origin:064-gtp-channel-conf 28_372 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[41] origin:064-gtp-channel-conf 29_372 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[42] origin:064-gtp-channel-conf 28_373 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[43] origin:064-gtp-channel-conf 29_373 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[44] origin:064-gtp-channel-conf 28_374 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[45] origin:064-gtp-channel-conf 29_374 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[46] origin:064-gtp-channel-conf 28_375 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[47] origin:064-gtp-channel-conf 29_375 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[48] origin:064-gtp-channel-conf 28_376 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[49] origin:064-gtp-channel-conf 29_376 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[50] origin:064-gtp-channel-conf 28_377 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[51] origin:064-gtp-channel-conf 29_377 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[52] origin:064-gtp-channel-conf 28_378 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[53] origin:064-gtp-channel-conf 29_378 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[54] origin:064-gtp-channel-conf 28_379 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[55] origin:064-gtp-channel-conf 29_379 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[56] origin:064-gtp-channel-conf 28_380 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[57] origin:064-gtp-channel-conf 29_380 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[58] origin:064-gtp-channel-conf 28_381 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[59] origin:064-gtp-channel-conf 29_381 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[60] origin:064-gtp-channel-conf 28_382 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[61] origin:064-gtp-channel-conf 29_382 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[62] origin:064-gtp-channel-conf 28_383 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[63] origin:064-gtp-channel-conf 29_383 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[64] origin:064-gtp-channel-conf 28_384 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[65] origin:064-gtp-channel-conf 29_384 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[66] origin:064-gtp-channel-conf 28_385 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[67] origin:064-gtp-channel-conf 29_385 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[68] origin:064-gtp-channel-conf 28_386 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[69] origin:064-gtp-channel-conf 29_386 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[70] origin:064-gtp-channel-conf 28_387 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[71] origin:064-gtp-channel-conf 29_387 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[72] origin:064-gtp-channel-conf 28_388 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[73] origin:064-gtp-channel-conf 29_388 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[74] origin:064-gtp-channel-conf 28_389 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[75] origin:064-gtp-channel-conf 29_389 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[76] origin:064-gtp-channel-conf 28_390 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[77] origin:064-gtp-channel-conf 29_390 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[78] origin:064-gtp-channel-conf 28_391 -GTP_CHANNEL_2.GTPE2.ES_QUALIFIER[79] origin:064-gtp-channel-conf 29_391 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[0] origin:064-gtp-channel-conf 28_432 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[1] origin:064-gtp-channel-conf 29_432 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[2] origin:064-gtp-channel-conf 28_433 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[3] origin:064-gtp-channel-conf 29_433 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[4] origin:064-gtp-channel-conf 28_434 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[5] origin:064-gtp-channel-conf 29_434 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[6] origin:064-gtp-channel-conf 28_435 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[7] origin:064-gtp-channel-conf 29_435 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[8] origin:064-gtp-channel-conf 28_436 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[9] origin:064-gtp-channel-conf 29_436 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[10] origin:064-gtp-channel-conf 28_437 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[11] origin:064-gtp-channel-conf 29_437 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[12] origin:064-gtp-channel-conf 28_438 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[13] origin:064-gtp-channel-conf 29_438 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[14] origin:064-gtp-channel-conf 28_439 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[15] origin:064-gtp-channel-conf 29_439 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[16] origin:064-gtp-channel-conf 28_440 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[17] origin:064-gtp-channel-conf 29_440 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[18] origin:064-gtp-channel-conf 28_441 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[19] origin:064-gtp-channel-conf 29_441 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[20] origin:064-gtp-channel-conf 28_442 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[21] origin:064-gtp-channel-conf 29_442 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[22] origin:064-gtp-channel-conf 28_443 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[23] origin:064-gtp-channel-conf 29_443 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[24] origin:064-gtp-channel-conf 28_444 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[25] origin:064-gtp-channel-conf 29_444 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[26] origin:064-gtp-channel-conf 28_445 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[27] origin:064-gtp-channel-conf 29_445 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[28] origin:064-gtp-channel-conf 28_446 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[29] origin:064-gtp-channel-conf 29_446 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[30] origin:064-gtp-channel-conf 28_447 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[31] origin:064-gtp-channel-conf 29_447 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[32] origin:064-gtp-channel-conf 28_448 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[33] origin:064-gtp-channel-conf 29_448 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[34] origin:064-gtp-channel-conf 28_449 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[35] origin:064-gtp-channel-conf 29_449 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[36] origin:064-gtp-channel-conf 28_450 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[37] origin:064-gtp-channel-conf 29_450 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[38] origin:064-gtp-channel-conf 28_451 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[39] origin:064-gtp-channel-conf 29_451 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[40] origin:064-gtp-channel-conf 28_452 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[41] origin:064-gtp-channel-conf 29_452 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[42] origin:064-gtp-channel-conf 28_453 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[43] origin:064-gtp-channel-conf 29_453 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[44] origin:064-gtp-channel-conf 28_454 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[45] origin:064-gtp-channel-conf 29_454 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[46] origin:064-gtp-channel-conf 28_455 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[47] origin:064-gtp-channel-conf 29_455 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[48] origin:064-gtp-channel-conf 28_456 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[49] origin:064-gtp-channel-conf 29_456 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[50] origin:064-gtp-channel-conf 28_457 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[51] origin:064-gtp-channel-conf 29_457 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[52] origin:064-gtp-channel-conf 28_458 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[53] origin:064-gtp-channel-conf 29_458 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[54] origin:064-gtp-channel-conf 28_459 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[55] origin:064-gtp-channel-conf 29_459 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[56] origin:064-gtp-channel-conf 28_460 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[57] origin:064-gtp-channel-conf 29_460 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[58] origin:064-gtp-channel-conf 28_461 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[59] origin:064-gtp-channel-conf 29_461 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[60] origin:064-gtp-channel-conf 28_462 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[61] origin:064-gtp-channel-conf 29_462 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[62] origin:064-gtp-channel-conf 28_463 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[63] origin:064-gtp-channel-conf 29_463 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[64] origin:064-gtp-channel-conf 28_464 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[65] origin:064-gtp-channel-conf 29_464 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[66] origin:064-gtp-channel-conf 28_465 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[67] origin:064-gtp-channel-conf 29_465 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[68] origin:064-gtp-channel-conf 28_466 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[69] origin:064-gtp-channel-conf 29_466 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[70] origin:064-gtp-channel-conf 28_467 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[71] origin:064-gtp-channel-conf 29_467 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[72] origin:064-gtp-channel-conf 28_468 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[73] origin:064-gtp-channel-conf 29_468 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[74] origin:064-gtp-channel-conf 28_469 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[75] origin:064-gtp-channel-conf 29_469 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[76] origin:064-gtp-channel-conf 28_470 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[77] origin:064-gtp-channel-conf 29_470 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[78] origin:064-gtp-channel-conf 28_471 -GTP_CHANNEL_2.GTPE2.ES_SDATA_MASK[79] origin:064-gtp-channel-conf 29_471 -GTP_CHANNEL_2.GTPE2.ES_VERT_OFFSET[0] origin:064-gtp-channel-conf 28_472 -GTP_CHANNEL_2.GTPE2.ES_VERT_OFFSET[1] origin:064-gtp-channel-conf 29_472 -GTP_CHANNEL_2.GTPE2.ES_VERT_OFFSET[2] origin:064-gtp-channel-conf 28_473 -GTP_CHANNEL_2.GTPE2.ES_VERT_OFFSET[3] origin:064-gtp-channel-conf 29_473 -GTP_CHANNEL_2.GTPE2.ES_VERT_OFFSET[4] origin:064-gtp-channel-conf 28_474 -GTP_CHANNEL_2.GTPE2.ES_VERT_OFFSET[5] origin:064-gtp-channel-conf 29_474 -GTP_CHANNEL_2.GTPE2.ES_VERT_OFFSET[6] origin:064-gtp-channel-conf 28_475 -GTP_CHANNEL_2.GTPE2.ES_VERT_OFFSET[7] origin:064-gtp-channel-conf 29_475 -GTP_CHANNEL_2.GTPE2.ES_VERT_OFFSET[8] origin:064-gtp-channel-conf 28_476 -GTP_CHANNEL_2.GTPE2.FTS_DESKEW_SEQ_ENABLE[0] origin:064-gtp-channel-conf 28_662 -GTP_CHANNEL_2.GTPE2.FTS_DESKEW_SEQ_ENABLE[1] origin:064-gtp-channel-conf 29_662 -GTP_CHANNEL_2.GTPE2.FTS_DESKEW_SEQ_ENABLE[2] origin:064-gtp-channel-conf 28_663 -GTP_CHANNEL_2.GTPE2.FTS_DESKEW_SEQ_ENABLE[3] origin:064-gtp-channel-conf 29_663 -GTP_CHANNEL_2.GTPE2.FTS_LANE_DESKEW_CFG[0] origin:064-gtp-channel-conf 28_654 -GTP_CHANNEL_2.GTPE2.FTS_LANE_DESKEW_CFG[1] origin:064-gtp-channel-conf 29_654 -GTP_CHANNEL_2.GTPE2.FTS_LANE_DESKEW_CFG[2] origin:064-gtp-channel-conf 28_655 -GTP_CHANNEL_2.GTPE2.FTS_LANE_DESKEW_CFG[3] origin:064-gtp-channel-conf 29_655 -GTP_CHANNEL_2.GTPE2.FTS_LANE_DESKEW_EN origin:064-gtp-channel-conf 29_653 -GTP_CHANNEL_2.GTPE2.GEARBOX_MODE[0] origin:064-gtp-channel-conf 28_224 -GTP_CHANNEL_2.GTPE2.GEARBOX_MODE[1] origin:064-gtp-channel-conf 29_224 -GTP_CHANNEL_2.GTPE2.GEARBOX_MODE[2] origin:064-gtp-channel-conf 28_225 -GTP_CHANNEL_2.GTPE2.IN_USE origin:064-gtp-channel-conf 28_00 28_01 28_47 28_52 28_53 28_65 29_01 29_47 30_129 -GTP_CHANNEL_2.GTPE2.LOOPBACK_CFG[0] origin:064-gtp-channel-conf 30_20 -GTP_CHANNEL_2.GTPE2.OUTREFCLK_SEL_INV[0] origin:064-gtp-channel-conf 28_149 -GTP_CHANNEL_2.GTPE2.OUTREFCLK_SEL_INV[1] origin:064-gtp-channel-conf 29_149 -GTP_CHANNEL_2.GTPE2.PCS_PCIE_EN origin:064-gtp-channel-conf 28_216 -GTP_CHANNEL_2.GTPE2.PCS_RSVD_ATTR[0] origin:064-gtp-channel-conf 30_184 -GTP_CHANNEL_2.GTPE2.PCS_RSVD_ATTR[1] origin:064-gtp-channel-conf 31_184 -GTP_CHANNEL_2.GTPE2.PCS_RSVD_ATTR[2] origin:064-gtp-channel-conf 30_185 -GTP_CHANNEL_2.GTPE2.PCS_RSVD_ATTR[3] origin:064-gtp-channel-conf 31_185 -GTP_CHANNEL_2.GTPE2.PCS_RSVD_ATTR[4] origin:064-gtp-channel-conf 30_186 -GTP_CHANNEL_2.GTPE2.PCS_RSVD_ATTR[5] origin:064-gtp-channel-conf 31_186 -GTP_CHANNEL_2.GTPE2.PCS_RSVD_ATTR[6] origin:064-gtp-channel-conf 30_187 -GTP_CHANNEL_2.GTPE2.PCS_RSVD_ATTR[7] origin:064-gtp-channel-conf 31_187 -GTP_CHANNEL_2.GTPE2.PCS_RSVD_ATTR[8] origin:064-gtp-channel-conf 30_188 -GTP_CHANNEL_2.GTPE2.PCS_RSVD_ATTR[9] origin:064-gtp-channel-conf 31_188 -GTP_CHANNEL_2.GTPE2.PCS_RSVD_ATTR[10] origin:064-gtp-channel-conf 30_189 -GTP_CHANNEL_2.GTPE2.PCS_RSVD_ATTR[11] origin:064-gtp-channel-conf 31_189 -GTP_CHANNEL_2.GTPE2.PCS_RSVD_ATTR[12] origin:064-gtp-channel-conf 30_190 -GTP_CHANNEL_2.GTPE2.PCS_RSVD_ATTR[13] origin:064-gtp-channel-conf 31_190 -GTP_CHANNEL_2.GTPE2.PCS_RSVD_ATTR[14] origin:064-gtp-channel-conf 30_191 -GTP_CHANNEL_2.GTPE2.PCS_RSVD_ATTR[15] origin:064-gtp-channel-conf 31_191 -GTP_CHANNEL_2.GTPE2.PCS_RSVD_ATTR[16] origin:064-gtp-channel-conf 30_192 -GTP_CHANNEL_2.GTPE2.PCS_RSVD_ATTR[17] origin:064-gtp-channel-conf 31_192 -GTP_CHANNEL_2.GTPE2.PCS_RSVD_ATTR[18] origin:064-gtp-channel-conf 30_193 -GTP_CHANNEL_2.GTPE2.PCS_RSVD_ATTR[19] origin:064-gtp-channel-conf 31_193 -GTP_CHANNEL_2.GTPE2.PCS_RSVD_ATTR[20] origin:064-gtp-channel-conf 30_194 -GTP_CHANNEL_2.GTPE2.PCS_RSVD_ATTR[21] origin:064-gtp-channel-conf 31_194 -GTP_CHANNEL_2.GTPE2.PCS_RSVD_ATTR[22] origin:064-gtp-channel-conf 30_195 -GTP_CHANNEL_2.GTPE2.PCS_RSVD_ATTR[23] origin:064-gtp-channel-conf 31_195 -GTP_CHANNEL_2.GTPE2.PCS_RSVD_ATTR[24] origin:064-gtp-channel-conf 30_196 -GTP_CHANNEL_2.GTPE2.PCS_RSVD_ATTR[25] origin:064-gtp-channel-conf 31_196 -GTP_CHANNEL_2.GTPE2.PCS_RSVD_ATTR[26] origin:064-gtp-channel-conf 30_197 -GTP_CHANNEL_2.GTPE2.PCS_RSVD_ATTR[27] origin:064-gtp-channel-conf 31_197 -GTP_CHANNEL_2.GTPE2.PCS_RSVD_ATTR[28] origin:064-gtp-channel-conf 30_198 -GTP_CHANNEL_2.GTPE2.PCS_RSVD_ATTR[29] origin:064-gtp-channel-conf 31_198 -GTP_CHANNEL_2.GTPE2.PCS_RSVD_ATTR[30] origin:064-gtp-channel-conf 30_199 -GTP_CHANNEL_2.GTPE2.PCS_RSVD_ATTR[31] origin:064-gtp-channel-conf 31_199 -GTP_CHANNEL_2.GTPE2.PCS_RSVD_ATTR[32] origin:064-gtp-channel-conf 30_200 -GTP_CHANNEL_2.GTPE2.PCS_RSVD_ATTR[33] origin:064-gtp-channel-conf 31_200 -GTP_CHANNEL_2.GTPE2.PCS_RSVD_ATTR[34] origin:064-gtp-channel-conf 30_201 -GTP_CHANNEL_2.GTPE2.PCS_RSVD_ATTR[35] origin:064-gtp-channel-conf 31_201 -GTP_CHANNEL_2.GTPE2.PCS_RSVD_ATTR[36] origin:064-gtp-channel-conf 30_202 -GTP_CHANNEL_2.GTPE2.PCS_RSVD_ATTR[37] origin:064-gtp-channel-conf 31_202 -GTP_CHANNEL_2.GTPE2.PCS_RSVD_ATTR[38] origin:064-gtp-channel-conf 30_203 -GTP_CHANNEL_2.GTPE2.PCS_RSVD_ATTR[39] origin:064-gtp-channel-conf 31_203 -GTP_CHANNEL_2.GTPE2.PCS_RSVD_ATTR[40] origin:064-gtp-channel-conf 30_204 -GTP_CHANNEL_2.GTPE2.PCS_RSVD_ATTR[41] origin:064-gtp-channel-conf 31_204 -GTP_CHANNEL_2.GTPE2.PCS_RSVD_ATTR[42] origin:064-gtp-channel-conf 30_205 -GTP_CHANNEL_2.GTPE2.PCS_RSVD_ATTR[43] origin:064-gtp-channel-conf 31_205 -GTP_CHANNEL_2.GTPE2.PCS_RSVD_ATTR[44] origin:064-gtp-channel-conf 30_206 -GTP_CHANNEL_2.GTPE2.PCS_RSVD_ATTR[45] origin:064-gtp-channel-conf 31_206 -GTP_CHANNEL_2.GTPE2.PCS_RSVD_ATTR[46] origin:064-gtp-channel-conf 30_207 -GTP_CHANNEL_2.GTPE2.PCS_RSVD_ATTR[47] origin:064-gtp-channel-conf 31_207 -GTP_CHANNEL_2.GTPE2.PD_TRANS_TIME_FROM_P2[0] origin:064-gtp-channel-conf 29_216 -GTP_CHANNEL_2.GTPE2.PD_TRANS_TIME_FROM_P2[1] origin:064-gtp-channel-conf 28_217 -GTP_CHANNEL_2.GTPE2.PD_TRANS_TIME_FROM_P2[2] origin:064-gtp-channel-conf 29_217 -GTP_CHANNEL_2.GTPE2.PD_TRANS_TIME_FROM_P2[3] origin:064-gtp-channel-conf 28_218 -GTP_CHANNEL_2.GTPE2.PD_TRANS_TIME_FROM_P2[4] origin:064-gtp-channel-conf 29_218 -GTP_CHANNEL_2.GTPE2.PD_TRANS_TIME_FROM_P2[5] origin:064-gtp-channel-conf 28_219 -GTP_CHANNEL_2.GTPE2.PD_TRANS_TIME_FROM_P2[6] origin:064-gtp-channel-conf 29_219 -GTP_CHANNEL_2.GTPE2.PD_TRANS_TIME_FROM_P2[7] origin:064-gtp-channel-conf 28_220 -GTP_CHANNEL_2.GTPE2.PD_TRANS_TIME_FROM_P2[8] origin:064-gtp-channel-conf 29_220 -GTP_CHANNEL_2.GTPE2.PD_TRANS_TIME_FROM_P2[9] origin:064-gtp-channel-conf 28_221 -GTP_CHANNEL_2.GTPE2.PD_TRANS_TIME_FROM_P2[10] origin:064-gtp-channel-conf 29_221 -GTP_CHANNEL_2.GTPE2.PD_TRANS_TIME_FROM_P2[11] origin:064-gtp-channel-conf 28_222 -GTP_CHANNEL_2.GTPE2.PD_TRANS_TIME_NONE_P2[0] origin:064-gtp-channel-conf 28_208 -GTP_CHANNEL_2.GTPE2.PD_TRANS_TIME_NONE_P2[1] origin:064-gtp-channel-conf 29_208 -GTP_CHANNEL_2.GTPE2.PD_TRANS_TIME_NONE_P2[2] origin:064-gtp-channel-conf 28_209 -GTP_CHANNEL_2.GTPE2.PD_TRANS_TIME_NONE_P2[3] origin:064-gtp-channel-conf 29_209 -GTP_CHANNEL_2.GTPE2.PD_TRANS_TIME_NONE_P2[4] origin:064-gtp-channel-conf 28_210 -GTP_CHANNEL_2.GTPE2.PD_TRANS_TIME_NONE_P2[5] origin:064-gtp-channel-conf 29_210 -GTP_CHANNEL_2.GTPE2.PD_TRANS_TIME_NONE_P2[6] origin:064-gtp-channel-conf 28_211 -GTP_CHANNEL_2.GTPE2.PD_TRANS_TIME_NONE_P2[7] origin:064-gtp-channel-conf 29_211 -GTP_CHANNEL_2.GTPE2.PD_TRANS_TIME_TO_P2[0] origin:064-gtp-channel-conf 28_212 -GTP_CHANNEL_2.GTPE2.PD_TRANS_TIME_TO_P2[1] origin:064-gtp-channel-conf 29_212 -GTP_CHANNEL_2.GTPE2.PD_TRANS_TIME_TO_P2[2] origin:064-gtp-channel-conf 28_213 -GTP_CHANNEL_2.GTPE2.PD_TRANS_TIME_TO_P2[3] origin:064-gtp-channel-conf 29_213 -GTP_CHANNEL_2.GTPE2.PD_TRANS_TIME_TO_P2[4] origin:064-gtp-channel-conf 28_214 -GTP_CHANNEL_2.GTPE2.PD_TRANS_TIME_TO_P2[5] origin:064-gtp-channel-conf 29_214 -GTP_CHANNEL_2.GTPE2.PD_TRANS_TIME_TO_P2[6] origin:064-gtp-channel-conf 28_215 -GTP_CHANNEL_2.GTPE2.PD_TRANS_TIME_TO_P2[7] origin:064-gtp-channel-conf 29_215 -GTP_CHANNEL_2.GTPE2.PMA_LOOPBACK_CFG[0] origin:064-gtp-channel-conf 29_207 -GTP_CHANNEL_2.GTPE2.PMA_RSV[0] origin:064-gtp-channel-conf 30_520 -GTP_CHANNEL_2.GTPE2.PMA_RSV[1] origin:064-gtp-channel-conf 31_520 -GTP_CHANNEL_2.GTPE2.PMA_RSV[2] origin:064-gtp-channel-conf 30_521 -GTP_CHANNEL_2.GTPE2.PMA_RSV[3] origin:064-gtp-channel-conf 31_521 -GTP_CHANNEL_2.GTPE2.PMA_RSV[4] origin:064-gtp-channel-conf 30_522 -GTP_CHANNEL_2.GTPE2.PMA_RSV[5] origin:064-gtp-channel-conf 31_522 -GTP_CHANNEL_2.GTPE2.PMA_RSV[6] origin:064-gtp-channel-conf 30_523 -GTP_CHANNEL_2.GTPE2.PMA_RSV[7] origin:064-gtp-channel-conf 31_523 -GTP_CHANNEL_2.GTPE2.PMA_RSV[8] origin:064-gtp-channel-conf 30_524 -GTP_CHANNEL_2.GTPE2.PMA_RSV[9] origin:064-gtp-channel-conf 31_524 -GTP_CHANNEL_2.GTPE2.PMA_RSV[10] origin:064-gtp-channel-conf 30_525 -GTP_CHANNEL_2.GTPE2.PMA_RSV[11] origin:064-gtp-channel-conf 31_525 -GTP_CHANNEL_2.GTPE2.PMA_RSV[12] origin:064-gtp-channel-conf 30_526 -GTP_CHANNEL_2.GTPE2.PMA_RSV[13] origin:064-gtp-channel-conf 31_526 -GTP_CHANNEL_2.GTPE2.PMA_RSV[14] origin:064-gtp-channel-conf 30_527 -GTP_CHANNEL_2.GTPE2.PMA_RSV[15] origin:064-gtp-channel-conf 31_527 -GTP_CHANNEL_2.GTPE2.PMA_RSV[16] origin:064-gtp-channel-conf 30_528 -GTP_CHANNEL_2.GTPE2.PMA_RSV[17] origin:064-gtp-channel-conf 31_528 -GTP_CHANNEL_2.GTPE2.PMA_RSV[18] origin:064-gtp-channel-conf 30_529 -GTP_CHANNEL_2.GTPE2.PMA_RSV[19] origin:064-gtp-channel-conf 31_529 -GTP_CHANNEL_2.GTPE2.PMA_RSV[20] origin:064-gtp-channel-conf 30_530 -GTP_CHANNEL_2.GTPE2.PMA_RSV[21] origin:064-gtp-channel-conf 31_530 -GTP_CHANNEL_2.GTPE2.PMA_RSV[22] origin:064-gtp-channel-conf 30_531 -GTP_CHANNEL_2.GTPE2.PMA_RSV[23] origin:064-gtp-channel-conf 31_531 -GTP_CHANNEL_2.GTPE2.PMA_RSV[24] origin:064-gtp-channel-conf 30_532 -GTP_CHANNEL_2.GTPE2.PMA_RSV[25] origin:064-gtp-channel-conf 31_532 -GTP_CHANNEL_2.GTPE2.PMA_RSV[26] origin:064-gtp-channel-conf 30_533 -GTP_CHANNEL_2.GTPE2.PMA_RSV[27] origin:064-gtp-channel-conf 31_533 -GTP_CHANNEL_2.GTPE2.PMA_RSV[28] origin:064-gtp-channel-conf 30_534 -GTP_CHANNEL_2.GTPE2.PMA_RSV[29] origin:064-gtp-channel-conf 31_534 -GTP_CHANNEL_2.GTPE2.PMA_RSV[30] origin:064-gtp-channel-conf 30_535 -GTP_CHANNEL_2.GTPE2.PMA_RSV[31] origin:064-gtp-channel-conf 31_535 -GTP_CHANNEL_2.GTPE2.PMA_RSV2[0] origin:064-gtp-channel-conf 30_336 -GTP_CHANNEL_2.GTPE2.PMA_RSV2[1] origin:064-gtp-channel-conf 31_336 -GTP_CHANNEL_2.GTPE2.PMA_RSV2[2] origin:064-gtp-channel-conf 30_337 -GTP_CHANNEL_2.GTPE2.PMA_RSV2[3] origin:064-gtp-channel-conf 31_337 -GTP_CHANNEL_2.GTPE2.PMA_RSV2[4] origin:064-gtp-channel-conf 30_338 -GTP_CHANNEL_2.GTPE2.PMA_RSV2[5] origin:064-gtp-channel-conf 31_338 -GTP_CHANNEL_2.GTPE2.PMA_RSV2[6] origin:064-gtp-channel-conf 30_339 -GTP_CHANNEL_2.GTPE2.PMA_RSV2[7] origin:064-gtp-channel-conf 31_339 -GTP_CHANNEL_2.GTPE2.PMA_RSV2[8] origin:064-gtp-channel-conf 30_340 -GTP_CHANNEL_2.GTPE2.PMA_RSV2[9] origin:064-gtp-channel-conf 31_340 -GTP_CHANNEL_2.GTPE2.PMA_RSV2[10] origin:064-gtp-channel-conf 30_341 -GTP_CHANNEL_2.GTPE2.PMA_RSV2[11] origin:064-gtp-channel-conf 31_341 -GTP_CHANNEL_2.GTPE2.PMA_RSV2[12] origin:064-gtp-channel-conf 30_342 -GTP_CHANNEL_2.GTPE2.PMA_RSV2[13] origin:064-gtp-channel-conf 31_342 -GTP_CHANNEL_2.GTPE2.PMA_RSV2[14] origin:064-gtp-channel-conf 30_343 -GTP_CHANNEL_2.GTPE2.PMA_RSV2[15] origin:064-gtp-channel-conf 31_343 -GTP_CHANNEL_2.GTPE2.PMA_RSV2[16] origin:064-gtp-channel-conf 30_344 -GTP_CHANNEL_2.GTPE2.PMA_RSV2[17] origin:064-gtp-channel-conf 31_344 -GTP_CHANNEL_2.GTPE2.PMA_RSV2[18] origin:064-gtp-channel-conf 30_345 -GTP_CHANNEL_2.GTPE2.PMA_RSV2[19] origin:064-gtp-channel-conf 31_345 -GTP_CHANNEL_2.GTPE2.PMA_RSV2[20] origin:064-gtp-channel-conf 30_346 -GTP_CHANNEL_2.GTPE2.PMA_RSV2[21] origin:064-gtp-channel-conf 31_346 -GTP_CHANNEL_2.GTPE2.PMA_RSV2[22] origin:064-gtp-channel-conf 30_347 -GTP_CHANNEL_2.GTPE2.PMA_RSV2[23] origin:064-gtp-channel-conf 31_347 -GTP_CHANNEL_2.GTPE2.PMA_RSV2[24] origin:064-gtp-channel-conf 30_348 -GTP_CHANNEL_2.GTPE2.PMA_RSV2[25] origin:064-gtp-channel-conf 31_348 -GTP_CHANNEL_2.GTPE2.PMA_RSV2[26] origin:064-gtp-channel-conf 30_349 -GTP_CHANNEL_2.GTPE2.PMA_RSV2[27] origin:064-gtp-channel-conf 31_349 -GTP_CHANNEL_2.GTPE2.PMA_RSV2[28] origin:064-gtp-channel-conf 30_350 -GTP_CHANNEL_2.GTPE2.PMA_RSV2[29] origin:064-gtp-channel-conf 31_350 -GTP_CHANNEL_2.GTPE2.PMA_RSV2[30] origin:064-gtp-channel-conf 30_351 -GTP_CHANNEL_2.GTPE2.PMA_RSV2[31] origin:064-gtp-channel-conf 31_351 -GTP_CHANNEL_2.GTPE2.PMA_RSV3[0] origin:064-gtp-channel-conf 30_288 -GTP_CHANNEL_2.GTPE2.PMA_RSV3[1] origin:064-gtp-channel-conf 31_288 -GTP_CHANNEL_2.GTPE2.PMA_RSV4[0] origin:064-gtp-channel-conf 30_156 -GTP_CHANNEL_2.GTPE2.PMA_RSV4[1] origin:064-gtp-channel-conf 31_156 -GTP_CHANNEL_2.GTPE2.PMA_RSV4[2] origin:064-gtp-channel-conf 30_157 -GTP_CHANNEL_2.GTPE2.PMA_RSV4[3] origin:064-gtp-channel-conf 31_157 -GTP_CHANNEL_2.GTPE2.PMA_RSV5[0] origin:064-gtp-channel-conf 31_159 -GTP_CHANNEL_2.GTPE2.PMA_RSV6[0] origin:064-gtp-channel-conf 30_303 -GTP_CHANNEL_2.GTPE2.PMA_RSV7[0] origin:064-gtp-channel-conf 31_303 -GTP_CHANNEL_2.GTPE2.RX_BIAS_CFG[0] origin:064-gtp-channel-conf 30_112 -GTP_CHANNEL_2.GTPE2.RX_BIAS_CFG[1] origin:064-gtp-channel-conf 31_112 -GTP_CHANNEL_2.GTPE2.RX_BIAS_CFG[2] origin:064-gtp-channel-conf 30_113 -GTP_CHANNEL_2.GTPE2.RX_BIAS_CFG[3] origin:064-gtp-channel-conf 31_113 -GTP_CHANNEL_2.GTPE2.RX_BIAS_CFG[4] origin:064-gtp-channel-conf 30_114 -GTP_CHANNEL_2.GTPE2.RX_BIAS_CFG[5] origin:064-gtp-channel-conf 31_114 -GTP_CHANNEL_2.GTPE2.RX_BIAS_CFG[6] origin:064-gtp-channel-conf 30_115 -GTP_CHANNEL_2.GTPE2.RX_BIAS_CFG[7] origin:064-gtp-channel-conf 31_115 -GTP_CHANNEL_2.GTPE2.RX_BIAS_CFG[8] origin:064-gtp-channel-conf 30_116 -GTP_CHANNEL_2.GTPE2.RX_BIAS_CFG[9] origin:064-gtp-channel-conf 31_116 -GTP_CHANNEL_2.GTPE2.RX_BIAS_CFG[10] origin:064-gtp-channel-conf 30_117 -GTP_CHANNEL_2.GTPE2.RX_BIAS_CFG[11] origin:064-gtp-channel-conf 31_117 -GTP_CHANNEL_2.GTPE2.RX_BIAS_CFG[12] origin:064-gtp-channel-conf 30_118 -GTP_CHANNEL_2.GTPE2.RX_BIAS_CFG[13] origin:064-gtp-channel-conf 31_118 -GTP_CHANNEL_2.GTPE2.RX_BIAS_CFG[14] origin:064-gtp-channel-conf 30_119 -GTP_CHANNEL_2.GTPE2.RX_BIAS_CFG[15] origin:064-gtp-channel-conf 31_119 -GTP_CHANNEL_2.GTPE2.RX_BUFFER_CFG[0] origin:064-gtp-channel-conf 30_536 -GTP_CHANNEL_2.GTPE2.RX_BUFFER_CFG[1] origin:064-gtp-channel-conf 31_536 -GTP_CHANNEL_2.GTPE2.RX_BUFFER_CFG[2] origin:064-gtp-channel-conf 30_537 -GTP_CHANNEL_2.GTPE2.RX_BUFFER_CFG[3] origin:064-gtp-channel-conf 31_537 -GTP_CHANNEL_2.GTPE2.RX_BUFFER_CFG[4] origin:064-gtp-channel-conf 30_538 -GTP_CHANNEL_2.GTPE2.RX_BUFFER_CFG[5] origin:064-gtp-channel-conf 31_538 -GTP_CHANNEL_2.GTPE2.RX_CLKMUX_EN[0] origin:064-gtp-channel-conf 30_128 -GTP_CHANNEL_2.GTPE2.RX_CM_SEL[0] origin:064-gtp-channel-conf 28_138 -GTP_CHANNEL_2.GTPE2.RX_CM_SEL[1] origin:064-gtp-channel-conf 29_138 -GTP_CHANNEL_2.GTPE2.RX_CM_TRIM[0] origin:064-gtp-channel-conf 30_304 -GTP_CHANNEL_2.GTPE2.RX_CM_TRIM[1] origin:064-gtp-channel-conf 31_304 -GTP_CHANNEL_2.GTPE2.RX_CM_TRIM[2] origin:064-gtp-channel-conf 30_305 -GTP_CHANNEL_2.GTPE2.RX_CM_TRIM[3] origin:064-gtp-channel-conf 31_305 -GTP_CHANNEL_2.GTPE2.RX_DATA_WIDTH[0] origin:064-gtp-channel-conf 29_141 -GTP_CHANNEL_2.GTPE2.RX_DATA_WIDTH[1] origin:064-gtp-channel-conf 28_142 -GTP_CHANNEL_2.GTPE2.RX_DATA_WIDTH[2] origin:064-gtp-channel-conf 29_142 -GTP_CHANNEL_2.GTPE2.RX_DDI_SEL[0] origin:064-gtp-channel-conf 28_696 -GTP_CHANNEL_2.GTPE2.RX_DDI_SEL[1] origin:064-gtp-channel-conf 29_696 -GTP_CHANNEL_2.GTPE2.RX_DDI_SEL[2] origin:064-gtp-channel-conf 28_697 -GTP_CHANNEL_2.GTPE2.RX_DDI_SEL[3] origin:064-gtp-channel-conf 29_697 -GTP_CHANNEL_2.GTPE2.RX_DDI_SEL[4] origin:064-gtp-channel-conf 28_698 -GTP_CHANNEL_2.GTPE2.RX_DDI_SEL[5] origin:064-gtp-channel-conf 29_698 -GTP_CHANNEL_2.GTPE2.RX_DEBUG_CFG[0] origin:064-gtp-channel-conf 30_616 -GTP_CHANNEL_2.GTPE2.RX_DEBUG_CFG[1] origin:064-gtp-channel-conf 31_616 -GTP_CHANNEL_2.GTPE2.RX_DEBUG_CFG[2] origin:064-gtp-channel-conf 30_617 -GTP_CHANNEL_2.GTPE2.RX_DEBUG_CFG[3] origin:064-gtp-channel-conf 31_617 -GTP_CHANNEL_2.GTPE2.RX_DEBUG_CFG[4] origin:064-gtp-channel-conf 30_618 -GTP_CHANNEL_2.GTPE2.RX_DEBUG_CFG[5] origin:064-gtp-channel-conf 31_618 -GTP_CHANNEL_2.GTPE2.RX_DEBUG_CFG[6] origin:064-gtp-channel-conf 30_619 -GTP_CHANNEL_2.GTPE2.RX_DEBUG_CFG[7] origin:064-gtp-channel-conf 31_619 -GTP_CHANNEL_2.GTPE2.RX_DEBUG_CFG[8] origin:064-gtp-channel-conf 30_620 -GTP_CHANNEL_2.GTPE2.RX_DEBUG_CFG[9] origin:064-gtp-channel-conf 31_620 -GTP_CHANNEL_2.GTPE2.RX_DEBUG_CFG[10] origin:064-gtp-channel-conf 30_621 -GTP_CHANNEL_2.GTPE2.RX_DEBUG_CFG[11] origin:064-gtp-channel-conf 31_621 -GTP_CHANNEL_2.GTPE2.RX_DEBUG_CFG[12] origin:064-gtp-channel-conf 30_622 -GTP_CHANNEL_2.GTPE2.RX_DEBUG_CFG[13] origin:064-gtp-channel-conf 31_622 -GTP_CHANNEL_2.GTPE2.RX_DEFER_RESET_BUF_EN origin:064-gtp-channel-conf 30_552 -GTP_CHANNEL_2.GTPE2.RX_DISPERR_SEQ_MATCH origin:064-gtp-channel-conf 29_495 -GTP_CHANNEL_2.GTPE2.RX_OS_CFG[0] origin:064-gtp-channel-conf 28_288 -GTP_CHANNEL_2.GTPE2.RX_OS_CFG[1] origin:064-gtp-channel-conf 29_288 -GTP_CHANNEL_2.GTPE2.RX_OS_CFG[2] origin:064-gtp-channel-conf 28_289 -GTP_CHANNEL_2.GTPE2.RX_OS_CFG[3] origin:064-gtp-channel-conf 29_289 -GTP_CHANNEL_2.GTPE2.RX_OS_CFG[4] origin:064-gtp-channel-conf 28_290 -GTP_CHANNEL_2.GTPE2.RX_OS_CFG[5] origin:064-gtp-channel-conf 29_290 -GTP_CHANNEL_2.GTPE2.RX_OS_CFG[6] origin:064-gtp-channel-conf 28_291 -GTP_CHANNEL_2.GTPE2.RX_OS_CFG[7] origin:064-gtp-channel-conf 29_291 -GTP_CHANNEL_2.GTPE2.RX_OS_CFG[8] origin:064-gtp-channel-conf 28_292 -GTP_CHANNEL_2.GTPE2.RX_OS_CFG[9] origin:064-gtp-channel-conf 29_292 -GTP_CHANNEL_2.GTPE2.RX_OS_CFG[10] origin:064-gtp-channel-conf 28_293 -GTP_CHANNEL_2.GTPE2.RX_OS_CFG[11] origin:064-gtp-channel-conf 29_293 -GTP_CHANNEL_2.GTPE2.RX_OS_CFG[12] origin:064-gtp-channel-conf 28_294 -GTP_CHANNEL_2.GTPE2.RX_SIG_VALID_DLY[0] origin:064-gtp-channel-conf 28_524 -GTP_CHANNEL_2.GTPE2.RX_SIG_VALID_DLY[1] origin:064-gtp-channel-conf 29_524 -GTP_CHANNEL_2.GTPE2.RX_SIG_VALID_DLY[2] origin:064-gtp-channel-conf 28_525 -GTP_CHANNEL_2.GTPE2.RX_SIG_VALID_DLY[3] origin:064-gtp-channel-conf 29_525 -GTP_CHANNEL_2.GTPE2.RX_SIG_VALID_DLY[4] origin:064-gtp-channel-conf 28_526 -GTP_CHANNEL_2.GTPE2.RX_XCLK_SEL.RXUSR origin:064-gtp-channel-conf 28_143 -GTP_CHANNEL_2.GTPE2.RX_CLK25_DIV[0] origin:064-gtp-channel-conf 28_139 -GTP_CHANNEL_2.GTPE2.RX_CLK25_DIV[1] origin:064-gtp-channel-conf 29_139 -GTP_CHANNEL_2.GTPE2.RX_CLK25_DIV[2] origin:064-gtp-channel-conf 28_140 -GTP_CHANNEL_2.GTPE2.RX_CLK25_DIV[3] origin:064-gtp-channel-conf 29_140 -GTP_CHANNEL_2.GTPE2.RX_CLK25_DIV[4] origin:064-gtp-channel-conf 28_141 -GTP_CHANNEL_2.GTPE2.RXBUF_ADDR_MODE.FAST origin:064-gtp-channel-conf 31_555 -GTP_CHANNEL_2.GTPE2.RXBUF_EIDLE_HI_CNT[0] origin:064-gtp-channel-conf 30_558 -GTP_CHANNEL_2.GTPE2.RXBUF_EIDLE_HI_CNT[1] origin:064-gtp-channel-conf 31_558 -GTP_CHANNEL_2.GTPE2.RXBUF_EIDLE_HI_CNT[2] origin:064-gtp-channel-conf 30_559 -GTP_CHANNEL_2.GTPE2.RXBUF_EIDLE_HI_CNT[3] origin:064-gtp-channel-conf 31_559 -GTP_CHANNEL_2.GTPE2.RXBUF_EIDLE_LO_CNT[0] origin:064-gtp-channel-conf 30_556 -GTP_CHANNEL_2.GTPE2.RXBUF_EIDLE_LO_CNT[1] origin:064-gtp-channel-conf 31_556 -GTP_CHANNEL_2.GTPE2.RXBUF_EIDLE_LO_CNT[2] origin:064-gtp-channel-conf 30_557 -GTP_CHANNEL_2.GTPE2.RXBUF_EIDLE_LO_CNT[3] origin:064-gtp-channel-conf 31_557 -GTP_CHANNEL_2.GTPE2.RXBUF_EN origin:064-gtp-channel-conf 30_11 -GTP_CHANNEL_2.GTPE2.RXBUF_RESET_ON_CB_CHANGE origin:064-gtp-channel-conf 30_560 -GTP_CHANNEL_2.GTPE2.RXBUF_RESET_ON_COMMAALIGN origin:064-gtp-channel-conf 30_561 -GTP_CHANNEL_2.GTPE2.RXBUF_RESET_ON_EIDLE origin:064-gtp-channel-conf 30_547 -GTP_CHANNEL_2.GTPE2.RXBUF_RESET_ON_RATE_CHANGE origin:064-gtp-channel-conf 31_560 -GTP_CHANNEL_2.GTPE2.RXBUF_THRESH_OVFLW[0] origin:064-gtp-channel-conf 31_552 -GTP_CHANNEL_2.GTPE2.RXBUF_THRESH_OVFLW[1] origin:064-gtp-channel-conf 30_553 -GTP_CHANNEL_2.GTPE2.RXBUF_THRESH_OVFLW[2] origin:064-gtp-channel-conf 31_553 -GTP_CHANNEL_2.GTPE2.RXBUF_THRESH_OVFLW[3] origin:064-gtp-channel-conf 30_554 -GTP_CHANNEL_2.GTPE2.RXBUF_THRESH_OVFLW[4] origin:064-gtp-channel-conf 31_554 -GTP_CHANNEL_2.GTPE2.RXBUF_THRESH_OVFLW[5] origin:064-gtp-channel-conf 30_555 -GTP_CHANNEL_2.GTPE2.RXBUF_THRESH_OVRD origin:064-gtp-channel-conf 30_548 -GTP_CHANNEL_2.GTPE2.RXBUF_THRESH_UNDFLW[0] origin:064-gtp-channel-conf 30_544 -GTP_CHANNEL_2.GTPE2.RXBUF_THRESH_UNDFLW[1] origin:064-gtp-channel-conf 31_544 -GTP_CHANNEL_2.GTPE2.RXBUF_THRESH_UNDFLW[2] origin:064-gtp-channel-conf 30_545 -GTP_CHANNEL_2.GTPE2.RXBUF_THRESH_UNDFLW[3] origin:064-gtp-channel-conf 31_545 -GTP_CHANNEL_2.GTPE2.RXBUF_THRESH_UNDFLW[4] origin:064-gtp-channel-conf 30_546 -GTP_CHANNEL_2.GTPE2.RXBUF_THRESH_UNDFLW[5] origin:064-gtp-channel-conf 31_546 -GTP_CHANNEL_2.GTPE2.RXBUFRESET_TIME[0] origin:064-gtp-channel-conf 29_101 -GTP_CHANNEL_2.GTPE2.RXBUFRESET_TIME[1] origin:064-gtp-channel-conf 28_102 -GTP_CHANNEL_2.GTPE2.RXBUFRESET_TIME[2] origin:064-gtp-channel-conf 29_102 -GTP_CHANNEL_2.GTPE2.RXBUFRESET_TIME[3] origin:064-gtp-channel-conf 28_103 -GTP_CHANNEL_2.GTPE2.RXBUFRESET_TIME[4] origin:064-gtp-channel-conf 29_103 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[0] origin:064-gtp-channel-conf 30_640 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[1] origin:064-gtp-channel-conf 31_640 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[2] origin:064-gtp-channel-conf 30_641 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[3] origin:064-gtp-channel-conf 31_641 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[4] origin:064-gtp-channel-conf 30_642 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[5] origin:064-gtp-channel-conf 31_642 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[6] origin:064-gtp-channel-conf 30_643 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[7] origin:064-gtp-channel-conf 31_643 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[8] origin:064-gtp-channel-conf 30_644 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[9] origin:064-gtp-channel-conf 31_644 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[10] origin:064-gtp-channel-conf 30_645 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[11] origin:064-gtp-channel-conf 31_645 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[12] origin:064-gtp-channel-conf 30_646 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[13] origin:064-gtp-channel-conf 31_646 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[14] origin:064-gtp-channel-conf 30_647 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[15] origin:064-gtp-channel-conf 31_647 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[16] origin:064-gtp-channel-conf 30_648 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[17] origin:064-gtp-channel-conf 31_648 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[18] origin:064-gtp-channel-conf 30_649 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[19] origin:064-gtp-channel-conf 31_649 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[20] origin:064-gtp-channel-conf 30_650 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[21] origin:064-gtp-channel-conf 31_650 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[22] origin:064-gtp-channel-conf 30_651 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[23] origin:064-gtp-channel-conf 31_651 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[24] origin:064-gtp-channel-conf 30_652 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[25] origin:064-gtp-channel-conf 31_652 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[26] origin:064-gtp-channel-conf 30_653 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[27] origin:064-gtp-channel-conf 31_653 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[28] origin:064-gtp-channel-conf 30_654 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[29] origin:064-gtp-channel-conf 31_654 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[30] origin:064-gtp-channel-conf 30_655 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[31] origin:064-gtp-channel-conf 31_655 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[32] origin:064-gtp-channel-conf 30_656 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[33] origin:064-gtp-channel-conf 31_656 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[34] origin:064-gtp-channel-conf 30_657 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[35] origin:064-gtp-channel-conf 31_657 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[36] origin:064-gtp-channel-conf 30_658 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[37] origin:064-gtp-channel-conf 31_658 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[38] origin:064-gtp-channel-conf 30_659 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[39] origin:064-gtp-channel-conf 31_659 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[40] origin:064-gtp-channel-conf 30_660 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[41] origin:064-gtp-channel-conf 31_660 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[42] origin:064-gtp-channel-conf 30_661 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[43] origin:064-gtp-channel-conf 31_661 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[44] origin:064-gtp-channel-conf 30_662 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[45] origin:064-gtp-channel-conf 31_662 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[46] origin:064-gtp-channel-conf 30_663 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[47] origin:064-gtp-channel-conf 31_663 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[48] origin:064-gtp-channel-conf 30_664 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[49] origin:064-gtp-channel-conf 31_664 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[50] origin:064-gtp-channel-conf 30_665 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[51] origin:064-gtp-channel-conf 31_665 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[52] origin:064-gtp-channel-conf 30_666 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[53] origin:064-gtp-channel-conf 31_666 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[54] origin:064-gtp-channel-conf 30_667 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[55] origin:064-gtp-channel-conf 31_667 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[56] origin:064-gtp-channel-conf 30_668 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[57] origin:064-gtp-channel-conf 31_668 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[58] origin:064-gtp-channel-conf 30_669 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[59] origin:064-gtp-channel-conf 31_669 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[60] origin:064-gtp-channel-conf 30_670 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[61] origin:064-gtp-channel-conf 31_670 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[62] origin:064-gtp-channel-conf 30_671 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[63] origin:064-gtp-channel-conf 31_671 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[64] origin:064-gtp-channel-conf 30_672 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[65] origin:064-gtp-channel-conf 31_672 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[66] origin:064-gtp-channel-conf 30_673 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[67] origin:064-gtp-channel-conf 31_673 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[68] origin:064-gtp-channel-conf 30_674 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[69] origin:064-gtp-channel-conf 31_674 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[70] origin:064-gtp-channel-conf 30_675 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[71] origin:064-gtp-channel-conf 31_675 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[72] origin:064-gtp-channel-conf 30_676 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[73] origin:064-gtp-channel-conf 31_676 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[74] origin:064-gtp-channel-conf 30_677 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[75] origin:064-gtp-channel-conf 31_677 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[76] origin:064-gtp-channel-conf 30_678 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[77] origin:064-gtp-channel-conf 31_678 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[78] origin:064-gtp-channel-conf 30_679 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[79] origin:064-gtp-channel-conf 31_679 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[80] origin:064-gtp-channel-conf 30_680 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[81] origin:064-gtp-channel-conf 31_680 -GTP_CHANNEL_2.GTPE2.RXCDR_CFG[82] origin:064-gtp-channel-conf 30_681 -GTP_CHANNEL_2.GTPE2.RXCDR_FR_RESET_ON_EIDLE[0] origin:064-gtp-channel-conf 30_638 -GTP_CHANNEL_2.GTPE2.RXCDR_HOLD_DURING_EIDLE[0] origin:064-gtp-channel-conf 31_637 -GTP_CHANNEL_2.GTPE2.RXCDR_LOCK_CFG[0] origin:064-gtp-channel-conf 30_632 -GTP_CHANNEL_2.GTPE2.RXCDR_LOCK_CFG[1] origin:064-gtp-channel-conf 31_632 -GTP_CHANNEL_2.GTPE2.RXCDR_LOCK_CFG[2] origin:064-gtp-channel-conf 30_633 -GTP_CHANNEL_2.GTPE2.RXCDR_LOCK_CFG[3] origin:064-gtp-channel-conf 31_633 -GTP_CHANNEL_2.GTPE2.RXCDR_LOCK_CFG[4] origin:064-gtp-channel-conf 30_634 -GTP_CHANNEL_2.GTPE2.RXCDR_LOCK_CFG[5] origin:064-gtp-channel-conf 31_634 -GTP_CHANNEL_2.GTPE2.RXCDR_PH_RESET_ON_EIDLE[0] origin:064-gtp-channel-conf 31_638 -GTP_CHANNEL_2.GTPE2.RXCDRFREQRESET_TIME[0] origin:064-gtp-channel-conf 29_106 -GTP_CHANNEL_2.GTPE2.RXCDRFREQRESET_TIME[1] origin:064-gtp-channel-conf 28_107 -GTP_CHANNEL_2.GTPE2.RXCDRFREQRESET_TIME[2] origin:064-gtp-channel-conf 29_107 -GTP_CHANNEL_2.GTPE2.RXCDRFREQRESET_TIME[3] origin:064-gtp-channel-conf 28_108 -GTP_CHANNEL_2.GTPE2.RXCDRFREQRESET_TIME[4] origin:064-gtp-channel-conf 29_108 -GTP_CHANNEL_2.GTPE2.RXCDRPHRESET_TIME[0] origin:064-gtp-channel-conf 28_109 -GTP_CHANNEL_2.GTPE2.RXCDRPHRESET_TIME[1] origin:064-gtp-channel-conf 29_109 -GTP_CHANNEL_2.GTPE2.RXCDRPHRESET_TIME[2] origin:064-gtp-channel-conf 28_110 -GTP_CHANNEL_2.GTPE2.RXCDRPHRESET_TIME[3] origin:064-gtp-channel-conf 29_110 -GTP_CHANNEL_2.GTPE2.RXCDRPHRESET_TIME[4] origin:064-gtp-channel-conf 28_111 -GTP_CHANNEL_2.GTPE2.RXDLY_CFG[0] origin:064-gtp-channel-conf 28_680 -GTP_CHANNEL_2.GTPE2.RXDLY_CFG[1] origin:064-gtp-channel-conf 29_680 -GTP_CHANNEL_2.GTPE2.RXDLY_CFG[2] origin:064-gtp-channel-conf 28_681 -GTP_CHANNEL_2.GTPE2.RXDLY_CFG[3] origin:064-gtp-channel-conf 29_681 -GTP_CHANNEL_2.GTPE2.RXDLY_CFG[4] origin:064-gtp-channel-conf 28_682 -GTP_CHANNEL_2.GTPE2.RXDLY_CFG[5] origin:064-gtp-channel-conf 29_682 -GTP_CHANNEL_2.GTPE2.RXDLY_CFG[6] origin:064-gtp-channel-conf 28_683 -GTP_CHANNEL_2.GTPE2.RXDLY_CFG[7] origin:064-gtp-channel-conf 29_683 -GTP_CHANNEL_2.GTPE2.RXDLY_CFG[8] origin:064-gtp-channel-conf 28_684 -GTP_CHANNEL_2.GTPE2.RXDLY_CFG[9] origin:064-gtp-channel-conf 29_684 -GTP_CHANNEL_2.GTPE2.RXDLY_CFG[10] origin:064-gtp-channel-conf 28_685 -GTP_CHANNEL_2.GTPE2.RXDLY_CFG[11] origin:064-gtp-channel-conf 29_685 -GTP_CHANNEL_2.GTPE2.RXDLY_CFG[12] origin:064-gtp-channel-conf 28_686 -GTP_CHANNEL_2.GTPE2.RXDLY_CFG[13] origin:064-gtp-channel-conf 29_686 -GTP_CHANNEL_2.GTPE2.RXDLY_CFG[14] origin:064-gtp-channel-conf 28_687 -GTP_CHANNEL_2.GTPE2.RXDLY_CFG[15] origin:064-gtp-channel-conf 29_687 -GTP_CHANNEL_2.GTPE2.RXDLY_LCFG[0] origin:064-gtp-channel-conf 30_576 -GTP_CHANNEL_2.GTPE2.RXDLY_LCFG[1] origin:064-gtp-channel-conf 31_576 -GTP_CHANNEL_2.GTPE2.RXDLY_LCFG[2] origin:064-gtp-channel-conf 30_577 -GTP_CHANNEL_2.GTPE2.RXDLY_LCFG[3] origin:064-gtp-channel-conf 31_577 -GTP_CHANNEL_2.GTPE2.RXDLY_LCFG[4] origin:064-gtp-channel-conf 30_578 -GTP_CHANNEL_2.GTPE2.RXDLY_LCFG[5] origin:064-gtp-channel-conf 31_578 -GTP_CHANNEL_2.GTPE2.RXDLY_LCFG[6] origin:064-gtp-channel-conf 30_579 -GTP_CHANNEL_2.GTPE2.RXDLY_LCFG[7] origin:064-gtp-channel-conf 31_579 -GTP_CHANNEL_2.GTPE2.RXDLY_LCFG[8] origin:064-gtp-channel-conf 30_580 -GTP_CHANNEL_2.GTPE2.RXDLY_TAP_CFG[0] origin:064-gtp-channel-conf 28_672 -GTP_CHANNEL_2.GTPE2.RXDLY_TAP_CFG[1] origin:064-gtp-channel-conf 29_672 -GTP_CHANNEL_2.GTPE2.RXDLY_TAP_CFG[2] origin:064-gtp-channel-conf 28_673 -GTP_CHANNEL_2.GTPE2.RXDLY_TAP_CFG[3] origin:064-gtp-channel-conf 29_673 -GTP_CHANNEL_2.GTPE2.RXDLY_TAP_CFG[4] origin:064-gtp-channel-conf 28_674 -GTP_CHANNEL_2.GTPE2.RXDLY_TAP_CFG[5] origin:064-gtp-channel-conf 29_674 -GTP_CHANNEL_2.GTPE2.RXDLY_TAP_CFG[6] origin:064-gtp-channel-conf 28_675 -GTP_CHANNEL_2.GTPE2.RXDLY_TAP_CFG[7] origin:064-gtp-channel-conf 29_675 -GTP_CHANNEL_2.GTPE2.RXDLY_TAP_CFG[8] origin:064-gtp-channel-conf 28_676 -GTP_CHANNEL_2.GTPE2.RXDLY_TAP_CFG[9] origin:064-gtp-channel-conf 29_676 -GTP_CHANNEL_2.GTPE2.RXDLY_TAP_CFG[10] origin:064-gtp-channel-conf 28_677 -GTP_CHANNEL_2.GTPE2.RXDLY_TAP_CFG[11] origin:064-gtp-channel-conf 29_677 -GTP_CHANNEL_2.GTPE2.RXDLY_TAP_CFG[12] origin:064-gtp-channel-conf 28_678 -GTP_CHANNEL_2.GTPE2.RXDLY_TAP_CFG[13] origin:064-gtp-channel-conf 29_678 -GTP_CHANNEL_2.GTPE2.RXDLY_TAP_CFG[14] origin:064-gtp-channel-conf 28_679 -GTP_CHANNEL_2.GTPE2.RXDLY_TAP_CFG[15] origin:064-gtp-channel-conf 29_679 -GTP_CHANNEL_2.GTPE2.RXGEARBOX_EN origin:064-gtp-channel-conf 29_607 -GTP_CHANNEL_2.GTPE2.RXISCANRESET_TIME[0] origin:064-gtp-channel-conf 29_123 -GTP_CHANNEL_2.GTPE2.RXISCANRESET_TIME[1] origin:064-gtp-channel-conf 28_124 -GTP_CHANNEL_2.GTPE2.RXISCANRESET_TIME[2] origin:064-gtp-channel-conf 29_124 -GTP_CHANNEL_2.GTPE2.RXISCANRESET_TIME[3] origin:064-gtp-channel-conf 28_125 -GTP_CHANNEL_2.GTPE2.RXISCANRESET_TIME[4] origin:064-gtp-channel-conf 29_125 -GTP_CHANNEL_2.GTPE2.RXLPM_BIAS_STARTUP_DISABLE[0] origin:064-gtp-channel-conf 31_391 -GTP_CHANNEL_2.GTPE2.RXLPM_CFG[0] origin:064-gtp-channel-conf 30_328 -GTP_CHANNEL_2.GTPE2.RXLPM_CFG[1] origin:064-gtp-channel-conf 31_328 -GTP_CHANNEL_2.GTPE2.RXLPM_CFG[2] origin:064-gtp-channel-conf 30_329 -GTP_CHANNEL_2.GTPE2.RXLPM_CFG[3] origin:064-gtp-channel-conf 31_329 -GTP_CHANNEL_2.GTPE2.RXLPM_CM_CFG[0] origin:064-gtp-channel-conf 30_430 -GTP_CHANNEL_2.GTPE2.RXLPM_GC_CFG[0] origin:064-gtp-channel-conf 30_432 -GTP_CHANNEL_2.GTPE2.RXLPM_GC_CFG[1] origin:064-gtp-channel-conf 31_432 -GTP_CHANNEL_2.GTPE2.RXLPM_GC_CFG[2] origin:064-gtp-channel-conf 30_433 -GTP_CHANNEL_2.GTPE2.RXLPM_GC_CFG[3] origin:064-gtp-channel-conf 31_433 -GTP_CHANNEL_2.GTPE2.RXLPM_GC_CFG[4] origin:064-gtp-channel-conf 30_434 -GTP_CHANNEL_2.GTPE2.RXLPM_GC_CFG[5] origin:064-gtp-channel-conf 31_434 -GTP_CHANNEL_2.GTPE2.RXLPM_GC_CFG[6] origin:064-gtp-channel-conf 30_435 -GTP_CHANNEL_2.GTPE2.RXLPM_GC_CFG[7] origin:064-gtp-channel-conf 31_435 -GTP_CHANNEL_2.GTPE2.RXLPM_GC_CFG[8] origin:064-gtp-channel-conf 30_436 -GTP_CHANNEL_2.GTPE2.RXLPM_GC_CFG2[0] origin:064-gtp-channel-conf 31_442 -GTP_CHANNEL_2.GTPE2.RXLPM_GC_CFG2[1] origin:064-gtp-channel-conf 30_443 -GTP_CHANNEL_2.GTPE2.RXLPM_GC_CFG2[2] origin:064-gtp-channel-conf 31_443 -GTP_CHANNEL_2.GTPE2.RXLPM_HF_CFG[0] origin:064-gtp-channel-conf 28_336 -GTP_CHANNEL_2.GTPE2.RXLPM_HF_CFG[1] origin:064-gtp-channel-conf 29_336 -GTP_CHANNEL_2.GTPE2.RXLPM_HF_CFG[2] origin:064-gtp-channel-conf 28_337 -GTP_CHANNEL_2.GTPE2.RXLPM_HF_CFG[3] origin:064-gtp-channel-conf 29_337 -GTP_CHANNEL_2.GTPE2.RXLPM_HF_CFG[4] origin:064-gtp-channel-conf 28_338 -GTP_CHANNEL_2.GTPE2.RXLPM_HF_CFG[5] origin:064-gtp-channel-conf 29_338 -GTP_CHANNEL_2.GTPE2.RXLPM_HF_CFG[6] origin:064-gtp-channel-conf 28_339 -GTP_CHANNEL_2.GTPE2.RXLPM_HF_CFG[7] origin:064-gtp-channel-conf 29_339 -GTP_CHANNEL_2.GTPE2.RXLPM_HF_CFG[8] origin:064-gtp-channel-conf 28_340 -GTP_CHANNEL_2.GTPE2.RXLPM_HF_CFG[9] origin:064-gtp-channel-conf 29_340 -GTP_CHANNEL_2.GTPE2.RXLPM_HF_CFG[10] origin:064-gtp-channel-conf 28_341 -GTP_CHANNEL_2.GTPE2.RXLPM_HF_CFG[11] origin:064-gtp-channel-conf 29_341 -GTP_CHANNEL_2.GTPE2.RXLPM_HF_CFG[12] origin:064-gtp-channel-conf 28_342 -GTP_CHANNEL_2.GTPE2.RXLPM_HF_CFG[13] origin:064-gtp-channel-conf 29_342 -GTP_CHANNEL_2.GTPE2.RXLPM_HF_CFG2[0] origin:064-gtp-channel-conf 30_424 -GTP_CHANNEL_2.GTPE2.RXLPM_HF_CFG2[1] origin:064-gtp-channel-conf 31_424 -GTP_CHANNEL_2.GTPE2.RXLPM_HF_CFG2[2] origin:064-gtp-channel-conf 30_425 -GTP_CHANNEL_2.GTPE2.RXLPM_HF_CFG2[3] origin:064-gtp-channel-conf 31_425 -GTP_CHANNEL_2.GTPE2.RXLPM_HF_CFG2[4] origin:064-gtp-channel-conf 30_426 -GTP_CHANNEL_2.GTPE2.RXLPM_HF_CFG3[0] origin:064-gtp-channel-conf 31_389 -GTP_CHANNEL_2.GTPE2.RXLPM_HF_CFG3[1] origin:064-gtp-channel-conf 30_390 -GTP_CHANNEL_2.GTPE2.RXLPM_HF_CFG3[2] origin:064-gtp-channel-conf 31_390 -GTP_CHANNEL_2.GTPE2.RXLPM_HF_CFG3[3] origin:064-gtp-channel-conf 30_391 -GTP_CHANNEL_2.GTPE2.RXLPM_HOLD_DURING_EIDLE[0] origin:064-gtp-channel-conf 28_247 -GTP_CHANNEL_2.GTPE2.RXLPM_INCM_CFG[0] origin:064-gtp-channel-conf 30_439 -GTP_CHANNEL_2.GTPE2.RXLPM_IPCM_CFG[0] origin:064-gtp-channel-conf 31_439 -GTP_CHANNEL_2.GTPE2.RXLPM_LF_CFG[0] origin:064-gtp-channel-conf 28_344 -GTP_CHANNEL_2.GTPE2.RXLPM_LF_CFG[1] origin:064-gtp-channel-conf 29_344 -GTP_CHANNEL_2.GTPE2.RXLPM_LF_CFG[2] origin:064-gtp-channel-conf 28_345 -GTP_CHANNEL_2.GTPE2.RXLPM_LF_CFG[3] origin:064-gtp-channel-conf 29_345 -GTP_CHANNEL_2.GTPE2.RXLPM_LF_CFG[4] origin:064-gtp-channel-conf 28_346 -GTP_CHANNEL_2.GTPE2.RXLPM_LF_CFG[5] origin:064-gtp-channel-conf 29_346 -GTP_CHANNEL_2.GTPE2.RXLPM_LF_CFG[6] origin:064-gtp-channel-conf 28_347 -GTP_CHANNEL_2.GTPE2.RXLPM_LF_CFG[7] origin:064-gtp-channel-conf 29_347 -GTP_CHANNEL_2.GTPE2.RXLPM_LF_CFG[8] origin:064-gtp-channel-conf 28_348 -GTP_CHANNEL_2.GTPE2.RXLPM_LF_CFG[9] origin:064-gtp-channel-conf 29_348 -GTP_CHANNEL_2.GTPE2.RXLPM_LF_CFG[10] origin:064-gtp-channel-conf 28_349 -GTP_CHANNEL_2.GTPE2.RXLPM_LF_CFG[11] origin:064-gtp-channel-conf 29_349 -GTP_CHANNEL_2.GTPE2.RXLPM_LF_CFG[12] origin:064-gtp-channel-conf 28_350 -GTP_CHANNEL_2.GTPE2.RXLPM_LF_CFG[13] origin:064-gtp-channel-conf 29_350 -GTP_CHANNEL_2.GTPE2.RXLPM_LF_CFG[14] origin:064-gtp-channel-conf 28_351 -GTP_CHANNEL_2.GTPE2.RXLPM_LF_CFG[15] origin:064-gtp-channel-conf 29_351 -GTP_CHANNEL_2.GTPE2.RXLPM_LF_CFG[16] origin:064-gtp-channel-conf 28_343 -GTP_CHANNEL_2.GTPE2.RXLPM_LF_CFG[17] origin:064-gtp-channel-conf 29_343 -GTP_CHANNEL_2.GTPE2.RXLPM_LF_CFG2[0] origin:064-gtp-channel-conf 31_426 -GTP_CHANNEL_2.GTPE2.RXLPM_LF_CFG2[1] origin:064-gtp-channel-conf 30_427 -GTP_CHANNEL_2.GTPE2.RXLPM_LF_CFG2[2] origin:064-gtp-channel-conf 31_427 -GTP_CHANNEL_2.GTPE2.RXLPM_LF_CFG2[3] origin:064-gtp-channel-conf 30_428 -GTP_CHANNEL_2.GTPE2.RXLPM_LF_CFG2[4] origin:064-gtp-channel-conf 31_428 -GTP_CHANNEL_2.GTPE2.RXLPM_OSINT_CFG[0] origin:064-gtp-channel-conf 30_440 -GTP_CHANNEL_2.GTPE2.RXLPM_OSINT_CFG[1] origin:064-gtp-channel-conf 31_440 -GTP_CHANNEL_2.GTPE2.RXLPM_OSINT_CFG[2] origin:064-gtp-channel-conf 30_441 -GTP_CHANNEL_2.GTPE2.RXLPM_CFG1[0] origin:064-gtp-channel-conf 30_330 -GTP_CHANNEL_2.GTPE2.RXLPMRESET_TIME[0] origin:064-gtp-channel-conf 28_112 -GTP_CHANNEL_2.GTPE2.RXLPMRESET_TIME[1] origin:064-gtp-channel-conf 29_112 -GTP_CHANNEL_2.GTPE2.RXLPMRESET_TIME[2] origin:064-gtp-channel-conf 28_113 -GTP_CHANNEL_2.GTPE2.RXLPMRESET_TIME[3] origin:064-gtp-channel-conf 29_113 -GTP_CHANNEL_2.GTPE2.RXLPMRESET_TIME[4] origin:064-gtp-channel-conf 28_114 -GTP_CHANNEL_2.GTPE2.RXLPMRESET_TIME[5] origin:064-gtp-channel-conf 29_114 -GTP_CHANNEL_2.GTPE2.RXLPMRESET_TIME[6] origin:064-gtp-channel-conf 28_115 -GTP_CHANNEL_2.GTPE2.RXOOB_CFG[0] origin:064-gtp-channel-conf 28_144 -GTP_CHANNEL_2.GTPE2.RXOOB_CFG[1] origin:064-gtp-channel-conf 29_144 -GTP_CHANNEL_2.GTPE2.RXOOB_CFG[2] origin:064-gtp-channel-conf 28_145 -GTP_CHANNEL_2.GTPE2.RXOOB_CFG[3] origin:064-gtp-channel-conf 29_145 -GTP_CHANNEL_2.GTPE2.RXOOB_CFG[4] origin:064-gtp-channel-conf 28_146 -GTP_CHANNEL_2.GTPE2.RXOOB_CFG[5] origin:064-gtp-channel-conf 29_146 -GTP_CHANNEL_2.GTPE2.RXOOB_CFG[6] origin:064-gtp-channel-conf 28_147 -GTP_CHANNEL_2.GTPE2.RXOOB_CLK_CFG.FABRIC origin:064-gtp-channel-conf 31_129 -GTP_CHANNEL_2.GTPE2.RXOSCALRESET_TIME[0] origin:064-gtp-channel-conf 28_187 -GTP_CHANNEL_2.GTPE2.RXOSCALRESET_TIME[1] origin:064-gtp-channel-conf 29_187 -GTP_CHANNEL_2.GTPE2.RXOSCALRESET_TIME[2] origin:064-gtp-channel-conf 28_188 -GTP_CHANNEL_2.GTPE2.RXOSCALRESET_TIME[3] origin:064-gtp-channel-conf 29_188 -GTP_CHANNEL_2.GTPE2.RXOSCALRESET_TIME[4] origin:064-gtp-channel-conf 28_189 -GTP_CHANNEL_2.GTPE2.RXOSCALRESET_TIMEOUT[0] origin:064-gtp-channel-conf 29_189 -GTP_CHANNEL_2.GTPE2.RXOSCALRESET_TIMEOUT[1] origin:064-gtp-channel-conf 28_190 -GTP_CHANNEL_2.GTPE2.RXOSCALRESET_TIMEOUT[2] origin:064-gtp-channel-conf 29_190 -GTP_CHANNEL_2.GTPE2.RXOSCALRESET_TIMEOUT[3] origin:064-gtp-channel-conf 28_191 -GTP_CHANNEL_2.GTPE2.RXOSCALRESET_TIMEOUT[4] origin:064-gtp-channel-conf 29_191 -GTP_CHANNEL_2.GTPE2.RXOUT_DIV[0] origin:064-gtp-channel-conf 30_384 -GTP_CHANNEL_2.GTPE2.RXOUT_DIV[1] origin:064-gtp-channel-conf 31_384 -GTP_CHANNEL_2.GTPE2.RXPCSRESET_TIME[0] origin:064-gtp-channel-conf 29_115 -GTP_CHANNEL_2.GTPE2.RXPCSRESET_TIME[1] origin:064-gtp-channel-conf 28_116 -GTP_CHANNEL_2.GTPE2.RXPCSRESET_TIME[2] origin:064-gtp-channel-conf 29_116 -GTP_CHANNEL_2.GTPE2.RXPCSRESET_TIME[3] origin:064-gtp-channel-conf 28_117 -GTP_CHANNEL_2.GTPE2.RXPCSRESET_TIME[4] origin:064-gtp-channel-conf 29_117 -GTP_CHANNEL_2.GTPE2.RXPH_CFG[0] origin:064-gtp-channel-conf 30_584 -GTP_CHANNEL_2.GTPE2.RXPH_CFG[1] origin:064-gtp-channel-conf 31_584 -GTP_CHANNEL_2.GTPE2.RXPH_CFG[2] origin:064-gtp-channel-conf 30_585 -GTP_CHANNEL_2.GTPE2.RXPH_CFG[3] origin:064-gtp-channel-conf 31_585 -GTP_CHANNEL_2.GTPE2.RXPH_CFG[4] origin:064-gtp-channel-conf 30_586 -GTP_CHANNEL_2.GTPE2.RXPH_CFG[5] origin:064-gtp-channel-conf 31_586 -GTP_CHANNEL_2.GTPE2.RXPH_CFG[6] origin:064-gtp-channel-conf 30_587 -GTP_CHANNEL_2.GTPE2.RXPH_CFG[7] origin:064-gtp-channel-conf 31_587 -GTP_CHANNEL_2.GTPE2.RXPH_CFG[8] origin:064-gtp-channel-conf 30_588 -GTP_CHANNEL_2.GTPE2.RXPH_CFG[9] origin:064-gtp-channel-conf 31_588 -GTP_CHANNEL_2.GTPE2.RXPH_CFG[10] origin:064-gtp-channel-conf 30_589 -GTP_CHANNEL_2.GTPE2.RXPH_CFG[11] origin:064-gtp-channel-conf 31_589 -GTP_CHANNEL_2.GTPE2.RXPH_CFG[12] origin:064-gtp-channel-conf 30_590 -GTP_CHANNEL_2.GTPE2.RXPH_CFG[13] origin:064-gtp-channel-conf 31_590 -GTP_CHANNEL_2.GTPE2.RXPH_CFG[14] origin:064-gtp-channel-conf 30_591 -GTP_CHANNEL_2.GTPE2.RXPH_CFG[15] origin:064-gtp-channel-conf 31_591 -GTP_CHANNEL_2.GTPE2.RXPH_CFG[16] origin:064-gtp-channel-conf 30_592 -GTP_CHANNEL_2.GTPE2.RXPH_CFG[17] origin:064-gtp-channel-conf 31_592 -GTP_CHANNEL_2.GTPE2.RXPH_CFG[18] origin:064-gtp-channel-conf 30_593 -GTP_CHANNEL_2.GTPE2.RXPH_CFG[19] origin:064-gtp-channel-conf 31_593 -GTP_CHANNEL_2.GTPE2.RXPH_CFG[20] origin:064-gtp-channel-conf 30_594 -GTP_CHANNEL_2.GTPE2.RXPH_CFG[21] origin:064-gtp-channel-conf 31_594 -GTP_CHANNEL_2.GTPE2.RXPH_CFG[22] origin:064-gtp-channel-conf 30_595 -GTP_CHANNEL_2.GTPE2.RXPH_CFG[23] origin:064-gtp-channel-conf 31_595 -GTP_CHANNEL_2.GTPE2.RXPH_MONITOR_SEL[0] origin:064-gtp-channel-conf 28_700 -GTP_CHANNEL_2.GTPE2.RXPH_MONITOR_SEL[1] origin:064-gtp-channel-conf 29_700 -GTP_CHANNEL_2.GTPE2.RXPH_MONITOR_SEL[2] origin:064-gtp-channel-conf 28_701 -GTP_CHANNEL_2.GTPE2.RXPH_MONITOR_SEL[3] origin:064-gtp-channel-conf 29_701 -GTP_CHANNEL_2.GTPE2.RXPH_MONITOR_SEL[4] origin:064-gtp-channel-conf 28_702 -GTP_CHANNEL_2.GTPE2.RXPHDLY_CFG[0] origin:064-gtp-channel-conf 30_600 -GTP_CHANNEL_2.GTPE2.RXPHDLY_CFG[1] origin:064-gtp-channel-conf 31_600 -GTP_CHANNEL_2.GTPE2.RXPHDLY_CFG[2] origin:064-gtp-channel-conf 30_601 -GTP_CHANNEL_2.GTPE2.RXPHDLY_CFG[3] origin:064-gtp-channel-conf 31_601 -GTP_CHANNEL_2.GTPE2.RXPHDLY_CFG[4] origin:064-gtp-channel-conf 30_602 -GTP_CHANNEL_2.GTPE2.RXPHDLY_CFG[5] origin:064-gtp-channel-conf 31_602 -GTP_CHANNEL_2.GTPE2.RXPHDLY_CFG[6] origin:064-gtp-channel-conf 30_603 -GTP_CHANNEL_2.GTPE2.RXPHDLY_CFG[7] origin:064-gtp-channel-conf 31_603 -GTP_CHANNEL_2.GTPE2.RXPHDLY_CFG[8] origin:064-gtp-channel-conf 30_604 -GTP_CHANNEL_2.GTPE2.RXPHDLY_CFG[9] origin:064-gtp-channel-conf 31_604 -GTP_CHANNEL_2.GTPE2.RXPHDLY_CFG[10] origin:064-gtp-channel-conf 30_605 -GTP_CHANNEL_2.GTPE2.RXPHDLY_CFG[11] origin:064-gtp-channel-conf 31_605 -GTP_CHANNEL_2.GTPE2.RXPHDLY_CFG[12] origin:064-gtp-channel-conf 30_606 -GTP_CHANNEL_2.GTPE2.RXPHDLY_CFG[13] origin:064-gtp-channel-conf 31_606 -GTP_CHANNEL_2.GTPE2.RXPHDLY_CFG[14] origin:064-gtp-channel-conf 30_607 -GTP_CHANNEL_2.GTPE2.RXPHDLY_CFG[15] origin:064-gtp-channel-conf 31_607 -GTP_CHANNEL_2.GTPE2.RXPHDLY_CFG[16] origin:064-gtp-channel-conf 30_608 -GTP_CHANNEL_2.GTPE2.RXPHDLY_CFG[17] origin:064-gtp-channel-conf 31_608 -GTP_CHANNEL_2.GTPE2.RXPHDLY_CFG[18] origin:064-gtp-channel-conf 30_609 -GTP_CHANNEL_2.GTPE2.RXPHDLY_CFG[19] origin:064-gtp-channel-conf 31_609 -GTP_CHANNEL_2.GTPE2.RXPHDLY_CFG[20] origin:064-gtp-channel-conf 30_610 -GTP_CHANNEL_2.GTPE2.RXPHDLY_CFG[21] origin:064-gtp-channel-conf 31_610 -GTP_CHANNEL_2.GTPE2.RXPHDLY_CFG[22] origin:064-gtp-channel-conf 30_611 -GTP_CHANNEL_2.GTPE2.RXPHDLY_CFG[23] origin:064-gtp-channel-conf 31_611 -GTP_CHANNEL_2.GTPE2.RXPI_CFG0[0] origin:064-gtp-channel-conf 31_430 -GTP_CHANNEL_2.GTPE2.RXPI_CFG0[1] origin:064-gtp-channel-conf 30_431 -GTP_CHANNEL_2.GTPE2.RXPI_CFG0[2] origin:064-gtp-channel-conf 31_431 -GTP_CHANNEL_2.GTPE2.RXPI_CFG1[0] origin:064-gtp-channel-conf 30_442 -GTP_CHANNEL_2.GTPE2.RXPI_CFG2[0] origin:064-gtp-channel-conf 31_441 -GTP_CHANNEL_2.GTPE2.RXPMARESET_TIME[0] origin:064-gtp-channel-conf 28_104 -GTP_CHANNEL_2.GTPE2.RXPMARESET_TIME[1] origin:064-gtp-channel-conf 29_104 -GTP_CHANNEL_2.GTPE2.RXPMARESET_TIME[2] origin:064-gtp-channel-conf 28_105 -GTP_CHANNEL_2.GTPE2.RXPMARESET_TIME[3] origin:064-gtp-channel-conf 29_105 -GTP_CHANNEL_2.GTPE2.RXPMARESET_TIME[4] origin:064-gtp-channel-conf 28_106 -GTP_CHANNEL_2.GTPE2.RXPRBS_ERR_LOOPBACK[0] origin:064-gtp-channel-conf 28_136 -GTP_CHANNEL_2.GTPE2.RXSLIDE_AUTO_WAIT[0] origin:064-gtp-channel-conf 28_520 -GTP_CHANNEL_2.GTPE2.RXSLIDE_AUTO_WAIT[1] origin:064-gtp-channel-conf 29_520 -GTP_CHANNEL_2.GTPE2.RXSLIDE_AUTO_WAIT[2] origin:064-gtp-channel-conf 28_521 -GTP_CHANNEL_2.GTPE2.RXSLIDE_AUTO_WAIT[3] origin:064-gtp-channel-conf 29_521 -GTP_CHANNEL_2.GTPE2.RXSLIDE_MODE.AUTO origin:064-gtp-channel-conf !29_519 28_519 -GTP_CHANNEL_2.GTPE2.RXSLIDE_MODE.PCS origin:064-gtp-channel-conf !28_519 29_519 -GTP_CHANNEL_2.GTPE2.RXSLIDE_MODE.PMA origin:064-gtp-channel-conf 28_519 29_519 -GTP_CHANNEL_2.GTPE2.RXSYNC_MULTILANE[0] origin:064-gtp-channel-conf 28_133 -GTP_CHANNEL_2.GTPE2.RXSYNC_OVRD[0] origin:064-gtp-channel-conf 29_135 -GTP_CHANNEL_2.GTPE2.RXSYNC_SKIP_DA[0] origin:064-gtp-channel-conf 29_134 -GTP_CHANNEL_2.GTPE2.SAS_MAX_COM[0] origin:064-gtp-channel-conf 28_171 -GTP_CHANNEL_2.GTPE2.SAS_MAX_COM[1] origin:064-gtp-channel-conf 29_171 -GTP_CHANNEL_2.GTPE2.SAS_MAX_COM[2] origin:064-gtp-channel-conf 28_172 -GTP_CHANNEL_2.GTPE2.SAS_MAX_COM[3] origin:064-gtp-channel-conf 29_172 -GTP_CHANNEL_2.GTPE2.SAS_MAX_COM[4] origin:064-gtp-channel-conf 28_173 -GTP_CHANNEL_2.GTPE2.SAS_MAX_COM[5] origin:064-gtp-channel-conf 29_173 -GTP_CHANNEL_2.GTPE2.SAS_MAX_COM[6] origin:064-gtp-channel-conf 28_174 -GTP_CHANNEL_2.GTPE2.SAS_MIN_COM[0] origin:064-gtp-channel-conf 29_156 -GTP_CHANNEL_2.GTPE2.SAS_MIN_COM[1] origin:064-gtp-channel-conf 28_157 -GTP_CHANNEL_2.GTPE2.SAS_MIN_COM[2] origin:064-gtp-channel-conf 29_157 -GTP_CHANNEL_2.GTPE2.SAS_MIN_COM[3] origin:064-gtp-channel-conf 28_158 -GTP_CHANNEL_2.GTPE2.SAS_MIN_COM[4] origin:064-gtp-channel-conf 29_158 -GTP_CHANNEL_2.GTPE2.SAS_MIN_COM[5] origin:064-gtp-channel-conf 28_159 -GTP_CHANNEL_2.GTPE2.SATA_BURST_SEQ_LEN[0] origin:064-gtp-channel-conf 28_150 -GTP_CHANNEL_2.GTPE2.SATA_BURST_SEQ_LEN[1] origin:064-gtp-channel-conf 29_150 -GTP_CHANNEL_2.GTPE2.SATA_BURST_SEQ_LEN[2] origin:064-gtp-channel-conf 28_151 -GTP_CHANNEL_2.GTPE2.SATA_BURST_SEQ_LEN[3] origin:064-gtp-channel-conf 29_151 -GTP_CHANNEL_2.GTPE2.SATA_BURST_VAL[0] origin:064-gtp-channel-conf 29_147 -GTP_CHANNEL_2.GTPE2.SATA_BURST_VAL[1] origin:064-gtp-channel-conf 28_148 -GTP_CHANNEL_2.GTPE2.SATA_BURST_VAL[2] origin:064-gtp-channel-conf 29_148 -GTP_CHANNEL_2.GTPE2.SATA_EIDLE_VAL[0] origin:064-gtp-channel-conf 28_152 -GTP_CHANNEL_2.GTPE2.SATA_EIDLE_VAL[1] origin:064-gtp-channel-conf 29_152 -GTP_CHANNEL_2.GTPE2.SATA_EIDLE_VAL[2] origin:064-gtp-channel-conf 28_153 -GTP_CHANNEL_2.GTPE2.SATA_MAX_BURST[0] origin:064-gtp-channel-conf 28_168 -GTP_CHANNEL_2.GTPE2.SATA_MAX_BURST[1] origin:064-gtp-channel-conf 29_168 -GTP_CHANNEL_2.GTPE2.SATA_MAX_BURST[2] origin:064-gtp-channel-conf 28_169 -GTP_CHANNEL_2.GTPE2.SATA_MAX_BURST[3] origin:064-gtp-channel-conf 29_169 -GTP_CHANNEL_2.GTPE2.SATA_MAX_BURST[4] origin:064-gtp-channel-conf 28_170 -GTP_CHANNEL_2.GTPE2.SATA_MAX_BURST[5] origin:064-gtp-channel-conf 29_170 -GTP_CHANNEL_2.GTPE2.SATA_MAX_INIT[0] origin:064-gtp-channel-conf 28_176 -GTP_CHANNEL_2.GTPE2.SATA_MAX_INIT[1] origin:064-gtp-channel-conf 29_176 -GTP_CHANNEL_2.GTPE2.SATA_MAX_INIT[2] origin:064-gtp-channel-conf 28_177 -GTP_CHANNEL_2.GTPE2.SATA_MAX_INIT[3] origin:064-gtp-channel-conf 29_177 -GTP_CHANNEL_2.GTPE2.SATA_MAX_INIT[4] origin:064-gtp-channel-conf 28_178 -GTP_CHANNEL_2.GTPE2.SATA_MAX_INIT[5] origin:064-gtp-channel-conf 29_178 -GTP_CHANNEL_2.GTPE2.SATA_MAX_WAKE[0] origin:064-gtp-channel-conf 28_179 -GTP_CHANNEL_2.GTPE2.SATA_MAX_WAKE[1] origin:064-gtp-channel-conf 29_179 -GTP_CHANNEL_2.GTPE2.SATA_MAX_WAKE[2] origin:064-gtp-channel-conf 28_180 -GTP_CHANNEL_2.GTPE2.SATA_MAX_WAKE[3] origin:064-gtp-channel-conf 29_180 -GTP_CHANNEL_2.GTPE2.SATA_MAX_WAKE[4] origin:064-gtp-channel-conf 28_181 -GTP_CHANNEL_2.GTPE2.SATA_MAX_WAKE[5] origin:064-gtp-channel-conf 29_181 -GTP_CHANNEL_2.GTPE2.SATA_MIN_BURST[0] origin:064-gtp-channel-conf 29_153 -GTP_CHANNEL_2.GTPE2.SATA_MIN_BURST[1] origin:064-gtp-channel-conf 28_154 -GTP_CHANNEL_2.GTPE2.SATA_MIN_BURST[2] origin:064-gtp-channel-conf 29_154 -GTP_CHANNEL_2.GTPE2.SATA_MIN_BURST[3] origin:064-gtp-channel-conf 28_155 -GTP_CHANNEL_2.GTPE2.SATA_MIN_BURST[4] origin:064-gtp-channel-conf 29_155 -GTP_CHANNEL_2.GTPE2.SATA_MIN_BURST[5] origin:064-gtp-channel-conf 28_156 -GTP_CHANNEL_2.GTPE2.SATA_MIN_INIT[0] origin:064-gtp-channel-conf 28_160 -GTP_CHANNEL_2.GTPE2.SATA_MIN_INIT[1] origin:064-gtp-channel-conf 29_160 -GTP_CHANNEL_2.GTPE2.SATA_MIN_INIT[2] origin:064-gtp-channel-conf 28_161 -GTP_CHANNEL_2.GTPE2.SATA_MIN_INIT[3] origin:064-gtp-channel-conf 29_161 -GTP_CHANNEL_2.GTPE2.SATA_MIN_INIT[4] origin:064-gtp-channel-conf 28_162 -GTP_CHANNEL_2.GTPE2.SATA_MIN_INIT[5] origin:064-gtp-channel-conf 29_162 -GTP_CHANNEL_2.GTPE2.SATA_MIN_WAKE[0] origin:064-gtp-channel-conf 28_163 -GTP_CHANNEL_2.GTPE2.SATA_MIN_WAKE[1] origin:064-gtp-channel-conf 29_163 -GTP_CHANNEL_2.GTPE2.SATA_MIN_WAKE[2] origin:064-gtp-channel-conf 28_164 -GTP_CHANNEL_2.GTPE2.SATA_MIN_WAKE[3] origin:064-gtp-channel-conf 29_164 -GTP_CHANNEL_2.GTPE2.SATA_MIN_WAKE[4] origin:064-gtp-channel-conf 28_165 -GTP_CHANNEL_2.GTPE2.SATA_MIN_WAKE[5] origin:064-gtp-channel-conf 29_165 -GTP_CHANNEL_2.GTPE2.SATA_PLL_CFG.VCO_1500MHZ origin:064-gtp-channel-conf 30_55 -GTP_CHANNEL_2.GTPE2.SATA_PLL_CFG.VCO_750MHZ origin:064-gtp-channel-conf 31_55 -GTP_CHANNEL_2.GTPE2.SHOW_REALIGN_COMMA origin:064-gtp-channel-conf 29_522 -GTP_CHANNEL_2.GTPE2.TERM_RCAL_CFG[0] origin:064-gtp-channel-conf 30_136 -GTP_CHANNEL_2.GTPE2.TERM_RCAL_CFG[1] origin:064-gtp-channel-conf 31_136 -GTP_CHANNEL_2.GTPE2.TERM_RCAL_CFG[2] origin:064-gtp-channel-conf 30_137 -GTP_CHANNEL_2.GTPE2.TERM_RCAL_CFG[3] origin:064-gtp-channel-conf 31_137 -GTP_CHANNEL_2.GTPE2.TERM_RCAL_CFG[4] origin:064-gtp-channel-conf 30_138 -GTP_CHANNEL_2.GTPE2.TERM_RCAL_CFG[5] origin:064-gtp-channel-conf 31_138 -GTP_CHANNEL_2.GTPE2.TERM_RCAL_CFG[6] origin:064-gtp-channel-conf 30_139 -GTP_CHANNEL_2.GTPE2.TERM_RCAL_CFG[7] origin:064-gtp-channel-conf 31_139 -GTP_CHANNEL_2.GTPE2.TERM_RCAL_CFG[8] origin:064-gtp-channel-conf 30_140 -GTP_CHANNEL_2.GTPE2.TERM_RCAL_CFG[9] origin:064-gtp-channel-conf 31_140 -GTP_CHANNEL_2.GTPE2.TERM_RCAL_CFG[10] origin:064-gtp-channel-conf 30_141 -GTP_CHANNEL_2.GTPE2.TERM_RCAL_CFG[11] origin:064-gtp-channel-conf 31_141 -GTP_CHANNEL_2.GTPE2.TERM_RCAL_CFG[12] origin:064-gtp-channel-conf 30_142 -GTP_CHANNEL_2.GTPE2.TERM_RCAL_CFG[13] origin:064-gtp-channel-conf 31_142 -GTP_CHANNEL_2.GTPE2.TERM_RCAL_CFG[14] origin:064-gtp-channel-conf 30_143 -GTP_CHANNEL_2.GTPE2.TERM_RCAL_OVRD[0] origin:064-gtp-channel-conf 31_150 -GTP_CHANNEL_2.GTPE2.TERM_RCAL_OVRD[1] origin:064-gtp-channel-conf 30_151 -GTP_CHANNEL_2.GTPE2.TERM_RCAL_OVRD[2] origin:064-gtp-channel-conf 31_151 -GTP_CHANNEL_2.GTPE2.TRANS_TIME_RATE[0] origin:064-gtp-channel-conf 28_192 -GTP_CHANNEL_2.GTPE2.TRANS_TIME_RATE[1] origin:064-gtp-channel-conf 29_192 -GTP_CHANNEL_2.GTPE2.TRANS_TIME_RATE[2] origin:064-gtp-channel-conf 28_193 -GTP_CHANNEL_2.GTPE2.TRANS_TIME_RATE[3] origin:064-gtp-channel-conf 29_193 -GTP_CHANNEL_2.GTPE2.TRANS_TIME_RATE[4] origin:064-gtp-channel-conf 28_194 -GTP_CHANNEL_2.GTPE2.TRANS_TIME_RATE[5] origin:064-gtp-channel-conf 29_194 -GTP_CHANNEL_2.GTPE2.TRANS_TIME_RATE[6] origin:064-gtp-channel-conf 28_195 -GTP_CHANNEL_2.GTPE2.TRANS_TIME_RATE[7] origin:064-gtp-channel-conf 29_195 -GTP_CHANNEL_2.GTPE2.TST_RSV[0] origin:064-gtp-channel-conf 30_504 -GTP_CHANNEL_2.GTPE2.TST_RSV[1] origin:064-gtp-channel-conf 31_504 -GTP_CHANNEL_2.GTPE2.TST_RSV[2] origin:064-gtp-channel-conf 30_505 -GTP_CHANNEL_2.GTPE2.TST_RSV[3] origin:064-gtp-channel-conf 31_505 -GTP_CHANNEL_2.GTPE2.TST_RSV[4] origin:064-gtp-channel-conf 30_506 -GTP_CHANNEL_2.GTPE2.TST_RSV[5] origin:064-gtp-channel-conf 31_506 -GTP_CHANNEL_2.GTPE2.TST_RSV[6] origin:064-gtp-channel-conf 30_507 -GTP_CHANNEL_2.GTPE2.TST_RSV[7] origin:064-gtp-channel-conf 31_507 -GTP_CHANNEL_2.GTPE2.TST_RSV[8] origin:064-gtp-channel-conf 30_508 -GTP_CHANNEL_2.GTPE2.TST_RSV[9] origin:064-gtp-channel-conf 31_508 -GTP_CHANNEL_2.GTPE2.TST_RSV[10] origin:064-gtp-channel-conf 30_509 -GTP_CHANNEL_2.GTPE2.TST_RSV[11] origin:064-gtp-channel-conf 31_509 -GTP_CHANNEL_2.GTPE2.TST_RSV[12] origin:064-gtp-channel-conf 30_510 -GTP_CHANNEL_2.GTPE2.TST_RSV[13] origin:064-gtp-channel-conf 31_510 -GTP_CHANNEL_2.GTPE2.TST_RSV[14] origin:064-gtp-channel-conf 30_511 -GTP_CHANNEL_2.GTPE2.TST_RSV[15] origin:064-gtp-channel-conf 31_511 -GTP_CHANNEL_2.GTPE2.TST_RSV[16] origin:064-gtp-channel-conf 30_512 -GTP_CHANNEL_2.GTPE2.TST_RSV[17] origin:064-gtp-channel-conf 31_512 -GTP_CHANNEL_2.GTPE2.TST_RSV[18] origin:064-gtp-channel-conf 30_513 -GTP_CHANNEL_2.GTPE2.TST_RSV[19] origin:064-gtp-channel-conf 31_513 -GTP_CHANNEL_2.GTPE2.TST_RSV[20] origin:064-gtp-channel-conf 30_514 -GTP_CHANNEL_2.GTPE2.TST_RSV[21] origin:064-gtp-channel-conf 31_514 -GTP_CHANNEL_2.GTPE2.TST_RSV[22] origin:064-gtp-channel-conf 30_515 -GTP_CHANNEL_2.GTPE2.TST_RSV[23] origin:064-gtp-channel-conf 31_515 -GTP_CHANNEL_2.GTPE2.TST_RSV[24] origin:064-gtp-channel-conf 30_516 -GTP_CHANNEL_2.GTPE2.TST_RSV[25] origin:064-gtp-channel-conf 31_516 -GTP_CHANNEL_2.GTPE2.TST_RSV[26] origin:064-gtp-channel-conf 30_517 -GTP_CHANNEL_2.GTPE2.TST_RSV[27] origin:064-gtp-channel-conf 31_517 -GTP_CHANNEL_2.GTPE2.TST_RSV[28] origin:064-gtp-channel-conf 30_518 -GTP_CHANNEL_2.GTPE2.TST_RSV[29] origin:064-gtp-channel-conf 31_518 -GTP_CHANNEL_2.GTPE2.TST_RSV[30] origin:064-gtp-channel-conf 30_519 -GTP_CHANNEL_2.GTPE2.TST_RSV[31] origin:064-gtp-channel-conf 31_519 -GTP_CHANNEL_2.GTPE2.TX_CLKMUX_EN[0] origin:064-gtp-channel-conf 31_128 -GTP_CHANNEL_2.GTPE2.TX_DATA_WIDTH[0] origin:064-gtp-channel-conf 30_152 -GTP_CHANNEL_2.GTPE2.TX_DATA_WIDTH[1] origin:064-gtp-channel-conf 31_152 -GTP_CHANNEL_2.GTPE2.TX_DATA_WIDTH[2] origin:064-gtp-channel-conf 30_153 -GTP_CHANNEL_2.GTPE2.TX_DRIVE_MODE.PIPE origin:064-gtp-channel-conf 28_200 -GTP_CHANNEL_2.GTPE2.TX_EIDLE_ASSERT_DELAY[0] origin:064-gtp-channel-conf 28_203 -GTP_CHANNEL_2.GTPE2.TX_EIDLE_ASSERT_DELAY[1] origin:064-gtp-channel-conf 29_203 -GTP_CHANNEL_2.GTPE2.TX_EIDLE_ASSERT_DELAY[2] origin:064-gtp-channel-conf 28_204 -GTP_CHANNEL_2.GTPE2.TX_EIDLE_DEASSERT_DELAY[0] origin:064-gtp-channel-conf 29_204 -GTP_CHANNEL_2.GTPE2.TX_EIDLE_DEASSERT_DELAY[1] origin:064-gtp-channel-conf 28_205 -GTP_CHANNEL_2.GTPE2.TX_EIDLE_DEASSERT_DELAY[2] origin:064-gtp-channel-conf 29_205 -GTP_CHANNEL_2.GTPE2.TX_LOOPBACK_DRIVE_HIZ origin:064-gtp-channel-conf 29_202 -GTP_CHANNEL_2.GTPE2.TX_MAINCURSOR_SEL[0] origin:064-gtp-channel-conf 31_289 -GTP_CHANNEL_2.GTPE2.TX_MARGIN_FULL_0[0] origin:064-gtp-channel-conf 30_232 -GTP_CHANNEL_2.GTPE2.TX_MARGIN_FULL_0[1] origin:064-gtp-channel-conf 31_232 -GTP_CHANNEL_2.GTPE2.TX_MARGIN_FULL_0[2] origin:064-gtp-channel-conf 30_233 -GTP_CHANNEL_2.GTPE2.TX_MARGIN_FULL_0[3] origin:064-gtp-channel-conf 31_233 -GTP_CHANNEL_2.GTPE2.TX_MARGIN_FULL_0[4] origin:064-gtp-channel-conf 30_234 -GTP_CHANNEL_2.GTPE2.TX_MARGIN_FULL_0[5] origin:064-gtp-channel-conf 31_234 -GTP_CHANNEL_2.GTPE2.TX_MARGIN_FULL_0[6] origin:064-gtp-channel-conf 30_235 -GTP_CHANNEL_2.GTPE2.TX_MARGIN_FULL_1[0] origin:064-gtp-channel-conf 30_236 -GTP_CHANNEL_2.GTPE2.TX_MARGIN_FULL_1[1] origin:064-gtp-channel-conf 31_236 -GTP_CHANNEL_2.GTPE2.TX_MARGIN_FULL_1[2] origin:064-gtp-channel-conf 30_237 -GTP_CHANNEL_2.GTPE2.TX_MARGIN_FULL_1[3] origin:064-gtp-channel-conf 31_237 -GTP_CHANNEL_2.GTPE2.TX_MARGIN_FULL_1[4] origin:064-gtp-channel-conf 30_238 -GTP_CHANNEL_2.GTPE2.TX_MARGIN_FULL_1[5] origin:064-gtp-channel-conf 31_238 -GTP_CHANNEL_2.GTPE2.TX_MARGIN_FULL_1[6] origin:064-gtp-channel-conf 30_239 -GTP_CHANNEL_2.GTPE2.TX_MARGIN_FULL_2[0] origin:064-gtp-channel-conf 30_240 -GTP_CHANNEL_2.GTPE2.TX_MARGIN_FULL_2[1] origin:064-gtp-channel-conf 31_240 -GTP_CHANNEL_2.GTPE2.TX_MARGIN_FULL_2[2] origin:064-gtp-channel-conf 30_241 -GTP_CHANNEL_2.GTPE2.TX_MARGIN_FULL_2[3] origin:064-gtp-channel-conf 31_241 -GTP_CHANNEL_2.GTPE2.TX_MARGIN_FULL_2[4] origin:064-gtp-channel-conf 30_242 -GTP_CHANNEL_2.GTPE2.TX_MARGIN_FULL_2[5] origin:064-gtp-channel-conf 31_242 -GTP_CHANNEL_2.GTPE2.TX_MARGIN_FULL_2[6] origin:064-gtp-channel-conf 30_243 -GTP_CHANNEL_2.GTPE2.TX_MARGIN_FULL_3[0] origin:064-gtp-channel-conf 30_244 -GTP_CHANNEL_2.GTPE2.TX_MARGIN_FULL_3[1] origin:064-gtp-channel-conf 31_244 -GTP_CHANNEL_2.GTPE2.TX_MARGIN_FULL_3[2] origin:064-gtp-channel-conf 30_245 -GTP_CHANNEL_2.GTPE2.TX_MARGIN_FULL_3[3] origin:064-gtp-channel-conf 31_245 -GTP_CHANNEL_2.GTPE2.TX_MARGIN_FULL_3[4] origin:064-gtp-channel-conf 30_246 -GTP_CHANNEL_2.GTPE2.TX_MARGIN_FULL_3[5] origin:064-gtp-channel-conf 31_246 -GTP_CHANNEL_2.GTPE2.TX_MARGIN_FULL_3[6] origin:064-gtp-channel-conf 30_247 -GTP_CHANNEL_2.GTPE2.TX_MARGIN_FULL_4[0] origin:064-gtp-channel-conf 30_248 -GTP_CHANNEL_2.GTPE2.TX_MARGIN_FULL_4[1] origin:064-gtp-channel-conf 31_248 -GTP_CHANNEL_2.GTPE2.TX_MARGIN_FULL_4[2] origin:064-gtp-channel-conf 30_249 -GTP_CHANNEL_2.GTPE2.TX_MARGIN_FULL_4[3] origin:064-gtp-channel-conf 31_249 -GTP_CHANNEL_2.GTPE2.TX_MARGIN_FULL_4[4] origin:064-gtp-channel-conf 30_250 -GTP_CHANNEL_2.GTPE2.TX_MARGIN_FULL_4[5] origin:064-gtp-channel-conf 31_250 -GTP_CHANNEL_2.GTPE2.TX_MARGIN_FULL_4[6] origin:064-gtp-channel-conf 30_251 -GTP_CHANNEL_2.GTPE2.TX_MARGIN_LOW_0[0] origin:064-gtp-channel-conf 30_252 -GTP_CHANNEL_2.GTPE2.TX_MARGIN_LOW_0[1] origin:064-gtp-channel-conf 31_252 -GTP_CHANNEL_2.GTPE2.TX_MARGIN_LOW_0[2] origin:064-gtp-channel-conf 30_253 -GTP_CHANNEL_2.GTPE2.TX_MARGIN_LOW_0[3] origin:064-gtp-channel-conf 31_253 -GTP_CHANNEL_2.GTPE2.TX_MARGIN_LOW_0[4] origin:064-gtp-channel-conf 30_254 -GTP_CHANNEL_2.GTPE2.TX_MARGIN_LOW_0[5] origin:064-gtp-channel-conf 31_254 -GTP_CHANNEL_2.GTPE2.TX_MARGIN_LOW_0[6] origin:064-gtp-channel-conf 30_255 -GTP_CHANNEL_2.GTPE2.TX_MARGIN_LOW_1[0] origin:064-gtp-channel-conf 30_256 -GTP_CHANNEL_2.GTPE2.TX_MARGIN_LOW_1[1] origin:064-gtp-channel-conf 31_256 -GTP_CHANNEL_2.GTPE2.TX_MARGIN_LOW_1[2] origin:064-gtp-channel-conf 30_257 -GTP_CHANNEL_2.GTPE2.TX_MARGIN_LOW_1[3] origin:064-gtp-channel-conf 31_257 -GTP_CHANNEL_2.GTPE2.TX_MARGIN_LOW_1[4] origin:064-gtp-channel-conf 30_258 -GTP_CHANNEL_2.GTPE2.TX_MARGIN_LOW_1[5] origin:064-gtp-channel-conf 31_258 -GTP_CHANNEL_2.GTPE2.TX_MARGIN_LOW_1[6] origin:064-gtp-channel-conf 30_259 -GTP_CHANNEL_2.GTPE2.TX_MARGIN_LOW_2[0] origin:064-gtp-channel-conf 30_260 -GTP_CHANNEL_2.GTPE2.TX_MARGIN_LOW_2[1] origin:064-gtp-channel-conf 31_260 -GTP_CHANNEL_2.GTPE2.TX_MARGIN_LOW_2[2] origin:064-gtp-channel-conf 30_261 -GTP_CHANNEL_2.GTPE2.TX_MARGIN_LOW_2[3] origin:064-gtp-channel-conf 31_261 -GTP_CHANNEL_2.GTPE2.TX_MARGIN_LOW_2[4] origin:064-gtp-channel-conf 30_262 -GTP_CHANNEL_2.GTPE2.TX_MARGIN_LOW_2[5] origin:064-gtp-channel-conf 31_262 -GTP_CHANNEL_2.GTPE2.TX_MARGIN_LOW_2[6] origin:064-gtp-channel-conf 30_263 -GTP_CHANNEL_2.GTPE2.TX_MARGIN_LOW_3[0] origin:064-gtp-channel-conf 30_264 -GTP_CHANNEL_2.GTPE2.TX_MARGIN_LOW_3[1] origin:064-gtp-channel-conf 31_264 -GTP_CHANNEL_2.GTPE2.TX_MARGIN_LOW_3[2] origin:064-gtp-channel-conf 30_265 -GTP_CHANNEL_2.GTPE2.TX_MARGIN_LOW_3[3] origin:064-gtp-channel-conf 31_265 -GTP_CHANNEL_2.GTPE2.TX_MARGIN_LOW_3[4] origin:064-gtp-channel-conf 30_266 -GTP_CHANNEL_2.GTPE2.TX_MARGIN_LOW_3[5] origin:064-gtp-channel-conf 31_266 -GTP_CHANNEL_2.GTPE2.TX_MARGIN_LOW_3[6] origin:064-gtp-channel-conf 30_267 -GTP_CHANNEL_2.GTPE2.TX_MARGIN_LOW_4[0] origin:064-gtp-channel-conf 30_268 -GTP_CHANNEL_2.GTPE2.TX_MARGIN_LOW_4[1] origin:064-gtp-channel-conf 31_268 -GTP_CHANNEL_2.GTPE2.TX_MARGIN_LOW_4[2] origin:064-gtp-channel-conf 30_269 -GTP_CHANNEL_2.GTPE2.TX_MARGIN_LOW_4[3] origin:064-gtp-channel-conf 31_269 -GTP_CHANNEL_2.GTPE2.TX_MARGIN_LOW_4[4] origin:064-gtp-channel-conf 30_270 -GTP_CHANNEL_2.GTPE2.TX_MARGIN_LOW_4[5] origin:064-gtp-channel-conf 31_270 -GTP_CHANNEL_2.GTPE2.TX_MARGIN_LOW_4[6] origin:064-gtp-channel-conf 30_271 -GTP_CHANNEL_2.GTPE2.TX_PREDRIVER_MODE[0] origin:064-gtp-channel-conf 28_206 -GTP_CHANNEL_2.GTPE2.TX_RXDETECT_CFG[0] origin:064-gtp-channel-conf 30_296 -GTP_CHANNEL_2.GTPE2.TX_RXDETECT_CFG[1] origin:064-gtp-channel-conf 31_296 -GTP_CHANNEL_2.GTPE2.TX_RXDETECT_CFG[2] origin:064-gtp-channel-conf 30_297 -GTP_CHANNEL_2.GTPE2.TX_RXDETECT_CFG[3] origin:064-gtp-channel-conf 31_297 -GTP_CHANNEL_2.GTPE2.TX_RXDETECT_CFG[4] origin:064-gtp-channel-conf 30_298 -GTP_CHANNEL_2.GTPE2.TX_RXDETECT_CFG[5] origin:064-gtp-channel-conf 31_298 -GTP_CHANNEL_2.GTPE2.TX_RXDETECT_CFG[6] origin:064-gtp-channel-conf 30_299 -GTP_CHANNEL_2.GTPE2.TX_RXDETECT_CFG[7] origin:064-gtp-channel-conf 31_299 -GTP_CHANNEL_2.GTPE2.TX_RXDETECT_CFG[8] origin:064-gtp-channel-conf 30_300 -GTP_CHANNEL_2.GTPE2.TX_RXDETECT_CFG[9] origin:064-gtp-channel-conf 31_300 -GTP_CHANNEL_2.GTPE2.TX_RXDETECT_CFG[10] origin:064-gtp-channel-conf 30_301 -GTP_CHANNEL_2.GTPE2.TX_RXDETECT_CFG[11] origin:064-gtp-channel-conf 31_301 -GTP_CHANNEL_2.GTPE2.TX_RXDETECT_CFG[12] origin:064-gtp-channel-conf 30_302 -GTP_CHANNEL_2.GTPE2.TX_RXDETECT_CFG[13] origin:064-gtp-channel-conf 31_302 -GTP_CHANNEL_2.GTPE2.TX_RXDETECT_REF[0] origin:064-gtp-channel-conf 30_292 -GTP_CHANNEL_2.GTPE2.TX_RXDETECT_REF[1] origin:064-gtp-channel-conf 31_292 -GTP_CHANNEL_2.GTPE2.TX_RXDETECT_REF[2] origin:064-gtp-channel-conf 30_293 -GTP_CHANNEL_2.GTPE2.TX_XCLK_SEL.TXUSR origin:064-gtp-channel-conf 31_11 -GTP_CHANNEL_2.GTPE2.TX_CLK25_DIV[0] origin:064-gtp-channel-conf 30_144 -GTP_CHANNEL_2.GTPE2.TX_CLK25_DIV[1] origin:064-gtp-channel-conf 31_144 -GTP_CHANNEL_2.GTPE2.TX_CLK25_DIV[2] origin:064-gtp-channel-conf 30_145 -GTP_CHANNEL_2.GTPE2.TX_CLK25_DIV[3] origin:064-gtp-channel-conf 31_145 -GTP_CHANNEL_2.GTPE2.TX_CLK25_DIV[4] origin:064-gtp-channel-conf 30_146 -GTP_CHANNEL_2.GTPE2.TX_DEEMPH0[0] origin:064-gtp-channel-conf 30_272 -GTP_CHANNEL_2.GTPE2.TX_DEEMPH0[1] origin:064-gtp-channel-conf 31_272 -GTP_CHANNEL_2.GTPE2.TX_DEEMPH0[2] origin:064-gtp-channel-conf 30_273 -GTP_CHANNEL_2.GTPE2.TX_DEEMPH0[3] origin:064-gtp-channel-conf 31_273 -GTP_CHANNEL_2.GTPE2.TX_DEEMPH0[4] origin:064-gtp-channel-conf 30_274 -GTP_CHANNEL_2.GTPE2.TX_DEEMPH0[5] origin:064-gtp-channel-conf 31_274 -GTP_CHANNEL_2.GTPE2.TX_DEEMPH1[0] origin:064-gtp-channel-conf 30_276 -GTP_CHANNEL_2.GTPE2.TX_DEEMPH1[1] origin:064-gtp-channel-conf 31_276 -GTP_CHANNEL_2.GTPE2.TX_DEEMPH1[2] origin:064-gtp-channel-conf 30_277 -GTP_CHANNEL_2.GTPE2.TX_DEEMPH1[3] origin:064-gtp-channel-conf 31_277 -GTP_CHANNEL_2.GTPE2.TX_DEEMPH1[4] origin:064-gtp-channel-conf 30_278 -GTP_CHANNEL_2.GTPE2.TX_DEEMPH1[5] origin:064-gtp-channel-conf 31_278 -GTP_CHANNEL_2.GTPE2.TXBUF_EN origin:064-gtp-channel-conf 28_231 -GTP_CHANNEL_2.GTPE2.TXBUF_RESET_ON_RATE_CHANGE origin:064-gtp-channel-conf 29_231 -GTP_CHANNEL_2.GTPE2.TXDLY_CFG[0] origin:064-gtp-channel-conf 30_80 -GTP_CHANNEL_2.GTPE2.TXDLY_CFG[1] origin:064-gtp-channel-conf 31_80 -GTP_CHANNEL_2.GTPE2.TXDLY_CFG[2] origin:064-gtp-channel-conf 30_81 -GTP_CHANNEL_2.GTPE2.TXDLY_CFG[3] origin:064-gtp-channel-conf 31_81 -GTP_CHANNEL_2.GTPE2.TXDLY_CFG[4] origin:064-gtp-channel-conf 30_82 -GTP_CHANNEL_2.GTPE2.TXDLY_CFG[5] origin:064-gtp-channel-conf 31_82 -GTP_CHANNEL_2.GTPE2.TXDLY_CFG[6] origin:064-gtp-channel-conf 30_83 -GTP_CHANNEL_2.GTPE2.TXDLY_CFG[7] origin:064-gtp-channel-conf 31_83 -GTP_CHANNEL_2.GTPE2.TXDLY_CFG[8] origin:064-gtp-channel-conf 30_84 -GTP_CHANNEL_2.GTPE2.TXDLY_CFG[9] origin:064-gtp-channel-conf 31_84 -GTP_CHANNEL_2.GTPE2.TXDLY_CFG[10] origin:064-gtp-channel-conf 30_85 -GTP_CHANNEL_2.GTPE2.TXDLY_CFG[11] origin:064-gtp-channel-conf 31_85 -GTP_CHANNEL_2.GTPE2.TXDLY_CFG[12] origin:064-gtp-channel-conf 30_86 -GTP_CHANNEL_2.GTPE2.TXDLY_CFG[13] origin:064-gtp-channel-conf 31_86 -GTP_CHANNEL_2.GTPE2.TXDLY_CFG[14] origin:064-gtp-channel-conf 30_87 -GTP_CHANNEL_2.GTPE2.TXDLY_CFG[15] origin:064-gtp-channel-conf 31_87 -GTP_CHANNEL_2.GTPE2.TXDLY_LCFG[0] origin:064-gtp-channel-conf 30_568 -GTP_CHANNEL_2.GTPE2.TXDLY_LCFG[1] origin:064-gtp-channel-conf 31_568 -GTP_CHANNEL_2.GTPE2.TXDLY_LCFG[2] origin:064-gtp-channel-conf 30_569 -GTP_CHANNEL_2.GTPE2.TXDLY_LCFG[3] origin:064-gtp-channel-conf 31_569 -GTP_CHANNEL_2.GTPE2.TXDLY_LCFG[4] origin:064-gtp-channel-conf 30_570 -GTP_CHANNEL_2.GTPE2.TXDLY_LCFG[5] origin:064-gtp-channel-conf 31_570 -GTP_CHANNEL_2.GTPE2.TXDLY_LCFG[6] origin:064-gtp-channel-conf 30_571 -GTP_CHANNEL_2.GTPE2.TXDLY_LCFG[7] origin:064-gtp-channel-conf 31_571 -GTP_CHANNEL_2.GTPE2.TXDLY_LCFG[8] origin:064-gtp-channel-conf 30_572 -GTP_CHANNEL_2.GTPE2.TXDLY_TAP_CFG[0] origin:064-gtp-channel-conf 30_88 -GTP_CHANNEL_2.GTPE2.TXDLY_TAP_CFG[1] origin:064-gtp-channel-conf 31_88 -GTP_CHANNEL_2.GTPE2.TXDLY_TAP_CFG[2] origin:064-gtp-channel-conf 30_89 -GTP_CHANNEL_2.GTPE2.TXDLY_TAP_CFG[3] origin:064-gtp-channel-conf 31_89 -GTP_CHANNEL_2.GTPE2.TXDLY_TAP_CFG[4] origin:064-gtp-channel-conf 30_90 -GTP_CHANNEL_2.GTPE2.TXDLY_TAP_CFG[5] origin:064-gtp-channel-conf 31_90 -GTP_CHANNEL_2.GTPE2.TXDLY_TAP_CFG[6] origin:064-gtp-channel-conf 30_91 -GTP_CHANNEL_2.GTPE2.TXDLY_TAP_CFG[7] origin:064-gtp-channel-conf 31_91 -GTP_CHANNEL_2.GTPE2.TXDLY_TAP_CFG[8] origin:064-gtp-channel-conf 30_92 -GTP_CHANNEL_2.GTPE2.TXDLY_TAP_CFG[9] origin:064-gtp-channel-conf 31_92 -GTP_CHANNEL_2.GTPE2.TXDLY_TAP_CFG[10] origin:064-gtp-channel-conf 30_93 -GTP_CHANNEL_2.GTPE2.TXDLY_TAP_CFG[11] origin:064-gtp-channel-conf 31_93 -GTP_CHANNEL_2.GTPE2.TXDLY_TAP_CFG[12] origin:064-gtp-channel-conf 30_94 -GTP_CHANNEL_2.GTPE2.TXDLY_TAP_CFG[13] origin:064-gtp-channel-conf 31_94 -GTP_CHANNEL_2.GTPE2.TXDLY_TAP_CFG[14] origin:064-gtp-channel-conf 30_95 -GTP_CHANNEL_2.GTPE2.TXDLY_TAP_CFG[15] origin:064-gtp-channel-conf 31_95 -GTP_CHANNEL_2.GTPE2.TXGEARBOX_EN origin:064-gtp-channel-conf 29_226 -GTP_CHANNEL_2.GTPE2.TXOOB_CFG[0] origin:064-gtp-channel-conf 31_20 -GTP_CHANNEL_2.GTPE2.TXOUT_DIV[0] origin:064-gtp-channel-conf 30_386 -GTP_CHANNEL_2.GTPE2.TXOUT_DIV[1] origin:064-gtp-channel-conf 31_386 -GTP_CHANNEL_2.GTPE2.TXPCSRESET_TIME[0] origin:064-gtp-channel-conf 29_130 -GTP_CHANNEL_2.GTPE2.TXPCSRESET_TIME[1] origin:064-gtp-channel-conf 28_131 -GTP_CHANNEL_2.GTPE2.TXPCSRESET_TIME[2] origin:064-gtp-channel-conf 29_131 -GTP_CHANNEL_2.GTPE2.TXPCSRESET_TIME[3] origin:064-gtp-channel-conf 28_132 -GTP_CHANNEL_2.GTPE2.TXPCSRESET_TIME[4] origin:064-gtp-channel-conf 29_132 -GTP_CHANNEL_2.GTPE2.TXPH_CFG[0] origin:064-gtp-channel-conf 30_96 -GTP_CHANNEL_2.GTPE2.TXPH_CFG[1] origin:064-gtp-channel-conf 31_96 -GTP_CHANNEL_2.GTPE2.TXPH_CFG[2] origin:064-gtp-channel-conf 30_97 -GTP_CHANNEL_2.GTPE2.TXPH_CFG[3] origin:064-gtp-channel-conf 31_97 -GTP_CHANNEL_2.GTPE2.TXPH_CFG[4] origin:064-gtp-channel-conf 30_98 -GTP_CHANNEL_2.GTPE2.TXPH_CFG[5] origin:064-gtp-channel-conf 31_98 -GTP_CHANNEL_2.GTPE2.TXPH_CFG[6] origin:064-gtp-channel-conf 30_99 -GTP_CHANNEL_2.GTPE2.TXPH_CFG[7] origin:064-gtp-channel-conf 31_99 -GTP_CHANNEL_2.GTPE2.TXPH_CFG[8] origin:064-gtp-channel-conf 30_100 -GTP_CHANNEL_2.GTPE2.TXPH_CFG[9] origin:064-gtp-channel-conf 31_100 -GTP_CHANNEL_2.GTPE2.TXPH_CFG[10] origin:064-gtp-channel-conf 30_101 -GTP_CHANNEL_2.GTPE2.TXPH_CFG[11] origin:064-gtp-channel-conf 31_101 -GTP_CHANNEL_2.GTPE2.TXPH_CFG[12] origin:064-gtp-channel-conf 30_102 -GTP_CHANNEL_2.GTPE2.TXPH_CFG[13] origin:064-gtp-channel-conf 31_102 -GTP_CHANNEL_2.GTPE2.TXPH_CFG[14] origin:064-gtp-channel-conf 30_103 -GTP_CHANNEL_2.GTPE2.TXPH_CFG[15] origin:064-gtp-channel-conf 31_103 -GTP_CHANNEL_2.GTPE2.TXPH_MONITOR_SEL[0] origin:064-gtp-channel-conf 30_108 -GTP_CHANNEL_2.GTPE2.TXPH_MONITOR_SEL[1] origin:064-gtp-channel-conf 31_108 -GTP_CHANNEL_2.GTPE2.TXPH_MONITOR_SEL[2] origin:064-gtp-channel-conf 30_109 -GTP_CHANNEL_2.GTPE2.TXPH_MONITOR_SEL[3] origin:064-gtp-channel-conf 31_109 -GTP_CHANNEL_2.GTPE2.TXPH_MONITOR_SEL[4] origin:064-gtp-channel-conf 30_110 -GTP_CHANNEL_2.GTPE2.TXPHDLY_CFG[0] origin:064-gtp-channel-conf 30_64 -GTP_CHANNEL_2.GTPE2.TXPHDLY_CFG[1] origin:064-gtp-channel-conf 31_64 -GTP_CHANNEL_2.GTPE2.TXPHDLY_CFG[2] origin:064-gtp-channel-conf 30_65 -GTP_CHANNEL_2.GTPE2.TXPHDLY_CFG[3] origin:064-gtp-channel-conf 31_65 -GTP_CHANNEL_2.GTPE2.TXPHDLY_CFG[4] origin:064-gtp-channel-conf 30_66 -GTP_CHANNEL_2.GTPE2.TXPHDLY_CFG[5] origin:064-gtp-channel-conf 31_66 -GTP_CHANNEL_2.GTPE2.TXPHDLY_CFG[6] origin:064-gtp-channel-conf 30_67 -GTP_CHANNEL_2.GTPE2.TXPHDLY_CFG[7] origin:064-gtp-channel-conf 31_67 -GTP_CHANNEL_2.GTPE2.TXPHDLY_CFG[8] origin:064-gtp-channel-conf 30_68 -GTP_CHANNEL_2.GTPE2.TXPHDLY_CFG[9] origin:064-gtp-channel-conf 31_68 -GTP_CHANNEL_2.GTPE2.TXPHDLY_CFG[10] origin:064-gtp-channel-conf 30_69 -GTP_CHANNEL_2.GTPE2.TXPHDLY_CFG[11] origin:064-gtp-channel-conf 31_69 -GTP_CHANNEL_2.GTPE2.TXPHDLY_CFG[12] origin:064-gtp-channel-conf 30_70 -GTP_CHANNEL_2.GTPE2.TXPHDLY_CFG[13] origin:064-gtp-channel-conf 31_70 -GTP_CHANNEL_2.GTPE2.TXPHDLY_CFG[14] origin:064-gtp-channel-conf 30_71 -GTP_CHANNEL_2.GTPE2.TXPHDLY_CFG[15] origin:064-gtp-channel-conf 31_71 -GTP_CHANNEL_2.GTPE2.TXPHDLY_CFG[16] origin:064-gtp-channel-conf 30_72 -GTP_CHANNEL_2.GTPE2.TXPHDLY_CFG[17] origin:064-gtp-channel-conf 31_72 -GTP_CHANNEL_2.GTPE2.TXPHDLY_CFG[18] origin:064-gtp-channel-conf 30_73 -GTP_CHANNEL_2.GTPE2.TXPHDLY_CFG[19] origin:064-gtp-channel-conf 31_73 -GTP_CHANNEL_2.GTPE2.TXPHDLY_CFG[20] origin:064-gtp-channel-conf 30_74 -GTP_CHANNEL_2.GTPE2.TXPHDLY_CFG[21] origin:064-gtp-channel-conf 31_74 -GTP_CHANNEL_2.GTPE2.TXPHDLY_CFG[22] origin:064-gtp-channel-conf 30_75 -GTP_CHANNEL_2.GTPE2.TXPHDLY_CFG[23] origin:064-gtp-channel-conf 31_75 -GTP_CHANNEL_2.GTPE2.TXPI_GREY_SEL[0] origin:064-gtp-channel-conf 31_498 -GTP_CHANNEL_2.GTPE2.TXPI_INVSTROBE_SEL[0] origin:064-gtp-channel-conf 30_498 -GTP_CHANNEL_2.GTPE2.TXPI_PPM_CFG[0] origin:064-gtp-channel-conf 30_488 -GTP_CHANNEL_2.GTPE2.TXPI_PPM_CFG[1] origin:064-gtp-channel-conf 31_488 -GTP_CHANNEL_2.GTPE2.TXPI_PPM_CFG[2] origin:064-gtp-channel-conf 30_489 -GTP_CHANNEL_2.GTPE2.TXPI_PPM_CFG[3] origin:064-gtp-channel-conf 31_489 -GTP_CHANNEL_2.GTPE2.TXPI_PPM_CFG[4] origin:064-gtp-channel-conf 30_490 -GTP_CHANNEL_2.GTPE2.TXPI_PPM_CFG[5] origin:064-gtp-channel-conf 31_490 -GTP_CHANNEL_2.GTPE2.TXPI_PPM_CFG[6] origin:064-gtp-channel-conf 30_491 -GTP_CHANNEL_2.GTPE2.TXPI_PPM_CFG[7] origin:064-gtp-channel-conf 31_491 -GTP_CHANNEL_2.GTPE2.TXPI_PPMCLK_SEL.TXUSRCLK2 origin:064-gtp-channel-conf 31_497 -GTP_CHANNEL_2.GTPE2.TXPI_SYNFREQ_PPM[0] origin:064-gtp-channel-conf 30_496 -GTP_CHANNEL_2.GTPE2.TXPI_SYNFREQ_PPM[1] origin:064-gtp-channel-conf 31_496 -GTP_CHANNEL_2.GTPE2.TXPI_SYNFREQ_PPM[2] origin:064-gtp-channel-conf 30_497 -GTP_CHANNEL_2.GTPE2.TXPI_CFG0[0] origin:064-gtp-channel-conf 30_40 -GTP_CHANNEL_2.GTPE2.TXPI_CFG0[1] origin:064-gtp-channel-conf 31_40 -GTP_CHANNEL_2.GTPE2.TXPI_CFG1[0] origin:064-gtp-channel-conf 30_41 -GTP_CHANNEL_2.GTPE2.TXPI_CFG1[1] origin:064-gtp-channel-conf 31_41 -GTP_CHANNEL_2.GTPE2.TXPI_CFG2[0] origin:064-gtp-channel-conf 30_42 -GTP_CHANNEL_2.GTPE2.TXPI_CFG2[1] origin:064-gtp-channel-conf 31_42 -GTP_CHANNEL_2.GTPE2.TXPI_CFG3[0] origin:064-gtp-channel-conf 30_43 -GTP_CHANNEL_2.GTPE2.TXPI_CFG4[0] origin:064-gtp-channel-conf 31_43 -GTP_CHANNEL_2.GTPE2.TXPI_CFG5[0] origin:064-gtp-channel-conf 30_44 -GTP_CHANNEL_2.GTPE2.TXPI_CFG5[1] origin:064-gtp-channel-conf 31_44 -GTP_CHANNEL_2.GTPE2.TXPI_CFG5[2] origin:064-gtp-channel-conf 30_45 -GTP_CHANNEL_2.GTPE2.TXPMARESET_TIME[0] origin:064-gtp-channel-conf 28_128 -GTP_CHANNEL_2.GTPE2.TXPMARESET_TIME[1] origin:064-gtp-channel-conf 29_128 -GTP_CHANNEL_2.GTPE2.TXPMARESET_TIME[2] origin:064-gtp-channel-conf 28_129 -GTP_CHANNEL_2.GTPE2.TXPMARESET_TIME[3] origin:064-gtp-channel-conf 29_129 -GTP_CHANNEL_2.GTPE2.TXPMARESET_TIME[4] origin:064-gtp-channel-conf 28_130 -GTP_CHANNEL_2.GTPE2.TXSYNC_MULTILANE[0] origin:064-gtp-channel-conf 29_133 -GTP_CHANNEL_2.GTPE2.TXSYNC_OVRD[0] origin:064-gtp-channel-conf 28_135 -GTP_CHANNEL_2.GTPE2.TXSYNC_SKIP_DA[0] origin:064-gtp-channel-conf 28_134 -GTP_CHANNEL_2.GTPE2.UCODEER_CLR[0] origin:064-gtp-channel-conf 29_00 -GTP_CHANNEL_2.GTPE2.USE_PCS_CLK_PHASE_SEL[0] origin:064-gtp-channel-conf 30_463 -GTP_CHANNEL_2.GTPE2.ZINV_DMONITORCLK origin:064-gtp-channel-conf 30_13 -GTP_CHANNEL_2.GTPE2.ZINV_DRPCLK origin:064-gtp-channel-conf 30_00 -GTP_CHANNEL_2.GTPE2.ZINV_RXUSRCLK origin:064-gtp-channel-conf 31_01 -GTP_CHANNEL_2.GTPE2.ZINV_SIGVALIDCLK origin:064-gtp-channel-conf 31_13 -GTP_CHANNEL_2.GTPE2.ZINV_TXPHDLYTSTCLK origin:064-gtp-channel-conf 30_03 -GTP_CHANNEL_2.GTPE2.ZINV_TXUSRCLK origin:064-gtp-channel-conf 31_04 -GTP_CHANNEL_2.GTPE2.ZINV_CLKRSVD0 origin:064-gtp-channel-conf 30_23 -GTP_CHANNEL_2.GTPE2.ZINV_CLKRSVD1 origin:064-gtp-channel-conf 31_23 -GTP_CHANNEL_2.GTPE2.ZINV_RXUSRCLK2 origin:064-gtp-channel-conf 30_02 -GTP_CHANNEL_2.GTPE2.ZINV_TXUSRCLK2 origin:064-gtp-channel-conf 30_05 +GTP_CHANNEL_2.GTPE2_CHANNEL.ACJTAG_DEBUG_MODE[0] origin:064-gtp-channel-conf 28_07 +GTP_CHANNEL_2.GTPE2_CHANNEL.ACJTAG_MODE[0] origin:064-gtp-channel-conf 29_06 +GTP_CHANNEL_2.GTPE2_CHANNEL.ACJTAG_RESET[0] origin:064-gtp-channel-conf 29_07 +GTP_CHANNEL_2.GTPE2_CHANNEL.ADAPT_CFG0[0] origin:064-gtp-channel-conf 30_464 +GTP_CHANNEL_2.GTPE2_CHANNEL.ADAPT_CFG0[1] origin:064-gtp-channel-conf 31_464 +GTP_CHANNEL_2.GTPE2_CHANNEL.ADAPT_CFG0[2] origin:064-gtp-channel-conf 30_465 +GTP_CHANNEL_2.GTPE2_CHANNEL.ADAPT_CFG0[3] origin:064-gtp-channel-conf 31_465 +GTP_CHANNEL_2.GTPE2_CHANNEL.ADAPT_CFG0[4] origin:064-gtp-channel-conf 30_466 +GTP_CHANNEL_2.GTPE2_CHANNEL.ADAPT_CFG0[5] origin:064-gtp-channel-conf 31_466 +GTP_CHANNEL_2.GTPE2_CHANNEL.ADAPT_CFG0[6] origin:064-gtp-channel-conf 30_467 +GTP_CHANNEL_2.GTPE2_CHANNEL.ADAPT_CFG0[7] origin:064-gtp-channel-conf 31_467 +GTP_CHANNEL_2.GTPE2_CHANNEL.ADAPT_CFG0[8] origin:064-gtp-channel-conf 30_468 +GTP_CHANNEL_2.GTPE2_CHANNEL.ADAPT_CFG0[9] origin:064-gtp-channel-conf 31_468 +GTP_CHANNEL_2.GTPE2_CHANNEL.ADAPT_CFG0[10] origin:064-gtp-channel-conf 30_469 +GTP_CHANNEL_2.GTPE2_CHANNEL.ADAPT_CFG0[11] origin:064-gtp-channel-conf 31_469 +GTP_CHANNEL_2.GTPE2_CHANNEL.ADAPT_CFG0[12] origin:064-gtp-channel-conf 30_470 +GTP_CHANNEL_2.GTPE2_CHANNEL.ADAPT_CFG0[13] origin:064-gtp-channel-conf 31_470 +GTP_CHANNEL_2.GTPE2_CHANNEL.ADAPT_CFG0[14] origin:064-gtp-channel-conf 30_471 +GTP_CHANNEL_2.GTPE2_CHANNEL.ADAPT_CFG0[15] origin:064-gtp-channel-conf 31_471 +GTP_CHANNEL_2.GTPE2_CHANNEL.ADAPT_CFG0[16] origin:064-gtp-channel-conf 30_472 +GTP_CHANNEL_2.GTPE2_CHANNEL.ADAPT_CFG0[17] origin:064-gtp-channel-conf 31_472 +GTP_CHANNEL_2.GTPE2_CHANNEL.ADAPT_CFG0[18] origin:064-gtp-channel-conf 30_473 +GTP_CHANNEL_2.GTPE2_CHANNEL.ADAPT_CFG0[19] origin:064-gtp-channel-conf 31_473 +GTP_CHANNEL_2.GTPE2_CHANNEL.ALIGN_COMMA_DOUBLE origin:064-gtp-channel-conf 28_522 +GTP_CHANNEL_2.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[0] origin:064-gtp-channel-conf 28_496 +GTP_CHANNEL_2.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[1] origin:064-gtp-channel-conf 29_496 +GTP_CHANNEL_2.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[2] origin:064-gtp-channel-conf 28_497 +GTP_CHANNEL_2.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[3] origin:064-gtp-channel-conf 29_497 +GTP_CHANNEL_2.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[4] origin:064-gtp-channel-conf 28_498 +GTP_CHANNEL_2.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[5] origin:064-gtp-channel-conf 29_498 +GTP_CHANNEL_2.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[6] origin:064-gtp-channel-conf 28_499 +GTP_CHANNEL_2.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[7] origin:064-gtp-channel-conf 29_499 +GTP_CHANNEL_2.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[8] origin:064-gtp-channel-conf 28_500 +GTP_CHANNEL_2.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[9] origin:064-gtp-channel-conf 29_500 +GTP_CHANNEL_2.GTPE2_CHANNEL.ALIGN_COMMA_WORD[0] origin:064-gtp-channel-conf 29_526 +GTP_CHANNEL_2.GTPE2_CHANNEL.ALIGN_COMMA_WORD[1] origin:064-gtp-channel-conf 28_527 +GTP_CHANNEL_2.GTPE2_CHANNEL.ALIGN_MCOMMA_DET origin:064-gtp-channel-conf 28_523 +GTP_CHANNEL_2.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[0] origin:064-gtp-channel-conf 28_504 +GTP_CHANNEL_2.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[1] origin:064-gtp-channel-conf 29_504 +GTP_CHANNEL_2.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[2] origin:064-gtp-channel-conf 28_505 +GTP_CHANNEL_2.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[3] origin:064-gtp-channel-conf 29_505 +GTP_CHANNEL_2.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[4] origin:064-gtp-channel-conf 28_506 +GTP_CHANNEL_2.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[5] origin:064-gtp-channel-conf 29_506 +GTP_CHANNEL_2.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[6] origin:064-gtp-channel-conf 28_507 +GTP_CHANNEL_2.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[7] origin:064-gtp-channel-conf 29_507 +GTP_CHANNEL_2.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[8] origin:064-gtp-channel-conf 28_508 +GTP_CHANNEL_2.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[9] origin:064-gtp-channel-conf 29_508 +GTP_CHANNEL_2.GTPE2_CHANNEL.ALIGN_PCOMMA_DET origin:064-gtp-channel-conf 29_523 +GTP_CHANNEL_2.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[0] origin:064-gtp-channel-conf 28_512 +GTP_CHANNEL_2.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[1] origin:064-gtp-channel-conf 29_512 +GTP_CHANNEL_2.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[2] origin:064-gtp-channel-conf 28_513 +GTP_CHANNEL_2.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[3] origin:064-gtp-channel-conf 29_513 +GTP_CHANNEL_2.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[4] origin:064-gtp-channel-conf 28_514 +GTP_CHANNEL_2.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[5] origin:064-gtp-channel-conf 29_514 +GTP_CHANNEL_2.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[6] origin:064-gtp-channel-conf 28_515 +GTP_CHANNEL_2.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[7] origin:064-gtp-channel-conf 29_515 +GTP_CHANNEL_2.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[8] origin:064-gtp-channel-conf 28_516 +GTP_CHANNEL_2.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[9] origin:064-gtp-channel-conf 29_516 +GTP_CHANNEL_2.GTPE2_CHANNEL.CBCC_DATA_SOURCE_SEL.DECODED origin:064-gtp-channel-conf 29_661 +GTP_CHANNEL_2.GTPE2_CHANNEL.CFOK_CFG[0] origin:064-gtp-channel-conf 30_392 +GTP_CHANNEL_2.GTPE2_CHANNEL.CFOK_CFG[1] origin:064-gtp-channel-conf 31_392 +GTP_CHANNEL_2.GTPE2_CHANNEL.CFOK_CFG[2] origin:064-gtp-channel-conf 30_393 +GTP_CHANNEL_2.GTPE2_CHANNEL.CFOK_CFG[3] origin:064-gtp-channel-conf 31_393 +GTP_CHANNEL_2.GTPE2_CHANNEL.CFOK_CFG[4] origin:064-gtp-channel-conf 30_394 +GTP_CHANNEL_2.GTPE2_CHANNEL.CFOK_CFG[5] origin:064-gtp-channel-conf 31_394 +GTP_CHANNEL_2.GTPE2_CHANNEL.CFOK_CFG[6] origin:064-gtp-channel-conf 30_395 +GTP_CHANNEL_2.GTPE2_CHANNEL.CFOK_CFG[7] origin:064-gtp-channel-conf 31_395 +GTP_CHANNEL_2.GTPE2_CHANNEL.CFOK_CFG[8] origin:064-gtp-channel-conf 30_396 +GTP_CHANNEL_2.GTPE2_CHANNEL.CFOK_CFG[9] origin:064-gtp-channel-conf 31_396 +GTP_CHANNEL_2.GTPE2_CHANNEL.CFOK_CFG[10] origin:064-gtp-channel-conf 30_397 +GTP_CHANNEL_2.GTPE2_CHANNEL.CFOK_CFG[11] origin:064-gtp-channel-conf 31_397 +GTP_CHANNEL_2.GTPE2_CHANNEL.CFOK_CFG[12] origin:064-gtp-channel-conf 30_398 +GTP_CHANNEL_2.GTPE2_CHANNEL.CFOK_CFG[13] origin:064-gtp-channel-conf 31_398 +GTP_CHANNEL_2.GTPE2_CHANNEL.CFOK_CFG[14] origin:064-gtp-channel-conf 30_399 +GTP_CHANNEL_2.GTPE2_CHANNEL.CFOK_CFG[15] origin:064-gtp-channel-conf 31_399 +GTP_CHANNEL_2.GTPE2_CHANNEL.CFOK_CFG[16] origin:064-gtp-channel-conf 30_400 +GTP_CHANNEL_2.GTPE2_CHANNEL.CFOK_CFG[17] origin:064-gtp-channel-conf 31_400 +GTP_CHANNEL_2.GTPE2_CHANNEL.CFOK_CFG[18] origin:064-gtp-channel-conf 30_401 +GTP_CHANNEL_2.GTPE2_CHANNEL.CFOK_CFG[19] origin:064-gtp-channel-conf 31_401 +GTP_CHANNEL_2.GTPE2_CHANNEL.CFOK_CFG[20] origin:064-gtp-channel-conf 30_402 +GTP_CHANNEL_2.GTPE2_CHANNEL.CFOK_CFG[21] origin:064-gtp-channel-conf 31_402 +GTP_CHANNEL_2.GTPE2_CHANNEL.CFOK_CFG[22] origin:064-gtp-channel-conf 30_403 +GTP_CHANNEL_2.GTPE2_CHANNEL.CFOK_CFG[23] origin:064-gtp-channel-conf 31_403 +GTP_CHANNEL_2.GTPE2_CHANNEL.CFOK_CFG[24] origin:064-gtp-channel-conf 30_404 +GTP_CHANNEL_2.GTPE2_CHANNEL.CFOK_CFG[25] origin:064-gtp-channel-conf 31_404 +GTP_CHANNEL_2.GTPE2_CHANNEL.CFOK_CFG[26] origin:064-gtp-channel-conf 30_405 +GTP_CHANNEL_2.GTPE2_CHANNEL.CFOK_CFG[27] origin:064-gtp-channel-conf 31_405 +GTP_CHANNEL_2.GTPE2_CHANNEL.CFOK_CFG[28] origin:064-gtp-channel-conf 30_406 +GTP_CHANNEL_2.GTPE2_CHANNEL.CFOK_CFG[29] origin:064-gtp-channel-conf 31_406 +GTP_CHANNEL_2.GTPE2_CHANNEL.CFOK_CFG[30] origin:064-gtp-channel-conf 30_407 +GTP_CHANNEL_2.GTPE2_CHANNEL.CFOK_CFG[31] origin:064-gtp-channel-conf 31_407 +GTP_CHANNEL_2.GTPE2_CHANNEL.CFOK_CFG[32] origin:064-gtp-channel-conf 30_408 +GTP_CHANNEL_2.GTPE2_CHANNEL.CFOK_CFG[33] origin:064-gtp-channel-conf 31_408 +GTP_CHANNEL_2.GTPE2_CHANNEL.CFOK_CFG[34] origin:064-gtp-channel-conf 30_409 +GTP_CHANNEL_2.GTPE2_CHANNEL.CFOK_CFG[35] origin:064-gtp-channel-conf 31_409 +GTP_CHANNEL_2.GTPE2_CHANNEL.CFOK_CFG[36] origin:064-gtp-channel-conf 30_410 +GTP_CHANNEL_2.GTPE2_CHANNEL.CFOK_CFG[37] origin:064-gtp-channel-conf 31_410 +GTP_CHANNEL_2.GTPE2_CHANNEL.CFOK_CFG[38] origin:064-gtp-channel-conf 30_411 +GTP_CHANNEL_2.GTPE2_CHANNEL.CFOK_CFG[39] origin:064-gtp-channel-conf 31_411 +GTP_CHANNEL_2.GTPE2_CHANNEL.CFOK_CFG[40] origin:064-gtp-channel-conf 30_412 +GTP_CHANNEL_2.GTPE2_CHANNEL.CFOK_CFG[41] origin:064-gtp-channel-conf 31_412 +GTP_CHANNEL_2.GTPE2_CHANNEL.CFOK_CFG[42] origin:064-gtp-channel-conf 30_413 +GTP_CHANNEL_2.GTPE2_CHANNEL.CFOK_CFG2[0] origin:064-gtp-channel-conf 30_459 +GTP_CHANNEL_2.GTPE2_CHANNEL.CFOK_CFG2[1] origin:064-gtp-channel-conf 31_459 +GTP_CHANNEL_2.GTPE2_CHANNEL.CFOK_CFG2[2] origin:064-gtp-channel-conf 30_460 +GTP_CHANNEL_2.GTPE2_CHANNEL.CFOK_CFG2[3] origin:064-gtp-channel-conf 31_460 +GTP_CHANNEL_2.GTPE2_CHANNEL.CFOK_CFG2[4] origin:064-gtp-channel-conf 30_461 +GTP_CHANNEL_2.GTPE2_CHANNEL.CFOK_CFG2[5] origin:064-gtp-channel-conf 31_461 +GTP_CHANNEL_2.GTPE2_CHANNEL.CFOK_CFG2[6] origin:064-gtp-channel-conf 30_462 +GTP_CHANNEL_2.GTPE2_CHANNEL.CFOK_CFG3[0] origin:064-gtp-channel-conf 30_416 +GTP_CHANNEL_2.GTPE2_CHANNEL.CFOK_CFG3[1] origin:064-gtp-channel-conf 31_416 +GTP_CHANNEL_2.GTPE2_CHANNEL.CFOK_CFG3[2] origin:064-gtp-channel-conf 30_417 +GTP_CHANNEL_2.GTPE2_CHANNEL.CFOK_CFG3[3] origin:064-gtp-channel-conf 31_417 +GTP_CHANNEL_2.GTPE2_CHANNEL.CFOK_CFG3[4] origin:064-gtp-channel-conf 30_418 +GTP_CHANNEL_2.GTPE2_CHANNEL.CFOK_CFG3[5] origin:064-gtp-channel-conf 31_418 +GTP_CHANNEL_2.GTPE2_CHANNEL.CFOK_CFG3[6] origin:064-gtp-channel-conf 30_419 +GTP_CHANNEL_2.GTPE2_CHANNEL.CFOK_CFG4[0] origin:064-gtp-channel-conf 31_438 +GTP_CHANNEL_2.GTPE2_CHANNEL.CFOK_CFG5[0] origin:064-gtp-channel-conf 30_429 +GTP_CHANNEL_2.GTPE2_CHANNEL.CFOK_CFG5[1] origin:064-gtp-channel-conf 31_429 +GTP_CHANNEL_2.GTPE2_CHANNEL.CFOK_CFG6[0] origin:064-gtp-channel-conf 31_436 +GTP_CHANNEL_2.GTPE2_CHANNEL.CFOK_CFG6[1] origin:064-gtp-channel-conf 30_437 +GTP_CHANNEL_2.GTPE2_CHANNEL.CFOK_CFG6[2] origin:064-gtp-channel-conf 31_437 +GTP_CHANNEL_2.GTPE2_CHANNEL.CFOK_CFG6[3] origin:064-gtp-channel-conf 30_438 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_KEEP_ALIGN origin:064-gtp-channel-conf 29_631 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_MAX_SKEW[0] origin:064-gtp-channel-conf 28_670 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_MAX_SKEW[1] origin:064-gtp-channel-conf 29_670 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_MAX_SKEW[2] origin:064-gtp-channel-conf 28_671 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_MAX_SKEW[3] origin:064-gtp-channel-conf 29_671 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[0] origin:064-gtp-channel-conf 28_608 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[1] origin:064-gtp-channel-conf 29_608 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[2] origin:064-gtp-channel-conf 28_609 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[3] origin:064-gtp-channel-conf 29_609 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[4] origin:064-gtp-channel-conf 28_610 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[5] origin:064-gtp-channel-conf 29_610 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[6] origin:064-gtp-channel-conf 28_611 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[7] origin:064-gtp-channel-conf 29_611 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[8] origin:064-gtp-channel-conf 28_612 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[9] origin:064-gtp-channel-conf 29_612 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[0] origin:064-gtp-channel-conf 28_616 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[1] origin:064-gtp-channel-conf 29_616 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[2] origin:064-gtp-channel-conf 28_617 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[3] origin:064-gtp-channel-conf 29_617 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[4] origin:064-gtp-channel-conf 28_618 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[5] origin:064-gtp-channel-conf 29_618 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[6] origin:064-gtp-channel-conf 28_619 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[7] origin:064-gtp-channel-conf 29_619 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[8] origin:064-gtp-channel-conf 28_620 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[9] origin:064-gtp-channel-conf 29_620 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[0] origin:064-gtp-channel-conf 28_624 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[1] origin:064-gtp-channel-conf 29_624 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[2] origin:064-gtp-channel-conf 28_625 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[3] origin:064-gtp-channel-conf 29_625 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[4] origin:064-gtp-channel-conf 28_626 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[5] origin:064-gtp-channel-conf 29_626 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[6] origin:064-gtp-channel-conf 28_627 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[7] origin:064-gtp-channel-conf 29_627 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[8] origin:064-gtp-channel-conf 28_628 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[9] origin:064-gtp-channel-conf 29_628 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[0] origin:064-gtp-channel-conf 28_632 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[1] origin:064-gtp-channel-conf 29_632 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[2] origin:064-gtp-channel-conf 28_633 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[3] origin:064-gtp-channel-conf 29_633 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[4] origin:064-gtp-channel-conf 28_634 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[5] origin:064-gtp-channel-conf 29_634 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[6] origin:064-gtp-channel-conf 28_635 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[7] origin:064-gtp-channel-conf 29_635 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[8] origin:064-gtp-channel-conf 28_636 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[9] origin:064-gtp-channel-conf 29_636 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_ENABLE[0] origin:064-gtp-channel-conf 28_614 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_ENABLE[1] origin:064-gtp-channel-conf 29_614 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_ENABLE[2] origin:064-gtp-channel-conf 28_615 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_ENABLE[3] origin:064-gtp-channel-conf 29_615 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[0] origin:064-gtp-channel-conf 28_640 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[1] origin:064-gtp-channel-conf 29_640 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[2] origin:064-gtp-channel-conf 28_641 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[3] origin:064-gtp-channel-conf 29_641 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[4] origin:064-gtp-channel-conf 28_642 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[5] origin:064-gtp-channel-conf 29_642 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[6] origin:064-gtp-channel-conf 28_643 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[7] origin:064-gtp-channel-conf 29_643 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[8] origin:064-gtp-channel-conf 28_644 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[9] origin:064-gtp-channel-conf 29_644 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[0] origin:064-gtp-channel-conf 28_648 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[1] origin:064-gtp-channel-conf 29_648 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[2] origin:064-gtp-channel-conf 28_649 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[3] origin:064-gtp-channel-conf 29_649 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[4] origin:064-gtp-channel-conf 28_650 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[5] origin:064-gtp-channel-conf 29_650 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[6] origin:064-gtp-channel-conf 28_651 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[7] origin:064-gtp-channel-conf 29_651 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[8] origin:064-gtp-channel-conf 28_652 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[9] origin:064-gtp-channel-conf 29_652 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[0] origin:064-gtp-channel-conf 28_656 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[1] origin:064-gtp-channel-conf 29_656 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[2] origin:064-gtp-channel-conf 28_657 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[3] origin:064-gtp-channel-conf 29_657 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[4] origin:064-gtp-channel-conf 28_658 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[5] origin:064-gtp-channel-conf 29_658 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[6] origin:064-gtp-channel-conf 28_659 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[7] origin:064-gtp-channel-conf 29_659 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[8] origin:064-gtp-channel-conf 28_660 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[9] origin:064-gtp-channel-conf 29_660 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[0] origin:064-gtp-channel-conf 28_664 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[1] origin:064-gtp-channel-conf 29_664 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[2] origin:064-gtp-channel-conf 28_665 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[3] origin:064-gtp-channel-conf 29_665 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[4] origin:064-gtp-channel-conf 28_666 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[5] origin:064-gtp-channel-conf 29_666 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[6] origin:064-gtp-channel-conf 28_667 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[7] origin:064-gtp-channel-conf 29_667 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[8] origin:064-gtp-channel-conf 28_668 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[9] origin:064-gtp-channel-conf 29_668 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_ENABLE[0] origin:064-gtp-channel-conf 28_646 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_ENABLE[1] origin:064-gtp-channel-conf 29_646 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_ENABLE[2] origin:064-gtp-channel-conf 28_647 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_ENABLE[3] origin:064-gtp-channel-conf 29_647 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_USE origin:064-gtp-channel-conf 29_645 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_LEN[0] origin:064-gtp-channel-conf 28_623 +GTP_CHANNEL_2.GTPE2_CHANNEL.CHAN_BOND_SEQ_LEN[1] origin:064-gtp-channel-conf 29_623 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COMMON_SWING[0] origin:064-gtp-channel-conf 31_311 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_KEEP_IDLE origin:064-gtp-channel-conf 28_591 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_MAX_LAT[0] origin:064-gtp-channel-conf 28_557 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_MAX_LAT[1] origin:064-gtp-channel-conf 29_557 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_MAX_LAT[2] origin:064-gtp-channel-conf 28_558 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_MAX_LAT[3] origin:064-gtp-channel-conf 29_558 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_MAX_LAT[4] origin:064-gtp-channel-conf 28_559 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_MAX_LAT[5] origin:064-gtp-channel-conf 29_559 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_MIN_LAT[0] origin:064-gtp-channel-conf 28_565 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_MIN_LAT[1] origin:064-gtp-channel-conf 29_565 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_MIN_LAT[2] origin:064-gtp-channel-conf 28_566 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_MIN_LAT[3] origin:064-gtp-channel-conf 29_566 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_MIN_LAT[4] origin:064-gtp-channel-conf 28_567 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_MIN_LAT[5] origin:064-gtp-channel-conf 29_567 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_PRECEDENCE origin:064-gtp-channel-conf 28_590 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_REPEAT_WAIT[0] origin:064-gtp-channel-conf 28_573 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_REPEAT_WAIT[1] origin:064-gtp-channel-conf 29_573 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_REPEAT_WAIT[2] origin:064-gtp-channel-conf 28_574 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_REPEAT_WAIT[3] origin:064-gtp-channel-conf 29_574 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_REPEAT_WAIT[4] origin:064-gtp-channel-conf 28_575 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[0] origin:064-gtp-channel-conf 28_544 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[1] origin:064-gtp-channel-conf 29_544 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[2] origin:064-gtp-channel-conf 28_545 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[3] origin:064-gtp-channel-conf 29_545 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[4] origin:064-gtp-channel-conf 28_546 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[5] origin:064-gtp-channel-conf 29_546 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[6] origin:064-gtp-channel-conf 28_547 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[7] origin:064-gtp-channel-conf 29_547 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[8] origin:064-gtp-channel-conf 28_548 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[9] origin:064-gtp-channel-conf 29_548 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[0] origin:064-gtp-channel-conf 28_552 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[1] origin:064-gtp-channel-conf 29_552 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[2] origin:064-gtp-channel-conf 28_553 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[3] origin:064-gtp-channel-conf 29_553 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[4] origin:064-gtp-channel-conf 28_554 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[5] origin:064-gtp-channel-conf 29_554 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[6] origin:064-gtp-channel-conf 28_555 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[7] origin:064-gtp-channel-conf 29_555 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[8] origin:064-gtp-channel-conf 28_556 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[9] origin:064-gtp-channel-conf 29_556 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[0] origin:064-gtp-channel-conf 28_560 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[1] origin:064-gtp-channel-conf 29_560 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[2] origin:064-gtp-channel-conf 28_561 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[3] origin:064-gtp-channel-conf 29_561 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[4] origin:064-gtp-channel-conf 28_562 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[5] origin:064-gtp-channel-conf 29_562 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[6] origin:064-gtp-channel-conf 28_563 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[7] origin:064-gtp-channel-conf 29_563 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[8] origin:064-gtp-channel-conf 28_564 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[9] origin:064-gtp-channel-conf 29_564 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[0] origin:064-gtp-channel-conf 28_568 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[1] origin:064-gtp-channel-conf 29_568 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[2] origin:064-gtp-channel-conf 28_569 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[3] origin:064-gtp-channel-conf 29_569 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[4] origin:064-gtp-channel-conf 28_570 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[5] origin:064-gtp-channel-conf 29_570 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[6] origin:064-gtp-channel-conf 28_571 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[7] origin:064-gtp-channel-conf 29_571 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[8] origin:064-gtp-channel-conf 28_572 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[9] origin:064-gtp-channel-conf 29_572 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_1_ENABLE[0] origin:064-gtp-channel-conf 28_549 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_1_ENABLE[1] origin:064-gtp-channel-conf 29_549 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_1_ENABLE[2] origin:064-gtp-channel-conf 28_550 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_1_ENABLE[3] origin:064-gtp-channel-conf 29_550 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[0] origin:064-gtp-channel-conf 28_576 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[1] origin:064-gtp-channel-conf 29_576 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[2] origin:064-gtp-channel-conf 28_577 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[3] origin:064-gtp-channel-conf 29_577 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[4] origin:064-gtp-channel-conf 28_578 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[5] origin:064-gtp-channel-conf 29_578 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[6] origin:064-gtp-channel-conf 28_579 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[7] origin:064-gtp-channel-conf 29_579 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[8] origin:064-gtp-channel-conf 28_580 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[9] origin:064-gtp-channel-conf 29_580 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[0] origin:064-gtp-channel-conf 28_584 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[1] origin:064-gtp-channel-conf 29_584 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[2] origin:064-gtp-channel-conf 28_585 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[3] origin:064-gtp-channel-conf 29_585 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[4] origin:064-gtp-channel-conf 28_586 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[5] origin:064-gtp-channel-conf 29_586 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[6] origin:064-gtp-channel-conf 28_587 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[7] origin:064-gtp-channel-conf 29_587 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[8] origin:064-gtp-channel-conf 28_588 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[9] origin:064-gtp-channel-conf 29_588 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[0] origin:064-gtp-channel-conf 28_592 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[1] origin:064-gtp-channel-conf 29_592 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[2] origin:064-gtp-channel-conf 28_593 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[3] origin:064-gtp-channel-conf 29_593 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[4] origin:064-gtp-channel-conf 28_594 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[5] origin:064-gtp-channel-conf 29_594 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[6] origin:064-gtp-channel-conf 28_595 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[7] origin:064-gtp-channel-conf 29_595 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[8] origin:064-gtp-channel-conf 28_596 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[9] origin:064-gtp-channel-conf 29_596 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[0] origin:064-gtp-channel-conf 28_600 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[1] origin:064-gtp-channel-conf 29_600 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[2] origin:064-gtp-channel-conf 28_601 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[3] origin:064-gtp-channel-conf 29_601 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[4] origin:064-gtp-channel-conf 28_602 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[5] origin:064-gtp-channel-conf 29_602 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[6] origin:064-gtp-channel-conf 28_603 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[7] origin:064-gtp-channel-conf 29_603 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[8] origin:064-gtp-channel-conf 28_604 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[9] origin:064-gtp-channel-conf 29_604 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_2_ENABLE[0] origin:064-gtp-channel-conf 28_581 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_2_ENABLE[1] origin:064-gtp-channel-conf 29_581 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_2_ENABLE[2] origin:064-gtp-channel-conf 28_582 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_2_ENABLE[3] origin:064-gtp-channel-conf 29_582 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_2_USE origin:064-gtp-channel-conf 28_583 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_LEN[0] origin:064-gtp-channel-conf 28_589 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_COR_SEQ_LEN[1] origin:064-gtp-channel-conf 29_589 +GTP_CHANNEL_2.GTPE2_CHANNEL.CLK_CORRECT_USE origin:064-gtp-channel-conf 28_551 +GTP_CHANNEL_2.GTPE2_CHANNEL.DEC_MCOMMA_DETECT origin:064-gtp-channel-conf 29_494 +GTP_CHANNEL_2.GTPE2_CHANNEL.DEC_PCOMMA_DETECT origin:064-gtp-channel-conf 28_495 +GTP_CHANNEL_2.GTPE2_CHANNEL.DEC_VALID_COMMA_ONLY origin:064-gtp-channel-conf 28_494 +GTP_CHANNEL_2.GTPE2_CHANNEL.DMONITOR_CFG[0] origin:064-gtp-channel-conf 30_368 +GTP_CHANNEL_2.GTPE2_CHANNEL.DMONITOR_CFG[1] origin:064-gtp-channel-conf 31_368 +GTP_CHANNEL_2.GTPE2_CHANNEL.DMONITOR_CFG[2] origin:064-gtp-channel-conf 30_369 +GTP_CHANNEL_2.GTPE2_CHANNEL.DMONITOR_CFG[3] origin:064-gtp-channel-conf 31_369 +GTP_CHANNEL_2.GTPE2_CHANNEL.DMONITOR_CFG[4] origin:064-gtp-channel-conf 30_370 +GTP_CHANNEL_2.GTPE2_CHANNEL.DMONITOR_CFG[5] origin:064-gtp-channel-conf 31_370 +GTP_CHANNEL_2.GTPE2_CHANNEL.DMONITOR_CFG[6] origin:064-gtp-channel-conf 30_371 +GTP_CHANNEL_2.GTPE2_CHANNEL.DMONITOR_CFG[7] origin:064-gtp-channel-conf 31_371 +GTP_CHANNEL_2.GTPE2_CHANNEL.DMONITOR_CFG[8] origin:064-gtp-channel-conf 30_372 +GTP_CHANNEL_2.GTPE2_CHANNEL.DMONITOR_CFG[9] origin:064-gtp-channel-conf 31_372 +GTP_CHANNEL_2.GTPE2_CHANNEL.DMONITOR_CFG[10] origin:064-gtp-channel-conf 30_373 +GTP_CHANNEL_2.GTPE2_CHANNEL.DMONITOR_CFG[11] origin:064-gtp-channel-conf 31_373 +GTP_CHANNEL_2.GTPE2_CHANNEL.DMONITOR_CFG[12] origin:064-gtp-channel-conf 30_374 +GTP_CHANNEL_2.GTPE2_CHANNEL.DMONITOR_CFG[13] origin:064-gtp-channel-conf 31_374 +GTP_CHANNEL_2.GTPE2_CHANNEL.DMONITOR_CFG[14] origin:064-gtp-channel-conf 30_375 +GTP_CHANNEL_2.GTPE2_CHANNEL.DMONITOR_CFG[15] origin:064-gtp-channel-conf 31_375 +GTP_CHANNEL_2.GTPE2_CHANNEL.DMONITOR_CFG[16] origin:064-gtp-channel-conf 30_376 +GTP_CHANNEL_2.GTPE2_CHANNEL.DMONITOR_CFG[17] origin:064-gtp-channel-conf 31_376 +GTP_CHANNEL_2.GTPE2_CHANNEL.DMONITOR_CFG[18] origin:064-gtp-channel-conf 30_377 +GTP_CHANNEL_2.GTPE2_CHANNEL.DMONITOR_CFG[19] origin:064-gtp-channel-conf 31_377 +GTP_CHANNEL_2.GTPE2_CHANNEL.DMONITOR_CFG[20] origin:064-gtp-channel-conf 30_378 +GTP_CHANNEL_2.GTPE2_CHANNEL.DMONITOR_CFG[21] origin:064-gtp-channel-conf 31_378 +GTP_CHANNEL_2.GTPE2_CHANNEL.DMONITOR_CFG[22] origin:064-gtp-channel-conf 30_379 +GTP_CHANNEL_2.GTPE2_CHANNEL.DMONITOR_CFG[23] origin:064-gtp-channel-conf 31_379 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_CLK_PHASE_SEL[0] origin:064-gtp-channel-conf 31_463 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_CONTROL[0] origin:064-gtp-channel-conf 28_488 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_CONTROL[1] origin:064-gtp-channel-conf 29_488 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_CONTROL[2] origin:064-gtp-channel-conf 28_489 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_CONTROL[3] origin:064-gtp-channel-conf 29_489 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_CONTROL[4] origin:064-gtp-channel-conf 28_490 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_CONTROL[5] origin:064-gtp-channel-conf 29_490 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_ERRDET_EN origin:064-gtp-channel-conf 29_492 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_EYE_SCAN_EN origin:064-gtp-channel-conf 28_492 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_HORZ_OFFSET[0] origin:064-gtp-channel-conf 28_480 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_HORZ_OFFSET[1] origin:064-gtp-channel-conf 29_480 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_HORZ_OFFSET[2] origin:064-gtp-channel-conf 28_481 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_HORZ_OFFSET[3] origin:064-gtp-channel-conf 29_481 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_HORZ_OFFSET[4] origin:064-gtp-channel-conf 28_482 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_HORZ_OFFSET[5] origin:064-gtp-channel-conf 29_482 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_HORZ_OFFSET[6] origin:064-gtp-channel-conf 28_483 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_HORZ_OFFSET[7] origin:064-gtp-channel-conf 29_483 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_HORZ_OFFSET[8] origin:064-gtp-channel-conf 28_484 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_HORZ_OFFSET[9] origin:064-gtp-channel-conf 29_484 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_HORZ_OFFSET[10] origin:064-gtp-channel-conf 28_485 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_HORZ_OFFSET[11] origin:064-gtp-channel-conf 29_485 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_PMA_CFG[0] origin:064-gtp-channel-conf 30_624 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_PMA_CFG[1] origin:064-gtp-channel-conf 31_624 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_PMA_CFG[2] origin:064-gtp-channel-conf 30_625 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_PMA_CFG[3] origin:064-gtp-channel-conf 31_625 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_PMA_CFG[4] origin:064-gtp-channel-conf 30_626 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_PMA_CFG[5] origin:064-gtp-channel-conf 31_626 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_PMA_CFG[6] origin:064-gtp-channel-conf 30_627 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_PMA_CFG[7] origin:064-gtp-channel-conf 31_627 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_PMA_CFG[8] origin:064-gtp-channel-conf 30_628 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_PMA_CFG[9] origin:064-gtp-channel-conf 31_628 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_PRESCALE[0] origin:064-gtp-channel-conf 29_477 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_PRESCALE[1] origin:064-gtp-channel-conf 28_478 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_PRESCALE[2] origin:064-gtp-channel-conf 29_478 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_PRESCALE[3] origin:064-gtp-channel-conf 28_479 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_PRESCALE[4] origin:064-gtp-channel-conf 29_479 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[0] origin:064-gtp-channel-conf 28_392 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[1] origin:064-gtp-channel-conf 29_392 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[2] origin:064-gtp-channel-conf 28_393 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[3] origin:064-gtp-channel-conf 29_393 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[4] origin:064-gtp-channel-conf 28_394 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[5] origin:064-gtp-channel-conf 29_394 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[6] origin:064-gtp-channel-conf 28_395 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[7] origin:064-gtp-channel-conf 29_395 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[8] origin:064-gtp-channel-conf 28_396 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[9] origin:064-gtp-channel-conf 29_396 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[10] origin:064-gtp-channel-conf 28_397 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[11] origin:064-gtp-channel-conf 29_397 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[12] origin:064-gtp-channel-conf 28_398 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[13] origin:064-gtp-channel-conf 29_398 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[14] origin:064-gtp-channel-conf 28_399 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[15] origin:064-gtp-channel-conf 29_399 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[16] origin:064-gtp-channel-conf 28_400 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[17] origin:064-gtp-channel-conf 29_400 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[18] origin:064-gtp-channel-conf 28_401 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[19] origin:064-gtp-channel-conf 29_401 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[20] origin:064-gtp-channel-conf 28_402 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[21] origin:064-gtp-channel-conf 29_402 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[22] origin:064-gtp-channel-conf 28_403 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[23] origin:064-gtp-channel-conf 29_403 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[24] origin:064-gtp-channel-conf 28_404 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[25] origin:064-gtp-channel-conf 29_404 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[26] origin:064-gtp-channel-conf 28_405 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[27] origin:064-gtp-channel-conf 29_405 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[28] origin:064-gtp-channel-conf 28_406 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[29] origin:064-gtp-channel-conf 29_406 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[30] origin:064-gtp-channel-conf 28_407 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[31] origin:064-gtp-channel-conf 29_407 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[32] origin:064-gtp-channel-conf 28_408 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[33] origin:064-gtp-channel-conf 29_408 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[34] origin:064-gtp-channel-conf 28_409 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[35] origin:064-gtp-channel-conf 29_409 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[36] origin:064-gtp-channel-conf 28_410 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[37] origin:064-gtp-channel-conf 29_410 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[38] origin:064-gtp-channel-conf 28_411 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[39] origin:064-gtp-channel-conf 29_411 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[40] origin:064-gtp-channel-conf 28_412 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[41] origin:064-gtp-channel-conf 29_412 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[42] origin:064-gtp-channel-conf 28_413 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[43] origin:064-gtp-channel-conf 29_413 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[44] origin:064-gtp-channel-conf 28_414 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[45] origin:064-gtp-channel-conf 29_414 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[46] origin:064-gtp-channel-conf 28_415 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[47] origin:064-gtp-channel-conf 29_415 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[48] origin:064-gtp-channel-conf 28_416 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[49] origin:064-gtp-channel-conf 29_416 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[50] origin:064-gtp-channel-conf 28_417 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[51] origin:064-gtp-channel-conf 29_417 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[52] origin:064-gtp-channel-conf 28_418 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[53] origin:064-gtp-channel-conf 29_418 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[54] origin:064-gtp-channel-conf 28_419 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[55] origin:064-gtp-channel-conf 29_419 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[56] origin:064-gtp-channel-conf 28_420 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[57] origin:064-gtp-channel-conf 29_420 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[58] origin:064-gtp-channel-conf 28_421 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[59] origin:064-gtp-channel-conf 29_421 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[60] origin:064-gtp-channel-conf 28_422 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[61] origin:064-gtp-channel-conf 29_422 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[62] origin:064-gtp-channel-conf 28_423 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[63] origin:064-gtp-channel-conf 29_423 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[64] origin:064-gtp-channel-conf 28_424 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[65] origin:064-gtp-channel-conf 29_424 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[66] origin:064-gtp-channel-conf 28_425 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[67] origin:064-gtp-channel-conf 29_425 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[68] origin:064-gtp-channel-conf 28_426 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[69] origin:064-gtp-channel-conf 29_426 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[70] origin:064-gtp-channel-conf 28_427 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[71] origin:064-gtp-channel-conf 29_427 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[72] origin:064-gtp-channel-conf 28_428 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[73] origin:064-gtp-channel-conf 29_428 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[74] origin:064-gtp-channel-conf 28_429 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[75] origin:064-gtp-channel-conf 29_429 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[76] origin:064-gtp-channel-conf 28_430 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[77] origin:064-gtp-channel-conf 29_430 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[78] origin:064-gtp-channel-conf 28_431 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUAL_MASK[79] origin:064-gtp-channel-conf 29_431 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[0] origin:064-gtp-channel-conf 28_352 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[1] origin:064-gtp-channel-conf 29_352 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[2] origin:064-gtp-channel-conf 28_353 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[3] origin:064-gtp-channel-conf 29_353 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[4] origin:064-gtp-channel-conf 28_354 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[5] origin:064-gtp-channel-conf 29_354 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[6] origin:064-gtp-channel-conf 28_355 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[7] origin:064-gtp-channel-conf 29_355 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[8] origin:064-gtp-channel-conf 28_356 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[9] origin:064-gtp-channel-conf 29_356 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[10] origin:064-gtp-channel-conf 28_357 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[11] origin:064-gtp-channel-conf 29_357 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[12] origin:064-gtp-channel-conf 28_358 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[13] origin:064-gtp-channel-conf 29_358 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[14] origin:064-gtp-channel-conf 28_359 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[15] origin:064-gtp-channel-conf 29_359 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[16] origin:064-gtp-channel-conf 28_360 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[17] origin:064-gtp-channel-conf 29_360 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[18] origin:064-gtp-channel-conf 28_361 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[19] origin:064-gtp-channel-conf 29_361 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[20] origin:064-gtp-channel-conf 28_362 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[21] origin:064-gtp-channel-conf 29_362 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[22] origin:064-gtp-channel-conf 28_363 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[23] origin:064-gtp-channel-conf 29_363 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[24] origin:064-gtp-channel-conf 28_364 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[25] origin:064-gtp-channel-conf 29_364 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[26] origin:064-gtp-channel-conf 28_365 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[27] origin:064-gtp-channel-conf 29_365 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[28] origin:064-gtp-channel-conf 28_366 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[29] origin:064-gtp-channel-conf 29_366 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[30] origin:064-gtp-channel-conf 28_367 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[31] origin:064-gtp-channel-conf 29_367 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[32] origin:064-gtp-channel-conf 28_368 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[33] origin:064-gtp-channel-conf 29_368 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[34] origin:064-gtp-channel-conf 28_369 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[35] origin:064-gtp-channel-conf 29_369 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[36] origin:064-gtp-channel-conf 28_370 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[37] origin:064-gtp-channel-conf 29_370 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[38] origin:064-gtp-channel-conf 28_371 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[39] origin:064-gtp-channel-conf 29_371 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[40] origin:064-gtp-channel-conf 28_372 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[41] origin:064-gtp-channel-conf 29_372 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[42] origin:064-gtp-channel-conf 28_373 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[43] origin:064-gtp-channel-conf 29_373 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[44] origin:064-gtp-channel-conf 28_374 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[45] origin:064-gtp-channel-conf 29_374 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[46] origin:064-gtp-channel-conf 28_375 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[47] origin:064-gtp-channel-conf 29_375 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[48] origin:064-gtp-channel-conf 28_376 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[49] origin:064-gtp-channel-conf 29_376 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[50] origin:064-gtp-channel-conf 28_377 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[51] origin:064-gtp-channel-conf 29_377 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[52] origin:064-gtp-channel-conf 28_378 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[53] origin:064-gtp-channel-conf 29_378 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[54] origin:064-gtp-channel-conf 28_379 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[55] origin:064-gtp-channel-conf 29_379 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[56] origin:064-gtp-channel-conf 28_380 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[57] origin:064-gtp-channel-conf 29_380 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[58] origin:064-gtp-channel-conf 28_381 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[59] origin:064-gtp-channel-conf 29_381 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[60] origin:064-gtp-channel-conf 28_382 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[61] origin:064-gtp-channel-conf 29_382 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[62] origin:064-gtp-channel-conf 28_383 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[63] origin:064-gtp-channel-conf 29_383 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[64] origin:064-gtp-channel-conf 28_384 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[65] origin:064-gtp-channel-conf 29_384 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[66] origin:064-gtp-channel-conf 28_385 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[67] origin:064-gtp-channel-conf 29_385 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[68] origin:064-gtp-channel-conf 28_386 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[69] origin:064-gtp-channel-conf 29_386 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[70] origin:064-gtp-channel-conf 28_387 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[71] origin:064-gtp-channel-conf 29_387 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[72] origin:064-gtp-channel-conf 28_388 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[73] origin:064-gtp-channel-conf 29_388 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[74] origin:064-gtp-channel-conf 28_389 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[75] origin:064-gtp-channel-conf 29_389 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[76] origin:064-gtp-channel-conf 28_390 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[77] origin:064-gtp-channel-conf 29_390 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[78] origin:064-gtp-channel-conf 28_391 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_QUALIFIER[79] origin:064-gtp-channel-conf 29_391 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[0] origin:064-gtp-channel-conf 28_432 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[1] origin:064-gtp-channel-conf 29_432 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[2] origin:064-gtp-channel-conf 28_433 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[3] origin:064-gtp-channel-conf 29_433 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[4] origin:064-gtp-channel-conf 28_434 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[5] origin:064-gtp-channel-conf 29_434 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[6] origin:064-gtp-channel-conf 28_435 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[7] origin:064-gtp-channel-conf 29_435 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[8] origin:064-gtp-channel-conf 28_436 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[9] origin:064-gtp-channel-conf 29_436 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[10] origin:064-gtp-channel-conf 28_437 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[11] origin:064-gtp-channel-conf 29_437 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[12] origin:064-gtp-channel-conf 28_438 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[13] origin:064-gtp-channel-conf 29_438 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[14] origin:064-gtp-channel-conf 28_439 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[15] origin:064-gtp-channel-conf 29_439 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[16] origin:064-gtp-channel-conf 28_440 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[17] origin:064-gtp-channel-conf 29_440 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[18] origin:064-gtp-channel-conf 28_441 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[19] origin:064-gtp-channel-conf 29_441 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[20] origin:064-gtp-channel-conf 28_442 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[21] origin:064-gtp-channel-conf 29_442 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[22] origin:064-gtp-channel-conf 28_443 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[23] origin:064-gtp-channel-conf 29_443 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[24] origin:064-gtp-channel-conf 28_444 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[25] origin:064-gtp-channel-conf 29_444 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[26] origin:064-gtp-channel-conf 28_445 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[27] origin:064-gtp-channel-conf 29_445 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[28] origin:064-gtp-channel-conf 28_446 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[29] origin:064-gtp-channel-conf 29_446 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[30] origin:064-gtp-channel-conf 28_447 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[31] origin:064-gtp-channel-conf 29_447 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[32] origin:064-gtp-channel-conf 28_448 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[33] origin:064-gtp-channel-conf 29_448 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[34] origin:064-gtp-channel-conf 28_449 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[35] origin:064-gtp-channel-conf 29_449 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[36] origin:064-gtp-channel-conf 28_450 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[37] origin:064-gtp-channel-conf 29_450 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[38] origin:064-gtp-channel-conf 28_451 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[39] origin:064-gtp-channel-conf 29_451 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[40] origin:064-gtp-channel-conf 28_452 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[41] origin:064-gtp-channel-conf 29_452 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[42] origin:064-gtp-channel-conf 28_453 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[43] origin:064-gtp-channel-conf 29_453 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[44] origin:064-gtp-channel-conf 28_454 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[45] origin:064-gtp-channel-conf 29_454 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[46] origin:064-gtp-channel-conf 28_455 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[47] origin:064-gtp-channel-conf 29_455 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[48] origin:064-gtp-channel-conf 28_456 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[49] origin:064-gtp-channel-conf 29_456 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[50] origin:064-gtp-channel-conf 28_457 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[51] origin:064-gtp-channel-conf 29_457 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[52] origin:064-gtp-channel-conf 28_458 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[53] origin:064-gtp-channel-conf 29_458 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[54] origin:064-gtp-channel-conf 28_459 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[55] origin:064-gtp-channel-conf 29_459 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[56] origin:064-gtp-channel-conf 28_460 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[57] origin:064-gtp-channel-conf 29_460 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[58] origin:064-gtp-channel-conf 28_461 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[59] origin:064-gtp-channel-conf 29_461 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[60] origin:064-gtp-channel-conf 28_462 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[61] origin:064-gtp-channel-conf 29_462 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[62] origin:064-gtp-channel-conf 28_463 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[63] origin:064-gtp-channel-conf 29_463 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[64] origin:064-gtp-channel-conf 28_464 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[65] origin:064-gtp-channel-conf 29_464 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[66] origin:064-gtp-channel-conf 28_465 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[67] origin:064-gtp-channel-conf 29_465 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[68] origin:064-gtp-channel-conf 28_466 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[69] origin:064-gtp-channel-conf 29_466 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[70] origin:064-gtp-channel-conf 28_467 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[71] origin:064-gtp-channel-conf 29_467 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[72] origin:064-gtp-channel-conf 28_468 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[73] origin:064-gtp-channel-conf 29_468 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[74] origin:064-gtp-channel-conf 28_469 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[75] origin:064-gtp-channel-conf 29_469 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[76] origin:064-gtp-channel-conf 28_470 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[77] origin:064-gtp-channel-conf 29_470 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[78] origin:064-gtp-channel-conf 28_471 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_SDATA_MASK[79] origin:064-gtp-channel-conf 29_471 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_VERT_OFFSET[0] origin:064-gtp-channel-conf 28_472 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_VERT_OFFSET[1] origin:064-gtp-channel-conf 29_472 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_VERT_OFFSET[2] origin:064-gtp-channel-conf 28_473 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_VERT_OFFSET[3] origin:064-gtp-channel-conf 29_473 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_VERT_OFFSET[4] origin:064-gtp-channel-conf 28_474 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_VERT_OFFSET[5] origin:064-gtp-channel-conf 29_474 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_VERT_OFFSET[6] origin:064-gtp-channel-conf 28_475 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_VERT_OFFSET[7] origin:064-gtp-channel-conf 29_475 +GTP_CHANNEL_2.GTPE2_CHANNEL.ES_VERT_OFFSET[8] origin:064-gtp-channel-conf 28_476 +GTP_CHANNEL_2.GTPE2_CHANNEL.FTS_DESKEW_SEQ_ENABLE[0] origin:064-gtp-channel-conf 28_662 +GTP_CHANNEL_2.GTPE2_CHANNEL.FTS_DESKEW_SEQ_ENABLE[1] origin:064-gtp-channel-conf 29_662 +GTP_CHANNEL_2.GTPE2_CHANNEL.FTS_DESKEW_SEQ_ENABLE[2] origin:064-gtp-channel-conf 28_663 +GTP_CHANNEL_2.GTPE2_CHANNEL.FTS_DESKEW_SEQ_ENABLE[3] origin:064-gtp-channel-conf 29_663 +GTP_CHANNEL_2.GTPE2_CHANNEL.FTS_LANE_DESKEW_CFG[0] origin:064-gtp-channel-conf 28_654 +GTP_CHANNEL_2.GTPE2_CHANNEL.FTS_LANE_DESKEW_CFG[1] origin:064-gtp-channel-conf 29_654 +GTP_CHANNEL_2.GTPE2_CHANNEL.FTS_LANE_DESKEW_CFG[2] origin:064-gtp-channel-conf 28_655 +GTP_CHANNEL_2.GTPE2_CHANNEL.FTS_LANE_DESKEW_CFG[3] origin:064-gtp-channel-conf 29_655 +GTP_CHANNEL_2.GTPE2_CHANNEL.FTS_LANE_DESKEW_EN origin:064-gtp-channel-conf 29_653 +GTP_CHANNEL_2.GTPE2_CHANNEL.GEARBOX_MODE[0] origin:064-gtp-channel-conf 28_224 +GTP_CHANNEL_2.GTPE2_CHANNEL.GEARBOX_MODE[1] origin:064-gtp-channel-conf 29_224 +GTP_CHANNEL_2.GTPE2_CHANNEL.GEARBOX_MODE[2] origin:064-gtp-channel-conf 28_225 +GTP_CHANNEL_2.GTPE2_CHANNEL.IN_USE origin:064-gtp-channel-conf 28_00 28_01 28_47 28_52 28_53 28_65 29_01 29_47 30_129 +GTP_CHANNEL_2.GTPE2_CHANNEL.INV_DMONITORCLK origin:064-gtp-channel-conf 30_13 +GTP_CHANNEL_2.GTPE2_CHANNEL.INV_DRPCLK origin:064-gtp-channel-conf 30_00 +GTP_CHANNEL_2.GTPE2_CHANNEL.INV_RXUSRCLK origin:064-gtp-channel-conf 31_01 +GTP_CHANNEL_2.GTPE2_CHANNEL.INV_SIGVALIDCLK origin:064-gtp-channel-conf 31_13 +GTP_CHANNEL_2.GTPE2_CHANNEL.INV_TXPHDLYTSTCLK origin:064-gtp-channel-conf 30_03 +GTP_CHANNEL_2.GTPE2_CHANNEL.INV_TXUSRCLK origin:064-gtp-channel-conf 31_04 +GTP_CHANNEL_2.GTPE2_CHANNEL.INV_CLKRSVD0 origin:064-gtp-channel-conf 30_23 +GTP_CHANNEL_2.GTPE2_CHANNEL.INV_CLKRSVD1 origin:064-gtp-channel-conf 31_23 +GTP_CHANNEL_2.GTPE2_CHANNEL.INV_RXUSRCLK2 origin:064-gtp-channel-conf 30_02 +GTP_CHANNEL_2.GTPE2_CHANNEL.INV_TXUSRCLK2 origin:064-gtp-channel-conf 30_05 +GTP_CHANNEL_2.GTPE2_CHANNEL.LOOPBACK_CFG[0] origin:064-gtp-channel-conf 30_20 +GTP_CHANNEL_2.GTPE2_CHANNEL.OUTREFCLK_SEL_INV[0] origin:064-gtp-channel-conf 28_149 +GTP_CHANNEL_2.GTPE2_CHANNEL.OUTREFCLK_SEL_INV[1] origin:064-gtp-channel-conf 29_149 +GTP_CHANNEL_2.GTPE2_CHANNEL.PCS_PCIE_EN origin:064-gtp-channel-conf 28_216 +GTP_CHANNEL_2.GTPE2_CHANNEL.PCS_RSVD_ATTR[0] origin:064-gtp-channel-conf 30_184 +GTP_CHANNEL_2.GTPE2_CHANNEL.PCS_RSVD_ATTR[1] origin:064-gtp-channel-conf 31_184 +GTP_CHANNEL_2.GTPE2_CHANNEL.PCS_RSVD_ATTR[2] origin:064-gtp-channel-conf 30_185 +GTP_CHANNEL_2.GTPE2_CHANNEL.PCS_RSVD_ATTR[3] origin:064-gtp-channel-conf 31_185 +GTP_CHANNEL_2.GTPE2_CHANNEL.PCS_RSVD_ATTR[4] origin:064-gtp-channel-conf 30_186 +GTP_CHANNEL_2.GTPE2_CHANNEL.PCS_RSVD_ATTR[5] origin:064-gtp-channel-conf 31_186 +GTP_CHANNEL_2.GTPE2_CHANNEL.PCS_RSVD_ATTR[6] origin:064-gtp-channel-conf 30_187 +GTP_CHANNEL_2.GTPE2_CHANNEL.PCS_RSVD_ATTR[7] origin:064-gtp-channel-conf 31_187 +GTP_CHANNEL_2.GTPE2_CHANNEL.PCS_RSVD_ATTR[8] origin:064-gtp-channel-conf 30_188 +GTP_CHANNEL_2.GTPE2_CHANNEL.PCS_RSVD_ATTR[9] origin:064-gtp-channel-conf 31_188 +GTP_CHANNEL_2.GTPE2_CHANNEL.PCS_RSVD_ATTR[10] origin:064-gtp-channel-conf 30_189 +GTP_CHANNEL_2.GTPE2_CHANNEL.PCS_RSVD_ATTR[11] origin:064-gtp-channel-conf 31_189 +GTP_CHANNEL_2.GTPE2_CHANNEL.PCS_RSVD_ATTR[12] origin:064-gtp-channel-conf 30_190 +GTP_CHANNEL_2.GTPE2_CHANNEL.PCS_RSVD_ATTR[13] origin:064-gtp-channel-conf 31_190 +GTP_CHANNEL_2.GTPE2_CHANNEL.PCS_RSVD_ATTR[14] origin:064-gtp-channel-conf 30_191 +GTP_CHANNEL_2.GTPE2_CHANNEL.PCS_RSVD_ATTR[15] origin:064-gtp-channel-conf 31_191 +GTP_CHANNEL_2.GTPE2_CHANNEL.PCS_RSVD_ATTR[16] origin:064-gtp-channel-conf 30_192 +GTP_CHANNEL_2.GTPE2_CHANNEL.PCS_RSVD_ATTR[17] origin:064-gtp-channel-conf 31_192 +GTP_CHANNEL_2.GTPE2_CHANNEL.PCS_RSVD_ATTR[18] origin:064-gtp-channel-conf 30_193 +GTP_CHANNEL_2.GTPE2_CHANNEL.PCS_RSVD_ATTR[19] origin:064-gtp-channel-conf 31_193 +GTP_CHANNEL_2.GTPE2_CHANNEL.PCS_RSVD_ATTR[20] origin:064-gtp-channel-conf 30_194 +GTP_CHANNEL_2.GTPE2_CHANNEL.PCS_RSVD_ATTR[21] origin:064-gtp-channel-conf 31_194 +GTP_CHANNEL_2.GTPE2_CHANNEL.PCS_RSVD_ATTR[22] origin:064-gtp-channel-conf 30_195 +GTP_CHANNEL_2.GTPE2_CHANNEL.PCS_RSVD_ATTR[23] origin:064-gtp-channel-conf 31_195 +GTP_CHANNEL_2.GTPE2_CHANNEL.PCS_RSVD_ATTR[24] origin:064-gtp-channel-conf 30_196 +GTP_CHANNEL_2.GTPE2_CHANNEL.PCS_RSVD_ATTR[25] origin:064-gtp-channel-conf 31_196 +GTP_CHANNEL_2.GTPE2_CHANNEL.PCS_RSVD_ATTR[26] origin:064-gtp-channel-conf 30_197 +GTP_CHANNEL_2.GTPE2_CHANNEL.PCS_RSVD_ATTR[27] origin:064-gtp-channel-conf 31_197 +GTP_CHANNEL_2.GTPE2_CHANNEL.PCS_RSVD_ATTR[28] origin:064-gtp-channel-conf 30_198 +GTP_CHANNEL_2.GTPE2_CHANNEL.PCS_RSVD_ATTR[29] origin:064-gtp-channel-conf 31_198 +GTP_CHANNEL_2.GTPE2_CHANNEL.PCS_RSVD_ATTR[30] origin:064-gtp-channel-conf 30_199 +GTP_CHANNEL_2.GTPE2_CHANNEL.PCS_RSVD_ATTR[31] origin:064-gtp-channel-conf 31_199 +GTP_CHANNEL_2.GTPE2_CHANNEL.PCS_RSVD_ATTR[32] origin:064-gtp-channel-conf 30_200 +GTP_CHANNEL_2.GTPE2_CHANNEL.PCS_RSVD_ATTR[33] origin:064-gtp-channel-conf 31_200 +GTP_CHANNEL_2.GTPE2_CHANNEL.PCS_RSVD_ATTR[34] origin:064-gtp-channel-conf 30_201 +GTP_CHANNEL_2.GTPE2_CHANNEL.PCS_RSVD_ATTR[35] origin:064-gtp-channel-conf 31_201 +GTP_CHANNEL_2.GTPE2_CHANNEL.PCS_RSVD_ATTR[36] origin:064-gtp-channel-conf 30_202 +GTP_CHANNEL_2.GTPE2_CHANNEL.PCS_RSVD_ATTR[37] origin:064-gtp-channel-conf 31_202 +GTP_CHANNEL_2.GTPE2_CHANNEL.PCS_RSVD_ATTR[38] origin:064-gtp-channel-conf 30_203 +GTP_CHANNEL_2.GTPE2_CHANNEL.PCS_RSVD_ATTR[39] origin:064-gtp-channel-conf 31_203 +GTP_CHANNEL_2.GTPE2_CHANNEL.PCS_RSVD_ATTR[40] origin:064-gtp-channel-conf 30_204 +GTP_CHANNEL_2.GTPE2_CHANNEL.PCS_RSVD_ATTR[41] origin:064-gtp-channel-conf 31_204 +GTP_CHANNEL_2.GTPE2_CHANNEL.PCS_RSVD_ATTR[42] origin:064-gtp-channel-conf 30_205 +GTP_CHANNEL_2.GTPE2_CHANNEL.PCS_RSVD_ATTR[43] origin:064-gtp-channel-conf 31_205 +GTP_CHANNEL_2.GTPE2_CHANNEL.PCS_RSVD_ATTR[44] origin:064-gtp-channel-conf 30_206 +GTP_CHANNEL_2.GTPE2_CHANNEL.PCS_RSVD_ATTR[45] origin:064-gtp-channel-conf 31_206 +GTP_CHANNEL_2.GTPE2_CHANNEL.PCS_RSVD_ATTR[46] origin:064-gtp-channel-conf 30_207 +GTP_CHANNEL_2.GTPE2_CHANNEL.PCS_RSVD_ATTR[47] origin:064-gtp-channel-conf 31_207 +GTP_CHANNEL_2.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[0] origin:064-gtp-channel-conf 29_216 +GTP_CHANNEL_2.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[1] origin:064-gtp-channel-conf 28_217 +GTP_CHANNEL_2.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[2] origin:064-gtp-channel-conf 29_217 +GTP_CHANNEL_2.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[3] origin:064-gtp-channel-conf 28_218 +GTP_CHANNEL_2.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[4] origin:064-gtp-channel-conf 29_218 +GTP_CHANNEL_2.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[5] origin:064-gtp-channel-conf 28_219 +GTP_CHANNEL_2.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[6] origin:064-gtp-channel-conf 29_219 +GTP_CHANNEL_2.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[7] origin:064-gtp-channel-conf 28_220 +GTP_CHANNEL_2.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[8] origin:064-gtp-channel-conf 29_220 +GTP_CHANNEL_2.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[9] origin:064-gtp-channel-conf 28_221 +GTP_CHANNEL_2.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[10] origin:064-gtp-channel-conf 29_221 +GTP_CHANNEL_2.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[11] origin:064-gtp-channel-conf 28_222 +GTP_CHANNEL_2.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[0] origin:064-gtp-channel-conf 28_208 +GTP_CHANNEL_2.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[1] origin:064-gtp-channel-conf 29_208 +GTP_CHANNEL_2.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[2] origin:064-gtp-channel-conf 28_209 +GTP_CHANNEL_2.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[3] origin:064-gtp-channel-conf 29_209 +GTP_CHANNEL_2.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[4] origin:064-gtp-channel-conf 28_210 +GTP_CHANNEL_2.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[5] origin:064-gtp-channel-conf 29_210 +GTP_CHANNEL_2.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[6] origin:064-gtp-channel-conf 28_211 +GTP_CHANNEL_2.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[7] origin:064-gtp-channel-conf 29_211 +GTP_CHANNEL_2.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[0] origin:064-gtp-channel-conf 28_212 +GTP_CHANNEL_2.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[1] origin:064-gtp-channel-conf 29_212 +GTP_CHANNEL_2.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[2] origin:064-gtp-channel-conf 28_213 +GTP_CHANNEL_2.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[3] origin:064-gtp-channel-conf 29_213 +GTP_CHANNEL_2.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[4] origin:064-gtp-channel-conf 28_214 +GTP_CHANNEL_2.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[5] origin:064-gtp-channel-conf 29_214 +GTP_CHANNEL_2.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[6] origin:064-gtp-channel-conf 28_215 +GTP_CHANNEL_2.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[7] origin:064-gtp-channel-conf 29_215 +GTP_CHANNEL_2.GTPE2_CHANNEL.PMA_LOOPBACK_CFG[0] origin:064-gtp-channel-conf 29_207 +GTP_CHANNEL_2.GTPE2_CHANNEL.PMA_RSV[0] origin:064-gtp-channel-conf 30_520 +GTP_CHANNEL_2.GTPE2_CHANNEL.PMA_RSV[1] origin:064-gtp-channel-conf 31_520 +GTP_CHANNEL_2.GTPE2_CHANNEL.PMA_RSV[2] origin:064-gtp-channel-conf 30_521 +GTP_CHANNEL_2.GTPE2_CHANNEL.PMA_RSV[3] origin:064-gtp-channel-conf 31_521 +GTP_CHANNEL_2.GTPE2_CHANNEL.PMA_RSV[4] origin:064-gtp-channel-conf 30_522 +GTP_CHANNEL_2.GTPE2_CHANNEL.PMA_RSV[5] origin:064-gtp-channel-conf 31_522 +GTP_CHANNEL_2.GTPE2_CHANNEL.PMA_RSV[6] origin:064-gtp-channel-conf 30_523 +GTP_CHANNEL_2.GTPE2_CHANNEL.PMA_RSV[7] origin:064-gtp-channel-conf 31_523 +GTP_CHANNEL_2.GTPE2_CHANNEL.PMA_RSV[8] origin:064-gtp-channel-conf 30_524 +GTP_CHANNEL_2.GTPE2_CHANNEL.PMA_RSV[9] origin:064-gtp-channel-conf 31_524 +GTP_CHANNEL_2.GTPE2_CHANNEL.PMA_RSV[10] origin:064-gtp-channel-conf 30_525 +GTP_CHANNEL_2.GTPE2_CHANNEL.PMA_RSV[11] origin:064-gtp-channel-conf 31_525 +GTP_CHANNEL_2.GTPE2_CHANNEL.PMA_RSV[12] origin:064-gtp-channel-conf 30_526 +GTP_CHANNEL_2.GTPE2_CHANNEL.PMA_RSV[13] origin:064-gtp-channel-conf 31_526 +GTP_CHANNEL_2.GTPE2_CHANNEL.PMA_RSV[14] origin:064-gtp-channel-conf 30_527 +GTP_CHANNEL_2.GTPE2_CHANNEL.PMA_RSV[15] origin:064-gtp-channel-conf 31_527 +GTP_CHANNEL_2.GTPE2_CHANNEL.PMA_RSV[16] origin:064-gtp-channel-conf 30_528 +GTP_CHANNEL_2.GTPE2_CHANNEL.PMA_RSV[17] origin:064-gtp-channel-conf 31_528 +GTP_CHANNEL_2.GTPE2_CHANNEL.PMA_RSV[18] origin:064-gtp-channel-conf 30_529 +GTP_CHANNEL_2.GTPE2_CHANNEL.PMA_RSV[19] origin:064-gtp-channel-conf 31_529 +GTP_CHANNEL_2.GTPE2_CHANNEL.PMA_RSV[20] origin:064-gtp-channel-conf 30_530 +GTP_CHANNEL_2.GTPE2_CHANNEL.PMA_RSV[21] origin:064-gtp-channel-conf 31_530 +GTP_CHANNEL_2.GTPE2_CHANNEL.PMA_RSV[22] origin:064-gtp-channel-conf 30_531 +GTP_CHANNEL_2.GTPE2_CHANNEL.PMA_RSV[23] origin:064-gtp-channel-conf 31_531 +GTP_CHANNEL_2.GTPE2_CHANNEL.PMA_RSV[24] origin:064-gtp-channel-conf 30_532 +GTP_CHANNEL_2.GTPE2_CHANNEL.PMA_RSV[25] origin:064-gtp-channel-conf 31_532 +GTP_CHANNEL_2.GTPE2_CHANNEL.PMA_RSV[26] origin:064-gtp-channel-conf 30_533 +GTP_CHANNEL_2.GTPE2_CHANNEL.PMA_RSV[27] origin:064-gtp-channel-conf 31_533 +GTP_CHANNEL_2.GTPE2_CHANNEL.PMA_RSV[28] origin:064-gtp-channel-conf 30_534 +GTP_CHANNEL_2.GTPE2_CHANNEL.PMA_RSV[29] origin:064-gtp-channel-conf 31_534 +GTP_CHANNEL_2.GTPE2_CHANNEL.PMA_RSV[30] origin:064-gtp-channel-conf 30_535 +GTP_CHANNEL_2.GTPE2_CHANNEL.PMA_RSV[31] origin:064-gtp-channel-conf 31_535 +GTP_CHANNEL_2.GTPE2_CHANNEL.PMA_RSV2[0] origin:064-gtp-channel-conf 30_336 +GTP_CHANNEL_2.GTPE2_CHANNEL.PMA_RSV2[1] origin:064-gtp-channel-conf 31_336 +GTP_CHANNEL_2.GTPE2_CHANNEL.PMA_RSV2[2] origin:064-gtp-channel-conf 30_337 +GTP_CHANNEL_2.GTPE2_CHANNEL.PMA_RSV2[3] origin:064-gtp-channel-conf 31_337 +GTP_CHANNEL_2.GTPE2_CHANNEL.PMA_RSV2[4] origin:064-gtp-channel-conf 30_338 +GTP_CHANNEL_2.GTPE2_CHANNEL.PMA_RSV2[5] origin:064-gtp-channel-conf 31_338 +GTP_CHANNEL_2.GTPE2_CHANNEL.PMA_RSV2[6] origin:064-gtp-channel-conf 30_339 +GTP_CHANNEL_2.GTPE2_CHANNEL.PMA_RSV2[7] origin:064-gtp-channel-conf 31_339 +GTP_CHANNEL_2.GTPE2_CHANNEL.PMA_RSV2[8] origin:064-gtp-channel-conf 30_340 +GTP_CHANNEL_2.GTPE2_CHANNEL.PMA_RSV2[9] origin:064-gtp-channel-conf 31_340 +GTP_CHANNEL_2.GTPE2_CHANNEL.PMA_RSV2[10] origin:064-gtp-channel-conf 30_341 +GTP_CHANNEL_2.GTPE2_CHANNEL.PMA_RSV2[11] origin:064-gtp-channel-conf 31_341 +GTP_CHANNEL_2.GTPE2_CHANNEL.PMA_RSV2[12] origin:064-gtp-channel-conf 30_342 +GTP_CHANNEL_2.GTPE2_CHANNEL.PMA_RSV2[13] origin:064-gtp-channel-conf 31_342 +GTP_CHANNEL_2.GTPE2_CHANNEL.PMA_RSV2[14] origin:064-gtp-channel-conf 30_343 +GTP_CHANNEL_2.GTPE2_CHANNEL.PMA_RSV2[15] origin:064-gtp-channel-conf 31_343 +GTP_CHANNEL_2.GTPE2_CHANNEL.PMA_RSV2[16] origin:064-gtp-channel-conf 30_344 +GTP_CHANNEL_2.GTPE2_CHANNEL.PMA_RSV2[17] origin:064-gtp-channel-conf 31_344 +GTP_CHANNEL_2.GTPE2_CHANNEL.PMA_RSV2[18] origin:064-gtp-channel-conf 30_345 +GTP_CHANNEL_2.GTPE2_CHANNEL.PMA_RSV2[19] origin:064-gtp-channel-conf 31_345 +GTP_CHANNEL_2.GTPE2_CHANNEL.PMA_RSV2[20] origin:064-gtp-channel-conf 30_346 +GTP_CHANNEL_2.GTPE2_CHANNEL.PMA_RSV2[21] origin:064-gtp-channel-conf 31_346 +GTP_CHANNEL_2.GTPE2_CHANNEL.PMA_RSV2[22] origin:064-gtp-channel-conf 30_347 +GTP_CHANNEL_2.GTPE2_CHANNEL.PMA_RSV2[23] origin:064-gtp-channel-conf 31_347 +GTP_CHANNEL_2.GTPE2_CHANNEL.PMA_RSV2[24] origin:064-gtp-channel-conf 30_348 +GTP_CHANNEL_2.GTPE2_CHANNEL.PMA_RSV2[25] origin:064-gtp-channel-conf 31_348 +GTP_CHANNEL_2.GTPE2_CHANNEL.PMA_RSV2[26] origin:064-gtp-channel-conf 30_349 +GTP_CHANNEL_2.GTPE2_CHANNEL.PMA_RSV2[27] origin:064-gtp-channel-conf 31_349 +GTP_CHANNEL_2.GTPE2_CHANNEL.PMA_RSV2[28] origin:064-gtp-channel-conf 30_350 +GTP_CHANNEL_2.GTPE2_CHANNEL.PMA_RSV2[29] origin:064-gtp-channel-conf 31_350 +GTP_CHANNEL_2.GTPE2_CHANNEL.PMA_RSV2[30] origin:064-gtp-channel-conf 30_351 +GTP_CHANNEL_2.GTPE2_CHANNEL.PMA_RSV2[31] origin:064-gtp-channel-conf 31_351 +GTP_CHANNEL_2.GTPE2_CHANNEL.PMA_RSV3[0] origin:064-gtp-channel-conf 30_288 +GTP_CHANNEL_2.GTPE2_CHANNEL.PMA_RSV3[1] origin:064-gtp-channel-conf 31_288 +GTP_CHANNEL_2.GTPE2_CHANNEL.PMA_RSV4[0] origin:064-gtp-channel-conf 30_156 +GTP_CHANNEL_2.GTPE2_CHANNEL.PMA_RSV4[1] origin:064-gtp-channel-conf 31_156 +GTP_CHANNEL_2.GTPE2_CHANNEL.PMA_RSV4[2] origin:064-gtp-channel-conf 30_157 +GTP_CHANNEL_2.GTPE2_CHANNEL.PMA_RSV4[3] origin:064-gtp-channel-conf 31_157 +GTP_CHANNEL_2.GTPE2_CHANNEL.PMA_RSV5[0] origin:064-gtp-channel-conf 31_159 +GTP_CHANNEL_2.GTPE2_CHANNEL.PMA_RSV6[0] origin:064-gtp-channel-conf 30_303 +GTP_CHANNEL_2.GTPE2_CHANNEL.PMA_RSV7[0] origin:064-gtp-channel-conf 31_303 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_BIAS_CFG[0] origin:064-gtp-channel-conf 30_112 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_BIAS_CFG[1] origin:064-gtp-channel-conf 31_112 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_BIAS_CFG[2] origin:064-gtp-channel-conf 30_113 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_BIAS_CFG[3] origin:064-gtp-channel-conf 31_113 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_BIAS_CFG[4] origin:064-gtp-channel-conf 30_114 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_BIAS_CFG[5] origin:064-gtp-channel-conf 31_114 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_BIAS_CFG[6] origin:064-gtp-channel-conf 30_115 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_BIAS_CFG[7] origin:064-gtp-channel-conf 31_115 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_BIAS_CFG[8] origin:064-gtp-channel-conf 30_116 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_BIAS_CFG[9] origin:064-gtp-channel-conf 31_116 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_BIAS_CFG[10] origin:064-gtp-channel-conf 30_117 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_BIAS_CFG[11] origin:064-gtp-channel-conf 31_117 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_BIAS_CFG[12] origin:064-gtp-channel-conf 30_118 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_BIAS_CFG[13] origin:064-gtp-channel-conf 31_118 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_BIAS_CFG[14] origin:064-gtp-channel-conf 30_119 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_BIAS_CFG[15] origin:064-gtp-channel-conf 31_119 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_BUFFER_CFG[0] origin:064-gtp-channel-conf 30_536 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_BUFFER_CFG[1] origin:064-gtp-channel-conf 31_536 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_BUFFER_CFG[2] origin:064-gtp-channel-conf 30_537 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_BUFFER_CFG[3] origin:064-gtp-channel-conf 31_537 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_BUFFER_CFG[4] origin:064-gtp-channel-conf 30_538 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_BUFFER_CFG[5] origin:064-gtp-channel-conf 31_538 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_CLKMUX_EN[0] origin:064-gtp-channel-conf 30_128 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_CM_SEL[0] origin:064-gtp-channel-conf 28_138 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_CM_SEL[1] origin:064-gtp-channel-conf 29_138 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_CM_TRIM[0] origin:064-gtp-channel-conf 30_304 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_CM_TRIM[1] origin:064-gtp-channel-conf 31_304 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_CM_TRIM[2] origin:064-gtp-channel-conf 30_305 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_CM_TRIM[3] origin:064-gtp-channel-conf 31_305 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_DATA_WIDTH[0] origin:064-gtp-channel-conf 29_141 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_DATA_WIDTH[1] origin:064-gtp-channel-conf 28_142 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_DATA_WIDTH[2] origin:064-gtp-channel-conf 29_142 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_DDI_SEL[0] origin:064-gtp-channel-conf 28_696 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_DDI_SEL[1] origin:064-gtp-channel-conf 29_696 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_DDI_SEL[2] origin:064-gtp-channel-conf 28_697 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_DDI_SEL[3] origin:064-gtp-channel-conf 29_697 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_DDI_SEL[4] origin:064-gtp-channel-conf 28_698 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_DDI_SEL[5] origin:064-gtp-channel-conf 29_698 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_DEBUG_CFG[0] origin:064-gtp-channel-conf 30_616 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_DEBUG_CFG[1] origin:064-gtp-channel-conf 31_616 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_DEBUG_CFG[2] origin:064-gtp-channel-conf 30_617 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_DEBUG_CFG[3] origin:064-gtp-channel-conf 31_617 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_DEBUG_CFG[4] origin:064-gtp-channel-conf 30_618 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_DEBUG_CFG[5] origin:064-gtp-channel-conf 31_618 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_DEBUG_CFG[6] origin:064-gtp-channel-conf 30_619 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_DEBUG_CFG[7] origin:064-gtp-channel-conf 31_619 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_DEBUG_CFG[8] origin:064-gtp-channel-conf 30_620 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_DEBUG_CFG[9] origin:064-gtp-channel-conf 31_620 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_DEBUG_CFG[10] origin:064-gtp-channel-conf 30_621 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_DEBUG_CFG[11] origin:064-gtp-channel-conf 31_621 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_DEBUG_CFG[12] origin:064-gtp-channel-conf 30_622 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_DEBUG_CFG[13] origin:064-gtp-channel-conf 31_622 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_DEFER_RESET_BUF_EN origin:064-gtp-channel-conf 30_552 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_DISPERR_SEQ_MATCH origin:064-gtp-channel-conf 29_495 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_OS_CFG[0] origin:064-gtp-channel-conf 28_288 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_OS_CFG[1] origin:064-gtp-channel-conf 29_288 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_OS_CFG[2] origin:064-gtp-channel-conf 28_289 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_OS_CFG[3] origin:064-gtp-channel-conf 29_289 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_OS_CFG[4] origin:064-gtp-channel-conf 28_290 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_OS_CFG[5] origin:064-gtp-channel-conf 29_290 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_OS_CFG[6] origin:064-gtp-channel-conf 28_291 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_OS_CFG[7] origin:064-gtp-channel-conf 29_291 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_OS_CFG[8] origin:064-gtp-channel-conf 28_292 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_OS_CFG[9] origin:064-gtp-channel-conf 29_292 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_OS_CFG[10] origin:064-gtp-channel-conf 28_293 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_OS_CFG[11] origin:064-gtp-channel-conf 29_293 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_OS_CFG[12] origin:064-gtp-channel-conf 28_294 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_SIG_VALID_DLY[0] origin:064-gtp-channel-conf 28_524 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_SIG_VALID_DLY[1] origin:064-gtp-channel-conf 29_524 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_SIG_VALID_DLY[2] origin:064-gtp-channel-conf 28_525 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_SIG_VALID_DLY[3] origin:064-gtp-channel-conf 29_525 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_SIG_VALID_DLY[4] origin:064-gtp-channel-conf 28_526 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_XCLK_SEL.RXUSR origin:064-gtp-channel-conf 28_143 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_CLK25_DIV[0] origin:064-gtp-channel-conf 28_139 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_CLK25_DIV[1] origin:064-gtp-channel-conf 29_139 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_CLK25_DIV[2] origin:064-gtp-channel-conf 28_140 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_CLK25_DIV[3] origin:064-gtp-channel-conf 29_140 +GTP_CHANNEL_2.GTPE2_CHANNEL.RX_CLK25_DIV[4] origin:064-gtp-channel-conf 28_141 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXBUF_ADDR_MODE.FAST origin:064-gtp-channel-conf 31_555 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXBUF_EIDLE_HI_CNT[0] origin:064-gtp-channel-conf 30_558 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXBUF_EIDLE_HI_CNT[1] origin:064-gtp-channel-conf 31_558 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXBUF_EIDLE_HI_CNT[2] origin:064-gtp-channel-conf 30_559 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXBUF_EIDLE_HI_CNT[3] origin:064-gtp-channel-conf 31_559 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXBUF_EIDLE_LO_CNT[0] origin:064-gtp-channel-conf 30_556 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXBUF_EIDLE_LO_CNT[1] origin:064-gtp-channel-conf 31_556 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXBUF_EIDLE_LO_CNT[2] origin:064-gtp-channel-conf 30_557 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXBUF_EIDLE_LO_CNT[3] origin:064-gtp-channel-conf 31_557 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXBUF_EN origin:064-gtp-channel-conf 30_11 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXBUF_RESET_ON_CB_CHANGE origin:064-gtp-channel-conf 30_560 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXBUF_RESET_ON_COMMAALIGN origin:064-gtp-channel-conf 30_561 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXBUF_RESET_ON_EIDLE origin:064-gtp-channel-conf 30_547 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXBUF_RESET_ON_RATE_CHANGE origin:064-gtp-channel-conf 31_560 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXBUF_THRESH_OVFLW[0] origin:064-gtp-channel-conf 31_552 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXBUF_THRESH_OVFLW[1] origin:064-gtp-channel-conf 30_553 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXBUF_THRESH_OVFLW[2] origin:064-gtp-channel-conf 31_553 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXBUF_THRESH_OVFLW[3] origin:064-gtp-channel-conf 30_554 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXBUF_THRESH_OVFLW[4] origin:064-gtp-channel-conf 31_554 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXBUF_THRESH_OVFLW[5] origin:064-gtp-channel-conf 30_555 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXBUF_THRESH_OVRD origin:064-gtp-channel-conf 30_548 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXBUF_THRESH_UNDFLW[0] origin:064-gtp-channel-conf 30_544 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXBUF_THRESH_UNDFLW[1] origin:064-gtp-channel-conf 31_544 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXBUF_THRESH_UNDFLW[2] origin:064-gtp-channel-conf 30_545 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXBUF_THRESH_UNDFLW[3] origin:064-gtp-channel-conf 31_545 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXBUF_THRESH_UNDFLW[4] origin:064-gtp-channel-conf 30_546 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXBUF_THRESH_UNDFLW[5] origin:064-gtp-channel-conf 31_546 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXBUFRESET_TIME[0] origin:064-gtp-channel-conf 29_101 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXBUFRESET_TIME[1] origin:064-gtp-channel-conf 28_102 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXBUFRESET_TIME[2] origin:064-gtp-channel-conf 29_102 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXBUFRESET_TIME[3] origin:064-gtp-channel-conf 28_103 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXBUFRESET_TIME[4] origin:064-gtp-channel-conf 29_103 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[0] origin:064-gtp-channel-conf 30_640 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[1] origin:064-gtp-channel-conf 31_640 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[2] origin:064-gtp-channel-conf 30_641 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[3] origin:064-gtp-channel-conf 31_641 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[4] origin:064-gtp-channel-conf 30_642 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[5] origin:064-gtp-channel-conf 31_642 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[6] origin:064-gtp-channel-conf 30_643 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[7] origin:064-gtp-channel-conf 31_643 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[8] origin:064-gtp-channel-conf 30_644 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[9] origin:064-gtp-channel-conf 31_644 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[10] origin:064-gtp-channel-conf 30_645 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[11] origin:064-gtp-channel-conf 31_645 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[12] origin:064-gtp-channel-conf 30_646 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[13] origin:064-gtp-channel-conf 31_646 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[14] origin:064-gtp-channel-conf 30_647 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[15] origin:064-gtp-channel-conf 31_647 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[16] origin:064-gtp-channel-conf 30_648 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[17] origin:064-gtp-channel-conf 31_648 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[18] origin:064-gtp-channel-conf 30_649 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[19] origin:064-gtp-channel-conf 31_649 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[20] origin:064-gtp-channel-conf 30_650 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[21] origin:064-gtp-channel-conf 31_650 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[22] origin:064-gtp-channel-conf 30_651 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[23] origin:064-gtp-channel-conf 31_651 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[24] origin:064-gtp-channel-conf 30_652 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[25] origin:064-gtp-channel-conf 31_652 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[26] origin:064-gtp-channel-conf 30_653 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[27] origin:064-gtp-channel-conf 31_653 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[28] origin:064-gtp-channel-conf 30_654 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[29] origin:064-gtp-channel-conf 31_654 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[30] origin:064-gtp-channel-conf 30_655 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[31] origin:064-gtp-channel-conf 31_655 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[32] origin:064-gtp-channel-conf 30_656 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[33] origin:064-gtp-channel-conf 31_656 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[34] origin:064-gtp-channel-conf 30_657 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[35] origin:064-gtp-channel-conf 31_657 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[36] origin:064-gtp-channel-conf 30_658 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[37] origin:064-gtp-channel-conf 31_658 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[38] origin:064-gtp-channel-conf 30_659 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[39] origin:064-gtp-channel-conf 31_659 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[40] origin:064-gtp-channel-conf 30_660 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[41] origin:064-gtp-channel-conf 31_660 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[42] origin:064-gtp-channel-conf 30_661 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[43] origin:064-gtp-channel-conf 31_661 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[44] origin:064-gtp-channel-conf 30_662 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[45] origin:064-gtp-channel-conf 31_662 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[46] origin:064-gtp-channel-conf 30_663 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[47] origin:064-gtp-channel-conf 31_663 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[48] origin:064-gtp-channel-conf 30_664 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[49] origin:064-gtp-channel-conf 31_664 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[50] origin:064-gtp-channel-conf 30_665 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[51] origin:064-gtp-channel-conf 31_665 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[52] origin:064-gtp-channel-conf 30_666 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[53] origin:064-gtp-channel-conf 31_666 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[54] origin:064-gtp-channel-conf 30_667 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[55] origin:064-gtp-channel-conf 31_667 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[56] origin:064-gtp-channel-conf 30_668 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[57] origin:064-gtp-channel-conf 31_668 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[58] origin:064-gtp-channel-conf 30_669 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[59] origin:064-gtp-channel-conf 31_669 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[60] origin:064-gtp-channel-conf 30_670 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[61] origin:064-gtp-channel-conf 31_670 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[62] origin:064-gtp-channel-conf 30_671 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[63] origin:064-gtp-channel-conf 31_671 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[64] origin:064-gtp-channel-conf 30_672 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[65] origin:064-gtp-channel-conf 31_672 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[66] origin:064-gtp-channel-conf 30_673 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[67] origin:064-gtp-channel-conf 31_673 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[68] origin:064-gtp-channel-conf 30_674 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[69] origin:064-gtp-channel-conf 31_674 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[70] origin:064-gtp-channel-conf 30_675 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[71] origin:064-gtp-channel-conf 31_675 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[72] origin:064-gtp-channel-conf 30_676 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[73] origin:064-gtp-channel-conf 31_676 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[74] origin:064-gtp-channel-conf 30_677 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[75] origin:064-gtp-channel-conf 31_677 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[76] origin:064-gtp-channel-conf 30_678 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[77] origin:064-gtp-channel-conf 31_678 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[78] origin:064-gtp-channel-conf 30_679 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[79] origin:064-gtp-channel-conf 31_679 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[80] origin:064-gtp-channel-conf 30_680 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[81] origin:064-gtp-channel-conf 31_680 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_CFG[82] origin:064-gtp-channel-conf 30_681 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_FR_RESET_ON_EIDLE[0] origin:064-gtp-channel-conf 30_638 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_HOLD_DURING_EIDLE[0] origin:064-gtp-channel-conf 31_637 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_LOCK_CFG[0] origin:064-gtp-channel-conf 30_632 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_LOCK_CFG[1] origin:064-gtp-channel-conf 31_632 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_LOCK_CFG[2] origin:064-gtp-channel-conf 30_633 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_LOCK_CFG[3] origin:064-gtp-channel-conf 31_633 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_LOCK_CFG[4] origin:064-gtp-channel-conf 30_634 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_LOCK_CFG[5] origin:064-gtp-channel-conf 31_634 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDR_PH_RESET_ON_EIDLE[0] origin:064-gtp-channel-conf 31_638 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDRFREQRESET_TIME[0] origin:064-gtp-channel-conf 29_106 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDRFREQRESET_TIME[1] origin:064-gtp-channel-conf 28_107 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDRFREQRESET_TIME[2] origin:064-gtp-channel-conf 29_107 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDRFREQRESET_TIME[3] origin:064-gtp-channel-conf 28_108 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDRFREQRESET_TIME[4] origin:064-gtp-channel-conf 29_108 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDRPHRESET_TIME[0] origin:064-gtp-channel-conf 28_109 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDRPHRESET_TIME[1] origin:064-gtp-channel-conf 29_109 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDRPHRESET_TIME[2] origin:064-gtp-channel-conf 28_110 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDRPHRESET_TIME[3] origin:064-gtp-channel-conf 29_110 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXCDRPHRESET_TIME[4] origin:064-gtp-channel-conf 28_111 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXDLY_CFG[0] origin:064-gtp-channel-conf 28_680 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXDLY_CFG[1] origin:064-gtp-channel-conf 29_680 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXDLY_CFG[2] origin:064-gtp-channel-conf 28_681 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXDLY_CFG[3] origin:064-gtp-channel-conf 29_681 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXDLY_CFG[4] origin:064-gtp-channel-conf 28_682 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXDLY_CFG[5] origin:064-gtp-channel-conf 29_682 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXDLY_CFG[6] origin:064-gtp-channel-conf 28_683 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXDLY_CFG[7] origin:064-gtp-channel-conf 29_683 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXDLY_CFG[8] origin:064-gtp-channel-conf 28_684 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXDLY_CFG[9] origin:064-gtp-channel-conf 29_684 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXDLY_CFG[10] origin:064-gtp-channel-conf 28_685 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXDLY_CFG[11] origin:064-gtp-channel-conf 29_685 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXDLY_CFG[12] origin:064-gtp-channel-conf 28_686 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXDLY_CFG[13] origin:064-gtp-channel-conf 29_686 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXDLY_CFG[14] origin:064-gtp-channel-conf 28_687 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXDLY_CFG[15] origin:064-gtp-channel-conf 29_687 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXDLY_LCFG[0] origin:064-gtp-channel-conf 30_576 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXDLY_LCFG[1] origin:064-gtp-channel-conf 31_576 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXDLY_LCFG[2] origin:064-gtp-channel-conf 30_577 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXDLY_LCFG[3] origin:064-gtp-channel-conf 31_577 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXDLY_LCFG[4] origin:064-gtp-channel-conf 30_578 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXDLY_LCFG[5] origin:064-gtp-channel-conf 31_578 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXDLY_LCFG[6] origin:064-gtp-channel-conf 30_579 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXDLY_LCFG[7] origin:064-gtp-channel-conf 31_579 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXDLY_LCFG[8] origin:064-gtp-channel-conf 30_580 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXDLY_TAP_CFG[0] origin:064-gtp-channel-conf 28_672 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXDLY_TAP_CFG[1] origin:064-gtp-channel-conf 29_672 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXDLY_TAP_CFG[2] origin:064-gtp-channel-conf 28_673 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXDLY_TAP_CFG[3] origin:064-gtp-channel-conf 29_673 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXDLY_TAP_CFG[4] origin:064-gtp-channel-conf 28_674 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXDLY_TAP_CFG[5] origin:064-gtp-channel-conf 29_674 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXDLY_TAP_CFG[6] origin:064-gtp-channel-conf 28_675 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXDLY_TAP_CFG[7] origin:064-gtp-channel-conf 29_675 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXDLY_TAP_CFG[8] origin:064-gtp-channel-conf 28_676 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXDLY_TAP_CFG[9] origin:064-gtp-channel-conf 29_676 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXDLY_TAP_CFG[10] origin:064-gtp-channel-conf 28_677 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXDLY_TAP_CFG[11] origin:064-gtp-channel-conf 29_677 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXDLY_TAP_CFG[12] origin:064-gtp-channel-conf 28_678 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXDLY_TAP_CFG[13] origin:064-gtp-channel-conf 29_678 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXDLY_TAP_CFG[14] origin:064-gtp-channel-conf 28_679 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXDLY_TAP_CFG[15] origin:064-gtp-channel-conf 29_679 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXGEARBOX_EN origin:064-gtp-channel-conf 29_607 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXISCANRESET_TIME[0] origin:064-gtp-channel-conf 29_123 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXISCANRESET_TIME[1] origin:064-gtp-channel-conf 28_124 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXISCANRESET_TIME[2] origin:064-gtp-channel-conf 29_124 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXISCANRESET_TIME[3] origin:064-gtp-channel-conf 28_125 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXISCANRESET_TIME[4] origin:064-gtp-channel-conf 29_125 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPM_BIAS_STARTUP_DISABLE[0] origin:064-gtp-channel-conf 31_391 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPM_CFG[0] origin:064-gtp-channel-conf 30_328 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPM_CFG[1] origin:064-gtp-channel-conf 31_328 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPM_CFG[2] origin:064-gtp-channel-conf 30_329 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPM_CFG[3] origin:064-gtp-channel-conf 31_329 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPM_CM_CFG[0] origin:064-gtp-channel-conf 30_430 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPM_GC_CFG[0] origin:064-gtp-channel-conf 30_432 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPM_GC_CFG[1] origin:064-gtp-channel-conf 31_432 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPM_GC_CFG[2] origin:064-gtp-channel-conf 30_433 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPM_GC_CFG[3] origin:064-gtp-channel-conf 31_433 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPM_GC_CFG[4] origin:064-gtp-channel-conf 30_434 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPM_GC_CFG[5] origin:064-gtp-channel-conf 31_434 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPM_GC_CFG[6] origin:064-gtp-channel-conf 30_435 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPM_GC_CFG[7] origin:064-gtp-channel-conf 31_435 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPM_GC_CFG[8] origin:064-gtp-channel-conf 30_436 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPM_GC_CFG2[0] origin:064-gtp-channel-conf 31_442 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPM_GC_CFG2[1] origin:064-gtp-channel-conf 30_443 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPM_GC_CFG2[2] origin:064-gtp-channel-conf 31_443 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPM_HF_CFG[0] origin:064-gtp-channel-conf 28_336 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPM_HF_CFG[1] origin:064-gtp-channel-conf 29_336 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPM_HF_CFG[2] origin:064-gtp-channel-conf 28_337 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPM_HF_CFG[3] origin:064-gtp-channel-conf 29_337 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPM_HF_CFG[4] origin:064-gtp-channel-conf 28_338 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPM_HF_CFG[5] origin:064-gtp-channel-conf 29_338 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPM_HF_CFG[6] origin:064-gtp-channel-conf 28_339 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPM_HF_CFG[7] origin:064-gtp-channel-conf 29_339 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPM_HF_CFG[8] origin:064-gtp-channel-conf 28_340 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPM_HF_CFG[9] origin:064-gtp-channel-conf 29_340 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPM_HF_CFG[10] origin:064-gtp-channel-conf 28_341 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPM_HF_CFG[11] origin:064-gtp-channel-conf 29_341 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPM_HF_CFG[12] origin:064-gtp-channel-conf 28_342 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPM_HF_CFG[13] origin:064-gtp-channel-conf 29_342 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPM_HF_CFG2[0] origin:064-gtp-channel-conf 30_424 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPM_HF_CFG2[1] origin:064-gtp-channel-conf 31_424 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPM_HF_CFG2[2] origin:064-gtp-channel-conf 30_425 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPM_HF_CFG2[3] origin:064-gtp-channel-conf 31_425 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPM_HF_CFG2[4] origin:064-gtp-channel-conf 30_426 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPM_HF_CFG3[0] origin:064-gtp-channel-conf 31_389 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPM_HF_CFG3[1] origin:064-gtp-channel-conf 30_390 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPM_HF_CFG3[2] origin:064-gtp-channel-conf 31_390 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPM_HF_CFG3[3] origin:064-gtp-channel-conf 30_391 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPM_HOLD_DURING_EIDLE[0] origin:064-gtp-channel-conf 28_247 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPM_INCM_CFG[0] origin:064-gtp-channel-conf 30_439 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPM_IPCM_CFG[0] origin:064-gtp-channel-conf 31_439 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPM_LF_CFG[0] origin:064-gtp-channel-conf 28_344 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPM_LF_CFG[1] origin:064-gtp-channel-conf 29_344 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPM_LF_CFG[2] origin:064-gtp-channel-conf 28_345 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPM_LF_CFG[3] origin:064-gtp-channel-conf 29_345 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPM_LF_CFG[4] origin:064-gtp-channel-conf 28_346 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPM_LF_CFG[5] origin:064-gtp-channel-conf 29_346 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPM_LF_CFG[6] origin:064-gtp-channel-conf 28_347 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPM_LF_CFG[7] origin:064-gtp-channel-conf 29_347 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPM_LF_CFG[8] origin:064-gtp-channel-conf 28_348 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPM_LF_CFG[9] origin:064-gtp-channel-conf 29_348 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPM_LF_CFG[10] origin:064-gtp-channel-conf 28_349 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPM_LF_CFG[11] origin:064-gtp-channel-conf 29_349 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPM_LF_CFG[12] origin:064-gtp-channel-conf 28_350 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPM_LF_CFG[13] origin:064-gtp-channel-conf 29_350 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPM_LF_CFG[14] origin:064-gtp-channel-conf 28_351 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPM_LF_CFG[15] origin:064-gtp-channel-conf 29_351 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPM_LF_CFG[16] origin:064-gtp-channel-conf 28_343 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPM_LF_CFG[17] origin:064-gtp-channel-conf 29_343 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPM_LF_CFG2[0] origin:064-gtp-channel-conf 31_426 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPM_LF_CFG2[1] origin:064-gtp-channel-conf 30_427 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPM_LF_CFG2[2] origin:064-gtp-channel-conf 31_427 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPM_LF_CFG2[3] origin:064-gtp-channel-conf 30_428 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPM_LF_CFG2[4] origin:064-gtp-channel-conf 31_428 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPM_OSINT_CFG[0] origin:064-gtp-channel-conf 30_440 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPM_OSINT_CFG[1] origin:064-gtp-channel-conf 31_440 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPM_OSINT_CFG[2] origin:064-gtp-channel-conf 30_441 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPM_CFG1[0] origin:064-gtp-channel-conf 30_330 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPMRESET_TIME[0] origin:064-gtp-channel-conf 28_112 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPMRESET_TIME[1] origin:064-gtp-channel-conf 29_112 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPMRESET_TIME[2] origin:064-gtp-channel-conf 28_113 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPMRESET_TIME[3] origin:064-gtp-channel-conf 29_113 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPMRESET_TIME[4] origin:064-gtp-channel-conf 28_114 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPMRESET_TIME[5] origin:064-gtp-channel-conf 29_114 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXLPMRESET_TIME[6] origin:064-gtp-channel-conf 28_115 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXOOB_CFG[0] origin:064-gtp-channel-conf 28_144 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXOOB_CFG[1] origin:064-gtp-channel-conf 29_144 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXOOB_CFG[2] origin:064-gtp-channel-conf 28_145 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXOOB_CFG[3] origin:064-gtp-channel-conf 29_145 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXOOB_CFG[4] origin:064-gtp-channel-conf 28_146 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXOOB_CFG[5] origin:064-gtp-channel-conf 29_146 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXOOB_CFG[6] origin:064-gtp-channel-conf 28_147 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXOOB_CLK_CFG.FABRIC origin:064-gtp-channel-conf 31_129 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXOSCALRESET_TIME[0] origin:064-gtp-channel-conf 28_187 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXOSCALRESET_TIME[1] origin:064-gtp-channel-conf 29_187 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXOSCALRESET_TIME[2] origin:064-gtp-channel-conf 28_188 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXOSCALRESET_TIME[3] origin:064-gtp-channel-conf 29_188 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXOSCALRESET_TIME[4] origin:064-gtp-channel-conf 28_189 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXOSCALRESET_TIMEOUT[0] origin:064-gtp-channel-conf 29_189 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXOSCALRESET_TIMEOUT[1] origin:064-gtp-channel-conf 28_190 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXOSCALRESET_TIMEOUT[2] origin:064-gtp-channel-conf 29_190 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXOSCALRESET_TIMEOUT[3] origin:064-gtp-channel-conf 28_191 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXOSCALRESET_TIMEOUT[4] origin:064-gtp-channel-conf 29_191 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXOUT_DIV[0] origin:064-gtp-channel-conf 30_384 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXOUT_DIV[1] origin:064-gtp-channel-conf 31_384 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXPCSRESET_TIME[0] origin:064-gtp-channel-conf 29_115 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXPCSRESET_TIME[1] origin:064-gtp-channel-conf 28_116 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXPCSRESET_TIME[2] origin:064-gtp-channel-conf 29_116 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXPCSRESET_TIME[3] origin:064-gtp-channel-conf 28_117 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXPCSRESET_TIME[4] origin:064-gtp-channel-conf 29_117 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXPH_CFG[0] origin:064-gtp-channel-conf 30_584 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXPH_CFG[1] origin:064-gtp-channel-conf 31_584 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXPH_CFG[2] origin:064-gtp-channel-conf 30_585 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXPH_CFG[3] origin:064-gtp-channel-conf 31_585 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXPH_CFG[4] origin:064-gtp-channel-conf 30_586 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXPH_CFG[5] origin:064-gtp-channel-conf 31_586 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXPH_CFG[6] origin:064-gtp-channel-conf 30_587 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXPH_CFG[7] origin:064-gtp-channel-conf 31_587 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXPH_CFG[8] origin:064-gtp-channel-conf 30_588 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXPH_CFG[9] origin:064-gtp-channel-conf 31_588 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXPH_CFG[10] origin:064-gtp-channel-conf 30_589 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXPH_CFG[11] origin:064-gtp-channel-conf 31_589 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXPH_CFG[12] origin:064-gtp-channel-conf 30_590 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXPH_CFG[13] origin:064-gtp-channel-conf 31_590 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXPH_CFG[14] origin:064-gtp-channel-conf 30_591 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXPH_CFG[15] origin:064-gtp-channel-conf 31_591 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXPH_CFG[16] origin:064-gtp-channel-conf 30_592 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXPH_CFG[17] origin:064-gtp-channel-conf 31_592 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXPH_CFG[18] origin:064-gtp-channel-conf 30_593 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXPH_CFG[19] origin:064-gtp-channel-conf 31_593 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXPH_CFG[20] origin:064-gtp-channel-conf 30_594 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXPH_CFG[21] origin:064-gtp-channel-conf 31_594 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXPH_CFG[22] origin:064-gtp-channel-conf 30_595 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXPH_CFG[23] origin:064-gtp-channel-conf 31_595 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXPH_MONITOR_SEL[0] origin:064-gtp-channel-conf 28_700 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXPH_MONITOR_SEL[1] origin:064-gtp-channel-conf 29_700 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXPH_MONITOR_SEL[2] origin:064-gtp-channel-conf 28_701 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXPH_MONITOR_SEL[3] origin:064-gtp-channel-conf 29_701 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXPH_MONITOR_SEL[4] origin:064-gtp-channel-conf 28_702 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXPHDLY_CFG[0] origin:064-gtp-channel-conf 30_600 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXPHDLY_CFG[1] origin:064-gtp-channel-conf 31_600 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXPHDLY_CFG[2] origin:064-gtp-channel-conf 30_601 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXPHDLY_CFG[3] origin:064-gtp-channel-conf 31_601 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXPHDLY_CFG[4] origin:064-gtp-channel-conf 30_602 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXPHDLY_CFG[5] origin:064-gtp-channel-conf 31_602 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXPHDLY_CFG[6] origin:064-gtp-channel-conf 30_603 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXPHDLY_CFG[7] origin:064-gtp-channel-conf 31_603 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXPHDLY_CFG[8] origin:064-gtp-channel-conf 30_604 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXPHDLY_CFG[9] origin:064-gtp-channel-conf 31_604 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXPHDLY_CFG[10] origin:064-gtp-channel-conf 30_605 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXPHDLY_CFG[11] origin:064-gtp-channel-conf 31_605 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXPHDLY_CFG[12] origin:064-gtp-channel-conf 30_606 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXPHDLY_CFG[13] origin:064-gtp-channel-conf 31_606 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXPHDLY_CFG[14] origin:064-gtp-channel-conf 30_607 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXPHDLY_CFG[15] origin:064-gtp-channel-conf 31_607 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXPHDLY_CFG[16] origin:064-gtp-channel-conf 30_608 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXPHDLY_CFG[17] origin:064-gtp-channel-conf 31_608 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXPHDLY_CFG[18] origin:064-gtp-channel-conf 30_609 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXPHDLY_CFG[19] origin:064-gtp-channel-conf 31_609 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXPHDLY_CFG[20] origin:064-gtp-channel-conf 30_610 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXPHDLY_CFG[21] origin:064-gtp-channel-conf 31_610 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXPHDLY_CFG[22] origin:064-gtp-channel-conf 30_611 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXPHDLY_CFG[23] origin:064-gtp-channel-conf 31_611 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXPI_CFG0[0] origin:064-gtp-channel-conf 31_430 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXPI_CFG0[1] origin:064-gtp-channel-conf 30_431 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXPI_CFG0[2] origin:064-gtp-channel-conf 31_431 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXPI_CFG1[0] origin:064-gtp-channel-conf 30_442 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXPI_CFG2[0] origin:064-gtp-channel-conf 31_441 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXPMARESET_TIME[0] origin:064-gtp-channel-conf 28_104 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXPMARESET_TIME[1] origin:064-gtp-channel-conf 29_104 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXPMARESET_TIME[2] origin:064-gtp-channel-conf 28_105 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXPMARESET_TIME[3] origin:064-gtp-channel-conf 29_105 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXPMARESET_TIME[4] origin:064-gtp-channel-conf 28_106 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXPRBS_ERR_LOOPBACK[0] origin:064-gtp-channel-conf 28_136 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXSLIDE_AUTO_WAIT[0] origin:064-gtp-channel-conf 28_520 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXSLIDE_AUTO_WAIT[1] origin:064-gtp-channel-conf 29_520 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXSLIDE_AUTO_WAIT[2] origin:064-gtp-channel-conf 28_521 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXSLIDE_AUTO_WAIT[3] origin:064-gtp-channel-conf 29_521 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXSLIDE_MODE.AUTO origin:064-gtp-channel-conf !29_519 28_519 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXSLIDE_MODE.PCS origin:064-gtp-channel-conf !28_519 29_519 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXSLIDE_MODE.PMA origin:064-gtp-channel-conf 28_519 29_519 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXSYNC_MULTILANE[0] origin:064-gtp-channel-conf 28_133 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXSYNC_OVRD[0] origin:064-gtp-channel-conf 29_135 +GTP_CHANNEL_2.GTPE2_CHANNEL.RXSYNC_SKIP_DA[0] origin:064-gtp-channel-conf 29_134 +GTP_CHANNEL_2.GTPE2_CHANNEL.SAS_MAX_COM[0] origin:064-gtp-channel-conf 28_171 +GTP_CHANNEL_2.GTPE2_CHANNEL.SAS_MAX_COM[1] origin:064-gtp-channel-conf 29_171 +GTP_CHANNEL_2.GTPE2_CHANNEL.SAS_MAX_COM[2] origin:064-gtp-channel-conf 28_172 +GTP_CHANNEL_2.GTPE2_CHANNEL.SAS_MAX_COM[3] origin:064-gtp-channel-conf 29_172 +GTP_CHANNEL_2.GTPE2_CHANNEL.SAS_MAX_COM[4] origin:064-gtp-channel-conf 28_173 +GTP_CHANNEL_2.GTPE2_CHANNEL.SAS_MAX_COM[5] origin:064-gtp-channel-conf 29_173 +GTP_CHANNEL_2.GTPE2_CHANNEL.SAS_MAX_COM[6] origin:064-gtp-channel-conf 28_174 +GTP_CHANNEL_2.GTPE2_CHANNEL.SAS_MIN_COM[0] origin:064-gtp-channel-conf 29_156 +GTP_CHANNEL_2.GTPE2_CHANNEL.SAS_MIN_COM[1] origin:064-gtp-channel-conf 28_157 +GTP_CHANNEL_2.GTPE2_CHANNEL.SAS_MIN_COM[2] origin:064-gtp-channel-conf 29_157 +GTP_CHANNEL_2.GTPE2_CHANNEL.SAS_MIN_COM[3] origin:064-gtp-channel-conf 28_158 +GTP_CHANNEL_2.GTPE2_CHANNEL.SAS_MIN_COM[4] origin:064-gtp-channel-conf 29_158 +GTP_CHANNEL_2.GTPE2_CHANNEL.SAS_MIN_COM[5] origin:064-gtp-channel-conf 28_159 +GTP_CHANNEL_2.GTPE2_CHANNEL.SATA_BURST_SEQ_LEN[0] origin:064-gtp-channel-conf 28_150 +GTP_CHANNEL_2.GTPE2_CHANNEL.SATA_BURST_SEQ_LEN[1] origin:064-gtp-channel-conf 29_150 +GTP_CHANNEL_2.GTPE2_CHANNEL.SATA_BURST_SEQ_LEN[2] origin:064-gtp-channel-conf 28_151 +GTP_CHANNEL_2.GTPE2_CHANNEL.SATA_BURST_SEQ_LEN[3] origin:064-gtp-channel-conf 29_151 +GTP_CHANNEL_2.GTPE2_CHANNEL.SATA_BURST_VAL[0] origin:064-gtp-channel-conf 29_147 +GTP_CHANNEL_2.GTPE2_CHANNEL.SATA_BURST_VAL[1] origin:064-gtp-channel-conf 28_148 +GTP_CHANNEL_2.GTPE2_CHANNEL.SATA_BURST_VAL[2] origin:064-gtp-channel-conf 29_148 +GTP_CHANNEL_2.GTPE2_CHANNEL.SATA_EIDLE_VAL[0] origin:064-gtp-channel-conf 28_152 +GTP_CHANNEL_2.GTPE2_CHANNEL.SATA_EIDLE_VAL[1] origin:064-gtp-channel-conf 29_152 +GTP_CHANNEL_2.GTPE2_CHANNEL.SATA_EIDLE_VAL[2] origin:064-gtp-channel-conf 28_153 +GTP_CHANNEL_2.GTPE2_CHANNEL.SATA_MAX_BURST[0] origin:064-gtp-channel-conf 28_168 +GTP_CHANNEL_2.GTPE2_CHANNEL.SATA_MAX_BURST[1] origin:064-gtp-channel-conf 29_168 +GTP_CHANNEL_2.GTPE2_CHANNEL.SATA_MAX_BURST[2] origin:064-gtp-channel-conf 28_169 +GTP_CHANNEL_2.GTPE2_CHANNEL.SATA_MAX_BURST[3] origin:064-gtp-channel-conf 29_169 +GTP_CHANNEL_2.GTPE2_CHANNEL.SATA_MAX_BURST[4] origin:064-gtp-channel-conf 28_170 +GTP_CHANNEL_2.GTPE2_CHANNEL.SATA_MAX_BURST[5] origin:064-gtp-channel-conf 29_170 +GTP_CHANNEL_2.GTPE2_CHANNEL.SATA_MAX_INIT[0] origin:064-gtp-channel-conf 28_176 +GTP_CHANNEL_2.GTPE2_CHANNEL.SATA_MAX_INIT[1] origin:064-gtp-channel-conf 29_176 +GTP_CHANNEL_2.GTPE2_CHANNEL.SATA_MAX_INIT[2] origin:064-gtp-channel-conf 28_177 +GTP_CHANNEL_2.GTPE2_CHANNEL.SATA_MAX_INIT[3] origin:064-gtp-channel-conf 29_177 +GTP_CHANNEL_2.GTPE2_CHANNEL.SATA_MAX_INIT[4] origin:064-gtp-channel-conf 28_178 +GTP_CHANNEL_2.GTPE2_CHANNEL.SATA_MAX_INIT[5] origin:064-gtp-channel-conf 29_178 +GTP_CHANNEL_2.GTPE2_CHANNEL.SATA_MAX_WAKE[0] origin:064-gtp-channel-conf 28_179 +GTP_CHANNEL_2.GTPE2_CHANNEL.SATA_MAX_WAKE[1] origin:064-gtp-channel-conf 29_179 +GTP_CHANNEL_2.GTPE2_CHANNEL.SATA_MAX_WAKE[2] origin:064-gtp-channel-conf 28_180 +GTP_CHANNEL_2.GTPE2_CHANNEL.SATA_MAX_WAKE[3] origin:064-gtp-channel-conf 29_180 +GTP_CHANNEL_2.GTPE2_CHANNEL.SATA_MAX_WAKE[4] origin:064-gtp-channel-conf 28_181 +GTP_CHANNEL_2.GTPE2_CHANNEL.SATA_MAX_WAKE[5] origin:064-gtp-channel-conf 29_181 +GTP_CHANNEL_2.GTPE2_CHANNEL.SATA_MIN_BURST[0] origin:064-gtp-channel-conf 29_153 +GTP_CHANNEL_2.GTPE2_CHANNEL.SATA_MIN_BURST[1] origin:064-gtp-channel-conf 28_154 +GTP_CHANNEL_2.GTPE2_CHANNEL.SATA_MIN_BURST[2] origin:064-gtp-channel-conf 29_154 +GTP_CHANNEL_2.GTPE2_CHANNEL.SATA_MIN_BURST[3] origin:064-gtp-channel-conf 28_155 +GTP_CHANNEL_2.GTPE2_CHANNEL.SATA_MIN_BURST[4] origin:064-gtp-channel-conf 29_155 +GTP_CHANNEL_2.GTPE2_CHANNEL.SATA_MIN_BURST[5] origin:064-gtp-channel-conf 28_156 +GTP_CHANNEL_2.GTPE2_CHANNEL.SATA_MIN_INIT[0] origin:064-gtp-channel-conf 28_160 +GTP_CHANNEL_2.GTPE2_CHANNEL.SATA_MIN_INIT[1] origin:064-gtp-channel-conf 29_160 +GTP_CHANNEL_2.GTPE2_CHANNEL.SATA_MIN_INIT[2] origin:064-gtp-channel-conf 28_161 +GTP_CHANNEL_2.GTPE2_CHANNEL.SATA_MIN_INIT[3] origin:064-gtp-channel-conf 29_161 +GTP_CHANNEL_2.GTPE2_CHANNEL.SATA_MIN_INIT[4] origin:064-gtp-channel-conf 28_162 +GTP_CHANNEL_2.GTPE2_CHANNEL.SATA_MIN_INIT[5] origin:064-gtp-channel-conf 29_162 +GTP_CHANNEL_2.GTPE2_CHANNEL.SATA_MIN_WAKE[0] origin:064-gtp-channel-conf 28_163 +GTP_CHANNEL_2.GTPE2_CHANNEL.SATA_MIN_WAKE[1] origin:064-gtp-channel-conf 29_163 +GTP_CHANNEL_2.GTPE2_CHANNEL.SATA_MIN_WAKE[2] origin:064-gtp-channel-conf 28_164 +GTP_CHANNEL_2.GTPE2_CHANNEL.SATA_MIN_WAKE[3] origin:064-gtp-channel-conf 29_164 +GTP_CHANNEL_2.GTPE2_CHANNEL.SATA_MIN_WAKE[4] origin:064-gtp-channel-conf 28_165 +GTP_CHANNEL_2.GTPE2_CHANNEL.SATA_MIN_WAKE[5] origin:064-gtp-channel-conf 29_165 +GTP_CHANNEL_2.GTPE2_CHANNEL.SATA_PLL_CFG.VCO_1500MHZ origin:064-gtp-channel-conf 30_55 +GTP_CHANNEL_2.GTPE2_CHANNEL.SATA_PLL_CFG.VCO_750MHZ origin:064-gtp-channel-conf 31_55 +GTP_CHANNEL_2.GTPE2_CHANNEL.SHOW_REALIGN_COMMA origin:064-gtp-channel-conf 29_522 +GTP_CHANNEL_2.GTPE2_CHANNEL.TERM_RCAL_CFG[0] origin:064-gtp-channel-conf 30_136 +GTP_CHANNEL_2.GTPE2_CHANNEL.TERM_RCAL_CFG[1] origin:064-gtp-channel-conf 31_136 +GTP_CHANNEL_2.GTPE2_CHANNEL.TERM_RCAL_CFG[2] origin:064-gtp-channel-conf 30_137 +GTP_CHANNEL_2.GTPE2_CHANNEL.TERM_RCAL_CFG[3] origin:064-gtp-channel-conf 31_137 +GTP_CHANNEL_2.GTPE2_CHANNEL.TERM_RCAL_CFG[4] origin:064-gtp-channel-conf 30_138 +GTP_CHANNEL_2.GTPE2_CHANNEL.TERM_RCAL_CFG[5] origin:064-gtp-channel-conf 31_138 +GTP_CHANNEL_2.GTPE2_CHANNEL.TERM_RCAL_CFG[6] origin:064-gtp-channel-conf 30_139 +GTP_CHANNEL_2.GTPE2_CHANNEL.TERM_RCAL_CFG[7] origin:064-gtp-channel-conf 31_139 +GTP_CHANNEL_2.GTPE2_CHANNEL.TERM_RCAL_CFG[8] origin:064-gtp-channel-conf 30_140 +GTP_CHANNEL_2.GTPE2_CHANNEL.TERM_RCAL_CFG[9] origin:064-gtp-channel-conf 31_140 +GTP_CHANNEL_2.GTPE2_CHANNEL.TERM_RCAL_CFG[10] origin:064-gtp-channel-conf 30_141 +GTP_CHANNEL_2.GTPE2_CHANNEL.TERM_RCAL_CFG[11] origin:064-gtp-channel-conf 31_141 +GTP_CHANNEL_2.GTPE2_CHANNEL.TERM_RCAL_CFG[12] origin:064-gtp-channel-conf 30_142 +GTP_CHANNEL_2.GTPE2_CHANNEL.TERM_RCAL_CFG[13] origin:064-gtp-channel-conf 31_142 +GTP_CHANNEL_2.GTPE2_CHANNEL.TERM_RCAL_CFG[14] origin:064-gtp-channel-conf 30_143 +GTP_CHANNEL_2.GTPE2_CHANNEL.TERM_RCAL_OVRD[0] origin:064-gtp-channel-conf 31_150 +GTP_CHANNEL_2.GTPE2_CHANNEL.TERM_RCAL_OVRD[1] origin:064-gtp-channel-conf 30_151 +GTP_CHANNEL_2.GTPE2_CHANNEL.TERM_RCAL_OVRD[2] origin:064-gtp-channel-conf 31_151 +GTP_CHANNEL_2.GTPE2_CHANNEL.TRANS_TIME_RATE[0] origin:064-gtp-channel-conf 28_192 +GTP_CHANNEL_2.GTPE2_CHANNEL.TRANS_TIME_RATE[1] origin:064-gtp-channel-conf 29_192 +GTP_CHANNEL_2.GTPE2_CHANNEL.TRANS_TIME_RATE[2] origin:064-gtp-channel-conf 28_193 +GTP_CHANNEL_2.GTPE2_CHANNEL.TRANS_TIME_RATE[3] origin:064-gtp-channel-conf 29_193 +GTP_CHANNEL_2.GTPE2_CHANNEL.TRANS_TIME_RATE[4] origin:064-gtp-channel-conf 28_194 +GTP_CHANNEL_2.GTPE2_CHANNEL.TRANS_TIME_RATE[5] origin:064-gtp-channel-conf 29_194 +GTP_CHANNEL_2.GTPE2_CHANNEL.TRANS_TIME_RATE[6] origin:064-gtp-channel-conf 28_195 +GTP_CHANNEL_2.GTPE2_CHANNEL.TRANS_TIME_RATE[7] origin:064-gtp-channel-conf 29_195 +GTP_CHANNEL_2.GTPE2_CHANNEL.TST_RSV[0] origin:064-gtp-channel-conf 30_504 +GTP_CHANNEL_2.GTPE2_CHANNEL.TST_RSV[1] origin:064-gtp-channel-conf 31_504 +GTP_CHANNEL_2.GTPE2_CHANNEL.TST_RSV[2] origin:064-gtp-channel-conf 30_505 +GTP_CHANNEL_2.GTPE2_CHANNEL.TST_RSV[3] origin:064-gtp-channel-conf 31_505 +GTP_CHANNEL_2.GTPE2_CHANNEL.TST_RSV[4] origin:064-gtp-channel-conf 30_506 +GTP_CHANNEL_2.GTPE2_CHANNEL.TST_RSV[5] origin:064-gtp-channel-conf 31_506 +GTP_CHANNEL_2.GTPE2_CHANNEL.TST_RSV[6] origin:064-gtp-channel-conf 30_507 +GTP_CHANNEL_2.GTPE2_CHANNEL.TST_RSV[7] origin:064-gtp-channel-conf 31_507 +GTP_CHANNEL_2.GTPE2_CHANNEL.TST_RSV[8] origin:064-gtp-channel-conf 30_508 +GTP_CHANNEL_2.GTPE2_CHANNEL.TST_RSV[9] origin:064-gtp-channel-conf 31_508 +GTP_CHANNEL_2.GTPE2_CHANNEL.TST_RSV[10] origin:064-gtp-channel-conf 30_509 +GTP_CHANNEL_2.GTPE2_CHANNEL.TST_RSV[11] origin:064-gtp-channel-conf 31_509 +GTP_CHANNEL_2.GTPE2_CHANNEL.TST_RSV[12] origin:064-gtp-channel-conf 30_510 +GTP_CHANNEL_2.GTPE2_CHANNEL.TST_RSV[13] origin:064-gtp-channel-conf 31_510 +GTP_CHANNEL_2.GTPE2_CHANNEL.TST_RSV[14] origin:064-gtp-channel-conf 30_511 +GTP_CHANNEL_2.GTPE2_CHANNEL.TST_RSV[15] origin:064-gtp-channel-conf 31_511 +GTP_CHANNEL_2.GTPE2_CHANNEL.TST_RSV[16] origin:064-gtp-channel-conf 30_512 +GTP_CHANNEL_2.GTPE2_CHANNEL.TST_RSV[17] origin:064-gtp-channel-conf 31_512 +GTP_CHANNEL_2.GTPE2_CHANNEL.TST_RSV[18] origin:064-gtp-channel-conf 30_513 +GTP_CHANNEL_2.GTPE2_CHANNEL.TST_RSV[19] origin:064-gtp-channel-conf 31_513 +GTP_CHANNEL_2.GTPE2_CHANNEL.TST_RSV[20] origin:064-gtp-channel-conf 30_514 +GTP_CHANNEL_2.GTPE2_CHANNEL.TST_RSV[21] origin:064-gtp-channel-conf 31_514 +GTP_CHANNEL_2.GTPE2_CHANNEL.TST_RSV[22] origin:064-gtp-channel-conf 30_515 +GTP_CHANNEL_2.GTPE2_CHANNEL.TST_RSV[23] origin:064-gtp-channel-conf 31_515 +GTP_CHANNEL_2.GTPE2_CHANNEL.TST_RSV[24] origin:064-gtp-channel-conf 30_516 +GTP_CHANNEL_2.GTPE2_CHANNEL.TST_RSV[25] origin:064-gtp-channel-conf 31_516 +GTP_CHANNEL_2.GTPE2_CHANNEL.TST_RSV[26] origin:064-gtp-channel-conf 30_517 +GTP_CHANNEL_2.GTPE2_CHANNEL.TST_RSV[27] origin:064-gtp-channel-conf 31_517 +GTP_CHANNEL_2.GTPE2_CHANNEL.TST_RSV[28] origin:064-gtp-channel-conf 30_518 +GTP_CHANNEL_2.GTPE2_CHANNEL.TST_RSV[29] origin:064-gtp-channel-conf 31_518 +GTP_CHANNEL_2.GTPE2_CHANNEL.TST_RSV[30] origin:064-gtp-channel-conf 30_519 +GTP_CHANNEL_2.GTPE2_CHANNEL.TST_RSV[31] origin:064-gtp-channel-conf 31_519 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_CLKMUX_EN[0] origin:064-gtp-channel-conf 31_128 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_DATA_WIDTH[0] origin:064-gtp-channel-conf 30_152 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_DATA_WIDTH[1] origin:064-gtp-channel-conf 31_152 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_DATA_WIDTH[2] origin:064-gtp-channel-conf 30_153 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_DRIVE_MODE.PIPE origin:064-gtp-channel-conf 28_200 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_EIDLE_ASSERT_DELAY[0] origin:064-gtp-channel-conf 28_203 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_EIDLE_ASSERT_DELAY[1] origin:064-gtp-channel-conf 29_203 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_EIDLE_ASSERT_DELAY[2] origin:064-gtp-channel-conf 28_204 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_EIDLE_DEASSERT_DELAY[0] origin:064-gtp-channel-conf 29_204 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_EIDLE_DEASSERT_DELAY[1] origin:064-gtp-channel-conf 28_205 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_EIDLE_DEASSERT_DELAY[2] origin:064-gtp-channel-conf 29_205 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_LOOPBACK_DRIVE_HIZ origin:064-gtp-channel-conf 29_202 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_MAINCURSOR_SEL[0] origin:064-gtp-channel-conf 31_289 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_MARGIN_FULL_0[0] origin:064-gtp-channel-conf 30_232 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_MARGIN_FULL_0[1] origin:064-gtp-channel-conf 31_232 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_MARGIN_FULL_0[2] origin:064-gtp-channel-conf 30_233 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_MARGIN_FULL_0[3] origin:064-gtp-channel-conf 31_233 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_MARGIN_FULL_0[4] origin:064-gtp-channel-conf 30_234 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_MARGIN_FULL_0[5] origin:064-gtp-channel-conf 31_234 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_MARGIN_FULL_0[6] origin:064-gtp-channel-conf 30_235 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_MARGIN_FULL_1[0] origin:064-gtp-channel-conf 30_236 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_MARGIN_FULL_1[1] origin:064-gtp-channel-conf 31_236 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_MARGIN_FULL_1[2] origin:064-gtp-channel-conf 30_237 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_MARGIN_FULL_1[3] origin:064-gtp-channel-conf 31_237 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_MARGIN_FULL_1[4] origin:064-gtp-channel-conf 30_238 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_MARGIN_FULL_1[5] origin:064-gtp-channel-conf 31_238 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_MARGIN_FULL_1[6] origin:064-gtp-channel-conf 30_239 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_MARGIN_FULL_2[0] origin:064-gtp-channel-conf 30_240 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_MARGIN_FULL_2[1] origin:064-gtp-channel-conf 31_240 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_MARGIN_FULL_2[2] origin:064-gtp-channel-conf 30_241 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_MARGIN_FULL_2[3] origin:064-gtp-channel-conf 31_241 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_MARGIN_FULL_2[4] origin:064-gtp-channel-conf 30_242 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_MARGIN_FULL_2[5] origin:064-gtp-channel-conf 31_242 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_MARGIN_FULL_2[6] origin:064-gtp-channel-conf 30_243 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_MARGIN_FULL_3[0] origin:064-gtp-channel-conf 30_244 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_MARGIN_FULL_3[1] origin:064-gtp-channel-conf 31_244 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_MARGIN_FULL_3[2] origin:064-gtp-channel-conf 30_245 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_MARGIN_FULL_3[3] origin:064-gtp-channel-conf 31_245 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_MARGIN_FULL_3[4] origin:064-gtp-channel-conf 30_246 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_MARGIN_FULL_3[5] origin:064-gtp-channel-conf 31_246 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_MARGIN_FULL_3[6] origin:064-gtp-channel-conf 30_247 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_MARGIN_FULL_4[0] origin:064-gtp-channel-conf 30_248 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_MARGIN_FULL_4[1] origin:064-gtp-channel-conf 31_248 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_MARGIN_FULL_4[2] origin:064-gtp-channel-conf 30_249 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_MARGIN_FULL_4[3] origin:064-gtp-channel-conf 31_249 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_MARGIN_FULL_4[4] origin:064-gtp-channel-conf 30_250 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_MARGIN_FULL_4[5] origin:064-gtp-channel-conf 31_250 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_MARGIN_FULL_4[6] origin:064-gtp-channel-conf 30_251 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_MARGIN_LOW_0[0] origin:064-gtp-channel-conf 30_252 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_MARGIN_LOW_0[1] origin:064-gtp-channel-conf 31_252 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_MARGIN_LOW_0[2] origin:064-gtp-channel-conf 30_253 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_MARGIN_LOW_0[3] origin:064-gtp-channel-conf 31_253 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_MARGIN_LOW_0[4] origin:064-gtp-channel-conf 30_254 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_MARGIN_LOW_0[5] origin:064-gtp-channel-conf 31_254 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_MARGIN_LOW_0[6] origin:064-gtp-channel-conf 30_255 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_MARGIN_LOW_1[0] origin:064-gtp-channel-conf 30_256 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_MARGIN_LOW_1[1] origin:064-gtp-channel-conf 31_256 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_MARGIN_LOW_1[2] origin:064-gtp-channel-conf 30_257 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_MARGIN_LOW_1[3] origin:064-gtp-channel-conf 31_257 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_MARGIN_LOW_1[4] origin:064-gtp-channel-conf 30_258 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_MARGIN_LOW_1[5] origin:064-gtp-channel-conf 31_258 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_MARGIN_LOW_1[6] origin:064-gtp-channel-conf 30_259 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_MARGIN_LOW_2[0] origin:064-gtp-channel-conf 30_260 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_MARGIN_LOW_2[1] origin:064-gtp-channel-conf 31_260 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_MARGIN_LOW_2[2] origin:064-gtp-channel-conf 30_261 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_MARGIN_LOW_2[3] origin:064-gtp-channel-conf 31_261 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_MARGIN_LOW_2[4] origin:064-gtp-channel-conf 30_262 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_MARGIN_LOW_2[5] origin:064-gtp-channel-conf 31_262 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_MARGIN_LOW_2[6] origin:064-gtp-channel-conf 30_263 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_MARGIN_LOW_3[0] origin:064-gtp-channel-conf 30_264 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_MARGIN_LOW_3[1] origin:064-gtp-channel-conf 31_264 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_MARGIN_LOW_3[2] origin:064-gtp-channel-conf 30_265 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_MARGIN_LOW_3[3] origin:064-gtp-channel-conf 31_265 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_MARGIN_LOW_3[4] origin:064-gtp-channel-conf 30_266 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_MARGIN_LOW_3[5] origin:064-gtp-channel-conf 31_266 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_MARGIN_LOW_3[6] origin:064-gtp-channel-conf 30_267 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_MARGIN_LOW_4[0] origin:064-gtp-channel-conf 30_268 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_MARGIN_LOW_4[1] origin:064-gtp-channel-conf 31_268 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_MARGIN_LOW_4[2] origin:064-gtp-channel-conf 30_269 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_MARGIN_LOW_4[3] origin:064-gtp-channel-conf 31_269 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_MARGIN_LOW_4[4] origin:064-gtp-channel-conf 30_270 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_MARGIN_LOW_4[5] origin:064-gtp-channel-conf 31_270 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_MARGIN_LOW_4[6] origin:064-gtp-channel-conf 30_271 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_PREDRIVER_MODE[0] origin:064-gtp-channel-conf 28_206 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_RXDETECT_CFG[0] origin:064-gtp-channel-conf 30_296 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_RXDETECT_CFG[1] origin:064-gtp-channel-conf 31_296 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_RXDETECT_CFG[2] origin:064-gtp-channel-conf 30_297 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_RXDETECT_CFG[3] origin:064-gtp-channel-conf 31_297 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_RXDETECT_CFG[4] origin:064-gtp-channel-conf 30_298 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_RXDETECT_CFG[5] origin:064-gtp-channel-conf 31_298 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_RXDETECT_CFG[6] origin:064-gtp-channel-conf 30_299 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_RXDETECT_CFG[7] origin:064-gtp-channel-conf 31_299 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_RXDETECT_CFG[8] origin:064-gtp-channel-conf 30_300 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_RXDETECT_CFG[9] origin:064-gtp-channel-conf 31_300 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_RXDETECT_CFG[10] origin:064-gtp-channel-conf 30_301 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_RXDETECT_CFG[11] origin:064-gtp-channel-conf 31_301 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_RXDETECT_CFG[12] origin:064-gtp-channel-conf 30_302 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_RXDETECT_CFG[13] origin:064-gtp-channel-conf 31_302 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_RXDETECT_REF[0] origin:064-gtp-channel-conf 30_292 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_RXDETECT_REF[1] origin:064-gtp-channel-conf 31_292 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_RXDETECT_REF[2] origin:064-gtp-channel-conf 30_293 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_XCLK_SEL.TXUSR origin:064-gtp-channel-conf 31_11 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_CLK25_DIV[0] origin:064-gtp-channel-conf 30_144 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_CLK25_DIV[1] origin:064-gtp-channel-conf 31_144 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_CLK25_DIV[2] origin:064-gtp-channel-conf 30_145 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_CLK25_DIV[3] origin:064-gtp-channel-conf 31_145 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_CLK25_DIV[4] origin:064-gtp-channel-conf 30_146 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_DEEMPH0[0] origin:064-gtp-channel-conf 30_272 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_DEEMPH0[1] origin:064-gtp-channel-conf 31_272 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_DEEMPH0[2] origin:064-gtp-channel-conf 30_273 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_DEEMPH0[3] origin:064-gtp-channel-conf 31_273 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_DEEMPH0[4] origin:064-gtp-channel-conf 30_274 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_DEEMPH0[5] origin:064-gtp-channel-conf 31_274 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_DEEMPH1[0] origin:064-gtp-channel-conf 30_276 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_DEEMPH1[1] origin:064-gtp-channel-conf 31_276 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_DEEMPH1[2] origin:064-gtp-channel-conf 30_277 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_DEEMPH1[3] origin:064-gtp-channel-conf 31_277 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_DEEMPH1[4] origin:064-gtp-channel-conf 30_278 +GTP_CHANNEL_2.GTPE2_CHANNEL.TX_DEEMPH1[5] origin:064-gtp-channel-conf 31_278 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXBUF_EN origin:064-gtp-channel-conf 28_231 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXBUF_RESET_ON_RATE_CHANGE origin:064-gtp-channel-conf 29_231 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXDLY_CFG[0] origin:064-gtp-channel-conf 30_80 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXDLY_CFG[1] origin:064-gtp-channel-conf 31_80 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXDLY_CFG[2] origin:064-gtp-channel-conf 30_81 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXDLY_CFG[3] origin:064-gtp-channel-conf 31_81 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXDLY_CFG[4] origin:064-gtp-channel-conf 30_82 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXDLY_CFG[5] origin:064-gtp-channel-conf 31_82 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXDLY_CFG[6] origin:064-gtp-channel-conf 30_83 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXDLY_CFG[7] origin:064-gtp-channel-conf 31_83 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXDLY_CFG[8] origin:064-gtp-channel-conf 30_84 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXDLY_CFG[9] origin:064-gtp-channel-conf 31_84 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXDLY_CFG[10] origin:064-gtp-channel-conf 30_85 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXDLY_CFG[11] origin:064-gtp-channel-conf 31_85 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXDLY_CFG[12] origin:064-gtp-channel-conf 30_86 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXDLY_CFG[13] origin:064-gtp-channel-conf 31_86 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXDLY_CFG[14] origin:064-gtp-channel-conf 30_87 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXDLY_CFG[15] origin:064-gtp-channel-conf 31_87 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXDLY_LCFG[0] origin:064-gtp-channel-conf 30_568 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXDLY_LCFG[1] origin:064-gtp-channel-conf 31_568 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXDLY_LCFG[2] origin:064-gtp-channel-conf 30_569 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXDLY_LCFG[3] origin:064-gtp-channel-conf 31_569 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXDLY_LCFG[4] origin:064-gtp-channel-conf 30_570 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXDLY_LCFG[5] origin:064-gtp-channel-conf 31_570 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXDLY_LCFG[6] origin:064-gtp-channel-conf 30_571 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXDLY_LCFG[7] origin:064-gtp-channel-conf 31_571 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXDLY_LCFG[8] origin:064-gtp-channel-conf 30_572 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXDLY_TAP_CFG[0] origin:064-gtp-channel-conf 30_88 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXDLY_TAP_CFG[1] origin:064-gtp-channel-conf 31_88 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXDLY_TAP_CFG[2] origin:064-gtp-channel-conf 30_89 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXDLY_TAP_CFG[3] origin:064-gtp-channel-conf 31_89 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXDLY_TAP_CFG[4] origin:064-gtp-channel-conf 30_90 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXDLY_TAP_CFG[5] origin:064-gtp-channel-conf 31_90 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXDLY_TAP_CFG[6] origin:064-gtp-channel-conf 30_91 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXDLY_TAP_CFG[7] origin:064-gtp-channel-conf 31_91 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXDLY_TAP_CFG[8] origin:064-gtp-channel-conf 30_92 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXDLY_TAP_CFG[9] origin:064-gtp-channel-conf 31_92 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXDLY_TAP_CFG[10] origin:064-gtp-channel-conf 30_93 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXDLY_TAP_CFG[11] origin:064-gtp-channel-conf 31_93 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXDLY_TAP_CFG[12] origin:064-gtp-channel-conf 30_94 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXDLY_TAP_CFG[13] origin:064-gtp-channel-conf 31_94 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXDLY_TAP_CFG[14] origin:064-gtp-channel-conf 30_95 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXDLY_TAP_CFG[15] origin:064-gtp-channel-conf 31_95 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXGEARBOX_EN origin:064-gtp-channel-conf 29_226 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXOOB_CFG[0] origin:064-gtp-channel-conf 31_20 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXOUT_DIV[0] origin:064-gtp-channel-conf 30_386 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXOUT_DIV[1] origin:064-gtp-channel-conf 31_386 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPCSRESET_TIME[0] origin:064-gtp-channel-conf 29_130 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPCSRESET_TIME[1] origin:064-gtp-channel-conf 28_131 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPCSRESET_TIME[2] origin:064-gtp-channel-conf 29_131 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPCSRESET_TIME[3] origin:064-gtp-channel-conf 28_132 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPCSRESET_TIME[4] origin:064-gtp-channel-conf 29_132 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPH_CFG[0] origin:064-gtp-channel-conf 30_96 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPH_CFG[1] origin:064-gtp-channel-conf 31_96 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPH_CFG[2] origin:064-gtp-channel-conf 30_97 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPH_CFG[3] origin:064-gtp-channel-conf 31_97 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPH_CFG[4] origin:064-gtp-channel-conf 30_98 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPH_CFG[5] origin:064-gtp-channel-conf 31_98 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPH_CFG[6] origin:064-gtp-channel-conf 30_99 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPH_CFG[7] origin:064-gtp-channel-conf 31_99 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPH_CFG[8] origin:064-gtp-channel-conf 30_100 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPH_CFG[9] origin:064-gtp-channel-conf 31_100 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPH_CFG[10] origin:064-gtp-channel-conf 30_101 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPH_CFG[11] origin:064-gtp-channel-conf 31_101 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPH_CFG[12] origin:064-gtp-channel-conf 30_102 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPH_CFG[13] origin:064-gtp-channel-conf 31_102 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPH_CFG[14] origin:064-gtp-channel-conf 30_103 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPH_CFG[15] origin:064-gtp-channel-conf 31_103 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPH_MONITOR_SEL[0] origin:064-gtp-channel-conf 30_108 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPH_MONITOR_SEL[1] origin:064-gtp-channel-conf 31_108 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPH_MONITOR_SEL[2] origin:064-gtp-channel-conf 30_109 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPH_MONITOR_SEL[3] origin:064-gtp-channel-conf 31_109 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPH_MONITOR_SEL[4] origin:064-gtp-channel-conf 30_110 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPHDLY_CFG[0] origin:064-gtp-channel-conf 30_64 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPHDLY_CFG[1] origin:064-gtp-channel-conf 31_64 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPHDLY_CFG[2] origin:064-gtp-channel-conf 30_65 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPHDLY_CFG[3] origin:064-gtp-channel-conf 31_65 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPHDLY_CFG[4] origin:064-gtp-channel-conf 30_66 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPHDLY_CFG[5] origin:064-gtp-channel-conf 31_66 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPHDLY_CFG[6] origin:064-gtp-channel-conf 30_67 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPHDLY_CFG[7] origin:064-gtp-channel-conf 31_67 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPHDLY_CFG[8] origin:064-gtp-channel-conf 30_68 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPHDLY_CFG[9] origin:064-gtp-channel-conf 31_68 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPHDLY_CFG[10] origin:064-gtp-channel-conf 30_69 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPHDLY_CFG[11] origin:064-gtp-channel-conf 31_69 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPHDLY_CFG[12] origin:064-gtp-channel-conf 30_70 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPHDLY_CFG[13] origin:064-gtp-channel-conf 31_70 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPHDLY_CFG[14] origin:064-gtp-channel-conf 30_71 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPHDLY_CFG[15] origin:064-gtp-channel-conf 31_71 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPHDLY_CFG[16] origin:064-gtp-channel-conf 30_72 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPHDLY_CFG[17] origin:064-gtp-channel-conf 31_72 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPHDLY_CFG[18] origin:064-gtp-channel-conf 30_73 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPHDLY_CFG[19] origin:064-gtp-channel-conf 31_73 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPHDLY_CFG[20] origin:064-gtp-channel-conf 30_74 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPHDLY_CFG[21] origin:064-gtp-channel-conf 31_74 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPHDLY_CFG[22] origin:064-gtp-channel-conf 30_75 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPHDLY_CFG[23] origin:064-gtp-channel-conf 31_75 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPI_GREY_SEL[0] origin:064-gtp-channel-conf 31_498 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPI_INVSTROBE_SEL[0] origin:064-gtp-channel-conf 30_498 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPI_PPM_CFG[0] origin:064-gtp-channel-conf 30_488 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPI_PPM_CFG[1] origin:064-gtp-channel-conf 31_488 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPI_PPM_CFG[2] origin:064-gtp-channel-conf 30_489 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPI_PPM_CFG[3] origin:064-gtp-channel-conf 31_489 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPI_PPM_CFG[4] origin:064-gtp-channel-conf 30_490 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPI_PPM_CFG[5] origin:064-gtp-channel-conf 31_490 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPI_PPM_CFG[6] origin:064-gtp-channel-conf 30_491 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPI_PPM_CFG[7] origin:064-gtp-channel-conf 31_491 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPI_PPMCLK_SEL.TXUSRCLK2 origin:064-gtp-channel-conf 31_497 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPI_SYNFREQ_PPM[0] origin:064-gtp-channel-conf 30_496 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPI_SYNFREQ_PPM[1] origin:064-gtp-channel-conf 31_496 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPI_SYNFREQ_PPM[2] origin:064-gtp-channel-conf 30_497 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPI_CFG0[0] origin:064-gtp-channel-conf 30_40 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPI_CFG0[1] origin:064-gtp-channel-conf 31_40 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPI_CFG1[0] origin:064-gtp-channel-conf 30_41 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPI_CFG1[1] origin:064-gtp-channel-conf 31_41 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPI_CFG2[0] origin:064-gtp-channel-conf 30_42 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPI_CFG2[1] origin:064-gtp-channel-conf 31_42 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPI_CFG3[0] origin:064-gtp-channel-conf 30_43 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPI_CFG4[0] origin:064-gtp-channel-conf 31_43 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPI_CFG5[0] origin:064-gtp-channel-conf 30_44 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPI_CFG5[1] origin:064-gtp-channel-conf 31_44 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPI_CFG5[2] origin:064-gtp-channel-conf 30_45 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPMARESET_TIME[0] origin:064-gtp-channel-conf 28_128 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPMARESET_TIME[1] origin:064-gtp-channel-conf 29_128 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPMARESET_TIME[2] origin:064-gtp-channel-conf 28_129 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPMARESET_TIME[3] origin:064-gtp-channel-conf 29_129 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXPMARESET_TIME[4] origin:064-gtp-channel-conf 28_130 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXSYNC_MULTILANE[0] origin:064-gtp-channel-conf 29_133 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXSYNC_OVRD[0] origin:064-gtp-channel-conf 28_135 +GTP_CHANNEL_2.GTPE2_CHANNEL.TXSYNC_SKIP_DA[0] origin:064-gtp-channel-conf 28_134 +GTP_CHANNEL_2.GTPE2_CHANNEL.UCODEER_CLR[0] origin:064-gtp-channel-conf 29_00 +GTP_CHANNEL_2.GTPE2_CHANNEL.USE_PCS_CLK_PHASE_SEL[0] origin:064-gtp-channel-conf 30_463 diff --git a/artix7/segbits_gtp_channel_2_mid_left.db b/artix7/segbits_gtp_channel_2_mid_left.db index d41f891..1def539 100644 --- a/artix7/segbits_gtp_channel_2_mid_left.db +++ b/artix7/segbits_gtp_channel_2_mid_left.db @@ -1,1627 +1,1627 @@ -GTP_CHANNEL_2_MID_LEFT.GTPE2.ACJTAG_DEBUG_MODE[0] 00_07 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ACJTAG_MODE[0] 01_06 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ACJTAG_RESET[0] 01_07 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ADAPT_CFG0[0] 02_464 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ADAPT_CFG0[1] 03_464 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ADAPT_CFG0[2] 02_465 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ADAPT_CFG0[3] 03_465 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ADAPT_CFG0[4] 02_466 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ADAPT_CFG0[5] 03_466 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ADAPT_CFG0[6] 02_467 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ADAPT_CFG0[7] 03_467 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ADAPT_CFG0[8] 02_468 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ADAPT_CFG0[9] 03_468 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ADAPT_CFG0[10] 02_469 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ADAPT_CFG0[11] 03_469 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ADAPT_CFG0[12] 02_470 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ADAPT_CFG0[13] 03_470 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ADAPT_CFG0[14] 02_471 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ADAPT_CFG0[15] 03_471 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ADAPT_CFG0[16] 02_472 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ADAPT_CFG0[17] 03_472 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ADAPT_CFG0[18] 02_473 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ADAPT_CFG0[19] 03_473 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ALIGN_COMMA_DOUBLE 00_522 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ALIGN_COMMA_ENABLE[0] 00_496 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ALIGN_COMMA_ENABLE[1] 01_496 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ALIGN_COMMA_ENABLE[2] 00_497 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ALIGN_COMMA_ENABLE[3] 01_497 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ALIGN_COMMA_ENABLE[4] 00_498 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ALIGN_COMMA_ENABLE[5] 01_498 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ALIGN_COMMA_ENABLE[6] 00_499 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ALIGN_COMMA_ENABLE[7] 01_499 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ALIGN_COMMA_ENABLE[8] 00_500 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ALIGN_COMMA_ENABLE[9] 01_500 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ALIGN_COMMA_WORD[0] 01_526 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ALIGN_COMMA_WORD[1] 00_527 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ALIGN_MCOMMA_DET 00_523 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ALIGN_MCOMMA_VALUE[0] 00_504 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ALIGN_MCOMMA_VALUE[1] 01_504 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ALIGN_MCOMMA_VALUE[2] 00_505 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ALIGN_MCOMMA_VALUE[3] 01_505 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ALIGN_MCOMMA_VALUE[4] 00_506 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ALIGN_MCOMMA_VALUE[5] 01_506 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ALIGN_MCOMMA_VALUE[6] 00_507 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ALIGN_MCOMMA_VALUE[7] 01_507 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ALIGN_MCOMMA_VALUE[8] 00_508 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ALIGN_MCOMMA_VALUE[9] 01_508 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ALIGN_PCOMMA_DET 01_523 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ALIGN_PCOMMA_VALUE[0] 00_512 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ALIGN_PCOMMA_VALUE[1] 01_512 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ALIGN_PCOMMA_VALUE[2] 00_513 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ALIGN_PCOMMA_VALUE[3] 01_513 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ALIGN_PCOMMA_VALUE[4] 00_514 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ALIGN_PCOMMA_VALUE[5] 01_514 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ALIGN_PCOMMA_VALUE[6] 00_515 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ALIGN_PCOMMA_VALUE[7] 01_515 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ALIGN_PCOMMA_VALUE[8] 00_516 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ALIGN_PCOMMA_VALUE[9] 01_516 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CBCC_DATA_SOURCE_SEL.DECODED 01_661 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CFOK_CFG[0] 02_392 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CFOK_CFG[1] 03_392 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CFOK_CFG[2] 02_393 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CFOK_CFG[3] 03_393 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CFOK_CFG[4] 02_394 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CFOK_CFG[5] 03_394 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CFOK_CFG[6] 02_395 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CFOK_CFG[7] 03_395 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CFOK_CFG[8] 02_396 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CFOK_CFG[9] 03_396 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CFOK_CFG[10] 02_397 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CFOK_CFG[11] 03_397 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CFOK_CFG[12] 02_398 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CFOK_CFG[13] 03_398 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CFOK_CFG[14] 02_399 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CFOK_CFG[15] 03_399 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CFOK_CFG[16] 02_400 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CFOK_CFG[17] 03_400 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CFOK_CFG[18] 02_401 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CFOK_CFG[19] 03_401 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CFOK_CFG[20] 02_402 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CFOK_CFG[21] 03_402 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CFOK_CFG[22] 02_403 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CFOK_CFG[23] 03_403 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CFOK_CFG[24] 02_404 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CFOK_CFG[25] 03_404 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CFOK_CFG[26] 02_405 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CFOK_CFG[27] 03_405 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CFOK_CFG[28] 02_406 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CFOK_CFG[29] 03_406 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CFOK_CFG[30] 02_407 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CFOK_CFG[31] 03_407 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CFOK_CFG[32] 02_408 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CFOK_CFG[33] 03_408 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CFOK_CFG[34] 02_409 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CFOK_CFG[35] 03_409 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CFOK_CFG[36] 02_410 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CFOK_CFG[37] 03_410 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CFOK_CFG[38] 02_411 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CFOK_CFG[39] 03_411 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CFOK_CFG[40] 02_412 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CFOK_CFG[41] 03_412 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CFOK_CFG[42] 02_413 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CFOK_CFG2[0] 02_459 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CFOK_CFG2[1] 03_459 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CFOK_CFG2[2] 02_460 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CFOK_CFG2[3] 03_460 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CFOK_CFG2[4] 02_461 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CFOK_CFG2[5] 03_461 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CFOK_CFG2[6] 02_462 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CFOK_CFG3[0] 02_416 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CFOK_CFG3[1] 03_416 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CFOK_CFG3[2] 02_417 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CFOK_CFG3[3] 03_417 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CFOK_CFG3[4] 02_418 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CFOK_CFG3[5] 03_418 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CFOK_CFG3[6] 02_419 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CFOK_CFG4[0] 03_438 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CFOK_CFG5[0] 02_429 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CFOK_CFG5[1] 03_429 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CFOK_CFG6[0] 03_436 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CFOK_CFG6[1] 02_437 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CFOK_CFG6[2] 03_437 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CFOK_CFG6[3] 02_438 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_KEEP_ALIGN 01_631 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_MAX_SKEW[0] 00_670 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_MAX_SKEW[1] 01_670 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_MAX_SKEW[2] 00_671 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_MAX_SKEW[3] 01_671 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_1[0] 00_608 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_1[1] 01_608 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_1[2] 00_609 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_1[3] 01_609 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_1[4] 00_610 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_1[5] 01_610 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_1[6] 00_611 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_1[7] 01_611 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_1[8] 00_612 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_1[9] 01_612 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_2[0] 00_616 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_2[1] 01_616 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_2[2] 00_617 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_2[3] 01_617 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_2[4] 00_618 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_2[5] 01_618 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_2[6] 00_619 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_2[7] 01_619 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_2[8] 00_620 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_2[9] 01_620 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_3[0] 00_624 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_3[1] 01_624 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_3[2] 00_625 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_3[3] 01_625 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_3[4] 00_626 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_3[5] 01_626 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_3[6] 00_627 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_3[7] 01_627 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_3[8] 00_628 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_3[9] 01_628 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_4[0] 00_632 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_4[1] 01_632 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_4[2] 00_633 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_4[3] 01_633 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_4[4] 00_634 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_4[5] 01_634 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_4[6] 00_635 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_4[7] 01_635 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_4[8] 00_636 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_4[9] 01_636 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_ENABLE[0] 00_614 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_ENABLE[1] 01_614 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_ENABLE[2] 00_615 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_ENABLE[3] 01_615 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_1[0] 00_640 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_1[1] 01_640 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_1[2] 00_641 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_1[3] 01_641 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_1[4] 00_642 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_1[5] 01_642 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_1[6] 00_643 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_1[7] 01_643 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_1[8] 00_644 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_1[9] 01_644 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_2[0] 00_648 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_2[1] 01_648 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_2[2] 00_649 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_2[3] 01_649 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_2[4] 00_650 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_2[5] 01_650 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_2[6] 00_651 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_2[7] 01_651 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_2[8] 00_652 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_2[9] 01_652 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_3[0] 00_656 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_3[1] 01_656 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_3[2] 00_657 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_3[3] 01_657 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_3[4] 00_658 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_3[5] 01_658 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_3[6] 00_659 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_3[7] 01_659 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_3[8] 00_660 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_3[9] 01_660 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_4[0] 00_664 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_4[1] 01_664 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_4[2] 00_665 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_4[3] 01_665 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_4[4] 00_666 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_4[5] 01_666 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_4[6] 00_667 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_4[7] 01_667 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_4[8] 00_668 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_4[9] 01_668 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_ENABLE[0] 00_646 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_ENABLE[1] 01_646 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_ENABLE[2] 00_647 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_ENABLE[3] 01_647 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_USE 01_645 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_LEN[0] 00_623 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_LEN[1] 01_623 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COMMON_SWING[0] 03_311 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_KEEP_IDLE 00_591 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_MAX_LAT[0] 00_557 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_MAX_LAT[1] 01_557 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_MAX_LAT[2] 00_558 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_MAX_LAT[3] 01_558 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_MAX_LAT[4] 00_559 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_MAX_LAT[5] 01_559 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_MIN_LAT[0] 00_565 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_MIN_LAT[1] 01_565 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_MIN_LAT[2] 00_566 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_MIN_LAT[3] 01_566 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_MIN_LAT[4] 00_567 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_MIN_LAT[5] 01_567 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_PRECEDENCE 00_590 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_REPEAT_WAIT[0] 00_573 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_REPEAT_WAIT[1] 01_573 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_REPEAT_WAIT[2] 00_574 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_REPEAT_WAIT[3] 01_574 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_REPEAT_WAIT[4] 00_575 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_1_1[0] 00_544 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_1_1[1] 01_544 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_1_1[2] 00_545 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_1_1[3] 01_545 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_1_1[4] 00_546 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_1_1[5] 01_546 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_1_1[6] 00_547 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_1_1[7] 01_547 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_1_1[8] 00_548 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_1_1[9] 01_548 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_1_2[0] 00_552 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_1_2[1] 01_552 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_1_2[2] 00_553 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_1_2[3] 01_553 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_1_2[4] 00_554 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_1_2[5] 01_554 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_1_2[6] 00_555 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_1_2[7] 01_555 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_1_2[8] 00_556 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_1_2[9] 01_556 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_1_3[0] 00_560 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_1_3[1] 01_560 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_1_3[2] 00_561 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_1_3[3] 01_561 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_1_3[4] 00_562 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_1_3[5] 01_562 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_1_3[6] 00_563 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_1_3[7] 01_563 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_1_3[8] 00_564 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_1_3[9] 01_564 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_1_4[0] 00_568 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_1_4[1] 01_568 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_1_4[2] 00_569 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_1_4[3] 01_569 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_1_4[4] 00_570 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_1_4[5] 01_570 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_1_4[6] 00_571 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_1_4[7] 01_571 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_1_4[8] 00_572 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_1_4[9] 01_572 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_1_ENABLE[0] 00_549 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_1_ENABLE[1] 01_549 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_1_ENABLE[2] 00_550 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_1_ENABLE[3] 01_550 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_2_1[0] 00_576 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_2_1[1] 01_576 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_2_1[2] 00_577 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_2_1[3] 01_577 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_2_1[4] 00_578 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_2_1[5] 01_578 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_2_1[6] 00_579 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_2_1[7] 01_579 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_2_1[8] 00_580 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_2_1[9] 01_580 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_2_2[0] 00_584 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_2_2[1] 01_584 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_2_2[2] 00_585 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_2_2[3] 01_585 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_2_2[4] 00_586 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_2_2[5] 01_586 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_2_2[6] 00_587 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_2_2[7] 01_587 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_2_2[8] 00_588 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_2_2[9] 01_588 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_2_3[0] 00_592 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_2_3[1] 01_592 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_2_3[2] 00_593 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_2_3[3] 01_593 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_2_3[4] 00_594 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_2_3[5] 01_594 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_2_3[6] 00_595 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_2_3[7] 01_595 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_2_3[8] 00_596 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_2_3[9] 01_596 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_2_4[0] 00_600 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_2_4[1] 01_600 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_2_4[2] 00_601 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_2_4[3] 01_601 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_2_4[4] 00_602 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_2_4[5] 01_602 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_2_4[6] 00_603 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_2_4[7] 01_603 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_2_4[8] 00_604 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_2_4[9] 01_604 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_2_ENABLE[0] 00_581 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_2_ENABLE[1] 01_581 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_2_ENABLE[2] 00_582 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_2_ENABLE[3] 01_582 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_2_USE 00_583 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_LEN[0] 00_589 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_LEN[1] 01_589 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_CORRECT_USE 00_551 -GTP_CHANNEL_2_MID_LEFT.GTPE2.DEC_MCOMMA_DETECT 01_494 -GTP_CHANNEL_2_MID_LEFT.GTPE2.DEC_PCOMMA_DETECT 00_495 -GTP_CHANNEL_2_MID_LEFT.GTPE2.DEC_VALID_COMMA_ONLY 00_494 -GTP_CHANNEL_2_MID_LEFT.GTPE2.DMONITOR_CFG[0] 02_368 -GTP_CHANNEL_2_MID_LEFT.GTPE2.DMONITOR_CFG[1] 03_368 -GTP_CHANNEL_2_MID_LEFT.GTPE2.DMONITOR_CFG[2] 02_369 -GTP_CHANNEL_2_MID_LEFT.GTPE2.DMONITOR_CFG[3] 03_369 -GTP_CHANNEL_2_MID_LEFT.GTPE2.DMONITOR_CFG[4] 02_370 -GTP_CHANNEL_2_MID_LEFT.GTPE2.DMONITOR_CFG[5] 03_370 -GTP_CHANNEL_2_MID_LEFT.GTPE2.DMONITOR_CFG[6] 02_371 -GTP_CHANNEL_2_MID_LEFT.GTPE2.DMONITOR_CFG[7] 03_371 -GTP_CHANNEL_2_MID_LEFT.GTPE2.DMONITOR_CFG[8] 02_372 -GTP_CHANNEL_2_MID_LEFT.GTPE2.DMONITOR_CFG[9] 03_372 -GTP_CHANNEL_2_MID_LEFT.GTPE2.DMONITOR_CFG[10] 02_373 -GTP_CHANNEL_2_MID_LEFT.GTPE2.DMONITOR_CFG[11] 03_373 -GTP_CHANNEL_2_MID_LEFT.GTPE2.DMONITOR_CFG[12] 02_374 -GTP_CHANNEL_2_MID_LEFT.GTPE2.DMONITOR_CFG[13] 03_374 -GTP_CHANNEL_2_MID_LEFT.GTPE2.DMONITOR_CFG[14] 02_375 -GTP_CHANNEL_2_MID_LEFT.GTPE2.DMONITOR_CFG[15] 03_375 -GTP_CHANNEL_2_MID_LEFT.GTPE2.DMONITOR_CFG[16] 02_376 -GTP_CHANNEL_2_MID_LEFT.GTPE2.DMONITOR_CFG[17] 03_376 -GTP_CHANNEL_2_MID_LEFT.GTPE2.DMONITOR_CFG[18] 02_377 -GTP_CHANNEL_2_MID_LEFT.GTPE2.DMONITOR_CFG[19] 03_377 -GTP_CHANNEL_2_MID_LEFT.GTPE2.DMONITOR_CFG[20] 02_378 -GTP_CHANNEL_2_MID_LEFT.GTPE2.DMONITOR_CFG[21] 03_378 -GTP_CHANNEL_2_MID_LEFT.GTPE2.DMONITOR_CFG[22] 02_379 -GTP_CHANNEL_2_MID_LEFT.GTPE2.DMONITOR_CFG[23] 03_379 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_CLK_PHASE_SEL[0] 03_463 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_CONTROL[0] 00_488 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_CONTROL[1] 01_488 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_CONTROL[2] 00_489 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_CONTROL[3] 01_489 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_CONTROL[4] 00_490 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_CONTROL[5] 01_490 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_ERRDET_EN 01_492 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_EYE_SCAN_EN 00_492 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_HORZ_OFFSET[0] 00_480 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_HORZ_OFFSET[1] 01_480 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_HORZ_OFFSET[2] 00_481 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_HORZ_OFFSET[3] 01_481 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_HORZ_OFFSET[4] 00_482 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_HORZ_OFFSET[5] 01_482 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_HORZ_OFFSET[6] 00_483 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_HORZ_OFFSET[7] 01_483 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_HORZ_OFFSET[8] 00_484 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_HORZ_OFFSET[9] 01_484 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_HORZ_OFFSET[10] 00_485 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_HORZ_OFFSET[11] 01_485 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_PMA_CFG[0] 02_624 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_PMA_CFG[1] 03_624 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_PMA_CFG[2] 02_625 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_PMA_CFG[3] 03_625 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_PMA_CFG[4] 02_626 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_PMA_CFG[5] 03_626 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_PMA_CFG[6] 02_627 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_PMA_CFG[7] 03_627 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_PMA_CFG[8] 02_628 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_PMA_CFG[9] 03_628 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_PRESCALE[0] 01_477 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_PRESCALE[1] 00_478 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_PRESCALE[2] 01_478 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_PRESCALE[3] 00_479 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_PRESCALE[4] 01_479 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[0] 00_392 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[1] 01_392 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[2] 00_393 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[3] 01_393 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[4] 00_394 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[5] 01_394 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[6] 00_395 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[7] 01_395 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[8] 00_396 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[9] 01_396 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[10] 00_397 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[11] 01_397 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[12] 00_398 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[13] 01_398 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[14] 00_399 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[15] 01_399 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[16] 00_400 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[17] 01_400 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[18] 00_401 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[19] 01_401 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[20] 00_402 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[21] 01_402 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[22] 00_403 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[23] 01_403 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[24] 00_404 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[25] 01_404 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[26] 00_405 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[27] 01_405 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[28] 00_406 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[29] 01_406 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[30] 00_407 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[31] 01_407 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[32] 00_408 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[33] 01_408 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[34] 00_409 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[35] 01_409 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[36] 00_410 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[37] 01_410 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[38] 00_411 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[39] 01_411 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[40] 00_412 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[41] 01_412 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[42] 00_413 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[43] 01_413 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[44] 00_414 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[45] 01_414 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[46] 00_415 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[47] 01_415 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[48] 00_416 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[49] 01_416 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[50] 00_417 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[51] 01_417 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[52] 00_418 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[53] 01_418 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[54] 00_419 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[55] 01_419 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[56] 00_420 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[57] 01_420 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[58] 00_421 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[59] 01_421 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[60] 00_422 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[61] 01_422 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[62] 00_423 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[63] 01_423 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[64] 00_424 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[65] 01_424 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[66] 00_425 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[67] 01_425 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[68] 00_426 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[69] 01_426 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[70] 00_427 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[71] 01_427 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[72] 00_428 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[73] 01_428 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[74] 00_429 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[75] 01_429 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[76] 00_430 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[77] 01_430 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[78] 00_431 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[79] 01_431 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[0] 00_352 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[1] 01_352 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[2] 00_353 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[3] 01_353 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[4] 00_354 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[5] 01_354 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[6] 00_355 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[7] 01_355 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[8] 00_356 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[9] 01_356 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[10] 00_357 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[11] 01_357 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[12] 00_358 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[13] 01_358 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[14] 00_359 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[15] 01_359 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[16] 00_360 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[17] 01_360 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[18] 00_361 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[19] 01_361 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[20] 00_362 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[21] 01_362 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[22] 00_363 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[23] 01_363 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[24] 00_364 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[25] 01_364 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[26] 00_365 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[27] 01_365 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[28] 00_366 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[29] 01_366 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[30] 00_367 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[31] 01_367 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[32] 00_368 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[33] 01_368 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[34] 00_369 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[35] 01_369 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[36] 00_370 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[37] 01_370 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[38] 00_371 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[39] 01_371 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[40] 00_372 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[41] 01_372 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[42] 00_373 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[43] 01_373 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[44] 00_374 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[45] 01_374 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[46] 00_375 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[47] 01_375 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[48] 00_376 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[49] 01_376 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[50] 00_377 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[51] 01_377 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[52] 00_378 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[53] 01_378 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[54] 00_379 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[55] 01_379 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[56] 00_380 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[57] 01_380 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[58] 00_381 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[59] 01_381 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[60] 00_382 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[61] 01_382 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[62] 00_383 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[63] 01_383 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[64] 00_384 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[65] 01_384 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[66] 00_385 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[67] 01_385 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[68] 00_386 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[69] 01_386 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[70] 00_387 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[71] 01_387 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[72] 00_388 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[73] 01_388 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[74] 00_389 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[75] 01_389 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[76] 00_390 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[77] 01_390 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[78] 00_391 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[79] 01_391 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[0] 00_432 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[1] 01_432 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[2] 00_433 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[3] 01_433 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[4] 00_434 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[5] 01_434 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[6] 00_435 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[7] 01_435 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[8] 00_436 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[9] 01_436 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[10] 00_437 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[11] 01_437 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[12] 00_438 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[13] 01_438 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[14] 00_439 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[15] 01_439 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[16] 00_440 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[17] 01_440 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[18] 00_441 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[19] 01_441 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[20] 00_442 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[21] 01_442 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[22] 00_443 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[23] 01_443 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[24] 00_444 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[25] 01_444 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[26] 00_445 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[27] 01_445 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[28] 00_446 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[29] 01_446 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[30] 00_447 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[31] 01_447 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[32] 00_448 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[33] 01_448 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[34] 00_449 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[35] 01_449 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[36] 00_450 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[37] 01_450 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[38] 00_451 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[39] 01_451 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[40] 00_452 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[41] 01_452 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[42] 00_453 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[43] 01_453 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[44] 00_454 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[45] 01_454 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[46] 00_455 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[47] 01_455 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[48] 00_456 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[49] 01_456 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[50] 00_457 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[51] 01_457 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[52] 00_458 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[53] 01_458 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[54] 00_459 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[55] 01_459 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[56] 00_460 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[57] 01_460 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[58] 00_461 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[59] 01_461 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[60] 00_462 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[61] 01_462 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[62] 00_463 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[63] 01_463 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[64] 00_464 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[65] 01_464 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[66] 00_465 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[67] 01_465 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[68] 00_466 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[69] 01_466 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[70] 00_467 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[71] 01_467 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[72] 00_468 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[73] 01_468 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[74] 00_469 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[75] 01_469 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[76] 00_470 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[77] 01_470 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[78] 00_471 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[79] 01_471 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_VERT_OFFSET[0] 00_472 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_VERT_OFFSET[1] 01_472 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_VERT_OFFSET[2] 00_473 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_VERT_OFFSET[3] 01_473 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_VERT_OFFSET[4] 00_474 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_VERT_OFFSET[5] 01_474 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_VERT_OFFSET[6] 00_475 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_VERT_OFFSET[7] 01_475 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_VERT_OFFSET[8] 00_476 -GTP_CHANNEL_2_MID_LEFT.GTPE2.FTS_DESKEW_SEQ_ENABLE[0] 00_662 -GTP_CHANNEL_2_MID_LEFT.GTPE2.FTS_DESKEW_SEQ_ENABLE[1] 01_662 -GTP_CHANNEL_2_MID_LEFT.GTPE2.FTS_DESKEW_SEQ_ENABLE[2] 00_663 -GTP_CHANNEL_2_MID_LEFT.GTPE2.FTS_DESKEW_SEQ_ENABLE[3] 01_663 -GTP_CHANNEL_2_MID_LEFT.GTPE2.FTS_LANE_DESKEW_CFG[0] 00_654 -GTP_CHANNEL_2_MID_LEFT.GTPE2.FTS_LANE_DESKEW_CFG[1] 01_654 -GTP_CHANNEL_2_MID_LEFT.GTPE2.FTS_LANE_DESKEW_CFG[2] 00_655 -GTP_CHANNEL_2_MID_LEFT.GTPE2.FTS_LANE_DESKEW_CFG[3] 01_655 -GTP_CHANNEL_2_MID_LEFT.GTPE2.FTS_LANE_DESKEW_EN 01_653 -GTP_CHANNEL_2_MID_LEFT.GTPE2.GEARBOX_MODE[0] 00_224 -GTP_CHANNEL_2_MID_LEFT.GTPE2.GEARBOX_MODE[1] 01_224 -GTP_CHANNEL_2_MID_LEFT.GTPE2.GEARBOX_MODE[2] 00_225 -GTP_CHANNEL_2_MID_LEFT.GTPE2.IN_USE 00_00 00_01 00_47 00_52 00_53 00_65 01_01 01_47 02_129 -GTP_CHANNEL_2_MID_LEFT.GTPE2.LOOPBACK_CFG[0] 02_20 -GTP_CHANNEL_2_MID_LEFT.GTPE2.OUTREFCLK_SEL_INV[0] 00_149 -GTP_CHANNEL_2_MID_LEFT.GTPE2.OUTREFCLK_SEL_INV[1] 01_149 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PCS_PCIE_EN 00_216 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PCS_RSVD_ATTR[0] 02_184 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PCS_RSVD_ATTR[1] 03_184 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PCS_RSVD_ATTR[2] 02_185 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PCS_RSVD_ATTR[3] 03_185 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PCS_RSVD_ATTR[4] 02_186 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PCS_RSVD_ATTR[5] 03_186 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PCS_RSVD_ATTR[6] 02_187 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PCS_RSVD_ATTR[7] 03_187 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PCS_RSVD_ATTR[8] 02_188 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PCS_RSVD_ATTR[9] 03_188 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PCS_RSVD_ATTR[10] 02_189 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PCS_RSVD_ATTR[11] 03_189 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PCS_RSVD_ATTR[12] 02_190 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PCS_RSVD_ATTR[13] 03_190 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PCS_RSVD_ATTR[14] 02_191 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PCS_RSVD_ATTR[15] 03_191 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PCS_RSVD_ATTR[16] 02_192 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PCS_RSVD_ATTR[17] 03_192 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PCS_RSVD_ATTR[18] 02_193 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PCS_RSVD_ATTR[19] 03_193 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PCS_RSVD_ATTR[20] 02_194 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PCS_RSVD_ATTR[21] 03_194 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PCS_RSVD_ATTR[22] 02_195 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PCS_RSVD_ATTR[23] 03_195 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PCS_RSVD_ATTR[24] 02_196 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PCS_RSVD_ATTR[25] 03_196 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PCS_RSVD_ATTR[26] 02_197 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PCS_RSVD_ATTR[27] 03_197 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PCS_RSVD_ATTR[28] 02_198 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PCS_RSVD_ATTR[29] 03_198 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PCS_RSVD_ATTR[30] 02_199 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PCS_RSVD_ATTR[31] 03_199 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PCS_RSVD_ATTR[32] 02_200 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PCS_RSVD_ATTR[33] 03_200 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PCS_RSVD_ATTR[34] 02_201 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PCS_RSVD_ATTR[35] 03_201 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PCS_RSVD_ATTR[36] 02_202 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PCS_RSVD_ATTR[37] 03_202 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PCS_RSVD_ATTR[38] 02_203 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PCS_RSVD_ATTR[39] 03_203 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PCS_RSVD_ATTR[40] 02_204 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PCS_RSVD_ATTR[41] 03_204 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PCS_RSVD_ATTR[42] 02_205 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PCS_RSVD_ATTR[43] 03_205 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PCS_RSVD_ATTR[44] 02_206 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PCS_RSVD_ATTR[45] 03_206 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PCS_RSVD_ATTR[46] 02_207 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PCS_RSVD_ATTR[47] 03_207 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PD_TRANS_TIME_FROM_P2[0] 01_216 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PD_TRANS_TIME_FROM_P2[1] 00_217 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PD_TRANS_TIME_FROM_P2[2] 01_217 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PD_TRANS_TIME_FROM_P2[3] 00_218 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PD_TRANS_TIME_FROM_P2[4] 01_218 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PD_TRANS_TIME_FROM_P2[5] 00_219 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PD_TRANS_TIME_FROM_P2[6] 01_219 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PD_TRANS_TIME_FROM_P2[7] 00_220 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PD_TRANS_TIME_FROM_P2[8] 01_220 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PD_TRANS_TIME_FROM_P2[9] 00_221 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PD_TRANS_TIME_FROM_P2[10] 01_221 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PD_TRANS_TIME_FROM_P2[11] 00_222 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PD_TRANS_TIME_NONE_P2[0] 00_208 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PD_TRANS_TIME_NONE_P2[1] 01_208 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PD_TRANS_TIME_NONE_P2[2] 00_209 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PD_TRANS_TIME_NONE_P2[3] 01_209 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PD_TRANS_TIME_NONE_P2[4] 00_210 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PD_TRANS_TIME_NONE_P2[5] 01_210 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PD_TRANS_TIME_NONE_P2[6] 00_211 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PD_TRANS_TIME_NONE_P2[7] 01_211 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PD_TRANS_TIME_TO_P2[0] 00_212 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PD_TRANS_TIME_TO_P2[1] 01_212 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PD_TRANS_TIME_TO_P2[2] 00_213 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PD_TRANS_TIME_TO_P2[3] 01_213 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PD_TRANS_TIME_TO_P2[4] 00_214 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PD_TRANS_TIME_TO_P2[5] 01_214 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PD_TRANS_TIME_TO_P2[6] 00_215 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PD_TRANS_TIME_TO_P2[7] 01_215 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PMA_LOOPBACK_CFG[0] 01_207 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PMA_RSV[0] 02_520 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PMA_RSV[1] 03_520 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PMA_RSV[2] 02_521 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PMA_RSV[3] 03_521 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PMA_RSV[4] 02_522 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PMA_RSV[5] 03_522 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PMA_RSV[6] 02_523 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PMA_RSV[7] 03_523 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PMA_RSV[8] 02_524 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PMA_RSV[9] 03_524 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PMA_RSV[10] 02_525 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PMA_RSV[11] 03_525 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PMA_RSV[12] 02_526 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PMA_RSV[13] 03_526 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PMA_RSV[14] 02_527 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PMA_RSV[15] 03_527 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PMA_RSV[16] 02_528 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PMA_RSV[17] 03_528 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PMA_RSV[18] 02_529 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PMA_RSV[19] 03_529 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PMA_RSV[20] 02_530 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PMA_RSV[21] 03_530 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PMA_RSV[22] 02_531 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PMA_RSV[23] 03_531 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PMA_RSV[24] 02_532 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PMA_RSV[25] 03_532 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PMA_RSV[26] 02_533 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PMA_RSV[27] 03_533 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PMA_RSV[28] 02_534 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PMA_RSV[29] 03_534 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PMA_RSV[30] 02_535 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PMA_RSV[31] 03_535 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PMA_RSV2[0] 02_336 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PMA_RSV2[1] 03_336 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PMA_RSV2[2] 02_337 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PMA_RSV2[3] 03_337 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PMA_RSV2[4] 02_338 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PMA_RSV2[5] 03_338 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PMA_RSV2[6] 02_339 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PMA_RSV2[7] 03_339 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PMA_RSV2[8] 02_340 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PMA_RSV2[9] 03_340 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PMA_RSV2[10] 02_341 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PMA_RSV2[11] 03_341 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PMA_RSV2[12] 02_342 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PMA_RSV2[13] 03_342 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PMA_RSV2[14] 02_343 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PMA_RSV2[15] 03_343 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PMA_RSV2[16] 02_344 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PMA_RSV2[17] 03_344 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PMA_RSV2[18] 02_345 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PMA_RSV2[19] 03_345 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PMA_RSV2[20] 02_346 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PMA_RSV2[21] 03_346 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PMA_RSV2[22] 02_347 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PMA_RSV2[23] 03_347 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PMA_RSV2[24] 02_348 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PMA_RSV2[25] 03_348 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PMA_RSV2[26] 02_349 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PMA_RSV2[27] 03_349 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PMA_RSV2[28] 02_350 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PMA_RSV2[29] 03_350 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PMA_RSV2[30] 02_351 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PMA_RSV2[31] 03_351 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PMA_RSV3[0] 02_288 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PMA_RSV3[1] 03_288 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PMA_RSV4[0] 02_156 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PMA_RSV4[1] 03_156 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PMA_RSV4[2] 02_157 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PMA_RSV4[3] 03_157 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PMA_RSV5[0] 03_159 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PMA_RSV6[0] 02_303 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PMA_RSV7[0] 03_303 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_BIAS_CFG[0] 02_112 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_BIAS_CFG[1] 03_112 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_BIAS_CFG[2] 02_113 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_BIAS_CFG[3] 03_113 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_BIAS_CFG[4] 02_114 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_BIAS_CFG[5] 03_114 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_BIAS_CFG[6] 02_115 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_BIAS_CFG[7] 03_115 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_BIAS_CFG[8] 02_116 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_BIAS_CFG[9] 03_116 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_BIAS_CFG[10] 02_117 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_BIAS_CFG[11] 03_117 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_BIAS_CFG[12] 02_118 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_BIAS_CFG[13] 03_118 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_BIAS_CFG[14] 02_119 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_BIAS_CFG[15] 03_119 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_BUFFER_CFG[0] 02_536 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_BUFFER_CFG[1] 03_536 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_BUFFER_CFG[2] 02_537 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_BUFFER_CFG[3] 03_537 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_BUFFER_CFG[4] 02_538 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_BUFFER_CFG[5] 03_538 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_CLKMUX_EN[0] 02_128 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_CM_SEL[0] 00_138 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_CM_SEL[1] 01_138 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_CM_TRIM[0] 02_304 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_CM_TRIM[1] 03_304 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_CM_TRIM[2] 02_305 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_CM_TRIM[3] 03_305 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_DATA_WIDTH[0] 01_141 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_DATA_WIDTH[1] 00_142 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_DATA_WIDTH[2] 01_142 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_DDI_SEL[0] 00_696 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_DDI_SEL[1] 01_696 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_DDI_SEL[2] 00_697 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_DDI_SEL[3] 01_697 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_DDI_SEL[4] 00_698 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_DDI_SEL[5] 01_698 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_DEBUG_CFG[0] 02_616 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_DEBUG_CFG[1] 03_616 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_DEBUG_CFG[2] 02_617 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_DEBUG_CFG[3] 03_617 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_DEBUG_CFG[4] 02_618 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_DEBUG_CFG[5] 03_618 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_DEBUG_CFG[6] 02_619 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_DEBUG_CFG[7] 03_619 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_DEBUG_CFG[8] 02_620 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_DEBUG_CFG[9] 03_620 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_DEBUG_CFG[10] 02_621 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_DEBUG_CFG[11] 03_621 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_DEBUG_CFG[12] 02_622 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_DEBUG_CFG[13] 03_622 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_DEFER_RESET_BUF_EN 02_552 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_DISPERR_SEQ_MATCH 01_495 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_OS_CFG[0] 00_288 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_OS_CFG[1] 01_288 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_OS_CFG[2] 00_289 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_OS_CFG[3] 01_289 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_OS_CFG[4] 00_290 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_OS_CFG[5] 01_290 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_OS_CFG[6] 00_291 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_OS_CFG[7] 01_291 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_OS_CFG[8] 00_292 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_OS_CFG[9] 01_292 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_OS_CFG[10] 00_293 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_OS_CFG[11] 01_293 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_OS_CFG[12] 00_294 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_SIG_VALID_DLY[0] 00_524 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_SIG_VALID_DLY[1] 01_524 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_SIG_VALID_DLY[2] 00_525 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_SIG_VALID_DLY[3] 01_525 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_SIG_VALID_DLY[4] 00_526 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_XCLK_SEL.RXUSR 00_143 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_CLK25_DIV[0] 00_139 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_CLK25_DIV[1] 01_139 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_CLK25_DIV[2] 00_140 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_CLK25_DIV[3] 01_140 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_CLK25_DIV[4] 00_141 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXBUF_ADDR_MODE.FAST 03_555 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXBUF_EIDLE_HI_CNT[0] 02_558 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXBUF_EIDLE_HI_CNT[1] 03_558 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXBUF_EIDLE_HI_CNT[2] 02_559 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXBUF_EIDLE_HI_CNT[3] 03_559 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXBUF_EIDLE_LO_CNT[0] 02_556 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXBUF_EIDLE_LO_CNT[1] 03_556 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXBUF_EIDLE_LO_CNT[2] 02_557 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXBUF_EIDLE_LO_CNT[3] 03_557 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXBUF_EN 02_11 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXBUF_RESET_ON_CB_CHANGE 02_560 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXBUF_RESET_ON_COMMAALIGN 02_561 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXBUF_RESET_ON_EIDLE 02_547 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXBUF_RESET_ON_RATE_CHANGE 03_560 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXBUF_THRESH_OVFLW[0] 03_552 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXBUF_THRESH_OVFLW[1] 02_553 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXBUF_THRESH_OVFLW[2] 03_553 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXBUF_THRESH_OVFLW[3] 02_554 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXBUF_THRESH_OVFLW[4] 03_554 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXBUF_THRESH_OVFLW[5] 02_555 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXBUF_THRESH_OVRD 02_548 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXBUF_THRESH_UNDFLW[0] 02_544 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXBUF_THRESH_UNDFLW[1] 03_544 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXBUF_THRESH_UNDFLW[2] 02_545 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXBUF_THRESH_UNDFLW[3] 03_545 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXBUF_THRESH_UNDFLW[4] 02_546 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXBUF_THRESH_UNDFLW[5] 03_546 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXBUFRESET_TIME[0] 01_101 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXBUFRESET_TIME[1] 00_102 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXBUFRESET_TIME[2] 01_102 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXBUFRESET_TIME[3] 00_103 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXBUFRESET_TIME[4] 01_103 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[0] 02_640 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[1] 03_640 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[2] 02_641 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[3] 03_641 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[4] 02_642 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[5] 03_642 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[6] 02_643 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[7] 03_643 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[8] 02_644 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[9] 03_644 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[10] 02_645 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[11] 03_645 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[12] 02_646 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[13] 03_646 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[14] 02_647 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[15] 03_647 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[16] 02_648 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[17] 03_648 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[18] 02_649 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[19] 03_649 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[20] 02_650 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[21] 03_650 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[22] 02_651 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[23] 03_651 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[24] 02_652 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[25] 03_652 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[26] 02_653 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[27] 03_653 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[28] 02_654 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[29] 03_654 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[30] 02_655 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[31] 03_655 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[32] 02_656 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[33] 03_656 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[34] 02_657 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[35] 03_657 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[36] 02_658 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[37] 03_658 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[38] 02_659 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[39] 03_659 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[40] 02_660 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[41] 03_660 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[42] 02_661 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[43] 03_661 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[44] 02_662 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[45] 03_662 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[46] 02_663 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[47] 03_663 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[48] 02_664 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[49] 03_664 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[50] 02_665 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[51] 03_665 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[52] 02_666 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[53] 03_666 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[54] 02_667 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[55] 03_667 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[56] 02_668 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[57] 03_668 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[58] 02_669 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[59] 03_669 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[60] 02_670 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[61] 03_670 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[62] 02_671 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[63] 03_671 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[64] 02_672 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[65] 03_672 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[66] 02_673 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[67] 03_673 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[68] 02_674 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[69] 03_674 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[70] 02_675 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[71] 03_675 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[72] 02_676 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[73] 03_676 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[74] 02_677 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[75] 03_677 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[76] 02_678 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[77] 03_678 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[78] 02_679 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[79] 03_679 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[80] 02_680 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[81] 03_680 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[82] 02_681 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_FR_RESET_ON_EIDLE[0] 02_638 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_HOLD_DURING_EIDLE[0] 03_637 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_LOCK_CFG[0] 02_632 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_LOCK_CFG[1] 03_632 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_LOCK_CFG[2] 02_633 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_LOCK_CFG[3] 03_633 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_LOCK_CFG[4] 02_634 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_LOCK_CFG[5] 03_634 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_PH_RESET_ON_EIDLE[0] 03_638 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDRFREQRESET_TIME[0] 01_106 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDRFREQRESET_TIME[1] 00_107 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDRFREQRESET_TIME[2] 01_107 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDRFREQRESET_TIME[3] 00_108 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDRFREQRESET_TIME[4] 01_108 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDRPHRESET_TIME[0] 00_109 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDRPHRESET_TIME[1] 01_109 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDRPHRESET_TIME[2] 00_110 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDRPHRESET_TIME[3] 01_110 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDRPHRESET_TIME[4] 00_111 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXDLY_CFG[0] 00_680 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXDLY_CFG[1] 01_680 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXDLY_CFG[2] 00_681 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXDLY_CFG[3] 01_681 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXDLY_CFG[4] 00_682 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXDLY_CFG[5] 01_682 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXDLY_CFG[6] 00_683 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXDLY_CFG[7] 01_683 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXDLY_CFG[8] 00_684 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXDLY_CFG[9] 01_684 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXDLY_CFG[10] 00_685 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXDLY_CFG[11] 01_685 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXDLY_CFG[12] 00_686 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXDLY_CFG[13] 01_686 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXDLY_CFG[14] 00_687 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXDLY_CFG[15] 01_687 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXDLY_LCFG[0] 02_576 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXDLY_LCFG[1] 03_576 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXDLY_LCFG[2] 02_577 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXDLY_LCFG[3] 03_577 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXDLY_LCFG[4] 02_578 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXDLY_LCFG[5] 03_578 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXDLY_LCFG[6] 02_579 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXDLY_LCFG[7] 03_579 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXDLY_LCFG[8] 02_580 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXDLY_TAP_CFG[0] 00_672 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXDLY_TAP_CFG[1] 01_672 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXDLY_TAP_CFG[2] 00_673 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXDLY_TAP_CFG[3] 01_673 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXDLY_TAP_CFG[4] 00_674 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXDLY_TAP_CFG[5] 01_674 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXDLY_TAP_CFG[6] 00_675 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXDLY_TAP_CFG[7] 01_675 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXDLY_TAP_CFG[8] 00_676 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXDLY_TAP_CFG[9] 01_676 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXDLY_TAP_CFG[10] 00_677 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXDLY_TAP_CFG[11] 01_677 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXDLY_TAP_CFG[12] 00_678 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXDLY_TAP_CFG[13] 01_678 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXDLY_TAP_CFG[14] 00_679 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXDLY_TAP_CFG[15] 01_679 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXGEARBOX_EN 01_607 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXISCANRESET_TIME[0] 01_123 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXISCANRESET_TIME[1] 00_124 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXISCANRESET_TIME[2] 01_124 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXISCANRESET_TIME[3] 00_125 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXISCANRESET_TIME[4] 01_125 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPM_BIAS_STARTUP_DISABLE[0] 03_391 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPM_CFG[0] 02_328 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPM_CFG[1] 03_328 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPM_CFG[2] 02_329 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPM_CFG[3] 03_329 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPM_CM_CFG[0] 02_430 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPM_GC_CFG[0] 02_432 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPM_GC_CFG[1] 03_432 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPM_GC_CFG[2] 02_433 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPM_GC_CFG[3] 03_433 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPM_GC_CFG[4] 02_434 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPM_GC_CFG[5] 03_434 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPM_GC_CFG[6] 02_435 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPM_GC_CFG[7] 03_435 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPM_GC_CFG[8] 02_436 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPM_GC_CFG2[0] 03_442 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPM_GC_CFG2[1] 02_443 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPM_GC_CFG2[2] 03_443 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPM_HF_CFG[0] 00_336 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPM_HF_CFG[1] 01_336 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPM_HF_CFG[2] 00_337 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPM_HF_CFG[3] 01_337 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPM_HF_CFG[4] 00_338 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPM_HF_CFG[5] 01_338 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPM_HF_CFG[6] 00_339 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPM_HF_CFG[7] 01_339 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPM_HF_CFG[8] 00_340 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPM_HF_CFG[9] 01_340 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPM_HF_CFG[10] 00_341 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPM_HF_CFG[11] 01_341 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPM_HF_CFG[12] 00_342 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPM_HF_CFG[13] 01_342 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPM_HF_CFG2[0] 02_424 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPM_HF_CFG2[1] 03_424 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPM_HF_CFG2[2] 02_425 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPM_HF_CFG2[3] 03_425 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPM_HF_CFG2[4] 02_426 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPM_HF_CFG3[0] 03_389 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPM_HF_CFG3[1] 02_390 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPM_HF_CFG3[2] 03_390 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPM_HF_CFG3[3] 02_391 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPM_HOLD_DURING_EIDLE[0] 00_247 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPM_INCM_CFG[0] 02_439 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPM_IPCM_CFG[0] 03_439 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPM_LF_CFG[0] 00_344 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPM_LF_CFG[1] 01_344 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPM_LF_CFG[2] 00_345 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPM_LF_CFG[3] 01_345 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPM_LF_CFG[4] 00_346 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPM_LF_CFG[5] 01_346 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPM_LF_CFG[6] 00_347 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPM_LF_CFG[7] 01_347 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPM_LF_CFG[8] 00_348 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPM_LF_CFG[9] 01_348 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPM_LF_CFG[10] 00_349 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPM_LF_CFG[11] 01_349 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPM_LF_CFG[12] 00_350 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPM_LF_CFG[13] 01_350 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPM_LF_CFG[14] 00_351 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPM_LF_CFG[15] 01_351 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPM_LF_CFG[16] 00_343 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPM_LF_CFG[17] 01_343 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPM_LF_CFG2[0] 03_426 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPM_LF_CFG2[1] 02_427 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPM_LF_CFG2[2] 03_427 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPM_LF_CFG2[3] 02_428 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPM_LF_CFG2[4] 03_428 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPM_OSINT_CFG[0] 02_440 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPM_OSINT_CFG[1] 03_440 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPM_OSINT_CFG[2] 02_441 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPM_CFG1[0] 02_330 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPMRESET_TIME[0] 00_112 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPMRESET_TIME[1] 01_112 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPMRESET_TIME[2] 00_113 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPMRESET_TIME[3] 01_113 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPMRESET_TIME[4] 00_114 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPMRESET_TIME[5] 01_114 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPMRESET_TIME[6] 00_115 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXOOB_CFG[0] 00_144 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXOOB_CFG[1] 01_144 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXOOB_CFG[2] 00_145 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXOOB_CFG[3] 01_145 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXOOB_CFG[4] 00_146 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXOOB_CFG[5] 01_146 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXOOB_CFG[6] 00_147 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXOOB_CLK_CFG.FABRIC 03_129 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXOSCALRESET_TIME[0] 00_187 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXOSCALRESET_TIME[1] 01_187 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXOSCALRESET_TIME[2] 00_188 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXOSCALRESET_TIME[3] 01_188 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXOSCALRESET_TIME[4] 00_189 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXOSCALRESET_TIMEOUT[0] 01_189 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXOSCALRESET_TIMEOUT[1] 00_190 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXOSCALRESET_TIMEOUT[2] 01_190 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXOSCALRESET_TIMEOUT[3] 00_191 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXOSCALRESET_TIMEOUT[4] 01_191 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXOUT_DIV[0] 02_384 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXOUT_DIV[1] 03_384 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXPCSRESET_TIME[0] 01_115 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXPCSRESET_TIME[1] 00_116 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXPCSRESET_TIME[2] 01_116 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXPCSRESET_TIME[3] 00_117 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXPCSRESET_TIME[4] 01_117 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXPH_CFG[0] 02_584 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXPH_CFG[1] 03_584 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXPH_CFG[2] 02_585 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXPH_CFG[3] 03_585 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXPH_CFG[4] 02_586 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXPH_CFG[5] 03_586 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXPH_CFG[6] 02_587 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXPH_CFG[7] 03_587 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXPH_CFG[8] 02_588 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXPH_CFG[9] 03_588 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXPH_CFG[10] 02_589 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXPH_CFG[11] 03_589 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXPH_CFG[12] 02_590 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXPH_CFG[13] 03_590 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXPH_CFG[14] 02_591 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXPH_CFG[15] 03_591 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXPH_CFG[16] 02_592 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXPH_CFG[17] 03_592 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXPH_CFG[18] 02_593 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXPH_CFG[19] 03_593 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXPH_CFG[20] 02_594 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXPH_CFG[21] 03_594 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXPH_CFG[22] 02_595 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXPH_CFG[23] 03_595 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXPH_MONITOR_SEL[0] 00_700 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXPH_MONITOR_SEL[1] 01_700 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXPH_MONITOR_SEL[2] 00_701 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXPH_MONITOR_SEL[3] 01_701 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXPH_MONITOR_SEL[4] 00_702 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXPHDLY_CFG[0] 02_600 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXPHDLY_CFG[1] 03_600 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXPHDLY_CFG[2] 02_601 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXPHDLY_CFG[3] 03_601 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXPHDLY_CFG[4] 02_602 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXPHDLY_CFG[5] 03_602 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXPHDLY_CFG[6] 02_603 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXPHDLY_CFG[7] 03_603 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXPHDLY_CFG[8] 02_604 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXPHDLY_CFG[9] 03_604 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXPHDLY_CFG[10] 02_605 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXPHDLY_CFG[11] 03_605 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXPHDLY_CFG[12] 02_606 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXPHDLY_CFG[13] 03_606 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXPHDLY_CFG[14] 02_607 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXPHDLY_CFG[15] 03_607 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXPHDLY_CFG[16] 02_608 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXPHDLY_CFG[17] 03_608 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXPHDLY_CFG[18] 02_609 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXPHDLY_CFG[19] 03_609 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXPHDLY_CFG[20] 02_610 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXPHDLY_CFG[21] 03_610 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXPHDLY_CFG[22] 02_611 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXPHDLY_CFG[23] 03_611 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXPI_CFG0[0] 03_430 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXPI_CFG0[1] 02_431 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXPI_CFG0[2] 03_431 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXPI_CFG1[0] 02_442 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXPI_CFG2[0] 03_441 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXPMARESET_TIME[0] 00_104 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXPMARESET_TIME[1] 01_104 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXPMARESET_TIME[2] 00_105 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXPMARESET_TIME[3] 01_105 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXPMARESET_TIME[4] 00_106 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXPRBS_ERR_LOOPBACK[0] 00_136 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXSLIDE_AUTO_WAIT[0] 00_520 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXSLIDE_AUTO_WAIT[1] 01_520 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXSLIDE_AUTO_WAIT[2] 00_521 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXSLIDE_AUTO_WAIT[3] 01_521 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXSLIDE_MODE.AUTO 00_519 !01_519 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXSLIDE_MODE.PCS !00_519 01_519 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXSLIDE_MODE.PMA 00_519 01_519 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXSYNC_MULTILANE[0] 00_133 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXSYNC_OVRD[0] 01_135 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXSYNC_SKIP_DA[0] 01_134 -GTP_CHANNEL_2_MID_LEFT.GTPE2.SAS_MAX_COM[0] 00_171 -GTP_CHANNEL_2_MID_LEFT.GTPE2.SAS_MAX_COM[1] 01_171 -GTP_CHANNEL_2_MID_LEFT.GTPE2.SAS_MAX_COM[2] 00_172 -GTP_CHANNEL_2_MID_LEFT.GTPE2.SAS_MAX_COM[3] 01_172 -GTP_CHANNEL_2_MID_LEFT.GTPE2.SAS_MAX_COM[4] 00_173 -GTP_CHANNEL_2_MID_LEFT.GTPE2.SAS_MAX_COM[5] 01_173 -GTP_CHANNEL_2_MID_LEFT.GTPE2.SAS_MAX_COM[6] 00_174 -GTP_CHANNEL_2_MID_LEFT.GTPE2.SAS_MIN_COM[0] 01_156 -GTP_CHANNEL_2_MID_LEFT.GTPE2.SAS_MIN_COM[1] 00_157 -GTP_CHANNEL_2_MID_LEFT.GTPE2.SAS_MIN_COM[2] 01_157 -GTP_CHANNEL_2_MID_LEFT.GTPE2.SAS_MIN_COM[3] 00_158 -GTP_CHANNEL_2_MID_LEFT.GTPE2.SAS_MIN_COM[4] 01_158 -GTP_CHANNEL_2_MID_LEFT.GTPE2.SAS_MIN_COM[5] 00_159 -GTP_CHANNEL_2_MID_LEFT.GTPE2.SATA_BURST_SEQ_LEN[0] 00_150 -GTP_CHANNEL_2_MID_LEFT.GTPE2.SATA_BURST_SEQ_LEN[1] 01_150 -GTP_CHANNEL_2_MID_LEFT.GTPE2.SATA_BURST_SEQ_LEN[2] 00_151 -GTP_CHANNEL_2_MID_LEFT.GTPE2.SATA_BURST_SEQ_LEN[3] 01_151 -GTP_CHANNEL_2_MID_LEFT.GTPE2.SATA_BURST_VAL[0] 01_147 -GTP_CHANNEL_2_MID_LEFT.GTPE2.SATA_BURST_VAL[1] 00_148 -GTP_CHANNEL_2_MID_LEFT.GTPE2.SATA_BURST_VAL[2] 01_148 -GTP_CHANNEL_2_MID_LEFT.GTPE2.SATA_EIDLE_VAL[0] 00_152 -GTP_CHANNEL_2_MID_LEFT.GTPE2.SATA_EIDLE_VAL[1] 01_152 -GTP_CHANNEL_2_MID_LEFT.GTPE2.SATA_EIDLE_VAL[2] 00_153 -GTP_CHANNEL_2_MID_LEFT.GTPE2.SATA_MAX_BURST[0] 00_168 -GTP_CHANNEL_2_MID_LEFT.GTPE2.SATA_MAX_BURST[1] 01_168 -GTP_CHANNEL_2_MID_LEFT.GTPE2.SATA_MAX_BURST[2] 00_169 -GTP_CHANNEL_2_MID_LEFT.GTPE2.SATA_MAX_BURST[3] 01_169 -GTP_CHANNEL_2_MID_LEFT.GTPE2.SATA_MAX_BURST[4] 00_170 -GTP_CHANNEL_2_MID_LEFT.GTPE2.SATA_MAX_BURST[5] 01_170 -GTP_CHANNEL_2_MID_LEFT.GTPE2.SATA_MAX_INIT[0] 00_176 -GTP_CHANNEL_2_MID_LEFT.GTPE2.SATA_MAX_INIT[1] 01_176 -GTP_CHANNEL_2_MID_LEFT.GTPE2.SATA_MAX_INIT[2] 00_177 -GTP_CHANNEL_2_MID_LEFT.GTPE2.SATA_MAX_INIT[3] 01_177 -GTP_CHANNEL_2_MID_LEFT.GTPE2.SATA_MAX_INIT[4] 00_178 -GTP_CHANNEL_2_MID_LEFT.GTPE2.SATA_MAX_INIT[5] 01_178 -GTP_CHANNEL_2_MID_LEFT.GTPE2.SATA_MAX_WAKE[0] 00_179 -GTP_CHANNEL_2_MID_LEFT.GTPE2.SATA_MAX_WAKE[1] 01_179 -GTP_CHANNEL_2_MID_LEFT.GTPE2.SATA_MAX_WAKE[2] 00_180 -GTP_CHANNEL_2_MID_LEFT.GTPE2.SATA_MAX_WAKE[3] 01_180 -GTP_CHANNEL_2_MID_LEFT.GTPE2.SATA_MAX_WAKE[4] 00_181 -GTP_CHANNEL_2_MID_LEFT.GTPE2.SATA_MAX_WAKE[5] 01_181 -GTP_CHANNEL_2_MID_LEFT.GTPE2.SATA_MIN_BURST[0] 01_153 -GTP_CHANNEL_2_MID_LEFT.GTPE2.SATA_MIN_BURST[1] 00_154 -GTP_CHANNEL_2_MID_LEFT.GTPE2.SATA_MIN_BURST[2] 01_154 -GTP_CHANNEL_2_MID_LEFT.GTPE2.SATA_MIN_BURST[3] 00_155 -GTP_CHANNEL_2_MID_LEFT.GTPE2.SATA_MIN_BURST[4] 01_155 -GTP_CHANNEL_2_MID_LEFT.GTPE2.SATA_MIN_BURST[5] 00_156 -GTP_CHANNEL_2_MID_LEFT.GTPE2.SATA_MIN_INIT[0] 00_160 -GTP_CHANNEL_2_MID_LEFT.GTPE2.SATA_MIN_INIT[1] 01_160 -GTP_CHANNEL_2_MID_LEFT.GTPE2.SATA_MIN_INIT[2] 00_161 -GTP_CHANNEL_2_MID_LEFT.GTPE2.SATA_MIN_INIT[3] 01_161 -GTP_CHANNEL_2_MID_LEFT.GTPE2.SATA_MIN_INIT[4] 00_162 -GTP_CHANNEL_2_MID_LEFT.GTPE2.SATA_MIN_INIT[5] 01_162 -GTP_CHANNEL_2_MID_LEFT.GTPE2.SATA_MIN_WAKE[0] 00_163 -GTP_CHANNEL_2_MID_LEFT.GTPE2.SATA_MIN_WAKE[1] 01_163 -GTP_CHANNEL_2_MID_LEFT.GTPE2.SATA_MIN_WAKE[2] 00_164 -GTP_CHANNEL_2_MID_LEFT.GTPE2.SATA_MIN_WAKE[3] 01_164 -GTP_CHANNEL_2_MID_LEFT.GTPE2.SATA_MIN_WAKE[4] 00_165 -GTP_CHANNEL_2_MID_LEFT.GTPE2.SATA_MIN_WAKE[5] 01_165 -GTP_CHANNEL_2_MID_LEFT.GTPE2.SATA_PLL_CFG.VCO_1500MHZ 02_55 -GTP_CHANNEL_2_MID_LEFT.GTPE2.SATA_PLL_CFG.VCO_750MHZ 03_55 -GTP_CHANNEL_2_MID_LEFT.GTPE2.SHOW_REALIGN_COMMA 01_522 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TERM_RCAL_CFG[0] 02_136 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TERM_RCAL_CFG[1] 03_136 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TERM_RCAL_CFG[2] 02_137 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TERM_RCAL_CFG[3] 03_137 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TERM_RCAL_CFG[4] 02_138 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TERM_RCAL_CFG[5] 03_138 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TERM_RCAL_CFG[6] 02_139 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TERM_RCAL_CFG[7] 03_139 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TERM_RCAL_CFG[8] 02_140 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TERM_RCAL_CFG[9] 03_140 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TERM_RCAL_CFG[10] 02_141 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TERM_RCAL_CFG[11] 03_141 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TERM_RCAL_CFG[12] 02_142 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TERM_RCAL_CFG[13] 03_142 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TERM_RCAL_CFG[14] 02_143 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TERM_RCAL_OVRD[0] 03_150 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TERM_RCAL_OVRD[1] 02_151 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TERM_RCAL_OVRD[2] 03_151 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TRANS_TIME_RATE[0] 00_192 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TRANS_TIME_RATE[1] 01_192 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TRANS_TIME_RATE[2] 00_193 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TRANS_TIME_RATE[3] 01_193 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TRANS_TIME_RATE[4] 00_194 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TRANS_TIME_RATE[5] 01_194 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TRANS_TIME_RATE[6] 00_195 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TRANS_TIME_RATE[7] 01_195 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TST_RSV[0] 02_504 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TST_RSV[1] 03_504 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TST_RSV[2] 02_505 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TST_RSV[3] 03_505 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TST_RSV[4] 02_506 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TST_RSV[5] 03_506 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TST_RSV[6] 02_507 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TST_RSV[7] 03_507 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TST_RSV[8] 02_508 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TST_RSV[9] 03_508 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TST_RSV[10] 02_509 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TST_RSV[11] 03_509 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TST_RSV[12] 02_510 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TST_RSV[13] 03_510 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TST_RSV[14] 02_511 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TST_RSV[15] 03_511 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TST_RSV[16] 02_512 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TST_RSV[17] 03_512 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TST_RSV[18] 02_513 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TST_RSV[19] 03_513 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TST_RSV[20] 02_514 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TST_RSV[21] 03_514 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TST_RSV[22] 02_515 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TST_RSV[23] 03_515 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TST_RSV[24] 02_516 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TST_RSV[25] 03_516 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TST_RSV[26] 02_517 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TST_RSV[27] 03_517 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TST_RSV[28] 02_518 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TST_RSV[29] 03_518 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TST_RSV[30] 02_519 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TST_RSV[31] 03_519 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_CLKMUX_EN[0] 03_128 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_DATA_WIDTH[0] 02_152 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_DATA_WIDTH[1] 03_152 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_DATA_WIDTH[2] 02_153 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_DRIVE_MODE.PIPE 00_200 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_EIDLE_ASSERT_DELAY[0] 00_203 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_EIDLE_ASSERT_DELAY[1] 01_203 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_EIDLE_ASSERT_DELAY[2] 00_204 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_EIDLE_DEASSERT_DELAY[0] 01_204 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_EIDLE_DEASSERT_DELAY[1] 00_205 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_EIDLE_DEASSERT_DELAY[2] 01_205 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_LOOPBACK_DRIVE_HIZ 01_202 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_MAINCURSOR_SEL[0] 03_289 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_MARGIN_FULL_0[0] 02_232 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_MARGIN_FULL_0[1] 03_232 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_MARGIN_FULL_0[2] 02_233 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_MARGIN_FULL_0[3] 03_233 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_MARGIN_FULL_0[4] 02_234 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_MARGIN_FULL_0[5] 03_234 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_MARGIN_FULL_0[6] 02_235 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_MARGIN_FULL_1[0] 02_236 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_MARGIN_FULL_1[1] 03_236 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_MARGIN_FULL_1[2] 02_237 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_MARGIN_FULL_1[3] 03_237 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_MARGIN_FULL_1[4] 02_238 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_MARGIN_FULL_1[5] 03_238 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_MARGIN_FULL_1[6] 02_239 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_MARGIN_FULL_2[0] 02_240 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_MARGIN_FULL_2[1] 03_240 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_MARGIN_FULL_2[2] 02_241 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_MARGIN_FULL_2[3] 03_241 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_MARGIN_FULL_2[4] 02_242 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_MARGIN_FULL_2[5] 03_242 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_MARGIN_FULL_2[6] 02_243 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_MARGIN_FULL_3[0] 02_244 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_MARGIN_FULL_3[1] 03_244 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_MARGIN_FULL_3[2] 02_245 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_MARGIN_FULL_3[3] 03_245 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_MARGIN_FULL_3[4] 02_246 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_MARGIN_FULL_3[5] 03_246 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_MARGIN_FULL_3[6] 02_247 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_MARGIN_FULL_4[0] 02_248 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_MARGIN_FULL_4[1] 03_248 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_MARGIN_FULL_4[2] 02_249 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_MARGIN_FULL_4[3] 03_249 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_MARGIN_FULL_4[4] 02_250 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_MARGIN_FULL_4[5] 03_250 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_MARGIN_FULL_4[6] 02_251 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_MARGIN_LOW_0[0] 02_252 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_MARGIN_LOW_0[1] 03_252 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_MARGIN_LOW_0[2] 02_253 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_MARGIN_LOW_0[3] 03_253 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_MARGIN_LOW_0[4] 02_254 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_MARGIN_LOW_0[5] 03_254 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_MARGIN_LOW_0[6] 02_255 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_MARGIN_LOW_1[0] 02_256 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_MARGIN_LOW_1[1] 03_256 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_MARGIN_LOW_1[2] 02_257 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_MARGIN_LOW_1[3] 03_257 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_MARGIN_LOW_1[4] 02_258 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_MARGIN_LOW_1[5] 03_258 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_MARGIN_LOW_1[6] 02_259 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_MARGIN_LOW_2[0] 02_260 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_MARGIN_LOW_2[1] 03_260 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_MARGIN_LOW_2[2] 02_261 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_MARGIN_LOW_2[3] 03_261 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_MARGIN_LOW_2[4] 02_262 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_MARGIN_LOW_2[5] 03_262 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_MARGIN_LOW_2[6] 02_263 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_MARGIN_LOW_3[0] 02_264 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_MARGIN_LOW_3[1] 03_264 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_MARGIN_LOW_3[2] 02_265 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_MARGIN_LOW_3[3] 03_265 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_MARGIN_LOW_3[4] 02_266 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_MARGIN_LOW_3[5] 03_266 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_MARGIN_LOW_3[6] 02_267 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_MARGIN_LOW_4[0] 02_268 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_MARGIN_LOW_4[1] 03_268 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_MARGIN_LOW_4[2] 02_269 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_MARGIN_LOW_4[3] 03_269 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_MARGIN_LOW_4[4] 02_270 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_MARGIN_LOW_4[5] 03_270 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_MARGIN_LOW_4[6] 02_271 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_PREDRIVER_MODE[0] 00_206 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_RXDETECT_CFG[0] 02_296 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_RXDETECT_CFG[1] 03_296 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_RXDETECT_CFG[2] 02_297 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_RXDETECT_CFG[3] 03_297 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_RXDETECT_CFG[4] 02_298 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_RXDETECT_CFG[5] 03_298 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_RXDETECT_CFG[6] 02_299 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_RXDETECT_CFG[7] 03_299 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_RXDETECT_CFG[8] 02_300 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_RXDETECT_CFG[9] 03_300 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_RXDETECT_CFG[10] 02_301 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_RXDETECT_CFG[11] 03_301 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_RXDETECT_CFG[12] 02_302 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_RXDETECT_CFG[13] 03_302 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_RXDETECT_REF[0] 02_292 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_RXDETECT_REF[1] 03_292 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_RXDETECT_REF[2] 02_293 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_XCLK_SEL.TXUSR 03_11 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_CLK25_DIV[0] 02_144 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_CLK25_DIV[1] 03_144 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_CLK25_DIV[2] 02_145 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_CLK25_DIV[3] 03_145 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_CLK25_DIV[4] 02_146 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_DEEMPH0[0] 02_272 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_DEEMPH0[1] 03_272 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_DEEMPH0[2] 02_273 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_DEEMPH0[3] 03_273 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_DEEMPH0[4] 02_274 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_DEEMPH0[5] 03_274 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_DEEMPH1[0] 02_276 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_DEEMPH1[1] 03_276 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_DEEMPH1[2] 02_277 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_DEEMPH1[3] 03_277 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_DEEMPH1[4] 02_278 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_DEEMPH1[5] 03_278 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXBUF_EN 00_231 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXBUF_RESET_ON_RATE_CHANGE 01_231 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXDLY_CFG[0] 02_80 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXDLY_CFG[1] 03_80 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXDLY_CFG[2] 02_81 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXDLY_CFG[3] 03_81 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXDLY_CFG[4] 02_82 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXDLY_CFG[5] 03_82 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXDLY_CFG[6] 02_83 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXDLY_CFG[7] 03_83 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXDLY_CFG[8] 02_84 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXDLY_CFG[9] 03_84 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXDLY_CFG[10] 02_85 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXDLY_CFG[11] 03_85 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXDLY_CFG[12] 02_86 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXDLY_CFG[13] 03_86 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXDLY_CFG[14] 02_87 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXDLY_CFG[15] 03_87 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXDLY_LCFG[0] 02_568 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXDLY_LCFG[1] 03_568 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXDLY_LCFG[2] 02_569 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXDLY_LCFG[3] 03_569 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXDLY_LCFG[4] 02_570 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXDLY_LCFG[5] 03_570 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXDLY_LCFG[6] 02_571 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXDLY_LCFG[7] 03_571 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXDLY_LCFG[8] 02_572 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXDLY_TAP_CFG[0] 02_88 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXDLY_TAP_CFG[1] 03_88 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXDLY_TAP_CFG[2] 02_89 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXDLY_TAP_CFG[3] 03_89 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXDLY_TAP_CFG[4] 02_90 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXDLY_TAP_CFG[5] 03_90 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXDLY_TAP_CFG[6] 02_91 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXDLY_TAP_CFG[7] 03_91 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXDLY_TAP_CFG[8] 02_92 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXDLY_TAP_CFG[9] 03_92 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXDLY_TAP_CFG[10] 02_93 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXDLY_TAP_CFG[11] 03_93 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXDLY_TAP_CFG[12] 02_94 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXDLY_TAP_CFG[13] 03_94 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXDLY_TAP_CFG[14] 02_95 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXDLY_TAP_CFG[15] 03_95 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXGEARBOX_EN 01_226 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXOOB_CFG[0] 03_20 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXOUT_DIV[0] 02_386 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXOUT_DIV[1] 03_386 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPCSRESET_TIME[0] 01_130 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPCSRESET_TIME[1] 00_131 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPCSRESET_TIME[2] 01_131 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPCSRESET_TIME[3] 00_132 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPCSRESET_TIME[4] 01_132 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPH_CFG[0] 02_96 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPH_CFG[1] 03_96 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPH_CFG[2] 02_97 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPH_CFG[3] 03_97 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPH_CFG[4] 02_98 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPH_CFG[5] 03_98 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPH_CFG[6] 02_99 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPH_CFG[7] 03_99 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPH_CFG[8] 02_100 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPH_CFG[9] 03_100 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPH_CFG[10] 02_101 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPH_CFG[11] 03_101 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPH_CFG[12] 02_102 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPH_CFG[13] 03_102 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPH_CFG[14] 02_103 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPH_CFG[15] 03_103 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPH_MONITOR_SEL[0] 02_108 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPH_MONITOR_SEL[1] 03_108 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPH_MONITOR_SEL[2] 02_109 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPH_MONITOR_SEL[3] 03_109 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPH_MONITOR_SEL[4] 02_110 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPHDLY_CFG[0] 02_64 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPHDLY_CFG[1] 03_64 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPHDLY_CFG[2] 02_65 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPHDLY_CFG[3] 03_65 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPHDLY_CFG[4] 02_66 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPHDLY_CFG[5] 03_66 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPHDLY_CFG[6] 02_67 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPHDLY_CFG[7] 03_67 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPHDLY_CFG[8] 02_68 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPHDLY_CFG[9] 03_68 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPHDLY_CFG[10] 02_69 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPHDLY_CFG[11] 03_69 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPHDLY_CFG[12] 02_70 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPHDLY_CFG[13] 03_70 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPHDLY_CFG[14] 02_71 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPHDLY_CFG[15] 03_71 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPHDLY_CFG[16] 02_72 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPHDLY_CFG[17] 03_72 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPHDLY_CFG[18] 02_73 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPHDLY_CFG[19] 03_73 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPHDLY_CFG[20] 02_74 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPHDLY_CFG[21] 03_74 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPHDLY_CFG[22] 02_75 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPHDLY_CFG[23] 03_75 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPI_GREY_SEL[0] 03_498 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPI_INVSTROBE_SEL[0] 02_498 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPI_PPM_CFG[0] 02_488 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPI_PPM_CFG[1] 03_488 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPI_PPM_CFG[2] 02_489 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPI_PPM_CFG[3] 03_489 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPI_PPM_CFG[4] 02_490 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPI_PPM_CFG[5] 03_490 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPI_PPM_CFG[6] 02_491 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPI_PPM_CFG[7] 03_491 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPI_PPMCLK_SEL.TXUSRCLK2 03_497 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPI_SYNFREQ_PPM[0] 02_496 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPI_SYNFREQ_PPM[1] 03_496 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPI_SYNFREQ_PPM[2] 02_497 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPI_CFG0[0] 02_40 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPI_CFG0[1] 03_40 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPI_CFG1[0] 02_41 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPI_CFG1[1] 03_41 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPI_CFG2[0] 02_42 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPI_CFG2[1] 03_42 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPI_CFG3[0] 02_43 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPI_CFG4[0] 03_43 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPI_CFG5[0] 02_44 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPI_CFG5[1] 03_44 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPI_CFG5[2] 02_45 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPMARESET_TIME[0] 00_128 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPMARESET_TIME[1] 01_128 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPMARESET_TIME[2] 00_129 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPMARESET_TIME[3] 01_129 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPMARESET_TIME[4] 00_130 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXSYNC_MULTILANE[0] 01_133 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXSYNC_OVRD[0] 00_135 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXSYNC_SKIP_DA[0] 00_134 -GTP_CHANNEL_2_MID_LEFT.GTPE2.UCODEER_CLR[0] 01_00 -GTP_CHANNEL_2_MID_LEFT.GTPE2.USE_PCS_CLK_PHASE_SEL[0] 02_463 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ZINV_DMONITORCLK 02_13 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ZINV_DRPCLK 02_00 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ZINV_RXUSRCLK 03_01 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ZINV_SIGVALIDCLK 03_13 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ZINV_TXPHDLYTSTCLK 02_03 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ZINV_TXUSRCLK 03_04 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ZINV_CLKRSVD0 02_23 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ZINV_CLKRSVD1 03_23 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ZINV_RXUSRCLK2 02_02 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ZINV_TXUSRCLK2 02_05 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ACJTAG_DEBUG_MODE[0] 00_07 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ACJTAG_MODE[0] 01_06 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ACJTAG_RESET[0] 01_07 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[0] 02_464 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[1] 03_464 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[2] 02_465 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[3] 03_465 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[4] 02_466 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[5] 03_466 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[6] 02_467 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[7] 03_467 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[8] 02_468 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[9] 03_468 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[10] 02_469 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[11] 03_469 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[12] 02_470 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[13] 03_470 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[14] 02_471 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[15] 03_471 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[16] 02_472 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[17] 03_472 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[18] 02_473 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[19] 03_473 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ALIGN_COMMA_DOUBLE 00_522 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[0] 00_496 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[1] 01_496 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[2] 00_497 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[3] 01_497 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[4] 00_498 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[5] 01_498 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[6] 00_499 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[7] 01_499 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[8] 00_500 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[9] 01_500 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ALIGN_COMMA_WORD[0] 01_526 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ALIGN_COMMA_WORD[1] 00_527 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ALIGN_MCOMMA_DET 00_523 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[0] 00_504 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[1] 01_504 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[2] 00_505 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[3] 01_505 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[4] 00_506 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[5] 01_506 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[6] 00_507 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[7] 01_507 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[8] 00_508 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[9] 01_508 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ALIGN_PCOMMA_DET 01_523 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[0] 00_512 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[1] 01_512 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[2] 00_513 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[3] 01_513 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[4] 00_514 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[5] 01_514 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[6] 00_515 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[7] 01_515 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[8] 00_516 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[9] 01_516 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CBCC_DATA_SOURCE_SEL.DECODED 01_661 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[0] 02_392 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[1] 03_392 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[2] 02_393 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[3] 03_393 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[4] 02_394 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[5] 03_394 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[6] 02_395 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[7] 03_395 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[8] 02_396 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[9] 03_396 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[10] 02_397 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[11] 03_397 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[12] 02_398 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[13] 03_398 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[14] 02_399 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[15] 03_399 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[16] 02_400 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[17] 03_400 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[18] 02_401 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[19] 03_401 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[20] 02_402 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[21] 03_402 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[22] 02_403 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[23] 03_403 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[24] 02_404 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[25] 03_404 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[26] 02_405 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[27] 03_405 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[28] 02_406 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[29] 03_406 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[30] 02_407 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[31] 03_407 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[32] 02_408 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[33] 03_408 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[34] 02_409 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[35] 03_409 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[36] 02_410 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[37] 03_410 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[38] 02_411 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[39] 03_411 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[40] 02_412 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[41] 03_412 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[42] 02_413 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG2[0] 02_459 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG2[1] 03_459 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG2[2] 02_460 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG2[3] 03_460 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG2[4] 02_461 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG2[5] 03_461 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG2[6] 02_462 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG3[0] 02_416 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG3[1] 03_416 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG3[2] 02_417 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG3[3] 03_417 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG3[4] 02_418 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG3[5] 03_418 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG3[6] 02_419 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG4[0] 03_438 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG5[0] 02_429 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG5[1] 03_429 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG6[0] 03_436 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG6[1] 02_437 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG6[2] 03_437 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG6[3] 02_438 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_KEEP_ALIGN 01_631 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_MAX_SKEW[0] 00_670 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_MAX_SKEW[1] 01_670 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_MAX_SKEW[2] 00_671 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_MAX_SKEW[3] 01_671 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[0] 00_608 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[1] 01_608 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[2] 00_609 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[3] 01_609 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[4] 00_610 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[5] 01_610 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[6] 00_611 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[7] 01_611 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[8] 00_612 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[9] 01_612 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[0] 00_616 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[1] 01_616 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[2] 00_617 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[3] 01_617 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[4] 00_618 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[5] 01_618 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[6] 00_619 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[7] 01_619 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[8] 00_620 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[9] 01_620 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[0] 00_624 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[1] 01_624 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[2] 00_625 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[3] 01_625 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[4] 00_626 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[5] 01_626 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[6] 00_627 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[7] 01_627 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[8] 00_628 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[9] 01_628 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[0] 00_632 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[1] 01_632 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[2] 00_633 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[3] 01_633 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[4] 00_634 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[5] 01_634 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[6] 00_635 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[7] 01_635 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[8] 00_636 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[9] 01_636 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_ENABLE[0] 00_614 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_ENABLE[1] 01_614 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_ENABLE[2] 00_615 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_ENABLE[3] 01_615 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[0] 00_640 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[1] 01_640 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[2] 00_641 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[3] 01_641 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[4] 00_642 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[5] 01_642 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[6] 00_643 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[7] 01_643 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[8] 00_644 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[9] 01_644 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[0] 00_648 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[1] 01_648 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[2] 00_649 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[3] 01_649 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[4] 00_650 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[5] 01_650 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[6] 00_651 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[7] 01_651 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[8] 00_652 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[9] 01_652 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[0] 00_656 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[1] 01_656 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[2] 00_657 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[3] 01_657 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[4] 00_658 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[5] 01_658 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[6] 00_659 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[7] 01_659 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[8] 00_660 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[9] 01_660 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[0] 00_664 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[1] 01_664 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[2] 00_665 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[3] 01_665 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[4] 00_666 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[5] 01_666 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[6] 00_667 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[7] 01_667 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[8] 00_668 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[9] 01_668 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_ENABLE[0] 00_646 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_ENABLE[1] 01_646 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_ENABLE[2] 00_647 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_ENABLE[3] 01_647 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_USE 01_645 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_LEN[0] 00_623 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_LEN[1] 01_623 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COMMON_SWING[0] 03_311 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_KEEP_IDLE 00_591 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_MAX_LAT[0] 00_557 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_MAX_LAT[1] 01_557 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_MAX_LAT[2] 00_558 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_MAX_LAT[3] 01_558 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_MAX_LAT[4] 00_559 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_MAX_LAT[5] 01_559 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_MIN_LAT[0] 00_565 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_MIN_LAT[1] 01_565 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_MIN_LAT[2] 00_566 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_MIN_LAT[3] 01_566 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_MIN_LAT[4] 00_567 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_MIN_LAT[5] 01_567 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_PRECEDENCE 00_590 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_REPEAT_WAIT[0] 00_573 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_REPEAT_WAIT[1] 01_573 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_REPEAT_WAIT[2] 00_574 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_REPEAT_WAIT[3] 01_574 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_REPEAT_WAIT[4] 00_575 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[0] 00_544 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[1] 01_544 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[2] 00_545 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[3] 01_545 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[4] 00_546 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[5] 01_546 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[6] 00_547 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[7] 01_547 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[8] 00_548 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[9] 01_548 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[0] 00_552 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[1] 01_552 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[2] 00_553 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[3] 01_553 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[4] 00_554 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[5] 01_554 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[6] 00_555 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[7] 01_555 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[8] 00_556 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[9] 01_556 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[0] 00_560 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[1] 01_560 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[2] 00_561 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[3] 01_561 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[4] 00_562 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[5] 01_562 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[6] 00_563 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[7] 01_563 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[8] 00_564 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[9] 01_564 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[0] 00_568 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[1] 01_568 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[2] 00_569 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[3] 01_569 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[4] 00_570 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[5] 01_570 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[6] 00_571 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[7] 01_571 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[8] 00_572 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[9] 01_572 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_ENABLE[0] 00_549 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_ENABLE[1] 01_549 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_ENABLE[2] 00_550 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_ENABLE[3] 01_550 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[0] 00_576 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[1] 01_576 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[2] 00_577 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[3] 01_577 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[4] 00_578 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[5] 01_578 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[6] 00_579 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[7] 01_579 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[8] 00_580 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[9] 01_580 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[0] 00_584 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[1] 01_584 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[2] 00_585 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[3] 01_585 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[4] 00_586 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[5] 01_586 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[6] 00_587 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[7] 01_587 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[8] 00_588 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[9] 01_588 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[0] 00_592 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[1] 01_592 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[2] 00_593 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[3] 01_593 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[4] 00_594 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[5] 01_594 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[6] 00_595 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[7] 01_595 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[8] 00_596 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[9] 01_596 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[0] 00_600 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[1] 01_600 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[2] 00_601 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[3] 01_601 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[4] 00_602 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[5] 01_602 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[6] 00_603 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[7] 01_603 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[8] 00_604 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[9] 01_604 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_ENABLE[0] 00_581 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_ENABLE[1] 01_581 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_ENABLE[2] 00_582 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_ENABLE[3] 01_582 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_USE 00_583 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_LEN[0] 00_589 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_LEN[1] 01_589 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_CORRECT_USE 00_551 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.DEC_MCOMMA_DETECT 01_494 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.DEC_PCOMMA_DETECT 00_495 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.DEC_VALID_COMMA_ONLY 00_494 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[0] 02_368 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[1] 03_368 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[2] 02_369 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[3] 03_369 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[4] 02_370 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[5] 03_370 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[6] 02_371 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[7] 03_371 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[8] 02_372 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[9] 03_372 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[10] 02_373 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[11] 03_373 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[12] 02_374 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[13] 03_374 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[14] 02_375 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[15] 03_375 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[16] 02_376 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[17] 03_376 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[18] 02_377 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[19] 03_377 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[20] 02_378 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[21] 03_378 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[22] 02_379 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[23] 03_379 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_CLK_PHASE_SEL[0] 03_463 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_CONTROL[0] 00_488 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_CONTROL[1] 01_488 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_CONTROL[2] 00_489 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_CONTROL[3] 01_489 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_CONTROL[4] 00_490 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_CONTROL[5] 01_490 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_ERRDET_EN 01_492 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_EYE_SCAN_EN 00_492 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_HORZ_OFFSET[0] 00_480 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_HORZ_OFFSET[1] 01_480 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_HORZ_OFFSET[2] 00_481 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_HORZ_OFFSET[3] 01_481 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_HORZ_OFFSET[4] 00_482 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_HORZ_OFFSET[5] 01_482 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_HORZ_OFFSET[6] 00_483 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_HORZ_OFFSET[7] 01_483 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_HORZ_OFFSET[8] 00_484 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_HORZ_OFFSET[9] 01_484 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_HORZ_OFFSET[10] 00_485 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_HORZ_OFFSET[11] 01_485 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_PMA_CFG[0] 02_624 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_PMA_CFG[1] 03_624 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_PMA_CFG[2] 02_625 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_PMA_CFG[3] 03_625 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_PMA_CFG[4] 02_626 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_PMA_CFG[5] 03_626 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_PMA_CFG[6] 02_627 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_PMA_CFG[7] 03_627 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_PMA_CFG[8] 02_628 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_PMA_CFG[9] 03_628 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_PRESCALE[0] 01_477 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_PRESCALE[1] 00_478 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_PRESCALE[2] 01_478 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_PRESCALE[3] 00_479 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_PRESCALE[4] 01_479 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[0] 00_392 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[1] 01_392 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[2] 00_393 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[3] 01_393 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[4] 00_394 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[5] 01_394 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[6] 00_395 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[7] 01_395 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[8] 00_396 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[9] 01_396 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[10] 00_397 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[11] 01_397 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[12] 00_398 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[13] 01_398 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[14] 00_399 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[15] 01_399 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[16] 00_400 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[17] 01_400 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[18] 00_401 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[19] 01_401 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[20] 00_402 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[21] 01_402 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[22] 00_403 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[23] 01_403 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[24] 00_404 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[25] 01_404 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[26] 00_405 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[27] 01_405 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[28] 00_406 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[29] 01_406 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[30] 00_407 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[31] 01_407 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[32] 00_408 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[33] 01_408 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[34] 00_409 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[35] 01_409 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[36] 00_410 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[37] 01_410 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[38] 00_411 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[39] 01_411 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[40] 00_412 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[41] 01_412 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[42] 00_413 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[43] 01_413 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[44] 00_414 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[45] 01_414 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[46] 00_415 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[47] 01_415 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[48] 00_416 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[49] 01_416 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[50] 00_417 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[51] 01_417 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[52] 00_418 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[53] 01_418 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[54] 00_419 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[55] 01_419 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[56] 00_420 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[57] 01_420 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[58] 00_421 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[59] 01_421 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[60] 00_422 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[61] 01_422 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[62] 00_423 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[63] 01_423 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[64] 00_424 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[65] 01_424 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[66] 00_425 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[67] 01_425 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[68] 00_426 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[69] 01_426 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[70] 00_427 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[71] 01_427 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[72] 00_428 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[73] 01_428 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[74] 00_429 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[75] 01_429 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[76] 00_430 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[77] 01_430 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[78] 00_431 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[79] 01_431 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[0] 00_352 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[1] 01_352 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[2] 00_353 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[3] 01_353 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[4] 00_354 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[5] 01_354 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[6] 00_355 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[7] 01_355 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[8] 00_356 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[9] 01_356 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[10] 00_357 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[11] 01_357 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[12] 00_358 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[13] 01_358 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[14] 00_359 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[15] 01_359 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[16] 00_360 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[17] 01_360 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[18] 00_361 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[19] 01_361 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[20] 00_362 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[21] 01_362 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[22] 00_363 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[23] 01_363 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[24] 00_364 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[25] 01_364 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[26] 00_365 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[27] 01_365 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[28] 00_366 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[29] 01_366 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[30] 00_367 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[31] 01_367 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[32] 00_368 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[33] 01_368 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[34] 00_369 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[35] 01_369 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[36] 00_370 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[37] 01_370 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[38] 00_371 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[39] 01_371 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[40] 00_372 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[41] 01_372 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[42] 00_373 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[43] 01_373 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[44] 00_374 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[45] 01_374 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[46] 00_375 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[47] 01_375 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[48] 00_376 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[49] 01_376 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[50] 00_377 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[51] 01_377 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[52] 00_378 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[53] 01_378 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[54] 00_379 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[55] 01_379 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[56] 00_380 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[57] 01_380 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[58] 00_381 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[59] 01_381 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[60] 00_382 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[61] 01_382 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[62] 00_383 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[63] 01_383 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[64] 00_384 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[65] 01_384 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[66] 00_385 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[67] 01_385 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[68] 00_386 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[69] 01_386 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[70] 00_387 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[71] 01_387 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[72] 00_388 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[73] 01_388 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[74] 00_389 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[75] 01_389 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[76] 00_390 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[77] 01_390 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[78] 00_391 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[79] 01_391 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[0] 00_432 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[1] 01_432 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[2] 00_433 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[3] 01_433 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[4] 00_434 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[5] 01_434 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[6] 00_435 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[7] 01_435 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[8] 00_436 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[9] 01_436 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[10] 00_437 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[11] 01_437 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[12] 00_438 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[13] 01_438 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[14] 00_439 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[15] 01_439 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[16] 00_440 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[17] 01_440 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[18] 00_441 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[19] 01_441 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[20] 00_442 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[21] 01_442 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[22] 00_443 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[23] 01_443 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[24] 00_444 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[25] 01_444 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[26] 00_445 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[27] 01_445 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[28] 00_446 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[29] 01_446 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[30] 00_447 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[31] 01_447 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[32] 00_448 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[33] 01_448 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[34] 00_449 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[35] 01_449 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[36] 00_450 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[37] 01_450 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[38] 00_451 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[39] 01_451 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[40] 00_452 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[41] 01_452 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[42] 00_453 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[43] 01_453 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[44] 00_454 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[45] 01_454 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[46] 00_455 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[47] 01_455 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[48] 00_456 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[49] 01_456 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[50] 00_457 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[51] 01_457 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[52] 00_458 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[53] 01_458 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[54] 00_459 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[55] 01_459 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[56] 00_460 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[57] 01_460 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[58] 00_461 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[59] 01_461 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[60] 00_462 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[61] 01_462 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[62] 00_463 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[63] 01_463 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[64] 00_464 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[65] 01_464 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[66] 00_465 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[67] 01_465 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[68] 00_466 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[69] 01_466 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[70] 00_467 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[71] 01_467 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[72] 00_468 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[73] 01_468 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[74] 00_469 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[75] 01_469 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[76] 00_470 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[77] 01_470 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[78] 00_471 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[79] 01_471 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_VERT_OFFSET[0] 00_472 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_VERT_OFFSET[1] 01_472 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_VERT_OFFSET[2] 00_473 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_VERT_OFFSET[3] 01_473 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_VERT_OFFSET[4] 00_474 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_VERT_OFFSET[5] 01_474 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_VERT_OFFSET[6] 00_475 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_VERT_OFFSET[7] 01_475 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_VERT_OFFSET[8] 00_476 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.FTS_DESKEW_SEQ_ENABLE[0] 00_662 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.FTS_DESKEW_SEQ_ENABLE[1] 01_662 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.FTS_DESKEW_SEQ_ENABLE[2] 00_663 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.FTS_DESKEW_SEQ_ENABLE[3] 01_663 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.FTS_LANE_DESKEW_CFG[0] 00_654 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.FTS_LANE_DESKEW_CFG[1] 01_654 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.FTS_LANE_DESKEW_CFG[2] 00_655 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.FTS_LANE_DESKEW_CFG[3] 01_655 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.FTS_LANE_DESKEW_EN 01_653 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.GEARBOX_MODE[0] 00_224 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.GEARBOX_MODE[1] 01_224 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.GEARBOX_MODE[2] 00_225 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.IN_USE 00_00 00_01 00_47 00_52 00_53 00_65 01_01 01_47 02_129 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.INV_DMONITORCLK 02_13 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.INV_DRPCLK 02_00 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.INV_RXUSRCLK 03_01 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.INV_SIGVALIDCLK 03_13 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.INV_TXPHDLYTSTCLK 02_03 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.INV_TXUSRCLK 03_04 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.INV_CLKRSVD0 02_23 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.INV_CLKRSVD1 03_23 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.INV_RXUSRCLK2 02_02 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.INV_TXUSRCLK2 02_05 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.LOOPBACK_CFG[0] 02_20 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.OUTREFCLK_SEL_INV[0] 00_149 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.OUTREFCLK_SEL_INV[1] 01_149 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PCS_PCIE_EN 00_216 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[0] 02_184 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[1] 03_184 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[2] 02_185 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[3] 03_185 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[4] 02_186 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[5] 03_186 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[6] 02_187 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[7] 03_187 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[8] 02_188 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[9] 03_188 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[10] 02_189 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[11] 03_189 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[12] 02_190 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[13] 03_190 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[14] 02_191 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[15] 03_191 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[16] 02_192 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[17] 03_192 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[18] 02_193 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[19] 03_193 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[20] 02_194 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[21] 03_194 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[22] 02_195 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[23] 03_195 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[24] 02_196 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[25] 03_196 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[26] 02_197 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[27] 03_197 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[28] 02_198 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[29] 03_198 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[30] 02_199 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[31] 03_199 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[32] 02_200 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[33] 03_200 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[34] 02_201 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[35] 03_201 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[36] 02_202 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[37] 03_202 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[38] 02_203 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[39] 03_203 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[40] 02_204 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[41] 03_204 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[42] 02_205 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[43] 03_205 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[44] 02_206 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[45] 03_206 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[46] 02_207 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[47] 03_207 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[0] 01_216 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[1] 00_217 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[2] 01_217 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[3] 00_218 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[4] 01_218 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[5] 00_219 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[6] 01_219 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[7] 00_220 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[8] 01_220 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[9] 00_221 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[10] 01_221 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[11] 00_222 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[0] 00_208 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[1] 01_208 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[2] 00_209 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[3] 01_209 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[4] 00_210 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[5] 01_210 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[6] 00_211 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[7] 01_211 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[0] 00_212 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[1] 01_212 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[2] 00_213 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[3] 01_213 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[4] 00_214 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[5] 01_214 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[6] 00_215 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[7] 01_215 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PMA_LOOPBACK_CFG[0] 01_207 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[0] 02_520 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[1] 03_520 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[2] 02_521 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[3] 03_521 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[4] 02_522 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[5] 03_522 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[6] 02_523 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[7] 03_523 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[8] 02_524 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[9] 03_524 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[10] 02_525 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[11] 03_525 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[12] 02_526 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[13] 03_526 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[14] 02_527 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[15] 03_527 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[16] 02_528 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[17] 03_528 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[18] 02_529 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[19] 03_529 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[20] 02_530 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[21] 03_530 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[22] 02_531 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[23] 03_531 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[24] 02_532 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[25] 03_532 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[26] 02_533 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[27] 03_533 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[28] 02_534 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[29] 03_534 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[30] 02_535 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[31] 03_535 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[0] 02_336 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[1] 03_336 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[2] 02_337 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[3] 03_337 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[4] 02_338 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[5] 03_338 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[6] 02_339 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[7] 03_339 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[8] 02_340 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[9] 03_340 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[10] 02_341 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[11] 03_341 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[12] 02_342 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[13] 03_342 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[14] 02_343 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[15] 03_343 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[16] 02_344 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[17] 03_344 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[18] 02_345 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[19] 03_345 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[20] 02_346 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[21] 03_346 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[22] 02_347 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[23] 03_347 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[24] 02_348 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[25] 03_348 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[26] 02_349 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[27] 03_349 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[28] 02_350 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[29] 03_350 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[30] 02_351 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[31] 03_351 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PMA_RSV3[0] 02_288 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PMA_RSV3[1] 03_288 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PMA_RSV4[0] 02_156 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PMA_RSV4[1] 03_156 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PMA_RSV4[2] 02_157 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PMA_RSV4[3] 03_157 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PMA_RSV5[0] 03_159 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PMA_RSV6[0] 02_303 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PMA_RSV7[0] 03_303 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_BIAS_CFG[0] 02_112 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_BIAS_CFG[1] 03_112 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_BIAS_CFG[2] 02_113 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_BIAS_CFG[3] 03_113 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_BIAS_CFG[4] 02_114 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_BIAS_CFG[5] 03_114 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_BIAS_CFG[6] 02_115 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_BIAS_CFG[7] 03_115 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_BIAS_CFG[8] 02_116 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_BIAS_CFG[9] 03_116 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_BIAS_CFG[10] 02_117 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_BIAS_CFG[11] 03_117 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_BIAS_CFG[12] 02_118 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_BIAS_CFG[13] 03_118 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_BIAS_CFG[14] 02_119 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_BIAS_CFG[15] 03_119 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_BUFFER_CFG[0] 02_536 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_BUFFER_CFG[1] 03_536 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_BUFFER_CFG[2] 02_537 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_BUFFER_CFG[3] 03_537 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_BUFFER_CFG[4] 02_538 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_BUFFER_CFG[5] 03_538 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_CLKMUX_EN[0] 02_128 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_CM_SEL[0] 00_138 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_CM_SEL[1] 01_138 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_CM_TRIM[0] 02_304 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_CM_TRIM[1] 03_304 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_CM_TRIM[2] 02_305 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_CM_TRIM[3] 03_305 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_DATA_WIDTH[0] 01_141 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_DATA_WIDTH[1] 00_142 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_DATA_WIDTH[2] 01_142 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_DDI_SEL[0] 00_696 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_DDI_SEL[1] 01_696 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_DDI_SEL[2] 00_697 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_DDI_SEL[3] 01_697 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_DDI_SEL[4] 00_698 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_DDI_SEL[5] 01_698 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_DEBUG_CFG[0] 02_616 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_DEBUG_CFG[1] 03_616 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_DEBUG_CFG[2] 02_617 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_DEBUG_CFG[3] 03_617 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_DEBUG_CFG[4] 02_618 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_DEBUG_CFG[5] 03_618 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_DEBUG_CFG[6] 02_619 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_DEBUG_CFG[7] 03_619 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_DEBUG_CFG[8] 02_620 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_DEBUG_CFG[9] 03_620 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_DEBUG_CFG[10] 02_621 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_DEBUG_CFG[11] 03_621 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_DEBUG_CFG[12] 02_622 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_DEBUG_CFG[13] 03_622 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_DEFER_RESET_BUF_EN 02_552 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_DISPERR_SEQ_MATCH 01_495 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_OS_CFG[0] 00_288 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_OS_CFG[1] 01_288 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_OS_CFG[2] 00_289 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_OS_CFG[3] 01_289 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_OS_CFG[4] 00_290 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_OS_CFG[5] 01_290 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_OS_CFG[6] 00_291 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_OS_CFG[7] 01_291 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_OS_CFG[8] 00_292 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_OS_CFG[9] 01_292 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_OS_CFG[10] 00_293 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_OS_CFG[11] 01_293 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_OS_CFG[12] 00_294 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_SIG_VALID_DLY[0] 00_524 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_SIG_VALID_DLY[1] 01_524 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_SIG_VALID_DLY[2] 00_525 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_SIG_VALID_DLY[3] 01_525 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_SIG_VALID_DLY[4] 00_526 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_XCLK_SEL.RXUSR 00_143 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_CLK25_DIV[0] 00_139 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_CLK25_DIV[1] 01_139 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_CLK25_DIV[2] 00_140 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_CLK25_DIV[3] 01_140 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_CLK25_DIV[4] 00_141 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXBUF_ADDR_MODE.FAST 03_555 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXBUF_EIDLE_HI_CNT[0] 02_558 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXBUF_EIDLE_HI_CNT[1] 03_558 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXBUF_EIDLE_HI_CNT[2] 02_559 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXBUF_EIDLE_HI_CNT[3] 03_559 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXBUF_EIDLE_LO_CNT[0] 02_556 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXBUF_EIDLE_LO_CNT[1] 03_556 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXBUF_EIDLE_LO_CNT[2] 02_557 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXBUF_EIDLE_LO_CNT[3] 03_557 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXBUF_EN 02_11 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXBUF_RESET_ON_CB_CHANGE 02_560 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXBUF_RESET_ON_COMMAALIGN 02_561 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXBUF_RESET_ON_EIDLE 02_547 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXBUF_RESET_ON_RATE_CHANGE 03_560 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXBUF_THRESH_OVFLW[0] 03_552 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXBUF_THRESH_OVFLW[1] 02_553 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXBUF_THRESH_OVFLW[2] 03_553 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXBUF_THRESH_OVFLW[3] 02_554 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXBUF_THRESH_OVFLW[4] 03_554 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXBUF_THRESH_OVFLW[5] 02_555 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXBUF_THRESH_OVRD 02_548 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXBUF_THRESH_UNDFLW[0] 02_544 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXBUF_THRESH_UNDFLW[1] 03_544 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXBUF_THRESH_UNDFLW[2] 02_545 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXBUF_THRESH_UNDFLW[3] 03_545 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXBUF_THRESH_UNDFLW[4] 02_546 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXBUF_THRESH_UNDFLW[5] 03_546 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXBUFRESET_TIME[0] 01_101 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXBUFRESET_TIME[1] 00_102 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXBUFRESET_TIME[2] 01_102 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXBUFRESET_TIME[3] 00_103 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXBUFRESET_TIME[4] 01_103 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[0] 02_640 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[1] 03_640 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[2] 02_641 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[3] 03_641 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[4] 02_642 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[5] 03_642 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[6] 02_643 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[7] 03_643 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[8] 02_644 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[9] 03_644 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[10] 02_645 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[11] 03_645 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[12] 02_646 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[13] 03_646 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[14] 02_647 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[15] 03_647 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[16] 02_648 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[17] 03_648 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[18] 02_649 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[19] 03_649 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[20] 02_650 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[21] 03_650 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[22] 02_651 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[23] 03_651 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[24] 02_652 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[25] 03_652 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[26] 02_653 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[27] 03_653 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[28] 02_654 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[29] 03_654 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[30] 02_655 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[31] 03_655 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[32] 02_656 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[33] 03_656 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[34] 02_657 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[35] 03_657 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[36] 02_658 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[37] 03_658 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[38] 02_659 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[39] 03_659 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[40] 02_660 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[41] 03_660 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[42] 02_661 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[43] 03_661 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[44] 02_662 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[45] 03_662 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[46] 02_663 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[47] 03_663 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[48] 02_664 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[49] 03_664 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[50] 02_665 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[51] 03_665 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[52] 02_666 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[53] 03_666 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[54] 02_667 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[55] 03_667 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[56] 02_668 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[57] 03_668 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[58] 02_669 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[59] 03_669 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[60] 02_670 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[61] 03_670 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[62] 02_671 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[63] 03_671 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[64] 02_672 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[65] 03_672 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[66] 02_673 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[67] 03_673 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[68] 02_674 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[69] 03_674 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[70] 02_675 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[71] 03_675 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[72] 02_676 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[73] 03_676 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[74] 02_677 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[75] 03_677 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[76] 02_678 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[77] 03_678 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[78] 02_679 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[79] 03_679 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[80] 02_680 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[81] 03_680 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[82] 02_681 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_FR_RESET_ON_EIDLE[0] 02_638 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_HOLD_DURING_EIDLE[0] 03_637 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_LOCK_CFG[0] 02_632 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_LOCK_CFG[1] 03_632 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_LOCK_CFG[2] 02_633 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_LOCK_CFG[3] 03_633 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_LOCK_CFG[4] 02_634 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_LOCK_CFG[5] 03_634 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_PH_RESET_ON_EIDLE[0] 03_638 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDRFREQRESET_TIME[0] 01_106 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDRFREQRESET_TIME[1] 00_107 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDRFREQRESET_TIME[2] 01_107 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDRFREQRESET_TIME[3] 00_108 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDRFREQRESET_TIME[4] 01_108 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDRPHRESET_TIME[0] 00_109 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDRPHRESET_TIME[1] 01_109 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDRPHRESET_TIME[2] 00_110 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDRPHRESET_TIME[3] 01_110 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDRPHRESET_TIME[4] 00_111 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXDLY_CFG[0] 00_680 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXDLY_CFG[1] 01_680 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXDLY_CFG[2] 00_681 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXDLY_CFG[3] 01_681 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXDLY_CFG[4] 00_682 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXDLY_CFG[5] 01_682 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXDLY_CFG[6] 00_683 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXDLY_CFG[7] 01_683 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXDLY_CFG[8] 00_684 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXDLY_CFG[9] 01_684 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXDLY_CFG[10] 00_685 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXDLY_CFG[11] 01_685 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXDLY_CFG[12] 00_686 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXDLY_CFG[13] 01_686 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXDLY_CFG[14] 00_687 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXDLY_CFG[15] 01_687 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXDLY_LCFG[0] 02_576 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXDLY_LCFG[1] 03_576 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXDLY_LCFG[2] 02_577 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXDLY_LCFG[3] 03_577 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXDLY_LCFG[4] 02_578 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXDLY_LCFG[5] 03_578 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXDLY_LCFG[6] 02_579 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXDLY_LCFG[7] 03_579 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXDLY_LCFG[8] 02_580 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXDLY_TAP_CFG[0] 00_672 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXDLY_TAP_CFG[1] 01_672 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXDLY_TAP_CFG[2] 00_673 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXDLY_TAP_CFG[3] 01_673 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXDLY_TAP_CFG[4] 00_674 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXDLY_TAP_CFG[5] 01_674 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXDLY_TAP_CFG[6] 00_675 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXDLY_TAP_CFG[7] 01_675 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXDLY_TAP_CFG[8] 00_676 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXDLY_TAP_CFG[9] 01_676 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXDLY_TAP_CFG[10] 00_677 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXDLY_TAP_CFG[11] 01_677 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXDLY_TAP_CFG[12] 00_678 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXDLY_TAP_CFG[13] 01_678 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXDLY_TAP_CFG[14] 00_679 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXDLY_TAP_CFG[15] 01_679 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXGEARBOX_EN 01_607 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXISCANRESET_TIME[0] 01_123 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXISCANRESET_TIME[1] 00_124 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXISCANRESET_TIME[2] 01_124 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXISCANRESET_TIME[3] 00_125 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXISCANRESET_TIME[4] 01_125 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPM_BIAS_STARTUP_DISABLE[0] 03_391 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPM_CFG[0] 02_328 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPM_CFG[1] 03_328 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPM_CFG[2] 02_329 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPM_CFG[3] 03_329 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPM_CM_CFG[0] 02_430 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPM_GC_CFG[0] 02_432 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPM_GC_CFG[1] 03_432 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPM_GC_CFG[2] 02_433 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPM_GC_CFG[3] 03_433 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPM_GC_CFG[4] 02_434 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPM_GC_CFG[5] 03_434 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPM_GC_CFG[6] 02_435 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPM_GC_CFG[7] 03_435 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPM_GC_CFG[8] 02_436 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPM_GC_CFG2[0] 03_442 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPM_GC_CFG2[1] 02_443 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPM_GC_CFG2[2] 03_443 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG[0] 00_336 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG[1] 01_336 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG[2] 00_337 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG[3] 01_337 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG[4] 00_338 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG[5] 01_338 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG[6] 00_339 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG[7] 01_339 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG[8] 00_340 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG[9] 01_340 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG[10] 00_341 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG[11] 01_341 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG[12] 00_342 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG[13] 01_342 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG2[0] 02_424 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG2[1] 03_424 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG2[2] 02_425 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG2[3] 03_425 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG2[4] 02_426 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG3[0] 03_389 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG3[1] 02_390 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG3[2] 03_390 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG3[3] 02_391 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPM_HOLD_DURING_EIDLE[0] 00_247 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPM_INCM_CFG[0] 02_439 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPM_IPCM_CFG[0] 03_439 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG[0] 00_344 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG[1] 01_344 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG[2] 00_345 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG[3] 01_345 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG[4] 00_346 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG[5] 01_346 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG[6] 00_347 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG[7] 01_347 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG[8] 00_348 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG[9] 01_348 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG[10] 00_349 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG[11] 01_349 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG[12] 00_350 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG[13] 01_350 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG[14] 00_351 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG[15] 01_351 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG[16] 00_343 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG[17] 01_343 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG2[0] 03_426 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG2[1] 02_427 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG2[2] 03_427 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG2[3] 02_428 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG2[4] 03_428 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPM_OSINT_CFG[0] 02_440 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPM_OSINT_CFG[1] 03_440 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPM_OSINT_CFG[2] 02_441 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPM_CFG1[0] 02_330 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPMRESET_TIME[0] 00_112 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPMRESET_TIME[1] 01_112 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPMRESET_TIME[2] 00_113 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPMRESET_TIME[3] 01_113 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPMRESET_TIME[4] 00_114 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPMRESET_TIME[5] 01_114 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPMRESET_TIME[6] 00_115 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXOOB_CFG[0] 00_144 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXOOB_CFG[1] 01_144 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXOOB_CFG[2] 00_145 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXOOB_CFG[3] 01_145 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXOOB_CFG[4] 00_146 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXOOB_CFG[5] 01_146 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXOOB_CFG[6] 00_147 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXOOB_CLK_CFG.FABRIC 03_129 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXOSCALRESET_TIME[0] 00_187 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXOSCALRESET_TIME[1] 01_187 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXOSCALRESET_TIME[2] 00_188 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXOSCALRESET_TIME[3] 01_188 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXOSCALRESET_TIME[4] 00_189 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXOSCALRESET_TIMEOUT[0] 01_189 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXOSCALRESET_TIMEOUT[1] 00_190 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXOSCALRESET_TIMEOUT[2] 01_190 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXOSCALRESET_TIMEOUT[3] 00_191 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXOSCALRESET_TIMEOUT[4] 01_191 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXOUT_DIV[0] 02_384 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXOUT_DIV[1] 03_384 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXPCSRESET_TIME[0] 01_115 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXPCSRESET_TIME[1] 00_116 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXPCSRESET_TIME[2] 01_116 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXPCSRESET_TIME[3] 00_117 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXPCSRESET_TIME[4] 01_117 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[0] 02_584 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[1] 03_584 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[2] 02_585 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[3] 03_585 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[4] 02_586 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[5] 03_586 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[6] 02_587 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[7] 03_587 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[8] 02_588 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[9] 03_588 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[10] 02_589 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[11] 03_589 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[12] 02_590 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[13] 03_590 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[14] 02_591 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[15] 03_591 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[16] 02_592 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[17] 03_592 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[18] 02_593 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[19] 03_593 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[20] 02_594 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[21] 03_594 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[22] 02_595 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[23] 03_595 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXPH_MONITOR_SEL[0] 00_700 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXPH_MONITOR_SEL[1] 01_700 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXPH_MONITOR_SEL[2] 00_701 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXPH_MONITOR_SEL[3] 01_701 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXPH_MONITOR_SEL[4] 00_702 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[0] 02_600 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[1] 03_600 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[2] 02_601 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[3] 03_601 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[4] 02_602 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[5] 03_602 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[6] 02_603 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[7] 03_603 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[8] 02_604 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[9] 03_604 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[10] 02_605 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[11] 03_605 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[12] 02_606 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[13] 03_606 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[14] 02_607 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[15] 03_607 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[16] 02_608 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[17] 03_608 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[18] 02_609 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[19] 03_609 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[20] 02_610 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[21] 03_610 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[22] 02_611 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[23] 03_611 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXPI_CFG0[0] 03_430 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXPI_CFG0[1] 02_431 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXPI_CFG0[2] 03_431 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXPI_CFG1[0] 02_442 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXPI_CFG2[0] 03_441 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXPMARESET_TIME[0] 00_104 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXPMARESET_TIME[1] 01_104 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXPMARESET_TIME[2] 00_105 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXPMARESET_TIME[3] 01_105 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXPMARESET_TIME[4] 00_106 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXPRBS_ERR_LOOPBACK[0] 00_136 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXSLIDE_AUTO_WAIT[0] 00_520 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXSLIDE_AUTO_WAIT[1] 01_520 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXSLIDE_AUTO_WAIT[2] 00_521 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXSLIDE_AUTO_WAIT[3] 01_521 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXSLIDE_MODE.AUTO 00_519 !01_519 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXSLIDE_MODE.PCS !00_519 01_519 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXSLIDE_MODE.PMA 00_519 01_519 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXSYNC_MULTILANE[0] 00_133 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXSYNC_OVRD[0] 01_135 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXSYNC_SKIP_DA[0] 01_134 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.SAS_MAX_COM[0] 00_171 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.SAS_MAX_COM[1] 01_171 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.SAS_MAX_COM[2] 00_172 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.SAS_MAX_COM[3] 01_172 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.SAS_MAX_COM[4] 00_173 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.SAS_MAX_COM[5] 01_173 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.SAS_MAX_COM[6] 00_174 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.SAS_MIN_COM[0] 01_156 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.SAS_MIN_COM[1] 00_157 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.SAS_MIN_COM[2] 01_157 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.SAS_MIN_COM[3] 00_158 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.SAS_MIN_COM[4] 01_158 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.SAS_MIN_COM[5] 00_159 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.SATA_BURST_SEQ_LEN[0] 00_150 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.SATA_BURST_SEQ_LEN[1] 01_150 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.SATA_BURST_SEQ_LEN[2] 00_151 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.SATA_BURST_SEQ_LEN[3] 01_151 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.SATA_BURST_VAL[0] 01_147 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.SATA_BURST_VAL[1] 00_148 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.SATA_BURST_VAL[2] 01_148 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.SATA_EIDLE_VAL[0] 00_152 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.SATA_EIDLE_VAL[1] 01_152 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.SATA_EIDLE_VAL[2] 00_153 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.SATA_MAX_BURST[0] 00_168 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.SATA_MAX_BURST[1] 01_168 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.SATA_MAX_BURST[2] 00_169 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.SATA_MAX_BURST[3] 01_169 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.SATA_MAX_BURST[4] 00_170 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.SATA_MAX_BURST[5] 01_170 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.SATA_MAX_INIT[0] 00_176 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.SATA_MAX_INIT[1] 01_176 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.SATA_MAX_INIT[2] 00_177 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.SATA_MAX_INIT[3] 01_177 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.SATA_MAX_INIT[4] 00_178 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.SATA_MAX_INIT[5] 01_178 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.SATA_MAX_WAKE[0] 00_179 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.SATA_MAX_WAKE[1] 01_179 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.SATA_MAX_WAKE[2] 00_180 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.SATA_MAX_WAKE[3] 01_180 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.SATA_MAX_WAKE[4] 00_181 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.SATA_MAX_WAKE[5] 01_181 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.SATA_MIN_BURST[0] 01_153 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.SATA_MIN_BURST[1] 00_154 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.SATA_MIN_BURST[2] 01_154 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.SATA_MIN_BURST[3] 00_155 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.SATA_MIN_BURST[4] 01_155 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.SATA_MIN_BURST[5] 00_156 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.SATA_MIN_INIT[0] 00_160 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.SATA_MIN_INIT[1] 01_160 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.SATA_MIN_INIT[2] 00_161 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.SATA_MIN_INIT[3] 01_161 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.SATA_MIN_INIT[4] 00_162 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.SATA_MIN_INIT[5] 01_162 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.SATA_MIN_WAKE[0] 00_163 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.SATA_MIN_WAKE[1] 01_163 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.SATA_MIN_WAKE[2] 00_164 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.SATA_MIN_WAKE[3] 01_164 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.SATA_MIN_WAKE[4] 00_165 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.SATA_MIN_WAKE[5] 01_165 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.SATA_PLL_CFG.VCO_1500MHZ 02_55 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.SATA_PLL_CFG.VCO_750MHZ 03_55 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.SHOW_REALIGN_COMMA 01_522 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TERM_RCAL_CFG[0] 02_136 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TERM_RCAL_CFG[1] 03_136 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TERM_RCAL_CFG[2] 02_137 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TERM_RCAL_CFG[3] 03_137 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TERM_RCAL_CFG[4] 02_138 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TERM_RCAL_CFG[5] 03_138 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TERM_RCAL_CFG[6] 02_139 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TERM_RCAL_CFG[7] 03_139 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TERM_RCAL_CFG[8] 02_140 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TERM_RCAL_CFG[9] 03_140 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TERM_RCAL_CFG[10] 02_141 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TERM_RCAL_CFG[11] 03_141 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TERM_RCAL_CFG[12] 02_142 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TERM_RCAL_CFG[13] 03_142 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TERM_RCAL_CFG[14] 02_143 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TERM_RCAL_OVRD[0] 03_150 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TERM_RCAL_OVRD[1] 02_151 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TERM_RCAL_OVRD[2] 03_151 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TRANS_TIME_RATE[0] 00_192 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TRANS_TIME_RATE[1] 01_192 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TRANS_TIME_RATE[2] 00_193 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TRANS_TIME_RATE[3] 01_193 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TRANS_TIME_RATE[4] 00_194 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TRANS_TIME_RATE[5] 01_194 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TRANS_TIME_RATE[6] 00_195 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TRANS_TIME_RATE[7] 01_195 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TST_RSV[0] 02_504 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TST_RSV[1] 03_504 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TST_RSV[2] 02_505 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TST_RSV[3] 03_505 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TST_RSV[4] 02_506 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TST_RSV[5] 03_506 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TST_RSV[6] 02_507 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TST_RSV[7] 03_507 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TST_RSV[8] 02_508 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TST_RSV[9] 03_508 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TST_RSV[10] 02_509 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TST_RSV[11] 03_509 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TST_RSV[12] 02_510 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TST_RSV[13] 03_510 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TST_RSV[14] 02_511 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TST_RSV[15] 03_511 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TST_RSV[16] 02_512 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TST_RSV[17] 03_512 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TST_RSV[18] 02_513 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TST_RSV[19] 03_513 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TST_RSV[20] 02_514 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TST_RSV[21] 03_514 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TST_RSV[22] 02_515 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TST_RSV[23] 03_515 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TST_RSV[24] 02_516 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TST_RSV[25] 03_516 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TST_RSV[26] 02_517 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TST_RSV[27] 03_517 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TST_RSV[28] 02_518 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TST_RSV[29] 03_518 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TST_RSV[30] 02_519 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TST_RSV[31] 03_519 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_CLKMUX_EN[0] 03_128 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_DATA_WIDTH[0] 02_152 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_DATA_WIDTH[1] 03_152 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_DATA_WIDTH[2] 02_153 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_DRIVE_MODE.PIPE 00_200 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_EIDLE_ASSERT_DELAY[0] 00_203 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_EIDLE_ASSERT_DELAY[1] 01_203 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_EIDLE_ASSERT_DELAY[2] 00_204 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_EIDLE_DEASSERT_DELAY[0] 01_204 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_EIDLE_DEASSERT_DELAY[1] 00_205 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_EIDLE_DEASSERT_DELAY[2] 01_205 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_LOOPBACK_DRIVE_HIZ 01_202 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_MAINCURSOR_SEL[0] 03_289 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_0[0] 02_232 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_0[1] 03_232 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_0[2] 02_233 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_0[3] 03_233 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_0[4] 02_234 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_0[5] 03_234 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_0[6] 02_235 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_1[0] 02_236 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_1[1] 03_236 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_1[2] 02_237 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_1[3] 03_237 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_1[4] 02_238 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_1[5] 03_238 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_1[6] 02_239 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_2[0] 02_240 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_2[1] 03_240 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_2[2] 02_241 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_2[3] 03_241 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_2[4] 02_242 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_2[5] 03_242 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_2[6] 02_243 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_3[0] 02_244 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_3[1] 03_244 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_3[2] 02_245 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_3[3] 03_245 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_3[4] 02_246 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_3[5] 03_246 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_3[6] 02_247 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_4[0] 02_248 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_4[1] 03_248 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_4[2] 02_249 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_4[3] 03_249 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_4[4] 02_250 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_4[5] 03_250 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_4[6] 02_251 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_0[0] 02_252 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_0[1] 03_252 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_0[2] 02_253 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_0[3] 03_253 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_0[4] 02_254 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_0[5] 03_254 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_0[6] 02_255 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_1[0] 02_256 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_1[1] 03_256 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_1[2] 02_257 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_1[3] 03_257 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_1[4] 02_258 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_1[5] 03_258 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_1[6] 02_259 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_2[0] 02_260 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_2[1] 03_260 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_2[2] 02_261 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_2[3] 03_261 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_2[4] 02_262 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_2[5] 03_262 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_2[6] 02_263 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_3[0] 02_264 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_3[1] 03_264 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_3[2] 02_265 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_3[3] 03_265 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_3[4] 02_266 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_3[5] 03_266 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_3[6] 02_267 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_4[0] 02_268 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_4[1] 03_268 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_4[2] 02_269 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_4[3] 03_269 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_4[4] 02_270 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_4[5] 03_270 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_4[6] 02_271 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_PREDRIVER_MODE[0] 00_206 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_RXDETECT_CFG[0] 02_296 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_RXDETECT_CFG[1] 03_296 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_RXDETECT_CFG[2] 02_297 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_RXDETECT_CFG[3] 03_297 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_RXDETECT_CFG[4] 02_298 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_RXDETECT_CFG[5] 03_298 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_RXDETECT_CFG[6] 02_299 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_RXDETECT_CFG[7] 03_299 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_RXDETECT_CFG[8] 02_300 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_RXDETECT_CFG[9] 03_300 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_RXDETECT_CFG[10] 02_301 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_RXDETECT_CFG[11] 03_301 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_RXDETECT_CFG[12] 02_302 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_RXDETECT_CFG[13] 03_302 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_RXDETECT_REF[0] 02_292 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_RXDETECT_REF[1] 03_292 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_RXDETECT_REF[2] 02_293 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_XCLK_SEL.TXUSR 03_11 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_CLK25_DIV[0] 02_144 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_CLK25_DIV[1] 03_144 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_CLK25_DIV[2] 02_145 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_CLK25_DIV[3] 03_145 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_CLK25_DIV[4] 02_146 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_DEEMPH0[0] 02_272 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_DEEMPH0[1] 03_272 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_DEEMPH0[2] 02_273 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_DEEMPH0[3] 03_273 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_DEEMPH0[4] 02_274 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_DEEMPH0[5] 03_274 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_DEEMPH1[0] 02_276 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_DEEMPH1[1] 03_276 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_DEEMPH1[2] 02_277 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_DEEMPH1[3] 03_277 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_DEEMPH1[4] 02_278 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_DEEMPH1[5] 03_278 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXBUF_EN 00_231 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXBUF_RESET_ON_RATE_CHANGE 01_231 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXDLY_CFG[0] 02_80 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXDLY_CFG[1] 03_80 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXDLY_CFG[2] 02_81 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXDLY_CFG[3] 03_81 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXDLY_CFG[4] 02_82 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXDLY_CFG[5] 03_82 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXDLY_CFG[6] 02_83 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXDLY_CFG[7] 03_83 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXDLY_CFG[8] 02_84 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXDLY_CFG[9] 03_84 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXDLY_CFG[10] 02_85 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXDLY_CFG[11] 03_85 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXDLY_CFG[12] 02_86 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXDLY_CFG[13] 03_86 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXDLY_CFG[14] 02_87 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXDLY_CFG[15] 03_87 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXDLY_LCFG[0] 02_568 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXDLY_LCFG[1] 03_568 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXDLY_LCFG[2] 02_569 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXDLY_LCFG[3] 03_569 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXDLY_LCFG[4] 02_570 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXDLY_LCFG[5] 03_570 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXDLY_LCFG[6] 02_571 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXDLY_LCFG[7] 03_571 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXDLY_LCFG[8] 02_572 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXDLY_TAP_CFG[0] 02_88 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXDLY_TAP_CFG[1] 03_88 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXDLY_TAP_CFG[2] 02_89 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXDLY_TAP_CFG[3] 03_89 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXDLY_TAP_CFG[4] 02_90 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXDLY_TAP_CFG[5] 03_90 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXDLY_TAP_CFG[6] 02_91 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXDLY_TAP_CFG[7] 03_91 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXDLY_TAP_CFG[8] 02_92 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXDLY_TAP_CFG[9] 03_92 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXDLY_TAP_CFG[10] 02_93 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXDLY_TAP_CFG[11] 03_93 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXDLY_TAP_CFG[12] 02_94 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXDLY_TAP_CFG[13] 03_94 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXDLY_TAP_CFG[14] 02_95 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXDLY_TAP_CFG[15] 03_95 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXGEARBOX_EN 01_226 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXOOB_CFG[0] 03_20 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXOUT_DIV[0] 02_386 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXOUT_DIV[1] 03_386 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPCSRESET_TIME[0] 01_130 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPCSRESET_TIME[1] 00_131 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPCSRESET_TIME[2] 01_131 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPCSRESET_TIME[3] 00_132 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPCSRESET_TIME[4] 01_132 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPH_CFG[0] 02_96 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPH_CFG[1] 03_96 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPH_CFG[2] 02_97 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPH_CFG[3] 03_97 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPH_CFG[4] 02_98 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPH_CFG[5] 03_98 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPH_CFG[6] 02_99 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPH_CFG[7] 03_99 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPH_CFG[8] 02_100 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPH_CFG[9] 03_100 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPH_CFG[10] 02_101 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPH_CFG[11] 03_101 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPH_CFG[12] 02_102 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPH_CFG[13] 03_102 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPH_CFG[14] 02_103 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPH_CFG[15] 03_103 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPH_MONITOR_SEL[0] 02_108 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPH_MONITOR_SEL[1] 03_108 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPH_MONITOR_SEL[2] 02_109 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPH_MONITOR_SEL[3] 03_109 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPH_MONITOR_SEL[4] 02_110 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[0] 02_64 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[1] 03_64 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[2] 02_65 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[3] 03_65 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[4] 02_66 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[5] 03_66 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[6] 02_67 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[7] 03_67 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[8] 02_68 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[9] 03_68 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[10] 02_69 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[11] 03_69 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[12] 02_70 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[13] 03_70 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[14] 02_71 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[15] 03_71 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[16] 02_72 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[17] 03_72 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[18] 02_73 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[19] 03_73 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[20] 02_74 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[21] 03_74 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[22] 02_75 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[23] 03_75 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPI_GREY_SEL[0] 03_498 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPI_INVSTROBE_SEL[0] 02_498 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPI_PPM_CFG[0] 02_488 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPI_PPM_CFG[1] 03_488 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPI_PPM_CFG[2] 02_489 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPI_PPM_CFG[3] 03_489 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPI_PPM_CFG[4] 02_490 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPI_PPM_CFG[5] 03_490 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPI_PPM_CFG[6] 02_491 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPI_PPM_CFG[7] 03_491 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPI_PPMCLK_SEL.TXUSRCLK2 03_497 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPI_SYNFREQ_PPM[0] 02_496 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPI_SYNFREQ_PPM[1] 03_496 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPI_SYNFREQ_PPM[2] 02_497 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPI_CFG0[0] 02_40 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPI_CFG0[1] 03_40 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPI_CFG1[0] 02_41 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPI_CFG1[1] 03_41 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPI_CFG2[0] 02_42 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPI_CFG2[1] 03_42 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPI_CFG3[0] 02_43 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPI_CFG4[0] 03_43 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPI_CFG5[0] 02_44 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPI_CFG5[1] 03_44 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPI_CFG5[2] 02_45 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPMARESET_TIME[0] 00_128 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPMARESET_TIME[1] 01_128 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPMARESET_TIME[2] 00_129 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPMARESET_TIME[3] 01_129 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPMARESET_TIME[4] 00_130 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXSYNC_MULTILANE[0] 01_133 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXSYNC_OVRD[0] 00_135 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXSYNC_SKIP_DA[0] 00_134 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.UCODEER_CLR[0] 01_00 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.USE_PCS_CLK_PHASE_SEL[0] 02_463 diff --git a/artix7/segbits_gtp_channel_2_mid_left.origin_info.db b/artix7/segbits_gtp_channel_2_mid_left.origin_info.db index 6e151fd..51e9a14 100644 --- a/artix7/segbits_gtp_channel_2_mid_left.origin_info.db +++ b/artix7/segbits_gtp_channel_2_mid_left.origin_info.db @@ -1,1627 +1,1627 @@ -GTP_CHANNEL_2_MID_LEFT.GTPE2.ACJTAG_DEBUG_MODE[0] origin:064-gtp-channel-conf 00_07 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ACJTAG_MODE[0] origin:064-gtp-channel-conf 01_06 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ACJTAG_RESET[0] origin:064-gtp-channel-conf 01_07 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ADAPT_CFG0[0] origin:064-gtp-channel-conf 02_464 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ADAPT_CFG0[1] origin:064-gtp-channel-conf 03_464 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ADAPT_CFG0[2] origin:064-gtp-channel-conf 02_465 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ADAPT_CFG0[3] origin:064-gtp-channel-conf 03_465 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ADAPT_CFG0[4] origin:064-gtp-channel-conf 02_466 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ADAPT_CFG0[5] origin:064-gtp-channel-conf 03_466 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ADAPT_CFG0[6] origin:064-gtp-channel-conf 02_467 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ADAPT_CFG0[7] origin:064-gtp-channel-conf 03_467 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ADAPT_CFG0[8] origin:064-gtp-channel-conf 02_468 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ADAPT_CFG0[9] origin:064-gtp-channel-conf 03_468 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ADAPT_CFG0[10] origin:064-gtp-channel-conf 02_469 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ADAPT_CFG0[11] origin:064-gtp-channel-conf 03_469 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ADAPT_CFG0[12] origin:064-gtp-channel-conf 02_470 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ADAPT_CFG0[13] origin:064-gtp-channel-conf 03_470 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ADAPT_CFG0[14] origin:064-gtp-channel-conf 02_471 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ADAPT_CFG0[15] origin:064-gtp-channel-conf 03_471 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ADAPT_CFG0[16] origin:064-gtp-channel-conf 02_472 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ADAPT_CFG0[17] origin:064-gtp-channel-conf 03_472 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ADAPT_CFG0[18] origin:064-gtp-channel-conf 02_473 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ADAPT_CFG0[19] origin:064-gtp-channel-conf 03_473 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ALIGN_COMMA_DOUBLE origin:064-gtp-channel-conf 00_522 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ALIGN_COMMA_ENABLE[0] origin:064-gtp-channel-conf 00_496 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ALIGN_COMMA_ENABLE[1] origin:064-gtp-channel-conf 01_496 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ALIGN_COMMA_ENABLE[2] origin:064-gtp-channel-conf 00_497 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ALIGN_COMMA_ENABLE[3] origin:064-gtp-channel-conf 01_497 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ALIGN_COMMA_ENABLE[4] origin:064-gtp-channel-conf 00_498 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ALIGN_COMMA_ENABLE[5] origin:064-gtp-channel-conf 01_498 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ALIGN_COMMA_ENABLE[6] origin:064-gtp-channel-conf 00_499 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ALIGN_COMMA_ENABLE[7] origin:064-gtp-channel-conf 01_499 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ALIGN_COMMA_ENABLE[8] origin:064-gtp-channel-conf 00_500 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ALIGN_COMMA_ENABLE[9] origin:064-gtp-channel-conf 01_500 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ALIGN_COMMA_WORD[0] origin:064-gtp-channel-conf 01_526 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ALIGN_COMMA_WORD[1] origin:064-gtp-channel-conf 00_527 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ALIGN_MCOMMA_DET origin:064-gtp-channel-conf 00_523 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ALIGN_MCOMMA_VALUE[0] origin:064-gtp-channel-conf 00_504 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ALIGN_MCOMMA_VALUE[1] origin:064-gtp-channel-conf 01_504 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ALIGN_MCOMMA_VALUE[2] origin:064-gtp-channel-conf 00_505 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ALIGN_MCOMMA_VALUE[3] origin:064-gtp-channel-conf 01_505 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ALIGN_MCOMMA_VALUE[4] origin:064-gtp-channel-conf 00_506 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ALIGN_MCOMMA_VALUE[5] origin:064-gtp-channel-conf 01_506 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ALIGN_MCOMMA_VALUE[6] origin:064-gtp-channel-conf 00_507 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ALIGN_MCOMMA_VALUE[7] origin:064-gtp-channel-conf 01_507 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ALIGN_MCOMMA_VALUE[8] origin:064-gtp-channel-conf 00_508 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ALIGN_MCOMMA_VALUE[9] origin:064-gtp-channel-conf 01_508 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ALIGN_PCOMMA_DET origin:064-gtp-channel-conf 01_523 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ALIGN_PCOMMA_VALUE[0] origin:064-gtp-channel-conf 00_512 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ALIGN_PCOMMA_VALUE[1] origin:064-gtp-channel-conf 01_512 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ALIGN_PCOMMA_VALUE[2] origin:064-gtp-channel-conf 00_513 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ALIGN_PCOMMA_VALUE[3] origin:064-gtp-channel-conf 01_513 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ALIGN_PCOMMA_VALUE[4] origin:064-gtp-channel-conf 00_514 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ALIGN_PCOMMA_VALUE[5] origin:064-gtp-channel-conf 01_514 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ALIGN_PCOMMA_VALUE[6] origin:064-gtp-channel-conf 00_515 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ALIGN_PCOMMA_VALUE[7] origin:064-gtp-channel-conf 01_515 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ALIGN_PCOMMA_VALUE[8] origin:064-gtp-channel-conf 00_516 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ALIGN_PCOMMA_VALUE[9] origin:064-gtp-channel-conf 01_516 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CBCC_DATA_SOURCE_SEL.DECODED origin:064-gtp-channel-conf 01_661 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CFOK_CFG[0] origin:064-gtp-channel-conf 02_392 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CFOK_CFG[1] origin:064-gtp-channel-conf 03_392 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CFOK_CFG[2] origin:064-gtp-channel-conf 02_393 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CFOK_CFG[3] origin:064-gtp-channel-conf 03_393 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CFOK_CFG[4] origin:064-gtp-channel-conf 02_394 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CFOK_CFG[5] origin:064-gtp-channel-conf 03_394 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CFOK_CFG[6] origin:064-gtp-channel-conf 02_395 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CFOK_CFG[7] origin:064-gtp-channel-conf 03_395 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CFOK_CFG[8] origin:064-gtp-channel-conf 02_396 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CFOK_CFG[9] origin:064-gtp-channel-conf 03_396 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CFOK_CFG[10] origin:064-gtp-channel-conf 02_397 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CFOK_CFG[11] origin:064-gtp-channel-conf 03_397 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CFOK_CFG[12] origin:064-gtp-channel-conf 02_398 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CFOK_CFG[13] origin:064-gtp-channel-conf 03_398 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CFOK_CFG[14] origin:064-gtp-channel-conf 02_399 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CFOK_CFG[15] origin:064-gtp-channel-conf 03_399 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CFOK_CFG[16] origin:064-gtp-channel-conf 02_400 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CFOK_CFG[17] origin:064-gtp-channel-conf 03_400 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CFOK_CFG[18] origin:064-gtp-channel-conf 02_401 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CFOK_CFG[19] origin:064-gtp-channel-conf 03_401 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CFOK_CFG[20] origin:064-gtp-channel-conf 02_402 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CFOK_CFG[21] origin:064-gtp-channel-conf 03_402 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CFOK_CFG[22] origin:064-gtp-channel-conf 02_403 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CFOK_CFG[23] origin:064-gtp-channel-conf 03_403 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CFOK_CFG[24] origin:064-gtp-channel-conf 02_404 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CFOK_CFG[25] origin:064-gtp-channel-conf 03_404 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CFOK_CFG[26] origin:064-gtp-channel-conf 02_405 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CFOK_CFG[27] origin:064-gtp-channel-conf 03_405 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CFOK_CFG[28] origin:064-gtp-channel-conf 02_406 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CFOK_CFG[29] origin:064-gtp-channel-conf 03_406 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CFOK_CFG[30] origin:064-gtp-channel-conf 02_407 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CFOK_CFG[31] origin:064-gtp-channel-conf 03_407 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CFOK_CFG[32] origin:064-gtp-channel-conf 02_408 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CFOK_CFG[33] origin:064-gtp-channel-conf 03_408 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CFOK_CFG[34] origin:064-gtp-channel-conf 02_409 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CFOK_CFG[35] origin:064-gtp-channel-conf 03_409 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CFOK_CFG[36] origin:064-gtp-channel-conf 02_410 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CFOK_CFG[37] origin:064-gtp-channel-conf 03_410 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CFOK_CFG[38] origin:064-gtp-channel-conf 02_411 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CFOK_CFG[39] origin:064-gtp-channel-conf 03_411 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CFOK_CFG[40] origin:064-gtp-channel-conf 02_412 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CFOK_CFG[41] origin:064-gtp-channel-conf 03_412 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CFOK_CFG[42] origin:064-gtp-channel-conf 02_413 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CFOK_CFG2[0] origin:064-gtp-channel-conf 02_459 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CFOK_CFG2[1] origin:064-gtp-channel-conf 03_459 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CFOK_CFG2[2] origin:064-gtp-channel-conf 02_460 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CFOK_CFG2[3] origin:064-gtp-channel-conf 03_460 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CFOK_CFG2[4] origin:064-gtp-channel-conf 02_461 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CFOK_CFG2[5] origin:064-gtp-channel-conf 03_461 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CFOK_CFG2[6] origin:064-gtp-channel-conf 02_462 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CFOK_CFG3[0] origin:064-gtp-channel-conf 02_416 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CFOK_CFG3[1] origin:064-gtp-channel-conf 03_416 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CFOK_CFG3[2] origin:064-gtp-channel-conf 02_417 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CFOK_CFG3[3] origin:064-gtp-channel-conf 03_417 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CFOK_CFG3[4] origin:064-gtp-channel-conf 02_418 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CFOK_CFG3[5] origin:064-gtp-channel-conf 03_418 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CFOK_CFG3[6] origin:064-gtp-channel-conf 02_419 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CFOK_CFG4[0] origin:064-gtp-channel-conf 03_438 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CFOK_CFG5[0] origin:064-gtp-channel-conf 02_429 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CFOK_CFG5[1] origin:064-gtp-channel-conf 03_429 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CFOK_CFG6[0] origin:064-gtp-channel-conf 03_436 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CFOK_CFG6[1] origin:064-gtp-channel-conf 02_437 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CFOK_CFG6[2] origin:064-gtp-channel-conf 03_437 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CFOK_CFG6[3] origin:064-gtp-channel-conf 02_438 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_KEEP_ALIGN origin:064-gtp-channel-conf 01_631 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_MAX_SKEW[0] origin:064-gtp-channel-conf 00_670 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_MAX_SKEW[1] origin:064-gtp-channel-conf 01_670 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_MAX_SKEW[2] origin:064-gtp-channel-conf 00_671 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_MAX_SKEW[3] origin:064-gtp-channel-conf 01_671 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_1[0] origin:064-gtp-channel-conf 00_608 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_1[1] origin:064-gtp-channel-conf 01_608 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_1[2] origin:064-gtp-channel-conf 00_609 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_1[3] origin:064-gtp-channel-conf 01_609 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_1[4] origin:064-gtp-channel-conf 00_610 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_1[5] origin:064-gtp-channel-conf 01_610 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_1[6] origin:064-gtp-channel-conf 00_611 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_1[7] origin:064-gtp-channel-conf 01_611 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_1[8] origin:064-gtp-channel-conf 00_612 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_1[9] origin:064-gtp-channel-conf 01_612 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_2[0] origin:064-gtp-channel-conf 00_616 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_2[1] origin:064-gtp-channel-conf 01_616 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_2[2] origin:064-gtp-channel-conf 00_617 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_2[3] origin:064-gtp-channel-conf 01_617 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_2[4] origin:064-gtp-channel-conf 00_618 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_2[5] origin:064-gtp-channel-conf 01_618 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_2[6] origin:064-gtp-channel-conf 00_619 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_2[7] origin:064-gtp-channel-conf 01_619 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_2[8] origin:064-gtp-channel-conf 00_620 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_2[9] origin:064-gtp-channel-conf 01_620 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_3[0] origin:064-gtp-channel-conf 00_624 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_3[1] origin:064-gtp-channel-conf 01_624 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_3[2] origin:064-gtp-channel-conf 00_625 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_3[3] origin:064-gtp-channel-conf 01_625 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_3[4] origin:064-gtp-channel-conf 00_626 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_3[5] origin:064-gtp-channel-conf 01_626 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_3[6] origin:064-gtp-channel-conf 00_627 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_3[7] origin:064-gtp-channel-conf 01_627 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_3[8] origin:064-gtp-channel-conf 00_628 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_3[9] origin:064-gtp-channel-conf 01_628 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_4[0] origin:064-gtp-channel-conf 00_632 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_4[1] origin:064-gtp-channel-conf 01_632 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_4[2] origin:064-gtp-channel-conf 00_633 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_4[3] origin:064-gtp-channel-conf 01_633 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_4[4] origin:064-gtp-channel-conf 00_634 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_4[5] origin:064-gtp-channel-conf 01_634 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_4[6] origin:064-gtp-channel-conf 00_635 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_4[7] origin:064-gtp-channel-conf 01_635 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_4[8] origin:064-gtp-channel-conf 00_636 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_4[9] origin:064-gtp-channel-conf 01_636 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_ENABLE[0] origin:064-gtp-channel-conf 00_614 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_ENABLE[1] origin:064-gtp-channel-conf 01_614 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_ENABLE[2] origin:064-gtp-channel-conf 00_615 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_ENABLE[3] origin:064-gtp-channel-conf 01_615 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_1[0] origin:064-gtp-channel-conf 00_640 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_1[1] origin:064-gtp-channel-conf 01_640 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_1[2] origin:064-gtp-channel-conf 00_641 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_1[3] origin:064-gtp-channel-conf 01_641 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_1[4] origin:064-gtp-channel-conf 00_642 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_1[5] origin:064-gtp-channel-conf 01_642 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_1[6] origin:064-gtp-channel-conf 00_643 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_1[7] origin:064-gtp-channel-conf 01_643 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_1[8] origin:064-gtp-channel-conf 00_644 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_1[9] origin:064-gtp-channel-conf 01_644 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_2[0] origin:064-gtp-channel-conf 00_648 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_2[1] origin:064-gtp-channel-conf 01_648 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_2[2] origin:064-gtp-channel-conf 00_649 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_2[3] origin:064-gtp-channel-conf 01_649 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_2[4] origin:064-gtp-channel-conf 00_650 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_2[5] origin:064-gtp-channel-conf 01_650 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_2[6] origin:064-gtp-channel-conf 00_651 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_2[7] origin:064-gtp-channel-conf 01_651 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_2[8] origin:064-gtp-channel-conf 00_652 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_2[9] origin:064-gtp-channel-conf 01_652 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_3[0] origin:064-gtp-channel-conf 00_656 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_3[1] origin:064-gtp-channel-conf 01_656 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_3[2] origin:064-gtp-channel-conf 00_657 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_3[3] origin:064-gtp-channel-conf 01_657 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_3[4] origin:064-gtp-channel-conf 00_658 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_3[5] origin:064-gtp-channel-conf 01_658 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_3[6] origin:064-gtp-channel-conf 00_659 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_3[7] origin:064-gtp-channel-conf 01_659 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_3[8] origin:064-gtp-channel-conf 00_660 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_3[9] origin:064-gtp-channel-conf 01_660 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_4[0] origin:064-gtp-channel-conf 00_664 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_4[1] origin:064-gtp-channel-conf 01_664 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_4[2] origin:064-gtp-channel-conf 00_665 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_4[3] origin:064-gtp-channel-conf 01_665 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_4[4] origin:064-gtp-channel-conf 00_666 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_4[5] origin:064-gtp-channel-conf 01_666 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_4[6] origin:064-gtp-channel-conf 00_667 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_4[7] origin:064-gtp-channel-conf 01_667 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_4[8] origin:064-gtp-channel-conf 00_668 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_4[9] origin:064-gtp-channel-conf 01_668 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_ENABLE[0] origin:064-gtp-channel-conf 00_646 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_ENABLE[1] origin:064-gtp-channel-conf 01_646 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_ENABLE[2] origin:064-gtp-channel-conf 00_647 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_ENABLE[3] origin:064-gtp-channel-conf 01_647 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_USE origin:064-gtp-channel-conf 01_645 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_LEN[0] origin:064-gtp-channel-conf 00_623 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CHAN_BOND_SEQ_LEN[1] origin:064-gtp-channel-conf 01_623 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COMMON_SWING[0] origin:064-gtp-channel-conf 03_311 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_KEEP_IDLE origin:064-gtp-channel-conf 00_591 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_MAX_LAT[0] origin:064-gtp-channel-conf 00_557 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_MAX_LAT[1] origin:064-gtp-channel-conf 01_557 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_MAX_LAT[2] origin:064-gtp-channel-conf 00_558 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_MAX_LAT[3] origin:064-gtp-channel-conf 01_558 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_MAX_LAT[4] origin:064-gtp-channel-conf 00_559 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_MAX_LAT[5] origin:064-gtp-channel-conf 01_559 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_MIN_LAT[0] origin:064-gtp-channel-conf 00_565 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_MIN_LAT[1] origin:064-gtp-channel-conf 01_565 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_MIN_LAT[2] origin:064-gtp-channel-conf 00_566 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_MIN_LAT[3] origin:064-gtp-channel-conf 01_566 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_MIN_LAT[4] origin:064-gtp-channel-conf 00_567 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_MIN_LAT[5] origin:064-gtp-channel-conf 01_567 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_PRECEDENCE origin:064-gtp-channel-conf 00_590 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_REPEAT_WAIT[0] origin:064-gtp-channel-conf 00_573 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_REPEAT_WAIT[1] origin:064-gtp-channel-conf 01_573 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_REPEAT_WAIT[2] origin:064-gtp-channel-conf 00_574 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_REPEAT_WAIT[3] origin:064-gtp-channel-conf 01_574 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_REPEAT_WAIT[4] origin:064-gtp-channel-conf 00_575 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_1_1[0] origin:064-gtp-channel-conf 00_544 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_1_1[1] origin:064-gtp-channel-conf 01_544 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_1_1[2] origin:064-gtp-channel-conf 00_545 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_1_1[3] origin:064-gtp-channel-conf 01_545 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_1_1[4] origin:064-gtp-channel-conf 00_546 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_1_1[5] origin:064-gtp-channel-conf 01_546 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_1_1[6] origin:064-gtp-channel-conf 00_547 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_1_1[7] origin:064-gtp-channel-conf 01_547 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_1_1[8] origin:064-gtp-channel-conf 00_548 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_1_1[9] origin:064-gtp-channel-conf 01_548 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_1_2[0] origin:064-gtp-channel-conf 00_552 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_1_2[1] origin:064-gtp-channel-conf 01_552 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_1_2[2] origin:064-gtp-channel-conf 00_553 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_1_2[3] origin:064-gtp-channel-conf 01_553 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_1_2[4] origin:064-gtp-channel-conf 00_554 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_1_2[5] origin:064-gtp-channel-conf 01_554 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_1_2[6] origin:064-gtp-channel-conf 00_555 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_1_2[7] origin:064-gtp-channel-conf 01_555 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_1_2[8] origin:064-gtp-channel-conf 00_556 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_1_2[9] origin:064-gtp-channel-conf 01_556 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_1_3[0] origin:064-gtp-channel-conf 00_560 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_1_3[1] origin:064-gtp-channel-conf 01_560 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_1_3[2] origin:064-gtp-channel-conf 00_561 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_1_3[3] origin:064-gtp-channel-conf 01_561 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_1_3[4] origin:064-gtp-channel-conf 00_562 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_1_3[5] origin:064-gtp-channel-conf 01_562 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_1_3[6] origin:064-gtp-channel-conf 00_563 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_1_3[7] origin:064-gtp-channel-conf 01_563 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_1_3[8] origin:064-gtp-channel-conf 00_564 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_1_3[9] origin:064-gtp-channel-conf 01_564 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_1_4[0] origin:064-gtp-channel-conf 00_568 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_1_4[1] origin:064-gtp-channel-conf 01_568 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_1_4[2] origin:064-gtp-channel-conf 00_569 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_1_4[3] origin:064-gtp-channel-conf 01_569 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_1_4[4] origin:064-gtp-channel-conf 00_570 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_1_4[5] origin:064-gtp-channel-conf 01_570 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_1_4[6] origin:064-gtp-channel-conf 00_571 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_1_4[7] origin:064-gtp-channel-conf 01_571 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_1_4[8] origin:064-gtp-channel-conf 00_572 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_1_4[9] origin:064-gtp-channel-conf 01_572 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_1_ENABLE[0] origin:064-gtp-channel-conf 00_549 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_1_ENABLE[1] origin:064-gtp-channel-conf 01_549 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_1_ENABLE[2] origin:064-gtp-channel-conf 00_550 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_1_ENABLE[3] origin:064-gtp-channel-conf 01_550 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_2_1[0] origin:064-gtp-channel-conf 00_576 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_2_1[1] origin:064-gtp-channel-conf 01_576 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_2_1[2] origin:064-gtp-channel-conf 00_577 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_2_1[3] origin:064-gtp-channel-conf 01_577 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_2_1[4] origin:064-gtp-channel-conf 00_578 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_2_1[5] origin:064-gtp-channel-conf 01_578 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_2_1[6] origin:064-gtp-channel-conf 00_579 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_2_1[7] origin:064-gtp-channel-conf 01_579 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_2_1[8] origin:064-gtp-channel-conf 00_580 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_2_1[9] origin:064-gtp-channel-conf 01_580 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_2_2[0] origin:064-gtp-channel-conf 00_584 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_2_2[1] origin:064-gtp-channel-conf 01_584 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_2_2[2] origin:064-gtp-channel-conf 00_585 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_2_2[3] origin:064-gtp-channel-conf 01_585 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_2_2[4] origin:064-gtp-channel-conf 00_586 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_2_2[5] origin:064-gtp-channel-conf 01_586 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_2_2[6] origin:064-gtp-channel-conf 00_587 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_2_2[7] origin:064-gtp-channel-conf 01_587 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_2_2[8] origin:064-gtp-channel-conf 00_588 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_2_2[9] origin:064-gtp-channel-conf 01_588 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_2_3[0] origin:064-gtp-channel-conf 00_592 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_2_3[1] origin:064-gtp-channel-conf 01_592 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_2_3[2] origin:064-gtp-channel-conf 00_593 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_2_3[3] origin:064-gtp-channel-conf 01_593 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_2_3[4] origin:064-gtp-channel-conf 00_594 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_2_3[5] origin:064-gtp-channel-conf 01_594 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_2_3[6] origin:064-gtp-channel-conf 00_595 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_2_3[7] origin:064-gtp-channel-conf 01_595 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_2_3[8] origin:064-gtp-channel-conf 00_596 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_2_3[9] origin:064-gtp-channel-conf 01_596 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_2_4[0] origin:064-gtp-channel-conf 00_600 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_2_4[1] origin:064-gtp-channel-conf 01_600 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_2_4[2] origin:064-gtp-channel-conf 00_601 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_2_4[3] origin:064-gtp-channel-conf 01_601 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_2_4[4] origin:064-gtp-channel-conf 00_602 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_2_4[5] origin:064-gtp-channel-conf 01_602 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_2_4[6] origin:064-gtp-channel-conf 00_603 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_2_4[7] origin:064-gtp-channel-conf 01_603 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_2_4[8] origin:064-gtp-channel-conf 00_604 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_2_4[9] origin:064-gtp-channel-conf 01_604 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_2_ENABLE[0] origin:064-gtp-channel-conf 00_581 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_2_ENABLE[1] origin:064-gtp-channel-conf 01_581 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_2_ENABLE[2] origin:064-gtp-channel-conf 00_582 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_2_ENABLE[3] origin:064-gtp-channel-conf 01_582 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_2_USE origin:064-gtp-channel-conf 00_583 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_LEN[0] origin:064-gtp-channel-conf 00_589 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_COR_SEQ_LEN[1] origin:064-gtp-channel-conf 01_589 -GTP_CHANNEL_2_MID_LEFT.GTPE2.CLK_CORRECT_USE origin:064-gtp-channel-conf 00_551 -GTP_CHANNEL_2_MID_LEFT.GTPE2.DEC_MCOMMA_DETECT origin:064-gtp-channel-conf 01_494 -GTP_CHANNEL_2_MID_LEFT.GTPE2.DEC_PCOMMA_DETECT origin:064-gtp-channel-conf 00_495 -GTP_CHANNEL_2_MID_LEFT.GTPE2.DEC_VALID_COMMA_ONLY origin:064-gtp-channel-conf 00_494 -GTP_CHANNEL_2_MID_LEFT.GTPE2.DMONITOR_CFG[0] origin:064-gtp-channel-conf 02_368 -GTP_CHANNEL_2_MID_LEFT.GTPE2.DMONITOR_CFG[1] origin:064-gtp-channel-conf 03_368 -GTP_CHANNEL_2_MID_LEFT.GTPE2.DMONITOR_CFG[2] origin:064-gtp-channel-conf 02_369 -GTP_CHANNEL_2_MID_LEFT.GTPE2.DMONITOR_CFG[3] origin:064-gtp-channel-conf 03_369 -GTP_CHANNEL_2_MID_LEFT.GTPE2.DMONITOR_CFG[4] origin:064-gtp-channel-conf 02_370 -GTP_CHANNEL_2_MID_LEFT.GTPE2.DMONITOR_CFG[5] origin:064-gtp-channel-conf 03_370 -GTP_CHANNEL_2_MID_LEFT.GTPE2.DMONITOR_CFG[6] origin:064-gtp-channel-conf 02_371 -GTP_CHANNEL_2_MID_LEFT.GTPE2.DMONITOR_CFG[7] origin:064-gtp-channel-conf 03_371 -GTP_CHANNEL_2_MID_LEFT.GTPE2.DMONITOR_CFG[8] origin:064-gtp-channel-conf 02_372 -GTP_CHANNEL_2_MID_LEFT.GTPE2.DMONITOR_CFG[9] origin:064-gtp-channel-conf 03_372 -GTP_CHANNEL_2_MID_LEFT.GTPE2.DMONITOR_CFG[10] origin:064-gtp-channel-conf 02_373 -GTP_CHANNEL_2_MID_LEFT.GTPE2.DMONITOR_CFG[11] origin:064-gtp-channel-conf 03_373 -GTP_CHANNEL_2_MID_LEFT.GTPE2.DMONITOR_CFG[12] origin:064-gtp-channel-conf 02_374 -GTP_CHANNEL_2_MID_LEFT.GTPE2.DMONITOR_CFG[13] origin:064-gtp-channel-conf 03_374 -GTP_CHANNEL_2_MID_LEFT.GTPE2.DMONITOR_CFG[14] origin:064-gtp-channel-conf 02_375 -GTP_CHANNEL_2_MID_LEFT.GTPE2.DMONITOR_CFG[15] origin:064-gtp-channel-conf 03_375 -GTP_CHANNEL_2_MID_LEFT.GTPE2.DMONITOR_CFG[16] origin:064-gtp-channel-conf 02_376 -GTP_CHANNEL_2_MID_LEFT.GTPE2.DMONITOR_CFG[17] origin:064-gtp-channel-conf 03_376 -GTP_CHANNEL_2_MID_LEFT.GTPE2.DMONITOR_CFG[18] origin:064-gtp-channel-conf 02_377 -GTP_CHANNEL_2_MID_LEFT.GTPE2.DMONITOR_CFG[19] origin:064-gtp-channel-conf 03_377 -GTP_CHANNEL_2_MID_LEFT.GTPE2.DMONITOR_CFG[20] origin:064-gtp-channel-conf 02_378 -GTP_CHANNEL_2_MID_LEFT.GTPE2.DMONITOR_CFG[21] origin:064-gtp-channel-conf 03_378 -GTP_CHANNEL_2_MID_LEFT.GTPE2.DMONITOR_CFG[22] origin:064-gtp-channel-conf 02_379 -GTP_CHANNEL_2_MID_LEFT.GTPE2.DMONITOR_CFG[23] origin:064-gtp-channel-conf 03_379 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_CLK_PHASE_SEL[0] origin:064-gtp-channel-conf 03_463 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_CONTROL[0] origin:064-gtp-channel-conf 00_488 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_CONTROL[1] origin:064-gtp-channel-conf 01_488 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_CONTROL[2] origin:064-gtp-channel-conf 00_489 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_CONTROL[3] origin:064-gtp-channel-conf 01_489 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_CONTROL[4] origin:064-gtp-channel-conf 00_490 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_CONTROL[5] origin:064-gtp-channel-conf 01_490 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_ERRDET_EN origin:064-gtp-channel-conf 01_492 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_EYE_SCAN_EN origin:064-gtp-channel-conf 00_492 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_HORZ_OFFSET[0] origin:064-gtp-channel-conf 00_480 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_HORZ_OFFSET[1] origin:064-gtp-channel-conf 01_480 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_HORZ_OFFSET[2] origin:064-gtp-channel-conf 00_481 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_HORZ_OFFSET[3] origin:064-gtp-channel-conf 01_481 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_HORZ_OFFSET[4] origin:064-gtp-channel-conf 00_482 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_HORZ_OFFSET[5] origin:064-gtp-channel-conf 01_482 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_HORZ_OFFSET[6] origin:064-gtp-channel-conf 00_483 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_HORZ_OFFSET[7] origin:064-gtp-channel-conf 01_483 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_HORZ_OFFSET[8] origin:064-gtp-channel-conf 00_484 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_HORZ_OFFSET[9] origin:064-gtp-channel-conf 01_484 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_HORZ_OFFSET[10] origin:064-gtp-channel-conf 00_485 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_HORZ_OFFSET[11] origin:064-gtp-channel-conf 01_485 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_PMA_CFG[0] origin:064-gtp-channel-conf 02_624 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_PMA_CFG[1] origin:064-gtp-channel-conf 03_624 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_PMA_CFG[2] origin:064-gtp-channel-conf 02_625 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_PMA_CFG[3] origin:064-gtp-channel-conf 03_625 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_PMA_CFG[4] origin:064-gtp-channel-conf 02_626 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_PMA_CFG[5] origin:064-gtp-channel-conf 03_626 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_PMA_CFG[6] origin:064-gtp-channel-conf 02_627 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_PMA_CFG[7] origin:064-gtp-channel-conf 03_627 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_PMA_CFG[8] origin:064-gtp-channel-conf 02_628 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_PMA_CFG[9] origin:064-gtp-channel-conf 03_628 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_PRESCALE[0] origin:064-gtp-channel-conf 01_477 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_PRESCALE[1] origin:064-gtp-channel-conf 00_478 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_PRESCALE[2] origin:064-gtp-channel-conf 01_478 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_PRESCALE[3] origin:064-gtp-channel-conf 00_479 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_PRESCALE[4] origin:064-gtp-channel-conf 01_479 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[0] origin:064-gtp-channel-conf 00_392 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[1] origin:064-gtp-channel-conf 01_392 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[2] origin:064-gtp-channel-conf 00_393 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[3] origin:064-gtp-channel-conf 01_393 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[4] origin:064-gtp-channel-conf 00_394 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[5] origin:064-gtp-channel-conf 01_394 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[6] origin:064-gtp-channel-conf 00_395 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[7] origin:064-gtp-channel-conf 01_395 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[8] origin:064-gtp-channel-conf 00_396 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[9] origin:064-gtp-channel-conf 01_396 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[10] origin:064-gtp-channel-conf 00_397 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[11] origin:064-gtp-channel-conf 01_397 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[12] origin:064-gtp-channel-conf 00_398 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[13] origin:064-gtp-channel-conf 01_398 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[14] origin:064-gtp-channel-conf 00_399 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[15] origin:064-gtp-channel-conf 01_399 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[16] origin:064-gtp-channel-conf 00_400 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[17] origin:064-gtp-channel-conf 01_400 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[18] origin:064-gtp-channel-conf 00_401 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[19] origin:064-gtp-channel-conf 01_401 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[20] origin:064-gtp-channel-conf 00_402 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[21] origin:064-gtp-channel-conf 01_402 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[22] origin:064-gtp-channel-conf 00_403 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[23] origin:064-gtp-channel-conf 01_403 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[24] origin:064-gtp-channel-conf 00_404 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[25] origin:064-gtp-channel-conf 01_404 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[26] origin:064-gtp-channel-conf 00_405 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[27] origin:064-gtp-channel-conf 01_405 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[28] origin:064-gtp-channel-conf 00_406 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[29] origin:064-gtp-channel-conf 01_406 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[30] origin:064-gtp-channel-conf 00_407 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[31] origin:064-gtp-channel-conf 01_407 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[32] origin:064-gtp-channel-conf 00_408 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[33] origin:064-gtp-channel-conf 01_408 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[34] origin:064-gtp-channel-conf 00_409 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[35] origin:064-gtp-channel-conf 01_409 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[36] origin:064-gtp-channel-conf 00_410 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[37] origin:064-gtp-channel-conf 01_410 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[38] origin:064-gtp-channel-conf 00_411 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[39] origin:064-gtp-channel-conf 01_411 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[40] origin:064-gtp-channel-conf 00_412 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[41] origin:064-gtp-channel-conf 01_412 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[42] origin:064-gtp-channel-conf 00_413 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[43] origin:064-gtp-channel-conf 01_413 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[44] origin:064-gtp-channel-conf 00_414 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[45] origin:064-gtp-channel-conf 01_414 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[46] origin:064-gtp-channel-conf 00_415 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[47] origin:064-gtp-channel-conf 01_415 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[48] origin:064-gtp-channel-conf 00_416 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[49] origin:064-gtp-channel-conf 01_416 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[50] origin:064-gtp-channel-conf 00_417 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[51] origin:064-gtp-channel-conf 01_417 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[52] origin:064-gtp-channel-conf 00_418 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[53] origin:064-gtp-channel-conf 01_418 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[54] origin:064-gtp-channel-conf 00_419 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[55] origin:064-gtp-channel-conf 01_419 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[56] origin:064-gtp-channel-conf 00_420 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[57] origin:064-gtp-channel-conf 01_420 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[58] origin:064-gtp-channel-conf 00_421 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[59] origin:064-gtp-channel-conf 01_421 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[60] origin:064-gtp-channel-conf 00_422 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[61] origin:064-gtp-channel-conf 01_422 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[62] origin:064-gtp-channel-conf 00_423 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[63] origin:064-gtp-channel-conf 01_423 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[64] origin:064-gtp-channel-conf 00_424 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[65] origin:064-gtp-channel-conf 01_424 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[66] origin:064-gtp-channel-conf 00_425 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[67] origin:064-gtp-channel-conf 01_425 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[68] origin:064-gtp-channel-conf 00_426 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[69] origin:064-gtp-channel-conf 01_426 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[70] origin:064-gtp-channel-conf 00_427 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[71] origin:064-gtp-channel-conf 01_427 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[72] origin:064-gtp-channel-conf 00_428 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[73] origin:064-gtp-channel-conf 01_428 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[74] origin:064-gtp-channel-conf 00_429 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[75] origin:064-gtp-channel-conf 01_429 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[76] origin:064-gtp-channel-conf 00_430 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[77] origin:064-gtp-channel-conf 01_430 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[78] origin:064-gtp-channel-conf 00_431 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUAL_MASK[79] origin:064-gtp-channel-conf 01_431 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[0] origin:064-gtp-channel-conf 00_352 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[1] origin:064-gtp-channel-conf 01_352 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[2] origin:064-gtp-channel-conf 00_353 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[3] origin:064-gtp-channel-conf 01_353 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[4] origin:064-gtp-channel-conf 00_354 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[5] origin:064-gtp-channel-conf 01_354 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[6] origin:064-gtp-channel-conf 00_355 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[7] origin:064-gtp-channel-conf 01_355 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[8] origin:064-gtp-channel-conf 00_356 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[9] origin:064-gtp-channel-conf 01_356 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[10] origin:064-gtp-channel-conf 00_357 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[11] origin:064-gtp-channel-conf 01_357 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[12] origin:064-gtp-channel-conf 00_358 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[13] origin:064-gtp-channel-conf 01_358 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[14] origin:064-gtp-channel-conf 00_359 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[15] origin:064-gtp-channel-conf 01_359 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[16] origin:064-gtp-channel-conf 00_360 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[17] origin:064-gtp-channel-conf 01_360 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[18] origin:064-gtp-channel-conf 00_361 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[19] origin:064-gtp-channel-conf 01_361 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[20] origin:064-gtp-channel-conf 00_362 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[21] origin:064-gtp-channel-conf 01_362 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[22] origin:064-gtp-channel-conf 00_363 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[23] origin:064-gtp-channel-conf 01_363 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[24] origin:064-gtp-channel-conf 00_364 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[25] origin:064-gtp-channel-conf 01_364 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[26] origin:064-gtp-channel-conf 00_365 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[27] origin:064-gtp-channel-conf 01_365 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[28] origin:064-gtp-channel-conf 00_366 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[29] origin:064-gtp-channel-conf 01_366 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[30] origin:064-gtp-channel-conf 00_367 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[31] origin:064-gtp-channel-conf 01_367 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[32] origin:064-gtp-channel-conf 00_368 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[33] origin:064-gtp-channel-conf 01_368 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[34] origin:064-gtp-channel-conf 00_369 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[35] origin:064-gtp-channel-conf 01_369 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[36] origin:064-gtp-channel-conf 00_370 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[37] origin:064-gtp-channel-conf 01_370 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[38] origin:064-gtp-channel-conf 00_371 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[39] origin:064-gtp-channel-conf 01_371 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[40] origin:064-gtp-channel-conf 00_372 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[41] origin:064-gtp-channel-conf 01_372 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[42] origin:064-gtp-channel-conf 00_373 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[43] origin:064-gtp-channel-conf 01_373 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[44] origin:064-gtp-channel-conf 00_374 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[45] origin:064-gtp-channel-conf 01_374 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[46] origin:064-gtp-channel-conf 00_375 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[47] origin:064-gtp-channel-conf 01_375 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[48] origin:064-gtp-channel-conf 00_376 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[49] origin:064-gtp-channel-conf 01_376 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[50] origin:064-gtp-channel-conf 00_377 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[51] origin:064-gtp-channel-conf 01_377 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[52] origin:064-gtp-channel-conf 00_378 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[53] origin:064-gtp-channel-conf 01_378 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[54] origin:064-gtp-channel-conf 00_379 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[55] origin:064-gtp-channel-conf 01_379 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[56] origin:064-gtp-channel-conf 00_380 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[57] origin:064-gtp-channel-conf 01_380 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[58] origin:064-gtp-channel-conf 00_381 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[59] origin:064-gtp-channel-conf 01_381 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[60] origin:064-gtp-channel-conf 00_382 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[61] origin:064-gtp-channel-conf 01_382 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[62] origin:064-gtp-channel-conf 00_383 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[63] origin:064-gtp-channel-conf 01_383 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[64] origin:064-gtp-channel-conf 00_384 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[65] origin:064-gtp-channel-conf 01_384 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[66] origin:064-gtp-channel-conf 00_385 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[67] origin:064-gtp-channel-conf 01_385 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[68] origin:064-gtp-channel-conf 00_386 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[69] origin:064-gtp-channel-conf 01_386 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[70] origin:064-gtp-channel-conf 00_387 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[71] origin:064-gtp-channel-conf 01_387 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[72] origin:064-gtp-channel-conf 00_388 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[73] origin:064-gtp-channel-conf 01_388 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[74] origin:064-gtp-channel-conf 00_389 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[75] origin:064-gtp-channel-conf 01_389 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[76] origin:064-gtp-channel-conf 00_390 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[77] origin:064-gtp-channel-conf 01_390 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[78] origin:064-gtp-channel-conf 00_391 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_QUALIFIER[79] origin:064-gtp-channel-conf 01_391 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[0] origin:064-gtp-channel-conf 00_432 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[1] origin:064-gtp-channel-conf 01_432 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[2] origin:064-gtp-channel-conf 00_433 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[3] origin:064-gtp-channel-conf 01_433 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[4] origin:064-gtp-channel-conf 00_434 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[5] origin:064-gtp-channel-conf 01_434 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[6] origin:064-gtp-channel-conf 00_435 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[7] origin:064-gtp-channel-conf 01_435 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[8] origin:064-gtp-channel-conf 00_436 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[9] origin:064-gtp-channel-conf 01_436 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[10] origin:064-gtp-channel-conf 00_437 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[11] origin:064-gtp-channel-conf 01_437 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[12] origin:064-gtp-channel-conf 00_438 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[13] origin:064-gtp-channel-conf 01_438 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[14] origin:064-gtp-channel-conf 00_439 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[15] origin:064-gtp-channel-conf 01_439 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[16] origin:064-gtp-channel-conf 00_440 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[17] origin:064-gtp-channel-conf 01_440 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[18] origin:064-gtp-channel-conf 00_441 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[19] origin:064-gtp-channel-conf 01_441 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[20] origin:064-gtp-channel-conf 00_442 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[21] origin:064-gtp-channel-conf 01_442 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[22] origin:064-gtp-channel-conf 00_443 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[23] origin:064-gtp-channel-conf 01_443 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[24] origin:064-gtp-channel-conf 00_444 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[25] origin:064-gtp-channel-conf 01_444 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[26] origin:064-gtp-channel-conf 00_445 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[27] origin:064-gtp-channel-conf 01_445 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[28] origin:064-gtp-channel-conf 00_446 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[29] origin:064-gtp-channel-conf 01_446 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[30] origin:064-gtp-channel-conf 00_447 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[31] origin:064-gtp-channel-conf 01_447 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[32] origin:064-gtp-channel-conf 00_448 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[33] origin:064-gtp-channel-conf 01_448 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[34] origin:064-gtp-channel-conf 00_449 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[35] origin:064-gtp-channel-conf 01_449 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[36] origin:064-gtp-channel-conf 00_450 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[37] origin:064-gtp-channel-conf 01_450 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[38] origin:064-gtp-channel-conf 00_451 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[39] origin:064-gtp-channel-conf 01_451 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[40] origin:064-gtp-channel-conf 00_452 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[41] origin:064-gtp-channel-conf 01_452 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[42] origin:064-gtp-channel-conf 00_453 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[43] origin:064-gtp-channel-conf 01_453 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[44] origin:064-gtp-channel-conf 00_454 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[45] origin:064-gtp-channel-conf 01_454 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[46] origin:064-gtp-channel-conf 00_455 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[47] origin:064-gtp-channel-conf 01_455 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[48] origin:064-gtp-channel-conf 00_456 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[49] origin:064-gtp-channel-conf 01_456 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[50] origin:064-gtp-channel-conf 00_457 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[51] origin:064-gtp-channel-conf 01_457 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[52] origin:064-gtp-channel-conf 00_458 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[53] origin:064-gtp-channel-conf 01_458 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[54] origin:064-gtp-channel-conf 00_459 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[55] origin:064-gtp-channel-conf 01_459 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[56] origin:064-gtp-channel-conf 00_460 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[57] origin:064-gtp-channel-conf 01_460 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[58] origin:064-gtp-channel-conf 00_461 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[59] origin:064-gtp-channel-conf 01_461 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[60] origin:064-gtp-channel-conf 00_462 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[61] origin:064-gtp-channel-conf 01_462 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[62] origin:064-gtp-channel-conf 00_463 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[63] origin:064-gtp-channel-conf 01_463 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[64] origin:064-gtp-channel-conf 00_464 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[65] origin:064-gtp-channel-conf 01_464 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[66] origin:064-gtp-channel-conf 00_465 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[67] origin:064-gtp-channel-conf 01_465 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[68] origin:064-gtp-channel-conf 00_466 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[69] origin:064-gtp-channel-conf 01_466 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[70] origin:064-gtp-channel-conf 00_467 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[71] origin:064-gtp-channel-conf 01_467 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[72] origin:064-gtp-channel-conf 00_468 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[73] origin:064-gtp-channel-conf 01_468 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[74] origin:064-gtp-channel-conf 00_469 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[75] origin:064-gtp-channel-conf 01_469 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[76] origin:064-gtp-channel-conf 00_470 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[77] origin:064-gtp-channel-conf 01_470 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[78] origin:064-gtp-channel-conf 00_471 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_SDATA_MASK[79] origin:064-gtp-channel-conf 01_471 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_VERT_OFFSET[0] origin:064-gtp-channel-conf 00_472 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_VERT_OFFSET[1] origin:064-gtp-channel-conf 01_472 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_VERT_OFFSET[2] origin:064-gtp-channel-conf 00_473 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_VERT_OFFSET[3] origin:064-gtp-channel-conf 01_473 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_VERT_OFFSET[4] origin:064-gtp-channel-conf 00_474 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_VERT_OFFSET[5] origin:064-gtp-channel-conf 01_474 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_VERT_OFFSET[6] origin:064-gtp-channel-conf 00_475 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_VERT_OFFSET[7] origin:064-gtp-channel-conf 01_475 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ES_VERT_OFFSET[8] origin:064-gtp-channel-conf 00_476 -GTP_CHANNEL_2_MID_LEFT.GTPE2.FTS_DESKEW_SEQ_ENABLE[0] origin:064-gtp-channel-conf 00_662 -GTP_CHANNEL_2_MID_LEFT.GTPE2.FTS_DESKEW_SEQ_ENABLE[1] origin:064-gtp-channel-conf 01_662 -GTP_CHANNEL_2_MID_LEFT.GTPE2.FTS_DESKEW_SEQ_ENABLE[2] origin:064-gtp-channel-conf 00_663 -GTP_CHANNEL_2_MID_LEFT.GTPE2.FTS_DESKEW_SEQ_ENABLE[3] origin:064-gtp-channel-conf 01_663 -GTP_CHANNEL_2_MID_LEFT.GTPE2.FTS_LANE_DESKEW_CFG[0] origin:064-gtp-channel-conf 00_654 -GTP_CHANNEL_2_MID_LEFT.GTPE2.FTS_LANE_DESKEW_CFG[1] origin:064-gtp-channel-conf 01_654 -GTP_CHANNEL_2_MID_LEFT.GTPE2.FTS_LANE_DESKEW_CFG[2] origin:064-gtp-channel-conf 00_655 -GTP_CHANNEL_2_MID_LEFT.GTPE2.FTS_LANE_DESKEW_CFG[3] origin:064-gtp-channel-conf 01_655 -GTP_CHANNEL_2_MID_LEFT.GTPE2.FTS_LANE_DESKEW_EN origin:064-gtp-channel-conf 01_653 -GTP_CHANNEL_2_MID_LEFT.GTPE2.GEARBOX_MODE[0] origin:064-gtp-channel-conf 00_224 -GTP_CHANNEL_2_MID_LEFT.GTPE2.GEARBOX_MODE[1] origin:064-gtp-channel-conf 01_224 -GTP_CHANNEL_2_MID_LEFT.GTPE2.GEARBOX_MODE[2] origin:064-gtp-channel-conf 00_225 -GTP_CHANNEL_2_MID_LEFT.GTPE2.IN_USE origin:064-gtp-channel-conf 00_00 00_01 00_47 00_52 00_53 00_65 01_01 01_47 02_129 -GTP_CHANNEL_2_MID_LEFT.GTPE2.LOOPBACK_CFG[0] origin:064-gtp-channel-conf 02_20 -GTP_CHANNEL_2_MID_LEFT.GTPE2.OUTREFCLK_SEL_INV[0] origin:064-gtp-channel-conf 00_149 -GTP_CHANNEL_2_MID_LEFT.GTPE2.OUTREFCLK_SEL_INV[1] origin:064-gtp-channel-conf 01_149 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PCS_PCIE_EN origin:064-gtp-channel-conf 00_216 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PCS_RSVD_ATTR[0] origin:064-gtp-channel-conf 02_184 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PCS_RSVD_ATTR[1] origin:064-gtp-channel-conf 03_184 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PCS_RSVD_ATTR[2] origin:064-gtp-channel-conf 02_185 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PCS_RSVD_ATTR[3] origin:064-gtp-channel-conf 03_185 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PCS_RSVD_ATTR[4] origin:064-gtp-channel-conf 02_186 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PCS_RSVD_ATTR[5] origin:064-gtp-channel-conf 03_186 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PCS_RSVD_ATTR[6] origin:064-gtp-channel-conf 02_187 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PCS_RSVD_ATTR[7] origin:064-gtp-channel-conf 03_187 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PCS_RSVD_ATTR[8] origin:064-gtp-channel-conf 02_188 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PCS_RSVD_ATTR[9] origin:064-gtp-channel-conf 03_188 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PCS_RSVD_ATTR[10] origin:064-gtp-channel-conf 02_189 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PCS_RSVD_ATTR[11] origin:064-gtp-channel-conf 03_189 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PCS_RSVD_ATTR[12] origin:064-gtp-channel-conf 02_190 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PCS_RSVD_ATTR[13] origin:064-gtp-channel-conf 03_190 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PCS_RSVD_ATTR[14] origin:064-gtp-channel-conf 02_191 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PCS_RSVD_ATTR[15] origin:064-gtp-channel-conf 03_191 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PCS_RSVD_ATTR[16] origin:064-gtp-channel-conf 02_192 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PCS_RSVD_ATTR[17] origin:064-gtp-channel-conf 03_192 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PCS_RSVD_ATTR[18] origin:064-gtp-channel-conf 02_193 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PCS_RSVD_ATTR[19] origin:064-gtp-channel-conf 03_193 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PCS_RSVD_ATTR[20] origin:064-gtp-channel-conf 02_194 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PCS_RSVD_ATTR[21] origin:064-gtp-channel-conf 03_194 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PCS_RSVD_ATTR[22] origin:064-gtp-channel-conf 02_195 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PCS_RSVD_ATTR[23] origin:064-gtp-channel-conf 03_195 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PCS_RSVD_ATTR[24] origin:064-gtp-channel-conf 02_196 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PCS_RSVD_ATTR[25] origin:064-gtp-channel-conf 03_196 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PCS_RSVD_ATTR[26] origin:064-gtp-channel-conf 02_197 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PCS_RSVD_ATTR[27] origin:064-gtp-channel-conf 03_197 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PCS_RSVD_ATTR[28] origin:064-gtp-channel-conf 02_198 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PCS_RSVD_ATTR[29] origin:064-gtp-channel-conf 03_198 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PCS_RSVD_ATTR[30] origin:064-gtp-channel-conf 02_199 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PCS_RSVD_ATTR[31] origin:064-gtp-channel-conf 03_199 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PCS_RSVD_ATTR[32] origin:064-gtp-channel-conf 02_200 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PCS_RSVD_ATTR[33] origin:064-gtp-channel-conf 03_200 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PCS_RSVD_ATTR[34] origin:064-gtp-channel-conf 02_201 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PCS_RSVD_ATTR[35] origin:064-gtp-channel-conf 03_201 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PCS_RSVD_ATTR[36] origin:064-gtp-channel-conf 02_202 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PCS_RSVD_ATTR[37] origin:064-gtp-channel-conf 03_202 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PCS_RSVD_ATTR[38] origin:064-gtp-channel-conf 02_203 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PCS_RSVD_ATTR[39] origin:064-gtp-channel-conf 03_203 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PCS_RSVD_ATTR[40] origin:064-gtp-channel-conf 02_204 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PCS_RSVD_ATTR[41] origin:064-gtp-channel-conf 03_204 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PCS_RSVD_ATTR[42] origin:064-gtp-channel-conf 02_205 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PCS_RSVD_ATTR[43] origin:064-gtp-channel-conf 03_205 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PCS_RSVD_ATTR[44] origin:064-gtp-channel-conf 02_206 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PCS_RSVD_ATTR[45] origin:064-gtp-channel-conf 03_206 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PCS_RSVD_ATTR[46] origin:064-gtp-channel-conf 02_207 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PCS_RSVD_ATTR[47] origin:064-gtp-channel-conf 03_207 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PD_TRANS_TIME_FROM_P2[0] origin:064-gtp-channel-conf 01_216 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PD_TRANS_TIME_FROM_P2[1] origin:064-gtp-channel-conf 00_217 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PD_TRANS_TIME_FROM_P2[2] origin:064-gtp-channel-conf 01_217 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PD_TRANS_TIME_FROM_P2[3] origin:064-gtp-channel-conf 00_218 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PD_TRANS_TIME_FROM_P2[4] origin:064-gtp-channel-conf 01_218 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PD_TRANS_TIME_FROM_P2[5] origin:064-gtp-channel-conf 00_219 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PD_TRANS_TIME_FROM_P2[6] origin:064-gtp-channel-conf 01_219 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PD_TRANS_TIME_FROM_P2[7] origin:064-gtp-channel-conf 00_220 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PD_TRANS_TIME_FROM_P2[8] origin:064-gtp-channel-conf 01_220 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PD_TRANS_TIME_FROM_P2[9] origin:064-gtp-channel-conf 00_221 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PD_TRANS_TIME_FROM_P2[10] origin:064-gtp-channel-conf 01_221 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PD_TRANS_TIME_FROM_P2[11] origin:064-gtp-channel-conf 00_222 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PD_TRANS_TIME_NONE_P2[0] origin:064-gtp-channel-conf 00_208 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PD_TRANS_TIME_NONE_P2[1] origin:064-gtp-channel-conf 01_208 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PD_TRANS_TIME_NONE_P2[2] origin:064-gtp-channel-conf 00_209 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PD_TRANS_TIME_NONE_P2[3] origin:064-gtp-channel-conf 01_209 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PD_TRANS_TIME_NONE_P2[4] origin:064-gtp-channel-conf 00_210 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PD_TRANS_TIME_NONE_P2[5] origin:064-gtp-channel-conf 01_210 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PD_TRANS_TIME_NONE_P2[6] origin:064-gtp-channel-conf 00_211 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PD_TRANS_TIME_NONE_P2[7] origin:064-gtp-channel-conf 01_211 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PD_TRANS_TIME_TO_P2[0] origin:064-gtp-channel-conf 00_212 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PD_TRANS_TIME_TO_P2[1] origin:064-gtp-channel-conf 01_212 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PD_TRANS_TIME_TO_P2[2] origin:064-gtp-channel-conf 00_213 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PD_TRANS_TIME_TO_P2[3] origin:064-gtp-channel-conf 01_213 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PD_TRANS_TIME_TO_P2[4] origin:064-gtp-channel-conf 00_214 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PD_TRANS_TIME_TO_P2[5] origin:064-gtp-channel-conf 01_214 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PD_TRANS_TIME_TO_P2[6] origin:064-gtp-channel-conf 00_215 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PD_TRANS_TIME_TO_P2[7] origin:064-gtp-channel-conf 01_215 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PMA_LOOPBACK_CFG[0] origin:064-gtp-channel-conf 01_207 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PMA_RSV[0] origin:064-gtp-channel-conf 02_520 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PMA_RSV[1] origin:064-gtp-channel-conf 03_520 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PMA_RSV[2] origin:064-gtp-channel-conf 02_521 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PMA_RSV[3] origin:064-gtp-channel-conf 03_521 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PMA_RSV[4] origin:064-gtp-channel-conf 02_522 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PMA_RSV[5] origin:064-gtp-channel-conf 03_522 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PMA_RSV[6] origin:064-gtp-channel-conf 02_523 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PMA_RSV[7] origin:064-gtp-channel-conf 03_523 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PMA_RSV[8] origin:064-gtp-channel-conf 02_524 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PMA_RSV[9] origin:064-gtp-channel-conf 03_524 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PMA_RSV[10] origin:064-gtp-channel-conf 02_525 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PMA_RSV[11] origin:064-gtp-channel-conf 03_525 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PMA_RSV[12] origin:064-gtp-channel-conf 02_526 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PMA_RSV[13] origin:064-gtp-channel-conf 03_526 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PMA_RSV[14] origin:064-gtp-channel-conf 02_527 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PMA_RSV[15] origin:064-gtp-channel-conf 03_527 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PMA_RSV[16] origin:064-gtp-channel-conf 02_528 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PMA_RSV[17] origin:064-gtp-channel-conf 03_528 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PMA_RSV[18] origin:064-gtp-channel-conf 02_529 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PMA_RSV[19] origin:064-gtp-channel-conf 03_529 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PMA_RSV[20] origin:064-gtp-channel-conf 02_530 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PMA_RSV[21] origin:064-gtp-channel-conf 03_530 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PMA_RSV[22] origin:064-gtp-channel-conf 02_531 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PMA_RSV[23] origin:064-gtp-channel-conf 03_531 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PMA_RSV[24] origin:064-gtp-channel-conf 02_532 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PMA_RSV[25] origin:064-gtp-channel-conf 03_532 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PMA_RSV[26] origin:064-gtp-channel-conf 02_533 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PMA_RSV[27] origin:064-gtp-channel-conf 03_533 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PMA_RSV[28] origin:064-gtp-channel-conf 02_534 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PMA_RSV[29] origin:064-gtp-channel-conf 03_534 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PMA_RSV[30] origin:064-gtp-channel-conf 02_535 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PMA_RSV[31] origin:064-gtp-channel-conf 03_535 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PMA_RSV2[0] origin:064-gtp-channel-conf 02_336 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PMA_RSV2[1] origin:064-gtp-channel-conf 03_336 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PMA_RSV2[2] origin:064-gtp-channel-conf 02_337 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PMA_RSV2[3] origin:064-gtp-channel-conf 03_337 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PMA_RSV2[4] origin:064-gtp-channel-conf 02_338 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PMA_RSV2[5] origin:064-gtp-channel-conf 03_338 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PMA_RSV2[6] origin:064-gtp-channel-conf 02_339 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PMA_RSV2[7] origin:064-gtp-channel-conf 03_339 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PMA_RSV2[8] origin:064-gtp-channel-conf 02_340 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PMA_RSV2[9] origin:064-gtp-channel-conf 03_340 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PMA_RSV2[10] origin:064-gtp-channel-conf 02_341 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PMA_RSV2[11] origin:064-gtp-channel-conf 03_341 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PMA_RSV2[12] origin:064-gtp-channel-conf 02_342 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PMA_RSV2[13] origin:064-gtp-channel-conf 03_342 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PMA_RSV2[14] origin:064-gtp-channel-conf 02_343 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PMA_RSV2[15] origin:064-gtp-channel-conf 03_343 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PMA_RSV2[16] origin:064-gtp-channel-conf 02_344 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PMA_RSV2[17] origin:064-gtp-channel-conf 03_344 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PMA_RSV2[18] origin:064-gtp-channel-conf 02_345 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PMA_RSV2[19] origin:064-gtp-channel-conf 03_345 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PMA_RSV2[20] origin:064-gtp-channel-conf 02_346 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PMA_RSV2[21] origin:064-gtp-channel-conf 03_346 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PMA_RSV2[22] origin:064-gtp-channel-conf 02_347 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PMA_RSV2[23] origin:064-gtp-channel-conf 03_347 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PMA_RSV2[24] origin:064-gtp-channel-conf 02_348 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PMA_RSV2[25] origin:064-gtp-channel-conf 03_348 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PMA_RSV2[26] origin:064-gtp-channel-conf 02_349 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PMA_RSV2[27] origin:064-gtp-channel-conf 03_349 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PMA_RSV2[28] origin:064-gtp-channel-conf 02_350 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PMA_RSV2[29] origin:064-gtp-channel-conf 03_350 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PMA_RSV2[30] origin:064-gtp-channel-conf 02_351 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PMA_RSV2[31] origin:064-gtp-channel-conf 03_351 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PMA_RSV3[0] origin:064-gtp-channel-conf 02_288 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PMA_RSV3[1] origin:064-gtp-channel-conf 03_288 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PMA_RSV4[0] origin:064-gtp-channel-conf 02_156 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PMA_RSV4[1] origin:064-gtp-channel-conf 03_156 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PMA_RSV4[2] origin:064-gtp-channel-conf 02_157 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PMA_RSV4[3] origin:064-gtp-channel-conf 03_157 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PMA_RSV5[0] origin:064-gtp-channel-conf 03_159 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PMA_RSV6[0] origin:064-gtp-channel-conf 02_303 -GTP_CHANNEL_2_MID_LEFT.GTPE2.PMA_RSV7[0] origin:064-gtp-channel-conf 03_303 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_BIAS_CFG[0] origin:064-gtp-channel-conf 02_112 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_BIAS_CFG[1] origin:064-gtp-channel-conf 03_112 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_BIAS_CFG[2] origin:064-gtp-channel-conf 02_113 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_BIAS_CFG[3] origin:064-gtp-channel-conf 03_113 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_BIAS_CFG[4] origin:064-gtp-channel-conf 02_114 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_BIAS_CFG[5] origin:064-gtp-channel-conf 03_114 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_BIAS_CFG[6] origin:064-gtp-channel-conf 02_115 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_BIAS_CFG[7] origin:064-gtp-channel-conf 03_115 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_BIAS_CFG[8] origin:064-gtp-channel-conf 02_116 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_BIAS_CFG[9] origin:064-gtp-channel-conf 03_116 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_BIAS_CFG[10] origin:064-gtp-channel-conf 02_117 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_BIAS_CFG[11] origin:064-gtp-channel-conf 03_117 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_BIAS_CFG[12] origin:064-gtp-channel-conf 02_118 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_BIAS_CFG[13] origin:064-gtp-channel-conf 03_118 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_BIAS_CFG[14] origin:064-gtp-channel-conf 02_119 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_BIAS_CFG[15] origin:064-gtp-channel-conf 03_119 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_BUFFER_CFG[0] origin:064-gtp-channel-conf 02_536 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_BUFFER_CFG[1] origin:064-gtp-channel-conf 03_536 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_BUFFER_CFG[2] origin:064-gtp-channel-conf 02_537 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_BUFFER_CFG[3] origin:064-gtp-channel-conf 03_537 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_BUFFER_CFG[4] origin:064-gtp-channel-conf 02_538 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_BUFFER_CFG[5] origin:064-gtp-channel-conf 03_538 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_CLKMUX_EN[0] origin:064-gtp-channel-conf 02_128 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_CM_SEL[0] origin:064-gtp-channel-conf 00_138 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_CM_SEL[1] origin:064-gtp-channel-conf 01_138 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_CM_TRIM[0] origin:064-gtp-channel-conf 02_304 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_CM_TRIM[1] origin:064-gtp-channel-conf 03_304 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_CM_TRIM[2] origin:064-gtp-channel-conf 02_305 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_CM_TRIM[3] origin:064-gtp-channel-conf 03_305 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_DATA_WIDTH[0] origin:064-gtp-channel-conf 01_141 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_DATA_WIDTH[1] origin:064-gtp-channel-conf 00_142 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_DATA_WIDTH[2] origin:064-gtp-channel-conf 01_142 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_DDI_SEL[0] origin:064-gtp-channel-conf 00_696 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_DDI_SEL[1] origin:064-gtp-channel-conf 01_696 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_DDI_SEL[2] origin:064-gtp-channel-conf 00_697 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_DDI_SEL[3] origin:064-gtp-channel-conf 01_697 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_DDI_SEL[4] origin:064-gtp-channel-conf 00_698 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_DDI_SEL[5] origin:064-gtp-channel-conf 01_698 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_DEBUG_CFG[0] origin:064-gtp-channel-conf 02_616 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_DEBUG_CFG[1] origin:064-gtp-channel-conf 03_616 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_DEBUG_CFG[2] origin:064-gtp-channel-conf 02_617 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_DEBUG_CFG[3] origin:064-gtp-channel-conf 03_617 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_DEBUG_CFG[4] origin:064-gtp-channel-conf 02_618 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_DEBUG_CFG[5] origin:064-gtp-channel-conf 03_618 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_DEBUG_CFG[6] origin:064-gtp-channel-conf 02_619 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_DEBUG_CFG[7] origin:064-gtp-channel-conf 03_619 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_DEBUG_CFG[8] origin:064-gtp-channel-conf 02_620 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_DEBUG_CFG[9] origin:064-gtp-channel-conf 03_620 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_DEBUG_CFG[10] origin:064-gtp-channel-conf 02_621 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_DEBUG_CFG[11] origin:064-gtp-channel-conf 03_621 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_DEBUG_CFG[12] origin:064-gtp-channel-conf 02_622 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_DEBUG_CFG[13] origin:064-gtp-channel-conf 03_622 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_DEFER_RESET_BUF_EN origin:064-gtp-channel-conf 02_552 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_DISPERR_SEQ_MATCH origin:064-gtp-channel-conf 01_495 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_OS_CFG[0] origin:064-gtp-channel-conf 00_288 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_OS_CFG[1] origin:064-gtp-channel-conf 01_288 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_OS_CFG[2] origin:064-gtp-channel-conf 00_289 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_OS_CFG[3] origin:064-gtp-channel-conf 01_289 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_OS_CFG[4] origin:064-gtp-channel-conf 00_290 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_OS_CFG[5] origin:064-gtp-channel-conf 01_290 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_OS_CFG[6] origin:064-gtp-channel-conf 00_291 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_OS_CFG[7] origin:064-gtp-channel-conf 01_291 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_OS_CFG[8] origin:064-gtp-channel-conf 00_292 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_OS_CFG[9] origin:064-gtp-channel-conf 01_292 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_OS_CFG[10] origin:064-gtp-channel-conf 00_293 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_OS_CFG[11] origin:064-gtp-channel-conf 01_293 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_OS_CFG[12] origin:064-gtp-channel-conf 00_294 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_SIG_VALID_DLY[0] origin:064-gtp-channel-conf 00_524 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_SIG_VALID_DLY[1] origin:064-gtp-channel-conf 01_524 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_SIG_VALID_DLY[2] origin:064-gtp-channel-conf 00_525 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_SIG_VALID_DLY[3] origin:064-gtp-channel-conf 01_525 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_SIG_VALID_DLY[4] origin:064-gtp-channel-conf 00_526 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_XCLK_SEL.RXUSR origin:064-gtp-channel-conf 00_143 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_CLK25_DIV[0] origin:064-gtp-channel-conf 00_139 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_CLK25_DIV[1] origin:064-gtp-channel-conf 01_139 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_CLK25_DIV[2] origin:064-gtp-channel-conf 00_140 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_CLK25_DIV[3] origin:064-gtp-channel-conf 01_140 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RX_CLK25_DIV[4] origin:064-gtp-channel-conf 00_141 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXBUF_ADDR_MODE.FAST origin:064-gtp-channel-conf 03_555 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXBUF_EIDLE_HI_CNT[0] origin:064-gtp-channel-conf 02_558 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXBUF_EIDLE_HI_CNT[1] origin:064-gtp-channel-conf 03_558 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXBUF_EIDLE_HI_CNT[2] origin:064-gtp-channel-conf 02_559 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXBUF_EIDLE_HI_CNT[3] origin:064-gtp-channel-conf 03_559 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXBUF_EIDLE_LO_CNT[0] origin:064-gtp-channel-conf 02_556 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXBUF_EIDLE_LO_CNT[1] origin:064-gtp-channel-conf 03_556 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXBUF_EIDLE_LO_CNT[2] origin:064-gtp-channel-conf 02_557 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXBUF_EIDLE_LO_CNT[3] origin:064-gtp-channel-conf 03_557 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXBUF_EN origin:064-gtp-channel-conf 02_11 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXBUF_RESET_ON_CB_CHANGE origin:064-gtp-channel-conf 02_560 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXBUF_RESET_ON_COMMAALIGN origin:064-gtp-channel-conf 02_561 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXBUF_RESET_ON_EIDLE origin:064-gtp-channel-conf 02_547 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXBUF_RESET_ON_RATE_CHANGE origin:064-gtp-channel-conf 03_560 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXBUF_THRESH_OVFLW[0] origin:064-gtp-channel-conf 03_552 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXBUF_THRESH_OVFLW[1] origin:064-gtp-channel-conf 02_553 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXBUF_THRESH_OVFLW[2] origin:064-gtp-channel-conf 03_553 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXBUF_THRESH_OVFLW[3] origin:064-gtp-channel-conf 02_554 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXBUF_THRESH_OVFLW[4] origin:064-gtp-channel-conf 03_554 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXBUF_THRESH_OVFLW[5] origin:064-gtp-channel-conf 02_555 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXBUF_THRESH_OVRD origin:064-gtp-channel-conf 02_548 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXBUF_THRESH_UNDFLW[0] origin:064-gtp-channel-conf 02_544 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXBUF_THRESH_UNDFLW[1] origin:064-gtp-channel-conf 03_544 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXBUF_THRESH_UNDFLW[2] origin:064-gtp-channel-conf 02_545 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXBUF_THRESH_UNDFLW[3] origin:064-gtp-channel-conf 03_545 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXBUF_THRESH_UNDFLW[4] origin:064-gtp-channel-conf 02_546 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXBUF_THRESH_UNDFLW[5] origin:064-gtp-channel-conf 03_546 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXBUFRESET_TIME[0] origin:064-gtp-channel-conf 01_101 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXBUFRESET_TIME[1] origin:064-gtp-channel-conf 00_102 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXBUFRESET_TIME[2] origin:064-gtp-channel-conf 01_102 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXBUFRESET_TIME[3] origin:064-gtp-channel-conf 00_103 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXBUFRESET_TIME[4] origin:064-gtp-channel-conf 01_103 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[0] origin:064-gtp-channel-conf 02_640 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[1] origin:064-gtp-channel-conf 03_640 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[2] origin:064-gtp-channel-conf 02_641 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[3] origin:064-gtp-channel-conf 03_641 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[4] origin:064-gtp-channel-conf 02_642 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[5] origin:064-gtp-channel-conf 03_642 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[6] origin:064-gtp-channel-conf 02_643 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[7] origin:064-gtp-channel-conf 03_643 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[8] origin:064-gtp-channel-conf 02_644 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[9] origin:064-gtp-channel-conf 03_644 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[10] origin:064-gtp-channel-conf 02_645 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[11] origin:064-gtp-channel-conf 03_645 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[12] origin:064-gtp-channel-conf 02_646 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[13] origin:064-gtp-channel-conf 03_646 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[14] origin:064-gtp-channel-conf 02_647 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[15] origin:064-gtp-channel-conf 03_647 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[16] origin:064-gtp-channel-conf 02_648 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[17] origin:064-gtp-channel-conf 03_648 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[18] origin:064-gtp-channel-conf 02_649 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[19] origin:064-gtp-channel-conf 03_649 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[20] origin:064-gtp-channel-conf 02_650 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[21] origin:064-gtp-channel-conf 03_650 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[22] origin:064-gtp-channel-conf 02_651 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[23] origin:064-gtp-channel-conf 03_651 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[24] origin:064-gtp-channel-conf 02_652 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[25] origin:064-gtp-channel-conf 03_652 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[26] origin:064-gtp-channel-conf 02_653 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[27] origin:064-gtp-channel-conf 03_653 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[28] origin:064-gtp-channel-conf 02_654 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[29] origin:064-gtp-channel-conf 03_654 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[30] origin:064-gtp-channel-conf 02_655 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[31] origin:064-gtp-channel-conf 03_655 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[32] origin:064-gtp-channel-conf 02_656 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[33] origin:064-gtp-channel-conf 03_656 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[34] origin:064-gtp-channel-conf 02_657 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[35] origin:064-gtp-channel-conf 03_657 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[36] origin:064-gtp-channel-conf 02_658 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[37] origin:064-gtp-channel-conf 03_658 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[38] origin:064-gtp-channel-conf 02_659 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[39] origin:064-gtp-channel-conf 03_659 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[40] origin:064-gtp-channel-conf 02_660 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[41] origin:064-gtp-channel-conf 03_660 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[42] origin:064-gtp-channel-conf 02_661 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[43] origin:064-gtp-channel-conf 03_661 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[44] origin:064-gtp-channel-conf 02_662 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[45] origin:064-gtp-channel-conf 03_662 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[46] origin:064-gtp-channel-conf 02_663 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[47] origin:064-gtp-channel-conf 03_663 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[48] origin:064-gtp-channel-conf 02_664 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[49] origin:064-gtp-channel-conf 03_664 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[50] origin:064-gtp-channel-conf 02_665 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[51] origin:064-gtp-channel-conf 03_665 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[52] origin:064-gtp-channel-conf 02_666 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[53] origin:064-gtp-channel-conf 03_666 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[54] origin:064-gtp-channel-conf 02_667 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[55] origin:064-gtp-channel-conf 03_667 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[56] origin:064-gtp-channel-conf 02_668 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[57] origin:064-gtp-channel-conf 03_668 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[58] origin:064-gtp-channel-conf 02_669 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[59] origin:064-gtp-channel-conf 03_669 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[60] origin:064-gtp-channel-conf 02_670 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[61] origin:064-gtp-channel-conf 03_670 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[62] origin:064-gtp-channel-conf 02_671 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[63] origin:064-gtp-channel-conf 03_671 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[64] origin:064-gtp-channel-conf 02_672 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[65] origin:064-gtp-channel-conf 03_672 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[66] origin:064-gtp-channel-conf 02_673 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[67] origin:064-gtp-channel-conf 03_673 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[68] origin:064-gtp-channel-conf 02_674 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[69] origin:064-gtp-channel-conf 03_674 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[70] origin:064-gtp-channel-conf 02_675 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[71] origin:064-gtp-channel-conf 03_675 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[72] origin:064-gtp-channel-conf 02_676 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[73] origin:064-gtp-channel-conf 03_676 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[74] origin:064-gtp-channel-conf 02_677 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[75] origin:064-gtp-channel-conf 03_677 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[76] origin:064-gtp-channel-conf 02_678 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[77] origin:064-gtp-channel-conf 03_678 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[78] origin:064-gtp-channel-conf 02_679 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[79] origin:064-gtp-channel-conf 03_679 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[80] origin:064-gtp-channel-conf 02_680 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[81] origin:064-gtp-channel-conf 03_680 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_CFG[82] origin:064-gtp-channel-conf 02_681 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_FR_RESET_ON_EIDLE[0] origin:064-gtp-channel-conf 02_638 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_HOLD_DURING_EIDLE[0] origin:064-gtp-channel-conf 03_637 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_LOCK_CFG[0] origin:064-gtp-channel-conf 02_632 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_LOCK_CFG[1] origin:064-gtp-channel-conf 03_632 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_LOCK_CFG[2] origin:064-gtp-channel-conf 02_633 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_LOCK_CFG[3] origin:064-gtp-channel-conf 03_633 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_LOCK_CFG[4] origin:064-gtp-channel-conf 02_634 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_LOCK_CFG[5] origin:064-gtp-channel-conf 03_634 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDR_PH_RESET_ON_EIDLE[0] origin:064-gtp-channel-conf 03_638 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDRFREQRESET_TIME[0] origin:064-gtp-channel-conf 01_106 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDRFREQRESET_TIME[1] origin:064-gtp-channel-conf 00_107 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDRFREQRESET_TIME[2] origin:064-gtp-channel-conf 01_107 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDRFREQRESET_TIME[3] origin:064-gtp-channel-conf 00_108 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDRFREQRESET_TIME[4] origin:064-gtp-channel-conf 01_108 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDRPHRESET_TIME[0] origin:064-gtp-channel-conf 00_109 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDRPHRESET_TIME[1] origin:064-gtp-channel-conf 01_109 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDRPHRESET_TIME[2] origin:064-gtp-channel-conf 00_110 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDRPHRESET_TIME[3] origin:064-gtp-channel-conf 01_110 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXCDRPHRESET_TIME[4] origin:064-gtp-channel-conf 00_111 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXDLY_CFG[0] origin:064-gtp-channel-conf 00_680 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXDLY_CFG[1] origin:064-gtp-channel-conf 01_680 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXDLY_CFG[2] origin:064-gtp-channel-conf 00_681 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXDLY_CFG[3] origin:064-gtp-channel-conf 01_681 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXDLY_CFG[4] origin:064-gtp-channel-conf 00_682 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXDLY_CFG[5] origin:064-gtp-channel-conf 01_682 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXDLY_CFG[6] origin:064-gtp-channel-conf 00_683 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXDLY_CFG[7] origin:064-gtp-channel-conf 01_683 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXDLY_CFG[8] origin:064-gtp-channel-conf 00_684 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXDLY_CFG[9] origin:064-gtp-channel-conf 01_684 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXDLY_CFG[10] origin:064-gtp-channel-conf 00_685 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXDLY_CFG[11] origin:064-gtp-channel-conf 01_685 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXDLY_CFG[12] origin:064-gtp-channel-conf 00_686 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXDLY_CFG[13] origin:064-gtp-channel-conf 01_686 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXDLY_CFG[14] origin:064-gtp-channel-conf 00_687 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXDLY_CFG[15] origin:064-gtp-channel-conf 01_687 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXDLY_LCFG[0] origin:064-gtp-channel-conf 02_576 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXDLY_LCFG[1] origin:064-gtp-channel-conf 03_576 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXDLY_LCFG[2] origin:064-gtp-channel-conf 02_577 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXDLY_LCFG[3] origin:064-gtp-channel-conf 03_577 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXDLY_LCFG[4] origin:064-gtp-channel-conf 02_578 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXDLY_LCFG[5] origin:064-gtp-channel-conf 03_578 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXDLY_LCFG[6] origin:064-gtp-channel-conf 02_579 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXDLY_LCFG[7] origin:064-gtp-channel-conf 03_579 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXDLY_LCFG[8] origin:064-gtp-channel-conf 02_580 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXDLY_TAP_CFG[0] origin:064-gtp-channel-conf 00_672 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXDLY_TAP_CFG[1] origin:064-gtp-channel-conf 01_672 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXDLY_TAP_CFG[2] origin:064-gtp-channel-conf 00_673 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXDLY_TAP_CFG[3] origin:064-gtp-channel-conf 01_673 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXDLY_TAP_CFG[4] origin:064-gtp-channel-conf 00_674 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXDLY_TAP_CFG[5] origin:064-gtp-channel-conf 01_674 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXDLY_TAP_CFG[6] origin:064-gtp-channel-conf 00_675 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXDLY_TAP_CFG[7] origin:064-gtp-channel-conf 01_675 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXDLY_TAP_CFG[8] origin:064-gtp-channel-conf 00_676 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXDLY_TAP_CFG[9] origin:064-gtp-channel-conf 01_676 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXDLY_TAP_CFG[10] origin:064-gtp-channel-conf 00_677 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXDLY_TAP_CFG[11] origin:064-gtp-channel-conf 01_677 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXDLY_TAP_CFG[12] origin:064-gtp-channel-conf 00_678 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXDLY_TAP_CFG[13] origin:064-gtp-channel-conf 01_678 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXDLY_TAP_CFG[14] origin:064-gtp-channel-conf 00_679 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXDLY_TAP_CFG[15] origin:064-gtp-channel-conf 01_679 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXGEARBOX_EN origin:064-gtp-channel-conf 01_607 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXISCANRESET_TIME[0] origin:064-gtp-channel-conf 01_123 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXISCANRESET_TIME[1] origin:064-gtp-channel-conf 00_124 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXISCANRESET_TIME[2] origin:064-gtp-channel-conf 01_124 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXISCANRESET_TIME[3] origin:064-gtp-channel-conf 00_125 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXISCANRESET_TIME[4] origin:064-gtp-channel-conf 01_125 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPM_BIAS_STARTUP_DISABLE[0] origin:064-gtp-channel-conf 03_391 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPM_CFG[0] origin:064-gtp-channel-conf 02_328 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPM_CFG[1] origin:064-gtp-channel-conf 03_328 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPM_CFG[2] origin:064-gtp-channel-conf 02_329 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPM_CFG[3] origin:064-gtp-channel-conf 03_329 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPM_CM_CFG[0] origin:064-gtp-channel-conf 02_430 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPM_GC_CFG[0] origin:064-gtp-channel-conf 02_432 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPM_GC_CFG[1] origin:064-gtp-channel-conf 03_432 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPM_GC_CFG[2] origin:064-gtp-channel-conf 02_433 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPM_GC_CFG[3] origin:064-gtp-channel-conf 03_433 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPM_GC_CFG[4] origin:064-gtp-channel-conf 02_434 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPM_GC_CFG[5] origin:064-gtp-channel-conf 03_434 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPM_GC_CFG[6] origin:064-gtp-channel-conf 02_435 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPM_GC_CFG[7] origin:064-gtp-channel-conf 03_435 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPM_GC_CFG[8] origin:064-gtp-channel-conf 02_436 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPM_GC_CFG2[0] origin:064-gtp-channel-conf 03_442 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPM_GC_CFG2[1] origin:064-gtp-channel-conf 02_443 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPM_GC_CFG2[2] origin:064-gtp-channel-conf 03_443 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPM_HF_CFG[0] origin:064-gtp-channel-conf 00_336 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPM_HF_CFG[1] origin:064-gtp-channel-conf 01_336 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPM_HF_CFG[2] origin:064-gtp-channel-conf 00_337 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPM_HF_CFG[3] origin:064-gtp-channel-conf 01_337 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPM_HF_CFG[4] origin:064-gtp-channel-conf 00_338 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPM_HF_CFG[5] origin:064-gtp-channel-conf 01_338 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPM_HF_CFG[6] origin:064-gtp-channel-conf 00_339 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPM_HF_CFG[7] origin:064-gtp-channel-conf 01_339 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPM_HF_CFG[8] origin:064-gtp-channel-conf 00_340 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPM_HF_CFG[9] origin:064-gtp-channel-conf 01_340 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPM_HF_CFG[10] origin:064-gtp-channel-conf 00_341 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPM_HF_CFG[11] origin:064-gtp-channel-conf 01_341 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPM_HF_CFG[12] origin:064-gtp-channel-conf 00_342 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPM_HF_CFG[13] origin:064-gtp-channel-conf 01_342 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPM_HF_CFG2[0] origin:064-gtp-channel-conf 02_424 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPM_HF_CFG2[1] origin:064-gtp-channel-conf 03_424 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPM_HF_CFG2[2] origin:064-gtp-channel-conf 02_425 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPM_HF_CFG2[3] origin:064-gtp-channel-conf 03_425 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPM_HF_CFG2[4] origin:064-gtp-channel-conf 02_426 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPM_HF_CFG3[0] origin:064-gtp-channel-conf 03_389 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPM_HF_CFG3[1] origin:064-gtp-channel-conf 02_390 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPM_HF_CFG3[2] origin:064-gtp-channel-conf 03_390 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPM_HF_CFG3[3] origin:064-gtp-channel-conf 02_391 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPM_HOLD_DURING_EIDLE[0] origin:064-gtp-channel-conf 00_247 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPM_INCM_CFG[0] origin:064-gtp-channel-conf 02_439 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPM_IPCM_CFG[0] origin:064-gtp-channel-conf 03_439 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPM_LF_CFG[0] origin:064-gtp-channel-conf 00_344 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPM_LF_CFG[1] origin:064-gtp-channel-conf 01_344 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPM_LF_CFG[2] origin:064-gtp-channel-conf 00_345 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPM_LF_CFG[3] origin:064-gtp-channel-conf 01_345 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPM_LF_CFG[4] origin:064-gtp-channel-conf 00_346 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPM_LF_CFG[5] origin:064-gtp-channel-conf 01_346 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPM_LF_CFG[6] origin:064-gtp-channel-conf 00_347 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPM_LF_CFG[7] origin:064-gtp-channel-conf 01_347 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPM_LF_CFG[8] origin:064-gtp-channel-conf 00_348 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPM_LF_CFG[9] origin:064-gtp-channel-conf 01_348 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPM_LF_CFG[10] origin:064-gtp-channel-conf 00_349 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPM_LF_CFG[11] origin:064-gtp-channel-conf 01_349 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPM_LF_CFG[12] origin:064-gtp-channel-conf 00_350 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPM_LF_CFG[13] origin:064-gtp-channel-conf 01_350 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPM_LF_CFG[14] origin:064-gtp-channel-conf 00_351 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPM_LF_CFG[15] origin:064-gtp-channel-conf 01_351 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPM_LF_CFG[16] origin:064-gtp-channel-conf 00_343 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPM_LF_CFG[17] origin:064-gtp-channel-conf 01_343 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPM_LF_CFG2[0] origin:064-gtp-channel-conf 03_426 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPM_LF_CFG2[1] origin:064-gtp-channel-conf 02_427 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPM_LF_CFG2[2] origin:064-gtp-channel-conf 03_427 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPM_LF_CFG2[3] origin:064-gtp-channel-conf 02_428 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPM_LF_CFG2[4] origin:064-gtp-channel-conf 03_428 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPM_OSINT_CFG[0] origin:064-gtp-channel-conf 02_440 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPM_OSINT_CFG[1] origin:064-gtp-channel-conf 03_440 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPM_OSINT_CFG[2] origin:064-gtp-channel-conf 02_441 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPM_CFG1[0] origin:064-gtp-channel-conf 02_330 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPMRESET_TIME[0] origin:064-gtp-channel-conf 00_112 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPMRESET_TIME[1] origin:064-gtp-channel-conf 01_112 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPMRESET_TIME[2] origin:064-gtp-channel-conf 00_113 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPMRESET_TIME[3] origin:064-gtp-channel-conf 01_113 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPMRESET_TIME[4] origin:064-gtp-channel-conf 00_114 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPMRESET_TIME[5] origin:064-gtp-channel-conf 01_114 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXLPMRESET_TIME[6] origin:064-gtp-channel-conf 00_115 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXOOB_CFG[0] origin:064-gtp-channel-conf 00_144 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXOOB_CFG[1] origin:064-gtp-channel-conf 01_144 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXOOB_CFG[2] origin:064-gtp-channel-conf 00_145 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXOOB_CFG[3] origin:064-gtp-channel-conf 01_145 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXOOB_CFG[4] origin:064-gtp-channel-conf 00_146 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXOOB_CFG[5] origin:064-gtp-channel-conf 01_146 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXOOB_CFG[6] origin:064-gtp-channel-conf 00_147 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXOOB_CLK_CFG.FABRIC origin:064-gtp-channel-conf 03_129 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXOSCALRESET_TIME[0] origin:064-gtp-channel-conf 00_187 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXOSCALRESET_TIME[1] origin:064-gtp-channel-conf 01_187 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXOSCALRESET_TIME[2] origin:064-gtp-channel-conf 00_188 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXOSCALRESET_TIME[3] origin:064-gtp-channel-conf 01_188 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXOSCALRESET_TIME[4] origin:064-gtp-channel-conf 00_189 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXOSCALRESET_TIMEOUT[0] origin:064-gtp-channel-conf 01_189 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXOSCALRESET_TIMEOUT[1] origin:064-gtp-channel-conf 00_190 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXOSCALRESET_TIMEOUT[2] origin:064-gtp-channel-conf 01_190 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXOSCALRESET_TIMEOUT[3] origin:064-gtp-channel-conf 00_191 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXOSCALRESET_TIMEOUT[4] origin:064-gtp-channel-conf 01_191 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXOUT_DIV[0] origin:064-gtp-channel-conf 02_384 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXOUT_DIV[1] origin:064-gtp-channel-conf 03_384 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXPCSRESET_TIME[0] origin:064-gtp-channel-conf 01_115 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXPCSRESET_TIME[1] origin:064-gtp-channel-conf 00_116 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXPCSRESET_TIME[2] origin:064-gtp-channel-conf 01_116 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXPCSRESET_TIME[3] origin:064-gtp-channel-conf 00_117 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXPCSRESET_TIME[4] origin:064-gtp-channel-conf 01_117 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXPH_CFG[0] origin:064-gtp-channel-conf 02_584 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXPH_CFG[1] origin:064-gtp-channel-conf 03_584 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXPH_CFG[2] origin:064-gtp-channel-conf 02_585 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXPH_CFG[3] origin:064-gtp-channel-conf 03_585 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXPH_CFG[4] origin:064-gtp-channel-conf 02_586 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXPH_CFG[5] origin:064-gtp-channel-conf 03_586 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXPH_CFG[6] origin:064-gtp-channel-conf 02_587 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXPH_CFG[7] origin:064-gtp-channel-conf 03_587 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXPH_CFG[8] origin:064-gtp-channel-conf 02_588 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXPH_CFG[9] origin:064-gtp-channel-conf 03_588 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXPH_CFG[10] origin:064-gtp-channel-conf 02_589 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXPH_CFG[11] origin:064-gtp-channel-conf 03_589 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXPH_CFG[12] origin:064-gtp-channel-conf 02_590 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXPH_CFG[13] origin:064-gtp-channel-conf 03_590 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXPH_CFG[14] origin:064-gtp-channel-conf 02_591 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXPH_CFG[15] origin:064-gtp-channel-conf 03_591 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXPH_CFG[16] origin:064-gtp-channel-conf 02_592 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXPH_CFG[17] origin:064-gtp-channel-conf 03_592 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXPH_CFG[18] origin:064-gtp-channel-conf 02_593 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXPH_CFG[19] origin:064-gtp-channel-conf 03_593 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXPH_CFG[20] origin:064-gtp-channel-conf 02_594 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXPH_CFG[21] origin:064-gtp-channel-conf 03_594 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXPH_CFG[22] origin:064-gtp-channel-conf 02_595 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXPH_CFG[23] origin:064-gtp-channel-conf 03_595 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXPH_MONITOR_SEL[0] origin:064-gtp-channel-conf 00_700 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXPH_MONITOR_SEL[1] origin:064-gtp-channel-conf 01_700 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXPH_MONITOR_SEL[2] origin:064-gtp-channel-conf 00_701 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXPH_MONITOR_SEL[3] origin:064-gtp-channel-conf 01_701 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXPH_MONITOR_SEL[4] origin:064-gtp-channel-conf 00_702 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXPHDLY_CFG[0] origin:064-gtp-channel-conf 02_600 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXPHDLY_CFG[1] origin:064-gtp-channel-conf 03_600 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXPHDLY_CFG[2] origin:064-gtp-channel-conf 02_601 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXPHDLY_CFG[3] origin:064-gtp-channel-conf 03_601 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXPHDLY_CFG[4] origin:064-gtp-channel-conf 02_602 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXPHDLY_CFG[5] origin:064-gtp-channel-conf 03_602 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXPHDLY_CFG[6] origin:064-gtp-channel-conf 02_603 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXPHDLY_CFG[7] origin:064-gtp-channel-conf 03_603 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXPHDLY_CFG[8] origin:064-gtp-channel-conf 02_604 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXPHDLY_CFG[9] origin:064-gtp-channel-conf 03_604 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXPHDLY_CFG[10] origin:064-gtp-channel-conf 02_605 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXPHDLY_CFG[11] origin:064-gtp-channel-conf 03_605 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXPHDLY_CFG[12] origin:064-gtp-channel-conf 02_606 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXPHDLY_CFG[13] origin:064-gtp-channel-conf 03_606 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXPHDLY_CFG[14] origin:064-gtp-channel-conf 02_607 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXPHDLY_CFG[15] origin:064-gtp-channel-conf 03_607 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXPHDLY_CFG[16] origin:064-gtp-channel-conf 02_608 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXPHDLY_CFG[17] origin:064-gtp-channel-conf 03_608 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXPHDLY_CFG[18] origin:064-gtp-channel-conf 02_609 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXPHDLY_CFG[19] origin:064-gtp-channel-conf 03_609 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXPHDLY_CFG[20] origin:064-gtp-channel-conf 02_610 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXPHDLY_CFG[21] origin:064-gtp-channel-conf 03_610 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXPHDLY_CFG[22] origin:064-gtp-channel-conf 02_611 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXPHDLY_CFG[23] origin:064-gtp-channel-conf 03_611 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXPI_CFG0[0] origin:064-gtp-channel-conf 03_430 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXPI_CFG0[1] origin:064-gtp-channel-conf 02_431 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXPI_CFG0[2] origin:064-gtp-channel-conf 03_431 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXPI_CFG1[0] origin:064-gtp-channel-conf 02_442 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXPI_CFG2[0] origin:064-gtp-channel-conf 03_441 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXPMARESET_TIME[0] origin:064-gtp-channel-conf 00_104 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXPMARESET_TIME[1] origin:064-gtp-channel-conf 01_104 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXPMARESET_TIME[2] origin:064-gtp-channel-conf 00_105 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXPMARESET_TIME[3] origin:064-gtp-channel-conf 01_105 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXPMARESET_TIME[4] origin:064-gtp-channel-conf 00_106 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXPRBS_ERR_LOOPBACK[0] origin:064-gtp-channel-conf 00_136 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXSLIDE_AUTO_WAIT[0] origin:064-gtp-channel-conf 00_520 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXSLIDE_AUTO_WAIT[1] origin:064-gtp-channel-conf 01_520 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXSLIDE_AUTO_WAIT[2] origin:064-gtp-channel-conf 00_521 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXSLIDE_AUTO_WAIT[3] origin:064-gtp-channel-conf 01_521 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXSLIDE_MODE.AUTO origin:064-gtp-channel-conf !01_519 00_519 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXSLIDE_MODE.PCS origin:064-gtp-channel-conf !00_519 01_519 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXSLIDE_MODE.PMA origin:064-gtp-channel-conf 00_519 01_519 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXSYNC_MULTILANE[0] origin:064-gtp-channel-conf 00_133 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXSYNC_OVRD[0] origin:064-gtp-channel-conf 01_135 -GTP_CHANNEL_2_MID_LEFT.GTPE2.RXSYNC_SKIP_DA[0] origin:064-gtp-channel-conf 01_134 -GTP_CHANNEL_2_MID_LEFT.GTPE2.SAS_MAX_COM[0] origin:064-gtp-channel-conf 00_171 -GTP_CHANNEL_2_MID_LEFT.GTPE2.SAS_MAX_COM[1] origin:064-gtp-channel-conf 01_171 -GTP_CHANNEL_2_MID_LEFT.GTPE2.SAS_MAX_COM[2] origin:064-gtp-channel-conf 00_172 -GTP_CHANNEL_2_MID_LEFT.GTPE2.SAS_MAX_COM[3] origin:064-gtp-channel-conf 01_172 -GTP_CHANNEL_2_MID_LEFT.GTPE2.SAS_MAX_COM[4] origin:064-gtp-channel-conf 00_173 -GTP_CHANNEL_2_MID_LEFT.GTPE2.SAS_MAX_COM[5] origin:064-gtp-channel-conf 01_173 -GTP_CHANNEL_2_MID_LEFT.GTPE2.SAS_MAX_COM[6] origin:064-gtp-channel-conf 00_174 -GTP_CHANNEL_2_MID_LEFT.GTPE2.SAS_MIN_COM[0] origin:064-gtp-channel-conf 01_156 -GTP_CHANNEL_2_MID_LEFT.GTPE2.SAS_MIN_COM[1] origin:064-gtp-channel-conf 00_157 -GTP_CHANNEL_2_MID_LEFT.GTPE2.SAS_MIN_COM[2] origin:064-gtp-channel-conf 01_157 -GTP_CHANNEL_2_MID_LEFT.GTPE2.SAS_MIN_COM[3] origin:064-gtp-channel-conf 00_158 -GTP_CHANNEL_2_MID_LEFT.GTPE2.SAS_MIN_COM[4] origin:064-gtp-channel-conf 01_158 -GTP_CHANNEL_2_MID_LEFT.GTPE2.SAS_MIN_COM[5] origin:064-gtp-channel-conf 00_159 -GTP_CHANNEL_2_MID_LEFT.GTPE2.SATA_BURST_SEQ_LEN[0] origin:064-gtp-channel-conf 00_150 -GTP_CHANNEL_2_MID_LEFT.GTPE2.SATA_BURST_SEQ_LEN[1] origin:064-gtp-channel-conf 01_150 -GTP_CHANNEL_2_MID_LEFT.GTPE2.SATA_BURST_SEQ_LEN[2] origin:064-gtp-channel-conf 00_151 -GTP_CHANNEL_2_MID_LEFT.GTPE2.SATA_BURST_SEQ_LEN[3] origin:064-gtp-channel-conf 01_151 -GTP_CHANNEL_2_MID_LEFT.GTPE2.SATA_BURST_VAL[0] origin:064-gtp-channel-conf 01_147 -GTP_CHANNEL_2_MID_LEFT.GTPE2.SATA_BURST_VAL[1] origin:064-gtp-channel-conf 00_148 -GTP_CHANNEL_2_MID_LEFT.GTPE2.SATA_BURST_VAL[2] origin:064-gtp-channel-conf 01_148 -GTP_CHANNEL_2_MID_LEFT.GTPE2.SATA_EIDLE_VAL[0] origin:064-gtp-channel-conf 00_152 -GTP_CHANNEL_2_MID_LEFT.GTPE2.SATA_EIDLE_VAL[1] origin:064-gtp-channel-conf 01_152 -GTP_CHANNEL_2_MID_LEFT.GTPE2.SATA_EIDLE_VAL[2] origin:064-gtp-channel-conf 00_153 -GTP_CHANNEL_2_MID_LEFT.GTPE2.SATA_MAX_BURST[0] origin:064-gtp-channel-conf 00_168 -GTP_CHANNEL_2_MID_LEFT.GTPE2.SATA_MAX_BURST[1] origin:064-gtp-channel-conf 01_168 -GTP_CHANNEL_2_MID_LEFT.GTPE2.SATA_MAX_BURST[2] origin:064-gtp-channel-conf 00_169 -GTP_CHANNEL_2_MID_LEFT.GTPE2.SATA_MAX_BURST[3] origin:064-gtp-channel-conf 01_169 -GTP_CHANNEL_2_MID_LEFT.GTPE2.SATA_MAX_BURST[4] origin:064-gtp-channel-conf 00_170 -GTP_CHANNEL_2_MID_LEFT.GTPE2.SATA_MAX_BURST[5] origin:064-gtp-channel-conf 01_170 -GTP_CHANNEL_2_MID_LEFT.GTPE2.SATA_MAX_INIT[0] origin:064-gtp-channel-conf 00_176 -GTP_CHANNEL_2_MID_LEFT.GTPE2.SATA_MAX_INIT[1] origin:064-gtp-channel-conf 01_176 -GTP_CHANNEL_2_MID_LEFT.GTPE2.SATA_MAX_INIT[2] origin:064-gtp-channel-conf 00_177 -GTP_CHANNEL_2_MID_LEFT.GTPE2.SATA_MAX_INIT[3] origin:064-gtp-channel-conf 01_177 -GTP_CHANNEL_2_MID_LEFT.GTPE2.SATA_MAX_INIT[4] origin:064-gtp-channel-conf 00_178 -GTP_CHANNEL_2_MID_LEFT.GTPE2.SATA_MAX_INIT[5] origin:064-gtp-channel-conf 01_178 -GTP_CHANNEL_2_MID_LEFT.GTPE2.SATA_MAX_WAKE[0] origin:064-gtp-channel-conf 00_179 -GTP_CHANNEL_2_MID_LEFT.GTPE2.SATA_MAX_WAKE[1] origin:064-gtp-channel-conf 01_179 -GTP_CHANNEL_2_MID_LEFT.GTPE2.SATA_MAX_WAKE[2] origin:064-gtp-channel-conf 00_180 -GTP_CHANNEL_2_MID_LEFT.GTPE2.SATA_MAX_WAKE[3] origin:064-gtp-channel-conf 01_180 -GTP_CHANNEL_2_MID_LEFT.GTPE2.SATA_MAX_WAKE[4] origin:064-gtp-channel-conf 00_181 -GTP_CHANNEL_2_MID_LEFT.GTPE2.SATA_MAX_WAKE[5] origin:064-gtp-channel-conf 01_181 -GTP_CHANNEL_2_MID_LEFT.GTPE2.SATA_MIN_BURST[0] origin:064-gtp-channel-conf 01_153 -GTP_CHANNEL_2_MID_LEFT.GTPE2.SATA_MIN_BURST[1] origin:064-gtp-channel-conf 00_154 -GTP_CHANNEL_2_MID_LEFT.GTPE2.SATA_MIN_BURST[2] origin:064-gtp-channel-conf 01_154 -GTP_CHANNEL_2_MID_LEFT.GTPE2.SATA_MIN_BURST[3] origin:064-gtp-channel-conf 00_155 -GTP_CHANNEL_2_MID_LEFT.GTPE2.SATA_MIN_BURST[4] origin:064-gtp-channel-conf 01_155 -GTP_CHANNEL_2_MID_LEFT.GTPE2.SATA_MIN_BURST[5] origin:064-gtp-channel-conf 00_156 -GTP_CHANNEL_2_MID_LEFT.GTPE2.SATA_MIN_INIT[0] origin:064-gtp-channel-conf 00_160 -GTP_CHANNEL_2_MID_LEFT.GTPE2.SATA_MIN_INIT[1] origin:064-gtp-channel-conf 01_160 -GTP_CHANNEL_2_MID_LEFT.GTPE2.SATA_MIN_INIT[2] origin:064-gtp-channel-conf 00_161 -GTP_CHANNEL_2_MID_LEFT.GTPE2.SATA_MIN_INIT[3] origin:064-gtp-channel-conf 01_161 -GTP_CHANNEL_2_MID_LEFT.GTPE2.SATA_MIN_INIT[4] origin:064-gtp-channel-conf 00_162 -GTP_CHANNEL_2_MID_LEFT.GTPE2.SATA_MIN_INIT[5] origin:064-gtp-channel-conf 01_162 -GTP_CHANNEL_2_MID_LEFT.GTPE2.SATA_MIN_WAKE[0] origin:064-gtp-channel-conf 00_163 -GTP_CHANNEL_2_MID_LEFT.GTPE2.SATA_MIN_WAKE[1] origin:064-gtp-channel-conf 01_163 -GTP_CHANNEL_2_MID_LEFT.GTPE2.SATA_MIN_WAKE[2] origin:064-gtp-channel-conf 00_164 -GTP_CHANNEL_2_MID_LEFT.GTPE2.SATA_MIN_WAKE[3] origin:064-gtp-channel-conf 01_164 -GTP_CHANNEL_2_MID_LEFT.GTPE2.SATA_MIN_WAKE[4] origin:064-gtp-channel-conf 00_165 -GTP_CHANNEL_2_MID_LEFT.GTPE2.SATA_MIN_WAKE[5] origin:064-gtp-channel-conf 01_165 -GTP_CHANNEL_2_MID_LEFT.GTPE2.SATA_PLL_CFG.VCO_1500MHZ origin:064-gtp-channel-conf 02_55 -GTP_CHANNEL_2_MID_LEFT.GTPE2.SATA_PLL_CFG.VCO_750MHZ origin:064-gtp-channel-conf 03_55 -GTP_CHANNEL_2_MID_LEFT.GTPE2.SHOW_REALIGN_COMMA origin:064-gtp-channel-conf 01_522 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TERM_RCAL_CFG[0] origin:064-gtp-channel-conf 02_136 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TERM_RCAL_CFG[1] origin:064-gtp-channel-conf 03_136 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TERM_RCAL_CFG[2] origin:064-gtp-channel-conf 02_137 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TERM_RCAL_CFG[3] origin:064-gtp-channel-conf 03_137 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TERM_RCAL_CFG[4] origin:064-gtp-channel-conf 02_138 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TERM_RCAL_CFG[5] origin:064-gtp-channel-conf 03_138 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TERM_RCAL_CFG[6] origin:064-gtp-channel-conf 02_139 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TERM_RCAL_CFG[7] origin:064-gtp-channel-conf 03_139 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TERM_RCAL_CFG[8] origin:064-gtp-channel-conf 02_140 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TERM_RCAL_CFG[9] origin:064-gtp-channel-conf 03_140 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TERM_RCAL_CFG[10] origin:064-gtp-channel-conf 02_141 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TERM_RCAL_CFG[11] origin:064-gtp-channel-conf 03_141 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TERM_RCAL_CFG[12] origin:064-gtp-channel-conf 02_142 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TERM_RCAL_CFG[13] origin:064-gtp-channel-conf 03_142 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TERM_RCAL_CFG[14] origin:064-gtp-channel-conf 02_143 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TERM_RCAL_OVRD[0] origin:064-gtp-channel-conf 03_150 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TERM_RCAL_OVRD[1] origin:064-gtp-channel-conf 02_151 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TERM_RCAL_OVRD[2] origin:064-gtp-channel-conf 03_151 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TRANS_TIME_RATE[0] origin:064-gtp-channel-conf 00_192 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TRANS_TIME_RATE[1] origin:064-gtp-channel-conf 01_192 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TRANS_TIME_RATE[2] origin:064-gtp-channel-conf 00_193 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TRANS_TIME_RATE[3] origin:064-gtp-channel-conf 01_193 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TRANS_TIME_RATE[4] origin:064-gtp-channel-conf 00_194 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TRANS_TIME_RATE[5] origin:064-gtp-channel-conf 01_194 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TRANS_TIME_RATE[6] origin:064-gtp-channel-conf 00_195 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TRANS_TIME_RATE[7] origin:064-gtp-channel-conf 01_195 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TST_RSV[0] origin:064-gtp-channel-conf 02_504 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TST_RSV[1] origin:064-gtp-channel-conf 03_504 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TST_RSV[2] origin:064-gtp-channel-conf 02_505 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TST_RSV[3] origin:064-gtp-channel-conf 03_505 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TST_RSV[4] origin:064-gtp-channel-conf 02_506 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TST_RSV[5] origin:064-gtp-channel-conf 03_506 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TST_RSV[6] origin:064-gtp-channel-conf 02_507 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TST_RSV[7] origin:064-gtp-channel-conf 03_507 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TST_RSV[8] origin:064-gtp-channel-conf 02_508 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TST_RSV[9] origin:064-gtp-channel-conf 03_508 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TST_RSV[10] origin:064-gtp-channel-conf 02_509 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TST_RSV[11] origin:064-gtp-channel-conf 03_509 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TST_RSV[12] origin:064-gtp-channel-conf 02_510 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TST_RSV[13] origin:064-gtp-channel-conf 03_510 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TST_RSV[14] origin:064-gtp-channel-conf 02_511 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TST_RSV[15] origin:064-gtp-channel-conf 03_511 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TST_RSV[16] origin:064-gtp-channel-conf 02_512 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TST_RSV[17] origin:064-gtp-channel-conf 03_512 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TST_RSV[18] origin:064-gtp-channel-conf 02_513 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TST_RSV[19] origin:064-gtp-channel-conf 03_513 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TST_RSV[20] origin:064-gtp-channel-conf 02_514 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TST_RSV[21] origin:064-gtp-channel-conf 03_514 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TST_RSV[22] origin:064-gtp-channel-conf 02_515 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TST_RSV[23] origin:064-gtp-channel-conf 03_515 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TST_RSV[24] origin:064-gtp-channel-conf 02_516 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TST_RSV[25] origin:064-gtp-channel-conf 03_516 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TST_RSV[26] origin:064-gtp-channel-conf 02_517 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TST_RSV[27] origin:064-gtp-channel-conf 03_517 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TST_RSV[28] origin:064-gtp-channel-conf 02_518 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TST_RSV[29] origin:064-gtp-channel-conf 03_518 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TST_RSV[30] origin:064-gtp-channel-conf 02_519 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TST_RSV[31] origin:064-gtp-channel-conf 03_519 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_CLKMUX_EN[0] origin:064-gtp-channel-conf 03_128 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_DATA_WIDTH[0] origin:064-gtp-channel-conf 02_152 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_DATA_WIDTH[1] origin:064-gtp-channel-conf 03_152 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_DATA_WIDTH[2] origin:064-gtp-channel-conf 02_153 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_DRIVE_MODE.PIPE origin:064-gtp-channel-conf 00_200 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_EIDLE_ASSERT_DELAY[0] origin:064-gtp-channel-conf 00_203 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_EIDLE_ASSERT_DELAY[1] origin:064-gtp-channel-conf 01_203 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_EIDLE_ASSERT_DELAY[2] origin:064-gtp-channel-conf 00_204 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_EIDLE_DEASSERT_DELAY[0] origin:064-gtp-channel-conf 01_204 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_EIDLE_DEASSERT_DELAY[1] origin:064-gtp-channel-conf 00_205 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_EIDLE_DEASSERT_DELAY[2] origin:064-gtp-channel-conf 01_205 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_LOOPBACK_DRIVE_HIZ origin:064-gtp-channel-conf 01_202 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_MAINCURSOR_SEL[0] origin:064-gtp-channel-conf 03_289 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_MARGIN_FULL_0[0] origin:064-gtp-channel-conf 02_232 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_MARGIN_FULL_0[1] origin:064-gtp-channel-conf 03_232 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_MARGIN_FULL_0[2] origin:064-gtp-channel-conf 02_233 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_MARGIN_FULL_0[3] origin:064-gtp-channel-conf 03_233 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_MARGIN_FULL_0[4] origin:064-gtp-channel-conf 02_234 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_MARGIN_FULL_0[5] origin:064-gtp-channel-conf 03_234 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_MARGIN_FULL_0[6] origin:064-gtp-channel-conf 02_235 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_MARGIN_FULL_1[0] origin:064-gtp-channel-conf 02_236 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_MARGIN_FULL_1[1] origin:064-gtp-channel-conf 03_236 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_MARGIN_FULL_1[2] origin:064-gtp-channel-conf 02_237 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_MARGIN_FULL_1[3] origin:064-gtp-channel-conf 03_237 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_MARGIN_FULL_1[4] origin:064-gtp-channel-conf 02_238 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_MARGIN_FULL_1[5] origin:064-gtp-channel-conf 03_238 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_MARGIN_FULL_1[6] origin:064-gtp-channel-conf 02_239 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_MARGIN_FULL_2[0] origin:064-gtp-channel-conf 02_240 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_MARGIN_FULL_2[1] origin:064-gtp-channel-conf 03_240 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_MARGIN_FULL_2[2] origin:064-gtp-channel-conf 02_241 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_MARGIN_FULL_2[3] origin:064-gtp-channel-conf 03_241 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_MARGIN_FULL_2[4] origin:064-gtp-channel-conf 02_242 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_MARGIN_FULL_2[5] origin:064-gtp-channel-conf 03_242 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_MARGIN_FULL_2[6] origin:064-gtp-channel-conf 02_243 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_MARGIN_FULL_3[0] origin:064-gtp-channel-conf 02_244 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_MARGIN_FULL_3[1] origin:064-gtp-channel-conf 03_244 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_MARGIN_FULL_3[2] origin:064-gtp-channel-conf 02_245 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_MARGIN_FULL_3[3] origin:064-gtp-channel-conf 03_245 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_MARGIN_FULL_3[4] origin:064-gtp-channel-conf 02_246 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_MARGIN_FULL_3[5] origin:064-gtp-channel-conf 03_246 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_MARGIN_FULL_3[6] origin:064-gtp-channel-conf 02_247 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_MARGIN_FULL_4[0] origin:064-gtp-channel-conf 02_248 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_MARGIN_FULL_4[1] origin:064-gtp-channel-conf 03_248 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_MARGIN_FULL_4[2] origin:064-gtp-channel-conf 02_249 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_MARGIN_FULL_4[3] origin:064-gtp-channel-conf 03_249 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_MARGIN_FULL_4[4] origin:064-gtp-channel-conf 02_250 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_MARGIN_FULL_4[5] origin:064-gtp-channel-conf 03_250 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_MARGIN_FULL_4[6] origin:064-gtp-channel-conf 02_251 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_MARGIN_LOW_0[0] origin:064-gtp-channel-conf 02_252 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_MARGIN_LOW_0[1] origin:064-gtp-channel-conf 03_252 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_MARGIN_LOW_0[2] origin:064-gtp-channel-conf 02_253 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_MARGIN_LOW_0[3] origin:064-gtp-channel-conf 03_253 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_MARGIN_LOW_0[4] origin:064-gtp-channel-conf 02_254 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_MARGIN_LOW_0[5] origin:064-gtp-channel-conf 03_254 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_MARGIN_LOW_0[6] origin:064-gtp-channel-conf 02_255 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_MARGIN_LOW_1[0] origin:064-gtp-channel-conf 02_256 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_MARGIN_LOW_1[1] origin:064-gtp-channel-conf 03_256 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_MARGIN_LOW_1[2] origin:064-gtp-channel-conf 02_257 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_MARGIN_LOW_1[3] origin:064-gtp-channel-conf 03_257 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_MARGIN_LOW_1[4] origin:064-gtp-channel-conf 02_258 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_MARGIN_LOW_1[5] origin:064-gtp-channel-conf 03_258 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_MARGIN_LOW_1[6] origin:064-gtp-channel-conf 02_259 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_MARGIN_LOW_2[0] origin:064-gtp-channel-conf 02_260 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_MARGIN_LOW_2[1] origin:064-gtp-channel-conf 03_260 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_MARGIN_LOW_2[2] origin:064-gtp-channel-conf 02_261 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_MARGIN_LOW_2[3] origin:064-gtp-channel-conf 03_261 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_MARGIN_LOW_2[4] origin:064-gtp-channel-conf 02_262 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_MARGIN_LOW_2[5] origin:064-gtp-channel-conf 03_262 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_MARGIN_LOW_2[6] origin:064-gtp-channel-conf 02_263 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_MARGIN_LOW_3[0] origin:064-gtp-channel-conf 02_264 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_MARGIN_LOW_3[1] origin:064-gtp-channel-conf 03_264 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_MARGIN_LOW_3[2] origin:064-gtp-channel-conf 02_265 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_MARGIN_LOW_3[3] origin:064-gtp-channel-conf 03_265 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_MARGIN_LOW_3[4] origin:064-gtp-channel-conf 02_266 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_MARGIN_LOW_3[5] origin:064-gtp-channel-conf 03_266 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_MARGIN_LOW_3[6] origin:064-gtp-channel-conf 02_267 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_MARGIN_LOW_4[0] origin:064-gtp-channel-conf 02_268 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_MARGIN_LOW_4[1] origin:064-gtp-channel-conf 03_268 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_MARGIN_LOW_4[2] origin:064-gtp-channel-conf 02_269 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_MARGIN_LOW_4[3] origin:064-gtp-channel-conf 03_269 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_MARGIN_LOW_4[4] origin:064-gtp-channel-conf 02_270 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_MARGIN_LOW_4[5] origin:064-gtp-channel-conf 03_270 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_MARGIN_LOW_4[6] origin:064-gtp-channel-conf 02_271 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_PREDRIVER_MODE[0] origin:064-gtp-channel-conf 00_206 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_RXDETECT_CFG[0] origin:064-gtp-channel-conf 02_296 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_RXDETECT_CFG[1] origin:064-gtp-channel-conf 03_296 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_RXDETECT_CFG[2] origin:064-gtp-channel-conf 02_297 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_RXDETECT_CFG[3] origin:064-gtp-channel-conf 03_297 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_RXDETECT_CFG[4] origin:064-gtp-channel-conf 02_298 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_RXDETECT_CFG[5] origin:064-gtp-channel-conf 03_298 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_RXDETECT_CFG[6] origin:064-gtp-channel-conf 02_299 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_RXDETECT_CFG[7] origin:064-gtp-channel-conf 03_299 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_RXDETECT_CFG[8] origin:064-gtp-channel-conf 02_300 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_RXDETECT_CFG[9] origin:064-gtp-channel-conf 03_300 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_RXDETECT_CFG[10] origin:064-gtp-channel-conf 02_301 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_RXDETECT_CFG[11] origin:064-gtp-channel-conf 03_301 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_RXDETECT_CFG[12] origin:064-gtp-channel-conf 02_302 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_RXDETECT_CFG[13] origin:064-gtp-channel-conf 03_302 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_RXDETECT_REF[0] origin:064-gtp-channel-conf 02_292 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_RXDETECT_REF[1] origin:064-gtp-channel-conf 03_292 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_RXDETECT_REF[2] origin:064-gtp-channel-conf 02_293 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_XCLK_SEL.TXUSR origin:064-gtp-channel-conf 03_11 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_CLK25_DIV[0] origin:064-gtp-channel-conf 02_144 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_CLK25_DIV[1] origin:064-gtp-channel-conf 03_144 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_CLK25_DIV[2] origin:064-gtp-channel-conf 02_145 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_CLK25_DIV[3] origin:064-gtp-channel-conf 03_145 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_CLK25_DIV[4] origin:064-gtp-channel-conf 02_146 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_DEEMPH0[0] origin:064-gtp-channel-conf 02_272 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_DEEMPH0[1] origin:064-gtp-channel-conf 03_272 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_DEEMPH0[2] origin:064-gtp-channel-conf 02_273 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_DEEMPH0[3] origin:064-gtp-channel-conf 03_273 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_DEEMPH0[4] origin:064-gtp-channel-conf 02_274 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_DEEMPH0[5] origin:064-gtp-channel-conf 03_274 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_DEEMPH1[0] origin:064-gtp-channel-conf 02_276 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_DEEMPH1[1] origin:064-gtp-channel-conf 03_276 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_DEEMPH1[2] origin:064-gtp-channel-conf 02_277 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_DEEMPH1[3] origin:064-gtp-channel-conf 03_277 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_DEEMPH1[4] origin:064-gtp-channel-conf 02_278 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TX_DEEMPH1[5] origin:064-gtp-channel-conf 03_278 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXBUF_EN origin:064-gtp-channel-conf 00_231 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXBUF_RESET_ON_RATE_CHANGE origin:064-gtp-channel-conf 01_231 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXDLY_CFG[0] origin:064-gtp-channel-conf 02_80 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXDLY_CFG[1] origin:064-gtp-channel-conf 03_80 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXDLY_CFG[2] origin:064-gtp-channel-conf 02_81 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXDLY_CFG[3] origin:064-gtp-channel-conf 03_81 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXDLY_CFG[4] origin:064-gtp-channel-conf 02_82 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXDLY_CFG[5] origin:064-gtp-channel-conf 03_82 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXDLY_CFG[6] origin:064-gtp-channel-conf 02_83 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXDLY_CFG[7] origin:064-gtp-channel-conf 03_83 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXDLY_CFG[8] origin:064-gtp-channel-conf 02_84 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXDLY_CFG[9] origin:064-gtp-channel-conf 03_84 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXDLY_CFG[10] origin:064-gtp-channel-conf 02_85 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXDLY_CFG[11] origin:064-gtp-channel-conf 03_85 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXDLY_CFG[12] origin:064-gtp-channel-conf 02_86 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXDLY_CFG[13] origin:064-gtp-channel-conf 03_86 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXDLY_CFG[14] origin:064-gtp-channel-conf 02_87 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXDLY_CFG[15] origin:064-gtp-channel-conf 03_87 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXDLY_LCFG[0] origin:064-gtp-channel-conf 02_568 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXDLY_LCFG[1] origin:064-gtp-channel-conf 03_568 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXDLY_LCFG[2] origin:064-gtp-channel-conf 02_569 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXDLY_LCFG[3] origin:064-gtp-channel-conf 03_569 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXDLY_LCFG[4] origin:064-gtp-channel-conf 02_570 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXDLY_LCFG[5] origin:064-gtp-channel-conf 03_570 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXDLY_LCFG[6] origin:064-gtp-channel-conf 02_571 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXDLY_LCFG[7] origin:064-gtp-channel-conf 03_571 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXDLY_LCFG[8] origin:064-gtp-channel-conf 02_572 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXDLY_TAP_CFG[0] origin:064-gtp-channel-conf 02_88 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXDLY_TAP_CFG[1] origin:064-gtp-channel-conf 03_88 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXDLY_TAP_CFG[2] origin:064-gtp-channel-conf 02_89 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXDLY_TAP_CFG[3] origin:064-gtp-channel-conf 03_89 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXDLY_TAP_CFG[4] origin:064-gtp-channel-conf 02_90 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXDLY_TAP_CFG[5] origin:064-gtp-channel-conf 03_90 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXDLY_TAP_CFG[6] origin:064-gtp-channel-conf 02_91 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXDLY_TAP_CFG[7] origin:064-gtp-channel-conf 03_91 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXDLY_TAP_CFG[8] origin:064-gtp-channel-conf 02_92 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXDLY_TAP_CFG[9] origin:064-gtp-channel-conf 03_92 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXDLY_TAP_CFG[10] origin:064-gtp-channel-conf 02_93 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXDLY_TAP_CFG[11] origin:064-gtp-channel-conf 03_93 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXDLY_TAP_CFG[12] origin:064-gtp-channel-conf 02_94 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXDLY_TAP_CFG[13] origin:064-gtp-channel-conf 03_94 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXDLY_TAP_CFG[14] origin:064-gtp-channel-conf 02_95 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXDLY_TAP_CFG[15] origin:064-gtp-channel-conf 03_95 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXGEARBOX_EN origin:064-gtp-channel-conf 01_226 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXOOB_CFG[0] origin:064-gtp-channel-conf 03_20 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXOUT_DIV[0] origin:064-gtp-channel-conf 02_386 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXOUT_DIV[1] origin:064-gtp-channel-conf 03_386 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPCSRESET_TIME[0] origin:064-gtp-channel-conf 01_130 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPCSRESET_TIME[1] origin:064-gtp-channel-conf 00_131 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPCSRESET_TIME[2] origin:064-gtp-channel-conf 01_131 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPCSRESET_TIME[3] origin:064-gtp-channel-conf 00_132 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPCSRESET_TIME[4] origin:064-gtp-channel-conf 01_132 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPH_CFG[0] origin:064-gtp-channel-conf 02_96 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPH_CFG[1] origin:064-gtp-channel-conf 03_96 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPH_CFG[2] origin:064-gtp-channel-conf 02_97 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPH_CFG[3] origin:064-gtp-channel-conf 03_97 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPH_CFG[4] origin:064-gtp-channel-conf 02_98 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPH_CFG[5] origin:064-gtp-channel-conf 03_98 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPH_CFG[6] origin:064-gtp-channel-conf 02_99 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPH_CFG[7] origin:064-gtp-channel-conf 03_99 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPH_CFG[8] origin:064-gtp-channel-conf 02_100 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPH_CFG[9] origin:064-gtp-channel-conf 03_100 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPH_CFG[10] origin:064-gtp-channel-conf 02_101 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPH_CFG[11] origin:064-gtp-channel-conf 03_101 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPH_CFG[12] origin:064-gtp-channel-conf 02_102 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPH_CFG[13] origin:064-gtp-channel-conf 03_102 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPH_CFG[14] origin:064-gtp-channel-conf 02_103 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPH_CFG[15] origin:064-gtp-channel-conf 03_103 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPH_MONITOR_SEL[0] origin:064-gtp-channel-conf 02_108 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPH_MONITOR_SEL[1] origin:064-gtp-channel-conf 03_108 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPH_MONITOR_SEL[2] origin:064-gtp-channel-conf 02_109 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPH_MONITOR_SEL[3] origin:064-gtp-channel-conf 03_109 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPH_MONITOR_SEL[4] origin:064-gtp-channel-conf 02_110 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPHDLY_CFG[0] origin:064-gtp-channel-conf 02_64 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPHDLY_CFG[1] origin:064-gtp-channel-conf 03_64 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPHDLY_CFG[2] origin:064-gtp-channel-conf 02_65 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPHDLY_CFG[3] origin:064-gtp-channel-conf 03_65 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPHDLY_CFG[4] origin:064-gtp-channel-conf 02_66 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPHDLY_CFG[5] origin:064-gtp-channel-conf 03_66 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPHDLY_CFG[6] origin:064-gtp-channel-conf 02_67 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPHDLY_CFG[7] origin:064-gtp-channel-conf 03_67 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPHDLY_CFG[8] origin:064-gtp-channel-conf 02_68 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPHDLY_CFG[9] origin:064-gtp-channel-conf 03_68 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPHDLY_CFG[10] origin:064-gtp-channel-conf 02_69 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPHDLY_CFG[11] origin:064-gtp-channel-conf 03_69 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPHDLY_CFG[12] origin:064-gtp-channel-conf 02_70 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPHDLY_CFG[13] origin:064-gtp-channel-conf 03_70 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPHDLY_CFG[14] origin:064-gtp-channel-conf 02_71 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPHDLY_CFG[15] origin:064-gtp-channel-conf 03_71 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPHDLY_CFG[16] origin:064-gtp-channel-conf 02_72 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPHDLY_CFG[17] origin:064-gtp-channel-conf 03_72 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPHDLY_CFG[18] origin:064-gtp-channel-conf 02_73 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPHDLY_CFG[19] origin:064-gtp-channel-conf 03_73 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPHDLY_CFG[20] origin:064-gtp-channel-conf 02_74 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPHDLY_CFG[21] origin:064-gtp-channel-conf 03_74 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPHDLY_CFG[22] origin:064-gtp-channel-conf 02_75 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPHDLY_CFG[23] origin:064-gtp-channel-conf 03_75 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPI_GREY_SEL[0] origin:064-gtp-channel-conf 03_498 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPI_INVSTROBE_SEL[0] origin:064-gtp-channel-conf 02_498 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPI_PPM_CFG[0] origin:064-gtp-channel-conf 02_488 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPI_PPM_CFG[1] origin:064-gtp-channel-conf 03_488 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPI_PPM_CFG[2] origin:064-gtp-channel-conf 02_489 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPI_PPM_CFG[3] origin:064-gtp-channel-conf 03_489 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPI_PPM_CFG[4] origin:064-gtp-channel-conf 02_490 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPI_PPM_CFG[5] origin:064-gtp-channel-conf 03_490 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPI_PPM_CFG[6] origin:064-gtp-channel-conf 02_491 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPI_PPM_CFG[7] origin:064-gtp-channel-conf 03_491 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPI_PPMCLK_SEL.TXUSRCLK2 origin:064-gtp-channel-conf 03_497 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPI_SYNFREQ_PPM[0] origin:064-gtp-channel-conf 02_496 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPI_SYNFREQ_PPM[1] origin:064-gtp-channel-conf 03_496 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPI_SYNFREQ_PPM[2] origin:064-gtp-channel-conf 02_497 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPI_CFG0[0] origin:064-gtp-channel-conf 02_40 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPI_CFG0[1] origin:064-gtp-channel-conf 03_40 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPI_CFG1[0] origin:064-gtp-channel-conf 02_41 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPI_CFG1[1] origin:064-gtp-channel-conf 03_41 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPI_CFG2[0] origin:064-gtp-channel-conf 02_42 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPI_CFG2[1] origin:064-gtp-channel-conf 03_42 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPI_CFG3[0] origin:064-gtp-channel-conf 02_43 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPI_CFG4[0] origin:064-gtp-channel-conf 03_43 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPI_CFG5[0] origin:064-gtp-channel-conf 02_44 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPI_CFG5[1] origin:064-gtp-channel-conf 03_44 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPI_CFG5[2] origin:064-gtp-channel-conf 02_45 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPMARESET_TIME[0] origin:064-gtp-channel-conf 00_128 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPMARESET_TIME[1] origin:064-gtp-channel-conf 01_128 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPMARESET_TIME[2] origin:064-gtp-channel-conf 00_129 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPMARESET_TIME[3] origin:064-gtp-channel-conf 01_129 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXPMARESET_TIME[4] origin:064-gtp-channel-conf 00_130 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXSYNC_MULTILANE[0] origin:064-gtp-channel-conf 01_133 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXSYNC_OVRD[0] origin:064-gtp-channel-conf 00_135 -GTP_CHANNEL_2_MID_LEFT.GTPE2.TXSYNC_SKIP_DA[0] origin:064-gtp-channel-conf 00_134 -GTP_CHANNEL_2_MID_LEFT.GTPE2.UCODEER_CLR[0] origin:064-gtp-channel-conf 01_00 -GTP_CHANNEL_2_MID_LEFT.GTPE2.USE_PCS_CLK_PHASE_SEL[0] origin:064-gtp-channel-conf 02_463 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ZINV_DMONITORCLK origin:064-gtp-channel-conf 02_13 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ZINV_DRPCLK origin:064-gtp-channel-conf 02_00 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ZINV_RXUSRCLK origin:064-gtp-channel-conf 03_01 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ZINV_SIGVALIDCLK origin:064-gtp-channel-conf 03_13 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ZINV_TXPHDLYTSTCLK origin:064-gtp-channel-conf 02_03 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ZINV_TXUSRCLK origin:064-gtp-channel-conf 03_04 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ZINV_CLKRSVD0 origin:064-gtp-channel-conf 02_23 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ZINV_CLKRSVD1 origin:064-gtp-channel-conf 03_23 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ZINV_RXUSRCLK2 origin:064-gtp-channel-conf 02_02 -GTP_CHANNEL_2_MID_LEFT.GTPE2.ZINV_TXUSRCLK2 origin:064-gtp-channel-conf 02_05 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ACJTAG_DEBUG_MODE[0] origin:064-gtp-channel-conf 00_07 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ACJTAG_MODE[0] origin:064-gtp-channel-conf 01_06 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ACJTAG_RESET[0] origin:064-gtp-channel-conf 01_07 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[0] origin:064-gtp-channel-conf 02_464 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[1] origin:064-gtp-channel-conf 03_464 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[2] origin:064-gtp-channel-conf 02_465 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[3] origin:064-gtp-channel-conf 03_465 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[4] origin:064-gtp-channel-conf 02_466 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[5] origin:064-gtp-channel-conf 03_466 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[6] origin:064-gtp-channel-conf 02_467 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[7] origin:064-gtp-channel-conf 03_467 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[8] origin:064-gtp-channel-conf 02_468 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[9] origin:064-gtp-channel-conf 03_468 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[10] origin:064-gtp-channel-conf 02_469 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[11] origin:064-gtp-channel-conf 03_469 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[12] origin:064-gtp-channel-conf 02_470 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[13] origin:064-gtp-channel-conf 03_470 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[14] origin:064-gtp-channel-conf 02_471 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[15] origin:064-gtp-channel-conf 03_471 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[16] origin:064-gtp-channel-conf 02_472 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[17] origin:064-gtp-channel-conf 03_472 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[18] origin:064-gtp-channel-conf 02_473 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[19] origin:064-gtp-channel-conf 03_473 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ALIGN_COMMA_DOUBLE origin:064-gtp-channel-conf 00_522 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[0] origin:064-gtp-channel-conf 00_496 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[1] origin:064-gtp-channel-conf 01_496 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[2] origin:064-gtp-channel-conf 00_497 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[3] origin:064-gtp-channel-conf 01_497 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[4] origin:064-gtp-channel-conf 00_498 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[5] origin:064-gtp-channel-conf 01_498 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[6] origin:064-gtp-channel-conf 00_499 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[7] origin:064-gtp-channel-conf 01_499 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[8] origin:064-gtp-channel-conf 00_500 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[9] origin:064-gtp-channel-conf 01_500 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ALIGN_COMMA_WORD[0] origin:064-gtp-channel-conf 01_526 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ALIGN_COMMA_WORD[1] origin:064-gtp-channel-conf 00_527 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ALIGN_MCOMMA_DET origin:064-gtp-channel-conf 00_523 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[0] origin:064-gtp-channel-conf 00_504 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[1] origin:064-gtp-channel-conf 01_504 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[2] origin:064-gtp-channel-conf 00_505 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[3] origin:064-gtp-channel-conf 01_505 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[4] origin:064-gtp-channel-conf 00_506 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[5] origin:064-gtp-channel-conf 01_506 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[6] origin:064-gtp-channel-conf 00_507 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[7] origin:064-gtp-channel-conf 01_507 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[8] origin:064-gtp-channel-conf 00_508 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[9] origin:064-gtp-channel-conf 01_508 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ALIGN_PCOMMA_DET origin:064-gtp-channel-conf 01_523 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[0] origin:064-gtp-channel-conf 00_512 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[1] origin:064-gtp-channel-conf 01_512 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[2] origin:064-gtp-channel-conf 00_513 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[3] origin:064-gtp-channel-conf 01_513 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[4] origin:064-gtp-channel-conf 00_514 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[5] origin:064-gtp-channel-conf 01_514 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[6] origin:064-gtp-channel-conf 00_515 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[7] origin:064-gtp-channel-conf 01_515 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[8] origin:064-gtp-channel-conf 00_516 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[9] origin:064-gtp-channel-conf 01_516 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CBCC_DATA_SOURCE_SEL.DECODED origin:064-gtp-channel-conf 01_661 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[0] origin:064-gtp-channel-conf 02_392 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[1] origin:064-gtp-channel-conf 03_392 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[2] origin:064-gtp-channel-conf 02_393 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[3] origin:064-gtp-channel-conf 03_393 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[4] origin:064-gtp-channel-conf 02_394 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[5] origin:064-gtp-channel-conf 03_394 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[6] origin:064-gtp-channel-conf 02_395 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[7] origin:064-gtp-channel-conf 03_395 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[8] origin:064-gtp-channel-conf 02_396 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[9] origin:064-gtp-channel-conf 03_396 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[10] origin:064-gtp-channel-conf 02_397 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[11] origin:064-gtp-channel-conf 03_397 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[12] origin:064-gtp-channel-conf 02_398 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[13] origin:064-gtp-channel-conf 03_398 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[14] origin:064-gtp-channel-conf 02_399 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[15] origin:064-gtp-channel-conf 03_399 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[16] origin:064-gtp-channel-conf 02_400 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[17] origin:064-gtp-channel-conf 03_400 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[18] origin:064-gtp-channel-conf 02_401 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[19] origin:064-gtp-channel-conf 03_401 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[20] origin:064-gtp-channel-conf 02_402 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[21] origin:064-gtp-channel-conf 03_402 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[22] origin:064-gtp-channel-conf 02_403 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[23] origin:064-gtp-channel-conf 03_403 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[24] origin:064-gtp-channel-conf 02_404 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[25] origin:064-gtp-channel-conf 03_404 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[26] origin:064-gtp-channel-conf 02_405 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[27] origin:064-gtp-channel-conf 03_405 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[28] origin:064-gtp-channel-conf 02_406 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[29] origin:064-gtp-channel-conf 03_406 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[30] origin:064-gtp-channel-conf 02_407 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[31] origin:064-gtp-channel-conf 03_407 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[32] origin:064-gtp-channel-conf 02_408 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[33] origin:064-gtp-channel-conf 03_408 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[34] origin:064-gtp-channel-conf 02_409 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[35] origin:064-gtp-channel-conf 03_409 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[36] origin:064-gtp-channel-conf 02_410 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[37] origin:064-gtp-channel-conf 03_410 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[38] origin:064-gtp-channel-conf 02_411 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[39] origin:064-gtp-channel-conf 03_411 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[40] origin:064-gtp-channel-conf 02_412 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[41] origin:064-gtp-channel-conf 03_412 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[42] origin:064-gtp-channel-conf 02_413 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG2[0] origin:064-gtp-channel-conf 02_459 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG2[1] origin:064-gtp-channel-conf 03_459 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG2[2] origin:064-gtp-channel-conf 02_460 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG2[3] origin:064-gtp-channel-conf 03_460 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG2[4] origin:064-gtp-channel-conf 02_461 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG2[5] origin:064-gtp-channel-conf 03_461 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG2[6] origin:064-gtp-channel-conf 02_462 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG3[0] origin:064-gtp-channel-conf 02_416 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG3[1] origin:064-gtp-channel-conf 03_416 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG3[2] origin:064-gtp-channel-conf 02_417 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG3[3] origin:064-gtp-channel-conf 03_417 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG3[4] origin:064-gtp-channel-conf 02_418 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG3[5] origin:064-gtp-channel-conf 03_418 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG3[6] origin:064-gtp-channel-conf 02_419 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG4[0] origin:064-gtp-channel-conf 03_438 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG5[0] origin:064-gtp-channel-conf 02_429 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG5[1] origin:064-gtp-channel-conf 03_429 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG6[0] origin:064-gtp-channel-conf 03_436 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG6[1] origin:064-gtp-channel-conf 02_437 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG6[2] origin:064-gtp-channel-conf 03_437 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG6[3] origin:064-gtp-channel-conf 02_438 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_KEEP_ALIGN origin:064-gtp-channel-conf 01_631 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_MAX_SKEW[0] origin:064-gtp-channel-conf 00_670 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_MAX_SKEW[1] origin:064-gtp-channel-conf 01_670 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_MAX_SKEW[2] origin:064-gtp-channel-conf 00_671 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_MAX_SKEW[3] origin:064-gtp-channel-conf 01_671 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[0] origin:064-gtp-channel-conf 00_608 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[1] origin:064-gtp-channel-conf 01_608 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[2] origin:064-gtp-channel-conf 00_609 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[3] origin:064-gtp-channel-conf 01_609 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[4] origin:064-gtp-channel-conf 00_610 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[5] origin:064-gtp-channel-conf 01_610 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[6] origin:064-gtp-channel-conf 00_611 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[7] origin:064-gtp-channel-conf 01_611 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[8] origin:064-gtp-channel-conf 00_612 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[9] origin:064-gtp-channel-conf 01_612 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[0] origin:064-gtp-channel-conf 00_616 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[1] origin:064-gtp-channel-conf 01_616 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[2] origin:064-gtp-channel-conf 00_617 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[3] origin:064-gtp-channel-conf 01_617 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[4] origin:064-gtp-channel-conf 00_618 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[5] origin:064-gtp-channel-conf 01_618 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[6] origin:064-gtp-channel-conf 00_619 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[7] origin:064-gtp-channel-conf 01_619 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[8] origin:064-gtp-channel-conf 00_620 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[9] origin:064-gtp-channel-conf 01_620 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[0] origin:064-gtp-channel-conf 00_624 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[1] origin:064-gtp-channel-conf 01_624 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[2] origin:064-gtp-channel-conf 00_625 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[3] origin:064-gtp-channel-conf 01_625 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[4] origin:064-gtp-channel-conf 00_626 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[5] origin:064-gtp-channel-conf 01_626 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[6] origin:064-gtp-channel-conf 00_627 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[7] origin:064-gtp-channel-conf 01_627 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[8] origin:064-gtp-channel-conf 00_628 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[9] origin:064-gtp-channel-conf 01_628 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[0] origin:064-gtp-channel-conf 00_632 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[1] origin:064-gtp-channel-conf 01_632 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[2] origin:064-gtp-channel-conf 00_633 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[3] origin:064-gtp-channel-conf 01_633 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[4] origin:064-gtp-channel-conf 00_634 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[5] origin:064-gtp-channel-conf 01_634 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[6] origin:064-gtp-channel-conf 00_635 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[7] origin:064-gtp-channel-conf 01_635 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[8] origin:064-gtp-channel-conf 00_636 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[9] origin:064-gtp-channel-conf 01_636 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_ENABLE[0] origin:064-gtp-channel-conf 00_614 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_ENABLE[1] origin:064-gtp-channel-conf 01_614 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_ENABLE[2] origin:064-gtp-channel-conf 00_615 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_ENABLE[3] origin:064-gtp-channel-conf 01_615 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[0] origin:064-gtp-channel-conf 00_640 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[1] origin:064-gtp-channel-conf 01_640 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[2] origin:064-gtp-channel-conf 00_641 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[3] origin:064-gtp-channel-conf 01_641 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[4] origin:064-gtp-channel-conf 00_642 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[5] origin:064-gtp-channel-conf 01_642 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[6] origin:064-gtp-channel-conf 00_643 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[7] origin:064-gtp-channel-conf 01_643 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[8] origin:064-gtp-channel-conf 00_644 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[9] origin:064-gtp-channel-conf 01_644 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[0] origin:064-gtp-channel-conf 00_648 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[1] origin:064-gtp-channel-conf 01_648 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[2] origin:064-gtp-channel-conf 00_649 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[3] origin:064-gtp-channel-conf 01_649 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[4] origin:064-gtp-channel-conf 00_650 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[5] origin:064-gtp-channel-conf 01_650 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[6] origin:064-gtp-channel-conf 00_651 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[7] origin:064-gtp-channel-conf 01_651 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[8] origin:064-gtp-channel-conf 00_652 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[9] origin:064-gtp-channel-conf 01_652 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[0] origin:064-gtp-channel-conf 00_656 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[1] origin:064-gtp-channel-conf 01_656 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[2] origin:064-gtp-channel-conf 00_657 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[3] origin:064-gtp-channel-conf 01_657 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[4] origin:064-gtp-channel-conf 00_658 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[5] origin:064-gtp-channel-conf 01_658 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[6] origin:064-gtp-channel-conf 00_659 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[7] origin:064-gtp-channel-conf 01_659 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[8] origin:064-gtp-channel-conf 00_660 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[9] origin:064-gtp-channel-conf 01_660 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[0] origin:064-gtp-channel-conf 00_664 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[1] origin:064-gtp-channel-conf 01_664 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[2] origin:064-gtp-channel-conf 00_665 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[3] origin:064-gtp-channel-conf 01_665 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[4] origin:064-gtp-channel-conf 00_666 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[5] origin:064-gtp-channel-conf 01_666 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[6] origin:064-gtp-channel-conf 00_667 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[7] origin:064-gtp-channel-conf 01_667 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[8] origin:064-gtp-channel-conf 00_668 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[9] origin:064-gtp-channel-conf 01_668 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_ENABLE[0] origin:064-gtp-channel-conf 00_646 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_ENABLE[1] origin:064-gtp-channel-conf 01_646 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_ENABLE[2] origin:064-gtp-channel-conf 00_647 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_ENABLE[3] origin:064-gtp-channel-conf 01_647 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_USE origin:064-gtp-channel-conf 01_645 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_LEN[0] origin:064-gtp-channel-conf 00_623 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_LEN[1] origin:064-gtp-channel-conf 01_623 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COMMON_SWING[0] origin:064-gtp-channel-conf 03_311 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_KEEP_IDLE origin:064-gtp-channel-conf 00_591 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_MAX_LAT[0] origin:064-gtp-channel-conf 00_557 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_MAX_LAT[1] origin:064-gtp-channel-conf 01_557 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_MAX_LAT[2] origin:064-gtp-channel-conf 00_558 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_MAX_LAT[3] origin:064-gtp-channel-conf 01_558 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_MAX_LAT[4] origin:064-gtp-channel-conf 00_559 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_MAX_LAT[5] origin:064-gtp-channel-conf 01_559 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_MIN_LAT[0] origin:064-gtp-channel-conf 00_565 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_MIN_LAT[1] origin:064-gtp-channel-conf 01_565 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_MIN_LAT[2] origin:064-gtp-channel-conf 00_566 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_MIN_LAT[3] origin:064-gtp-channel-conf 01_566 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_MIN_LAT[4] origin:064-gtp-channel-conf 00_567 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_MIN_LAT[5] origin:064-gtp-channel-conf 01_567 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_PRECEDENCE origin:064-gtp-channel-conf 00_590 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_REPEAT_WAIT[0] origin:064-gtp-channel-conf 00_573 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_REPEAT_WAIT[1] origin:064-gtp-channel-conf 01_573 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_REPEAT_WAIT[2] origin:064-gtp-channel-conf 00_574 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_REPEAT_WAIT[3] origin:064-gtp-channel-conf 01_574 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_REPEAT_WAIT[4] origin:064-gtp-channel-conf 00_575 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[0] origin:064-gtp-channel-conf 00_544 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[1] origin:064-gtp-channel-conf 01_544 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[2] origin:064-gtp-channel-conf 00_545 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[3] origin:064-gtp-channel-conf 01_545 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[4] origin:064-gtp-channel-conf 00_546 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[5] origin:064-gtp-channel-conf 01_546 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[6] origin:064-gtp-channel-conf 00_547 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[7] origin:064-gtp-channel-conf 01_547 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[8] origin:064-gtp-channel-conf 00_548 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[9] origin:064-gtp-channel-conf 01_548 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[0] origin:064-gtp-channel-conf 00_552 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[1] origin:064-gtp-channel-conf 01_552 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[2] origin:064-gtp-channel-conf 00_553 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[3] origin:064-gtp-channel-conf 01_553 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[4] origin:064-gtp-channel-conf 00_554 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[5] origin:064-gtp-channel-conf 01_554 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[6] origin:064-gtp-channel-conf 00_555 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[7] origin:064-gtp-channel-conf 01_555 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[8] origin:064-gtp-channel-conf 00_556 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[9] origin:064-gtp-channel-conf 01_556 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[0] origin:064-gtp-channel-conf 00_560 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[1] origin:064-gtp-channel-conf 01_560 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[2] origin:064-gtp-channel-conf 00_561 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[3] origin:064-gtp-channel-conf 01_561 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[4] origin:064-gtp-channel-conf 00_562 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[5] origin:064-gtp-channel-conf 01_562 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[6] origin:064-gtp-channel-conf 00_563 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[7] origin:064-gtp-channel-conf 01_563 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[8] origin:064-gtp-channel-conf 00_564 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[9] origin:064-gtp-channel-conf 01_564 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[0] origin:064-gtp-channel-conf 00_568 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[1] origin:064-gtp-channel-conf 01_568 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[2] origin:064-gtp-channel-conf 00_569 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[3] origin:064-gtp-channel-conf 01_569 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[4] origin:064-gtp-channel-conf 00_570 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[5] origin:064-gtp-channel-conf 01_570 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[6] origin:064-gtp-channel-conf 00_571 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[7] origin:064-gtp-channel-conf 01_571 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[8] origin:064-gtp-channel-conf 00_572 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[9] origin:064-gtp-channel-conf 01_572 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_ENABLE[0] origin:064-gtp-channel-conf 00_549 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_ENABLE[1] origin:064-gtp-channel-conf 01_549 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_ENABLE[2] origin:064-gtp-channel-conf 00_550 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_ENABLE[3] origin:064-gtp-channel-conf 01_550 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[0] origin:064-gtp-channel-conf 00_576 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[1] origin:064-gtp-channel-conf 01_576 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[2] origin:064-gtp-channel-conf 00_577 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[3] origin:064-gtp-channel-conf 01_577 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[4] origin:064-gtp-channel-conf 00_578 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[5] origin:064-gtp-channel-conf 01_578 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[6] origin:064-gtp-channel-conf 00_579 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[7] origin:064-gtp-channel-conf 01_579 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[8] origin:064-gtp-channel-conf 00_580 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[9] origin:064-gtp-channel-conf 01_580 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[0] origin:064-gtp-channel-conf 00_584 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[1] origin:064-gtp-channel-conf 01_584 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[2] origin:064-gtp-channel-conf 00_585 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[3] origin:064-gtp-channel-conf 01_585 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[4] origin:064-gtp-channel-conf 00_586 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[5] origin:064-gtp-channel-conf 01_586 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[6] origin:064-gtp-channel-conf 00_587 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[7] origin:064-gtp-channel-conf 01_587 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[8] origin:064-gtp-channel-conf 00_588 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[9] origin:064-gtp-channel-conf 01_588 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[0] origin:064-gtp-channel-conf 00_592 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[1] origin:064-gtp-channel-conf 01_592 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[2] origin:064-gtp-channel-conf 00_593 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[3] origin:064-gtp-channel-conf 01_593 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[4] origin:064-gtp-channel-conf 00_594 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[5] origin:064-gtp-channel-conf 01_594 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[6] origin:064-gtp-channel-conf 00_595 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[7] origin:064-gtp-channel-conf 01_595 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[8] origin:064-gtp-channel-conf 00_596 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[9] origin:064-gtp-channel-conf 01_596 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[0] origin:064-gtp-channel-conf 00_600 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[1] origin:064-gtp-channel-conf 01_600 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[2] origin:064-gtp-channel-conf 00_601 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[3] origin:064-gtp-channel-conf 01_601 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[4] origin:064-gtp-channel-conf 00_602 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[5] origin:064-gtp-channel-conf 01_602 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[6] origin:064-gtp-channel-conf 00_603 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[7] origin:064-gtp-channel-conf 01_603 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[8] origin:064-gtp-channel-conf 00_604 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[9] origin:064-gtp-channel-conf 01_604 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_ENABLE[0] origin:064-gtp-channel-conf 00_581 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_ENABLE[1] origin:064-gtp-channel-conf 01_581 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_ENABLE[2] origin:064-gtp-channel-conf 00_582 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_ENABLE[3] origin:064-gtp-channel-conf 01_582 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_USE origin:064-gtp-channel-conf 00_583 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_LEN[0] origin:064-gtp-channel-conf 00_589 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_LEN[1] origin:064-gtp-channel-conf 01_589 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.CLK_CORRECT_USE origin:064-gtp-channel-conf 00_551 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.DEC_MCOMMA_DETECT origin:064-gtp-channel-conf 01_494 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.DEC_PCOMMA_DETECT origin:064-gtp-channel-conf 00_495 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.DEC_VALID_COMMA_ONLY origin:064-gtp-channel-conf 00_494 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[0] origin:064-gtp-channel-conf 02_368 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[1] origin:064-gtp-channel-conf 03_368 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[2] origin:064-gtp-channel-conf 02_369 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[3] origin:064-gtp-channel-conf 03_369 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[4] origin:064-gtp-channel-conf 02_370 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[5] origin:064-gtp-channel-conf 03_370 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[6] origin:064-gtp-channel-conf 02_371 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[7] origin:064-gtp-channel-conf 03_371 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[8] origin:064-gtp-channel-conf 02_372 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[9] origin:064-gtp-channel-conf 03_372 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[10] origin:064-gtp-channel-conf 02_373 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[11] origin:064-gtp-channel-conf 03_373 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[12] origin:064-gtp-channel-conf 02_374 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[13] origin:064-gtp-channel-conf 03_374 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[14] origin:064-gtp-channel-conf 02_375 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[15] origin:064-gtp-channel-conf 03_375 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[16] origin:064-gtp-channel-conf 02_376 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[17] origin:064-gtp-channel-conf 03_376 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[18] origin:064-gtp-channel-conf 02_377 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[19] origin:064-gtp-channel-conf 03_377 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[20] origin:064-gtp-channel-conf 02_378 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[21] origin:064-gtp-channel-conf 03_378 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[22] origin:064-gtp-channel-conf 02_379 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[23] origin:064-gtp-channel-conf 03_379 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_CLK_PHASE_SEL[0] origin:064-gtp-channel-conf 03_463 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_CONTROL[0] origin:064-gtp-channel-conf 00_488 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_CONTROL[1] origin:064-gtp-channel-conf 01_488 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_CONTROL[2] origin:064-gtp-channel-conf 00_489 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_CONTROL[3] origin:064-gtp-channel-conf 01_489 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_CONTROL[4] origin:064-gtp-channel-conf 00_490 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_CONTROL[5] origin:064-gtp-channel-conf 01_490 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_ERRDET_EN origin:064-gtp-channel-conf 01_492 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_EYE_SCAN_EN origin:064-gtp-channel-conf 00_492 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_HORZ_OFFSET[0] origin:064-gtp-channel-conf 00_480 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_HORZ_OFFSET[1] origin:064-gtp-channel-conf 01_480 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_HORZ_OFFSET[2] origin:064-gtp-channel-conf 00_481 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_HORZ_OFFSET[3] origin:064-gtp-channel-conf 01_481 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_HORZ_OFFSET[4] origin:064-gtp-channel-conf 00_482 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_HORZ_OFFSET[5] origin:064-gtp-channel-conf 01_482 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_HORZ_OFFSET[6] origin:064-gtp-channel-conf 00_483 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_HORZ_OFFSET[7] origin:064-gtp-channel-conf 01_483 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_HORZ_OFFSET[8] origin:064-gtp-channel-conf 00_484 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_HORZ_OFFSET[9] origin:064-gtp-channel-conf 01_484 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_HORZ_OFFSET[10] origin:064-gtp-channel-conf 00_485 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_HORZ_OFFSET[11] origin:064-gtp-channel-conf 01_485 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_PMA_CFG[0] origin:064-gtp-channel-conf 02_624 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_PMA_CFG[1] origin:064-gtp-channel-conf 03_624 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_PMA_CFG[2] origin:064-gtp-channel-conf 02_625 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_PMA_CFG[3] origin:064-gtp-channel-conf 03_625 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_PMA_CFG[4] origin:064-gtp-channel-conf 02_626 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_PMA_CFG[5] origin:064-gtp-channel-conf 03_626 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_PMA_CFG[6] origin:064-gtp-channel-conf 02_627 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_PMA_CFG[7] origin:064-gtp-channel-conf 03_627 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_PMA_CFG[8] origin:064-gtp-channel-conf 02_628 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_PMA_CFG[9] origin:064-gtp-channel-conf 03_628 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_PRESCALE[0] origin:064-gtp-channel-conf 01_477 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_PRESCALE[1] origin:064-gtp-channel-conf 00_478 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_PRESCALE[2] origin:064-gtp-channel-conf 01_478 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_PRESCALE[3] origin:064-gtp-channel-conf 00_479 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_PRESCALE[4] origin:064-gtp-channel-conf 01_479 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[0] origin:064-gtp-channel-conf 00_392 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[1] origin:064-gtp-channel-conf 01_392 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[2] origin:064-gtp-channel-conf 00_393 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[3] origin:064-gtp-channel-conf 01_393 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[4] origin:064-gtp-channel-conf 00_394 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[5] origin:064-gtp-channel-conf 01_394 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[6] origin:064-gtp-channel-conf 00_395 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[7] origin:064-gtp-channel-conf 01_395 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[8] origin:064-gtp-channel-conf 00_396 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[9] origin:064-gtp-channel-conf 01_396 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[10] origin:064-gtp-channel-conf 00_397 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[11] origin:064-gtp-channel-conf 01_397 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[12] origin:064-gtp-channel-conf 00_398 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[13] origin:064-gtp-channel-conf 01_398 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[14] origin:064-gtp-channel-conf 00_399 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[15] origin:064-gtp-channel-conf 01_399 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[16] origin:064-gtp-channel-conf 00_400 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[17] origin:064-gtp-channel-conf 01_400 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[18] origin:064-gtp-channel-conf 00_401 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[19] origin:064-gtp-channel-conf 01_401 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[20] origin:064-gtp-channel-conf 00_402 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[21] origin:064-gtp-channel-conf 01_402 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[22] origin:064-gtp-channel-conf 00_403 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[23] origin:064-gtp-channel-conf 01_403 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[24] origin:064-gtp-channel-conf 00_404 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[25] origin:064-gtp-channel-conf 01_404 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[26] origin:064-gtp-channel-conf 00_405 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[27] origin:064-gtp-channel-conf 01_405 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[28] origin:064-gtp-channel-conf 00_406 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[29] origin:064-gtp-channel-conf 01_406 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[30] origin:064-gtp-channel-conf 00_407 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[31] origin:064-gtp-channel-conf 01_407 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[32] origin:064-gtp-channel-conf 00_408 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[33] origin:064-gtp-channel-conf 01_408 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[34] origin:064-gtp-channel-conf 00_409 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[35] origin:064-gtp-channel-conf 01_409 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[36] origin:064-gtp-channel-conf 00_410 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[37] origin:064-gtp-channel-conf 01_410 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[38] origin:064-gtp-channel-conf 00_411 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[39] origin:064-gtp-channel-conf 01_411 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[40] origin:064-gtp-channel-conf 00_412 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[41] origin:064-gtp-channel-conf 01_412 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[42] origin:064-gtp-channel-conf 00_413 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[43] origin:064-gtp-channel-conf 01_413 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[44] origin:064-gtp-channel-conf 00_414 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[45] origin:064-gtp-channel-conf 01_414 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[46] origin:064-gtp-channel-conf 00_415 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[47] origin:064-gtp-channel-conf 01_415 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[48] origin:064-gtp-channel-conf 00_416 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[49] origin:064-gtp-channel-conf 01_416 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[50] origin:064-gtp-channel-conf 00_417 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[51] origin:064-gtp-channel-conf 01_417 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[52] origin:064-gtp-channel-conf 00_418 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[53] origin:064-gtp-channel-conf 01_418 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[54] origin:064-gtp-channel-conf 00_419 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[55] origin:064-gtp-channel-conf 01_419 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[56] origin:064-gtp-channel-conf 00_420 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[57] origin:064-gtp-channel-conf 01_420 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[58] origin:064-gtp-channel-conf 00_421 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[59] origin:064-gtp-channel-conf 01_421 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[60] origin:064-gtp-channel-conf 00_422 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[61] origin:064-gtp-channel-conf 01_422 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[62] origin:064-gtp-channel-conf 00_423 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[63] origin:064-gtp-channel-conf 01_423 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[64] origin:064-gtp-channel-conf 00_424 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[65] origin:064-gtp-channel-conf 01_424 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[66] origin:064-gtp-channel-conf 00_425 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[67] origin:064-gtp-channel-conf 01_425 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[68] origin:064-gtp-channel-conf 00_426 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[69] origin:064-gtp-channel-conf 01_426 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[70] origin:064-gtp-channel-conf 00_427 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[71] origin:064-gtp-channel-conf 01_427 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[72] origin:064-gtp-channel-conf 00_428 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[73] origin:064-gtp-channel-conf 01_428 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[74] origin:064-gtp-channel-conf 00_429 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[75] origin:064-gtp-channel-conf 01_429 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[76] origin:064-gtp-channel-conf 00_430 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[77] origin:064-gtp-channel-conf 01_430 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[78] origin:064-gtp-channel-conf 00_431 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[79] origin:064-gtp-channel-conf 01_431 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[0] origin:064-gtp-channel-conf 00_352 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[1] origin:064-gtp-channel-conf 01_352 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[2] origin:064-gtp-channel-conf 00_353 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[3] origin:064-gtp-channel-conf 01_353 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[4] origin:064-gtp-channel-conf 00_354 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[5] origin:064-gtp-channel-conf 01_354 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[6] origin:064-gtp-channel-conf 00_355 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[7] origin:064-gtp-channel-conf 01_355 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[8] origin:064-gtp-channel-conf 00_356 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[9] origin:064-gtp-channel-conf 01_356 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[10] origin:064-gtp-channel-conf 00_357 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[11] origin:064-gtp-channel-conf 01_357 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[12] origin:064-gtp-channel-conf 00_358 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[13] origin:064-gtp-channel-conf 01_358 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[14] origin:064-gtp-channel-conf 00_359 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[15] origin:064-gtp-channel-conf 01_359 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[16] origin:064-gtp-channel-conf 00_360 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[17] origin:064-gtp-channel-conf 01_360 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[18] origin:064-gtp-channel-conf 00_361 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[19] origin:064-gtp-channel-conf 01_361 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[20] origin:064-gtp-channel-conf 00_362 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[21] origin:064-gtp-channel-conf 01_362 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[22] origin:064-gtp-channel-conf 00_363 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[23] origin:064-gtp-channel-conf 01_363 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[24] origin:064-gtp-channel-conf 00_364 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[25] origin:064-gtp-channel-conf 01_364 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[26] origin:064-gtp-channel-conf 00_365 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[27] origin:064-gtp-channel-conf 01_365 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[28] origin:064-gtp-channel-conf 00_366 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[29] origin:064-gtp-channel-conf 01_366 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[30] origin:064-gtp-channel-conf 00_367 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[31] origin:064-gtp-channel-conf 01_367 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[32] origin:064-gtp-channel-conf 00_368 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[33] origin:064-gtp-channel-conf 01_368 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[34] origin:064-gtp-channel-conf 00_369 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[35] origin:064-gtp-channel-conf 01_369 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[36] origin:064-gtp-channel-conf 00_370 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[37] origin:064-gtp-channel-conf 01_370 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[38] origin:064-gtp-channel-conf 00_371 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[39] origin:064-gtp-channel-conf 01_371 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[40] origin:064-gtp-channel-conf 00_372 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[41] origin:064-gtp-channel-conf 01_372 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[42] origin:064-gtp-channel-conf 00_373 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[43] origin:064-gtp-channel-conf 01_373 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[44] origin:064-gtp-channel-conf 00_374 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[45] origin:064-gtp-channel-conf 01_374 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[46] origin:064-gtp-channel-conf 00_375 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[47] origin:064-gtp-channel-conf 01_375 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[48] origin:064-gtp-channel-conf 00_376 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[49] origin:064-gtp-channel-conf 01_376 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[50] origin:064-gtp-channel-conf 00_377 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[51] origin:064-gtp-channel-conf 01_377 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[52] origin:064-gtp-channel-conf 00_378 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[53] origin:064-gtp-channel-conf 01_378 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[54] origin:064-gtp-channel-conf 00_379 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[55] origin:064-gtp-channel-conf 01_379 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[56] origin:064-gtp-channel-conf 00_380 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[57] origin:064-gtp-channel-conf 01_380 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[58] origin:064-gtp-channel-conf 00_381 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[59] origin:064-gtp-channel-conf 01_381 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[60] origin:064-gtp-channel-conf 00_382 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[61] origin:064-gtp-channel-conf 01_382 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[62] origin:064-gtp-channel-conf 00_383 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[63] origin:064-gtp-channel-conf 01_383 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[64] origin:064-gtp-channel-conf 00_384 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[65] origin:064-gtp-channel-conf 01_384 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[66] origin:064-gtp-channel-conf 00_385 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[67] origin:064-gtp-channel-conf 01_385 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[68] origin:064-gtp-channel-conf 00_386 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[69] origin:064-gtp-channel-conf 01_386 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[70] origin:064-gtp-channel-conf 00_387 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[71] origin:064-gtp-channel-conf 01_387 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[72] origin:064-gtp-channel-conf 00_388 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[73] origin:064-gtp-channel-conf 01_388 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[74] origin:064-gtp-channel-conf 00_389 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[75] origin:064-gtp-channel-conf 01_389 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[76] origin:064-gtp-channel-conf 00_390 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[77] origin:064-gtp-channel-conf 01_390 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[78] origin:064-gtp-channel-conf 00_391 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[79] origin:064-gtp-channel-conf 01_391 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[0] origin:064-gtp-channel-conf 00_432 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[1] origin:064-gtp-channel-conf 01_432 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[2] origin:064-gtp-channel-conf 00_433 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[3] origin:064-gtp-channel-conf 01_433 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[4] origin:064-gtp-channel-conf 00_434 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[5] origin:064-gtp-channel-conf 01_434 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[6] origin:064-gtp-channel-conf 00_435 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[7] origin:064-gtp-channel-conf 01_435 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[8] origin:064-gtp-channel-conf 00_436 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[9] origin:064-gtp-channel-conf 01_436 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[10] origin:064-gtp-channel-conf 00_437 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[11] origin:064-gtp-channel-conf 01_437 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[12] origin:064-gtp-channel-conf 00_438 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[13] origin:064-gtp-channel-conf 01_438 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[14] origin:064-gtp-channel-conf 00_439 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[15] origin:064-gtp-channel-conf 01_439 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[16] origin:064-gtp-channel-conf 00_440 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[17] origin:064-gtp-channel-conf 01_440 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[18] origin:064-gtp-channel-conf 00_441 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[19] origin:064-gtp-channel-conf 01_441 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[20] origin:064-gtp-channel-conf 00_442 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[21] origin:064-gtp-channel-conf 01_442 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[22] origin:064-gtp-channel-conf 00_443 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[23] origin:064-gtp-channel-conf 01_443 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[24] origin:064-gtp-channel-conf 00_444 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[25] origin:064-gtp-channel-conf 01_444 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[26] origin:064-gtp-channel-conf 00_445 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[27] origin:064-gtp-channel-conf 01_445 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[28] origin:064-gtp-channel-conf 00_446 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[29] origin:064-gtp-channel-conf 01_446 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[30] origin:064-gtp-channel-conf 00_447 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[31] origin:064-gtp-channel-conf 01_447 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[32] origin:064-gtp-channel-conf 00_448 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[33] origin:064-gtp-channel-conf 01_448 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[34] origin:064-gtp-channel-conf 00_449 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[35] origin:064-gtp-channel-conf 01_449 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[36] origin:064-gtp-channel-conf 00_450 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[37] origin:064-gtp-channel-conf 01_450 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[38] origin:064-gtp-channel-conf 00_451 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[39] origin:064-gtp-channel-conf 01_451 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[40] origin:064-gtp-channel-conf 00_452 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[41] origin:064-gtp-channel-conf 01_452 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[42] origin:064-gtp-channel-conf 00_453 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[43] origin:064-gtp-channel-conf 01_453 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[44] origin:064-gtp-channel-conf 00_454 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[45] origin:064-gtp-channel-conf 01_454 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[46] origin:064-gtp-channel-conf 00_455 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[47] origin:064-gtp-channel-conf 01_455 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[48] origin:064-gtp-channel-conf 00_456 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[49] origin:064-gtp-channel-conf 01_456 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[50] origin:064-gtp-channel-conf 00_457 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[51] origin:064-gtp-channel-conf 01_457 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[52] origin:064-gtp-channel-conf 00_458 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[53] origin:064-gtp-channel-conf 01_458 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[54] origin:064-gtp-channel-conf 00_459 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[55] origin:064-gtp-channel-conf 01_459 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[56] origin:064-gtp-channel-conf 00_460 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[57] origin:064-gtp-channel-conf 01_460 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[58] origin:064-gtp-channel-conf 00_461 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[59] origin:064-gtp-channel-conf 01_461 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[60] origin:064-gtp-channel-conf 00_462 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[61] origin:064-gtp-channel-conf 01_462 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[62] origin:064-gtp-channel-conf 00_463 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[63] origin:064-gtp-channel-conf 01_463 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[64] origin:064-gtp-channel-conf 00_464 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[65] origin:064-gtp-channel-conf 01_464 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[66] origin:064-gtp-channel-conf 00_465 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[67] origin:064-gtp-channel-conf 01_465 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[68] origin:064-gtp-channel-conf 00_466 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[69] origin:064-gtp-channel-conf 01_466 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[70] origin:064-gtp-channel-conf 00_467 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[71] origin:064-gtp-channel-conf 01_467 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[72] origin:064-gtp-channel-conf 00_468 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[73] origin:064-gtp-channel-conf 01_468 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[74] origin:064-gtp-channel-conf 00_469 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[75] origin:064-gtp-channel-conf 01_469 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[76] origin:064-gtp-channel-conf 00_470 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[77] origin:064-gtp-channel-conf 01_470 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[78] origin:064-gtp-channel-conf 00_471 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[79] origin:064-gtp-channel-conf 01_471 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_VERT_OFFSET[0] origin:064-gtp-channel-conf 00_472 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_VERT_OFFSET[1] origin:064-gtp-channel-conf 01_472 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_VERT_OFFSET[2] origin:064-gtp-channel-conf 00_473 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_VERT_OFFSET[3] origin:064-gtp-channel-conf 01_473 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_VERT_OFFSET[4] origin:064-gtp-channel-conf 00_474 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_VERT_OFFSET[5] origin:064-gtp-channel-conf 01_474 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_VERT_OFFSET[6] origin:064-gtp-channel-conf 00_475 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_VERT_OFFSET[7] origin:064-gtp-channel-conf 01_475 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.ES_VERT_OFFSET[8] origin:064-gtp-channel-conf 00_476 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.FTS_DESKEW_SEQ_ENABLE[0] origin:064-gtp-channel-conf 00_662 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.FTS_DESKEW_SEQ_ENABLE[1] origin:064-gtp-channel-conf 01_662 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.FTS_DESKEW_SEQ_ENABLE[2] origin:064-gtp-channel-conf 00_663 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.FTS_DESKEW_SEQ_ENABLE[3] origin:064-gtp-channel-conf 01_663 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.FTS_LANE_DESKEW_CFG[0] origin:064-gtp-channel-conf 00_654 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.FTS_LANE_DESKEW_CFG[1] origin:064-gtp-channel-conf 01_654 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.FTS_LANE_DESKEW_CFG[2] origin:064-gtp-channel-conf 00_655 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.FTS_LANE_DESKEW_CFG[3] origin:064-gtp-channel-conf 01_655 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.FTS_LANE_DESKEW_EN origin:064-gtp-channel-conf 01_653 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.GEARBOX_MODE[0] origin:064-gtp-channel-conf 00_224 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.GEARBOX_MODE[1] origin:064-gtp-channel-conf 01_224 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.GEARBOX_MODE[2] origin:064-gtp-channel-conf 00_225 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.IN_USE origin:064-gtp-channel-conf 00_00 00_01 00_47 00_52 00_53 00_65 01_01 01_47 02_129 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.INV_DMONITORCLK origin:064-gtp-channel-conf 02_13 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.INV_DRPCLK origin:064-gtp-channel-conf 02_00 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.INV_RXUSRCLK origin:064-gtp-channel-conf 03_01 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.INV_SIGVALIDCLK origin:064-gtp-channel-conf 03_13 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.INV_TXPHDLYTSTCLK origin:064-gtp-channel-conf 02_03 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.INV_TXUSRCLK origin:064-gtp-channel-conf 03_04 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.INV_CLKRSVD0 origin:064-gtp-channel-conf 02_23 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.INV_CLKRSVD1 origin:064-gtp-channel-conf 03_23 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.INV_RXUSRCLK2 origin:064-gtp-channel-conf 02_02 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.INV_TXUSRCLK2 origin:064-gtp-channel-conf 02_05 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.LOOPBACK_CFG[0] origin:064-gtp-channel-conf 02_20 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.OUTREFCLK_SEL_INV[0] origin:064-gtp-channel-conf 00_149 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.OUTREFCLK_SEL_INV[1] origin:064-gtp-channel-conf 01_149 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PCS_PCIE_EN origin:064-gtp-channel-conf 00_216 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[0] origin:064-gtp-channel-conf 02_184 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[1] origin:064-gtp-channel-conf 03_184 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[2] origin:064-gtp-channel-conf 02_185 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[3] origin:064-gtp-channel-conf 03_185 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[4] origin:064-gtp-channel-conf 02_186 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[5] origin:064-gtp-channel-conf 03_186 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[6] origin:064-gtp-channel-conf 02_187 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[7] origin:064-gtp-channel-conf 03_187 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[8] origin:064-gtp-channel-conf 02_188 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[9] origin:064-gtp-channel-conf 03_188 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[10] origin:064-gtp-channel-conf 02_189 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[11] origin:064-gtp-channel-conf 03_189 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[12] origin:064-gtp-channel-conf 02_190 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[13] origin:064-gtp-channel-conf 03_190 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[14] origin:064-gtp-channel-conf 02_191 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[15] origin:064-gtp-channel-conf 03_191 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[16] origin:064-gtp-channel-conf 02_192 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[17] origin:064-gtp-channel-conf 03_192 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[18] origin:064-gtp-channel-conf 02_193 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[19] origin:064-gtp-channel-conf 03_193 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[20] origin:064-gtp-channel-conf 02_194 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[21] origin:064-gtp-channel-conf 03_194 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[22] origin:064-gtp-channel-conf 02_195 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[23] origin:064-gtp-channel-conf 03_195 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[24] origin:064-gtp-channel-conf 02_196 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[25] origin:064-gtp-channel-conf 03_196 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[26] origin:064-gtp-channel-conf 02_197 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[27] origin:064-gtp-channel-conf 03_197 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[28] origin:064-gtp-channel-conf 02_198 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[29] origin:064-gtp-channel-conf 03_198 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[30] origin:064-gtp-channel-conf 02_199 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[31] origin:064-gtp-channel-conf 03_199 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[32] origin:064-gtp-channel-conf 02_200 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[33] origin:064-gtp-channel-conf 03_200 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[34] origin:064-gtp-channel-conf 02_201 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[35] origin:064-gtp-channel-conf 03_201 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[36] origin:064-gtp-channel-conf 02_202 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[37] origin:064-gtp-channel-conf 03_202 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[38] origin:064-gtp-channel-conf 02_203 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[39] origin:064-gtp-channel-conf 03_203 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[40] origin:064-gtp-channel-conf 02_204 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[41] origin:064-gtp-channel-conf 03_204 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[42] origin:064-gtp-channel-conf 02_205 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[43] origin:064-gtp-channel-conf 03_205 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[44] origin:064-gtp-channel-conf 02_206 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[45] origin:064-gtp-channel-conf 03_206 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[46] origin:064-gtp-channel-conf 02_207 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[47] origin:064-gtp-channel-conf 03_207 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[0] origin:064-gtp-channel-conf 01_216 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[1] origin:064-gtp-channel-conf 00_217 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[2] origin:064-gtp-channel-conf 01_217 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[3] origin:064-gtp-channel-conf 00_218 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[4] origin:064-gtp-channel-conf 01_218 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[5] origin:064-gtp-channel-conf 00_219 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[6] origin:064-gtp-channel-conf 01_219 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[7] origin:064-gtp-channel-conf 00_220 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[8] origin:064-gtp-channel-conf 01_220 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[9] origin:064-gtp-channel-conf 00_221 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[10] origin:064-gtp-channel-conf 01_221 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[11] origin:064-gtp-channel-conf 00_222 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[0] origin:064-gtp-channel-conf 00_208 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[1] origin:064-gtp-channel-conf 01_208 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[2] origin:064-gtp-channel-conf 00_209 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[3] origin:064-gtp-channel-conf 01_209 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[4] origin:064-gtp-channel-conf 00_210 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[5] origin:064-gtp-channel-conf 01_210 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[6] origin:064-gtp-channel-conf 00_211 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[7] origin:064-gtp-channel-conf 01_211 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[0] origin:064-gtp-channel-conf 00_212 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[1] origin:064-gtp-channel-conf 01_212 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[2] origin:064-gtp-channel-conf 00_213 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[3] origin:064-gtp-channel-conf 01_213 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[4] origin:064-gtp-channel-conf 00_214 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[5] origin:064-gtp-channel-conf 01_214 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[6] origin:064-gtp-channel-conf 00_215 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[7] origin:064-gtp-channel-conf 01_215 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PMA_LOOPBACK_CFG[0] origin:064-gtp-channel-conf 01_207 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[0] origin:064-gtp-channel-conf 02_520 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[1] origin:064-gtp-channel-conf 03_520 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[2] origin:064-gtp-channel-conf 02_521 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[3] origin:064-gtp-channel-conf 03_521 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[4] origin:064-gtp-channel-conf 02_522 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[5] origin:064-gtp-channel-conf 03_522 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[6] origin:064-gtp-channel-conf 02_523 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[7] origin:064-gtp-channel-conf 03_523 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[8] origin:064-gtp-channel-conf 02_524 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[9] origin:064-gtp-channel-conf 03_524 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[10] origin:064-gtp-channel-conf 02_525 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[11] origin:064-gtp-channel-conf 03_525 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[12] origin:064-gtp-channel-conf 02_526 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[13] origin:064-gtp-channel-conf 03_526 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[14] origin:064-gtp-channel-conf 02_527 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[15] origin:064-gtp-channel-conf 03_527 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[16] origin:064-gtp-channel-conf 02_528 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[17] origin:064-gtp-channel-conf 03_528 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[18] origin:064-gtp-channel-conf 02_529 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[19] origin:064-gtp-channel-conf 03_529 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[20] origin:064-gtp-channel-conf 02_530 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[21] origin:064-gtp-channel-conf 03_530 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[22] origin:064-gtp-channel-conf 02_531 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[23] origin:064-gtp-channel-conf 03_531 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[24] origin:064-gtp-channel-conf 02_532 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[25] origin:064-gtp-channel-conf 03_532 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[26] origin:064-gtp-channel-conf 02_533 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[27] origin:064-gtp-channel-conf 03_533 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[28] origin:064-gtp-channel-conf 02_534 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[29] origin:064-gtp-channel-conf 03_534 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[30] origin:064-gtp-channel-conf 02_535 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[31] origin:064-gtp-channel-conf 03_535 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[0] origin:064-gtp-channel-conf 02_336 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[1] origin:064-gtp-channel-conf 03_336 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[2] origin:064-gtp-channel-conf 02_337 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[3] origin:064-gtp-channel-conf 03_337 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[4] origin:064-gtp-channel-conf 02_338 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[5] origin:064-gtp-channel-conf 03_338 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[6] origin:064-gtp-channel-conf 02_339 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[7] origin:064-gtp-channel-conf 03_339 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[8] origin:064-gtp-channel-conf 02_340 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[9] origin:064-gtp-channel-conf 03_340 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[10] origin:064-gtp-channel-conf 02_341 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[11] origin:064-gtp-channel-conf 03_341 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[12] origin:064-gtp-channel-conf 02_342 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[13] origin:064-gtp-channel-conf 03_342 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[14] origin:064-gtp-channel-conf 02_343 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[15] origin:064-gtp-channel-conf 03_343 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[16] origin:064-gtp-channel-conf 02_344 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[17] origin:064-gtp-channel-conf 03_344 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[18] origin:064-gtp-channel-conf 02_345 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[19] origin:064-gtp-channel-conf 03_345 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[20] origin:064-gtp-channel-conf 02_346 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[21] origin:064-gtp-channel-conf 03_346 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[22] origin:064-gtp-channel-conf 02_347 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[23] origin:064-gtp-channel-conf 03_347 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[24] origin:064-gtp-channel-conf 02_348 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[25] origin:064-gtp-channel-conf 03_348 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[26] origin:064-gtp-channel-conf 02_349 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[27] origin:064-gtp-channel-conf 03_349 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[28] origin:064-gtp-channel-conf 02_350 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[29] origin:064-gtp-channel-conf 03_350 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[30] origin:064-gtp-channel-conf 02_351 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[31] origin:064-gtp-channel-conf 03_351 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PMA_RSV3[0] origin:064-gtp-channel-conf 02_288 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PMA_RSV3[1] origin:064-gtp-channel-conf 03_288 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PMA_RSV4[0] origin:064-gtp-channel-conf 02_156 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PMA_RSV4[1] origin:064-gtp-channel-conf 03_156 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PMA_RSV4[2] origin:064-gtp-channel-conf 02_157 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PMA_RSV4[3] origin:064-gtp-channel-conf 03_157 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PMA_RSV5[0] origin:064-gtp-channel-conf 03_159 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PMA_RSV6[0] origin:064-gtp-channel-conf 02_303 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.PMA_RSV7[0] origin:064-gtp-channel-conf 03_303 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_BIAS_CFG[0] origin:064-gtp-channel-conf 02_112 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_BIAS_CFG[1] origin:064-gtp-channel-conf 03_112 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_BIAS_CFG[2] origin:064-gtp-channel-conf 02_113 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_BIAS_CFG[3] origin:064-gtp-channel-conf 03_113 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_BIAS_CFG[4] origin:064-gtp-channel-conf 02_114 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_BIAS_CFG[5] origin:064-gtp-channel-conf 03_114 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_BIAS_CFG[6] origin:064-gtp-channel-conf 02_115 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_BIAS_CFG[7] origin:064-gtp-channel-conf 03_115 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_BIAS_CFG[8] origin:064-gtp-channel-conf 02_116 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_BIAS_CFG[9] origin:064-gtp-channel-conf 03_116 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_BIAS_CFG[10] origin:064-gtp-channel-conf 02_117 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_BIAS_CFG[11] origin:064-gtp-channel-conf 03_117 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_BIAS_CFG[12] origin:064-gtp-channel-conf 02_118 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_BIAS_CFG[13] origin:064-gtp-channel-conf 03_118 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_BIAS_CFG[14] origin:064-gtp-channel-conf 02_119 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_BIAS_CFG[15] origin:064-gtp-channel-conf 03_119 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_BUFFER_CFG[0] origin:064-gtp-channel-conf 02_536 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_BUFFER_CFG[1] origin:064-gtp-channel-conf 03_536 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_BUFFER_CFG[2] origin:064-gtp-channel-conf 02_537 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_BUFFER_CFG[3] origin:064-gtp-channel-conf 03_537 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_BUFFER_CFG[4] origin:064-gtp-channel-conf 02_538 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_BUFFER_CFG[5] origin:064-gtp-channel-conf 03_538 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_CLKMUX_EN[0] origin:064-gtp-channel-conf 02_128 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_CM_SEL[0] origin:064-gtp-channel-conf 00_138 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_CM_SEL[1] origin:064-gtp-channel-conf 01_138 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_CM_TRIM[0] origin:064-gtp-channel-conf 02_304 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_CM_TRIM[1] origin:064-gtp-channel-conf 03_304 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_CM_TRIM[2] origin:064-gtp-channel-conf 02_305 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_CM_TRIM[3] origin:064-gtp-channel-conf 03_305 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_DATA_WIDTH[0] origin:064-gtp-channel-conf 01_141 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_DATA_WIDTH[1] origin:064-gtp-channel-conf 00_142 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_DATA_WIDTH[2] origin:064-gtp-channel-conf 01_142 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_DDI_SEL[0] origin:064-gtp-channel-conf 00_696 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_DDI_SEL[1] origin:064-gtp-channel-conf 01_696 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_DDI_SEL[2] origin:064-gtp-channel-conf 00_697 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_DDI_SEL[3] origin:064-gtp-channel-conf 01_697 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_DDI_SEL[4] origin:064-gtp-channel-conf 00_698 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_DDI_SEL[5] origin:064-gtp-channel-conf 01_698 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_DEBUG_CFG[0] origin:064-gtp-channel-conf 02_616 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_DEBUG_CFG[1] origin:064-gtp-channel-conf 03_616 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_DEBUG_CFG[2] origin:064-gtp-channel-conf 02_617 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_DEBUG_CFG[3] origin:064-gtp-channel-conf 03_617 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_DEBUG_CFG[4] origin:064-gtp-channel-conf 02_618 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_DEBUG_CFG[5] origin:064-gtp-channel-conf 03_618 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_DEBUG_CFG[6] origin:064-gtp-channel-conf 02_619 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_DEBUG_CFG[7] origin:064-gtp-channel-conf 03_619 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_DEBUG_CFG[8] origin:064-gtp-channel-conf 02_620 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_DEBUG_CFG[9] origin:064-gtp-channel-conf 03_620 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_DEBUG_CFG[10] origin:064-gtp-channel-conf 02_621 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_DEBUG_CFG[11] origin:064-gtp-channel-conf 03_621 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_DEBUG_CFG[12] origin:064-gtp-channel-conf 02_622 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_DEBUG_CFG[13] origin:064-gtp-channel-conf 03_622 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_DEFER_RESET_BUF_EN origin:064-gtp-channel-conf 02_552 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_DISPERR_SEQ_MATCH origin:064-gtp-channel-conf 01_495 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_OS_CFG[0] origin:064-gtp-channel-conf 00_288 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_OS_CFG[1] origin:064-gtp-channel-conf 01_288 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_OS_CFG[2] origin:064-gtp-channel-conf 00_289 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_OS_CFG[3] origin:064-gtp-channel-conf 01_289 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_OS_CFG[4] origin:064-gtp-channel-conf 00_290 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_OS_CFG[5] origin:064-gtp-channel-conf 01_290 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_OS_CFG[6] origin:064-gtp-channel-conf 00_291 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_OS_CFG[7] origin:064-gtp-channel-conf 01_291 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_OS_CFG[8] origin:064-gtp-channel-conf 00_292 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_OS_CFG[9] origin:064-gtp-channel-conf 01_292 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_OS_CFG[10] origin:064-gtp-channel-conf 00_293 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_OS_CFG[11] origin:064-gtp-channel-conf 01_293 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_OS_CFG[12] origin:064-gtp-channel-conf 00_294 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_SIG_VALID_DLY[0] origin:064-gtp-channel-conf 00_524 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_SIG_VALID_DLY[1] origin:064-gtp-channel-conf 01_524 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_SIG_VALID_DLY[2] origin:064-gtp-channel-conf 00_525 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_SIG_VALID_DLY[3] origin:064-gtp-channel-conf 01_525 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_SIG_VALID_DLY[4] origin:064-gtp-channel-conf 00_526 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_XCLK_SEL.RXUSR origin:064-gtp-channel-conf 00_143 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_CLK25_DIV[0] origin:064-gtp-channel-conf 00_139 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_CLK25_DIV[1] origin:064-gtp-channel-conf 01_139 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_CLK25_DIV[2] origin:064-gtp-channel-conf 00_140 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_CLK25_DIV[3] origin:064-gtp-channel-conf 01_140 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RX_CLK25_DIV[4] origin:064-gtp-channel-conf 00_141 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXBUF_ADDR_MODE.FAST origin:064-gtp-channel-conf 03_555 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXBUF_EIDLE_HI_CNT[0] origin:064-gtp-channel-conf 02_558 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXBUF_EIDLE_HI_CNT[1] origin:064-gtp-channel-conf 03_558 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXBUF_EIDLE_HI_CNT[2] origin:064-gtp-channel-conf 02_559 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXBUF_EIDLE_HI_CNT[3] origin:064-gtp-channel-conf 03_559 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXBUF_EIDLE_LO_CNT[0] origin:064-gtp-channel-conf 02_556 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXBUF_EIDLE_LO_CNT[1] origin:064-gtp-channel-conf 03_556 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXBUF_EIDLE_LO_CNT[2] origin:064-gtp-channel-conf 02_557 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXBUF_EIDLE_LO_CNT[3] origin:064-gtp-channel-conf 03_557 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXBUF_EN origin:064-gtp-channel-conf 02_11 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXBUF_RESET_ON_CB_CHANGE origin:064-gtp-channel-conf 02_560 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXBUF_RESET_ON_COMMAALIGN origin:064-gtp-channel-conf 02_561 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXBUF_RESET_ON_EIDLE origin:064-gtp-channel-conf 02_547 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXBUF_RESET_ON_RATE_CHANGE origin:064-gtp-channel-conf 03_560 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXBUF_THRESH_OVFLW[0] origin:064-gtp-channel-conf 03_552 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXBUF_THRESH_OVFLW[1] origin:064-gtp-channel-conf 02_553 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXBUF_THRESH_OVFLW[2] origin:064-gtp-channel-conf 03_553 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXBUF_THRESH_OVFLW[3] origin:064-gtp-channel-conf 02_554 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXBUF_THRESH_OVFLW[4] origin:064-gtp-channel-conf 03_554 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXBUF_THRESH_OVFLW[5] origin:064-gtp-channel-conf 02_555 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXBUF_THRESH_OVRD origin:064-gtp-channel-conf 02_548 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXBUF_THRESH_UNDFLW[0] origin:064-gtp-channel-conf 02_544 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXBUF_THRESH_UNDFLW[1] origin:064-gtp-channel-conf 03_544 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXBUF_THRESH_UNDFLW[2] origin:064-gtp-channel-conf 02_545 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXBUF_THRESH_UNDFLW[3] origin:064-gtp-channel-conf 03_545 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXBUF_THRESH_UNDFLW[4] origin:064-gtp-channel-conf 02_546 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXBUF_THRESH_UNDFLW[5] origin:064-gtp-channel-conf 03_546 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXBUFRESET_TIME[0] origin:064-gtp-channel-conf 01_101 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXBUFRESET_TIME[1] origin:064-gtp-channel-conf 00_102 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXBUFRESET_TIME[2] origin:064-gtp-channel-conf 01_102 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXBUFRESET_TIME[3] origin:064-gtp-channel-conf 00_103 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXBUFRESET_TIME[4] origin:064-gtp-channel-conf 01_103 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[0] origin:064-gtp-channel-conf 02_640 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[1] origin:064-gtp-channel-conf 03_640 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[2] origin:064-gtp-channel-conf 02_641 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[3] origin:064-gtp-channel-conf 03_641 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[4] origin:064-gtp-channel-conf 02_642 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[5] origin:064-gtp-channel-conf 03_642 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[6] origin:064-gtp-channel-conf 02_643 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[7] origin:064-gtp-channel-conf 03_643 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[8] origin:064-gtp-channel-conf 02_644 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[9] origin:064-gtp-channel-conf 03_644 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[10] origin:064-gtp-channel-conf 02_645 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[11] origin:064-gtp-channel-conf 03_645 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[12] origin:064-gtp-channel-conf 02_646 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[13] origin:064-gtp-channel-conf 03_646 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[14] origin:064-gtp-channel-conf 02_647 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[15] origin:064-gtp-channel-conf 03_647 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[16] origin:064-gtp-channel-conf 02_648 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[17] origin:064-gtp-channel-conf 03_648 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[18] origin:064-gtp-channel-conf 02_649 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[19] origin:064-gtp-channel-conf 03_649 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[20] origin:064-gtp-channel-conf 02_650 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[21] origin:064-gtp-channel-conf 03_650 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[22] origin:064-gtp-channel-conf 02_651 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[23] origin:064-gtp-channel-conf 03_651 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[24] origin:064-gtp-channel-conf 02_652 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[25] origin:064-gtp-channel-conf 03_652 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[26] origin:064-gtp-channel-conf 02_653 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[27] origin:064-gtp-channel-conf 03_653 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[28] origin:064-gtp-channel-conf 02_654 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[29] origin:064-gtp-channel-conf 03_654 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[30] origin:064-gtp-channel-conf 02_655 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[31] origin:064-gtp-channel-conf 03_655 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[32] origin:064-gtp-channel-conf 02_656 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[33] origin:064-gtp-channel-conf 03_656 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[34] origin:064-gtp-channel-conf 02_657 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[35] origin:064-gtp-channel-conf 03_657 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[36] origin:064-gtp-channel-conf 02_658 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[37] origin:064-gtp-channel-conf 03_658 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[38] origin:064-gtp-channel-conf 02_659 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[39] origin:064-gtp-channel-conf 03_659 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[40] origin:064-gtp-channel-conf 02_660 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[41] origin:064-gtp-channel-conf 03_660 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[42] origin:064-gtp-channel-conf 02_661 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[43] origin:064-gtp-channel-conf 03_661 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[44] origin:064-gtp-channel-conf 02_662 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[45] origin:064-gtp-channel-conf 03_662 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[46] origin:064-gtp-channel-conf 02_663 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[47] origin:064-gtp-channel-conf 03_663 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[48] origin:064-gtp-channel-conf 02_664 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[49] origin:064-gtp-channel-conf 03_664 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[50] origin:064-gtp-channel-conf 02_665 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[51] origin:064-gtp-channel-conf 03_665 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[52] origin:064-gtp-channel-conf 02_666 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[53] origin:064-gtp-channel-conf 03_666 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[54] origin:064-gtp-channel-conf 02_667 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[55] origin:064-gtp-channel-conf 03_667 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[56] origin:064-gtp-channel-conf 02_668 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[57] origin:064-gtp-channel-conf 03_668 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[58] origin:064-gtp-channel-conf 02_669 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[59] origin:064-gtp-channel-conf 03_669 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[60] origin:064-gtp-channel-conf 02_670 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[61] origin:064-gtp-channel-conf 03_670 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[62] origin:064-gtp-channel-conf 02_671 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[63] origin:064-gtp-channel-conf 03_671 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[64] origin:064-gtp-channel-conf 02_672 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[65] origin:064-gtp-channel-conf 03_672 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[66] origin:064-gtp-channel-conf 02_673 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[67] origin:064-gtp-channel-conf 03_673 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[68] origin:064-gtp-channel-conf 02_674 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[69] origin:064-gtp-channel-conf 03_674 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[70] origin:064-gtp-channel-conf 02_675 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[71] origin:064-gtp-channel-conf 03_675 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[72] origin:064-gtp-channel-conf 02_676 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[73] origin:064-gtp-channel-conf 03_676 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[74] origin:064-gtp-channel-conf 02_677 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[75] origin:064-gtp-channel-conf 03_677 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[76] origin:064-gtp-channel-conf 02_678 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[77] origin:064-gtp-channel-conf 03_678 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[78] origin:064-gtp-channel-conf 02_679 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[79] origin:064-gtp-channel-conf 03_679 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[80] origin:064-gtp-channel-conf 02_680 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[81] origin:064-gtp-channel-conf 03_680 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[82] origin:064-gtp-channel-conf 02_681 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_FR_RESET_ON_EIDLE[0] origin:064-gtp-channel-conf 02_638 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_HOLD_DURING_EIDLE[0] origin:064-gtp-channel-conf 03_637 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_LOCK_CFG[0] origin:064-gtp-channel-conf 02_632 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_LOCK_CFG[1] origin:064-gtp-channel-conf 03_632 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_LOCK_CFG[2] origin:064-gtp-channel-conf 02_633 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_LOCK_CFG[3] origin:064-gtp-channel-conf 03_633 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_LOCK_CFG[4] origin:064-gtp-channel-conf 02_634 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_LOCK_CFG[5] origin:064-gtp-channel-conf 03_634 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDR_PH_RESET_ON_EIDLE[0] origin:064-gtp-channel-conf 03_638 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDRFREQRESET_TIME[0] origin:064-gtp-channel-conf 01_106 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDRFREQRESET_TIME[1] origin:064-gtp-channel-conf 00_107 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDRFREQRESET_TIME[2] origin:064-gtp-channel-conf 01_107 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDRFREQRESET_TIME[3] origin:064-gtp-channel-conf 00_108 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDRFREQRESET_TIME[4] origin:064-gtp-channel-conf 01_108 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDRPHRESET_TIME[0] origin:064-gtp-channel-conf 00_109 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDRPHRESET_TIME[1] origin:064-gtp-channel-conf 01_109 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDRPHRESET_TIME[2] origin:064-gtp-channel-conf 00_110 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDRPHRESET_TIME[3] origin:064-gtp-channel-conf 01_110 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXCDRPHRESET_TIME[4] origin:064-gtp-channel-conf 00_111 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXDLY_CFG[0] origin:064-gtp-channel-conf 00_680 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXDLY_CFG[1] origin:064-gtp-channel-conf 01_680 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXDLY_CFG[2] origin:064-gtp-channel-conf 00_681 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXDLY_CFG[3] origin:064-gtp-channel-conf 01_681 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXDLY_CFG[4] origin:064-gtp-channel-conf 00_682 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXDLY_CFG[5] origin:064-gtp-channel-conf 01_682 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXDLY_CFG[6] origin:064-gtp-channel-conf 00_683 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXDLY_CFG[7] origin:064-gtp-channel-conf 01_683 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXDLY_CFG[8] origin:064-gtp-channel-conf 00_684 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXDLY_CFG[9] origin:064-gtp-channel-conf 01_684 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXDLY_CFG[10] origin:064-gtp-channel-conf 00_685 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXDLY_CFG[11] origin:064-gtp-channel-conf 01_685 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXDLY_CFG[12] origin:064-gtp-channel-conf 00_686 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXDLY_CFG[13] origin:064-gtp-channel-conf 01_686 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXDLY_CFG[14] origin:064-gtp-channel-conf 00_687 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXDLY_CFG[15] origin:064-gtp-channel-conf 01_687 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXDLY_LCFG[0] origin:064-gtp-channel-conf 02_576 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXDLY_LCFG[1] origin:064-gtp-channel-conf 03_576 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXDLY_LCFG[2] origin:064-gtp-channel-conf 02_577 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXDLY_LCFG[3] origin:064-gtp-channel-conf 03_577 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXDLY_LCFG[4] origin:064-gtp-channel-conf 02_578 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXDLY_LCFG[5] origin:064-gtp-channel-conf 03_578 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXDLY_LCFG[6] origin:064-gtp-channel-conf 02_579 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXDLY_LCFG[7] origin:064-gtp-channel-conf 03_579 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXDLY_LCFG[8] origin:064-gtp-channel-conf 02_580 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXDLY_TAP_CFG[0] origin:064-gtp-channel-conf 00_672 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXDLY_TAP_CFG[1] origin:064-gtp-channel-conf 01_672 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXDLY_TAP_CFG[2] origin:064-gtp-channel-conf 00_673 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXDLY_TAP_CFG[3] origin:064-gtp-channel-conf 01_673 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXDLY_TAP_CFG[4] origin:064-gtp-channel-conf 00_674 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXDLY_TAP_CFG[5] origin:064-gtp-channel-conf 01_674 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXDLY_TAP_CFG[6] origin:064-gtp-channel-conf 00_675 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXDLY_TAP_CFG[7] origin:064-gtp-channel-conf 01_675 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXDLY_TAP_CFG[8] origin:064-gtp-channel-conf 00_676 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXDLY_TAP_CFG[9] origin:064-gtp-channel-conf 01_676 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXDLY_TAP_CFG[10] origin:064-gtp-channel-conf 00_677 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXDLY_TAP_CFG[11] origin:064-gtp-channel-conf 01_677 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXDLY_TAP_CFG[12] origin:064-gtp-channel-conf 00_678 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXDLY_TAP_CFG[13] origin:064-gtp-channel-conf 01_678 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXDLY_TAP_CFG[14] origin:064-gtp-channel-conf 00_679 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXDLY_TAP_CFG[15] origin:064-gtp-channel-conf 01_679 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXGEARBOX_EN origin:064-gtp-channel-conf 01_607 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXISCANRESET_TIME[0] origin:064-gtp-channel-conf 01_123 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXISCANRESET_TIME[1] origin:064-gtp-channel-conf 00_124 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXISCANRESET_TIME[2] origin:064-gtp-channel-conf 01_124 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXISCANRESET_TIME[3] origin:064-gtp-channel-conf 00_125 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXISCANRESET_TIME[4] origin:064-gtp-channel-conf 01_125 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPM_BIAS_STARTUP_DISABLE[0] origin:064-gtp-channel-conf 03_391 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPM_CFG[0] origin:064-gtp-channel-conf 02_328 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPM_CFG[1] origin:064-gtp-channel-conf 03_328 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPM_CFG[2] origin:064-gtp-channel-conf 02_329 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPM_CFG[3] origin:064-gtp-channel-conf 03_329 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPM_CM_CFG[0] origin:064-gtp-channel-conf 02_430 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPM_GC_CFG[0] origin:064-gtp-channel-conf 02_432 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPM_GC_CFG[1] origin:064-gtp-channel-conf 03_432 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPM_GC_CFG[2] origin:064-gtp-channel-conf 02_433 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPM_GC_CFG[3] origin:064-gtp-channel-conf 03_433 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPM_GC_CFG[4] origin:064-gtp-channel-conf 02_434 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPM_GC_CFG[5] origin:064-gtp-channel-conf 03_434 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPM_GC_CFG[6] origin:064-gtp-channel-conf 02_435 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPM_GC_CFG[7] origin:064-gtp-channel-conf 03_435 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPM_GC_CFG[8] origin:064-gtp-channel-conf 02_436 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPM_GC_CFG2[0] origin:064-gtp-channel-conf 03_442 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPM_GC_CFG2[1] origin:064-gtp-channel-conf 02_443 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPM_GC_CFG2[2] origin:064-gtp-channel-conf 03_443 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG[0] origin:064-gtp-channel-conf 00_336 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG[1] origin:064-gtp-channel-conf 01_336 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG[2] origin:064-gtp-channel-conf 00_337 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG[3] origin:064-gtp-channel-conf 01_337 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG[4] origin:064-gtp-channel-conf 00_338 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG[5] origin:064-gtp-channel-conf 01_338 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG[6] origin:064-gtp-channel-conf 00_339 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG[7] origin:064-gtp-channel-conf 01_339 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG[8] origin:064-gtp-channel-conf 00_340 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG[9] origin:064-gtp-channel-conf 01_340 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG[10] origin:064-gtp-channel-conf 00_341 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG[11] origin:064-gtp-channel-conf 01_341 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG[12] origin:064-gtp-channel-conf 00_342 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG[13] origin:064-gtp-channel-conf 01_342 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG2[0] origin:064-gtp-channel-conf 02_424 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG2[1] origin:064-gtp-channel-conf 03_424 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG2[2] origin:064-gtp-channel-conf 02_425 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG2[3] origin:064-gtp-channel-conf 03_425 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG2[4] origin:064-gtp-channel-conf 02_426 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG3[0] origin:064-gtp-channel-conf 03_389 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG3[1] origin:064-gtp-channel-conf 02_390 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG3[2] origin:064-gtp-channel-conf 03_390 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG3[3] origin:064-gtp-channel-conf 02_391 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPM_HOLD_DURING_EIDLE[0] origin:064-gtp-channel-conf 00_247 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPM_INCM_CFG[0] origin:064-gtp-channel-conf 02_439 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPM_IPCM_CFG[0] origin:064-gtp-channel-conf 03_439 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG[0] origin:064-gtp-channel-conf 00_344 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG[1] origin:064-gtp-channel-conf 01_344 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG[2] origin:064-gtp-channel-conf 00_345 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG[3] origin:064-gtp-channel-conf 01_345 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG[4] origin:064-gtp-channel-conf 00_346 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG[5] origin:064-gtp-channel-conf 01_346 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG[6] origin:064-gtp-channel-conf 00_347 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG[7] origin:064-gtp-channel-conf 01_347 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG[8] origin:064-gtp-channel-conf 00_348 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG[9] origin:064-gtp-channel-conf 01_348 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG[10] origin:064-gtp-channel-conf 00_349 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG[11] origin:064-gtp-channel-conf 01_349 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG[12] origin:064-gtp-channel-conf 00_350 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG[13] origin:064-gtp-channel-conf 01_350 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG[14] origin:064-gtp-channel-conf 00_351 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG[15] origin:064-gtp-channel-conf 01_351 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG[16] origin:064-gtp-channel-conf 00_343 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG[17] origin:064-gtp-channel-conf 01_343 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG2[0] origin:064-gtp-channel-conf 03_426 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG2[1] origin:064-gtp-channel-conf 02_427 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG2[2] origin:064-gtp-channel-conf 03_427 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG2[3] origin:064-gtp-channel-conf 02_428 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG2[4] origin:064-gtp-channel-conf 03_428 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPM_OSINT_CFG[0] origin:064-gtp-channel-conf 02_440 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPM_OSINT_CFG[1] origin:064-gtp-channel-conf 03_440 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPM_OSINT_CFG[2] origin:064-gtp-channel-conf 02_441 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPM_CFG1[0] origin:064-gtp-channel-conf 02_330 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPMRESET_TIME[0] origin:064-gtp-channel-conf 00_112 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPMRESET_TIME[1] origin:064-gtp-channel-conf 01_112 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPMRESET_TIME[2] origin:064-gtp-channel-conf 00_113 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPMRESET_TIME[3] origin:064-gtp-channel-conf 01_113 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPMRESET_TIME[4] origin:064-gtp-channel-conf 00_114 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPMRESET_TIME[5] origin:064-gtp-channel-conf 01_114 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXLPMRESET_TIME[6] origin:064-gtp-channel-conf 00_115 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXOOB_CFG[0] origin:064-gtp-channel-conf 00_144 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXOOB_CFG[1] origin:064-gtp-channel-conf 01_144 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXOOB_CFG[2] origin:064-gtp-channel-conf 00_145 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXOOB_CFG[3] origin:064-gtp-channel-conf 01_145 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXOOB_CFG[4] origin:064-gtp-channel-conf 00_146 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXOOB_CFG[5] origin:064-gtp-channel-conf 01_146 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXOOB_CFG[6] origin:064-gtp-channel-conf 00_147 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXOOB_CLK_CFG.FABRIC origin:064-gtp-channel-conf 03_129 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXOSCALRESET_TIME[0] origin:064-gtp-channel-conf 00_187 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXOSCALRESET_TIME[1] origin:064-gtp-channel-conf 01_187 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXOSCALRESET_TIME[2] origin:064-gtp-channel-conf 00_188 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXOSCALRESET_TIME[3] origin:064-gtp-channel-conf 01_188 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXOSCALRESET_TIME[4] origin:064-gtp-channel-conf 00_189 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXOSCALRESET_TIMEOUT[0] origin:064-gtp-channel-conf 01_189 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXOSCALRESET_TIMEOUT[1] origin:064-gtp-channel-conf 00_190 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXOSCALRESET_TIMEOUT[2] origin:064-gtp-channel-conf 01_190 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXOSCALRESET_TIMEOUT[3] origin:064-gtp-channel-conf 00_191 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXOSCALRESET_TIMEOUT[4] origin:064-gtp-channel-conf 01_191 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXOUT_DIV[0] origin:064-gtp-channel-conf 02_384 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXOUT_DIV[1] origin:064-gtp-channel-conf 03_384 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXPCSRESET_TIME[0] origin:064-gtp-channel-conf 01_115 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXPCSRESET_TIME[1] origin:064-gtp-channel-conf 00_116 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXPCSRESET_TIME[2] origin:064-gtp-channel-conf 01_116 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXPCSRESET_TIME[3] origin:064-gtp-channel-conf 00_117 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXPCSRESET_TIME[4] origin:064-gtp-channel-conf 01_117 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[0] origin:064-gtp-channel-conf 02_584 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[1] origin:064-gtp-channel-conf 03_584 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[2] origin:064-gtp-channel-conf 02_585 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[3] origin:064-gtp-channel-conf 03_585 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[4] origin:064-gtp-channel-conf 02_586 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[5] origin:064-gtp-channel-conf 03_586 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[6] origin:064-gtp-channel-conf 02_587 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[7] origin:064-gtp-channel-conf 03_587 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[8] origin:064-gtp-channel-conf 02_588 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[9] origin:064-gtp-channel-conf 03_588 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[10] origin:064-gtp-channel-conf 02_589 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[11] origin:064-gtp-channel-conf 03_589 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[12] origin:064-gtp-channel-conf 02_590 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[13] origin:064-gtp-channel-conf 03_590 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[14] origin:064-gtp-channel-conf 02_591 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[15] origin:064-gtp-channel-conf 03_591 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[16] origin:064-gtp-channel-conf 02_592 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[17] origin:064-gtp-channel-conf 03_592 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[18] origin:064-gtp-channel-conf 02_593 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[19] origin:064-gtp-channel-conf 03_593 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[20] origin:064-gtp-channel-conf 02_594 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[21] origin:064-gtp-channel-conf 03_594 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[22] origin:064-gtp-channel-conf 02_595 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[23] origin:064-gtp-channel-conf 03_595 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXPH_MONITOR_SEL[0] origin:064-gtp-channel-conf 00_700 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXPH_MONITOR_SEL[1] origin:064-gtp-channel-conf 01_700 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXPH_MONITOR_SEL[2] origin:064-gtp-channel-conf 00_701 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXPH_MONITOR_SEL[3] origin:064-gtp-channel-conf 01_701 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXPH_MONITOR_SEL[4] origin:064-gtp-channel-conf 00_702 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[0] origin:064-gtp-channel-conf 02_600 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[1] origin:064-gtp-channel-conf 03_600 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[2] origin:064-gtp-channel-conf 02_601 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[3] origin:064-gtp-channel-conf 03_601 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[4] origin:064-gtp-channel-conf 02_602 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[5] origin:064-gtp-channel-conf 03_602 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[6] origin:064-gtp-channel-conf 02_603 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[7] origin:064-gtp-channel-conf 03_603 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[8] origin:064-gtp-channel-conf 02_604 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[9] origin:064-gtp-channel-conf 03_604 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[10] origin:064-gtp-channel-conf 02_605 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[11] origin:064-gtp-channel-conf 03_605 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[12] origin:064-gtp-channel-conf 02_606 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[13] origin:064-gtp-channel-conf 03_606 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[14] origin:064-gtp-channel-conf 02_607 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[15] origin:064-gtp-channel-conf 03_607 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[16] origin:064-gtp-channel-conf 02_608 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[17] origin:064-gtp-channel-conf 03_608 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[18] origin:064-gtp-channel-conf 02_609 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[19] origin:064-gtp-channel-conf 03_609 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[20] origin:064-gtp-channel-conf 02_610 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[21] origin:064-gtp-channel-conf 03_610 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[22] origin:064-gtp-channel-conf 02_611 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[23] origin:064-gtp-channel-conf 03_611 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXPI_CFG0[0] origin:064-gtp-channel-conf 03_430 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXPI_CFG0[1] origin:064-gtp-channel-conf 02_431 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXPI_CFG0[2] origin:064-gtp-channel-conf 03_431 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXPI_CFG1[0] origin:064-gtp-channel-conf 02_442 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXPI_CFG2[0] origin:064-gtp-channel-conf 03_441 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXPMARESET_TIME[0] origin:064-gtp-channel-conf 00_104 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXPMARESET_TIME[1] origin:064-gtp-channel-conf 01_104 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXPMARESET_TIME[2] origin:064-gtp-channel-conf 00_105 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXPMARESET_TIME[3] origin:064-gtp-channel-conf 01_105 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXPMARESET_TIME[4] origin:064-gtp-channel-conf 00_106 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXPRBS_ERR_LOOPBACK[0] origin:064-gtp-channel-conf 00_136 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXSLIDE_AUTO_WAIT[0] origin:064-gtp-channel-conf 00_520 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXSLIDE_AUTO_WAIT[1] origin:064-gtp-channel-conf 01_520 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXSLIDE_AUTO_WAIT[2] origin:064-gtp-channel-conf 00_521 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXSLIDE_AUTO_WAIT[3] origin:064-gtp-channel-conf 01_521 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXSLIDE_MODE.AUTO origin:064-gtp-channel-conf !01_519 00_519 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXSLIDE_MODE.PCS origin:064-gtp-channel-conf !00_519 01_519 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXSLIDE_MODE.PMA origin:064-gtp-channel-conf 00_519 01_519 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXSYNC_MULTILANE[0] origin:064-gtp-channel-conf 00_133 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXSYNC_OVRD[0] origin:064-gtp-channel-conf 01_135 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.RXSYNC_SKIP_DA[0] origin:064-gtp-channel-conf 01_134 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.SAS_MAX_COM[0] origin:064-gtp-channel-conf 00_171 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.SAS_MAX_COM[1] origin:064-gtp-channel-conf 01_171 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.SAS_MAX_COM[2] origin:064-gtp-channel-conf 00_172 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.SAS_MAX_COM[3] origin:064-gtp-channel-conf 01_172 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.SAS_MAX_COM[4] origin:064-gtp-channel-conf 00_173 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.SAS_MAX_COM[5] origin:064-gtp-channel-conf 01_173 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.SAS_MAX_COM[6] origin:064-gtp-channel-conf 00_174 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.SAS_MIN_COM[0] origin:064-gtp-channel-conf 01_156 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.SAS_MIN_COM[1] origin:064-gtp-channel-conf 00_157 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.SAS_MIN_COM[2] origin:064-gtp-channel-conf 01_157 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.SAS_MIN_COM[3] origin:064-gtp-channel-conf 00_158 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.SAS_MIN_COM[4] origin:064-gtp-channel-conf 01_158 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.SAS_MIN_COM[5] origin:064-gtp-channel-conf 00_159 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.SATA_BURST_SEQ_LEN[0] origin:064-gtp-channel-conf 00_150 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.SATA_BURST_SEQ_LEN[1] origin:064-gtp-channel-conf 01_150 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.SATA_BURST_SEQ_LEN[2] origin:064-gtp-channel-conf 00_151 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.SATA_BURST_SEQ_LEN[3] origin:064-gtp-channel-conf 01_151 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.SATA_BURST_VAL[0] origin:064-gtp-channel-conf 01_147 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.SATA_BURST_VAL[1] origin:064-gtp-channel-conf 00_148 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.SATA_BURST_VAL[2] origin:064-gtp-channel-conf 01_148 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.SATA_EIDLE_VAL[0] origin:064-gtp-channel-conf 00_152 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.SATA_EIDLE_VAL[1] origin:064-gtp-channel-conf 01_152 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.SATA_EIDLE_VAL[2] origin:064-gtp-channel-conf 00_153 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.SATA_MAX_BURST[0] origin:064-gtp-channel-conf 00_168 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.SATA_MAX_BURST[1] origin:064-gtp-channel-conf 01_168 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.SATA_MAX_BURST[2] origin:064-gtp-channel-conf 00_169 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.SATA_MAX_BURST[3] origin:064-gtp-channel-conf 01_169 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.SATA_MAX_BURST[4] origin:064-gtp-channel-conf 00_170 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.SATA_MAX_BURST[5] origin:064-gtp-channel-conf 01_170 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.SATA_MAX_INIT[0] origin:064-gtp-channel-conf 00_176 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.SATA_MAX_INIT[1] origin:064-gtp-channel-conf 01_176 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.SATA_MAX_INIT[2] origin:064-gtp-channel-conf 00_177 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.SATA_MAX_INIT[3] origin:064-gtp-channel-conf 01_177 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.SATA_MAX_INIT[4] origin:064-gtp-channel-conf 00_178 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.SATA_MAX_INIT[5] origin:064-gtp-channel-conf 01_178 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.SATA_MAX_WAKE[0] origin:064-gtp-channel-conf 00_179 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.SATA_MAX_WAKE[1] origin:064-gtp-channel-conf 01_179 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.SATA_MAX_WAKE[2] origin:064-gtp-channel-conf 00_180 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.SATA_MAX_WAKE[3] origin:064-gtp-channel-conf 01_180 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.SATA_MAX_WAKE[4] origin:064-gtp-channel-conf 00_181 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.SATA_MAX_WAKE[5] origin:064-gtp-channel-conf 01_181 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.SATA_MIN_BURST[0] origin:064-gtp-channel-conf 01_153 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.SATA_MIN_BURST[1] origin:064-gtp-channel-conf 00_154 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.SATA_MIN_BURST[2] origin:064-gtp-channel-conf 01_154 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.SATA_MIN_BURST[3] origin:064-gtp-channel-conf 00_155 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.SATA_MIN_BURST[4] origin:064-gtp-channel-conf 01_155 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.SATA_MIN_BURST[5] origin:064-gtp-channel-conf 00_156 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.SATA_MIN_INIT[0] origin:064-gtp-channel-conf 00_160 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.SATA_MIN_INIT[1] origin:064-gtp-channel-conf 01_160 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.SATA_MIN_INIT[2] origin:064-gtp-channel-conf 00_161 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.SATA_MIN_INIT[3] origin:064-gtp-channel-conf 01_161 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.SATA_MIN_INIT[4] origin:064-gtp-channel-conf 00_162 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.SATA_MIN_INIT[5] origin:064-gtp-channel-conf 01_162 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.SATA_MIN_WAKE[0] origin:064-gtp-channel-conf 00_163 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.SATA_MIN_WAKE[1] origin:064-gtp-channel-conf 01_163 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.SATA_MIN_WAKE[2] origin:064-gtp-channel-conf 00_164 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.SATA_MIN_WAKE[3] origin:064-gtp-channel-conf 01_164 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.SATA_MIN_WAKE[4] origin:064-gtp-channel-conf 00_165 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.SATA_MIN_WAKE[5] origin:064-gtp-channel-conf 01_165 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.SATA_PLL_CFG.VCO_1500MHZ origin:064-gtp-channel-conf 02_55 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.SATA_PLL_CFG.VCO_750MHZ origin:064-gtp-channel-conf 03_55 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.SHOW_REALIGN_COMMA origin:064-gtp-channel-conf 01_522 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TERM_RCAL_CFG[0] origin:064-gtp-channel-conf 02_136 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TERM_RCAL_CFG[1] origin:064-gtp-channel-conf 03_136 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TERM_RCAL_CFG[2] origin:064-gtp-channel-conf 02_137 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TERM_RCAL_CFG[3] origin:064-gtp-channel-conf 03_137 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TERM_RCAL_CFG[4] origin:064-gtp-channel-conf 02_138 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TERM_RCAL_CFG[5] origin:064-gtp-channel-conf 03_138 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TERM_RCAL_CFG[6] origin:064-gtp-channel-conf 02_139 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TERM_RCAL_CFG[7] origin:064-gtp-channel-conf 03_139 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TERM_RCAL_CFG[8] origin:064-gtp-channel-conf 02_140 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TERM_RCAL_CFG[9] origin:064-gtp-channel-conf 03_140 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TERM_RCAL_CFG[10] origin:064-gtp-channel-conf 02_141 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TERM_RCAL_CFG[11] origin:064-gtp-channel-conf 03_141 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TERM_RCAL_CFG[12] origin:064-gtp-channel-conf 02_142 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TERM_RCAL_CFG[13] origin:064-gtp-channel-conf 03_142 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TERM_RCAL_CFG[14] origin:064-gtp-channel-conf 02_143 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TERM_RCAL_OVRD[0] origin:064-gtp-channel-conf 03_150 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TERM_RCAL_OVRD[1] origin:064-gtp-channel-conf 02_151 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TERM_RCAL_OVRD[2] origin:064-gtp-channel-conf 03_151 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TRANS_TIME_RATE[0] origin:064-gtp-channel-conf 00_192 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TRANS_TIME_RATE[1] origin:064-gtp-channel-conf 01_192 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TRANS_TIME_RATE[2] origin:064-gtp-channel-conf 00_193 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TRANS_TIME_RATE[3] origin:064-gtp-channel-conf 01_193 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TRANS_TIME_RATE[4] origin:064-gtp-channel-conf 00_194 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TRANS_TIME_RATE[5] origin:064-gtp-channel-conf 01_194 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TRANS_TIME_RATE[6] origin:064-gtp-channel-conf 00_195 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TRANS_TIME_RATE[7] origin:064-gtp-channel-conf 01_195 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TST_RSV[0] origin:064-gtp-channel-conf 02_504 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TST_RSV[1] origin:064-gtp-channel-conf 03_504 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TST_RSV[2] origin:064-gtp-channel-conf 02_505 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TST_RSV[3] origin:064-gtp-channel-conf 03_505 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TST_RSV[4] origin:064-gtp-channel-conf 02_506 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TST_RSV[5] origin:064-gtp-channel-conf 03_506 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TST_RSV[6] origin:064-gtp-channel-conf 02_507 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TST_RSV[7] origin:064-gtp-channel-conf 03_507 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TST_RSV[8] origin:064-gtp-channel-conf 02_508 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TST_RSV[9] origin:064-gtp-channel-conf 03_508 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TST_RSV[10] origin:064-gtp-channel-conf 02_509 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TST_RSV[11] origin:064-gtp-channel-conf 03_509 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TST_RSV[12] origin:064-gtp-channel-conf 02_510 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TST_RSV[13] origin:064-gtp-channel-conf 03_510 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TST_RSV[14] origin:064-gtp-channel-conf 02_511 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TST_RSV[15] origin:064-gtp-channel-conf 03_511 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TST_RSV[16] origin:064-gtp-channel-conf 02_512 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TST_RSV[17] origin:064-gtp-channel-conf 03_512 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TST_RSV[18] origin:064-gtp-channel-conf 02_513 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TST_RSV[19] origin:064-gtp-channel-conf 03_513 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TST_RSV[20] origin:064-gtp-channel-conf 02_514 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TST_RSV[21] origin:064-gtp-channel-conf 03_514 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TST_RSV[22] origin:064-gtp-channel-conf 02_515 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TST_RSV[23] origin:064-gtp-channel-conf 03_515 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TST_RSV[24] origin:064-gtp-channel-conf 02_516 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TST_RSV[25] origin:064-gtp-channel-conf 03_516 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TST_RSV[26] origin:064-gtp-channel-conf 02_517 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TST_RSV[27] origin:064-gtp-channel-conf 03_517 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TST_RSV[28] origin:064-gtp-channel-conf 02_518 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TST_RSV[29] origin:064-gtp-channel-conf 03_518 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TST_RSV[30] origin:064-gtp-channel-conf 02_519 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TST_RSV[31] origin:064-gtp-channel-conf 03_519 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_CLKMUX_EN[0] origin:064-gtp-channel-conf 03_128 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_DATA_WIDTH[0] origin:064-gtp-channel-conf 02_152 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_DATA_WIDTH[1] origin:064-gtp-channel-conf 03_152 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_DATA_WIDTH[2] origin:064-gtp-channel-conf 02_153 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_DRIVE_MODE.PIPE origin:064-gtp-channel-conf 00_200 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_EIDLE_ASSERT_DELAY[0] origin:064-gtp-channel-conf 00_203 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_EIDLE_ASSERT_DELAY[1] origin:064-gtp-channel-conf 01_203 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_EIDLE_ASSERT_DELAY[2] origin:064-gtp-channel-conf 00_204 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_EIDLE_DEASSERT_DELAY[0] origin:064-gtp-channel-conf 01_204 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_EIDLE_DEASSERT_DELAY[1] origin:064-gtp-channel-conf 00_205 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_EIDLE_DEASSERT_DELAY[2] origin:064-gtp-channel-conf 01_205 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_LOOPBACK_DRIVE_HIZ origin:064-gtp-channel-conf 01_202 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_MAINCURSOR_SEL[0] origin:064-gtp-channel-conf 03_289 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_0[0] origin:064-gtp-channel-conf 02_232 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_0[1] origin:064-gtp-channel-conf 03_232 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_0[2] origin:064-gtp-channel-conf 02_233 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_0[3] origin:064-gtp-channel-conf 03_233 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_0[4] origin:064-gtp-channel-conf 02_234 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_0[5] origin:064-gtp-channel-conf 03_234 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_0[6] origin:064-gtp-channel-conf 02_235 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_1[0] origin:064-gtp-channel-conf 02_236 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_1[1] origin:064-gtp-channel-conf 03_236 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_1[2] origin:064-gtp-channel-conf 02_237 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_1[3] origin:064-gtp-channel-conf 03_237 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_1[4] origin:064-gtp-channel-conf 02_238 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_1[5] origin:064-gtp-channel-conf 03_238 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_1[6] origin:064-gtp-channel-conf 02_239 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_2[0] origin:064-gtp-channel-conf 02_240 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_2[1] origin:064-gtp-channel-conf 03_240 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_2[2] origin:064-gtp-channel-conf 02_241 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_2[3] origin:064-gtp-channel-conf 03_241 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_2[4] origin:064-gtp-channel-conf 02_242 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_2[5] origin:064-gtp-channel-conf 03_242 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_2[6] origin:064-gtp-channel-conf 02_243 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_3[0] origin:064-gtp-channel-conf 02_244 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_3[1] origin:064-gtp-channel-conf 03_244 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_3[2] origin:064-gtp-channel-conf 02_245 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_3[3] origin:064-gtp-channel-conf 03_245 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_3[4] origin:064-gtp-channel-conf 02_246 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_3[5] origin:064-gtp-channel-conf 03_246 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_3[6] origin:064-gtp-channel-conf 02_247 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_4[0] origin:064-gtp-channel-conf 02_248 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_4[1] origin:064-gtp-channel-conf 03_248 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_4[2] origin:064-gtp-channel-conf 02_249 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_4[3] origin:064-gtp-channel-conf 03_249 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_4[4] origin:064-gtp-channel-conf 02_250 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_4[5] origin:064-gtp-channel-conf 03_250 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_4[6] origin:064-gtp-channel-conf 02_251 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_0[0] origin:064-gtp-channel-conf 02_252 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_0[1] origin:064-gtp-channel-conf 03_252 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_0[2] origin:064-gtp-channel-conf 02_253 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_0[3] origin:064-gtp-channel-conf 03_253 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_0[4] origin:064-gtp-channel-conf 02_254 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_0[5] origin:064-gtp-channel-conf 03_254 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_0[6] origin:064-gtp-channel-conf 02_255 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_1[0] origin:064-gtp-channel-conf 02_256 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_1[1] origin:064-gtp-channel-conf 03_256 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_1[2] origin:064-gtp-channel-conf 02_257 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_1[3] origin:064-gtp-channel-conf 03_257 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_1[4] origin:064-gtp-channel-conf 02_258 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_1[5] origin:064-gtp-channel-conf 03_258 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_1[6] origin:064-gtp-channel-conf 02_259 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_2[0] origin:064-gtp-channel-conf 02_260 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_2[1] origin:064-gtp-channel-conf 03_260 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_2[2] origin:064-gtp-channel-conf 02_261 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_2[3] origin:064-gtp-channel-conf 03_261 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_2[4] origin:064-gtp-channel-conf 02_262 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_2[5] origin:064-gtp-channel-conf 03_262 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_2[6] origin:064-gtp-channel-conf 02_263 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_3[0] origin:064-gtp-channel-conf 02_264 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_3[1] origin:064-gtp-channel-conf 03_264 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_3[2] origin:064-gtp-channel-conf 02_265 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_3[3] origin:064-gtp-channel-conf 03_265 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_3[4] origin:064-gtp-channel-conf 02_266 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_3[5] origin:064-gtp-channel-conf 03_266 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_3[6] origin:064-gtp-channel-conf 02_267 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_4[0] origin:064-gtp-channel-conf 02_268 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_4[1] origin:064-gtp-channel-conf 03_268 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_4[2] origin:064-gtp-channel-conf 02_269 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_4[3] origin:064-gtp-channel-conf 03_269 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_4[4] origin:064-gtp-channel-conf 02_270 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_4[5] origin:064-gtp-channel-conf 03_270 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_4[6] origin:064-gtp-channel-conf 02_271 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_PREDRIVER_MODE[0] origin:064-gtp-channel-conf 00_206 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_RXDETECT_CFG[0] origin:064-gtp-channel-conf 02_296 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_RXDETECT_CFG[1] origin:064-gtp-channel-conf 03_296 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_RXDETECT_CFG[2] origin:064-gtp-channel-conf 02_297 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_RXDETECT_CFG[3] origin:064-gtp-channel-conf 03_297 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_RXDETECT_CFG[4] origin:064-gtp-channel-conf 02_298 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_RXDETECT_CFG[5] origin:064-gtp-channel-conf 03_298 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_RXDETECT_CFG[6] origin:064-gtp-channel-conf 02_299 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_RXDETECT_CFG[7] origin:064-gtp-channel-conf 03_299 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_RXDETECT_CFG[8] origin:064-gtp-channel-conf 02_300 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_RXDETECT_CFG[9] origin:064-gtp-channel-conf 03_300 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_RXDETECT_CFG[10] origin:064-gtp-channel-conf 02_301 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_RXDETECT_CFG[11] origin:064-gtp-channel-conf 03_301 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_RXDETECT_CFG[12] origin:064-gtp-channel-conf 02_302 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_RXDETECT_CFG[13] origin:064-gtp-channel-conf 03_302 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_RXDETECT_REF[0] origin:064-gtp-channel-conf 02_292 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_RXDETECT_REF[1] origin:064-gtp-channel-conf 03_292 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_RXDETECT_REF[2] origin:064-gtp-channel-conf 02_293 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_XCLK_SEL.TXUSR origin:064-gtp-channel-conf 03_11 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_CLK25_DIV[0] origin:064-gtp-channel-conf 02_144 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_CLK25_DIV[1] origin:064-gtp-channel-conf 03_144 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_CLK25_DIV[2] origin:064-gtp-channel-conf 02_145 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_CLK25_DIV[3] origin:064-gtp-channel-conf 03_145 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_CLK25_DIV[4] origin:064-gtp-channel-conf 02_146 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_DEEMPH0[0] origin:064-gtp-channel-conf 02_272 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_DEEMPH0[1] origin:064-gtp-channel-conf 03_272 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_DEEMPH0[2] origin:064-gtp-channel-conf 02_273 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_DEEMPH0[3] origin:064-gtp-channel-conf 03_273 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_DEEMPH0[4] origin:064-gtp-channel-conf 02_274 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_DEEMPH0[5] origin:064-gtp-channel-conf 03_274 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_DEEMPH1[0] origin:064-gtp-channel-conf 02_276 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_DEEMPH1[1] origin:064-gtp-channel-conf 03_276 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_DEEMPH1[2] origin:064-gtp-channel-conf 02_277 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_DEEMPH1[3] origin:064-gtp-channel-conf 03_277 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_DEEMPH1[4] origin:064-gtp-channel-conf 02_278 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TX_DEEMPH1[5] origin:064-gtp-channel-conf 03_278 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXBUF_EN origin:064-gtp-channel-conf 00_231 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXBUF_RESET_ON_RATE_CHANGE origin:064-gtp-channel-conf 01_231 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXDLY_CFG[0] origin:064-gtp-channel-conf 02_80 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXDLY_CFG[1] origin:064-gtp-channel-conf 03_80 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXDLY_CFG[2] origin:064-gtp-channel-conf 02_81 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXDLY_CFG[3] origin:064-gtp-channel-conf 03_81 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXDLY_CFG[4] origin:064-gtp-channel-conf 02_82 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXDLY_CFG[5] origin:064-gtp-channel-conf 03_82 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXDLY_CFG[6] origin:064-gtp-channel-conf 02_83 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXDLY_CFG[7] origin:064-gtp-channel-conf 03_83 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXDLY_CFG[8] origin:064-gtp-channel-conf 02_84 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXDLY_CFG[9] origin:064-gtp-channel-conf 03_84 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXDLY_CFG[10] origin:064-gtp-channel-conf 02_85 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXDLY_CFG[11] origin:064-gtp-channel-conf 03_85 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXDLY_CFG[12] origin:064-gtp-channel-conf 02_86 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXDLY_CFG[13] origin:064-gtp-channel-conf 03_86 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXDLY_CFG[14] origin:064-gtp-channel-conf 02_87 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXDLY_CFG[15] origin:064-gtp-channel-conf 03_87 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXDLY_LCFG[0] origin:064-gtp-channel-conf 02_568 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXDLY_LCFG[1] origin:064-gtp-channel-conf 03_568 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXDLY_LCFG[2] origin:064-gtp-channel-conf 02_569 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXDLY_LCFG[3] origin:064-gtp-channel-conf 03_569 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXDLY_LCFG[4] origin:064-gtp-channel-conf 02_570 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXDLY_LCFG[5] origin:064-gtp-channel-conf 03_570 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXDLY_LCFG[6] origin:064-gtp-channel-conf 02_571 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXDLY_LCFG[7] origin:064-gtp-channel-conf 03_571 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXDLY_LCFG[8] origin:064-gtp-channel-conf 02_572 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXDLY_TAP_CFG[0] origin:064-gtp-channel-conf 02_88 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXDLY_TAP_CFG[1] origin:064-gtp-channel-conf 03_88 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXDLY_TAP_CFG[2] origin:064-gtp-channel-conf 02_89 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXDLY_TAP_CFG[3] origin:064-gtp-channel-conf 03_89 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXDLY_TAP_CFG[4] origin:064-gtp-channel-conf 02_90 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXDLY_TAP_CFG[5] origin:064-gtp-channel-conf 03_90 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXDLY_TAP_CFG[6] origin:064-gtp-channel-conf 02_91 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXDLY_TAP_CFG[7] origin:064-gtp-channel-conf 03_91 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXDLY_TAP_CFG[8] origin:064-gtp-channel-conf 02_92 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXDLY_TAP_CFG[9] origin:064-gtp-channel-conf 03_92 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXDLY_TAP_CFG[10] origin:064-gtp-channel-conf 02_93 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXDLY_TAP_CFG[11] origin:064-gtp-channel-conf 03_93 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXDLY_TAP_CFG[12] origin:064-gtp-channel-conf 02_94 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXDLY_TAP_CFG[13] origin:064-gtp-channel-conf 03_94 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXDLY_TAP_CFG[14] origin:064-gtp-channel-conf 02_95 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXDLY_TAP_CFG[15] origin:064-gtp-channel-conf 03_95 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXGEARBOX_EN origin:064-gtp-channel-conf 01_226 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXOOB_CFG[0] origin:064-gtp-channel-conf 03_20 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXOUT_DIV[0] origin:064-gtp-channel-conf 02_386 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXOUT_DIV[1] origin:064-gtp-channel-conf 03_386 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPCSRESET_TIME[0] origin:064-gtp-channel-conf 01_130 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPCSRESET_TIME[1] origin:064-gtp-channel-conf 00_131 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPCSRESET_TIME[2] origin:064-gtp-channel-conf 01_131 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPCSRESET_TIME[3] origin:064-gtp-channel-conf 00_132 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPCSRESET_TIME[4] origin:064-gtp-channel-conf 01_132 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPH_CFG[0] origin:064-gtp-channel-conf 02_96 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPH_CFG[1] origin:064-gtp-channel-conf 03_96 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPH_CFG[2] origin:064-gtp-channel-conf 02_97 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPH_CFG[3] origin:064-gtp-channel-conf 03_97 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPH_CFG[4] origin:064-gtp-channel-conf 02_98 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPH_CFG[5] origin:064-gtp-channel-conf 03_98 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPH_CFG[6] origin:064-gtp-channel-conf 02_99 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPH_CFG[7] origin:064-gtp-channel-conf 03_99 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPH_CFG[8] origin:064-gtp-channel-conf 02_100 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPH_CFG[9] origin:064-gtp-channel-conf 03_100 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPH_CFG[10] origin:064-gtp-channel-conf 02_101 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPH_CFG[11] origin:064-gtp-channel-conf 03_101 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPH_CFG[12] origin:064-gtp-channel-conf 02_102 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPH_CFG[13] origin:064-gtp-channel-conf 03_102 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPH_CFG[14] origin:064-gtp-channel-conf 02_103 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPH_CFG[15] origin:064-gtp-channel-conf 03_103 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPH_MONITOR_SEL[0] origin:064-gtp-channel-conf 02_108 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPH_MONITOR_SEL[1] origin:064-gtp-channel-conf 03_108 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPH_MONITOR_SEL[2] origin:064-gtp-channel-conf 02_109 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPH_MONITOR_SEL[3] origin:064-gtp-channel-conf 03_109 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPH_MONITOR_SEL[4] origin:064-gtp-channel-conf 02_110 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[0] origin:064-gtp-channel-conf 02_64 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[1] origin:064-gtp-channel-conf 03_64 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[2] origin:064-gtp-channel-conf 02_65 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[3] origin:064-gtp-channel-conf 03_65 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[4] origin:064-gtp-channel-conf 02_66 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[5] origin:064-gtp-channel-conf 03_66 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[6] origin:064-gtp-channel-conf 02_67 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[7] origin:064-gtp-channel-conf 03_67 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[8] origin:064-gtp-channel-conf 02_68 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[9] origin:064-gtp-channel-conf 03_68 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[10] origin:064-gtp-channel-conf 02_69 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[11] origin:064-gtp-channel-conf 03_69 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[12] origin:064-gtp-channel-conf 02_70 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[13] origin:064-gtp-channel-conf 03_70 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[14] origin:064-gtp-channel-conf 02_71 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[15] origin:064-gtp-channel-conf 03_71 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[16] origin:064-gtp-channel-conf 02_72 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[17] origin:064-gtp-channel-conf 03_72 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[18] origin:064-gtp-channel-conf 02_73 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[19] origin:064-gtp-channel-conf 03_73 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[20] origin:064-gtp-channel-conf 02_74 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[21] origin:064-gtp-channel-conf 03_74 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[22] origin:064-gtp-channel-conf 02_75 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[23] origin:064-gtp-channel-conf 03_75 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPI_GREY_SEL[0] origin:064-gtp-channel-conf 03_498 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPI_INVSTROBE_SEL[0] origin:064-gtp-channel-conf 02_498 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPI_PPM_CFG[0] origin:064-gtp-channel-conf 02_488 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPI_PPM_CFG[1] origin:064-gtp-channel-conf 03_488 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPI_PPM_CFG[2] origin:064-gtp-channel-conf 02_489 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPI_PPM_CFG[3] origin:064-gtp-channel-conf 03_489 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPI_PPM_CFG[4] origin:064-gtp-channel-conf 02_490 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPI_PPM_CFG[5] origin:064-gtp-channel-conf 03_490 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPI_PPM_CFG[6] origin:064-gtp-channel-conf 02_491 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPI_PPM_CFG[7] origin:064-gtp-channel-conf 03_491 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPI_PPMCLK_SEL.TXUSRCLK2 origin:064-gtp-channel-conf 03_497 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPI_SYNFREQ_PPM[0] origin:064-gtp-channel-conf 02_496 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPI_SYNFREQ_PPM[1] origin:064-gtp-channel-conf 03_496 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPI_SYNFREQ_PPM[2] origin:064-gtp-channel-conf 02_497 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPI_CFG0[0] origin:064-gtp-channel-conf 02_40 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPI_CFG0[1] origin:064-gtp-channel-conf 03_40 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPI_CFG1[0] origin:064-gtp-channel-conf 02_41 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPI_CFG1[1] origin:064-gtp-channel-conf 03_41 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPI_CFG2[0] origin:064-gtp-channel-conf 02_42 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPI_CFG2[1] origin:064-gtp-channel-conf 03_42 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPI_CFG3[0] origin:064-gtp-channel-conf 02_43 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPI_CFG4[0] origin:064-gtp-channel-conf 03_43 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPI_CFG5[0] origin:064-gtp-channel-conf 02_44 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPI_CFG5[1] origin:064-gtp-channel-conf 03_44 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPI_CFG5[2] origin:064-gtp-channel-conf 02_45 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPMARESET_TIME[0] origin:064-gtp-channel-conf 00_128 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPMARESET_TIME[1] origin:064-gtp-channel-conf 01_128 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPMARESET_TIME[2] origin:064-gtp-channel-conf 00_129 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPMARESET_TIME[3] origin:064-gtp-channel-conf 01_129 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXPMARESET_TIME[4] origin:064-gtp-channel-conf 00_130 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXSYNC_MULTILANE[0] origin:064-gtp-channel-conf 01_133 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXSYNC_OVRD[0] origin:064-gtp-channel-conf 00_135 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.TXSYNC_SKIP_DA[0] origin:064-gtp-channel-conf 00_134 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.UCODEER_CLR[0] origin:064-gtp-channel-conf 01_00 +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL.USE_PCS_CLK_PHASE_SEL[0] origin:064-gtp-channel-conf 02_463 diff --git a/artix7/segbits_gtp_channel_2_mid_right.db b/artix7/segbits_gtp_channel_2_mid_right.db index b5a680b..d944988 100644 --- a/artix7/segbits_gtp_channel_2_mid_right.db +++ b/artix7/segbits_gtp_channel_2_mid_right.db @@ -1,1627 +1,1627 @@ -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ACJTAG_DEBUG_MODE[0] 00_07 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ACJTAG_MODE[0] 01_06 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ACJTAG_RESET[0] 01_07 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ADAPT_CFG0[0] 02_464 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ADAPT_CFG0[1] 03_464 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ADAPT_CFG0[2] 02_465 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ADAPT_CFG0[3] 03_465 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ADAPT_CFG0[4] 02_466 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ADAPT_CFG0[5] 03_466 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ADAPT_CFG0[6] 02_467 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ADAPT_CFG0[7] 03_467 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ADAPT_CFG0[8] 02_468 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ADAPT_CFG0[9] 03_468 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ADAPT_CFG0[10] 02_469 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ADAPT_CFG0[11] 03_469 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ADAPT_CFG0[12] 02_470 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ADAPT_CFG0[13] 03_470 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ADAPT_CFG0[14] 02_471 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ADAPT_CFG0[15] 03_471 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ADAPT_CFG0[16] 02_472 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ADAPT_CFG0[17] 03_472 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ADAPT_CFG0[18] 02_473 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ADAPT_CFG0[19] 03_473 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ALIGN_COMMA_DOUBLE 00_522 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ALIGN_COMMA_ENABLE[0] 00_496 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ALIGN_COMMA_ENABLE[1] 01_496 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ALIGN_COMMA_ENABLE[2] 00_497 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ALIGN_COMMA_ENABLE[3] 01_497 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ALIGN_COMMA_ENABLE[4] 00_498 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ALIGN_COMMA_ENABLE[5] 01_498 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ALIGN_COMMA_ENABLE[6] 00_499 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ALIGN_COMMA_ENABLE[7] 01_499 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ALIGN_COMMA_ENABLE[8] 00_500 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ALIGN_COMMA_ENABLE[9] 01_500 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ALIGN_COMMA_WORD[0] 01_526 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ALIGN_COMMA_WORD[1] 00_527 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ALIGN_MCOMMA_DET 00_523 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ALIGN_MCOMMA_VALUE[0] 00_504 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ALIGN_MCOMMA_VALUE[1] 01_504 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ALIGN_MCOMMA_VALUE[2] 00_505 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ALIGN_MCOMMA_VALUE[3] 01_505 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ALIGN_MCOMMA_VALUE[4] 00_506 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ALIGN_MCOMMA_VALUE[5] 01_506 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ALIGN_MCOMMA_VALUE[6] 00_507 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ALIGN_MCOMMA_VALUE[7] 01_507 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ALIGN_MCOMMA_VALUE[8] 00_508 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ALIGN_MCOMMA_VALUE[9] 01_508 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ALIGN_PCOMMA_DET 01_523 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ALIGN_PCOMMA_VALUE[0] 00_512 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ALIGN_PCOMMA_VALUE[1] 01_512 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ALIGN_PCOMMA_VALUE[2] 00_513 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ALIGN_PCOMMA_VALUE[3] 01_513 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ALIGN_PCOMMA_VALUE[4] 00_514 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ALIGN_PCOMMA_VALUE[5] 01_514 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ALIGN_PCOMMA_VALUE[6] 00_515 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ALIGN_PCOMMA_VALUE[7] 01_515 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ALIGN_PCOMMA_VALUE[8] 00_516 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ALIGN_PCOMMA_VALUE[9] 01_516 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CBCC_DATA_SOURCE_SEL.DECODED 01_661 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CFOK_CFG[0] 02_392 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CFOK_CFG[1] 03_392 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CFOK_CFG[2] 02_393 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CFOK_CFG[3] 03_393 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CFOK_CFG[4] 02_394 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CFOK_CFG[5] 03_394 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CFOK_CFG[6] 02_395 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CFOK_CFG[7] 03_395 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CFOK_CFG[8] 02_396 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CFOK_CFG[9] 03_396 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CFOK_CFG[10] 02_397 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CFOK_CFG[11] 03_397 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CFOK_CFG[12] 02_398 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CFOK_CFG[13] 03_398 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CFOK_CFG[14] 02_399 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CFOK_CFG[15] 03_399 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CFOK_CFG[16] 02_400 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CFOK_CFG[17] 03_400 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CFOK_CFG[18] 02_401 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CFOK_CFG[19] 03_401 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CFOK_CFG[20] 02_402 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CFOK_CFG[21] 03_402 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CFOK_CFG[22] 02_403 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CFOK_CFG[23] 03_403 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CFOK_CFG[24] 02_404 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CFOK_CFG[25] 03_404 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CFOK_CFG[26] 02_405 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CFOK_CFG[27] 03_405 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CFOK_CFG[28] 02_406 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CFOK_CFG[29] 03_406 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CFOK_CFG[30] 02_407 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CFOK_CFG[31] 03_407 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CFOK_CFG[32] 02_408 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CFOK_CFG[33] 03_408 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CFOK_CFG[34] 02_409 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CFOK_CFG[35] 03_409 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CFOK_CFG[36] 02_410 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CFOK_CFG[37] 03_410 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CFOK_CFG[38] 02_411 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CFOK_CFG[39] 03_411 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CFOK_CFG[40] 02_412 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CFOK_CFG[41] 03_412 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CFOK_CFG[42] 02_413 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CFOK_CFG2[0] 02_459 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CFOK_CFG2[1] 03_459 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CFOK_CFG2[2] 02_460 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CFOK_CFG2[3] 03_460 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CFOK_CFG2[4] 02_461 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CFOK_CFG2[5] 03_461 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CFOK_CFG2[6] 02_462 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CFOK_CFG3[0] 02_416 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CFOK_CFG3[1] 03_416 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CFOK_CFG3[2] 02_417 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CFOK_CFG3[3] 03_417 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CFOK_CFG3[4] 02_418 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CFOK_CFG3[5] 03_418 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CFOK_CFG3[6] 02_419 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CFOK_CFG4[0] 03_438 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CFOK_CFG5[0] 02_429 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CFOK_CFG5[1] 03_429 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CFOK_CFG6[0] 03_436 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CFOK_CFG6[1] 02_437 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CFOK_CFG6[2] 03_437 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CFOK_CFG6[3] 02_438 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_KEEP_ALIGN 01_631 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_MAX_SKEW[0] 00_670 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_MAX_SKEW[1] 01_670 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_MAX_SKEW[2] 00_671 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_MAX_SKEW[3] 01_671 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_1[0] 00_608 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_1[1] 01_608 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_1[2] 00_609 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_1[3] 01_609 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_1[4] 00_610 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_1[5] 01_610 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_1[6] 00_611 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_1[7] 01_611 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_1[8] 00_612 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_1[9] 01_612 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_2[0] 00_616 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_2[1] 01_616 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_2[2] 00_617 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_2[3] 01_617 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_2[4] 00_618 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_2[5] 01_618 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_2[6] 00_619 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_2[7] 01_619 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_2[8] 00_620 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_2[9] 01_620 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_3[0] 00_624 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_3[1] 01_624 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_3[2] 00_625 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_3[3] 01_625 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_3[4] 00_626 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_3[5] 01_626 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_3[6] 00_627 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_3[7] 01_627 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_3[8] 00_628 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_3[9] 01_628 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_4[0] 00_632 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_4[1] 01_632 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_4[2] 00_633 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_4[3] 01_633 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_4[4] 00_634 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_4[5] 01_634 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_4[6] 00_635 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_4[7] 01_635 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_4[8] 00_636 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_4[9] 01_636 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_ENABLE[0] 00_614 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_ENABLE[1] 01_614 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_ENABLE[2] 00_615 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_ENABLE[3] 01_615 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_1[0] 00_640 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_1[1] 01_640 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_1[2] 00_641 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_1[3] 01_641 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_1[4] 00_642 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_1[5] 01_642 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_1[6] 00_643 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_1[7] 01_643 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_1[8] 00_644 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_1[9] 01_644 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_2[0] 00_648 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_2[1] 01_648 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_2[2] 00_649 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_2[3] 01_649 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_2[4] 00_650 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_2[5] 01_650 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_2[6] 00_651 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_2[7] 01_651 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_2[8] 00_652 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_2[9] 01_652 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_3[0] 00_656 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_3[1] 01_656 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_3[2] 00_657 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_3[3] 01_657 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_3[4] 00_658 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_3[5] 01_658 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_3[6] 00_659 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_3[7] 01_659 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_3[8] 00_660 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_3[9] 01_660 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_4[0] 00_664 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_4[1] 01_664 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_4[2] 00_665 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_4[3] 01_665 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_4[4] 00_666 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_4[5] 01_666 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_4[6] 00_667 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_4[7] 01_667 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_4[8] 00_668 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_4[9] 01_668 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_ENABLE[0] 00_646 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_ENABLE[1] 01_646 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_ENABLE[2] 00_647 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_ENABLE[3] 01_647 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_USE 01_645 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_LEN[0] 00_623 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_LEN[1] 01_623 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COMMON_SWING[0] 03_311 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_KEEP_IDLE 00_591 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_MAX_LAT[0] 00_557 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_MAX_LAT[1] 01_557 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_MAX_LAT[2] 00_558 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_MAX_LAT[3] 01_558 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_MAX_LAT[4] 00_559 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_MAX_LAT[5] 01_559 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_MIN_LAT[0] 00_565 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_MIN_LAT[1] 01_565 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_MIN_LAT[2] 00_566 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_MIN_LAT[3] 01_566 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_MIN_LAT[4] 00_567 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_MIN_LAT[5] 01_567 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_PRECEDENCE 00_590 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_REPEAT_WAIT[0] 00_573 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_REPEAT_WAIT[1] 01_573 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_REPEAT_WAIT[2] 00_574 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_REPEAT_WAIT[3] 01_574 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_REPEAT_WAIT[4] 00_575 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_1[0] 00_544 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_1[1] 01_544 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_1[2] 00_545 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_1[3] 01_545 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_1[4] 00_546 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_1[5] 01_546 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_1[6] 00_547 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_1[7] 01_547 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_1[8] 00_548 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_1[9] 01_548 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_2[0] 00_552 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_2[1] 01_552 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_2[2] 00_553 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_2[3] 01_553 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_2[4] 00_554 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_2[5] 01_554 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_2[6] 00_555 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_2[7] 01_555 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_2[8] 00_556 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_2[9] 01_556 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_3[0] 00_560 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_3[1] 01_560 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_3[2] 00_561 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_3[3] 01_561 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_3[4] 00_562 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_3[5] 01_562 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_3[6] 00_563 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_3[7] 01_563 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_3[8] 00_564 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_3[9] 01_564 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_4[0] 00_568 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_4[1] 01_568 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_4[2] 00_569 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_4[3] 01_569 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_4[4] 00_570 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_4[5] 01_570 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_4[6] 00_571 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_4[7] 01_571 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_4[8] 00_572 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_4[9] 01_572 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_ENABLE[0] 00_549 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_ENABLE[1] 01_549 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_ENABLE[2] 00_550 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_ENABLE[3] 01_550 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_1[0] 00_576 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_1[1] 01_576 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_1[2] 00_577 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_1[3] 01_577 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_1[4] 00_578 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_1[5] 01_578 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_1[6] 00_579 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_1[7] 01_579 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_1[8] 00_580 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_1[9] 01_580 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_2[0] 00_584 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_2[1] 01_584 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_2[2] 00_585 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_2[3] 01_585 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_2[4] 00_586 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_2[5] 01_586 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_2[6] 00_587 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_2[7] 01_587 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_2[8] 00_588 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_2[9] 01_588 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_3[0] 00_592 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_3[1] 01_592 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_3[2] 00_593 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_3[3] 01_593 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_3[4] 00_594 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_3[5] 01_594 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_3[6] 00_595 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_3[7] 01_595 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_3[8] 00_596 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_3[9] 01_596 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_4[0] 00_600 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_4[1] 01_600 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_4[2] 00_601 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_4[3] 01_601 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_4[4] 00_602 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_4[5] 01_602 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_4[6] 00_603 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_4[7] 01_603 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_4[8] 00_604 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_4[9] 01_604 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_ENABLE[0] 00_581 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_ENABLE[1] 01_581 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_ENABLE[2] 00_582 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_ENABLE[3] 01_582 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_USE 00_583 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_LEN[0] 00_589 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_LEN[1] 01_589 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_CORRECT_USE 00_551 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.DEC_MCOMMA_DETECT 01_494 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.DEC_PCOMMA_DETECT 00_495 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.DEC_VALID_COMMA_ONLY 00_494 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.DMONITOR_CFG[0] 02_368 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.DMONITOR_CFG[1] 03_368 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.DMONITOR_CFG[2] 02_369 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.DMONITOR_CFG[3] 03_369 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.DMONITOR_CFG[4] 02_370 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.DMONITOR_CFG[5] 03_370 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.DMONITOR_CFG[6] 02_371 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.DMONITOR_CFG[7] 03_371 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.DMONITOR_CFG[8] 02_372 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.DMONITOR_CFG[9] 03_372 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.DMONITOR_CFG[10] 02_373 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.DMONITOR_CFG[11] 03_373 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.DMONITOR_CFG[12] 02_374 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.DMONITOR_CFG[13] 03_374 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.DMONITOR_CFG[14] 02_375 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.DMONITOR_CFG[15] 03_375 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.DMONITOR_CFG[16] 02_376 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.DMONITOR_CFG[17] 03_376 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.DMONITOR_CFG[18] 02_377 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.DMONITOR_CFG[19] 03_377 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.DMONITOR_CFG[20] 02_378 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.DMONITOR_CFG[21] 03_378 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.DMONITOR_CFG[22] 02_379 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.DMONITOR_CFG[23] 03_379 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_CLK_PHASE_SEL[0] 03_463 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_CONTROL[0] 00_488 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_CONTROL[1] 01_488 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_CONTROL[2] 00_489 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_CONTROL[3] 01_489 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_CONTROL[4] 00_490 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_CONTROL[5] 01_490 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_ERRDET_EN 01_492 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_EYE_SCAN_EN 00_492 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_HORZ_OFFSET[0] 00_480 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_HORZ_OFFSET[1] 01_480 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_HORZ_OFFSET[2] 00_481 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_HORZ_OFFSET[3] 01_481 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_HORZ_OFFSET[4] 00_482 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_HORZ_OFFSET[5] 01_482 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_HORZ_OFFSET[6] 00_483 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_HORZ_OFFSET[7] 01_483 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_HORZ_OFFSET[8] 00_484 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_HORZ_OFFSET[9] 01_484 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_HORZ_OFFSET[10] 00_485 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_HORZ_OFFSET[11] 01_485 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_PMA_CFG[0] 02_624 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_PMA_CFG[1] 03_624 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_PMA_CFG[2] 02_625 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_PMA_CFG[3] 03_625 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_PMA_CFG[4] 02_626 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_PMA_CFG[5] 03_626 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_PMA_CFG[6] 02_627 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_PMA_CFG[7] 03_627 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_PMA_CFG[8] 02_628 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_PMA_CFG[9] 03_628 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_PRESCALE[0] 01_477 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_PRESCALE[1] 00_478 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_PRESCALE[2] 01_478 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_PRESCALE[3] 00_479 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_PRESCALE[4] 01_479 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[0] 00_392 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[1] 01_392 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[2] 00_393 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[3] 01_393 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[4] 00_394 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[5] 01_394 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[6] 00_395 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[7] 01_395 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[8] 00_396 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[9] 01_396 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[10] 00_397 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[11] 01_397 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[12] 00_398 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[13] 01_398 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[14] 00_399 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[15] 01_399 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[16] 00_400 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[17] 01_400 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[18] 00_401 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[19] 01_401 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[20] 00_402 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[21] 01_402 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[22] 00_403 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[23] 01_403 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[24] 00_404 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[25] 01_404 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[26] 00_405 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[27] 01_405 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[28] 00_406 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[29] 01_406 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[30] 00_407 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[31] 01_407 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[32] 00_408 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[33] 01_408 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[34] 00_409 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[35] 01_409 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[36] 00_410 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[37] 01_410 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[38] 00_411 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[39] 01_411 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[40] 00_412 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[41] 01_412 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[42] 00_413 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[43] 01_413 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[44] 00_414 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[45] 01_414 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[46] 00_415 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[47] 01_415 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[48] 00_416 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[49] 01_416 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[50] 00_417 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[51] 01_417 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[52] 00_418 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[53] 01_418 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[54] 00_419 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[55] 01_419 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[56] 00_420 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[57] 01_420 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[58] 00_421 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[59] 01_421 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[60] 00_422 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[61] 01_422 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[62] 00_423 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[63] 01_423 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[64] 00_424 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[65] 01_424 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[66] 00_425 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[67] 01_425 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[68] 00_426 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[69] 01_426 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[70] 00_427 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[71] 01_427 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[72] 00_428 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[73] 01_428 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[74] 00_429 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[75] 01_429 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[76] 00_430 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[77] 01_430 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[78] 00_431 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[79] 01_431 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[0] 00_352 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[1] 01_352 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[2] 00_353 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[3] 01_353 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[4] 00_354 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[5] 01_354 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[6] 00_355 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[7] 01_355 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[8] 00_356 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[9] 01_356 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[10] 00_357 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[11] 01_357 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[12] 00_358 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[13] 01_358 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[14] 00_359 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[15] 01_359 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[16] 00_360 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[17] 01_360 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[18] 00_361 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[19] 01_361 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[20] 00_362 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[21] 01_362 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[22] 00_363 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[23] 01_363 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[24] 00_364 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[25] 01_364 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[26] 00_365 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[27] 01_365 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[28] 00_366 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[29] 01_366 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[30] 00_367 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[31] 01_367 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[32] 00_368 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[33] 01_368 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[34] 00_369 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[35] 01_369 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[36] 00_370 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[37] 01_370 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[38] 00_371 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[39] 01_371 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[40] 00_372 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[41] 01_372 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[42] 00_373 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[43] 01_373 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[44] 00_374 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[45] 01_374 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[46] 00_375 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[47] 01_375 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[48] 00_376 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[49] 01_376 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[50] 00_377 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[51] 01_377 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[52] 00_378 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[53] 01_378 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[54] 00_379 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[55] 01_379 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[56] 00_380 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[57] 01_380 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[58] 00_381 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[59] 01_381 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[60] 00_382 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[61] 01_382 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[62] 00_383 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[63] 01_383 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[64] 00_384 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[65] 01_384 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[66] 00_385 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[67] 01_385 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[68] 00_386 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[69] 01_386 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[70] 00_387 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[71] 01_387 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[72] 00_388 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[73] 01_388 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[74] 00_389 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[75] 01_389 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[76] 00_390 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[77] 01_390 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[78] 00_391 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[79] 01_391 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[0] 00_432 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[1] 01_432 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[2] 00_433 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[3] 01_433 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[4] 00_434 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[5] 01_434 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[6] 00_435 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[7] 01_435 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[8] 00_436 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[9] 01_436 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[10] 00_437 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[11] 01_437 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[12] 00_438 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[13] 01_438 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[14] 00_439 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[15] 01_439 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[16] 00_440 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[17] 01_440 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[18] 00_441 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[19] 01_441 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[20] 00_442 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[21] 01_442 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[22] 00_443 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[23] 01_443 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[24] 00_444 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[25] 01_444 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[26] 00_445 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[27] 01_445 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[28] 00_446 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[29] 01_446 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[30] 00_447 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[31] 01_447 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[32] 00_448 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[33] 01_448 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[34] 00_449 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[35] 01_449 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[36] 00_450 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[37] 01_450 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[38] 00_451 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[39] 01_451 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[40] 00_452 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[41] 01_452 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[42] 00_453 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[43] 01_453 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[44] 00_454 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[45] 01_454 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[46] 00_455 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[47] 01_455 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[48] 00_456 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[49] 01_456 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[50] 00_457 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[51] 01_457 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[52] 00_458 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[53] 01_458 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[54] 00_459 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[55] 01_459 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[56] 00_460 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[57] 01_460 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[58] 00_461 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[59] 01_461 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[60] 00_462 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[61] 01_462 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[62] 00_463 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[63] 01_463 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[64] 00_464 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[65] 01_464 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[66] 00_465 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[67] 01_465 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[68] 00_466 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[69] 01_466 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[70] 00_467 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[71] 01_467 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[72] 00_468 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[73] 01_468 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[74] 00_469 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[75] 01_469 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[76] 00_470 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[77] 01_470 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[78] 00_471 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[79] 01_471 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_VERT_OFFSET[0] 00_472 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_VERT_OFFSET[1] 01_472 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_VERT_OFFSET[2] 00_473 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_VERT_OFFSET[3] 01_473 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_VERT_OFFSET[4] 00_474 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_VERT_OFFSET[5] 01_474 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_VERT_OFFSET[6] 00_475 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_VERT_OFFSET[7] 01_475 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_VERT_OFFSET[8] 00_476 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.FTS_DESKEW_SEQ_ENABLE[0] 00_662 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.FTS_DESKEW_SEQ_ENABLE[1] 01_662 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.FTS_DESKEW_SEQ_ENABLE[2] 00_663 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.FTS_DESKEW_SEQ_ENABLE[3] 01_663 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.FTS_LANE_DESKEW_CFG[0] 00_654 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.FTS_LANE_DESKEW_CFG[1] 01_654 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.FTS_LANE_DESKEW_CFG[2] 00_655 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.FTS_LANE_DESKEW_CFG[3] 01_655 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.FTS_LANE_DESKEW_EN 01_653 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.GEARBOX_MODE[0] 00_224 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.GEARBOX_MODE[1] 01_224 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.GEARBOX_MODE[2] 00_225 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.IN_USE 00_00 00_01 00_47 00_52 00_53 00_65 01_01 01_47 02_129 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.LOOPBACK_CFG[0] 02_20 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.OUTREFCLK_SEL_INV[0] 00_149 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.OUTREFCLK_SEL_INV[1] 01_149 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PCS_PCIE_EN 00_216 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[0] 02_184 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[1] 03_184 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[2] 02_185 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[3] 03_185 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[4] 02_186 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[5] 03_186 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[6] 02_187 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[7] 03_187 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[8] 02_188 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[9] 03_188 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[10] 02_189 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[11] 03_189 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[12] 02_190 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[13] 03_190 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[14] 02_191 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[15] 03_191 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[16] 02_192 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[17] 03_192 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[18] 02_193 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[19] 03_193 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[20] 02_194 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[21] 03_194 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[22] 02_195 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[23] 03_195 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[24] 02_196 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[25] 03_196 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[26] 02_197 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[27] 03_197 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[28] 02_198 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[29] 03_198 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[30] 02_199 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[31] 03_199 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[32] 02_200 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[33] 03_200 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[34] 02_201 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[35] 03_201 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[36] 02_202 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[37] 03_202 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[38] 02_203 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[39] 03_203 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[40] 02_204 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[41] 03_204 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[42] 02_205 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[43] 03_205 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[44] 02_206 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[45] 03_206 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[46] 02_207 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[47] 03_207 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PD_TRANS_TIME_FROM_P2[0] 01_216 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PD_TRANS_TIME_FROM_P2[1] 00_217 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PD_TRANS_TIME_FROM_P2[2] 01_217 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PD_TRANS_TIME_FROM_P2[3] 00_218 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PD_TRANS_TIME_FROM_P2[4] 01_218 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PD_TRANS_TIME_FROM_P2[5] 00_219 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PD_TRANS_TIME_FROM_P2[6] 01_219 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PD_TRANS_TIME_FROM_P2[7] 00_220 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PD_TRANS_TIME_FROM_P2[8] 01_220 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PD_TRANS_TIME_FROM_P2[9] 00_221 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PD_TRANS_TIME_FROM_P2[10] 01_221 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PD_TRANS_TIME_FROM_P2[11] 00_222 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PD_TRANS_TIME_NONE_P2[0] 00_208 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PD_TRANS_TIME_NONE_P2[1] 01_208 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PD_TRANS_TIME_NONE_P2[2] 00_209 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PD_TRANS_TIME_NONE_P2[3] 01_209 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PD_TRANS_TIME_NONE_P2[4] 00_210 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PD_TRANS_TIME_NONE_P2[5] 01_210 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PD_TRANS_TIME_NONE_P2[6] 00_211 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PD_TRANS_TIME_NONE_P2[7] 01_211 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PD_TRANS_TIME_TO_P2[0] 00_212 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PD_TRANS_TIME_TO_P2[1] 01_212 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PD_TRANS_TIME_TO_P2[2] 00_213 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PD_TRANS_TIME_TO_P2[3] 01_213 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PD_TRANS_TIME_TO_P2[4] 00_214 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PD_TRANS_TIME_TO_P2[5] 01_214 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PD_TRANS_TIME_TO_P2[6] 00_215 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PD_TRANS_TIME_TO_P2[7] 01_215 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PMA_LOOPBACK_CFG[0] 01_207 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PMA_RSV[0] 02_520 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PMA_RSV[1] 03_520 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PMA_RSV[2] 02_521 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PMA_RSV[3] 03_521 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PMA_RSV[4] 02_522 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PMA_RSV[5] 03_522 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PMA_RSV[6] 02_523 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PMA_RSV[7] 03_523 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PMA_RSV[8] 02_524 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PMA_RSV[9] 03_524 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PMA_RSV[10] 02_525 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PMA_RSV[11] 03_525 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PMA_RSV[12] 02_526 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PMA_RSV[13] 03_526 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PMA_RSV[14] 02_527 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PMA_RSV[15] 03_527 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PMA_RSV[16] 02_528 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PMA_RSV[17] 03_528 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PMA_RSV[18] 02_529 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PMA_RSV[19] 03_529 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PMA_RSV[20] 02_530 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PMA_RSV[21] 03_530 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PMA_RSV[22] 02_531 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PMA_RSV[23] 03_531 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PMA_RSV[24] 02_532 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PMA_RSV[25] 03_532 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PMA_RSV[26] 02_533 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PMA_RSV[27] 03_533 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PMA_RSV[28] 02_534 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PMA_RSV[29] 03_534 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PMA_RSV[30] 02_535 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PMA_RSV[31] 03_535 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PMA_RSV2[0] 02_336 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PMA_RSV2[1] 03_336 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PMA_RSV2[2] 02_337 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PMA_RSV2[3] 03_337 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PMA_RSV2[4] 02_338 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PMA_RSV2[5] 03_338 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PMA_RSV2[6] 02_339 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PMA_RSV2[7] 03_339 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PMA_RSV2[8] 02_340 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PMA_RSV2[9] 03_340 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PMA_RSV2[10] 02_341 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PMA_RSV2[11] 03_341 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PMA_RSV2[12] 02_342 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PMA_RSV2[13] 03_342 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PMA_RSV2[14] 02_343 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PMA_RSV2[15] 03_343 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PMA_RSV2[16] 02_344 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PMA_RSV2[17] 03_344 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PMA_RSV2[18] 02_345 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PMA_RSV2[19] 03_345 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PMA_RSV2[20] 02_346 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PMA_RSV2[21] 03_346 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PMA_RSV2[22] 02_347 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PMA_RSV2[23] 03_347 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PMA_RSV2[24] 02_348 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PMA_RSV2[25] 03_348 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PMA_RSV2[26] 02_349 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PMA_RSV2[27] 03_349 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PMA_RSV2[28] 02_350 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PMA_RSV2[29] 03_350 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PMA_RSV2[30] 02_351 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PMA_RSV2[31] 03_351 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PMA_RSV3[0] 02_288 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PMA_RSV3[1] 03_288 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PMA_RSV4[0] 02_156 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PMA_RSV4[1] 03_156 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PMA_RSV4[2] 02_157 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PMA_RSV4[3] 03_157 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PMA_RSV5[0] 03_159 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PMA_RSV6[0] 02_303 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PMA_RSV7[0] 03_303 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_BIAS_CFG[0] 02_112 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_BIAS_CFG[1] 03_112 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_BIAS_CFG[2] 02_113 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_BIAS_CFG[3] 03_113 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_BIAS_CFG[4] 02_114 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_BIAS_CFG[5] 03_114 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_BIAS_CFG[6] 02_115 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_BIAS_CFG[7] 03_115 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_BIAS_CFG[8] 02_116 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_BIAS_CFG[9] 03_116 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_BIAS_CFG[10] 02_117 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_BIAS_CFG[11] 03_117 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_BIAS_CFG[12] 02_118 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_BIAS_CFG[13] 03_118 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_BIAS_CFG[14] 02_119 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_BIAS_CFG[15] 03_119 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_BUFFER_CFG[0] 02_536 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_BUFFER_CFG[1] 03_536 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_BUFFER_CFG[2] 02_537 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_BUFFER_CFG[3] 03_537 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_BUFFER_CFG[4] 02_538 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_BUFFER_CFG[5] 03_538 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_CLKMUX_EN[0] 02_128 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_CM_SEL[0] 00_138 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_CM_SEL[1] 01_138 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_CM_TRIM[0] 02_304 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_CM_TRIM[1] 03_304 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_CM_TRIM[2] 02_305 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_CM_TRIM[3] 03_305 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_DATA_WIDTH[0] 01_141 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_DATA_WIDTH[1] 00_142 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_DATA_WIDTH[2] 01_142 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_DDI_SEL[0] 00_696 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_DDI_SEL[1] 01_696 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_DDI_SEL[2] 00_697 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_DDI_SEL[3] 01_697 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_DDI_SEL[4] 00_698 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_DDI_SEL[5] 01_698 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_DEBUG_CFG[0] 02_616 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_DEBUG_CFG[1] 03_616 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_DEBUG_CFG[2] 02_617 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_DEBUG_CFG[3] 03_617 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_DEBUG_CFG[4] 02_618 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_DEBUG_CFG[5] 03_618 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_DEBUG_CFG[6] 02_619 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_DEBUG_CFG[7] 03_619 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_DEBUG_CFG[8] 02_620 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_DEBUG_CFG[9] 03_620 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_DEBUG_CFG[10] 02_621 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_DEBUG_CFG[11] 03_621 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_DEBUG_CFG[12] 02_622 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_DEBUG_CFG[13] 03_622 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_DEFER_RESET_BUF_EN 02_552 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_DISPERR_SEQ_MATCH 01_495 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_OS_CFG[0] 00_288 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_OS_CFG[1] 01_288 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_OS_CFG[2] 00_289 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_OS_CFG[3] 01_289 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_OS_CFG[4] 00_290 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_OS_CFG[5] 01_290 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_OS_CFG[6] 00_291 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_OS_CFG[7] 01_291 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_OS_CFG[8] 00_292 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_OS_CFG[9] 01_292 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_OS_CFG[10] 00_293 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_OS_CFG[11] 01_293 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_OS_CFG[12] 00_294 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_SIG_VALID_DLY[0] 00_524 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_SIG_VALID_DLY[1] 01_524 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_SIG_VALID_DLY[2] 00_525 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_SIG_VALID_DLY[3] 01_525 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_SIG_VALID_DLY[4] 00_526 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_XCLK_SEL.RXUSR 00_143 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_CLK25_DIV[0] 00_139 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_CLK25_DIV[1] 01_139 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_CLK25_DIV[2] 00_140 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_CLK25_DIV[3] 01_140 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_CLK25_DIV[4] 00_141 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXBUF_ADDR_MODE.FAST 03_555 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXBUF_EIDLE_HI_CNT[0] 02_558 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXBUF_EIDLE_HI_CNT[1] 03_558 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXBUF_EIDLE_HI_CNT[2] 02_559 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXBUF_EIDLE_HI_CNT[3] 03_559 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXBUF_EIDLE_LO_CNT[0] 02_556 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXBUF_EIDLE_LO_CNT[1] 03_556 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXBUF_EIDLE_LO_CNT[2] 02_557 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXBUF_EIDLE_LO_CNT[3] 03_557 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXBUF_EN 02_11 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXBUF_RESET_ON_CB_CHANGE 02_560 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXBUF_RESET_ON_COMMAALIGN 02_561 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXBUF_RESET_ON_EIDLE 02_547 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXBUF_RESET_ON_RATE_CHANGE 03_560 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXBUF_THRESH_OVFLW[0] 03_552 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXBUF_THRESH_OVFLW[1] 02_553 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXBUF_THRESH_OVFLW[2] 03_553 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXBUF_THRESH_OVFLW[3] 02_554 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXBUF_THRESH_OVFLW[4] 03_554 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXBUF_THRESH_OVFLW[5] 02_555 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXBUF_THRESH_OVRD 02_548 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXBUF_THRESH_UNDFLW[0] 02_544 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXBUF_THRESH_UNDFLW[1] 03_544 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXBUF_THRESH_UNDFLW[2] 02_545 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXBUF_THRESH_UNDFLW[3] 03_545 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXBUF_THRESH_UNDFLW[4] 02_546 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXBUF_THRESH_UNDFLW[5] 03_546 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXBUFRESET_TIME[0] 01_101 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXBUFRESET_TIME[1] 00_102 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXBUFRESET_TIME[2] 01_102 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXBUFRESET_TIME[3] 00_103 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXBUFRESET_TIME[4] 01_103 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[0] 02_640 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[1] 03_640 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[2] 02_641 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[3] 03_641 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[4] 02_642 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[5] 03_642 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[6] 02_643 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[7] 03_643 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[8] 02_644 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[9] 03_644 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[10] 02_645 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[11] 03_645 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[12] 02_646 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[13] 03_646 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[14] 02_647 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[15] 03_647 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[16] 02_648 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[17] 03_648 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[18] 02_649 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[19] 03_649 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[20] 02_650 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[21] 03_650 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[22] 02_651 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[23] 03_651 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[24] 02_652 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[25] 03_652 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[26] 02_653 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[27] 03_653 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[28] 02_654 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[29] 03_654 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[30] 02_655 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[31] 03_655 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[32] 02_656 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[33] 03_656 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[34] 02_657 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[35] 03_657 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[36] 02_658 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[37] 03_658 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[38] 02_659 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[39] 03_659 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[40] 02_660 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[41] 03_660 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[42] 02_661 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[43] 03_661 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[44] 02_662 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[45] 03_662 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[46] 02_663 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[47] 03_663 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[48] 02_664 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[49] 03_664 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[50] 02_665 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[51] 03_665 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[52] 02_666 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[53] 03_666 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[54] 02_667 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[55] 03_667 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[56] 02_668 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[57] 03_668 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[58] 02_669 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[59] 03_669 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[60] 02_670 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[61] 03_670 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[62] 02_671 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[63] 03_671 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[64] 02_672 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[65] 03_672 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[66] 02_673 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[67] 03_673 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[68] 02_674 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[69] 03_674 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[70] 02_675 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[71] 03_675 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[72] 02_676 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[73] 03_676 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[74] 02_677 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[75] 03_677 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[76] 02_678 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[77] 03_678 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[78] 02_679 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[79] 03_679 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[80] 02_680 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[81] 03_680 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[82] 02_681 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_FR_RESET_ON_EIDLE[0] 02_638 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_HOLD_DURING_EIDLE[0] 03_637 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_LOCK_CFG[0] 02_632 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_LOCK_CFG[1] 03_632 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_LOCK_CFG[2] 02_633 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_LOCK_CFG[3] 03_633 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_LOCK_CFG[4] 02_634 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_LOCK_CFG[5] 03_634 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_PH_RESET_ON_EIDLE[0] 03_638 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDRFREQRESET_TIME[0] 01_106 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDRFREQRESET_TIME[1] 00_107 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDRFREQRESET_TIME[2] 01_107 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDRFREQRESET_TIME[3] 00_108 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDRFREQRESET_TIME[4] 01_108 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDRPHRESET_TIME[0] 00_109 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDRPHRESET_TIME[1] 01_109 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDRPHRESET_TIME[2] 00_110 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDRPHRESET_TIME[3] 01_110 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDRPHRESET_TIME[4] 00_111 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXDLY_CFG[0] 00_680 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXDLY_CFG[1] 01_680 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXDLY_CFG[2] 00_681 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXDLY_CFG[3] 01_681 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXDLY_CFG[4] 00_682 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXDLY_CFG[5] 01_682 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXDLY_CFG[6] 00_683 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXDLY_CFG[7] 01_683 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXDLY_CFG[8] 00_684 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXDLY_CFG[9] 01_684 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXDLY_CFG[10] 00_685 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXDLY_CFG[11] 01_685 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXDLY_CFG[12] 00_686 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXDLY_CFG[13] 01_686 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXDLY_CFG[14] 00_687 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXDLY_CFG[15] 01_687 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXDLY_LCFG[0] 02_576 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXDLY_LCFG[1] 03_576 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXDLY_LCFG[2] 02_577 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXDLY_LCFG[3] 03_577 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXDLY_LCFG[4] 02_578 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXDLY_LCFG[5] 03_578 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXDLY_LCFG[6] 02_579 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXDLY_LCFG[7] 03_579 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXDLY_LCFG[8] 02_580 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXDLY_TAP_CFG[0] 00_672 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXDLY_TAP_CFG[1] 01_672 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXDLY_TAP_CFG[2] 00_673 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXDLY_TAP_CFG[3] 01_673 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXDLY_TAP_CFG[4] 00_674 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXDLY_TAP_CFG[5] 01_674 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXDLY_TAP_CFG[6] 00_675 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXDLY_TAP_CFG[7] 01_675 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXDLY_TAP_CFG[8] 00_676 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXDLY_TAP_CFG[9] 01_676 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXDLY_TAP_CFG[10] 00_677 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXDLY_TAP_CFG[11] 01_677 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXDLY_TAP_CFG[12] 00_678 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXDLY_TAP_CFG[13] 01_678 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXDLY_TAP_CFG[14] 00_679 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXDLY_TAP_CFG[15] 01_679 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXGEARBOX_EN 01_607 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXISCANRESET_TIME[0] 01_123 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXISCANRESET_TIME[1] 00_124 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXISCANRESET_TIME[2] 01_124 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXISCANRESET_TIME[3] 00_125 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXISCANRESET_TIME[4] 01_125 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPM_BIAS_STARTUP_DISABLE[0] 03_391 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPM_CFG[0] 02_328 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPM_CFG[1] 03_328 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPM_CFG[2] 02_329 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPM_CFG[3] 03_329 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPM_CM_CFG[0] 02_430 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPM_GC_CFG[0] 02_432 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPM_GC_CFG[1] 03_432 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPM_GC_CFG[2] 02_433 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPM_GC_CFG[3] 03_433 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPM_GC_CFG[4] 02_434 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPM_GC_CFG[5] 03_434 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPM_GC_CFG[6] 02_435 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPM_GC_CFG[7] 03_435 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPM_GC_CFG[8] 02_436 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPM_GC_CFG2[0] 03_442 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPM_GC_CFG2[1] 02_443 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPM_GC_CFG2[2] 03_443 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPM_HF_CFG[0] 00_336 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPM_HF_CFG[1] 01_336 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPM_HF_CFG[2] 00_337 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPM_HF_CFG[3] 01_337 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPM_HF_CFG[4] 00_338 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPM_HF_CFG[5] 01_338 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPM_HF_CFG[6] 00_339 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPM_HF_CFG[7] 01_339 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPM_HF_CFG[8] 00_340 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPM_HF_CFG[9] 01_340 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPM_HF_CFG[10] 00_341 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPM_HF_CFG[11] 01_341 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPM_HF_CFG[12] 00_342 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPM_HF_CFG[13] 01_342 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPM_HF_CFG2[0] 02_424 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPM_HF_CFG2[1] 03_424 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPM_HF_CFG2[2] 02_425 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPM_HF_CFG2[3] 03_425 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPM_HF_CFG2[4] 02_426 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPM_HF_CFG3[0] 03_389 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPM_HF_CFG3[1] 02_390 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPM_HF_CFG3[2] 03_390 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPM_HF_CFG3[3] 02_391 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPM_HOLD_DURING_EIDLE[0] 00_247 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPM_INCM_CFG[0] 02_439 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPM_IPCM_CFG[0] 03_439 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPM_LF_CFG[0] 00_344 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPM_LF_CFG[1] 01_344 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPM_LF_CFG[2] 00_345 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPM_LF_CFG[3] 01_345 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPM_LF_CFG[4] 00_346 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPM_LF_CFG[5] 01_346 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPM_LF_CFG[6] 00_347 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPM_LF_CFG[7] 01_347 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPM_LF_CFG[8] 00_348 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPM_LF_CFG[9] 01_348 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPM_LF_CFG[10] 00_349 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPM_LF_CFG[11] 01_349 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPM_LF_CFG[12] 00_350 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPM_LF_CFG[13] 01_350 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPM_LF_CFG[14] 00_351 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPM_LF_CFG[15] 01_351 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPM_LF_CFG[16] 00_343 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPM_LF_CFG[17] 01_343 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPM_LF_CFG2[0] 03_426 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPM_LF_CFG2[1] 02_427 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPM_LF_CFG2[2] 03_427 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPM_LF_CFG2[3] 02_428 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPM_LF_CFG2[4] 03_428 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPM_OSINT_CFG[0] 02_440 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPM_OSINT_CFG[1] 03_440 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPM_OSINT_CFG[2] 02_441 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPM_CFG1[0] 02_330 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPMRESET_TIME[0] 00_112 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPMRESET_TIME[1] 01_112 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPMRESET_TIME[2] 00_113 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPMRESET_TIME[3] 01_113 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPMRESET_TIME[4] 00_114 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPMRESET_TIME[5] 01_114 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPMRESET_TIME[6] 00_115 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXOOB_CFG[0] 00_144 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXOOB_CFG[1] 01_144 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXOOB_CFG[2] 00_145 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXOOB_CFG[3] 01_145 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXOOB_CFG[4] 00_146 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXOOB_CFG[5] 01_146 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXOOB_CFG[6] 00_147 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXOOB_CLK_CFG.FABRIC 03_129 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXOSCALRESET_TIME[0] 00_187 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXOSCALRESET_TIME[1] 01_187 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXOSCALRESET_TIME[2] 00_188 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXOSCALRESET_TIME[3] 01_188 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXOSCALRESET_TIME[4] 00_189 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXOSCALRESET_TIMEOUT[0] 01_189 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXOSCALRESET_TIMEOUT[1] 00_190 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXOSCALRESET_TIMEOUT[2] 01_190 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXOSCALRESET_TIMEOUT[3] 00_191 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXOSCALRESET_TIMEOUT[4] 01_191 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXOUT_DIV[0] 02_384 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXOUT_DIV[1] 03_384 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXPCSRESET_TIME[0] 01_115 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXPCSRESET_TIME[1] 00_116 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXPCSRESET_TIME[2] 01_116 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXPCSRESET_TIME[3] 00_117 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXPCSRESET_TIME[4] 01_117 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXPH_CFG[0] 02_584 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXPH_CFG[1] 03_584 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXPH_CFG[2] 02_585 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXPH_CFG[3] 03_585 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXPH_CFG[4] 02_586 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXPH_CFG[5] 03_586 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXPH_CFG[6] 02_587 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXPH_CFG[7] 03_587 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXPH_CFG[8] 02_588 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXPH_CFG[9] 03_588 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXPH_CFG[10] 02_589 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXPH_CFG[11] 03_589 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXPH_CFG[12] 02_590 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXPH_CFG[13] 03_590 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXPH_CFG[14] 02_591 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXPH_CFG[15] 03_591 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXPH_CFG[16] 02_592 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXPH_CFG[17] 03_592 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXPH_CFG[18] 02_593 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXPH_CFG[19] 03_593 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXPH_CFG[20] 02_594 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXPH_CFG[21] 03_594 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXPH_CFG[22] 02_595 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXPH_CFG[23] 03_595 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXPH_MONITOR_SEL[0] 00_700 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXPH_MONITOR_SEL[1] 01_700 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXPH_MONITOR_SEL[2] 00_701 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXPH_MONITOR_SEL[3] 01_701 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXPH_MONITOR_SEL[4] 00_702 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXPHDLY_CFG[0] 02_600 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXPHDLY_CFG[1] 03_600 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXPHDLY_CFG[2] 02_601 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXPHDLY_CFG[3] 03_601 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXPHDLY_CFG[4] 02_602 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXPHDLY_CFG[5] 03_602 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXPHDLY_CFG[6] 02_603 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXPHDLY_CFG[7] 03_603 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXPHDLY_CFG[8] 02_604 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXPHDLY_CFG[9] 03_604 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXPHDLY_CFG[10] 02_605 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXPHDLY_CFG[11] 03_605 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXPHDLY_CFG[12] 02_606 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXPHDLY_CFG[13] 03_606 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXPHDLY_CFG[14] 02_607 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXPHDLY_CFG[15] 03_607 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXPHDLY_CFG[16] 02_608 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXPHDLY_CFG[17] 03_608 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXPHDLY_CFG[18] 02_609 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXPHDLY_CFG[19] 03_609 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXPHDLY_CFG[20] 02_610 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXPHDLY_CFG[21] 03_610 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXPHDLY_CFG[22] 02_611 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXPHDLY_CFG[23] 03_611 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXPI_CFG0[0] 03_430 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXPI_CFG0[1] 02_431 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXPI_CFG0[2] 03_431 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXPI_CFG1[0] 02_442 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXPI_CFG2[0] 03_441 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXPMARESET_TIME[0] 00_104 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXPMARESET_TIME[1] 01_104 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXPMARESET_TIME[2] 00_105 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXPMARESET_TIME[3] 01_105 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXPMARESET_TIME[4] 00_106 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXPRBS_ERR_LOOPBACK[0] 00_136 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXSLIDE_AUTO_WAIT[0] 00_520 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXSLIDE_AUTO_WAIT[1] 01_520 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXSLIDE_AUTO_WAIT[2] 00_521 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXSLIDE_AUTO_WAIT[3] 01_521 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXSLIDE_MODE.AUTO 00_519 !01_519 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXSLIDE_MODE.PCS !00_519 01_519 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXSLIDE_MODE.PMA 00_519 01_519 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXSYNC_MULTILANE[0] 00_133 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXSYNC_OVRD[0] 01_135 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXSYNC_SKIP_DA[0] 01_134 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.SAS_MAX_COM[0] 00_171 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.SAS_MAX_COM[1] 01_171 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.SAS_MAX_COM[2] 00_172 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.SAS_MAX_COM[3] 01_172 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.SAS_MAX_COM[4] 00_173 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.SAS_MAX_COM[5] 01_173 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.SAS_MAX_COM[6] 00_174 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.SAS_MIN_COM[0] 01_156 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.SAS_MIN_COM[1] 00_157 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.SAS_MIN_COM[2] 01_157 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.SAS_MIN_COM[3] 00_158 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.SAS_MIN_COM[4] 01_158 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.SAS_MIN_COM[5] 00_159 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.SATA_BURST_SEQ_LEN[0] 00_150 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.SATA_BURST_SEQ_LEN[1] 01_150 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.SATA_BURST_SEQ_LEN[2] 00_151 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.SATA_BURST_SEQ_LEN[3] 01_151 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.SATA_BURST_VAL[0] 01_147 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.SATA_BURST_VAL[1] 00_148 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.SATA_BURST_VAL[2] 01_148 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.SATA_EIDLE_VAL[0] 00_152 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.SATA_EIDLE_VAL[1] 01_152 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.SATA_EIDLE_VAL[2] 00_153 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.SATA_MAX_BURST[0] 00_168 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.SATA_MAX_BURST[1] 01_168 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.SATA_MAX_BURST[2] 00_169 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.SATA_MAX_BURST[3] 01_169 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.SATA_MAX_BURST[4] 00_170 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.SATA_MAX_BURST[5] 01_170 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.SATA_MAX_INIT[0] 00_176 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.SATA_MAX_INIT[1] 01_176 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.SATA_MAX_INIT[2] 00_177 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.SATA_MAX_INIT[3] 01_177 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.SATA_MAX_INIT[4] 00_178 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.SATA_MAX_INIT[5] 01_178 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.SATA_MAX_WAKE[0] 00_179 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.SATA_MAX_WAKE[1] 01_179 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.SATA_MAX_WAKE[2] 00_180 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.SATA_MAX_WAKE[3] 01_180 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.SATA_MAX_WAKE[4] 00_181 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.SATA_MAX_WAKE[5] 01_181 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.SATA_MIN_BURST[0] 01_153 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.SATA_MIN_BURST[1] 00_154 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.SATA_MIN_BURST[2] 01_154 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.SATA_MIN_BURST[3] 00_155 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.SATA_MIN_BURST[4] 01_155 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.SATA_MIN_BURST[5] 00_156 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.SATA_MIN_INIT[0] 00_160 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.SATA_MIN_INIT[1] 01_160 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.SATA_MIN_INIT[2] 00_161 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.SATA_MIN_INIT[3] 01_161 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.SATA_MIN_INIT[4] 00_162 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.SATA_MIN_INIT[5] 01_162 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.SATA_MIN_WAKE[0] 00_163 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.SATA_MIN_WAKE[1] 01_163 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.SATA_MIN_WAKE[2] 00_164 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.SATA_MIN_WAKE[3] 01_164 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.SATA_MIN_WAKE[4] 00_165 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.SATA_MIN_WAKE[5] 01_165 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.SATA_PLL_CFG.VCO_1500MHZ 02_55 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.SATA_PLL_CFG.VCO_750MHZ 03_55 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.SHOW_REALIGN_COMMA 01_522 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TERM_RCAL_CFG[0] 02_136 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TERM_RCAL_CFG[1] 03_136 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TERM_RCAL_CFG[2] 02_137 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TERM_RCAL_CFG[3] 03_137 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TERM_RCAL_CFG[4] 02_138 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TERM_RCAL_CFG[5] 03_138 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TERM_RCAL_CFG[6] 02_139 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TERM_RCAL_CFG[7] 03_139 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TERM_RCAL_CFG[8] 02_140 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TERM_RCAL_CFG[9] 03_140 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TERM_RCAL_CFG[10] 02_141 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TERM_RCAL_CFG[11] 03_141 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TERM_RCAL_CFG[12] 02_142 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TERM_RCAL_CFG[13] 03_142 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TERM_RCAL_CFG[14] 02_143 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TERM_RCAL_OVRD[0] 03_150 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TERM_RCAL_OVRD[1] 02_151 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TERM_RCAL_OVRD[2] 03_151 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TRANS_TIME_RATE[0] 00_192 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TRANS_TIME_RATE[1] 01_192 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TRANS_TIME_RATE[2] 00_193 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TRANS_TIME_RATE[3] 01_193 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TRANS_TIME_RATE[4] 00_194 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TRANS_TIME_RATE[5] 01_194 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TRANS_TIME_RATE[6] 00_195 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TRANS_TIME_RATE[7] 01_195 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TST_RSV[0] 02_504 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TST_RSV[1] 03_504 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TST_RSV[2] 02_505 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TST_RSV[3] 03_505 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TST_RSV[4] 02_506 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TST_RSV[5] 03_506 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TST_RSV[6] 02_507 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TST_RSV[7] 03_507 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TST_RSV[8] 02_508 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TST_RSV[9] 03_508 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TST_RSV[10] 02_509 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TST_RSV[11] 03_509 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TST_RSV[12] 02_510 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TST_RSV[13] 03_510 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TST_RSV[14] 02_511 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TST_RSV[15] 03_511 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TST_RSV[16] 02_512 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TST_RSV[17] 03_512 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TST_RSV[18] 02_513 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TST_RSV[19] 03_513 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TST_RSV[20] 02_514 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TST_RSV[21] 03_514 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TST_RSV[22] 02_515 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TST_RSV[23] 03_515 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TST_RSV[24] 02_516 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TST_RSV[25] 03_516 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TST_RSV[26] 02_517 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TST_RSV[27] 03_517 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TST_RSV[28] 02_518 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TST_RSV[29] 03_518 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TST_RSV[30] 02_519 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TST_RSV[31] 03_519 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_CLKMUX_EN[0] 03_128 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_DATA_WIDTH[0] 02_152 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_DATA_WIDTH[1] 03_152 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_DATA_WIDTH[2] 02_153 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_DRIVE_MODE.PIPE 00_200 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_EIDLE_ASSERT_DELAY[0] 00_203 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_EIDLE_ASSERT_DELAY[1] 01_203 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_EIDLE_ASSERT_DELAY[2] 00_204 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_EIDLE_DEASSERT_DELAY[0] 01_204 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_EIDLE_DEASSERT_DELAY[1] 00_205 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_EIDLE_DEASSERT_DELAY[2] 01_205 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_LOOPBACK_DRIVE_HIZ 01_202 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_MAINCURSOR_SEL[0] 03_289 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_MARGIN_FULL_0[0] 02_232 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_MARGIN_FULL_0[1] 03_232 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_MARGIN_FULL_0[2] 02_233 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_MARGIN_FULL_0[3] 03_233 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_MARGIN_FULL_0[4] 02_234 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_MARGIN_FULL_0[5] 03_234 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_MARGIN_FULL_0[6] 02_235 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_MARGIN_FULL_1[0] 02_236 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_MARGIN_FULL_1[1] 03_236 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_MARGIN_FULL_1[2] 02_237 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_MARGIN_FULL_1[3] 03_237 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_MARGIN_FULL_1[4] 02_238 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_MARGIN_FULL_1[5] 03_238 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_MARGIN_FULL_1[6] 02_239 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_MARGIN_FULL_2[0] 02_240 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_MARGIN_FULL_2[1] 03_240 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_MARGIN_FULL_2[2] 02_241 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_MARGIN_FULL_2[3] 03_241 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_MARGIN_FULL_2[4] 02_242 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_MARGIN_FULL_2[5] 03_242 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_MARGIN_FULL_2[6] 02_243 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_MARGIN_FULL_3[0] 02_244 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_MARGIN_FULL_3[1] 03_244 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_MARGIN_FULL_3[2] 02_245 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_MARGIN_FULL_3[3] 03_245 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_MARGIN_FULL_3[4] 02_246 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_MARGIN_FULL_3[5] 03_246 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_MARGIN_FULL_3[6] 02_247 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_MARGIN_FULL_4[0] 02_248 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_MARGIN_FULL_4[1] 03_248 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_MARGIN_FULL_4[2] 02_249 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_MARGIN_FULL_4[3] 03_249 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_MARGIN_FULL_4[4] 02_250 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_MARGIN_FULL_4[5] 03_250 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_MARGIN_FULL_4[6] 02_251 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_MARGIN_LOW_0[0] 02_252 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_MARGIN_LOW_0[1] 03_252 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_MARGIN_LOW_0[2] 02_253 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_MARGIN_LOW_0[3] 03_253 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_MARGIN_LOW_0[4] 02_254 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_MARGIN_LOW_0[5] 03_254 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_MARGIN_LOW_0[6] 02_255 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_MARGIN_LOW_1[0] 02_256 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_MARGIN_LOW_1[1] 03_256 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_MARGIN_LOW_1[2] 02_257 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_MARGIN_LOW_1[3] 03_257 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_MARGIN_LOW_1[4] 02_258 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_MARGIN_LOW_1[5] 03_258 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_MARGIN_LOW_1[6] 02_259 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_MARGIN_LOW_2[0] 02_260 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_MARGIN_LOW_2[1] 03_260 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_MARGIN_LOW_2[2] 02_261 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_MARGIN_LOW_2[3] 03_261 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_MARGIN_LOW_2[4] 02_262 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_MARGIN_LOW_2[5] 03_262 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_MARGIN_LOW_2[6] 02_263 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_MARGIN_LOW_3[0] 02_264 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_MARGIN_LOW_3[1] 03_264 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_MARGIN_LOW_3[2] 02_265 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_MARGIN_LOW_3[3] 03_265 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_MARGIN_LOW_3[4] 02_266 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_MARGIN_LOW_3[5] 03_266 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_MARGIN_LOW_3[6] 02_267 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_MARGIN_LOW_4[0] 02_268 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_MARGIN_LOW_4[1] 03_268 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_MARGIN_LOW_4[2] 02_269 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_MARGIN_LOW_4[3] 03_269 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_MARGIN_LOW_4[4] 02_270 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_MARGIN_LOW_4[5] 03_270 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_MARGIN_LOW_4[6] 02_271 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_PREDRIVER_MODE[0] 00_206 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_RXDETECT_CFG[0] 02_296 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_RXDETECT_CFG[1] 03_296 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_RXDETECT_CFG[2] 02_297 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_RXDETECT_CFG[3] 03_297 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_RXDETECT_CFG[4] 02_298 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_RXDETECT_CFG[5] 03_298 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_RXDETECT_CFG[6] 02_299 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_RXDETECT_CFG[7] 03_299 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_RXDETECT_CFG[8] 02_300 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_RXDETECT_CFG[9] 03_300 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_RXDETECT_CFG[10] 02_301 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_RXDETECT_CFG[11] 03_301 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_RXDETECT_CFG[12] 02_302 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_RXDETECT_CFG[13] 03_302 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_RXDETECT_REF[0] 02_292 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_RXDETECT_REF[1] 03_292 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_RXDETECT_REF[2] 02_293 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_XCLK_SEL.TXUSR 03_11 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_CLK25_DIV[0] 02_144 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_CLK25_DIV[1] 03_144 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_CLK25_DIV[2] 02_145 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_CLK25_DIV[3] 03_145 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_CLK25_DIV[4] 02_146 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_DEEMPH0[0] 02_272 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_DEEMPH0[1] 03_272 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_DEEMPH0[2] 02_273 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_DEEMPH0[3] 03_273 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_DEEMPH0[4] 02_274 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_DEEMPH0[5] 03_274 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_DEEMPH1[0] 02_276 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_DEEMPH1[1] 03_276 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_DEEMPH1[2] 02_277 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_DEEMPH1[3] 03_277 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_DEEMPH1[4] 02_278 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_DEEMPH1[5] 03_278 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXBUF_EN 00_231 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXBUF_RESET_ON_RATE_CHANGE 01_231 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXDLY_CFG[0] 02_80 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXDLY_CFG[1] 03_80 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXDLY_CFG[2] 02_81 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXDLY_CFG[3] 03_81 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXDLY_CFG[4] 02_82 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXDLY_CFG[5] 03_82 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXDLY_CFG[6] 02_83 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXDLY_CFG[7] 03_83 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXDLY_CFG[8] 02_84 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXDLY_CFG[9] 03_84 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXDLY_CFG[10] 02_85 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXDLY_CFG[11] 03_85 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXDLY_CFG[12] 02_86 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXDLY_CFG[13] 03_86 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXDLY_CFG[14] 02_87 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXDLY_CFG[15] 03_87 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXDLY_LCFG[0] 02_568 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXDLY_LCFG[1] 03_568 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXDLY_LCFG[2] 02_569 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXDLY_LCFG[3] 03_569 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXDLY_LCFG[4] 02_570 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXDLY_LCFG[5] 03_570 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXDLY_LCFG[6] 02_571 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXDLY_LCFG[7] 03_571 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXDLY_LCFG[8] 02_572 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXDLY_TAP_CFG[0] 02_88 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXDLY_TAP_CFG[1] 03_88 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXDLY_TAP_CFG[2] 02_89 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXDLY_TAP_CFG[3] 03_89 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXDLY_TAP_CFG[4] 02_90 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXDLY_TAP_CFG[5] 03_90 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXDLY_TAP_CFG[6] 02_91 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXDLY_TAP_CFG[7] 03_91 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXDLY_TAP_CFG[8] 02_92 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXDLY_TAP_CFG[9] 03_92 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXDLY_TAP_CFG[10] 02_93 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXDLY_TAP_CFG[11] 03_93 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXDLY_TAP_CFG[12] 02_94 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXDLY_TAP_CFG[13] 03_94 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXDLY_TAP_CFG[14] 02_95 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXDLY_TAP_CFG[15] 03_95 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXGEARBOX_EN 01_226 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXOOB_CFG[0] 03_20 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXOUT_DIV[0] 02_386 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXOUT_DIV[1] 03_386 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPCSRESET_TIME[0] 01_130 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPCSRESET_TIME[1] 00_131 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPCSRESET_TIME[2] 01_131 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPCSRESET_TIME[3] 00_132 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPCSRESET_TIME[4] 01_132 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPH_CFG[0] 02_96 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPH_CFG[1] 03_96 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPH_CFG[2] 02_97 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPH_CFG[3] 03_97 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPH_CFG[4] 02_98 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPH_CFG[5] 03_98 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPH_CFG[6] 02_99 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPH_CFG[7] 03_99 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPH_CFG[8] 02_100 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPH_CFG[9] 03_100 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPH_CFG[10] 02_101 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPH_CFG[11] 03_101 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPH_CFG[12] 02_102 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPH_CFG[13] 03_102 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPH_CFG[14] 02_103 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPH_CFG[15] 03_103 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPH_MONITOR_SEL[0] 02_108 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPH_MONITOR_SEL[1] 03_108 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPH_MONITOR_SEL[2] 02_109 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPH_MONITOR_SEL[3] 03_109 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPH_MONITOR_SEL[4] 02_110 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPHDLY_CFG[0] 02_64 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPHDLY_CFG[1] 03_64 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPHDLY_CFG[2] 02_65 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPHDLY_CFG[3] 03_65 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPHDLY_CFG[4] 02_66 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPHDLY_CFG[5] 03_66 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPHDLY_CFG[6] 02_67 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPHDLY_CFG[7] 03_67 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPHDLY_CFG[8] 02_68 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPHDLY_CFG[9] 03_68 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPHDLY_CFG[10] 02_69 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPHDLY_CFG[11] 03_69 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPHDLY_CFG[12] 02_70 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPHDLY_CFG[13] 03_70 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPHDLY_CFG[14] 02_71 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPHDLY_CFG[15] 03_71 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPHDLY_CFG[16] 02_72 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPHDLY_CFG[17] 03_72 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPHDLY_CFG[18] 02_73 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPHDLY_CFG[19] 03_73 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPHDLY_CFG[20] 02_74 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPHDLY_CFG[21] 03_74 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPHDLY_CFG[22] 02_75 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPHDLY_CFG[23] 03_75 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPI_GREY_SEL[0] 03_498 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPI_INVSTROBE_SEL[0] 02_498 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPI_PPM_CFG[0] 02_488 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPI_PPM_CFG[1] 03_488 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPI_PPM_CFG[2] 02_489 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPI_PPM_CFG[3] 03_489 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPI_PPM_CFG[4] 02_490 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPI_PPM_CFG[5] 03_490 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPI_PPM_CFG[6] 02_491 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPI_PPM_CFG[7] 03_491 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPI_PPMCLK_SEL.TXUSRCLK2 03_497 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPI_SYNFREQ_PPM[0] 02_496 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPI_SYNFREQ_PPM[1] 03_496 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPI_SYNFREQ_PPM[2] 02_497 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPI_CFG0[0] 02_40 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPI_CFG0[1] 03_40 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPI_CFG1[0] 02_41 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPI_CFG1[1] 03_41 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPI_CFG2[0] 02_42 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPI_CFG2[1] 03_42 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPI_CFG3[0] 02_43 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPI_CFG4[0] 03_43 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPI_CFG5[0] 02_44 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPI_CFG5[1] 03_44 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPI_CFG5[2] 02_45 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPMARESET_TIME[0] 00_128 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPMARESET_TIME[1] 01_128 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPMARESET_TIME[2] 00_129 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPMARESET_TIME[3] 01_129 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPMARESET_TIME[4] 00_130 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXSYNC_MULTILANE[0] 01_133 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXSYNC_OVRD[0] 00_135 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXSYNC_SKIP_DA[0] 00_134 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.UCODEER_CLR[0] 01_00 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.USE_PCS_CLK_PHASE_SEL[0] 02_463 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ZINV_DMONITORCLK 02_13 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ZINV_DRPCLK 02_00 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ZINV_RXUSRCLK 03_01 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ZINV_SIGVALIDCLK 03_13 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ZINV_TXPHDLYTSTCLK 02_03 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ZINV_TXUSRCLK 03_04 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ZINV_CLKRSVD0 02_23 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ZINV_CLKRSVD1 03_23 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ZINV_RXUSRCLK2 02_02 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ZINV_TXUSRCLK2 02_05 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ACJTAG_DEBUG_MODE[0] 00_07 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ACJTAG_MODE[0] 01_06 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ACJTAG_RESET[0] 01_07 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[0] 02_464 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[1] 03_464 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[2] 02_465 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[3] 03_465 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[4] 02_466 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[5] 03_466 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[6] 02_467 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[7] 03_467 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[8] 02_468 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[9] 03_468 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[10] 02_469 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[11] 03_469 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[12] 02_470 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[13] 03_470 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[14] 02_471 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[15] 03_471 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[16] 02_472 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[17] 03_472 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[18] 02_473 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[19] 03_473 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ALIGN_COMMA_DOUBLE 00_522 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[0] 00_496 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[1] 01_496 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[2] 00_497 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[3] 01_497 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[4] 00_498 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[5] 01_498 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[6] 00_499 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[7] 01_499 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[8] 00_500 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[9] 01_500 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ALIGN_COMMA_WORD[0] 01_526 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ALIGN_COMMA_WORD[1] 00_527 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ALIGN_MCOMMA_DET 00_523 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[0] 00_504 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[1] 01_504 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[2] 00_505 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[3] 01_505 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[4] 00_506 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[5] 01_506 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[6] 00_507 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[7] 01_507 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[8] 00_508 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[9] 01_508 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ALIGN_PCOMMA_DET 01_523 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[0] 00_512 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[1] 01_512 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[2] 00_513 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[3] 01_513 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[4] 00_514 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[5] 01_514 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[6] 00_515 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[7] 01_515 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[8] 00_516 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[9] 01_516 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CBCC_DATA_SOURCE_SEL.DECODED 01_661 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[0] 02_392 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[1] 03_392 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[2] 02_393 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[3] 03_393 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[4] 02_394 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[5] 03_394 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[6] 02_395 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[7] 03_395 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[8] 02_396 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[9] 03_396 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[10] 02_397 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[11] 03_397 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[12] 02_398 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[13] 03_398 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[14] 02_399 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[15] 03_399 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[16] 02_400 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[17] 03_400 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[18] 02_401 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[19] 03_401 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[20] 02_402 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[21] 03_402 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[22] 02_403 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[23] 03_403 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[24] 02_404 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[25] 03_404 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[26] 02_405 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[27] 03_405 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[28] 02_406 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[29] 03_406 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[30] 02_407 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[31] 03_407 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[32] 02_408 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[33] 03_408 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[34] 02_409 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[35] 03_409 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[36] 02_410 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[37] 03_410 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[38] 02_411 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[39] 03_411 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[40] 02_412 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[41] 03_412 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[42] 02_413 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG2[0] 02_459 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG2[1] 03_459 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG2[2] 02_460 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG2[3] 03_460 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG2[4] 02_461 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG2[5] 03_461 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG2[6] 02_462 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG3[0] 02_416 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG3[1] 03_416 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG3[2] 02_417 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG3[3] 03_417 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG3[4] 02_418 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG3[5] 03_418 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG3[6] 02_419 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG4[0] 03_438 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG5[0] 02_429 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG5[1] 03_429 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG6[0] 03_436 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG6[1] 02_437 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG6[2] 03_437 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG6[3] 02_438 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_KEEP_ALIGN 01_631 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_MAX_SKEW[0] 00_670 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_MAX_SKEW[1] 01_670 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_MAX_SKEW[2] 00_671 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_MAX_SKEW[3] 01_671 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[0] 00_608 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[1] 01_608 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[2] 00_609 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[3] 01_609 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[4] 00_610 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[5] 01_610 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[6] 00_611 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[7] 01_611 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[8] 00_612 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[9] 01_612 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[0] 00_616 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[1] 01_616 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[2] 00_617 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[3] 01_617 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[4] 00_618 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[5] 01_618 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[6] 00_619 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[7] 01_619 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[8] 00_620 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[9] 01_620 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[0] 00_624 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[1] 01_624 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[2] 00_625 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[3] 01_625 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[4] 00_626 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[5] 01_626 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[6] 00_627 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[7] 01_627 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[8] 00_628 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[9] 01_628 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[0] 00_632 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[1] 01_632 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[2] 00_633 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[3] 01_633 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[4] 00_634 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[5] 01_634 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[6] 00_635 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[7] 01_635 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[8] 00_636 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[9] 01_636 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_ENABLE[0] 00_614 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_ENABLE[1] 01_614 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_ENABLE[2] 00_615 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_ENABLE[3] 01_615 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[0] 00_640 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[1] 01_640 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[2] 00_641 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[3] 01_641 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[4] 00_642 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[5] 01_642 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[6] 00_643 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[7] 01_643 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[8] 00_644 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[9] 01_644 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[0] 00_648 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[1] 01_648 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[2] 00_649 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[3] 01_649 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[4] 00_650 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[5] 01_650 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[6] 00_651 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[7] 01_651 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[8] 00_652 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[9] 01_652 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[0] 00_656 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[1] 01_656 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[2] 00_657 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[3] 01_657 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[4] 00_658 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[5] 01_658 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[6] 00_659 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[7] 01_659 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[8] 00_660 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[9] 01_660 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[0] 00_664 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[1] 01_664 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[2] 00_665 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[3] 01_665 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[4] 00_666 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[5] 01_666 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[6] 00_667 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[7] 01_667 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[8] 00_668 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[9] 01_668 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_ENABLE[0] 00_646 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_ENABLE[1] 01_646 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_ENABLE[2] 00_647 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_ENABLE[3] 01_647 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_USE 01_645 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_LEN[0] 00_623 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_LEN[1] 01_623 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COMMON_SWING[0] 03_311 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_KEEP_IDLE 00_591 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_MAX_LAT[0] 00_557 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_MAX_LAT[1] 01_557 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_MAX_LAT[2] 00_558 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_MAX_LAT[3] 01_558 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_MAX_LAT[4] 00_559 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_MAX_LAT[5] 01_559 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_MIN_LAT[0] 00_565 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_MIN_LAT[1] 01_565 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_MIN_LAT[2] 00_566 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_MIN_LAT[3] 01_566 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_MIN_LAT[4] 00_567 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_MIN_LAT[5] 01_567 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_PRECEDENCE 00_590 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_REPEAT_WAIT[0] 00_573 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_REPEAT_WAIT[1] 01_573 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_REPEAT_WAIT[2] 00_574 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_REPEAT_WAIT[3] 01_574 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_REPEAT_WAIT[4] 00_575 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[0] 00_544 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[1] 01_544 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[2] 00_545 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[3] 01_545 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[4] 00_546 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[5] 01_546 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[6] 00_547 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[7] 01_547 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[8] 00_548 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[9] 01_548 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[0] 00_552 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[1] 01_552 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[2] 00_553 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[3] 01_553 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[4] 00_554 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[5] 01_554 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[6] 00_555 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[7] 01_555 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[8] 00_556 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[9] 01_556 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[0] 00_560 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[1] 01_560 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[2] 00_561 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[3] 01_561 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[4] 00_562 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[5] 01_562 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[6] 00_563 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[7] 01_563 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[8] 00_564 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[9] 01_564 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[0] 00_568 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[1] 01_568 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[2] 00_569 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[3] 01_569 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[4] 00_570 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[5] 01_570 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[6] 00_571 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[7] 01_571 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[8] 00_572 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[9] 01_572 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_ENABLE[0] 00_549 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_ENABLE[1] 01_549 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_ENABLE[2] 00_550 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_ENABLE[3] 01_550 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[0] 00_576 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[1] 01_576 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[2] 00_577 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[3] 01_577 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[4] 00_578 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[5] 01_578 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[6] 00_579 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[7] 01_579 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[8] 00_580 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[9] 01_580 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[0] 00_584 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[1] 01_584 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[2] 00_585 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[3] 01_585 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[4] 00_586 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[5] 01_586 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[6] 00_587 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[7] 01_587 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[8] 00_588 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[9] 01_588 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[0] 00_592 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[1] 01_592 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[2] 00_593 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[3] 01_593 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[4] 00_594 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[5] 01_594 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[6] 00_595 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[7] 01_595 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[8] 00_596 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[9] 01_596 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[0] 00_600 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[1] 01_600 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[2] 00_601 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[3] 01_601 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[4] 00_602 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[5] 01_602 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[6] 00_603 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[7] 01_603 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[8] 00_604 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[9] 01_604 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_ENABLE[0] 00_581 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_ENABLE[1] 01_581 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_ENABLE[2] 00_582 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_ENABLE[3] 01_582 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_USE 00_583 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_LEN[0] 00_589 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_LEN[1] 01_589 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_CORRECT_USE 00_551 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.DEC_MCOMMA_DETECT 01_494 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.DEC_PCOMMA_DETECT 00_495 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.DEC_VALID_COMMA_ONLY 00_494 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[0] 02_368 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[1] 03_368 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[2] 02_369 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[3] 03_369 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[4] 02_370 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[5] 03_370 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[6] 02_371 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[7] 03_371 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[8] 02_372 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[9] 03_372 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[10] 02_373 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[11] 03_373 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[12] 02_374 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[13] 03_374 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[14] 02_375 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[15] 03_375 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[16] 02_376 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[17] 03_376 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[18] 02_377 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[19] 03_377 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[20] 02_378 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[21] 03_378 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[22] 02_379 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[23] 03_379 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_CLK_PHASE_SEL[0] 03_463 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_CONTROL[0] 00_488 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_CONTROL[1] 01_488 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_CONTROL[2] 00_489 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_CONTROL[3] 01_489 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_CONTROL[4] 00_490 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_CONTROL[5] 01_490 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_ERRDET_EN 01_492 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_EYE_SCAN_EN 00_492 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_HORZ_OFFSET[0] 00_480 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_HORZ_OFFSET[1] 01_480 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_HORZ_OFFSET[2] 00_481 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_HORZ_OFFSET[3] 01_481 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_HORZ_OFFSET[4] 00_482 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_HORZ_OFFSET[5] 01_482 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_HORZ_OFFSET[6] 00_483 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_HORZ_OFFSET[7] 01_483 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_HORZ_OFFSET[8] 00_484 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_HORZ_OFFSET[9] 01_484 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_HORZ_OFFSET[10] 00_485 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_HORZ_OFFSET[11] 01_485 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_PMA_CFG[0] 02_624 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_PMA_CFG[1] 03_624 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_PMA_CFG[2] 02_625 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_PMA_CFG[3] 03_625 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_PMA_CFG[4] 02_626 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_PMA_CFG[5] 03_626 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_PMA_CFG[6] 02_627 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_PMA_CFG[7] 03_627 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_PMA_CFG[8] 02_628 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_PMA_CFG[9] 03_628 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_PRESCALE[0] 01_477 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_PRESCALE[1] 00_478 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_PRESCALE[2] 01_478 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_PRESCALE[3] 00_479 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_PRESCALE[4] 01_479 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[0] 00_392 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[1] 01_392 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[2] 00_393 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[3] 01_393 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[4] 00_394 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[5] 01_394 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[6] 00_395 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[7] 01_395 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[8] 00_396 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[9] 01_396 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[10] 00_397 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[11] 01_397 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[12] 00_398 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[13] 01_398 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[14] 00_399 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[15] 01_399 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[16] 00_400 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[17] 01_400 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[18] 00_401 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[19] 01_401 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[20] 00_402 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[21] 01_402 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[22] 00_403 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[23] 01_403 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[24] 00_404 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[25] 01_404 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[26] 00_405 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[27] 01_405 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[28] 00_406 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[29] 01_406 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[30] 00_407 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[31] 01_407 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[32] 00_408 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[33] 01_408 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[34] 00_409 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[35] 01_409 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[36] 00_410 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[37] 01_410 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[38] 00_411 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[39] 01_411 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[40] 00_412 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[41] 01_412 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[42] 00_413 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[43] 01_413 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[44] 00_414 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[45] 01_414 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[46] 00_415 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[47] 01_415 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[48] 00_416 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[49] 01_416 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[50] 00_417 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[51] 01_417 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[52] 00_418 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[53] 01_418 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[54] 00_419 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[55] 01_419 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[56] 00_420 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[57] 01_420 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[58] 00_421 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[59] 01_421 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[60] 00_422 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[61] 01_422 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[62] 00_423 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[63] 01_423 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[64] 00_424 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[65] 01_424 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[66] 00_425 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[67] 01_425 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[68] 00_426 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[69] 01_426 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[70] 00_427 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[71] 01_427 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[72] 00_428 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[73] 01_428 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[74] 00_429 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[75] 01_429 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[76] 00_430 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[77] 01_430 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[78] 00_431 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[79] 01_431 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[0] 00_352 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[1] 01_352 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[2] 00_353 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[3] 01_353 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[4] 00_354 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[5] 01_354 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[6] 00_355 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[7] 01_355 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[8] 00_356 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[9] 01_356 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[10] 00_357 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[11] 01_357 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[12] 00_358 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[13] 01_358 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[14] 00_359 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[15] 01_359 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[16] 00_360 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[17] 01_360 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[18] 00_361 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[19] 01_361 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[20] 00_362 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[21] 01_362 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[22] 00_363 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[23] 01_363 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[24] 00_364 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[25] 01_364 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[26] 00_365 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[27] 01_365 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[28] 00_366 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[29] 01_366 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[30] 00_367 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[31] 01_367 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[32] 00_368 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[33] 01_368 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[34] 00_369 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[35] 01_369 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[36] 00_370 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[37] 01_370 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[38] 00_371 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[39] 01_371 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[40] 00_372 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[41] 01_372 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[42] 00_373 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[43] 01_373 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[44] 00_374 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[45] 01_374 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[46] 00_375 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[47] 01_375 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[48] 00_376 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[49] 01_376 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[50] 00_377 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[51] 01_377 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[52] 00_378 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[53] 01_378 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[54] 00_379 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[55] 01_379 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[56] 00_380 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[57] 01_380 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[58] 00_381 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[59] 01_381 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[60] 00_382 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[61] 01_382 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[62] 00_383 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[63] 01_383 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[64] 00_384 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[65] 01_384 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[66] 00_385 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[67] 01_385 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[68] 00_386 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[69] 01_386 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[70] 00_387 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[71] 01_387 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[72] 00_388 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[73] 01_388 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[74] 00_389 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[75] 01_389 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[76] 00_390 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[77] 01_390 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[78] 00_391 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[79] 01_391 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[0] 00_432 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[1] 01_432 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[2] 00_433 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[3] 01_433 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[4] 00_434 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[5] 01_434 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[6] 00_435 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[7] 01_435 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[8] 00_436 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[9] 01_436 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[10] 00_437 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[11] 01_437 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[12] 00_438 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[13] 01_438 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[14] 00_439 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[15] 01_439 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[16] 00_440 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[17] 01_440 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[18] 00_441 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[19] 01_441 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[20] 00_442 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[21] 01_442 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[22] 00_443 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[23] 01_443 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[24] 00_444 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[25] 01_444 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[26] 00_445 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[27] 01_445 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[28] 00_446 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[29] 01_446 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[30] 00_447 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[31] 01_447 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[32] 00_448 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[33] 01_448 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[34] 00_449 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[35] 01_449 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[36] 00_450 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[37] 01_450 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[38] 00_451 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[39] 01_451 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[40] 00_452 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[41] 01_452 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[42] 00_453 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[43] 01_453 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[44] 00_454 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[45] 01_454 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[46] 00_455 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[47] 01_455 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[48] 00_456 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[49] 01_456 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[50] 00_457 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[51] 01_457 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[52] 00_458 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[53] 01_458 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[54] 00_459 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[55] 01_459 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[56] 00_460 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[57] 01_460 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[58] 00_461 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[59] 01_461 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[60] 00_462 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[61] 01_462 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[62] 00_463 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[63] 01_463 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[64] 00_464 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[65] 01_464 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[66] 00_465 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[67] 01_465 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[68] 00_466 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[69] 01_466 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[70] 00_467 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[71] 01_467 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[72] 00_468 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[73] 01_468 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[74] 00_469 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[75] 01_469 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[76] 00_470 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[77] 01_470 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[78] 00_471 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[79] 01_471 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_VERT_OFFSET[0] 00_472 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_VERT_OFFSET[1] 01_472 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_VERT_OFFSET[2] 00_473 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_VERT_OFFSET[3] 01_473 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_VERT_OFFSET[4] 00_474 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_VERT_OFFSET[5] 01_474 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_VERT_OFFSET[6] 00_475 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_VERT_OFFSET[7] 01_475 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_VERT_OFFSET[8] 00_476 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.FTS_DESKEW_SEQ_ENABLE[0] 00_662 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.FTS_DESKEW_SEQ_ENABLE[1] 01_662 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.FTS_DESKEW_SEQ_ENABLE[2] 00_663 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.FTS_DESKEW_SEQ_ENABLE[3] 01_663 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.FTS_LANE_DESKEW_CFG[0] 00_654 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.FTS_LANE_DESKEW_CFG[1] 01_654 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.FTS_LANE_DESKEW_CFG[2] 00_655 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.FTS_LANE_DESKEW_CFG[3] 01_655 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.FTS_LANE_DESKEW_EN 01_653 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.GEARBOX_MODE[0] 00_224 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.GEARBOX_MODE[1] 01_224 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.GEARBOX_MODE[2] 00_225 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.IN_USE 00_00 00_01 00_47 00_52 00_53 00_65 01_01 01_47 02_129 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.INV_DMONITORCLK 02_13 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.INV_DRPCLK 02_00 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.INV_RXUSRCLK 03_01 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.INV_SIGVALIDCLK 03_13 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.INV_TXPHDLYTSTCLK 02_03 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.INV_TXUSRCLK 03_04 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.INV_CLKRSVD0 02_23 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.INV_CLKRSVD1 03_23 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.INV_RXUSRCLK2 02_02 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.INV_TXUSRCLK2 02_05 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.LOOPBACK_CFG[0] 02_20 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.OUTREFCLK_SEL_INV[0] 00_149 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.OUTREFCLK_SEL_INV[1] 01_149 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PCS_PCIE_EN 00_216 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[0] 02_184 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[1] 03_184 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[2] 02_185 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[3] 03_185 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[4] 02_186 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[5] 03_186 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[6] 02_187 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[7] 03_187 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[8] 02_188 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[9] 03_188 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[10] 02_189 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[11] 03_189 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[12] 02_190 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[13] 03_190 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[14] 02_191 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[15] 03_191 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[16] 02_192 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[17] 03_192 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[18] 02_193 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[19] 03_193 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[20] 02_194 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[21] 03_194 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[22] 02_195 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[23] 03_195 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[24] 02_196 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[25] 03_196 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[26] 02_197 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[27] 03_197 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[28] 02_198 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[29] 03_198 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[30] 02_199 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[31] 03_199 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[32] 02_200 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[33] 03_200 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[34] 02_201 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[35] 03_201 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[36] 02_202 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[37] 03_202 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[38] 02_203 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[39] 03_203 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[40] 02_204 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[41] 03_204 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[42] 02_205 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[43] 03_205 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[44] 02_206 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[45] 03_206 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[46] 02_207 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[47] 03_207 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[0] 01_216 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[1] 00_217 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[2] 01_217 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[3] 00_218 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[4] 01_218 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[5] 00_219 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[6] 01_219 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[7] 00_220 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[8] 01_220 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[9] 00_221 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[10] 01_221 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[11] 00_222 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[0] 00_208 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[1] 01_208 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[2] 00_209 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[3] 01_209 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[4] 00_210 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[5] 01_210 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[6] 00_211 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[7] 01_211 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[0] 00_212 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[1] 01_212 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[2] 00_213 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[3] 01_213 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[4] 00_214 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[5] 01_214 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[6] 00_215 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[7] 01_215 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PMA_LOOPBACK_CFG[0] 01_207 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[0] 02_520 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[1] 03_520 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[2] 02_521 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[3] 03_521 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[4] 02_522 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[5] 03_522 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[6] 02_523 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[7] 03_523 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[8] 02_524 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[9] 03_524 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[10] 02_525 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[11] 03_525 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[12] 02_526 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[13] 03_526 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[14] 02_527 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[15] 03_527 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[16] 02_528 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[17] 03_528 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[18] 02_529 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[19] 03_529 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[20] 02_530 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[21] 03_530 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[22] 02_531 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[23] 03_531 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[24] 02_532 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[25] 03_532 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[26] 02_533 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[27] 03_533 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[28] 02_534 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[29] 03_534 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[30] 02_535 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[31] 03_535 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[0] 02_336 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[1] 03_336 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[2] 02_337 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[3] 03_337 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[4] 02_338 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[5] 03_338 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[6] 02_339 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[7] 03_339 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[8] 02_340 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[9] 03_340 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[10] 02_341 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[11] 03_341 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[12] 02_342 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[13] 03_342 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[14] 02_343 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[15] 03_343 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[16] 02_344 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[17] 03_344 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[18] 02_345 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[19] 03_345 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[20] 02_346 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[21] 03_346 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[22] 02_347 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[23] 03_347 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[24] 02_348 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[25] 03_348 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[26] 02_349 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[27] 03_349 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[28] 02_350 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[29] 03_350 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[30] 02_351 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[31] 03_351 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV3[0] 02_288 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV3[1] 03_288 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV4[0] 02_156 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV4[1] 03_156 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV4[2] 02_157 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV4[3] 03_157 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV5[0] 03_159 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV6[0] 02_303 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV7[0] 03_303 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_BIAS_CFG[0] 02_112 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_BIAS_CFG[1] 03_112 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_BIAS_CFG[2] 02_113 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_BIAS_CFG[3] 03_113 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_BIAS_CFG[4] 02_114 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_BIAS_CFG[5] 03_114 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_BIAS_CFG[6] 02_115 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_BIAS_CFG[7] 03_115 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_BIAS_CFG[8] 02_116 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_BIAS_CFG[9] 03_116 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_BIAS_CFG[10] 02_117 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_BIAS_CFG[11] 03_117 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_BIAS_CFG[12] 02_118 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_BIAS_CFG[13] 03_118 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_BIAS_CFG[14] 02_119 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_BIAS_CFG[15] 03_119 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_BUFFER_CFG[0] 02_536 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_BUFFER_CFG[1] 03_536 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_BUFFER_CFG[2] 02_537 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_BUFFER_CFG[3] 03_537 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_BUFFER_CFG[4] 02_538 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_BUFFER_CFG[5] 03_538 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_CLKMUX_EN[0] 02_128 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_CM_SEL[0] 00_138 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_CM_SEL[1] 01_138 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_CM_TRIM[0] 02_304 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_CM_TRIM[1] 03_304 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_CM_TRIM[2] 02_305 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_CM_TRIM[3] 03_305 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_DATA_WIDTH[0] 01_141 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_DATA_WIDTH[1] 00_142 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_DATA_WIDTH[2] 01_142 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_DDI_SEL[0] 00_696 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_DDI_SEL[1] 01_696 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_DDI_SEL[2] 00_697 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_DDI_SEL[3] 01_697 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_DDI_SEL[4] 00_698 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_DDI_SEL[5] 01_698 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_DEBUG_CFG[0] 02_616 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_DEBUG_CFG[1] 03_616 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_DEBUG_CFG[2] 02_617 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_DEBUG_CFG[3] 03_617 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_DEBUG_CFG[4] 02_618 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_DEBUG_CFG[5] 03_618 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_DEBUG_CFG[6] 02_619 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_DEBUG_CFG[7] 03_619 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_DEBUG_CFG[8] 02_620 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_DEBUG_CFG[9] 03_620 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_DEBUG_CFG[10] 02_621 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_DEBUG_CFG[11] 03_621 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_DEBUG_CFG[12] 02_622 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_DEBUG_CFG[13] 03_622 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_DEFER_RESET_BUF_EN 02_552 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_DISPERR_SEQ_MATCH 01_495 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_OS_CFG[0] 00_288 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_OS_CFG[1] 01_288 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_OS_CFG[2] 00_289 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_OS_CFG[3] 01_289 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_OS_CFG[4] 00_290 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_OS_CFG[5] 01_290 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_OS_CFG[6] 00_291 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_OS_CFG[7] 01_291 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_OS_CFG[8] 00_292 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_OS_CFG[9] 01_292 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_OS_CFG[10] 00_293 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_OS_CFG[11] 01_293 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_OS_CFG[12] 00_294 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_SIG_VALID_DLY[0] 00_524 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_SIG_VALID_DLY[1] 01_524 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_SIG_VALID_DLY[2] 00_525 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_SIG_VALID_DLY[3] 01_525 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_SIG_VALID_DLY[4] 00_526 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_XCLK_SEL.RXUSR 00_143 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_CLK25_DIV[0] 00_139 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_CLK25_DIV[1] 01_139 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_CLK25_DIV[2] 00_140 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_CLK25_DIV[3] 01_140 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_CLK25_DIV[4] 00_141 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXBUF_ADDR_MODE.FAST 03_555 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXBUF_EIDLE_HI_CNT[0] 02_558 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXBUF_EIDLE_HI_CNT[1] 03_558 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXBUF_EIDLE_HI_CNT[2] 02_559 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXBUF_EIDLE_HI_CNT[3] 03_559 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXBUF_EIDLE_LO_CNT[0] 02_556 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXBUF_EIDLE_LO_CNT[1] 03_556 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXBUF_EIDLE_LO_CNT[2] 02_557 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXBUF_EIDLE_LO_CNT[3] 03_557 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXBUF_EN 02_11 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXBUF_RESET_ON_CB_CHANGE 02_560 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXBUF_RESET_ON_COMMAALIGN 02_561 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXBUF_RESET_ON_EIDLE 02_547 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXBUF_RESET_ON_RATE_CHANGE 03_560 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXBUF_THRESH_OVFLW[0] 03_552 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXBUF_THRESH_OVFLW[1] 02_553 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXBUF_THRESH_OVFLW[2] 03_553 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXBUF_THRESH_OVFLW[3] 02_554 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXBUF_THRESH_OVFLW[4] 03_554 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXBUF_THRESH_OVFLW[5] 02_555 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXBUF_THRESH_OVRD 02_548 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXBUF_THRESH_UNDFLW[0] 02_544 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXBUF_THRESH_UNDFLW[1] 03_544 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXBUF_THRESH_UNDFLW[2] 02_545 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXBUF_THRESH_UNDFLW[3] 03_545 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXBUF_THRESH_UNDFLW[4] 02_546 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXBUF_THRESH_UNDFLW[5] 03_546 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXBUFRESET_TIME[0] 01_101 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXBUFRESET_TIME[1] 00_102 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXBUFRESET_TIME[2] 01_102 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXBUFRESET_TIME[3] 00_103 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXBUFRESET_TIME[4] 01_103 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[0] 02_640 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[1] 03_640 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[2] 02_641 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[3] 03_641 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[4] 02_642 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[5] 03_642 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[6] 02_643 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[7] 03_643 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[8] 02_644 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[9] 03_644 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[10] 02_645 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[11] 03_645 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[12] 02_646 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[13] 03_646 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[14] 02_647 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[15] 03_647 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[16] 02_648 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[17] 03_648 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[18] 02_649 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[19] 03_649 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[20] 02_650 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[21] 03_650 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[22] 02_651 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[23] 03_651 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[24] 02_652 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[25] 03_652 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[26] 02_653 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[27] 03_653 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[28] 02_654 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[29] 03_654 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[30] 02_655 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[31] 03_655 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[32] 02_656 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[33] 03_656 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[34] 02_657 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[35] 03_657 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[36] 02_658 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[37] 03_658 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[38] 02_659 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[39] 03_659 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[40] 02_660 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[41] 03_660 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[42] 02_661 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[43] 03_661 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[44] 02_662 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[45] 03_662 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[46] 02_663 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[47] 03_663 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[48] 02_664 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[49] 03_664 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[50] 02_665 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[51] 03_665 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[52] 02_666 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[53] 03_666 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[54] 02_667 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[55] 03_667 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[56] 02_668 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[57] 03_668 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[58] 02_669 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[59] 03_669 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[60] 02_670 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[61] 03_670 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[62] 02_671 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[63] 03_671 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[64] 02_672 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[65] 03_672 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[66] 02_673 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[67] 03_673 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[68] 02_674 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[69] 03_674 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[70] 02_675 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[71] 03_675 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[72] 02_676 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[73] 03_676 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[74] 02_677 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[75] 03_677 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[76] 02_678 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[77] 03_678 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[78] 02_679 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[79] 03_679 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[80] 02_680 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[81] 03_680 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[82] 02_681 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_FR_RESET_ON_EIDLE[0] 02_638 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_HOLD_DURING_EIDLE[0] 03_637 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_LOCK_CFG[0] 02_632 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_LOCK_CFG[1] 03_632 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_LOCK_CFG[2] 02_633 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_LOCK_CFG[3] 03_633 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_LOCK_CFG[4] 02_634 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_LOCK_CFG[5] 03_634 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_PH_RESET_ON_EIDLE[0] 03_638 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDRFREQRESET_TIME[0] 01_106 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDRFREQRESET_TIME[1] 00_107 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDRFREQRESET_TIME[2] 01_107 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDRFREQRESET_TIME[3] 00_108 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDRFREQRESET_TIME[4] 01_108 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDRPHRESET_TIME[0] 00_109 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDRPHRESET_TIME[1] 01_109 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDRPHRESET_TIME[2] 00_110 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDRPHRESET_TIME[3] 01_110 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDRPHRESET_TIME[4] 00_111 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXDLY_CFG[0] 00_680 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXDLY_CFG[1] 01_680 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXDLY_CFG[2] 00_681 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXDLY_CFG[3] 01_681 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXDLY_CFG[4] 00_682 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXDLY_CFG[5] 01_682 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXDLY_CFG[6] 00_683 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXDLY_CFG[7] 01_683 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXDLY_CFG[8] 00_684 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXDLY_CFG[9] 01_684 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXDLY_CFG[10] 00_685 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXDLY_CFG[11] 01_685 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXDLY_CFG[12] 00_686 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXDLY_CFG[13] 01_686 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXDLY_CFG[14] 00_687 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXDLY_CFG[15] 01_687 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXDLY_LCFG[0] 02_576 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXDLY_LCFG[1] 03_576 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXDLY_LCFG[2] 02_577 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXDLY_LCFG[3] 03_577 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXDLY_LCFG[4] 02_578 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXDLY_LCFG[5] 03_578 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXDLY_LCFG[6] 02_579 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXDLY_LCFG[7] 03_579 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXDLY_LCFG[8] 02_580 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXDLY_TAP_CFG[0] 00_672 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXDLY_TAP_CFG[1] 01_672 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXDLY_TAP_CFG[2] 00_673 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXDLY_TAP_CFG[3] 01_673 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXDLY_TAP_CFG[4] 00_674 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXDLY_TAP_CFG[5] 01_674 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXDLY_TAP_CFG[6] 00_675 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXDLY_TAP_CFG[7] 01_675 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXDLY_TAP_CFG[8] 00_676 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXDLY_TAP_CFG[9] 01_676 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXDLY_TAP_CFG[10] 00_677 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXDLY_TAP_CFG[11] 01_677 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXDLY_TAP_CFG[12] 00_678 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXDLY_TAP_CFG[13] 01_678 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXDLY_TAP_CFG[14] 00_679 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXDLY_TAP_CFG[15] 01_679 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXGEARBOX_EN 01_607 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXISCANRESET_TIME[0] 01_123 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXISCANRESET_TIME[1] 00_124 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXISCANRESET_TIME[2] 01_124 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXISCANRESET_TIME[3] 00_125 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXISCANRESET_TIME[4] 01_125 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPM_BIAS_STARTUP_DISABLE[0] 03_391 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPM_CFG[0] 02_328 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPM_CFG[1] 03_328 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPM_CFG[2] 02_329 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPM_CFG[3] 03_329 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPM_CM_CFG[0] 02_430 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPM_GC_CFG[0] 02_432 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPM_GC_CFG[1] 03_432 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPM_GC_CFG[2] 02_433 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPM_GC_CFG[3] 03_433 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPM_GC_CFG[4] 02_434 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPM_GC_CFG[5] 03_434 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPM_GC_CFG[6] 02_435 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPM_GC_CFG[7] 03_435 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPM_GC_CFG[8] 02_436 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPM_GC_CFG2[0] 03_442 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPM_GC_CFG2[1] 02_443 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPM_GC_CFG2[2] 03_443 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG[0] 00_336 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG[1] 01_336 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG[2] 00_337 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG[3] 01_337 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG[4] 00_338 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG[5] 01_338 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG[6] 00_339 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG[7] 01_339 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG[8] 00_340 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG[9] 01_340 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG[10] 00_341 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG[11] 01_341 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG[12] 00_342 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG[13] 01_342 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG2[0] 02_424 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG2[1] 03_424 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG2[2] 02_425 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG2[3] 03_425 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG2[4] 02_426 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG3[0] 03_389 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG3[1] 02_390 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG3[2] 03_390 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG3[3] 02_391 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HOLD_DURING_EIDLE[0] 00_247 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPM_INCM_CFG[0] 02_439 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPM_IPCM_CFG[0] 03_439 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG[0] 00_344 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG[1] 01_344 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG[2] 00_345 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG[3] 01_345 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG[4] 00_346 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG[5] 01_346 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG[6] 00_347 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG[7] 01_347 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG[8] 00_348 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG[9] 01_348 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG[10] 00_349 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG[11] 01_349 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG[12] 00_350 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG[13] 01_350 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG[14] 00_351 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG[15] 01_351 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG[16] 00_343 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG[17] 01_343 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG2[0] 03_426 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG2[1] 02_427 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG2[2] 03_427 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG2[3] 02_428 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG2[4] 03_428 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPM_OSINT_CFG[0] 02_440 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPM_OSINT_CFG[1] 03_440 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPM_OSINT_CFG[2] 02_441 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPM_CFG1[0] 02_330 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPMRESET_TIME[0] 00_112 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPMRESET_TIME[1] 01_112 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPMRESET_TIME[2] 00_113 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPMRESET_TIME[3] 01_113 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPMRESET_TIME[4] 00_114 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPMRESET_TIME[5] 01_114 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPMRESET_TIME[6] 00_115 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXOOB_CFG[0] 00_144 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXOOB_CFG[1] 01_144 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXOOB_CFG[2] 00_145 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXOOB_CFG[3] 01_145 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXOOB_CFG[4] 00_146 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXOOB_CFG[5] 01_146 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXOOB_CFG[6] 00_147 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXOOB_CLK_CFG.FABRIC 03_129 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXOSCALRESET_TIME[0] 00_187 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXOSCALRESET_TIME[1] 01_187 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXOSCALRESET_TIME[2] 00_188 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXOSCALRESET_TIME[3] 01_188 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXOSCALRESET_TIME[4] 00_189 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXOSCALRESET_TIMEOUT[0] 01_189 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXOSCALRESET_TIMEOUT[1] 00_190 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXOSCALRESET_TIMEOUT[2] 01_190 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXOSCALRESET_TIMEOUT[3] 00_191 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXOSCALRESET_TIMEOUT[4] 01_191 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXOUT_DIV[0] 02_384 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXOUT_DIV[1] 03_384 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXPCSRESET_TIME[0] 01_115 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXPCSRESET_TIME[1] 00_116 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXPCSRESET_TIME[2] 01_116 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXPCSRESET_TIME[3] 00_117 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXPCSRESET_TIME[4] 01_117 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[0] 02_584 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[1] 03_584 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[2] 02_585 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[3] 03_585 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[4] 02_586 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[5] 03_586 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[6] 02_587 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[7] 03_587 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[8] 02_588 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[9] 03_588 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[10] 02_589 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[11] 03_589 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[12] 02_590 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[13] 03_590 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[14] 02_591 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[15] 03_591 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[16] 02_592 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[17] 03_592 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[18] 02_593 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[19] 03_593 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[20] 02_594 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[21] 03_594 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[22] 02_595 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[23] 03_595 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXPH_MONITOR_SEL[0] 00_700 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXPH_MONITOR_SEL[1] 01_700 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXPH_MONITOR_SEL[2] 00_701 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXPH_MONITOR_SEL[3] 01_701 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXPH_MONITOR_SEL[4] 00_702 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[0] 02_600 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[1] 03_600 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[2] 02_601 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[3] 03_601 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[4] 02_602 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[5] 03_602 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[6] 02_603 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[7] 03_603 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[8] 02_604 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[9] 03_604 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[10] 02_605 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[11] 03_605 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[12] 02_606 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[13] 03_606 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[14] 02_607 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[15] 03_607 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[16] 02_608 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[17] 03_608 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[18] 02_609 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[19] 03_609 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[20] 02_610 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[21] 03_610 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[22] 02_611 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[23] 03_611 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXPI_CFG0[0] 03_430 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXPI_CFG0[1] 02_431 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXPI_CFG0[2] 03_431 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXPI_CFG1[0] 02_442 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXPI_CFG2[0] 03_441 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXPMARESET_TIME[0] 00_104 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXPMARESET_TIME[1] 01_104 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXPMARESET_TIME[2] 00_105 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXPMARESET_TIME[3] 01_105 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXPMARESET_TIME[4] 00_106 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXPRBS_ERR_LOOPBACK[0] 00_136 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXSLIDE_AUTO_WAIT[0] 00_520 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXSLIDE_AUTO_WAIT[1] 01_520 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXSLIDE_AUTO_WAIT[2] 00_521 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXSLIDE_AUTO_WAIT[3] 01_521 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXSLIDE_MODE.AUTO 00_519 !01_519 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXSLIDE_MODE.PCS !00_519 01_519 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXSLIDE_MODE.PMA 00_519 01_519 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXSYNC_MULTILANE[0] 00_133 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXSYNC_OVRD[0] 01_135 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXSYNC_SKIP_DA[0] 01_134 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.SAS_MAX_COM[0] 00_171 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.SAS_MAX_COM[1] 01_171 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.SAS_MAX_COM[2] 00_172 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.SAS_MAX_COM[3] 01_172 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.SAS_MAX_COM[4] 00_173 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.SAS_MAX_COM[5] 01_173 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.SAS_MAX_COM[6] 00_174 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.SAS_MIN_COM[0] 01_156 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.SAS_MIN_COM[1] 00_157 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.SAS_MIN_COM[2] 01_157 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.SAS_MIN_COM[3] 00_158 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.SAS_MIN_COM[4] 01_158 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.SAS_MIN_COM[5] 00_159 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.SATA_BURST_SEQ_LEN[0] 00_150 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.SATA_BURST_SEQ_LEN[1] 01_150 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.SATA_BURST_SEQ_LEN[2] 00_151 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.SATA_BURST_SEQ_LEN[3] 01_151 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.SATA_BURST_VAL[0] 01_147 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.SATA_BURST_VAL[1] 00_148 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.SATA_BURST_VAL[2] 01_148 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.SATA_EIDLE_VAL[0] 00_152 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.SATA_EIDLE_VAL[1] 01_152 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.SATA_EIDLE_VAL[2] 00_153 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.SATA_MAX_BURST[0] 00_168 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.SATA_MAX_BURST[1] 01_168 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.SATA_MAX_BURST[2] 00_169 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.SATA_MAX_BURST[3] 01_169 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.SATA_MAX_BURST[4] 00_170 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.SATA_MAX_BURST[5] 01_170 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.SATA_MAX_INIT[0] 00_176 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.SATA_MAX_INIT[1] 01_176 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.SATA_MAX_INIT[2] 00_177 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.SATA_MAX_INIT[3] 01_177 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.SATA_MAX_INIT[4] 00_178 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.SATA_MAX_INIT[5] 01_178 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.SATA_MAX_WAKE[0] 00_179 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.SATA_MAX_WAKE[1] 01_179 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.SATA_MAX_WAKE[2] 00_180 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.SATA_MAX_WAKE[3] 01_180 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.SATA_MAX_WAKE[4] 00_181 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.SATA_MAX_WAKE[5] 01_181 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.SATA_MIN_BURST[0] 01_153 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.SATA_MIN_BURST[1] 00_154 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.SATA_MIN_BURST[2] 01_154 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.SATA_MIN_BURST[3] 00_155 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.SATA_MIN_BURST[4] 01_155 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.SATA_MIN_BURST[5] 00_156 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.SATA_MIN_INIT[0] 00_160 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.SATA_MIN_INIT[1] 01_160 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.SATA_MIN_INIT[2] 00_161 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.SATA_MIN_INIT[3] 01_161 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.SATA_MIN_INIT[4] 00_162 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.SATA_MIN_INIT[5] 01_162 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.SATA_MIN_WAKE[0] 00_163 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.SATA_MIN_WAKE[1] 01_163 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.SATA_MIN_WAKE[2] 00_164 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.SATA_MIN_WAKE[3] 01_164 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.SATA_MIN_WAKE[4] 00_165 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.SATA_MIN_WAKE[5] 01_165 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.SATA_PLL_CFG.VCO_1500MHZ 02_55 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.SATA_PLL_CFG.VCO_750MHZ 03_55 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.SHOW_REALIGN_COMMA 01_522 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TERM_RCAL_CFG[0] 02_136 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TERM_RCAL_CFG[1] 03_136 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TERM_RCAL_CFG[2] 02_137 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TERM_RCAL_CFG[3] 03_137 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TERM_RCAL_CFG[4] 02_138 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TERM_RCAL_CFG[5] 03_138 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TERM_RCAL_CFG[6] 02_139 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TERM_RCAL_CFG[7] 03_139 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TERM_RCAL_CFG[8] 02_140 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TERM_RCAL_CFG[9] 03_140 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TERM_RCAL_CFG[10] 02_141 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TERM_RCAL_CFG[11] 03_141 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TERM_RCAL_CFG[12] 02_142 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TERM_RCAL_CFG[13] 03_142 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TERM_RCAL_CFG[14] 02_143 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TERM_RCAL_OVRD[0] 03_150 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TERM_RCAL_OVRD[1] 02_151 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TERM_RCAL_OVRD[2] 03_151 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TRANS_TIME_RATE[0] 00_192 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TRANS_TIME_RATE[1] 01_192 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TRANS_TIME_RATE[2] 00_193 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TRANS_TIME_RATE[3] 01_193 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TRANS_TIME_RATE[4] 00_194 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TRANS_TIME_RATE[5] 01_194 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TRANS_TIME_RATE[6] 00_195 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TRANS_TIME_RATE[7] 01_195 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[0] 02_504 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[1] 03_504 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[2] 02_505 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[3] 03_505 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[4] 02_506 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[5] 03_506 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[6] 02_507 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[7] 03_507 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[8] 02_508 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[9] 03_508 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[10] 02_509 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[11] 03_509 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[12] 02_510 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[13] 03_510 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[14] 02_511 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[15] 03_511 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[16] 02_512 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[17] 03_512 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[18] 02_513 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[19] 03_513 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[20] 02_514 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[21] 03_514 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[22] 02_515 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[23] 03_515 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[24] 02_516 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[25] 03_516 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[26] 02_517 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[27] 03_517 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[28] 02_518 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[29] 03_518 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[30] 02_519 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[31] 03_519 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_CLKMUX_EN[0] 03_128 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_DATA_WIDTH[0] 02_152 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_DATA_WIDTH[1] 03_152 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_DATA_WIDTH[2] 02_153 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_DRIVE_MODE.PIPE 00_200 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_EIDLE_ASSERT_DELAY[0] 00_203 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_EIDLE_ASSERT_DELAY[1] 01_203 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_EIDLE_ASSERT_DELAY[2] 00_204 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_EIDLE_DEASSERT_DELAY[0] 01_204 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_EIDLE_DEASSERT_DELAY[1] 00_205 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_EIDLE_DEASSERT_DELAY[2] 01_205 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_LOOPBACK_DRIVE_HIZ 01_202 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_MAINCURSOR_SEL[0] 03_289 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_0[0] 02_232 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_0[1] 03_232 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_0[2] 02_233 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_0[3] 03_233 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_0[4] 02_234 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_0[5] 03_234 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_0[6] 02_235 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_1[0] 02_236 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_1[1] 03_236 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_1[2] 02_237 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_1[3] 03_237 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_1[4] 02_238 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_1[5] 03_238 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_1[6] 02_239 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_2[0] 02_240 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_2[1] 03_240 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_2[2] 02_241 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_2[3] 03_241 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_2[4] 02_242 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_2[5] 03_242 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_2[6] 02_243 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_3[0] 02_244 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_3[1] 03_244 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_3[2] 02_245 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_3[3] 03_245 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_3[4] 02_246 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_3[5] 03_246 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_3[6] 02_247 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_4[0] 02_248 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_4[1] 03_248 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_4[2] 02_249 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_4[3] 03_249 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_4[4] 02_250 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_4[5] 03_250 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_4[6] 02_251 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_0[0] 02_252 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_0[1] 03_252 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_0[2] 02_253 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_0[3] 03_253 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_0[4] 02_254 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_0[5] 03_254 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_0[6] 02_255 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_1[0] 02_256 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_1[1] 03_256 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_1[2] 02_257 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_1[3] 03_257 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_1[4] 02_258 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_1[5] 03_258 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_1[6] 02_259 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_2[0] 02_260 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_2[1] 03_260 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_2[2] 02_261 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_2[3] 03_261 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_2[4] 02_262 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_2[5] 03_262 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_2[6] 02_263 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_3[0] 02_264 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_3[1] 03_264 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_3[2] 02_265 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_3[3] 03_265 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_3[4] 02_266 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_3[5] 03_266 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_3[6] 02_267 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_4[0] 02_268 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_4[1] 03_268 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_4[2] 02_269 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_4[3] 03_269 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_4[4] 02_270 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_4[5] 03_270 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_4[6] 02_271 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_PREDRIVER_MODE[0] 00_206 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_RXDETECT_CFG[0] 02_296 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_RXDETECT_CFG[1] 03_296 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_RXDETECT_CFG[2] 02_297 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_RXDETECT_CFG[3] 03_297 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_RXDETECT_CFG[4] 02_298 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_RXDETECT_CFG[5] 03_298 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_RXDETECT_CFG[6] 02_299 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_RXDETECT_CFG[7] 03_299 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_RXDETECT_CFG[8] 02_300 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_RXDETECT_CFG[9] 03_300 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_RXDETECT_CFG[10] 02_301 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_RXDETECT_CFG[11] 03_301 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_RXDETECT_CFG[12] 02_302 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_RXDETECT_CFG[13] 03_302 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_RXDETECT_REF[0] 02_292 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_RXDETECT_REF[1] 03_292 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_RXDETECT_REF[2] 02_293 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_XCLK_SEL.TXUSR 03_11 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_CLK25_DIV[0] 02_144 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_CLK25_DIV[1] 03_144 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_CLK25_DIV[2] 02_145 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_CLK25_DIV[3] 03_145 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_CLK25_DIV[4] 02_146 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_DEEMPH0[0] 02_272 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_DEEMPH0[1] 03_272 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_DEEMPH0[2] 02_273 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_DEEMPH0[3] 03_273 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_DEEMPH0[4] 02_274 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_DEEMPH0[5] 03_274 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_DEEMPH1[0] 02_276 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_DEEMPH1[1] 03_276 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_DEEMPH1[2] 02_277 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_DEEMPH1[3] 03_277 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_DEEMPH1[4] 02_278 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_DEEMPH1[5] 03_278 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXBUF_EN 00_231 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXBUF_RESET_ON_RATE_CHANGE 01_231 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXDLY_CFG[0] 02_80 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXDLY_CFG[1] 03_80 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXDLY_CFG[2] 02_81 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXDLY_CFG[3] 03_81 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXDLY_CFG[4] 02_82 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXDLY_CFG[5] 03_82 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXDLY_CFG[6] 02_83 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXDLY_CFG[7] 03_83 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXDLY_CFG[8] 02_84 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXDLY_CFG[9] 03_84 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXDLY_CFG[10] 02_85 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXDLY_CFG[11] 03_85 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXDLY_CFG[12] 02_86 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXDLY_CFG[13] 03_86 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXDLY_CFG[14] 02_87 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXDLY_CFG[15] 03_87 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXDLY_LCFG[0] 02_568 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXDLY_LCFG[1] 03_568 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXDLY_LCFG[2] 02_569 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXDLY_LCFG[3] 03_569 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXDLY_LCFG[4] 02_570 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXDLY_LCFG[5] 03_570 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXDLY_LCFG[6] 02_571 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXDLY_LCFG[7] 03_571 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXDLY_LCFG[8] 02_572 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXDLY_TAP_CFG[0] 02_88 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXDLY_TAP_CFG[1] 03_88 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXDLY_TAP_CFG[2] 02_89 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXDLY_TAP_CFG[3] 03_89 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXDLY_TAP_CFG[4] 02_90 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXDLY_TAP_CFG[5] 03_90 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXDLY_TAP_CFG[6] 02_91 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXDLY_TAP_CFG[7] 03_91 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXDLY_TAP_CFG[8] 02_92 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXDLY_TAP_CFG[9] 03_92 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXDLY_TAP_CFG[10] 02_93 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXDLY_TAP_CFG[11] 03_93 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXDLY_TAP_CFG[12] 02_94 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXDLY_TAP_CFG[13] 03_94 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXDLY_TAP_CFG[14] 02_95 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXDLY_TAP_CFG[15] 03_95 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXGEARBOX_EN 01_226 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXOOB_CFG[0] 03_20 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXOUT_DIV[0] 02_386 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXOUT_DIV[1] 03_386 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPCSRESET_TIME[0] 01_130 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPCSRESET_TIME[1] 00_131 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPCSRESET_TIME[2] 01_131 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPCSRESET_TIME[3] 00_132 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPCSRESET_TIME[4] 01_132 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPH_CFG[0] 02_96 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPH_CFG[1] 03_96 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPH_CFG[2] 02_97 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPH_CFG[3] 03_97 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPH_CFG[4] 02_98 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPH_CFG[5] 03_98 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPH_CFG[6] 02_99 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPH_CFG[7] 03_99 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPH_CFG[8] 02_100 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPH_CFG[9] 03_100 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPH_CFG[10] 02_101 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPH_CFG[11] 03_101 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPH_CFG[12] 02_102 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPH_CFG[13] 03_102 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPH_CFG[14] 02_103 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPH_CFG[15] 03_103 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPH_MONITOR_SEL[0] 02_108 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPH_MONITOR_SEL[1] 03_108 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPH_MONITOR_SEL[2] 02_109 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPH_MONITOR_SEL[3] 03_109 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPH_MONITOR_SEL[4] 02_110 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[0] 02_64 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[1] 03_64 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[2] 02_65 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[3] 03_65 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[4] 02_66 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[5] 03_66 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[6] 02_67 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[7] 03_67 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[8] 02_68 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[9] 03_68 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[10] 02_69 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[11] 03_69 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[12] 02_70 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[13] 03_70 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[14] 02_71 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[15] 03_71 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[16] 02_72 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[17] 03_72 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[18] 02_73 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[19] 03_73 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[20] 02_74 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[21] 03_74 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[22] 02_75 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[23] 03_75 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPI_GREY_SEL[0] 03_498 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPI_INVSTROBE_SEL[0] 02_498 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPI_PPM_CFG[0] 02_488 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPI_PPM_CFG[1] 03_488 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPI_PPM_CFG[2] 02_489 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPI_PPM_CFG[3] 03_489 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPI_PPM_CFG[4] 02_490 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPI_PPM_CFG[5] 03_490 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPI_PPM_CFG[6] 02_491 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPI_PPM_CFG[7] 03_491 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPI_PPMCLK_SEL.TXUSRCLK2 03_497 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPI_SYNFREQ_PPM[0] 02_496 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPI_SYNFREQ_PPM[1] 03_496 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPI_SYNFREQ_PPM[2] 02_497 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPI_CFG0[0] 02_40 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPI_CFG0[1] 03_40 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPI_CFG1[0] 02_41 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPI_CFG1[1] 03_41 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPI_CFG2[0] 02_42 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPI_CFG2[1] 03_42 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPI_CFG3[0] 02_43 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPI_CFG4[0] 03_43 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPI_CFG5[0] 02_44 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPI_CFG5[1] 03_44 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPI_CFG5[2] 02_45 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPMARESET_TIME[0] 00_128 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPMARESET_TIME[1] 01_128 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPMARESET_TIME[2] 00_129 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPMARESET_TIME[3] 01_129 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPMARESET_TIME[4] 00_130 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXSYNC_MULTILANE[0] 01_133 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXSYNC_OVRD[0] 00_135 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXSYNC_SKIP_DA[0] 00_134 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.UCODEER_CLR[0] 01_00 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.USE_PCS_CLK_PHASE_SEL[0] 02_463 diff --git a/artix7/segbits_gtp_channel_2_mid_right.origin_info.db b/artix7/segbits_gtp_channel_2_mid_right.origin_info.db index 0b49db3..7635696 100644 --- a/artix7/segbits_gtp_channel_2_mid_right.origin_info.db +++ b/artix7/segbits_gtp_channel_2_mid_right.origin_info.db @@ -1,1627 +1,1627 @@ -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ACJTAG_DEBUG_MODE[0] origin:064-gtp-channel-conf 00_07 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ACJTAG_MODE[0] origin:064-gtp-channel-conf 01_06 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ACJTAG_RESET[0] origin:064-gtp-channel-conf 01_07 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ADAPT_CFG0[0] origin:064-gtp-channel-conf 02_464 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ADAPT_CFG0[1] origin:064-gtp-channel-conf 03_464 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ADAPT_CFG0[2] origin:064-gtp-channel-conf 02_465 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ADAPT_CFG0[3] origin:064-gtp-channel-conf 03_465 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ADAPT_CFG0[4] origin:064-gtp-channel-conf 02_466 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ADAPT_CFG0[5] origin:064-gtp-channel-conf 03_466 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ADAPT_CFG0[6] origin:064-gtp-channel-conf 02_467 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ADAPT_CFG0[7] origin:064-gtp-channel-conf 03_467 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ADAPT_CFG0[8] origin:064-gtp-channel-conf 02_468 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ADAPT_CFG0[9] origin:064-gtp-channel-conf 03_468 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ADAPT_CFG0[10] origin:064-gtp-channel-conf 02_469 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ADAPT_CFG0[11] origin:064-gtp-channel-conf 03_469 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ADAPT_CFG0[12] origin:064-gtp-channel-conf 02_470 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ADAPT_CFG0[13] origin:064-gtp-channel-conf 03_470 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ADAPT_CFG0[14] origin:064-gtp-channel-conf 02_471 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ADAPT_CFG0[15] origin:064-gtp-channel-conf 03_471 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ADAPT_CFG0[16] origin:064-gtp-channel-conf 02_472 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ADAPT_CFG0[17] origin:064-gtp-channel-conf 03_472 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ADAPT_CFG0[18] origin:064-gtp-channel-conf 02_473 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ADAPT_CFG0[19] origin:064-gtp-channel-conf 03_473 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ALIGN_COMMA_DOUBLE origin:064-gtp-channel-conf 00_522 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ALIGN_COMMA_ENABLE[0] origin:064-gtp-channel-conf 00_496 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ALIGN_COMMA_ENABLE[1] origin:064-gtp-channel-conf 01_496 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ALIGN_COMMA_ENABLE[2] origin:064-gtp-channel-conf 00_497 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ALIGN_COMMA_ENABLE[3] origin:064-gtp-channel-conf 01_497 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ALIGN_COMMA_ENABLE[4] origin:064-gtp-channel-conf 00_498 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ALIGN_COMMA_ENABLE[5] origin:064-gtp-channel-conf 01_498 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ALIGN_COMMA_ENABLE[6] origin:064-gtp-channel-conf 00_499 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ALIGN_COMMA_ENABLE[7] origin:064-gtp-channel-conf 01_499 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ALIGN_COMMA_ENABLE[8] origin:064-gtp-channel-conf 00_500 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ALIGN_COMMA_ENABLE[9] origin:064-gtp-channel-conf 01_500 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ALIGN_COMMA_WORD[0] origin:064-gtp-channel-conf 01_526 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ALIGN_COMMA_WORD[1] origin:064-gtp-channel-conf 00_527 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ALIGN_MCOMMA_DET origin:064-gtp-channel-conf 00_523 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ALIGN_MCOMMA_VALUE[0] origin:064-gtp-channel-conf 00_504 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ALIGN_MCOMMA_VALUE[1] origin:064-gtp-channel-conf 01_504 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ALIGN_MCOMMA_VALUE[2] origin:064-gtp-channel-conf 00_505 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ALIGN_MCOMMA_VALUE[3] origin:064-gtp-channel-conf 01_505 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ALIGN_MCOMMA_VALUE[4] origin:064-gtp-channel-conf 00_506 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ALIGN_MCOMMA_VALUE[5] origin:064-gtp-channel-conf 01_506 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ALIGN_MCOMMA_VALUE[6] origin:064-gtp-channel-conf 00_507 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ALIGN_MCOMMA_VALUE[7] origin:064-gtp-channel-conf 01_507 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ALIGN_MCOMMA_VALUE[8] origin:064-gtp-channel-conf 00_508 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ALIGN_MCOMMA_VALUE[9] origin:064-gtp-channel-conf 01_508 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ALIGN_PCOMMA_DET origin:064-gtp-channel-conf 01_523 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ALIGN_PCOMMA_VALUE[0] origin:064-gtp-channel-conf 00_512 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ALIGN_PCOMMA_VALUE[1] origin:064-gtp-channel-conf 01_512 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ALIGN_PCOMMA_VALUE[2] origin:064-gtp-channel-conf 00_513 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ALIGN_PCOMMA_VALUE[3] origin:064-gtp-channel-conf 01_513 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ALIGN_PCOMMA_VALUE[4] origin:064-gtp-channel-conf 00_514 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ALIGN_PCOMMA_VALUE[5] origin:064-gtp-channel-conf 01_514 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ALIGN_PCOMMA_VALUE[6] origin:064-gtp-channel-conf 00_515 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ALIGN_PCOMMA_VALUE[7] origin:064-gtp-channel-conf 01_515 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ALIGN_PCOMMA_VALUE[8] origin:064-gtp-channel-conf 00_516 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ALIGN_PCOMMA_VALUE[9] origin:064-gtp-channel-conf 01_516 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CBCC_DATA_SOURCE_SEL.DECODED origin:064-gtp-channel-conf 01_661 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CFOK_CFG[0] origin:064-gtp-channel-conf 02_392 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CFOK_CFG[1] origin:064-gtp-channel-conf 03_392 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CFOK_CFG[2] origin:064-gtp-channel-conf 02_393 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CFOK_CFG[3] origin:064-gtp-channel-conf 03_393 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CFOK_CFG[4] origin:064-gtp-channel-conf 02_394 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CFOK_CFG[5] origin:064-gtp-channel-conf 03_394 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CFOK_CFG[6] origin:064-gtp-channel-conf 02_395 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CFOK_CFG[7] origin:064-gtp-channel-conf 03_395 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CFOK_CFG[8] origin:064-gtp-channel-conf 02_396 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CFOK_CFG[9] origin:064-gtp-channel-conf 03_396 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CFOK_CFG[10] origin:064-gtp-channel-conf 02_397 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CFOK_CFG[11] origin:064-gtp-channel-conf 03_397 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CFOK_CFG[12] origin:064-gtp-channel-conf 02_398 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CFOK_CFG[13] origin:064-gtp-channel-conf 03_398 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CFOK_CFG[14] origin:064-gtp-channel-conf 02_399 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CFOK_CFG[15] origin:064-gtp-channel-conf 03_399 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CFOK_CFG[16] origin:064-gtp-channel-conf 02_400 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CFOK_CFG[17] origin:064-gtp-channel-conf 03_400 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CFOK_CFG[18] origin:064-gtp-channel-conf 02_401 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CFOK_CFG[19] origin:064-gtp-channel-conf 03_401 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CFOK_CFG[20] origin:064-gtp-channel-conf 02_402 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CFOK_CFG[21] origin:064-gtp-channel-conf 03_402 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CFOK_CFG[22] origin:064-gtp-channel-conf 02_403 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CFOK_CFG[23] origin:064-gtp-channel-conf 03_403 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CFOK_CFG[24] origin:064-gtp-channel-conf 02_404 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CFOK_CFG[25] origin:064-gtp-channel-conf 03_404 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CFOK_CFG[26] origin:064-gtp-channel-conf 02_405 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CFOK_CFG[27] origin:064-gtp-channel-conf 03_405 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CFOK_CFG[28] origin:064-gtp-channel-conf 02_406 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CFOK_CFG[29] origin:064-gtp-channel-conf 03_406 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CFOK_CFG[30] origin:064-gtp-channel-conf 02_407 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CFOK_CFG[31] origin:064-gtp-channel-conf 03_407 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CFOK_CFG[32] origin:064-gtp-channel-conf 02_408 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CFOK_CFG[33] origin:064-gtp-channel-conf 03_408 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CFOK_CFG[34] origin:064-gtp-channel-conf 02_409 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CFOK_CFG[35] origin:064-gtp-channel-conf 03_409 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CFOK_CFG[36] origin:064-gtp-channel-conf 02_410 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CFOK_CFG[37] origin:064-gtp-channel-conf 03_410 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CFOK_CFG[38] origin:064-gtp-channel-conf 02_411 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CFOK_CFG[39] origin:064-gtp-channel-conf 03_411 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CFOK_CFG[40] origin:064-gtp-channel-conf 02_412 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CFOK_CFG[41] origin:064-gtp-channel-conf 03_412 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CFOK_CFG[42] origin:064-gtp-channel-conf 02_413 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CFOK_CFG2[0] origin:064-gtp-channel-conf 02_459 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CFOK_CFG2[1] origin:064-gtp-channel-conf 03_459 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CFOK_CFG2[2] origin:064-gtp-channel-conf 02_460 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CFOK_CFG2[3] origin:064-gtp-channel-conf 03_460 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CFOK_CFG2[4] origin:064-gtp-channel-conf 02_461 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CFOK_CFG2[5] origin:064-gtp-channel-conf 03_461 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CFOK_CFG2[6] origin:064-gtp-channel-conf 02_462 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CFOK_CFG3[0] origin:064-gtp-channel-conf 02_416 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CFOK_CFG3[1] origin:064-gtp-channel-conf 03_416 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CFOK_CFG3[2] origin:064-gtp-channel-conf 02_417 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CFOK_CFG3[3] origin:064-gtp-channel-conf 03_417 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CFOK_CFG3[4] origin:064-gtp-channel-conf 02_418 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CFOK_CFG3[5] origin:064-gtp-channel-conf 03_418 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CFOK_CFG3[6] origin:064-gtp-channel-conf 02_419 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CFOK_CFG4[0] origin:064-gtp-channel-conf 03_438 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CFOK_CFG5[0] origin:064-gtp-channel-conf 02_429 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CFOK_CFG5[1] origin:064-gtp-channel-conf 03_429 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CFOK_CFG6[0] origin:064-gtp-channel-conf 03_436 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CFOK_CFG6[1] origin:064-gtp-channel-conf 02_437 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CFOK_CFG6[2] origin:064-gtp-channel-conf 03_437 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CFOK_CFG6[3] origin:064-gtp-channel-conf 02_438 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_KEEP_ALIGN origin:064-gtp-channel-conf 01_631 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_MAX_SKEW[0] origin:064-gtp-channel-conf 00_670 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_MAX_SKEW[1] origin:064-gtp-channel-conf 01_670 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_MAX_SKEW[2] origin:064-gtp-channel-conf 00_671 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_MAX_SKEW[3] origin:064-gtp-channel-conf 01_671 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_1[0] origin:064-gtp-channel-conf 00_608 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_1[1] origin:064-gtp-channel-conf 01_608 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_1[2] origin:064-gtp-channel-conf 00_609 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_1[3] origin:064-gtp-channel-conf 01_609 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_1[4] origin:064-gtp-channel-conf 00_610 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_1[5] origin:064-gtp-channel-conf 01_610 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_1[6] origin:064-gtp-channel-conf 00_611 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_1[7] origin:064-gtp-channel-conf 01_611 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_1[8] origin:064-gtp-channel-conf 00_612 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_1[9] origin:064-gtp-channel-conf 01_612 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_2[0] origin:064-gtp-channel-conf 00_616 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_2[1] origin:064-gtp-channel-conf 01_616 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_2[2] origin:064-gtp-channel-conf 00_617 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_2[3] origin:064-gtp-channel-conf 01_617 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_2[4] origin:064-gtp-channel-conf 00_618 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_2[5] origin:064-gtp-channel-conf 01_618 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_2[6] origin:064-gtp-channel-conf 00_619 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_2[7] origin:064-gtp-channel-conf 01_619 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_2[8] origin:064-gtp-channel-conf 00_620 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_2[9] origin:064-gtp-channel-conf 01_620 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_3[0] origin:064-gtp-channel-conf 00_624 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_3[1] origin:064-gtp-channel-conf 01_624 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_3[2] origin:064-gtp-channel-conf 00_625 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_3[3] origin:064-gtp-channel-conf 01_625 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_3[4] origin:064-gtp-channel-conf 00_626 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_3[5] origin:064-gtp-channel-conf 01_626 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_3[6] origin:064-gtp-channel-conf 00_627 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_3[7] origin:064-gtp-channel-conf 01_627 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_3[8] origin:064-gtp-channel-conf 00_628 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_3[9] origin:064-gtp-channel-conf 01_628 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_4[0] origin:064-gtp-channel-conf 00_632 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_4[1] origin:064-gtp-channel-conf 01_632 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_4[2] origin:064-gtp-channel-conf 00_633 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_4[3] origin:064-gtp-channel-conf 01_633 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_4[4] origin:064-gtp-channel-conf 00_634 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_4[5] origin:064-gtp-channel-conf 01_634 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_4[6] origin:064-gtp-channel-conf 00_635 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_4[7] origin:064-gtp-channel-conf 01_635 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_4[8] origin:064-gtp-channel-conf 00_636 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_4[9] origin:064-gtp-channel-conf 01_636 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_ENABLE[0] origin:064-gtp-channel-conf 00_614 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_ENABLE[1] origin:064-gtp-channel-conf 01_614 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_ENABLE[2] origin:064-gtp-channel-conf 00_615 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_ENABLE[3] origin:064-gtp-channel-conf 01_615 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_1[0] origin:064-gtp-channel-conf 00_640 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_1[1] origin:064-gtp-channel-conf 01_640 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_1[2] origin:064-gtp-channel-conf 00_641 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_1[3] origin:064-gtp-channel-conf 01_641 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_1[4] origin:064-gtp-channel-conf 00_642 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_1[5] origin:064-gtp-channel-conf 01_642 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_1[6] origin:064-gtp-channel-conf 00_643 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_1[7] origin:064-gtp-channel-conf 01_643 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_1[8] origin:064-gtp-channel-conf 00_644 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_1[9] origin:064-gtp-channel-conf 01_644 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_2[0] origin:064-gtp-channel-conf 00_648 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_2[1] origin:064-gtp-channel-conf 01_648 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_2[2] origin:064-gtp-channel-conf 00_649 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_2[3] origin:064-gtp-channel-conf 01_649 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_2[4] origin:064-gtp-channel-conf 00_650 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_2[5] origin:064-gtp-channel-conf 01_650 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_2[6] origin:064-gtp-channel-conf 00_651 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_2[7] origin:064-gtp-channel-conf 01_651 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_2[8] origin:064-gtp-channel-conf 00_652 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_2[9] origin:064-gtp-channel-conf 01_652 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_3[0] origin:064-gtp-channel-conf 00_656 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_3[1] origin:064-gtp-channel-conf 01_656 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_3[2] origin:064-gtp-channel-conf 00_657 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_3[3] origin:064-gtp-channel-conf 01_657 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_3[4] origin:064-gtp-channel-conf 00_658 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_3[5] origin:064-gtp-channel-conf 01_658 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_3[6] origin:064-gtp-channel-conf 00_659 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_3[7] origin:064-gtp-channel-conf 01_659 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_3[8] origin:064-gtp-channel-conf 00_660 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_3[9] origin:064-gtp-channel-conf 01_660 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_4[0] origin:064-gtp-channel-conf 00_664 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_4[1] origin:064-gtp-channel-conf 01_664 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_4[2] origin:064-gtp-channel-conf 00_665 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_4[3] origin:064-gtp-channel-conf 01_665 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_4[4] origin:064-gtp-channel-conf 00_666 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_4[5] origin:064-gtp-channel-conf 01_666 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_4[6] origin:064-gtp-channel-conf 00_667 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_4[7] origin:064-gtp-channel-conf 01_667 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_4[8] origin:064-gtp-channel-conf 00_668 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_4[9] origin:064-gtp-channel-conf 01_668 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_ENABLE[0] origin:064-gtp-channel-conf 00_646 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_ENABLE[1] origin:064-gtp-channel-conf 01_646 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_ENABLE[2] origin:064-gtp-channel-conf 00_647 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_ENABLE[3] origin:064-gtp-channel-conf 01_647 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_USE origin:064-gtp-channel-conf 01_645 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_LEN[0] origin:064-gtp-channel-conf 00_623 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_LEN[1] origin:064-gtp-channel-conf 01_623 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COMMON_SWING[0] origin:064-gtp-channel-conf 03_311 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_KEEP_IDLE origin:064-gtp-channel-conf 00_591 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_MAX_LAT[0] origin:064-gtp-channel-conf 00_557 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_MAX_LAT[1] origin:064-gtp-channel-conf 01_557 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_MAX_LAT[2] origin:064-gtp-channel-conf 00_558 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_MAX_LAT[3] origin:064-gtp-channel-conf 01_558 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_MAX_LAT[4] origin:064-gtp-channel-conf 00_559 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_MAX_LAT[5] origin:064-gtp-channel-conf 01_559 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_MIN_LAT[0] origin:064-gtp-channel-conf 00_565 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_MIN_LAT[1] origin:064-gtp-channel-conf 01_565 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_MIN_LAT[2] origin:064-gtp-channel-conf 00_566 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_MIN_LAT[3] origin:064-gtp-channel-conf 01_566 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_MIN_LAT[4] origin:064-gtp-channel-conf 00_567 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_MIN_LAT[5] origin:064-gtp-channel-conf 01_567 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_PRECEDENCE origin:064-gtp-channel-conf 00_590 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_REPEAT_WAIT[0] origin:064-gtp-channel-conf 00_573 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_REPEAT_WAIT[1] origin:064-gtp-channel-conf 01_573 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_REPEAT_WAIT[2] origin:064-gtp-channel-conf 00_574 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_REPEAT_WAIT[3] origin:064-gtp-channel-conf 01_574 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_REPEAT_WAIT[4] origin:064-gtp-channel-conf 00_575 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_1[0] origin:064-gtp-channel-conf 00_544 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_1[1] origin:064-gtp-channel-conf 01_544 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_1[2] origin:064-gtp-channel-conf 00_545 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_1[3] origin:064-gtp-channel-conf 01_545 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_1[4] origin:064-gtp-channel-conf 00_546 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_1[5] origin:064-gtp-channel-conf 01_546 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_1[6] origin:064-gtp-channel-conf 00_547 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_1[7] origin:064-gtp-channel-conf 01_547 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_1[8] origin:064-gtp-channel-conf 00_548 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_1[9] origin:064-gtp-channel-conf 01_548 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_2[0] origin:064-gtp-channel-conf 00_552 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_2[1] origin:064-gtp-channel-conf 01_552 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_2[2] origin:064-gtp-channel-conf 00_553 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_2[3] origin:064-gtp-channel-conf 01_553 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_2[4] origin:064-gtp-channel-conf 00_554 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_2[5] origin:064-gtp-channel-conf 01_554 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_2[6] origin:064-gtp-channel-conf 00_555 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_2[7] origin:064-gtp-channel-conf 01_555 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_2[8] origin:064-gtp-channel-conf 00_556 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_2[9] origin:064-gtp-channel-conf 01_556 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_3[0] origin:064-gtp-channel-conf 00_560 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_3[1] origin:064-gtp-channel-conf 01_560 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_3[2] origin:064-gtp-channel-conf 00_561 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_3[3] origin:064-gtp-channel-conf 01_561 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_3[4] origin:064-gtp-channel-conf 00_562 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_3[5] origin:064-gtp-channel-conf 01_562 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_3[6] origin:064-gtp-channel-conf 00_563 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_3[7] origin:064-gtp-channel-conf 01_563 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_3[8] origin:064-gtp-channel-conf 00_564 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_3[9] origin:064-gtp-channel-conf 01_564 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_4[0] origin:064-gtp-channel-conf 00_568 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_4[1] origin:064-gtp-channel-conf 01_568 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_4[2] origin:064-gtp-channel-conf 00_569 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_4[3] origin:064-gtp-channel-conf 01_569 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_4[4] origin:064-gtp-channel-conf 00_570 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_4[5] origin:064-gtp-channel-conf 01_570 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_4[6] origin:064-gtp-channel-conf 00_571 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_4[7] origin:064-gtp-channel-conf 01_571 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_4[8] origin:064-gtp-channel-conf 00_572 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_4[9] origin:064-gtp-channel-conf 01_572 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_ENABLE[0] origin:064-gtp-channel-conf 00_549 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_ENABLE[1] origin:064-gtp-channel-conf 01_549 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_ENABLE[2] origin:064-gtp-channel-conf 00_550 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_ENABLE[3] origin:064-gtp-channel-conf 01_550 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_1[0] origin:064-gtp-channel-conf 00_576 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_1[1] origin:064-gtp-channel-conf 01_576 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_1[2] origin:064-gtp-channel-conf 00_577 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_1[3] origin:064-gtp-channel-conf 01_577 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_1[4] origin:064-gtp-channel-conf 00_578 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_1[5] origin:064-gtp-channel-conf 01_578 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_1[6] origin:064-gtp-channel-conf 00_579 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_1[7] origin:064-gtp-channel-conf 01_579 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_1[8] origin:064-gtp-channel-conf 00_580 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_1[9] origin:064-gtp-channel-conf 01_580 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_2[0] origin:064-gtp-channel-conf 00_584 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_2[1] origin:064-gtp-channel-conf 01_584 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_2[2] origin:064-gtp-channel-conf 00_585 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_2[3] origin:064-gtp-channel-conf 01_585 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_2[4] origin:064-gtp-channel-conf 00_586 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_2[5] origin:064-gtp-channel-conf 01_586 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_2[6] origin:064-gtp-channel-conf 00_587 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_2[7] origin:064-gtp-channel-conf 01_587 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_2[8] origin:064-gtp-channel-conf 00_588 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_2[9] origin:064-gtp-channel-conf 01_588 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_3[0] origin:064-gtp-channel-conf 00_592 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_3[1] origin:064-gtp-channel-conf 01_592 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_3[2] origin:064-gtp-channel-conf 00_593 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_3[3] origin:064-gtp-channel-conf 01_593 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_3[4] origin:064-gtp-channel-conf 00_594 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_3[5] origin:064-gtp-channel-conf 01_594 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_3[6] origin:064-gtp-channel-conf 00_595 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_3[7] origin:064-gtp-channel-conf 01_595 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_3[8] origin:064-gtp-channel-conf 00_596 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_3[9] origin:064-gtp-channel-conf 01_596 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_4[0] origin:064-gtp-channel-conf 00_600 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_4[1] origin:064-gtp-channel-conf 01_600 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_4[2] origin:064-gtp-channel-conf 00_601 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_4[3] origin:064-gtp-channel-conf 01_601 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_4[4] origin:064-gtp-channel-conf 00_602 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_4[5] origin:064-gtp-channel-conf 01_602 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_4[6] origin:064-gtp-channel-conf 00_603 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_4[7] origin:064-gtp-channel-conf 01_603 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_4[8] origin:064-gtp-channel-conf 00_604 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_4[9] origin:064-gtp-channel-conf 01_604 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_ENABLE[0] origin:064-gtp-channel-conf 00_581 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_ENABLE[1] origin:064-gtp-channel-conf 01_581 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_ENABLE[2] origin:064-gtp-channel-conf 00_582 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_ENABLE[3] origin:064-gtp-channel-conf 01_582 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_USE origin:064-gtp-channel-conf 00_583 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_LEN[0] origin:064-gtp-channel-conf 00_589 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_COR_SEQ_LEN[1] origin:064-gtp-channel-conf 01_589 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.CLK_CORRECT_USE origin:064-gtp-channel-conf 00_551 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.DEC_MCOMMA_DETECT origin:064-gtp-channel-conf 01_494 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.DEC_PCOMMA_DETECT origin:064-gtp-channel-conf 00_495 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.DEC_VALID_COMMA_ONLY origin:064-gtp-channel-conf 00_494 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.DMONITOR_CFG[0] origin:064-gtp-channel-conf 02_368 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.DMONITOR_CFG[1] origin:064-gtp-channel-conf 03_368 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.DMONITOR_CFG[2] origin:064-gtp-channel-conf 02_369 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.DMONITOR_CFG[3] origin:064-gtp-channel-conf 03_369 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.DMONITOR_CFG[4] origin:064-gtp-channel-conf 02_370 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.DMONITOR_CFG[5] origin:064-gtp-channel-conf 03_370 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.DMONITOR_CFG[6] origin:064-gtp-channel-conf 02_371 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.DMONITOR_CFG[7] origin:064-gtp-channel-conf 03_371 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.DMONITOR_CFG[8] origin:064-gtp-channel-conf 02_372 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.DMONITOR_CFG[9] origin:064-gtp-channel-conf 03_372 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.DMONITOR_CFG[10] origin:064-gtp-channel-conf 02_373 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.DMONITOR_CFG[11] origin:064-gtp-channel-conf 03_373 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.DMONITOR_CFG[12] origin:064-gtp-channel-conf 02_374 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.DMONITOR_CFG[13] origin:064-gtp-channel-conf 03_374 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.DMONITOR_CFG[14] origin:064-gtp-channel-conf 02_375 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.DMONITOR_CFG[15] origin:064-gtp-channel-conf 03_375 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.DMONITOR_CFG[16] origin:064-gtp-channel-conf 02_376 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.DMONITOR_CFG[17] origin:064-gtp-channel-conf 03_376 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.DMONITOR_CFG[18] origin:064-gtp-channel-conf 02_377 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.DMONITOR_CFG[19] origin:064-gtp-channel-conf 03_377 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.DMONITOR_CFG[20] origin:064-gtp-channel-conf 02_378 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.DMONITOR_CFG[21] origin:064-gtp-channel-conf 03_378 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.DMONITOR_CFG[22] origin:064-gtp-channel-conf 02_379 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.DMONITOR_CFG[23] origin:064-gtp-channel-conf 03_379 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_CLK_PHASE_SEL[0] origin:064-gtp-channel-conf 03_463 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_CONTROL[0] origin:064-gtp-channel-conf 00_488 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_CONTROL[1] origin:064-gtp-channel-conf 01_488 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_CONTROL[2] origin:064-gtp-channel-conf 00_489 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_CONTROL[3] origin:064-gtp-channel-conf 01_489 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_CONTROL[4] origin:064-gtp-channel-conf 00_490 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_CONTROL[5] origin:064-gtp-channel-conf 01_490 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_ERRDET_EN origin:064-gtp-channel-conf 01_492 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_EYE_SCAN_EN origin:064-gtp-channel-conf 00_492 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_HORZ_OFFSET[0] origin:064-gtp-channel-conf 00_480 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_HORZ_OFFSET[1] origin:064-gtp-channel-conf 01_480 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_HORZ_OFFSET[2] origin:064-gtp-channel-conf 00_481 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_HORZ_OFFSET[3] origin:064-gtp-channel-conf 01_481 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_HORZ_OFFSET[4] origin:064-gtp-channel-conf 00_482 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_HORZ_OFFSET[5] origin:064-gtp-channel-conf 01_482 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_HORZ_OFFSET[6] origin:064-gtp-channel-conf 00_483 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_HORZ_OFFSET[7] origin:064-gtp-channel-conf 01_483 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_HORZ_OFFSET[8] origin:064-gtp-channel-conf 00_484 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_HORZ_OFFSET[9] origin:064-gtp-channel-conf 01_484 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_HORZ_OFFSET[10] origin:064-gtp-channel-conf 00_485 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_HORZ_OFFSET[11] origin:064-gtp-channel-conf 01_485 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_PMA_CFG[0] origin:064-gtp-channel-conf 02_624 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_PMA_CFG[1] origin:064-gtp-channel-conf 03_624 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_PMA_CFG[2] origin:064-gtp-channel-conf 02_625 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_PMA_CFG[3] origin:064-gtp-channel-conf 03_625 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_PMA_CFG[4] origin:064-gtp-channel-conf 02_626 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_PMA_CFG[5] origin:064-gtp-channel-conf 03_626 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_PMA_CFG[6] origin:064-gtp-channel-conf 02_627 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_PMA_CFG[7] origin:064-gtp-channel-conf 03_627 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_PMA_CFG[8] origin:064-gtp-channel-conf 02_628 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_PMA_CFG[9] origin:064-gtp-channel-conf 03_628 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_PRESCALE[0] origin:064-gtp-channel-conf 01_477 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_PRESCALE[1] origin:064-gtp-channel-conf 00_478 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_PRESCALE[2] origin:064-gtp-channel-conf 01_478 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_PRESCALE[3] origin:064-gtp-channel-conf 00_479 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_PRESCALE[4] origin:064-gtp-channel-conf 01_479 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[0] origin:064-gtp-channel-conf 00_392 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[1] origin:064-gtp-channel-conf 01_392 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[2] origin:064-gtp-channel-conf 00_393 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[3] origin:064-gtp-channel-conf 01_393 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[4] origin:064-gtp-channel-conf 00_394 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[5] origin:064-gtp-channel-conf 01_394 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[6] origin:064-gtp-channel-conf 00_395 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[7] origin:064-gtp-channel-conf 01_395 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[8] origin:064-gtp-channel-conf 00_396 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[9] origin:064-gtp-channel-conf 01_396 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[10] origin:064-gtp-channel-conf 00_397 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[11] origin:064-gtp-channel-conf 01_397 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[12] origin:064-gtp-channel-conf 00_398 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[13] origin:064-gtp-channel-conf 01_398 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[14] origin:064-gtp-channel-conf 00_399 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[15] origin:064-gtp-channel-conf 01_399 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[16] origin:064-gtp-channel-conf 00_400 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[17] origin:064-gtp-channel-conf 01_400 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[18] origin:064-gtp-channel-conf 00_401 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[19] origin:064-gtp-channel-conf 01_401 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[20] origin:064-gtp-channel-conf 00_402 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[21] origin:064-gtp-channel-conf 01_402 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[22] origin:064-gtp-channel-conf 00_403 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[23] origin:064-gtp-channel-conf 01_403 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[24] origin:064-gtp-channel-conf 00_404 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[25] origin:064-gtp-channel-conf 01_404 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[26] origin:064-gtp-channel-conf 00_405 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[27] origin:064-gtp-channel-conf 01_405 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[28] origin:064-gtp-channel-conf 00_406 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[29] origin:064-gtp-channel-conf 01_406 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[30] origin:064-gtp-channel-conf 00_407 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[31] origin:064-gtp-channel-conf 01_407 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[32] origin:064-gtp-channel-conf 00_408 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[33] origin:064-gtp-channel-conf 01_408 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[34] origin:064-gtp-channel-conf 00_409 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[35] origin:064-gtp-channel-conf 01_409 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[36] origin:064-gtp-channel-conf 00_410 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[37] origin:064-gtp-channel-conf 01_410 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[38] origin:064-gtp-channel-conf 00_411 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[39] origin:064-gtp-channel-conf 01_411 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[40] origin:064-gtp-channel-conf 00_412 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[41] origin:064-gtp-channel-conf 01_412 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[42] origin:064-gtp-channel-conf 00_413 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[43] origin:064-gtp-channel-conf 01_413 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[44] origin:064-gtp-channel-conf 00_414 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[45] origin:064-gtp-channel-conf 01_414 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[46] origin:064-gtp-channel-conf 00_415 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[47] origin:064-gtp-channel-conf 01_415 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[48] origin:064-gtp-channel-conf 00_416 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[49] origin:064-gtp-channel-conf 01_416 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[50] origin:064-gtp-channel-conf 00_417 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[51] origin:064-gtp-channel-conf 01_417 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[52] origin:064-gtp-channel-conf 00_418 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[53] origin:064-gtp-channel-conf 01_418 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[54] origin:064-gtp-channel-conf 00_419 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[55] origin:064-gtp-channel-conf 01_419 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[56] origin:064-gtp-channel-conf 00_420 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[57] origin:064-gtp-channel-conf 01_420 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[58] origin:064-gtp-channel-conf 00_421 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[59] origin:064-gtp-channel-conf 01_421 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[60] origin:064-gtp-channel-conf 00_422 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[61] origin:064-gtp-channel-conf 01_422 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[62] origin:064-gtp-channel-conf 00_423 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[63] origin:064-gtp-channel-conf 01_423 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[64] origin:064-gtp-channel-conf 00_424 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[65] origin:064-gtp-channel-conf 01_424 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[66] origin:064-gtp-channel-conf 00_425 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[67] origin:064-gtp-channel-conf 01_425 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[68] origin:064-gtp-channel-conf 00_426 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[69] origin:064-gtp-channel-conf 01_426 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[70] origin:064-gtp-channel-conf 00_427 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[71] origin:064-gtp-channel-conf 01_427 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[72] origin:064-gtp-channel-conf 00_428 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[73] origin:064-gtp-channel-conf 01_428 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[74] origin:064-gtp-channel-conf 00_429 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[75] origin:064-gtp-channel-conf 01_429 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[76] origin:064-gtp-channel-conf 00_430 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[77] origin:064-gtp-channel-conf 01_430 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[78] origin:064-gtp-channel-conf 00_431 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUAL_MASK[79] origin:064-gtp-channel-conf 01_431 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[0] origin:064-gtp-channel-conf 00_352 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[1] origin:064-gtp-channel-conf 01_352 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[2] origin:064-gtp-channel-conf 00_353 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[3] origin:064-gtp-channel-conf 01_353 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[4] origin:064-gtp-channel-conf 00_354 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[5] origin:064-gtp-channel-conf 01_354 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[6] origin:064-gtp-channel-conf 00_355 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[7] origin:064-gtp-channel-conf 01_355 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[8] origin:064-gtp-channel-conf 00_356 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[9] origin:064-gtp-channel-conf 01_356 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[10] origin:064-gtp-channel-conf 00_357 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[11] origin:064-gtp-channel-conf 01_357 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[12] origin:064-gtp-channel-conf 00_358 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[13] origin:064-gtp-channel-conf 01_358 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[14] origin:064-gtp-channel-conf 00_359 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[15] origin:064-gtp-channel-conf 01_359 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[16] origin:064-gtp-channel-conf 00_360 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[17] origin:064-gtp-channel-conf 01_360 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[18] origin:064-gtp-channel-conf 00_361 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[19] origin:064-gtp-channel-conf 01_361 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[20] origin:064-gtp-channel-conf 00_362 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[21] origin:064-gtp-channel-conf 01_362 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[22] origin:064-gtp-channel-conf 00_363 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[23] origin:064-gtp-channel-conf 01_363 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[24] origin:064-gtp-channel-conf 00_364 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[25] origin:064-gtp-channel-conf 01_364 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[26] origin:064-gtp-channel-conf 00_365 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[27] origin:064-gtp-channel-conf 01_365 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[28] origin:064-gtp-channel-conf 00_366 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[29] origin:064-gtp-channel-conf 01_366 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[30] origin:064-gtp-channel-conf 00_367 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[31] origin:064-gtp-channel-conf 01_367 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[32] origin:064-gtp-channel-conf 00_368 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[33] origin:064-gtp-channel-conf 01_368 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[34] origin:064-gtp-channel-conf 00_369 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[35] origin:064-gtp-channel-conf 01_369 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[36] origin:064-gtp-channel-conf 00_370 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[37] origin:064-gtp-channel-conf 01_370 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[38] origin:064-gtp-channel-conf 00_371 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[39] origin:064-gtp-channel-conf 01_371 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[40] origin:064-gtp-channel-conf 00_372 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[41] origin:064-gtp-channel-conf 01_372 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[42] origin:064-gtp-channel-conf 00_373 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[43] origin:064-gtp-channel-conf 01_373 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[44] origin:064-gtp-channel-conf 00_374 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[45] origin:064-gtp-channel-conf 01_374 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[46] origin:064-gtp-channel-conf 00_375 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[47] origin:064-gtp-channel-conf 01_375 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[48] origin:064-gtp-channel-conf 00_376 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[49] origin:064-gtp-channel-conf 01_376 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[50] origin:064-gtp-channel-conf 00_377 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[51] origin:064-gtp-channel-conf 01_377 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[52] origin:064-gtp-channel-conf 00_378 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[53] origin:064-gtp-channel-conf 01_378 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[54] origin:064-gtp-channel-conf 00_379 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[55] origin:064-gtp-channel-conf 01_379 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[56] origin:064-gtp-channel-conf 00_380 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[57] origin:064-gtp-channel-conf 01_380 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[58] origin:064-gtp-channel-conf 00_381 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[59] origin:064-gtp-channel-conf 01_381 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[60] origin:064-gtp-channel-conf 00_382 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[61] origin:064-gtp-channel-conf 01_382 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[62] origin:064-gtp-channel-conf 00_383 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[63] origin:064-gtp-channel-conf 01_383 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[64] origin:064-gtp-channel-conf 00_384 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[65] origin:064-gtp-channel-conf 01_384 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[66] origin:064-gtp-channel-conf 00_385 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[67] origin:064-gtp-channel-conf 01_385 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[68] origin:064-gtp-channel-conf 00_386 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[69] origin:064-gtp-channel-conf 01_386 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[70] origin:064-gtp-channel-conf 00_387 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[71] origin:064-gtp-channel-conf 01_387 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[72] origin:064-gtp-channel-conf 00_388 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[73] origin:064-gtp-channel-conf 01_388 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[74] origin:064-gtp-channel-conf 00_389 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[75] origin:064-gtp-channel-conf 01_389 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[76] origin:064-gtp-channel-conf 00_390 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[77] origin:064-gtp-channel-conf 01_390 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[78] origin:064-gtp-channel-conf 00_391 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_QUALIFIER[79] origin:064-gtp-channel-conf 01_391 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[0] origin:064-gtp-channel-conf 00_432 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[1] origin:064-gtp-channel-conf 01_432 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[2] origin:064-gtp-channel-conf 00_433 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[3] origin:064-gtp-channel-conf 01_433 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[4] origin:064-gtp-channel-conf 00_434 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[5] origin:064-gtp-channel-conf 01_434 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[6] origin:064-gtp-channel-conf 00_435 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[7] origin:064-gtp-channel-conf 01_435 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[8] origin:064-gtp-channel-conf 00_436 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[9] origin:064-gtp-channel-conf 01_436 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[10] origin:064-gtp-channel-conf 00_437 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[11] origin:064-gtp-channel-conf 01_437 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[12] origin:064-gtp-channel-conf 00_438 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[13] origin:064-gtp-channel-conf 01_438 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[14] origin:064-gtp-channel-conf 00_439 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[15] origin:064-gtp-channel-conf 01_439 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[16] origin:064-gtp-channel-conf 00_440 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[17] origin:064-gtp-channel-conf 01_440 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[18] origin:064-gtp-channel-conf 00_441 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[19] origin:064-gtp-channel-conf 01_441 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[20] origin:064-gtp-channel-conf 00_442 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[21] origin:064-gtp-channel-conf 01_442 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[22] origin:064-gtp-channel-conf 00_443 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[23] origin:064-gtp-channel-conf 01_443 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[24] origin:064-gtp-channel-conf 00_444 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[25] origin:064-gtp-channel-conf 01_444 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[26] origin:064-gtp-channel-conf 00_445 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[27] origin:064-gtp-channel-conf 01_445 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[28] origin:064-gtp-channel-conf 00_446 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[29] origin:064-gtp-channel-conf 01_446 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[30] origin:064-gtp-channel-conf 00_447 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[31] origin:064-gtp-channel-conf 01_447 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[32] origin:064-gtp-channel-conf 00_448 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[33] origin:064-gtp-channel-conf 01_448 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[34] origin:064-gtp-channel-conf 00_449 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[35] origin:064-gtp-channel-conf 01_449 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[36] origin:064-gtp-channel-conf 00_450 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[37] origin:064-gtp-channel-conf 01_450 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[38] origin:064-gtp-channel-conf 00_451 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[39] origin:064-gtp-channel-conf 01_451 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[40] origin:064-gtp-channel-conf 00_452 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[41] origin:064-gtp-channel-conf 01_452 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[42] origin:064-gtp-channel-conf 00_453 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[43] origin:064-gtp-channel-conf 01_453 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[44] origin:064-gtp-channel-conf 00_454 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[45] origin:064-gtp-channel-conf 01_454 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[46] origin:064-gtp-channel-conf 00_455 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[47] origin:064-gtp-channel-conf 01_455 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[48] origin:064-gtp-channel-conf 00_456 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[49] origin:064-gtp-channel-conf 01_456 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[50] origin:064-gtp-channel-conf 00_457 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[51] origin:064-gtp-channel-conf 01_457 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[52] origin:064-gtp-channel-conf 00_458 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[53] origin:064-gtp-channel-conf 01_458 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[54] origin:064-gtp-channel-conf 00_459 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[55] origin:064-gtp-channel-conf 01_459 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[56] origin:064-gtp-channel-conf 00_460 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[57] origin:064-gtp-channel-conf 01_460 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[58] origin:064-gtp-channel-conf 00_461 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[59] origin:064-gtp-channel-conf 01_461 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[60] origin:064-gtp-channel-conf 00_462 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[61] origin:064-gtp-channel-conf 01_462 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[62] origin:064-gtp-channel-conf 00_463 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[63] origin:064-gtp-channel-conf 01_463 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[64] origin:064-gtp-channel-conf 00_464 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[65] origin:064-gtp-channel-conf 01_464 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[66] origin:064-gtp-channel-conf 00_465 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[67] origin:064-gtp-channel-conf 01_465 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[68] origin:064-gtp-channel-conf 00_466 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[69] origin:064-gtp-channel-conf 01_466 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[70] origin:064-gtp-channel-conf 00_467 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[71] origin:064-gtp-channel-conf 01_467 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[72] origin:064-gtp-channel-conf 00_468 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[73] origin:064-gtp-channel-conf 01_468 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[74] origin:064-gtp-channel-conf 00_469 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[75] origin:064-gtp-channel-conf 01_469 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[76] origin:064-gtp-channel-conf 00_470 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[77] origin:064-gtp-channel-conf 01_470 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[78] origin:064-gtp-channel-conf 00_471 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_SDATA_MASK[79] origin:064-gtp-channel-conf 01_471 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_VERT_OFFSET[0] origin:064-gtp-channel-conf 00_472 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_VERT_OFFSET[1] origin:064-gtp-channel-conf 01_472 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_VERT_OFFSET[2] origin:064-gtp-channel-conf 00_473 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_VERT_OFFSET[3] origin:064-gtp-channel-conf 01_473 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_VERT_OFFSET[4] origin:064-gtp-channel-conf 00_474 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_VERT_OFFSET[5] origin:064-gtp-channel-conf 01_474 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_VERT_OFFSET[6] origin:064-gtp-channel-conf 00_475 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_VERT_OFFSET[7] origin:064-gtp-channel-conf 01_475 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ES_VERT_OFFSET[8] origin:064-gtp-channel-conf 00_476 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.FTS_DESKEW_SEQ_ENABLE[0] origin:064-gtp-channel-conf 00_662 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.FTS_DESKEW_SEQ_ENABLE[1] origin:064-gtp-channel-conf 01_662 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.FTS_DESKEW_SEQ_ENABLE[2] origin:064-gtp-channel-conf 00_663 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.FTS_DESKEW_SEQ_ENABLE[3] origin:064-gtp-channel-conf 01_663 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.FTS_LANE_DESKEW_CFG[0] origin:064-gtp-channel-conf 00_654 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.FTS_LANE_DESKEW_CFG[1] origin:064-gtp-channel-conf 01_654 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.FTS_LANE_DESKEW_CFG[2] origin:064-gtp-channel-conf 00_655 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.FTS_LANE_DESKEW_CFG[3] origin:064-gtp-channel-conf 01_655 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.FTS_LANE_DESKEW_EN origin:064-gtp-channel-conf 01_653 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.GEARBOX_MODE[0] origin:064-gtp-channel-conf 00_224 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.GEARBOX_MODE[1] origin:064-gtp-channel-conf 01_224 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.GEARBOX_MODE[2] origin:064-gtp-channel-conf 00_225 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.IN_USE origin:064-gtp-channel-conf 00_00 00_01 00_47 00_52 00_53 00_65 01_01 01_47 02_129 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.LOOPBACK_CFG[0] origin:064-gtp-channel-conf 02_20 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.OUTREFCLK_SEL_INV[0] origin:064-gtp-channel-conf 00_149 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.OUTREFCLK_SEL_INV[1] origin:064-gtp-channel-conf 01_149 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PCS_PCIE_EN origin:064-gtp-channel-conf 00_216 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[0] origin:064-gtp-channel-conf 02_184 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[1] origin:064-gtp-channel-conf 03_184 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[2] origin:064-gtp-channel-conf 02_185 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[3] origin:064-gtp-channel-conf 03_185 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[4] origin:064-gtp-channel-conf 02_186 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[5] origin:064-gtp-channel-conf 03_186 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[6] origin:064-gtp-channel-conf 02_187 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[7] origin:064-gtp-channel-conf 03_187 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[8] origin:064-gtp-channel-conf 02_188 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[9] origin:064-gtp-channel-conf 03_188 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[10] origin:064-gtp-channel-conf 02_189 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[11] origin:064-gtp-channel-conf 03_189 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[12] origin:064-gtp-channel-conf 02_190 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[13] origin:064-gtp-channel-conf 03_190 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[14] origin:064-gtp-channel-conf 02_191 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[15] origin:064-gtp-channel-conf 03_191 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[16] origin:064-gtp-channel-conf 02_192 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[17] origin:064-gtp-channel-conf 03_192 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[18] origin:064-gtp-channel-conf 02_193 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[19] origin:064-gtp-channel-conf 03_193 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[20] origin:064-gtp-channel-conf 02_194 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[21] origin:064-gtp-channel-conf 03_194 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[22] origin:064-gtp-channel-conf 02_195 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[23] origin:064-gtp-channel-conf 03_195 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[24] origin:064-gtp-channel-conf 02_196 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[25] origin:064-gtp-channel-conf 03_196 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[26] origin:064-gtp-channel-conf 02_197 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[27] origin:064-gtp-channel-conf 03_197 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[28] origin:064-gtp-channel-conf 02_198 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[29] origin:064-gtp-channel-conf 03_198 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[30] origin:064-gtp-channel-conf 02_199 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[31] origin:064-gtp-channel-conf 03_199 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[32] origin:064-gtp-channel-conf 02_200 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[33] origin:064-gtp-channel-conf 03_200 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[34] origin:064-gtp-channel-conf 02_201 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[35] origin:064-gtp-channel-conf 03_201 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[36] origin:064-gtp-channel-conf 02_202 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[37] origin:064-gtp-channel-conf 03_202 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[38] origin:064-gtp-channel-conf 02_203 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[39] origin:064-gtp-channel-conf 03_203 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[40] origin:064-gtp-channel-conf 02_204 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[41] origin:064-gtp-channel-conf 03_204 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[42] origin:064-gtp-channel-conf 02_205 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[43] origin:064-gtp-channel-conf 03_205 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[44] origin:064-gtp-channel-conf 02_206 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[45] origin:064-gtp-channel-conf 03_206 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[46] origin:064-gtp-channel-conf 02_207 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[47] origin:064-gtp-channel-conf 03_207 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PD_TRANS_TIME_FROM_P2[0] origin:064-gtp-channel-conf 01_216 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PD_TRANS_TIME_FROM_P2[1] origin:064-gtp-channel-conf 00_217 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PD_TRANS_TIME_FROM_P2[2] origin:064-gtp-channel-conf 01_217 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PD_TRANS_TIME_FROM_P2[3] origin:064-gtp-channel-conf 00_218 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PD_TRANS_TIME_FROM_P2[4] origin:064-gtp-channel-conf 01_218 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PD_TRANS_TIME_FROM_P2[5] origin:064-gtp-channel-conf 00_219 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PD_TRANS_TIME_FROM_P2[6] origin:064-gtp-channel-conf 01_219 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PD_TRANS_TIME_FROM_P2[7] origin:064-gtp-channel-conf 00_220 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PD_TRANS_TIME_FROM_P2[8] origin:064-gtp-channel-conf 01_220 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PD_TRANS_TIME_FROM_P2[9] origin:064-gtp-channel-conf 00_221 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PD_TRANS_TIME_FROM_P2[10] origin:064-gtp-channel-conf 01_221 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PD_TRANS_TIME_FROM_P2[11] origin:064-gtp-channel-conf 00_222 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PD_TRANS_TIME_NONE_P2[0] origin:064-gtp-channel-conf 00_208 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PD_TRANS_TIME_NONE_P2[1] origin:064-gtp-channel-conf 01_208 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PD_TRANS_TIME_NONE_P2[2] origin:064-gtp-channel-conf 00_209 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PD_TRANS_TIME_NONE_P2[3] origin:064-gtp-channel-conf 01_209 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PD_TRANS_TIME_NONE_P2[4] origin:064-gtp-channel-conf 00_210 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PD_TRANS_TIME_NONE_P2[5] origin:064-gtp-channel-conf 01_210 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PD_TRANS_TIME_NONE_P2[6] origin:064-gtp-channel-conf 00_211 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PD_TRANS_TIME_NONE_P2[7] origin:064-gtp-channel-conf 01_211 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PD_TRANS_TIME_TO_P2[0] origin:064-gtp-channel-conf 00_212 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PD_TRANS_TIME_TO_P2[1] origin:064-gtp-channel-conf 01_212 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PD_TRANS_TIME_TO_P2[2] origin:064-gtp-channel-conf 00_213 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PD_TRANS_TIME_TO_P2[3] origin:064-gtp-channel-conf 01_213 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PD_TRANS_TIME_TO_P2[4] origin:064-gtp-channel-conf 00_214 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PD_TRANS_TIME_TO_P2[5] origin:064-gtp-channel-conf 01_214 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PD_TRANS_TIME_TO_P2[6] origin:064-gtp-channel-conf 00_215 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PD_TRANS_TIME_TO_P2[7] origin:064-gtp-channel-conf 01_215 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PMA_LOOPBACK_CFG[0] origin:064-gtp-channel-conf 01_207 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PMA_RSV[0] origin:064-gtp-channel-conf 02_520 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PMA_RSV[1] origin:064-gtp-channel-conf 03_520 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PMA_RSV[2] origin:064-gtp-channel-conf 02_521 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PMA_RSV[3] origin:064-gtp-channel-conf 03_521 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PMA_RSV[4] origin:064-gtp-channel-conf 02_522 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PMA_RSV[5] origin:064-gtp-channel-conf 03_522 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PMA_RSV[6] origin:064-gtp-channel-conf 02_523 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PMA_RSV[7] origin:064-gtp-channel-conf 03_523 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PMA_RSV[8] origin:064-gtp-channel-conf 02_524 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PMA_RSV[9] origin:064-gtp-channel-conf 03_524 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PMA_RSV[10] origin:064-gtp-channel-conf 02_525 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PMA_RSV[11] origin:064-gtp-channel-conf 03_525 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PMA_RSV[12] origin:064-gtp-channel-conf 02_526 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PMA_RSV[13] origin:064-gtp-channel-conf 03_526 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PMA_RSV[14] origin:064-gtp-channel-conf 02_527 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PMA_RSV[15] origin:064-gtp-channel-conf 03_527 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PMA_RSV[16] origin:064-gtp-channel-conf 02_528 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PMA_RSV[17] origin:064-gtp-channel-conf 03_528 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PMA_RSV[18] origin:064-gtp-channel-conf 02_529 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PMA_RSV[19] origin:064-gtp-channel-conf 03_529 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PMA_RSV[20] origin:064-gtp-channel-conf 02_530 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PMA_RSV[21] origin:064-gtp-channel-conf 03_530 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PMA_RSV[22] origin:064-gtp-channel-conf 02_531 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PMA_RSV[23] origin:064-gtp-channel-conf 03_531 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PMA_RSV[24] origin:064-gtp-channel-conf 02_532 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PMA_RSV[25] origin:064-gtp-channel-conf 03_532 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PMA_RSV[26] origin:064-gtp-channel-conf 02_533 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PMA_RSV[27] origin:064-gtp-channel-conf 03_533 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PMA_RSV[28] origin:064-gtp-channel-conf 02_534 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PMA_RSV[29] origin:064-gtp-channel-conf 03_534 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PMA_RSV[30] origin:064-gtp-channel-conf 02_535 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PMA_RSV[31] origin:064-gtp-channel-conf 03_535 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PMA_RSV2[0] origin:064-gtp-channel-conf 02_336 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PMA_RSV2[1] origin:064-gtp-channel-conf 03_336 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PMA_RSV2[2] origin:064-gtp-channel-conf 02_337 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PMA_RSV2[3] origin:064-gtp-channel-conf 03_337 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PMA_RSV2[4] origin:064-gtp-channel-conf 02_338 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PMA_RSV2[5] origin:064-gtp-channel-conf 03_338 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PMA_RSV2[6] origin:064-gtp-channel-conf 02_339 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PMA_RSV2[7] origin:064-gtp-channel-conf 03_339 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PMA_RSV2[8] origin:064-gtp-channel-conf 02_340 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PMA_RSV2[9] origin:064-gtp-channel-conf 03_340 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PMA_RSV2[10] origin:064-gtp-channel-conf 02_341 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PMA_RSV2[11] origin:064-gtp-channel-conf 03_341 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PMA_RSV2[12] origin:064-gtp-channel-conf 02_342 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PMA_RSV2[13] origin:064-gtp-channel-conf 03_342 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PMA_RSV2[14] origin:064-gtp-channel-conf 02_343 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PMA_RSV2[15] origin:064-gtp-channel-conf 03_343 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PMA_RSV2[16] origin:064-gtp-channel-conf 02_344 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PMA_RSV2[17] origin:064-gtp-channel-conf 03_344 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PMA_RSV2[18] origin:064-gtp-channel-conf 02_345 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PMA_RSV2[19] origin:064-gtp-channel-conf 03_345 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PMA_RSV2[20] origin:064-gtp-channel-conf 02_346 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PMA_RSV2[21] origin:064-gtp-channel-conf 03_346 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PMA_RSV2[22] origin:064-gtp-channel-conf 02_347 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PMA_RSV2[23] origin:064-gtp-channel-conf 03_347 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PMA_RSV2[24] origin:064-gtp-channel-conf 02_348 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PMA_RSV2[25] origin:064-gtp-channel-conf 03_348 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PMA_RSV2[26] origin:064-gtp-channel-conf 02_349 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PMA_RSV2[27] origin:064-gtp-channel-conf 03_349 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PMA_RSV2[28] origin:064-gtp-channel-conf 02_350 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PMA_RSV2[29] origin:064-gtp-channel-conf 03_350 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PMA_RSV2[30] origin:064-gtp-channel-conf 02_351 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PMA_RSV2[31] origin:064-gtp-channel-conf 03_351 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PMA_RSV3[0] origin:064-gtp-channel-conf 02_288 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PMA_RSV3[1] origin:064-gtp-channel-conf 03_288 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PMA_RSV4[0] origin:064-gtp-channel-conf 02_156 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PMA_RSV4[1] origin:064-gtp-channel-conf 03_156 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PMA_RSV4[2] origin:064-gtp-channel-conf 02_157 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PMA_RSV4[3] origin:064-gtp-channel-conf 03_157 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PMA_RSV5[0] origin:064-gtp-channel-conf 03_159 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PMA_RSV6[0] origin:064-gtp-channel-conf 02_303 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.PMA_RSV7[0] origin:064-gtp-channel-conf 03_303 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_BIAS_CFG[0] origin:064-gtp-channel-conf 02_112 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_BIAS_CFG[1] origin:064-gtp-channel-conf 03_112 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_BIAS_CFG[2] origin:064-gtp-channel-conf 02_113 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_BIAS_CFG[3] origin:064-gtp-channel-conf 03_113 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_BIAS_CFG[4] origin:064-gtp-channel-conf 02_114 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_BIAS_CFG[5] origin:064-gtp-channel-conf 03_114 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_BIAS_CFG[6] origin:064-gtp-channel-conf 02_115 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_BIAS_CFG[7] origin:064-gtp-channel-conf 03_115 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_BIAS_CFG[8] origin:064-gtp-channel-conf 02_116 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_BIAS_CFG[9] origin:064-gtp-channel-conf 03_116 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_BIAS_CFG[10] origin:064-gtp-channel-conf 02_117 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_BIAS_CFG[11] origin:064-gtp-channel-conf 03_117 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_BIAS_CFG[12] origin:064-gtp-channel-conf 02_118 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_BIAS_CFG[13] origin:064-gtp-channel-conf 03_118 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_BIAS_CFG[14] origin:064-gtp-channel-conf 02_119 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_BIAS_CFG[15] origin:064-gtp-channel-conf 03_119 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_BUFFER_CFG[0] origin:064-gtp-channel-conf 02_536 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_BUFFER_CFG[1] origin:064-gtp-channel-conf 03_536 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_BUFFER_CFG[2] origin:064-gtp-channel-conf 02_537 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_BUFFER_CFG[3] origin:064-gtp-channel-conf 03_537 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_BUFFER_CFG[4] origin:064-gtp-channel-conf 02_538 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_BUFFER_CFG[5] origin:064-gtp-channel-conf 03_538 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_CLKMUX_EN[0] origin:064-gtp-channel-conf 02_128 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_CM_SEL[0] origin:064-gtp-channel-conf 00_138 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_CM_SEL[1] origin:064-gtp-channel-conf 01_138 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_CM_TRIM[0] origin:064-gtp-channel-conf 02_304 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_CM_TRIM[1] origin:064-gtp-channel-conf 03_304 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_CM_TRIM[2] origin:064-gtp-channel-conf 02_305 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_CM_TRIM[3] origin:064-gtp-channel-conf 03_305 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_DATA_WIDTH[0] origin:064-gtp-channel-conf 01_141 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_DATA_WIDTH[1] origin:064-gtp-channel-conf 00_142 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_DATA_WIDTH[2] origin:064-gtp-channel-conf 01_142 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_DDI_SEL[0] origin:064-gtp-channel-conf 00_696 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_DDI_SEL[1] origin:064-gtp-channel-conf 01_696 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_DDI_SEL[2] origin:064-gtp-channel-conf 00_697 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_DDI_SEL[3] origin:064-gtp-channel-conf 01_697 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_DDI_SEL[4] origin:064-gtp-channel-conf 00_698 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_DDI_SEL[5] origin:064-gtp-channel-conf 01_698 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_DEBUG_CFG[0] origin:064-gtp-channel-conf 02_616 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_DEBUG_CFG[1] origin:064-gtp-channel-conf 03_616 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_DEBUG_CFG[2] origin:064-gtp-channel-conf 02_617 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_DEBUG_CFG[3] origin:064-gtp-channel-conf 03_617 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_DEBUG_CFG[4] origin:064-gtp-channel-conf 02_618 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_DEBUG_CFG[5] origin:064-gtp-channel-conf 03_618 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_DEBUG_CFG[6] origin:064-gtp-channel-conf 02_619 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_DEBUG_CFG[7] origin:064-gtp-channel-conf 03_619 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_DEBUG_CFG[8] origin:064-gtp-channel-conf 02_620 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_DEBUG_CFG[9] origin:064-gtp-channel-conf 03_620 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_DEBUG_CFG[10] origin:064-gtp-channel-conf 02_621 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_DEBUG_CFG[11] origin:064-gtp-channel-conf 03_621 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_DEBUG_CFG[12] origin:064-gtp-channel-conf 02_622 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_DEBUG_CFG[13] origin:064-gtp-channel-conf 03_622 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_DEFER_RESET_BUF_EN origin:064-gtp-channel-conf 02_552 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_DISPERR_SEQ_MATCH origin:064-gtp-channel-conf 01_495 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_OS_CFG[0] origin:064-gtp-channel-conf 00_288 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_OS_CFG[1] origin:064-gtp-channel-conf 01_288 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_OS_CFG[2] origin:064-gtp-channel-conf 00_289 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_OS_CFG[3] origin:064-gtp-channel-conf 01_289 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_OS_CFG[4] origin:064-gtp-channel-conf 00_290 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_OS_CFG[5] origin:064-gtp-channel-conf 01_290 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_OS_CFG[6] origin:064-gtp-channel-conf 00_291 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_OS_CFG[7] origin:064-gtp-channel-conf 01_291 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_OS_CFG[8] origin:064-gtp-channel-conf 00_292 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_OS_CFG[9] origin:064-gtp-channel-conf 01_292 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_OS_CFG[10] origin:064-gtp-channel-conf 00_293 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_OS_CFG[11] origin:064-gtp-channel-conf 01_293 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_OS_CFG[12] origin:064-gtp-channel-conf 00_294 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_SIG_VALID_DLY[0] origin:064-gtp-channel-conf 00_524 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_SIG_VALID_DLY[1] origin:064-gtp-channel-conf 01_524 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_SIG_VALID_DLY[2] origin:064-gtp-channel-conf 00_525 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_SIG_VALID_DLY[3] origin:064-gtp-channel-conf 01_525 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_SIG_VALID_DLY[4] origin:064-gtp-channel-conf 00_526 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_XCLK_SEL.RXUSR origin:064-gtp-channel-conf 00_143 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_CLK25_DIV[0] origin:064-gtp-channel-conf 00_139 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_CLK25_DIV[1] origin:064-gtp-channel-conf 01_139 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_CLK25_DIV[2] origin:064-gtp-channel-conf 00_140 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_CLK25_DIV[3] origin:064-gtp-channel-conf 01_140 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RX_CLK25_DIV[4] origin:064-gtp-channel-conf 00_141 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXBUF_ADDR_MODE.FAST origin:064-gtp-channel-conf 03_555 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXBUF_EIDLE_HI_CNT[0] origin:064-gtp-channel-conf 02_558 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXBUF_EIDLE_HI_CNT[1] origin:064-gtp-channel-conf 03_558 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXBUF_EIDLE_HI_CNT[2] origin:064-gtp-channel-conf 02_559 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXBUF_EIDLE_HI_CNT[3] origin:064-gtp-channel-conf 03_559 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXBUF_EIDLE_LO_CNT[0] origin:064-gtp-channel-conf 02_556 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXBUF_EIDLE_LO_CNT[1] origin:064-gtp-channel-conf 03_556 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXBUF_EIDLE_LO_CNT[2] origin:064-gtp-channel-conf 02_557 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXBUF_EIDLE_LO_CNT[3] origin:064-gtp-channel-conf 03_557 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXBUF_EN origin:064-gtp-channel-conf 02_11 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXBUF_RESET_ON_CB_CHANGE origin:064-gtp-channel-conf 02_560 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXBUF_RESET_ON_COMMAALIGN origin:064-gtp-channel-conf 02_561 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXBUF_RESET_ON_EIDLE origin:064-gtp-channel-conf 02_547 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXBUF_RESET_ON_RATE_CHANGE origin:064-gtp-channel-conf 03_560 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXBUF_THRESH_OVFLW[0] origin:064-gtp-channel-conf 03_552 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXBUF_THRESH_OVFLW[1] origin:064-gtp-channel-conf 02_553 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXBUF_THRESH_OVFLW[2] origin:064-gtp-channel-conf 03_553 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXBUF_THRESH_OVFLW[3] origin:064-gtp-channel-conf 02_554 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXBUF_THRESH_OVFLW[4] origin:064-gtp-channel-conf 03_554 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXBUF_THRESH_OVFLW[5] origin:064-gtp-channel-conf 02_555 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXBUF_THRESH_OVRD origin:064-gtp-channel-conf 02_548 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXBUF_THRESH_UNDFLW[0] origin:064-gtp-channel-conf 02_544 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXBUF_THRESH_UNDFLW[1] origin:064-gtp-channel-conf 03_544 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXBUF_THRESH_UNDFLW[2] origin:064-gtp-channel-conf 02_545 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXBUF_THRESH_UNDFLW[3] origin:064-gtp-channel-conf 03_545 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXBUF_THRESH_UNDFLW[4] origin:064-gtp-channel-conf 02_546 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXBUF_THRESH_UNDFLW[5] origin:064-gtp-channel-conf 03_546 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXBUFRESET_TIME[0] origin:064-gtp-channel-conf 01_101 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXBUFRESET_TIME[1] origin:064-gtp-channel-conf 00_102 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXBUFRESET_TIME[2] origin:064-gtp-channel-conf 01_102 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXBUFRESET_TIME[3] origin:064-gtp-channel-conf 00_103 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXBUFRESET_TIME[4] origin:064-gtp-channel-conf 01_103 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[0] origin:064-gtp-channel-conf 02_640 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[1] origin:064-gtp-channel-conf 03_640 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[2] origin:064-gtp-channel-conf 02_641 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[3] origin:064-gtp-channel-conf 03_641 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[4] origin:064-gtp-channel-conf 02_642 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[5] origin:064-gtp-channel-conf 03_642 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[6] origin:064-gtp-channel-conf 02_643 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[7] origin:064-gtp-channel-conf 03_643 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[8] origin:064-gtp-channel-conf 02_644 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[9] origin:064-gtp-channel-conf 03_644 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[10] origin:064-gtp-channel-conf 02_645 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[11] origin:064-gtp-channel-conf 03_645 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[12] origin:064-gtp-channel-conf 02_646 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[13] origin:064-gtp-channel-conf 03_646 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[14] origin:064-gtp-channel-conf 02_647 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[15] origin:064-gtp-channel-conf 03_647 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[16] origin:064-gtp-channel-conf 02_648 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[17] origin:064-gtp-channel-conf 03_648 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[18] origin:064-gtp-channel-conf 02_649 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[19] origin:064-gtp-channel-conf 03_649 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[20] origin:064-gtp-channel-conf 02_650 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[21] origin:064-gtp-channel-conf 03_650 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[22] origin:064-gtp-channel-conf 02_651 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[23] origin:064-gtp-channel-conf 03_651 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[24] origin:064-gtp-channel-conf 02_652 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[25] origin:064-gtp-channel-conf 03_652 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[26] origin:064-gtp-channel-conf 02_653 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[27] origin:064-gtp-channel-conf 03_653 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[28] origin:064-gtp-channel-conf 02_654 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[29] origin:064-gtp-channel-conf 03_654 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[30] origin:064-gtp-channel-conf 02_655 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[31] origin:064-gtp-channel-conf 03_655 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[32] origin:064-gtp-channel-conf 02_656 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[33] origin:064-gtp-channel-conf 03_656 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[34] origin:064-gtp-channel-conf 02_657 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[35] origin:064-gtp-channel-conf 03_657 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[36] origin:064-gtp-channel-conf 02_658 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[37] origin:064-gtp-channel-conf 03_658 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[38] origin:064-gtp-channel-conf 02_659 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[39] origin:064-gtp-channel-conf 03_659 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[40] origin:064-gtp-channel-conf 02_660 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[41] origin:064-gtp-channel-conf 03_660 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[42] origin:064-gtp-channel-conf 02_661 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[43] origin:064-gtp-channel-conf 03_661 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[44] origin:064-gtp-channel-conf 02_662 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[45] origin:064-gtp-channel-conf 03_662 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[46] origin:064-gtp-channel-conf 02_663 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[47] origin:064-gtp-channel-conf 03_663 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[48] origin:064-gtp-channel-conf 02_664 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[49] origin:064-gtp-channel-conf 03_664 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[50] origin:064-gtp-channel-conf 02_665 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[51] origin:064-gtp-channel-conf 03_665 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[52] origin:064-gtp-channel-conf 02_666 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[53] origin:064-gtp-channel-conf 03_666 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[54] origin:064-gtp-channel-conf 02_667 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[55] origin:064-gtp-channel-conf 03_667 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[56] origin:064-gtp-channel-conf 02_668 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[57] origin:064-gtp-channel-conf 03_668 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[58] origin:064-gtp-channel-conf 02_669 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[59] origin:064-gtp-channel-conf 03_669 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[60] origin:064-gtp-channel-conf 02_670 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[61] origin:064-gtp-channel-conf 03_670 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[62] origin:064-gtp-channel-conf 02_671 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[63] origin:064-gtp-channel-conf 03_671 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[64] origin:064-gtp-channel-conf 02_672 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[65] origin:064-gtp-channel-conf 03_672 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[66] origin:064-gtp-channel-conf 02_673 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[67] origin:064-gtp-channel-conf 03_673 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[68] origin:064-gtp-channel-conf 02_674 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[69] origin:064-gtp-channel-conf 03_674 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[70] origin:064-gtp-channel-conf 02_675 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[71] origin:064-gtp-channel-conf 03_675 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[72] origin:064-gtp-channel-conf 02_676 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[73] origin:064-gtp-channel-conf 03_676 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[74] origin:064-gtp-channel-conf 02_677 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[75] origin:064-gtp-channel-conf 03_677 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[76] origin:064-gtp-channel-conf 02_678 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[77] origin:064-gtp-channel-conf 03_678 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[78] origin:064-gtp-channel-conf 02_679 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[79] origin:064-gtp-channel-conf 03_679 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[80] origin:064-gtp-channel-conf 02_680 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[81] origin:064-gtp-channel-conf 03_680 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_CFG[82] origin:064-gtp-channel-conf 02_681 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_FR_RESET_ON_EIDLE[0] origin:064-gtp-channel-conf 02_638 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_HOLD_DURING_EIDLE[0] origin:064-gtp-channel-conf 03_637 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_LOCK_CFG[0] origin:064-gtp-channel-conf 02_632 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_LOCK_CFG[1] origin:064-gtp-channel-conf 03_632 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_LOCK_CFG[2] origin:064-gtp-channel-conf 02_633 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_LOCK_CFG[3] origin:064-gtp-channel-conf 03_633 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_LOCK_CFG[4] origin:064-gtp-channel-conf 02_634 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_LOCK_CFG[5] origin:064-gtp-channel-conf 03_634 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDR_PH_RESET_ON_EIDLE[0] origin:064-gtp-channel-conf 03_638 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDRFREQRESET_TIME[0] origin:064-gtp-channel-conf 01_106 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDRFREQRESET_TIME[1] origin:064-gtp-channel-conf 00_107 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDRFREQRESET_TIME[2] origin:064-gtp-channel-conf 01_107 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDRFREQRESET_TIME[3] origin:064-gtp-channel-conf 00_108 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDRFREQRESET_TIME[4] origin:064-gtp-channel-conf 01_108 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDRPHRESET_TIME[0] origin:064-gtp-channel-conf 00_109 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDRPHRESET_TIME[1] origin:064-gtp-channel-conf 01_109 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDRPHRESET_TIME[2] origin:064-gtp-channel-conf 00_110 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDRPHRESET_TIME[3] origin:064-gtp-channel-conf 01_110 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXCDRPHRESET_TIME[4] origin:064-gtp-channel-conf 00_111 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXDLY_CFG[0] origin:064-gtp-channel-conf 00_680 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXDLY_CFG[1] origin:064-gtp-channel-conf 01_680 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXDLY_CFG[2] origin:064-gtp-channel-conf 00_681 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXDLY_CFG[3] origin:064-gtp-channel-conf 01_681 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXDLY_CFG[4] origin:064-gtp-channel-conf 00_682 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXDLY_CFG[5] origin:064-gtp-channel-conf 01_682 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXDLY_CFG[6] origin:064-gtp-channel-conf 00_683 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXDLY_CFG[7] origin:064-gtp-channel-conf 01_683 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXDLY_CFG[8] origin:064-gtp-channel-conf 00_684 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXDLY_CFG[9] origin:064-gtp-channel-conf 01_684 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXDLY_CFG[10] origin:064-gtp-channel-conf 00_685 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXDLY_CFG[11] origin:064-gtp-channel-conf 01_685 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXDLY_CFG[12] origin:064-gtp-channel-conf 00_686 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXDLY_CFG[13] origin:064-gtp-channel-conf 01_686 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXDLY_CFG[14] origin:064-gtp-channel-conf 00_687 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXDLY_CFG[15] origin:064-gtp-channel-conf 01_687 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXDLY_LCFG[0] origin:064-gtp-channel-conf 02_576 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXDLY_LCFG[1] origin:064-gtp-channel-conf 03_576 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXDLY_LCFG[2] origin:064-gtp-channel-conf 02_577 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXDLY_LCFG[3] origin:064-gtp-channel-conf 03_577 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXDLY_LCFG[4] origin:064-gtp-channel-conf 02_578 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXDLY_LCFG[5] origin:064-gtp-channel-conf 03_578 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXDLY_LCFG[6] origin:064-gtp-channel-conf 02_579 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXDLY_LCFG[7] origin:064-gtp-channel-conf 03_579 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXDLY_LCFG[8] origin:064-gtp-channel-conf 02_580 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXDLY_TAP_CFG[0] origin:064-gtp-channel-conf 00_672 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXDLY_TAP_CFG[1] origin:064-gtp-channel-conf 01_672 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXDLY_TAP_CFG[2] origin:064-gtp-channel-conf 00_673 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXDLY_TAP_CFG[3] origin:064-gtp-channel-conf 01_673 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXDLY_TAP_CFG[4] origin:064-gtp-channel-conf 00_674 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXDLY_TAP_CFG[5] origin:064-gtp-channel-conf 01_674 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXDLY_TAP_CFG[6] origin:064-gtp-channel-conf 00_675 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXDLY_TAP_CFG[7] origin:064-gtp-channel-conf 01_675 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXDLY_TAP_CFG[8] origin:064-gtp-channel-conf 00_676 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXDLY_TAP_CFG[9] origin:064-gtp-channel-conf 01_676 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXDLY_TAP_CFG[10] origin:064-gtp-channel-conf 00_677 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXDLY_TAP_CFG[11] origin:064-gtp-channel-conf 01_677 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXDLY_TAP_CFG[12] origin:064-gtp-channel-conf 00_678 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXDLY_TAP_CFG[13] origin:064-gtp-channel-conf 01_678 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXDLY_TAP_CFG[14] origin:064-gtp-channel-conf 00_679 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXDLY_TAP_CFG[15] origin:064-gtp-channel-conf 01_679 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXGEARBOX_EN origin:064-gtp-channel-conf 01_607 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXISCANRESET_TIME[0] origin:064-gtp-channel-conf 01_123 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXISCANRESET_TIME[1] origin:064-gtp-channel-conf 00_124 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXISCANRESET_TIME[2] origin:064-gtp-channel-conf 01_124 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXISCANRESET_TIME[3] origin:064-gtp-channel-conf 00_125 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXISCANRESET_TIME[4] origin:064-gtp-channel-conf 01_125 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPM_BIAS_STARTUP_DISABLE[0] origin:064-gtp-channel-conf 03_391 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPM_CFG[0] origin:064-gtp-channel-conf 02_328 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPM_CFG[1] origin:064-gtp-channel-conf 03_328 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPM_CFG[2] origin:064-gtp-channel-conf 02_329 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPM_CFG[3] origin:064-gtp-channel-conf 03_329 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPM_CM_CFG[0] origin:064-gtp-channel-conf 02_430 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPM_GC_CFG[0] origin:064-gtp-channel-conf 02_432 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPM_GC_CFG[1] origin:064-gtp-channel-conf 03_432 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPM_GC_CFG[2] origin:064-gtp-channel-conf 02_433 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPM_GC_CFG[3] origin:064-gtp-channel-conf 03_433 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPM_GC_CFG[4] origin:064-gtp-channel-conf 02_434 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPM_GC_CFG[5] origin:064-gtp-channel-conf 03_434 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPM_GC_CFG[6] origin:064-gtp-channel-conf 02_435 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPM_GC_CFG[7] origin:064-gtp-channel-conf 03_435 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPM_GC_CFG[8] origin:064-gtp-channel-conf 02_436 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPM_GC_CFG2[0] origin:064-gtp-channel-conf 03_442 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPM_GC_CFG2[1] origin:064-gtp-channel-conf 02_443 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPM_GC_CFG2[2] origin:064-gtp-channel-conf 03_443 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPM_HF_CFG[0] origin:064-gtp-channel-conf 00_336 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPM_HF_CFG[1] origin:064-gtp-channel-conf 01_336 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPM_HF_CFG[2] origin:064-gtp-channel-conf 00_337 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPM_HF_CFG[3] origin:064-gtp-channel-conf 01_337 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPM_HF_CFG[4] origin:064-gtp-channel-conf 00_338 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPM_HF_CFG[5] origin:064-gtp-channel-conf 01_338 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPM_HF_CFG[6] origin:064-gtp-channel-conf 00_339 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPM_HF_CFG[7] origin:064-gtp-channel-conf 01_339 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPM_HF_CFG[8] origin:064-gtp-channel-conf 00_340 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPM_HF_CFG[9] origin:064-gtp-channel-conf 01_340 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPM_HF_CFG[10] origin:064-gtp-channel-conf 00_341 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPM_HF_CFG[11] origin:064-gtp-channel-conf 01_341 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPM_HF_CFG[12] origin:064-gtp-channel-conf 00_342 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPM_HF_CFG[13] origin:064-gtp-channel-conf 01_342 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPM_HF_CFG2[0] origin:064-gtp-channel-conf 02_424 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPM_HF_CFG2[1] origin:064-gtp-channel-conf 03_424 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPM_HF_CFG2[2] origin:064-gtp-channel-conf 02_425 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPM_HF_CFG2[3] origin:064-gtp-channel-conf 03_425 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPM_HF_CFG2[4] origin:064-gtp-channel-conf 02_426 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPM_HF_CFG3[0] origin:064-gtp-channel-conf 03_389 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPM_HF_CFG3[1] origin:064-gtp-channel-conf 02_390 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPM_HF_CFG3[2] origin:064-gtp-channel-conf 03_390 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPM_HF_CFG3[3] origin:064-gtp-channel-conf 02_391 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPM_HOLD_DURING_EIDLE[0] origin:064-gtp-channel-conf 00_247 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPM_INCM_CFG[0] origin:064-gtp-channel-conf 02_439 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPM_IPCM_CFG[0] origin:064-gtp-channel-conf 03_439 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPM_LF_CFG[0] origin:064-gtp-channel-conf 00_344 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPM_LF_CFG[1] origin:064-gtp-channel-conf 01_344 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPM_LF_CFG[2] origin:064-gtp-channel-conf 00_345 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPM_LF_CFG[3] origin:064-gtp-channel-conf 01_345 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPM_LF_CFG[4] origin:064-gtp-channel-conf 00_346 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPM_LF_CFG[5] origin:064-gtp-channel-conf 01_346 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPM_LF_CFG[6] origin:064-gtp-channel-conf 00_347 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPM_LF_CFG[7] origin:064-gtp-channel-conf 01_347 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPM_LF_CFG[8] origin:064-gtp-channel-conf 00_348 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPM_LF_CFG[9] origin:064-gtp-channel-conf 01_348 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPM_LF_CFG[10] origin:064-gtp-channel-conf 00_349 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPM_LF_CFG[11] origin:064-gtp-channel-conf 01_349 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPM_LF_CFG[12] origin:064-gtp-channel-conf 00_350 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPM_LF_CFG[13] origin:064-gtp-channel-conf 01_350 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPM_LF_CFG[14] origin:064-gtp-channel-conf 00_351 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPM_LF_CFG[15] origin:064-gtp-channel-conf 01_351 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPM_LF_CFG[16] origin:064-gtp-channel-conf 00_343 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPM_LF_CFG[17] origin:064-gtp-channel-conf 01_343 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPM_LF_CFG2[0] origin:064-gtp-channel-conf 03_426 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPM_LF_CFG2[1] origin:064-gtp-channel-conf 02_427 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPM_LF_CFG2[2] origin:064-gtp-channel-conf 03_427 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPM_LF_CFG2[3] origin:064-gtp-channel-conf 02_428 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPM_LF_CFG2[4] origin:064-gtp-channel-conf 03_428 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPM_OSINT_CFG[0] origin:064-gtp-channel-conf 02_440 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPM_OSINT_CFG[1] origin:064-gtp-channel-conf 03_440 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPM_OSINT_CFG[2] origin:064-gtp-channel-conf 02_441 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPM_CFG1[0] origin:064-gtp-channel-conf 02_330 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPMRESET_TIME[0] origin:064-gtp-channel-conf 00_112 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPMRESET_TIME[1] origin:064-gtp-channel-conf 01_112 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPMRESET_TIME[2] origin:064-gtp-channel-conf 00_113 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPMRESET_TIME[3] origin:064-gtp-channel-conf 01_113 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPMRESET_TIME[4] origin:064-gtp-channel-conf 00_114 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPMRESET_TIME[5] origin:064-gtp-channel-conf 01_114 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXLPMRESET_TIME[6] origin:064-gtp-channel-conf 00_115 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXOOB_CFG[0] origin:064-gtp-channel-conf 00_144 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXOOB_CFG[1] origin:064-gtp-channel-conf 01_144 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXOOB_CFG[2] origin:064-gtp-channel-conf 00_145 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXOOB_CFG[3] origin:064-gtp-channel-conf 01_145 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXOOB_CFG[4] origin:064-gtp-channel-conf 00_146 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXOOB_CFG[5] origin:064-gtp-channel-conf 01_146 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXOOB_CFG[6] origin:064-gtp-channel-conf 00_147 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXOOB_CLK_CFG.FABRIC origin:064-gtp-channel-conf 03_129 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXOSCALRESET_TIME[0] origin:064-gtp-channel-conf 00_187 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXOSCALRESET_TIME[1] origin:064-gtp-channel-conf 01_187 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXOSCALRESET_TIME[2] origin:064-gtp-channel-conf 00_188 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXOSCALRESET_TIME[3] origin:064-gtp-channel-conf 01_188 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXOSCALRESET_TIME[4] origin:064-gtp-channel-conf 00_189 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXOSCALRESET_TIMEOUT[0] origin:064-gtp-channel-conf 01_189 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXOSCALRESET_TIMEOUT[1] origin:064-gtp-channel-conf 00_190 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXOSCALRESET_TIMEOUT[2] origin:064-gtp-channel-conf 01_190 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXOSCALRESET_TIMEOUT[3] origin:064-gtp-channel-conf 00_191 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXOSCALRESET_TIMEOUT[4] origin:064-gtp-channel-conf 01_191 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXOUT_DIV[0] origin:064-gtp-channel-conf 02_384 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXOUT_DIV[1] origin:064-gtp-channel-conf 03_384 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXPCSRESET_TIME[0] origin:064-gtp-channel-conf 01_115 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXPCSRESET_TIME[1] origin:064-gtp-channel-conf 00_116 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXPCSRESET_TIME[2] origin:064-gtp-channel-conf 01_116 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXPCSRESET_TIME[3] origin:064-gtp-channel-conf 00_117 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXPCSRESET_TIME[4] origin:064-gtp-channel-conf 01_117 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXPH_CFG[0] origin:064-gtp-channel-conf 02_584 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXPH_CFG[1] origin:064-gtp-channel-conf 03_584 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXPH_CFG[2] origin:064-gtp-channel-conf 02_585 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXPH_CFG[3] origin:064-gtp-channel-conf 03_585 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXPH_CFG[4] origin:064-gtp-channel-conf 02_586 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXPH_CFG[5] origin:064-gtp-channel-conf 03_586 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXPH_CFG[6] origin:064-gtp-channel-conf 02_587 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXPH_CFG[7] origin:064-gtp-channel-conf 03_587 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXPH_CFG[8] origin:064-gtp-channel-conf 02_588 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXPH_CFG[9] origin:064-gtp-channel-conf 03_588 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXPH_CFG[10] origin:064-gtp-channel-conf 02_589 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXPH_CFG[11] origin:064-gtp-channel-conf 03_589 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXPH_CFG[12] origin:064-gtp-channel-conf 02_590 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXPH_CFG[13] origin:064-gtp-channel-conf 03_590 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXPH_CFG[14] origin:064-gtp-channel-conf 02_591 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXPH_CFG[15] origin:064-gtp-channel-conf 03_591 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXPH_CFG[16] origin:064-gtp-channel-conf 02_592 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXPH_CFG[17] origin:064-gtp-channel-conf 03_592 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXPH_CFG[18] origin:064-gtp-channel-conf 02_593 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXPH_CFG[19] origin:064-gtp-channel-conf 03_593 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXPH_CFG[20] origin:064-gtp-channel-conf 02_594 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXPH_CFG[21] origin:064-gtp-channel-conf 03_594 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXPH_CFG[22] origin:064-gtp-channel-conf 02_595 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXPH_CFG[23] origin:064-gtp-channel-conf 03_595 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXPH_MONITOR_SEL[0] origin:064-gtp-channel-conf 00_700 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXPH_MONITOR_SEL[1] origin:064-gtp-channel-conf 01_700 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXPH_MONITOR_SEL[2] origin:064-gtp-channel-conf 00_701 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXPH_MONITOR_SEL[3] origin:064-gtp-channel-conf 01_701 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXPH_MONITOR_SEL[4] origin:064-gtp-channel-conf 00_702 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXPHDLY_CFG[0] origin:064-gtp-channel-conf 02_600 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXPHDLY_CFG[1] origin:064-gtp-channel-conf 03_600 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXPHDLY_CFG[2] origin:064-gtp-channel-conf 02_601 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXPHDLY_CFG[3] origin:064-gtp-channel-conf 03_601 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXPHDLY_CFG[4] origin:064-gtp-channel-conf 02_602 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXPHDLY_CFG[5] origin:064-gtp-channel-conf 03_602 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXPHDLY_CFG[6] origin:064-gtp-channel-conf 02_603 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXPHDLY_CFG[7] origin:064-gtp-channel-conf 03_603 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXPHDLY_CFG[8] origin:064-gtp-channel-conf 02_604 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXPHDLY_CFG[9] origin:064-gtp-channel-conf 03_604 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXPHDLY_CFG[10] origin:064-gtp-channel-conf 02_605 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXPHDLY_CFG[11] origin:064-gtp-channel-conf 03_605 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXPHDLY_CFG[12] origin:064-gtp-channel-conf 02_606 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXPHDLY_CFG[13] origin:064-gtp-channel-conf 03_606 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXPHDLY_CFG[14] origin:064-gtp-channel-conf 02_607 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXPHDLY_CFG[15] origin:064-gtp-channel-conf 03_607 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXPHDLY_CFG[16] origin:064-gtp-channel-conf 02_608 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXPHDLY_CFG[17] origin:064-gtp-channel-conf 03_608 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXPHDLY_CFG[18] origin:064-gtp-channel-conf 02_609 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXPHDLY_CFG[19] origin:064-gtp-channel-conf 03_609 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXPHDLY_CFG[20] origin:064-gtp-channel-conf 02_610 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXPHDLY_CFG[21] origin:064-gtp-channel-conf 03_610 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXPHDLY_CFG[22] origin:064-gtp-channel-conf 02_611 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXPHDLY_CFG[23] origin:064-gtp-channel-conf 03_611 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXPI_CFG0[0] origin:064-gtp-channel-conf 03_430 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXPI_CFG0[1] origin:064-gtp-channel-conf 02_431 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXPI_CFG0[2] origin:064-gtp-channel-conf 03_431 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXPI_CFG1[0] origin:064-gtp-channel-conf 02_442 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXPI_CFG2[0] origin:064-gtp-channel-conf 03_441 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXPMARESET_TIME[0] origin:064-gtp-channel-conf 00_104 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXPMARESET_TIME[1] origin:064-gtp-channel-conf 01_104 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXPMARESET_TIME[2] origin:064-gtp-channel-conf 00_105 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXPMARESET_TIME[3] origin:064-gtp-channel-conf 01_105 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXPMARESET_TIME[4] origin:064-gtp-channel-conf 00_106 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXPRBS_ERR_LOOPBACK[0] origin:064-gtp-channel-conf 00_136 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXSLIDE_AUTO_WAIT[0] origin:064-gtp-channel-conf 00_520 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXSLIDE_AUTO_WAIT[1] origin:064-gtp-channel-conf 01_520 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXSLIDE_AUTO_WAIT[2] origin:064-gtp-channel-conf 00_521 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXSLIDE_AUTO_WAIT[3] origin:064-gtp-channel-conf 01_521 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXSLIDE_MODE.AUTO origin:064-gtp-channel-conf !01_519 00_519 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXSLIDE_MODE.PCS origin:064-gtp-channel-conf !00_519 01_519 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXSLIDE_MODE.PMA origin:064-gtp-channel-conf 00_519 01_519 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXSYNC_MULTILANE[0] origin:064-gtp-channel-conf 00_133 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXSYNC_OVRD[0] origin:064-gtp-channel-conf 01_135 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.RXSYNC_SKIP_DA[0] origin:064-gtp-channel-conf 01_134 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.SAS_MAX_COM[0] origin:064-gtp-channel-conf 00_171 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.SAS_MAX_COM[1] origin:064-gtp-channel-conf 01_171 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.SAS_MAX_COM[2] origin:064-gtp-channel-conf 00_172 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.SAS_MAX_COM[3] origin:064-gtp-channel-conf 01_172 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.SAS_MAX_COM[4] origin:064-gtp-channel-conf 00_173 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.SAS_MAX_COM[5] origin:064-gtp-channel-conf 01_173 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.SAS_MAX_COM[6] origin:064-gtp-channel-conf 00_174 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.SAS_MIN_COM[0] origin:064-gtp-channel-conf 01_156 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.SAS_MIN_COM[1] origin:064-gtp-channel-conf 00_157 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.SAS_MIN_COM[2] origin:064-gtp-channel-conf 01_157 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.SAS_MIN_COM[3] origin:064-gtp-channel-conf 00_158 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.SAS_MIN_COM[4] origin:064-gtp-channel-conf 01_158 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.SAS_MIN_COM[5] origin:064-gtp-channel-conf 00_159 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.SATA_BURST_SEQ_LEN[0] origin:064-gtp-channel-conf 00_150 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.SATA_BURST_SEQ_LEN[1] origin:064-gtp-channel-conf 01_150 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.SATA_BURST_SEQ_LEN[2] origin:064-gtp-channel-conf 00_151 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.SATA_BURST_SEQ_LEN[3] origin:064-gtp-channel-conf 01_151 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.SATA_BURST_VAL[0] origin:064-gtp-channel-conf 01_147 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.SATA_BURST_VAL[1] origin:064-gtp-channel-conf 00_148 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.SATA_BURST_VAL[2] origin:064-gtp-channel-conf 01_148 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.SATA_EIDLE_VAL[0] origin:064-gtp-channel-conf 00_152 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.SATA_EIDLE_VAL[1] origin:064-gtp-channel-conf 01_152 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.SATA_EIDLE_VAL[2] origin:064-gtp-channel-conf 00_153 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.SATA_MAX_BURST[0] origin:064-gtp-channel-conf 00_168 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.SATA_MAX_BURST[1] origin:064-gtp-channel-conf 01_168 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.SATA_MAX_BURST[2] origin:064-gtp-channel-conf 00_169 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.SATA_MAX_BURST[3] origin:064-gtp-channel-conf 01_169 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.SATA_MAX_BURST[4] origin:064-gtp-channel-conf 00_170 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.SATA_MAX_BURST[5] origin:064-gtp-channel-conf 01_170 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.SATA_MAX_INIT[0] origin:064-gtp-channel-conf 00_176 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.SATA_MAX_INIT[1] origin:064-gtp-channel-conf 01_176 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.SATA_MAX_INIT[2] origin:064-gtp-channel-conf 00_177 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.SATA_MAX_INIT[3] origin:064-gtp-channel-conf 01_177 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.SATA_MAX_INIT[4] origin:064-gtp-channel-conf 00_178 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.SATA_MAX_INIT[5] origin:064-gtp-channel-conf 01_178 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.SATA_MAX_WAKE[0] origin:064-gtp-channel-conf 00_179 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.SATA_MAX_WAKE[1] origin:064-gtp-channel-conf 01_179 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.SATA_MAX_WAKE[2] origin:064-gtp-channel-conf 00_180 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.SATA_MAX_WAKE[3] origin:064-gtp-channel-conf 01_180 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.SATA_MAX_WAKE[4] origin:064-gtp-channel-conf 00_181 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.SATA_MAX_WAKE[5] origin:064-gtp-channel-conf 01_181 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.SATA_MIN_BURST[0] origin:064-gtp-channel-conf 01_153 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.SATA_MIN_BURST[1] origin:064-gtp-channel-conf 00_154 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.SATA_MIN_BURST[2] origin:064-gtp-channel-conf 01_154 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.SATA_MIN_BURST[3] origin:064-gtp-channel-conf 00_155 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.SATA_MIN_BURST[4] origin:064-gtp-channel-conf 01_155 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.SATA_MIN_BURST[5] origin:064-gtp-channel-conf 00_156 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.SATA_MIN_INIT[0] origin:064-gtp-channel-conf 00_160 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.SATA_MIN_INIT[1] origin:064-gtp-channel-conf 01_160 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.SATA_MIN_INIT[2] origin:064-gtp-channel-conf 00_161 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.SATA_MIN_INIT[3] origin:064-gtp-channel-conf 01_161 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.SATA_MIN_INIT[4] origin:064-gtp-channel-conf 00_162 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.SATA_MIN_INIT[5] origin:064-gtp-channel-conf 01_162 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.SATA_MIN_WAKE[0] origin:064-gtp-channel-conf 00_163 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.SATA_MIN_WAKE[1] origin:064-gtp-channel-conf 01_163 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.SATA_MIN_WAKE[2] origin:064-gtp-channel-conf 00_164 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.SATA_MIN_WAKE[3] origin:064-gtp-channel-conf 01_164 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.SATA_MIN_WAKE[4] origin:064-gtp-channel-conf 00_165 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.SATA_MIN_WAKE[5] origin:064-gtp-channel-conf 01_165 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.SATA_PLL_CFG.VCO_1500MHZ origin:064-gtp-channel-conf 02_55 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.SATA_PLL_CFG.VCO_750MHZ origin:064-gtp-channel-conf 03_55 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.SHOW_REALIGN_COMMA origin:064-gtp-channel-conf 01_522 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TERM_RCAL_CFG[0] origin:064-gtp-channel-conf 02_136 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TERM_RCAL_CFG[1] origin:064-gtp-channel-conf 03_136 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TERM_RCAL_CFG[2] origin:064-gtp-channel-conf 02_137 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TERM_RCAL_CFG[3] origin:064-gtp-channel-conf 03_137 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TERM_RCAL_CFG[4] origin:064-gtp-channel-conf 02_138 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TERM_RCAL_CFG[5] origin:064-gtp-channel-conf 03_138 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TERM_RCAL_CFG[6] origin:064-gtp-channel-conf 02_139 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TERM_RCAL_CFG[7] origin:064-gtp-channel-conf 03_139 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TERM_RCAL_CFG[8] origin:064-gtp-channel-conf 02_140 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TERM_RCAL_CFG[9] origin:064-gtp-channel-conf 03_140 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TERM_RCAL_CFG[10] origin:064-gtp-channel-conf 02_141 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TERM_RCAL_CFG[11] origin:064-gtp-channel-conf 03_141 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TERM_RCAL_CFG[12] origin:064-gtp-channel-conf 02_142 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TERM_RCAL_CFG[13] origin:064-gtp-channel-conf 03_142 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TERM_RCAL_CFG[14] origin:064-gtp-channel-conf 02_143 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TERM_RCAL_OVRD[0] origin:064-gtp-channel-conf 03_150 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TERM_RCAL_OVRD[1] origin:064-gtp-channel-conf 02_151 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TERM_RCAL_OVRD[2] origin:064-gtp-channel-conf 03_151 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TRANS_TIME_RATE[0] origin:064-gtp-channel-conf 00_192 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TRANS_TIME_RATE[1] origin:064-gtp-channel-conf 01_192 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TRANS_TIME_RATE[2] origin:064-gtp-channel-conf 00_193 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TRANS_TIME_RATE[3] origin:064-gtp-channel-conf 01_193 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TRANS_TIME_RATE[4] origin:064-gtp-channel-conf 00_194 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TRANS_TIME_RATE[5] origin:064-gtp-channel-conf 01_194 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TRANS_TIME_RATE[6] origin:064-gtp-channel-conf 00_195 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TRANS_TIME_RATE[7] origin:064-gtp-channel-conf 01_195 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TST_RSV[0] origin:064-gtp-channel-conf 02_504 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TST_RSV[1] origin:064-gtp-channel-conf 03_504 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TST_RSV[2] origin:064-gtp-channel-conf 02_505 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TST_RSV[3] origin:064-gtp-channel-conf 03_505 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TST_RSV[4] origin:064-gtp-channel-conf 02_506 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TST_RSV[5] origin:064-gtp-channel-conf 03_506 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TST_RSV[6] origin:064-gtp-channel-conf 02_507 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TST_RSV[7] origin:064-gtp-channel-conf 03_507 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TST_RSV[8] origin:064-gtp-channel-conf 02_508 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TST_RSV[9] origin:064-gtp-channel-conf 03_508 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TST_RSV[10] origin:064-gtp-channel-conf 02_509 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TST_RSV[11] origin:064-gtp-channel-conf 03_509 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TST_RSV[12] origin:064-gtp-channel-conf 02_510 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TST_RSV[13] origin:064-gtp-channel-conf 03_510 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TST_RSV[14] origin:064-gtp-channel-conf 02_511 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TST_RSV[15] origin:064-gtp-channel-conf 03_511 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TST_RSV[16] origin:064-gtp-channel-conf 02_512 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TST_RSV[17] origin:064-gtp-channel-conf 03_512 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TST_RSV[18] origin:064-gtp-channel-conf 02_513 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TST_RSV[19] origin:064-gtp-channel-conf 03_513 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TST_RSV[20] origin:064-gtp-channel-conf 02_514 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TST_RSV[21] origin:064-gtp-channel-conf 03_514 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TST_RSV[22] origin:064-gtp-channel-conf 02_515 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TST_RSV[23] origin:064-gtp-channel-conf 03_515 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TST_RSV[24] origin:064-gtp-channel-conf 02_516 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TST_RSV[25] origin:064-gtp-channel-conf 03_516 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TST_RSV[26] origin:064-gtp-channel-conf 02_517 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TST_RSV[27] origin:064-gtp-channel-conf 03_517 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TST_RSV[28] origin:064-gtp-channel-conf 02_518 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TST_RSV[29] origin:064-gtp-channel-conf 03_518 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TST_RSV[30] origin:064-gtp-channel-conf 02_519 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TST_RSV[31] origin:064-gtp-channel-conf 03_519 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_CLKMUX_EN[0] origin:064-gtp-channel-conf 03_128 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_DATA_WIDTH[0] origin:064-gtp-channel-conf 02_152 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_DATA_WIDTH[1] origin:064-gtp-channel-conf 03_152 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_DATA_WIDTH[2] origin:064-gtp-channel-conf 02_153 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_DRIVE_MODE.PIPE origin:064-gtp-channel-conf 00_200 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_EIDLE_ASSERT_DELAY[0] origin:064-gtp-channel-conf 00_203 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_EIDLE_ASSERT_DELAY[1] origin:064-gtp-channel-conf 01_203 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_EIDLE_ASSERT_DELAY[2] origin:064-gtp-channel-conf 00_204 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_EIDLE_DEASSERT_DELAY[0] origin:064-gtp-channel-conf 01_204 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_EIDLE_DEASSERT_DELAY[1] origin:064-gtp-channel-conf 00_205 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_EIDLE_DEASSERT_DELAY[2] origin:064-gtp-channel-conf 01_205 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_LOOPBACK_DRIVE_HIZ origin:064-gtp-channel-conf 01_202 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_MAINCURSOR_SEL[0] origin:064-gtp-channel-conf 03_289 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_MARGIN_FULL_0[0] origin:064-gtp-channel-conf 02_232 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_MARGIN_FULL_0[1] origin:064-gtp-channel-conf 03_232 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_MARGIN_FULL_0[2] origin:064-gtp-channel-conf 02_233 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_MARGIN_FULL_0[3] origin:064-gtp-channel-conf 03_233 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_MARGIN_FULL_0[4] origin:064-gtp-channel-conf 02_234 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_MARGIN_FULL_0[5] origin:064-gtp-channel-conf 03_234 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_MARGIN_FULL_0[6] origin:064-gtp-channel-conf 02_235 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_MARGIN_FULL_1[0] origin:064-gtp-channel-conf 02_236 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_MARGIN_FULL_1[1] origin:064-gtp-channel-conf 03_236 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_MARGIN_FULL_1[2] origin:064-gtp-channel-conf 02_237 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_MARGIN_FULL_1[3] origin:064-gtp-channel-conf 03_237 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_MARGIN_FULL_1[4] origin:064-gtp-channel-conf 02_238 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_MARGIN_FULL_1[5] origin:064-gtp-channel-conf 03_238 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_MARGIN_FULL_1[6] origin:064-gtp-channel-conf 02_239 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_MARGIN_FULL_2[0] origin:064-gtp-channel-conf 02_240 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_MARGIN_FULL_2[1] origin:064-gtp-channel-conf 03_240 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_MARGIN_FULL_2[2] origin:064-gtp-channel-conf 02_241 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_MARGIN_FULL_2[3] origin:064-gtp-channel-conf 03_241 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_MARGIN_FULL_2[4] origin:064-gtp-channel-conf 02_242 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_MARGIN_FULL_2[5] origin:064-gtp-channel-conf 03_242 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_MARGIN_FULL_2[6] origin:064-gtp-channel-conf 02_243 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_MARGIN_FULL_3[0] origin:064-gtp-channel-conf 02_244 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_MARGIN_FULL_3[1] origin:064-gtp-channel-conf 03_244 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_MARGIN_FULL_3[2] origin:064-gtp-channel-conf 02_245 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_MARGIN_FULL_3[3] origin:064-gtp-channel-conf 03_245 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_MARGIN_FULL_3[4] origin:064-gtp-channel-conf 02_246 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_MARGIN_FULL_3[5] origin:064-gtp-channel-conf 03_246 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_MARGIN_FULL_3[6] origin:064-gtp-channel-conf 02_247 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_MARGIN_FULL_4[0] origin:064-gtp-channel-conf 02_248 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_MARGIN_FULL_4[1] origin:064-gtp-channel-conf 03_248 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_MARGIN_FULL_4[2] origin:064-gtp-channel-conf 02_249 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_MARGIN_FULL_4[3] origin:064-gtp-channel-conf 03_249 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_MARGIN_FULL_4[4] origin:064-gtp-channel-conf 02_250 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_MARGIN_FULL_4[5] origin:064-gtp-channel-conf 03_250 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_MARGIN_FULL_4[6] origin:064-gtp-channel-conf 02_251 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_MARGIN_LOW_0[0] origin:064-gtp-channel-conf 02_252 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_MARGIN_LOW_0[1] origin:064-gtp-channel-conf 03_252 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_MARGIN_LOW_0[2] origin:064-gtp-channel-conf 02_253 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_MARGIN_LOW_0[3] origin:064-gtp-channel-conf 03_253 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_MARGIN_LOW_0[4] origin:064-gtp-channel-conf 02_254 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_MARGIN_LOW_0[5] origin:064-gtp-channel-conf 03_254 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_MARGIN_LOW_0[6] origin:064-gtp-channel-conf 02_255 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_MARGIN_LOW_1[0] origin:064-gtp-channel-conf 02_256 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_MARGIN_LOW_1[1] origin:064-gtp-channel-conf 03_256 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_MARGIN_LOW_1[2] origin:064-gtp-channel-conf 02_257 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_MARGIN_LOW_1[3] origin:064-gtp-channel-conf 03_257 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_MARGIN_LOW_1[4] origin:064-gtp-channel-conf 02_258 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_MARGIN_LOW_1[5] origin:064-gtp-channel-conf 03_258 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_MARGIN_LOW_1[6] origin:064-gtp-channel-conf 02_259 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_MARGIN_LOW_2[0] origin:064-gtp-channel-conf 02_260 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_MARGIN_LOW_2[1] origin:064-gtp-channel-conf 03_260 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_MARGIN_LOW_2[2] origin:064-gtp-channel-conf 02_261 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_MARGIN_LOW_2[3] origin:064-gtp-channel-conf 03_261 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_MARGIN_LOW_2[4] origin:064-gtp-channel-conf 02_262 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_MARGIN_LOW_2[5] origin:064-gtp-channel-conf 03_262 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_MARGIN_LOW_2[6] origin:064-gtp-channel-conf 02_263 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_MARGIN_LOW_3[0] origin:064-gtp-channel-conf 02_264 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_MARGIN_LOW_3[1] origin:064-gtp-channel-conf 03_264 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_MARGIN_LOW_3[2] origin:064-gtp-channel-conf 02_265 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_MARGIN_LOW_3[3] origin:064-gtp-channel-conf 03_265 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_MARGIN_LOW_3[4] origin:064-gtp-channel-conf 02_266 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_MARGIN_LOW_3[5] origin:064-gtp-channel-conf 03_266 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_MARGIN_LOW_3[6] origin:064-gtp-channel-conf 02_267 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_MARGIN_LOW_4[0] origin:064-gtp-channel-conf 02_268 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_MARGIN_LOW_4[1] origin:064-gtp-channel-conf 03_268 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_MARGIN_LOW_4[2] origin:064-gtp-channel-conf 02_269 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_MARGIN_LOW_4[3] origin:064-gtp-channel-conf 03_269 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_MARGIN_LOW_4[4] origin:064-gtp-channel-conf 02_270 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_MARGIN_LOW_4[5] origin:064-gtp-channel-conf 03_270 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_MARGIN_LOW_4[6] origin:064-gtp-channel-conf 02_271 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_PREDRIVER_MODE[0] origin:064-gtp-channel-conf 00_206 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_RXDETECT_CFG[0] origin:064-gtp-channel-conf 02_296 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_RXDETECT_CFG[1] origin:064-gtp-channel-conf 03_296 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_RXDETECT_CFG[2] origin:064-gtp-channel-conf 02_297 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_RXDETECT_CFG[3] origin:064-gtp-channel-conf 03_297 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_RXDETECT_CFG[4] origin:064-gtp-channel-conf 02_298 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_RXDETECT_CFG[5] origin:064-gtp-channel-conf 03_298 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_RXDETECT_CFG[6] origin:064-gtp-channel-conf 02_299 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_RXDETECT_CFG[7] origin:064-gtp-channel-conf 03_299 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_RXDETECT_CFG[8] origin:064-gtp-channel-conf 02_300 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_RXDETECT_CFG[9] origin:064-gtp-channel-conf 03_300 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_RXDETECT_CFG[10] origin:064-gtp-channel-conf 02_301 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_RXDETECT_CFG[11] origin:064-gtp-channel-conf 03_301 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_RXDETECT_CFG[12] origin:064-gtp-channel-conf 02_302 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_RXDETECT_CFG[13] origin:064-gtp-channel-conf 03_302 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_RXDETECT_REF[0] origin:064-gtp-channel-conf 02_292 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_RXDETECT_REF[1] origin:064-gtp-channel-conf 03_292 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_RXDETECT_REF[2] origin:064-gtp-channel-conf 02_293 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_XCLK_SEL.TXUSR origin:064-gtp-channel-conf 03_11 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_CLK25_DIV[0] origin:064-gtp-channel-conf 02_144 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_CLK25_DIV[1] origin:064-gtp-channel-conf 03_144 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_CLK25_DIV[2] origin:064-gtp-channel-conf 02_145 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_CLK25_DIV[3] origin:064-gtp-channel-conf 03_145 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_CLK25_DIV[4] origin:064-gtp-channel-conf 02_146 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_DEEMPH0[0] origin:064-gtp-channel-conf 02_272 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_DEEMPH0[1] origin:064-gtp-channel-conf 03_272 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_DEEMPH0[2] origin:064-gtp-channel-conf 02_273 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_DEEMPH0[3] origin:064-gtp-channel-conf 03_273 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_DEEMPH0[4] origin:064-gtp-channel-conf 02_274 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_DEEMPH0[5] origin:064-gtp-channel-conf 03_274 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_DEEMPH1[0] origin:064-gtp-channel-conf 02_276 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_DEEMPH1[1] origin:064-gtp-channel-conf 03_276 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_DEEMPH1[2] origin:064-gtp-channel-conf 02_277 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_DEEMPH1[3] origin:064-gtp-channel-conf 03_277 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_DEEMPH1[4] origin:064-gtp-channel-conf 02_278 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TX_DEEMPH1[5] origin:064-gtp-channel-conf 03_278 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXBUF_EN origin:064-gtp-channel-conf 00_231 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXBUF_RESET_ON_RATE_CHANGE origin:064-gtp-channel-conf 01_231 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXDLY_CFG[0] origin:064-gtp-channel-conf 02_80 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXDLY_CFG[1] origin:064-gtp-channel-conf 03_80 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXDLY_CFG[2] origin:064-gtp-channel-conf 02_81 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXDLY_CFG[3] origin:064-gtp-channel-conf 03_81 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXDLY_CFG[4] origin:064-gtp-channel-conf 02_82 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXDLY_CFG[5] origin:064-gtp-channel-conf 03_82 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXDLY_CFG[6] origin:064-gtp-channel-conf 02_83 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXDLY_CFG[7] origin:064-gtp-channel-conf 03_83 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXDLY_CFG[8] origin:064-gtp-channel-conf 02_84 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXDLY_CFG[9] origin:064-gtp-channel-conf 03_84 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXDLY_CFG[10] origin:064-gtp-channel-conf 02_85 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXDLY_CFG[11] origin:064-gtp-channel-conf 03_85 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXDLY_CFG[12] origin:064-gtp-channel-conf 02_86 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXDLY_CFG[13] origin:064-gtp-channel-conf 03_86 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXDLY_CFG[14] origin:064-gtp-channel-conf 02_87 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXDLY_CFG[15] origin:064-gtp-channel-conf 03_87 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXDLY_LCFG[0] origin:064-gtp-channel-conf 02_568 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXDLY_LCFG[1] origin:064-gtp-channel-conf 03_568 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXDLY_LCFG[2] origin:064-gtp-channel-conf 02_569 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXDLY_LCFG[3] origin:064-gtp-channel-conf 03_569 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXDLY_LCFG[4] origin:064-gtp-channel-conf 02_570 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXDLY_LCFG[5] origin:064-gtp-channel-conf 03_570 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXDLY_LCFG[6] origin:064-gtp-channel-conf 02_571 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXDLY_LCFG[7] origin:064-gtp-channel-conf 03_571 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXDLY_LCFG[8] origin:064-gtp-channel-conf 02_572 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXDLY_TAP_CFG[0] origin:064-gtp-channel-conf 02_88 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXDLY_TAP_CFG[1] origin:064-gtp-channel-conf 03_88 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXDLY_TAP_CFG[2] origin:064-gtp-channel-conf 02_89 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXDLY_TAP_CFG[3] origin:064-gtp-channel-conf 03_89 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXDLY_TAP_CFG[4] origin:064-gtp-channel-conf 02_90 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXDLY_TAP_CFG[5] origin:064-gtp-channel-conf 03_90 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXDLY_TAP_CFG[6] origin:064-gtp-channel-conf 02_91 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXDLY_TAP_CFG[7] origin:064-gtp-channel-conf 03_91 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXDLY_TAP_CFG[8] origin:064-gtp-channel-conf 02_92 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXDLY_TAP_CFG[9] origin:064-gtp-channel-conf 03_92 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXDLY_TAP_CFG[10] origin:064-gtp-channel-conf 02_93 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXDLY_TAP_CFG[11] origin:064-gtp-channel-conf 03_93 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXDLY_TAP_CFG[12] origin:064-gtp-channel-conf 02_94 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXDLY_TAP_CFG[13] origin:064-gtp-channel-conf 03_94 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXDLY_TAP_CFG[14] origin:064-gtp-channel-conf 02_95 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXDLY_TAP_CFG[15] origin:064-gtp-channel-conf 03_95 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXGEARBOX_EN origin:064-gtp-channel-conf 01_226 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXOOB_CFG[0] origin:064-gtp-channel-conf 03_20 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXOUT_DIV[0] origin:064-gtp-channel-conf 02_386 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXOUT_DIV[1] origin:064-gtp-channel-conf 03_386 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPCSRESET_TIME[0] origin:064-gtp-channel-conf 01_130 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPCSRESET_TIME[1] origin:064-gtp-channel-conf 00_131 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPCSRESET_TIME[2] origin:064-gtp-channel-conf 01_131 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPCSRESET_TIME[3] origin:064-gtp-channel-conf 00_132 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPCSRESET_TIME[4] origin:064-gtp-channel-conf 01_132 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPH_CFG[0] origin:064-gtp-channel-conf 02_96 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPH_CFG[1] origin:064-gtp-channel-conf 03_96 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPH_CFG[2] origin:064-gtp-channel-conf 02_97 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPH_CFG[3] origin:064-gtp-channel-conf 03_97 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPH_CFG[4] origin:064-gtp-channel-conf 02_98 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPH_CFG[5] origin:064-gtp-channel-conf 03_98 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPH_CFG[6] origin:064-gtp-channel-conf 02_99 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPH_CFG[7] origin:064-gtp-channel-conf 03_99 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPH_CFG[8] origin:064-gtp-channel-conf 02_100 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPH_CFG[9] origin:064-gtp-channel-conf 03_100 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPH_CFG[10] origin:064-gtp-channel-conf 02_101 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPH_CFG[11] origin:064-gtp-channel-conf 03_101 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPH_CFG[12] origin:064-gtp-channel-conf 02_102 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPH_CFG[13] origin:064-gtp-channel-conf 03_102 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPH_CFG[14] origin:064-gtp-channel-conf 02_103 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPH_CFG[15] origin:064-gtp-channel-conf 03_103 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPH_MONITOR_SEL[0] origin:064-gtp-channel-conf 02_108 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPH_MONITOR_SEL[1] origin:064-gtp-channel-conf 03_108 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPH_MONITOR_SEL[2] origin:064-gtp-channel-conf 02_109 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPH_MONITOR_SEL[3] origin:064-gtp-channel-conf 03_109 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPH_MONITOR_SEL[4] origin:064-gtp-channel-conf 02_110 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPHDLY_CFG[0] origin:064-gtp-channel-conf 02_64 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPHDLY_CFG[1] origin:064-gtp-channel-conf 03_64 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPHDLY_CFG[2] origin:064-gtp-channel-conf 02_65 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPHDLY_CFG[3] origin:064-gtp-channel-conf 03_65 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPHDLY_CFG[4] origin:064-gtp-channel-conf 02_66 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPHDLY_CFG[5] origin:064-gtp-channel-conf 03_66 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPHDLY_CFG[6] origin:064-gtp-channel-conf 02_67 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPHDLY_CFG[7] origin:064-gtp-channel-conf 03_67 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPHDLY_CFG[8] origin:064-gtp-channel-conf 02_68 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPHDLY_CFG[9] origin:064-gtp-channel-conf 03_68 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPHDLY_CFG[10] origin:064-gtp-channel-conf 02_69 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPHDLY_CFG[11] origin:064-gtp-channel-conf 03_69 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPHDLY_CFG[12] origin:064-gtp-channel-conf 02_70 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPHDLY_CFG[13] origin:064-gtp-channel-conf 03_70 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPHDLY_CFG[14] origin:064-gtp-channel-conf 02_71 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPHDLY_CFG[15] origin:064-gtp-channel-conf 03_71 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPHDLY_CFG[16] origin:064-gtp-channel-conf 02_72 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPHDLY_CFG[17] origin:064-gtp-channel-conf 03_72 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPHDLY_CFG[18] origin:064-gtp-channel-conf 02_73 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPHDLY_CFG[19] origin:064-gtp-channel-conf 03_73 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPHDLY_CFG[20] origin:064-gtp-channel-conf 02_74 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPHDLY_CFG[21] origin:064-gtp-channel-conf 03_74 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPHDLY_CFG[22] origin:064-gtp-channel-conf 02_75 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPHDLY_CFG[23] origin:064-gtp-channel-conf 03_75 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPI_GREY_SEL[0] origin:064-gtp-channel-conf 03_498 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPI_INVSTROBE_SEL[0] origin:064-gtp-channel-conf 02_498 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPI_PPM_CFG[0] origin:064-gtp-channel-conf 02_488 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPI_PPM_CFG[1] origin:064-gtp-channel-conf 03_488 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPI_PPM_CFG[2] origin:064-gtp-channel-conf 02_489 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPI_PPM_CFG[3] origin:064-gtp-channel-conf 03_489 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPI_PPM_CFG[4] origin:064-gtp-channel-conf 02_490 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPI_PPM_CFG[5] origin:064-gtp-channel-conf 03_490 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPI_PPM_CFG[6] origin:064-gtp-channel-conf 02_491 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPI_PPM_CFG[7] origin:064-gtp-channel-conf 03_491 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPI_PPMCLK_SEL.TXUSRCLK2 origin:064-gtp-channel-conf 03_497 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPI_SYNFREQ_PPM[0] origin:064-gtp-channel-conf 02_496 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPI_SYNFREQ_PPM[1] origin:064-gtp-channel-conf 03_496 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPI_SYNFREQ_PPM[2] origin:064-gtp-channel-conf 02_497 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPI_CFG0[0] origin:064-gtp-channel-conf 02_40 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPI_CFG0[1] origin:064-gtp-channel-conf 03_40 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPI_CFG1[0] origin:064-gtp-channel-conf 02_41 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPI_CFG1[1] origin:064-gtp-channel-conf 03_41 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPI_CFG2[0] origin:064-gtp-channel-conf 02_42 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPI_CFG2[1] origin:064-gtp-channel-conf 03_42 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPI_CFG3[0] origin:064-gtp-channel-conf 02_43 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPI_CFG4[0] origin:064-gtp-channel-conf 03_43 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPI_CFG5[0] origin:064-gtp-channel-conf 02_44 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPI_CFG5[1] origin:064-gtp-channel-conf 03_44 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPI_CFG5[2] origin:064-gtp-channel-conf 02_45 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPMARESET_TIME[0] origin:064-gtp-channel-conf 00_128 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPMARESET_TIME[1] origin:064-gtp-channel-conf 01_128 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPMARESET_TIME[2] origin:064-gtp-channel-conf 00_129 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPMARESET_TIME[3] origin:064-gtp-channel-conf 01_129 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXPMARESET_TIME[4] origin:064-gtp-channel-conf 00_130 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXSYNC_MULTILANE[0] origin:064-gtp-channel-conf 01_133 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXSYNC_OVRD[0] origin:064-gtp-channel-conf 00_135 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.TXSYNC_SKIP_DA[0] origin:064-gtp-channel-conf 00_134 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.UCODEER_CLR[0] origin:064-gtp-channel-conf 01_00 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.USE_PCS_CLK_PHASE_SEL[0] origin:064-gtp-channel-conf 02_463 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ZINV_DMONITORCLK origin:064-gtp-channel-conf 02_13 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ZINV_DRPCLK origin:064-gtp-channel-conf 02_00 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ZINV_RXUSRCLK origin:064-gtp-channel-conf 03_01 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ZINV_SIGVALIDCLK origin:064-gtp-channel-conf 03_13 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ZINV_TXPHDLYTSTCLK origin:064-gtp-channel-conf 02_03 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ZINV_TXUSRCLK origin:064-gtp-channel-conf 03_04 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ZINV_CLKRSVD0 origin:064-gtp-channel-conf 02_23 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ZINV_CLKRSVD1 origin:064-gtp-channel-conf 03_23 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ZINV_RXUSRCLK2 origin:064-gtp-channel-conf 02_02 -GTP_CHANNEL_2_MID_RIGHT.GTPE2.ZINV_TXUSRCLK2 origin:064-gtp-channel-conf 02_05 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ACJTAG_DEBUG_MODE[0] origin:064-gtp-channel-conf 00_07 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ACJTAG_MODE[0] origin:064-gtp-channel-conf 01_06 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ACJTAG_RESET[0] origin:064-gtp-channel-conf 01_07 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[0] origin:064-gtp-channel-conf 02_464 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[1] origin:064-gtp-channel-conf 03_464 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[2] origin:064-gtp-channel-conf 02_465 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[3] origin:064-gtp-channel-conf 03_465 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[4] origin:064-gtp-channel-conf 02_466 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[5] origin:064-gtp-channel-conf 03_466 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[6] origin:064-gtp-channel-conf 02_467 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[7] origin:064-gtp-channel-conf 03_467 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[8] origin:064-gtp-channel-conf 02_468 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[9] origin:064-gtp-channel-conf 03_468 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[10] origin:064-gtp-channel-conf 02_469 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[11] origin:064-gtp-channel-conf 03_469 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[12] origin:064-gtp-channel-conf 02_470 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[13] origin:064-gtp-channel-conf 03_470 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[14] origin:064-gtp-channel-conf 02_471 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[15] origin:064-gtp-channel-conf 03_471 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[16] origin:064-gtp-channel-conf 02_472 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[17] origin:064-gtp-channel-conf 03_472 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[18] origin:064-gtp-channel-conf 02_473 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[19] origin:064-gtp-channel-conf 03_473 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ALIGN_COMMA_DOUBLE origin:064-gtp-channel-conf 00_522 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[0] origin:064-gtp-channel-conf 00_496 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[1] origin:064-gtp-channel-conf 01_496 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[2] origin:064-gtp-channel-conf 00_497 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[3] origin:064-gtp-channel-conf 01_497 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[4] origin:064-gtp-channel-conf 00_498 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[5] origin:064-gtp-channel-conf 01_498 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[6] origin:064-gtp-channel-conf 00_499 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[7] origin:064-gtp-channel-conf 01_499 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[8] origin:064-gtp-channel-conf 00_500 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[9] origin:064-gtp-channel-conf 01_500 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ALIGN_COMMA_WORD[0] origin:064-gtp-channel-conf 01_526 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ALIGN_COMMA_WORD[1] origin:064-gtp-channel-conf 00_527 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ALIGN_MCOMMA_DET origin:064-gtp-channel-conf 00_523 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[0] origin:064-gtp-channel-conf 00_504 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[1] origin:064-gtp-channel-conf 01_504 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[2] origin:064-gtp-channel-conf 00_505 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[3] origin:064-gtp-channel-conf 01_505 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[4] origin:064-gtp-channel-conf 00_506 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[5] origin:064-gtp-channel-conf 01_506 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[6] origin:064-gtp-channel-conf 00_507 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[7] origin:064-gtp-channel-conf 01_507 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[8] origin:064-gtp-channel-conf 00_508 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[9] origin:064-gtp-channel-conf 01_508 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ALIGN_PCOMMA_DET origin:064-gtp-channel-conf 01_523 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[0] origin:064-gtp-channel-conf 00_512 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[1] origin:064-gtp-channel-conf 01_512 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[2] origin:064-gtp-channel-conf 00_513 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[3] origin:064-gtp-channel-conf 01_513 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[4] origin:064-gtp-channel-conf 00_514 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[5] origin:064-gtp-channel-conf 01_514 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[6] origin:064-gtp-channel-conf 00_515 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[7] origin:064-gtp-channel-conf 01_515 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[8] origin:064-gtp-channel-conf 00_516 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[9] origin:064-gtp-channel-conf 01_516 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CBCC_DATA_SOURCE_SEL.DECODED origin:064-gtp-channel-conf 01_661 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[0] origin:064-gtp-channel-conf 02_392 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[1] origin:064-gtp-channel-conf 03_392 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[2] origin:064-gtp-channel-conf 02_393 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[3] origin:064-gtp-channel-conf 03_393 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[4] origin:064-gtp-channel-conf 02_394 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[5] origin:064-gtp-channel-conf 03_394 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[6] origin:064-gtp-channel-conf 02_395 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[7] origin:064-gtp-channel-conf 03_395 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[8] origin:064-gtp-channel-conf 02_396 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[9] origin:064-gtp-channel-conf 03_396 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[10] origin:064-gtp-channel-conf 02_397 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[11] origin:064-gtp-channel-conf 03_397 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[12] origin:064-gtp-channel-conf 02_398 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[13] origin:064-gtp-channel-conf 03_398 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[14] origin:064-gtp-channel-conf 02_399 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[15] origin:064-gtp-channel-conf 03_399 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[16] origin:064-gtp-channel-conf 02_400 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[17] origin:064-gtp-channel-conf 03_400 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[18] origin:064-gtp-channel-conf 02_401 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[19] origin:064-gtp-channel-conf 03_401 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[20] origin:064-gtp-channel-conf 02_402 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[21] origin:064-gtp-channel-conf 03_402 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[22] origin:064-gtp-channel-conf 02_403 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[23] origin:064-gtp-channel-conf 03_403 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[24] origin:064-gtp-channel-conf 02_404 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[25] origin:064-gtp-channel-conf 03_404 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[26] origin:064-gtp-channel-conf 02_405 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[27] origin:064-gtp-channel-conf 03_405 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[28] origin:064-gtp-channel-conf 02_406 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[29] origin:064-gtp-channel-conf 03_406 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[30] origin:064-gtp-channel-conf 02_407 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[31] origin:064-gtp-channel-conf 03_407 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[32] origin:064-gtp-channel-conf 02_408 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[33] origin:064-gtp-channel-conf 03_408 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[34] origin:064-gtp-channel-conf 02_409 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[35] origin:064-gtp-channel-conf 03_409 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[36] origin:064-gtp-channel-conf 02_410 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[37] origin:064-gtp-channel-conf 03_410 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[38] origin:064-gtp-channel-conf 02_411 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[39] origin:064-gtp-channel-conf 03_411 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[40] origin:064-gtp-channel-conf 02_412 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[41] origin:064-gtp-channel-conf 03_412 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[42] origin:064-gtp-channel-conf 02_413 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG2[0] origin:064-gtp-channel-conf 02_459 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG2[1] origin:064-gtp-channel-conf 03_459 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG2[2] origin:064-gtp-channel-conf 02_460 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG2[3] origin:064-gtp-channel-conf 03_460 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG2[4] origin:064-gtp-channel-conf 02_461 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG2[5] origin:064-gtp-channel-conf 03_461 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG2[6] origin:064-gtp-channel-conf 02_462 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG3[0] origin:064-gtp-channel-conf 02_416 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG3[1] origin:064-gtp-channel-conf 03_416 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG3[2] origin:064-gtp-channel-conf 02_417 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG3[3] origin:064-gtp-channel-conf 03_417 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG3[4] origin:064-gtp-channel-conf 02_418 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG3[5] origin:064-gtp-channel-conf 03_418 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG3[6] origin:064-gtp-channel-conf 02_419 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG4[0] origin:064-gtp-channel-conf 03_438 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG5[0] origin:064-gtp-channel-conf 02_429 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG5[1] origin:064-gtp-channel-conf 03_429 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG6[0] origin:064-gtp-channel-conf 03_436 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG6[1] origin:064-gtp-channel-conf 02_437 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG6[2] origin:064-gtp-channel-conf 03_437 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG6[3] origin:064-gtp-channel-conf 02_438 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_KEEP_ALIGN origin:064-gtp-channel-conf 01_631 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_MAX_SKEW[0] origin:064-gtp-channel-conf 00_670 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_MAX_SKEW[1] origin:064-gtp-channel-conf 01_670 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_MAX_SKEW[2] origin:064-gtp-channel-conf 00_671 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_MAX_SKEW[3] origin:064-gtp-channel-conf 01_671 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[0] origin:064-gtp-channel-conf 00_608 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[1] origin:064-gtp-channel-conf 01_608 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[2] origin:064-gtp-channel-conf 00_609 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[3] origin:064-gtp-channel-conf 01_609 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[4] origin:064-gtp-channel-conf 00_610 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[5] origin:064-gtp-channel-conf 01_610 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[6] origin:064-gtp-channel-conf 00_611 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[7] origin:064-gtp-channel-conf 01_611 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[8] origin:064-gtp-channel-conf 00_612 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[9] origin:064-gtp-channel-conf 01_612 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[0] origin:064-gtp-channel-conf 00_616 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[1] origin:064-gtp-channel-conf 01_616 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[2] origin:064-gtp-channel-conf 00_617 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[3] origin:064-gtp-channel-conf 01_617 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[4] origin:064-gtp-channel-conf 00_618 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[5] origin:064-gtp-channel-conf 01_618 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[6] origin:064-gtp-channel-conf 00_619 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[7] origin:064-gtp-channel-conf 01_619 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[8] origin:064-gtp-channel-conf 00_620 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[9] origin:064-gtp-channel-conf 01_620 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[0] origin:064-gtp-channel-conf 00_624 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[1] origin:064-gtp-channel-conf 01_624 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[2] origin:064-gtp-channel-conf 00_625 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[3] origin:064-gtp-channel-conf 01_625 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[4] origin:064-gtp-channel-conf 00_626 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[5] origin:064-gtp-channel-conf 01_626 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[6] origin:064-gtp-channel-conf 00_627 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[7] origin:064-gtp-channel-conf 01_627 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[8] origin:064-gtp-channel-conf 00_628 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[9] origin:064-gtp-channel-conf 01_628 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[0] origin:064-gtp-channel-conf 00_632 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[1] origin:064-gtp-channel-conf 01_632 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[2] origin:064-gtp-channel-conf 00_633 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[3] origin:064-gtp-channel-conf 01_633 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[4] origin:064-gtp-channel-conf 00_634 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[5] origin:064-gtp-channel-conf 01_634 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[6] origin:064-gtp-channel-conf 00_635 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[7] origin:064-gtp-channel-conf 01_635 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[8] origin:064-gtp-channel-conf 00_636 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[9] origin:064-gtp-channel-conf 01_636 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_ENABLE[0] origin:064-gtp-channel-conf 00_614 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_ENABLE[1] origin:064-gtp-channel-conf 01_614 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_ENABLE[2] origin:064-gtp-channel-conf 00_615 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_ENABLE[3] origin:064-gtp-channel-conf 01_615 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[0] origin:064-gtp-channel-conf 00_640 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[1] origin:064-gtp-channel-conf 01_640 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[2] origin:064-gtp-channel-conf 00_641 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[3] origin:064-gtp-channel-conf 01_641 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[4] origin:064-gtp-channel-conf 00_642 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[5] origin:064-gtp-channel-conf 01_642 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[6] origin:064-gtp-channel-conf 00_643 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[7] origin:064-gtp-channel-conf 01_643 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[8] origin:064-gtp-channel-conf 00_644 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[9] origin:064-gtp-channel-conf 01_644 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[0] origin:064-gtp-channel-conf 00_648 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[1] origin:064-gtp-channel-conf 01_648 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[2] origin:064-gtp-channel-conf 00_649 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[3] origin:064-gtp-channel-conf 01_649 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[4] origin:064-gtp-channel-conf 00_650 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[5] origin:064-gtp-channel-conf 01_650 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[6] origin:064-gtp-channel-conf 00_651 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[7] origin:064-gtp-channel-conf 01_651 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[8] origin:064-gtp-channel-conf 00_652 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[9] origin:064-gtp-channel-conf 01_652 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[0] origin:064-gtp-channel-conf 00_656 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[1] origin:064-gtp-channel-conf 01_656 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[2] origin:064-gtp-channel-conf 00_657 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[3] origin:064-gtp-channel-conf 01_657 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[4] origin:064-gtp-channel-conf 00_658 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[5] origin:064-gtp-channel-conf 01_658 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[6] origin:064-gtp-channel-conf 00_659 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[7] origin:064-gtp-channel-conf 01_659 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[8] origin:064-gtp-channel-conf 00_660 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[9] origin:064-gtp-channel-conf 01_660 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[0] origin:064-gtp-channel-conf 00_664 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[1] origin:064-gtp-channel-conf 01_664 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[2] origin:064-gtp-channel-conf 00_665 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[3] origin:064-gtp-channel-conf 01_665 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[4] origin:064-gtp-channel-conf 00_666 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[5] origin:064-gtp-channel-conf 01_666 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[6] origin:064-gtp-channel-conf 00_667 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[7] origin:064-gtp-channel-conf 01_667 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[8] origin:064-gtp-channel-conf 00_668 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[9] origin:064-gtp-channel-conf 01_668 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_ENABLE[0] origin:064-gtp-channel-conf 00_646 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_ENABLE[1] origin:064-gtp-channel-conf 01_646 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_ENABLE[2] origin:064-gtp-channel-conf 00_647 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_ENABLE[3] origin:064-gtp-channel-conf 01_647 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_USE origin:064-gtp-channel-conf 01_645 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_LEN[0] origin:064-gtp-channel-conf 00_623 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_LEN[1] origin:064-gtp-channel-conf 01_623 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COMMON_SWING[0] origin:064-gtp-channel-conf 03_311 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_KEEP_IDLE origin:064-gtp-channel-conf 00_591 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_MAX_LAT[0] origin:064-gtp-channel-conf 00_557 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_MAX_LAT[1] origin:064-gtp-channel-conf 01_557 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_MAX_LAT[2] origin:064-gtp-channel-conf 00_558 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_MAX_LAT[3] origin:064-gtp-channel-conf 01_558 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_MAX_LAT[4] origin:064-gtp-channel-conf 00_559 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_MAX_LAT[5] origin:064-gtp-channel-conf 01_559 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_MIN_LAT[0] origin:064-gtp-channel-conf 00_565 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_MIN_LAT[1] origin:064-gtp-channel-conf 01_565 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_MIN_LAT[2] origin:064-gtp-channel-conf 00_566 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_MIN_LAT[3] origin:064-gtp-channel-conf 01_566 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_MIN_LAT[4] origin:064-gtp-channel-conf 00_567 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_MIN_LAT[5] origin:064-gtp-channel-conf 01_567 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_PRECEDENCE origin:064-gtp-channel-conf 00_590 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_REPEAT_WAIT[0] origin:064-gtp-channel-conf 00_573 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_REPEAT_WAIT[1] origin:064-gtp-channel-conf 01_573 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_REPEAT_WAIT[2] origin:064-gtp-channel-conf 00_574 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_REPEAT_WAIT[3] origin:064-gtp-channel-conf 01_574 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_REPEAT_WAIT[4] origin:064-gtp-channel-conf 00_575 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[0] origin:064-gtp-channel-conf 00_544 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[1] origin:064-gtp-channel-conf 01_544 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[2] origin:064-gtp-channel-conf 00_545 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[3] origin:064-gtp-channel-conf 01_545 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[4] origin:064-gtp-channel-conf 00_546 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[5] origin:064-gtp-channel-conf 01_546 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[6] origin:064-gtp-channel-conf 00_547 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[7] origin:064-gtp-channel-conf 01_547 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[8] origin:064-gtp-channel-conf 00_548 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[9] origin:064-gtp-channel-conf 01_548 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[0] origin:064-gtp-channel-conf 00_552 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[1] origin:064-gtp-channel-conf 01_552 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[2] origin:064-gtp-channel-conf 00_553 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[3] origin:064-gtp-channel-conf 01_553 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[4] origin:064-gtp-channel-conf 00_554 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[5] origin:064-gtp-channel-conf 01_554 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[6] origin:064-gtp-channel-conf 00_555 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[7] origin:064-gtp-channel-conf 01_555 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[8] origin:064-gtp-channel-conf 00_556 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[9] origin:064-gtp-channel-conf 01_556 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[0] origin:064-gtp-channel-conf 00_560 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[1] origin:064-gtp-channel-conf 01_560 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[2] origin:064-gtp-channel-conf 00_561 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[3] origin:064-gtp-channel-conf 01_561 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[4] origin:064-gtp-channel-conf 00_562 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[5] origin:064-gtp-channel-conf 01_562 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[6] origin:064-gtp-channel-conf 00_563 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[7] origin:064-gtp-channel-conf 01_563 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[8] origin:064-gtp-channel-conf 00_564 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[9] origin:064-gtp-channel-conf 01_564 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[0] origin:064-gtp-channel-conf 00_568 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[1] origin:064-gtp-channel-conf 01_568 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[2] origin:064-gtp-channel-conf 00_569 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[3] origin:064-gtp-channel-conf 01_569 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[4] origin:064-gtp-channel-conf 00_570 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[5] origin:064-gtp-channel-conf 01_570 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[6] origin:064-gtp-channel-conf 00_571 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[7] origin:064-gtp-channel-conf 01_571 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[8] origin:064-gtp-channel-conf 00_572 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[9] origin:064-gtp-channel-conf 01_572 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_ENABLE[0] origin:064-gtp-channel-conf 00_549 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_ENABLE[1] origin:064-gtp-channel-conf 01_549 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_ENABLE[2] origin:064-gtp-channel-conf 00_550 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_ENABLE[3] origin:064-gtp-channel-conf 01_550 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[0] origin:064-gtp-channel-conf 00_576 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[1] origin:064-gtp-channel-conf 01_576 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[2] origin:064-gtp-channel-conf 00_577 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[3] origin:064-gtp-channel-conf 01_577 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[4] origin:064-gtp-channel-conf 00_578 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[5] origin:064-gtp-channel-conf 01_578 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[6] origin:064-gtp-channel-conf 00_579 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[7] origin:064-gtp-channel-conf 01_579 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[8] origin:064-gtp-channel-conf 00_580 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[9] origin:064-gtp-channel-conf 01_580 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[0] origin:064-gtp-channel-conf 00_584 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[1] origin:064-gtp-channel-conf 01_584 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[2] origin:064-gtp-channel-conf 00_585 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[3] origin:064-gtp-channel-conf 01_585 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[4] origin:064-gtp-channel-conf 00_586 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[5] origin:064-gtp-channel-conf 01_586 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[6] origin:064-gtp-channel-conf 00_587 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[7] origin:064-gtp-channel-conf 01_587 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[8] origin:064-gtp-channel-conf 00_588 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[9] origin:064-gtp-channel-conf 01_588 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[0] origin:064-gtp-channel-conf 00_592 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[1] origin:064-gtp-channel-conf 01_592 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[2] origin:064-gtp-channel-conf 00_593 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[3] origin:064-gtp-channel-conf 01_593 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[4] origin:064-gtp-channel-conf 00_594 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[5] origin:064-gtp-channel-conf 01_594 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[6] origin:064-gtp-channel-conf 00_595 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[7] origin:064-gtp-channel-conf 01_595 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[8] origin:064-gtp-channel-conf 00_596 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[9] origin:064-gtp-channel-conf 01_596 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[0] origin:064-gtp-channel-conf 00_600 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[1] origin:064-gtp-channel-conf 01_600 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[2] origin:064-gtp-channel-conf 00_601 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[3] origin:064-gtp-channel-conf 01_601 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[4] origin:064-gtp-channel-conf 00_602 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[5] origin:064-gtp-channel-conf 01_602 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[6] origin:064-gtp-channel-conf 00_603 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[7] origin:064-gtp-channel-conf 01_603 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[8] origin:064-gtp-channel-conf 00_604 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[9] origin:064-gtp-channel-conf 01_604 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_ENABLE[0] origin:064-gtp-channel-conf 00_581 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_ENABLE[1] origin:064-gtp-channel-conf 01_581 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_ENABLE[2] origin:064-gtp-channel-conf 00_582 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_ENABLE[3] origin:064-gtp-channel-conf 01_582 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_USE origin:064-gtp-channel-conf 00_583 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_LEN[0] origin:064-gtp-channel-conf 00_589 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_LEN[1] origin:064-gtp-channel-conf 01_589 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.CLK_CORRECT_USE origin:064-gtp-channel-conf 00_551 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.DEC_MCOMMA_DETECT origin:064-gtp-channel-conf 01_494 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.DEC_PCOMMA_DETECT origin:064-gtp-channel-conf 00_495 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.DEC_VALID_COMMA_ONLY origin:064-gtp-channel-conf 00_494 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[0] origin:064-gtp-channel-conf 02_368 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[1] origin:064-gtp-channel-conf 03_368 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[2] origin:064-gtp-channel-conf 02_369 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[3] origin:064-gtp-channel-conf 03_369 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[4] origin:064-gtp-channel-conf 02_370 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[5] origin:064-gtp-channel-conf 03_370 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[6] origin:064-gtp-channel-conf 02_371 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[7] origin:064-gtp-channel-conf 03_371 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[8] origin:064-gtp-channel-conf 02_372 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[9] origin:064-gtp-channel-conf 03_372 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[10] origin:064-gtp-channel-conf 02_373 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[11] origin:064-gtp-channel-conf 03_373 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[12] origin:064-gtp-channel-conf 02_374 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[13] origin:064-gtp-channel-conf 03_374 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[14] origin:064-gtp-channel-conf 02_375 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[15] origin:064-gtp-channel-conf 03_375 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[16] origin:064-gtp-channel-conf 02_376 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[17] origin:064-gtp-channel-conf 03_376 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[18] origin:064-gtp-channel-conf 02_377 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[19] origin:064-gtp-channel-conf 03_377 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[20] origin:064-gtp-channel-conf 02_378 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[21] origin:064-gtp-channel-conf 03_378 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[22] origin:064-gtp-channel-conf 02_379 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[23] origin:064-gtp-channel-conf 03_379 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_CLK_PHASE_SEL[0] origin:064-gtp-channel-conf 03_463 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_CONTROL[0] origin:064-gtp-channel-conf 00_488 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_CONTROL[1] origin:064-gtp-channel-conf 01_488 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_CONTROL[2] origin:064-gtp-channel-conf 00_489 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_CONTROL[3] origin:064-gtp-channel-conf 01_489 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_CONTROL[4] origin:064-gtp-channel-conf 00_490 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_CONTROL[5] origin:064-gtp-channel-conf 01_490 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_ERRDET_EN origin:064-gtp-channel-conf 01_492 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_EYE_SCAN_EN origin:064-gtp-channel-conf 00_492 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_HORZ_OFFSET[0] origin:064-gtp-channel-conf 00_480 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_HORZ_OFFSET[1] origin:064-gtp-channel-conf 01_480 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_HORZ_OFFSET[2] origin:064-gtp-channel-conf 00_481 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_HORZ_OFFSET[3] origin:064-gtp-channel-conf 01_481 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_HORZ_OFFSET[4] origin:064-gtp-channel-conf 00_482 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_HORZ_OFFSET[5] origin:064-gtp-channel-conf 01_482 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_HORZ_OFFSET[6] origin:064-gtp-channel-conf 00_483 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_HORZ_OFFSET[7] origin:064-gtp-channel-conf 01_483 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_HORZ_OFFSET[8] origin:064-gtp-channel-conf 00_484 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_HORZ_OFFSET[9] origin:064-gtp-channel-conf 01_484 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_HORZ_OFFSET[10] origin:064-gtp-channel-conf 00_485 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_HORZ_OFFSET[11] origin:064-gtp-channel-conf 01_485 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_PMA_CFG[0] origin:064-gtp-channel-conf 02_624 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_PMA_CFG[1] origin:064-gtp-channel-conf 03_624 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_PMA_CFG[2] origin:064-gtp-channel-conf 02_625 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_PMA_CFG[3] origin:064-gtp-channel-conf 03_625 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_PMA_CFG[4] origin:064-gtp-channel-conf 02_626 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_PMA_CFG[5] origin:064-gtp-channel-conf 03_626 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_PMA_CFG[6] origin:064-gtp-channel-conf 02_627 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_PMA_CFG[7] origin:064-gtp-channel-conf 03_627 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_PMA_CFG[8] origin:064-gtp-channel-conf 02_628 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_PMA_CFG[9] origin:064-gtp-channel-conf 03_628 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_PRESCALE[0] origin:064-gtp-channel-conf 01_477 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_PRESCALE[1] origin:064-gtp-channel-conf 00_478 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_PRESCALE[2] origin:064-gtp-channel-conf 01_478 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_PRESCALE[3] origin:064-gtp-channel-conf 00_479 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_PRESCALE[4] origin:064-gtp-channel-conf 01_479 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[0] origin:064-gtp-channel-conf 00_392 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[1] origin:064-gtp-channel-conf 01_392 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[2] origin:064-gtp-channel-conf 00_393 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[3] origin:064-gtp-channel-conf 01_393 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[4] origin:064-gtp-channel-conf 00_394 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[5] origin:064-gtp-channel-conf 01_394 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[6] origin:064-gtp-channel-conf 00_395 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[7] origin:064-gtp-channel-conf 01_395 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[8] origin:064-gtp-channel-conf 00_396 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[9] origin:064-gtp-channel-conf 01_396 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[10] origin:064-gtp-channel-conf 00_397 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[11] origin:064-gtp-channel-conf 01_397 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[12] origin:064-gtp-channel-conf 00_398 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[13] origin:064-gtp-channel-conf 01_398 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[14] origin:064-gtp-channel-conf 00_399 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[15] origin:064-gtp-channel-conf 01_399 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[16] origin:064-gtp-channel-conf 00_400 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[17] origin:064-gtp-channel-conf 01_400 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[18] origin:064-gtp-channel-conf 00_401 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[19] origin:064-gtp-channel-conf 01_401 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[20] origin:064-gtp-channel-conf 00_402 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[21] origin:064-gtp-channel-conf 01_402 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[22] origin:064-gtp-channel-conf 00_403 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[23] origin:064-gtp-channel-conf 01_403 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[24] origin:064-gtp-channel-conf 00_404 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[25] origin:064-gtp-channel-conf 01_404 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[26] origin:064-gtp-channel-conf 00_405 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[27] origin:064-gtp-channel-conf 01_405 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[28] origin:064-gtp-channel-conf 00_406 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[29] origin:064-gtp-channel-conf 01_406 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[30] origin:064-gtp-channel-conf 00_407 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[31] origin:064-gtp-channel-conf 01_407 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[32] origin:064-gtp-channel-conf 00_408 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[33] origin:064-gtp-channel-conf 01_408 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[34] origin:064-gtp-channel-conf 00_409 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[35] origin:064-gtp-channel-conf 01_409 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[36] origin:064-gtp-channel-conf 00_410 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[37] origin:064-gtp-channel-conf 01_410 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[38] origin:064-gtp-channel-conf 00_411 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[39] origin:064-gtp-channel-conf 01_411 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[40] origin:064-gtp-channel-conf 00_412 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[41] origin:064-gtp-channel-conf 01_412 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[42] origin:064-gtp-channel-conf 00_413 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[43] origin:064-gtp-channel-conf 01_413 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[44] origin:064-gtp-channel-conf 00_414 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[45] origin:064-gtp-channel-conf 01_414 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[46] origin:064-gtp-channel-conf 00_415 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[47] origin:064-gtp-channel-conf 01_415 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[48] origin:064-gtp-channel-conf 00_416 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[49] origin:064-gtp-channel-conf 01_416 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[50] origin:064-gtp-channel-conf 00_417 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[51] origin:064-gtp-channel-conf 01_417 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[52] origin:064-gtp-channel-conf 00_418 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[53] origin:064-gtp-channel-conf 01_418 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[54] origin:064-gtp-channel-conf 00_419 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[55] origin:064-gtp-channel-conf 01_419 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[56] origin:064-gtp-channel-conf 00_420 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[57] origin:064-gtp-channel-conf 01_420 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[58] origin:064-gtp-channel-conf 00_421 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[59] origin:064-gtp-channel-conf 01_421 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[60] origin:064-gtp-channel-conf 00_422 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[61] origin:064-gtp-channel-conf 01_422 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[62] origin:064-gtp-channel-conf 00_423 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[63] origin:064-gtp-channel-conf 01_423 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[64] origin:064-gtp-channel-conf 00_424 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[65] origin:064-gtp-channel-conf 01_424 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[66] origin:064-gtp-channel-conf 00_425 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[67] origin:064-gtp-channel-conf 01_425 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[68] origin:064-gtp-channel-conf 00_426 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[69] origin:064-gtp-channel-conf 01_426 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[70] origin:064-gtp-channel-conf 00_427 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[71] origin:064-gtp-channel-conf 01_427 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[72] origin:064-gtp-channel-conf 00_428 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[73] origin:064-gtp-channel-conf 01_428 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[74] origin:064-gtp-channel-conf 00_429 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[75] origin:064-gtp-channel-conf 01_429 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[76] origin:064-gtp-channel-conf 00_430 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[77] origin:064-gtp-channel-conf 01_430 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[78] origin:064-gtp-channel-conf 00_431 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[79] origin:064-gtp-channel-conf 01_431 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[0] origin:064-gtp-channel-conf 00_352 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[1] origin:064-gtp-channel-conf 01_352 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[2] origin:064-gtp-channel-conf 00_353 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[3] origin:064-gtp-channel-conf 01_353 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[4] origin:064-gtp-channel-conf 00_354 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[5] origin:064-gtp-channel-conf 01_354 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[6] origin:064-gtp-channel-conf 00_355 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[7] origin:064-gtp-channel-conf 01_355 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[8] origin:064-gtp-channel-conf 00_356 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[9] origin:064-gtp-channel-conf 01_356 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[10] origin:064-gtp-channel-conf 00_357 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[11] origin:064-gtp-channel-conf 01_357 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[12] origin:064-gtp-channel-conf 00_358 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[13] origin:064-gtp-channel-conf 01_358 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[14] origin:064-gtp-channel-conf 00_359 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[15] origin:064-gtp-channel-conf 01_359 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[16] origin:064-gtp-channel-conf 00_360 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[17] origin:064-gtp-channel-conf 01_360 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[18] origin:064-gtp-channel-conf 00_361 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[19] origin:064-gtp-channel-conf 01_361 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[20] origin:064-gtp-channel-conf 00_362 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[21] origin:064-gtp-channel-conf 01_362 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[22] origin:064-gtp-channel-conf 00_363 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[23] origin:064-gtp-channel-conf 01_363 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[24] origin:064-gtp-channel-conf 00_364 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[25] origin:064-gtp-channel-conf 01_364 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[26] origin:064-gtp-channel-conf 00_365 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[27] origin:064-gtp-channel-conf 01_365 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[28] origin:064-gtp-channel-conf 00_366 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[29] origin:064-gtp-channel-conf 01_366 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[30] origin:064-gtp-channel-conf 00_367 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[31] origin:064-gtp-channel-conf 01_367 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[32] origin:064-gtp-channel-conf 00_368 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[33] origin:064-gtp-channel-conf 01_368 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[34] origin:064-gtp-channel-conf 00_369 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[35] origin:064-gtp-channel-conf 01_369 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[36] origin:064-gtp-channel-conf 00_370 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[37] origin:064-gtp-channel-conf 01_370 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[38] origin:064-gtp-channel-conf 00_371 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[39] origin:064-gtp-channel-conf 01_371 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[40] origin:064-gtp-channel-conf 00_372 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[41] origin:064-gtp-channel-conf 01_372 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[42] origin:064-gtp-channel-conf 00_373 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[43] origin:064-gtp-channel-conf 01_373 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[44] origin:064-gtp-channel-conf 00_374 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[45] origin:064-gtp-channel-conf 01_374 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[46] origin:064-gtp-channel-conf 00_375 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[47] origin:064-gtp-channel-conf 01_375 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[48] origin:064-gtp-channel-conf 00_376 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[49] origin:064-gtp-channel-conf 01_376 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[50] origin:064-gtp-channel-conf 00_377 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[51] origin:064-gtp-channel-conf 01_377 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[52] origin:064-gtp-channel-conf 00_378 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[53] origin:064-gtp-channel-conf 01_378 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[54] origin:064-gtp-channel-conf 00_379 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[55] origin:064-gtp-channel-conf 01_379 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[56] origin:064-gtp-channel-conf 00_380 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[57] origin:064-gtp-channel-conf 01_380 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[58] origin:064-gtp-channel-conf 00_381 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[59] origin:064-gtp-channel-conf 01_381 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[60] origin:064-gtp-channel-conf 00_382 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[61] origin:064-gtp-channel-conf 01_382 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[62] origin:064-gtp-channel-conf 00_383 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[63] origin:064-gtp-channel-conf 01_383 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[64] origin:064-gtp-channel-conf 00_384 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[65] origin:064-gtp-channel-conf 01_384 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[66] origin:064-gtp-channel-conf 00_385 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[67] origin:064-gtp-channel-conf 01_385 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[68] origin:064-gtp-channel-conf 00_386 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[69] origin:064-gtp-channel-conf 01_386 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[70] origin:064-gtp-channel-conf 00_387 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[71] origin:064-gtp-channel-conf 01_387 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[72] origin:064-gtp-channel-conf 00_388 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[73] origin:064-gtp-channel-conf 01_388 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[74] origin:064-gtp-channel-conf 00_389 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[75] origin:064-gtp-channel-conf 01_389 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[76] origin:064-gtp-channel-conf 00_390 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[77] origin:064-gtp-channel-conf 01_390 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[78] origin:064-gtp-channel-conf 00_391 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[79] origin:064-gtp-channel-conf 01_391 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[0] origin:064-gtp-channel-conf 00_432 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[1] origin:064-gtp-channel-conf 01_432 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[2] origin:064-gtp-channel-conf 00_433 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[3] origin:064-gtp-channel-conf 01_433 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[4] origin:064-gtp-channel-conf 00_434 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[5] origin:064-gtp-channel-conf 01_434 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[6] origin:064-gtp-channel-conf 00_435 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[7] origin:064-gtp-channel-conf 01_435 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[8] origin:064-gtp-channel-conf 00_436 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[9] origin:064-gtp-channel-conf 01_436 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[10] origin:064-gtp-channel-conf 00_437 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[11] origin:064-gtp-channel-conf 01_437 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[12] origin:064-gtp-channel-conf 00_438 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[13] origin:064-gtp-channel-conf 01_438 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[14] origin:064-gtp-channel-conf 00_439 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[15] origin:064-gtp-channel-conf 01_439 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[16] origin:064-gtp-channel-conf 00_440 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[17] origin:064-gtp-channel-conf 01_440 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[18] origin:064-gtp-channel-conf 00_441 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[19] origin:064-gtp-channel-conf 01_441 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[20] origin:064-gtp-channel-conf 00_442 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[21] origin:064-gtp-channel-conf 01_442 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[22] origin:064-gtp-channel-conf 00_443 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[23] origin:064-gtp-channel-conf 01_443 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[24] origin:064-gtp-channel-conf 00_444 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[25] origin:064-gtp-channel-conf 01_444 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[26] origin:064-gtp-channel-conf 00_445 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[27] origin:064-gtp-channel-conf 01_445 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[28] origin:064-gtp-channel-conf 00_446 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[29] origin:064-gtp-channel-conf 01_446 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[30] origin:064-gtp-channel-conf 00_447 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[31] origin:064-gtp-channel-conf 01_447 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[32] origin:064-gtp-channel-conf 00_448 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[33] origin:064-gtp-channel-conf 01_448 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[34] origin:064-gtp-channel-conf 00_449 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[35] origin:064-gtp-channel-conf 01_449 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[36] origin:064-gtp-channel-conf 00_450 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[37] origin:064-gtp-channel-conf 01_450 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[38] origin:064-gtp-channel-conf 00_451 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[39] origin:064-gtp-channel-conf 01_451 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[40] origin:064-gtp-channel-conf 00_452 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[41] origin:064-gtp-channel-conf 01_452 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[42] origin:064-gtp-channel-conf 00_453 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[43] origin:064-gtp-channel-conf 01_453 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[44] origin:064-gtp-channel-conf 00_454 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[45] origin:064-gtp-channel-conf 01_454 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[46] origin:064-gtp-channel-conf 00_455 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[47] origin:064-gtp-channel-conf 01_455 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[48] origin:064-gtp-channel-conf 00_456 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[49] origin:064-gtp-channel-conf 01_456 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[50] origin:064-gtp-channel-conf 00_457 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[51] origin:064-gtp-channel-conf 01_457 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[52] origin:064-gtp-channel-conf 00_458 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[53] origin:064-gtp-channel-conf 01_458 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[54] origin:064-gtp-channel-conf 00_459 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[55] origin:064-gtp-channel-conf 01_459 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[56] origin:064-gtp-channel-conf 00_460 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[57] origin:064-gtp-channel-conf 01_460 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[58] origin:064-gtp-channel-conf 00_461 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[59] origin:064-gtp-channel-conf 01_461 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[60] origin:064-gtp-channel-conf 00_462 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[61] origin:064-gtp-channel-conf 01_462 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[62] origin:064-gtp-channel-conf 00_463 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[63] origin:064-gtp-channel-conf 01_463 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[64] origin:064-gtp-channel-conf 00_464 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[65] origin:064-gtp-channel-conf 01_464 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[66] origin:064-gtp-channel-conf 00_465 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[67] origin:064-gtp-channel-conf 01_465 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[68] origin:064-gtp-channel-conf 00_466 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[69] origin:064-gtp-channel-conf 01_466 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[70] origin:064-gtp-channel-conf 00_467 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[71] origin:064-gtp-channel-conf 01_467 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[72] origin:064-gtp-channel-conf 00_468 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[73] origin:064-gtp-channel-conf 01_468 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[74] origin:064-gtp-channel-conf 00_469 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[75] origin:064-gtp-channel-conf 01_469 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[76] origin:064-gtp-channel-conf 00_470 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[77] origin:064-gtp-channel-conf 01_470 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[78] origin:064-gtp-channel-conf 00_471 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[79] origin:064-gtp-channel-conf 01_471 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_VERT_OFFSET[0] origin:064-gtp-channel-conf 00_472 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_VERT_OFFSET[1] origin:064-gtp-channel-conf 01_472 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_VERT_OFFSET[2] origin:064-gtp-channel-conf 00_473 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_VERT_OFFSET[3] origin:064-gtp-channel-conf 01_473 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_VERT_OFFSET[4] origin:064-gtp-channel-conf 00_474 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_VERT_OFFSET[5] origin:064-gtp-channel-conf 01_474 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_VERT_OFFSET[6] origin:064-gtp-channel-conf 00_475 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_VERT_OFFSET[7] origin:064-gtp-channel-conf 01_475 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.ES_VERT_OFFSET[8] origin:064-gtp-channel-conf 00_476 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.FTS_DESKEW_SEQ_ENABLE[0] origin:064-gtp-channel-conf 00_662 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.FTS_DESKEW_SEQ_ENABLE[1] origin:064-gtp-channel-conf 01_662 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.FTS_DESKEW_SEQ_ENABLE[2] origin:064-gtp-channel-conf 00_663 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.FTS_DESKEW_SEQ_ENABLE[3] origin:064-gtp-channel-conf 01_663 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.FTS_LANE_DESKEW_CFG[0] origin:064-gtp-channel-conf 00_654 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.FTS_LANE_DESKEW_CFG[1] origin:064-gtp-channel-conf 01_654 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.FTS_LANE_DESKEW_CFG[2] origin:064-gtp-channel-conf 00_655 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.FTS_LANE_DESKEW_CFG[3] origin:064-gtp-channel-conf 01_655 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.FTS_LANE_DESKEW_EN origin:064-gtp-channel-conf 01_653 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.GEARBOX_MODE[0] origin:064-gtp-channel-conf 00_224 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.GEARBOX_MODE[1] origin:064-gtp-channel-conf 01_224 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.GEARBOX_MODE[2] origin:064-gtp-channel-conf 00_225 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.IN_USE origin:064-gtp-channel-conf 00_00 00_01 00_47 00_52 00_53 00_65 01_01 01_47 02_129 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.INV_DMONITORCLK origin:064-gtp-channel-conf 02_13 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.INV_DRPCLK origin:064-gtp-channel-conf 02_00 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.INV_RXUSRCLK origin:064-gtp-channel-conf 03_01 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.INV_SIGVALIDCLK origin:064-gtp-channel-conf 03_13 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.INV_TXPHDLYTSTCLK origin:064-gtp-channel-conf 02_03 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.INV_TXUSRCLK origin:064-gtp-channel-conf 03_04 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.INV_CLKRSVD0 origin:064-gtp-channel-conf 02_23 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.INV_CLKRSVD1 origin:064-gtp-channel-conf 03_23 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.INV_RXUSRCLK2 origin:064-gtp-channel-conf 02_02 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.INV_TXUSRCLK2 origin:064-gtp-channel-conf 02_05 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.LOOPBACK_CFG[0] origin:064-gtp-channel-conf 02_20 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.OUTREFCLK_SEL_INV[0] origin:064-gtp-channel-conf 00_149 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.OUTREFCLK_SEL_INV[1] origin:064-gtp-channel-conf 01_149 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PCS_PCIE_EN origin:064-gtp-channel-conf 00_216 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[0] origin:064-gtp-channel-conf 02_184 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[1] origin:064-gtp-channel-conf 03_184 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[2] origin:064-gtp-channel-conf 02_185 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[3] origin:064-gtp-channel-conf 03_185 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[4] origin:064-gtp-channel-conf 02_186 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[5] origin:064-gtp-channel-conf 03_186 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[6] origin:064-gtp-channel-conf 02_187 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[7] origin:064-gtp-channel-conf 03_187 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[8] origin:064-gtp-channel-conf 02_188 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[9] origin:064-gtp-channel-conf 03_188 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[10] origin:064-gtp-channel-conf 02_189 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[11] origin:064-gtp-channel-conf 03_189 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[12] origin:064-gtp-channel-conf 02_190 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[13] origin:064-gtp-channel-conf 03_190 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[14] origin:064-gtp-channel-conf 02_191 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[15] origin:064-gtp-channel-conf 03_191 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[16] origin:064-gtp-channel-conf 02_192 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[17] origin:064-gtp-channel-conf 03_192 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[18] origin:064-gtp-channel-conf 02_193 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[19] origin:064-gtp-channel-conf 03_193 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[20] origin:064-gtp-channel-conf 02_194 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[21] origin:064-gtp-channel-conf 03_194 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[22] origin:064-gtp-channel-conf 02_195 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[23] origin:064-gtp-channel-conf 03_195 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[24] origin:064-gtp-channel-conf 02_196 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[25] origin:064-gtp-channel-conf 03_196 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[26] origin:064-gtp-channel-conf 02_197 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[27] origin:064-gtp-channel-conf 03_197 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[28] origin:064-gtp-channel-conf 02_198 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[29] origin:064-gtp-channel-conf 03_198 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[30] origin:064-gtp-channel-conf 02_199 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[31] origin:064-gtp-channel-conf 03_199 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[32] origin:064-gtp-channel-conf 02_200 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[33] origin:064-gtp-channel-conf 03_200 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[34] origin:064-gtp-channel-conf 02_201 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[35] origin:064-gtp-channel-conf 03_201 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[36] origin:064-gtp-channel-conf 02_202 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[37] origin:064-gtp-channel-conf 03_202 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[38] origin:064-gtp-channel-conf 02_203 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[39] origin:064-gtp-channel-conf 03_203 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[40] origin:064-gtp-channel-conf 02_204 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[41] origin:064-gtp-channel-conf 03_204 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[42] origin:064-gtp-channel-conf 02_205 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[43] origin:064-gtp-channel-conf 03_205 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[44] origin:064-gtp-channel-conf 02_206 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[45] origin:064-gtp-channel-conf 03_206 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[46] origin:064-gtp-channel-conf 02_207 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[47] origin:064-gtp-channel-conf 03_207 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[0] origin:064-gtp-channel-conf 01_216 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[1] origin:064-gtp-channel-conf 00_217 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[2] origin:064-gtp-channel-conf 01_217 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[3] origin:064-gtp-channel-conf 00_218 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[4] origin:064-gtp-channel-conf 01_218 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[5] origin:064-gtp-channel-conf 00_219 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[6] origin:064-gtp-channel-conf 01_219 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[7] origin:064-gtp-channel-conf 00_220 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[8] origin:064-gtp-channel-conf 01_220 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[9] origin:064-gtp-channel-conf 00_221 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[10] origin:064-gtp-channel-conf 01_221 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[11] origin:064-gtp-channel-conf 00_222 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[0] origin:064-gtp-channel-conf 00_208 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[1] origin:064-gtp-channel-conf 01_208 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[2] origin:064-gtp-channel-conf 00_209 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[3] origin:064-gtp-channel-conf 01_209 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[4] origin:064-gtp-channel-conf 00_210 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[5] origin:064-gtp-channel-conf 01_210 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[6] origin:064-gtp-channel-conf 00_211 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[7] origin:064-gtp-channel-conf 01_211 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[0] origin:064-gtp-channel-conf 00_212 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[1] origin:064-gtp-channel-conf 01_212 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[2] origin:064-gtp-channel-conf 00_213 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[3] origin:064-gtp-channel-conf 01_213 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[4] origin:064-gtp-channel-conf 00_214 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[5] origin:064-gtp-channel-conf 01_214 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[6] origin:064-gtp-channel-conf 00_215 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[7] origin:064-gtp-channel-conf 01_215 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PMA_LOOPBACK_CFG[0] origin:064-gtp-channel-conf 01_207 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[0] origin:064-gtp-channel-conf 02_520 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[1] origin:064-gtp-channel-conf 03_520 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[2] origin:064-gtp-channel-conf 02_521 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[3] origin:064-gtp-channel-conf 03_521 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[4] origin:064-gtp-channel-conf 02_522 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[5] origin:064-gtp-channel-conf 03_522 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[6] origin:064-gtp-channel-conf 02_523 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[7] origin:064-gtp-channel-conf 03_523 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[8] origin:064-gtp-channel-conf 02_524 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[9] origin:064-gtp-channel-conf 03_524 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[10] origin:064-gtp-channel-conf 02_525 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[11] origin:064-gtp-channel-conf 03_525 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[12] origin:064-gtp-channel-conf 02_526 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[13] origin:064-gtp-channel-conf 03_526 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[14] origin:064-gtp-channel-conf 02_527 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[15] origin:064-gtp-channel-conf 03_527 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[16] origin:064-gtp-channel-conf 02_528 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[17] origin:064-gtp-channel-conf 03_528 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[18] origin:064-gtp-channel-conf 02_529 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[19] origin:064-gtp-channel-conf 03_529 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[20] origin:064-gtp-channel-conf 02_530 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[21] origin:064-gtp-channel-conf 03_530 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[22] origin:064-gtp-channel-conf 02_531 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[23] origin:064-gtp-channel-conf 03_531 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[24] origin:064-gtp-channel-conf 02_532 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[25] origin:064-gtp-channel-conf 03_532 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[26] origin:064-gtp-channel-conf 02_533 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[27] origin:064-gtp-channel-conf 03_533 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[28] origin:064-gtp-channel-conf 02_534 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[29] origin:064-gtp-channel-conf 03_534 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[30] origin:064-gtp-channel-conf 02_535 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[31] origin:064-gtp-channel-conf 03_535 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[0] origin:064-gtp-channel-conf 02_336 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[1] origin:064-gtp-channel-conf 03_336 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[2] origin:064-gtp-channel-conf 02_337 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[3] origin:064-gtp-channel-conf 03_337 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[4] origin:064-gtp-channel-conf 02_338 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[5] origin:064-gtp-channel-conf 03_338 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[6] origin:064-gtp-channel-conf 02_339 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[7] origin:064-gtp-channel-conf 03_339 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[8] origin:064-gtp-channel-conf 02_340 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[9] origin:064-gtp-channel-conf 03_340 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[10] origin:064-gtp-channel-conf 02_341 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[11] origin:064-gtp-channel-conf 03_341 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[12] origin:064-gtp-channel-conf 02_342 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[13] origin:064-gtp-channel-conf 03_342 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[14] origin:064-gtp-channel-conf 02_343 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[15] origin:064-gtp-channel-conf 03_343 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[16] origin:064-gtp-channel-conf 02_344 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[17] origin:064-gtp-channel-conf 03_344 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[18] origin:064-gtp-channel-conf 02_345 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[19] origin:064-gtp-channel-conf 03_345 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[20] origin:064-gtp-channel-conf 02_346 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[21] origin:064-gtp-channel-conf 03_346 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[22] origin:064-gtp-channel-conf 02_347 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[23] origin:064-gtp-channel-conf 03_347 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[24] origin:064-gtp-channel-conf 02_348 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[25] origin:064-gtp-channel-conf 03_348 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[26] origin:064-gtp-channel-conf 02_349 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[27] origin:064-gtp-channel-conf 03_349 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[28] origin:064-gtp-channel-conf 02_350 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[29] origin:064-gtp-channel-conf 03_350 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[30] origin:064-gtp-channel-conf 02_351 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[31] origin:064-gtp-channel-conf 03_351 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV3[0] origin:064-gtp-channel-conf 02_288 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV3[1] origin:064-gtp-channel-conf 03_288 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV4[0] origin:064-gtp-channel-conf 02_156 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV4[1] origin:064-gtp-channel-conf 03_156 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV4[2] origin:064-gtp-channel-conf 02_157 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV4[3] origin:064-gtp-channel-conf 03_157 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV5[0] origin:064-gtp-channel-conf 03_159 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV6[0] origin:064-gtp-channel-conf 02_303 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV7[0] origin:064-gtp-channel-conf 03_303 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_BIAS_CFG[0] origin:064-gtp-channel-conf 02_112 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_BIAS_CFG[1] origin:064-gtp-channel-conf 03_112 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_BIAS_CFG[2] origin:064-gtp-channel-conf 02_113 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_BIAS_CFG[3] origin:064-gtp-channel-conf 03_113 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_BIAS_CFG[4] origin:064-gtp-channel-conf 02_114 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_BIAS_CFG[5] origin:064-gtp-channel-conf 03_114 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_BIAS_CFG[6] origin:064-gtp-channel-conf 02_115 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_BIAS_CFG[7] origin:064-gtp-channel-conf 03_115 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_BIAS_CFG[8] origin:064-gtp-channel-conf 02_116 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_BIAS_CFG[9] origin:064-gtp-channel-conf 03_116 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_BIAS_CFG[10] origin:064-gtp-channel-conf 02_117 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_BIAS_CFG[11] origin:064-gtp-channel-conf 03_117 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_BIAS_CFG[12] origin:064-gtp-channel-conf 02_118 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_BIAS_CFG[13] origin:064-gtp-channel-conf 03_118 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_BIAS_CFG[14] origin:064-gtp-channel-conf 02_119 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_BIAS_CFG[15] origin:064-gtp-channel-conf 03_119 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_BUFFER_CFG[0] origin:064-gtp-channel-conf 02_536 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_BUFFER_CFG[1] origin:064-gtp-channel-conf 03_536 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_BUFFER_CFG[2] origin:064-gtp-channel-conf 02_537 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_BUFFER_CFG[3] origin:064-gtp-channel-conf 03_537 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_BUFFER_CFG[4] origin:064-gtp-channel-conf 02_538 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_BUFFER_CFG[5] origin:064-gtp-channel-conf 03_538 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_CLKMUX_EN[0] origin:064-gtp-channel-conf 02_128 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_CM_SEL[0] origin:064-gtp-channel-conf 00_138 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_CM_SEL[1] origin:064-gtp-channel-conf 01_138 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_CM_TRIM[0] origin:064-gtp-channel-conf 02_304 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_CM_TRIM[1] origin:064-gtp-channel-conf 03_304 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_CM_TRIM[2] origin:064-gtp-channel-conf 02_305 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_CM_TRIM[3] origin:064-gtp-channel-conf 03_305 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_DATA_WIDTH[0] origin:064-gtp-channel-conf 01_141 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_DATA_WIDTH[1] origin:064-gtp-channel-conf 00_142 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_DATA_WIDTH[2] origin:064-gtp-channel-conf 01_142 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_DDI_SEL[0] origin:064-gtp-channel-conf 00_696 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_DDI_SEL[1] origin:064-gtp-channel-conf 01_696 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_DDI_SEL[2] origin:064-gtp-channel-conf 00_697 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_DDI_SEL[3] origin:064-gtp-channel-conf 01_697 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_DDI_SEL[4] origin:064-gtp-channel-conf 00_698 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_DDI_SEL[5] origin:064-gtp-channel-conf 01_698 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_DEBUG_CFG[0] origin:064-gtp-channel-conf 02_616 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_DEBUG_CFG[1] origin:064-gtp-channel-conf 03_616 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_DEBUG_CFG[2] origin:064-gtp-channel-conf 02_617 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_DEBUG_CFG[3] origin:064-gtp-channel-conf 03_617 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_DEBUG_CFG[4] origin:064-gtp-channel-conf 02_618 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_DEBUG_CFG[5] origin:064-gtp-channel-conf 03_618 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_DEBUG_CFG[6] origin:064-gtp-channel-conf 02_619 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_DEBUG_CFG[7] origin:064-gtp-channel-conf 03_619 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_DEBUG_CFG[8] origin:064-gtp-channel-conf 02_620 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_DEBUG_CFG[9] origin:064-gtp-channel-conf 03_620 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_DEBUG_CFG[10] origin:064-gtp-channel-conf 02_621 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_DEBUG_CFG[11] origin:064-gtp-channel-conf 03_621 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_DEBUG_CFG[12] origin:064-gtp-channel-conf 02_622 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_DEBUG_CFG[13] origin:064-gtp-channel-conf 03_622 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_DEFER_RESET_BUF_EN origin:064-gtp-channel-conf 02_552 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_DISPERR_SEQ_MATCH origin:064-gtp-channel-conf 01_495 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_OS_CFG[0] origin:064-gtp-channel-conf 00_288 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_OS_CFG[1] origin:064-gtp-channel-conf 01_288 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_OS_CFG[2] origin:064-gtp-channel-conf 00_289 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_OS_CFG[3] origin:064-gtp-channel-conf 01_289 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_OS_CFG[4] origin:064-gtp-channel-conf 00_290 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_OS_CFG[5] origin:064-gtp-channel-conf 01_290 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_OS_CFG[6] origin:064-gtp-channel-conf 00_291 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_OS_CFG[7] origin:064-gtp-channel-conf 01_291 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_OS_CFG[8] origin:064-gtp-channel-conf 00_292 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_OS_CFG[9] origin:064-gtp-channel-conf 01_292 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_OS_CFG[10] origin:064-gtp-channel-conf 00_293 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_OS_CFG[11] origin:064-gtp-channel-conf 01_293 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_OS_CFG[12] origin:064-gtp-channel-conf 00_294 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_SIG_VALID_DLY[0] origin:064-gtp-channel-conf 00_524 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_SIG_VALID_DLY[1] origin:064-gtp-channel-conf 01_524 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_SIG_VALID_DLY[2] origin:064-gtp-channel-conf 00_525 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_SIG_VALID_DLY[3] origin:064-gtp-channel-conf 01_525 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_SIG_VALID_DLY[4] origin:064-gtp-channel-conf 00_526 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_XCLK_SEL.RXUSR origin:064-gtp-channel-conf 00_143 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_CLK25_DIV[0] origin:064-gtp-channel-conf 00_139 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_CLK25_DIV[1] origin:064-gtp-channel-conf 01_139 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_CLK25_DIV[2] origin:064-gtp-channel-conf 00_140 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_CLK25_DIV[3] origin:064-gtp-channel-conf 01_140 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RX_CLK25_DIV[4] origin:064-gtp-channel-conf 00_141 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXBUF_ADDR_MODE.FAST origin:064-gtp-channel-conf 03_555 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXBUF_EIDLE_HI_CNT[0] origin:064-gtp-channel-conf 02_558 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXBUF_EIDLE_HI_CNT[1] origin:064-gtp-channel-conf 03_558 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXBUF_EIDLE_HI_CNT[2] origin:064-gtp-channel-conf 02_559 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXBUF_EIDLE_HI_CNT[3] origin:064-gtp-channel-conf 03_559 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXBUF_EIDLE_LO_CNT[0] origin:064-gtp-channel-conf 02_556 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXBUF_EIDLE_LO_CNT[1] origin:064-gtp-channel-conf 03_556 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXBUF_EIDLE_LO_CNT[2] origin:064-gtp-channel-conf 02_557 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXBUF_EIDLE_LO_CNT[3] origin:064-gtp-channel-conf 03_557 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXBUF_EN origin:064-gtp-channel-conf 02_11 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXBUF_RESET_ON_CB_CHANGE origin:064-gtp-channel-conf 02_560 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXBUF_RESET_ON_COMMAALIGN origin:064-gtp-channel-conf 02_561 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXBUF_RESET_ON_EIDLE origin:064-gtp-channel-conf 02_547 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXBUF_RESET_ON_RATE_CHANGE origin:064-gtp-channel-conf 03_560 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXBUF_THRESH_OVFLW[0] origin:064-gtp-channel-conf 03_552 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXBUF_THRESH_OVFLW[1] origin:064-gtp-channel-conf 02_553 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXBUF_THRESH_OVFLW[2] origin:064-gtp-channel-conf 03_553 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXBUF_THRESH_OVFLW[3] origin:064-gtp-channel-conf 02_554 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXBUF_THRESH_OVFLW[4] origin:064-gtp-channel-conf 03_554 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXBUF_THRESH_OVFLW[5] origin:064-gtp-channel-conf 02_555 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXBUF_THRESH_OVRD origin:064-gtp-channel-conf 02_548 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXBUF_THRESH_UNDFLW[0] origin:064-gtp-channel-conf 02_544 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXBUF_THRESH_UNDFLW[1] origin:064-gtp-channel-conf 03_544 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXBUF_THRESH_UNDFLW[2] origin:064-gtp-channel-conf 02_545 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXBUF_THRESH_UNDFLW[3] origin:064-gtp-channel-conf 03_545 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXBUF_THRESH_UNDFLW[4] origin:064-gtp-channel-conf 02_546 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXBUF_THRESH_UNDFLW[5] origin:064-gtp-channel-conf 03_546 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXBUFRESET_TIME[0] origin:064-gtp-channel-conf 01_101 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXBUFRESET_TIME[1] origin:064-gtp-channel-conf 00_102 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXBUFRESET_TIME[2] origin:064-gtp-channel-conf 01_102 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXBUFRESET_TIME[3] origin:064-gtp-channel-conf 00_103 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXBUFRESET_TIME[4] origin:064-gtp-channel-conf 01_103 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[0] origin:064-gtp-channel-conf 02_640 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[1] origin:064-gtp-channel-conf 03_640 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[2] origin:064-gtp-channel-conf 02_641 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[3] origin:064-gtp-channel-conf 03_641 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[4] origin:064-gtp-channel-conf 02_642 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[5] origin:064-gtp-channel-conf 03_642 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[6] origin:064-gtp-channel-conf 02_643 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[7] origin:064-gtp-channel-conf 03_643 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[8] origin:064-gtp-channel-conf 02_644 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[9] origin:064-gtp-channel-conf 03_644 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[10] origin:064-gtp-channel-conf 02_645 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[11] origin:064-gtp-channel-conf 03_645 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[12] origin:064-gtp-channel-conf 02_646 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[13] origin:064-gtp-channel-conf 03_646 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[14] origin:064-gtp-channel-conf 02_647 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[15] origin:064-gtp-channel-conf 03_647 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[16] origin:064-gtp-channel-conf 02_648 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[17] origin:064-gtp-channel-conf 03_648 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[18] origin:064-gtp-channel-conf 02_649 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[19] origin:064-gtp-channel-conf 03_649 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[20] origin:064-gtp-channel-conf 02_650 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[21] origin:064-gtp-channel-conf 03_650 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[22] origin:064-gtp-channel-conf 02_651 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[23] origin:064-gtp-channel-conf 03_651 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[24] origin:064-gtp-channel-conf 02_652 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[25] origin:064-gtp-channel-conf 03_652 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[26] origin:064-gtp-channel-conf 02_653 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[27] origin:064-gtp-channel-conf 03_653 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[28] origin:064-gtp-channel-conf 02_654 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[29] origin:064-gtp-channel-conf 03_654 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[30] origin:064-gtp-channel-conf 02_655 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[31] origin:064-gtp-channel-conf 03_655 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[32] origin:064-gtp-channel-conf 02_656 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[33] origin:064-gtp-channel-conf 03_656 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[34] origin:064-gtp-channel-conf 02_657 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[35] origin:064-gtp-channel-conf 03_657 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[36] origin:064-gtp-channel-conf 02_658 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[37] origin:064-gtp-channel-conf 03_658 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[38] origin:064-gtp-channel-conf 02_659 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[39] origin:064-gtp-channel-conf 03_659 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[40] origin:064-gtp-channel-conf 02_660 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[41] origin:064-gtp-channel-conf 03_660 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[42] origin:064-gtp-channel-conf 02_661 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[43] origin:064-gtp-channel-conf 03_661 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[44] origin:064-gtp-channel-conf 02_662 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[45] origin:064-gtp-channel-conf 03_662 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[46] origin:064-gtp-channel-conf 02_663 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[47] origin:064-gtp-channel-conf 03_663 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[48] origin:064-gtp-channel-conf 02_664 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[49] origin:064-gtp-channel-conf 03_664 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[50] origin:064-gtp-channel-conf 02_665 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[51] origin:064-gtp-channel-conf 03_665 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[52] origin:064-gtp-channel-conf 02_666 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[53] origin:064-gtp-channel-conf 03_666 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[54] origin:064-gtp-channel-conf 02_667 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[55] origin:064-gtp-channel-conf 03_667 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[56] origin:064-gtp-channel-conf 02_668 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[57] origin:064-gtp-channel-conf 03_668 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[58] origin:064-gtp-channel-conf 02_669 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[59] origin:064-gtp-channel-conf 03_669 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[60] origin:064-gtp-channel-conf 02_670 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[61] origin:064-gtp-channel-conf 03_670 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[62] origin:064-gtp-channel-conf 02_671 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[63] origin:064-gtp-channel-conf 03_671 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[64] origin:064-gtp-channel-conf 02_672 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[65] origin:064-gtp-channel-conf 03_672 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[66] origin:064-gtp-channel-conf 02_673 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[67] origin:064-gtp-channel-conf 03_673 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[68] origin:064-gtp-channel-conf 02_674 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[69] origin:064-gtp-channel-conf 03_674 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[70] origin:064-gtp-channel-conf 02_675 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[71] origin:064-gtp-channel-conf 03_675 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[72] origin:064-gtp-channel-conf 02_676 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[73] origin:064-gtp-channel-conf 03_676 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[74] origin:064-gtp-channel-conf 02_677 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[75] origin:064-gtp-channel-conf 03_677 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[76] origin:064-gtp-channel-conf 02_678 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[77] origin:064-gtp-channel-conf 03_678 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[78] origin:064-gtp-channel-conf 02_679 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[79] origin:064-gtp-channel-conf 03_679 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[80] origin:064-gtp-channel-conf 02_680 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[81] origin:064-gtp-channel-conf 03_680 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[82] origin:064-gtp-channel-conf 02_681 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_FR_RESET_ON_EIDLE[0] origin:064-gtp-channel-conf 02_638 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_HOLD_DURING_EIDLE[0] origin:064-gtp-channel-conf 03_637 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_LOCK_CFG[0] origin:064-gtp-channel-conf 02_632 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_LOCK_CFG[1] origin:064-gtp-channel-conf 03_632 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_LOCK_CFG[2] origin:064-gtp-channel-conf 02_633 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_LOCK_CFG[3] origin:064-gtp-channel-conf 03_633 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_LOCK_CFG[4] origin:064-gtp-channel-conf 02_634 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_LOCK_CFG[5] origin:064-gtp-channel-conf 03_634 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDR_PH_RESET_ON_EIDLE[0] origin:064-gtp-channel-conf 03_638 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDRFREQRESET_TIME[0] origin:064-gtp-channel-conf 01_106 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDRFREQRESET_TIME[1] origin:064-gtp-channel-conf 00_107 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDRFREQRESET_TIME[2] origin:064-gtp-channel-conf 01_107 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDRFREQRESET_TIME[3] origin:064-gtp-channel-conf 00_108 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDRFREQRESET_TIME[4] origin:064-gtp-channel-conf 01_108 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDRPHRESET_TIME[0] origin:064-gtp-channel-conf 00_109 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDRPHRESET_TIME[1] origin:064-gtp-channel-conf 01_109 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDRPHRESET_TIME[2] origin:064-gtp-channel-conf 00_110 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDRPHRESET_TIME[3] origin:064-gtp-channel-conf 01_110 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXCDRPHRESET_TIME[4] origin:064-gtp-channel-conf 00_111 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXDLY_CFG[0] origin:064-gtp-channel-conf 00_680 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXDLY_CFG[1] origin:064-gtp-channel-conf 01_680 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXDLY_CFG[2] origin:064-gtp-channel-conf 00_681 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXDLY_CFG[3] origin:064-gtp-channel-conf 01_681 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXDLY_CFG[4] origin:064-gtp-channel-conf 00_682 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXDLY_CFG[5] origin:064-gtp-channel-conf 01_682 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXDLY_CFG[6] origin:064-gtp-channel-conf 00_683 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXDLY_CFG[7] origin:064-gtp-channel-conf 01_683 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXDLY_CFG[8] origin:064-gtp-channel-conf 00_684 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXDLY_CFG[9] origin:064-gtp-channel-conf 01_684 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXDLY_CFG[10] origin:064-gtp-channel-conf 00_685 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXDLY_CFG[11] origin:064-gtp-channel-conf 01_685 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXDLY_CFG[12] origin:064-gtp-channel-conf 00_686 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXDLY_CFG[13] origin:064-gtp-channel-conf 01_686 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXDLY_CFG[14] origin:064-gtp-channel-conf 00_687 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXDLY_CFG[15] origin:064-gtp-channel-conf 01_687 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXDLY_LCFG[0] origin:064-gtp-channel-conf 02_576 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXDLY_LCFG[1] origin:064-gtp-channel-conf 03_576 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXDLY_LCFG[2] origin:064-gtp-channel-conf 02_577 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXDLY_LCFG[3] origin:064-gtp-channel-conf 03_577 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXDLY_LCFG[4] origin:064-gtp-channel-conf 02_578 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXDLY_LCFG[5] origin:064-gtp-channel-conf 03_578 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXDLY_LCFG[6] origin:064-gtp-channel-conf 02_579 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXDLY_LCFG[7] origin:064-gtp-channel-conf 03_579 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXDLY_LCFG[8] origin:064-gtp-channel-conf 02_580 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXDLY_TAP_CFG[0] origin:064-gtp-channel-conf 00_672 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXDLY_TAP_CFG[1] origin:064-gtp-channel-conf 01_672 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXDLY_TAP_CFG[2] origin:064-gtp-channel-conf 00_673 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXDLY_TAP_CFG[3] origin:064-gtp-channel-conf 01_673 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXDLY_TAP_CFG[4] origin:064-gtp-channel-conf 00_674 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXDLY_TAP_CFG[5] origin:064-gtp-channel-conf 01_674 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXDLY_TAP_CFG[6] origin:064-gtp-channel-conf 00_675 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXDLY_TAP_CFG[7] origin:064-gtp-channel-conf 01_675 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXDLY_TAP_CFG[8] origin:064-gtp-channel-conf 00_676 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXDLY_TAP_CFG[9] origin:064-gtp-channel-conf 01_676 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXDLY_TAP_CFG[10] origin:064-gtp-channel-conf 00_677 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXDLY_TAP_CFG[11] origin:064-gtp-channel-conf 01_677 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXDLY_TAP_CFG[12] origin:064-gtp-channel-conf 00_678 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXDLY_TAP_CFG[13] origin:064-gtp-channel-conf 01_678 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXDLY_TAP_CFG[14] origin:064-gtp-channel-conf 00_679 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXDLY_TAP_CFG[15] origin:064-gtp-channel-conf 01_679 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXGEARBOX_EN origin:064-gtp-channel-conf 01_607 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXISCANRESET_TIME[0] origin:064-gtp-channel-conf 01_123 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXISCANRESET_TIME[1] origin:064-gtp-channel-conf 00_124 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXISCANRESET_TIME[2] origin:064-gtp-channel-conf 01_124 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXISCANRESET_TIME[3] origin:064-gtp-channel-conf 00_125 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXISCANRESET_TIME[4] origin:064-gtp-channel-conf 01_125 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPM_BIAS_STARTUP_DISABLE[0] origin:064-gtp-channel-conf 03_391 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPM_CFG[0] origin:064-gtp-channel-conf 02_328 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPM_CFG[1] origin:064-gtp-channel-conf 03_328 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPM_CFG[2] origin:064-gtp-channel-conf 02_329 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPM_CFG[3] origin:064-gtp-channel-conf 03_329 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPM_CM_CFG[0] origin:064-gtp-channel-conf 02_430 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPM_GC_CFG[0] origin:064-gtp-channel-conf 02_432 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPM_GC_CFG[1] origin:064-gtp-channel-conf 03_432 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPM_GC_CFG[2] origin:064-gtp-channel-conf 02_433 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPM_GC_CFG[3] origin:064-gtp-channel-conf 03_433 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPM_GC_CFG[4] origin:064-gtp-channel-conf 02_434 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPM_GC_CFG[5] origin:064-gtp-channel-conf 03_434 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPM_GC_CFG[6] origin:064-gtp-channel-conf 02_435 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPM_GC_CFG[7] origin:064-gtp-channel-conf 03_435 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPM_GC_CFG[8] origin:064-gtp-channel-conf 02_436 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPM_GC_CFG2[0] origin:064-gtp-channel-conf 03_442 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPM_GC_CFG2[1] origin:064-gtp-channel-conf 02_443 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPM_GC_CFG2[2] origin:064-gtp-channel-conf 03_443 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG[0] origin:064-gtp-channel-conf 00_336 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG[1] origin:064-gtp-channel-conf 01_336 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG[2] origin:064-gtp-channel-conf 00_337 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG[3] origin:064-gtp-channel-conf 01_337 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG[4] origin:064-gtp-channel-conf 00_338 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG[5] origin:064-gtp-channel-conf 01_338 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG[6] origin:064-gtp-channel-conf 00_339 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG[7] origin:064-gtp-channel-conf 01_339 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG[8] origin:064-gtp-channel-conf 00_340 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG[9] origin:064-gtp-channel-conf 01_340 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG[10] origin:064-gtp-channel-conf 00_341 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG[11] origin:064-gtp-channel-conf 01_341 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG[12] origin:064-gtp-channel-conf 00_342 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG[13] origin:064-gtp-channel-conf 01_342 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG2[0] origin:064-gtp-channel-conf 02_424 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG2[1] origin:064-gtp-channel-conf 03_424 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG2[2] origin:064-gtp-channel-conf 02_425 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG2[3] origin:064-gtp-channel-conf 03_425 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG2[4] origin:064-gtp-channel-conf 02_426 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG3[0] origin:064-gtp-channel-conf 03_389 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG3[1] origin:064-gtp-channel-conf 02_390 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG3[2] origin:064-gtp-channel-conf 03_390 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG3[3] origin:064-gtp-channel-conf 02_391 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HOLD_DURING_EIDLE[0] origin:064-gtp-channel-conf 00_247 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPM_INCM_CFG[0] origin:064-gtp-channel-conf 02_439 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPM_IPCM_CFG[0] origin:064-gtp-channel-conf 03_439 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG[0] origin:064-gtp-channel-conf 00_344 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG[1] origin:064-gtp-channel-conf 01_344 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG[2] origin:064-gtp-channel-conf 00_345 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG[3] origin:064-gtp-channel-conf 01_345 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG[4] origin:064-gtp-channel-conf 00_346 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG[5] origin:064-gtp-channel-conf 01_346 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG[6] origin:064-gtp-channel-conf 00_347 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG[7] origin:064-gtp-channel-conf 01_347 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG[8] origin:064-gtp-channel-conf 00_348 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG[9] origin:064-gtp-channel-conf 01_348 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG[10] origin:064-gtp-channel-conf 00_349 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG[11] origin:064-gtp-channel-conf 01_349 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG[12] origin:064-gtp-channel-conf 00_350 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG[13] origin:064-gtp-channel-conf 01_350 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG[14] origin:064-gtp-channel-conf 00_351 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG[15] origin:064-gtp-channel-conf 01_351 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG[16] origin:064-gtp-channel-conf 00_343 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG[17] origin:064-gtp-channel-conf 01_343 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG2[0] origin:064-gtp-channel-conf 03_426 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG2[1] origin:064-gtp-channel-conf 02_427 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG2[2] origin:064-gtp-channel-conf 03_427 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG2[3] origin:064-gtp-channel-conf 02_428 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG2[4] origin:064-gtp-channel-conf 03_428 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPM_OSINT_CFG[0] origin:064-gtp-channel-conf 02_440 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPM_OSINT_CFG[1] origin:064-gtp-channel-conf 03_440 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPM_OSINT_CFG[2] origin:064-gtp-channel-conf 02_441 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPM_CFG1[0] origin:064-gtp-channel-conf 02_330 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPMRESET_TIME[0] origin:064-gtp-channel-conf 00_112 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPMRESET_TIME[1] origin:064-gtp-channel-conf 01_112 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPMRESET_TIME[2] origin:064-gtp-channel-conf 00_113 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPMRESET_TIME[3] origin:064-gtp-channel-conf 01_113 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPMRESET_TIME[4] origin:064-gtp-channel-conf 00_114 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPMRESET_TIME[5] origin:064-gtp-channel-conf 01_114 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXLPMRESET_TIME[6] origin:064-gtp-channel-conf 00_115 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXOOB_CFG[0] origin:064-gtp-channel-conf 00_144 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXOOB_CFG[1] origin:064-gtp-channel-conf 01_144 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXOOB_CFG[2] origin:064-gtp-channel-conf 00_145 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXOOB_CFG[3] origin:064-gtp-channel-conf 01_145 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXOOB_CFG[4] origin:064-gtp-channel-conf 00_146 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXOOB_CFG[5] origin:064-gtp-channel-conf 01_146 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXOOB_CFG[6] origin:064-gtp-channel-conf 00_147 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXOOB_CLK_CFG.FABRIC origin:064-gtp-channel-conf 03_129 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXOSCALRESET_TIME[0] origin:064-gtp-channel-conf 00_187 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXOSCALRESET_TIME[1] origin:064-gtp-channel-conf 01_187 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXOSCALRESET_TIME[2] origin:064-gtp-channel-conf 00_188 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXOSCALRESET_TIME[3] origin:064-gtp-channel-conf 01_188 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXOSCALRESET_TIME[4] origin:064-gtp-channel-conf 00_189 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXOSCALRESET_TIMEOUT[0] origin:064-gtp-channel-conf 01_189 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXOSCALRESET_TIMEOUT[1] origin:064-gtp-channel-conf 00_190 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXOSCALRESET_TIMEOUT[2] origin:064-gtp-channel-conf 01_190 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXOSCALRESET_TIMEOUT[3] origin:064-gtp-channel-conf 00_191 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXOSCALRESET_TIMEOUT[4] origin:064-gtp-channel-conf 01_191 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXOUT_DIV[0] origin:064-gtp-channel-conf 02_384 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXOUT_DIV[1] origin:064-gtp-channel-conf 03_384 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXPCSRESET_TIME[0] origin:064-gtp-channel-conf 01_115 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXPCSRESET_TIME[1] origin:064-gtp-channel-conf 00_116 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXPCSRESET_TIME[2] origin:064-gtp-channel-conf 01_116 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXPCSRESET_TIME[3] origin:064-gtp-channel-conf 00_117 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXPCSRESET_TIME[4] origin:064-gtp-channel-conf 01_117 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[0] origin:064-gtp-channel-conf 02_584 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[1] origin:064-gtp-channel-conf 03_584 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[2] origin:064-gtp-channel-conf 02_585 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[3] origin:064-gtp-channel-conf 03_585 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[4] origin:064-gtp-channel-conf 02_586 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[5] origin:064-gtp-channel-conf 03_586 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[6] origin:064-gtp-channel-conf 02_587 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[7] origin:064-gtp-channel-conf 03_587 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[8] origin:064-gtp-channel-conf 02_588 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[9] origin:064-gtp-channel-conf 03_588 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[10] origin:064-gtp-channel-conf 02_589 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[11] origin:064-gtp-channel-conf 03_589 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[12] origin:064-gtp-channel-conf 02_590 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[13] origin:064-gtp-channel-conf 03_590 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[14] origin:064-gtp-channel-conf 02_591 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[15] origin:064-gtp-channel-conf 03_591 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[16] origin:064-gtp-channel-conf 02_592 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[17] origin:064-gtp-channel-conf 03_592 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[18] origin:064-gtp-channel-conf 02_593 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[19] origin:064-gtp-channel-conf 03_593 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[20] origin:064-gtp-channel-conf 02_594 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[21] origin:064-gtp-channel-conf 03_594 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[22] origin:064-gtp-channel-conf 02_595 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[23] origin:064-gtp-channel-conf 03_595 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXPH_MONITOR_SEL[0] origin:064-gtp-channel-conf 00_700 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXPH_MONITOR_SEL[1] origin:064-gtp-channel-conf 01_700 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXPH_MONITOR_SEL[2] origin:064-gtp-channel-conf 00_701 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXPH_MONITOR_SEL[3] origin:064-gtp-channel-conf 01_701 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXPH_MONITOR_SEL[4] origin:064-gtp-channel-conf 00_702 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[0] origin:064-gtp-channel-conf 02_600 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[1] origin:064-gtp-channel-conf 03_600 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[2] origin:064-gtp-channel-conf 02_601 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[3] origin:064-gtp-channel-conf 03_601 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[4] origin:064-gtp-channel-conf 02_602 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[5] origin:064-gtp-channel-conf 03_602 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[6] origin:064-gtp-channel-conf 02_603 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[7] origin:064-gtp-channel-conf 03_603 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[8] origin:064-gtp-channel-conf 02_604 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[9] origin:064-gtp-channel-conf 03_604 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[10] origin:064-gtp-channel-conf 02_605 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[11] origin:064-gtp-channel-conf 03_605 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[12] origin:064-gtp-channel-conf 02_606 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[13] origin:064-gtp-channel-conf 03_606 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[14] origin:064-gtp-channel-conf 02_607 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[15] origin:064-gtp-channel-conf 03_607 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[16] origin:064-gtp-channel-conf 02_608 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[17] origin:064-gtp-channel-conf 03_608 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[18] origin:064-gtp-channel-conf 02_609 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[19] origin:064-gtp-channel-conf 03_609 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[20] origin:064-gtp-channel-conf 02_610 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[21] origin:064-gtp-channel-conf 03_610 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[22] origin:064-gtp-channel-conf 02_611 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[23] origin:064-gtp-channel-conf 03_611 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXPI_CFG0[0] origin:064-gtp-channel-conf 03_430 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXPI_CFG0[1] origin:064-gtp-channel-conf 02_431 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXPI_CFG0[2] origin:064-gtp-channel-conf 03_431 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXPI_CFG1[0] origin:064-gtp-channel-conf 02_442 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXPI_CFG2[0] origin:064-gtp-channel-conf 03_441 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXPMARESET_TIME[0] origin:064-gtp-channel-conf 00_104 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXPMARESET_TIME[1] origin:064-gtp-channel-conf 01_104 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXPMARESET_TIME[2] origin:064-gtp-channel-conf 00_105 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXPMARESET_TIME[3] origin:064-gtp-channel-conf 01_105 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXPMARESET_TIME[4] origin:064-gtp-channel-conf 00_106 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXPRBS_ERR_LOOPBACK[0] origin:064-gtp-channel-conf 00_136 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXSLIDE_AUTO_WAIT[0] origin:064-gtp-channel-conf 00_520 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXSLIDE_AUTO_WAIT[1] origin:064-gtp-channel-conf 01_520 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXSLIDE_AUTO_WAIT[2] origin:064-gtp-channel-conf 00_521 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXSLIDE_AUTO_WAIT[3] origin:064-gtp-channel-conf 01_521 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXSLIDE_MODE.AUTO origin:064-gtp-channel-conf !01_519 00_519 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXSLIDE_MODE.PCS origin:064-gtp-channel-conf !00_519 01_519 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXSLIDE_MODE.PMA origin:064-gtp-channel-conf 00_519 01_519 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXSYNC_MULTILANE[0] origin:064-gtp-channel-conf 00_133 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXSYNC_OVRD[0] origin:064-gtp-channel-conf 01_135 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.RXSYNC_SKIP_DA[0] origin:064-gtp-channel-conf 01_134 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.SAS_MAX_COM[0] origin:064-gtp-channel-conf 00_171 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.SAS_MAX_COM[1] origin:064-gtp-channel-conf 01_171 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.SAS_MAX_COM[2] origin:064-gtp-channel-conf 00_172 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.SAS_MAX_COM[3] origin:064-gtp-channel-conf 01_172 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.SAS_MAX_COM[4] origin:064-gtp-channel-conf 00_173 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.SAS_MAX_COM[5] origin:064-gtp-channel-conf 01_173 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.SAS_MAX_COM[6] origin:064-gtp-channel-conf 00_174 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.SAS_MIN_COM[0] origin:064-gtp-channel-conf 01_156 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.SAS_MIN_COM[1] origin:064-gtp-channel-conf 00_157 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.SAS_MIN_COM[2] origin:064-gtp-channel-conf 01_157 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.SAS_MIN_COM[3] origin:064-gtp-channel-conf 00_158 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.SAS_MIN_COM[4] origin:064-gtp-channel-conf 01_158 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.SAS_MIN_COM[5] origin:064-gtp-channel-conf 00_159 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.SATA_BURST_SEQ_LEN[0] origin:064-gtp-channel-conf 00_150 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.SATA_BURST_SEQ_LEN[1] origin:064-gtp-channel-conf 01_150 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.SATA_BURST_SEQ_LEN[2] origin:064-gtp-channel-conf 00_151 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.SATA_BURST_SEQ_LEN[3] origin:064-gtp-channel-conf 01_151 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.SATA_BURST_VAL[0] origin:064-gtp-channel-conf 01_147 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.SATA_BURST_VAL[1] origin:064-gtp-channel-conf 00_148 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.SATA_BURST_VAL[2] origin:064-gtp-channel-conf 01_148 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.SATA_EIDLE_VAL[0] origin:064-gtp-channel-conf 00_152 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.SATA_EIDLE_VAL[1] origin:064-gtp-channel-conf 01_152 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.SATA_EIDLE_VAL[2] origin:064-gtp-channel-conf 00_153 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.SATA_MAX_BURST[0] origin:064-gtp-channel-conf 00_168 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.SATA_MAX_BURST[1] origin:064-gtp-channel-conf 01_168 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.SATA_MAX_BURST[2] origin:064-gtp-channel-conf 00_169 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.SATA_MAX_BURST[3] origin:064-gtp-channel-conf 01_169 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.SATA_MAX_BURST[4] origin:064-gtp-channel-conf 00_170 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.SATA_MAX_BURST[5] origin:064-gtp-channel-conf 01_170 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.SATA_MAX_INIT[0] origin:064-gtp-channel-conf 00_176 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.SATA_MAX_INIT[1] origin:064-gtp-channel-conf 01_176 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.SATA_MAX_INIT[2] origin:064-gtp-channel-conf 00_177 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.SATA_MAX_INIT[3] origin:064-gtp-channel-conf 01_177 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.SATA_MAX_INIT[4] origin:064-gtp-channel-conf 00_178 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.SATA_MAX_INIT[5] origin:064-gtp-channel-conf 01_178 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.SATA_MAX_WAKE[0] origin:064-gtp-channel-conf 00_179 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.SATA_MAX_WAKE[1] origin:064-gtp-channel-conf 01_179 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.SATA_MAX_WAKE[2] origin:064-gtp-channel-conf 00_180 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.SATA_MAX_WAKE[3] origin:064-gtp-channel-conf 01_180 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.SATA_MAX_WAKE[4] origin:064-gtp-channel-conf 00_181 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.SATA_MAX_WAKE[5] origin:064-gtp-channel-conf 01_181 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.SATA_MIN_BURST[0] origin:064-gtp-channel-conf 01_153 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.SATA_MIN_BURST[1] origin:064-gtp-channel-conf 00_154 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.SATA_MIN_BURST[2] origin:064-gtp-channel-conf 01_154 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.SATA_MIN_BURST[3] origin:064-gtp-channel-conf 00_155 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.SATA_MIN_BURST[4] origin:064-gtp-channel-conf 01_155 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.SATA_MIN_BURST[5] origin:064-gtp-channel-conf 00_156 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.SATA_MIN_INIT[0] origin:064-gtp-channel-conf 00_160 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.SATA_MIN_INIT[1] origin:064-gtp-channel-conf 01_160 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.SATA_MIN_INIT[2] origin:064-gtp-channel-conf 00_161 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.SATA_MIN_INIT[3] origin:064-gtp-channel-conf 01_161 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.SATA_MIN_INIT[4] origin:064-gtp-channel-conf 00_162 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.SATA_MIN_INIT[5] origin:064-gtp-channel-conf 01_162 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.SATA_MIN_WAKE[0] origin:064-gtp-channel-conf 00_163 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.SATA_MIN_WAKE[1] origin:064-gtp-channel-conf 01_163 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.SATA_MIN_WAKE[2] origin:064-gtp-channel-conf 00_164 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.SATA_MIN_WAKE[3] origin:064-gtp-channel-conf 01_164 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.SATA_MIN_WAKE[4] origin:064-gtp-channel-conf 00_165 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.SATA_MIN_WAKE[5] origin:064-gtp-channel-conf 01_165 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.SATA_PLL_CFG.VCO_1500MHZ origin:064-gtp-channel-conf 02_55 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.SATA_PLL_CFG.VCO_750MHZ origin:064-gtp-channel-conf 03_55 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.SHOW_REALIGN_COMMA origin:064-gtp-channel-conf 01_522 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TERM_RCAL_CFG[0] origin:064-gtp-channel-conf 02_136 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TERM_RCAL_CFG[1] origin:064-gtp-channel-conf 03_136 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TERM_RCAL_CFG[2] origin:064-gtp-channel-conf 02_137 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TERM_RCAL_CFG[3] origin:064-gtp-channel-conf 03_137 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TERM_RCAL_CFG[4] origin:064-gtp-channel-conf 02_138 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TERM_RCAL_CFG[5] origin:064-gtp-channel-conf 03_138 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TERM_RCAL_CFG[6] origin:064-gtp-channel-conf 02_139 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TERM_RCAL_CFG[7] origin:064-gtp-channel-conf 03_139 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TERM_RCAL_CFG[8] origin:064-gtp-channel-conf 02_140 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TERM_RCAL_CFG[9] origin:064-gtp-channel-conf 03_140 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TERM_RCAL_CFG[10] origin:064-gtp-channel-conf 02_141 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TERM_RCAL_CFG[11] origin:064-gtp-channel-conf 03_141 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TERM_RCAL_CFG[12] origin:064-gtp-channel-conf 02_142 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TERM_RCAL_CFG[13] origin:064-gtp-channel-conf 03_142 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TERM_RCAL_CFG[14] origin:064-gtp-channel-conf 02_143 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TERM_RCAL_OVRD[0] origin:064-gtp-channel-conf 03_150 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TERM_RCAL_OVRD[1] origin:064-gtp-channel-conf 02_151 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TERM_RCAL_OVRD[2] origin:064-gtp-channel-conf 03_151 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TRANS_TIME_RATE[0] origin:064-gtp-channel-conf 00_192 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TRANS_TIME_RATE[1] origin:064-gtp-channel-conf 01_192 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TRANS_TIME_RATE[2] origin:064-gtp-channel-conf 00_193 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TRANS_TIME_RATE[3] origin:064-gtp-channel-conf 01_193 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TRANS_TIME_RATE[4] origin:064-gtp-channel-conf 00_194 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TRANS_TIME_RATE[5] origin:064-gtp-channel-conf 01_194 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TRANS_TIME_RATE[6] origin:064-gtp-channel-conf 00_195 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TRANS_TIME_RATE[7] origin:064-gtp-channel-conf 01_195 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[0] origin:064-gtp-channel-conf 02_504 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[1] origin:064-gtp-channel-conf 03_504 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[2] origin:064-gtp-channel-conf 02_505 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[3] origin:064-gtp-channel-conf 03_505 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[4] origin:064-gtp-channel-conf 02_506 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[5] origin:064-gtp-channel-conf 03_506 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[6] origin:064-gtp-channel-conf 02_507 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[7] origin:064-gtp-channel-conf 03_507 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[8] origin:064-gtp-channel-conf 02_508 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[9] origin:064-gtp-channel-conf 03_508 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[10] origin:064-gtp-channel-conf 02_509 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[11] origin:064-gtp-channel-conf 03_509 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[12] origin:064-gtp-channel-conf 02_510 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[13] origin:064-gtp-channel-conf 03_510 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[14] origin:064-gtp-channel-conf 02_511 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[15] origin:064-gtp-channel-conf 03_511 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[16] origin:064-gtp-channel-conf 02_512 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[17] origin:064-gtp-channel-conf 03_512 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[18] origin:064-gtp-channel-conf 02_513 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[19] origin:064-gtp-channel-conf 03_513 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[20] origin:064-gtp-channel-conf 02_514 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[21] origin:064-gtp-channel-conf 03_514 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[22] origin:064-gtp-channel-conf 02_515 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[23] origin:064-gtp-channel-conf 03_515 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[24] origin:064-gtp-channel-conf 02_516 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[25] origin:064-gtp-channel-conf 03_516 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[26] origin:064-gtp-channel-conf 02_517 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[27] origin:064-gtp-channel-conf 03_517 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[28] origin:064-gtp-channel-conf 02_518 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[29] origin:064-gtp-channel-conf 03_518 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[30] origin:064-gtp-channel-conf 02_519 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[31] origin:064-gtp-channel-conf 03_519 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_CLKMUX_EN[0] origin:064-gtp-channel-conf 03_128 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_DATA_WIDTH[0] origin:064-gtp-channel-conf 02_152 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_DATA_WIDTH[1] origin:064-gtp-channel-conf 03_152 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_DATA_WIDTH[2] origin:064-gtp-channel-conf 02_153 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_DRIVE_MODE.PIPE origin:064-gtp-channel-conf 00_200 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_EIDLE_ASSERT_DELAY[0] origin:064-gtp-channel-conf 00_203 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_EIDLE_ASSERT_DELAY[1] origin:064-gtp-channel-conf 01_203 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_EIDLE_ASSERT_DELAY[2] origin:064-gtp-channel-conf 00_204 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_EIDLE_DEASSERT_DELAY[0] origin:064-gtp-channel-conf 01_204 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_EIDLE_DEASSERT_DELAY[1] origin:064-gtp-channel-conf 00_205 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_EIDLE_DEASSERT_DELAY[2] origin:064-gtp-channel-conf 01_205 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_LOOPBACK_DRIVE_HIZ origin:064-gtp-channel-conf 01_202 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_MAINCURSOR_SEL[0] origin:064-gtp-channel-conf 03_289 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_0[0] origin:064-gtp-channel-conf 02_232 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_0[1] origin:064-gtp-channel-conf 03_232 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_0[2] origin:064-gtp-channel-conf 02_233 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_0[3] origin:064-gtp-channel-conf 03_233 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_0[4] origin:064-gtp-channel-conf 02_234 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_0[5] origin:064-gtp-channel-conf 03_234 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_0[6] origin:064-gtp-channel-conf 02_235 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_1[0] origin:064-gtp-channel-conf 02_236 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_1[1] origin:064-gtp-channel-conf 03_236 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_1[2] origin:064-gtp-channel-conf 02_237 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_1[3] origin:064-gtp-channel-conf 03_237 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_1[4] origin:064-gtp-channel-conf 02_238 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_1[5] origin:064-gtp-channel-conf 03_238 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_1[6] origin:064-gtp-channel-conf 02_239 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_2[0] origin:064-gtp-channel-conf 02_240 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_2[1] origin:064-gtp-channel-conf 03_240 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_2[2] origin:064-gtp-channel-conf 02_241 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_2[3] origin:064-gtp-channel-conf 03_241 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_2[4] origin:064-gtp-channel-conf 02_242 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_2[5] origin:064-gtp-channel-conf 03_242 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_2[6] origin:064-gtp-channel-conf 02_243 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_3[0] origin:064-gtp-channel-conf 02_244 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_3[1] origin:064-gtp-channel-conf 03_244 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_3[2] origin:064-gtp-channel-conf 02_245 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_3[3] origin:064-gtp-channel-conf 03_245 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_3[4] origin:064-gtp-channel-conf 02_246 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_3[5] origin:064-gtp-channel-conf 03_246 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_3[6] origin:064-gtp-channel-conf 02_247 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_4[0] origin:064-gtp-channel-conf 02_248 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_4[1] origin:064-gtp-channel-conf 03_248 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_4[2] origin:064-gtp-channel-conf 02_249 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_4[3] origin:064-gtp-channel-conf 03_249 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_4[4] origin:064-gtp-channel-conf 02_250 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_4[5] origin:064-gtp-channel-conf 03_250 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_4[6] origin:064-gtp-channel-conf 02_251 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_0[0] origin:064-gtp-channel-conf 02_252 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_0[1] origin:064-gtp-channel-conf 03_252 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_0[2] origin:064-gtp-channel-conf 02_253 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_0[3] origin:064-gtp-channel-conf 03_253 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_0[4] origin:064-gtp-channel-conf 02_254 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_0[5] origin:064-gtp-channel-conf 03_254 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_0[6] origin:064-gtp-channel-conf 02_255 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_1[0] origin:064-gtp-channel-conf 02_256 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_1[1] origin:064-gtp-channel-conf 03_256 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_1[2] origin:064-gtp-channel-conf 02_257 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_1[3] origin:064-gtp-channel-conf 03_257 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_1[4] origin:064-gtp-channel-conf 02_258 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_1[5] origin:064-gtp-channel-conf 03_258 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_1[6] origin:064-gtp-channel-conf 02_259 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_2[0] origin:064-gtp-channel-conf 02_260 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_2[1] origin:064-gtp-channel-conf 03_260 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_2[2] origin:064-gtp-channel-conf 02_261 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_2[3] origin:064-gtp-channel-conf 03_261 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_2[4] origin:064-gtp-channel-conf 02_262 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_2[5] origin:064-gtp-channel-conf 03_262 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_2[6] origin:064-gtp-channel-conf 02_263 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_3[0] origin:064-gtp-channel-conf 02_264 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_3[1] origin:064-gtp-channel-conf 03_264 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_3[2] origin:064-gtp-channel-conf 02_265 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_3[3] origin:064-gtp-channel-conf 03_265 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_3[4] origin:064-gtp-channel-conf 02_266 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_3[5] origin:064-gtp-channel-conf 03_266 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_3[6] origin:064-gtp-channel-conf 02_267 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_4[0] origin:064-gtp-channel-conf 02_268 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_4[1] origin:064-gtp-channel-conf 03_268 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_4[2] origin:064-gtp-channel-conf 02_269 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_4[3] origin:064-gtp-channel-conf 03_269 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_4[4] origin:064-gtp-channel-conf 02_270 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_4[5] origin:064-gtp-channel-conf 03_270 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_4[6] origin:064-gtp-channel-conf 02_271 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_PREDRIVER_MODE[0] origin:064-gtp-channel-conf 00_206 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_RXDETECT_CFG[0] origin:064-gtp-channel-conf 02_296 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_RXDETECT_CFG[1] origin:064-gtp-channel-conf 03_296 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_RXDETECT_CFG[2] origin:064-gtp-channel-conf 02_297 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_RXDETECT_CFG[3] origin:064-gtp-channel-conf 03_297 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_RXDETECT_CFG[4] origin:064-gtp-channel-conf 02_298 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_RXDETECT_CFG[5] origin:064-gtp-channel-conf 03_298 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_RXDETECT_CFG[6] origin:064-gtp-channel-conf 02_299 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_RXDETECT_CFG[7] origin:064-gtp-channel-conf 03_299 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_RXDETECT_CFG[8] origin:064-gtp-channel-conf 02_300 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_RXDETECT_CFG[9] origin:064-gtp-channel-conf 03_300 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_RXDETECT_CFG[10] origin:064-gtp-channel-conf 02_301 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_RXDETECT_CFG[11] origin:064-gtp-channel-conf 03_301 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_RXDETECT_CFG[12] origin:064-gtp-channel-conf 02_302 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_RXDETECT_CFG[13] origin:064-gtp-channel-conf 03_302 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_RXDETECT_REF[0] origin:064-gtp-channel-conf 02_292 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_RXDETECT_REF[1] origin:064-gtp-channel-conf 03_292 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_RXDETECT_REF[2] origin:064-gtp-channel-conf 02_293 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_XCLK_SEL.TXUSR origin:064-gtp-channel-conf 03_11 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_CLK25_DIV[0] origin:064-gtp-channel-conf 02_144 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_CLK25_DIV[1] origin:064-gtp-channel-conf 03_144 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_CLK25_DIV[2] origin:064-gtp-channel-conf 02_145 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_CLK25_DIV[3] origin:064-gtp-channel-conf 03_145 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_CLK25_DIV[4] origin:064-gtp-channel-conf 02_146 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_DEEMPH0[0] origin:064-gtp-channel-conf 02_272 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_DEEMPH0[1] origin:064-gtp-channel-conf 03_272 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_DEEMPH0[2] origin:064-gtp-channel-conf 02_273 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_DEEMPH0[3] origin:064-gtp-channel-conf 03_273 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_DEEMPH0[4] origin:064-gtp-channel-conf 02_274 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_DEEMPH0[5] origin:064-gtp-channel-conf 03_274 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_DEEMPH1[0] origin:064-gtp-channel-conf 02_276 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_DEEMPH1[1] origin:064-gtp-channel-conf 03_276 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_DEEMPH1[2] origin:064-gtp-channel-conf 02_277 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_DEEMPH1[3] origin:064-gtp-channel-conf 03_277 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_DEEMPH1[4] origin:064-gtp-channel-conf 02_278 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TX_DEEMPH1[5] origin:064-gtp-channel-conf 03_278 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXBUF_EN origin:064-gtp-channel-conf 00_231 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXBUF_RESET_ON_RATE_CHANGE origin:064-gtp-channel-conf 01_231 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXDLY_CFG[0] origin:064-gtp-channel-conf 02_80 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXDLY_CFG[1] origin:064-gtp-channel-conf 03_80 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXDLY_CFG[2] origin:064-gtp-channel-conf 02_81 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXDLY_CFG[3] origin:064-gtp-channel-conf 03_81 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXDLY_CFG[4] origin:064-gtp-channel-conf 02_82 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXDLY_CFG[5] origin:064-gtp-channel-conf 03_82 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXDLY_CFG[6] origin:064-gtp-channel-conf 02_83 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXDLY_CFG[7] origin:064-gtp-channel-conf 03_83 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXDLY_CFG[8] origin:064-gtp-channel-conf 02_84 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXDLY_CFG[9] origin:064-gtp-channel-conf 03_84 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXDLY_CFG[10] origin:064-gtp-channel-conf 02_85 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXDLY_CFG[11] origin:064-gtp-channel-conf 03_85 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXDLY_CFG[12] origin:064-gtp-channel-conf 02_86 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXDLY_CFG[13] origin:064-gtp-channel-conf 03_86 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXDLY_CFG[14] origin:064-gtp-channel-conf 02_87 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXDLY_CFG[15] origin:064-gtp-channel-conf 03_87 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXDLY_LCFG[0] origin:064-gtp-channel-conf 02_568 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXDLY_LCFG[1] origin:064-gtp-channel-conf 03_568 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXDLY_LCFG[2] origin:064-gtp-channel-conf 02_569 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXDLY_LCFG[3] origin:064-gtp-channel-conf 03_569 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXDLY_LCFG[4] origin:064-gtp-channel-conf 02_570 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXDLY_LCFG[5] origin:064-gtp-channel-conf 03_570 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXDLY_LCFG[6] origin:064-gtp-channel-conf 02_571 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXDLY_LCFG[7] origin:064-gtp-channel-conf 03_571 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXDLY_LCFG[8] origin:064-gtp-channel-conf 02_572 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXDLY_TAP_CFG[0] origin:064-gtp-channel-conf 02_88 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXDLY_TAP_CFG[1] origin:064-gtp-channel-conf 03_88 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXDLY_TAP_CFG[2] origin:064-gtp-channel-conf 02_89 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXDLY_TAP_CFG[3] origin:064-gtp-channel-conf 03_89 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXDLY_TAP_CFG[4] origin:064-gtp-channel-conf 02_90 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXDLY_TAP_CFG[5] origin:064-gtp-channel-conf 03_90 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXDLY_TAP_CFG[6] origin:064-gtp-channel-conf 02_91 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXDLY_TAP_CFG[7] origin:064-gtp-channel-conf 03_91 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXDLY_TAP_CFG[8] origin:064-gtp-channel-conf 02_92 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXDLY_TAP_CFG[9] origin:064-gtp-channel-conf 03_92 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXDLY_TAP_CFG[10] origin:064-gtp-channel-conf 02_93 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXDLY_TAP_CFG[11] origin:064-gtp-channel-conf 03_93 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXDLY_TAP_CFG[12] origin:064-gtp-channel-conf 02_94 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXDLY_TAP_CFG[13] origin:064-gtp-channel-conf 03_94 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXDLY_TAP_CFG[14] origin:064-gtp-channel-conf 02_95 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXDLY_TAP_CFG[15] origin:064-gtp-channel-conf 03_95 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXGEARBOX_EN origin:064-gtp-channel-conf 01_226 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXOOB_CFG[0] origin:064-gtp-channel-conf 03_20 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXOUT_DIV[0] origin:064-gtp-channel-conf 02_386 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXOUT_DIV[1] origin:064-gtp-channel-conf 03_386 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPCSRESET_TIME[0] origin:064-gtp-channel-conf 01_130 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPCSRESET_TIME[1] origin:064-gtp-channel-conf 00_131 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPCSRESET_TIME[2] origin:064-gtp-channel-conf 01_131 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPCSRESET_TIME[3] origin:064-gtp-channel-conf 00_132 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPCSRESET_TIME[4] origin:064-gtp-channel-conf 01_132 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPH_CFG[0] origin:064-gtp-channel-conf 02_96 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPH_CFG[1] origin:064-gtp-channel-conf 03_96 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPH_CFG[2] origin:064-gtp-channel-conf 02_97 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPH_CFG[3] origin:064-gtp-channel-conf 03_97 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPH_CFG[4] origin:064-gtp-channel-conf 02_98 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPH_CFG[5] origin:064-gtp-channel-conf 03_98 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPH_CFG[6] origin:064-gtp-channel-conf 02_99 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPH_CFG[7] origin:064-gtp-channel-conf 03_99 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPH_CFG[8] origin:064-gtp-channel-conf 02_100 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPH_CFG[9] origin:064-gtp-channel-conf 03_100 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPH_CFG[10] origin:064-gtp-channel-conf 02_101 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPH_CFG[11] origin:064-gtp-channel-conf 03_101 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPH_CFG[12] origin:064-gtp-channel-conf 02_102 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPH_CFG[13] origin:064-gtp-channel-conf 03_102 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPH_CFG[14] origin:064-gtp-channel-conf 02_103 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPH_CFG[15] origin:064-gtp-channel-conf 03_103 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPH_MONITOR_SEL[0] origin:064-gtp-channel-conf 02_108 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPH_MONITOR_SEL[1] origin:064-gtp-channel-conf 03_108 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPH_MONITOR_SEL[2] origin:064-gtp-channel-conf 02_109 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPH_MONITOR_SEL[3] origin:064-gtp-channel-conf 03_109 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPH_MONITOR_SEL[4] origin:064-gtp-channel-conf 02_110 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[0] origin:064-gtp-channel-conf 02_64 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[1] origin:064-gtp-channel-conf 03_64 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[2] origin:064-gtp-channel-conf 02_65 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[3] origin:064-gtp-channel-conf 03_65 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[4] origin:064-gtp-channel-conf 02_66 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[5] origin:064-gtp-channel-conf 03_66 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[6] origin:064-gtp-channel-conf 02_67 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[7] origin:064-gtp-channel-conf 03_67 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[8] origin:064-gtp-channel-conf 02_68 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[9] origin:064-gtp-channel-conf 03_68 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[10] origin:064-gtp-channel-conf 02_69 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[11] origin:064-gtp-channel-conf 03_69 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[12] origin:064-gtp-channel-conf 02_70 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[13] origin:064-gtp-channel-conf 03_70 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[14] origin:064-gtp-channel-conf 02_71 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[15] origin:064-gtp-channel-conf 03_71 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[16] origin:064-gtp-channel-conf 02_72 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[17] origin:064-gtp-channel-conf 03_72 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[18] origin:064-gtp-channel-conf 02_73 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[19] origin:064-gtp-channel-conf 03_73 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[20] origin:064-gtp-channel-conf 02_74 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[21] origin:064-gtp-channel-conf 03_74 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[22] origin:064-gtp-channel-conf 02_75 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[23] origin:064-gtp-channel-conf 03_75 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPI_GREY_SEL[0] origin:064-gtp-channel-conf 03_498 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPI_INVSTROBE_SEL[0] origin:064-gtp-channel-conf 02_498 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPI_PPM_CFG[0] origin:064-gtp-channel-conf 02_488 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPI_PPM_CFG[1] origin:064-gtp-channel-conf 03_488 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPI_PPM_CFG[2] origin:064-gtp-channel-conf 02_489 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPI_PPM_CFG[3] origin:064-gtp-channel-conf 03_489 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPI_PPM_CFG[4] origin:064-gtp-channel-conf 02_490 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPI_PPM_CFG[5] origin:064-gtp-channel-conf 03_490 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPI_PPM_CFG[6] origin:064-gtp-channel-conf 02_491 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPI_PPM_CFG[7] origin:064-gtp-channel-conf 03_491 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPI_PPMCLK_SEL.TXUSRCLK2 origin:064-gtp-channel-conf 03_497 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPI_SYNFREQ_PPM[0] origin:064-gtp-channel-conf 02_496 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPI_SYNFREQ_PPM[1] origin:064-gtp-channel-conf 03_496 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPI_SYNFREQ_PPM[2] origin:064-gtp-channel-conf 02_497 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPI_CFG0[0] origin:064-gtp-channel-conf 02_40 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPI_CFG0[1] origin:064-gtp-channel-conf 03_40 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPI_CFG1[0] origin:064-gtp-channel-conf 02_41 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPI_CFG1[1] origin:064-gtp-channel-conf 03_41 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPI_CFG2[0] origin:064-gtp-channel-conf 02_42 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPI_CFG2[1] origin:064-gtp-channel-conf 03_42 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPI_CFG3[0] origin:064-gtp-channel-conf 02_43 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPI_CFG4[0] origin:064-gtp-channel-conf 03_43 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPI_CFG5[0] origin:064-gtp-channel-conf 02_44 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPI_CFG5[1] origin:064-gtp-channel-conf 03_44 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPI_CFG5[2] origin:064-gtp-channel-conf 02_45 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPMARESET_TIME[0] origin:064-gtp-channel-conf 00_128 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPMARESET_TIME[1] origin:064-gtp-channel-conf 01_128 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPMARESET_TIME[2] origin:064-gtp-channel-conf 00_129 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPMARESET_TIME[3] origin:064-gtp-channel-conf 01_129 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXPMARESET_TIME[4] origin:064-gtp-channel-conf 00_130 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXSYNC_MULTILANE[0] origin:064-gtp-channel-conf 01_133 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXSYNC_OVRD[0] origin:064-gtp-channel-conf 00_135 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.TXSYNC_SKIP_DA[0] origin:064-gtp-channel-conf 00_134 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.UCODEER_CLR[0] origin:064-gtp-channel-conf 01_00 +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL.USE_PCS_CLK_PHASE_SEL[0] origin:064-gtp-channel-conf 02_463 diff --git a/artix7/segbits_gtp_channel_3.db b/artix7/segbits_gtp_channel_3.db index f263534..ba58804 100644 --- a/artix7/segbits_gtp_channel_3.db +++ b/artix7/segbits_gtp_channel_3.db @@ -1,1627 +1,1627 @@ -GTP_CHANNEL_3.GTPE2.ACJTAG_DEBUG_MODE[0] 28_07 -GTP_CHANNEL_3.GTPE2.ACJTAG_MODE[0] 29_06 -GTP_CHANNEL_3.GTPE2.ACJTAG_RESET[0] 29_07 -GTP_CHANNEL_3.GTPE2.ADAPT_CFG0[0] 30_464 -GTP_CHANNEL_3.GTPE2.ADAPT_CFG0[1] 31_464 -GTP_CHANNEL_3.GTPE2.ADAPT_CFG0[2] 30_465 -GTP_CHANNEL_3.GTPE2.ADAPT_CFG0[3] 31_465 -GTP_CHANNEL_3.GTPE2.ADAPT_CFG0[4] 30_466 -GTP_CHANNEL_3.GTPE2.ADAPT_CFG0[5] 31_466 -GTP_CHANNEL_3.GTPE2.ADAPT_CFG0[6] 30_467 -GTP_CHANNEL_3.GTPE2.ADAPT_CFG0[7] 31_467 -GTP_CHANNEL_3.GTPE2.ADAPT_CFG0[8] 30_468 -GTP_CHANNEL_3.GTPE2.ADAPT_CFG0[9] 31_468 -GTP_CHANNEL_3.GTPE2.ADAPT_CFG0[10] 30_469 -GTP_CHANNEL_3.GTPE2.ADAPT_CFG0[11] 31_469 -GTP_CHANNEL_3.GTPE2.ADAPT_CFG0[12] 30_470 -GTP_CHANNEL_3.GTPE2.ADAPT_CFG0[13] 31_470 -GTP_CHANNEL_3.GTPE2.ADAPT_CFG0[14] 30_471 -GTP_CHANNEL_3.GTPE2.ADAPT_CFG0[15] 31_471 -GTP_CHANNEL_3.GTPE2.ADAPT_CFG0[16] 30_472 -GTP_CHANNEL_3.GTPE2.ADAPT_CFG0[17] 31_472 -GTP_CHANNEL_3.GTPE2.ADAPT_CFG0[18] 30_473 -GTP_CHANNEL_3.GTPE2.ADAPT_CFG0[19] 31_473 -GTP_CHANNEL_3.GTPE2.ALIGN_COMMA_DOUBLE 28_522 -GTP_CHANNEL_3.GTPE2.ALIGN_COMMA_ENABLE[0] 28_496 -GTP_CHANNEL_3.GTPE2.ALIGN_COMMA_ENABLE[1] 29_496 -GTP_CHANNEL_3.GTPE2.ALIGN_COMMA_ENABLE[2] 28_497 -GTP_CHANNEL_3.GTPE2.ALIGN_COMMA_ENABLE[3] 29_497 -GTP_CHANNEL_3.GTPE2.ALIGN_COMMA_ENABLE[4] 28_498 -GTP_CHANNEL_3.GTPE2.ALIGN_COMMA_ENABLE[5] 29_498 -GTP_CHANNEL_3.GTPE2.ALIGN_COMMA_ENABLE[6] 28_499 -GTP_CHANNEL_3.GTPE2.ALIGN_COMMA_ENABLE[7] 29_499 -GTP_CHANNEL_3.GTPE2.ALIGN_COMMA_ENABLE[8] 28_500 -GTP_CHANNEL_3.GTPE2.ALIGN_COMMA_ENABLE[9] 29_500 -GTP_CHANNEL_3.GTPE2.ALIGN_COMMA_WORD[0] 29_526 -GTP_CHANNEL_3.GTPE2.ALIGN_COMMA_WORD[1] 28_527 -GTP_CHANNEL_3.GTPE2.ALIGN_MCOMMA_DET 28_523 -GTP_CHANNEL_3.GTPE2.ALIGN_MCOMMA_VALUE[0] 28_504 -GTP_CHANNEL_3.GTPE2.ALIGN_MCOMMA_VALUE[1] 29_504 -GTP_CHANNEL_3.GTPE2.ALIGN_MCOMMA_VALUE[2] 28_505 -GTP_CHANNEL_3.GTPE2.ALIGN_MCOMMA_VALUE[3] 29_505 -GTP_CHANNEL_3.GTPE2.ALIGN_MCOMMA_VALUE[4] 28_506 -GTP_CHANNEL_3.GTPE2.ALIGN_MCOMMA_VALUE[5] 29_506 -GTP_CHANNEL_3.GTPE2.ALIGN_MCOMMA_VALUE[6] 28_507 -GTP_CHANNEL_3.GTPE2.ALIGN_MCOMMA_VALUE[7] 29_507 -GTP_CHANNEL_3.GTPE2.ALIGN_MCOMMA_VALUE[8] 28_508 -GTP_CHANNEL_3.GTPE2.ALIGN_MCOMMA_VALUE[9] 29_508 -GTP_CHANNEL_3.GTPE2.ALIGN_PCOMMA_DET 29_523 -GTP_CHANNEL_3.GTPE2.ALIGN_PCOMMA_VALUE[0] 28_512 -GTP_CHANNEL_3.GTPE2.ALIGN_PCOMMA_VALUE[1] 29_512 -GTP_CHANNEL_3.GTPE2.ALIGN_PCOMMA_VALUE[2] 28_513 -GTP_CHANNEL_3.GTPE2.ALIGN_PCOMMA_VALUE[3] 29_513 -GTP_CHANNEL_3.GTPE2.ALIGN_PCOMMA_VALUE[4] 28_514 -GTP_CHANNEL_3.GTPE2.ALIGN_PCOMMA_VALUE[5] 29_514 -GTP_CHANNEL_3.GTPE2.ALIGN_PCOMMA_VALUE[6] 28_515 -GTP_CHANNEL_3.GTPE2.ALIGN_PCOMMA_VALUE[7] 29_515 -GTP_CHANNEL_3.GTPE2.ALIGN_PCOMMA_VALUE[8] 28_516 -GTP_CHANNEL_3.GTPE2.ALIGN_PCOMMA_VALUE[9] 29_516 -GTP_CHANNEL_3.GTPE2.CBCC_DATA_SOURCE_SEL.DECODED 29_661 -GTP_CHANNEL_3.GTPE2.CFOK_CFG[0] 30_392 -GTP_CHANNEL_3.GTPE2.CFOK_CFG[1] 31_392 -GTP_CHANNEL_3.GTPE2.CFOK_CFG[2] 30_393 -GTP_CHANNEL_3.GTPE2.CFOK_CFG[3] 31_393 -GTP_CHANNEL_3.GTPE2.CFOK_CFG[4] 30_394 -GTP_CHANNEL_3.GTPE2.CFOK_CFG[5] 31_394 -GTP_CHANNEL_3.GTPE2.CFOK_CFG[6] 30_395 -GTP_CHANNEL_3.GTPE2.CFOK_CFG[7] 31_395 -GTP_CHANNEL_3.GTPE2.CFOK_CFG[8] 30_396 -GTP_CHANNEL_3.GTPE2.CFOK_CFG[9] 31_396 -GTP_CHANNEL_3.GTPE2.CFOK_CFG[10] 30_397 -GTP_CHANNEL_3.GTPE2.CFOK_CFG[11] 31_397 -GTP_CHANNEL_3.GTPE2.CFOK_CFG[12] 30_398 -GTP_CHANNEL_3.GTPE2.CFOK_CFG[13] 31_398 -GTP_CHANNEL_3.GTPE2.CFOK_CFG[14] 30_399 -GTP_CHANNEL_3.GTPE2.CFOK_CFG[15] 31_399 -GTP_CHANNEL_3.GTPE2.CFOK_CFG[16] 30_400 -GTP_CHANNEL_3.GTPE2.CFOK_CFG[17] 31_400 -GTP_CHANNEL_3.GTPE2.CFOK_CFG[18] 30_401 -GTP_CHANNEL_3.GTPE2.CFOK_CFG[19] 31_401 -GTP_CHANNEL_3.GTPE2.CFOK_CFG[20] 30_402 -GTP_CHANNEL_3.GTPE2.CFOK_CFG[21] 31_402 -GTP_CHANNEL_3.GTPE2.CFOK_CFG[22] 30_403 -GTP_CHANNEL_3.GTPE2.CFOK_CFG[23] 31_403 -GTP_CHANNEL_3.GTPE2.CFOK_CFG[24] 30_404 -GTP_CHANNEL_3.GTPE2.CFOK_CFG[25] 31_404 -GTP_CHANNEL_3.GTPE2.CFOK_CFG[26] 30_405 -GTP_CHANNEL_3.GTPE2.CFOK_CFG[27] 31_405 -GTP_CHANNEL_3.GTPE2.CFOK_CFG[28] 30_406 -GTP_CHANNEL_3.GTPE2.CFOK_CFG[29] 31_406 -GTP_CHANNEL_3.GTPE2.CFOK_CFG[30] 30_407 -GTP_CHANNEL_3.GTPE2.CFOK_CFG[31] 31_407 -GTP_CHANNEL_3.GTPE2.CFOK_CFG[32] 30_408 -GTP_CHANNEL_3.GTPE2.CFOK_CFG[33] 31_408 -GTP_CHANNEL_3.GTPE2.CFOK_CFG[34] 30_409 -GTP_CHANNEL_3.GTPE2.CFOK_CFG[35] 31_409 -GTP_CHANNEL_3.GTPE2.CFOK_CFG[36] 30_410 -GTP_CHANNEL_3.GTPE2.CFOK_CFG[37] 31_410 -GTP_CHANNEL_3.GTPE2.CFOK_CFG[38] 30_411 -GTP_CHANNEL_3.GTPE2.CFOK_CFG[39] 31_411 -GTP_CHANNEL_3.GTPE2.CFOK_CFG[40] 30_412 -GTP_CHANNEL_3.GTPE2.CFOK_CFG[41] 31_412 -GTP_CHANNEL_3.GTPE2.CFOK_CFG[42] 30_413 -GTP_CHANNEL_3.GTPE2.CFOK_CFG2[0] 30_459 -GTP_CHANNEL_3.GTPE2.CFOK_CFG2[1] 31_459 -GTP_CHANNEL_3.GTPE2.CFOK_CFG2[2] 30_460 -GTP_CHANNEL_3.GTPE2.CFOK_CFG2[3] 31_460 -GTP_CHANNEL_3.GTPE2.CFOK_CFG2[4] 30_461 -GTP_CHANNEL_3.GTPE2.CFOK_CFG2[5] 31_461 -GTP_CHANNEL_3.GTPE2.CFOK_CFG2[6] 30_462 -GTP_CHANNEL_3.GTPE2.CFOK_CFG3[0] 30_416 -GTP_CHANNEL_3.GTPE2.CFOK_CFG3[1] 31_416 -GTP_CHANNEL_3.GTPE2.CFOK_CFG3[2] 30_417 -GTP_CHANNEL_3.GTPE2.CFOK_CFG3[3] 31_417 -GTP_CHANNEL_3.GTPE2.CFOK_CFG3[4] 30_418 -GTP_CHANNEL_3.GTPE2.CFOK_CFG3[5] 31_418 -GTP_CHANNEL_3.GTPE2.CFOK_CFG3[6] 30_419 -GTP_CHANNEL_3.GTPE2.CFOK_CFG4[0] 31_438 -GTP_CHANNEL_3.GTPE2.CFOK_CFG5[0] 30_429 -GTP_CHANNEL_3.GTPE2.CFOK_CFG5[1] 31_429 -GTP_CHANNEL_3.GTPE2.CFOK_CFG6[0] 31_436 -GTP_CHANNEL_3.GTPE2.CFOK_CFG6[1] 30_437 -GTP_CHANNEL_3.GTPE2.CFOK_CFG6[2] 31_437 -GTP_CHANNEL_3.GTPE2.CFOK_CFG6[3] 30_438 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_KEEP_ALIGN 29_631 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_MAX_SKEW[0] 28_670 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_MAX_SKEW[1] 29_670 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_MAX_SKEW[2] 28_671 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_MAX_SKEW[3] 29_671 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_1_1[0] 28_608 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_1_1[1] 29_608 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_1_1[2] 28_609 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_1_1[3] 29_609 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_1_1[4] 28_610 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_1_1[5] 29_610 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_1_1[6] 28_611 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_1_1[7] 29_611 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_1_1[8] 28_612 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_1_1[9] 29_612 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_1_2[0] 28_616 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_1_2[1] 29_616 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_1_2[2] 28_617 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_1_2[3] 29_617 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_1_2[4] 28_618 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_1_2[5] 29_618 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_1_2[6] 28_619 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_1_2[7] 29_619 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_1_2[8] 28_620 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_1_2[9] 29_620 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_1_3[0] 28_624 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_1_3[1] 29_624 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_1_3[2] 28_625 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_1_3[3] 29_625 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_1_3[4] 28_626 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_1_3[5] 29_626 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_1_3[6] 28_627 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_1_3[7] 29_627 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_1_3[8] 28_628 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_1_3[9] 29_628 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_1_4[0] 28_632 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_1_4[1] 29_632 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_1_4[2] 28_633 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_1_4[3] 29_633 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_1_4[4] 28_634 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_1_4[5] 29_634 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_1_4[6] 28_635 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_1_4[7] 29_635 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_1_4[8] 28_636 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_1_4[9] 29_636 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_1_ENABLE[0] 28_614 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_1_ENABLE[1] 29_614 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_1_ENABLE[2] 28_615 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_1_ENABLE[3] 29_615 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_2_1[0] 28_640 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_2_1[1] 29_640 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_2_1[2] 28_641 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_2_1[3] 29_641 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_2_1[4] 28_642 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_2_1[5] 29_642 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_2_1[6] 28_643 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_2_1[7] 29_643 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_2_1[8] 28_644 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_2_1[9] 29_644 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_2_2[0] 28_648 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_2_2[1] 29_648 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_2_2[2] 28_649 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_2_2[3] 29_649 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_2_2[4] 28_650 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_2_2[5] 29_650 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_2_2[6] 28_651 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_2_2[7] 29_651 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_2_2[8] 28_652 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_2_2[9] 29_652 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_2_3[0] 28_656 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_2_3[1] 29_656 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_2_3[2] 28_657 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_2_3[3] 29_657 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_2_3[4] 28_658 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_2_3[5] 29_658 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_2_3[6] 28_659 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_2_3[7] 29_659 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_2_3[8] 28_660 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_2_3[9] 29_660 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_2_4[0] 28_664 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_2_4[1] 29_664 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_2_4[2] 28_665 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_2_4[3] 29_665 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_2_4[4] 28_666 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_2_4[5] 29_666 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_2_4[6] 28_667 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_2_4[7] 29_667 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_2_4[8] 28_668 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_2_4[9] 29_668 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_2_ENABLE[0] 28_646 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_2_ENABLE[1] 29_646 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_2_ENABLE[2] 28_647 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_2_ENABLE[3] 29_647 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_2_USE 29_645 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_LEN[0] 28_623 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_LEN[1] 29_623 -GTP_CHANNEL_3.GTPE2.CLK_COMMON_SWING[0] 31_311 -GTP_CHANNEL_3.GTPE2.CLK_COR_KEEP_IDLE 28_591 -GTP_CHANNEL_3.GTPE2.CLK_COR_MAX_LAT[0] 28_557 -GTP_CHANNEL_3.GTPE2.CLK_COR_MAX_LAT[1] 29_557 -GTP_CHANNEL_3.GTPE2.CLK_COR_MAX_LAT[2] 28_558 -GTP_CHANNEL_3.GTPE2.CLK_COR_MAX_LAT[3] 29_558 -GTP_CHANNEL_3.GTPE2.CLK_COR_MAX_LAT[4] 28_559 -GTP_CHANNEL_3.GTPE2.CLK_COR_MAX_LAT[5] 29_559 -GTP_CHANNEL_3.GTPE2.CLK_COR_MIN_LAT[0] 28_565 -GTP_CHANNEL_3.GTPE2.CLK_COR_MIN_LAT[1] 29_565 -GTP_CHANNEL_3.GTPE2.CLK_COR_MIN_LAT[2] 28_566 -GTP_CHANNEL_3.GTPE2.CLK_COR_MIN_LAT[3] 29_566 -GTP_CHANNEL_3.GTPE2.CLK_COR_MIN_LAT[4] 28_567 -GTP_CHANNEL_3.GTPE2.CLK_COR_MIN_LAT[5] 29_567 -GTP_CHANNEL_3.GTPE2.CLK_COR_PRECEDENCE 28_590 -GTP_CHANNEL_3.GTPE2.CLK_COR_REPEAT_WAIT[0] 28_573 -GTP_CHANNEL_3.GTPE2.CLK_COR_REPEAT_WAIT[1] 29_573 -GTP_CHANNEL_3.GTPE2.CLK_COR_REPEAT_WAIT[2] 28_574 -GTP_CHANNEL_3.GTPE2.CLK_COR_REPEAT_WAIT[3] 29_574 -GTP_CHANNEL_3.GTPE2.CLK_COR_REPEAT_WAIT[4] 28_575 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_1_1[0] 28_544 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_1_1[1] 29_544 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_1_1[2] 28_545 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_1_1[3] 29_545 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_1_1[4] 28_546 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_1_1[5] 29_546 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_1_1[6] 28_547 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_1_1[7] 29_547 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_1_1[8] 28_548 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_1_1[9] 29_548 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_1_2[0] 28_552 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_1_2[1] 29_552 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_1_2[2] 28_553 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_1_2[3] 29_553 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_1_2[4] 28_554 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_1_2[5] 29_554 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_1_2[6] 28_555 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_1_2[7] 29_555 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_1_2[8] 28_556 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_1_2[9] 29_556 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_1_3[0] 28_560 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_1_3[1] 29_560 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_1_3[2] 28_561 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_1_3[3] 29_561 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_1_3[4] 28_562 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_1_3[5] 29_562 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_1_3[6] 28_563 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_1_3[7] 29_563 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_1_3[8] 28_564 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_1_3[9] 29_564 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_1_4[0] 28_568 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_1_4[1] 29_568 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_1_4[2] 28_569 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_1_4[3] 29_569 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_1_4[4] 28_570 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_1_4[5] 29_570 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_1_4[6] 28_571 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_1_4[7] 29_571 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_1_4[8] 28_572 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_1_4[9] 29_572 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_1_ENABLE[0] 28_549 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_1_ENABLE[1] 29_549 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_1_ENABLE[2] 28_550 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_1_ENABLE[3] 29_550 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_2_1[0] 28_576 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_2_1[1] 29_576 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_2_1[2] 28_577 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_2_1[3] 29_577 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_2_1[4] 28_578 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_2_1[5] 29_578 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_2_1[6] 28_579 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_2_1[7] 29_579 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_2_1[8] 28_580 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_2_1[9] 29_580 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_2_2[0] 28_584 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_2_2[1] 29_584 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_2_2[2] 28_585 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_2_2[3] 29_585 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_2_2[4] 28_586 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_2_2[5] 29_586 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_2_2[6] 28_587 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_2_2[7] 29_587 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_2_2[8] 28_588 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_2_2[9] 29_588 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_2_3[0] 28_592 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_2_3[1] 29_592 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_2_3[2] 28_593 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_2_3[3] 29_593 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_2_3[4] 28_594 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_2_3[5] 29_594 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_2_3[6] 28_595 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_2_3[7] 29_595 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_2_3[8] 28_596 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_2_3[9] 29_596 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_2_4[0] 28_600 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_2_4[1] 29_600 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_2_4[2] 28_601 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_2_4[3] 29_601 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_2_4[4] 28_602 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_2_4[5] 29_602 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_2_4[6] 28_603 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_2_4[7] 29_603 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_2_4[8] 28_604 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_2_4[9] 29_604 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_2_ENABLE[0] 28_581 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_2_ENABLE[1] 29_581 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_2_ENABLE[2] 28_582 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_2_ENABLE[3] 29_582 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_2_USE 28_583 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_LEN[0] 28_589 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_LEN[1] 29_589 -GTP_CHANNEL_3.GTPE2.CLK_CORRECT_USE 28_551 -GTP_CHANNEL_3.GTPE2.DEC_MCOMMA_DETECT 29_494 -GTP_CHANNEL_3.GTPE2.DEC_PCOMMA_DETECT 28_495 -GTP_CHANNEL_3.GTPE2.DEC_VALID_COMMA_ONLY 28_494 -GTP_CHANNEL_3.GTPE2.DMONITOR_CFG[0] 30_368 -GTP_CHANNEL_3.GTPE2.DMONITOR_CFG[1] 31_368 -GTP_CHANNEL_3.GTPE2.DMONITOR_CFG[2] 30_369 -GTP_CHANNEL_3.GTPE2.DMONITOR_CFG[3] 31_369 -GTP_CHANNEL_3.GTPE2.DMONITOR_CFG[4] 30_370 -GTP_CHANNEL_3.GTPE2.DMONITOR_CFG[5] 31_370 -GTP_CHANNEL_3.GTPE2.DMONITOR_CFG[6] 30_371 -GTP_CHANNEL_3.GTPE2.DMONITOR_CFG[7] 31_371 -GTP_CHANNEL_3.GTPE2.DMONITOR_CFG[8] 30_372 -GTP_CHANNEL_3.GTPE2.DMONITOR_CFG[9] 31_372 -GTP_CHANNEL_3.GTPE2.DMONITOR_CFG[10] 30_373 -GTP_CHANNEL_3.GTPE2.DMONITOR_CFG[11] 31_373 -GTP_CHANNEL_3.GTPE2.DMONITOR_CFG[12] 30_374 -GTP_CHANNEL_3.GTPE2.DMONITOR_CFG[13] 31_374 -GTP_CHANNEL_3.GTPE2.DMONITOR_CFG[14] 30_375 -GTP_CHANNEL_3.GTPE2.DMONITOR_CFG[15] 31_375 -GTP_CHANNEL_3.GTPE2.DMONITOR_CFG[16] 30_376 -GTP_CHANNEL_3.GTPE2.DMONITOR_CFG[17] 31_376 -GTP_CHANNEL_3.GTPE2.DMONITOR_CFG[18] 30_377 -GTP_CHANNEL_3.GTPE2.DMONITOR_CFG[19] 31_377 -GTP_CHANNEL_3.GTPE2.DMONITOR_CFG[20] 30_378 -GTP_CHANNEL_3.GTPE2.DMONITOR_CFG[21] 31_378 -GTP_CHANNEL_3.GTPE2.DMONITOR_CFG[22] 30_379 -GTP_CHANNEL_3.GTPE2.DMONITOR_CFG[23] 31_379 -GTP_CHANNEL_3.GTPE2.ES_CLK_PHASE_SEL[0] 31_463 -GTP_CHANNEL_3.GTPE2.ES_CONTROL[0] 28_488 -GTP_CHANNEL_3.GTPE2.ES_CONTROL[1] 29_488 -GTP_CHANNEL_3.GTPE2.ES_CONTROL[2] 28_489 -GTP_CHANNEL_3.GTPE2.ES_CONTROL[3] 29_489 -GTP_CHANNEL_3.GTPE2.ES_CONTROL[4] 28_490 -GTP_CHANNEL_3.GTPE2.ES_CONTROL[5] 29_490 -GTP_CHANNEL_3.GTPE2.ES_ERRDET_EN 29_492 -GTP_CHANNEL_3.GTPE2.ES_EYE_SCAN_EN 28_492 -GTP_CHANNEL_3.GTPE2.ES_HORZ_OFFSET[0] 28_480 -GTP_CHANNEL_3.GTPE2.ES_HORZ_OFFSET[1] 29_480 -GTP_CHANNEL_3.GTPE2.ES_HORZ_OFFSET[2] 28_481 -GTP_CHANNEL_3.GTPE2.ES_HORZ_OFFSET[3] 29_481 -GTP_CHANNEL_3.GTPE2.ES_HORZ_OFFSET[4] 28_482 -GTP_CHANNEL_3.GTPE2.ES_HORZ_OFFSET[5] 29_482 -GTP_CHANNEL_3.GTPE2.ES_HORZ_OFFSET[6] 28_483 -GTP_CHANNEL_3.GTPE2.ES_HORZ_OFFSET[7] 29_483 -GTP_CHANNEL_3.GTPE2.ES_HORZ_OFFSET[8] 28_484 -GTP_CHANNEL_3.GTPE2.ES_HORZ_OFFSET[9] 29_484 -GTP_CHANNEL_3.GTPE2.ES_HORZ_OFFSET[10] 28_485 -GTP_CHANNEL_3.GTPE2.ES_HORZ_OFFSET[11] 29_485 -GTP_CHANNEL_3.GTPE2.ES_PMA_CFG[0] 30_624 -GTP_CHANNEL_3.GTPE2.ES_PMA_CFG[1] 31_624 -GTP_CHANNEL_3.GTPE2.ES_PMA_CFG[2] 30_625 -GTP_CHANNEL_3.GTPE2.ES_PMA_CFG[3] 31_625 -GTP_CHANNEL_3.GTPE2.ES_PMA_CFG[4] 30_626 -GTP_CHANNEL_3.GTPE2.ES_PMA_CFG[5] 31_626 -GTP_CHANNEL_3.GTPE2.ES_PMA_CFG[6] 30_627 -GTP_CHANNEL_3.GTPE2.ES_PMA_CFG[7] 31_627 -GTP_CHANNEL_3.GTPE2.ES_PMA_CFG[8] 30_628 -GTP_CHANNEL_3.GTPE2.ES_PMA_CFG[9] 31_628 -GTP_CHANNEL_3.GTPE2.ES_PRESCALE[0] 29_477 -GTP_CHANNEL_3.GTPE2.ES_PRESCALE[1] 28_478 -GTP_CHANNEL_3.GTPE2.ES_PRESCALE[2] 29_478 -GTP_CHANNEL_3.GTPE2.ES_PRESCALE[3] 28_479 -GTP_CHANNEL_3.GTPE2.ES_PRESCALE[4] 29_479 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[0] 28_392 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[1] 29_392 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[2] 28_393 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[3] 29_393 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[4] 28_394 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[5] 29_394 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[6] 28_395 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[7] 29_395 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[8] 28_396 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[9] 29_396 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[10] 28_397 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[11] 29_397 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[12] 28_398 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[13] 29_398 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[14] 28_399 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[15] 29_399 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[16] 28_400 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[17] 29_400 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[18] 28_401 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[19] 29_401 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[20] 28_402 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[21] 29_402 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[22] 28_403 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[23] 29_403 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[24] 28_404 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[25] 29_404 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[26] 28_405 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[27] 29_405 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[28] 28_406 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[29] 29_406 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[30] 28_407 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[31] 29_407 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[32] 28_408 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[33] 29_408 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[34] 28_409 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[35] 29_409 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[36] 28_410 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[37] 29_410 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[38] 28_411 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[39] 29_411 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[40] 28_412 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[41] 29_412 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[42] 28_413 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[43] 29_413 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[44] 28_414 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[45] 29_414 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[46] 28_415 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[47] 29_415 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[48] 28_416 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[49] 29_416 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[50] 28_417 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[51] 29_417 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[52] 28_418 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[53] 29_418 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[54] 28_419 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[55] 29_419 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[56] 28_420 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[57] 29_420 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[58] 28_421 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[59] 29_421 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[60] 28_422 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[61] 29_422 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[62] 28_423 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[63] 29_423 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[64] 28_424 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[65] 29_424 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[66] 28_425 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[67] 29_425 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[68] 28_426 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[69] 29_426 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[70] 28_427 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[71] 29_427 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[72] 28_428 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[73] 29_428 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[74] 28_429 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[75] 29_429 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[76] 28_430 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[77] 29_430 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[78] 28_431 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[79] 29_431 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[0] 28_352 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[1] 29_352 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[2] 28_353 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[3] 29_353 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[4] 28_354 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[5] 29_354 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[6] 28_355 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[7] 29_355 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[8] 28_356 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[9] 29_356 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[10] 28_357 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[11] 29_357 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[12] 28_358 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[13] 29_358 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[14] 28_359 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[15] 29_359 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[16] 28_360 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[17] 29_360 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[18] 28_361 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[19] 29_361 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[20] 28_362 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[21] 29_362 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[22] 28_363 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[23] 29_363 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[24] 28_364 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[25] 29_364 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[26] 28_365 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[27] 29_365 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[28] 28_366 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[29] 29_366 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[30] 28_367 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[31] 29_367 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[32] 28_368 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[33] 29_368 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[34] 28_369 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[35] 29_369 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[36] 28_370 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[37] 29_370 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[38] 28_371 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[39] 29_371 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[40] 28_372 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[41] 29_372 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[42] 28_373 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[43] 29_373 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[44] 28_374 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[45] 29_374 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[46] 28_375 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[47] 29_375 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[48] 28_376 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[49] 29_376 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[50] 28_377 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[51] 29_377 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[52] 28_378 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[53] 29_378 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[54] 28_379 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[55] 29_379 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[56] 28_380 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[57] 29_380 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[58] 28_381 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[59] 29_381 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[60] 28_382 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[61] 29_382 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[62] 28_383 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[63] 29_383 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[64] 28_384 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[65] 29_384 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[66] 28_385 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[67] 29_385 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[68] 28_386 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[69] 29_386 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[70] 28_387 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[71] 29_387 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[72] 28_388 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[73] 29_388 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[74] 28_389 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[75] 29_389 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[76] 28_390 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[77] 29_390 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[78] 28_391 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[79] 29_391 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[0] 28_432 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[1] 29_432 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[2] 28_433 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[3] 29_433 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[4] 28_434 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[5] 29_434 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[6] 28_435 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[7] 29_435 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[8] 28_436 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[9] 29_436 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[10] 28_437 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[11] 29_437 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[12] 28_438 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[13] 29_438 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[14] 28_439 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[15] 29_439 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[16] 28_440 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[17] 29_440 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[18] 28_441 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[19] 29_441 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[20] 28_442 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[21] 29_442 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[22] 28_443 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[23] 29_443 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[24] 28_444 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[25] 29_444 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[26] 28_445 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[27] 29_445 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[28] 28_446 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[29] 29_446 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[30] 28_447 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[31] 29_447 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[32] 28_448 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[33] 29_448 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[34] 28_449 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[35] 29_449 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[36] 28_450 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[37] 29_450 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[38] 28_451 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[39] 29_451 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[40] 28_452 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[41] 29_452 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[42] 28_453 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[43] 29_453 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[44] 28_454 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[45] 29_454 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[46] 28_455 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[47] 29_455 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[48] 28_456 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[49] 29_456 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[50] 28_457 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[51] 29_457 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[52] 28_458 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[53] 29_458 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[54] 28_459 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[55] 29_459 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[56] 28_460 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[57] 29_460 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[58] 28_461 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[59] 29_461 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[60] 28_462 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[61] 29_462 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[62] 28_463 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[63] 29_463 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[64] 28_464 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[65] 29_464 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[66] 28_465 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[67] 29_465 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[68] 28_466 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[69] 29_466 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[70] 28_467 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[71] 29_467 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[72] 28_468 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[73] 29_468 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[74] 28_469 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[75] 29_469 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[76] 28_470 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[77] 29_470 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[78] 28_471 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[79] 29_471 -GTP_CHANNEL_3.GTPE2.ES_VERT_OFFSET[0] 28_472 -GTP_CHANNEL_3.GTPE2.ES_VERT_OFFSET[1] 29_472 -GTP_CHANNEL_3.GTPE2.ES_VERT_OFFSET[2] 28_473 -GTP_CHANNEL_3.GTPE2.ES_VERT_OFFSET[3] 29_473 -GTP_CHANNEL_3.GTPE2.ES_VERT_OFFSET[4] 28_474 -GTP_CHANNEL_3.GTPE2.ES_VERT_OFFSET[5] 29_474 -GTP_CHANNEL_3.GTPE2.ES_VERT_OFFSET[6] 28_475 -GTP_CHANNEL_3.GTPE2.ES_VERT_OFFSET[7] 29_475 -GTP_CHANNEL_3.GTPE2.ES_VERT_OFFSET[8] 28_476 -GTP_CHANNEL_3.GTPE2.FTS_DESKEW_SEQ_ENABLE[0] 28_662 -GTP_CHANNEL_3.GTPE2.FTS_DESKEW_SEQ_ENABLE[1] 29_662 -GTP_CHANNEL_3.GTPE2.FTS_DESKEW_SEQ_ENABLE[2] 28_663 -GTP_CHANNEL_3.GTPE2.FTS_DESKEW_SEQ_ENABLE[3] 29_663 -GTP_CHANNEL_3.GTPE2.FTS_LANE_DESKEW_CFG[0] 28_654 -GTP_CHANNEL_3.GTPE2.FTS_LANE_DESKEW_CFG[1] 29_654 -GTP_CHANNEL_3.GTPE2.FTS_LANE_DESKEW_CFG[2] 28_655 -GTP_CHANNEL_3.GTPE2.FTS_LANE_DESKEW_CFG[3] 29_655 -GTP_CHANNEL_3.GTPE2.FTS_LANE_DESKEW_EN 29_653 -GTP_CHANNEL_3.GTPE2.GEARBOX_MODE[0] 28_224 -GTP_CHANNEL_3.GTPE2.GEARBOX_MODE[1] 29_224 -GTP_CHANNEL_3.GTPE2.GEARBOX_MODE[2] 28_225 -GTP_CHANNEL_3.GTPE2.IN_USE 28_00 28_01 28_47 28_52 28_53 28_65 29_01 29_47 30_129 -GTP_CHANNEL_3.GTPE2.LOOPBACK_CFG[0] 30_20 -GTP_CHANNEL_3.GTPE2.OUTREFCLK_SEL_INV[0] 28_149 -GTP_CHANNEL_3.GTPE2.OUTREFCLK_SEL_INV[1] 29_149 -GTP_CHANNEL_3.GTPE2.PCS_PCIE_EN 28_216 -GTP_CHANNEL_3.GTPE2.PCS_RSVD_ATTR[0] 30_184 -GTP_CHANNEL_3.GTPE2.PCS_RSVD_ATTR[1] 31_184 -GTP_CHANNEL_3.GTPE2.PCS_RSVD_ATTR[2] 30_185 -GTP_CHANNEL_3.GTPE2.PCS_RSVD_ATTR[3] 31_185 -GTP_CHANNEL_3.GTPE2.PCS_RSVD_ATTR[4] 30_186 -GTP_CHANNEL_3.GTPE2.PCS_RSVD_ATTR[5] 31_186 -GTP_CHANNEL_3.GTPE2.PCS_RSVD_ATTR[6] 30_187 -GTP_CHANNEL_3.GTPE2.PCS_RSVD_ATTR[7] 31_187 -GTP_CHANNEL_3.GTPE2.PCS_RSVD_ATTR[8] 30_188 -GTP_CHANNEL_3.GTPE2.PCS_RSVD_ATTR[9] 31_188 -GTP_CHANNEL_3.GTPE2.PCS_RSVD_ATTR[10] 30_189 -GTP_CHANNEL_3.GTPE2.PCS_RSVD_ATTR[11] 31_189 -GTP_CHANNEL_3.GTPE2.PCS_RSVD_ATTR[12] 30_190 -GTP_CHANNEL_3.GTPE2.PCS_RSVD_ATTR[13] 31_190 -GTP_CHANNEL_3.GTPE2.PCS_RSVD_ATTR[14] 30_191 -GTP_CHANNEL_3.GTPE2.PCS_RSVD_ATTR[15] 31_191 -GTP_CHANNEL_3.GTPE2.PCS_RSVD_ATTR[16] 30_192 -GTP_CHANNEL_3.GTPE2.PCS_RSVD_ATTR[17] 31_192 -GTP_CHANNEL_3.GTPE2.PCS_RSVD_ATTR[18] 30_193 -GTP_CHANNEL_3.GTPE2.PCS_RSVD_ATTR[19] 31_193 -GTP_CHANNEL_3.GTPE2.PCS_RSVD_ATTR[20] 30_194 -GTP_CHANNEL_3.GTPE2.PCS_RSVD_ATTR[21] 31_194 -GTP_CHANNEL_3.GTPE2.PCS_RSVD_ATTR[22] 30_195 -GTP_CHANNEL_3.GTPE2.PCS_RSVD_ATTR[23] 31_195 -GTP_CHANNEL_3.GTPE2.PCS_RSVD_ATTR[24] 30_196 -GTP_CHANNEL_3.GTPE2.PCS_RSVD_ATTR[25] 31_196 -GTP_CHANNEL_3.GTPE2.PCS_RSVD_ATTR[26] 30_197 -GTP_CHANNEL_3.GTPE2.PCS_RSVD_ATTR[27] 31_197 -GTP_CHANNEL_3.GTPE2.PCS_RSVD_ATTR[28] 30_198 -GTP_CHANNEL_3.GTPE2.PCS_RSVD_ATTR[29] 31_198 -GTP_CHANNEL_3.GTPE2.PCS_RSVD_ATTR[30] 30_199 -GTP_CHANNEL_3.GTPE2.PCS_RSVD_ATTR[31] 31_199 -GTP_CHANNEL_3.GTPE2.PCS_RSVD_ATTR[32] 30_200 -GTP_CHANNEL_3.GTPE2.PCS_RSVD_ATTR[33] 31_200 -GTP_CHANNEL_3.GTPE2.PCS_RSVD_ATTR[34] 30_201 -GTP_CHANNEL_3.GTPE2.PCS_RSVD_ATTR[35] 31_201 -GTP_CHANNEL_3.GTPE2.PCS_RSVD_ATTR[36] 30_202 -GTP_CHANNEL_3.GTPE2.PCS_RSVD_ATTR[37] 31_202 -GTP_CHANNEL_3.GTPE2.PCS_RSVD_ATTR[38] 30_203 -GTP_CHANNEL_3.GTPE2.PCS_RSVD_ATTR[39] 31_203 -GTP_CHANNEL_3.GTPE2.PCS_RSVD_ATTR[40] 30_204 -GTP_CHANNEL_3.GTPE2.PCS_RSVD_ATTR[41] 31_204 -GTP_CHANNEL_3.GTPE2.PCS_RSVD_ATTR[42] 30_205 -GTP_CHANNEL_3.GTPE2.PCS_RSVD_ATTR[43] 31_205 -GTP_CHANNEL_3.GTPE2.PCS_RSVD_ATTR[44] 30_206 -GTP_CHANNEL_3.GTPE2.PCS_RSVD_ATTR[45] 31_206 -GTP_CHANNEL_3.GTPE2.PCS_RSVD_ATTR[46] 30_207 -GTP_CHANNEL_3.GTPE2.PCS_RSVD_ATTR[47] 31_207 -GTP_CHANNEL_3.GTPE2.PD_TRANS_TIME_FROM_P2[0] 29_216 -GTP_CHANNEL_3.GTPE2.PD_TRANS_TIME_FROM_P2[1] 28_217 -GTP_CHANNEL_3.GTPE2.PD_TRANS_TIME_FROM_P2[2] 29_217 -GTP_CHANNEL_3.GTPE2.PD_TRANS_TIME_FROM_P2[3] 28_218 -GTP_CHANNEL_3.GTPE2.PD_TRANS_TIME_FROM_P2[4] 29_218 -GTP_CHANNEL_3.GTPE2.PD_TRANS_TIME_FROM_P2[5] 28_219 -GTP_CHANNEL_3.GTPE2.PD_TRANS_TIME_FROM_P2[6] 29_219 -GTP_CHANNEL_3.GTPE2.PD_TRANS_TIME_FROM_P2[7] 28_220 -GTP_CHANNEL_3.GTPE2.PD_TRANS_TIME_FROM_P2[8] 29_220 -GTP_CHANNEL_3.GTPE2.PD_TRANS_TIME_FROM_P2[9] 28_221 -GTP_CHANNEL_3.GTPE2.PD_TRANS_TIME_FROM_P2[10] 29_221 -GTP_CHANNEL_3.GTPE2.PD_TRANS_TIME_FROM_P2[11] 28_222 -GTP_CHANNEL_3.GTPE2.PD_TRANS_TIME_NONE_P2[0] 28_208 -GTP_CHANNEL_3.GTPE2.PD_TRANS_TIME_NONE_P2[1] 29_208 -GTP_CHANNEL_3.GTPE2.PD_TRANS_TIME_NONE_P2[2] 28_209 -GTP_CHANNEL_3.GTPE2.PD_TRANS_TIME_NONE_P2[3] 29_209 -GTP_CHANNEL_3.GTPE2.PD_TRANS_TIME_NONE_P2[4] 28_210 -GTP_CHANNEL_3.GTPE2.PD_TRANS_TIME_NONE_P2[5] 29_210 -GTP_CHANNEL_3.GTPE2.PD_TRANS_TIME_NONE_P2[6] 28_211 -GTP_CHANNEL_3.GTPE2.PD_TRANS_TIME_NONE_P2[7] 29_211 -GTP_CHANNEL_3.GTPE2.PD_TRANS_TIME_TO_P2[0] 28_212 -GTP_CHANNEL_3.GTPE2.PD_TRANS_TIME_TO_P2[1] 29_212 -GTP_CHANNEL_3.GTPE2.PD_TRANS_TIME_TO_P2[2] 28_213 -GTP_CHANNEL_3.GTPE2.PD_TRANS_TIME_TO_P2[3] 29_213 -GTP_CHANNEL_3.GTPE2.PD_TRANS_TIME_TO_P2[4] 28_214 -GTP_CHANNEL_3.GTPE2.PD_TRANS_TIME_TO_P2[5] 29_214 -GTP_CHANNEL_3.GTPE2.PD_TRANS_TIME_TO_P2[6] 28_215 -GTP_CHANNEL_3.GTPE2.PD_TRANS_TIME_TO_P2[7] 29_215 -GTP_CHANNEL_3.GTPE2.PMA_LOOPBACK_CFG[0] 29_207 -GTP_CHANNEL_3.GTPE2.PMA_RSV[0] 30_520 -GTP_CHANNEL_3.GTPE2.PMA_RSV[1] 31_520 -GTP_CHANNEL_3.GTPE2.PMA_RSV[2] 30_521 -GTP_CHANNEL_3.GTPE2.PMA_RSV[3] 31_521 -GTP_CHANNEL_3.GTPE2.PMA_RSV[4] 30_522 -GTP_CHANNEL_3.GTPE2.PMA_RSV[5] 31_522 -GTP_CHANNEL_3.GTPE2.PMA_RSV[6] 30_523 -GTP_CHANNEL_3.GTPE2.PMA_RSV[7] 31_523 -GTP_CHANNEL_3.GTPE2.PMA_RSV[8] 30_524 -GTP_CHANNEL_3.GTPE2.PMA_RSV[9] 31_524 -GTP_CHANNEL_3.GTPE2.PMA_RSV[10] 30_525 -GTP_CHANNEL_3.GTPE2.PMA_RSV[11] 31_525 -GTP_CHANNEL_3.GTPE2.PMA_RSV[12] 30_526 -GTP_CHANNEL_3.GTPE2.PMA_RSV[13] 31_526 -GTP_CHANNEL_3.GTPE2.PMA_RSV[14] 30_527 -GTP_CHANNEL_3.GTPE2.PMA_RSV[15] 31_527 -GTP_CHANNEL_3.GTPE2.PMA_RSV[16] 30_528 -GTP_CHANNEL_3.GTPE2.PMA_RSV[17] 31_528 -GTP_CHANNEL_3.GTPE2.PMA_RSV[18] 30_529 -GTP_CHANNEL_3.GTPE2.PMA_RSV[19] 31_529 -GTP_CHANNEL_3.GTPE2.PMA_RSV[20] 30_530 -GTP_CHANNEL_3.GTPE2.PMA_RSV[21] 31_530 -GTP_CHANNEL_3.GTPE2.PMA_RSV[22] 30_531 -GTP_CHANNEL_3.GTPE2.PMA_RSV[23] 31_531 -GTP_CHANNEL_3.GTPE2.PMA_RSV[24] 30_532 -GTP_CHANNEL_3.GTPE2.PMA_RSV[25] 31_532 -GTP_CHANNEL_3.GTPE2.PMA_RSV[26] 30_533 -GTP_CHANNEL_3.GTPE2.PMA_RSV[27] 31_533 -GTP_CHANNEL_3.GTPE2.PMA_RSV[28] 30_534 -GTP_CHANNEL_3.GTPE2.PMA_RSV[29] 31_534 -GTP_CHANNEL_3.GTPE2.PMA_RSV[30] 30_535 -GTP_CHANNEL_3.GTPE2.PMA_RSV[31] 31_535 -GTP_CHANNEL_3.GTPE2.PMA_RSV2[0] 30_336 -GTP_CHANNEL_3.GTPE2.PMA_RSV2[1] 31_336 -GTP_CHANNEL_3.GTPE2.PMA_RSV2[2] 30_337 -GTP_CHANNEL_3.GTPE2.PMA_RSV2[3] 31_337 -GTP_CHANNEL_3.GTPE2.PMA_RSV2[4] 30_338 -GTP_CHANNEL_3.GTPE2.PMA_RSV2[5] 31_338 -GTP_CHANNEL_3.GTPE2.PMA_RSV2[6] 30_339 -GTP_CHANNEL_3.GTPE2.PMA_RSV2[7] 31_339 -GTP_CHANNEL_3.GTPE2.PMA_RSV2[8] 30_340 -GTP_CHANNEL_3.GTPE2.PMA_RSV2[9] 31_340 -GTP_CHANNEL_3.GTPE2.PMA_RSV2[10] 30_341 -GTP_CHANNEL_3.GTPE2.PMA_RSV2[11] 31_341 -GTP_CHANNEL_3.GTPE2.PMA_RSV2[12] 30_342 -GTP_CHANNEL_3.GTPE2.PMA_RSV2[13] 31_342 -GTP_CHANNEL_3.GTPE2.PMA_RSV2[14] 30_343 -GTP_CHANNEL_3.GTPE2.PMA_RSV2[15] 31_343 -GTP_CHANNEL_3.GTPE2.PMA_RSV2[16] 30_344 -GTP_CHANNEL_3.GTPE2.PMA_RSV2[17] 31_344 -GTP_CHANNEL_3.GTPE2.PMA_RSV2[18] 30_345 -GTP_CHANNEL_3.GTPE2.PMA_RSV2[19] 31_345 -GTP_CHANNEL_3.GTPE2.PMA_RSV2[20] 30_346 -GTP_CHANNEL_3.GTPE2.PMA_RSV2[21] 31_346 -GTP_CHANNEL_3.GTPE2.PMA_RSV2[22] 30_347 -GTP_CHANNEL_3.GTPE2.PMA_RSV2[23] 31_347 -GTP_CHANNEL_3.GTPE2.PMA_RSV2[24] 30_348 -GTP_CHANNEL_3.GTPE2.PMA_RSV2[25] 31_348 -GTP_CHANNEL_3.GTPE2.PMA_RSV2[26] 30_349 -GTP_CHANNEL_3.GTPE2.PMA_RSV2[27] 31_349 -GTP_CHANNEL_3.GTPE2.PMA_RSV2[28] 30_350 -GTP_CHANNEL_3.GTPE2.PMA_RSV2[29] 31_350 -GTP_CHANNEL_3.GTPE2.PMA_RSV2[30] 30_351 -GTP_CHANNEL_3.GTPE2.PMA_RSV2[31] 31_351 -GTP_CHANNEL_3.GTPE2.PMA_RSV3[0] 30_288 -GTP_CHANNEL_3.GTPE2.PMA_RSV3[1] 31_288 -GTP_CHANNEL_3.GTPE2.PMA_RSV4[0] 30_156 -GTP_CHANNEL_3.GTPE2.PMA_RSV4[1] 31_156 -GTP_CHANNEL_3.GTPE2.PMA_RSV4[2] 30_157 -GTP_CHANNEL_3.GTPE2.PMA_RSV4[3] 31_157 -GTP_CHANNEL_3.GTPE2.PMA_RSV5[0] 31_159 -GTP_CHANNEL_3.GTPE2.PMA_RSV6[0] 30_303 -GTP_CHANNEL_3.GTPE2.PMA_RSV7[0] 31_303 -GTP_CHANNEL_3.GTPE2.RX_BIAS_CFG[0] 30_112 -GTP_CHANNEL_3.GTPE2.RX_BIAS_CFG[1] 31_112 -GTP_CHANNEL_3.GTPE2.RX_BIAS_CFG[2] 30_113 -GTP_CHANNEL_3.GTPE2.RX_BIAS_CFG[3] 31_113 -GTP_CHANNEL_3.GTPE2.RX_BIAS_CFG[4] 30_114 -GTP_CHANNEL_3.GTPE2.RX_BIAS_CFG[5] 31_114 -GTP_CHANNEL_3.GTPE2.RX_BIAS_CFG[6] 30_115 -GTP_CHANNEL_3.GTPE2.RX_BIAS_CFG[7] 31_115 -GTP_CHANNEL_3.GTPE2.RX_BIAS_CFG[8] 30_116 -GTP_CHANNEL_3.GTPE2.RX_BIAS_CFG[9] 31_116 -GTP_CHANNEL_3.GTPE2.RX_BIAS_CFG[10] 30_117 -GTP_CHANNEL_3.GTPE2.RX_BIAS_CFG[11] 31_117 -GTP_CHANNEL_3.GTPE2.RX_BIAS_CFG[12] 30_118 -GTP_CHANNEL_3.GTPE2.RX_BIAS_CFG[13] 31_118 -GTP_CHANNEL_3.GTPE2.RX_BIAS_CFG[14] 30_119 -GTP_CHANNEL_3.GTPE2.RX_BIAS_CFG[15] 31_119 -GTP_CHANNEL_3.GTPE2.RX_BUFFER_CFG[0] 30_536 -GTP_CHANNEL_3.GTPE2.RX_BUFFER_CFG[1] 31_536 -GTP_CHANNEL_3.GTPE2.RX_BUFFER_CFG[2] 30_537 -GTP_CHANNEL_3.GTPE2.RX_BUFFER_CFG[3] 31_537 -GTP_CHANNEL_3.GTPE2.RX_BUFFER_CFG[4] 30_538 -GTP_CHANNEL_3.GTPE2.RX_BUFFER_CFG[5] 31_538 -GTP_CHANNEL_3.GTPE2.RX_CLKMUX_EN[0] 30_128 -GTP_CHANNEL_3.GTPE2.RX_CM_SEL[0] 28_138 -GTP_CHANNEL_3.GTPE2.RX_CM_SEL[1] 29_138 -GTP_CHANNEL_3.GTPE2.RX_CM_TRIM[0] 30_304 -GTP_CHANNEL_3.GTPE2.RX_CM_TRIM[1] 31_304 -GTP_CHANNEL_3.GTPE2.RX_CM_TRIM[2] 30_305 -GTP_CHANNEL_3.GTPE2.RX_CM_TRIM[3] 31_305 -GTP_CHANNEL_3.GTPE2.RX_DATA_WIDTH[0] 29_141 -GTP_CHANNEL_3.GTPE2.RX_DATA_WIDTH[1] 28_142 -GTP_CHANNEL_3.GTPE2.RX_DATA_WIDTH[2] 29_142 -GTP_CHANNEL_3.GTPE2.RX_DDI_SEL[0] 28_696 -GTP_CHANNEL_3.GTPE2.RX_DDI_SEL[1] 29_696 -GTP_CHANNEL_3.GTPE2.RX_DDI_SEL[2] 28_697 -GTP_CHANNEL_3.GTPE2.RX_DDI_SEL[3] 29_697 -GTP_CHANNEL_3.GTPE2.RX_DDI_SEL[4] 28_698 -GTP_CHANNEL_3.GTPE2.RX_DDI_SEL[5] 29_698 -GTP_CHANNEL_3.GTPE2.RX_DEBUG_CFG[0] 30_616 -GTP_CHANNEL_3.GTPE2.RX_DEBUG_CFG[1] 31_616 -GTP_CHANNEL_3.GTPE2.RX_DEBUG_CFG[2] 30_617 -GTP_CHANNEL_3.GTPE2.RX_DEBUG_CFG[3] 31_617 -GTP_CHANNEL_3.GTPE2.RX_DEBUG_CFG[4] 30_618 -GTP_CHANNEL_3.GTPE2.RX_DEBUG_CFG[5] 31_618 -GTP_CHANNEL_3.GTPE2.RX_DEBUG_CFG[6] 30_619 -GTP_CHANNEL_3.GTPE2.RX_DEBUG_CFG[7] 31_619 -GTP_CHANNEL_3.GTPE2.RX_DEBUG_CFG[8] 30_620 -GTP_CHANNEL_3.GTPE2.RX_DEBUG_CFG[9] 31_620 -GTP_CHANNEL_3.GTPE2.RX_DEBUG_CFG[10] 30_621 -GTP_CHANNEL_3.GTPE2.RX_DEBUG_CFG[11] 31_621 -GTP_CHANNEL_3.GTPE2.RX_DEBUG_CFG[12] 30_622 -GTP_CHANNEL_3.GTPE2.RX_DEBUG_CFG[13] 31_622 -GTP_CHANNEL_3.GTPE2.RX_DEFER_RESET_BUF_EN 30_552 -GTP_CHANNEL_3.GTPE2.RX_DISPERR_SEQ_MATCH 29_495 -GTP_CHANNEL_3.GTPE2.RX_OS_CFG[0] 28_288 -GTP_CHANNEL_3.GTPE2.RX_OS_CFG[1] 29_288 -GTP_CHANNEL_3.GTPE2.RX_OS_CFG[2] 28_289 -GTP_CHANNEL_3.GTPE2.RX_OS_CFG[3] 29_289 -GTP_CHANNEL_3.GTPE2.RX_OS_CFG[4] 28_290 -GTP_CHANNEL_3.GTPE2.RX_OS_CFG[5] 29_290 -GTP_CHANNEL_3.GTPE2.RX_OS_CFG[6] 28_291 -GTP_CHANNEL_3.GTPE2.RX_OS_CFG[7] 29_291 -GTP_CHANNEL_3.GTPE2.RX_OS_CFG[8] 28_292 -GTP_CHANNEL_3.GTPE2.RX_OS_CFG[9] 29_292 -GTP_CHANNEL_3.GTPE2.RX_OS_CFG[10] 28_293 -GTP_CHANNEL_3.GTPE2.RX_OS_CFG[11] 29_293 -GTP_CHANNEL_3.GTPE2.RX_OS_CFG[12] 28_294 -GTP_CHANNEL_3.GTPE2.RX_SIG_VALID_DLY[0] 28_524 -GTP_CHANNEL_3.GTPE2.RX_SIG_VALID_DLY[1] 29_524 -GTP_CHANNEL_3.GTPE2.RX_SIG_VALID_DLY[2] 28_525 -GTP_CHANNEL_3.GTPE2.RX_SIG_VALID_DLY[3] 29_525 -GTP_CHANNEL_3.GTPE2.RX_SIG_VALID_DLY[4] 28_526 -GTP_CHANNEL_3.GTPE2.RX_XCLK_SEL.RXUSR 28_143 -GTP_CHANNEL_3.GTPE2.RX_CLK25_DIV[0] 28_139 -GTP_CHANNEL_3.GTPE2.RX_CLK25_DIV[1] 29_139 -GTP_CHANNEL_3.GTPE2.RX_CLK25_DIV[2] 28_140 -GTP_CHANNEL_3.GTPE2.RX_CLK25_DIV[3] 29_140 -GTP_CHANNEL_3.GTPE2.RX_CLK25_DIV[4] 28_141 -GTP_CHANNEL_3.GTPE2.RXBUF_ADDR_MODE.FAST 31_555 -GTP_CHANNEL_3.GTPE2.RXBUF_EIDLE_HI_CNT[0] 30_558 -GTP_CHANNEL_3.GTPE2.RXBUF_EIDLE_HI_CNT[1] 31_558 -GTP_CHANNEL_3.GTPE2.RXBUF_EIDLE_HI_CNT[2] 30_559 -GTP_CHANNEL_3.GTPE2.RXBUF_EIDLE_HI_CNT[3] 31_559 -GTP_CHANNEL_3.GTPE2.RXBUF_EIDLE_LO_CNT[0] 30_556 -GTP_CHANNEL_3.GTPE2.RXBUF_EIDLE_LO_CNT[1] 31_556 -GTP_CHANNEL_3.GTPE2.RXBUF_EIDLE_LO_CNT[2] 30_557 -GTP_CHANNEL_3.GTPE2.RXBUF_EIDLE_LO_CNT[3] 31_557 -GTP_CHANNEL_3.GTPE2.RXBUF_EN 30_11 -GTP_CHANNEL_3.GTPE2.RXBUF_RESET_ON_CB_CHANGE 30_560 -GTP_CHANNEL_3.GTPE2.RXBUF_RESET_ON_COMMAALIGN 30_561 -GTP_CHANNEL_3.GTPE2.RXBUF_RESET_ON_EIDLE 30_547 -GTP_CHANNEL_3.GTPE2.RXBUF_RESET_ON_RATE_CHANGE 31_560 -GTP_CHANNEL_3.GTPE2.RXBUF_THRESH_OVFLW[0] 31_552 -GTP_CHANNEL_3.GTPE2.RXBUF_THRESH_OVFLW[1] 30_553 -GTP_CHANNEL_3.GTPE2.RXBUF_THRESH_OVFLW[2] 31_553 -GTP_CHANNEL_3.GTPE2.RXBUF_THRESH_OVFLW[3] 30_554 -GTP_CHANNEL_3.GTPE2.RXBUF_THRESH_OVFLW[4] 31_554 -GTP_CHANNEL_3.GTPE2.RXBUF_THRESH_OVFLW[5] 30_555 -GTP_CHANNEL_3.GTPE2.RXBUF_THRESH_OVRD 30_548 -GTP_CHANNEL_3.GTPE2.RXBUF_THRESH_UNDFLW[0] 30_544 -GTP_CHANNEL_3.GTPE2.RXBUF_THRESH_UNDFLW[1] 31_544 -GTP_CHANNEL_3.GTPE2.RXBUF_THRESH_UNDFLW[2] 30_545 -GTP_CHANNEL_3.GTPE2.RXBUF_THRESH_UNDFLW[3] 31_545 -GTP_CHANNEL_3.GTPE2.RXBUF_THRESH_UNDFLW[4] 30_546 -GTP_CHANNEL_3.GTPE2.RXBUF_THRESH_UNDFLW[5] 31_546 -GTP_CHANNEL_3.GTPE2.RXBUFRESET_TIME[0] 29_101 -GTP_CHANNEL_3.GTPE2.RXBUFRESET_TIME[1] 28_102 -GTP_CHANNEL_3.GTPE2.RXBUFRESET_TIME[2] 29_102 -GTP_CHANNEL_3.GTPE2.RXBUFRESET_TIME[3] 28_103 -GTP_CHANNEL_3.GTPE2.RXBUFRESET_TIME[4] 29_103 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[0] 30_640 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[1] 31_640 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[2] 30_641 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[3] 31_641 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[4] 30_642 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[5] 31_642 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[6] 30_643 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[7] 31_643 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[8] 30_644 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[9] 31_644 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[10] 30_645 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[11] 31_645 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[12] 30_646 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[13] 31_646 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[14] 30_647 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[15] 31_647 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[16] 30_648 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[17] 31_648 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[18] 30_649 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[19] 31_649 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[20] 30_650 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[21] 31_650 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[22] 30_651 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[23] 31_651 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[24] 30_652 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[25] 31_652 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[26] 30_653 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[27] 31_653 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[28] 30_654 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[29] 31_654 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[30] 30_655 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[31] 31_655 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[32] 30_656 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[33] 31_656 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[34] 30_657 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[35] 31_657 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[36] 30_658 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[37] 31_658 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[38] 30_659 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[39] 31_659 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[40] 30_660 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[41] 31_660 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[42] 30_661 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[43] 31_661 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[44] 30_662 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[45] 31_662 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[46] 30_663 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[47] 31_663 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[48] 30_664 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[49] 31_664 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[50] 30_665 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[51] 31_665 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[52] 30_666 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[53] 31_666 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[54] 30_667 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[55] 31_667 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[56] 30_668 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[57] 31_668 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[58] 30_669 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[59] 31_669 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[60] 30_670 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[61] 31_670 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[62] 30_671 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[63] 31_671 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[64] 30_672 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[65] 31_672 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[66] 30_673 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[67] 31_673 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[68] 30_674 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[69] 31_674 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[70] 30_675 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[71] 31_675 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[72] 30_676 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[73] 31_676 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[74] 30_677 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[75] 31_677 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[76] 30_678 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[77] 31_678 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[78] 30_679 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[79] 31_679 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[80] 30_680 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[81] 31_680 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[82] 30_681 -GTP_CHANNEL_3.GTPE2.RXCDR_FR_RESET_ON_EIDLE[0] 30_638 -GTP_CHANNEL_3.GTPE2.RXCDR_HOLD_DURING_EIDLE[0] 31_637 -GTP_CHANNEL_3.GTPE2.RXCDR_LOCK_CFG[0] 30_632 -GTP_CHANNEL_3.GTPE2.RXCDR_LOCK_CFG[1] 31_632 -GTP_CHANNEL_3.GTPE2.RXCDR_LOCK_CFG[2] 30_633 -GTP_CHANNEL_3.GTPE2.RXCDR_LOCK_CFG[3] 31_633 -GTP_CHANNEL_3.GTPE2.RXCDR_LOCK_CFG[4] 30_634 -GTP_CHANNEL_3.GTPE2.RXCDR_LOCK_CFG[5] 31_634 -GTP_CHANNEL_3.GTPE2.RXCDR_PH_RESET_ON_EIDLE[0] 31_638 -GTP_CHANNEL_3.GTPE2.RXCDRFREQRESET_TIME[0] 29_106 -GTP_CHANNEL_3.GTPE2.RXCDRFREQRESET_TIME[1] 28_107 -GTP_CHANNEL_3.GTPE2.RXCDRFREQRESET_TIME[2] 29_107 -GTP_CHANNEL_3.GTPE2.RXCDRFREQRESET_TIME[3] 28_108 -GTP_CHANNEL_3.GTPE2.RXCDRFREQRESET_TIME[4] 29_108 -GTP_CHANNEL_3.GTPE2.RXCDRPHRESET_TIME[0] 28_109 -GTP_CHANNEL_3.GTPE2.RXCDRPHRESET_TIME[1] 29_109 -GTP_CHANNEL_3.GTPE2.RXCDRPHRESET_TIME[2] 28_110 -GTP_CHANNEL_3.GTPE2.RXCDRPHRESET_TIME[3] 29_110 -GTP_CHANNEL_3.GTPE2.RXCDRPHRESET_TIME[4] 28_111 -GTP_CHANNEL_3.GTPE2.RXDLY_CFG[0] 28_680 -GTP_CHANNEL_3.GTPE2.RXDLY_CFG[1] 29_680 -GTP_CHANNEL_3.GTPE2.RXDLY_CFG[2] 28_681 -GTP_CHANNEL_3.GTPE2.RXDLY_CFG[3] 29_681 -GTP_CHANNEL_3.GTPE2.RXDLY_CFG[4] 28_682 -GTP_CHANNEL_3.GTPE2.RXDLY_CFG[5] 29_682 -GTP_CHANNEL_3.GTPE2.RXDLY_CFG[6] 28_683 -GTP_CHANNEL_3.GTPE2.RXDLY_CFG[7] 29_683 -GTP_CHANNEL_3.GTPE2.RXDLY_CFG[8] 28_684 -GTP_CHANNEL_3.GTPE2.RXDLY_CFG[9] 29_684 -GTP_CHANNEL_3.GTPE2.RXDLY_CFG[10] 28_685 -GTP_CHANNEL_3.GTPE2.RXDLY_CFG[11] 29_685 -GTP_CHANNEL_3.GTPE2.RXDLY_CFG[12] 28_686 -GTP_CHANNEL_3.GTPE2.RXDLY_CFG[13] 29_686 -GTP_CHANNEL_3.GTPE2.RXDLY_CFG[14] 28_687 -GTP_CHANNEL_3.GTPE2.RXDLY_CFG[15] 29_687 -GTP_CHANNEL_3.GTPE2.RXDLY_LCFG[0] 30_576 -GTP_CHANNEL_3.GTPE2.RXDLY_LCFG[1] 31_576 -GTP_CHANNEL_3.GTPE2.RXDLY_LCFG[2] 30_577 -GTP_CHANNEL_3.GTPE2.RXDLY_LCFG[3] 31_577 -GTP_CHANNEL_3.GTPE2.RXDLY_LCFG[4] 30_578 -GTP_CHANNEL_3.GTPE2.RXDLY_LCFG[5] 31_578 -GTP_CHANNEL_3.GTPE2.RXDLY_LCFG[6] 30_579 -GTP_CHANNEL_3.GTPE2.RXDLY_LCFG[7] 31_579 -GTP_CHANNEL_3.GTPE2.RXDLY_LCFG[8] 30_580 -GTP_CHANNEL_3.GTPE2.RXDLY_TAP_CFG[0] 28_672 -GTP_CHANNEL_3.GTPE2.RXDLY_TAP_CFG[1] 29_672 -GTP_CHANNEL_3.GTPE2.RXDLY_TAP_CFG[2] 28_673 -GTP_CHANNEL_3.GTPE2.RXDLY_TAP_CFG[3] 29_673 -GTP_CHANNEL_3.GTPE2.RXDLY_TAP_CFG[4] 28_674 -GTP_CHANNEL_3.GTPE2.RXDLY_TAP_CFG[5] 29_674 -GTP_CHANNEL_3.GTPE2.RXDLY_TAP_CFG[6] 28_675 -GTP_CHANNEL_3.GTPE2.RXDLY_TAP_CFG[7] 29_675 -GTP_CHANNEL_3.GTPE2.RXDLY_TAP_CFG[8] 28_676 -GTP_CHANNEL_3.GTPE2.RXDLY_TAP_CFG[9] 29_676 -GTP_CHANNEL_3.GTPE2.RXDLY_TAP_CFG[10] 28_677 -GTP_CHANNEL_3.GTPE2.RXDLY_TAP_CFG[11] 29_677 -GTP_CHANNEL_3.GTPE2.RXDLY_TAP_CFG[12] 28_678 -GTP_CHANNEL_3.GTPE2.RXDLY_TAP_CFG[13] 29_678 -GTP_CHANNEL_3.GTPE2.RXDLY_TAP_CFG[14] 28_679 -GTP_CHANNEL_3.GTPE2.RXDLY_TAP_CFG[15] 29_679 -GTP_CHANNEL_3.GTPE2.RXGEARBOX_EN 29_607 -GTP_CHANNEL_3.GTPE2.RXISCANRESET_TIME[0] 29_123 -GTP_CHANNEL_3.GTPE2.RXISCANRESET_TIME[1] 28_124 -GTP_CHANNEL_3.GTPE2.RXISCANRESET_TIME[2] 29_124 -GTP_CHANNEL_3.GTPE2.RXISCANRESET_TIME[3] 28_125 -GTP_CHANNEL_3.GTPE2.RXISCANRESET_TIME[4] 29_125 -GTP_CHANNEL_3.GTPE2.RXLPM_BIAS_STARTUP_DISABLE[0] 31_391 -GTP_CHANNEL_3.GTPE2.RXLPM_CFG[0] 30_328 -GTP_CHANNEL_3.GTPE2.RXLPM_CFG[1] 31_328 -GTP_CHANNEL_3.GTPE2.RXLPM_CFG[2] 30_329 -GTP_CHANNEL_3.GTPE2.RXLPM_CFG[3] 31_329 -GTP_CHANNEL_3.GTPE2.RXLPM_CM_CFG[0] 30_430 -GTP_CHANNEL_3.GTPE2.RXLPM_GC_CFG[0] 30_432 -GTP_CHANNEL_3.GTPE2.RXLPM_GC_CFG[1] 31_432 -GTP_CHANNEL_3.GTPE2.RXLPM_GC_CFG[2] 30_433 -GTP_CHANNEL_3.GTPE2.RXLPM_GC_CFG[3] 31_433 -GTP_CHANNEL_3.GTPE2.RXLPM_GC_CFG[4] 30_434 -GTP_CHANNEL_3.GTPE2.RXLPM_GC_CFG[5] 31_434 -GTP_CHANNEL_3.GTPE2.RXLPM_GC_CFG[6] 30_435 -GTP_CHANNEL_3.GTPE2.RXLPM_GC_CFG[7] 31_435 -GTP_CHANNEL_3.GTPE2.RXLPM_GC_CFG[8] 30_436 -GTP_CHANNEL_3.GTPE2.RXLPM_GC_CFG2[0] 31_442 -GTP_CHANNEL_3.GTPE2.RXLPM_GC_CFG2[1] 30_443 -GTP_CHANNEL_3.GTPE2.RXLPM_GC_CFG2[2] 31_443 -GTP_CHANNEL_3.GTPE2.RXLPM_HF_CFG[0] 28_336 -GTP_CHANNEL_3.GTPE2.RXLPM_HF_CFG[1] 29_336 -GTP_CHANNEL_3.GTPE2.RXLPM_HF_CFG[2] 28_337 -GTP_CHANNEL_3.GTPE2.RXLPM_HF_CFG[3] 29_337 -GTP_CHANNEL_3.GTPE2.RXLPM_HF_CFG[4] 28_338 -GTP_CHANNEL_3.GTPE2.RXLPM_HF_CFG[5] 29_338 -GTP_CHANNEL_3.GTPE2.RXLPM_HF_CFG[6] 28_339 -GTP_CHANNEL_3.GTPE2.RXLPM_HF_CFG[7] 29_339 -GTP_CHANNEL_3.GTPE2.RXLPM_HF_CFG[8] 28_340 -GTP_CHANNEL_3.GTPE2.RXLPM_HF_CFG[9] 29_340 -GTP_CHANNEL_3.GTPE2.RXLPM_HF_CFG[10] 28_341 -GTP_CHANNEL_3.GTPE2.RXLPM_HF_CFG[11] 29_341 -GTP_CHANNEL_3.GTPE2.RXLPM_HF_CFG[12] 28_342 -GTP_CHANNEL_3.GTPE2.RXLPM_HF_CFG[13] 29_342 -GTP_CHANNEL_3.GTPE2.RXLPM_HF_CFG2[0] 30_424 -GTP_CHANNEL_3.GTPE2.RXLPM_HF_CFG2[1] 31_424 -GTP_CHANNEL_3.GTPE2.RXLPM_HF_CFG2[2] 30_425 -GTP_CHANNEL_3.GTPE2.RXLPM_HF_CFG2[3] 31_425 -GTP_CHANNEL_3.GTPE2.RXLPM_HF_CFG2[4] 30_426 -GTP_CHANNEL_3.GTPE2.RXLPM_HF_CFG3[0] 31_389 -GTP_CHANNEL_3.GTPE2.RXLPM_HF_CFG3[1] 30_390 -GTP_CHANNEL_3.GTPE2.RXLPM_HF_CFG3[2] 31_390 -GTP_CHANNEL_3.GTPE2.RXLPM_HF_CFG3[3] 30_391 -GTP_CHANNEL_3.GTPE2.RXLPM_HOLD_DURING_EIDLE[0] 28_247 -GTP_CHANNEL_3.GTPE2.RXLPM_INCM_CFG[0] 30_439 -GTP_CHANNEL_3.GTPE2.RXLPM_IPCM_CFG[0] 31_439 -GTP_CHANNEL_3.GTPE2.RXLPM_LF_CFG[0] 28_344 -GTP_CHANNEL_3.GTPE2.RXLPM_LF_CFG[1] 29_344 -GTP_CHANNEL_3.GTPE2.RXLPM_LF_CFG[2] 28_345 -GTP_CHANNEL_3.GTPE2.RXLPM_LF_CFG[3] 29_345 -GTP_CHANNEL_3.GTPE2.RXLPM_LF_CFG[4] 28_346 -GTP_CHANNEL_3.GTPE2.RXLPM_LF_CFG[5] 29_346 -GTP_CHANNEL_3.GTPE2.RXLPM_LF_CFG[6] 28_347 -GTP_CHANNEL_3.GTPE2.RXLPM_LF_CFG[7] 29_347 -GTP_CHANNEL_3.GTPE2.RXLPM_LF_CFG[8] 28_348 -GTP_CHANNEL_3.GTPE2.RXLPM_LF_CFG[9] 29_348 -GTP_CHANNEL_3.GTPE2.RXLPM_LF_CFG[10] 28_349 -GTP_CHANNEL_3.GTPE2.RXLPM_LF_CFG[11] 29_349 -GTP_CHANNEL_3.GTPE2.RXLPM_LF_CFG[12] 28_350 -GTP_CHANNEL_3.GTPE2.RXLPM_LF_CFG[13] 29_350 -GTP_CHANNEL_3.GTPE2.RXLPM_LF_CFG[14] 28_351 -GTP_CHANNEL_3.GTPE2.RXLPM_LF_CFG[15] 29_351 -GTP_CHANNEL_3.GTPE2.RXLPM_LF_CFG[16] 28_343 -GTP_CHANNEL_3.GTPE2.RXLPM_LF_CFG[17] 29_343 -GTP_CHANNEL_3.GTPE2.RXLPM_LF_CFG2[0] 31_426 -GTP_CHANNEL_3.GTPE2.RXLPM_LF_CFG2[1] 30_427 -GTP_CHANNEL_3.GTPE2.RXLPM_LF_CFG2[2] 31_427 -GTP_CHANNEL_3.GTPE2.RXLPM_LF_CFG2[3] 30_428 -GTP_CHANNEL_3.GTPE2.RXLPM_LF_CFG2[4] 31_428 -GTP_CHANNEL_3.GTPE2.RXLPM_OSINT_CFG[0] 30_440 -GTP_CHANNEL_3.GTPE2.RXLPM_OSINT_CFG[1] 31_440 -GTP_CHANNEL_3.GTPE2.RXLPM_OSINT_CFG[2] 30_441 -GTP_CHANNEL_3.GTPE2.RXLPM_CFG1[0] 30_330 -GTP_CHANNEL_3.GTPE2.RXLPMRESET_TIME[0] 28_112 -GTP_CHANNEL_3.GTPE2.RXLPMRESET_TIME[1] 29_112 -GTP_CHANNEL_3.GTPE2.RXLPMRESET_TIME[2] 28_113 -GTP_CHANNEL_3.GTPE2.RXLPMRESET_TIME[3] 29_113 -GTP_CHANNEL_3.GTPE2.RXLPMRESET_TIME[4] 28_114 -GTP_CHANNEL_3.GTPE2.RXLPMRESET_TIME[5] 29_114 -GTP_CHANNEL_3.GTPE2.RXLPMRESET_TIME[6] 28_115 -GTP_CHANNEL_3.GTPE2.RXOOB_CFG[0] 28_144 -GTP_CHANNEL_3.GTPE2.RXOOB_CFG[1] 29_144 -GTP_CHANNEL_3.GTPE2.RXOOB_CFG[2] 28_145 -GTP_CHANNEL_3.GTPE2.RXOOB_CFG[3] 29_145 -GTP_CHANNEL_3.GTPE2.RXOOB_CFG[4] 28_146 -GTP_CHANNEL_3.GTPE2.RXOOB_CFG[5] 29_146 -GTP_CHANNEL_3.GTPE2.RXOOB_CFG[6] 28_147 -GTP_CHANNEL_3.GTPE2.RXOOB_CLK_CFG.FABRIC 31_129 -GTP_CHANNEL_3.GTPE2.RXOSCALRESET_TIME[0] 28_187 -GTP_CHANNEL_3.GTPE2.RXOSCALRESET_TIME[1] 29_187 -GTP_CHANNEL_3.GTPE2.RXOSCALRESET_TIME[2] 28_188 -GTP_CHANNEL_3.GTPE2.RXOSCALRESET_TIME[3] 29_188 -GTP_CHANNEL_3.GTPE2.RXOSCALRESET_TIME[4] 28_189 -GTP_CHANNEL_3.GTPE2.RXOSCALRESET_TIMEOUT[0] 29_189 -GTP_CHANNEL_3.GTPE2.RXOSCALRESET_TIMEOUT[1] 28_190 -GTP_CHANNEL_3.GTPE2.RXOSCALRESET_TIMEOUT[2] 29_190 -GTP_CHANNEL_3.GTPE2.RXOSCALRESET_TIMEOUT[3] 28_191 -GTP_CHANNEL_3.GTPE2.RXOSCALRESET_TIMEOUT[4] 29_191 -GTP_CHANNEL_3.GTPE2.RXOUT_DIV[0] 30_384 -GTP_CHANNEL_3.GTPE2.RXOUT_DIV[1] 31_384 -GTP_CHANNEL_3.GTPE2.RXPCSRESET_TIME[0] 29_115 -GTP_CHANNEL_3.GTPE2.RXPCSRESET_TIME[1] 28_116 -GTP_CHANNEL_3.GTPE2.RXPCSRESET_TIME[2] 29_116 -GTP_CHANNEL_3.GTPE2.RXPCSRESET_TIME[3] 28_117 -GTP_CHANNEL_3.GTPE2.RXPCSRESET_TIME[4] 29_117 -GTP_CHANNEL_3.GTPE2.RXPH_CFG[0] 30_584 -GTP_CHANNEL_3.GTPE2.RXPH_CFG[1] 31_584 -GTP_CHANNEL_3.GTPE2.RXPH_CFG[2] 30_585 -GTP_CHANNEL_3.GTPE2.RXPH_CFG[3] 31_585 -GTP_CHANNEL_3.GTPE2.RXPH_CFG[4] 30_586 -GTP_CHANNEL_3.GTPE2.RXPH_CFG[5] 31_586 -GTP_CHANNEL_3.GTPE2.RXPH_CFG[6] 30_587 -GTP_CHANNEL_3.GTPE2.RXPH_CFG[7] 31_587 -GTP_CHANNEL_3.GTPE2.RXPH_CFG[8] 30_588 -GTP_CHANNEL_3.GTPE2.RXPH_CFG[9] 31_588 -GTP_CHANNEL_3.GTPE2.RXPH_CFG[10] 30_589 -GTP_CHANNEL_3.GTPE2.RXPH_CFG[11] 31_589 -GTP_CHANNEL_3.GTPE2.RXPH_CFG[12] 30_590 -GTP_CHANNEL_3.GTPE2.RXPH_CFG[13] 31_590 -GTP_CHANNEL_3.GTPE2.RXPH_CFG[14] 30_591 -GTP_CHANNEL_3.GTPE2.RXPH_CFG[15] 31_591 -GTP_CHANNEL_3.GTPE2.RXPH_CFG[16] 30_592 -GTP_CHANNEL_3.GTPE2.RXPH_CFG[17] 31_592 -GTP_CHANNEL_3.GTPE2.RXPH_CFG[18] 30_593 -GTP_CHANNEL_3.GTPE2.RXPH_CFG[19] 31_593 -GTP_CHANNEL_3.GTPE2.RXPH_CFG[20] 30_594 -GTP_CHANNEL_3.GTPE2.RXPH_CFG[21] 31_594 -GTP_CHANNEL_3.GTPE2.RXPH_CFG[22] 30_595 -GTP_CHANNEL_3.GTPE2.RXPH_CFG[23] 31_595 -GTP_CHANNEL_3.GTPE2.RXPH_MONITOR_SEL[0] 28_700 -GTP_CHANNEL_3.GTPE2.RXPH_MONITOR_SEL[1] 29_700 -GTP_CHANNEL_3.GTPE2.RXPH_MONITOR_SEL[2] 28_701 -GTP_CHANNEL_3.GTPE2.RXPH_MONITOR_SEL[3] 29_701 -GTP_CHANNEL_3.GTPE2.RXPH_MONITOR_SEL[4] 28_702 -GTP_CHANNEL_3.GTPE2.RXPHDLY_CFG[0] 30_600 -GTP_CHANNEL_3.GTPE2.RXPHDLY_CFG[1] 31_600 -GTP_CHANNEL_3.GTPE2.RXPHDLY_CFG[2] 30_601 -GTP_CHANNEL_3.GTPE2.RXPHDLY_CFG[3] 31_601 -GTP_CHANNEL_3.GTPE2.RXPHDLY_CFG[4] 30_602 -GTP_CHANNEL_3.GTPE2.RXPHDLY_CFG[5] 31_602 -GTP_CHANNEL_3.GTPE2.RXPHDLY_CFG[6] 30_603 -GTP_CHANNEL_3.GTPE2.RXPHDLY_CFG[7] 31_603 -GTP_CHANNEL_3.GTPE2.RXPHDLY_CFG[8] 30_604 -GTP_CHANNEL_3.GTPE2.RXPHDLY_CFG[9] 31_604 -GTP_CHANNEL_3.GTPE2.RXPHDLY_CFG[10] 30_605 -GTP_CHANNEL_3.GTPE2.RXPHDLY_CFG[11] 31_605 -GTP_CHANNEL_3.GTPE2.RXPHDLY_CFG[12] 30_606 -GTP_CHANNEL_3.GTPE2.RXPHDLY_CFG[13] 31_606 -GTP_CHANNEL_3.GTPE2.RXPHDLY_CFG[14] 30_607 -GTP_CHANNEL_3.GTPE2.RXPHDLY_CFG[15] 31_607 -GTP_CHANNEL_3.GTPE2.RXPHDLY_CFG[16] 30_608 -GTP_CHANNEL_3.GTPE2.RXPHDLY_CFG[17] 31_608 -GTP_CHANNEL_3.GTPE2.RXPHDLY_CFG[18] 30_609 -GTP_CHANNEL_3.GTPE2.RXPHDLY_CFG[19] 31_609 -GTP_CHANNEL_3.GTPE2.RXPHDLY_CFG[20] 30_610 -GTP_CHANNEL_3.GTPE2.RXPHDLY_CFG[21] 31_610 -GTP_CHANNEL_3.GTPE2.RXPHDLY_CFG[22] 30_611 -GTP_CHANNEL_3.GTPE2.RXPHDLY_CFG[23] 31_611 -GTP_CHANNEL_3.GTPE2.RXPI_CFG0[0] 31_430 -GTP_CHANNEL_3.GTPE2.RXPI_CFG0[1] 30_431 -GTP_CHANNEL_3.GTPE2.RXPI_CFG0[2] 31_431 -GTP_CHANNEL_3.GTPE2.RXPI_CFG1[0] 30_442 -GTP_CHANNEL_3.GTPE2.RXPI_CFG2[0] 31_441 -GTP_CHANNEL_3.GTPE2.RXPMARESET_TIME[0] 28_104 -GTP_CHANNEL_3.GTPE2.RXPMARESET_TIME[1] 29_104 -GTP_CHANNEL_3.GTPE2.RXPMARESET_TIME[2] 28_105 -GTP_CHANNEL_3.GTPE2.RXPMARESET_TIME[3] 29_105 -GTP_CHANNEL_3.GTPE2.RXPMARESET_TIME[4] 28_106 -GTP_CHANNEL_3.GTPE2.RXPRBS_ERR_LOOPBACK[0] 28_136 -GTP_CHANNEL_3.GTPE2.RXSLIDE_AUTO_WAIT[0] 28_520 -GTP_CHANNEL_3.GTPE2.RXSLIDE_AUTO_WAIT[1] 29_520 -GTP_CHANNEL_3.GTPE2.RXSLIDE_AUTO_WAIT[2] 28_521 -GTP_CHANNEL_3.GTPE2.RXSLIDE_AUTO_WAIT[3] 29_521 -GTP_CHANNEL_3.GTPE2.RXSLIDE_MODE.AUTO 28_519 !29_519 -GTP_CHANNEL_3.GTPE2.RXSLIDE_MODE.PCS !28_519 29_519 -GTP_CHANNEL_3.GTPE2.RXSLIDE_MODE.PMA 28_519 29_519 -GTP_CHANNEL_3.GTPE2.RXSYNC_MULTILANE[0] 28_133 -GTP_CHANNEL_3.GTPE2.RXSYNC_OVRD[0] 29_135 -GTP_CHANNEL_3.GTPE2.RXSYNC_SKIP_DA[0] 29_134 -GTP_CHANNEL_3.GTPE2.SAS_MAX_COM[0] 28_171 -GTP_CHANNEL_3.GTPE2.SAS_MAX_COM[1] 29_171 -GTP_CHANNEL_3.GTPE2.SAS_MAX_COM[2] 28_172 -GTP_CHANNEL_3.GTPE2.SAS_MAX_COM[3] 29_172 -GTP_CHANNEL_3.GTPE2.SAS_MAX_COM[4] 28_173 -GTP_CHANNEL_3.GTPE2.SAS_MAX_COM[5] 29_173 -GTP_CHANNEL_3.GTPE2.SAS_MAX_COM[6] 28_174 -GTP_CHANNEL_3.GTPE2.SAS_MIN_COM[0] 29_156 -GTP_CHANNEL_3.GTPE2.SAS_MIN_COM[1] 28_157 -GTP_CHANNEL_3.GTPE2.SAS_MIN_COM[2] 29_157 -GTP_CHANNEL_3.GTPE2.SAS_MIN_COM[3] 28_158 -GTP_CHANNEL_3.GTPE2.SAS_MIN_COM[4] 29_158 -GTP_CHANNEL_3.GTPE2.SAS_MIN_COM[5] 28_159 -GTP_CHANNEL_3.GTPE2.SATA_BURST_SEQ_LEN[0] 28_150 -GTP_CHANNEL_3.GTPE2.SATA_BURST_SEQ_LEN[1] 29_150 -GTP_CHANNEL_3.GTPE2.SATA_BURST_SEQ_LEN[2] 28_151 -GTP_CHANNEL_3.GTPE2.SATA_BURST_SEQ_LEN[3] 29_151 -GTP_CHANNEL_3.GTPE2.SATA_BURST_VAL[0] 29_147 -GTP_CHANNEL_3.GTPE2.SATA_BURST_VAL[1] 28_148 -GTP_CHANNEL_3.GTPE2.SATA_BURST_VAL[2] 29_148 -GTP_CHANNEL_3.GTPE2.SATA_EIDLE_VAL[0] 28_152 -GTP_CHANNEL_3.GTPE2.SATA_EIDLE_VAL[1] 29_152 -GTP_CHANNEL_3.GTPE2.SATA_EIDLE_VAL[2] 28_153 -GTP_CHANNEL_3.GTPE2.SATA_MAX_BURST[0] 28_168 -GTP_CHANNEL_3.GTPE2.SATA_MAX_BURST[1] 29_168 -GTP_CHANNEL_3.GTPE2.SATA_MAX_BURST[2] 28_169 -GTP_CHANNEL_3.GTPE2.SATA_MAX_BURST[3] 29_169 -GTP_CHANNEL_3.GTPE2.SATA_MAX_BURST[4] 28_170 -GTP_CHANNEL_3.GTPE2.SATA_MAX_BURST[5] 29_170 -GTP_CHANNEL_3.GTPE2.SATA_MAX_INIT[0] 28_176 -GTP_CHANNEL_3.GTPE2.SATA_MAX_INIT[1] 29_176 -GTP_CHANNEL_3.GTPE2.SATA_MAX_INIT[2] 28_177 -GTP_CHANNEL_3.GTPE2.SATA_MAX_INIT[3] 29_177 -GTP_CHANNEL_3.GTPE2.SATA_MAX_INIT[4] 28_178 -GTP_CHANNEL_3.GTPE2.SATA_MAX_INIT[5] 29_178 -GTP_CHANNEL_3.GTPE2.SATA_MAX_WAKE[0] 28_179 -GTP_CHANNEL_3.GTPE2.SATA_MAX_WAKE[1] 29_179 -GTP_CHANNEL_3.GTPE2.SATA_MAX_WAKE[2] 28_180 -GTP_CHANNEL_3.GTPE2.SATA_MAX_WAKE[3] 29_180 -GTP_CHANNEL_3.GTPE2.SATA_MAX_WAKE[4] 28_181 -GTP_CHANNEL_3.GTPE2.SATA_MAX_WAKE[5] 29_181 -GTP_CHANNEL_3.GTPE2.SATA_MIN_BURST[0] 29_153 -GTP_CHANNEL_3.GTPE2.SATA_MIN_BURST[1] 28_154 -GTP_CHANNEL_3.GTPE2.SATA_MIN_BURST[2] 29_154 -GTP_CHANNEL_3.GTPE2.SATA_MIN_BURST[3] 28_155 -GTP_CHANNEL_3.GTPE2.SATA_MIN_BURST[4] 29_155 -GTP_CHANNEL_3.GTPE2.SATA_MIN_BURST[5] 28_156 -GTP_CHANNEL_3.GTPE2.SATA_MIN_INIT[0] 28_160 -GTP_CHANNEL_3.GTPE2.SATA_MIN_INIT[1] 29_160 -GTP_CHANNEL_3.GTPE2.SATA_MIN_INIT[2] 28_161 -GTP_CHANNEL_3.GTPE2.SATA_MIN_INIT[3] 29_161 -GTP_CHANNEL_3.GTPE2.SATA_MIN_INIT[4] 28_162 -GTP_CHANNEL_3.GTPE2.SATA_MIN_INIT[5] 29_162 -GTP_CHANNEL_3.GTPE2.SATA_MIN_WAKE[0] 28_163 -GTP_CHANNEL_3.GTPE2.SATA_MIN_WAKE[1] 29_163 -GTP_CHANNEL_3.GTPE2.SATA_MIN_WAKE[2] 28_164 -GTP_CHANNEL_3.GTPE2.SATA_MIN_WAKE[3] 29_164 -GTP_CHANNEL_3.GTPE2.SATA_MIN_WAKE[4] 28_165 -GTP_CHANNEL_3.GTPE2.SATA_MIN_WAKE[5] 29_165 -GTP_CHANNEL_3.GTPE2.SATA_PLL_CFG.VCO_1500MHZ 30_55 -GTP_CHANNEL_3.GTPE2.SATA_PLL_CFG.VCO_750MHZ 31_55 -GTP_CHANNEL_3.GTPE2.SHOW_REALIGN_COMMA 29_522 -GTP_CHANNEL_3.GTPE2.TERM_RCAL_CFG[0] 30_136 -GTP_CHANNEL_3.GTPE2.TERM_RCAL_CFG[1] 31_136 -GTP_CHANNEL_3.GTPE2.TERM_RCAL_CFG[2] 30_137 -GTP_CHANNEL_3.GTPE2.TERM_RCAL_CFG[3] 31_137 -GTP_CHANNEL_3.GTPE2.TERM_RCAL_CFG[4] 30_138 -GTP_CHANNEL_3.GTPE2.TERM_RCAL_CFG[5] 31_138 -GTP_CHANNEL_3.GTPE2.TERM_RCAL_CFG[6] 30_139 -GTP_CHANNEL_3.GTPE2.TERM_RCAL_CFG[7] 31_139 -GTP_CHANNEL_3.GTPE2.TERM_RCAL_CFG[8] 30_140 -GTP_CHANNEL_3.GTPE2.TERM_RCAL_CFG[9] 31_140 -GTP_CHANNEL_3.GTPE2.TERM_RCAL_CFG[10] 30_141 -GTP_CHANNEL_3.GTPE2.TERM_RCAL_CFG[11] 31_141 -GTP_CHANNEL_3.GTPE2.TERM_RCAL_CFG[12] 30_142 -GTP_CHANNEL_3.GTPE2.TERM_RCAL_CFG[13] 31_142 -GTP_CHANNEL_3.GTPE2.TERM_RCAL_CFG[14] 30_143 -GTP_CHANNEL_3.GTPE2.TERM_RCAL_OVRD[0] 31_150 -GTP_CHANNEL_3.GTPE2.TERM_RCAL_OVRD[1] 30_151 -GTP_CHANNEL_3.GTPE2.TERM_RCAL_OVRD[2] 31_151 -GTP_CHANNEL_3.GTPE2.TRANS_TIME_RATE[0] 28_192 -GTP_CHANNEL_3.GTPE2.TRANS_TIME_RATE[1] 29_192 -GTP_CHANNEL_3.GTPE2.TRANS_TIME_RATE[2] 28_193 -GTP_CHANNEL_3.GTPE2.TRANS_TIME_RATE[3] 29_193 -GTP_CHANNEL_3.GTPE2.TRANS_TIME_RATE[4] 28_194 -GTP_CHANNEL_3.GTPE2.TRANS_TIME_RATE[5] 29_194 -GTP_CHANNEL_3.GTPE2.TRANS_TIME_RATE[6] 28_195 -GTP_CHANNEL_3.GTPE2.TRANS_TIME_RATE[7] 29_195 -GTP_CHANNEL_3.GTPE2.TST_RSV[0] 30_504 -GTP_CHANNEL_3.GTPE2.TST_RSV[1] 31_504 -GTP_CHANNEL_3.GTPE2.TST_RSV[2] 30_505 -GTP_CHANNEL_3.GTPE2.TST_RSV[3] 31_505 -GTP_CHANNEL_3.GTPE2.TST_RSV[4] 30_506 -GTP_CHANNEL_3.GTPE2.TST_RSV[5] 31_506 -GTP_CHANNEL_3.GTPE2.TST_RSV[6] 30_507 -GTP_CHANNEL_3.GTPE2.TST_RSV[7] 31_507 -GTP_CHANNEL_3.GTPE2.TST_RSV[8] 30_508 -GTP_CHANNEL_3.GTPE2.TST_RSV[9] 31_508 -GTP_CHANNEL_3.GTPE2.TST_RSV[10] 30_509 -GTP_CHANNEL_3.GTPE2.TST_RSV[11] 31_509 -GTP_CHANNEL_3.GTPE2.TST_RSV[12] 30_510 -GTP_CHANNEL_3.GTPE2.TST_RSV[13] 31_510 -GTP_CHANNEL_3.GTPE2.TST_RSV[14] 30_511 -GTP_CHANNEL_3.GTPE2.TST_RSV[15] 31_511 -GTP_CHANNEL_3.GTPE2.TST_RSV[16] 30_512 -GTP_CHANNEL_3.GTPE2.TST_RSV[17] 31_512 -GTP_CHANNEL_3.GTPE2.TST_RSV[18] 30_513 -GTP_CHANNEL_3.GTPE2.TST_RSV[19] 31_513 -GTP_CHANNEL_3.GTPE2.TST_RSV[20] 30_514 -GTP_CHANNEL_3.GTPE2.TST_RSV[21] 31_514 -GTP_CHANNEL_3.GTPE2.TST_RSV[22] 30_515 -GTP_CHANNEL_3.GTPE2.TST_RSV[23] 31_515 -GTP_CHANNEL_3.GTPE2.TST_RSV[24] 30_516 -GTP_CHANNEL_3.GTPE2.TST_RSV[25] 31_516 -GTP_CHANNEL_3.GTPE2.TST_RSV[26] 30_517 -GTP_CHANNEL_3.GTPE2.TST_RSV[27] 31_517 -GTP_CHANNEL_3.GTPE2.TST_RSV[28] 30_518 -GTP_CHANNEL_3.GTPE2.TST_RSV[29] 31_518 -GTP_CHANNEL_3.GTPE2.TST_RSV[30] 30_519 -GTP_CHANNEL_3.GTPE2.TST_RSV[31] 31_519 -GTP_CHANNEL_3.GTPE2.TX_CLKMUX_EN[0] 31_128 -GTP_CHANNEL_3.GTPE2.TX_DATA_WIDTH[0] 30_152 -GTP_CHANNEL_3.GTPE2.TX_DATA_WIDTH[1] 31_152 -GTP_CHANNEL_3.GTPE2.TX_DATA_WIDTH[2] 30_153 -GTP_CHANNEL_3.GTPE2.TX_DRIVE_MODE.PIPE 28_200 -GTP_CHANNEL_3.GTPE2.TX_EIDLE_ASSERT_DELAY[0] 28_203 -GTP_CHANNEL_3.GTPE2.TX_EIDLE_ASSERT_DELAY[1] 29_203 -GTP_CHANNEL_3.GTPE2.TX_EIDLE_ASSERT_DELAY[2] 28_204 -GTP_CHANNEL_3.GTPE2.TX_EIDLE_DEASSERT_DELAY[0] 29_204 -GTP_CHANNEL_3.GTPE2.TX_EIDLE_DEASSERT_DELAY[1] 28_205 -GTP_CHANNEL_3.GTPE2.TX_EIDLE_DEASSERT_DELAY[2] 29_205 -GTP_CHANNEL_3.GTPE2.TX_LOOPBACK_DRIVE_HIZ 29_202 -GTP_CHANNEL_3.GTPE2.TX_MAINCURSOR_SEL[0] 31_289 -GTP_CHANNEL_3.GTPE2.TX_MARGIN_FULL_0[0] 30_232 -GTP_CHANNEL_3.GTPE2.TX_MARGIN_FULL_0[1] 31_232 -GTP_CHANNEL_3.GTPE2.TX_MARGIN_FULL_0[2] 30_233 -GTP_CHANNEL_3.GTPE2.TX_MARGIN_FULL_0[3] 31_233 -GTP_CHANNEL_3.GTPE2.TX_MARGIN_FULL_0[4] 30_234 -GTP_CHANNEL_3.GTPE2.TX_MARGIN_FULL_0[5] 31_234 -GTP_CHANNEL_3.GTPE2.TX_MARGIN_FULL_0[6] 30_235 -GTP_CHANNEL_3.GTPE2.TX_MARGIN_FULL_1[0] 30_236 -GTP_CHANNEL_3.GTPE2.TX_MARGIN_FULL_1[1] 31_236 -GTP_CHANNEL_3.GTPE2.TX_MARGIN_FULL_1[2] 30_237 -GTP_CHANNEL_3.GTPE2.TX_MARGIN_FULL_1[3] 31_237 -GTP_CHANNEL_3.GTPE2.TX_MARGIN_FULL_1[4] 30_238 -GTP_CHANNEL_3.GTPE2.TX_MARGIN_FULL_1[5] 31_238 -GTP_CHANNEL_3.GTPE2.TX_MARGIN_FULL_1[6] 30_239 -GTP_CHANNEL_3.GTPE2.TX_MARGIN_FULL_2[0] 30_240 -GTP_CHANNEL_3.GTPE2.TX_MARGIN_FULL_2[1] 31_240 -GTP_CHANNEL_3.GTPE2.TX_MARGIN_FULL_2[2] 30_241 -GTP_CHANNEL_3.GTPE2.TX_MARGIN_FULL_2[3] 31_241 -GTP_CHANNEL_3.GTPE2.TX_MARGIN_FULL_2[4] 30_242 -GTP_CHANNEL_3.GTPE2.TX_MARGIN_FULL_2[5] 31_242 -GTP_CHANNEL_3.GTPE2.TX_MARGIN_FULL_2[6] 30_243 -GTP_CHANNEL_3.GTPE2.TX_MARGIN_FULL_3[0] 30_244 -GTP_CHANNEL_3.GTPE2.TX_MARGIN_FULL_3[1] 31_244 -GTP_CHANNEL_3.GTPE2.TX_MARGIN_FULL_3[2] 30_245 -GTP_CHANNEL_3.GTPE2.TX_MARGIN_FULL_3[3] 31_245 -GTP_CHANNEL_3.GTPE2.TX_MARGIN_FULL_3[4] 30_246 -GTP_CHANNEL_3.GTPE2.TX_MARGIN_FULL_3[5] 31_246 -GTP_CHANNEL_3.GTPE2.TX_MARGIN_FULL_3[6] 30_247 -GTP_CHANNEL_3.GTPE2.TX_MARGIN_FULL_4[0] 30_248 -GTP_CHANNEL_3.GTPE2.TX_MARGIN_FULL_4[1] 31_248 -GTP_CHANNEL_3.GTPE2.TX_MARGIN_FULL_4[2] 30_249 -GTP_CHANNEL_3.GTPE2.TX_MARGIN_FULL_4[3] 31_249 -GTP_CHANNEL_3.GTPE2.TX_MARGIN_FULL_4[4] 30_250 -GTP_CHANNEL_3.GTPE2.TX_MARGIN_FULL_4[5] 31_250 -GTP_CHANNEL_3.GTPE2.TX_MARGIN_FULL_4[6] 30_251 -GTP_CHANNEL_3.GTPE2.TX_MARGIN_LOW_0[0] 30_252 -GTP_CHANNEL_3.GTPE2.TX_MARGIN_LOW_0[1] 31_252 -GTP_CHANNEL_3.GTPE2.TX_MARGIN_LOW_0[2] 30_253 -GTP_CHANNEL_3.GTPE2.TX_MARGIN_LOW_0[3] 31_253 -GTP_CHANNEL_3.GTPE2.TX_MARGIN_LOW_0[4] 30_254 -GTP_CHANNEL_3.GTPE2.TX_MARGIN_LOW_0[5] 31_254 -GTP_CHANNEL_3.GTPE2.TX_MARGIN_LOW_0[6] 30_255 -GTP_CHANNEL_3.GTPE2.TX_MARGIN_LOW_1[0] 30_256 -GTP_CHANNEL_3.GTPE2.TX_MARGIN_LOW_1[1] 31_256 -GTP_CHANNEL_3.GTPE2.TX_MARGIN_LOW_1[2] 30_257 -GTP_CHANNEL_3.GTPE2.TX_MARGIN_LOW_1[3] 31_257 -GTP_CHANNEL_3.GTPE2.TX_MARGIN_LOW_1[4] 30_258 -GTP_CHANNEL_3.GTPE2.TX_MARGIN_LOW_1[5] 31_258 -GTP_CHANNEL_3.GTPE2.TX_MARGIN_LOW_1[6] 30_259 -GTP_CHANNEL_3.GTPE2.TX_MARGIN_LOW_2[0] 30_260 -GTP_CHANNEL_3.GTPE2.TX_MARGIN_LOW_2[1] 31_260 -GTP_CHANNEL_3.GTPE2.TX_MARGIN_LOW_2[2] 30_261 -GTP_CHANNEL_3.GTPE2.TX_MARGIN_LOW_2[3] 31_261 -GTP_CHANNEL_3.GTPE2.TX_MARGIN_LOW_2[4] 30_262 -GTP_CHANNEL_3.GTPE2.TX_MARGIN_LOW_2[5] 31_262 -GTP_CHANNEL_3.GTPE2.TX_MARGIN_LOW_2[6] 30_263 -GTP_CHANNEL_3.GTPE2.TX_MARGIN_LOW_3[0] 30_264 -GTP_CHANNEL_3.GTPE2.TX_MARGIN_LOW_3[1] 31_264 -GTP_CHANNEL_3.GTPE2.TX_MARGIN_LOW_3[2] 30_265 -GTP_CHANNEL_3.GTPE2.TX_MARGIN_LOW_3[3] 31_265 -GTP_CHANNEL_3.GTPE2.TX_MARGIN_LOW_3[4] 30_266 -GTP_CHANNEL_3.GTPE2.TX_MARGIN_LOW_3[5] 31_266 -GTP_CHANNEL_3.GTPE2.TX_MARGIN_LOW_3[6] 30_267 -GTP_CHANNEL_3.GTPE2.TX_MARGIN_LOW_4[0] 30_268 -GTP_CHANNEL_3.GTPE2.TX_MARGIN_LOW_4[1] 31_268 -GTP_CHANNEL_3.GTPE2.TX_MARGIN_LOW_4[2] 30_269 -GTP_CHANNEL_3.GTPE2.TX_MARGIN_LOW_4[3] 31_269 -GTP_CHANNEL_3.GTPE2.TX_MARGIN_LOW_4[4] 30_270 -GTP_CHANNEL_3.GTPE2.TX_MARGIN_LOW_4[5] 31_270 -GTP_CHANNEL_3.GTPE2.TX_MARGIN_LOW_4[6] 30_271 -GTP_CHANNEL_3.GTPE2.TX_PREDRIVER_MODE[0] 28_206 -GTP_CHANNEL_3.GTPE2.TX_RXDETECT_CFG[0] 30_296 -GTP_CHANNEL_3.GTPE2.TX_RXDETECT_CFG[1] 31_296 -GTP_CHANNEL_3.GTPE2.TX_RXDETECT_CFG[2] 30_297 -GTP_CHANNEL_3.GTPE2.TX_RXDETECT_CFG[3] 31_297 -GTP_CHANNEL_3.GTPE2.TX_RXDETECT_CFG[4] 30_298 -GTP_CHANNEL_3.GTPE2.TX_RXDETECT_CFG[5] 31_298 -GTP_CHANNEL_3.GTPE2.TX_RXDETECT_CFG[6] 30_299 -GTP_CHANNEL_3.GTPE2.TX_RXDETECT_CFG[7] 31_299 -GTP_CHANNEL_3.GTPE2.TX_RXDETECT_CFG[8] 30_300 -GTP_CHANNEL_3.GTPE2.TX_RXDETECT_CFG[9] 31_300 -GTP_CHANNEL_3.GTPE2.TX_RXDETECT_CFG[10] 30_301 -GTP_CHANNEL_3.GTPE2.TX_RXDETECT_CFG[11] 31_301 -GTP_CHANNEL_3.GTPE2.TX_RXDETECT_CFG[12] 30_302 -GTP_CHANNEL_3.GTPE2.TX_RXDETECT_CFG[13] 31_302 -GTP_CHANNEL_3.GTPE2.TX_RXDETECT_REF[0] 30_292 -GTP_CHANNEL_3.GTPE2.TX_RXDETECT_REF[1] 31_292 -GTP_CHANNEL_3.GTPE2.TX_RXDETECT_REF[2] 30_293 -GTP_CHANNEL_3.GTPE2.TX_XCLK_SEL.TXUSR 31_11 -GTP_CHANNEL_3.GTPE2.TX_CLK25_DIV[0] 30_144 -GTP_CHANNEL_3.GTPE2.TX_CLK25_DIV[1] 31_144 -GTP_CHANNEL_3.GTPE2.TX_CLK25_DIV[2] 30_145 -GTP_CHANNEL_3.GTPE2.TX_CLK25_DIV[3] 31_145 -GTP_CHANNEL_3.GTPE2.TX_CLK25_DIV[4] 30_146 -GTP_CHANNEL_3.GTPE2.TX_DEEMPH0[0] 30_272 -GTP_CHANNEL_3.GTPE2.TX_DEEMPH0[1] 31_272 -GTP_CHANNEL_3.GTPE2.TX_DEEMPH0[2] 30_273 -GTP_CHANNEL_3.GTPE2.TX_DEEMPH0[3] 31_273 -GTP_CHANNEL_3.GTPE2.TX_DEEMPH0[4] 30_274 -GTP_CHANNEL_3.GTPE2.TX_DEEMPH0[5] 31_274 -GTP_CHANNEL_3.GTPE2.TX_DEEMPH1[0] 30_276 -GTP_CHANNEL_3.GTPE2.TX_DEEMPH1[1] 31_276 -GTP_CHANNEL_3.GTPE2.TX_DEEMPH1[2] 30_277 -GTP_CHANNEL_3.GTPE2.TX_DEEMPH1[3] 31_277 -GTP_CHANNEL_3.GTPE2.TX_DEEMPH1[4] 30_278 -GTP_CHANNEL_3.GTPE2.TX_DEEMPH1[5] 31_278 -GTP_CHANNEL_3.GTPE2.TXBUF_EN 28_231 -GTP_CHANNEL_3.GTPE2.TXBUF_RESET_ON_RATE_CHANGE 29_231 -GTP_CHANNEL_3.GTPE2.TXDLY_CFG[0] 30_80 -GTP_CHANNEL_3.GTPE2.TXDLY_CFG[1] 31_80 -GTP_CHANNEL_3.GTPE2.TXDLY_CFG[2] 30_81 -GTP_CHANNEL_3.GTPE2.TXDLY_CFG[3] 31_81 -GTP_CHANNEL_3.GTPE2.TXDLY_CFG[4] 30_82 -GTP_CHANNEL_3.GTPE2.TXDLY_CFG[5] 31_82 -GTP_CHANNEL_3.GTPE2.TXDLY_CFG[6] 30_83 -GTP_CHANNEL_3.GTPE2.TXDLY_CFG[7] 31_83 -GTP_CHANNEL_3.GTPE2.TXDLY_CFG[8] 30_84 -GTP_CHANNEL_3.GTPE2.TXDLY_CFG[9] 31_84 -GTP_CHANNEL_3.GTPE2.TXDLY_CFG[10] 30_85 -GTP_CHANNEL_3.GTPE2.TXDLY_CFG[11] 31_85 -GTP_CHANNEL_3.GTPE2.TXDLY_CFG[12] 30_86 -GTP_CHANNEL_3.GTPE2.TXDLY_CFG[13] 31_86 -GTP_CHANNEL_3.GTPE2.TXDLY_CFG[14] 30_87 -GTP_CHANNEL_3.GTPE2.TXDLY_CFG[15] 31_87 -GTP_CHANNEL_3.GTPE2.TXDLY_LCFG[0] 30_568 -GTP_CHANNEL_3.GTPE2.TXDLY_LCFG[1] 31_568 -GTP_CHANNEL_3.GTPE2.TXDLY_LCFG[2] 30_569 -GTP_CHANNEL_3.GTPE2.TXDLY_LCFG[3] 31_569 -GTP_CHANNEL_3.GTPE2.TXDLY_LCFG[4] 30_570 -GTP_CHANNEL_3.GTPE2.TXDLY_LCFG[5] 31_570 -GTP_CHANNEL_3.GTPE2.TXDLY_LCFG[6] 30_571 -GTP_CHANNEL_3.GTPE2.TXDLY_LCFG[7] 31_571 -GTP_CHANNEL_3.GTPE2.TXDLY_LCFG[8] 30_572 -GTP_CHANNEL_3.GTPE2.TXDLY_TAP_CFG[0] 30_88 -GTP_CHANNEL_3.GTPE2.TXDLY_TAP_CFG[1] 31_88 -GTP_CHANNEL_3.GTPE2.TXDLY_TAP_CFG[2] 30_89 -GTP_CHANNEL_3.GTPE2.TXDLY_TAP_CFG[3] 31_89 -GTP_CHANNEL_3.GTPE2.TXDLY_TAP_CFG[4] 30_90 -GTP_CHANNEL_3.GTPE2.TXDLY_TAP_CFG[5] 31_90 -GTP_CHANNEL_3.GTPE2.TXDLY_TAP_CFG[6] 30_91 -GTP_CHANNEL_3.GTPE2.TXDLY_TAP_CFG[7] 31_91 -GTP_CHANNEL_3.GTPE2.TXDLY_TAP_CFG[8] 30_92 -GTP_CHANNEL_3.GTPE2.TXDLY_TAP_CFG[9] 31_92 -GTP_CHANNEL_3.GTPE2.TXDLY_TAP_CFG[10] 30_93 -GTP_CHANNEL_3.GTPE2.TXDLY_TAP_CFG[11] 31_93 -GTP_CHANNEL_3.GTPE2.TXDLY_TAP_CFG[12] 30_94 -GTP_CHANNEL_3.GTPE2.TXDLY_TAP_CFG[13] 31_94 -GTP_CHANNEL_3.GTPE2.TXDLY_TAP_CFG[14] 30_95 -GTP_CHANNEL_3.GTPE2.TXDLY_TAP_CFG[15] 31_95 -GTP_CHANNEL_3.GTPE2.TXGEARBOX_EN 29_226 -GTP_CHANNEL_3.GTPE2.TXOOB_CFG[0] 31_20 -GTP_CHANNEL_3.GTPE2.TXOUT_DIV[0] 30_386 -GTP_CHANNEL_3.GTPE2.TXOUT_DIV[1] 31_386 -GTP_CHANNEL_3.GTPE2.TXPCSRESET_TIME[0] 29_130 -GTP_CHANNEL_3.GTPE2.TXPCSRESET_TIME[1] 28_131 -GTP_CHANNEL_3.GTPE2.TXPCSRESET_TIME[2] 29_131 -GTP_CHANNEL_3.GTPE2.TXPCSRESET_TIME[3] 28_132 -GTP_CHANNEL_3.GTPE2.TXPCSRESET_TIME[4] 29_132 -GTP_CHANNEL_3.GTPE2.TXPH_CFG[0] 30_96 -GTP_CHANNEL_3.GTPE2.TXPH_CFG[1] 31_96 -GTP_CHANNEL_3.GTPE2.TXPH_CFG[2] 30_97 -GTP_CHANNEL_3.GTPE2.TXPH_CFG[3] 31_97 -GTP_CHANNEL_3.GTPE2.TXPH_CFG[4] 30_98 -GTP_CHANNEL_3.GTPE2.TXPH_CFG[5] 31_98 -GTP_CHANNEL_3.GTPE2.TXPH_CFG[6] 30_99 -GTP_CHANNEL_3.GTPE2.TXPH_CFG[7] 31_99 -GTP_CHANNEL_3.GTPE2.TXPH_CFG[8] 30_100 -GTP_CHANNEL_3.GTPE2.TXPH_CFG[9] 31_100 -GTP_CHANNEL_3.GTPE2.TXPH_CFG[10] 30_101 -GTP_CHANNEL_3.GTPE2.TXPH_CFG[11] 31_101 -GTP_CHANNEL_3.GTPE2.TXPH_CFG[12] 30_102 -GTP_CHANNEL_3.GTPE2.TXPH_CFG[13] 31_102 -GTP_CHANNEL_3.GTPE2.TXPH_CFG[14] 30_103 -GTP_CHANNEL_3.GTPE2.TXPH_CFG[15] 31_103 -GTP_CHANNEL_3.GTPE2.TXPH_MONITOR_SEL[0] 30_108 -GTP_CHANNEL_3.GTPE2.TXPH_MONITOR_SEL[1] 31_108 -GTP_CHANNEL_3.GTPE2.TXPH_MONITOR_SEL[2] 30_109 -GTP_CHANNEL_3.GTPE2.TXPH_MONITOR_SEL[3] 31_109 -GTP_CHANNEL_3.GTPE2.TXPH_MONITOR_SEL[4] 30_110 -GTP_CHANNEL_3.GTPE2.TXPHDLY_CFG[0] 30_64 -GTP_CHANNEL_3.GTPE2.TXPHDLY_CFG[1] 31_64 -GTP_CHANNEL_3.GTPE2.TXPHDLY_CFG[2] 30_65 -GTP_CHANNEL_3.GTPE2.TXPHDLY_CFG[3] 31_65 -GTP_CHANNEL_3.GTPE2.TXPHDLY_CFG[4] 30_66 -GTP_CHANNEL_3.GTPE2.TXPHDLY_CFG[5] 31_66 -GTP_CHANNEL_3.GTPE2.TXPHDLY_CFG[6] 30_67 -GTP_CHANNEL_3.GTPE2.TXPHDLY_CFG[7] 31_67 -GTP_CHANNEL_3.GTPE2.TXPHDLY_CFG[8] 30_68 -GTP_CHANNEL_3.GTPE2.TXPHDLY_CFG[9] 31_68 -GTP_CHANNEL_3.GTPE2.TXPHDLY_CFG[10] 30_69 -GTP_CHANNEL_3.GTPE2.TXPHDLY_CFG[11] 31_69 -GTP_CHANNEL_3.GTPE2.TXPHDLY_CFG[12] 30_70 -GTP_CHANNEL_3.GTPE2.TXPHDLY_CFG[13] 31_70 -GTP_CHANNEL_3.GTPE2.TXPHDLY_CFG[14] 30_71 -GTP_CHANNEL_3.GTPE2.TXPHDLY_CFG[15] 31_71 -GTP_CHANNEL_3.GTPE2.TXPHDLY_CFG[16] 30_72 -GTP_CHANNEL_3.GTPE2.TXPHDLY_CFG[17] 31_72 -GTP_CHANNEL_3.GTPE2.TXPHDLY_CFG[18] 30_73 -GTP_CHANNEL_3.GTPE2.TXPHDLY_CFG[19] 31_73 -GTP_CHANNEL_3.GTPE2.TXPHDLY_CFG[20] 30_74 -GTP_CHANNEL_3.GTPE2.TXPHDLY_CFG[21] 31_74 -GTP_CHANNEL_3.GTPE2.TXPHDLY_CFG[22] 30_75 -GTP_CHANNEL_3.GTPE2.TXPHDLY_CFG[23] 31_75 -GTP_CHANNEL_3.GTPE2.TXPI_GREY_SEL[0] 31_498 -GTP_CHANNEL_3.GTPE2.TXPI_INVSTROBE_SEL[0] 30_498 -GTP_CHANNEL_3.GTPE2.TXPI_PPM_CFG[0] 30_488 -GTP_CHANNEL_3.GTPE2.TXPI_PPM_CFG[1] 31_488 -GTP_CHANNEL_3.GTPE2.TXPI_PPM_CFG[2] 30_489 -GTP_CHANNEL_3.GTPE2.TXPI_PPM_CFG[3] 31_489 -GTP_CHANNEL_3.GTPE2.TXPI_PPM_CFG[4] 30_490 -GTP_CHANNEL_3.GTPE2.TXPI_PPM_CFG[5] 31_490 -GTP_CHANNEL_3.GTPE2.TXPI_PPM_CFG[6] 30_491 -GTP_CHANNEL_3.GTPE2.TXPI_PPM_CFG[7] 31_491 -GTP_CHANNEL_3.GTPE2.TXPI_PPMCLK_SEL.TXUSRCLK2 31_497 -GTP_CHANNEL_3.GTPE2.TXPI_SYNFREQ_PPM[0] 30_496 -GTP_CHANNEL_3.GTPE2.TXPI_SYNFREQ_PPM[1] 31_496 -GTP_CHANNEL_3.GTPE2.TXPI_SYNFREQ_PPM[2] 30_497 -GTP_CHANNEL_3.GTPE2.TXPI_CFG0[0] 30_40 -GTP_CHANNEL_3.GTPE2.TXPI_CFG0[1] 31_40 -GTP_CHANNEL_3.GTPE2.TXPI_CFG1[0] 30_41 -GTP_CHANNEL_3.GTPE2.TXPI_CFG1[1] 31_41 -GTP_CHANNEL_3.GTPE2.TXPI_CFG2[0] 30_42 -GTP_CHANNEL_3.GTPE2.TXPI_CFG2[1] 31_42 -GTP_CHANNEL_3.GTPE2.TXPI_CFG3[0] 30_43 -GTP_CHANNEL_3.GTPE2.TXPI_CFG4[0] 31_43 -GTP_CHANNEL_3.GTPE2.TXPI_CFG5[0] 30_44 -GTP_CHANNEL_3.GTPE2.TXPI_CFG5[1] 31_44 -GTP_CHANNEL_3.GTPE2.TXPI_CFG5[2] 30_45 -GTP_CHANNEL_3.GTPE2.TXPMARESET_TIME[0] 28_128 -GTP_CHANNEL_3.GTPE2.TXPMARESET_TIME[1] 29_128 -GTP_CHANNEL_3.GTPE2.TXPMARESET_TIME[2] 28_129 -GTP_CHANNEL_3.GTPE2.TXPMARESET_TIME[3] 29_129 -GTP_CHANNEL_3.GTPE2.TXPMARESET_TIME[4] 28_130 -GTP_CHANNEL_3.GTPE2.TXSYNC_MULTILANE[0] 29_133 -GTP_CHANNEL_3.GTPE2.TXSYNC_OVRD[0] 28_135 -GTP_CHANNEL_3.GTPE2.TXSYNC_SKIP_DA[0] 28_134 -GTP_CHANNEL_3.GTPE2.UCODEER_CLR[0] 29_00 -GTP_CHANNEL_3.GTPE2.USE_PCS_CLK_PHASE_SEL[0] 30_463 -GTP_CHANNEL_3.GTPE2.ZINV_DMONITORCLK 30_13 -GTP_CHANNEL_3.GTPE2.ZINV_DRPCLK 30_00 -GTP_CHANNEL_3.GTPE2.ZINV_RXUSRCLK 31_01 -GTP_CHANNEL_3.GTPE2.ZINV_SIGVALIDCLK 31_13 -GTP_CHANNEL_3.GTPE2.ZINV_TXPHDLYTSTCLK 30_03 -GTP_CHANNEL_3.GTPE2.ZINV_TXUSRCLK 31_04 -GTP_CHANNEL_3.GTPE2.ZINV_CLKRSVD0 30_23 -GTP_CHANNEL_3.GTPE2.ZINV_CLKRSVD1 31_23 -GTP_CHANNEL_3.GTPE2.ZINV_RXUSRCLK2 30_02 -GTP_CHANNEL_3.GTPE2.ZINV_TXUSRCLK2 30_05 +GTP_CHANNEL_3.GTPE2_CHANNEL.ACJTAG_DEBUG_MODE[0] 28_07 +GTP_CHANNEL_3.GTPE2_CHANNEL.ACJTAG_MODE[0] 29_06 +GTP_CHANNEL_3.GTPE2_CHANNEL.ACJTAG_RESET[0] 29_07 +GTP_CHANNEL_3.GTPE2_CHANNEL.ADAPT_CFG0[0] 30_464 +GTP_CHANNEL_3.GTPE2_CHANNEL.ADAPT_CFG0[1] 31_464 +GTP_CHANNEL_3.GTPE2_CHANNEL.ADAPT_CFG0[2] 30_465 +GTP_CHANNEL_3.GTPE2_CHANNEL.ADAPT_CFG0[3] 31_465 +GTP_CHANNEL_3.GTPE2_CHANNEL.ADAPT_CFG0[4] 30_466 +GTP_CHANNEL_3.GTPE2_CHANNEL.ADAPT_CFG0[5] 31_466 +GTP_CHANNEL_3.GTPE2_CHANNEL.ADAPT_CFG0[6] 30_467 +GTP_CHANNEL_3.GTPE2_CHANNEL.ADAPT_CFG0[7] 31_467 +GTP_CHANNEL_3.GTPE2_CHANNEL.ADAPT_CFG0[8] 30_468 +GTP_CHANNEL_3.GTPE2_CHANNEL.ADAPT_CFG0[9] 31_468 +GTP_CHANNEL_3.GTPE2_CHANNEL.ADAPT_CFG0[10] 30_469 +GTP_CHANNEL_3.GTPE2_CHANNEL.ADAPT_CFG0[11] 31_469 +GTP_CHANNEL_3.GTPE2_CHANNEL.ADAPT_CFG0[12] 30_470 +GTP_CHANNEL_3.GTPE2_CHANNEL.ADAPT_CFG0[13] 31_470 +GTP_CHANNEL_3.GTPE2_CHANNEL.ADAPT_CFG0[14] 30_471 +GTP_CHANNEL_3.GTPE2_CHANNEL.ADAPT_CFG0[15] 31_471 +GTP_CHANNEL_3.GTPE2_CHANNEL.ADAPT_CFG0[16] 30_472 +GTP_CHANNEL_3.GTPE2_CHANNEL.ADAPT_CFG0[17] 31_472 +GTP_CHANNEL_3.GTPE2_CHANNEL.ADAPT_CFG0[18] 30_473 +GTP_CHANNEL_3.GTPE2_CHANNEL.ADAPT_CFG0[19] 31_473 +GTP_CHANNEL_3.GTPE2_CHANNEL.ALIGN_COMMA_DOUBLE 28_522 +GTP_CHANNEL_3.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[0] 28_496 +GTP_CHANNEL_3.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[1] 29_496 +GTP_CHANNEL_3.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[2] 28_497 +GTP_CHANNEL_3.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[3] 29_497 +GTP_CHANNEL_3.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[4] 28_498 +GTP_CHANNEL_3.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[5] 29_498 +GTP_CHANNEL_3.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[6] 28_499 +GTP_CHANNEL_3.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[7] 29_499 +GTP_CHANNEL_3.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[8] 28_500 +GTP_CHANNEL_3.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[9] 29_500 +GTP_CHANNEL_3.GTPE2_CHANNEL.ALIGN_COMMA_WORD[0] 29_526 +GTP_CHANNEL_3.GTPE2_CHANNEL.ALIGN_COMMA_WORD[1] 28_527 +GTP_CHANNEL_3.GTPE2_CHANNEL.ALIGN_MCOMMA_DET 28_523 +GTP_CHANNEL_3.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[0] 28_504 +GTP_CHANNEL_3.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[1] 29_504 +GTP_CHANNEL_3.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[2] 28_505 +GTP_CHANNEL_3.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[3] 29_505 +GTP_CHANNEL_3.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[4] 28_506 +GTP_CHANNEL_3.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[5] 29_506 +GTP_CHANNEL_3.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[6] 28_507 +GTP_CHANNEL_3.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[7] 29_507 +GTP_CHANNEL_3.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[8] 28_508 +GTP_CHANNEL_3.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[9] 29_508 +GTP_CHANNEL_3.GTPE2_CHANNEL.ALIGN_PCOMMA_DET 29_523 +GTP_CHANNEL_3.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[0] 28_512 +GTP_CHANNEL_3.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[1] 29_512 +GTP_CHANNEL_3.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[2] 28_513 +GTP_CHANNEL_3.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[3] 29_513 +GTP_CHANNEL_3.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[4] 28_514 +GTP_CHANNEL_3.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[5] 29_514 +GTP_CHANNEL_3.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[6] 28_515 +GTP_CHANNEL_3.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[7] 29_515 +GTP_CHANNEL_3.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[8] 28_516 +GTP_CHANNEL_3.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[9] 29_516 +GTP_CHANNEL_3.GTPE2_CHANNEL.CBCC_DATA_SOURCE_SEL.DECODED 29_661 +GTP_CHANNEL_3.GTPE2_CHANNEL.CFOK_CFG[0] 30_392 +GTP_CHANNEL_3.GTPE2_CHANNEL.CFOK_CFG[1] 31_392 +GTP_CHANNEL_3.GTPE2_CHANNEL.CFOK_CFG[2] 30_393 +GTP_CHANNEL_3.GTPE2_CHANNEL.CFOK_CFG[3] 31_393 +GTP_CHANNEL_3.GTPE2_CHANNEL.CFOK_CFG[4] 30_394 +GTP_CHANNEL_3.GTPE2_CHANNEL.CFOK_CFG[5] 31_394 +GTP_CHANNEL_3.GTPE2_CHANNEL.CFOK_CFG[6] 30_395 +GTP_CHANNEL_3.GTPE2_CHANNEL.CFOK_CFG[7] 31_395 +GTP_CHANNEL_3.GTPE2_CHANNEL.CFOK_CFG[8] 30_396 +GTP_CHANNEL_3.GTPE2_CHANNEL.CFOK_CFG[9] 31_396 +GTP_CHANNEL_3.GTPE2_CHANNEL.CFOK_CFG[10] 30_397 +GTP_CHANNEL_3.GTPE2_CHANNEL.CFOK_CFG[11] 31_397 +GTP_CHANNEL_3.GTPE2_CHANNEL.CFOK_CFG[12] 30_398 +GTP_CHANNEL_3.GTPE2_CHANNEL.CFOK_CFG[13] 31_398 +GTP_CHANNEL_3.GTPE2_CHANNEL.CFOK_CFG[14] 30_399 +GTP_CHANNEL_3.GTPE2_CHANNEL.CFOK_CFG[15] 31_399 +GTP_CHANNEL_3.GTPE2_CHANNEL.CFOK_CFG[16] 30_400 +GTP_CHANNEL_3.GTPE2_CHANNEL.CFOK_CFG[17] 31_400 +GTP_CHANNEL_3.GTPE2_CHANNEL.CFOK_CFG[18] 30_401 +GTP_CHANNEL_3.GTPE2_CHANNEL.CFOK_CFG[19] 31_401 +GTP_CHANNEL_3.GTPE2_CHANNEL.CFOK_CFG[20] 30_402 +GTP_CHANNEL_3.GTPE2_CHANNEL.CFOK_CFG[21] 31_402 +GTP_CHANNEL_3.GTPE2_CHANNEL.CFOK_CFG[22] 30_403 +GTP_CHANNEL_3.GTPE2_CHANNEL.CFOK_CFG[23] 31_403 +GTP_CHANNEL_3.GTPE2_CHANNEL.CFOK_CFG[24] 30_404 +GTP_CHANNEL_3.GTPE2_CHANNEL.CFOK_CFG[25] 31_404 +GTP_CHANNEL_3.GTPE2_CHANNEL.CFOK_CFG[26] 30_405 +GTP_CHANNEL_3.GTPE2_CHANNEL.CFOK_CFG[27] 31_405 +GTP_CHANNEL_3.GTPE2_CHANNEL.CFOK_CFG[28] 30_406 +GTP_CHANNEL_3.GTPE2_CHANNEL.CFOK_CFG[29] 31_406 +GTP_CHANNEL_3.GTPE2_CHANNEL.CFOK_CFG[30] 30_407 +GTP_CHANNEL_3.GTPE2_CHANNEL.CFOK_CFG[31] 31_407 +GTP_CHANNEL_3.GTPE2_CHANNEL.CFOK_CFG[32] 30_408 +GTP_CHANNEL_3.GTPE2_CHANNEL.CFOK_CFG[33] 31_408 +GTP_CHANNEL_3.GTPE2_CHANNEL.CFOK_CFG[34] 30_409 +GTP_CHANNEL_3.GTPE2_CHANNEL.CFOK_CFG[35] 31_409 +GTP_CHANNEL_3.GTPE2_CHANNEL.CFOK_CFG[36] 30_410 +GTP_CHANNEL_3.GTPE2_CHANNEL.CFOK_CFG[37] 31_410 +GTP_CHANNEL_3.GTPE2_CHANNEL.CFOK_CFG[38] 30_411 +GTP_CHANNEL_3.GTPE2_CHANNEL.CFOK_CFG[39] 31_411 +GTP_CHANNEL_3.GTPE2_CHANNEL.CFOK_CFG[40] 30_412 +GTP_CHANNEL_3.GTPE2_CHANNEL.CFOK_CFG[41] 31_412 +GTP_CHANNEL_3.GTPE2_CHANNEL.CFOK_CFG[42] 30_413 +GTP_CHANNEL_3.GTPE2_CHANNEL.CFOK_CFG2[0] 30_459 +GTP_CHANNEL_3.GTPE2_CHANNEL.CFOK_CFG2[1] 31_459 +GTP_CHANNEL_3.GTPE2_CHANNEL.CFOK_CFG2[2] 30_460 +GTP_CHANNEL_3.GTPE2_CHANNEL.CFOK_CFG2[3] 31_460 +GTP_CHANNEL_3.GTPE2_CHANNEL.CFOK_CFG2[4] 30_461 +GTP_CHANNEL_3.GTPE2_CHANNEL.CFOK_CFG2[5] 31_461 +GTP_CHANNEL_3.GTPE2_CHANNEL.CFOK_CFG2[6] 30_462 +GTP_CHANNEL_3.GTPE2_CHANNEL.CFOK_CFG3[0] 30_416 +GTP_CHANNEL_3.GTPE2_CHANNEL.CFOK_CFG3[1] 31_416 +GTP_CHANNEL_3.GTPE2_CHANNEL.CFOK_CFG3[2] 30_417 +GTP_CHANNEL_3.GTPE2_CHANNEL.CFOK_CFG3[3] 31_417 +GTP_CHANNEL_3.GTPE2_CHANNEL.CFOK_CFG3[4] 30_418 +GTP_CHANNEL_3.GTPE2_CHANNEL.CFOK_CFG3[5] 31_418 +GTP_CHANNEL_3.GTPE2_CHANNEL.CFOK_CFG3[6] 30_419 +GTP_CHANNEL_3.GTPE2_CHANNEL.CFOK_CFG4[0] 31_438 +GTP_CHANNEL_3.GTPE2_CHANNEL.CFOK_CFG5[0] 30_429 +GTP_CHANNEL_3.GTPE2_CHANNEL.CFOK_CFG5[1] 31_429 +GTP_CHANNEL_3.GTPE2_CHANNEL.CFOK_CFG6[0] 31_436 +GTP_CHANNEL_3.GTPE2_CHANNEL.CFOK_CFG6[1] 30_437 +GTP_CHANNEL_3.GTPE2_CHANNEL.CFOK_CFG6[2] 31_437 +GTP_CHANNEL_3.GTPE2_CHANNEL.CFOK_CFG6[3] 30_438 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_KEEP_ALIGN 29_631 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_MAX_SKEW[0] 28_670 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_MAX_SKEW[1] 29_670 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_MAX_SKEW[2] 28_671 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_MAX_SKEW[3] 29_671 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[0] 28_608 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[1] 29_608 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[2] 28_609 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[3] 29_609 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[4] 28_610 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[5] 29_610 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[6] 28_611 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[7] 29_611 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[8] 28_612 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[9] 29_612 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[0] 28_616 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[1] 29_616 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[2] 28_617 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[3] 29_617 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[4] 28_618 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[5] 29_618 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[6] 28_619 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[7] 29_619 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[8] 28_620 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[9] 29_620 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[0] 28_624 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[1] 29_624 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[2] 28_625 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[3] 29_625 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[4] 28_626 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[5] 29_626 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[6] 28_627 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[7] 29_627 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[8] 28_628 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[9] 29_628 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[0] 28_632 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[1] 29_632 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[2] 28_633 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[3] 29_633 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[4] 28_634 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[5] 29_634 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[6] 28_635 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[7] 29_635 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[8] 28_636 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[9] 29_636 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_ENABLE[0] 28_614 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_ENABLE[1] 29_614 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_ENABLE[2] 28_615 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_ENABLE[3] 29_615 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[0] 28_640 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[1] 29_640 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[2] 28_641 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[3] 29_641 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[4] 28_642 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[5] 29_642 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[6] 28_643 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[7] 29_643 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[8] 28_644 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[9] 29_644 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[0] 28_648 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[1] 29_648 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[2] 28_649 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[3] 29_649 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[4] 28_650 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[5] 29_650 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[6] 28_651 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[7] 29_651 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[8] 28_652 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[9] 29_652 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[0] 28_656 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[1] 29_656 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[2] 28_657 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[3] 29_657 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[4] 28_658 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[5] 29_658 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[6] 28_659 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[7] 29_659 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[8] 28_660 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[9] 29_660 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[0] 28_664 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[1] 29_664 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[2] 28_665 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[3] 29_665 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[4] 28_666 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[5] 29_666 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[6] 28_667 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[7] 29_667 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[8] 28_668 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[9] 29_668 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_ENABLE[0] 28_646 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_ENABLE[1] 29_646 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_ENABLE[2] 28_647 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_ENABLE[3] 29_647 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_USE 29_645 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_LEN[0] 28_623 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_LEN[1] 29_623 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COMMON_SWING[0] 31_311 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_KEEP_IDLE 28_591 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_MAX_LAT[0] 28_557 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_MAX_LAT[1] 29_557 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_MAX_LAT[2] 28_558 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_MAX_LAT[3] 29_558 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_MAX_LAT[4] 28_559 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_MAX_LAT[5] 29_559 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_MIN_LAT[0] 28_565 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_MIN_LAT[1] 29_565 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_MIN_LAT[2] 28_566 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_MIN_LAT[3] 29_566 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_MIN_LAT[4] 28_567 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_MIN_LAT[5] 29_567 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_PRECEDENCE 28_590 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_REPEAT_WAIT[0] 28_573 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_REPEAT_WAIT[1] 29_573 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_REPEAT_WAIT[2] 28_574 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_REPEAT_WAIT[3] 29_574 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_REPEAT_WAIT[4] 28_575 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[0] 28_544 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[1] 29_544 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[2] 28_545 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[3] 29_545 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[4] 28_546 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[5] 29_546 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[6] 28_547 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[7] 29_547 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[8] 28_548 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[9] 29_548 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[0] 28_552 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[1] 29_552 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[2] 28_553 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[3] 29_553 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[4] 28_554 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[5] 29_554 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[6] 28_555 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[7] 29_555 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[8] 28_556 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[9] 29_556 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[0] 28_560 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[1] 29_560 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[2] 28_561 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[3] 29_561 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[4] 28_562 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[5] 29_562 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[6] 28_563 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[7] 29_563 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[8] 28_564 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[9] 29_564 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[0] 28_568 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[1] 29_568 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[2] 28_569 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[3] 29_569 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[4] 28_570 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[5] 29_570 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[6] 28_571 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[7] 29_571 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[8] 28_572 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[9] 29_572 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_1_ENABLE[0] 28_549 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_1_ENABLE[1] 29_549 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_1_ENABLE[2] 28_550 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_1_ENABLE[3] 29_550 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[0] 28_576 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[1] 29_576 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[2] 28_577 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[3] 29_577 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[4] 28_578 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[5] 29_578 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[6] 28_579 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[7] 29_579 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[8] 28_580 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[9] 29_580 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[0] 28_584 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[1] 29_584 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[2] 28_585 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[3] 29_585 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[4] 28_586 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[5] 29_586 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[6] 28_587 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[7] 29_587 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[8] 28_588 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[9] 29_588 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[0] 28_592 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[1] 29_592 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[2] 28_593 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[3] 29_593 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[4] 28_594 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[5] 29_594 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[6] 28_595 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[7] 29_595 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[8] 28_596 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[9] 29_596 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[0] 28_600 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[1] 29_600 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[2] 28_601 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[3] 29_601 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[4] 28_602 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[5] 29_602 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[6] 28_603 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[7] 29_603 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[8] 28_604 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[9] 29_604 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_2_ENABLE[0] 28_581 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_2_ENABLE[1] 29_581 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_2_ENABLE[2] 28_582 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_2_ENABLE[3] 29_582 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_2_USE 28_583 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_LEN[0] 28_589 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_LEN[1] 29_589 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_CORRECT_USE 28_551 +GTP_CHANNEL_3.GTPE2_CHANNEL.DEC_MCOMMA_DETECT 29_494 +GTP_CHANNEL_3.GTPE2_CHANNEL.DEC_PCOMMA_DETECT 28_495 +GTP_CHANNEL_3.GTPE2_CHANNEL.DEC_VALID_COMMA_ONLY 28_494 +GTP_CHANNEL_3.GTPE2_CHANNEL.DMONITOR_CFG[0] 30_368 +GTP_CHANNEL_3.GTPE2_CHANNEL.DMONITOR_CFG[1] 31_368 +GTP_CHANNEL_3.GTPE2_CHANNEL.DMONITOR_CFG[2] 30_369 +GTP_CHANNEL_3.GTPE2_CHANNEL.DMONITOR_CFG[3] 31_369 +GTP_CHANNEL_3.GTPE2_CHANNEL.DMONITOR_CFG[4] 30_370 +GTP_CHANNEL_3.GTPE2_CHANNEL.DMONITOR_CFG[5] 31_370 +GTP_CHANNEL_3.GTPE2_CHANNEL.DMONITOR_CFG[6] 30_371 +GTP_CHANNEL_3.GTPE2_CHANNEL.DMONITOR_CFG[7] 31_371 +GTP_CHANNEL_3.GTPE2_CHANNEL.DMONITOR_CFG[8] 30_372 +GTP_CHANNEL_3.GTPE2_CHANNEL.DMONITOR_CFG[9] 31_372 +GTP_CHANNEL_3.GTPE2_CHANNEL.DMONITOR_CFG[10] 30_373 +GTP_CHANNEL_3.GTPE2_CHANNEL.DMONITOR_CFG[11] 31_373 +GTP_CHANNEL_3.GTPE2_CHANNEL.DMONITOR_CFG[12] 30_374 +GTP_CHANNEL_3.GTPE2_CHANNEL.DMONITOR_CFG[13] 31_374 +GTP_CHANNEL_3.GTPE2_CHANNEL.DMONITOR_CFG[14] 30_375 +GTP_CHANNEL_3.GTPE2_CHANNEL.DMONITOR_CFG[15] 31_375 +GTP_CHANNEL_3.GTPE2_CHANNEL.DMONITOR_CFG[16] 30_376 +GTP_CHANNEL_3.GTPE2_CHANNEL.DMONITOR_CFG[17] 31_376 +GTP_CHANNEL_3.GTPE2_CHANNEL.DMONITOR_CFG[18] 30_377 +GTP_CHANNEL_3.GTPE2_CHANNEL.DMONITOR_CFG[19] 31_377 +GTP_CHANNEL_3.GTPE2_CHANNEL.DMONITOR_CFG[20] 30_378 +GTP_CHANNEL_3.GTPE2_CHANNEL.DMONITOR_CFG[21] 31_378 +GTP_CHANNEL_3.GTPE2_CHANNEL.DMONITOR_CFG[22] 30_379 +GTP_CHANNEL_3.GTPE2_CHANNEL.DMONITOR_CFG[23] 31_379 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_CLK_PHASE_SEL[0] 31_463 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_CONTROL[0] 28_488 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_CONTROL[1] 29_488 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_CONTROL[2] 28_489 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_CONTROL[3] 29_489 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_CONTROL[4] 28_490 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_CONTROL[5] 29_490 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_ERRDET_EN 29_492 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_EYE_SCAN_EN 28_492 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_HORZ_OFFSET[0] 28_480 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_HORZ_OFFSET[1] 29_480 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_HORZ_OFFSET[2] 28_481 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_HORZ_OFFSET[3] 29_481 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_HORZ_OFFSET[4] 28_482 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_HORZ_OFFSET[5] 29_482 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_HORZ_OFFSET[6] 28_483 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_HORZ_OFFSET[7] 29_483 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_HORZ_OFFSET[8] 28_484 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_HORZ_OFFSET[9] 29_484 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_HORZ_OFFSET[10] 28_485 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_HORZ_OFFSET[11] 29_485 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_PMA_CFG[0] 30_624 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_PMA_CFG[1] 31_624 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_PMA_CFG[2] 30_625 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_PMA_CFG[3] 31_625 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_PMA_CFG[4] 30_626 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_PMA_CFG[5] 31_626 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_PMA_CFG[6] 30_627 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_PMA_CFG[7] 31_627 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_PMA_CFG[8] 30_628 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_PMA_CFG[9] 31_628 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_PRESCALE[0] 29_477 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_PRESCALE[1] 28_478 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_PRESCALE[2] 29_478 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_PRESCALE[3] 28_479 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_PRESCALE[4] 29_479 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[0] 28_392 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[1] 29_392 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[2] 28_393 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[3] 29_393 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[4] 28_394 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[5] 29_394 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[6] 28_395 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[7] 29_395 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[8] 28_396 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[9] 29_396 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[10] 28_397 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[11] 29_397 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[12] 28_398 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[13] 29_398 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[14] 28_399 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[15] 29_399 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[16] 28_400 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[17] 29_400 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[18] 28_401 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[19] 29_401 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[20] 28_402 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[21] 29_402 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[22] 28_403 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[23] 29_403 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[24] 28_404 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[25] 29_404 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[26] 28_405 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[27] 29_405 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[28] 28_406 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[29] 29_406 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[30] 28_407 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[31] 29_407 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[32] 28_408 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[33] 29_408 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[34] 28_409 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[35] 29_409 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[36] 28_410 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[37] 29_410 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[38] 28_411 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[39] 29_411 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[40] 28_412 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[41] 29_412 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[42] 28_413 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[43] 29_413 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[44] 28_414 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[45] 29_414 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[46] 28_415 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[47] 29_415 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[48] 28_416 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[49] 29_416 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[50] 28_417 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[51] 29_417 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[52] 28_418 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[53] 29_418 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[54] 28_419 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[55] 29_419 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[56] 28_420 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[57] 29_420 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[58] 28_421 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[59] 29_421 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[60] 28_422 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[61] 29_422 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[62] 28_423 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[63] 29_423 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[64] 28_424 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[65] 29_424 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[66] 28_425 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[67] 29_425 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[68] 28_426 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[69] 29_426 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[70] 28_427 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[71] 29_427 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[72] 28_428 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[73] 29_428 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[74] 28_429 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[75] 29_429 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[76] 28_430 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[77] 29_430 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[78] 28_431 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[79] 29_431 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[0] 28_352 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[1] 29_352 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[2] 28_353 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[3] 29_353 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[4] 28_354 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[5] 29_354 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[6] 28_355 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[7] 29_355 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[8] 28_356 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[9] 29_356 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[10] 28_357 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[11] 29_357 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[12] 28_358 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[13] 29_358 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[14] 28_359 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[15] 29_359 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[16] 28_360 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[17] 29_360 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[18] 28_361 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[19] 29_361 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[20] 28_362 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[21] 29_362 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[22] 28_363 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[23] 29_363 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[24] 28_364 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[25] 29_364 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[26] 28_365 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[27] 29_365 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[28] 28_366 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[29] 29_366 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[30] 28_367 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[31] 29_367 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[32] 28_368 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[33] 29_368 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[34] 28_369 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[35] 29_369 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[36] 28_370 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[37] 29_370 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[38] 28_371 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[39] 29_371 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[40] 28_372 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[41] 29_372 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[42] 28_373 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[43] 29_373 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[44] 28_374 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[45] 29_374 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[46] 28_375 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[47] 29_375 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[48] 28_376 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[49] 29_376 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[50] 28_377 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[51] 29_377 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[52] 28_378 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[53] 29_378 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[54] 28_379 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[55] 29_379 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[56] 28_380 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[57] 29_380 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[58] 28_381 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[59] 29_381 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[60] 28_382 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[61] 29_382 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[62] 28_383 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[63] 29_383 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[64] 28_384 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[65] 29_384 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[66] 28_385 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[67] 29_385 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[68] 28_386 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[69] 29_386 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[70] 28_387 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[71] 29_387 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[72] 28_388 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[73] 29_388 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[74] 28_389 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[75] 29_389 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[76] 28_390 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[77] 29_390 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[78] 28_391 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[79] 29_391 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[0] 28_432 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[1] 29_432 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[2] 28_433 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[3] 29_433 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[4] 28_434 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[5] 29_434 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[6] 28_435 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[7] 29_435 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[8] 28_436 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[9] 29_436 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[10] 28_437 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[11] 29_437 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[12] 28_438 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[13] 29_438 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[14] 28_439 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[15] 29_439 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[16] 28_440 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[17] 29_440 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[18] 28_441 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[19] 29_441 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[20] 28_442 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[21] 29_442 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[22] 28_443 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[23] 29_443 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[24] 28_444 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[25] 29_444 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[26] 28_445 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[27] 29_445 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[28] 28_446 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[29] 29_446 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[30] 28_447 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[31] 29_447 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[32] 28_448 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[33] 29_448 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[34] 28_449 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[35] 29_449 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[36] 28_450 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[37] 29_450 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[38] 28_451 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[39] 29_451 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[40] 28_452 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[41] 29_452 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[42] 28_453 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[43] 29_453 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[44] 28_454 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[45] 29_454 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[46] 28_455 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[47] 29_455 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[48] 28_456 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[49] 29_456 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[50] 28_457 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[51] 29_457 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[52] 28_458 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[53] 29_458 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[54] 28_459 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[55] 29_459 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[56] 28_460 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[57] 29_460 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[58] 28_461 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[59] 29_461 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[60] 28_462 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[61] 29_462 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[62] 28_463 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[63] 29_463 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[64] 28_464 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[65] 29_464 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[66] 28_465 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[67] 29_465 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[68] 28_466 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[69] 29_466 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[70] 28_467 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[71] 29_467 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[72] 28_468 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[73] 29_468 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[74] 28_469 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[75] 29_469 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[76] 28_470 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[77] 29_470 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[78] 28_471 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[79] 29_471 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_VERT_OFFSET[0] 28_472 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_VERT_OFFSET[1] 29_472 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_VERT_OFFSET[2] 28_473 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_VERT_OFFSET[3] 29_473 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_VERT_OFFSET[4] 28_474 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_VERT_OFFSET[5] 29_474 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_VERT_OFFSET[6] 28_475 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_VERT_OFFSET[7] 29_475 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_VERT_OFFSET[8] 28_476 +GTP_CHANNEL_3.GTPE2_CHANNEL.FTS_DESKEW_SEQ_ENABLE[0] 28_662 +GTP_CHANNEL_3.GTPE2_CHANNEL.FTS_DESKEW_SEQ_ENABLE[1] 29_662 +GTP_CHANNEL_3.GTPE2_CHANNEL.FTS_DESKEW_SEQ_ENABLE[2] 28_663 +GTP_CHANNEL_3.GTPE2_CHANNEL.FTS_DESKEW_SEQ_ENABLE[3] 29_663 +GTP_CHANNEL_3.GTPE2_CHANNEL.FTS_LANE_DESKEW_CFG[0] 28_654 +GTP_CHANNEL_3.GTPE2_CHANNEL.FTS_LANE_DESKEW_CFG[1] 29_654 +GTP_CHANNEL_3.GTPE2_CHANNEL.FTS_LANE_DESKEW_CFG[2] 28_655 +GTP_CHANNEL_3.GTPE2_CHANNEL.FTS_LANE_DESKEW_CFG[3] 29_655 +GTP_CHANNEL_3.GTPE2_CHANNEL.FTS_LANE_DESKEW_EN 29_653 +GTP_CHANNEL_3.GTPE2_CHANNEL.GEARBOX_MODE[0] 28_224 +GTP_CHANNEL_3.GTPE2_CHANNEL.GEARBOX_MODE[1] 29_224 +GTP_CHANNEL_3.GTPE2_CHANNEL.GEARBOX_MODE[2] 28_225 +GTP_CHANNEL_3.GTPE2_CHANNEL.IN_USE 28_00 28_01 28_47 28_52 28_53 28_65 29_01 29_47 30_129 +GTP_CHANNEL_3.GTPE2_CHANNEL.INV_DMONITORCLK 30_13 +GTP_CHANNEL_3.GTPE2_CHANNEL.INV_DRPCLK 30_00 +GTP_CHANNEL_3.GTPE2_CHANNEL.INV_RXUSRCLK 31_01 +GTP_CHANNEL_3.GTPE2_CHANNEL.INV_SIGVALIDCLK 31_13 +GTP_CHANNEL_3.GTPE2_CHANNEL.INV_TXPHDLYTSTCLK 30_03 +GTP_CHANNEL_3.GTPE2_CHANNEL.INV_TXUSRCLK 31_04 +GTP_CHANNEL_3.GTPE2_CHANNEL.INV_CLKRSVD0 30_23 +GTP_CHANNEL_3.GTPE2_CHANNEL.INV_CLKRSVD1 31_23 +GTP_CHANNEL_3.GTPE2_CHANNEL.INV_RXUSRCLK2 30_02 +GTP_CHANNEL_3.GTPE2_CHANNEL.INV_TXUSRCLK2 30_05 +GTP_CHANNEL_3.GTPE2_CHANNEL.LOOPBACK_CFG[0] 30_20 +GTP_CHANNEL_3.GTPE2_CHANNEL.OUTREFCLK_SEL_INV[0] 28_149 +GTP_CHANNEL_3.GTPE2_CHANNEL.OUTREFCLK_SEL_INV[1] 29_149 +GTP_CHANNEL_3.GTPE2_CHANNEL.PCS_PCIE_EN 28_216 +GTP_CHANNEL_3.GTPE2_CHANNEL.PCS_RSVD_ATTR[0] 30_184 +GTP_CHANNEL_3.GTPE2_CHANNEL.PCS_RSVD_ATTR[1] 31_184 +GTP_CHANNEL_3.GTPE2_CHANNEL.PCS_RSVD_ATTR[2] 30_185 +GTP_CHANNEL_3.GTPE2_CHANNEL.PCS_RSVD_ATTR[3] 31_185 +GTP_CHANNEL_3.GTPE2_CHANNEL.PCS_RSVD_ATTR[4] 30_186 +GTP_CHANNEL_3.GTPE2_CHANNEL.PCS_RSVD_ATTR[5] 31_186 +GTP_CHANNEL_3.GTPE2_CHANNEL.PCS_RSVD_ATTR[6] 30_187 +GTP_CHANNEL_3.GTPE2_CHANNEL.PCS_RSVD_ATTR[7] 31_187 +GTP_CHANNEL_3.GTPE2_CHANNEL.PCS_RSVD_ATTR[8] 30_188 +GTP_CHANNEL_3.GTPE2_CHANNEL.PCS_RSVD_ATTR[9] 31_188 +GTP_CHANNEL_3.GTPE2_CHANNEL.PCS_RSVD_ATTR[10] 30_189 +GTP_CHANNEL_3.GTPE2_CHANNEL.PCS_RSVD_ATTR[11] 31_189 +GTP_CHANNEL_3.GTPE2_CHANNEL.PCS_RSVD_ATTR[12] 30_190 +GTP_CHANNEL_3.GTPE2_CHANNEL.PCS_RSVD_ATTR[13] 31_190 +GTP_CHANNEL_3.GTPE2_CHANNEL.PCS_RSVD_ATTR[14] 30_191 +GTP_CHANNEL_3.GTPE2_CHANNEL.PCS_RSVD_ATTR[15] 31_191 +GTP_CHANNEL_3.GTPE2_CHANNEL.PCS_RSVD_ATTR[16] 30_192 +GTP_CHANNEL_3.GTPE2_CHANNEL.PCS_RSVD_ATTR[17] 31_192 +GTP_CHANNEL_3.GTPE2_CHANNEL.PCS_RSVD_ATTR[18] 30_193 +GTP_CHANNEL_3.GTPE2_CHANNEL.PCS_RSVD_ATTR[19] 31_193 +GTP_CHANNEL_3.GTPE2_CHANNEL.PCS_RSVD_ATTR[20] 30_194 +GTP_CHANNEL_3.GTPE2_CHANNEL.PCS_RSVD_ATTR[21] 31_194 +GTP_CHANNEL_3.GTPE2_CHANNEL.PCS_RSVD_ATTR[22] 30_195 +GTP_CHANNEL_3.GTPE2_CHANNEL.PCS_RSVD_ATTR[23] 31_195 +GTP_CHANNEL_3.GTPE2_CHANNEL.PCS_RSVD_ATTR[24] 30_196 +GTP_CHANNEL_3.GTPE2_CHANNEL.PCS_RSVD_ATTR[25] 31_196 +GTP_CHANNEL_3.GTPE2_CHANNEL.PCS_RSVD_ATTR[26] 30_197 +GTP_CHANNEL_3.GTPE2_CHANNEL.PCS_RSVD_ATTR[27] 31_197 +GTP_CHANNEL_3.GTPE2_CHANNEL.PCS_RSVD_ATTR[28] 30_198 +GTP_CHANNEL_3.GTPE2_CHANNEL.PCS_RSVD_ATTR[29] 31_198 +GTP_CHANNEL_3.GTPE2_CHANNEL.PCS_RSVD_ATTR[30] 30_199 +GTP_CHANNEL_3.GTPE2_CHANNEL.PCS_RSVD_ATTR[31] 31_199 +GTP_CHANNEL_3.GTPE2_CHANNEL.PCS_RSVD_ATTR[32] 30_200 +GTP_CHANNEL_3.GTPE2_CHANNEL.PCS_RSVD_ATTR[33] 31_200 +GTP_CHANNEL_3.GTPE2_CHANNEL.PCS_RSVD_ATTR[34] 30_201 +GTP_CHANNEL_3.GTPE2_CHANNEL.PCS_RSVD_ATTR[35] 31_201 +GTP_CHANNEL_3.GTPE2_CHANNEL.PCS_RSVD_ATTR[36] 30_202 +GTP_CHANNEL_3.GTPE2_CHANNEL.PCS_RSVD_ATTR[37] 31_202 +GTP_CHANNEL_3.GTPE2_CHANNEL.PCS_RSVD_ATTR[38] 30_203 +GTP_CHANNEL_3.GTPE2_CHANNEL.PCS_RSVD_ATTR[39] 31_203 +GTP_CHANNEL_3.GTPE2_CHANNEL.PCS_RSVD_ATTR[40] 30_204 +GTP_CHANNEL_3.GTPE2_CHANNEL.PCS_RSVD_ATTR[41] 31_204 +GTP_CHANNEL_3.GTPE2_CHANNEL.PCS_RSVD_ATTR[42] 30_205 +GTP_CHANNEL_3.GTPE2_CHANNEL.PCS_RSVD_ATTR[43] 31_205 +GTP_CHANNEL_3.GTPE2_CHANNEL.PCS_RSVD_ATTR[44] 30_206 +GTP_CHANNEL_3.GTPE2_CHANNEL.PCS_RSVD_ATTR[45] 31_206 +GTP_CHANNEL_3.GTPE2_CHANNEL.PCS_RSVD_ATTR[46] 30_207 +GTP_CHANNEL_3.GTPE2_CHANNEL.PCS_RSVD_ATTR[47] 31_207 +GTP_CHANNEL_3.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[0] 29_216 +GTP_CHANNEL_3.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[1] 28_217 +GTP_CHANNEL_3.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[2] 29_217 +GTP_CHANNEL_3.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[3] 28_218 +GTP_CHANNEL_3.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[4] 29_218 +GTP_CHANNEL_3.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[5] 28_219 +GTP_CHANNEL_3.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[6] 29_219 +GTP_CHANNEL_3.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[7] 28_220 +GTP_CHANNEL_3.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[8] 29_220 +GTP_CHANNEL_3.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[9] 28_221 +GTP_CHANNEL_3.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[10] 29_221 +GTP_CHANNEL_3.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[11] 28_222 +GTP_CHANNEL_3.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[0] 28_208 +GTP_CHANNEL_3.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[1] 29_208 +GTP_CHANNEL_3.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[2] 28_209 +GTP_CHANNEL_3.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[3] 29_209 +GTP_CHANNEL_3.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[4] 28_210 +GTP_CHANNEL_3.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[5] 29_210 +GTP_CHANNEL_3.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[6] 28_211 +GTP_CHANNEL_3.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[7] 29_211 +GTP_CHANNEL_3.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[0] 28_212 +GTP_CHANNEL_3.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[1] 29_212 +GTP_CHANNEL_3.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[2] 28_213 +GTP_CHANNEL_3.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[3] 29_213 +GTP_CHANNEL_3.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[4] 28_214 +GTP_CHANNEL_3.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[5] 29_214 +GTP_CHANNEL_3.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[6] 28_215 +GTP_CHANNEL_3.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[7] 29_215 +GTP_CHANNEL_3.GTPE2_CHANNEL.PMA_LOOPBACK_CFG[0] 29_207 +GTP_CHANNEL_3.GTPE2_CHANNEL.PMA_RSV[0] 30_520 +GTP_CHANNEL_3.GTPE2_CHANNEL.PMA_RSV[1] 31_520 +GTP_CHANNEL_3.GTPE2_CHANNEL.PMA_RSV[2] 30_521 +GTP_CHANNEL_3.GTPE2_CHANNEL.PMA_RSV[3] 31_521 +GTP_CHANNEL_3.GTPE2_CHANNEL.PMA_RSV[4] 30_522 +GTP_CHANNEL_3.GTPE2_CHANNEL.PMA_RSV[5] 31_522 +GTP_CHANNEL_3.GTPE2_CHANNEL.PMA_RSV[6] 30_523 +GTP_CHANNEL_3.GTPE2_CHANNEL.PMA_RSV[7] 31_523 +GTP_CHANNEL_3.GTPE2_CHANNEL.PMA_RSV[8] 30_524 +GTP_CHANNEL_3.GTPE2_CHANNEL.PMA_RSV[9] 31_524 +GTP_CHANNEL_3.GTPE2_CHANNEL.PMA_RSV[10] 30_525 +GTP_CHANNEL_3.GTPE2_CHANNEL.PMA_RSV[11] 31_525 +GTP_CHANNEL_3.GTPE2_CHANNEL.PMA_RSV[12] 30_526 +GTP_CHANNEL_3.GTPE2_CHANNEL.PMA_RSV[13] 31_526 +GTP_CHANNEL_3.GTPE2_CHANNEL.PMA_RSV[14] 30_527 +GTP_CHANNEL_3.GTPE2_CHANNEL.PMA_RSV[15] 31_527 +GTP_CHANNEL_3.GTPE2_CHANNEL.PMA_RSV[16] 30_528 +GTP_CHANNEL_3.GTPE2_CHANNEL.PMA_RSV[17] 31_528 +GTP_CHANNEL_3.GTPE2_CHANNEL.PMA_RSV[18] 30_529 +GTP_CHANNEL_3.GTPE2_CHANNEL.PMA_RSV[19] 31_529 +GTP_CHANNEL_3.GTPE2_CHANNEL.PMA_RSV[20] 30_530 +GTP_CHANNEL_3.GTPE2_CHANNEL.PMA_RSV[21] 31_530 +GTP_CHANNEL_3.GTPE2_CHANNEL.PMA_RSV[22] 30_531 +GTP_CHANNEL_3.GTPE2_CHANNEL.PMA_RSV[23] 31_531 +GTP_CHANNEL_3.GTPE2_CHANNEL.PMA_RSV[24] 30_532 +GTP_CHANNEL_3.GTPE2_CHANNEL.PMA_RSV[25] 31_532 +GTP_CHANNEL_3.GTPE2_CHANNEL.PMA_RSV[26] 30_533 +GTP_CHANNEL_3.GTPE2_CHANNEL.PMA_RSV[27] 31_533 +GTP_CHANNEL_3.GTPE2_CHANNEL.PMA_RSV[28] 30_534 +GTP_CHANNEL_3.GTPE2_CHANNEL.PMA_RSV[29] 31_534 +GTP_CHANNEL_3.GTPE2_CHANNEL.PMA_RSV[30] 30_535 +GTP_CHANNEL_3.GTPE2_CHANNEL.PMA_RSV[31] 31_535 +GTP_CHANNEL_3.GTPE2_CHANNEL.PMA_RSV2[0] 30_336 +GTP_CHANNEL_3.GTPE2_CHANNEL.PMA_RSV2[1] 31_336 +GTP_CHANNEL_3.GTPE2_CHANNEL.PMA_RSV2[2] 30_337 +GTP_CHANNEL_3.GTPE2_CHANNEL.PMA_RSV2[3] 31_337 +GTP_CHANNEL_3.GTPE2_CHANNEL.PMA_RSV2[4] 30_338 +GTP_CHANNEL_3.GTPE2_CHANNEL.PMA_RSV2[5] 31_338 +GTP_CHANNEL_3.GTPE2_CHANNEL.PMA_RSV2[6] 30_339 +GTP_CHANNEL_3.GTPE2_CHANNEL.PMA_RSV2[7] 31_339 +GTP_CHANNEL_3.GTPE2_CHANNEL.PMA_RSV2[8] 30_340 +GTP_CHANNEL_3.GTPE2_CHANNEL.PMA_RSV2[9] 31_340 +GTP_CHANNEL_3.GTPE2_CHANNEL.PMA_RSV2[10] 30_341 +GTP_CHANNEL_3.GTPE2_CHANNEL.PMA_RSV2[11] 31_341 +GTP_CHANNEL_3.GTPE2_CHANNEL.PMA_RSV2[12] 30_342 +GTP_CHANNEL_3.GTPE2_CHANNEL.PMA_RSV2[13] 31_342 +GTP_CHANNEL_3.GTPE2_CHANNEL.PMA_RSV2[14] 30_343 +GTP_CHANNEL_3.GTPE2_CHANNEL.PMA_RSV2[15] 31_343 +GTP_CHANNEL_3.GTPE2_CHANNEL.PMA_RSV2[16] 30_344 +GTP_CHANNEL_3.GTPE2_CHANNEL.PMA_RSV2[17] 31_344 +GTP_CHANNEL_3.GTPE2_CHANNEL.PMA_RSV2[18] 30_345 +GTP_CHANNEL_3.GTPE2_CHANNEL.PMA_RSV2[19] 31_345 +GTP_CHANNEL_3.GTPE2_CHANNEL.PMA_RSV2[20] 30_346 +GTP_CHANNEL_3.GTPE2_CHANNEL.PMA_RSV2[21] 31_346 +GTP_CHANNEL_3.GTPE2_CHANNEL.PMA_RSV2[22] 30_347 +GTP_CHANNEL_3.GTPE2_CHANNEL.PMA_RSV2[23] 31_347 +GTP_CHANNEL_3.GTPE2_CHANNEL.PMA_RSV2[24] 30_348 +GTP_CHANNEL_3.GTPE2_CHANNEL.PMA_RSV2[25] 31_348 +GTP_CHANNEL_3.GTPE2_CHANNEL.PMA_RSV2[26] 30_349 +GTP_CHANNEL_3.GTPE2_CHANNEL.PMA_RSV2[27] 31_349 +GTP_CHANNEL_3.GTPE2_CHANNEL.PMA_RSV2[28] 30_350 +GTP_CHANNEL_3.GTPE2_CHANNEL.PMA_RSV2[29] 31_350 +GTP_CHANNEL_3.GTPE2_CHANNEL.PMA_RSV2[30] 30_351 +GTP_CHANNEL_3.GTPE2_CHANNEL.PMA_RSV2[31] 31_351 +GTP_CHANNEL_3.GTPE2_CHANNEL.PMA_RSV3[0] 30_288 +GTP_CHANNEL_3.GTPE2_CHANNEL.PMA_RSV3[1] 31_288 +GTP_CHANNEL_3.GTPE2_CHANNEL.PMA_RSV4[0] 30_156 +GTP_CHANNEL_3.GTPE2_CHANNEL.PMA_RSV4[1] 31_156 +GTP_CHANNEL_3.GTPE2_CHANNEL.PMA_RSV4[2] 30_157 +GTP_CHANNEL_3.GTPE2_CHANNEL.PMA_RSV4[3] 31_157 +GTP_CHANNEL_3.GTPE2_CHANNEL.PMA_RSV5[0] 31_159 +GTP_CHANNEL_3.GTPE2_CHANNEL.PMA_RSV6[0] 30_303 +GTP_CHANNEL_3.GTPE2_CHANNEL.PMA_RSV7[0] 31_303 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_BIAS_CFG[0] 30_112 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_BIAS_CFG[1] 31_112 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_BIAS_CFG[2] 30_113 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_BIAS_CFG[3] 31_113 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_BIAS_CFG[4] 30_114 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_BIAS_CFG[5] 31_114 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_BIAS_CFG[6] 30_115 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_BIAS_CFG[7] 31_115 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_BIAS_CFG[8] 30_116 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_BIAS_CFG[9] 31_116 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_BIAS_CFG[10] 30_117 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_BIAS_CFG[11] 31_117 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_BIAS_CFG[12] 30_118 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_BIAS_CFG[13] 31_118 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_BIAS_CFG[14] 30_119 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_BIAS_CFG[15] 31_119 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_BUFFER_CFG[0] 30_536 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_BUFFER_CFG[1] 31_536 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_BUFFER_CFG[2] 30_537 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_BUFFER_CFG[3] 31_537 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_BUFFER_CFG[4] 30_538 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_BUFFER_CFG[5] 31_538 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_CLKMUX_EN[0] 30_128 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_CM_SEL[0] 28_138 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_CM_SEL[1] 29_138 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_CM_TRIM[0] 30_304 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_CM_TRIM[1] 31_304 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_CM_TRIM[2] 30_305 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_CM_TRIM[3] 31_305 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_DATA_WIDTH[0] 29_141 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_DATA_WIDTH[1] 28_142 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_DATA_WIDTH[2] 29_142 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_DDI_SEL[0] 28_696 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_DDI_SEL[1] 29_696 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_DDI_SEL[2] 28_697 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_DDI_SEL[3] 29_697 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_DDI_SEL[4] 28_698 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_DDI_SEL[5] 29_698 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_DEBUG_CFG[0] 30_616 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_DEBUG_CFG[1] 31_616 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_DEBUG_CFG[2] 30_617 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_DEBUG_CFG[3] 31_617 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_DEBUG_CFG[4] 30_618 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_DEBUG_CFG[5] 31_618 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_DEBUG_CFG[6] 30_619 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_DEBUG_CFG[7] 31_619 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_DEBUG_CFG[8] 30_620 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_DEBUG_CFG[9] 31_620 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_DEBUG_CFG[10] 30_621 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_DEBUG_CFG[11] 31_621 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_DEBUG_CFG[12] 30_622 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_DEBUG_CFG[13] 31_622 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_DEFER_RESET_BUF_EN 30_552 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_DISPERR_SEQ_MATCH 29_495 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_OS_CFG[0] 28_288 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_OS_CFG[1] 29_288 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_OS_CFG[2] 28_289 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_OS_CFG[3] 29_289 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_OS_CFG[4] 28_290 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_OS_CFG[5] 29_290 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_OS_CFG[6] 28_291 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_OS_CFG[7] 29_291 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_OS_CFG[8] 28_292 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_OS_CFG[9] 29_292 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_OS_CFG[10] 28_293 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_OS_CFG[11] 29_293 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_OS_CFG[12] 28_294 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_SIG_VALID_DLY[0] 28_524 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_SIG_VALID_DLY[1] 29_524 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_SIG_VALID_DLY[2] 28_525 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_SIG_VALID_DLY[3] 29_525 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_SIG_VALID_DLY[4] 28_526 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_XCLK_SEL.RXUSR 28_143 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_CLK25_DIV[0] 28_139 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_CLK25_DIV[1] 29_139 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_CLK25_DIV[2] 28_140 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_CLK25_DIV[3] 29_140 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_CLK25_DIV[4] 28_141 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXBUF_ADDR_MODE.FAST 31_555 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXBUF_EIDLE_HI_CNT[0] 30_558 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXBUF_EIDLE_HI_CNT[1] 31_558 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXBUF_EIDLE_HI_CNT[2] 30_559 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXBUF_EIDLE_HI_CNT[3] 31_559 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXBUF_EIDLE_LO_CNT[0] 30_556 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXBUF_EIDLE_LO_CNT[1] 31_556 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXBUF_EIDLE_LO_CNT[2] 30_557 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXBUF_EIDLE_LO_CNT[3] 31_557 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXBUF_EN 30_11 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXBUF_RESET_ON_CB_CHANGE 30_560 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXBUF_RESET_ON_COMMAALIGN 30_561 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXBUF_RESET_ON_EIDLE 30_547 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXBUF_RESET_ON_RATE_CHANGE 31_560 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXBUF_THRESH_OVFLW[0] 31_552 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXBUF_THRESH_OVFLW[1] 30_553 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXBUF_THRESH_OVFLW[2] 31_553 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXBUF_THRESH_OVFLW[3] 30_554 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXBUF_THRESH_OVFLW[4] 31_554 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXBUF_THRESH_OVFLW[5] 30_555 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXBUF_THRESH_OVRD 30_548 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXBUF_THRESH_UNDFLW[0] 30_544 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXBUF_THRESH_UNDFLW[1] 31_544 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXBUF_THRESH_UNDFLW[2] 30_545 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXBUF_THRESH_UNDFLW[3] 31_545 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXBUF_THRESH_UNDFLW[4] 30_546 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXBUF_THRESH_UNDFLW[5] 31_546 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXBUFRESET_TIME[0] 29_101 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXBUFRESET_TIME[1] 28_102 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXBUFRESET_TIME[2] 29_102 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXBUFRESET_TIME[3] 28_103 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXBUFRESET_TIME[4] 29_103 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[0] 30_640 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[1] 31_640 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[2] 30_641 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[3] 31_641 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[4] 30_642 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[5] 31_642 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[6] 30_643 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[7] 31_643 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[8] 30_644 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[9] 31_644 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[10] 30_645 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[11] 31_645 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[12] 30_646 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[13] 31_646 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[14] 30_647 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[15] 31_647 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[16] 30_648 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[17] 31_648 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[18] 30_649 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[19] 31_649 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[20] 30_650 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[21] 31_650 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[22] 30_651 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[23] 31_651 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[24] 30_652 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[25] 31_652 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[26] 30_653 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[27] 31_653 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[28] 30_654 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[29] 31_654 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[30] 30_655 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[31] 31_655 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[32] 30_656 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[33] 31_656 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[34] 30_657 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[35] 31_657 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[36] 30_658 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[37] 31_658 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[38] 30_659 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[39] 31_659 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[40] 30_660 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[41] 31_660 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[42] 30_661 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[43] 31_661 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[44] 30_662 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[45] 31_662 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[46] 30_663 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[47] 31_663 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[48] 30_664 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[49] 31_664 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[50] 30_665 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[51] 31_665 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[52] 30_666 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[53] 31_666 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[54] 30_667 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[55] 31_667 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[56] 30_668 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[57] 31_668 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[58] 30_669 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[59] 31_669 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[60] 30_670 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[61] 31_670 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[62] 30_671 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[63] 31_671 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[64] 30_672 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[65] 31_672 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[66] 30_673 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[67] 31_673 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[68] 30_674 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[69] 31_674 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[70] 30_675 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[71] 31_675 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[72] 30_676 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[73] 31_676 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[74] 30_677 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[75] 31_677 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[76] 30_678 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[77] 31_678 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[78] 30_679 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[79] 31_679 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[80] 30_680 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[81] 31_680 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[82] 30_681 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_FR_RESET_ON_EIDLE[0] 30_638 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_HOLD_DURING_EIDLE[0] 31_637 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_LOCK_CFG[0] 30_632 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_LOCK_CFG[1] 31_632 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_LOCK_CFG[2] 30_633 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_LOCK_CFG[3] 31_633 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_LOCK_CFG[4] 30_634 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_LOCK_CFG[5] 31_634 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_PH_RESET_ON_EIDLE[0] 31_638 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDRFREQRESET_TIME[0] 29_106 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDRFREQRESET_TIME[1] 28_107 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDRFREQRESET_TIME[2] 29_107 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDRFREQRESET_TIME[3] 28_108 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDRFREQRESET_TIME[4] 29_108 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDRPHRESET_TIME[0] 28_109 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDRPHRESET_TIME[1] 29_109 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDRPHRESET_TIME[2] 28_110 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDRPHRESET_TIME[3] 29_110 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDRPHRESET_TIME[4] 28_111 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXDLY_CFG[0] 28_680 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXDLY_CFG[1] 29_680 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXDLY_CFG[2] 28_681 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXDLY_CFG[3] 29_681 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXDLY_CFG[4] 28_682 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXDLY_CFG[5] 29_682 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXDLY_CFG[6] 28_683 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXDLY_CFG[7] 29_683 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXDLY_CFG[8] 28_684 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXDLY_CFG[9] 29_684 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXDLY_CFG[10] 28_685 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXDLY_CFG[11] 29_685 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXDLY_CFG[12] 28_686 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXDLY_CFG[13] 29_686 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXDLY_CFG[14] 28_687 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXDLY_CFG[15] 29_687 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXDLY_LCFG[0] 30_576 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXDLY_LCFG[1] 31_576 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXDLY_LCFG[2] 30_577 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXDLY_LCFG[3] 31_577 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXDLY_LCFG[4] 30_578 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXDLY_LCFG[5] 31_578 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXDLY_LCFG[6] 30_579 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXDLY_LCFG[7] 31_579 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXDLY_LCFG[8] 30_580 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXDLY_TAP_CFG[0] 28_672 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXDLY_TAP_CFG[1] 29_672 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXDLY_TAP_CFG[2] 28_673 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXDLY_TAP_CFG[3] 29_673 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXDLY_TAP_CFG[4] 28_674 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXDLY_TAP_CFG[5] 29_674 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXDLY_TAP_CFG[6] 28_675 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXDLY_TAP_CFG[7] 29_675 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXDLY_TAP_CFG[8] 28_676 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXDLY_TAP_CFG[9] 29_676 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXDLY_TAP_CFG[10] 28_677 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXDLY_TAP_CFG[11] 29_677 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXDLY_TAP_CFG[12] 28_678 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXDLY_TAP_CFG[13] 29_678 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXDLY_TAP_CFG[14] 28_679 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXDLY_TAP_CFG[15] 29_679 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXGEARBOX_EN 29_607 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXISCANRESET_TIME[0] 29_123 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXISCANRESET_TIME[1] 28_124 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXISCANRESET_TIME[2] 29_124 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXISCANRESET_TIME[3] 28_125 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXISCANRESET_TIME[4] 29_125 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPM_BIAS_STARTUP_DISABLE[0] 31_391 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPM_CFG[0] 30_328 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPM_CFG[1] 31_328 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPM_CFG[2] 30_329 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPM_CFG[3] 31_329 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPM_CM_CFG[0] 30_430 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPM_GC_CFG[0] 30_432 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPM_GC_CFG[1] 31_432 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPM_GC_CFG[2] 30_433 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPM_GC_CFG[3] 31_433 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPM_GC_CFG[4] 30_434 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPM_GC_CFG[5] 31_434 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPM_GC_CFG[6] 30_435 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPM_GC_CFG[7] 31_435 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPM_GC_CFG[8] 30_436 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPM_GC_CFG2[0] 31_442 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPM_GC_CFG2[1] 30_443 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPM_GC_CFG2[2] 31_443 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPM_HF_CFG[0] 28_336 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPM_HF_CFG[1] 29_336 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPM_HF_CFG[2] 28_337 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPM_HF_CFG[3] 29_337 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPM_HF_CFG[4] 28_338 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPM_HF_CFG[5] 29_338 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPM_HF_CFG[6] 28_339 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPM_HF_CFG[7] 29_339 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPM_HF_CFG[8] 28_340 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPM_HF_CFG[9] 29_340 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPM_HF_CFG[10] 28_341 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPM_HF_CFG[11] 29_341 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPM_HF_CFG[12] 28_342 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPM_HF_CFG[13] 29_342 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPM_HF_CFG2[0] 30_424 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPM_HF_CFG2[1] 31_424 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPM_HF_CFG2[2] 30_425 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPM_HF_CFG2[3] 31_425 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPM_HF_CFG2[4] 30_426 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPM_HF_CFG3[0] 31_389 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPM_HF_CFG3[1] 30_390 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPM_HF_CFG3[2] 31_390 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPM_HF_CFG3[3] 30_391 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPM_HOLD_DURING_EIDLE[0] 28_247 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPM_INCM_CFG[0] 30_439 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPM_IPCM_CFG[0] 31_439 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPM_LF_CFG[0] 28_344 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPM_LF_CFG[1] 29_344 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPM_LF_CFG[2] 28_345 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPM_LF_CFG[3] 29_345 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPM_LF_CFG[4] 28_346 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPM_LF_CFG[5] 29_346 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPM_LF_CFG[6] 28_347 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPM_LF_CFG[7] 29_347 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPM_LF_CFG[8] 28_348 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPM_LF_CFG[9] 29_348 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPM_LF_CFG[10] 28_349 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPM_LF_CFG[11] 29_349 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPM_LF_CFG[12] 28_350 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPM_LF_CFG[13] 29_350 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPM_LF_CFG[14] 28_351 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPM_LF_CFG[15] 29_351 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPM_LF_CFG[16] 28_343 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPM_LF_CFG[17] 29_343 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPM_LF_CFG2[0] 31_426 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPM_LF_CFG2[1] 30_427 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPM_LF_CFG2[2] 31_427 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPM_LF_CFG2[3] 30_428 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPM_LF_CFG2[4] 31_428 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPM_OSINT_CFG[0] 30_440 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPM_OSINT_CFG[1] 31_440 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPM_OSINT_CFG[2] 30_441 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPM_CFG1[0] 30_330 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPMRESET_TIME[0] 28_112 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPMRESET_TIME[1] 29_112 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPMRESET_TIME[2] 28_113 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPMRESET_TIME[3] 29_113 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPMRESET_TIME[4] 28_114 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPMRESET_TIME[5] 29_114 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPMRESET_TIME[6] 28_115 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXOOB_CFG[0] 28_144 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXOOB_CFG[1] 29_144 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXOOB_CFG[2] 28_145 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXOOB_CFG[3] 29_145 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXOOB_CFG[4] 28_146 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXOOB_CFG[5] 29_146 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXOOB_CFG[6] 28_147 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXOOB_CLK_CFG.FABRIC 31_129 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXOSCALRESET_TIME[0] 28_187 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXOSCALRESET_TIME[1] 29_187 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXOSCALRESET_TIME[2] 28_188 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXOSCALRESET_TIME[3] 29_188 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXOSCALRESET_TIME[4] 28_189 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXOSCALRESET_TIMEOUT[0] 29_189 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXOSCALRESET_TIMEOUT[1] 28_190 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXOSCALRESET_TIMEOUT[2] 29_190 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXOSCALRESET_TIMEOUT[3] 28_191 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXOSCALRESET_TIMEOUT[4] 29_191 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXOUT_DIV[0] 30_384 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXOUT_DIV[1] 31_384 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXPCSRESET_TIME[0] 29_115 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXPCSRESET_TIME[1] 28_116 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXPCSRESET_TIME[2] 29_116 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXPCSRESET_TIME[3] 28_117 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXPCSRESET_TIME[4] 29_117 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXPH_CFG[0] 30_584 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXPH_CFG[1] 31_584 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXPH_CFG[2] 30_585 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXPH_CFG[3] 31_585 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXPH_CFG[4] 30_586 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXPH_CFG[5] 31_586 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXPH_CFG[6] 30_587 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXPH_CFG[7] 31_587 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXPH_CFG[8] 30_588 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXPH_CFG[9] 31_588 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXPH_CFG[10] 30_589 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXPH_CFG[11] 31_589 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXPH_CFG[12] 30_590 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXPH_CFG[13] 31_590 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXPH_CFG[14] 30_591 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXPH_CFG[15] 31_591 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXPH_CFG[16] 30_592 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXPH_CFG[17] 31_592 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXPH_CFG[18] 30_593 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXPH_CFG[19] 31_593 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXPH_CFG[20] 30_594 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXPH_CFG[21] 31_594 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXPH_CFG[22] 30_595 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXPH_CFG[23] 31_595 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXPH_MONITOR_SEL[0] 28_700 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXPH_MONITOR_SEL[1] 29_700 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXPH_MONITOR_SEL[2] 28_701 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXPH_MONITOR_SEL[3] 29_701 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXPH_MONITOR_SEL[4] 28_702 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXPHDLY_CFG[0] 30_600 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXPHDLY_CFG[1] 31_600 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXPHDLY_CFG[2] 30_601 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXPHDLY_CFG[3] 31_601 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXPHDLY_CFG[4] 30_602 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXPHDLY_CFG[5] 31_602 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXPHDLY_CFG[6] 30_603 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXPHDLY_CFG[7] 31_603 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXPHDLY_CFG[8] 30_604 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXPHDLY_CFG[9] 31_604 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXPHDLY_CFG[10] 30_605 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXPHDLY_CFG[11] 31_605 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXPHDLY_CFG[12] 30_606 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXPHDLY_CFG[13] 31_606 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXPHDLY_CFG[14] 30_607 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXPHDLY_CFG[15] 31_607 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXPHDLY_CFG[16] 30_608 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXPHDLY_CFG[17] 31_608 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXPHDLY_CFG[18] 30_609 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXPHDLY_CFG[19] 31_609 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXPHDLY_CFG[20] 30_610 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXPHDLY_CFG[21] 31_610 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXPHDLY_CFG[22] 30_611 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXPHDLY_CFG[23] 31_611 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXPI_CFG0[0] 31_430 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXPI_CFG0[1] 30_431 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXPI_CFG0[2] 31_431 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXPI_CFG1[0] 30_442 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXPI_CFG2[0] 31_441 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXPMARESET_TIME[0] 28_104 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXPMARESET_TIME[1] 29_104 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXPMARESET_TIME[2] 28_105 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXPMARESET_TIME[3] 29_105 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXPMARESET_TIME[4] 28_106 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXPRBS_ERR_LOOPBACK[0] 28_136 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXSLIDE_AUTO_WAIT[0] 28_520 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXSLIDE_AUTO_WAIT[1] 29_520 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXSLIDE_AUTO_WAIT[2] 28_521 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXSLIDE_AUTO_WAIT[3] 29_521 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXSLIDE_MODE.AUTO 28_519 !29_519 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXSLIDE_MODE.PCS !28_519 29_519 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXSLIDE_MODE.PMA 28_519 29_519 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXSYNC_MULTILANE[0] 28_133 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXSYNC_OVRD[0] 29_135 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXSYNC_SKIP_DA[0] 29_134 +GTP_CHANNEL_3.GTPE2_CHANNEL.SAS_MAX_COM[0] 28_171 +GTP_CHANNEL_3.GTPE2_CHANNEL.SAS_MAX_COM[1] 29_171 +GTP_CHANNEL_3.GTPE2_CHANNEL.SAS_MAX_COM[2] 28_172 +GTP_CHANNEL_3.GTPE2_CHANNEL.SAS_MAX_COM[3] 29_172 +GTP_CHANNEL_3.GTPE2_CHANNEL.SAS_MAX_COM[4] 28_173 +GTP_CHANNEL_3.GTPE2_CHANNEL.SAS_MAX_COM[5] 29_173 +GTP_CHANNEL_3.GTPE2_CHANNEL.SAS_MAX_COM[6] 28_174 +GTP_CHANNEL_3.GTPE2_CHANNEL.SAS_MIN_COM[0] 29_156 +GTP_CHANNEL_3.GTPE2_CHANNEL.SAS_MIN_COM[1] 28_157 +GTP_CHANNEL_3.GTPE2_CHANNEL.SAS_MIN_COM[2] 29_157 +GTP_CHANNEL_3.GTPE2_CHANNEL.SAS_MIN_COM[3] 28_158 +GTP_CHANNEL_3.GTPE2_CHANNEL.SAS_MIN_COM[4] 29_158 +GTP_CHANNEL_3.GTPE2_CHANNEL.SAS_MIN_COM[5] 28_159 +GTP_CHANNEL_3.GTPE2_CHANNEL.SATA_BURST_SEQ_LEN[0] 28_150 +GTP_CHANNEL_3.GTPE2_CHANNEL.SATA_BURST_SEQ_LEN[1] 29_150 +GTP_CHANNEL_3.GTPE2_CHANNEL.SATA_BURST_SEQ_LEN[2] 28_151 +GTP_CHANNEL_3.GTPE2_CHANNEL.SATA_BURST_SEQ_LEN[3] 29_151 +GTP_CHANNEL_3.GTPE2_CHANNEL.SATA_BURST_VAL[0] 29_147 +GTP_CHANNEL_3.GTPE2_CHANNEL.SATA_BURST_VAL[1] 28_148 +GTP_CHANNEL_3.GTPE2_CHANNEL.SATA_BURST_VAL[2] 29_148 +GTP_CHANNEL_3.GTPE2_CHANNEL.SATA_EIDLE_VAL[0] 28_152 +GTP_CHANNEL_3.GTPE2_CHANNEL.SATA_EIDLE_VAL[1] 29_152 +GTP_CHANNEL_3.GTPE2_CHANNEL.SATA_EIDLE_VAL[2] 28_153 +GTP_CHANNEL_3.GTPE2_CHANNEL.SATA_MAX_BURST[0] 28_168 +GTP_CHANNEL_3.GTPE2_CHANNEL.SATA_MAX_BURST[1] 29_168 +GTP_CHANNEL_3.GTPE2_CHANNEL.SATA_MAX_BURST[2] 28_169 +GTP_CHANNEL_3.GTPE2_CHANNEL.SATA_MAX_BURST[3] 29_169 +GTP_CHANNEL_3.GTPE2_CHANNEL.SATA_MAX_BURST[4] 28_170 +GTP_CHANNEL_3.GTPE2_CHANNEL.SATA_MAX_BURST[5] 29_170 +GTP_CHANNEL_3.GTPE2_CHANNEL.SATA_MAX_INIT[0] 28_176 +GTP_CHANNEL_3.GTPE2_CHANNEL.SATA_MAX_INIT[1] 29_176 +GTP_CHANNEL_3.GTPE2_CHANNEL.SATA_MAX_INIT[2] 28_177 +GTP_CHANNEL_3.GTPE2_CHANNEL.SATA_MAX_INIT[3] 29_177 +GTP_CHANNEL_3.GTPE2_CHANNEL.SATA_MAX_INIT[4] 28_178 +GTP_CHANNEL_3.GTPE2_CHANNEL.SATA_MAX_INIT[5] 29_178 +GTP_CHANNEL_3.GTPE2_CHANNEL.SATA_MAX_WAKE[0] 28_179 +GTP_CHANNEL_3.GTPE2_CHANNEL.SATA_MAX_WAKE[1] 29_179 +GTP_CHANNEL_3.GTPE2_CHANNEL.SATA_MAX_WAKE[2] 28_180 +GTP_CHANNEL_3.GTPE2_CHANNEL.SATA_MAX_WAKE[3] 29_180 +GTP_CHANNEL_3.GTPE2_CHANNEL.SATA_MAX_WAKE[4] 28_181 +GTP_CHANNEL_3.GTPE2_CHANNEL.SATA_MAX_WAKE[5] 29_181 +GTP_CHANNEL_3.GTPE2_CHANNEL.SATA_MIN_BURST[0] 29_153 +GTP_CHANNEL_3.GTPE2_CHANNEL.SATA_MIN_BURST[1] 28_154 +GTP_CHANNEL_3.GTPE2_CHANNEL.SATA_MIN_BURST[2] 29_154 +GTP_CHANNEL_3.GTPE2_CHANNEL.SATA_MIN_BURST[3] 28_155 +GTP_CHANNEL_3.GTPE2_CHANNEL.SATA_MIN_BURST[4] 29_155 +GTP_CHANNEL_3.GTPE2_CHANNEL.SATA_MIN_BURST[5] 28_156 +GTP_CHANNEL_3.GTPE2_CHANNEL.SATA_MIN_INIT[0] 28_160 +GTP_CHANNEL_3.GTPE2_CHANNEL.SATA_MIN_INIT[1] 29_160 +GTP_CHANNEL_3.GTPE2_CHANNEL.SATA_MIN_INIT[2] 28_161 +GTP_CHANNEL_3.GTPE2_CHANNEL.SATA_MIN_INIT[3] 29_161 +GTP_CHANNEL_3.GTPE2_CHANNEL.SATA_MIN_INIT[4] 28_162 +GTP_CHANNEL_3.GTPE2_CHANNEL.SATA_MIN_INIT[5] 29_162 +GTP_CHANNEL_3.GTPE2_CHANNEL.SATA_MIN_WAKE[0] 28_163 +GTP_CHANNEL_3.GTPE2_CHANNEL.SATA_MIN_WAKE[1] 29_163 +GTP_CHANNEL_3.GTPE2_CHANNEL.SATA_MIN_WAKE[2] 28_164 +GTP_CHANNEL_3.GTPE2_CHANNEL.SATA_MIN_WAKE[3] 29_164 +GTP_CHANNEL_3.GTPE2_CHANNEL.SATA_MIN_WAKE[4] 28_165 +GTP_CHANNEL_3.GTPE2_CHANNEL.SATA_MIN_WAKE[5] 29_165 +GTP_CHANNEL_3.GTPE2_CHANNEL.SATA_PLL_CFG.VCO_1500MHZ 30_55 +GTP_CHANNEL_3.GTPE2_CHANNEL.SATA_PLL_CFG.VCO_750MHZ 31_55 +GTP_CHANNEL_3.GTPE2_CHANNEL.SHOW_REALIGN_COMMA 29_522 +GTP_CHANNEL_3.GTPE2_CHANNEL.TERM_RCAL_CFG[0] 30_136 +GTP_CHANNEL_3.GTPE2_CHANNEL.TERM_RCAL_CFG[1] 31_136 +GTP_CHANNEL_3.GTPE2_CHANNEL.TERM_RCAL_CFG[2] 30_137 +GTP_CHANNEL_3.GTPE2_CHANNEL.TERM_RCAL_CFG[3] 31_137 +GTP_CHANNEL_3.GTPE2_CHANNEL.TERM_RCAL_CFG[4] 30_138 +GTP_CHANNEL_3.GTPE2_CHANNEL.TERM_RCAL_CFG[5] 31_138 +GTP_CHANNEL_3.GTPE2_CHANNEL.TERM_RCAL_CFG[6] 30_139 +GTP_CHANNEL_3.GTPE2_CHANNEL.TERM_RCAL_CFG[7] 31_139 +GTP_CHANNEL_3.GTPE2_CHANNEL.TERM_RCAL_CFG[8] 30_140 +GTP_CHANNEL_3.GTPE2_CHANNEL.TERM_RCAL_CFG[9] 31_140 +GTP_CHANNEL_3.GTPE2_CHANNEL.TERM_RCAL_CFG[10] 30_141 +GTP_CHANNEL_3.GTPE2_CHANNEL.TERM_RCAL_CFG[11] 31_141 +GTP_CHANNEL_3.GTPE2_CHANNEL.TERM_RCAL_CFG[12] 30_142 +GTP_CHANNEL_3.GTPE2_CHANNEL.TERM_RCAL_CFG[13] 31_142 +GTP_CHANNEL_3.GTPE2_CHANNEL.TERM_RCAL_CFG[14] 30_143 +GTP_CHANNEL_3.GTPE2_CHANNEL.TERM_RCAL_OVRD[0] 31_150 +GTP_CHANNEL_3.GTPE2_CHANNEL.TERM_RCAL_OVRD[1] 30_151 +GTP_CHANNEL_3.GTPE2_CHANNEL.TERM_RCAL_OVRD[2] 31_151 +GTP_CHANNEL_3.GTPE2_CHANNEL.TRANS_TIME_RATE[0] 28_192 +GTP_CHANNEL_3.GTPE2_CHANNEL.TRANS_TIME_RATE[1] 29_192 +GTP_CHANNEL_3.GTPE2_CHANNEL.TRANS_TIME_RATE[2] 28_193 +GTP_CHANNEL_3.GTPE2_CHANNEL.TRANS_TIME_RATE[3] 29_193 +GTP_CHANNEL_3.GTPE2_CHANNEL.TRANS_TIME_RATE[4] 28_194 +GTP_CHANNEL_3.GTPE2_CHANNEL.TRANS_TIME_RATE[5] 29_194 +GTP_CHANNEL_3.GTPE2_CHANNEL.TRANS_TIME_RATE[6] 28_195 +GTP_CHANNEL_3.GTPE2_CHANNEL.TRANS_TIME_RATE[7] 29_195 +GTP_CHANNEL_3.GTPE2_CHANNEL.TST_RSV[0] 30_504 +GTP_CHANNEL_3.GTPE2_CHANNEL.TST_RSV[1] 31_504 +GTP_CHANNEL_3.GTPE2_CHANNEL.TST_RSV[2] 30_505 +GTP_CHANNEL_3.GTPE2_CHANNEL.TST_RSV[3] 31_505 +GTP_CHANNEL_3.GTPE2_CHANNEL.TST_RSV[4] 30_506 +GTP_CHANNEL_3.GTPE2_CHANNEL.TST_RSV[5] 31_506 +GTP_CHANNEL_3.GTPE2_CHANNEL.TST_RSV[6] 30_507 +GTP_CHANNEL_3.GTPE2_CHANNEL.TST_RSV[7] 31_507 +GTP_CHANNEL_3.GTPE2_CHANNEL.TST_RSV[8] 30_508 +GTP_CHANNEL_3.GTPE2_CHANNEL.TST_RSV[9] 31_508 +GTP_CHANNEL_3.GTPE2_CHANNEL.TST_RSV[10] 30_509 +GTP_CHANNEL_3.GTPE2_CHANNEL.TST_RSV[11] 31_509 +GTP_CHANNEL_3.GTPE2_CHANNEL.TST_RSV[12] 30_510 +GTP_CHANNEL_3.GTPE2_CHANNEL.TST_RSV[13] 31_510 +GTP_CHANNEL_3.GTPE2_CHANNEL.TST_RSV[14] 30_511 +GTP_CHANNEL_3.GTPE2_CHANNEL.TST_RSV[15] 31_511 +GTP_CHANNEL_3.GTPE2_CHANNEL.TST_RSV[16] 30_512 +GTP_CHANNEL_3.GTPE2_CHANNEL.TST_RSV[17] 31_512 +GTP_CHANNEL_3.GTPE2_CHANNEL.TST_RSV[18] 30_513 +GTP_CHANNEL_3.GTPE2_CHANNEL.TST_RSV[19] 31_513 +GTP_CHANNEL_3.GTPE2_CHANNEL.TST_RSV[20] 30_514 +GTP_CHANNEL_3.GTPE2_CHANNEL.TST_RSV[21] 31_514 +GTP_CHANNEL_3.GTPE2_CHANNEL.TST_RSV[22] 30_515 +GTP_CHANNEL_3.GTPE2_CHANNEL.TST_RSV[23] 31_515 +GTP_CHANNEL_3.GTPE2_CHANNEL.TST_RSV[24] 30_516 +GTP_CHANNEL_3.GTPE2_CHANNEL.TST_RSV[25] 31_516 +GTP_CHANNEL_3.GTPE2_CHANNEL.TST_RSV[26] 30_517 +GTP_CHANNEL_3.GTPE2_CHANNEL.TST_RSV[27] 31_517 +GTP_CHANNEL_3.GTPE2_CHANNEL.TST_RSV[28] 30_518 +GTP_CHANNEL_3.GTPE2_CHANNEL.TST_RSV[29] 31_518 +GTP_CHANNEL_3.GTPE2_CHANNEL.TST_RSV[30] 30_519 +GTP_CHANNEL_3.GTPE2_CHANNEL.TST_RSV[31] 31_519 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_CLKMUX_EN[0] 31_128 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_DATA_WIDTH[0] 30_152 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_DATA_WIDTH[1] 31_152 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_DATA_WIDTH[2] 30_153 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_DRIVE_MODE.PIPE 28_200 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_EIDLE_ASSERT_DELAY[0] 28_203 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_EIDLE_ASSERT_DELAY[1] 29_203 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_EIDLE_ASSERT_DELAY[2] 28_204 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_EIDLE_DEASSERT_DELAY[0] 29_204 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_EIDLE_DEASSERT_DELAY[1] 28_205 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_EIDLE_DEASSERT_DELAY[2] 29_205 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_LOOPBACK_DRIVE_HIZ 29_202 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_MAINCURSOR_SEL[0] 31_289 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_MARGIN_FULL_0[0] 30_232 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_MARGIN_FULL_0[1] 31_232 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_MARGIN_FULL_0[2] 30_233 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_MARGIN_FULL_0[3] 31_233 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_MARGIN_FULL_0[4] 30_234 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_MARGIN_FULL_0[5] 31_234 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_MARGIN_FULL_0[6] 30_235 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_MARGIN_FULL_1[0] 30_236 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_MARGIN_FULL_1[1] 31_236 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_MARGIN_FULL_1[2] 30_237 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_MARGIN_FULL_1[3] 31_237 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_MARGIN_FULL_1[4] 30_238 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_MARGIN_FULL_1[5] 31_238 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_MARGIN_FULL_1[6] 30_239 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_MARGIN_FULL_2[0] 30_240 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_MARGIN_FULL_2[1] 31_240 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_MARGIN_FULL_2[2] 30_241 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_MARGIN_FULL_2[3] 31_241 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_MARGIN_FULL_2[4] 30_242 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_MARGIN_FULL_2[5] 31_242 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_MARGIN_FULL_2[6] 30_243 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_MARGIN_FULL_3[0] 30_244 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_MARGIN_FULL_3[1] 31_244 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_MARGIN_FULL_3[2] 30_245 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_MARGIN_FULL_3[3] 31_245 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_MARGIN_FULL_3[4] 30_246 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_MARGIN_FULL_3[5] 31_246 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_MARGIN_FULL_3[6] 30_247 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_MARGIN_FULL_4[0] 30_248 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_MARGIN_FULL_4[1] 31_248 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_MARGIN_FULL_4[2] 30_249 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_MARGIN_FULL_4[3] 31_249 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_MARGIN_FULL_4[4] 30_250 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_MARGIN_FULL_4[5] 31_250 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_MARGIN_FULL_4[6] 30_251 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_MARGIN_LOW_0[0] 30_252 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_MARGIN_LOW_0[1] 31_252 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_MARGIN_LOW_0[2] 30_253 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_MARGIN_LOW_0[3] 31_253 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_MARGIN_LOW_0[4] 30_254 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_MARGIN_LOW_0[5] 31_254 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_MARGIN_LOW_0[6] 30_255 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_MARGIN_LOW_1[0] 30_256 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_MARGIN_LOW_1[1] 31_256 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_MARGIN_LOW_1[2] 30_257 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_MARGIN_LOW_1[3] 31_257 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_MARGIN_LOW_1[4] 30_258 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_MARGIN_LOW_1[5] 31_258 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_MARGIN_LOW_1[6] 30_259 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_MARGIN_LOW_2[0] 30_260 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_MARGIN_LOW_2[1] 31_260 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_MARGIN_LOW_2[2] 30_261 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_MARGIN_LOW_2[3] 31_261 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_MARGIN_LOW_2[4] 30_262 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_MARGIN_LOW_2[5] 31_262 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_MARGIN_LOW_2[6] 30_263 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_MARGIN_LOW_3[0] 30_264 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_MARGIN_LOW_3[1] 31_264 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_MARGIN_LOW_3[2] 30_265 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_MARGIN_LOW_3[3] 31_265 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_MARGIN_LOW_3[4] 30_266 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_MARGIN_LOW_3[5] 31_266 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_MARGIN_LOW_3[6] 30_267 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_MARGIN_LOW_4[0] 30_268 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_MARGIN_LOW_4[1] 31_268 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_MARGIN_LOW_4[2] 30_269 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_MARGIN_LOW_4[3] 31_269 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_MARGIN_LOW_4[4] 30_270 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_MARGIN_LOW_4[5] 31_270 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_MARGIN_LOW_4[6] 30_271 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_PREDRIVER_MODE[0] 28_206 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_RXDETECT_CFG[0] 30_296 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_RXDETECT_CFG[1] 31_296 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_RXDETECT_CFG[2] 30_297 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_RXDETECT_CFG[3] 31_297 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_RXDETECT_CFG[4] 30_298 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_RXDETECT_CFG[5] 31_298 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_RXDETECT_CFG[6] 30_299 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_RXDETECT_CFG[7] 31_299 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_RXDETECT_CFG[8] 30_300 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_RXDETECT_CFG[9] 31_300 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_RXDETECT_CFG[10] 30_301 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_RXDETECT_CFG[11] 31_301 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_RXDETECT_CFG[12] 30_302 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_RXDETECT_CFG[13] 31_302 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_RXDETECT_REF[0] 30_292 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_RXDETECT_REF[1] 31_292 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_RXDETECT_REF[2] 30_293 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_XCLK_SEL.TXUSR 31_11 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_CLK25_DIV[0] 30_144 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_CLK25_DIV[1] 31_144 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_CLK25_DIV[2] 30_145 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_CLK25_DIV[3] 31_145 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_CLK25_DIV[4] 30_146 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_DEEMPH0[0] 30_272 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_DEEMPH0[1] 31_272 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_DEEMPH0[2] 30_273 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_DEEMPH0[3] 31_273 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_DEEMPH0[4] 30_274 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_DEEMPH0[5] 31_274 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_DEEMPH1[0] 30_276 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_DEEMPH1[1] 31_276 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_DEEMPH1[2] 30_277 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_DEEMPH1[3] 31_277 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_DEEMPH1[4] 30_278 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_DEEMPH1[5] 31_278 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXBUF_EN 28_231 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXBUF_RESET_ON_RATE_CHANGE 29_231 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXDLY_CFG[0] 30_80 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXDLY_CFG[1] 31_80 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXDLY_CFG[2] 30_81 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXDLY_CFG[3] 31_81 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXDLY_CFG[4] 30_82 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXDLY_CFG[5] 31_82 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXDLY_CFG[6] 30_83 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXDLY_CFG[7] 31_83 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXDLY_CFG[8] 30_84 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXDLY_CFG[9] 31_84 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXDLY_CFG[10] 30_85 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXDLY_CFG[11] 31_85 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXDLY_CFG[12] 30_86 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXDLY_CFG[13] 31_86 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXDLY_CFG[14] 30_87 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXDLY_CFG[15] 31_87 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXDLY_LCFG[0] 30_568 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXDLY_LCFG[1] 31_568 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXDLY_LCFG[2] 30_569 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXDLY_LCFG[3] 31_569 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXDLY_LCFG[4] 30_570 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXDLY_LCFG[5] 31_570 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXDLY_LCFG[6] 30_571 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXDLY_LCFG[7] 31_571 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXDLY_LCFG[8] 30_572 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXDLY_TAP_CFG[0] 30_88 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXDLY_TAP_CFG[1] 31_88 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXDLY_TAP_CFG[2] 30_89 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXDLY_TAP_CFG[3] 31_89 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXDLY_TAP_CFG[4] 30_90 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXDLY_TAP_CFG[5] 31_90 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXDLY_TAP_CFG[6] 30_91 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXDLY_TAP_CFG[7] 31_91 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXDLY_TAP_CFG[8] 30_92 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXDLY_TAP_CFG[9] 31_92 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXDLY_TAP_CFG[10] 30_93 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXDLY_TAP_CFG[11] 31_93 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXDLY_TAP_CFG[12] 30_94 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXDLY_TAP_CFG[13] 31_94 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXDLY_TAP_CFG[14] 30_95 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXDLY_TAP_CFG[15] 31_95 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXGEARBOX_EN 29_226 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXOOB_CFG[0] 31_20 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXOUT_DIV[0] 30_386 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXOUT_DIV[1] 31_386 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPCSRESET_TIME[0] 29_130 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPCSRESET_TIME[1] 28_131 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPCSRESET_TIME[2] 29_131 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPCSRESET_TIME[3] 28_132 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPCSRESET_TIME[4] 29_132 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPH_CFG[0] 30_96 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPH_CFG[1] 31_96 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPH_CFG[2] 30_97 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPH_CFG[3] 31_97 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPH_CFG[4] 30_98 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPH_CFG[5] 31_98 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPH_CFG[6] 30_99 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPH_CFG[7] 31_99 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPH_CFG[8] 30_100 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPH_CFG[9] 31_100 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPH_CFG[10] 30_101 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPH_CFG[11] 31_101 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPH_CFG[12] 30_102 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPH_CFG[13] 31_102 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPH_CFG[14] 30_103 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPH_CFG[15] 31_103 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPH_MONITOR_SEL[0] 30_108 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPH_MONITOR_SEL[1] 31_108 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPH_MONITOR_SEL[2] 30_109 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPH_MONITOR_SEL[3] 31_109 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPH_MONITOR_SEL[4] 30_110 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPHDLY_CFG[0] 30_64 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPHDLY_CFG[1] 31_64 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPHDLY_CFG[2] 30_65 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPHDLY_CFG[3] 31_65 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPHDLY_CFG[4] 30_66 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPHDLY_CFG[5] 31_66 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPHDLY_CFG[6] 30_67 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPHDLY_CFG[7] 31_67 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPHDLY_CFG[8] 30_68 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPHDLY_CFG[9] 31_68 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPHDLY_CFG[10] 30_69 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPHDLY_CFG[11] 31_69 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPHDLY_CFG[12] 30_70 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPHDLY_CFG[13] 31_70 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPHDLY_CFG[14] 30_71 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPHDLY_CFG[15] 31_71 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPHDLY_CFG[16] 30_72 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPHDLY_CFG[17] 31_72 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPHDLY_CFG[18] 30_73 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPHDLY_CFG[19] 31_73 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPHDLY_CFG[20] 30_74 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPHDLY_CFG[21] 31_74 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPHDLY_CFG[22] 30_75 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPHDLY_CFG[23] 31_75 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPI_GREY_SEL[0] 31_498 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPI_INVSTROBE_SEL[0] 30_498 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPI_PPM_CFG[0] 30_488 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPI_PPM_CFG[1] 31_488 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPI_PPM_CFG[2] 30_489 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPI_PPM_CFG[3] 31_489 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPI_PPM_CFG[4] 30_490 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPI_PPM_CFG[5] 31_490 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPI_PPM_CFG[6] 30_491 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPI_PPM_CFG[7] 31_491 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPI_PPMCLK_SEL.TXUSRCLK2 31_497 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPI_SYNFREQ_PPM[0] 30_496 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPI_SYNFREQ_PPM[1] 31_496 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPI_SYNFREQ_PPM[2] 30_497 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPI_CFG0[0] 30_40 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPI_CFG0[1] 31_40 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPI_CFG1[0] 30_41 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPI_CFG1[1] 31_41 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPI_CFG2[0] 30_42 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPI_CFG2[1] 31_42 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPI_CFG3[0] 30_43 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPI_CFG4[0] 31_43 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPI_CFG5[0] 30_44 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPI_CFG5[1] 31_44 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPI_CFG5[2] 30_45 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPMARESET_TIME[0] 28_128 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPMARESET_TIME[1] 29_128 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPMARESET_TIME[2] 28_129 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPMARESET_TIME[3] 29_129 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPMARESET_TIME[4] 28_130 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXSYNC_MULTILANE[0] 29_133 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXSYNC_OVRD[0] 28_135 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXSYNC_SKIP_DA[0] 28_134 +GTP_CHANNEL_3.GTPE2_CHANNEL.UCODEER_CLR[0] 29_00 +GTP_CHANNEL_3.GTPE2_CHANNEL.USE_PCS_CLK_PHASE_SEL[0] 30_463 diff --git a/artix7/segbits_gtp_channel_3.origin_info.db b/artix7/segbits_gtp_channel_3.origin_info.db index 2450283..1cd90b1 100644 --- a/artix7/segbits_gtp_channel_3.origin_info.db +++ b/artix7/segbits_gtp_channel_3.origin_info.db @@ -1,1627 +1,1627 @@ -GTP_CHANNEL_3.GTPE2.ACJTAG_DEBUG_MODE[0] origin:064-gtp-channel-conf 28_07 -GTP_CHANNEL_3.GTPE2.ACJTAG_MODE[0] origin:064-gtp-channel-conf 29_06 -GTP_CHANNEL_3.GTPE2.ACJTAG_RESET[0] origin:064-gtp-channel-conf 29_07 -GTP_CHANNEL_3.GTPE2.ADAPT_CFG0[0] origin:064-gtp-channel-conf 30_464 -GTP_CHANNEL_3.GTPE2.ADAPT_CFG0[1] origin:064-gtp-channel-conf 31_464 -GTP_CHANNEL_3.GTPE2.ADAPT_CFG0[2] origin:064-gtp-channel-conf 30_465 -GTP_CHANNEL_3.GTPE2.ADAPT_CFG0[3] origin:064-gtp-channel-conf 31_465 -GTP_CHANNEL_3.GTPE2.ADAPT_CFG0[4] origin:064-gtp-channel-conf 30_466 -GTP_CHANNEL_3.GTPE2.ADAPT_CFG0[5] origin:064-gtp-channel-conf 31_466 -GTP_CHANNEL_3.GTPE2.ADAPT_CFG0[6] origin:064-gtp-channel-conf 30_467 -GTP_CHANNEL_3.GTPE2.ADAPT_CFG0[7] origin:064-gtp-channel-conf 31_467 -GTP_CHANNEL_3.GTPE2.ADAPT_CFG0[8] origin:064-gtp-channel-conf 30_468 -GTP_CHANNEL_3.GTPE2.ADAPT_CFG0[9] origin:064-gtp-channel-conf 31_468 -GTP_CHANNEL_3.GTPE2.ADAPT_CFG0[10] origin:064-gtp-channel-conf 30_469 -GTP_CHANNEL_3.GTPE2.ADAPT_CFG0[11] origin:064-gtp-channel-conf 31_469 -GTP_CHANNEL_3.GTPE2.ADAPT_CFG0[12] origin:064-gtp-channel-conf 30_470 -GTP_CHANNEL_3.GTPE2.ADAPT_CFG0[13] origin:064-gtp-channel-conf 31_470 -GTP_CHANNEL_3.GTPE2.ADAPT_CFG0[14] origin:064-gtp-channel-conf 30_471 -GTP_CHANNEL_3.GTPE2.ADAPT_CFG0[15] origin:064-gtp-channel-conf 31_471 -GTP_CHANNEL_3.GTPE2.ADAPT_CFG0[16] origin:064-gtp-channel-conf 30_472 -GTP_CHANNEL_3.GTPE2.ADAPT_CFG0[17] origin:064-gtp-channel-conf 31_472 -GTP_CHANNEL_3.GTPE2.ADAPT_CFG0[18] origin:064-gtp-channel-conf 30_473 -GTP_CHANNEL_3.GTPE2.ADAPT_CFG0[19] origin:064-gtp-channel-conf 31_473 -GTP_CHANNEL_3.GTPE2.ALIGN_COMMA_DOUBLE origin:064-gtp-channel-conf 28_522 -GTP_CHANNEL_3.GTPE2.ALIGN_COMMA_ENABLE[0] origin:064-gtp-channel-conf 28_496 -GTP_CHANNEL_3.GTPE2.ALIGN_COMMA_ENABLE[1] origin:064-gtp-channel-conf 29_496 -GTP_CHANNEL_3.GTPE2.ALIGN_COMMA_ENABLE[2] origin:064-gtp-channel-conf 28_497 -GTP_CHANNEL_3.GTPE2.ALIGN_COMMA_ENABLE[3] origin:064-gtp-channel-conf 29_497 -GTP_CHANNEL_3.GTPE2.ALIGN_COMMA_ENABLE[4] origin:064-gtp-channel-conf 28_498 -GTP_CHANNEL_3.GTPE2.ALIGN_COMMA_ENABLE[5] origin:064-gtp-channel-conf 29_498 -GTP_CHANNEL_3.GTPE2.ALIGN_COMMA_ENABLE[6] origin:064-gtp-channel-conf 28_499 -GTP_CHANNEL_3.GTPE2.ALIGN_COMMA_ENABLE[7] origin:064-gtp-channel-conf 29_499 -GTP_CHANNEL_3.GTPE2.ALIGN_COMMA_ENABLE[8] origin:064-gtp-channel-conf 28_500 -GTP_CHANNEL_3.GTPE2.ALIGN_COMMA_ENABLE[9] origin:064-gtp-channel-conf 29_500 -GTP_CHANNEL_3.GTPE2.ALIGN_COMMA_WORD[0] origin:064-gtp-channel-conf 29_526 -GTP_CHANNEL_3.GTPE2.ALIGN_COMMA_WORD[1] origin:064-gtp-channel-conf 28_527 -GTP_CHANNEL_3.GTPE2.ALIGN_MCOMMA_DET origin:064-gtp-channel-conf 28_523 -GTP_CHANNEL_3.GTPE2.ALIGN_MCOMMA_VALUE[0] origin:064-gtp-channel-conf 28_504 -GTP_CHANNEL_3.GTPE2.ALIGN_MCOMMA_VALUE[1] origin:064-gtp-channel-conf 29_504 -GTP_CHANNEL_3.GTPE2.ALIGN_MCOMMA_VALUE[2] origin:064-gtp-channel-conf 28_505 -GTP_CHANNEL_3.GTPE2.ALIGN_MCOMMA_VALUE[3] origin:064-gtp-channel-conf 29_505 -GTP_CHANNEL_3.GTPE2.ALIGN_MCOMMA_VALUE[4] origin:064-gtp-channel-conf 28_506 -GTP_CHANNEL_3.GTPE2.ALIGN_MCOMMA_VALUE[5] origin:064-gtp-channel-conf 29_506 -GTP_CHANNEL_3.GTPE2.ALIGN_MCOMMA_VALUE[6] origin:064-gtp-channel-conf 28_507 -GTP_CHANNEL_3.GTPE2.ALIGN_MCOMMA_VALUE[7] origin:064-gtp-channel-conf 29_507 -GTP_CHANNEL_3.GTPE2.ALIGN_MCOMMA_VALUE[8] origin:064-gtp-channel-conf 28_508 -GTP_CHANNEL_3.GTPE2.ALIGN_MCOMMA_VALUE[9] origin:064-gtp-channel-conf 29_508 -GTP_CHANNEL_3.GTPE2.ALIGN_PCOMMA_DET origin:064-gtp-channel-conf 29_523 -GTP_CHANNEL_3.GTPE2.ALIGN_PCOMMA_VALUE[0] origin:064-gtp-channel-conf 28_512 -GTP_CHANNEL_3.GTPE2.ALIGN_PCOMMA_VALUE[1] origin:064-gtp-channel-conf 29_512 -GTP_CHANNEL_3.GTPE2.ALIGN_PCOMMA_VALUE[2] origin:064-gtp-channel-conf 28_513 -GTP_CHANNEL_3.GTPE2.ALIGN_PCOMMA_VALUE[3] origin:064-gtp-channel-conf 29_513 -GTP_CHANNEL_3.GTPE2.ALIGN_PCOMMA_VALUE[4] origin:064-gtp-channel-conf 28_514 -GTP_CHANNEL_3.GTPE2.ALIGN_PCOMMA_VALUE[5] origin:064-gtp-channel-conf 29_514 -GTP_CHANNEL_3.GTPE2.ALIGN_PCOMMA_VALUE[6] origin:064-gtp-channel-conf 28_515 -GTP_CHANNEL_3.GTPE2.ALIGN_PCOMMA_VALUE[7] origin:064-gtp-channel-conf 29_515 -GTP_CHANNEL_3.GTPE2.ALIGN_PCOMMA_VALUE[8] origin:064-gtp-channel-conf 28_516 -GTP_CHANNEL_3.GTPE2.ALIGN_PCOMMA_VALUE[9] origin:064-gtp-channel-conf 29_516 -GTP_CHANNEL_3.GTPE2.CBCC_DATA_SOURCE_SEL.DECODED origin:064-gtp-channel-conf 29_661 -GTP_CHANNEL_3.GTPE2.CFOK_CFG[0] origin:064-gtp-channel-conf 30_392 -GTP_CHANNEL_3.GTPE2.CFOK_CFG[1] origin:064-gtp-channel-conf 31_392 -GTP_CHANNEL_3.GTPE2.CFOK_CFG[2] origin:064-gtp-channel-conf 30_393 -GTP_CHANNEL_3.GTPE2.CFOK_CFG[3] origin:064-gtp-channel-conf 31_393 -GTP_CHANNEL_3.GTPE2.CFOK_CFG[4] origin:064-gtp-channel-conf 30_394 -GTP_CHANNEL_3.GTPE2.CFOK_CFG[5] origin:064-gtp-channel-conf 31_394 -GTP_CHANNEL_3.GTPE2.CFOK_CFG[6] origin:064-gtp-channel-conf 30_395 -GTP_CHANNEL_3.GTPE2.CFOK_CFG[7] origin:064-gtp-channel-conf 31_395 -GTP_CHANNEL_3.GTPE2.CFOK_CFG[8] origin:064-gtp-channel-conf 30_396 -GTP_CHANNEL_3.GTPE2.CFOK_CFG[9] origin:064-gtp-channel-conf 31_396 -GTP_CHANNEL_3.GTPE2.CFOK_CFG[10] origin:064-gtp-channel-conf 30_397 -GTP_CHANNEL_3.GTPE2.CFOK_CFG[11] origin:064-gtp-channel-conf 31_397 -GTP_CHANNEL_3.GTPE2.CFOK_CFG[12] origin:064-gtp-channel-conf 30_398 -GTP_CHANNEL_3.GTPE2.CFOK_CFG[13] origin:064-gtp-channel-conf 31_398 -GTP_CHANNEL_3.GTPE2.CFOK_CFG[14] origin:064-gtp-channel-conf 30_399 -GTP_CHANNEL_3.GTPE2.CFOK_CFG[15] origin:064-gtp-channel-conf 31_399 -GTP_CHANNEL_3.GTPE2.CFOK_CFG[16] origin:064-gtp-channel-conf 30_400 -GTP_CHANNEL_3.GTPE2.CFOK_CFG[17] origin:064-gtp-channel-conf 31_400 -GTP_CHANNEL_3.GTPE2.CFOK_CFG[18] origin:064-gtp-channel-conf 30_401 -GTP_CHANNEL_3.GTPE2.CFOK_CFG[19] origin:064-gtp-channel-conf 31_401 -GTP_CHANNEL_3.GTPE2.CFOK_CFG[20] origin:064-gtp-channel-conf 30_402 -GTP_CHANNEL_3.GTPE2.CFOK_CFG[21] origin:064-gtp-channel-conf 31_402 -GTP_CHANNEL_3.GTPE2.CFOK_CFG[22] origin:064-gtp-channel-conf 30_403 -GTP_CHANNEL_3.GTPE2.CFOK_CFG[23] origin:064-gtp-channel-conf 31_403 -GTP_CHANNEL_3.GTPE2.CFOK_CFG[24] origin:064-gtp-channel-conf 30_404 -GTP_CHANNEL_3.GTPE2.CFOK_CFG[25] origin:064-gtp-channel-conf 31_404 -GTP_CHANNEL_3.GTPE2.CFOK_CFG[26] origin:064-gtp-channel-conf 30_405 -GTP_CHANNEL_3.GTPE2.CFOK_CFG[27] origin:064-gtp-channel-conf 31_405 -GTP_CHANNEL_3.GTPE2.CFOK_CFG[28] origin:064-gtp-channel-conf 30_406 -GTP_CHANNEL_3.GTPE2.CFOK_CFG[29] origin:064-gtp-channel-conf 31_406 -GTP_CHANNEL_3.GTPE2.CFOK_CFG[30] origin:064-gtp-channel-conf 30_407 -GTP_CHANNEL_3.GTPE2.CFOK_CFG[31] origin:064-gtp-channel-conf 31_407 -GTP_CHANNEL_3.GTPE2.CFOK_CFG[32] origin:064-gtp-channel-conf 30_408 -GTP_CHANNEL_3.GTPE2.CFOK_CFG[33] origin:064-gtp-channel-conf 31_408 -GTP_CHANNEL_3.GTPE2.CFOK_CFG[34] origin:064-gtp-channel-conf 30_409 -GTP_CHANNEL_3.GTPE2.CFOK_CFG[35] origin:064-gtp-channel-conf 31_409 -GTP_CHANNEL_3.GTPE2.CFOK_CFG[36] origin:064-gtp-channel-conf 30_410 -GTP_CHANNEL_3.GTPE2.CFOK_CFG[37] origin:064-gtp-channel-conf 31_410 -GTP_CHANNEL_3.GTPE2.CFOK_CFG[38] origin:064-gtp-channel-conf 30_411 -GTP_CHANNEL_3.GTPE2.CFOK_CFG[39] origin:064-gtp-channel-conf 31_411 -GTP_CHANNEL_3.GTPE2.CFOK_CFG[40] origin:064-gtp-channel-conf 30_412 -GTP_CHANNEL_3.GTPE2.CFOK_CFG[41] origin:064-gtp-channel-conf 31_412 -GTP_CHANNEL_3.GTPE2.CFOK_CFG[42] origin:064-gtp-channel-conf 30_413 -GTP_CHANNEL_3.GTPE2.CFOK_CFG2[0] origin:064-gtp-channel-conf 30_459 -GTP_CHANNEL_3.GTPE2.CFOK_CFG2[1] origin:064-gtp-channel-conf 31_459 -GTP_CHANNEL_3.GTPE2.CFOK_CFG2[2] origin:064-gtp-channel-conf 30_460 -GTP_CHANNEL_3.GTPE2.CFOK_CFG2[3] origin:064-gtp-channel-conf 31_460 -GTP_CHANNEL_3.GTPE2.CFOK_CFG2[4] origin:064-gtp-channel-conf 30_461 -GTP_CHANNEL_3.GTPE2.CFOK_CFG2[5] origin:064-gtp-channel-conf 31_461 -GTP_CHANNEL_3.GTPE2.CFOK_CFG2[6] origin:064-gtp-channel-conf 30_462 -GTP_CHANNEL_3.GTPE2.CFOK_CFG3[0] origin:064-gtp-channel-conf 30_416 -GTP_CHANNEL_3.GTPE2.CFOK_CFG3[1] origin:064-gtp-channel-conf 31_416 -GTP_CHANNEL_3.GTPE2.CFOK_CFG3[2] origin:064-gtp-channel-conf 30_417 -GTP_CHANNEL_3.GTPE2.CFOK_CFG3[3] origin:064-gtp-channel-conf 31_417 -GTP_CHANNEL_3.GTPE2.CFOK_CFG3[4] origin:064-gtp-channel-conf 30_418 -GTP_CHANNEL_3.GTPE2.CFOK_CFG3[5] origin:064-gtp-channel-conf 31_418 -GTP_CHANNEL_3.GTPE2.CFOK_CFG3[6] origin:064-gtp-channel-conf 30_419 -GTP_CHANNEL_3.GTPE2.CFOK_CFG4[0] origin:064-gtp-channel-conf 31_438 -GTP_CHANNEL_3.GTPE2.CFOK_CFG5[0] origin:064-gtp-channel-conf 30_429 -GTP_CHANNEL_3.GTPE2.CFOK_CFG5[1] origin:064-gtp-channel-conf 31_429 -GTP_CHANNEL_3.GTPE2.CFOK_CFG6[0] origin:064-gtp-channel-conf 31_436 -GTP_CHANNEL_3.GTPE2.CFOK_CFG6[1] origin:064-gtp-channel-conf 30_437 -GTP_CHANNEL_3.GTPE2.CFOK_CFG6[2] origin:064-gtp-channel-conf 31_437 -GTP_CHANNEL_3.GTPE2.CFOK_CFG6[3] origin:064-gtp-channel-conf 30_438 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_KEEP_ALIGN origin:064-gtp-channel-conf 29_631 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_MAX_SKEW[0] origin:064-gtp-channel-conf 28_670 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_MAX_SKEW[1] origin:064-gtp-channel-conf 29_670 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_MAX_SKEW[2] origin:064-gtp-channel-conf 28_671 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_MAX_SKEW[3] origin:064-gtp-channel-conf 29_671 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_1_1[0] origin:064-gtp-channel-conf 28_608 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_1_1[1] origin:064-gtp-channel-conf 29_608 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_1_1[2] origin:064-gtp-channel-conf 28_609 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_1_1[3] origin:064-gtp-channel-conf 29_609 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_1_1[4] origin:064-gtp-channel-conf 28_610 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_1_1[5] origin:064-gtp-channel-conf 29_610 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_1_1[6] origin:064-gtp-channel-conf 28_611 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_1_1[7] origin:064-gtp-channel-conf 29_611 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_1_1[8] origin:064-gtp-channel-conf 28_612 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_1_1[9] origin:064-gtp-channel-conf 29_612 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_1_2[0] origin:064-gtp-channel-conf 28_616 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_1_2[1] origin:064-gtp-channel-conf 29_616 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_1_2[2] origin:064-gtp-channel-conf 28_617 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_1_2[3] origin:064-gtp-channel-conf 29_617 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_1_2[4] origin:064-gtp-channel-conf 28_618 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_1_2[5] origin:064-gtp-channel-conf 29_618 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_1_2[6] origin:064-gtp-channel-conf 28_619 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_1_2[7] origin:064-gtp-channel-conf 29_619 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_1_2[8] origin:064-gtp-channel-conf 28_620 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_1_2[9] origin:064-gtp-channel-conf 29_620 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_1_3[0] origin:064-gtp-channel-conf 28_624 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_1_3[1] origin:064-gtp-channel-conf 29_624 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_1_3[2] origin:064-gtp-channel-conf 28_625 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_1_3[3] origin:064-gtp-channel-conf 29_625 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_1_3[4] origin:064-gtp-channel-conf 28_626 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_1_3[5] origin:064-gtp-channel-conf 29_626 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_1_3[6] origin:064-gtp-channel-conf 28_627 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_1_3[7] origin:064-gtp-channel-conf 29_627 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_1_3[8] origin:064-gtp-channel-conf 28_628 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_1_3[9] origin:064-gtp-channel-conf 29_628 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_1_4[0] origin:064-gtp-channel-conf 28_632 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_1_4[1] origin:064-gtp-channel-conf 29_632 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_1_4[2] origin:064-gtp-channel-conf 28_633 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_1_4[3] origin:064-gtp-channel-conf 29_633 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_1_4[4] origin:064-gtp-channel-conf 28_634 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_1_4[5] origin:064-gtp-channel-conf 29_634 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_1_4[6] origin:064-gtp-channel-conf 28_635 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_1_4[7] origin:064-gtp-channel-conf 29_635 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_1_4[8] origin:064-gtp-channel-conf 28_636 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_1_4[9] origin:064-gtp-channel-conf 29_636 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_1_ENABLE[0] origin:064-gtp-channel-conf 28_614 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_1_ENABLE[1] origin:064-gtp-channel-conf 29_614 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_1_ENABLE[2] origin:064-gtp-channel-conf 28_615 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_1_ENABLE[3] origin:064-gtp-channel-conf 29_615 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_2_1[0] origin:064-gtp-channel-conf 28_640 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_2_1[1] origin:064-gtp-channel-conf 29_640 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_2_1[2] origin:064-gtp-channel-conf 28_641 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_2_1[3] origin:064-gtp-channel-conf 29_641 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_2_1[4] origin:064-gtp-channel-conf 28_642 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_2_1[5] origin:064-gtp-channel-conf 29_642 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_2_1[6] origin:064-gtp-channel-conf 28_643 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_2_1[7] origin:064-gtp-channel-conf 29_643 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_2_1[8] origin:064-gtp-channel-conf 28_644 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_2_1[9] origin:064-gtp-channel-conf 29_644 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_2_2[0] origin:064-gtp-channel-conf 28_648 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_2_2[1] origin:064-gtp-channel-conf 29_648 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_2_2[2] origin:064-gtp-channel-conf 28_649 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_2_2[3] origin:064-gtp-channel-conf 29_649 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_2_2[4] origin:064-gtp-channel-conf 28_650 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_2_2[5] origin:064-gtp-channel-conf 29_650 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_2_2[6] origin:064-gtp-channel-conf 28_651 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_2_2[7] origin:064-gtp-channel-conf 29_651 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_2_2[8] origin:064-gtp-channel-conf 28_652 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_2_2[9] origin:064-gtp-channel-conf 29_652 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_2_3[0] origin:064-gtp-channel-conf 28_656 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_2_3[1] origin:064-gtp-channel-conf 29_656 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_2_3[2] origin:064-gtp-channel-conf 28_657 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_2_3[3] origin:064-gtp-channel-conf 29_657 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_2_3[4] origin:064-gtp-channel-conf 28_658 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_2_3[5] origin:064-gtp-channel-conf 29_658 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_2_3[6] origin:064-gtp-channel-conf 28_659 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_2_3[7] origin:064-gtp-channel-conf 29_659 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_2_3[8] origin:064-gtp-channel-conf 28_660 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_2_3[9] origin:064-gtp-channel-conf 29_660 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_2_4[0] origin:064-gtp-channel-conf 28_664 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_2_4[1] origin:064-gtp-channel-conf 29_664 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_2_4[2] origin:064-gtp-channel-conf 28_665 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_2_4[3] origin:064-gtp-channel-conf 29_665 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_2_4[4] origin:064-gtp-channel-conf 28_666 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_2_4[5] origin:064-gtp-channel-conf 29_666 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_2_4[6] origin:064-gtp-channel-conf 28_667 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_2_4[7] origin:064-gtp-channel-conf 29_667 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_2_4[8] origin:064-gtp-channel-conf 28_668 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_2_4[9] origin:064-gtp-channel-conf 29_668 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_2_ENABLE[0] origin:064-gtp-channel-conf 28_646 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_2_ENABLE[1] origin:064-gtp-channel-conf 29_646 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_2_ENABLE[2] origin:064-gtp-channel-conf 28_647 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_2_ENABLE[3] origin:064-gtp-channel-conf 29_647 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_2_USE origin:064-gtp-channel-conf 29_645 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_LEN[0] origin:064-gtp-channel-conf 28_623 -GTP_CHANNEL_3.GTPE2.CHAN_BOND_SEQ_LEN[1] origin:064-gtp-channel-conf 29_623 -GTP_CHANNEL_3.GTPE2.CLK_COMMON_SWING[0] origin:064-gtp-channel-conf 31_311 -GTP_CHANNEL_3.GTPE2.CLK_COR_KEEP_IDLE origin:064-gtp-channel-conf 28_591 -GTP_CHANNEL_3.GTPE2.CLK_COR_MAX_LAT[0] origin:064-gtp-channel-conf 28_557 -GTP_CHANNEL_3.GTPE2.CLK_COR_MAX_LAT[1] origin:064-gtp-channel-conf 29_557 -GTP_CHANNEL_3.GTPE2.CLK_COR_MAX_LAT[2] origin:064-gtp-channel-conf 28_558 -GTP_CHANNEL_3.GTPE2.CLK_COR_MAX_LAT[3] origin:064-gtp-channel-conf 29_558 -GTP_CHANNEL_3.GTPE2.CLK_COR_MAX_LAT[4] origin:064-gtp-channel-conf 28_559 -GTP_CHANNEL_3.GTPE2.CLK_COR_MAX_LAT[5] origin:064-gtp-channel-conf 29_559 -GTP_CHANNEL_3.GTPE2.CLK_COR_MIN_LAT[0] origin:064-gtp-channel-conf 28_565 -GTP_CHANNEL_3.GTPE2.CLK_COR_MIN_LAT[1] origin:064-gtp-channel-conf 29_565 -GTP_CHANNEL_3.GTPE2.CLK_COR_MIN_LAT[2] origin:064-gtp-channel-conf 28_566 -GTP_CHANNEL_3.GTPE2.CLK_COR_MIN_LAT[3] origin:064-gtp-channel-conf 29_566 -GTP_CHANNEL_3.GTPE2.CLK_COR_MIN_LAT[4] origin:064-gtp-channel-conf 28_567 -GTP_CHANNEL_3.GTPE2.CLK_COR_MIN_LAT[5] origin:064-gtp-channel-conf 29_567 -GTP_CHANNEL_3.GTPE2.CLK_COR_PRECEDENCE origin:064-gtp-channel-conf 28_590 -GTP_CHANNEL_3.GTPE2.CLK_COR_REPEAT_WAIT[0] origin:064-gtp-channel-conf 28_573 -GTP_CHANNEL_3.GTPE2.CLK_COR_REPEAT_WAIT[1] origin:064-gtp-channel-conf 29_573 -GTP_CHANNEL_3.GTPE2.CLK_COR_REPEAT_WAIT[2] origin:064-gtp-channel-conf 28_574 -GTP_CHANNEL_3.GTPE2.CLK_COR_REPEAT_WAIT[3] origin:064-gtp-channel-conf 29_574 -GTP_CHANNEL_3.GTPE2.CLK_COR_REPEAT_WAIT[4] origin:064-gtp-channel-conf 28_575 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_1_1[0] origin:064-gtp-channel-conf 28_544 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_1_1[1] origin:064-gtp-channel-conf 29_544 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_1_1[2] origin:064-gtp-channel-conf 28_545 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_1_1[3] origin:064-gtp-channel-conf 29_545 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_1_1[4] origin:064-gtp-channel-conf 28_546 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_1_1[5] origin:064-gtp-channel-conf 29_546 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_1_1[6] origin:064-gtp-channel-conf 28_547 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_1_1[7] origin:064-gtp-channel-conf 29_547 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_1_1[8] origin:064-gtp-channel-conf 28_548 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_1_1[9] origin:064-gtp-channel-conf 29_548 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_1_2[0] origin:064-gtp-channel-conf 28_552 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_1_2[1] origin:064-gtp-channel-conf 29_552 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_1_2[2] origin:064-gtp-channel-conf 28_553 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_1_2[3] origin:064-gtp-channel-conf 29_553 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_1_2[4] origin:064-gtp-channel-conf 28_554 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_1_2[5] origin:064-gtp-channel-conf 29_554 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_1_2[6] origin:064-gtp-channel-conf 28_555 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_1_2[7] origin:064-gtp-channel-conf 29_555 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_1_2[8] origin:064-gtp-channel-conf 28_556 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_1_2[9] origin:064-gtp-channel-conf 29_556 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_1_3[0] origin:064-gtp-channel-conf 28_560 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_1_3[1] origin:064-gtp-channel-conf 29_560 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_1_3[2] origin:064-gtp-channel-conf 28_561 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_1_3[3] origin:064-gtp-channel-conf 29_561 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_1_3[4] origin:064-gtp-channel-conf 28_562 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_1_3[5] origin:064-gtp-channel-conf 29_562 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_1_3[6] origin:064-gtp-channel-conf 28_563 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_1_3[7] origin:064-gtp-channel-conf 29_563 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_1_3[8] origin:064-gtp-channel-conf 28_564 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_1_3[9] origin:064-gtp-channel-conf 29_564 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_1_4[0] origin:064-gtp-channel-conf 28_568 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_1_4[1] origin:064-gtp-channel-conf 29_568 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_1_4[2] origin:064-gtp-channel-conf 28_569 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_1_4[3] origin:064-gtp-channel-conf 29_569 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_1_4[4] origin:064-gtp-channel-conf 28_570 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_1_4[5] origin:064-gtp-channel-conf 29_570 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_1_4[6] origin:064-gtp-channel-conf 28_571 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_1_4[7] origin:064-gtp-channel-conf 29_571 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_1_4[8] origin:064-gtp-channel-conf 28_572 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_1_4[9] origin:064-gtp-channel-conf 29_572 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_1_ENABLE[0] origin:064-gtp-channel-conf 28_549 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_1_ENABLE[1] origin:064-gtp-channel-conf 29_549 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_1_ENABLE[2] origin:064-gtp-channel-conf 28_550 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_1_ENABLE[3] origin:064-gtp-channel-conf 29_550 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_2_1[0] origin:064-gtp-channel-conf 28_576 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_2_1[1] origin:064-gtp-channel-conf 29_576 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_2_1[2] origin:064-gtp-channel-conf 28_577 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_2_1[3] origin:064-gtp-channel-conf 29_577 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_2_1[4] origin:064-gtp-channel-conf 28_578 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_2_1[5] origin:064-gtp-channel-conf 29_578 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_2_1[6] origin:064-gtp-channel-conf 28_579 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_2_1[7] origin:064-gtp-channel-conf 29_579 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_2_1[8] origin:064-gtp-channel-conf 28_580 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_2_1[9] origin:064-gtp-channel-conf 29_580 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_2_2[0] origin:064-gtp-channel-conf 28_584 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_2_2[1] origin:064-gtp-channel-conf 29_584 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_2_2[2] origin:064-gtp-channel-conf 28_585 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_2_2[3] origin:064-gtp-channel-conf 29_585 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_2_2[4] origin:064-gtp-channel-conf 28_586 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_2_2[5] origin:064-gtp-channel-conf 29_586 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_2_2[6] origin:064-gtp-channel-conf 28_587 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_2_2[7] origin:064-gtp-channel-conf 29_587 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_2_2[8] origin:064-gtp-channel-conf 28_588 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_2_2[9] origin:064-gtp-channel-conf 29_588 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_2_3[0] origin:064-gtp-channel-conf 28_592 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_2_3[1] origin:064-gtp-channel-conf 29_592 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_2_3[2] origin:064-gtp-channel-conf 28_593 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_2_3[3] origin:064-gtp-channel-conf 29_593 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_2_3[4] origin:064-gtp-channel-conf 28_594 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_2_3[5] origin:064-gtp-channel-conf 29_594 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_2_3[6] origin:064-gtp-channel-conf 28_595 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_2_3[7] origin:064-gtp-channel-conf 29_595 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_2_3[8] origin:064-gtp-channel-conf 28_596 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_2_3[9] origin:064-gtp-channel-conf 29_596 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_2_4[0] origin:064-gtp-channel-conf 28_600 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_2_4[1] origin:064-gtp-channel-conf 29_600 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_2_4[2] origin:064-gtp-channel-conf 28_601 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_2_4[3] origin:064-gtp-channel-conf 29_601 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_2_4[4] origin:064-gtp-channel-conf 28_602 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_2_4[5] origin:064-gtp-channel-conf 29_602 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_2_4[6] origin:064-gtp-channel-conf 28_603 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_2_4[7] origin:064-gtp-channel-conf 29_603 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_2_4[8] origin:064-gtp-channel-conf 28_604 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_2_4[9] origin:064-gtp-channel-conf 29_604 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_2_ENABLE[0] origin:064-gtp-channel-conf 28_581 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_2_ENABLE[1] origin:064-gtp-channel-conf 29_581 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_2_ENABLE[2] origin:064-gtp-channel-conf 28_582 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_2_ENABLE[3] origin:064-gtp-channel-conf 29_582 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_2_USE origin:064-gtp-channel-conf 28_583 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_LEN[0] origin:064-gtp-channel-conf 28_589 -GTP_CHANNEL_3.GTPE2.CLK_COR_SEQ_LEN[1] origin:064-gtp-channel-conf 29_589 -GTP_CHANNEL_3.GTPE2.CLK_CORRECT_USE origin:064-gtp-channel-conf 28_551 -GTP_CHANNEL_3.GTPE2.DEC_MCOMMA_DETECT origin:064-gtp-channel-conf 29_494 -GTP_CHANNEL_3.GTPE2.DEC_PCOMMA_DETECT origin:064-gtp-channel-conf 28_495 -GTP_CHANNEL_3.GTPE2.DEC_VALID_COMMA_ONLY origin:064-gtp-channel-conf 28_494 -GTP_CHANNEL_3.GTPE2.DMONITOR_CFG[0] origin:064-gtp-channel-conf 30_368 -GTP_CHANNEL_3.GTPE2.DMONITOR_CFG[1] origin:064-gtp-channel-conf 31_368 -GTP_CHANNEL_3.GTPE2.DMONITOR_CFG[2] origin:064-gtp-channel-conf 30_369 -GTP_CHANNEL_3.GTPE2.DMONITOR_CFG[3] origin:064-gtp-channel-conf 31_369 -GTP_CHANNEL_3.GTPE2.DMONITOR_CFG[4] origin:064-gtp-channel-conf 30_370 -GTP_CHANNEL_3.GTPE2.DMONITOR_CFG[5] origin:064-gtp-channel-conf 31_370 -GTP_CHANNEL_3.GTPE2.DMONITOR_CFG[6] origin:064-gtp-channel-conf 30_371 -GTP_CHANNEL_3.GTPE2.DMONITOR_CFG[7] origin:064-gtp-channel-conf 31_371 -GTP_CHANNEL_3.GTPE2.DMONITOR_CFG[8] origin:064-gtp-channel-conf 30_372 -GTP_CHANNEL_3.GTPE2.DMONITOR_CFG[9] origin:064-gtp-channel-conf 31_372 -GTP_CHANNEL_3.GTPE2.DMONITOR_CFG[10] origin:064-gtp-channel-conf 30_373 -GTP_CHANNEL_3.GTPE2.DMONITOR_CFG[11] origin:064-gtp-channel-conf 31_373 -GTP_CHANNEL_3.GTPE2.DMONITOR_CFG[12] origin:064-gtp-channel-conf 30_374 -GTP_CHANNEL_3.GTPE2.DMONITOR_CFG[13] origin:064-gtp-channel-conf 31_374 -GTP_CHANNEL_3.GTPE2.DMONITOR_CFG[14] origin:064-gtp-channel-conf 30_375 -GTP_CHANNEL_3.GTPE2.DMONITOR_CFG[15] origin:064-gtp-channel-conf 31_375 -GTP_CHANNEL_3.GTPE2.DMONITOR_CFG[16] origin:064-gtp-channel-conf 30_376 -GTP_CHANNEL_3.GTPE2.DMONITOR_CFG[17] origin:064-gtp-channel-conf 31_376 -GTP_CHANNEL_3.GTPE2.DMONITOR_CFG[18] origin:064-gtp-channel-conf 30_377 -GTP_CHANNEL_3.GTPE2.DMONITOR_CFG[19] origin:064-gtp-channel-conf 31_377 -GTP_CHANNEL_3.GTPE2.DMONITOR_CFG[20] origin:064-gtp-channel-conf 30_378 -GTP_CHANNEL_3.GTPE2.DMONITOR_CFG[21] origin:064-gtp-channel-conf 31_378 -GTP_CHANNEL_3.GTPE2.DMONITOR_CFG[22] origin:064-gtp-channel-conf 30_379 -GTP_CHANNEL_3.GTPE2.DMONITOR_CFG[23] origin:064-gtp-channel-conf 31_379 -GTP_CHANNEL_3.GTPE2.ES_CLK_PHASE_SEL[0] origin:064-gtp-channel-conf 31_463 -GTP_CHANNEL_3.GTPE2.ES_CONTROL[0] origin:064-gtp-channel-conf 28_488 -GTP_CHANNEL_3.GTPE2.ES_CONTROL[1] origin:064-gtp-channel-conf 29_488 -GTP_CHANNEL_3.GTPE2.ES_CONTROL[2] origin:064-gtp-channel-conf 28_489 -GTP_CHANNEL_3.GTPE2.ES_CONTROL[3] origin:064-gtp-channel-conf 29_489 -GTP_CHANNEL_3.GTPE2.ES_CONTROL[4] origin:064-gtp-channel-conf 28_490 -GTP_CHANNEL_3.GTPE2.ES_CONTROL[5] origin:064-gtp-channel-conf 29_490 -GTP_CHANNEL_3.GTPE2.ES_ERRDET_EN origin:064-gtp-channel-conf 29_492 -GTP_CHANNEL_3.GTPE2.ES_EYE_SCAN_EN origin:064-gtp-channel-conf 28_492 -GTP_CHANNEL_3.GTPE2.ES_HORZ_OFFSET[0] origin:064-gtp-channel-conf 28_480 -GTP_CHANNEL_3.GTPE2.ES_HORZ_OFFSET[1] origin:064-gtp-channel-conf 29_480 -GTP_CHANNEL_3.GTPE2.ES_HORZ_OFFSET[2] origin:064-gtp-channel-conf 28_481 -GTP_CHANNEL_3.GTPE2.ES_HORZ_OFFSET[3] origin:064-gtp-channel-conf 29_481 -GTP_CHANNEL_3.GTPE2.ES_HORZ_OFFSET[4] origin:064-gtp-channel-conf 28_482 -GTP_CHANNEL_3.GTPE2.ES_HORZ_OFFSET[5] origin:064-gtp-channel-conf 29_482 -GTP_CHANNEL_3.GTPE2.ES_HORZ_OFFSET[6] origin:064-gtp-channel-conf 28_483 -GTP_CHANNEL_3.GTPE2.ES_HORZ_OFFSET[7] origin:064-gtp-channel-conf 29_483 -GTP_CHANNEL_3.GTPE2.ES_HORZ_OFFSET[8] origin:064-gtp-channel-conf 28_484 -GTP_CHANNEL_3.GTPE2.ES_HORZ_OFFSET[9] origin:064-gtp-channel-conf 29_484 -GTP_CHANNEL_3.GTPE2.ES_HORZ_OFFSET[10] origin:064-gtp-channel-conf 28_485 -GTP_CHANNEL_3.GTPE2.ES_HORZ_OFFSET[11] origin:064-gtp-channel-conf 29_485 -GTP_CHANNEL_3.GTPE2.ES_PMA_CFG[0] origin:064-gtp-channel-conf 30_624 -GTP_CHANNEL_3.GTPE2.ES_PMA_CFG[1] origin:064-gtp-channel-conf 31_624 -GTP_CHANNEL_3.GTPE2.ES_PMA_CFG[2] origin:064-gtp-channel-conf 30_625 -GTP_CHANNEL_3.GTPE2.ES_PMA_CFG[3] origin:064-gtp-channel-conf 31_625 -GTP_CHANNEL_3.GTPE2.ES_PMA_CFG[4] origin:064-gtp-channel-conf 30_626 -GTP_CHANNEL_3.GTPE2.ES_PMA_CFG[5] origin:064-gtp-channel-conf 31_626 -GTP_CHANNEL_3.GTPE2.ES_PMA_CFG[6] origin:064-gtp-channel-conf 30_627 -GTP_CHANNEL_3.GTPE2.ES_PMA_CFG[7] origin:064-gtp-channel-conf 31_627 -GTP_CHANNEL_3.GTPE2.ES_PMA_CFG[8] origin:064-gtp-channel-conf 30_628 -GTP_CHANNEL_3.GTPE2.ES_PMA_CFG[9] origin:064-gtp-channel-conf 31_628 -GTP_CHANNEL_3.GTPE2.ES_PRESCALE[0] origin:064-gtp-channel-conf 29_477 -GTP_CHANNEL_3.GTPE2.ES_PRESCALE[1] origin:064-gtp-channel-conf 28_478 -GTP_CHANNEL_3.GTPE2.ES_PRESCALE[2] origin:064-gtp-channel-conf 29_478 -GTP_CHANNEL_3.GTPE2.ES_PRESCALE[3] origin:064-gtp-channel-conf 28_479 -GTP_CHANNEL_3.GTPE2.ES_PRESCALE[4] origin:064-gtp-channel-conf 29_479 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[0] origin:064-gtp-channel-conf 28_392 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[1] origin:064-gtp-channel-conf 29_392 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[2] origin:064-gtp-channel-conf 28_393 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[3] origin:064-gtp-channel-conf 29_393 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[4] origin:064-gtp-channel-conf 28_394 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[5] origin:064-gtp-channel-conf 29_394 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[6] origin:064-gtp-channel-conf 28_395 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[7] origin:064-gtp-channel-conf 29_395 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[8] origin:064-gtp-channel-conf 28_396 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[9] origin:064-gtp-channel-conf 29_396 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[10] origin:064-gtp-channel-conf 28_397 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[11] origin:064-gtp-channel-conf 29_397 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[12] origin:064-gtp-channel-conf 28_398 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[13] origin:064-gtp-channel-conf 29_398 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[14] origin:064-gtp-channel-conf 28_399 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[15] origin:064-gtp-channel-conf 29_399 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[16] origin:064-gtp-channel-conf 28_400 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[17] origin:064-gtp-channel-conf 29_400 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[18] origin:064-gtp-channel-conf 28_401 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[19] origin:064-gtp-channel-conf 29_401 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[20] origin:064-gtp-channel-conf 28_402 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[21] origin:064-gtp-channel-conf 29_402 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[22] origin:064-gtp-channel-conf 28_403 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[23] origin:064-gtp-channel-conf 29_403 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[24] origin:064-gtp-channel-conf 28_404 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[25] origin:064-gtp-channel-conf 29_404 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[26] origin:064-gtp-channel-conf 28_405 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[27] origin:064-gtp-channel-conf 29_405 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[28] origin:064-gtp-channel-conf 28_406 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[29] origin:064-gtp-channel-conf 29_406 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[30] origin:064-gtp-channel-conf 28_407 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[31] origin:064-gtp-channel-conf 29_407 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[32] origin:064-gtp-channel-conf 28_408 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[33] origin:064-gtp-channel-conf 29_408 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[34] origin:064-gtp-channel-conf 28_409 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[35] origin:064-gtp-channel-conf 29_409 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[36] origin:064-gtp-channel-conf 28_410 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[37] origin:064-gtp-channel-conf 29_410 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[38] origin:064-gtp-channel-conf 28_411 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[39] origin:064-gtp-channel-conf 29_411 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[40] origin:064-gtp-channel-conf 28_412 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[41] origin:064-gtp-channel-conf 29_412 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[42] origin:064-gtp-channel-conf 28_413 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[43] origin:064-gtp-channel-conf 29_413 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[44] origin:064-gtp-channel-conf 28_414 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[45] origin:064-gtp-channel-conf 29_414 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[46] origin:064-gtp-channel-conf 28_415 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[47] origin:064-gtp-channel-conf 29_415 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[48] origin:064-gtp-channel-conf 28_416 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[49] origin:064-gtp-channel-conf 29_416 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[50] origin:064-gtp-channel-conf 28_417 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[51] origin:064-gtp-channel-conf 29_417 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[52] origin:064-gtp-channel-conf 28_418 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[53] origin:064-gtp-channel-conf 29_418 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[54] origin:064-gtp-channel-conf 28_419 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[55] origin:064-gtp-channel-conf 29_419 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[56] origin:064-gtp-channel-conf 28_420 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[57] origin:064-gtp-channel-conf 29_420 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[58] origin:064-gtp-channel-conf 28_421 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[59] origin:064-gtp-channel-conf 29_421 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[60] origin:064-gtp-channel-conf 28_422 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[61] origin:064-gtp-channel-conf 29_422 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[62] origin:064-gtp-channel-conf 28_423 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[63] origin:064-gtp-channel-conf 29_423 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[64] origin:064-gtp-channel-conf 28_424 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[65] origin:064-gtp-channel-conf 29_424 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[66] origin:064-gtp-channel-conf 28_425 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[67] origin:064-gtp-channel-conf 29_425 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[68] origin:064-gtp-channel-conf 28_426 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[69] origin:064-gtp-channel-conf 29_426 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[70] origin:064-gtp-channel-conf 28_427 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[71] origin:064-gtp-channel-conf 29_427 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[72] origin:064-gtp-channel-conf 28_428 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[73] origin:064-gtp-channel-conf 29_428 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[74] origin:064-gtp-channel-conf 28_429 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[75] origin:064-gtp-channel-conf 29_429 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[76] origin:064-gtp-channel-conf 28_430 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[77] origin:064-gtp-channel-conf 29_430 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[78] origin:064-gtp-channel-conf 28_431 -GTP_CHANNEL_3.GTPE2.ES_QUAL_MASK[79] origin:064-gtp-channel-conf 29_431 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[0] origin:064-gtp-channel-conf 28_352 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[1] origin:064-gtp-channel-conf 29_352 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[2] origin:064-gtp-channel-conf 28_353 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[3] origin:064-gtp-channel-conf 29_353 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[4] origin:064-gtp-channel-conf 28_354 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[5] origin:064-gtp-channel-conf 29_354 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[6] origin:064-gtp-channel-conf 28_355 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[7] origin:064-gtp-channel-conf 29_355 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[8] origin:064-gtp-channel-conf 28_356 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[9] origin:064-gtp-channel-conf 29_356 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[10] origin:064-gtp-channel-conf 28_357 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[11] origin:064-gtp-channel-conf 29_357 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[12] origin:064-gtp-channel-conf 28_358 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[13] origin:064-gtp-channel-conf 29_358 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[14] origin:064-gtp-channel-conf 28_359 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[15] origin:064-gtp-channel-conf 29_359 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[16] origin:064-gtp-channel-conf 28_360 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[17] origin:064-gtp-channel-conf 29_360 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[18] origin:064-gtp-channel-conf 28_361 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[19] origin:064-gtp-channel-conf 29_361 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[20] origin:064-gtp-channel-conf 28_362 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[21] origin:064-gtp-channel-conf 29_362 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[22] origin:064-gtp-channel-conf 28_363 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[23] origin:064-gtp-channel-conf 29_363 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[24] origin:064-gtp-channel-conf 28_364 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[25] origin:064-gtp-channel-conf 29_364 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[26] origin:064-gtp-channel-conf 28_365 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[27] origin:064-gtp-channel-conf 29_365 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[28] origin:064-gtp-channel-conf 28_366 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[29] origin:064-gtp-channel-conf 29_366 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[30] origin:064-gtp-channel-conf 28_367 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[31] origin:064-gtp-channel-conf 29_367 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[32] origin:064-gtp-channel-conf 28_368 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[33] origin:064-gtp-channel-conf 29_368 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[34] origin:064-gtp-channel-conf 28_369 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[35] origin:064-gtp-channel-conf 29_369 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[36] origin:064-gtp-channel-conf 28_370 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[37] origin:064-gtp-channel-conf 29_370 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[38] origin:064-gtp-channel-conf 28_371 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[39] origin:064-gtp-channel-conf 29_371 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[40] origin:064-gtp-channel-conf 28_372 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[41] origin:064-gtp-channel-conf 29_372 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[42] origin:064-gtp-channel-conf 28_373 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[43] origin:064-gtp-channel-conf 29_373 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[44] origin:064-gtp-channel-conf 28_374 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[45] origin:064-gtp-channel-conf 29_374 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[46] origin:064-gtp-channel-conf 28_375 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[47] origin:064-gtp-channel-conf 29_375 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[48] origin:064-gtp-channel-conf 28_376 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[49] origin:064-gtp-channel-conf 29_376 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[50] origin:064-gtp-channel-conf 28_377 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[51] origin:064-gtp-channel-conf 29_377 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[52] origin:064-gtp-channel-conf 28_378 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[53] origin:064-gtp-channel-conf 29_378 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[54] origin:064-gtp-channel-conf 28_379 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[55] origin:064-gtp-channel-conf 29_379 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[56] origin:064-gtp-channel-conf 28_380 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[57] origin:064-gtp-channel-conf 29_380 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[58] origin:064-gtp-channel-conf 28_381 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[59] origin:064-gtp-channel-conf 29_381 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[60] origin:064-gtp-channel-conf 28_382 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[61] origin:064-gtp-channel-conf 29_382 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[62] origin:064-gtp-channel-conf 28_383 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[63] origin:064-gtp-channel-conf 29_383 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[64] origin:064-gtp-channel-conf 28_384 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[65] origin:064-gtp-channel-conf 29_384 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[66] origin:064-gtp-channel-conf 28_385 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[67] origin:064-gtp-channel-conf 29_385 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[68] origin:064-gtp-channel-conf 28_386 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[69] origin:064-gtp-channel-conf 29_386 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[70] origin:064-gtp-channel-conf 28_387 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[71] origin:064-gtp-channel-conf 29_387 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[72] origin:064-gtp-channel-conf 28_388 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[73] origin:064-gtp-channel-conf 29_388 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[74] origin:064-gtp-channel-conf 28_389 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[75] origin:064-gtp-channel-conf 29_389 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[76] origin:064-gtp-channel-conf 28_390 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[77] origin:064-gtp-channel-conf 29_390 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[78] origin:064-gtp-channel-conf 28_391 -GTP_CHANNEL_3.GTPE2.ES_QUALIFIER[79] origin:064-gtp-channel-conf 29_391 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[0] origin:064-gtp-channel-conf 28_432 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[1] origin:064-gtp-channel-conf 29_432 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[2] origin:064-gtp-channel-conf 28_433 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[3] origin:064-gtp-channel-conf 29_433 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[4] origin:064-gtp-channel-conf 28_434 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[5] origin:064-gtp-channel-conf 29_434 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[6] origin:064-gtp-channel-conf 28_435 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[7] origin:064-gtp-channel-conf 29_435 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[8] origin:064-gtp-channel-conf 28_436 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[9] origin:064-gtp-channel-conf 29_436 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[10] origin:064-gtp-channel-conf 28_437 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[11] origin:064-gtp-channel-conf 29_437 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[12] origin:064-gtp-channel-conf 28_438 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[13] origin:064-gtp-channel-conf 29_438 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[14] origin:064-gtp-channel-conf 28_439 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[15] origin:064-gtp-channel-conf 29_439 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[16] origin:064-gtp-channel-conf 28_440 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[17] origin:064-gtp-channel-conf 29_440 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[18] origin:064-gtp-channel-conf 28_441 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[19] origin:064-gtp-channel-conf 29_441 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[20] origin:064-gtp-channel-conf 28_442 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[21] origin:064-gtp-channel-conf 29_442 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[22] origin:064-gtp-channel-conf 28_443 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[23] origin:064-gtp-channel-conf 29_443 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[24] origin:064-gtp-channel-conf 28_444 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[25] origin:064-gtp-channel-conf 29_444 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[26] origin:064-gtp-channel-conf 28_445 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[27] origin:064-gtp-channel-conf 29_445 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[28] origin:064-gtp-channel-conf 28_446 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[29] origin:064-gtp-channel-conf 29_446 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[30] origin:064-gtp-channel-conf 28_447 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[31] origin:064-gtp-channel-conf 29_447 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[32] origin:064-gtp-channel-conf 28_448 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[33] origin:064-gtp-channel-conf 29_448 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[34] origin:064-gtp-channel-conf 28_449 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[35] origin:064-gtp-channel-conf 29_449 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[36] origin:064-gtp-channel-conf 28_450 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[37] origin:064-gtp-channel-conf 29_450 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[38] origin:064-gtp-channel-conf 28_451 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[39] origin:064-gtp-channel-conf 29_451 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[40] origin:064-gtp-channel-conf 28_452 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[41] origin:064-gtp-channel-conf 29_452 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[42] origin:064-gtp-channel-conf 28_453 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[43] origin:064-gtp-channel-conf 29_453 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[44] origin:064-gtp-channel-conf 28_454 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[45] origin:064-gtp-channel-conf 29_454 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[46] origin:064-gtp-channel-conf 28_455 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[47] origin:064-gtp-channel-conf 29_455 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[48] origin:064-gtp-channel-conf 28_456 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[49] origin:064-gtp-channel-conf 29_456 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[50] origin:064-gtp-channel-conf 28_457 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[51] origin:064-gtp-channel-conf 29_457 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[52] origin:064-gtp-channel-conf 28_458 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[53] origin:064-gtp-channel-conf 29_458 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[54] origin:064-gtp-channel-conf 28_459 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[55] origin:064-gtp-channel-conf 29_459 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[56] origin:064-gtp-channel-conf 28_460 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[57] origin:064-gtp-channel-conf 29_460 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[58] origin:064-gtp-channel-conf 28_461 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[59] origin:064-gtp-channel-conf 29_461 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[60] origin:064-gtp-channel-conf 28_462 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[61] origin:064-gtp-channel-conf 29_462 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[62] origin:064-gtp-channel-conf 28_463 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[63] origin:064-gtp-channel-conf 29_463 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[64] origin:064-gtp-channel-conf 28_464 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[65] origin:064-gtp-channel-conf 29_464 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[66] origin:064-gtp-channel-conf 28_465 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[67] origin:064-gtp-channel-conf 29_465 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[68] origin:064-gtp-channel-conf 28_466 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[69] origin:064-gtp-channel-conf 29_466 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[70] origin:064-gtp-channel-conf 28_467 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[71] origin:064-gtp-channel-conf 29_467 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[72] origin:064-gtp-channel-conf 28_468 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[73] origin:064-gtp-channel-conf 29_468 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[74] origin:064-gtp-channel-conf 28_469 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[75] origin:064-gtp-channel-conf 29_469 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[76] origin:064-gtp-channel-conf 28_470 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[77] origin:064-gtp-channel-conf 29_470 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[78] origin:064-gtp-channel-conf 28_471 -GTP_CHANNEL_3.GTPE2.ES_SDATA_MASK[79] origin:064-gtp-channel-conf 29_471 -GTP_CHANNEL_3.GTPE2.ES_VERT_OFFSET[0] origin:064-gtp-channel-conf 28_472 -GTP_CHANNEL_3.GTPE2.ES_VERT_OFFSET[1] origin:064-gtp-channel-conf 29_472 -GTP_CHANNEL_3.GTPE2.ES_VERT_OFFSET[2] origin:064-gtp-channel-conf 28_473 -GTP_CHANNEL_3.GTPE2.ES_VERT_OFFSET[3] origin:064-gtp-channel-conf 29_473 -GTP_CHANNEL_3.GTPE2.ES_VERT_OFFSET[4] origin:064-gtp-channel-conf 28_474 -GTP_CHANNEL_3.GTPE2.ES_VERT_OFFSET[5] origin:064-gtp-channel-conf 29_474 -GTP_CHANNEL_3.GTPE2.ES_VERT_OFFSET[6] origin:064-gtp-channel-conf 28_475 -GTP_CHANNEL_3.GTPE2.ES_VERT_OFFSET[7] origin:064-gtp-channel-conf 29_475 -GTP_CHANNEL_3.GTPE2.ES_VERT_OFFSET[8] origin:064-gtp-channel-conf 28_476 -GTP_CHANNEL_3.GTPE2.FTS_DESKEW_SEQ_ENABLE[0] origin:064-gtp-channel-conf 28_662 -GTP_CHANNEL_3.GTPE2.FTS_DESKEW_SEQ_ENABLE[1] origin:064-gtp-channel-conf 29_662 -GTP_CHANNEL_3.GTPE2.FTS_DESKEW_SEQ_ENABLE[2] origin:064-gtp-channel-conf 28_663 -GTP_CHANNEL_3.GTPE2.FTS_DESKEW_SEQ_ENABLE[3] origin:064-gtp-channel-conf 29_663 -GTP_CHANNEL_3.GTPE2.FTS_LANE_DESKEW_CFG[0] origin:064-gtp-channel-conf 28_654 -GTP_CHANNEL_3.GTPE2.FTS_LANE_DESKEW_CFG[1] origin:064-gtp-channel-conf 29_654 -GTP_CHANNEL_3.GTPE2.FTS_LANE_DESKEW_CFG[2] origin:064-gtp-channel-conf 28_655 -GTP_CHANNEL_3.GTPE2.FTS_LANE_DESKEW_CFG[3] origin:064-gtp-channel-conf 29_655 -GTP_CHANNEL_3.GTPE2.FTS_LANE_DESKEW_EN origin:064-gtp-channel-conf 29_653 -GTP_CHANNEL_3.GTPE2.GEARBOX_MODE[0] origin:064-gtp-channel-conf 28_224 -GTP_CHANNEL_3.GTPE2.GEARBOX_MODE[1] origin:064-gtp-channel-conf 29_224 -GTP_CHANNEL_3.GTPE2.GEARBOX_MODE[2] origin:064-gtp-channel-conf 28_225 -GTP_CHANNEL_3.GTPE2.IN_USE origin:064-gtp-channel-conf 28_00 28_01 28_47 28_52 28_53 28_65 29_01 29_47 30_129 -GTP_CHANNEL_3.GTPE2.LOOPBACK_CFG[0] origin:064-gtp-channel-conf 30_20 -GTP_CHANNEL_3.GTPE2.OUTREFCLK_SEL_INV[0] origin:064-gtp-channel-conf 28_149 -GTP_CHANNEL_3.GTPE2.OUTREFCLK_SEL_INV[1] origin:064-gtp-channel-conf 29_149 -GTP_CHANNEL_3.GTPE2.PCS_PCIE_EN origin:064-gtp-channel-conf 28_216 -GTP_CHANNEL_3.GTPE2.PCS_RSVD_ATTR[0] origin:064-gtp-channel-conf 30_184 -GTP_CHANNEL_3.GTPE2.PCS_RSVD_ATTR[1] origin:064-gtp-channel-conf 31_184 -GTP_CHANNEL_3.GTPE2.PCS_RSVD_ATTR[2] origin:064-gtp-channel-conf 30_185 -GTP_CHANNEL_3.GTPE2.PCS_RSVD_ATTR[3] origin:064-gtp-channel-conf 31_185 -GTP_CHANNEL_3.GTPE2.PCS_RSVD_ATTR[4] origin:064-gtp-channel-conf 30_186 -GTP_CHANNEL_3.GTPE2.PCS_RSVD_ATTR[5] origin:064-gtp-channel-conf 31_186 -GTP_CHANNEL_3.GTPE2.PCS_RSVD_ATTR[6] origin:064-gtp-channel-conf 30_187 -GTP_CHANNEL_3.GTPE2.PCS_RSVD_ATTR[7] origin:064-gtp-channel-conf 31_187 -GTP_CHANNEL_3.GTPE2.PCS_RSVD_ATTR[8] origin:064-gtp-channel-conf 30_188 -GTP_CHANNEL_3.GTPE2.PCS_RSVD_ATTR[9] origin:064-gtp-channel-conf 31_188 -GTP_CHANNEL_3.GTPE2.PCS_RSVD_ATTR[10] origin:064-gtp-channel-conf 30_189 -GTP_CHANNEL_3.GTPE2.PCS_RSVD_ATTR[11] origin:064-gtp-channel-conf 31_189 -GTP_CHANNEL_3.GTPE2.PCS_RSVD_ATTR[12] origin:064-gtp-channel-conf 30_190 -GTP_CHANNEL_3.GTPE2.PCS_RSVD_ATTR[13] origin:064-gtp-channel-conf 31_190 -GTP_CHANNEL_3.GTPE2.PCS_RSVD_ATTR[14] origin:064-gtp-channel-conf 30_191 -GTP_CHANNEL_3.GTPE2.PCS_RSVD_ATTR[15] origin:064-gtp-channel-conf 31_191 -GTP_CHANNEL_3.GTPE2.PCS_RSVD_ATTR[16] origin:064-gtp-channel-conf 30_192 -GTP_CHANNEL_3.GTPE2.PCS_RSVD_ATTR[17] origin:064-gtp-channel-conf 31_192 -GTP_CHANNEL_3.GTPE2.PCS_RSVD_ATTR[18] origin:064-gtp-channel-conf 30_193 -GTP_CHANNEL_3.GTPE2.PCS_RSVD_ATTR[19] origin:064-gtp-channel-conf 31_193 -GTP_CHANNEL_3.GTPE2.PCS_RSVD_ATTR[20] origin:064-gtp-channel-conf 30_194 -GTP_CHANNEL_3.GTPE2.PCS_RSVD_ATTR[21] origin:064-gtp-channel-conf 31_194 -GTP_CHANNEL_3.GTPE2.PCS_RSVD_ATTR[22] origin:064-gtp-channel-conf 30_195 -GTP_CHANNEL_3.GTPE2.PCS_RSVD_ATTR[23] origin:064-gtp-channel-conf 31_195 -GTP_CHANNEL_3.GTPE2.PCS_RSVD_ATTR[24] origin:064-gtp-channel-conf 30_196 -GTP_CHANNEL_3.GTPE2.PCS_RSVD_ATTR[25] origin:064-gtp-channel-conf 31_196 -GTP_CHANNEL_3.GTPE2.PCS_RSVD_ATTR[26] origin:064-gtp-channel-conf 30_197 -GTP_CHANNEL_3.GTPE2.PCS_RSVD_ATTR[27] origin:064-gtp-channel-conf 31_197 -GTP_CHANNEL_3.GTPE2.PCS_RSVD_ATTR[28] origin:064-gtp-channel-conf 30_198 -GTP_CHANNEL_3.GTPE2.PCS_RSVD_ATTR[29] origin:064-gtp-channel-conf 31_198 -GTP_CHANNEL_3.GTPE2.PCS_RSVD_ATTR[30] origin:064-gtp-channel-conf 30_199 -GTP_CHANNEL_3.GTPE2.PCS_RSVD_ATTR[31] origin:064-gtp-channel-conf 31_199 -GTP_CHANNEL_3.GTPE2.PCS_RSVD_ATTR[32] origin:064-gtp-channel-conf 30_200 -GTP_CHANNEL_3.GTPE2.PCS_RSVD_ATTR[33] origin:064-gtp-channel-conf 31_200 -GTP_CHANNEL_3.GTPE2.PCS_RSVD_ATTR[34] origin:064-gtp-channel-conf 30_201 -GTP_CHANNEL_3.GTPE2.PCS_RSVD_ATTR[35] origin:064-gtp-channel-conf 31_201 -GTP_CHANNEL_3.GTPE2.PCS_RSVD_ATTR[36] origin:064-gtp-channel-conf 30_202 -GTP_CHANNEL_3.GTPE2.PCS_RSVD_ATTR[37] origin:064-gtp-channel-conf 31_202 -GTP_CHANNEL_3.GTPE2.PCS_RSVD_ATTR[38] origin:064-gtp-channel-conf 30_203 -GTP_CHANNEL_3.GTPE2.PCS_RSVD_ATTR[39] origin:064-gtp-channel-conf 31_203 -GTP_CHANNEL_3.GTPE2.PCS_RSVD_ATTR[40] origin:064-gtp-channel-conf 30_204 -GTP_CHANNEL_3.GTPE2.PCS_RSVD_ATTR[41] origin:064-gtp-channel-conf 31_204 -GTP_CHANNEL_3.GTPE2.PCS_RSVD_ATTR[42] origin:064-gtp-channel-conf 30_205 -GTP_CHANNEL_3.GTPE2.PCS_RSVD_ATTR[43] origin:064-gtp-channel-conf 31_205 -GTP_CHANNEL_3.GTPE2.PCS_RSVD_ATTR[44] origin:064-gtp-channel-conf 30_206 -GTP_CHANNEL_3.GTPE2.PCS_RSVD_ATTR[45] origin:064-gtp-channel-conf 31_206 -GTP_CHANNEL_3.GTPE2.PCS_RSVD_ATTR[46] origin:064-gtp-channel-conf 30_207 -GTP_CHANNEL_3.GTPE2.PCS_RSVD_ATTR[47] origin:064-gtp-channel-conf 31_207 -GTP_CHANNEL_3.GTPE2.PD_TRANS_TIME_FROM_P2[0] origin:064-gtp-channel-conf 29_216 -GTP_CHANNEL_3.GTPE2.PD_TRANS_TIME_FROM_P2[1] origin:064-gtp-channel-conf 28_217 -GTP_CHANNEL_3.GTPE2.PD_TRANS_TIME_FROM_P2[2] origin:064-gtp-channel-conf 29_217 -GTP_CHANNEL_3.GTPE2.PD_TRANS_TIME_FROM_P2[3] origin:064-gtp-channel-conf 28_218 -GTP_CHANNEL_3.GTPE2.PD_TRANS_TIME_FROM_P2[4] origin:064-gtp-channel-conf 29_218 -GTP_CHANNEL_3.GTPE2.PD_TRANS_TIME_FROM_P2[5] origin:064-gtp-channel-conf 28_219 -GTP_CHANNEL_3.GTPE2.PD_TRANS_TIME_FROM_P2[6] origin:064-gtp-channel-conf 29_219 -GTP_CHANNEL_3.GTPE2.PD_TRANS_TIME_FROM_P2[7] origin:064-gtp-channel-conf 28_220 -GTP_CHANNEL_3.GTPE2.PD_TRANS_TIME_FROM_P2[8] origin:064-gtp-channel-conf 29_220 -GTP_CHANNEL_3.GTPE2.PD_TRANS_TIME_FROM_P2[9] origin:064-gtp-channel-conf 28_221 -GTP_CHANNEL_3.GTPE2.PD_TRANS_TIME_FROM_P2[10] origin:064-gtp-channel-conf 29_221 -GTP_CHANNEL_3.GTPE2.PD_TRANS_TIME_FROM_P2[11] origin:064-gtp-channel-conf 28_222 -GTP_CHANNEL_3.GTPE2.PD_TRANS_TIME_NONE_P2[0] origin:064-gtp-channel-conf 28_208 -GTP_CHANNEL_3.GTPE2.PD_TRANS_TIME_NONE_P2[1] origin:064-gtp-channel-conf 29_208 -GTP_CHANNEL_3.GTPE2.PD_TRANS_TIME_NONE_P2[2] origin:064-gtp-channel-conf 28_209 -GTP_CHANNEL_3.GTPE2.PD_TRANS_TIME_NONE_P2[3] origin:064-gtp-channel-conf 29_209 -GTP_CHANNEL_3.GTPE2.PD_TRANS_TIME_NONE_P2[4] origin:064-gtp-channel-conf 28_210 -GTP_CHANNEL_3.GTPE2.PD_TRANS_TIME_NONE_P2[5] origin:064-gtp-channel-conf 29_210 -GTP_CHANNEL_3.GTPE2.PD_TRANS_TIME_NONE_P2[6] origin:064-gtp-channel-conf 28_211 -GTP_CHANNEL_3.GTPE2.PD_TRANS_TIME_NONE_P2[7] origin:064-gtp-channel-conf 29_211 -GTP_CHANNEL_3.GTPE2.PD_TRANS_TIME_TO_P2[0] origin:064-gtp-channel-conf 28_212 -GTP_CHANNEL_3.GTPE2.PD_TRANS_TIME_TO_P2[1] origin:064-gtp-channel-conf 29_212 -GTP_CHANNEL_3.GTPE2.PD_TRANS_TIME_TO_P2[2] origin:064-gtp-channel-conf 28_213 -GTP_CHANNEL_3.GTPE2.PD_TRANS_TIME_TO_P2[3] origin:064-gtp-channel-conf 29_213 -GTP_CHANNEL_3.GTPE2.PD_TRANS_TIME_TO_P2[4] origin:064-gtp-channel-conf 28_214 -GTP_CHANNEL_3.GTPE2.PD_TRANS_TIME_TO_P2[5] origin:064-gtp-channel-conf 29_214 -GTP_CHANNEL_3.GTPE2.PD_TRANS_TIME_TO_P2[6] origin:064-gtp-channel-conf 28_215 -GTP_CHANNEL_3.GTPE2.PD_TRANS_TIME_TO_P2[7] origin:064-gtp-channel-conf 29_215 -GTP_CHANNEL_3.GTPE2.PMA_LOOPBACK_CFG[0] origin:064-gtp-channel-conf 29_207 -GTP_CHANNEL_3.GTPE2.PMA_RSV[0] origin:064-gtp-channel-conf 30_520 -GTP_CHANNEL_3.GTPE2.PMA_RSV[1] origin:064-gtp-channel-conf 31_520 -GTP_CHANNEL_3.GTPE2.PMA_RSV[2] origin:064-gtp-channel-conf 30_521 -GTP_CHANNEL_3.GTPE2.PMA_RSV[3] origin:064-gtp-channel-conf 31_521 -GTP_CHANNEL_3.GTPE2.PMA_RSV[4] origin:064-gtp-channel-conf 30_522 -GTP_CHANNEL_3.GTPE2.PMA_RSV[5] origin:064-gtp-channel-conf 31_522 -GTP_CHANNEL_3.GTPE2.PMA_RSV[6] origin:064-gtp-channel-conf 30_523 -GTP_CHANNEL_3.GTPE2.PMA_RSV[7] origin:064-gtp-channel-conf 31_523 -GTP_CHANNEL_3.GTPE2.PMA_RSV[8] origin:064-gtp-channel-conf 30_524 -GTP_CHANNEL_3.GTPE2.PMA_RSV[9] origin:064-gtp-channel-conf 31_524 -GTP_CHANNEL_3.GTPE2.PMA_RSV[10] origin:064-gtp-channel-conf 30_525 -GTP_CHANNEL_3.GTPE2.PMA_RSV[11] origin:064-gtp-channel-conf 31_525 -GTP_CHANNEL_3.GTPE2.PMA_RSV[12] origin:064-gtp-channel-conf 30_526 -GTP_CHANNEL_3.GTPE2.PMA_RSV[13] origin:064-gtp-channel-conf 31_526 -GTP_CHANNEL_3.GTPE2.PMA_RSV[14] origin:064-gtp-channel-conf 30_527 -GTP_CHANNEL_3.GTPE2.PMA_RSV[15] origin:064-gtp-channel-conf 31_527 -GTP_CHANNEL_3.GTPE2.PMA_RSV[16] origin:064-gtp-channel-conf 30_528 -GTP_CHANNEL_3.GTPE2.PMA_RSV[17] origin:064-gtp-channel-conf 31_528 -GTP_CHANNEL_3.GTPE2.PMA_RSV[18] origin:064-gtp-channel-conf 30_529 -GTP_CHANNEL_3.GTPE2.PMA_RSV[19] origin:064-gtp-channel-conf 31_529 -GTP_CHANNEL_3.GTPE2.PMA_RSV[20] origin:064-gtp-channel-conf 30_530 -GTP_CHANNEL_3.GTPE2.PMA_RSV[21] origin:064-gtp-channel-conf 31_530 -GTP_CHANNEL_3.GTPE2.PMA_RSV[22] origin:064-gtp-channel-conf 30_531 -GTP_CHANNEL_3.GTPE2.PMA_RSV[23] origin:064-gtp-channel-conf 31_531 -GTP_CHANNEL_3.GTPE2.PMA_RSV[24] origin:064-gtp-channel-conf 30_532 -GTP_CHANNEL_3.GTPE2.PMA_RSV[25] origin:064-gtp-channel-conf 31_532 -GTP_CHANNEL_3.GTPE2.PMA_RSV[26] origin:064-gtp-channel-conf 30_533 -GTP_CHANNEL_3.GTPE2.PMA_RSV[27] origin:064-gtp-channel-conf 31_533 -GTP_CHANNEL_3.GTPE2.PMA_RSV[28] origin:064-gtp-channel-conf 30_534 -GTP_CHANNEL_3.GTPE2.PMA_RSV[29] origin:064-gtp-channel-conf 31_534 -GTP_CHANNEL_3.GTPE2.PMA_RSV[30] origin:064-gtp-channel-conf 30_535 -GTP_CHANNEL_3.GTPE2.PMA_RSV[31] origin:064-gtp-channel-conf 31_535 -GTP_CHANNEL_3.GTPE2.PMA_RSV2[0] origin:064-gtp-channel-conf 30_336 -GTP_CHANNEL_3.GTPE2.PMA_RSV2[1] origin:064-gtp-channel-conf 31_336 -GTP_CHANNEL_3.GTPE2.PMA_RSV2[2] origin:064-gtp-channel-conf 30_337 -GTP_CHANNEL_3.GTPE2.PMA_RSV2[3] origin:064-gtp-channel-conf 31_337 -GTP_CHANNEL_3.GTPE2.PMA_RSV2[4] origin:064-gtp-channel-conf 30_338 -GTP_CHANNEL_3.GTPE2.PMA_RSV2[5] origin:064-gtp-channel-conf 31_338 -GTP_CHANNEL_3.GTPE2.PMA_RSV2[6] origin:064-gtp-channel-conf 30_339 -GTP_CHANNEL_3.GTPE2.PMA_RSV2[7] origin:064-gtp-channel-conf 31_339 -GTP_CHANNEL_3.GTPE2.PMA_RSV2[8] origin:064-gtp-channel-conf 30_340 -GTP_CHANNEL_3.GTPE2.PMA_RSV2[9] origin:064-gtp-channel-conf 31_340 -GTP_CHANNEL_3.GTPE2.PMA_RSV2[10] origin:064-gtp-channel-conf 30_341 -GTP_CHANNEL_3.GTPE2.PMA_RSV2[11] origin:064-gtp-channel-conf 31_341 -GTP_CHANNEL_3.GTPE2.PMA_RSV2[12] origin:064-gtp-channel-conf 30_342 -GTP_CHANNEL_3.GTPE2.PMA_RSV2[13] origin:064-gtp-channel-conf 31_342 -GTP_CHANNEL_3.GTPE2.PMA_RSV2[14] origin:064-gtp-channel-conf 30_343 -GTP_CHANNEL_3.GTPE2.PMA_RSV2[15] origin:064-gtp-channel-conf 31_343 -GTP_CHANNEL_3.GTPE2.PMA_RSV2[16] origin:064-gtp-channel-conf 30_344 -GTP_CHANNEL_3.GTPE2.PMA_RSV2[17] origin:064-gtp-channel-conf 31_344 -GTP_CHANNEL_3.GTPE2.PMA_RSV2[18] origin:064-gtp-channel-conf 30_345 -GTP_CHANNEL_3.GTPE2.PMA_RSV2[19] origin:064-gtp-channel-conf 31_345 -GTP_CHANNEL_3.GTPE2.PMA_RSV2[20] origin:064-gtp-channel-conf 30_346 -GTP_CHANNEL_3.GTPE2.PMA_RSV2[21] origin:064-gtp-channel-conf 31_346 -GTP_CHANNEL_3.GTPE2.PMA_RSV2[22] origin:064-gtp-channel-conf 30_347 -GTP_CHANNEL_3.GTPE2.PMA_RSV2[23] origin:064-gtp-channel-conf 31_347 -GTP_CHANNEL_3.GTPE2.PMA_RSV2[24] origin:064-gtp-channel-conf 30_348 -GTP_CHANNEL_3.GTPE2.PMA_RSV2[25] origin:064-gtp-channel-conf 31_348 -GTP_CHANNEL_3.GTPE2.PMA_RSV2[26] origin:064-gtp-channel-conf 30_349 -GTP_CHANNEL_3.GTPE2.PMA_RSV2[27] origin:064-gtp-channel-conf 31_349 -GTP_CHANNEL_3.GTPE2.PMA_RSV2[28] origin:064-gtp-channel-conf 30_350 -GTP_CHANNEL_3.GTPE2.PMA_RSV2[29] origin:064-gtp-channel-conf 31_350 -GTP_CHANNEL_3.GTPE2.PMA_RSV2[30] origin:064-gtp-channel-conf 30_351 -GTP_CHANNEL_3.GTPE2.PMA_RSV2[31] origin:064-gtp-channel-conf 31_351 -GTP_CHANNEL_3.GTPE2.PMA_RSV3[0] origin:064-gtp-channel-conf 30_288 -GTP_CHANNEL_3.GTPE2.PMA_RSV3[1] origin:064-gtp-channel-conf 31_288 -GTP_CHANNEL_3.GTPE2.PMA_RSV4[0] origin:064-gtp-channel-conf 30_156 -GTP_CHANNEL_3.GTPE2.PMA_RSV4[1] origin:064-gtp-channel-conf 31_156 -GTP_CHANNEL_3.GTPE2.PMA_RSV4[2] origin:064-gtp-channel-conf 30_157 -GTP_CHANNEL_3.GTPE2.PMA_RSV4[3] origin:064-gtp-channel-conf 31_157 -GTP_CHANNEL_3.GTPE2.PMA_RSV5[0] origin:064-gtp-channel-conf 31_159 -GTP_CHANNEL_3.GTPE2.PMA_RSV6[0] origin:064-gtp-channel-conf 30_303 -GTP_CHANNEL_3.GTPE2.PMA_RSV7[0] origin:064-gtp-channel-conf 31_303 -GTP_CHANNEL_3.GTPE2.RX_BIAS_CFG[0] origin:064-gtp-channel-conf 30_112 -GTP_CHANNEL_3.GTPE2.RX_BIAS_CFG[1] origin:064-gtp-channel-conf 31_112 -GTP_CHANNEL_3.GTPE2.RX_BIAS_CFG[2] origin:064-gtp-channel-conf 30_113 -GTP_CHANNEL_3.GTPE2.RX_BIAS_CFG[3] origin:064-gtp-channel-conf 31_113 -GTP_CHANNEL_3.GTPE2.RX_BIAS_CFG[4] origin:064-gtp-channel-conf 30_114 -GTP_CHANNEL_3.GTPE2.RX_BIAS_CFG[5] origin:064-gtp-channel-conf 31_114 -GTP_CHANNEL_3.GTPE2.RX_BIAS_CFG[6] origin:064-gtp-channel-conf 30_115 -GTP_CHANNEL_3.GTPE2.RX_BIAS_CFG[7] origin:064-gtp-channel-conf 31_115 -GTP_CHANNEL_3.GTPE2.RX_BIAS_CFG[8] origin:064-gtp-channel-conf 30_116 -GTP_CHANNEL_3.GTPE2.RX_BIAS_CFG[9] origin:064-gtp-channel-conf 31_116 -GTP_CHANNEL_3.GTPE2.RX_BIAS_CFG[10] origin:064-gtp-channel-conf 30_117 -GTP_CHANNEL_3.GTPE2.RX_BIAS_CFG[11] origin:064-gtp-channel-conf 31_117 -GTP_CHANNEL_3.GTPE2.RX_BIAS_CFG[12] origin:064-gtp-channel-conf 30_118 -GTP_CHANNEL_3.GTPE2.RX_BIAS_CFG[13] origin:064-gtp-channel-conf 31_118 -GTP_CHANNEL_3.GTPE2.RX_BIAS_CFG[14] origin:064-gtp-channel-conf 30_119 -GTP_CHANNEL_3.GTPE2.RX_BIAS_CFG[15] origin:064-gtp-channel-conf 31_119 -GTP_CHANNEL_3.GTPE2.RX_BUFFER_CFG[0] origin:064-gtp-channel-conf 30_536 -GTP_CHANNEL_3.GTPE2.RX_BUFFER_CFG[1] origin:064-gtp-channel-conf 31_536 -GTP_CHANNEL_3.GTPE2.RX_BUFFER_CFG[2] origin:064-gtp-channel-conf 30_537 -GTP_CHANNEL_3.GTPE2.RX_BUFFER_CFG[3] origin:064-gtp-channel-conf 31_537 -GTP_CHANNEL_3.GTPE2.RX_BUFFER_CFG[4] origin:064-gtp-channel-conf 30_538 -GTP_CHANNEL_3.GTPE2.RX_BUFFER_CFG[5] origin:064-gtp-channel-conf 31_538 -GTP_CHANNEL_3.GTPE2.RX_CLKMUX_EN[0] origin:064-gtp-channel-conf 30_128 -GTP_CHANNEL_3.GTPE2.RX_CM_SEL[0] origin:064-gtp-channel-conf 28_138 -GTP_CHANNEL_3.GTPE2.RX_CM_SEL[1] origin:064-gtp-channel-conf 29_138 -GTP_CHANNEL_3.GTPE2.RX_CM_TRIM[0] origin:064-gtp-channel-conf 30_304 -GTP_CHANNEL_3.GTPE2.RX_CM_TRIM[1] origin:064-gtp-channel-conf 31_304 -GTP_CHANNEL_3.GTPE2.RX_CM_TRIM[2] origin:064-gtp-channel-conf 30_305 -GTP_CHANNEL_3.GTPE2.RX_CM_TRIM[3] origin:064-gtp-channel-conf 31_305 -GTP_CHANNEL_3.GTPE2.RX_DATA_WIDTH[0] origin:064-gtp-channel-conf 29_141 -GTP_CHANNEL_3.GTPE2.RX_DATA_WIDTH[1] origin:064-gtp-channel-conf 28_142 -GTP_CHANNEL_3.GTPE2.RX_DATA_WIDTH[2] origin:064-gtp-channel-conf 29_142 -GTP_CHANNEL_3.GTPE2.RX_DDI_SEL[0] origin:064-gtp-channel-conf 28_696 -GTP_CHANNEL_3.GTPE2.RX_DDI_SEL[1] origin:064-gtp-channel-conf 29_696 -GTP_CHANNEL_3.GTPE2.RX_DDI_SEL[2] origin:064-gtp-channel-conf 28_697 -GTP_CHANNEL_3.GTPE2.RX_DDI_SEL[3] origin:064-gtp-channel-conf 29_697 -GTP_CHANNEL_3.GTPE2.RX_DDI_SEL[4] origin:064-gtp-channel-conf 28_698 -GTP_CHANNEL_3.GTPE2.RX_DDI_SEL[5] origin:064-gtp-channel-conf 29_698 -GTP_CHANNEL_3.GTPE2.RX_DEBUG_CFG[0] origin:064-gtp-channel-conf 30_616 -GTP_CHANNEL_3.GTPE2.RX_DEBUG_CFG[1] origin:064-gtp-channel-conf 31_616 -GTP_CHANNEL_3.GTPE2.RX_DEBUG_CFG[2] origin:064-gtp-channel-conf 30_617 -GTP_CHANNEL_3.GTPE2.RX_DEBUG_CFG[3] origin:064-gtp-channel-conf 31_617 -GTP_CHANNEL_3.GTPE2.RX_DEBUG_CFG[4] origin:064-gtp-channel-conf 30_618 -GTP_CHANNEL_3.GTPE2.RX_DEBUG_CFG[5] origin:064-gtp-channel-conf 31_618 -GTP_CHANNEL_3.GTPE2.RX_DEBUG_CFG[6] origin:064-gtp-channel-conf 30_619 -GTP_CHANNEL_3.GTPE2.RX_DEBUG_CFG[7] origin:064-gtp-channel-conf 31_619 -GTP_CHANNEL_3.GTPE2.RX_DEBUG_CFG[8] origin:064-gtp-channel-conf 30_620 -GTP_CHANNEL_3.GTPE2.RX_DEBUG_CFG[9] origin:064-gtp-channel-conf 31_620 -GTP_CHANNEL_3.GTPE2.RX_DEBUG_CFG[10] origin:064-gtp-channel-conf 30_621 -GTP_CHANNEL_3.GTPE2.RX_DEBUG_CFG[11] origin:064-gtp-channel-conf 31_621 -GTP_CHANNEL_3.GTPE2.RX_DEBUG_CFG[12] origin:064-gtp-channel-conf 30_622 -GTP_CHANNEL_3.GTPE2.RX_DEBUG_CFG[13] origin:064-gtp-channel-conf 31_622 -GTP_CHANNEL_3.GTPE2.RX_DEFER_RESET_BUF_EN origin:064-gtp-channel-conf 30_552 -GTP_CHANNEL_3.GTPE2.RX_DISPERR_SEQ_MATCH origin:064-gtp-channel-conf 29_495 -GTP_CHANNEL_3.GTPE2.RX_OS_CFG[0] origin:064-gtp-channel-conf 28_288 -GTP_CHANNEL_3.GTPE2.RX_OS_CFG[1] origin:064-gtp-channel-conf 29_288 -GTP_CHANNEL_3.GTPE2.RX_OS_CFG[2] origin:064-gtp-channel-conf 28_289 -GTP_CHANNEL_3.GTPE2.RX_OS_CFG[3] origin:064-gtp-channel-conf 29_289 -GTP_CHANNEL_3.GTPE2.RX_OS_CFG[4] origin:064-gtp-channel-conf 28_290 -GTP_CHANNEL_3.GTPE2.RX_OS_CFG[5] origin:064-gtp-channel-conf 29_290 -GTP_CHANNEL_3.GTPE2.RX_OS_CFG[6] origin:064-gtp-channel-conf 28_291 -GTP_CHANNEL_3.GTPE2.RX_OS_CFG[7] origin:064-gtp-channel-conf 29_291 -GTP_CHANNEL_3.GTPE2.RX_OS_CFG[8] origin:064-gtp-channel-conf 28_292 -GTP_CHANNEL_3.GTPE2.RX_OS_CFG[9] origin:064-gtp-channel-conf 29_292 -GTP_CHANNEL_3.GTPE2.RX_OS_CFG[10] origin:064-gtp-channel-conf 28_293 -GTP_CHANNEL_3.GTPE2.RX_OS_CFG[11] origin:064-gtp-channel-conf 29_293 -GTP_CHANNEL_3.GTPE2.RX_OS_CFG[12] origin:064-gtp-channel-conf 28_294 -GTP_CHANNEL_3.GTPE2.RX_SIG_VALID_DLY[0] origin:064-gtp-channel-conf 28_524 -GTP_CHANNEL_3.GTPE2.RX_SIG_VALID_DLY[1] origin:064-gtp-channel-conf 29_524 -GTP_CHANNEL_3.GTPE2.RX_SIG_VALID_DLY[2] origin:064-gtp-channel-conf 28_525 -GTP_CHANNEL_3.GTPE2.RX_SIG_VALID_DLY[3] origin:064-gtp-channel-conf 29_525 -GTP_CHANNEL_3.GTPE2.RX_SIG_VALID_DLY[4] origin:064-gtp-channel-conf 28_526 -GTP_CHANNEL_3.GTPE2.RX_XCLK_SEL.RXUSR origin:064-gtp-channel-conf 28_143 -GTP_CHANNEL_3.GTPE2.RX_CLK25_DIV[0] origin:064-gtp-channel-conf 28_139 -GTP_CHANNEL_3.GTPE2.RX_CLK25_DIV[1] origin:064-gtp-channel-conf 29_139 -GTP_CHANNEL_3.GTPE2.RX_CLK25_DIV[2] origin:064-gtp-channel-conf 28_140 -GTP_CHANNEL_3.GTPE2.RX_CLK25_DIV[3] origin:064-gtp-channel-conf 29_140 -GTP_CHANNEL_3.GTPE2.RX_CLK25_DIV[4] origin:064-gtp-channel-conf 28_141 -GTP_CHANNEL_3.GTPE2.RXBUF_ADDR_MODE.FAST origin:064-gtp-channel-conf 31_555 -GTP_CHANNEL_3.GTPE2.RXBUF_EIDLE_HI_CNT[0] origin:064-gtp-channel-conf 30_558 -GTP_CHANNEL_3.GTPE2.RXBUF_EIDLE_HI_CNT[1] origin:064-gtp-channel-conf 31_558 -GTP_CHANNEL_3.GTPE2.RXBUF_EIDLE_HI_CNT[2] origin:064-gtp-channel-conf 30_559 -GTP_CHANNEL_3.GTPE2.RXBUF_EIDLE_HI_CNT[3] origin:064-gtp-channel-conf 31_559 -GTP_CHANNEL_3.GTPE2.RXBUF_EIDLE_LO_CNT[0] origin:064-gtp-channel-conf 30_556 -GTP_CHANNEL_3.GTPE2.RXBUF_EIDLE_LO_CNT[1] origin:064-gtp-channel-conf 31_556 -GTP_CHANNEL_3.GTPE2.RXBUF_EIDLE_LO_CNT[2] origin:064-gtp-channel-conf 30_557 -GTP_CHANNEL_3.GTPE2.RXBUF_EIDLE_LO_CNT[3] origin:064-gtp-channel-conf 31_557 -GTP_CHANNEL_3.GTPE2.RXBUF_EN origin:064-gtp-channel-conf 30_11 -GTP_CHANNEL_3.GTPE2.RXBUF_RESET_ON_CB_CHANGE origin:064-gtp-channel-conf 30_560 -GTP_CHANNEL_3.GTPE2.RXBUF_RESET_ON_COMMAALIGN origin:064-gtp-channel-conf 30_561 -GTP_CHANNEL_3.GTPE2.RXBUF_RESET_ON_EIDLE origin:064-gtp-channel-conf 30_547 -GTP_CHANNEL_3.GTPE2.RXBUF_RESET_ON_RATE_CHANGE origin:064-gtp-channel-conf 31_560 -GTP_CHANNEL_3.GTPE2.RXBUF_THRESH_OVFLW[0] origin:064-gtp-channel-conf 31_552 -GTP_CHANNEL_3.GTPE2.RXBUF_THRESH_OVFLW[1] origin:064-gtp-channel-conf 30_553 -GTP_CHANNEL_3.GTPE2.RXBUF_THRESH_OVFLW[2] origin:064-gtp-channel-conf 31_553 -GTP_CHANNEL_3.GTPE2.RXBUF_THRESH_OVFLW[3] origin:064-gtp-channel-conf 30_554 -GTP_CHANNEL_3.GTPE2.RXBUF_THRESH_OVFLW[4] origin:064-gtp-channel-conf 31_554 -GTP_CHANNEL_3.GTPE2.RXBUF_THRESH_OVFLW[5] origin:064-gtp-channel-conf 30_555 -GTP_CHANNEL_3.GTPE2.RXBUF_THRESH_OVRD origin:064-gtp-channel-conf 30_548 -GTP_CHANNEL_3.GTPE2.RXBUF_THRESH_UNDFLW[0] origin:064-gtp-channel-conf 30_544 -GTP_CHANNEL_3.GTPE2.RXBUF_THRESH_UNDFLW[1] origin:064-gtp-channel-conf 31_544 -GTP_CHANNEL_3.GTPE2.RXBUF_THRESH_UNDFLW[2] origin:064-gtp-channel-conf 30_545 -GTP_CHANNEL_3.GTPE2.RXBUF_THRESH_UNDFLW[3] origin:064-gtp-channel-conf 31_545 -GTP_CHANNEL_3.GTPE2.RXBUF_THRESH_UNDFLW[4] origin:064-gtp-channel-conf 30_546 -GTP_CHANNEL_3.GTPE2.RXBUF_THRESH_UNDFLW[5] origin:064-gtp-channel-conf 31_546 -GTP_CHANNEL_3.GTPE2.RXBUFRESET_TIME[0] origin:064-gtp-channel-conf 29_101 -GTP_CHANNEL_3.GTPE2.RXBUFRESET_TIME[1] origin:064-gtp-channel-conf 28_102 -GTP_CHANNEL_3.GTPE2.RXBUFRESET_TIME[2] origin:064-gtp-channel-conf 29_102 -GTP_CHANNEL_3.GTPE2.RXBUFRESET_TIME[3] origin:064-gtp-channel-conf 28_103 -GTP_CHANNEL_3.GTPE2.RXBUFRESET_TIME[4] origin:064-gtp-channel-conf 29_103 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[0] origin:064-gtp-channel-conf 30_640 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[1] origin:064-gtp-channel-conf 31_640 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[2] origin:064-gtp-channel-conf 30_641 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[3] origin:064-gtp-channel-conf 31_641 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[4] origin:064-gtp-channel-conf 30_642 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[5] origin:064-gtp-channel-conf 31_642 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[6] origin:064-gtp-channel-conf 30_643 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[7] origin:064-gtp-channel-conf 31_643 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[8] origin:064-gtp-channel-conf 30_644 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[9] origin:064-gtp-channel-conf 31_644 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[10] origin:064-gtp-channel-conf 30_645 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[11] origin:064-gtp-channel-conf 31_645 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[12] origin:064-gtp-channel-conf 30_646 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[13] origin:064-gtp-channel-conf 31_646 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[14] origin:064-gtp-channel-conf 30_647 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[15] origin:064-gtp-channel-conf 31_647 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[16] origin:064-gtp-channel-conf 30_648 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[17] origin:064-gtp-channel-conf 31_648 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[18] origin:064-gtp-channel-conf 30_649 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[19] origin:064-gtp-channel-conf 31_649 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[20] origin:064-gtp-channel-conf 30_650 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[21] origin:064-gtp-channel-conf 31_650 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[22] origin:064-gtp-channel-conf 30_651 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[23] origin:064-gtp-channel-conf 31_651 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[24] origin:064-gtp-channel-conf 30_652 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[25] origin:064-gtp-channel-conf 31_652 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[26] origin:064-gtp-channel-conf 30_653 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[27] origin:064-gtp-channel-conf 31_653 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[28] origin:064-gtp-channel-conf 30_654 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[29] origin:064-gtp-channel-conf 31_654 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[30] origin:064-gtp-channel-conf 30_655 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[31] origin:064-gtp-channel-conf 31_655 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[32] origin:064-gtp-channel-conf 30_656 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[33] origin:064-gtp-channel-conf 31_656 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[34] origin:064-gtp-channel-conf 30_657 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[35] origin:064-gtp-channel-conf 31_657 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[36] origin:064-gtp-channel-conf 30_658 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[37] origin:064-gtp-channel-conf 31_658 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[38] origin:064-gtp-channel-conf 30_659 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[39] origin:064-gtp-channel-conf 31_659 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[40] origin:064-gtp-channel-conf 30_660 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[41] origin:064-gtp-channel-conf 31_660 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[42] origin:064-gtp-channel-conf 30_661 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[43] origin:064-gtp-channel-conf 31_661 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[44] origin:064-gtp-channel-conf 30_662 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[45] origin:064-gtp-channel-conf 31_662 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[46] origin:064-gtp-channel-conf 30_663 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[47] origin:064-gtp-channel-conf 31_663 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[48] origin:064-gtp-channel-conf 30_664 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[49] origin:064-gtp-channel-conf 31_664 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[50] origin:064-gtp-channel-conf 30_665 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[51] origin:064-gtp-channel-conf 31_665 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[52] origin:064-gtp-channel-conf 30_666 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[53] origin:064-gtp-channel-conf 31_666 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[54] origin:064-gtp-channel-conf 30_667 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[55] origin:064-gtp-channel-conf 31_667 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[56] origin:064-gtp-channel-conf 30_668 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[57] origin:064-gtp-channel-conf 31_668 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[58] origin:064-gtp-channel-conf 30_669 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[59] origin:064-gtp-channel-conf 31_669 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[60] origin:064-gtp-channel-conf 30_670 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[61] origin:064-gtp-channel-conf 31_670 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[62] origin:064-gtp-channel-conf 30_671 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[63] origin:064-gtp-channel-conf 31_671 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[64] origin:064-gtp-channel-conf 30_672 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[65] origin:064-gtp-channel-conf 31_672 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[66] origin:064-gtp-channel-conf 30_673 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[67] origin:064-gtp-channel-conf 31_673 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[68] origin:064-gtp-channel-conf 30_674 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[69] origin:064-gtp-channel-conf 31_674 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[70] origin:064-gtp-channel-conf 30_675 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[71] origin:064-gtp-channel-conf 31_675 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[72] origin:064-gtp-channel-conf 30_676 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[73] origin:064-gtp-channel-conf 31_676 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[74] origin:064-gtp-channel-conf 30_677 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[75] origin:064-gtp-channel-conf 31_677 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[76] origin:064-gtp-channel-conf 30_678 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[77] origin:064-gtp-channel-conf 31_678 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[78] origin:064-gtp-channel-conf 30_679 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[79] origin:064-gtp-channel-conf 31_679 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[80] origin:064-gtp-channel-conf 30_680 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[81] origin:064-gtp-channel-conf 31_680 -GTP_CHANNEL_3.GTPE2.RXCDR_CFG[82] origin:064-gtp-channel-conf 30_681 -GTP_CHANNEL_3.GTPE2.RXCDR_FR_RESET_ON_EIDLE[0] origin:064-gtp-channel-conf 30_638 -GTP_CHANNEL_3.GTPE2.RXCDR_HOLD_DURING_EIDLE[0] origin:064-gtp-channel-conf 31_637 -GTP_CHANNEL_3.GTPE2.RXCDR_LOCK_CFG[0] origin:064-gtp-channel-conf 30_632 -GTP_CHANNEL_3.GTPE2.RXCDR_LOCK_CFG[1] origin:064-gtp-channel-conf 31_632 -GTP_CHANNEL_3.GTPE2.RXCDR_LOCK_CFG[2] origin:064-gtp-channel-conf 30_633 -GTP_CHANNEL_3.GTPE2.RXCDR_LOCK_CFG[3] origin:064-gtp-channel-conf 31_633 -GTP_CHANNEL_3.GTPE2.RXCDR_LOCK_CFG[4] origin:064-gtp-channel-conf 30_634 -GTP_CHANNEL_3.GTPE2.RXCDR_LOCK_CFG[5] origin:064-gtp-channel-conf 31_634 -GTP_CHANNEL_3.GTPE2.RXCDR_PH_RESET_ON_EIDLE[0] origin:064-gtp-channel-conf 31_638 -GTP_CHANNEL_3.GTPE2.RXCDRFREQRESET_TIME[0] origin:064-gtp-channel-conf 29_106 -GTP_CHANNEL_3.GTPE2.RXCDRFREQRESET_TIME[1] origin:064-gtp-channel-conf 28_107 -GTP_CHANNEL_3.GTPE2.RXCDRFREQRESET_TIME[2] origin:064-gtp-channel-conf 29_107 -GTP_CHANNEL_3.GTPE2.RXCDRFREQRESET_TIME[3] origin:064-gtp-channel-conf 28_108 -GTP_CHANNEL_3.GTPE2.RXCDRFREQRESET_TIME[4] origin:064-gtp-channel-conf 29_108 -GTP_CHANNEL_3.GTPE2.RXCDRPHRESET_TIME[0] origin:064-gtp-channel-conf 28_109 -GTP_CHANNEL_3.GTPE2.RXCDRPHRESET_TIME[1] origin:064-gtp-channel-conf 29_109 -GTP_CHANNEL_3.GTPE2.RXCDRPHRESET_TIME[2] origin:064-gtp-channel-conf 28_110 -GTP_CHANNEL_3.GTPE2.RXCDRPHRESET_TIME[3] origin:064-gtp-channel-conf 29_110 -GTP_CHANNEL_3.GTPE2.RXCDRPHRESET_TIME[4] origin:064-gtp-channel-conf 28_111 -GTP_CHANNEL_3.GTPE2.RXDLY_CFG[0] origin:064-gtp-channel-conf 28_680 -GTP_CHANNEL_3.GTPE2.RXDLY_CFG[1] origin:064-gtp-channel-conf 29_680 -GTP_CHANNEL_3.GTPE2.RXDLY_CFG[2] origin:064-gtp-channel-conf 28_681 -GTP_CHANNEL_3.GTPE2.RXDLY_CFG[3] origin:064-gtp-channel-conf 29_681 -GTP_CHANNEL_3.GTPE2.RXDLY_CFG[4] origin:064-gtp-channel-conf 28_682 -GTP_CHANNEL_3.GTPE2.RXDLY_CFG[5] origin:064-gtp-channel-conf 29_682 -GTP_CHANNEL_3.GTPE2.RXDLY_CFG[6] origin:064-gtp-channel-conf 28_683 -GTP_CHANNEL_3.GTPE2.RXDLY_CFG[7] origin:064-gtp-channel-conf 29_683 -GTP_CHANNEL_3.GTPE2.RXDLY_CFG[8] origin:064-gtp-channel-conf 28_684 -GTP_CHANNEL_3.GTPE2.RXDLY_CFG[9] origin:064-gtp-channel-conf 29_684 -GTP_CHANNEL_3.GTPE2.RXDLY_CFG[10] origin:064-gtp-channel-conf 28_685 -GTP_CHANNEL_3.GTPE2.RXDLY_CFG[11] origin:064-gtp-channel-conf 29_685 -GTP_CHANNEL_3.GTPE2.RXDLY_CFG[12] origin:064-gtp-channel-conf 28_686 -GTP_CHANNEL_3.GTPE2.RXDLY_CFG[13] origin:064-gtp-channel-conf 29_686 -GTP_CHANNEL_3.GTPE2.RXDLY_CFG[14] origin:064-gtp-channel-conf 28_687 -GTP_CHANNEL_3.GTPE2.RXDLY_CFG[15] origin:064-gtp-channel-conf 29_687 -GTP_CHANNEL_3.GTPE2.RXDLY_LCFG[0] origin:064-gtp-channel-conf 30_576 -GTP_CHANNEL_3.GTPE2.RXDLY_LCFG[1] origin:064-gtp-channel-conf 31_576 -GTP_CHANNEL_3.GTPE2.RXDLY_LCFG[2] origin:064-gtp-channel-conf 30_577 -GTP_CHANNEL_3.GTPE2.RXDLY_LCFG[3] origin:064-gtp-channel-conf 31_577 -GTP_CHANNEL_3.GTPE2.RXDLY_LCFG[4] origin:064-gtp-channel-conf 30_578 -GTP_CHANNEL_3.GTPE2.RXDLY_LCFG[5] origin:064-gtp-channel-conf 31_578 -GTP_CHANNEL_3.GTPE2.RXDLY_LCFG[6] origin:064-gtp-channel-conf 30_579 -GTP_CHANNEL_3.GTPE2.RXDLY_LCFG[7] origin:064-gtp-channel-conf 31_579 -GTP_CHANNEL_3.GTPE2.RXDLY_LCFG[8] origin:064-gtp-channel-conf 30_580 -GTP_CHANNEL_3.GTPE2.RXDLY_TAP_CFG[0] origin:064-gtp-channel-conf 28_672 -GTP_CHANNEL_3.GTPE2.RXDLY_TAP_CFG[1] origin:064-gtp-channel-conf 29_672 -GTP_CHANNEL_3.GTPE2.RXDLY_TAP_CFG[2] origin:064-gtp-channel-conf 28_673 -GTP_CHANNEL_3.GTPE2.RXDLY_TAP_CFG[3] origin:064-gtp-channel-conf 29_673 -GTP_CHANNEL_3.GTPE2.RXDLY_TAP_CFG[4] origin:064-gtp-channel-conf 28_674 -GTP_CHANNEL_3.GTPE2.RXDLY_TAP_CFG[5] origin:064-gtp-channel-conf 29_674 -GTP_CHANNEL_3.GTPE2.RXDLY_TAP_CFG[6] origin:064-gtp-channel-conf 28_675 -GTP_CHANNEL_3.GTPE2.RXDLY_TAP_CFG[7] origin:064-gtp-channel-conf 29_675 -GTP_CHANNEL_3.GTPE2.RXDLY_TAP_CFG[8] origin:064-gtp-channel-conf 28_676 -GTP_CHANNEL_3.GTPE2.RXDLY_TAP_CFG[9] origin:064-gtp-channel-conf 29_676 -GTP_CHANNEL_3.GTPE2.RXDLY_TAP_CFG[10] origin:064-gtp-channel-conf 28_677 -GTP_CHANNEL_3.GTPE2.RXDLY_TAP_CFG[11] origin:064-gtp-channel-conf 29_677 -GTP_CHANNEL_3.GTPE2.RXDLY_TAP_CFG[12] origin:064-gtp-channel-conf 28_678 -GTP_CHANNEL_3.GTPE2.RXDLY_TAP_CFG[13] origin:064-gtp-channel-conf 29_678 -GTP_CHANNEL_3.GTPE2.RXDLY_TAP_CFG[14] origin:064-gtp-channel-conf 28_679 -GTP_CHANNEL_3.GTPE2.RXDLY_TAP_CFG[15] origin:064-gtp-channel-conf 29_679 -GTP_CHANNEL_3.GTPE2.RXGEARBOX_EN origin:064-gtp-channel-conf 29_607 -GTP_CHANNEL_3.GTPE2.RXISCANRESET_TIME[0] origin:064-gtp-channel-conf 29_123 -GTP_CHANNEL_3.GTPE2.RXISCANRESET_TIME[1] origin:064-gtp-channel-conf 28_124 -GTP_CHANNEL_3.GTPE2.RXISCANRESET_TIME[2] origin:064-gtp-channel-conf 29_124 -GTP_CHANNEL_3.GTPE2.RXISCANRESET_TIME[3] origin:064-gtp-channel-conf 28_125 -GTP_CHANNEL_3.GTPE2.RXISCANRESET_TIME[4] origin:064-gtp-channel-conf 29_125 -GTP_CHANNEL_3.GTPE2.RXLPM_BIAS_STARTUP_DISABLE[0] origin:064-gtp-channel-conf 31_391 -GTP_CHANNEL_3.GTPE2.RXLPM_CFG[0] origin:064-gtp-channel-conf 30_328 -GTP_CHANNEL_3.GTPE2.RXLPM_CFG[1] origin:064-gtp-channel-conf 31_328 -GTP_CHANNEL_3.GTPE2.RXLPM_CFG[2] origin:064-gtp-channel-conf 30_329 -GTP_CHANNEL_3.GTPE2.RXLPM_CFG[3] origin:064-gtp-channel-conf 31_329 -GTP_CHANNEL_3.GTPE2.RXLPM_CM_CFG[0] origin:064-gtp-channel-conf 30_430 -GTP_CHANNEL_3.GTPE2.RXLPM_GC_CFG[0] origin:064-gtp-channel-conf 30_432 -GTP_CHANNEL_3.GTPE2.RXLPM_GC_CFG[1] origin:064-gtp-channel-conf 31_432 -GTP_CHANNEL_3.GTPE2.RXLPM_GC_CFG[2] origin:064-gtp-channel-conf 30_433 -GTP_CHANNEL_3.GTPE2.RXLPM_GC_CFG[3] origin:064-gtp-channel-conf 31_433 -GTP_CHANNEL_3.GTPE2.RXLPM_GC_CFG[4] origin:064-gtp-channel-conf 30_434 -GTP_CHANNEL_3.GTPE2.RXLPM_GC_CFG[5] origin:064-gtp-channel-conf 31_434 -GTP_CHANNEL_3.GTPE2.RXLPM_GC_CFG[6] origin:064-gtp-channel-conf 30_435 -GTP_CHANNEL_3.GTPE2.RXLPM_GC_CFG[7] origin:064-gtp-channel-conf 31_435 -GTP_CHANNEL_3.GTPE2.RXLPM_GC_CFG[8] origin:064-gtp-channel-conf 30_436 -GTP_CHANNEL_3.GTPE2.RXLPM_GC_CFG2[0] origin:064-gtp-channel-conf 31_442 -GTP_CHANNEL_3.GTPE2.RXLPM_GC_CFG2[1] origin:064-gtp-channel-conf 30_443 -GTP_CHANNEL_3.GTPE2.RXLPM_GC_CFG2[2] origin:064-gtp-channel-conf 31_443 -GTP_CHANNEL_3.GTPE2.RXLPM_HF_CFG[0] origin:064-gtp-channel-conf 28_336 -GTP_CHANNEL_3.GTPE2.RXLPM_HF_CFG[1] origin:064-gtp-channel-conf 29_336 -GTP_CHANNEL_3.GTPE2.RXLPM_HF_CFG[2] origin:064-gtp-channel-conf 28_337 -GTP_CHANNEL_3.GTPE2.RXLPM_HF_CFG[3] origin:064-gtp-channel-conf 29_337 -GTP_CHANNEL_3.GTPE2.RXLPM_HF_CFG[4] origin:064-gtp-channel-conf 28_338 -GTP_CHANNEL_3.GTPE2.RXLPM_HF_CFG[5] origin:064-gtp-channel-conf 29_338 -GTP_CHANNEL_3.GTPE2.RXLPM_HF_CFG[6] origin:064-gtp-channel-conf 28_339 -GTP_CHANNEL_3.GTPE2.RXLPM_HF_CFG[7] origin:064-gtp-channel-conf 29_339 -GTP_CHANNEL_3.GTPE2.RXLPM_HF_CFG[8] origin:064-gtp-channel-conf 28_340 -GTP_CHANNEL_3.GTPE2.RXLPM_HF_CFG[9] origin:064-gtp-channel-conf 29_340 -GTP_CHANNEL_3.GTPE2.RXLPM_HF_CFG[10] origin:064-gtp-channel-conf 28_341 -GTP_CHANNEL_3.GTPE2.RXLPM_HF_CFG[11] origin:064-gtp-channel-conf 29_341 -GTP_CHANNEL_3.GTPE2.RXLPM_HF_CFG[12] origin:064-gtp-channel-conf 28_342 -GTP_CHANNEL_3.GTPE2.RXLPM_HF_CFG[13] origin:064-gtp-channel-conf 29_342 -GTP_CHANNEL_3.GTPE2.RXLPM_HF_CFG2[0] origin:064-gtp-channel-conf 30_424 -GTP_CHANNEL_3.GTPE2.RXLPM_HF_CFG2[1] origin:064-gtp-channel-conf 31_424 -GTP_CHANNEL_3.GTPE2.RXLPM_HF_CFG2[2] origin:064-gtp-channel-conf 30_425 -GTP_CHANNEL_3.GTPE2.RXLPM_HF_CFG2[3] origin:064-gtp-channel-conf 31_425 -GTP_CHANNEL_3.GTPE2.RXLPM_HF_CFG2[4] origin:064-gtp-channel-conf 30_426 -GTP_CHANNEL_3.GTPE2.RXLPM_HF_CFG3[0] origin:064-gtp-channel-conf 31_389 -GTP_CHANNEL_3.GTPE2.RXLPM_HF_CFG3[1] origin:064-gtp-channel-conf 30_390 -GTP_CHANNEL_3.GTPE2.RXLPM_HF_CFG3[2] origin:064-gtp-channel-conf 31_390 -GTP_CHANNEL_3.GTPE2.RXLPM_HF_CFG3[3] origin:064-gtp-channel-conf 30_391 -GTP_CHANNEL_3.GTPE2.RXLPM_HOLD_DURING_EIDLE[0] origin:064-gtp-channel-conf 28_247 -GTP_CHANNEL_3.GTPE2.RXLPM_INCM_CFG[0] origin:064-gtp-channel-conf 30_439 -GTP_CHANNEL_3.GTPE2.RXLPM_IPCM_CFG[0] origin:064-gtp-channel-conf 31_439 -GTP_CHANNEL_3.GTPE2.RXLPM_LF_CFG[0] origin:064-gtp-channel-conf 28_344 -GTP_CHANNEL_3.GTPE2.RXLPM_LF_CFG[1] origin:064-gtp-channel-conf 29_344 -GTP_CHANNEL_3.GTPE2.RXLPM_LF_CFG[2] origin:064-gtp-channel-conf 28_345 -GTP_CHANNEL_3.GTPE2.RXLPM_LF_CFG[3] origin:064-gtp-channel-conf 29_345 -GTP_CHANNEL_3.GTPE2.RXLPM_LF_CFG[4] origin:064-gtp-channel-conf 28_346 -GTP_CHANNEL_3.GTPE2.RXLPM_LF_CFG[5] origin:064-gtp-channel-conf 29_346 -GTP_CHANNEL_3.GTPE2.RXLPM_LF_CFG[6] origin:064-gtp-channel-conf 28_347 -GTP_CHANNEL_3.GTPE2.RXLPM_LF_CFG[7] origin:064-gtp-channel-conf 29_347 -GTP_CHANNEL_3.GTPE2.RXLPM_LF_CFG[8] origin:064-gtp-channel-conf 28_348 -GTP_CHANNEL_3.GTPE2.RXLPM_LF_CFG[9] origin:064-gtp-channel-conf 29_348 -GTP_CHANNEL_3.GTPE2.RXLPM_LF_CFG[10] origin:064-gtp-channel-conf 28_349 -GTP_CHANNEL_3.GTPE2.RXLPM_LF_CFG[11] origin:064-gtp-channel-conf 29_349 -GTP_CHANNEL_3.GTPE2.RXLPM_LF_CFG[12] origin:064-gtp-channel-conf 28_350 -GTP_CHANNEL_3.GTPE2.RXLPM_LF_CFG[13] origin:064-gtp-channel-conf 29_350 -GTP_CHANNEL_3.GTPE2.RXLPM_LF_CFG[14] origin:064-gtp-channel-conf 28_351 -GTP_CHANNEL_3.GTPE2.RXLPM_LF_CFG[15] origin:064-gtp-channel-conf 29_351 -GTP_CHANNEL_3.GTPE2.RXLPM_LF_CFG[16] origin:064-gtp-channel-conf 28_343 -GTP_CHANNEL_3.GTPE2.RXLPM_LF_CFG[17] origin:064-gtp-channel-conf 29_343 -GTP_CHANNEL_3.GTPE2.RXLPM_LF_CFG2[0] origin:064-gtp-channel-conf 31_426 -GTP_CHANNEL_3.GTPE2.RXLPM_LF_CFG2[1] origin:064-gtp-channel-conf 30_427 -GTP_CHANNEL_3.GTPE2.RXLPM_LF_CFG2[2] origin:064-gtp-channel-conf 31_427 -GTP_CHANNEL_3.GTPE2.RXLPM_LF_CFG2[3] origin:064-gtp-channel-conf 30_428 -GTP_CHANNEL_3.GTPE2.RXLPM_LF_CFG2[4] origin:064-gtp-channel-conf 31_428 -GTP_CHANNEL_3.GTPE2.RXLPM_OSINT_CFG[0] origin:064-gtp-channel-conf 30_440 -GTP_CHANNEL_3.GTPE2.RXLPM_OSINT_CFG[1] origin:064-gtp-channel-conf 31_440 -GTP_CHANNEL_3.GTPE2.RXLPM_OSINT_CFG[2] origin:064-gtp-channel-conf 30_441 -GTP_CHANNEL_3.GTPE2.RXLPM_CFG1[0] origin:064-gtp-channel-conf 30_330 -GTP_CHANNEL_3.GTPE2.RXLPMRESET_TIME[0] origin:064-gtp-channel-conf 28_112 -GTP_CHANNEL_3.GTPE2.RXLPMRESET_TIME[1] origin:064-gtp-channel-conf 29_112 -GTP_CHANNEL_3.GTPE2.RXLPMRESET_TIME[2] origin:064-gtp-channel-conf 28_113 -GTP_CHANNEL_3.GTPE2.RXLPMRESET_TIME[3] origin:064-gtp-channel-conf 29_113 -GTP_CHANNEL_3.GTPE2.RXLPMRESET_TIME[4] origin:064-gtp-channel-conf 28_114 -GTP_CHANNEL_3.GTPE2.RXLPMRESET_TIME[5] origin:064-gtp-channel-conf 29_114 -GTP_CHANNEL_3.GTPE2.RXLPMRESET_TIME[6] origin:064-gtp-channel-conf 28_115 -GTP_CHANNEL_3.GTPE2.RXOOB_CFG[0] origin:064-gtp-channel-conf 28_144 -GTP_CHANNEL_3.GTPE2.RXOOB_CFG[1] origin:064-gtp-channel-conf 29_144 -GTP_CHANNEL_3.GTPE2.RXOOB_CFG[2] origin:064-gtp-channel-conf 28_145 -GTP_CHANNEL_3.GTPE2.RXOOB_CFG[3] origin:064-gtp-channel-conf 29_145 -GTP_CHANNEL_3.GTPE2.RXOOB_CFG[4] origin:064-gtp-channel-conf 28_146 -GTP_CHANNEL_3.GTPE2.RXOOB_CFG[5] origin:064-gtp-channel-conf 29_146 -GTP_CHANNEL_3.GTPE2.RXOOB_CFG[6] origin:064-gtp-channel-conf 28_147 -GTP_CHANNEL_3.GTPE2.RXOOB_CLK_CFG.FABRIC origin:064-gtp-channel-conf 31_129 -GTP_CHANNEL_3.GTPE2.RXOSCALRESET_TIME[0] origin:064-gtp-channel-conf 28_187 -GTP_CHANNEL_3.GTPE2.RXOSCALRESET_TIME[1] origin:064-gtp-channel-conf 29_187 -GTP_CHANNEL_3.GTPE2.RXOSCALRESET_TIME[2] origin:064-gtp-channel-conf 28_188 -GTP_CHANNEL_3.GTPE2.RXOSCALRESET_TIME[3] origin:064-gtp-channel-conf 29_188 -GTP_CHANNEL_3.GTPE2.RXOSCALRESET_TIME[4] origin:064-gtp-channel-conf 28_189 -GTP_CHANNEL_3.GTPE2.RXOSCALRESET_TIMEOUT[0] origin:064-gtp-channel-conf 29_189 -GTP_CHANNEL_3.GTPE2.RXOSCALRESET_TIMEOUT[1] origin:064-gtp-channel-conf 28_190 -GTP_CHANNEL_3.GTPE2.RXOSCALRESET_TIMEOUT[2] origin:064-gtp-channel-conf 29_190 -GTP_CHANNEL_3.GTPE2.RXOSCALRESET_TIMEOUT[3] origin:064-gtp-channel-conf 28_191 -GTP_CHANNEL_3.GTPE2.RXOSCALRESET_TIMEOUT[4] origin:064-gtp-channel-conf 29_191 -GTP_CHANNEL_3.GTPE2.RXOUT_DIV[0] origin:064-gtp-channel-conf 30_384 -GTP_CHANNEL_3.GTPE2.RXOUT_DIV[1] origin:064-gtp-channel-conf 31_384 -GTP_CHANNEL_3.GTPE2.RXPCSRESET_TIME[0] origin:064-gtp-channel-conf 29_115 -GTP_CHANNEL_3.GTPE2.RXPCSRESET_TIME[1] origin:064-gtp-channel-conf 28_116 -GTP_CHANNEL_3.GTPE2.RXPCSRESET_TIME[2] origin:064-gtp-channel-conf 29_116 -GTP_CHANNEL_3.GTPE2.RXPCSRESET_TIME[3] origin:064-gtp-channel-conf 28_117 -GTP_CHANNEL_3.GTPE2.RXPCSRESET_TIME[4] origin:064-gtp-channel-conf 29_117 -GTP_CHANNEL_3.GTPE2.RXPH_CFG[0] origin:064-gtp-channel-conf 30_584 -GTP_CHANNEL_3.GTPE2.RXPH_CFG[1] origin:064-gtp-channel-conf 31_584 -GTP_CHANNEL_3.GTPE2.RXPH_CFG[2] origin:064-gtp-channel-conf 30_585 -GTP_CHANNEL_3.GTPE2.RXPH_CFG[3] origin:064-gtp-channel-conf 31_585 -GTP_CHANNEL_3.GTPE2.RXPH_CFG[4] origin:064-gtp-channel-conf 30_586 -GTP_CHANNEL_3.GTPE2.RXPH_CFG[5] origin:064-gtp-channel-conf 31_586 -GTP_CHANNEL_3.GTPE2.RXPH_CFG[6] origin:064-gtp-channel-conf 30_587 -GTP_CHANNEL_3.GTPE2.RXPH_CFG[7] origin:064-gtp-channel-conf 31_587 -GTP_CHANNEL_3.GTPE2.RXPH_CFG[8] origin:064-gtp-channel-conf 30_588 -GTP_CHANNEL_3.GTPE2.RXPH_CFG[9] origin:064-gtp-channel-conf 31_588 -GTP_CHANNEL_3.GTPE2.RXPH_CFG[10] origin:064-gtp-channel-conf 30_589 -GTP_CHANNEL_3.GTPE2.RXPH_CFG[11] origin:064-gtp-channel-conf 31_589 -GTP_CHANNEL_3.GTPE2.RXPH_CFG[12] origin:064-gtp-channel-conf 30_590 -GTP_CHANNEL_3.GTPE2.RXPH_CFG[13] origin:064-gtp-channel-conf 31_590 -GTP_CHANNEL_3.GTPE2.RXPH_CFG[14] origin:064-gtp-channel-conf 30_591 -GTP_CHANNEL_3.GTPE2.RXPH_CFG[15] origin:064-gtp-channel-conf 31_591 -GTP_CHANNEL_3.GTPE2.RXPH_CFG[16] origin:064-gtp-channel-conf 30_592 -GTP_CHANNEL_3.GTPE2.RXPH_CFG[17] origin:064-gtp-channel-conf 31_592 -GTP_CHANNEL_3.GTPE2.RXPH_CFG[18] origin:064-gtp-channel-conf 30_593 -GTP_CHANNEL_3.GTPE2.RXPH_CFG[19] origin:064-gtp-channel-conf 31_593 -GTP_CHANNEL_3.GTPE2.RXPH_CFG[20] origin:064-gtp-channel-conf 30_594 -GTP_CHANNEL_3.GTPE2.RXPH_CFG[21] origin:064-gtp-channel-conf 31_594 -GTP_CHANNEL_3.GTPE2.RXPH_CFG[22] origin:064-gtp-channel-conf 30_595 -GTP_CHANNEL_3.GTPE2.RXPH_CFG[23] origin:064-gtp-channel-conf 31_595 -GTP_CHANNEL_3.GTPE2.RXPH_MONITOR_SEL[0] origin:064-gtp-channel-conf 28_700 -GTP_CHANNEL_3.GTPE2.RXPH_MONITOR_SEL[1] origin:064-gtp-channel-conf 29_700 -GTP_CHANNEL_3.GTPE2.RXPH_MONITOR_SEL[2] origin:064-gtp-channel-conf 28_701 -GTP_CHANNEL_3.GTPE2.RXPH_MONITOR_SEL[3] origin:064-gtp-channel-conf 29_701 -GTP_CHANNEL_3.GTPE2.RXPH_MONITOR_SEL[4] origin:064-gtp-channel-conf 28_702 -GTP_CHANNEL_3.GTPE2.RXPHDLY_CFG[0] origin:064-gtp-channel-conf 30_600 -GTP_CHANNEL_3.GTPE2.RXPHDLY_CFG[1] origin:064-gtp-channel-conf 31_600 -GTP_CHANNEL_3.GTPE2.RXPHDLY_CFG[2] origin:064-gtp-channel-conf 30_601 -GTP_CHANNEL_3.GTPE2.RXPHDLY_CFG[3] origin:064-gtp-channel-conf 31_601 -GTP_CHANNEL_3.GTPE2.RXPHDLY_CFG[4] origin:064-gtp-channel-conf 30_602 -GTP_CHANNEL_3.GTPE2.RXPHDLY_CFG[5] origin:064-gtp-channel-conf 31_602 -GTP_CHANNEL_3.GTPE2.RXPHDLY_CFG[6] origin:064-gtp-channel-conf 30_603 -GTP_CHANNEL_3.GTPE2.RXPHDLY_CFG[7] origin:064-gtp-channel-conf 31_603 -GTP_CHANNEL_3.GTPE2.RXPHDLY_CFG[8] origin:064-gtp-channel-conf 30_604 -GTP_CHANNEL_3.GTPE2.RXPHDLY_CFG[9] origin:064-gtp-channel-conf 31_604 -GTP_CHANNEL_3.GTPE2.RXPHDLY_CFG[10] origin:064-gtp-channel-conf 30_605 -GTP_CHANNEL_3.GTPE2.RXPHDLY_CFG[11] origin:064-gtp-channel-conf 31_605 -GTP_CHANNEL_3.GTPE2.RXPHDLY_CFG[12] origin:064-gtp-channel-conf 30_606 -GTP_CHANNEL_3.GTPE2.RXPHDLY_CFG[13] origin:064-gtp-channel-conf 31_606 -GTP_CHANNEL_3.GTPE2.RXPHDLY_CFG[14] origin:064-gtp-channel-conf 30_607 -GTP_CHANNEL_3.GTPE2.RXPHDLY_CFG[15] origin:064-gtp-channel-conf 31_607 -GTP_CHANNEL_3.GTPE2.RXPHDLY_CFG[16] origin:064-gtp-channel-conf 30_608 -GTP_CHANNEL_3.GTPE2.RXPHDLY_CFG[17] origin:064-gtp-channel-conf 31_608 -GTP_CHANNEL_3.GTPE2.RXPHDLY_CFG[18] origin:064-gtp-channel-conf 30_609 -GTP_CHANNEL_3.GTPE2.RXPHDLY_CFG[19] origin:064-gtp-channel-conf 31_609 -GTP_CHANNEL_3.GTPE2.RXPHDLY_CFG[20] origin:064-gtp-channel-conf 30_610 -GTP_CHANNEL_3.GTPE2.RXPHDLY_CFG[21] origin:064-gtp-channel-conf 31_610 -GTP_CHANNEL_3.GTPE2.RXPHDLY_CFG[22] origin:064-gtp-channel-conf 30_611 -GTP_CHANNEL_3.GTPE2.RXPHDLY_CFG[23] origin:064-gtp-channel-conf 31_611 -GTP_CHANNEL_3.GTPE2.RXPI_CFG0[0] origin:064-gtp-channel-conf 31_430 -GTP_CHANNEL_3.GTPE2.RXPI_CFG0[1] origin:064-gtp-channel-conf 30_431 -GTP_CHANNEL_3.GTPE2.RXPI_CFG0[2] origin:064-gtp-channel-conf 31_431 -GTP_CHANNEL_3.GTPE2.RXPI_CFG1[0] origin:064-gtp-channel-conf 30_442 -GTP_CHANNEL_3.GTPE2.RXPI_CFG2[0] origin:064-gtp-channel-conf 31_441 -GTP_CHANNEL_3.GTPE2.RXPMARESET_TIME[0] origin:064-gtp-channel-conf 28_104 -GTP_CHANNEL_3.GTPE2.RXPMARESET_TIME[1] origin:064-gtp-channel-conf 29_104 -GTP_CHANNEL_3.GTPE2.RXPMARESET_TIME[2] origin:064-gtp-channel-conf 28_105 -GTP_CHANNEL_3.GTPE2.RXPMARESET_TIME[3] origin:064-gtp-channel-conf 29_105 -GTP_CHANNEL_3.GTPE2.RXPMARESET_TIME[4] origin:064-gtp-channel-conf 28_106 -GTP_CHANNEL_3.GTPE2.RXPRBS_ERR_LOOPBACK[0] origin:064-gtp-channel-conf 28_136 -GTP_CHANNEL_3.GTPE2.RXSLIDE_AUTO_WAIT[0] origin:064-gtp-channel-conf 28_520 -GTP_CHANNEL_3.GTPE2.RXSLIDE_AUTO_WAIT[1] origin:064-gtp-channel-conf 29_520 -GTP_CHANNEL_3.GTPE2.RXSLIDE_AUTO_WAIT[2] origin:064-gtp-channel-conf 28_521 -GTP_CHANNEL_3.GTPE2.RXSLIDE_AUTO_WAIT[3] origin:064-gtp-channel-conf 29_521 -GTP_CHANNEL_3.GTPE2.RXSLIDE_MODE.AUTO origin:064-gtp-channel-conf !29_519 28_519 -GTP_CHANNEL_3.GTPE2.RXSLIDE_MODE.PCS origin:064-gtp-channel-conf !28_519 29_519 -GTP_CHANNEL_3.GTPE2.RXSLIDE_MODE.PMA origin:064-gtp-channel-conf 28_519 29_519 -GTP_CHANNEL_3.GTPE2.RXSYNC_MULTILANE[0] origin:064-gtp-channel-conf 28_133 -GTP_CHANNEL_3.GTPE2.RXSYNC_OVRD[0] origin:064-gtp-channel-conf 29_135 -GTP_CHANNEL_3.GTPE2.RXSYNC_SKIP_DA[0] origin:064-gtp-channel-conf 29_134 -GTP_CHANNEL_3.GTPE2.SAS_MAX_COM[0] origin:064-gtp-channel-conf 28_171 -GTP_CHANNEL_3.GTPE2.SAS_MAX_COM[1] origin:064-gtp-channel-conf 29_171 -GTP_CHANNEL_3.GTPE2.SAS_MAX_COM[2] origin:064-gtp-channel-conf 28_172 -GTP_CHANNEL_3.GTPE2.SAS_MAX_COM[3] origin:064-gtp-channel-conf 29_172 -GTP_CHANNEL_3.GTPE2.SAS_MAX_COM[4] origin:064-gtp-channel-conf 28_173 -GTP_CHANNEL_3.GTPE2.SAS_MAX_COM[5] origin:064-gtp-channel-conf 29_173 -GTP_CHANNEL_3.GTPE2.SAS_MAX_COM[6] origin:064-gtp-channel-conf 28_174 -GTP_CHANNEL_3.GTPE2.SAS_MIN_COM[0] origin:064-gtp-channel-conf 29_156 -GTP_CHANNEL_3.GTPE2.SAS_MIN_COM[1] origin:064-gtp-channel-conf 28_157 -GTP_CHANNEL_3.GTPE2.SAS_MIN_COM[2] origin:064-gtp-channel-conf 29_157 -GTP_CHANNEL_3.GTPE2.SAS_MIN_COM[3] origin:064-gtp-channel-conf 28_158 -GTP_CHANNEL_3.GTPE2.SAS_MIN_COM[4] origin:064-gtp-channel-conf 29_158 -GTP_CHANNEL_3.GTPE2.SAS_MIN_COM[5] origin:064-gtp-channel-conf 28_159 -GTP_CHANNEL_3.GTPE2.SATA_BURST_SEQ_LEN[0] origin:064-gtp-channel-conf 28_150 -GTP_CHANNEL_3.GTPE2.SATA_BURST_SEQ_LEN[1] origin:064-gtp-channel-conf 29_150 -GTP_CHANNEL_3.GTPE2.SATA_BURST_SEQ_LEN[2] origin:064-gtp-channel-conf 28_151 -GTP_CHANNEL_3.GTPE2.SATA_BURST_SEQ_LEN[3] origin:064-gtp-channel-conf 29_151 -GTP_CHANNEL_3.GTPE2.SATA_BURST_VAL[0] origin:064-gtp-channel-conf 29_147 -GTP_CHANNEL_3.GTPE2.SATA_BURST_VAL[1] origin:064-gtp-channel-conf 28_148 -GTP_CHANNEL_3.GTPE2.SATA_BURST_VAL[2] origin:064-gtp-channel-conf 29_148 -GTP_CHANNEL_3.GTPE2.SATA_EIDLE_VAL[0] origin:064-gtp-channel-conf 28_152 -GTP_CHANNEL_3.GTPE2.SATA_EIDLE_VAL[1] origin:064-gtp-channel-conf 29_152 -GTP_CHANNEL_3.GTPE2.SATA_EIDLE_VAL[2] origin:064-gtp-channel-conf 28_153 -GTP_CHANNEL_3.GTPE2.SATA_MAX_BURST[0] origin:064-gtp-channel-conf 28_168 -GTP_CHANNEL_3.GTPE2.SATA_MAX_BURST[1] origin:064-gtp-channel-conf 29_168 -GTP_CHANNEL_3.GTPE2.SATA_MAX_BURST[2] origin:064-gtp-channel-conf 28_169 -GTP_CHANNEL_3.GTPE2.SATA_MAX_BURST[3] origin:064-gtp-channel-conf 29_169 -GTP_CHANNEL_3.GTPE2.SATA_MAX_BURST[4] origin:064-gtp-channel-conf 28_170 -GTP_CHANNEL_3.GTPE2.SATA_MAX_BURST[5] origin:064-gtp-channel-conf 29_170 -GTP_CHANNEL_3.GTPE2.SATA_MAX_INIT[0] origin:064-gtp-channel-conf 28_176 -GTP_CHANNEL_3.GTPE2.SATA_MAX_INIT[1] origin:064-gtp-channel-conf 29_176 -GTP_CHANNEL_3.GTPE2.SATA_MAX_INIT[2] origin:064-gtp-channel-conf 28_177 -GTP_CHANNEL_3.GTPE2.SATA_MAX_INIT[3] origin:064-gtp-channel-conf 29_177 -GTP_CHANNEL_3.GTPE2.SATA_MAX_INIT[4] origin:064-gtp-channel-conf 28_178 -GTP_CHANNEL_3.GTPE2.SATA_MAX_INIT[5] origin:064-gtp-channel-conf 29_178 -GTP_CHANNEL_3.GTPE2.SATA_MAX_WAKE[0] origin:064-gtp-channel-conf 28_179 -GTP_CHANNEL_3.GTPE2.SATA_MAX_WAKE[1] origin:064-gtp-channel-conf 29_179 -GTP_CHANNEL_3.GTPE2.SATA_MAX_WAKE[2] origin:064-gtp-channel-conf 28_180 -GTP_CHANNEL_3.GTPE2.SATA_MAX_WAKE[3] origin:064-gtp-channel-conf 29_180 -GTP_CHANNEL_3.GTPE2.SATA_MAX_WAKE[4] origin:064-gtp-channel-conf 28_181 -GTP_CHANNEL_3.GTPE2.SATA_MAX_WAKE[5] origin:064-gtp-channel-conf 29_181 -GTP_CHANNEL_3.GTPE2.SATA_MIN_BURST[0] origin:064-gtp-channel-conf 29_153 -GTP_CHANNEL_3.GTPE2.SATA_MIN_BURST[1] origin:064-gtp-channel-conf 28_154 -GTP_CHANNEL_3.GTPE2.SATA_MIN_BURST[2] origin:064-gtp-channel-conf 29_154 -GTP_CHANNEL_3.GTPE2.SATA_MIN_BURST[3] origin:064-gtp-channel-conf 28_155 -GTP_CHANNEL_3.GTPE2.SATA_MIN_BURST[4] origin:064-gtp-channel-conf 29_155 -GTP_CHANNEL_3.GTPE2.SATA_MIN_BURST[5] origin:064-gtp-channel-conf 28_156 -GTP_CHANNEL_3.GTPE2.SATA_MIN_INIT[0] origin:064-gtp-channel-conf 28_160 -GTP_CHANNEL_3.GTPE2.SATA_MIN_INIT[1] origin:064-gtp-channel-conf 29_160 -GTP_CHANNEL_3.GTPE2.SATA_MIN_INIT[2] origin:064-gtp-channel-conf 28_161 -GTP_CHANNEL_3.GTPE2.SATA_MIN_INIT[3] origin:064-gtp-channel-conf 29_161 -GTP_CHANNEL_3.GTPE2.SATA_MIN_INIT[4] origin:064-gtp-channel-conf 28_162 -GTP_CHANNEL_3.GTPE2.SATA_MIN_INIT[5] origin:064-gtp-channel-conf 29_162 -GTP_CHANNEL_3.GTPE2.SATA_MIN_WAKE[0] origin:064-gtp-channel-conf 28_163 -GTP_CHANNEL_3.GTPE2.SATA_MIN_WAKE[1] origin:064-gtp-channel-conf 29_163 -GTP_CHANNEL_3.GTPE2.SATA_MIN_WAKE[2] origin:064-gtp-channel-conf 28_164 -GTP_CHANNEL_3.GTPE2.SATA_MIN_WAKE[3] origin:064-gtp-channel-conf 29_164 -GTP_CHANNEL_3.GTPE2.SATA_MIN_WAKE[4] origin:064-gtp-channel-conf 28_165 -GTP_CHANNEL_3.GTPE2.SATA_MIN_WAKE[5] origin:064-gtp-channel-conf 29_165 -GTP_CHANNEL_3.GTPE2.SATA_PLL_CFG.VCO_1500MHZ origin:064-gtp-channel-conf 30_55 -GTP_CHANNEL_3.GTPE2.SATA_PLL_CFG.VCO_750MHZ origin:064-gtp-channel-conf 31_55 -GTP_CHANNEL_3.GTPE2.SHOW_REALIGN_COMMA origin:064-gtp-channel-conf 29_522 -GTP_CHANNEL_3.GTPE2.TERM_RCAL_CFG[0] origin:064-gtp-channel-conf 30_136 -GTP_CHANNEL_3.GTPE2.TERM_RCAL_CFG[1] origin:064-gtp-channel-conf 31_136 -GTP_CHANNEL_3.GTPE2.TERM_RCAL_CFG[2] origin:064-gtp-channel-conf 30_137 -GTP_CHANNEL_3.GTPE2.TERM_RCAL_CFG[3] origin:064-gtp-channel-conf 31_137 -GTP_CHANNEL_3.GTPE2.TERM_RCAL_CFG[4] origin:064-gtp-channel-conf 30_138 -GTP_CHANNEL_3.GTPE2.TERM_RCAL_CFG[5] origin:064-gtp-channel-conf 31_138 -GTP_CHANNEL_3.GTPE2.TERM_RCAL_CFG[6] origin:064-gtp-channel-conf 30_139 -GTP_CHANNEL_3.GTPE2.TERM_RCAL_CFG[7] origin:064-gtp-channel-conf 31_139 -GTP_CHANNEL_3.GTPE2.TERM_RCAL_CFG[8] origin:064-gtp-channel-conf 30_140 -GTP_CHANNEL_3.GTPE2.TERM_RCAL_CFG[9] origin:064-gtp-channel-conf 31_140 -GTP_CHANNEL_3.GTPE2.TERM_RCAL_CFG[10] origin:064-gtp-channel-conf 30_141 -GTP_CHANNEL_3.GTPE2.TERM_RCAL_CFG[11] origin:064-gtp-channel-conf 31_141 -GTP_CHANNEL_3.GTPE2.TERM_RCAL_CFG[12] origin:064-gtp-channel-conf 30_142 -GTP_CHANNEL_3.GTPE2.TERM_RCAL_CFG[13] origin:064-gtp-channel-conf 31_142 -GTP_CHANNEL_3.GTPE2.TERM_RCAL_CFG[14] origin:064-gtp-channel-conf 30_143 -GTP_CHANNEL_3.GTPE2.TERM_RCAL_OVRD[0] origin:064-gtp-channel-conf 31_150 -GTP_CHANNEL_3.GTPE2.TERM_RCAL_OVRD[1] origin:064-gtp-channel-conf 30_151 -GTP_CHANNEL_3.GTPE2.TERM_RCAL_OVRD[2] origin:064-gtp-channel-conf 31_151 -GTP_CHANNEL_3.GTPE2.TRANS_TIME_RATE[0] origin:064-gtp-channel-conf 28_192 -GTP_CHANNEL_3.GTPE2.TRANS_TIME_RATE[1] origin:064-gtp-channel-conf 29_192 -GTP_CHANNEL_3.GTPE2.TRANS_TIME_RATE[2] origin:064-gtp-channel-conf 28_193 -GTP_CHANNEL_3.GTPE2.TRANS_TIME_RATE[3] origin:064-gtp-channel-conf 29_193 -GTP_CHANNEL_3.GTPE2.TRANS_TIME_RATE[4] origin:064-gtp-channel-conf 28_194 -GTP_CHANNEL_3.GTPE2.TRANS_TIME_RATE[5] origin:064-gtp-channel-conf 29_194 -GTP_CHANNEL_3.GTPE2.TRANS_TIME_RATE[6] origin:064-gtp-channel-conf 28_195 -GTP_CHANNEL_3.GTPE2.TRANS_TIME_RATE[7] origin:064-gtp-channel-conf 29_195 -GTP_CHANNEL_3.GTPE2.TST_RSV[0] origin:064-gtp-channel-conf 30_504 -GTP_CHANNEL_3.GTPE2.TST_RSV[1] origin:064-gtp-channel-conf 31_504 -GTP_CHANNEL_3.GTPE2.TST_RSV[2] origin:064-gtp-channel-conf 30_505 -GTP_CHANNEL_3.GTPE2.TST_RSV[3] origin:064-gtp-channel-conf 31_505 -GTP_CHANNEL_3.GTPE2.TST_RSV[4] origin:064-gtp-channel-conf 30_506 -GTP_CHANNEL_3.GTPE2.TST_RSV[5] origin:064-gtp-channel-conf 31_506 -GTP_CHANNEL_3.GTPE2.TST_RSV[6] origin:064-gtp-channel-conf 30_507 -GTP_CHANNEL_3.GTPE2.TST_RSV[7] origin:064-gtp-channel-conf 31_507 -GTP_CHANNEL_3.GTPE2.TST_RSV[8] origin:064-gtp-channel-conf 30_508 -GTP_CHANNEL_3.GTPE2.TST_RSV[9] origin:064-gtp-channel-conf 31_508 -GTP_CHANNEL_3.GTPE2.TST_RSV[10] origin:064-gtp-channel-conf 30_509 -GTP_CHANNEL_3.GTPE2.TST_RSV[11] origin:064-gtp-channel-conf 31_509 -GTP_CHANNEL_3.GTPE2.TST_RSV[12] origin:064-gtp-channel-conf 30_510 -GTP_CHANNEL_3.GTPE2.TST_RSV[13] origin:064-gtp-channel-conf 31_510 -GTP_CHANNEL_3.GTPE2.TST_RSV[14] origin:064-gtp-channel-conf 30_511 -GTP_CHANNEL_3.GTPE2.TST_RSV[15] origin:064-gtp-channel-conf 31_511 -GTP_CHANNEL_3.GTPE2.TST_RSV[16] origin:064-gtp-channel-conf 30_512 -GTP_CHANNEL_3.GTPE2.TST_RSV[17] origin:064-gtp-channel-conf 31_512 -GTP_CHANNEL_3.GTPE2.TST_RSV[18] origin:064-gtp-channel-conf 30_513 -GTP_CHANNEL_3.GTPE2.TST_RSV[19] origin:064-gtp-channel-conf 31_513 -GTP_CHANNEL_3.GTPE2.TST_RSV[20] origin:064-gtp-channel-conf 30_514 -GTP_CHANNEL_3.GTPE2.TST_RSV[21] origin:064-gtp-channel-conf 31_514 -GTP_CHANNEL_3.GTPE2.TST_RSV[22] origin:064-gtp-channel-conf 30_515 -GTP_CHANNEL_3.GTPE2.TST_RSV[23] origin:064-gtp-channel-conf 31_515 -GTP_CHANNEL_3.GTPE2.TST_RSV[24] origin:064-gtp-channel-conf 30_516 -GTP_CHANNEL_3.GTPE2.TST_RSV[25] origin:064-gtp-channel-conf 31_516 -GTP_CHANNEL_3.GTPE2.TST_RSV[26] origin:064-gtp-channel-conf 30_517 -GTP_CHANNEL_3.GTPE2.TST_RSV[27] origin:064-gtp-channel-conf 31_517 -GTP_CHANNEL_3.GTPE2.TST_RSV[28] origin:064-gtp-channel-conf 30_518 -GTP_CHANNEL_3.GTPE2.TST_RSV[29] origin:064-gtp-channel-conf 31_518 -GTP_CHANNEL_3.GTPE2.TST_RSV[30] origin:064-gtp-channel-conf 30_519 -GTP_CHANNEL_3.GTPE2.TST_RSV[31] origin:064-gtp-channel-conf 31_519 -GTP_CHANNEL_3.GTPE2.TX_CLKMUX_EN[0] origin:064-gtp-channel-conf 31_128 -GTP_CHANNEL_3.GTPE2.TX_DATA_WIDTH[0] origin:064-gtp-channel-conf 30_152 -GTP_CHANNEL_3.GTPE2.TX_DATA_WIDTH[1] origin:064-gtp-channel-conf 31_152 -GTP_CHANNEL_3.GTPE2.TX_DATA_WIDTH[2] origin:064-gtp-channel-conf 30_153 -GTP_CHANNEL_3.GTPE2.TX_DRIVE_MODE.PIPE origin:064-gtp-channel-conf 28_200 -GTP_CHANNEL_3.GTPE2.TX_EIDLE_ASSERT_DELAY[0] origin:064-gtp-channel-conf 28_203 -GTP_CHANNEL_3.GTPE2.TX_EIDLE_ASSERT_DELAY[1] origin:064-gtp-channel-conf 29_203 -GTP_CHANNEL_3.GTPE2.TX_EIDLE_ASSERT_DELAY[2] origin:064-gtp-channel-conf 28_204 -GTP_CHANNEL_3.GTPE2.TX_EIDLE_DEASSERT_DELAY[0] origin:064-gtp-channel-conf 29_204 -GTP_CHANNEL_3.GTPE2.TX_EIDLE_DEASSERT_DELAY[1] origin:064-gtp-channel-conf 28_205 -GTP_CHANNEL_3.GTPE2.TX_EIDLE_DEASSERT_DELAY[2] origin:064-gtp-channel-conf 29_205 -GTP_CHANNEL_3.GTPE2.TX_LOOPBACK_DRIVE_HIZ origin:064-gtp-channel-conf 29_202 -GTP_CHANNEL_3.GTPE2.TX_MAINCURSOR_SEL[0] origin:064-gtp-channel-conf 31_289 -GTP_CHANNEL_3.GTPE2.TX_MARGIN_FULL_0[0] origin:064-gtp-channel-conf 30_232 -GTP_CHANNEL_3.GTPE2.TX_MARGIN_FULL_0[1] origin:064-gtp-channel-conf 31_232 -GTP_CHANNEL_3.GTPE2.TX_MARGIN_FULL_0[2] origin:064-gtp-channel-conf 30_233 -GTP_CHANNEL_3.GTPE2.TX_MARGIN_FULL_0[3] origin:064-gtp-channel-conf 31_233 -GTP_CHANNEL_3.GTPE2.TX_MARGIN_FULL_0[4] origin:064-gtp-channel-conf 30_234 -GTP_CHANNEL_3.GTPE2.TX_MARGIN_FULL_0[5] origin:064-gtp-channel-conf 31_234 -GTP_CHANNEL_3.GTPE2.TX_MARGIN_FULL_0[6] origin:064-gtp-channel-conf 30_235 -GTP_CHANNEL_3.GTPE2.TX_MARGIN_FULL_1[0] origin:064-gtp-channel-conf 30_236 -GTP_CHANNEL_3.GTPE2.TX_MARGIN_FULL_1[1] origin:064-gtp-channel-conf 31_236 -GTP_CHANNEL_3.GTPE2.TX_MARGIN_FULL_1[2] origin:064-gtp-channel-conf 30_237 -GTP_CHANNEL_3.GTPE2.TX_MARGIN_FULL_1[3] origin:064-gtp-channel-conf 31_237 -GTP_CHANNEL_3.GTPE2.TX_MARGIN_FULL_1[4] origin:064-gtp-channel-conf 30_238 -GTP_CHANNEL_3.GTPE2.TX_MARGIN_FULL_1[5] origin:064-gtp-channel-conf 31_238 -GTP_CHANNEL_3.GTPE2.TX_MARGIN_FULL_1[6] origin:064-gtp-channel-conf 30_239 -GTP_CHANNEL_3.GTPE2.TX_MARGIN_FULL_2[0] origin:064-gtp-channel-conf 30_240 -GTP_CHANNEL_3.GTPE2.TX_MARGIN_FULL_2[1] origin:064-gtp-channel-conf 31_240 -GTP_CHANNEL_3.GTPE2.TX_MARGIN_FULL_2[2] origin:064-gtp-channel-conf 30_241 -GTP_CHANNEL_3.GTPE2.TX_MARGIN_FULL_2[3] origin:064-gtp-channel-conf 31_241 -GTP_CHANNEL_3.GTPE2.TX_MARGIN_FULL_2[4] origin:064-gtp-channel-conf 30_242 -GTP_CHANNEL_3.GTPE2.TX_MARGIN_FULL_2[5] origin:064-gtp-channel-conf 31_242 -GTP_CHANNEL_3.GTPE2.TX_MARGIN_FULL_2[6] origin:064-gtp-channel-conf 30_243 -GTP_CHANNEL_3.GTPE2.TX_MARGIN_FULL_3[0] origin:064-gtp-channel-conf 30_244 -GTP_CHANNEL_3.GTPE2.TX_MARGIN_FULL_3[1] origin:064-gtp-channel-conf 31_244 -GTP_CHANNEL_3.GTPE2.TX_MARGIN_FULL_3[2] origin:064-gtp-channel-conf 30_245 -GTP_CHANNEL_3.GTPE2.TX_MARGIN_FULL_3[3] origin:064-gtp-channel-conf 31_245 -GTP_CHANNEL_3.GTPE2.TX_MARGIN_FULL_3[4] origin:064-gtp-channel-conf 30_246 -GTP_CHANNEL_3.GTPE2.TX_MARGIN_FULL_3[5] origin:064-gtp-channel-conf 31_246 -GTP_CHANNEL_3.GTPE2.TX_MARGIN_FULL_3[6] origin:064-gtp-channel-conf 30_247 -GTP_CHANNEL_3.GTPE2.TX_MARGIN_FULL_4[0] origin:064-gtp-channel-conf 30_248 -GTP_CHANNEL_3.GTPE2.TX_MARGIN_FULL_4[1] origin:064-gtp-channel-conf 31_248 -GTP_CHANNEL_3.GTPE2.TX_MARGIN_FULL_4[2] origin:064-gtp-channel-conf 30_249 -GTP_CHANNEL_3.GTPE2.TX_MARGIN_FULL_4[3] origin:064-gtp-channel-conf 31_249 -GTP_CHANNEL_3.GTPE2.TX_MARGIN_FULL_4[4] origin:064-gtp-channel-conf 30_250 -GTP_CHANNEL_3.GTPE2.TX_MARGIN_FULL_4[5] origin:064-gtp-channel-conf 31_250 -GTP_CHANNEL_3.GTPE2.TX_MARGIN_FULL_4[6] origin:064-gtp-channel-conf 30_251 -GTP_CHANNEL_3.GTPE2.TX_MARGIN_LOW_0[0] origin:064-gtp-channel-conf 30_252 -GTP_CHANNEL_3.GTPE2.TX_MARGIN_LOW_0[1] origin:064-gtp-channel-conf 31_252 -GTP_CHANNEL_3.GTPE2.TX_MARGIN_LOW_0[2] origin:064-gtp-channel-conf 30_253 -GTP_CHANNEL_3.GTPE2.TX_MARGIN_LOW_0[3] origin:064-gtp-channel-conf 31_253 -GTP_CHANNEL_3.GTPE2.TX_MARGIN_LOW_0[4] origin:064-gtp-channel-conf 30_254 -GTP_CHANNEL_3.GTPE2.TX_MARGIN_LOW_0[5] origin:064-gtp-channel-conf 31_254 -GTP_CHANNEL_3.GTPE2.TX_MARGIN_LOW_0[6] origin:064-gtp-channel-conf 30_255 -GTP_CHANNEL_3.GTPE2.TX_MARGIN_LOW_1[0] origin:064-gtp-channel-conf 30_256 -GTP_CHANNEL_3.GTPE2.TX_MARGIN_LOW_1[1] origin:064-gtp-channel-conf 31_256 -GTP_CHANNEL_3.GTPE2.TX_MARGIN_LOW_1[2] origin:064-gtp-channel-conf 30_257 -GTP_CHANNEL_3.GTPE2.TX_MARGIN_LOW_1[3] origin:064-gtp-channel-conf 31_257 -GTP_CHANNEL_3.GTPE2.TX_MARGIN_LOW_1[4] origin:064-gtp-channel-conf 30_258 -GTP_CHANNEL_3.GTPE2.TX_MARGIN_LOW_1[5] origin:064-gtp-channel-conf 31_258 -GTP_CHANNEL_3.GTPE2.TX_MARGIN_LOW_1[6] origin:064-gtp-channel-conf 30_259 -GTP_CHANNEL_3.GTPE2.TX_MARGIN_LOW_2[0] origin:064-gtp-channel-conf 30_260 -GTP_CHANNEL_3.GTPE2.TX_MARGIN_LOW_2[1] origin:064-gtp-channel-conf 31_260 -GTP_CHANNEL_3.GTPE2.TX_MARGIN_LOW_2[2] origin:064-gtp-channel-conf 30_261 -GTP_CHANNEL_3.GTPE2.TX_MARGIN_LOW_2[3] origin:064-gtp-channel-conf 31_261 -GTP_CHANNEL_3.GTPE2.TX_MARGIN_LOW_2[4] origin:064-gtp-channel-conf 30_262 -GTP_CHANNEL_3.GTPE2.TX_MARGIN_LOW_2[5] origin:064-gtp-channel-conf 31_262 -GTP_CHANNEL_3.GTPE2.TX_MARGIN_LOW_2[6] origin:064-gtp-channel-conf 30_263 -GTP_CHANNEL_3.GTPE2.TX_MARGIN_LOW_3[0] origin:064-gtp-channel-conf 30_264 -GTP_CHANNEL_3.GTPE2.TX_MARGIN_LOW_3[1] origin:064-gtp-channel-conf 31_264 -GTP_CHANNEL_3.GTPE2.TX_MARGIN_LOW_3[2] origin:064-gtp-channel-conf 30_265 -GTP_CHANNEL_3.GTPE2.TX_MARGIN_LOW_3[3] origin:064-gtp-channel-conf 31_265 -GTP_CHANNEL_3.GTPE2.TX_MARGIN_LOW_3[4] origin:064-gtp-channel-conf 30_266 -GTP_CHANNEL_3.GTPE2.TX_MARGIN_LOW_3[5] origin:064-gtp-channel-conf 31_266 -GTP_CHANNEL_3.GTPE2.TX_MARGIN_LOW_3[6] origin:064-gtp-channel-conf 30_267 -GTP_CHANNEL_3.GTPE2.TX_MARGIN_LOW_4[0] origin:064-gtp-channel-conf 30_268 -GTP_CHANNEL_3.GTPE2.TX_MARGIN_LOW_4[1] origin:064-gtp-channel-conf 31_268 -GTP_CHANNEL_3.GTPE2.TX_MARGIN_LOW_4[2] origin:064-gtp-channel-conf 30_269 -GTP_CHANNEL_3.GTPE2.TX_MARGIN_LOW_4[3] origin:064-gtp-channel-conf 31_269 -GTP_CHANNEL_3.GTPE2.TX_MARGIN_LOW_4[4] origin:064-gtp-channel-conf 30_270 -GTP_CHANNEL_3.GTPE2.TX_MARGIN_LOW_4[5] origin:064-gtp-channel-conf 31_270 -GTP_CHANNEL_3.GTPE2.TX_MARGIN_LOW_4[6] origin:064-gtp-channel-conf 30_271 -GTP_CHANNEL_3.GTPE2.TX_PREDRIVER_MODE[0] origin:064-gtp-channel-conf 28_206 -GTP_CHANNEL_3.GTPE2.TX_RXDETECT_CFG[0] origin:064-gtp-channel-conf 30_296 -GTP_CHANNEL_3.GTPE2.TX_RXDETECT_CFG[1] origin:064-gtp-channel-conf 31_296 -GTP_CHANNEL_3.GTPE2.TX_RXDETECT_CFG[2] origin:064-gtp-channel-conf 30_297 -GTP_CHANNEL_3.GTPE2.TX_RXDETECT_CFG[3] origin:064-gtp-channel-conf 31_297 -GTP_CHANNEL_3.GTPE2.TX_RXDETECT_CFG[4] origin:064-gtp-channel-conf 30_298 -GTP_CHANNEL_3.GTPE2.TX_RXDETECT_CFG[5] origin:064-gtp-channel-conf 31_298 -GTP_CHANNEL_3.GTPE2.TX_RXDETECT_CFG[6] origin:064-gtp-channel-conf 30_299 -GTP_CHANNEL_3.GTPE2.TX_RXDETECT_CFG[7] origin:064-gtp-channel-conf 31_299 -GTP_CHANNEL_3.GTPE2.TX_RXDETECT_CFG[8] origin:064-gtp-channel-conf 30_300 -GTP_CHANNEL_3.GTPE2.TX_RXDETECT_CFG[9] origin:064-gtp-channel-conf 31_300 -GTP_CHANNEL_3.GTPE2.TX_RXDETECT_CFG[10] origin:064-gtp-channel-conf 30_301 -GTP_CHANNEL_3.GTPE2.TX_RXDETECT_CFG[11] origin:064-gtp-channel-conf 31_301 -GTP_CHANNEL_3.GTPE2.TX_RXDETECT_CFG[12] origin:064-gtp-channel-conf 30_302 -GTP_CHANNEL_3.GTPE2.TX_RXDETECT_CFG[13] origin:064-gtp-channel-conf 31_302 -GTP_CHANNEL_3.GTPE2.TX_RXDETECT_REF[0] origin:064-gtp-channel-conf 30_292 -GTP_CHANNEL_3.GTPE2.TX_RXDETECT_REF[1] origin:064-gtp-channel-conf 31_292 -GTP_CHANNEL_3.GTPE2.TX_RXDETECT_REF[2] origin:064-gtp-channel-conf 30_293 -GTP_CHANNEL_3.GTPE2.TX_XCLK_SEL.TXUSR origin:064-gtp-channel-conf 31_11 -GTP_CHANNEL_3.GTPE2.TX_CLK25_DIV[0] origin:064-gtp-channel-conf 30_144 -GTP_CHANNEL_3.GTPE2.TX_CLK25_DIV[1] origin:064-gtp-channel-conf 31_144 -GTP_CHANNEL_3.GTPE2.TX_CLK25_DIV[2] origin:064-gtp-channel-conf 30_145 -GTP_CHANNEL_3.GTPE2.TX_CLK25_DIV[3] origin:064-gtp-channel-conf 31_145 -GTP_CHANNEL_3.GTPE2.TX_CLK25_DIV[4] origin:064-gtp-channel-conf 30_146 -GTP_CHANNEL_3.GTPE2.TX_DEEMPH0[0] origin:064-gtp-channel-conf 30_272 -GTP_CHANNEL_3.GTPE2.TX_DEEMPH0[1] origin:064-gtp-channel-conf 31_272 -GTP_CHANNEL_3.GTPE2.TX_DEEMPH0[2] origin:064-gtp-channel-conf 30_273 -GTP_CHANNEL_3.GTPE2.TX_DEEMPH0[3] origin:064-gtp-channel-conf 31_273 -GTP_CHANNEL_3.GTPE2.TX_DEEMPH0[4] origin:064-gtp-channel-conf 30_274 -GTP_CHANNEL_3.GTPE2.TX_DEEMPH0[5] origin:064-gtp-channel-conf 31_274 -GTP_CHANNEL_3.GTPE2.TX_DEEMPH1[0] origin:064-gtp-channel-conf 30_276 -GTP_CHANNEL_3.GTPE2.TX_DEEMPH1[1] origin:064-gtp-channel-conf 31_276 -GTP_CHANNEL_3.GTPE2.TX_DEEMPH1[2] origin:064-gtp-channel-conf 30_277 -GTP_CHANNEL_3.GTPE2.TX_DEEMPH1[3] origin:064-gtp-channel-conf 31_277 -GTP_CHANNEL_3.GTPE2.TX_DEEMPH1[4] origin:064-gtp-channel-conf 30_278 -GTP_CHANNEL_3.GTPE2.TX_DEEMPH1[5] origin:064-gtp-channel-conf 31_278 -GTP_CHANNEL_3.GTPE2.TXBUF_EN origin:064-gtp-channel-conf 28_231 -GTP_CHANNEL_3.GTPE2.TXBUF_RESET_ON_RATE_CHANGE origin:064-gtp-channel-conf 29_231 -GTP_CHANNEL_3.GTPE2.TXDLY_CFG[0] origin:064-gtp-channel-conf 30_80 -GTP_CHANNEL_3.GTPE2.TXDLY_CFG[1] origin:064-gtp-channel-conf 31_80 -GTP_CHANNEL_3.GTPE2.TXDLY_CFG[2] origin:064-gtp-channel-conf 30_81 -GTP_CHANNEL_3.GTPE2.TXDLY_CFG[3] origin:064-gtp-channel-conf 31_81 -GTP_CHANNEL_3.GTPE2.TXDLY_CFG[4] origin:064-gtp-channel-conf 30_82 -GTP_CHANNEL_3.GTPE2.TXDLY_CFG[5] origin:064-gtp-channel-conf 31_82 -GTP_CHANNEL_3.GTPE2.TXDLY_CFG[6] origin:064-gtp-channel-conf 30_83 -GTP_CHANNEL_3.GTPE2.TXDLY_CFG[7] origin:064-gtp-channel-conf 31_83 -GTP_CHANNEL_3.GTPE2.TXDLY_CFG[8] origin:064-gtp-channel-conf 30_84 -GTP_CHANNEL_3.GTPE2.TXDLY_CFG[9] origin:064-gtp-channel-conf 31_84 -GTP_CHANNEL_3.GTPE2.TXDLY_CFG[10] origin:064-gtp-channel-conf 30_85 -GTP_CHANNEL_3.GTPE2.TXDLY_CFG[11] origin:064-gtp-channel-conf 31_85 -GTP_CHANNEL_3.GTPE2.TXDLY_CFG[12] origin:064-gtp-channel-conf 30_86 -GTP_CHANNEL_3.GTPE2.TXDLY_CFG[13] origin:064-gtp-channel-conf 31_86 -GTP_CHANNEL_3.GTPE2.TXDLY_CFG[14] origin:064-gtp-channel-conf 30_87 -GTP_CHANNEL_3.GTPE2.TXDLY_CFG[15] origin:064-gtp-channel-conf 31_87 -GTP_CHANNEL_3.GTPE2.TXDLY_LCFG[0] origin:064-gtp-channel-conf 30_568 -GTP_CHANNEL_3.GTPE2.TXDLY_LCFG[1] origin:064-gtp-channel-conf 31_568 -GTP_CHANNEL_3.GTPE2.TXDLY_LCFG[2] origin:064-gtp-channel-conf 30_569 -GTP_CHANNEL_3.GTPE2.TXDLY_LCFG[3] origin:064-gtp-channel-conf 31_569 -GTP_CHANNEL_3.GTPE2.TXDLY_LCFG[4] origin:064-gtp-channel-conf 30_570 -GTP_CHANNEL_3.GTPE2.TXDLY_LCFG[5] origin:064-gtp-channel-conf 31_570 -GTP_CHANNEL_3.GTPE2.TXDLY_LCFG[6] origin:064-gtp-channel-conf 30_571 -GTP_CHANNEL_3.GTPE2.TXDLY_LCFG[7] origin:064-gtp-channel-conf 31_571 -GTP_CHANNEL_3.GTPE2.TXDLY_LCFG[8] origin:064-gtp-channel-conf 30_572 -GTP_CHANNEL_3.GTPE2.TXDLY_TAP_CFG[0] origin:064-gtp-channel-conf 30_88 -GTP_CHANNEL_3.GTPE2.TXDLY_TAP_CFG[1] origin:064-gtp-channel-conf 31_88 -GTP_CHANNEL_3.GTPE2.TXDLY_TAP_CFG[2] origin:064-gtp-channel-conf 30_89 -GTP_CHANNEL_3.GTPE2.TXDLY_TAP_CFG[3] origin:064-gtp-channel-conf 31_89 -GTP_CHANNEL_3.GTPE2.TXDLY_TAP_CFG[4] origin:064-gtp-channel-conf 30_90 -GTP_CHANNEL_3.GTPE2.TXDLY_TAP_CFG[5] origin:064-gtp-channel-conf 31_90 -GTP_CHANNEL_3.GTPE2.TXDLY_TAP_CFG[6] origin:064-gtp-channel-conf 30_91 -GTP_CHANNEL_3.GTPE2.TXDLY_TAP_CFG[7] origin:064-gtp-channel-conf 31_91 -GTP_CHANNEL_3.GTPE2.TXDLY_TAP_CFG[8] origin:064-gtp-channel-conf 30_92 -GTP_CHANNEL_3.GTPE2.TXDLY_TAP_CFG[9] origin:064-gtp-channel-conf 31_92 -GTP_CHANNEL_3.GTPE2.TXDLY_TAP_CFG[10] origin:064-gtp-channel-conf 30_93 -GTP_CHANNEL_3.GTPE2.TXDLY_TAP_CFG[11] origin:064-gtp-channel-conf 31_93 -GTP_CHANNEL_3.GTPE2.TXDLY_TAP_CFG[12] origin:064-gtp-channel-conf 30_94 -GTP_CHANNEL_3.GTPE2.TXDLY_TAP_CFG[13] origin:064-gtp-channel-conf 31_94 -GTP_CHANNEL_3.GTPE2.TXDLY_TAP_CFG[14] origin:064-gtp-channel-conf 30_95 -GTP_CHANNEL_3.GTPE2.TXDLY_TAP_CFG[15] origin:064-gtp-channel-conf 31_95 -GTP_CHANNEL_3.GTPE2.TXGEARBOX_EN origin:064-gtp-channel-conf 29_226 -GTP_CHANNEL_3.GTPE2.TXOOB_CFG[0] origin:064-gtp-channel-conf 31_20 -GTP_CHANNEL_3.GTPE2.TXOUT_DIV[0] origin:064-gtp-channel-conf 30_386 -GTP_CHANNEL_3.GTPE2.TXOUT_DIV[1] origin:064-gtp-channel-conf 31_386 -GTP_CHANNEL_3.GTPE2.TXPCSRESET_TIME[0] origin:064-gtp-channel-conf 29_130 -GTP_CHANNEL_3.GTPE2.TXPCSRESET_TIME[1] origin:064-gtp-channel-conf 28_131 -GTP_CHANNEL_3.GTPE2.TXPCSRESET_TIME[2] origin:064-gtp-channel-conf 29_131 -GTP_CHANNEL_3.GTPE2.TXPCSRESET_TIME[3] origin:064-gtp-channel-conf 28_132 -GTP_CHANNEL_3.GTPE2.TXPCSRESET_TIME[4] origin:064-gtp-channel-conf 29_132 -GTP_CHANNEL_3.GTPE2.TXPH_CFG[0] origin:064-gtp-channel-conf 30_96 -GTP_CHANNEL_3.GTPE2.TXPH_CFG[1] origin:064-gtp-channel-conf 31_96 -GTP_CHANNEL_3.GTPE2.TXPH_CFG[2] origin:064-gtp-channel-conf 30_97 -GTP_CHANNEL_3.GTPE2.TXPH_CFG[3] origin:064-gtp-channel-conf 31_97 -GTP_CHANNEL_3.GTPE2.TXPH_CFG[4] origin:064-gtp-channel-conf 30_98 -GTP_CHANNEL_3.GTPE2.TXPH_CFG[5] origin:064-gtp-channel-conf 31_98 -GTP_CHANNEL_3.GTPE2.TXPH_CFG[6] origin:064-gtp-channel-conf 30_99 -GTP_CHANNEL_3.GTPE2.TXPH_CFG[7] origin:064-gtp-channel-conf 31_99 -GTP_CHANNEL_3.GTPE2.TXPH_CFG[8] origin:064-gtp-channel-conf 30_100 -GTP_CHANNEL_3.GTPE2.TXPH_CFG[9] origin:064-gtp-channel-conf 31_100 -GTP_CHANNEL_3.GTPE2.TXPH_CFG[10] origin:064-gtp-channel-conf 30_101 -GTP_CHANNEL_3.GTPE2.TXPH_CFG[11] origin:064-gtp-channel-conf 31_101 -GTP_CHANNEL_3.GTPE2.TXPH_CFG[12] origin:064-gtp-channel-conf 30_102 -GTP_CHANNEL_3.GTPE2.TXPH_CFG[13] origin:064-gtp-channel-conf 31_102 -GTP_CHANNEL_3.GTPE2.TXPH_CFG[14] origin:064-gtp-channel-conf 30_103 -GTP_CHANNEL_3.GTPE2.TXPH_CFG[15] origin:064-gtp-channel-conf 31_103 -GTP_CHANNEL_3.GTPE2.TXPH_MONITOR_SEL[0] origin:064-gtp-channel-conf 30_108 -GTP_CHANNEL_3.GTPE2.TXPH_MONITOR_SEL[1] origin:064-gtp-channel-conf 31_108 -GTP_CHANNEL_3.GTPE2.TXPH_MONITOR_SEL[2] origin:064-gtp-channel-conf 30_109 -GTP_CHANNEL_3.GTPE2.TXPH_MONITOR_SEL[3] origin:064-gtp-channel-conf 31_109 -GTP_CHANNEL_3.GTPE2.TXPH_MONITOR_SEL[4] origin:064-gtp-channel-conf 30_110 -GTP_CHANNEL_3.GTPE2.TXPHDLY_CFG[0] origin:064-gtp-channel-conf 30_64 -GTP_CHANNEL_3.GTPE2.TXPHDLY_CFG[1] origin:064-gtp-channel-conf 31_64 -GTP_CHANNEL_3.GTPE2.TXPHDLY_CFG[2] origin:064-gtp-channel-conf 30_65 -GTP_CHANNEL_3.GTPE2.TXPHDLY_CFG[3] origin:064-gtp-channel-conf 31_65 -GTP_CHANNEL_3.GTPE2.TXPHDLY_CFG[4] origin:064-gtp-channel-conf 30_66 -GTP_CHANNEL_3.GTPE2.TXPHDLY_CFG[5] origin:064-gtp-channel-conf 31_66 -GTP_CHANNEL_3.GTPE2.TXPHDLY_CFG[6] origin:064-gtp-channel-conf 30_67 -GTP_CHANNEL_3.GTPE2.TXPHDLY_CFG[7] origin:064-gtp-channel-conf 31_67 -GTP_CHANNEL_3.GTPE2.TXPHDLY_CFG[8] origin:064-gtp-channel-conf 30_68 -GTP_CHANNEL_3.GTPE2.TXPHDLY_CFG[9] origin:064-gtp-channel-conf 31_68 -GTP_CHANNEL_3.GTPE2.TXPHDLY_CFG[10] origin:064-gtp-channel-conf 30_69 -GTP_CHANNEL_3.GTPE2.TXPHDLY_CFG[11] origin:064-gtp-channel-conf 31_69 -GTP_CHANNEL_3.GTPE2.TXPHDLY_CFG[12] origin:064-gtp-channel-conf 30_70 -GTP_CHANNEL_3.GTPE2.TXPHDLY_CFG[13] origin:064-gtp-channel-conf 31_70 -GTP_CHANNEL_3.GTPE2.TXPHDLY_CFG[14] origin:064-gtp-channel-conf 30_71 -GTP_CHANNEL_3.GTPE2.TXPHDLY_CFG[15] origin:064-gtp-channel-conf 31_71 -GTP_CHANNEL_3.GTPE2.TXPHDLY_CFG[16] origin:064-gtp-channel-conf 30_72 -GTP_CHANNEL_3.GTPE2.TXPHDLY_CFG[17] origin:064-gtp-channel-conf 31_72 -GTP_CHANNEL_3.GTPE2.TXPHDLY_CFG[18] origin:064-gtp-channel-conf 30_73 -GTP_CHANNEL_3.GTPE2.TXPHDLY_CFG[19] origin:064-gtp-channel-conf 31_73 -GTP_CHANNEL_3.GTPE2.TXPHDLY_CFG[20] origin:064-gtp-channel-conf 30_74 -GTP_CHANNEL_3.GTPE2.TXPHDLY_CFG[21] origin:064-gtp-channel-conf 31_74 -GTP_CHANNEL_3.GTPE2.TXPHDLY_CFG[22] origin:064-gtp-channel-conf 30_75 -GTP_CHANNEL_3.GTPE2.TXPHDLY_CFG[23] origin:064-gtp-channel-conf 31_75 -GTP_CHANNEL_3.GTPE2.TXPI_GREY_SEL[0] origin:064-gtp-channel-conf 31_498 -GTP_CHANNEL_3.GTPE2.TXPI_INVSTROBE_SEL[0] origin:064-gtp-channel-conf 30_498 -GTP_CHANNEL_3.GTPE2.TXPI_PPM_CFG[0] origin:064-gtp-channel-conf 30_488 -GTP_CHANNEL_3.GTPE2.TXPI_PPM_CFG[1] origin:064-gtp-channel-conf 31_488 -GTP_CHANNEL_3.GTPE2.TXPI_PPM_CFG[2] origin:064-gtp-channel-conf 30_489 -GTP_CHANNEL_3.GTPE2.TXPI_PPM_CFG[3] origin:064-gtp-channel-conf 31_489 -GTP_CHANNEL_3.GTPE2.TXPI_PPM_CFG[4] origin:064-gtp-channel-conf 30_490 -GTP_CHANNEL_3.GTPE2.TXPI_PPM_CFG[5] origin:064-gtp-channel-conf 31_490 -GTP_CHANNEL_3.GTPE2.TXPI_PPM_CFG[6] origin:064-gtp-channel-conf 30_491 -GTP_CHANNEL_3.GTPE2.TXPI_PPM_CFG[7] origin:064-gtp-channel-conf 31_491 -GTP_CHANNEL_3.GTPE2.TXPI_PPMCLK_SEL.TXUSRCLK2 origin:064-gtp-channel-conf 31_497 -GTP_CHANNEL_3.GTPE2.TXPI_SYNFREQ_PPM[0] origin:064-gtp-channel-conf 30_496 -GTP_CHANNEL_3.GTPE2.TXPI_SYNFREQ_PPM[1] origin:064-gtp-channel-conf 31_496 -GTP_CHANNEL_3.GTPE2.TXPI_SYNFREQ_PPM[2] origin:064-gtp-channel-conf 30_497 -GTP_CHANNEL_3.GTPE2.TXPI_CFG0[0] origin:064-gtp-channel-conf 30_40 -GTP_CHANNEL_3.GTPE2.TXPI_CFG0[1] origin:064-gtp-channel-conf 31_40 -GTP_CHANNEL_3.GTPE2.TXPI_CFG1[0] origin:064-gtp-channel-conf 30_41 -GTP_CHANNEL_3.GTPE2.TXPI_CFG1[1] origin:064-gtp-channel-conf 31_41 -GTP_CHANNEL_3.GTPE2.TXPI_CFG2[0] origin:064-gtp-channel-conf 30_42 -GTP_CHANNEL_3.GTPE2.TXPI_CFG2[1] origin:064-gtp-channel-conf 31_42 -GTP_CHANNEL_3.GTPE2.TXPI_CFG3[0] origin:064-gtp-channel-conf 30_43 -GTP_CHANNEL_3.GTPE2.TXPI_CFG4[0] origin:064-gtp-channel-conf 31_43 -GTP_CHANNEL_3.GTPE2.TXPI_CFG5[0] origin:064-gtp-channel-conf 30_44 -GTP_CHANNEL_3.GTPE2.TXPI_CFG5[1] origin:064-gtp-channel-conf 31_44 -GTP_CHANNEL_3.GTPE2.TXPI_CFG5[2] origin:064-gtp-channel-conf 30_45 -GTP_CHANNEL_3.GTPE2.TXPMARESET_TIME[0] origin:064-gtp-channel-conf 28_128 -GTP_CHANNEL_3.GTPE2.TXPMARESET_TIME[1] origin:064-gtp-channel-conf 29_128 -GTP_CHANNEL_3.GTPE2.TXPMARESET_TIME[2] origin:064-gtp-channel-conf 28_129 -GTP_CHANNEL_3.GTPE2.TXPMARESET_TIME[3] origin:064-gtp-channel-conf 29_129 -GTP_CHANNEL_3.GTPE2.TXPMARESET_TIME[4] origin:064-gtp-channel-conf 28_130 -GTP_CHANNEL_3.GTPE2.TXSYNC_MULTILANE[0] origin:064-gtp-channel-conf 29_133 -GTP_CHANNEL_3.GTPE2.TXSYNC_OVRD[0] origin:064-gtp-channel-conf 28_135 -GTP_CHANNEL_3.GTPE2.TXSYNC_SKIP_DA[0] origin:064-gtp-channel-conf 28_134 -GTP_CHANNEL_3.GTPE2.UCODEER_CLR[0] origin:064-gtp-channel-conf 29_00 -GTP_CHANNEL_3.GTPE2.USE_PCS_CLK_PHASE_SEL[0] origin:064-gtp-channel-conf 30_463 -GTP_CHANNEL_3.GTPE2.ZINV_DMONITORCLK origin:064-gtp-channel-conf 30_13 -GTP_CHANNEL_3.GTPE2.ZINV_DRPCLK origin:064-gtp-channel-conf 30_00 -GTP_CHANNEL_3.GTPE2.ZINV_RXUSRCLK origin:064-gtp-channel-conf 31_01 -GTP_CHANNEL_3.GTPE2.ZINV_SIGVALIDCLK origin:064-gtp-channel-conf 31_13 -GTP_CHANNEL_3.GTPE2.ZINV_TXPHDLYTSTCLK origin:064-gtp-channel-conf 30_03 -GTP_CHANNEL_3.GTPE2.ZINV_TXUSRCLK origin:064-gtp-channel-conf 31_04 -GTP_CHANNEL_3.GTPE2.ZINV_CLKRSVD0 origin:064-gtp-channel-conf 30_23 -GTP_CHANNEL_3.GTPE2.ZINV_CLKRSVD1 origin:064-gtp-channel-conf 31_23 -GTP_CHANNEL_3.GTPE2.ZINV_RXUSRCLK2 origin:064-gtp-channel-conf 30_02 -GTP_CHANNEL_3.GTPE2.ZINV_TXUSRCLK2 origin:064-gtp-channel-conf 30_05 +GTP_CHANNEL_3.GTPE2_CHANNEL.ACJTAG_DEBUG_MODE[0] origin:064-gtp-channel-conf 28_07 +GTP_CHANNEL_3.GTPE2_CHANNEL.ACJTAG_MODE[0] origin:064-gtp-channel-conf 29_06 +GTP_CHANNEL_3.GTPE2_CHANNEL.ACJTAG_RESET[0] origin:064-gtp-channel-conf 29_07 +GTP_CHANNEL_3.GTPE2_CHANNEL.ADAPT_CFG0[0] origin:064-gtp-channel-conf 30_464 +GTP_CHANNEL_3.GTPE2_CHANNEL.ADAPT_CFG0[1] origin:064-gtp-channel-conf 31_464 +GTP_CHANNEL_3.GTPE2_CHANNEL.ADAPT_CFG0[2] origin:064-gtp-channel-conf 30_465 +GTP_CHANNEL_3.GTPE2_CHANNEL.ADAPT_CFG0[3] origin:064-gtp-channel-conf 31_465 +GTP_CHANNEL_3.GTPE2_CHANNEL.ADAPT_CFG0[4] origin:064-gtp-channel-conf 30_466 +GTP_CHANNEL_3.GTPE2_CHANNEL.ADAPT_CFG0[5] origin:064-gtp-channel-conf 31_466 +GTP_CHANNEL_3.GTPE2_CHANNEL.ADAPT_CFG0[6] origin:064-gtp-channel-conf 30_467 +GTP_CHANNEL_3.GTPE2_CHANNEL.ADAPT_CFG0[7] origin:064-gtp-channel-conf 31_467 +GTP_CHANNEL_3.GTPE2_CHANNEL.ADAPT_CFG0[8] origin:064-gtp-channel-conf 30_468 +GTP_CHANNEL_3.GTPE2_CHANNEL.ADAPT_CFG0[9] origin:064-gtp-channel-conf 31_468 +GTP_CHANNEL_3.GTPE2_CHANNEL.ADAPT_CFG0[10] origin:064-gtp-channel-conf 30_469 +GTP_CHANNEL_3.GTPE2_CHANNEL.ADAPT_CFG0[11] origin:064-gtp-channel-conf 31_469 +GTP_CHANNEL_3.GTPE2_CHANNEL.ADAPT_CFG0[12] origin:064-gtp-channel-conf 30_470 +GTP_CHANNEL_3.GTPE2_CHANNEL.ADAPT_CFG0[13] origin:064-gtp-channel-conf 31_470 +GTP_CHANNEL_3.GTPE2_CHANNEL.ADAPT_CFG0[14] origin:064-gtp-channel-conf 30_471 +GTP_CHANNEL_3.GTPE2_CHANNEL.ADAPT_CFG0[15] origin:064-gtp-channel-conf 31_471 +GTP_CHANNEL_3.GTPE2_CHANNEL.ADAPT_CFG0[16] origin:064-gtp-channel-conf 30_472 +GTP_CHANNEL_3.GTPE2_CHANNEL.ADAPT_CFG0[17] origin:064-gtp-channel-conf 31_472 +GTP_CHANNEL_3.GTPE2_CHANNEL.ADAPT_CFG0[18] origin:064-gtp-channel-conf 30_473 +GTP_CHANNEL_3.GTPE2_CHANNEL.ADAPT_CFG0[19] origin:064-gtp-channel-conf 31_473 +GTP_CHANNEL_3.GTPE2_CHANNEL.ALIGN_COMMA_DOUBLE origin:064-gtp-channel-conf 28_522 +GTP_CHANNEL_3.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[0] origin:064-gtp-channel-conf 28_496 +GTP_CHANNEL_3.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[1] origin:064-gtp-channel-conf 29_496 +GTP_CHANNEL_3.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[2] origin:064-gtp-channel-conf 28_497 +GTP_CHANNEL_3.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[3] origin:064-gtp-channel-conf 29_497 +GTP_CHANNEL_3.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[4] origin:064-gtp-channel-conf 28_498 +GTP_CHANNEL_3.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[5] origin:064-gtp-channel-conf 29_498 +GTP_CHANNEL_3.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[6] origin:064-gtp-channel-conf 28_499 +GTP_CHANNEL_3.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[7] origin:064-gtp-channel-conf 29_499 +GTP_CHANNEL_3.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[8] origin:064-gtp-channel-conf 28_500 +GTP_CHANNEL_3.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[9] origin:064-gtp-channel-conf 29_500 +GTP_CHANNEL_3.GTPE2_CHANNEL.ALIGN_COMMA_WORD[0] origin:064-gtp-channel-conf 29_526 +GTP_CHANNEL_3.GTPE2_CHANNEL.ALIGN_COMMA_WORD[1] origin:064-gtp-channel-conf 28_527 +GTP_CHANNEL_3.GTPE2_CHANNEL.ALIGN_MCOMMA_DET origin:064-gtp-channel-conf 28_523 +GTP_CHANNEL_3.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[0] origin:064-gtp-channel-conf 28_504 +GTP_CHANNEL_3.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[1] origin:064-gtp-channel-conf 29_504 +GTP_CHANNEL_3.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[2] origin:064-gtp-channel-conf 28_505 +GTP_CHANNEL_3.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[3] origin:064-gtp-channel-conf 29_505 +GTP_CHANNEL_3.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[4] origin:064-gtp-channel-conf 28_506 +GTP_CHANNEL_3.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[5] origin:064-gtp-channel-conf 29_506 +GTP_CHANNEL_3.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[6] origin:064-gtp-channel-conf 28_507 +GTP_CHANNEL_3.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[7] origin:064-gtp-channel-conf 29_507 +GTP_CHANNEL_3.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[8] origin:064-gtp-channel-conf 28_508 +GTP_CHANNEL_3.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[9] origin:064-gtp-channel-conf 29_508 +GTP_CHANNEL_3.GTPE2_CHANNEL.ALIGN_PCOMMA_DET origin:064-gtp-channel-conf 29_523 +GTP_CHANNEL_3.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[0] origin:064-gtp-channel-conf 28_512 +GTP_CHANNEL_3.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[1] origin:064-gtp-channel-conf 29_512 +GTP_CHANNEL_3.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[2] origin:064-gtp-channel-conf 28_513 +GTP_CHANNEL_3.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[3] origin:064-gtp-channel-conf 29_513 +GTP_CHANNEL_3.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[4] origin:064-gtp-channel-conf 28_514 +GTP_CHANNEL_3.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[5] origin:064-gtp-channel-conf 29_514 +GTP_CHANNEL_3.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[6] origin:064-gtp-channel-conf 28_515 +GTP_CHANNEL_3.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[7] origin:064-gtp-channel-conf 29_515 +GTP_CHANNEL_3.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[8] origin:064-gtp-channel-conf 28_516 +GTP_CHANNEL_3.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[9] origin:064-gtp-channel-conf 29_516 +GTP_CHANNEL_3.GTPE2_CHANNEL.CBCC_DATA_SOURCE_SEL.DECODED origin:064-gtp-channel-conf 29_661 +GTP_CHANNEL_3.GTPE2_CHANNEL.CFOK_CFG[0] origin:064-gtp-channel-conf 30_392 +GTP_CHANNEL_3.GTPE2_CHANNEL.CFOK_CFG[1] origin:064-gtp-channel-conf 31_392 +GTP_CHANNEL_3.GTPE2_CHANNEL.CFOK_CFG[2] origin:064-gtp-channel-conf 30_393 +GTP_CHANNEL_3.GTPE2_CHANNEL.CFOK_CFG[3] origin:064-gtp-channel-conf 31_393 +GTP_CHANNEL_3.GTPE2_CHANNEL.CFOK_CFG[4] origin:064-gtp-channel-conf 30_394 +GTP_CHANNEL_3.GTPE2_CHANNEL.CFOK_CFG[5] origin:064-gtp-channel-conf 31_394 +GTP_CHANNEL_3.GTPE2_CHANNEL.CFOK_CFG[6] origin:064-gtp-channel-conf 30_395 +GTP_CHANNEL_3.GTPE2_CHANNEL.CFOK_CFG[7] origin:064-gtp-channel-conf 31_395 +GTP_CHANNEL_3.GTPE2_CHANNEL.CFOK_CFG[8] origin:064-gtp-channel-conf 30_396 +GTP_CHANNEL_3.GTPE2_CHANNEL.CFOK_CFG[9] origin:064-gtp-channel-conf 31_396 +GTP_CHANNEL_3.GTPE2_CHANNEL.CFOK_CFG[10] origin:064-gtp-channel-conf 30_397 +GTP_CHANNEL_3.GTPE2_CHANNEL.CFOK_CFG[11] origin:064-gtp-channel-conf 31_397 +GTP_CHANNEL_3.GTPE2_CHANNEL.CFOK_CFG[12] origin:064-gtp-channel-conf 30_398 +GTP_CHANNEL_3.GTPE2_CHANNEL.CFOK_CFG[13] origin:064-gtp-channel-conf 31_398 +GTP_CHANNEL_3.GTPE2_CHANNEL.CFOK_CFG[14] origin:064-gtp-channel-conf 30_399 +GTP_CHANNEL_3.GTPE2_CHANNEL.CFOK_CFG[15] origin:064-gtp-channel-conf 31_399 +GTP_CHANNEL_3.GTPE2_CHANNEL.CFOK_CFG[16] origin:064-gtp-channel-conf 30_400 +GTP_CHANNEL_3.GTPE2_CHANNEL.CFOK_CFG[17] origin:064-gtp-channel-conf 31_400 +GTP_CHANNEL_3.GTPE2_CHANNEL.CFOK_CFG[18] origin:064-gtp-channel-conf 30_401 +GTP_CHANNEL_3.GTPE2_CHANNEL.CFOK_CFG[19] origin:064-gtp-channel-conf 31_401 +GTP_CHANNEL_3.GTPE2_CHANNEL.CFOK_CFG[20] origin:064-gtp-channel-conf 30_402 +GTP_CHANNEL_3.GTPE2_CHANNEL.CFOK_CFG[21] origin:064-gtp-channel-conf 31_402 +GTP_CHANNEL_3.GTPE2_CHANNEL.CFOK_CFG[22] origin:064-gtp-channel-conf 30_403 +GTP_CHANNEL_3.GTPE2_CHANNEL.CFOK_CFG[23] origin:064-gtp-channel-conf 31_403 +GTP_CHANNEL_3.GTPE2_CHANNEL.CFOK_CFG[24] origin:064-gtp-channel-conf 30_404 +GTP_CHANNEL_3.GTPE2_CHANNEL.CFOK_CFG[25] origin:064-gtp-channel-conf 31_404 +GTP_CHANNEL_3.GTPE2_CHANNEL.CFOK_CFG[26] origin:064-gtp-channel-conf 30_405 +GTP_CHANNEL_3.GTPE2_CHANNEL.CFOK_CFG[27] origin:064-gtp-channel-conf 31_405 +GTP_CHANNEL_3.GTPE2_CHANNEL.CFOK_CFG[28] origin:064-gtp-channel-conf 30_406 +GTP_CHANNEL_3.GTPE2_CHANNEL.CFOK_CFG[29] origin:064-gtp-channel-conf 31_406 +GTP_CHANNEL_3.GTPE2_CHANNEL.CFOK_CFG[30] origin:064-gtp-channel-conf 30_407 +GTP_CHANNEL_3.GTPE2_CHANNEL.CFOK_CFG[31] origin:064-gtp-channel-conf 31_407 +GTP_CHANNEL_3.GTPE2_CHANNEL.CFOK_CFG[32] origin:064-gtp-channel-conf 30_408 +GTP_CHANNEL_3.GTPE2_CHANNEL.CFOK_CFG[33] origin:064-gtp-channel-conf 31_408 +GTP_CHANNEL_3.GTPE2_CHANNEL.CFOK_CFG[34] origin:064-gtp-channel-conf 30_409 +GTP_CHANNEL_3.GTPE2_CHANNEL.CFOK_CFG[35] origin:064-gtp-channel-conf 31_409 +GTP_CHANNEL_3.GTPE2_CHANNEL.CFOK_CFG[36] origin:064-gtp-channel-conf 30_410 +GTP_CHANNEL_3.GTPE2_CHANNEL.CFOK_CFG[37] origin:064-gtp-channel-conf 31_410 +GTP_CHANNEL_3.GTPE2_CHANNEL.CFOK_CFG[38] origin:064-gtp-channel-conf 30_411 +GTP_CHANNEL_3.GTPE2_CHANNEL.CFOK_CFG[39] origin:064-gtp-channel-conf 31_411 +GTP_CHANNEL_3.GTPE2_CHANNEL.CFOK_CFG[40] origin:064-gtp-channel-conf 30_412 +GTP_CHANNEL_3.GTPE2_CHANNEL.CFOK_CFG[41] origin:064-gtp-channel-conf 31_412 +GTP_CHANNEL_3.GTPE2_CHANNEL.CFOK_CFG[42] origin:064-gtp-channel-conf 30_413 +GTP_CHANNEL_3.GTPE2_CHANNEL.CFOK_CFG2[0] origin:064-gtp-channel-conf 30_459 +GTP_CHANNEL_3.GTPE2_CHANNEL.CFOK_CFG2[1] origin:064-gtp-channel-conf 31_459 +GTP_CHANNEL_3.GTPE2_CHANNEL.CFOK_CFG2[2] origin:064-gtp-channel-conf 30_460 +GTP_CHANNEL_3.GTPE2_CHANNEL.CFOK_CFG2[3] origin:064-gtp-channel-conf 31_460 +GTP_CHANNEL_3.GTPE2_CHANNEL.CFOK_CFG2[4] origin:064-gtp-channel-conf 30_461 +GTP_CHANNEL_3.GTPE2_CHANNEL.CFOK_CFG2[5] origin:064-gtp-channel-conf 31_461 +GTP_CHANNEL_3.GTPE2_CHANNEL.CFOK_CFG2[6] origin:064-gtp-channel-conf 30_462 +GTP_CHANNEL_3.GTPE2_CHANNEL.CFOK_CFG3[0] origin:064-gtp-channel-conf 30_416 +GTP_CHANNEL_3.GTPE2_CHANNEL.CFOK_CFG3[1] origin:064-gtp-channel-conf 31_416 +GTP_CHANNEL_3.GTPE2_CHANNEL.CFOK_CFG3[2] origin:064-gtp-channel-conf 30_417 +GTP_CHANNEL_3.GTPE2_CHANNEL.CFOK_CFG3[3] origin:064-gtp-channel-conf 31_417 +GTP_CHANNEL_3.GTPE2_CHANNEL.CFOK_CFG3[4] origin:064-gtp-channel-conf 30_418 +GTP_CHANNEL_3.GTPE2_CHANNEL.CFOK_CFG3[5] origin:064-gtp-channel-conf 31_418 +GTP_CHANNEL_3.GTPE2_CHANNEL.CFOK_CFG3[6] origin:064-gtp-channel-conf 30_419 +GTP_CHANNEL_3.GTPE2_CHANNEL.CFOK_CFG4[0] origin:064-gtp-channel-conf 31_438 +GTP_CHANNEL_3.GTPE2_CHANNEL.CFOK_CFG5[0] origin:064-gtp-channel-conf 30_429 +GTP_CHANNEL_3.GTPE2_CHANNEL.CFOK_CFG5[1] origin:064-gtp-channel-conf 31_429 +GTP_CHANNEL_3.GTPE2_CHANNEL.CFOK_CFG6[0] origin:064-gtp-channel-conf 31_436 +GTP_CHANNEL_3.GTPE2_CHANNEL.CFOK_CFG6[1] origin:064-gtp-channel-conf 30_437 +GTP_CHANNEL_3.GTPE2_CHANNEL.CFOK_CFG6[2] origin:064-gtp-channel-conf 31_437 +GTP_CHANNEL_3.GTPE2_CHANNEL.CFOK_CFG6[3] origin:064-gtp-channel-conf 30_438 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_KEEP_ALIGN origin:064-gtp-channel-conf 29_631 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_MAX_SKEW[0] origin:064-gtp-channel-conf 28_670 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_MAX_SKEW[1] origin:064-gtp-channel-conf 29_670 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_MAX_SKEW[2] origin:064-gtp-channel-conf 28_671 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_MAX_SKEW[3] origin:064-gtp-channel-conf 29_671 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[0] origin:064-gtp-channel-conf 28_608 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[1] origin:064-gtp-channel-conf 29_608 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[2] origin:064-gtp-channel-conf 28_609 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[3] origin:064-gtp-channel-conf 29_609 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[4] origin:064-gtp-channel-conf 28_610 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[5] origin:064-gtp-channel-conf 29_610 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[6] origin:064-gtp-channel-conf 28_611 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[7] origin:064-gtp-channel-conf 29_611 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[8] origin:064-gtp-channel-conf 28_612 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[9] origin:064-gtp-channel-conf 29_612 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[0] origin:064-gtp-channel-conf 28_616 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[1] origin:064-gtp-channel-conf 29_616 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[2] origin:064-gtp-channel-conf 28_617 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[3] origin:064-gtp-channel-conf 29_617 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[4] origin:064-gtp-channel-conf 28_618 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[5] origin:064-gtp-channel-conf 29_618 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[6] origin:064-gtp-channel-conf 28_619 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[7] origin:064-gtp-channel-conf 29_619 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[8] origin:064-gtp-channel-conf 28_620 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[9] origin:064-gtp-channel-conf 29_620 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[0] origin:064-gtp-channel-conf 28_624 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[1] origin:064-gtp-channel-conf 29_624 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[2] origin:064-gtp-channel-conf 28_625 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[3] origin:064-gtp-channel-conf 29_625 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[4] origin:064-gtp-channel-conf 28_626 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[5] origin:064-gtp-channel-conf 29_626 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[6] origin:064-gtp-channel-conf 28_627 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[7] origin:064-gtp-channel-conf 29_627 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[8] origin:064-gtp-channel-conf 28_628 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[9] origin:064-gtp-channel-conf 29_628 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[0] origin:064-gtp-channel-conf 28_632 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[1] origin:064-gtp-channel-conf 29_632 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[2] origin:064-gtp-channel-conf 28_633 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[3] origin:064-gtp-channel-conf 29_633 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[4] origin:064-gtp-channel-conf 28_634 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[5] origin:064-gtp-channel-conf 29_634 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[6] origin:064-gtp-channel-conf 28_635 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[7] origin:064-gtp-channel-conf 29_635 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[8] origin:064-gtp-channel-conf 28_636 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[9] origin:064-gtp-channel-conf 29_636 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_ENABLE[0] origin:064-gtp-channel-conf 28_614 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_ENABLE[1] origin:064-gtp-channel-conf 29_614 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_ENABLE[2] origin:064-gtp-channel-conf 28_615 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_ENABLE[3] origin:064-gtp-channel-conf 29_615 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[0] origin:064-gtp-channel-conf 28_640 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[1] origin:064-gtp-channel-conf 29_640 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[2] origin:064-gtp-channel-conf 28_641 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[3] origin:064-gtp-channel-conf 29_641 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[4] origin:064-gtp-channel-conf 28_642 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[5] origin:064-gtp-channel-conf 29_642 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[6] origin:064-gtp-channel-conf 28_643 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[7] origin:064-gtp-channel-conf 29_643 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[8] origin:064-gtp-channel-conf 28_644 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[9] origin:064-gtp-channel-conf 29_644 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[0] origin:064-gtp-channel-conf 28_648 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[1] origin:064-gtp-channel-conf 29_648 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[2] origin:064-gtp-channel-conf 28_649 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[3] origin:064-gtp-channel-conf 29_649 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[4] origin:064-gtp-channel-conf 28_650 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[5] origin:064-gtp-channel-conf 29_650 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[6] origin:064-gtp-channel-conf 28_651 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[7] origin:064-gtp-channel-conf 29_651 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[8] origin:064-gtp-channel-conf 28_652 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[9] origin:064-gtp-channel-conf 29_652 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[0] origin:064-gtp-channel-conf 28_656 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[1] origin:064-gtp-channel-conf 29_656 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[2] origin:064-gtp-channel-conf 28_657 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[3] origin:064-gtp-channel-conf 29_657 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[4] origin:064-gtp-channel-conf 28_658 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[5] origin:064-gtp-channel-conf 29_658 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[6] origin:064-gtp-channel-conf 28_659 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[7] origin:064-gtp-channel-conf 29_659 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[8] origin:064-gtp-channel-conf 28_660 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[9] origin:064-gtp-channel-conf 29_660 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[0] origin:064-gtp-channel-conf 28_664 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[1] origin:064-gtp-channel-conf 29_664 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[2] origin:064-gtp-channel-conf 28_665 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[3] origin:064-gtp-channel-conf 29_665 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[4] origin:064-gtp-channel-conf 28_666 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[5] origin:064-gtp-channel-conf 29_666 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[6] origin:064-gtp-channel-conf 28_667 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[7] origin:064-gtp-channel-conf 29_667 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[8] origin:064-gtp-channel-conf 28_668 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[9] origin:064-gtp-channel-conf 29_668 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_ENABLE[0] origin:064-gtp-channel-conf 28_646 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_ENABLE[1] origin:064-gtp-channel-conf 29_646 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_ENABLE[2] origin:064-gtp-channel-conf 28_647 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_ENABLE[3] origin:064-gtp-channel-conf 29_647 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_USE origin:064-gtp-channel-conf 29_645 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_LEN[0] origin:064-gtp-channel-conf 28_623 +GTP_CHANNEL_3.GTPE2_CHANNEL.CHAN_BOND_SEQ_LEN[1] origin:064-gtp-channel-conf 29_623 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COMMON_SWING[0] origin:064-gtp-channel-conf 31_311 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_KEEP_IDLE origin:064-gtp-channel-conf 28_591 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_MAX_LAT[0] origin:064-gtp-channel-conf 28_557 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_MAX_LAT[1] origin:064-gtp-channel-conf 29_557 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_MAX_LAT[2] origin:064-gtp-channel-conf 28_558 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_MAX_LAT[3] origin:064-gtp-channel-conf 29_558 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_MAX_LAT[4] origin:064-gtp-channel-conf 28_559 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_MAX_LAT[5] origin:064-gtp-channel-conf 29_559 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_MIN_LAT[0] origin:064-gtp-channel-conf 28_565 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_MIN_LAT[1] origin:064-gtp-channel-conf 29_565 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_MIN_LAT[2] origin:064-gtp-channel-conf 28_566 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_MIN_LAT[3] origin:064-gtp-channel-conf 29_566 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_MIN_LAT[4] origin:064-gtp-channel-conf 28_567 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_MIN_LAT[5] origin:064-gtp-channel-conf 29_567 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_PRECEDENCE origin:064-gtp-channel-conf 28_590 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_REPEAT_WAIT[0] origin:064-gtp-channel-conf 28_573 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_REPEAT_WAIT[1] origin:064-gtp-channel-conf 29_573 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_REPEAT_WAIT[2] origin:064-gtp-channel-conf 28_574 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_REPEAT_WAIT[3] origin:064-gtp-channel-conf 29_574 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_REPEAT_WAIT[4] origin:064-gtp-channel-conf 28_575 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[0] origin:064-gtp-channel-conf 28_544 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[1] origin:064-gtp-channel-conf 29_544 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[2] origin:064-gtp-channel-conf 28_545 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[3] origin:064-gtp-channel-conf 29_545 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[4] origin:064-gtp-channel-conf 28_546 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[5] origin:064-gtp-channel-conf 29_546 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[6] origin:064-gtp-channel-conf 28_547 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[7] origin:064-gtp-channel-conf 29_547 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[8] origin:064-gtp-channel-conf 28_548 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[9] origin:064-gtp-channel-conf 29_548 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[0] origin:064-gtp-channel-conf 28_552 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[1] origin:064-gtp-channel-conf 29_552 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[2] origin:064-gtp-channel-conf 28_553 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[3] origin:064-gtp-channel-conf 29_553 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[4] origin:064-gtp-channel-conf 28_554 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[5] origin:064-gtp-channel-conf 29_554 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[6] origin:064-gtp-channel-conf 28_555 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[7] origin:064-gtp-channel-conf 29_555 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[8] origin:064-gtp-channel-conf 28_556 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[9] origin:064-gtp-channel-conf 29_556 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[0] origin:064-gtp-channel-conf 28_560 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[1] origin:064-gtp-channel-conf 29_560 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[2] origin:064-gtp-channel-conf 28_561 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[3] origin:064-gtp-channel-conf 29_561 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[4] origin:064-gtp-channel-conf 28_562 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[5] origin:064-gtp-channel-conf 29_562 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[6] origin:064-gtp-channel-conf 28_563 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[7] origin:064-gtp-channel-conf 29_563 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[8] origin:064-gtp-channel-conf 28_564 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[9] origin:064-gtp-channel-conf 29_564 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[0] origin:064-gtp-channel-conf 28_568 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[1] origin:064-gtp-channel-conf 29_568 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[2] origin:064-gtp-channel-conf 28_569 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[3] origin:064-gtp-channel-conf 29_569 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[4] origin:064-gtp-channel-conf 28_570 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[5] origin:064-gtp-channel-conf 29_570 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[6] origin:064-gtp-channel-conf 28_571 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[7] origin:064-gtp-channel-conf 29_571 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[8] origin:064-gtp-channel-conf 28_572 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[9] origin:064-gtp-channel-conf 29_572 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_1_ENABLE[0] origin:064-gtp-channel-conf 28_549 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_1_ENABLE[1] origin:064-gtp-channel-conf 29_549 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_1_ENABLE[2] origin:064-gtp-channel-conf 28_550 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_1_ENABLE[3] origin:064-gtp-channel-conf 29_550 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[0] origin:064-gtp-channel-conf 28_576 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[1] origin:064-gtp-channel-conf 29_576 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[2] origin:064-gtp-channel-conf 28_577 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[3] origin:064-gtp-channel-conf 29_577 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[4] origin:064-gtp-channel-conf 28_578 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[5] origin:064-gtp-channel-conf 29_578 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[6] origin:064-gtp-channel-conf 28_579 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[7] origin:064-gtp-channel-conf 29_579 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[8] origin:064-gtp-channel-conf 28_580 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[9] origin:064-gtp-channel-conf 29_580 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[0] origin:064-gtp-channel-conf 28_584 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[1] origin:064-gtp-channel-conf 29_584 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[2] origin:064-gtp-channel-conf 28_585 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[3] origin:064-gtp-channel-conf 29_585 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[4] origin:064-gtp-channel-conf 28_586 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[5] origin:064-gtp-channel-conf 29_586 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[6] origin:064-gtp-channel-conf 28_587 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[7] origin:064-gtp-channel-conf 29_587 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[8] origin:064-gtp-channel-conf 28_588 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[9] origin:064-gtp-channel-conf 29_588 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[0] origin:064-gtp-channel-conf 28_592 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[1] origin:064-gtp-channel-conf 29_592 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[2] origin:064-gtp-channel-conf 28_593 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[3] origin:064-gtp-channel-conf 29_593 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[4] origin:064-gtp-channel-conf 28_594 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[5] origin:064-gtp-channel-conf 29_594 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[6] origin:064-gtp-channel-conf 28_595 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[7] origin:064-gtp-channel-conf 29_595 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[8] origin:064-gtp-channel-conf 28_596 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[9] origin:064-gtp-channel-conf 29_596 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[0] origin:064-gtp-channel-conf 28_600 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[1] origin:064-gtp-channel-conf 29_600 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[2] origin:064-gtp-channel-conf 28_601 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[3] origin:064-gtp-channel-conf 29_601 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[4] origin:064-gtp-channel-conf 28_602 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[5] origin:064-gtp-channel-conf 29_602 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[6] origin:064-gtp-channel-conf 28_603 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[7] origin:064-gtp-channel-conf 29_603 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[8] origin:064-gtp-channel-conf 28_604 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[9] origin:064-gtp-channel-conf 29_604 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_2_ENABLE[0] origin:064-gtp-channel-conf 28_581 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_2_ENABLE[1] origin:064-gtp-channel-conf 29_581 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_2_ENABLE[2] origin:064-gtp-channel-conf 28_582 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_2_ENABLE[3] origin:064-gtp-channel-conf 29_582 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_2_USE origin:064-gtp-channel-conf 28_583 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_LEN[0] origin:064-gtp-channel-conf 28_589 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_COR_SEQ_LEN[1] origin:064-gtp-channel-conf 29_589 +GTP_CHANNEL_3.GTPE2_CHANNEL.CLK_CORRECT_USE origin:064-gtp-channel-conf 28_551 +GTP_CHANNEL_3.GTPE2_CHANNEL.DEC_MCOMMA_DETECT origin:064-gtp-channel-conf 29_494 +GTP_CHANNEL_3.GTPE2_CHANNEL.DEC_PCOMMA_DETECT origin:064-gtp-channel-conf 28_495 +GTP_CHANNEL_3.GTPE2_CHANNEL.DEC_VALID_COMMA_ONLY origin:064-gtp-channel-conf 28_494 +GTP_CHANNEL_3.GTPE2_CHANNEL.DMONITOR_CFG[0] origin:064-gtp-channel-conf 30_368 +GTP_CHANNEL_3.GTPE2_CHANNEL.DMONITOR_CFG[1] origin:064-gtp-channel-conf 31_368 +GTP_CHANNEL_3.GTPE2_CHANNEL.DMONITOR_CFG[2] origin:064-gtp-channel-conf 30_369 +GTP_CHANNEL_3.GTPE2_CHANNEL.DMONITOR_CFG[3] origin:064-gtp-channel-conf 31_369 +GTP_CHANNEL_3.GTPE2_CHANNEL.DMONITOR_CFG[4] origin:064-gtp-channel-conf 30_370 +GTP_CHANNEL_3.GTPE2_CHANNEL.DMONITOR_CFG[5] origin:064-gtp-channel-conf 31_370 +GTP_CHANNEL_3.GTPE2_CHANNEL.DMONITOR_CFG[6] origin:064-gtp-channel-conf 30_371 +GTP_CHANNEL_3.GTPE2_CHANNEL.DMONITOR_CFG[7] origin:064-gtp-channel-conf 31_371 +GTP_CHANNEL_3.GTPE2_CHANNEL.DMONITOR_CFG[8] origin:064-gtp-channel-conf 30_372 +GTP_CHANNEL_3.GTPE2_CHANNEL.DMONITOR_CFG[9] origin:064-gtp-channel-conf 31_372 +GTP_CHANNEL_3.GTPE2_CHANNEL.DMONITOR_CFG[10] origin:064-gtp-channel-conf 30_373 +GTP_CHANNEL_3.GTPE2_CHANNEL.DMONITOR_CFG[11] origin:064-gtp-channel-conf 31_373 +GTP_CHANNEL_3.GTPE2_CHANNEL.DMONITOR_CFG[12] origin:064-gtp-channel-conf 30_374 +GTP_CHANNEL_3.GTPE2_CHANNEL.DMONITOR_CFG[13] origin:064-gtp-channel-conf 31_374 +GTP_CHANNEL_3.GTPE2_CHANNEL.DMONITOR_CFG[14] origin:064-gtp-channel-conf 30_375 +GTP_CHANNEL_3.GTPE2_CHANNEL.DMONITOR_CFG[15] origin:064-gtp-channel-conf 31_375 +GTP_CHANNEL_3.GTPE2_CHANNEL.DMONITOR_CFG[16] origin:064-gtp-channel-conf 30_376 +GTP_CHANNEL_3.GTPE2_CHANNEL.DMONITOR_CFG[17] origin:064-gtp-channel-conf 31_376 +GTP_CHANNEL_3.GTPE2_CHANNEL.DMONITOR_CFG[18] origin:064-gtp-channel-conf 30_377 +GTP_CHANNEL_3.GTPE2_CHANNEL.DMONITOR_CFG[19] origin:064-gtp-channel-conf 31_377 +GTP_CHANNEL_3.GTPE2_CHANNEL.DMONITOR_CFG[20] origin:064-gtp-channel-conf 30_378 +GTP_CHANNEL_3.GTPE2_CHANNEL.DMONITOR_CFG[21] origin:064-gtp-channel-conf 31_378 +GTP_CHANNEL_3.GTPE2_CHANNEL.DMONITOR_CFG[22] origin:064-gtp-channel-conf 30_379 +GTP_CHANNEL_3.GTPE2_CHANNEL.DMONITOR_CFG[23] origin:064-gtp-channel-conf 31_379 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_CLK_PHASE_SEL[0] origin:064-gtp-channel-conf 31_463 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_CONTROL[0] origin:064-gtp-channel-conf 28_488 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_CONTROL[1] origin:064-gtp-channel-conf 29_488 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_CONTROL[2] origin:064-gtp-channel-conf 28_489 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_CONTROL[3] origin:064-gtp-channel-conf 29_489 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_CONTROL[4] origin:064-gtp-channel-conf 28_490 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_CONTROL[5] origin:064-gtp-channel-conf 29_490 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_ERRDET_EN origin:064-gtp-channel-conf 29_492 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_EYE_SCAN_EN origin:064-gtp-channel-conf 28_492 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_HORZ_OFFSET[0] origin:064-gtp-channel-conf 28_480 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_HORZ_OFFSET[1] origin:064-gtp-channel-conf 29_480 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_HORZ_OFFSET[2] origin:064-gtp-channel-conf 28_481 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_HORZ_OFFSET[3] origin:064-gtp-channel-conf 29_481 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_HORZ_OFFSET[4] origin:064-gtp-channel-conf 28_482 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_HORZ_OFFSET[5] origin:064-gtp-channel-conf 29_482 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_HORZ_OFFSET[6] origin:064-gtp-channel-conf 28_483 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_HORZ_OFFSET[7] origin:064-gtp-channel-conf 29_483 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_HORZ_OFFSET[8] origin:064-gtp-channel-conf 28_484 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_HORZ_OFFSET[9] origin:064-gtp-channel-conf 29_484 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_HORZ_OFFSET[10] origin:064-gtp-channel-conf 28_485 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_HORZ_OFFSET[11] origin:064-gtp-channel-conf 29_485 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_PMA_CFG[0] origin:064-gtp-channel-conf 30_624 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_PMA_CFG[1] origin:064-gtp-channel-conf 31_624 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_PMA_CFG[2] origin:064-gtp-channel-conf 30_625 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_PMA_CFG[3] origin:064-gtp-channel-conf 31_625 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_PMA_CFG[4] origin:064-gtp-channel-conf 30_626 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_PMA_CFG[5] origin:064-gtp-channel-conf 31_626 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_PMA_CFG[6] origin:064-gtp-channel-conf 30_627 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_PMA_CFG[7] origin:064-gtp-channel-conf 31_627 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_PMA_CFG[8] origin:064-gtp-channel-conf 30_628 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_PMA_CFG[9] origin:064-gtp-channel-conf 31_628 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_PRESCALE[0] origin:064-gtp-channel-conf 29_477 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_PRESCALE[1] origin:064-gtp-channel-conf 28_478 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_PRESCALE[2] origin:064-gtp-channel-conf 29_478 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_PRESCALE[3] origin:064-gtp-channel-conf 28_479 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_PRESCALE[4] origin:064-gtp-channel-conf 29_479 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[0] origin:064-gtp-channel-conf 28_392 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[1] origin:064-gtp-channel-conf 29_392 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[2] origin:064-gtp-channel-conf 28_393 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[3] origin:064-gtp-channel-conf 29_393 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[4] origin:064-gtp-channel-conf 28_394 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[5] origin:064-gtp-channel-conf 29_394 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[6] origin:064-gtp-channel-conf 28_395 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[7] origin:064-gtp-channel-conf 29_395 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[8] origin:064-gtp-channel-conf 28_396 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[9] origin:064-gtp-channel-conf 29_396 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[10] origin:064-gtp-channel-conf 28_397 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[11] origin:064-gtp-channel-conf 29_397 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[12] origin:064-gtp-channel-conf 28_398 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[13] origin:064-gtp-channel-conf 29_398 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[14] origin:064-gtp-channel-conf 28_399 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[15] origin:064-gtp-channel-conf 29_399 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[16] origin:064-gtp-channel-conf 28_400 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[17] origin:064-gtp-channel-conf 29_400 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[18] origin:064-gtp-channel-conf 28_401 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[19] origin:064-gtp-channel-conf 29_401 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[20] origin:064-gtp-channel-conf 28_402 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[21] origin:064-gtp-channel-conf 29_402 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[22] origin:064-gtp-channel-conf 28_403 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[23] origin:064-gtp-channel-conf 29_403 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[24] origin:064-gtp-channel-conf 28_404 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[25] origin:064-gtp-channel-conf 29_404 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[26] origin:064-gtp-channel-conf 28_405 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[27] origin:064-gtp-channel-conf 29_405 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[28] origin:064-gtp-channel-conf 28_406 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[29] origin:064-gtp-channel-conf 29_406 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[30] origin:064-gtp-channel-conf 28_407 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[31] origin:064-gtp-channel-conf 29_407 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[32] origin:064-gtp-channel-conf 28_408 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[33] origin:064-gtp-channel-conf 29_408 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[34] origin:064-gtp-channel-conf 28_409 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[35] origin:064-gtp-channel-conf 29_409 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[36] origin:064-gtp-channel-conf 28_410 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[37] origin:064-gtp-channel-conf 29_410 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[38] origin:064-gtp-channel-conf 28_411 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[39] origin:064-gtp-channel-conf 29_411 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[40] origin:064-gtp-channel-conf 28_412 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[41] origin:064-gtp-channel-conf 29_412 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[42] origin:064-gtp-channel-conf 28_413 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[43] origin:064-gtp-channel-conf 29_413 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[44] origin:064-gtp-channel-conf 28_414 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[45] origin:064-gtp-channel-conf 29_414 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[46] origin:064-gtp-channel-conf 28_415 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[47] origin:064-gtp-channel-conf 29_415 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[48] origin:064-gtp-channel-conf 28_416 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[49] origin:064-gtp-channel-conf 29_416 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[50] origin:064-gtp-channel-conf 28_417 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[51] origin:064-gtp-channel-conf 29_417 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[52] origin:064-gtp-channel-conf 28_418 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[53] origin:064-gtp-channel-conf 29_418 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[54] origin:064-gtp-channel-conf 28_419 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[55] origin:064-gtp-channel-conf 29_419 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[56] origin:064-gtp-channel-conf 28_420 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[57] origin:064-gtp-channel-conf 29_420 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[58] origin:064-gtp-channel-conf 28_421 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[59] origin:064-gtp-channel-conf 29_421 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[60] origin:064-gtp-channel-conf 28_422 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[61] origin:064-gtp-channel-conf 29_422 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[62] origin:064-gtp-channel-conf 28_423 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[63] origin:064-gtp-channel-conf 29_423 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[64] origin:064-gtp-channel-conf 28_424 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[65] origin:064-gtp-channel-conf 29_424 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[66] origin:064-gtp-channel-conf 28_425 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[67] origin:064-gtp-channel-conf 29_425 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[68] origin:064-gtp-channel-conf 28_426 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[69] origin:064-gtp-channel-conf 29_426 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[70] origin:064-gtp-channel-conf 28_427 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[71] origin:064-gtp-channel-conf 29_427 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[72] origin:064-gtp-channel-conf 28_428 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[73] origin:064-gtp-channel-conf 29_428 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[74] origin:064-gtp-channel-conf 28_429 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[75] origin:064-gtp-channel-conf 29_429 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[76] origin:064-gtp-channel-conf 28_430 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[77] origin:064-gtp-channel-conf 29_430 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[78] origin:064-gtp-channel-conf 28_431 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUAL_MASK[79] origin:064-gtp-channel-conf 29_431 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[0] origin:064-gtp-channel-conf 28_352 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[1] origin:064-gtp-channel-conf 29_352 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[2] origin:064-gtp-channel-conf 28_353 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[3] origin:064-gtp-channel-conf 29_353 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[4] origin:064-gtp-channel-conf 28_354 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[5] origin:064-gtp-channel-conf 29_354 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[6] origin:064-gtp-channel-conf 28_355 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[7] origin:064-gtp-channel-conf 29_355 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[8] origin:064-gtp-channel-conf 28_356 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[9] origin:064-gtp-channel-conf 29_356 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[10] origin:064-gtp-channel-conf 28_357 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[11] origin:064-gtp-channel-conf 29_357 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[12] origin:064-gtp-channel-conf 28_358 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[13] origin:064-gtp-channel-conf 29_358 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[14] origin:064-gtp-channel-conf 28_359 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[15] origin:064-gtp-channel-conf 29_359 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[16] origin:064-gtp-channel-conf 28_360 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[17] origin:064-gtp-channel-conf 29_360 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[18] origin:064-gtp-channel-conf 28_361 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[19] origin:064-gtp-channel-conf 29_361 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[20] origin:064-gtp-channel-conf 28_362 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[21] origin:064-gtp-channel-conf 29_362 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[22] origin:064-gtp-channel-conf 28_363 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[23] origin:064-gtp-channel-conf 29_363 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[24] origin:064-gtp-channel-conf 28_364 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[25] origin:064-gtp-channel-conf 29_364 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[26] origin:064-gtp-channel-conf 28_365 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[27] origin:064-gtp-channel-conf 29_365 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[28] origin:064-gtp-channel-conf 28_366 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[29] origin:064-gtp-channel-conf 29_366 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[30] origin:064-gtp-channel-conf 28_367 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[31] origin:064-gtp-channel-conf 29_367 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[32] origin:064-gtp-channel-conf 28_368 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[33] origin:064-gtp-channel-conf 29_368 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[34] origin:064-gtp-channel-conf 28_369 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[35] origin:064-gtp-channel-conf 29_369 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[36] origin:064-gtp-channel-conf 28_370 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[37] origin:064-gtp-channel-conf 29_370 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[38] origin:064-gtp-channel-conf 28_371 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[39] origin:064-gtp-channel-conf 29_371 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[40] origin:064-gtp-channel-conf 28_372 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[41] origin:064-gtp-channel-conf 29_372 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[42] origin:064-gtp-channel-conf 28_373 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[43] origin:064-gtp-channel-conf 29_373 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[44] origin:064-gtp-channel-conf 28_374 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[45] origin:064-gtp-channel-conf 29_374 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[46] origin:064-gtp-channel-conf 28_375 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[47] origin:064-gtp-channel-conf 29_375 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[48] origin:064-gtp-channel-conf 28_376 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[49] origin:064-gtp-channel-conf 29_376 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[50] origin:064-gtp-channel-conf 28_377 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[51] origin:064-gtp-channel-conf 29_377 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[52] origin:064-gtp-channel-conf 28_378 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[53] origin:064-gtp-channel-conf 29_378 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[54] origin:064-gtp-channel-conf 28_379 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[55] origin:064-gtp-channel-conf 29_379 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[56] origin:064-gtp-channel-conf 28_380 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[57] origin:064-gtp-channel-conf 29_380 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[58] origin:064-gtp-channel-conf 28_381 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[59] origin:064-gtp-channel-conf 29_381 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[60] origin:064-gtp-channel-conf 28_382 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[61] origin:064-gtp-channel-conf 29_382 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[62] origin:064-gtp-channel-conf 28_383 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[63] origin:064-gtp-channel-conf 29_383 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[64] origin:064-gtp-channel-conf 28_384 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[65] origin:064-gtp-channel-conf 29_384 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[66] origin:064-gtp-channel-conf 28_385 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[67] origin:064-gtp-channel-conf 29_385 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[68] origin:064-gtp-channel-conf 28_386 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[69] origin:064-gtp-channel-conf 29_386 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[70] origin:064-gtp-channel-conf 28_387 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[71] origin:064-gtp-channel-conf 29_387 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[72] origin:064-gtp-channel-conf 28_388 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[73] origin:064-gtp-channel-conf 29_388 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[74] origin:064-gtp-channel-conf 28_389 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[75] origin:064-gtp-channel-conf 29_389 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[76] origin:064-gtp-channel-conf 28_390 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[77] origin:064-gtp-channel-conf 29_390 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[78] origin:064-gtp-channel-conf 28_391 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_QUALIFIER[79] origin:064-gtp-channel-conf 29_391 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[0] origin:064-gtp-channel-conf 28_432 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[1] origin:064-gtp-channel-conf 29_432 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[2] origin:064-gtp-channel-conf 28_433 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[3] origin:064-gtp-channel-conf 29_433 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[4] origin:064-gtp-channel-conf 28_434 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[5] origin:064-gtp-channel-conf 29_434 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[6] origin:064-gtp-channel-conf 28_435 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[7] origin:064-gtp-channel-conf 29_435 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[8] origin:064-gtp-channel-conf 28_436 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[9] origin:064-gtp-channel-conf 29_436 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[10] origin:064-gtp-channel-conf 28_437 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[11] origin:064-gtp-channel-conf 29_437 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[12] origin:064-gtp-channel-conf 28_438 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[13] origin:064-gtp-channel-conf 29_438 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[14] origin:064-gtp-channel-conf 28_439 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[15] origin:064-gtp-channel-conf 29_439 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[16] origin:064-gtp-channel-conf 28_440 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[17] origin:064-gtp-channel-conf 29_440 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[18] origin:064-gtp-channel-conf 28_441 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[19] origin:064-gtp-channel-conf 29_441 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[20] origin:064-gtp-channel-conf 28_442 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[21] origin:064-gtp-channel-conf 29_442 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[22] origin:064-gtp-channel-conf 28_443 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[23] origin:064-gtp-channel-conf 29_443 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[24] origin:064-gtp-channel-conf 28_444 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[25] origin:064-gtp-channel-conf 29_444 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[26] origin:064-gtp-channel-conf 28_445 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[27] origin:064-gtp-channel-conf 29_445 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[28] origin:064-gtp-channel-conf 28_446 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[29] origin:064-gtp-channel-conf 29_446 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[30] origin:064-gtp-channel-conf 28_447 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[31] origin:064-gtp-channel-conf 29_447 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[32] origin:064-gtp-channel-conf 28_448 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[33] origin:064-gtp-channel-conf 29_448 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[34] origin:064-gtp-channel-conf 28_449 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[35] origin:064-gtp-channel-conf 29_449 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[36] origin:064-gtp-channel-conf 28_450 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[37] origin:064-gtp-channel-conf 29_450 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[38] origin:064-gtp-channel-conf 28_451 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[39] origin:064-gtp-channel-conf 29_451 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[40] origin:064-gtp-channel-conf 28_452 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[41] origin:064-gtp-channel-conf 29_452 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[42] origin:064-gtp-channel-conf 28_453 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[43] origin:064-gtp-channel-conf 29_453 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[44] origin:064-gtp-channel-conf 28_454 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[45] origin:064-gtp-channel-conf 29_454 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[46] origin:064-gtp-channel-conf 28_455 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[47] origin:064-gtp-channel-conf 29_455 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[48] origin:064-gtp-channel-conf 28_456 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[49] origin:064-gtp-channel-conf 29_456 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[50] origin:064-gtp-channel-conf 28_457 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[51] origin:064-gtp-channel-conf 29_457 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[52] origin:064-gtp-channel-conf 28_458 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[53] origin:064-gtp-channel-conf 29_458 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[54] origin:064-gtp-channel-conf 28_459 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[55] origin:064-gtp-channel-conf 29_459 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[56] origin:064-gtp-channel-conf 28_460 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[57] origin:064-gtp-channel-conf 29_460 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[58] origin:064-gtp-channel-conf 28_461 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[59] origin:064-gtp-channel-conf 29_461 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[60] origin:064-gtp-channel-conf 28_462 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[61] origin:064-gtp-channel-conf 29_462 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[62] origin:064-gtp-channel-conf 28_463 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[63] origin:064-gtp-channel-conf 29_463 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[64] origin:064-gtp-channel-conf 28_464 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[65] origin:064-gtp-channel-conf 29_464 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[66] origin:064-gtp-channel-conf 28_465 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[67] origin:064-gtp-channel-conf 29_465 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[68] origin:064-gtp-channel-conf 28_466 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[69] origin:064-gtp-channel-conf 29_466 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[70] origin:064-gtp-channel-conf 28_467 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[71] origin:064-gtp-channel-conf 29_467 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[72] origin:064-gtp-channel-conf 28_468 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[73] origin:064-gtp-channel-conf 29_468 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[74] origin:064-gtp-channel-conf 28_469 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[75] origin:064-gtp-channel-conf 29_469 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[76] origin:064-gtp-channel-conf 28_470 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[77] origin:064-gtp-channel-conf 29_470 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[78] origin:064-gtp-channel-conf 28_471 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_SDATA_MASK[79] origin:064-gtp-channel-conf 29_471 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_VERT_OFFSET[0] origin:064-gtp-channel-conf 28_472 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_VERT_OFFSET[1] origin:064-gtp-channel-conf 29_472 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_VERT_OFFSET[2] origin:064-gtp-channel-conf 28_473 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_VERT_OFFSET[3] origin:064-gtp-channel-conf 29_473 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_VERT_OFFSET[4] origin:064-gtp-channel-conf 28_474 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_VERT_OFFSET[5] origin:064-gtp-channel-conf 29_474 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_VERT_OFFSET[6] origin:064-gtp-channel-conf 28_475 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_VERT_OFFSET[7] origin:064-gtp-channel-conf 29_475 +GTP_CHANNEL_3.GTPE2_CHANNEL.ES_VERT_OFFSET[8] origin:064-gtp-channel-conf 28_476 +GTP_CHANNEL_3.GTPE2_CHANNEL.FTS_DESKEW_SEQ_ENABLE[0] origin:064-gtp-channel-conf 28_662 +GTP_CHANNEL_3.GTPE2_CHANNEL.FTS_DESKEW_SEQ_ENABLE[1] origin:064-gtp-channel-conf 29_662 +GTP_CHANNEL_3.GTPE2_CHANNEL.FTS_DESKEW_SEQ_ENABLE[2] origin:064-gtp-channel-conf 28_663 +GTP_CHANNEL_3.GTPE2_CHANNEL.FTS_DESKEW_SEQ_ENABLE[3] origin:064-gtp-channel-conf 29_663 +GTP_CHANNEL_3.GTPE2_CHANNEL.FTS_LANE_DESKEW_CFG[0] origin:064-gtp-channel-conf 28_654 +GTP_CHANNEL_3.GTPE2_CHANNEL.FTS_LANE_DESKEW_CFG[1] origin:064-gtp-channel-conf 29_654 +GTP_CHANNEL_3.GTPE2_CHANNEL.FTS_LANE_DESKEW_CFG[2] origin:064-gtp-channel-conf 28_655 +GTP_CHANNEL_3.GTPE2_CHANNEL.FTS_LANE_DESKEW_CFG[3] origin:064-gtp-channel-conf 29_655 +GTP_CHANNEL_3.GTPE2_CHANNEL.FTS_LANE_DESKEW_EN origin:064-gtp-channel-conf 29_653 +GTP_CHANNEL_3.GTPE2_CHANNEL.GEARBOX_MODE[0] origin:064-gtp-channel-conf 28_224 +GTP_CHANNEL_3.GTPE2_CHANNEL.GEARBOX_MODE[1] origin:064-gtp-channel-conf 29_224 +GTP_CHANNEL_3.GTPE2_CHANNEL.GEARBOX_MODE[2] origin:064-gtp-channel-conf 28_225 +GTP_CHANNEL_3.GTPE2_CHANNEL.IN_USE origin:064-gtp-channel-conf 28_00 28_01 28_47 28_52 28_53 28_65 29_01 29_47 30_129 +GTP_CHANNEL_3.GTPE2_CHANNEL.INV_DMONITORCLK origin:064-gtp-channel-conf 30_13 +GTP_CHANNEL_3.GTPE2_CHANNEL.INV_DRPCLK origin:064-gtp-channel-conf 30_00 +GTP_CHANNEL_3.GTPE2_CHANNEL.INV_RXUSRCLK origin:064-gtp-channel-conf 31_01 +GTP_CHANNEL_3.GTPE2_CHANNEL.INV_SIGVALIDCLK origin:064-gtp-channel-conf 31_13 +GTP_CHANNEL_3.GTPE2_CHANNEL.INV_TXPHDLYTSTCLK origin:064-gtp-channel-conf 30_03 +GTP_CHANNEL_3.GTPE2_CHANNEL.INV_TXUSRCLK origin:064-gtp-channel-conf 31_04 +GTP_CHANNEL_3.GTPE2_CHANNEL.INV_CLKRSVD0 origin:064-gtp-channel-conf 30_23 +GTP_CHANNEL_3.GTPE2_CHANNEL.INV_CLKRSVD1 origin:064-gtp-channel-conf 31_23 +GTP_CHANNEL_3.GTPE2_CHANNEL.INV_RXUSRCLK2 origin:064-gtp-channel-conf 30_02 +GTP_CHANNEL_3.GTPE2_CHANNEL.INV_TXUSRCLK2 origin:064-gtp-channel-conf 30_05 +GTP_CHANNEL_3.GTPE2_CHANNEL.LOOPBACK_CFG[0] origin:064-gtp-channel-conf 30_20 +GTP_CHANNEL_3.GTPE2_CHANNEL.OUTREFCLK_SEL_INV[0] origin:064-gtp-channel-conf 28_149 +GTP_CHANNEL_3.GTPE2_CHANNEL.OUTREFCLK_SEL_INV[1] origin:064-gtp-channel-conf 29_149 +GTP_CHANNEL_3.GTPE2_CHANNEL.PCS_PCIE_EN origin:064-gtp-channel-conf 28_216 +GTP_CHANNEL_3.GTPE2_CHANNEL.PCS_RSVD_ATTR[0] origin:064-gtp-channel-conf 30_184 +GTP_CHANNEL_3.GTPE2_CHANNEL.PCS_RSVD_ATTR[1] origin:064-gtp-channel-conf 31_184 +GTP_CHANNEL_3.GTPE2_CHANNEL.PCS_RSVD_ATTR[2] origin:064-gtp-channel-conf 30_185 +GTP_CHANNEL_3.GTPE2_CHANNEL.PCS_RSVD_ATTR[3] origin:064-gtp-channel-conf 31_185 +GTP_CHANNEL_3.GTPE2_CHANNEL.PCS_RSVD_ATTR[4] origin:064-gtp-channel-conf 30_186 +GTP_CHANNEL_3.GTPE2_CHANNEL.PCS_RSVD_ATTR[5] origin:064-gtp-channel-conf 31_186 +GTP_CHANNEL_3.GTPE2_CHANNEL.PCS_RSVD_ATTR[6] origin:064-gtp-channel-conf 30_187 +GTP_CHANNEL_3.GTPE2_CHANNEL.PCS_RSVD_ATTR[7] origin:064-gtp-channel-conf 31_187 +GTP_CHANNEL_3.GTPE2_CHANNEL.PCS_RSVD_ATTR[8] origin:064-gtp-channel-conf 30_188 +GTP_CHANNEL_3.GTPE2_CHANNEL.PCS_RSVD_ATTR[9] origin:064-gtp-channel-conf 31_188 +GTP_CHANNEL_3.GTPE2_CHANNEL.PCS_RSVD_ATTR[10] origin:064-gtp-channel-conf 30_189 +GTP_CHANNEL_3.GTPE2_CHANNEL.PCS_RSVD_ATTR[11] origin:064-gtp-channel-conf 31_189 +GTP_CHANNEL_3.GTPE2_CHANNEL.PCS_RSVD_ATTR[12] origin:064-gtp-channel-conf 30_190 +GTP_CHANNEL_3.GTPE2_CHANNEL.PCS_RSVD_ATTR[13] origin:064-gtp-channel-conf 31_190 +GTP_CHANNEL_3.GTPE2_CHANNEL.PCS_RSVD_ATTR[14] origin:064-gtp-channel-conf 30_191 +GTP_CHANNEL_3.GTPE2_CHANNEL.PCS_RSVD_ATTR[15] origin:064-gtp-channel-conf 31_191 +GTP_CHANNEL_3.GTPE2_CHANNEL.PCS_RSVD_ATTR[16] origin:064-gtp-channel-conf 30_192 +GTP_CHANNEL_3.GTPE2_CHANNEL.PCS_RSVD_ATTR[17] origin:064-gtp-channel-conf 31_192 +GTP_CHANNEL_3.GTPE2_CHANNEL.PCS_RSVD_ATTR[18] origin:064-gtp-channel-conf 30_193 +GTP_CHANNEL_3.GTPE2_CHANNEL.PCS_RSVD_ATTR[19] origin:064-gtp-channel-conf 31_193 +GTP_CHANNEL_3.GTPE2_CHANNEL.PCS_RSVD_ATTR[20] origin:064-gtp-channel-conf 30_194 +GTP_CHANNEL_3.GTPE2_CHANNEL.PCS_RSVD_ATTR[21] origin:064-gtp-channel-conf 31_194 +GTP_CHANNEL_3.GTPE2_CHANNEL.PCS_RSVD_ATTR[22] origin:064-gtp-channel-conf 30_195 +GTP_CHANNEL_3.GTPE2_CHANNEL.PCS_RSVD_ATTR[23] origin:064-gtp-channel-conf 31_195 +GTP_CHANNEL_3.GTPE2_CHANNEL.PCS_RSVD_ATTR[24] origin:064-gtp-channel-conf 30_196 +GTP_CHANNEL_3.GTPE2_CHANNEL.PCS_RSVD_ATTR[25] origin:064-gtp-channel-conf 31_196 +GTP_CHANNEL_3.GTPE2_CHANNEL.PCS_RSVD_ATTR[26] origin:064-gtp-channel-conf 30_197 +GTP_CHANNEL_3.GTPE2_CHANNEL.PCS_RSVD_ATTR[27] origin:064-gtp-channel-conf 31_197 +GTP_CHANNEL_3.GTPE2_CHANNEL.PCS_RSVD_ATTR[28] origin:064-gtp-channel-conf 30_198 +GTP_CHANNEL_3.GTPE2_CHANNEL.PCS_RSVD_ATTR[29] origin:064-gtp-channel-conf 31_198 +GTP_CHANNEL_3.GTPE2_CHANNEL.PCS_RSVD_ATTR[30] origin:064-gtp-channel-conf 30_199 +GTP_CHANNEL_3.GTPE2_CHANNEL.PCS_RSVD_ATTR[31] origin:064-gtp-channel-conf 31_199 +GTP_CHANNEL_3.GTPE2_CHANNEL.PCS_RSVD_ATTR[32] origin:064-gtp-channel-conf 30_200 +GTP_CHANNEL_3.GTPE2_CHANNEL.PCS_RSVD_ATTR[33] origin:064-gtp-channel-conf 31_200 +GTP_CHANNEL_3.GTPE2_CHANNEL.PCS_RSVD_ATTR[34] origin:064-gtp-channel-conf 30_201 +GTP_CHANNEL_3.GTPE2_CHANNEL.PCS_RSVD_ATTR[35] origin:064-gtp-channel-conf 31_201 +GTP_CHANNEL_3.GTPE2_CHANNEL.PCS_RSVD_ATTR[36] origin:064-gtp-channel-conf 30_202 +GTP_CHANNEL_3.GTPE2_CHANNEL.PCS_RSVD_ATTR[37] origin:064-gtp-channel-conf 31_202 +GTP_CHANNEL_3.GTPE2_CHANNEL.PCS_RSVD_ATTR[38] origin:064-gtp-channel-conf 30_203 +GTP_CHANNEL_3.GTPE2_CHANNEL.PCS_RSVD_ATTR[39] origin:064-gtp-channel-conf 31_203 +GTP_CHANNEL_3.GTPE2_CHANNEL.PCS_RSVD_ATTR[40] origin:064-gtp-channel-conf 30_204 +GTP_CHANNEL_3.GTPE2_CHANNEL.PCS_RSVD_ATTR[41] origin:064-gtp-channel-conf 31_204 +GTP_CHANNEL_3.GTPE2_CHANNEL.PCS_RSVD_ATTR[42] origin:064-gtp-channel-conf 30_205 +GTP_CHANNEL_3.GTPE2_CHANNEL.PCS_RSVD_ATTR[43] origin:064-gtp-channel-conf 31_205 +GTP_CHANNEL_3.GTPE2_CHANNEL.PCS_RSVD_ATTR[44] origin:064-gtp-channel-conf 30_206 +GTP_CHANNEL_3.GTPE2_CHANNEL.PCS_RSVD_ATTR[45] origin:064-gtp-channel-conf 31_206 +GTP_CHANNEL_3.GTPE2_CHANNEL.PCS_RSVD_ATTR[46] origin:064-gtp-channel-conf 30_207 +GTP_CHANNEL_3.GTPE2_CHANNEL.PCS_RSVD_ATTR[47] origin:064-gtp-channel-conf 31_207 +GTP_CHANNEL_3.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[0] origin:064-gtp-channel-conf 29_216 +GTP_CHANNEL_3.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[1] origin:064-gtp-channel-conf 28_217 +GTP_CHANNEL_3.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[2] origin:064-gtp-channel-conf 29_217 +GTP_CHANNEL_3.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[3] origin:064-gtp-channel-conf 28_218 +GTP_CHANNEL_3.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[4] origin:064-gtp-channel-conf 29_218 +GTP_CHANNEL_3.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[5] origin:064-gtp-channel-conf 28_219 +GTP_CHANNEL_3.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[6] origin:064-gtp-channel-conf 29_219 +GTP_CHANNEL_3.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[7] origin:064-gtp-channel-conf 28_220 +GTP_CHANNEL_3.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[8] origin:064-gtp-channel-conf 29_220 +GTP_CHANNEL_3.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[9] origin:064-gtp-channel-conf 28_221 +GTP_CHANNEL_3.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[10] origin:064-gtp-channel-conf 29_221 +GTP_CHANNEL_3.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[11] origin:064-gtp-channel-conf 28_222 +GTP_CHANNEL_3.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[0] origin:064-gtp-channel-conf 28_208 +GTP_CHANNEL_3.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[1] origin:064-gtp-channel-conf 29_208 +GTP_CHANNEL_3.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[2] origin:064-gtp-channel-conf 28_209 +GTP_CHANNEL_3.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[3] origin:064-gtp-channel-conf 29_209 +GTP_CHANNEL_3.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[4] origin:064-gtp-channel-conf 28_210 +GTP_CHANNEL_3.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[5] origin:064-gtp-channel-conf 29_210 +GTP_CHANNEL_3.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[6] origin:064-gtp-channel-conf 28_211 +GTP_CHANNEL_3.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[7] origin:064-gtp-channel-conf 29_211 +GTP_CHANNEL_3.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[0] origin:064-gtp-channel-conf 28_212 +GTP_CHANNEL_3.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[1] origin:064-gtp-channel-conf 29_212 +GTP_CHANNEL_3.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[2] origin:064-gtp-channel-conf 28_213 +GTP_CHANNEL_3.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[3] origin:064-gtp-channel-conf 29_213 +GTP_CHANNEL_3.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[4] origin:064-gtp-channel-conf 28_214 +GTP_CHANNEL_3.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[5] origin:064-gtp-channel-conf 29_214 +GTP_CHANNEL_3.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[6] origin:064-gtp-channel-conf 28_215 +GTP_CHANNEL_3.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[7] origin:064-gtp-channel-conf 29_215 +GTP_CHANNEL_3.GTPE2_CHANNEL.PMA_LOOPBACK_CFG[0] origin:064-gtp-channel-conf 29_207 +GTP_CHANNEL_3.GTPE2_CHANNEL.PMA_RSV[0] origin:064-gtp-channel-conf 30_520 +GTP_CHANNEL_3.GTPE2_CHANNEL.PMA_RSV[1] origin:064-gtp-channel-conf 31_520 +GTP_CHANNEL_3.GTPE2_CHANNEL.PMA_RSV[2] origin:064-gtp-channel-conf 30_521 +GTP_CHANNEL_3.GTPE2_CHANNEL.PMA_RSV[3] origin:064-gtp-channel-conf 31_521 +GTP_CHANNEL_3.GTPE2_CHANNEL.PMA_RSV[4] origin:064-gtp-channel-conf 30_522 +GTP_CHANNEL_3.GTPE2_CHANNEL.PMA_RSV[5] origin:064-gtp-channel-conf 31_522 +GTP_CHANNEL_3.GTPE2_CHANNEL.PMA_RSV[6] origin:064-gtp-channel-conf 30_523 +GTP_CHANNEL_3.GTPE2_CHANNEL.PMA_RSV[7] origin:064-gtp-channel-conf 31_523 +GTP_CHANNEL_3.GTPE2_CHANNEL.PMA_RSV[8] origin:064-gtp-channel-conf 30_524 +GTP_CHANNEL_3.GTPE2_CHANNEL.PMA_RSV[9] origin:064-gtp-channel-conf 31_524 +GTP_CHANNEL_3.GTPE2_CHANNEL.PMA_RSV[10] origin:064-gtp-channel-conf 30_525 +GTP_CHANNEL_3.GTPE2_CHANNEL.PMA_RSV[11] origin:064-gtp-channel-conf 31_525 +GTP_CHANNEL_3.GTPE2_CHANNEL.PMA_RSV[12] origin:064-gtp-channel-conf 30_526 +GTP_CHANNEL_3.GTPE2_CHANNEL.PMA_RSV[13] origin:064-gtp-channel-conf 31_526 +GTP_CHANNEL_3.GTPE2_CHANNEL.PMA_RSV[14] origin:064-gtp-channel-conf 30_527 +GTP_CHANNEL_3.GTPE2_CHANNEL.PMA_RSV[15] origin:064-gtp-channel-conf 31_527 +GTP_CHANNEL_3.GTPE2_CHANNEL.PMA_RSV[16] origin:064-gtp-channel-conf 30_528 +GTP_CHANNEL_3.GTPE2_CHANNEL.PMA_RSV[17] origin:064-gtp-channel-conf 31_528 +GTP_CHANNEL_3.GTPE2_CHANNEL.PMA_RSV[18] origin:064-gtp-channel-conf 30_529 +GTP_CHANNEL_3.GTPE2_CHANNEL.PMA_RSV[19] origin:064-gtp-channel-conf 31_529 +GTP_CHANNEL_3.GTPE2_CHANNEL.PMA_RSV[20] origin:064-gtp-channel-conf 30_530 +GTP_CHANNEL_3.GTPE2_CHANNEL.PMA_RSV[21] origin:064-gtp-channel-conf 31_530 +GTP_CHANNEL_3.GTPE2_CHANNEL.PMA_RSV[22] origin:064-gtp-channel-conf 30_531 +GTP_CHANNEL_3.GTPE2_CHANNEL.PMA_RSV[23] origin:064-gtp-channel-conf 31_531 +GTP_CHANNEL_3.GTPE2_CHANNEL.PMA_RSV[24] origin:064-gtp-channel-conf 30_532 +GTP_CHANNEL_3.GTPE2_CHANNEL.PMA_RSV[25] origin:064-gtp-channel-conf 31_532 +GTP_CHANNEL_3.GTPE2_CHANNEL.PMA_RSV[26] origin:064-gtp-channel-conf 30_533 +GTP_CHANNEL_3.GTPE2_CHANNEL.PMA_RSV[27] origin:064-gtp-channel-conf 31_533 +GTP_CHANNEL_3.GTPE2_CHANNEL.PMA_RSV[28] origin:064-gtp-channel-conf 30_534 +GTP_CHANNEL_3.GTPE2_CHANNEL.PMA_RSV[29] origin:064-gtp-channel-conf 31_534 +GTP_CHANNEL_3.GTPE2_CHANNEL.PMA_RSV[30] origin:064-gtp-channel-conf 30_535 +GTP_CHANNEL_3.GTPE2_CHANNEL.PMA_RSV[31] origin:064-gtp-channel-conf 31_535 +GTP_CHANNEL_3.GTPE2_CHANNEL.PMA_RSV2[0] origin:064-gtp-channel-conf 30_336 +GTP_CHANNEL_3.GTPE2_CHANNEL.PMA_RSV2[1] origin:064-gtp-channel-conf 31_336 +GTP_CHANNEL_3.GTPE2_CHANNEL.PMA_RSV2[2] origin:064-gtp-channel-conf 30_337 +GTP_CHANNEL_3.GTPE2_CHANNEL.PMA_RSV2[3] origin:064-gtp-channel-conf 31_337 +GTP_CHANNEL_3.GTPE2_CHANNEL.PMA_RSV2[4] origin:064-gtp-channel-conf 30_338 +GTP_CHANNEL_3.GTPE2_CHANNEL.PMA_RSV2[5] origin:064-gtp-channel-conf 31_338 +GTP_CHANNEL_3.GTPE2_CHANNEL.PMA_RSV2[6] origin:064-gtp-channel-conf 30_339 +GTP_CHANNEL_3.GTPE2_CHANNEL.PMA_RSV2[7] origin:064-gtp-channel-conf 31_339 +GTP_CHANNEL_3.GTPE2_CHANNEL.PMA_RSV2[8] origin:064-gtp-channel-conf 30_340 +GTP_CHANNEL_3.GTPE2_CHANNEL.PMA_RSV2[9] origin:064-gtp-channel-conf 31_340 +GTP_CHANNEL_3.GTPE2_CHANNEL.PMA_RSV2[10] origin:064-gtp-channel-conf 30_341 +GTP_CHANNEL_3.GTPE2_CHANNEL.PMA_RSV2[11] origin:064-gtp-channel-conf 31_341 +GTP_CHANNEL_3.GTPE2_CHANNEL.PMA_RSV2[12] origin:064-gtp-channel-conf 30_342 +GTP_CHANNEL_3.GTPE2_CHANNEL.PMA_RSV2[13] origin:064-gtp-channel-conf 31_342 +GTP_CHANNEL_3.GTPE2_CHANNEL.PMA_RSV2[14] origin:064-gtp-channel-conf 30_343 +GTP_CHANNEL_3.GTPE2_CHANNEL.PMA_RSV2[15] origin:064-gtp-channel-conf 31_343 +GTP_CHANNEL_3.GTPE2_CHANNEL.PMA_RSV2[16] origin:064-gtp-channel-conf 30_344 +GTP_CHANNEL_3.GTPE2_CHANNEL.PMA_RSV2[17] origin:064-gtp-channel-conf 31_344 +GTP_CHANNEL_3.GTPE2_CHANNEL.PMA_RSV2[18] origin:064-gtp-channel-conf 30_345 +GTP_CHANNEL_3.GTPE2_CHANNEL.PMA_RSV2[19] origin:064-gtp-channel-conf 31_345 +GTP_CHANNEL_3.GTPE2_CHANNEL.PMA_RSV2[20] origin:064-gtp-channel-conf 30_346 +GTP_CHANNEL_3.GTPE2_CHANNEL.PMA_RSV2[21] origin:064-gtp-channel-conf 31_346 +GTP_CHANNEL_3.GTPE2_CHANNEL.PMA_RSV2[22] origin:064-gtp-channel-conf 30_347 +GTP_CHANNEL_3.GTPE2_CHANNEL.PMA_RSV2[23] origin:064-gtp-channel-conf 31_347 +GTP_CHANNEL_3.GTPE2_CHANNEL.PMA_RSV2[24] origin:064-gtp-channel-conf 30_348 +GTP_CHANNEL_3.GTPE2_CHANNEL.PMA_RSV2[25] origin:064-gtp-channel-conf 31_348 +GTP_CHANNEL_3.GTPE2_CHANNEL.PMA_RSV2[26] origin:064-gtp-channel-conf 30_349 +GTP_CHANNEL_3.GTPE2_CHANNEL.PMA_RSV2[27] origin:064-gtp-channel-conf 31_349 +GTP_CHANNEL_3.GTPE2_CHANNEL.PMA_RSV2[28] origin:064-gtp-channel-conf 30_350 +GTP_CHANNEL_3.GTPE2_CHANNEL.PMA_RSV2[29] origin:064-gtp-channel-conf 31_350 +GTP_CHANNEL_3.GTPE2_CHANNEL.PMA_RSV2[30] origin:064-gtp-channel-conf 30_351 +GTP_CHANNEL_3.GTPE2_CHANNEL.PMA_RSV2[31] origin:064-gtp-channel-conf 31_351 +GTP_CHANNEL_3.GTPE2_CHANNEL.PMA_RSV3[0] origin:064-gtp-channel-conf 30_288 +GTP_CHANNEL_3.GTPE2_CHANNEL.PMA_RSV3[1] origin:064-gtp-channel-conf 31_288 +GTP_CHANNEL_3.GTPE2_CHANNEL.PMA_RSV4[0] origin:064-gtp-channel-conf 30_156 +GTP_CHANNEL_3.GTPE2_CHANNEL.PMA_RSV4[1] origin:064-gtp-channel-conf 31_156 +GTP_CHANNEL_3.GTPE2_CHANNEL.PMA_RSV4[2] origin:064-gtp-channel-conf 30_157 +GTP_CHANNEL_3.GTPE2_CHANNEL.PMA_RSV4[3] origin:064-gtp-channel-conf 31_157 +GTP_CHANNEL_3.GTPE2_CHANNEL.PMA_RSV5[0] origin:064-gtp-channel-conf 31_159 +GTP_CHANNEL_3.GTPE2_CHANNEL.PMA_RSV6[0] origin:064-gtp-channel-conf 30_303 +GTP_CHANNEL_3.GTPE2_CHANNEL.PMA_RSV7[0] origin:064-gtp-channel-conf 31_303 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_BIAS_CFG[0] origin:064-gtp-channel-conf 30_112 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_BIAS_CFG[1] origin:064-gtp-channel-conf 31_112 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_BIAS_CFG[2] origin:064-gtp-channel-conf 30_113 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_BIAS_CFG[3] origin:064-gtp-channel-conf 31_113 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_BIAS_CFG[4] origin:064-gtp-channel-conf 30_114 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_BIAS_CFG[5] origin:064-gtp-channel-conf 31_114 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_BIAS_CFG[6] origin:064-gtp-channel-conf 30_115 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_BIAS_CFG[7] origin:064-gtp-channel-conf 31_115 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_BIAS_CFG[8] origin:064-gtp-channel-conf 30_116 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_BIAS_CFG[9] origin:064-gtp-channel-conf 31_116 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_BIAS_CFG[10] origin:064-gtp-channel-conf 30_117 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_BIAS_CFG[11] origin:064-gtp-channel-conf 31_117 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_BIAS_CFG[12] origin:064-gtp-channel-conf 30_118 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_BIAS_CFG[13] origin:064-gtp-channel-conf 31_118 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_BIAS_CFG[14] origin:064-gtp-channel-conf 30_119 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_BIAS_CFG[15] origin:064-gtp-channel-conf 31_119 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_BUFFER_CFG[0] origin:064-gtp-channel-conf 30_536 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_BUFFER_CFG[1] origin:064-gtp-channel-conf 31_536 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_BUFFER_CFG[2] origin:064-gtp-channel-conf 30_537 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_BUFFER_CFG[3] origin:064-gtp-channel-conf 31_537 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_BUFFER_CFG[4] origin:064-gtp-channel-conf 30_538 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_BUFFER_CFG[5] origin:064-gtp-channel-conf 31_538 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_CLKMUX_EN[0] origin:064-gtp-channel-conf 30_128 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_CM_SEL[0] origin:064-gtp-channel-conf 28_138 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_CM_SEL[1] origin:064-gtp-channel-conf 29_138 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_CM_TRIM[0] origin:064-gtp-channel-conf 30_304 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_CM_TRIM[1] origin:064-gtp-channel-conf 31_304 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_CM_TRIM[2] origin:064-gtp-channel-conf 30_305 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_CM_TRIM[3] origin:064-gtp-channel-conf 31_305 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_DATA_WIDTH[0] origin:064-gtp-channel-conf 29_141 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_DATA_WIDTH[1] origin:064-gtp-channel-conf 28_142 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_DATA_WIDTH[2] origin:064-gtp-channel-conf 29_142 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_DDI_SEL[0] origin:064-gtp-channel-conf 28_696 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_DDI_SEL[1] origin:064-gtp-channel-conf 29_696 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_DDI_SEL[2] origin:064-gtp-channel-conf 28_697 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_DDI_SEL[3] origin:064-gtp-channel-conf 29_697 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_DDI_SEL[4] origin:064-gtp-channel-conf 28_698 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_DDI_SEL[5] origin:064-gtp-channel-conf 29_698 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_DEBUG_CFG[0] origin:064-gtp-channel-conf 30_616 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_DEBUG_CFG[1] origin:064-gtp-channel-conf 31_616 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_DEBUG_CFG[2] origin:064-gtp-channel-conf 30_617 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_DEBUG_CFG[3] origin:064-gtp-channel-conf 31_617 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_DEBUG_CFG[4] origin:064-gtp-channel-conf 30_618 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_DEBUG_CFG[5] origin:064-gtp-channel-conf 31_618 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_DEBUG_CFG[6] origin:064-gtp-channel-conf 30_619 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_DEBUG_CFG[7] origin:064-gtp-channel-conf 31_619 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_DEBUG_CFG[8] origin:064-gtp-channel-conf 30_620 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_DEBUG_CFG[9] origin:064-gtp-channel-conf 31_620 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_DEBUG_CFG[10] origin:064-gtp-channel-conf 30_621 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_DEBUG_CFG[11] origin:064-gtp-channel-conf 31_621 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_DEBUG_CFG[12] origin:064-gtp-channel-conf 30_622 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_DEBUG_CFG[13] origin:064-gtp-channel-conf 31_622 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_DEFER_RESET_BUF_EN origin:064-gtp-channel-conf 30_552 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_DISPERR_SEQ_MATCH origin:064-gtp-channel-conf 29_495 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_OS_CFG[0] origin:064-gtp-channel-conf 28_288 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_OS_CFG[1] origin:064-gtp-channel-conf 29_288 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_OS_CFG[2] origin:064-gtp-channel-conf 28_289 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_OS_CFG[3] origin:064-gtp-channel-conf 29_289 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_OS_CFG[4] origin:064-gtp-channel-conf 28_290 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_OS_CFG[5] origin:064-gtp-channel-conf 29_290 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_OS_CFG[6] origin:064-gtp-channel-conf 28_291 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_OS_CFG[7] origin:064-gtp-channel-conf 29_291 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_OS_CFG[8] origin:064-gtp-channel-conf 28_292 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_OS_CFG[9] origin:064-gtp-channel-conf 29_292 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_OS_CFG[10] origin:064-gtp-channel-conf 28_293 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_OS_CFG[11] origin:064-gtp-channel-conf 29_293 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_OS_CFG[12] origin:064-gtp-channel-conf 28_294 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_SIG_VALID_DLY[0] origin:064-gtp-channel-conf 28_524 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_SIG_VALID_DLY[1] origin:064-gtp-channel-conf 29_524 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_SIG_VALID_DLY[2] origin:064-gtp-channel-conf 28_525 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_SIG_VALID_DLY[3] origin:064-gtp-channel-conf 29_525 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_SIG_VALID_DLY[4] origin:064-gtp-channel-conf 28_526 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_XCLK_SEL.RXUSR origin:064-gtp-channel-conf 28_143 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_CLK25_DIV[0] origin:064-gtp-channel-conf 28_139 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_CLK25_DIV[1] origin:064-gtp-channel-conf 29_139 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_CLK25_DIV[2] origin:064-gtp-channel-conf 28_140 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_CLK25_DIV[3] origin:064-gtp-channel-conf 29_140 +GTP_CHANNEL_3.GTPE2_CHANNEL.RX_CLK25_DIV[4] origin:064-gtp-channel-conf 28_141 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXBUF_ADDR_MODE.FAST origin:064-gtp-channel-conf 31_555 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXBUF_EIDLE_HI_CNT[0] origin:064-gtp-channel-conf 30_558 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXBUF_EIDLE_HI_CNT[1] origin:064-gtp-channel-conf 31_558 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXBUF_EIDLE_HI_CNT[2] origin:064-gtp-channel-conf 30_559 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXBUF_EIDLE_HI_CNT[3] origin:064-gtp-channel-conf 31_559 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXBUF_EIDLE_LO_CNT[0] origin:064-gtp-channel-conf 30_556 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXBUF_EIDLE_LO_CNT[1] origin:064-gtp-channel-conf 31_556 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXBUF_EIDLE_LO_CNT[2] origin:064-gtp-channel-conf 30_557 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXBUF_EIDLE_LO_CNT[3] origin:064-gtp-channel-conf 31_557 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXBUF_EN origin:064-gtp-channel-conf 30_11 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXBUF_RESET_ON_CB_CHANGE origin:064-gtp-channel-conf 30_560 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXBUF_RESET_ON_COMMAALIGN origin:064-gtp-channel-conf 30_561 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXBUF_RESET_ON_EIDLE origin:064-gtp-channel-conf 30_547 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXBUF_RESET_ON_RATE_CHANGE origin:064-gtp-channel-conf 31_560 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXBUF_THRESH_OVFLW[0] origin:064-gtp-channel-conf 31_552 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXBUF_THRESH_OVFLW[1] origin:064-gtp-channel-conf 30_553 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXBUF_THRESH_OVFLW[2] origin:064-gtp-channel-conf 31_553 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXBUF_THRESH_OVFLW[3] origin:064-gtp-channel-conf 30_554 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXBUF_THRESH_OVFLW[4] origin:064-gtp-channel-conf 31_554 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXBUF_THRESH_OVFLW[5] origin:064-gtp-channel-conf 30_555 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXBUF_THRESH_OVRD origin:064-gtp-channel-conf 30_548 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXBUF_THRESH_UNDFLW[0] origin:064-gtp-channel-conf 30_544 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXBUF_THRESH_UNDFLW[1] origin:064-gtp-channel-conf 31_544 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXBUF_THRESH_UNDFLW[2] origin:064-gtp-channel-conf 30_545 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXBUF_THRESH_UNDFLW[3] origin:064-gtp-channel-conf 31_545 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXBUF_THRESH_UNDFLW[4] origin:064-gtp-channel-conf 30_546 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXBUF_THRESH_UNDFLW[5] origin:064-gtp-channel-conf 31_546 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXBUFRESET_TIME[0] origin:064-gtp-channel-conf 29_101 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXBUFRESET_TIME[1] origin:064-gtp-channel-conf 28_102 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXBUFRESET_TIME[2] origin:064-gtp-channel-conf 29_102 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXBUFRESET_TIME[3] origin:064-gtp-channel-conf 28_103 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXBUFRESET_TIME[4] origin:064-gtp-channel-conf 29_103 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[0] origin:064-gtp-channel-conf 30_640 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[1] origin:064-gtp-channel-conf 31_640 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[2] origin:064-gtp-channel-conf 30_641 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[3] origin:064-gtp-channel-conf 31_641 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[4] origin:064-gtp-channel-conf 30_642 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[5] origin:064-gtp-channel-conf 31_642 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[6] origin:064-gtp-channel-conf 30_643 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[7] origin:064-gtp-channel-conf 31_643 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[8] origin:064-gtp-channel-conf 30_644 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[9] origin:064-gtp-channel-conf 31_644 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[10] origin:064-gtp-channel-conf 30_645 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[11] origin:064-gtp-channel-conf 31_645 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[12] origin:064-gtp-channel-conf 30_646 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[13] origin:064-gtp-channel-conf 31_646 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[14] origin:064-gtp-channel-conf 30_647 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[15] origin:064-gtp-channel-conf 31_647 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[16] origin:064-gtp-channel-conf 30_648 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[17] origin:064-gtp-channel-conf 31_648 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[18] origin:064-gtp-channel-conf 30_649 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[19] origin:064-gtp-channel-conf 31_649 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[20] origin:064-gtp-channel-conf 30_650 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[21] origin:064-gtp-channel-conf 31_650 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[22] origin:064-gtp-channel-conf 30_651 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[23] origin:064-gtp-channel-conf 31_651 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[24] origin:064-gtp-channel-conf 30_652 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[25] origin:064-gtp-channel-conf 31_652 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[26] origin:064-gtp-channel-conf 30_653 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[27] origin:064-gtp-channel-conf 31_653 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[28] origin:064-gtp-channel-conf 30_654 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[29] origin:064-gtp-channel-conf 31_654 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[30] origin:064-gtp-channel-conf 30_655 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[31] origin:064-gtp-channel-conf 31_655 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[32] origin:064-gtp-channel-conf 30_656 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[33] origin:064-gtp-channel-conf 31_656 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[34] origin:064-gtp-channel-conf 30_657 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[35] origin:064-gtp-channel-conf 31_657 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[36] origin:064-gtp-channel-conf 30_658 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[37] origin:064-gtp-channel-conf 31_658 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[38] origin:064-gtp-channel-conf 30_659 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[39] origin:064-gtp-channel-conf 31_659 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[40] origin:064-gtp-channel-conf 30_660 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[41] origin:064-gtp-channel-conf 31_660 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[42] origin:064-gtp-channel-conf 30_661 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[43] origin:064-gtp-channel-conf 31_661 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[44] origin:064-gtp-channel-conf 30_662 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[45] origin:064-gtp-channel-conf 31_662 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[46] origin:064-gtp-channel-conf 30_663 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[47] origin:064-gtp-channel-conf 31_663 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[48] origin:064-gtp-channel-conf 30_664 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[49] origin:064-gtp-channel-conf 31_664 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[50] origin:064-gtp-channel-conf 30_665 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[51] origin:064-gtp-channel-conf 31_665 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[52] origin:064-gtp-channel-conf 30_666 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[53] origin:064-gtp-channel-conf 31_666 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[54] origin:064-gtp-channel-conf 30_667 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[55] origin:064-gtp-channel-conf 31_667 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[56] origin:064-gtp-channel-conf 30_668 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[57] origin:064-gtp-channel-conf 31_668 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[58] origin:064-gtp-channel-conf 30_669 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[59] origin:064-gtp-channel-conf 31_669 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[60] origin:064-gtp-channel-conf 30_670 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[61] origin:064-gtp-channel-conf 31_670 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[62] origin:064-gtp-channel-conf 30_671 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[63] origin:064-gtp-channel-conf 31_671 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[64] origin:064-gtp-channel-conf 30_672 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[65] origin:064-gtp-channel-conf 31_672 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[66] origin:064-gtp-channel-conf 30_673 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[67] origin:064-gtp-channel-conf 31_673 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[68] origin:064-gtp-channel-conf 30_674 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[69] origin:064-gtp-channel-conf 31_674 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[70] origin:064-gtp-channel-conf 30_675 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[71] origin:064-gtp-channel-conf 31_675 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[72] origin:064-gtp-channel-conf 30_676 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[73] origin:064-gtp-channel-conf 31_676 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[74] origin:064-gtp-channel-conf 30_677 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[75] origin:064-gtp-channel-conf 31_677 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[76] origin:064-gtp-channel-conf 30_678 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[77] origin:064-gtp-channel-conf 31_678 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[78] origin:064-gtp-channel-conf 30_679 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[79] origin:064-gtp-channel-conf 31_679 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[80] origin:064-gtp-channel-conf 30_680 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[81] origin:064-gtp-channel-conf 31_680 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_CFG[82] origin:064-gtp-channel-conf 30_681 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_FR_RESET_ON_EIDLE[0] origin:064-gtp-channel-conf 30_638 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_HOLD_DURING_EIDLE[0] origin:064-gtp-channel-conf 31_637 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_LOCK_CFG[0] origin:064-gtp-channel-conf 30_632 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_LOCK_CFG[1] origin:064-gtp-channel-conf 31_632 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_LOCK_CFG[2] origin:064-gtp-channel-conf 30_633 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_LOCK_CFG[3] origin:064-gtp-channel-conf 31_633 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_LOCK_CFG[4] origin:064-gtp-channel-conf 30_634 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_LOCK_CFG[5] origin:064-gtp-channel-conf 31_634 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDR_PH_RESET_ON_EIDLE[0] origin:064-gtp-channel-conf 31_638 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDRFREQRESET_TIME[0] origin:064-gtp-channel-conf 29_106 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDRFREQRESET_TIME[1] origin:064-gtp-channel-conf 28_107 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDRFREQRESET_TIME[2] origin:064-gtp-channel-conf 29_107 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDRFREQRESET_TIME[3] origin:064-gtp-channel-conf 28_108 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDRFREQRESET_TIME[4] origin:064-gtp-channel-conf 29_108 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDRPHRESET_TIME[0] origin:064-gtp-channel-conf 28_109 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDRPHRESET_TIME[1] origin:064-gtp-channel-conf 29_109 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDRPHRESET_TIME[2] origin:064-gtp-channel-conf 28_110 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDRPHRESET_TIME[3] origin:064-gtp-channel-conf 29_110 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXCDRPHRESET_TIME[4] origin:064-gtp-channel-conf 28_111 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXDLY_CFG[0] origin:064-gtp-channel-conf 28_680 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXDLY_CFG[1] origin:064-gtp-channel-conf 29_680 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXDLY_CFG[2] origin:064-gtp-channel-conf 28_681 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXDLY_CFG[3] origin:064-gtp-channel-conf 29_681 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXDLY_CFG[4] origin:064-gtp-channel-conf 28_682 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXDLY_CFG[5] origin:064-gtp-channel-conf 29_682 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXDLY_CFG[6] origin:064-gtp-channel-conf 28_683 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXDLY_CFG[7] origin:064-gtp-channel-conf 29_683 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXDLY_CFG[8] origin:064-gtp-channel-conf 28_684 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXDLY_CFG[9] origin:064-gtp-channel-conf 29_684 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXDLY_CFG[10] origin:064-gtp-channel-conf 28_685 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXDLY_CFG[11] origin:064-gtp-channel-conf 29_685 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXDLY_CFG[12] origin:064-gtp-channel-conf 28_686 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXDLY_CFG[13] origin:064-gtp-channel-conf 29_686 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXDLY_CFG[14] origin:064-gtp-channel-conf 28_687 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXDLY_CFG[15] origin:064-gtp-channel-conf 29_687 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXDLY_LCFG[0] origin:064-gtp-channel-conf 30_576 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXDLY_LCFG[1] origin:064-gtp-channel-conf 31_576 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXDLY_LCFG[2] origin:064-gtp-channel-conf 30_577 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXDLY_LCFG[3] origin:064-gtp-channel-conf 31_577 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXDLY_LCFG[4] origin:064-gtp-channel-conf 30_578 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXDLY_LCFG[5] origin:064-gtp-channel-conf 31_578 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXDLY_LCFG[6] origin:064-gtp-channel-conf 30_579 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXDLY_LCFG[7] origin:064-gtp-channel-conf 31_579 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXDLY_LCFG[8] origin:064-gtp-channel-conf 30_580 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXDLY_TAP_CFG[0] origin:064-gtp-channel-conf 28_672 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXDLY_TAP_CFG[1] origin:064-gtp-channel-conf 29_672 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXDLY_TAP_CFG[2] origin:064-gtp-channel-conf 28_673 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXDLY_TAP_CFG[3] origin:064-gtp-channel-conf 29_673 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXDLY_TAP_CFG[4] origin:064-gtp-channel-conf 28_674 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXDLY_TAP_CFG[5] origin:064-gtp-channel-conf 29_674 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXDLY_TAP_CFG[6] origin:064-gtp-channel-conf 28_675 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXDLY_TAP_CFG[7] origin:064-gtp-channel-conf 29_675 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXDLY_TAP_CFG[8] origin:064-gtp-channel-conf 28_676 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXDLY_TAP_CFG[9] origin:064-gtp-channel-conf 29_676 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXDLY_TAP_CFG[10] origin:064-gtp-channel-conf 28_677 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXDLY_TAP_CFG[11] origin:064-gtp-channel-conf 29_677 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXDLY_TAP_CFG[12] origin:064-gtp-channel-conf 28_678 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXDLY_TAP_CFG[13] origin:064-gtp-channel-conf 29_678 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXDLY_TAP_CFG[14] origin:064-gtp-channel-conf 28_679 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXDLY_TAP_CFG[15] origin:064-gtp-channel-conf 29_679 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXGEARBOX_EN origin:064-gtp-channel-conf 29_607 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXISCANRESET_TIME[0] origin:064-gtp-channel-conf 29_123 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXISCANRESET_TIME[1] origin:064-gtp-channel-conf 28_124 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXISCANRESET_TIME[2] origin:064-gtp-channel-conf 29_124 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXISCANRESET_TIME[3] origin:064-gtp-channel-conf 28_125 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXISCANRESET_TIME[4] origin:064-gtp-channel-conf 29_125 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPM_BIAS_STARTUP_DISABLE[0] origin:064-gtp-channel-conf 31_391 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPM_CFG[0] origin:064-gtp-channel-conf 30_328 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPM_CFG[1] origin:064-gtp-channel-conf 31_328 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPM_CFG[2] origin:064-gtp-channel-conf 30_329 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPM_CFG[3] origin:064-gtp-channel-conf 31_329 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPM_CM_CFG[0] origin:064-gtp-channel-conf 30_430 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPM_GC_CFG[0] origin:064-gtp-channel-conf 30_432 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPM_GC_CFG[1] origin:064-gtp-channel-conf 31_432 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPM_GC_CFG[2] origin:064-gtp-channel-conf 30_433 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPM_GC_CFG[3] origin:064-gtp-channel-conf 31_433 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPM_GC_CFG[4] origin:064-gtp-channel-conf 30_434 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPM_GC_CFG[5] origin:064-gtp-channel-conf 31_434 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPM_GC_CFG[6] origin:064-gtp-channel-conf 30_435 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPM_GC_CFG[7] origin:064-gtp-channel-conf 31_435 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPM_GC_CFG[8] origin:064-gtp-channel-conf 30_436 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPM_GC_CFG2[0] origin:064-gtp-channel-conf 31_442 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPM_GC_CFG2[1] origin:064-gtp-channel-conf 30_443 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPM_GC_CFG2[2] origin:064-gtp-channel-conf 31_443 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPM_HF_CFG[0] origin:064-gtp-channel-conf 28_336 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPM_HF_CFG[1] origin:064-gtp-channel-conf 29_336 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPM_HF_CFG[2] origin:064-gtp-channel-conf 28_337 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPM_HF_CFG[3] origin:064-gtp-channel-conf 29_337 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPM_HF_CFG[4] origin:064-gtp-channel-conf 28_338 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPM_HF_CFG[5] origin:064-gtp-channel-conf 29_338 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPM_HF_CFG[6] origin:064-gtp-channel-conf 28_339 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPM_HF_CFG[7] origin:064-gtp-channel-conf 29_339 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPM_HF_CFG[8] origin:064-gtp-channel-conf 28_340 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPM_HF_CFG[9] origin:064-gtp-channel-conf 29_340 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPM_HF_CFG[10] origin:064-gtp-channel-conf 28_341 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPM_HF_CFG[11] origin:064-gtp-channel-conf 29_341 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPM_HF_CFG[12] origin:064-gtp-channel-conf 28_342 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPM_HF_CFG[13] origin:064-gtp-channel-conf 29_342 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPM_HF_CFG2[0] origin:064-gtp-channel-conf 30_424 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPM_HF_CFG2[1] origin:064-gtp-channel-conf 31_424 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPM_HF_CFG2[2] origin:064-gtp-channel-conf 30_425 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPM_HF_CFG2[3] origin:064-gtp-channel-conf 31_425 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPM_HF_CFG2[4] origin:064-gtp-channel-conf 30_426 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPM_HF_CFG3[0] origin:064-gtp-channel-conf 31_389 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPM_HF_CFG3[1] origin:064-gtp-channel-conf 30_390 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPM_HF_CFG3[2] origin:064-gtp-channel-conf 31_390 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPM_HF_CFG3[3] origin:064-gtp-channel-conf 30_391 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPM_HOLD_DURING_EIDLE[0] origin:064-gtp-channel-conf 28_247 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPM_INCM_CFG[0] origin:064-gtp-channel-conf 30_439 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPM_IPCM_CFG[0] origin:064-gtp-channel-conf 31_439 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPM_LF_CFG[0] origin:064-gtp-channel-conf 28_344 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPM_LF_CFG[1] origin:064-gtp-channel-conf 29_344 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPM_LF_CFG[2] origin:064-gtp-channel-conf 28_345 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPM_LF_CFG[3] origin:064-gtp-channel-conf 29_345 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPM_LF_CFG[4] origin:064-gtp-channel-conf 28_346 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPM_LF_CFG[5] origin:064-gtp-channel-conf 29_346 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPM_LF_CFG[6] origin:064-gtp-channel-conf 28_347 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPM_LF_CFG[7] origin:064-gtp-channel-conf 29_347 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPM_LF_CFG[8] origin:064-gtp-channel-conf 28_348 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPM_LF_CFG[9] origin:064-gtp-channel-conf 29_348 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPM_LF_CFG[10] origin:064-gtp-channel-conf 28_349 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPM_LF_CFG[11] origin:064-gtp-channel-conf 29_349 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPM_LF_CFG[12] origin:064-gtp-channel-conf 28_350 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPM_LF_CFG[13] origin:064-gtp-channel-conf 29_350 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPM_LF_CFG[14] origin:064-gtp-channel-conf 28_351 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPM_LF_CFG[15] origin:064-gtp-channel-conf 29_351 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPM_LF_CFG[16] origin:064-gtp-channel-conf 28_343 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPM_LF_CFG[17] origin:064-gtp-channel-conf 29_343 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPM_LF_CFG2[0] origin:064-gtp-channel-conf 31_426 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPM_LF_CFG2[1] origin:064-gtp-channel-conf 30_427 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPM_LF_CFG2[2] origin:064-gtp-channel-conf 31_427 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPM_LF_CFG2[3] origin:064-gtp-channel-conf 30_428 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPM_LF_CFG2[4] origin:064-gtp-channel-conf 31_428 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPM_OSINT_CFG[0] origin:064-gtp-channel-conf 30_440 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPM_OSINT_CFG[1] origin:064-gtp-channel-conf 31_440 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPM_OSINT_CFG[2] origin:064-gtp-channel-conf 30_441 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPM_CFG1[0] origin:064-gtp-channel-conf 30_330 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPMRESET_TIME[0] origin:064-gtp-channel-conf 28_112 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPMRESET_TIME[1] origin:064-gtp-channel-conf 29_112 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPMRESET_TIME[2] origin:064-gtp-channel-conf 28_113 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPMRESET_TIME[3] origin:064-gtp-channel-conf 29_113 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPMRESET_TIME[4] origin:064-gtp-channel-conf 28_114 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPMRESET_TIME[5] origin:064-gtp-channel-conf 29_114 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXLPMRESET_TIME[6] origin:064-gtp-channel-conf 28_115 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXOOB_CFG[0] origin:064-gtp-channel-conf 28_144 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXOOB_CFG[1] origin:064-gtp-channel-conf 29_144 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXOOB_CFG[2] origin:064-gtp-channel-conf 28_145 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXOOB_CFG[3] origin:064-gtp-channel-conf 29_145 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXOOB_CFG[4] origin:064-gtp-channel-conf 28_146 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXOOB_CFG[5] origin:064-gtp-channel-conf 29_146 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXOOB_CFG[6] origin:064-gtp-channel-conf 28_147 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXOOB_CLK_CFG.FABRIC origin:064-gtp-channel-conf 31_129 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXOSCALRESET_TIME[0] origin:064-gtp-channel-conf 28_187 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXOSCALRESET_TIME[1] origin:064-gtp-channel-conf 29_187 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXOSCALRESET_TIME[2] origin:064-gtp-channel-conf 28_188 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXOSCALRESET_TIME[3] origin:064-gtp-channel-conf 29_188 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXOSCALRESET_TIME[4] origin:064-gtp-channel-conf 28_189 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXOSCALRESET_TIMEOUT[0] origin:064-gtp-channel-conf 29_189 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXOSCALRESET_TIMEOUT[1] origin:064-gtp-channel-conf 28_190 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXOSCALRESET_TIMEOUT[2] origin:064-gtp-channel-conf 29_190 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXOSCALRESET_TIMEOUT[3] origin:064-gtp-channel-conf 28_191 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXOSCALRESET_TIMEOUT[4] origin:064-gtp-channel-conf 29_191 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXOUT_DIV[0] origin:064-gtp-channel-conf 30_384 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXOUT_DIV[1] origin:064-gtp-channel-conf 31_384 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXPCSRESET_TIME[0] origin:064-gtp-channel-conf 29_115 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXPCSRESET_TIME[1] origin:064-gtp-channel-conf 28_116 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXPCSRESET_TIME[2] origin:064-gtp-channel-conf 29_116 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXPCSRESET_TIME[3] origin:064-gtp-channel-conf 28_117 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXPCSRESET_TIME[4] origin:064-gtp-channel-conf 29_117 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXPH_CFG[0] origin:064-gtp-channel-conf 30_584 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXPH_CFG[1] origin:064-gtp-channel-conf 31_584 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXPH_CFG[2] origin:064-gtp-channel-conf 30_585 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXPH_CFG[3] origin:064-gtp-channel-conf 31_585 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXPH_CFG[4] origin:064-gtp-channel-conf 30_586 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXPH_CFG[5] origin:064-gtp-channel-conf 31_586 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXPH_CFG[6] origin:064-gtp-channel-conf 30_587 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXPH_CFG[7] origin:064-gtp-channel-conf 31_587 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXPH_CFG[8] origin:064-gtp-channel-conf 30_588 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXPH_CFG[9] origin:064-gtp-channel-conf 31_588 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXPH_CFG[10] origin:064-gtp-channel-conf 30_589 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXPH_CFG[11] origin:064-gtp-channel-conf 31_589 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXPH_CFG[12] origin:064-gtp-channel-conf 30_590 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXPH_CFG[13] origin:064-gtp-channel-conf 31_590 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXPH_CFG[14] origin:064-gtp-channel-conf 30_591 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXPH_CFG[15] origin:064-gtp-channel-conf 31_591 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXPH_CFG[16] origin:064-gtp-channel-conf 30_592 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXPH_CFG[17] origin:064-gtp-channel-conf 31_592 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXPH_CFG[18] origin:064-gtp-channel-conf 30_593 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXPH_CFG[19] origin:064-gtp-channel-conf 31_593 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXPH_CFG[20] origin:064-gtp-channel-conf 30_594 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXPH_CFG[21] origin:064-gtp-channel-conf 31_594 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXPH_CFG[22] origin:064-gtp-channel-conf 30_595 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXPH_CFG[23] origin:064-gtp-channel-conf 31_595 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXPH_MONITOR_SEL[0] origin:064-gtp-channel-conf 28_700 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXPH_MONITOR_SEL[1] origin:064-gtp-channel-conf 29_700 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXPH_MONITOR_SEL[2] origin:064-gtp-channel-conf 28_701 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXPH_MONITOR_SEL[3] origin:064-gtp-channel-conf 29_701 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXPH_MONITOR_SEL[4] origin:064-gtp-channel-conf 28_702 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXPHDLY_CFG[0] origin:064-gtp-channel-conf 30_600 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXPHDLY_CFG[1] origin:064-gtp-channel-conf 31_600 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXPHDLY_CFG[2] origin:064-gtp-channel-conf 30_601 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXPHDLY_CFG[3] origin:064-gtp-channel-conf 31_601 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXPHDLY_CFG[4] origin:064-gtp-channel-conf 30_602 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXPHDLY_CFG[5] origin:064-gtp-channel-conf 31_602 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXPHDLY_CFG[6] origin:064-gtp-channel-conf 30_603 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXPHDLY_CFG[7] origin:064-gtp-channel-conf 31_603 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXPHDLY_CFG[8] origin:064-gtp-channel-conf 30_604 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXPHDLY_CFG[9] origin:064-gtp-channel-conf 31_604 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXPHDLY_CFG[10] origin:064-gtp-channel-conf 30_605 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXPHDLY_CFG[11] origin:064-gtp-channel-conf 31_605 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXPHDLY_CFG[12] origin:064-gtp-channel-conf 30_606 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXPHDLY_CFG[13] origin:064-gtp-channel-conf 31_606 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXPHDLY_CFG[14] origin:064-gtp-channel-conf 30_607 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXPHDLY_CFG[15] origin:064-gtp-channel-conf 31_607 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXPHDLY_CFG[16] origin:064-gtp-channel-conf 30_608 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXPHDLY_CFG[17] origin:064-gtp-channel-conf 31_608 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXPHDLY_CFG[18] origin:064-gtp-channel-conf 30_609 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXPHDLY_CFG[19] origin:064-gtp-channel-conf 31_609 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXPHDLY_CFG[20] origin:064-gtp-channel-conf 30_610 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXPHDLY_CFG[21] origin:064-gtp-channel-conf 31_610 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXPHDLY_CFG[22] origin:064-gtp-channel-conf 30_611 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXPHDLY_CFG[23] origin:064-gtp-channel-conf 31_611 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXPI_CFG0[0] origin:064-gtp-channel-conf 31_430 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXPI_CFG0[1] origin:064-gtp-channel-conf 30_431 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXPI_CFG0[2] origin:064-gtp-channel-conf 31_431 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXPI_CFG1[0] origin:064-gtp-channel-conf 30_442 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXPI_CFG2[0] origin:064-gtp-channel-conf 31_441 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXPMARESET_TIME[0] origin:064-gtp-channel-conf 28_104 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXPMARESET_TIME[1] origin:064-gtp-channel-conf 29_104 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXPMARESET_TIME[2] origin:064-gtp-channel-conf 28_105 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXPMARESET_TIME[3] origin:064-gtp-channel-conf 29_105 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXPMARESET_TIME[4] origin:064-gtp-channel-conf 28_106 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXPRBS_ERR_LOOPBACK[0] origin:064-gtp-channel-conf 28_136 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXSLIDE_AUTO_WAIT[0] origin:064-gtp-channel-conf 28_520 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXSLIDE_AUTO_WAIT[1] origin:064-gtp-channel-conf 29_520 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXSLIDE_AUTO_WAIT[2] origin:064-gtp-channel-conf 28_521 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXSLIDE_AUTO_WAIT[3] origin:064-gtp-channel-conf 29_521 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXSLIDE_MODE.AUTO origin:064-gtp-channel-conf !29_519 28_519 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXSLIDE_MODE.PCS origin:064-gtp-channel-conf !28_519 29_519 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXSLIDE_MODE.PMA origin:064-gtp-channel-conf 28_519 29_519 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXSYNC_MULTILANE[0] origin:064-gtp-channel-conf 28_133 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXSYNC_OVRD[0] origin:064-gtp-channel-conf 29_135 +GTP_CHANNEL_3.GTPE2_CHANNEL.RXSYNC_SKIP_DA[0] origin:064-gtp-channel-conf 29_134 +GTP_CHANNEL_3.GTPE2_CHANNEL.SAS_MAX_COM[0] origin:064-gtp-channel-conf 28_171 +GTP_CHANNEL_3.GTPE2_CHANNEL.SAS_MAX_COM[1] origin:064-gtp-channel-conf 29_171 +GTP_CHANNEL_3.GTPE2_CHANNEL.SAS_MAX_COM[2] origin:064-gtp-channel-conf 28_172 +GTP_CHANNEL_3.GTPE2_CHANNEL.SAS_MAX_COM[3] origin:064-gtp-channel-conf 29_172 +GTP_CHANNEL_3.GTPE2_CHANNEL.SAS_MAX_COM[4] origin:064-gtp-channel-conf 28_173 +GTP_CHANNEL_3.GTPE2_CHANNEL.SAS_MAX_COM[5] origin:064-gtp-channel-conf 29_173 +GTP_CHANNEL_3.GTPE2_CHANNEL.SAS_MAX_COM[6] origin:064-gtp-channel-conf 28_174 +GTP_CHANNEL_3.GTPE2_CHANNEL.SAS_MIN_COM[0] origin:064-gtp-channel-conf 29_156 +GTP_CHANNEL_3.GTPE2_CHANNEL.SAS_MIN_COM[1] origin:064-gtp-channel-conf 28_157 +GTP_CHANNEL_3.GTPE2_CHANNEL.SAS_MIN_COM[2] origin:064-gtp-channel-conf 29_157 +GTP_CHANNEL_3.GTPE2_CHANNEL.SAS_MIN_COM[3] origin:064-gtp-channel-conf 28_158 +GTP_CHANNEL_3.GTPE2_CHANNEL.SAS_MIN_COM[4] origin:064-gtp-channel-conf 29_158 +GTP_CHANNEL_3.GTPE2_CHANNEL.SAS_MIN_COM[5] origin:064-gtp-channel-conf 28_159 +GTP_CHANNEL_3.GTPE2_CHANNEL.SATA_BURST_SEQ_LEN[0] origin:064-gtp-channel-conf 28_150 +GTP_CHANNEL_3.GTPE2_CHANNEL.SATA_BURST_SEQ_LEN[1] origin:064-gtp-channel-conf 29_150 +GTP_CHANNEL_3.GTPE2_CHANNEL.SATA_BURST_SEQ_LEN[2] origin:064-gtp-channel-conf 28_151 +GTP_CHANNEL_3.GTPE2_CHANNEL.SATA_BURST_SEQ_LEN[3] origin:064-gtp-channel-conf 29_151 +GTP_CHANNEL_3.GTPE2_CHANNEL.SATA_BURST_VAL[0] origin:064-gtp-channel-conf 29_147 +GTP_CHANNEL_3.GTPE2_CHANNEL.SATA_BURST_VAL[1] origin:064-gtp-channel-conf 28_148 +GTP_CHANNEL_3.GTPE2_CHANNEL.SATA_BURST_VAL[2] origin:064-gtp-channel-conf 29_148 +GTP_CHANNEL_3.GTPE2_CHANNEL.SATA_EIDLE_VAL[0] origin:064-gtp-channel-conf 28_152 +GTP_CHANNEL_3.GTPE2_CHANNEL.SATA_EIDLE_VAL[1] origin:064-gtp-channel-conf 29_152 +GTP_CHANNEL_3.GTPE2_CHANNEL.SATA_EIDLE_VAL[2] origin:064-gtp-channel-conf 28_153 +GTP_CHANNEL_3.GTPE2_CHANNEL.SATA_MAX_BURST[0] origin:064-gtp-channel-conf 28_168 +GTP_CHANNEL_3.GTPE2_CHANNEL.SATA_MAX_BURST[1] origin:064-gtp-channel-conf 29_168 +GTP_CHANNEL_3.GTPE2_CHANNEL.SATA_MAX_BURST[2] origin:064-gtp-channel-conf 28_169 +GTP_CHANNEL_3.GTPE2_CHANNEL.SATA_MAX_BURST[3] origin:064-gtp-channel-conf 29_169 +GTP_CHANNEL_3.GTPE2_CHANNEL.SATA_MAX_BURST[4] origin:064-gtp-channel-conf 28_170 +GTP_CHANNEL_3.GTPE2_CHANNEL.SATA_MAX_BURST[5] origin:064-gtp-channel-conf 29_170 +GTP_CHANNEL_3.GTPE2_CHANNEL.SATA_MAX_INIT[0] origin:064-gtp-channel-conf 28_176 +GTP_CHANNEL_3.GTPE2_CHANNEL.SATA_MAX_INIT[1] origin:064-gtp-channel-conf 29_176 +GTP_CHANNEL_3.GTPE2_CHANNEL.SATA_MAX_INIT[2] origin:064-gtp-channel-conf 28_177 +GTP_CHANNEL_3.GTPE2_CHANNEL.SATA_MAX_INIT[3] origin:064-gtp-channel-conf 29_177 +GTP_CHANNEL_3.GTPE2_CHANNEL.SATA_MAX_INIT[4] origin:064-gtp-channel-conf 28_178 +GTP_CHANNEL_3.GTPE2_CHANNEL.SATA_MAX_INIT[5] origin:064-gtp-channel-conf 29_178 +GTP_CHANNEL_3.GTPE2_CHANNEL.SATA_MAX_WAKE[0] origin:064-gtp-channel-conf 28_179 +GTP_CHANNEL_3.GTPE2_CHANNEL.SATA_MAX_WAKE[1] origin:064-gtp-channel-conf 29_179 +GTP_CHANNEL_3.GTPE2_CHANNEL.SATA_MAX_WAKE[2] origin:064-gtp-channel-conf 28_180 +GTP_CHANNEL_3.GTPE2_CHANNEL.SATA_MAX_WAKE[3] origin:064-gtp-channel-conf 29_180 +GTP_CHANNEL_3.GTPE2_CHANNEL.SATA_MAX_WAKE[4] origin:064-gtp-channel-conf 28_181 +GTP_CHANNEL_3.GTPE2_CHANNEL.SATA_MAX_WAKE[5] origin:064-gtp-channel-conf 29_181 +GTP_CHANNEL_3.GTPE2_CHANNEL.SATA_MIN_BURST[0] origin:064-gtp-channel-conf 29_153 +GTP_CHANNEL_3.GTPE2_CHANNEL.SATA_MIN_BURST[1] origin:064-gtp-channel-conf 28_154 +GTP_CHANNEL_3.GTPE2_CHANNEL.SATA_MIN_BURST[2] origin:064-gtp-channel-conf 29_154 +GTP_CHANNEL_3.GTPE2_CHANNEL.SATA_MIN_BURST[3] origin:064-gtp-channel-conf 28_155 +GTP_CHANNEL_3.GTPE2_CHANNEL.SATA_MIN_BURST[4] origin:064-gtp-channel-conf 29_155 +GTP_CHANNEL_3.GTPE2_CHANNEL.SATA_MIN_BURST[5] origin:064-gtp-channel-conf 28_156 +GTP_CHANNEL_3.GTPE2_CHANNEL.SATA_MIN_INIT[0] origin:064-gtp-channel-conf 28_160 +GTP_CHANNEL_3.GTPE2_CHANNEL.SATA_MIN_INIT[1] origin:064-gtp-channel-conf 29_160 +GTP_CHANNEL_3.GTPE2_CHANNEL.SATA_MIN_INIT[2] origin:064-gtp-channel-conf 28_161 +GTP_CHANNEL_3.GTPE2_CHANNEL.SATA_MIN_INIT[3] origin:064-gtp-channel-conf 29_161 +GTP_CHANNEL_3.GTPE2_CHANNEL.SATA_MIN_INIT[4] origin:064-gtp-channel-conf 28_162 +GTP_CHANNEL_3.GTPE2_CHANNEL.SATA_MIN_INIT[5] origin:064-gtp-channel-conf 29_162 +GTP_CHANNEL_3.GTPE2_CHANNEL.SATA_MIN_WAKE[0] origin:064-gtp-channel-conf 28_163 +GTP_CHANNEL_3.GTPE2_CHANNEL.SATA_MIN_WAKE[1] origin:064-gtp-channel-conf 29_163 +GTP_CHANNEL_3.GTPE2_CHANNEL.SATA_MIN_WAKE[2] origin:064-gtp-channel-conf 28_164 +GTP_CHANNEL_3.GTPE2_CHANNEL.SATA_MIN_WAKE[3] origin:064-gtp-channel-conf 29_164 +GTP_CHANNEL_3.GTPE2_CHANNEL.SATA_MIN_WAKE[4] origin:064-gtp-channel-conf 28_165 +GTP_CHANNEL_3.GTPE2_CHANNEL.SATA_MIN_WAKE[5] origin:064-gtp-channel-conf 29_165 +GTP_CHANNEL_3.GTPE2_CHANNEL.SATA_PLL_CFG.VCO_1500MHZ origin:064-gtp-channel-conf 30_55 +GTP_CHANNEL_3.GTPE2_CHANNEL.SATA_PLL_CFG.VCO_750MHZ origin:064-gtp-channel-conf 31_55 +GTP_CHANNEL_3.GTPE2_CHANNEL.SHOW_REALIGN_COMMA origin:064-gtp-channel-conf 29_522 +GTP_CHANNEL_3.GTPE2_CHANNEL.TERM_RCAL_CFG[0] origin:064-gtp-channel-conf 30_136 +GTP_CHANNEL_3.GTPE2_CHANNEL.TERM_RCAL_CFG[1] origin:064-gtp-channel-conf 31_136 +GTP_CHANNEL_3.GTPE2_CHANNEL.TERM_RCAL_CFG[2] origin:064-gtp-channel-conf 30_137 +GTP_CHANNEL_3.GTPE2_CHANNEL.TERM_RCAL_CFG[3] origin:064-gtp-channel-conf 31_137 +GTP_CHANNEL_3.GTPE2_CHANNEL.TERM_RCAL_CFG[4] origin:064-gtp-channel-conf 30_138 +GTP_CHANNEL_3.GTPE2_CHANNEL.TERM_RCAL_CFG[5] origin:064-gtp-channel-conf 31_138 +GTP_CHANNEL_3.GTPE2_CHANNEL.TERM_RCAL_CFG[6] origin:064-gtp-channel-conf 30_139 +GTP_CHANNEL_3.GTPE2_CHANNEL.TERM_RCAL_CFG[7] origin:064-gtp-channel-conf 31_139 +GTP_CHANNEL_3.GTPE2_CHANNEL.TERM_RCAL_CFG[8] origin:064-gtp-channel-conf 30_140 +GTP_CHANNEL_3.GTPE2_CHANNEL.TERM_RCAL_CFG[9] origin:064-gtp-channel-conf 31_140 +GTP_CHANNEL_3.GTPE2_CHANNEL.TERM_RCAL_CFG[10] origin:064-gtp-channel-conf 30_141 +GTP_CHANNEL_3.GTPE2_CHANNEL.TERM_RCAL_CFG[11] origin:064-gtp-channel-conf 31_141 +GTP_CHANNEL_3.GTPE2_CHANNEL.TERM_RCAL_CFG[12] origin:064-gtp-channel-conf 30_142 +GTP_CHANNEL_3.GTPE2_CHANNEL.TERM_RCAL_CFG[13] origin:064-gtp-channel-conf 31_142 +GTP_CHANNEL_3.GTPE2_CHANNEL.TERM_RCAL_CFG[14] origin:064-gtp-channel-conf 30_143 +GTP_CHANNEL_3.GTPE2_CHANNEL.TERM_RCAL_OVRD[0] origin:064-gtp-channel-conf 31_150 +GTP_CHANNEL_3.GTPE2_CHANNEL.TERM_RCAL_OVRD[1] origin:064-gtp-channel-conf 30_151 +GTP_CHANNEL_3.GTPE2_CHANNEL.TERM_RCAL_OVRD[2] origin:064-gtp-channel-conf 31_151 +GTP_CHANNEL_3.GTPE2_CHANNEL.TRANS_TIME_RATE[0] origin:064-gtp-channel-conf 28_192 +GTP_CHANNEL_3.GTPE2_CHANNEL.TRANS_TIME_RATE[1] origin:064-gtp-channel-conf 29_192 +GTP_CHANNEL_3.GTPE2_CHANNEL.TRANS_TIME_RATE[2] origin:064-gtp-channel-conf 28_193 +GTP_CHANNEL_3.GTPE2_CHANNEL.TRANS_TIME_RATE[3] origin:064-gtp-channel-conf 29_193 +GTP_CHANNEL_3.GTPE2_CHANNEL.TRANS_TIME_RATE[4] origin:064-gtp-channel-conf 28_194 +GTP_CHANNEL_3.GTPE2_CHANNEL.TRANS_TIME_RATE[5] origin:064-gtp-channel-conf 29_194 +GTP_CHANNEL_3.GTPE2_CHANNEL.TRANS_TIME_RATE[6] origin:064-gtp-channel-conf 28_195 +GTP_CHANNEL_3.GTPE2_CHANNEL.TRANS_TIME_RATE[7] origin:064-gtp-channel-conf 29_195 +GTP_CHANNEL_3.GTPE2_CHANNEL.TST_RSV[0] origin:064-gtp-channel-conf 30_504 +GTP_CHANNEL_3.GTPE2_CHANNEL.TST_RSV[1] origin:064-gtp-channel-conf 31_504 +GTP_CHANNEL_3.GTPE2_CHANNEL.TST_RSV[2] origin:064-gtp-channel-conf 30_505 +GTP_CHANNEL_3.GTPE2_CHANNEL.TST_RSV[3] origin:064-gtp-channel-conf 31_505 +GTP_CHANNEL_3.GTPE2_CHANNEL.TST_RSV[4] origin:064-gtp-channel-conf 30_506 +GTP_CHANNEL_3.GTPE2_CHANNEL.TST_RSV[5] origin:064-gtp-channel-conf 31_506 +GTP_CHANNEL_3.GTPE2_CHANNEL.TST_RSV[6] origin:064-gtp-channel-conf 30_507 +GTP_CHANNEL_3.GTPE2_CHANNEL.TST_RSV[7] origin:064-gtp-channel-conf 31_507 +GTP_CHANNEL_3.GTPE2_CHANNEL.TST_RSV[8] origin:064-gtp-channel-conf 30_508 +GTP_CHANNEL_3.GTPE2_CHANNEL.TST_RSV[9] origin:064-gtp-channel-conf 31_508 +GTP_CHANNEL_3.GTPE2_CHANNEL.TST_RSV[10] origin:064-gtp-channel-conf 30_509 +GTP_CHANNEL_3.GTPE2_CHANNEL.TST_RSV[11] origin:064-gtp-channel-conf 31_509 +GTP_CHANNEL_3.GTPE2_CHANNEL.TST_RSV[12] origin:064-gtp-channel-conf 30_510 +GTP_CHANNEL_3.GTPE2_CHANNEL.TST_RSV[13] origin:064-gtp-channel-conf 31_510 +GTP_CHANNEL_3.GTPE2_CHANNEL.TST_RSV[14] origin:064-gtp-channel-conf 30_511 +GTP_CHANNEL_3.GTPE2_CHANNEL.TST_RSV[15] origin:064-gtp-channel-conf 31_511 +GTP_CHANNEL_3.GTPE2_CHANNEL.TST_RSV[16] origin:064-gtp-channel-conf 30_512 +GTP_CHANNEL_3.GTPE2_CHANNEL.TST_RSV[17] origin:064-gtp-channel-conf 31_512 +GTP_CHANNEL_3.GTPE2_CHANNEL.TST_RSV[18] origin:064-gtp-channel-conf 30_513 +GTP_CHANNEL_3.GTPE2_CHANNEL.TST_RSV[19] origin:064-gtp-channel-conf 31_513 +GTP_CHANNEL_3.GTPE2_CHANNEL.TST_RSV[20] origin:064-gtp-channel-conf 30_514 +GTP_CHANNEL_3.GTPE2_CHANNEL.TST_RSV[21] origin:064-gtp-channel-conf 31_514 +GTP_CHANNEL_3.GTPE2_CHANNEL.TST_RSV[22] origin:064-gtp-channel-conf 30_515 +GTP_CHANNEL_3.GTPE2_CHANNEL.TST_RSV[23] origin:064-gtp-channel-conf 31_515 +GTP_CHANNEL_3.GTPE2_CHANNEL.TST_RSV[24] origin:064-gtp-channel-conf 30_516 +GTP_CHANNEL_3.GTPE2_CHANNEL.TST_RSV[25] origin:064-gtp-channel-conf 31_516 +GTP_CHANNEL_3.GTPE2_CHANNEL.TST_RSV[26] origin:064-gtp-channel-conf 30_517 +GTP_CHANNEL_3.GTPE2_CHANNEL.TST_RSV[27] origin:064-gtp-channel-conf 31_517 +GTP_CHANNEL_3.GTPE2_CHANNEL.TST_RSV[28] origin:064-gtp-channel-conf 30_518 +GTP_CHANNEL_3.GTPE2_CHANNEL.TST_RSV[29] origin:064-gtp-channel-conf 31_518 +GTP_CHANNEL_3.GTPE2_CHANNEL.TST_RSV[30] origin:064-gtp-channel-conf 30_519 +GTP_CHANNEL_3.GTPE2_CHANNEL.TST_RSV[31] origin:064-gtp-channel-conf 31_519 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_CLKMUX_EN[0] origin:064-gtp-channel-conf 31_128 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_DATA_WIDTH[0] origin:064-gtp-channel-conf 30_152 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_DATA_WIDTH[1] origin:064-gtp-channel-conf 31_152 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_DATA_WIDTH[2] origin:064-gtp-channel-conf 30_153 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_DRIVE_MODE.PIPE origin:064-gtp-channel-conf 28_200 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_EIDLE_ASSERT_DELAY[0] origin:064-gtp-channel-conf 28_203 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_EIDLE_ASSERT_DELAY[1] origin:064-gtp-channel-conf 29_203 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_EIDLE_ASSERT_DELAY[2] origin:064-gtp-channel-conf 28_204 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_EIDLE_DEASSERT_DELAY[0] origin:064-gtp-channel-conf 29_204 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_EIDLE_DEASSERT_DELAY[1] origin:064-gtp-channel-conf 28_205 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_EIDLE_DEASSERT_DELAY[2] origin:064-gtp-channel-conf 29_205 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_LOOPBACK_DRIVE_HIZ origin:064-gtp-channel-conf 29_202 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_MAINCURSOR_SEL[0] origin:064-gtp-channel-conf 31_289 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_MARGIN_FULL_0[0] origin:064-gtp-channel-conf 30_232 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_MARGIN_FULL_0[1] origin:064-gtp-channel-conf 31_232 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_MARGIN_FULL_0[2] origin:064-gtp-channel-conf 30_233 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_MARGIN_FULL_0[3] origin:064-gtp-channel-conf 31_233 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_MARGIN_FULL_0[4] origin:064-gtp-channel-conf 30_234 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_MARGIN_FULL_0[5] origin:064-gtp-channel-conf 31_234 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_MARGIN_FULL_0[6] origin:064-gtp-channel-conf 30_235 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_MARGIN_FULL_1[0] origin:064-gtp-channel-conf 30_236 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_MARGIN_FULL_1[1] origin:064-gtp-channel-conf 31_236 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_MARGIN_FULL_1[2] origin:064-gtp-channel-conf 30_237 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_MARGIN_FULL_1[3] origin:064-gtp-channel-conf 31_237 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_MARGIN_FULL_1[4] origin:064-gtp-channel-conf 30_238 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_MARGIN_FULL_1[5] origin:064-gtp-channel-conf 31_238 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_MARGIN_FULL_1[6] origin:064-gtp-channel-conf 30_239 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_MARGIN_FULL_2[0] origin:064-gtp-channel-conf 30_240 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_MARGIN_FULL_2[1] origin:064-gtp-channel-conf 31_240 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_MARGIN_FULL_2[2] origin:064-gtp-channel-conf 30_241 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_MARGIN_FULL_2[3] origin:064-gtp-channel-conf 31_241 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_MARGIN_FULL_2[4] origin:064-gtp-channel-conf 30_242 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_MARGIN_FULL_2[5] origin:064-gtp-channel-conf 31_242 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_MARGIN_FULL_2[6] origin:064-gtp-channel-conf 30_243 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_MARGIN_FULL_3[0] origin:064-gtp-channel-conf 30_244 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_MARGIN_FULL_3[1] origin:064-gtp-channel-conf 31_244 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_MARGIN_FULL_3[2] origin:064-gtp-channel-conf 30_245 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_MARGIN_FULL_3[3] origin:064-gtp-channel-conf 31_245 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_MARGIN_FULL_3[4] origin:064-gtp-channel-conf 30_246 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_MARGIN_FULL_3[5] origin:064-gtp-channel-conf 31_246 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_MARGIN_FULL_3[6] origin:064-gtp-channel-conf 30_247 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_MARGIN_FULL_4[0] origin:064-gtp-channel-conf 30_248 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_MARGIN_FULL_4[1] origin:064-gtp-channel-conf 31_248 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_MARGIN_FULL_4[2] origin:064-gtp-channel-conf 30_249 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_MARGIN_FULL_4[3] origin:064-gtp-channel-conf 31_249 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_MARGIN_FULL_4[4] origin:064-gtp-channel-conf 30_250 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_MARGIN_FULL_4[5] origin:064-gtp-channel-conf 31_250 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_MARGIN_FULL_4[6] origin:064-gtp-channel-conf 30_251 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_MARGIN_LOW_0[0] origin:064-gtp-channel-conf 30_252 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_MARGIN_LOW_0[1] origin:064-gtp-channel-conf 31_252 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_MARGIN_LOW_0[2] origin:064-gtp-channel-conf 30_253 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_MARGIN_LOW_0[3] origin:064-gtp-channel-conf 31_253 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_MARGIN_LOW_0[4] origin:064-gtp-channel-conf 30_254 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_MARGIN_LOW_0[5] origin:064-gtp-channel-conf 31_254 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_MARGIN_LOW_0[6] origin:064-gtp-channel-conf 30_255 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_MARGIN_LOW_1[0] origin:064-gtp-channel-conf 30_256 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_MARGIN_LOW_1[1] origin:064-gtp-channel-conf 31_256 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_MARGIN_LOW_1[2] origin:064-gtp-channel-conf 30_257 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_MARGIN_LOW_1[3] origin:064-gtp-channel-conf 31_257 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_MARGIN_LOW_1[4] origin:064-gtp-channel-conf 30_258 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_MARGIN_LOW_1[5] origin:064-gtp-channel-conf 31_258 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_MARGIN_LOW_1[6] origin:064-gtp-channel-conf 30_259 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_MARGIN_LOW_2[0] origin:064-gtp-channel-conf 30_260 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_MARGIN_LOW_2[1] origin:064-gtp-channel-conf 31_260 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_MARGIN_LOW_2[2] origin:064-gtp-channel-conf 30_261 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_MARGIN_LOW_2[3] origin:064-gtp-channel-conf 31_261 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_MARGIN_LOW_2[4] origin:064-gtp-channel-conf 30_262 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_MARGIN_LOW_2[5] origin:064-gtp-channel-conf 31_262 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_MARGIN_LOW_2[6] origin:064-gtp-channel-conf 30_263 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_MARGIN_LOW_3[0] origin:064-gtp-channel-conf 30_264 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_MARGIN_LOW_3[1] origin:064-gtp-channel-conf 31_264 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_MARGIN_LOW_3[2] origin:064-gtp-channel-conf 30_265 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_MARGIN_LOW_3[3] origin:064-gtp-channel-conf 31_265 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_MARGIN_LOW_3[4] origin:064-gtp-channel-conf 30_266 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_MARGIN_LOW_3[5] origin:064-gtp-channel-conf 31_266 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_MARGIN_LOW_3[6] origin:064-gtp-channel-conf 30_267 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_MARGIN_LOW_4[0] origin:064-gtp-channel-conf 30_268 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_MARGIN_LOW_4[1] origin:064-gtp-channel-conf 31_268 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_MARGIN_LOW_4[2] origin:064-gtp-channel-conf 30_269 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_MARGIN_LOW_4[3] origin:064-gtp-channel-conf 31_269 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_MARGIN_LOW_4[4] origin:064-gtp-channel-conf 30_270 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_MARGIN_LOW_4[5] origin:064-gtp-channel-conf 31_270 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_MARGIN_LOW_4[6] origin:064-gtp-channel-conf 30_271 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_PREDRIVER_MODE[0] origin:064-gtp-channel-conf 28_206 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_RXDETECT_CFG[0] origin:064-gtp-channel-conf 30_296 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_RXDETECT_CFG[1] origin:064-gtp-channel-conf 31_296 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_RXDETECT_CFG[2] origin:064-gtp-channel-conf 30_297 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_RXDETECT_CFG[3] origin:064-gtp-channel-conf 31_297 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_RXDETECT_CFG[4] origin:064-gtp-channel-conf 30_298 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_RXDETECT_CFG[5] origin:064-gtp-channel-conf 31_298 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_RXDETECT_CFG[6] origin:064-gtp-channel-conf 30_299 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_RXDETECT_CFG[7] origin:064-gtp-channel-conf 31_299 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_RXDETECT_CFG[8] origin:064-gtp-channel-conf 30_300 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_RXDETECT_CFG[9] origin:064-gtp-channel-conf 31_300 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_RXDETECT_CFG[10] origin:064-gtp-channel-conf 30_301 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_RXDETECT_CFG[11] origin:064-gtp-channel-conf 31_301 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_RXDETECT_CFG[12] origin:064-gtp-channel-conf 30_302 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_RXDETECT_CFG[13] origin:064-gtp-channel-conf 31_302 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_RXDETECT_REF[0] origin:064-gtp-channel-conf 30_292 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_RXDETECT_REF[1] origin:064-gtp-channel-conf 31_292 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_RXDETECT_REF[2] origin:064-gtp-channel-conf 30_293 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_XCLK_SEL.TXUSR origin:064-gtp-channel-conf 31_11 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_CLK25_DIV[0] origin:064-gtp-channel-conf 30_144 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_CLK25_DIV[1] origin:064-gtp-channel-conf 31_144 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_CLK25_DIV[2] origin:064-gtp-channel-conf 30_145 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_CLK25_DIV[3] origin:064-gtp-channel-conf 31_145 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_CLK25_DIV[4] origin:064-gtp-channel-conf 30_146 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_DEEMPH0[0] origin:064-gtp-channel-conf 30_272 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_DEEMPH0[1] origin:064-gtp-channel-conf 31_272 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_DEEMPH0[2] origin:064-gtp-channel-conf 30_273 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_DEEMPH0[3] origin:064-gtp-channel-conf 31_273 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_DEEMPH0[4] origin:064-gtp-channel-conf 30_274 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_DEEMPH0[5] origin:064-gtp-channel-conf 31_274 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_DEEMPH1[0] origin:064-gtp-channel-conf 30_276 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_DEEMPH1[1] origin:064-gtp-channel-conf 31_276 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_DEEMPH1[2] origin:064-gtp-channel-conf 30_277 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_DEEMPH1[3] origin:064-gtp-channel-conf 31_277 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_DEEMPH1[4] origin:064-gtp-channel-conf 30_278 +GTP_CHANNEL_3.GTPE2_CHANNEL.TX_DEEMPH1[5] origin:064-gtp-channel-conf 31_278 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXBUF_EN origin:064-gtp-channel-conf 28_231 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXBUF_RESET_ON_RATE_CHANGE origin:064-gtp-channel-conf 29_231 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXDLY_CFG[0] origin:064-gtp-channel-conf 30_80 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXDLY_CFG[1] origin:064-gtp-channel-conf 31_80 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXDLY_CFG[2] origin:064-gtp-channel-conf 30_81 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXDLY_CFG[3] origin:064-gtp-channel-conf 31_81 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXDLY_CFG[4] origin:064-gtp-channel-conf 30_82 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXDLY_CFG[5] origin:064-gtp-channel-conf 31_82 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXDLY_CFG[6] origin:064-gtp-channel-conf 30_83 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXDLY_CFG[7] origin:064-gtp-channel-conf 31_83 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXDLY_CFG[8] origin:064-gtp-channel-conf 30_84 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXDLY_CFG[9] origin:064-gtp-channel-conf 31_84 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXDLY_CFG[10] origin:064-gtp-channel-conf 30_85 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXDLY_CFG[11] origin:064-gtp-channel-conf 31_85 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXDLY_CFG[12] origin:064-gtp-channel-conf 30_86 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXDLY_CFG[13] origin:064-gtp-channel-conf 31_86 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXDLY_CFG[14] origin:064-gtp-channel-conf 30_87 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXDLY_CFG[15] origin:064-gtp-channel-conf 31_87 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXDLY_LCFG[0] origin:064-gtp-channel-conf 30_568 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXDLY_LCFG[1] origin:064-gtp-channel-conf 31_568 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXDLY_LCFG[2] origin:064-gtp-channel-conf 30_569 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXDLY_LCFG[3] origin:064-gtp-channel-conf 31_569 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXDLY_LCFG[4] origin:064-gtp-channel-conf 30_570 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXDLY_LCFG[5] origin:064-gtp-channel-conf 31_570 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXDLY_LCFG[6] origin:064-gtp-channel-conf 30_571 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXDLY_LCFG[7] origin:064-gtp-channel-conf 31_571 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXDLY_LCFG[8] origin:064-gtp-channel-conf 30_572 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXDLY_TAP_CFG[0] origin:064-gtp-channel-conf 30_88 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXDLY_TAP_CFG[1] origin:064-gtp-channel-conf 31_88 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXDLY_TAP_CFG[2] origin:064-gtp-channel-conf 30_89 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXDLY_TAP_CFG[3] origin:064-gtp-channel-conf 31_89 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXDLY_TAP_CFG[4] origin:064-gtp-channel-conf 30_90 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXDLY_TAP_CFG[5] origin:064-gtp-channel-conf 31_90 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXDLY_TAP_CFG[6] origin:064-gtp-channel-conf 30_91 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXDLY_TAP_CFG[7] origin:064-gtp-channel-conf 31_91 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXDLY_TAP_CFG[8] origin:064-gtp-channel-conf 30_92 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXDLY_TAP_CFG[9] origin:064-gtp-channel-conf 31_92 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXDLY_TAP_CFG[10] origin:064-gtp-channel-conf 30_93 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXDLY_TAP_CFG[11] origin:064-gtp-channel-conf 31_93 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXDLY_TAP_CFG[12] origin:064-gtp-channel-conf 30_94 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXDLY_TAP_CFG[13] origin:064-gtp-channel-conf 31_94 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXDLY_TAP_CFG[14] origin:064-gtp-channel-conf 30_95 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXDLY_TAP_CFG[15] origin:064-gtp-channel-conf 31_95 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXGEARBOX_EN origin:064-gtp-channel-conf 29_226 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXOOB_CFG[0] origin:064-gtp-channel-conf 31_20 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXOUT_DIV[0] origin:064-gtp-channel-conf 30_386 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXOUT_DIV[1] origin:064-gtp-channel-conf 31_386 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPCSRESET_TIME[0] origin:064-gtp-channel-conf 29_130 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPCSRESET_TIME[1] origin:064-gtp-channel-conf 28_131 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPCSRESET_TIME[2] origin:064-gtp-channel-conf 29_131 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPCSRESET_TIME[3] origin:064-gtp-channel-conf 28_132 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPCSRESET_TIME[4] origin:064-gtp-channel-conf 29_132 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPH_CFG[0] origin:064-gtp-channel-conf 30_96 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPH_CFG[1] origin:064-gtp-channel-conf 31_96 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPH_CFG[2] origin:064-gtp-channel-conf 30_97 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPH_CFG[3] origin:064-gtp-channel-conf 31_97 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPH_CFG[4] origin:064-gtp-channel-conf 30_98 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPH_CFG[5] origin:064-gtp-channel-conf 31_98 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPH_CFG[6] origin:064-gtp-channel-conf 30_99 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPH_CFG[7] origin:064-gtp-channel-conf 31_99 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPH_CFG[8] origin:064-gtp-channel-conf 30_100 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPH_CFG[9] origin:064-gtp-channel-conf 31_100 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPH_CFG[10] origin:064-gtp-channel-conf 30_101 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPH_CFG[11] origin:064-gtp-channel-conf 31_101 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPH_CFG[12] origin:064-gtp-channel-conf 30_102 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPH_CFG[13] origin:064-gtp-channel-conf 31_102 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPH_CFG[14] origin:064-gtp-channel-conf 30_103 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPH_CFG[15] origin:064-gtp-channel-conf 31_103 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPH_MONITOR_SEL[0] origin:064-gtp-channel-conf 30_108 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPH_MONITOR_SEL[1] origin:064-gtp-channel-conf 31_108 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPH_MONITOR_SEL[2] origin:064-gtp-channel-conf 30_109 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPH_MONITOR_SEL[3] origin:064-gtp-channel-conf 31_109 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPH_MONITOR_SEL[4] origin:064-gtp-channel-conf 30_110 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPHDLY_CFG[0] origin:064-gtp-channel-conf 30_64 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPHDLY_CFG[1] origin:064-gtp-channel-conf 31_64 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPHDLY_CFG[2] origin:064-gtp-channel-conf 30_65 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPHDLY_CFG[3] origin:064-gtp-channel-conf 31_65 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPHDLY_CFG[4] origin:064-gtp-channel-conf 30_66 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPHDLY_CFG[5] origin:064-gtp-channel-conf 31_66 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPHDLY_CFG[6] origin:064-gtp-channel-conf 30_67 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPHDLY_CFG[7] origin:064-gtp-channel-conf 31_67 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPHDLY_CFG[8] origin:064-gtp-channel-conf 30_68 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPHDLY_CFG[9] origin:064-gtp-channel-conf 31_68 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPHDLY_CFG[10] origin:064-gtp-channel-conf 30_69 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPHDLY_CFG[11] origin:064-gtp-channel-conf 31_69 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPHDLY_CFG[12] origin:064-gtp-channel-conf 30_70 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPHDLY_CFG[13] origin:064-gtp-channel-conf 31_70 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPHDLY_CFG[14] origin:064-gtp-channel-conf 30_71 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPHDLY_CFG[15] origin:064-gtp-channel-conf 31_71 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPHDLY_CFG[16] origin:064-gtp-channel-conf 30_72 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPHDLY_CFG[17] origin:064-gtp-channel-conf 31_72 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPHDLY_CFG[18] origin:064-gtp-channel-conf 30_73 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPHDLY_CFG[19] origin:064-gtp-channel-conf 31_73 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPHDLY_CFG[20] origin:064-gtp-channel-conf 30_74 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPHDLY_CFG[21] origin:064-gtp-channel-conf 31_74 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPHDLY_CFG[22] origin:064-gtp-channel-conf 30_75 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPHDLY_CFG[23] origin:064-gtp-channel-conf 31_75 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPI_GREY_SEL[0] origin:064-gtp-channel-conf 31_498 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPI_INVSTROBE_SEL[0] origin:064-gtp-channel-conf 30_498 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPI_PPM_CFG[0] origin:064-gtp-channel-conf 30_488 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPI_PPM_CFG[1] origin:064-gtp-channel-conf 31_488 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPI_PPM_CFG[2] origin:064-gtp-channel-conf 30_489 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPI_PPM_CFG[3] origin:064-gtp-channel-conf 31_489 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPI_PPM_CFG[4] origin:064-gtp-channel-conf 30_490 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPI_PPM_CFG[5] origin:064-gtp-channel-conf 31_490 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPI_PPM_CFG[6] origin:064-gtp-channel-conf 30_491 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPI_PPM_CFG[7] origin:064-gtp-channel-conf 31_491 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPI_PPMCLK_SEL.TXUSRCLK2 origin:064-gtp-channel-conf 31_497 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPI_SYNFREQ_PPM[0] origin:064-gtp-channel-conf 30_496 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPI_SYNFREQ_PPM[1] origin:064-gtp-channel-conf 31_496 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPI_SYNFREQ_PPM[2] origin:064-gtp-channel-conf 30_497 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPI_CFG0[0] origin:064-gtp-channel-conf 30_40 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPI_CFG0[1] origin:064-gtp-channel-conf 31_40 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPI_CFG1[0] origin:064-gtp-channel-conf 30_41 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPI_CFG1[1] origin:064-gtp-channel-conf 31_41 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPI_CFG2[0] origin:064-gtp-channel-conf 30_42 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPI_CFG2[1] origin:064-gtp-channel-conf 31_42 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPI_CFG3[0] origin:064-gtp-channel-conf 30_43 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPI_CFG4[0] origin:064-gtp-channel-conf 31_43 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPI_CFG5[0] origin:064-gtp-channel-conf 30_44 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPI_CFG5[1] origin:064-gtp-channel-conf 31_44 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPI_CFG5[2] origin:064-gtp-channel-conf 30_45 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPMARESET_TIME[0] origin:064-gtp-channel-conf 28_128 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPMARESET_TIME[1] origin:064-gtp-channel-conf 29_128 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPMARESET_TIME[2] origin:064-gtp-channel-conf 28_129 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPMARESET_TIME[3] origin:064-gtp-channel-conf 29_129 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXPMARESET_TIME[4] origin:064-gtp-channel-conf 28_130 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXSYNC_MULTILANE[0] origin:064-gtp-channel-conf 29_133 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXSYNC_OVRD[0] origin:064-gtp-channel-conf 28_135 +GTP_CHANNEL_3.GTPE2_CHANNEL.TXSYNC_SKIP_DA[0] origin:064-gtp-channel-conf 28_134 +GTP_CHANNEL_3.GTPE2_CHANNEL.UCODEER_CLR[0] origin:064-gtp-channel-conf 29_00 +GTP_CHANNEL_3.GTPE2_CHANNEL.USE_PCS_CLK_PHASE_SEL[0] origin:064-gtp-channel-conf 30_463 diff --git a/artix7/segbits_gtp_channel_3_mid_left.db b/artix7/segbits_gtp_channel_3_mid_left.db index 8e3b4a4..cdfd533 100644 --- a/artix7/segbits_gtp_channel_3_mid_left.db +++ b/artix7/segbits_gtp_channel_3_mid_left.db @@ -1,1627 +1,1627 @@ -GTP_CHANNEL_3_MID_LEFT.GTPE2.ACJTAG_DEBUG_MODE[0] 00_07 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ACJTAG_MODE[0] 01_06 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ACJTAG_RESET[0] 01_07 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ADAPT_CFG0[0] 02_464 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ADAPT_CFG0[1] 03_464 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ADAPT_CFG0[2] 02_465 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ADAPT_CFG0[3] 03_465 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ADAPT_CFG0[4] 02_466 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ADAPT_CFG0[5] 03_466 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ADAPT_CFG0[6] 02_467 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ADAPT_CFG0[7] 03_467 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ADAPT_CFG0[8] 02_468 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ADAPT_CFG0[9] 03_468 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ADAPT_CFG0[10] 02_469 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ADAPT_CFG0[11] 03_469 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ADAPT_CFG0[12] 02_470 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ADAPT_CFG0[13] 03_470 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ADAPT_CFG0[14] 02_471 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ADAPT_CFG0[15] 03_471 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ADAPT_CFG0[16] 02_472 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ADAPT_CFG0[17] 03_472 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ADAPT_CFG0[18] 02_473 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ADAPT_CFG0[19] 03_473 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ALIGN_COMMA_DOUBLE 00_522 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ALIGN_COMMA_ENABLE[0] 00_496 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ALIGN_COMMA_ENABLE[1] 01_496 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ALIGN_COMMA_ENABLE[2] 00_497 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ALIGN_COMMA_ENABLE[3] 01_497 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ALIGN_COMMA_ENABLE[4] 00_498 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ALIGN_COMMA_ENABLE[5] 01_498 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ALIGN_COMMA_ENABLE[6] 00_499 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ALIGN_COMMA_ENABLE[7] 01_499 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ALIGN_COMMA_ENABLE[8] 00_500 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ALIGN_COMMA_ENABLE[9] 01_500 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ALIGN_COMMA_WORD[0] 01_526 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ALIGN_COMMA_WORD[1] 00_527 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ALIGN_MCOMMA_DET 00_523 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ALIGN_MCOMMA_VALUE[0] 00_504 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ALIGN_MCOMMA_VALUE[1] 01_504 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ALIGN_MCOMMA_VALUE[2] 00_505 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ALIGN_MCOMMA_VALUE[3] 01_505 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ALIGN_MCOMMA_VALUE[4] 00_506 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ALIGN_MCOMMA_VALUE[5] 01_506 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ALIGN_MCOMMA_VALUE[6] 00_507 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ALIGN_MCOMMA_VALUE[7] 01_507 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ALIGN_MCOMMA_VALUE[8] 00_508 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ALIGN_MCOMMA_VALUE[9] 01_508 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ALIGN_PCOMMA_DET 01_523 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ALIGN_PCOMMA_VALUE[0] 00_512 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ALIGN_PCOMMA_VALUE[1] 01_512 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ALIGN_PCOMMA_VALUE[2] 00_513 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ALIGN_PCOMMA_VALUE[3] 01_513 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ALIGN_PCOMMA_VALUE[4] 00_514 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ALIGN_PCOMMA_VALUE[5] 01_514 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ALIGN_PCOMMA_VALUE[6] 00_515 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ALIGN_PCOMMA_VALUE[7] 01_515 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ALIGN_PCOMMA_VALUE[8] 00_516 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ALIGN_PCOMMA_VALUE[9] 01_516 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CBCC_DATA_SOURCE_SEL.DECODED 01_661 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CFOK_CFG[0] 02_392 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CFOK_CFG[1] 03_392 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CFOK_CFG[2] 02_393 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CFOK_CFG[3] 03_393 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CFOK_CFG[4] 02_394 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CFOK_CFG[5] 03_394 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CFOK_CFG[6] 02_395 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CFOK_CFG[7] 03_395 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CFOK_CFG[8] 02_396 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CFOK_CFG[9] 03_396 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CFOK_CFG[10] 02_397 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CFOK_CFG[11] 03_397 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CFOK_CFG[12] 02_398 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CFOK_CFG[13] 03_398 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CFOK_CFG[14] 02_399 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CFOK_CFG[15] 03_399 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CFOK_CFG[16] 02_400 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CFOK_CFG[17] 03_400 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CFOK_CFG[18] 02_401 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CFOK_CFG[19] 03_401 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CFOK_CFG[20] 02_402 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CFOK_CFG[21] 03_402 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CFOK_CFG[22] 02_403 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CFOK_CFG[23] 03_403 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CFOK_CFG[24] 02_404 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CFOK_CFG[25] 03_404 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CFOK_CFG[26] 02_405 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CFOK_CFG[27] 03_405 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CFOK_CFG[28] 02_406 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CFOK_CFG[29] 03_406 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CFOK_CFG[30] 02_407 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CFOK_CFG[31] 03_407 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CFOK_CFG[32] 02_408 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CFOK_CFG[33] 03_408 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CFOK_CFG[34] 02_409 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CFOK_CFG[35] 03_409 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CFOK_CFG[36] 02_410 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CFOK_CFG[37] 03_410 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CFOK_CFG[38] 02_411 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CFOK_CFG[39] 03_411 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CFOK_CFG[40] 02_412 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CFOK_CFG[41] 03_412 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CFOK_CFG[42] 02_413 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CFOK_CFG2[0] 02_459 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CFOK_CFG2[1] 03_459 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CFOK_CFG2[2] 02_460 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CFOK_CFG2[3] 03_460 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CFOK_CFG2[4] 02_461 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CFOK_CFG2[5] 03_461 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CFOK_CFG2[6] 02_462 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CFOK_CFG3[0] 02_416 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CFOK_CFG3[1] 03_416 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CFOK_CFG3[2] 02_417 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CFOK_CFG3[3] 03_417 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CFOK_CFG3[4] 02_418 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CFOK_CFG3[5] 03_418 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CFOK_CFG3[6] 02_419 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CFOK_CFG4[0] 03_438 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CFOK_CFG5[0] 02_429 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CFOK_CFG5[1] 03_429 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CFOK_CFG6[0] 03_436 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CFOK_CFG6[1] 02_437 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CFOK_CFG6[2] 03_437 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CFOK_CFG6[3] 02_438 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_KEEP_ALIGN 01_631 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_MAX_SKEW[0] 00_670 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_MAX_SKEW[1] 01_670 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_MAX_SKEW[2] 00_671 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_MAX_SKEW[3] 01_671 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_1[0] 00_608 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_1[1] 01_608 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_1[2] 00_609 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_1[3] 01_609 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_1[4] 00_610 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_1[5] 01_610 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_1[6] 00_611 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_1[7] 01_611 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_1[8] 00_612 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_1[9] 01_612 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_2[0] 00_616 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_2[1] 01_616 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_2[2] 00_617 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_2[3] 01_617 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_2[4] 00_618 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_2[5] 01_618 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_2[6] 00_619 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_2[7] 01_619 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_2[8] 00_620 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_2[9] 01_620 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_3[0] 00_624 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_3[1] 01_624 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_3[2] 00_625 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_3[3] 01_625 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_3[4] 00_626 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_3[5] 01_626 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_3[6] 00_627 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_3[7] 01_627 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_3[8] 00_628 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_3[9] 01_628 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_4[0] 00_632 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_4[1] 01_632 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_4[2] 00_633 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_4[3] 01_633 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_4[4] 00_634 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_4[5] 01_634 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_4[6] 00_635 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_4[7] 01_635 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_4[8] 00_636 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_4[9] 01_636 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_ENABLE[0] 00_614 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_ENABLE[1] 01_614 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_ENABLE[2] 00_615 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_ENABLE[3] 01_615 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_1[0] 00_640 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_1[1] 01_640 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_1[2] 00_641 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_1[3] 01_641 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_1[4] 00_642 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_1[5] 01_642 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_1[6] 00_643 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_1[7] 01_643 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_1[8] 00_644 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_1[9] 01_644 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_2[0] 00_648 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_2[1] 01_648 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_2[2] 00_649 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_2[3] 01_649 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_2[4] 00_650 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_2[5] 01_650 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_2[6] 00_651 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_2[7] 01_651 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_2[8] 00_652 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_2[9] 01_652 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_3[0] 00_656 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_3[1] 01_656 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_3[2] 00_657 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_3[3] 01_657 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_3[4] 00_658 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_3[5] 01_658 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_3[6] 00_659 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_3[7] 01_659 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_3[8] 00_660 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_3[9] 01_660 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_4[0] 00_664 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_4[1] 01_664 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_4[2] 00_665 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_4[3] 01_665 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_4[4] 00_666 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_4[5] 01_666 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_4[6] 00_667 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_4[7] 01_667 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_4[8] 00_668 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_4[9] 01_668 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_ENABLE[0] 00_646 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_ENABLE[1] 01_646 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_ENABLE[2] 00_647 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_ENABLE[3] 01_647 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_USE 01_645 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_LEN[0] 00_623 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_LEN[1] 01_623 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COMMON_SWING[0] 03_311 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_KEEP_IDLE 00_591 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_MAX_LAT[0] 00_557 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_MAX_LAT[1] 01_557 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_MAX_LAT[2] 00_558 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_MAX_LAT[3] 01_558 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_MAX_LAT[4] 00_559 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_MAX_LAT[5] 01_559 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_MIN_LAT[0] 00_565 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_MIN_LAT[1] 01_565 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_MIN_LAT[2] 00_566 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_MIN_LAT[3] 01_566 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_MIN_LAT[4] 00_567 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_MIN_LAT[5] 01_567 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_PRECEDENCE 00_590 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_REPEAT_WAIT[0] 00_573 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_REPEAT_WAIT[1] 01_573 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_REPEAT_WAIT[2] 00_574 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_REPEAT_WAIT[3] 01_574 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_REPEAT_WAIT[4] 00_575 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_1_1[0] 00_544 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_1_1[1] 01_544 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_1_1[2] 00_545 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_1_1[3] 01_545 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_1_1[4] 00_546 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_1_1[5] 01_546 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_1_1[6] 00_547 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_1_1[7] 01_547 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_1_1[8] 00_548 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_1_1[9] 01_548 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_1_2[0] 00_552 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_1_2[1] 01_552 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_1_2[2] 00_553 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_1_2[3] 01_553 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_1_2[4] 00_554 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_1_2[5] 01_554 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_1_2[6] 00_555 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_1_2[7] 01_555 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_1_2[8] 00_556 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_1_2[9] 01_556 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_1_3[0] 00_560 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_1_3[1] 01_560 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_1_3[2] 00_561 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_1_3[3] 01_561 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_1_3[4] 00_562 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_1_3[5] 01_562 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_1_3[6] 00_563 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_1_3[7] 01_563 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_1_3[8] 00_564 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_1_3[9] 01_564 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_1_4[0] 00_568 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_1_4[1] 01_568 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_1_4[2] 00_569 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_1_4[3] 01_569 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_1_4[4] 00_570 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_1_4[5] 01_570 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_1_4[6] 00_571 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_1_4[7] 01_571 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_1_4[8] 00_572 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_1_4[9] 01_572 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_1_ENABLE[0] 00_549 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_1_ENABLE[1] 01_549 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_1_ENABLE[2] 00_550 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_1_ENABLE[3] 01_550 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_2_1[0] 00_576 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_2_1[1] 01_576 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_2_1[2] 00_577 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_2_1[3] 01_577 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_2_1[4] 00_578 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_2_1[5] 01_578 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_2_1[6] 00_579 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_2_1[7] 01_579 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_2_1[8] 00_580 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_2_1[9] 01_580 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_2_2[0] 00_584 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_2_2[1] 01_584 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_2_2[2] 00_585 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_2_2[3] 01_585 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_2_2[4] 00_586 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_2_2[5] 01_586 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_2_2[6] 00_587 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_2_2[7] 01_587 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_2_2[8] 00_588 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_2_2[9] 01_588 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_2_3[0] 00_592 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_2_3[1] 01_592 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_2_3[2] 00_593 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_2_3[3] 01_593 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_2_3[4] 00_594 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_2_3[5] 01_594 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_2_3[6] 00_595 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_2_3[7] 01_595 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_2_3[8] 00_596 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_2_3[9] 01_596 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_2_4[0] 00_600 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_2_4[1] 01_600 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_2_4[2] 00_601 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_2_4[3] 01_601 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_2_4[4] 00_602 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_2_4[5] 01_602 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_2_4[6] 00_603 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_2_4[7] 01_603 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_2_4[8] 00_604 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_2_4[9] 01_604 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_2_ENABLE[0] 00_581 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_2_ENABLE[1] 01_581 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_2_ENABLE[2] 00_582 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_2_ENABLE[3] 01_582 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_2_USE 00_583 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_LEN[0] 00_589 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_LEN[1] 01_589 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_CORRECT_USE 00_551 -GTP_CHANNEL_3_MID_LEFT.GTPE2.DEC_MCOMMA_DETECT 01_494 -GTP_CHANNEL_3_MID_LEFT.GTPE2.DEC_PCOMMA_DETECT 00_495 -GTP_CHANNEL_3_MID_LEFT.GTPE2.DEC_VALID_COMMA_ONLY 00_494 -GTP_CHANNEL_3_MID_LEFT.GTPE2.DMONITOR_CFG[0] 02_368 -GTP_CHANNEL_3_MID_LEFT.GTPE2.DMONITOR_CFG[1] 03_368 -GTP_CHANNEL_3_MID_LEFT.GTPE2.DMONITOR_CFG[2] 02_369 -GTP_CHANNEL_3_MID_LEFT.GTPE2.DMONITOR_CFG[3] 03_369 -GTP_CHANNEL_3_MID_LEFT.GTPE2.DMONITOR_CFG[4] 02_370 -GTP_CHANNEL_3_MID_LEFT.GTPE2.DMONITOR_CFG[5] 03_370 -GTP_CHANNEL_3_MID_LEFT.GTPE2.DMONITOR_CFG[6] 02_371 -GTP_CHANNEL_3_MID_LEFT.GTPE2.DMONITOR_CFG[7] 03_371 -GTP_CHANNEL_3_MID_LEFT.GTPE2.DMONITOR_CFG[8] 02_372 -GTP_CHANNEL_3_MID_LEFT.GTPE2.DMONITOR_CFG[9] 03_372 -GTP_CHANNEL_3_MID_LEFT.GTPE2.DMONITOR_CFG[10] 02_373 -GTP_CHANNEL_3_MID_LEFT.GTPE2.DMONITOR_CFG[11] 03_373 -GTP_CHANNEL_3_MID_LEFT.GTPE2.DMONITOR_CFG[12] 02_374 -GTP_CHANNEL_3_MID_LEFT.GTPE2.DMONITOR_CFG[13] 03_374 -GTP_CHANNEL_3_MID_LEFT.GTPE2.DMONITOR_CFG[14] 02_375 -GTP_CHANNEL_3_MID_LEFT.GTPE2.DMONITOR_CFG[15] 03_375 -GTP_CHANNEL_3_MID_LEFT.GTPE2.DMONITOR_CFG[16] 02_376 -GTP_CHANNEL_3_MID_LEFT.GTPE2.DMONITOR_CFG[17] 03_376 -GTP_CHANNEL_3_MID_LEFT.GTPE2.DMONITOR_CFG[18] 02_377 -GTP_CHANNEL_3_MID_LEFT.GTPE2.DMONITOR_CFG[19] 03_377 -GTP_CHANNEL_3_MID_LEFT.GTPE2.DMONITOR_CFG[20] 02_378 -GTP_CHANNEL_3_MID_LEFT.GTPE2.DMONITOR_CFG[21] 03_378 -GTP_CHANNEL_3_MID_LEFT.GTPE2.DMONITOR_CFG[22] 02_379 -GTP_CHANNEL_3_MID_LEFT.GTPE2.DMONITOR_CFG[23] 03_379 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_CLK_PHASE_SEL[0] 03_463 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_CONTROL[0] 00_488 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_CONTROL[1] 01_488 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_CONTROL[2] 00_489 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_CONTROL[3] 01_489 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_CONTROL[4] 00_490 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_CONTROL[5] 01_490 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_ERRDET_EN 01_492 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_EYE_SCAN_EN 00_492 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_HORZ_OFFSET[0] 00_480 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_HORZ_OFFSET[1] 01_480 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_HORZ_OFFSET[2] 00_481 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_HORZ_OFFSET[3] 01_481 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_HORZ_OFFSET[4] 00_482 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_HORZ_OFFSET[5] 01_482 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_HORZ_OFFSET[6] 00_483 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_HORZ_OFFSET[7] 01_483 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_HORZ_OFFSET[8] 00_484 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_HORZ_OFFSET[9] 01_484 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_HORZ_OFFSET[10] 00_485 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_HORZ_OFFSET[11] 01_485 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_PMA_CFG[0] 02_624 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_PMA_CFG[1] 03_624 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_PMA_CFG[2] 02_625 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_PMA_CFG[3] 03_625 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_PMA_CFG[4] 02_626 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_PMA_CFG[5] 03_626 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_PMA_CFG[6] 02_627 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_PMA_CFG[7] 03_627 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_PMA_CFG[8] 02_628 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_PMA_CFG[9] 03_628 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_PRESCALE[0] 01_477 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_PRESCALE[1] 00_478 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_PRESCALE[2] 01_478 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_PRESCALE[3] 00_479 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_PRESCALE[4] 01_479 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[0] 00_392 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[1] 01_392 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[2] 00_393 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[3] 01_393 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[4] 00_394 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[5] 01_394 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[6] 00_395 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[7] 01_395 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[8] 00_396 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[9] 01_396 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[10] 00_397 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[11] 01_397 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[12] 00_398 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[13] 01_398 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[14] 00_399 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[15] 01_399 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[16] 00_400 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[17] 01_400 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[18] 00_401 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[19] 01_401 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[20] 00_402 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[21] 01_402 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[22] 00_403 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[23] 01_403 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[24] 00_404 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[25] 01_404 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[26] 00_405 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[27] 01_405 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[28] 00_406 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[29] 01_406 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[30] 00_407 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[31] 01_407 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[32] 00_408 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[33] 01_408 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[34] 00_409 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[35] 01_409 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[36] 00_410 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[37] 01_410 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[38] 00_411 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[39] 01_411 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[40] 00_412 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[41] 01_412 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[42] 00_413 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[43] 01_413 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[44] 00_414 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[45] 01_414 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[46] 00_415 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[47] 01_415 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[48] 00_416 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[49] 01_416 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[50] 00_417 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[51] 01_417 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[52] 00_418 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[53] 01_418 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[54] 00_419 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[55] 01_419 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[56] 00_420 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[57] 01_420 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[58] 00_421 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[59] 01_421 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[60] 00_422 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[61] 01_422 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[62] 00_423 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[63] 01_423 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[64] 00_424 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[65] 01_424 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[66] 00_425 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[67] 01_425 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[68] 00_426 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[69] 01_426 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[70] 00_427 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[71] 01_427 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[72] 00_428 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[73] 01_428 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[74] 00_429 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[75] 01_429 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[76] 00_430 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[77] 01_430 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[78] 00_431 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[79] 01_431 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[0] 00_352 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[1] 01_352 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[2] 00_353 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[3] 01_353 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[4] 00_354 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[5] 01_354 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[6] 00_355 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[7] 01_355 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[8] 00_356 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[9] 01_356 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[10] 00_357 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[11] 01_357 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[12] 00_358 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[13] 01_358 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[14] 00_359 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[15] 01_359 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[16] 00_360 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[17] 01_360 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[18] 00_361 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[19] 01_361 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[20] 00_362 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[21] 01_362 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[22] 00_363 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[23] 01_363 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[24] 00_364 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[25] 01_364 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[26] 00_365 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[27] 01_365 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[28] 00_366 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[29] 01_366 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[30] 00_367 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[31] 01_367 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[32] 00_368 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[33] 01_368 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[34] 00_369 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[35] 01_369 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[36] 00_370 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[37] 01_370 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[38] 00_371 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[39] 01_371 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[40] 00_372 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[41] 01_372 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[42] 00_373 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[43] 01_373 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[44] 00_374 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[45] 01_374 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[46] 00_375 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[47] 01_375 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[48] 00_376 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[49] 01_376 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[50] 00_377 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[51] 01_377 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[52] 00_378 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[53] 01_378 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[54] 00_379 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[55] 01_379 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[56] 00_380 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[57] 01_380 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[58] 00_381 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[59] 01_381 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[60] 00_382 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[61] 01_382 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[62] 00_383 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[63] 01_383 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[64] 00_384 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[65] 01_384 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[66] 00_385 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[67] 01_385 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[68] 00_386 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[69] 01_386 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[70] 00_387 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[71] 01_387 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[72] 00_388 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[73] 01_388 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[74] 00_389 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[75] 01_389 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[76] 00_390 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[77] 01_390 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[78] 00_391 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[79] 01_391 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[0] 00_432 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[1] 01_432 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[2] 00_433 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[3] 01_433 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[4] 00_434 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[5] 01_434 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[6] 00_435 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[7] 01_435 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[8] 00_436 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[9] 01_436 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[10] 00_437 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[11] 01_437 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[12] 00_438 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[13] 01_438 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[14] 00_439 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[15] 01_439 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[16] 00_440 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[17] 01_440 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[18] 00_441 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[19] 01_441 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[20] 00_442 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[21] 01_442 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[22] 00_443 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[23] 01_443 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[24] 00_444 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[25] 01_444 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[26] 00_445 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[27] 01_445 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[28] 00_446 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[29] 01_446 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[30] 00_447 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[31] 01_447 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[32] 00_448 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[33] 01_448 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[34] 00_449 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[35] 01_449 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[36] 00_450 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[37] 01_450 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[38] 00_451 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[39] 01_451 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[40] 00_452 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[41] 01_452 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[42] 00_453 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[43] 01_453 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[44] 00_454 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[45] 01_454 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[46] 00_455 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[47] 01_455 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[48] 00_456 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[49] 01_456 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[50] 00_457 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[51] 01_457 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[52] 00_458 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[53] 01_458 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[54] 00_459 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[55] 01_459 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[56] 00_460 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[57] 01_460 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[58] 00_461 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[59] 01_461 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[60] 00_462 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[61] 01_462 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[62] 00_463 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[63] 01_463 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[64] 00_464 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[65] 01_464 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[66] 00_465 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[67] 01_465 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[68] 00_466 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[69] 01_466 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[70] 00_467 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[71] 01_467 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[72] 00_468 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[73] 01_468 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[74] 00_469 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[75] 01_469 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[76] 00_470 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[77] 01_470 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[78] 00_471 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[79] 01_471 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_VERT_OFFSET[0] 00_472 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_VERT_OFFSET[1] 01_472 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_VERT_OFFSET[2] 00_473 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_VERT_OFFSET[3] 01_473 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_VERT_OFFSET[4] 00_474 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_VERT_OFFSET[5] 01_474 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_VERT_OFFSET[6] 00_475 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_VERT_OFFSET[7] 01_475 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_VERT_OFFSET[8] 00_476 -GTP_CHANNEL_3_MID_LEFT.GTPE2.FTS_DESKEW_SEQ_ENABLE[0] 00_662 -GTP_CHANNEL_3_MID_LEFT.GTPE2.FTS_DESKEW_SEQ_ENABLE[1] 01_662 -GTP_CHANNEL_3_MID_LEFT.GTPE2.FTS_DESKEW_SEQ_ENABLE[2] 00_663 -GTP_CHANNEL_3_MID_LEFT.GTPE2.FTS_DESKEW_SEQ_ENABLE[3] 01_663 -GTP_CHANNEL_3_MID_LEFT.GTPE2.FTS_LANE_DESKEW_CFG[0] 00_654 -GTP_CHANNEL_3_MID_LEFT.GTPE2.FTS_LANE_DESKEW_CFG[1] 01_654 -GTP_CHANNEL_3_MID_LEFT.GTPE2.FTS_LANE_DESKEW_CFG[2] 00_655 -GTP_CHANNEL_3_MID_LEFT.GTPE2.FTS_LANE_DESKEW_CFG[3] 01_655 -GTP_CHANNEL_3_MID_LEFT.GTPE2.FTS_LANE_DESKEW_EN 01_653 -GTP_CHANNEL_3_MID_LEFT.GTPE2.GEARBOX_MODE[0] 00_224 -GTP_CHANNEL_3_MID_LEFT.GTPE2.GEARBOX_MODE[1] 01_224 -GTP_CHANNEL_3_MID_LEFT.GTPE2.GEARBOX_MODE[2] 00_225 -GTP_CHANNEL_3_MID_LEFT.GTPE2.IN_USE 00_00 00_01 00_47 00_52 00_53 00_65 01_01 01_47 02_129 -GTP_CHANNEL_3_MID_LEFT.GTPE2.LOOPBACK_CFG[0] 02_20 -GTP_CHANNEL_3_MID_LEFT.GTPE2.OUTREFCLK_SEL_INV[0] 00_149 -GTP_CHANNEL_3_MID_LEFT.GTPE2.OUTREFCLK_SEL_INV[1] 01_149 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PCS_PCIE_EN 00_216 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PCS_RSVD_ATTR[0] 02_184 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PCS_RSVD_ATTR[1] 03_184 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PCS_RSVD_ATTR[2] 02_185 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PCS_RSVD_ATTR[3] 03_185 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PCS_RSVD_ATTR[4] 02_186 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PCS_RSVD_ATTR[5] 03_186 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PCS_RSVD_ATTR[6] 02_187 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PCS_RSVD_ATTR[7] 03_187 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PCS_RSVD_ATTR[8] 02_188 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PCS_RSVD_ATTR[9] 03_188 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PCS_RSVD_ATTR[10] 02_189 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PCS_RSVD_ATTR[11] 03_189 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PCS_RSVD_ATTR[12] 02_190 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PCS_RSVD_ATTR[13] 03_190 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PCS_RSVD_ATTR[14] 02_191 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PCS_RSVD_ATTR[15] 03_191 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PCS_RSVD_ATTR[16] 02_192 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PCS_RSVD_ATTR[17] 03_192 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PCS_RSVD_ATTR[18] 02_193 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PCS_RSVD_ATTR[19] 03_193 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PCS_RSVD_ATTR[20] 02_194 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PCS_RSVD_ATTR[21] 03_194 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PCS_RSVD_ATTR[22] 02_195 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PCS_RSVD_ATTR[23] 03_195 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PCS_RSVD_ATTR[24] 02_196 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PCS_RSVD_ATTR[25] 03_196 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PCS_RSVD_ATTR[26] 02_197 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PCS_RSVD_ATTR[27] 03_197 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PCS_RSVD_ATTR[28] 02_198 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PCS_RSVD_ATTR[29] 03_198 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PCS_RSVD_ATTR[30] 02_199 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PCS_RSVD_ATTR[31] 03_199 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PCS_RSVD_ATTR[32] 02_200 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PCS_RSVD_ATTR[33] 03_200 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PCS_RSVD_ATTR[34] 02_201 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PCS_RSVD_ATTR[35] 03_201 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PCS_RSVD_ATTR[36] 02_202 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PCS_RSVD_ATTR[37] 03_202 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PCS_RSVD_ATTR[38] 02_203 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PCS_RSVD_ATTR[39] 03_203 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PCS_RSVD_ATTR[40] 02_204 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PCS_RSVD_ATTR[41] 03_204 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PCS_RSVD_ATTR[42] 02_205 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PCS_RSVD_ATTR[43] 03_205 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PCS_RSVD_ATTR[44] 02_206 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PCS_RSVD_ATTR[45] 03_206 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PCS_RSVD_ATTR[46] 02_207 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PCS_RSVD_ATTR[47] 03_207 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PD_TRANS_TIME_FROM_P2[0] 01_216 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PD_TRANS_TIME_FROM_P2[1] 00_217 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PD_TRANS_TIME_FROM_P2[2] 01_217 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PD_TRANS_TIME_FROM_P2[3] 00_218 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PD_TRANS_TIME_FROM_P2[4] 01_218 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PD_TRANS_TIME_FROM_P2[5] 00_219 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PD_TRANS_TIME_FROM_P2[6] 01_219 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PD_TRANS_TIME_FROM_P2[7] 00_220 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PD_TRANS_TIME_FROM_P2[8] 01_220 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PD_TRANS_TIME_FROM_P2[9] 00_221 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PD_TRANS_TIME_FROM_P2[10] 01_221 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PD_TRANS_TIME_FROM_P2[11] 00_222 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PD_TRANS_TIME_NONE_P2[0] 00_208 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PD_TRANS_TIME_NONE_P2[1] 01_208 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PD_TRANS_TIME_NONE_P2[2] 00_209 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PD_TRANS_TIME_NONE_P2[3] 01_209 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PD_TRANS_TIME_NONE_P2[4] 00_210 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PD_TRANS_TIME_NONE_P2[5] 01_210 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PD_TRANS_TIME_NONE_P2[6] 00_211 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PD_TRANS_TIME_NONE_P2[7] 01_211 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PD_TRANS_TIME_TO_P2[0] 00_212 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PD_TRANS_TIME_TO_P2[1] 01_212 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PD_TRANS_TIME_TO_P2[2] 00_213 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PD_TRANS_TIME_TO_P2[3] 01_213 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PD_TRANS_TIME_TO_P2[4] 00_214 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PD_TRANS_TIME_TO_P2[5] 01_214 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PD_TRANS_TIME_TO_P2[6] 00_215 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PD_TRANS_TIME_TO_P2[7] 01_215 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PMA_LOOPBACK_CFG[0] 01_207 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PMA_RSV[0] 02_520 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PMA_RSV[1] 03_520 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PMA_RSV[2] 02_521 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PMA_RSV[3] 03_521 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PMA_RSV[4] 02_522 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PMA_RSV[5] 03_522 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PMA_RSV[6] 02_523 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PMA_RSV[7] 03_523 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PMA_RSV[8] 02_524 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PMA_RSV[9] 03_524 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PMA_RSV[10] 02_525 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PMA_RSV[11] 03_525 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PMA_RSV[12] 02_526 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PMA_RSV[13] 03_526 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PMA_RSV[14] 02_527 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PMA_RSV[15] 03_527 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PMA_RSV[16] 02_528 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PMA_RSV[17] 03_528 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PMA_RSV[18] 02_529 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PMA_RSV[19] 03_529 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PMA_RSV[20] 02_530 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PMA_RSV[21] 03_530 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PMA_RSV[22] 02_531 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PMA_RSV[23] 03_531 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PMA_RSV[24] 02_532 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PMA_RSV[25] 03_532 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PMA_RSV[26] 02_533 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PMA_RSV[27] 03_533 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PMA_RSV[28] 02_534 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PMA_RSV[29] 03_534 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PMA_RSV[30] 02_535 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PMA_RSV[31] 03_535 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PMA_RSV2[0] 02_336 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PMA_RSV2[1] 03_336 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PMA_RSV2[2] 02_337 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PMA_RSV2[3] 03_337 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PMA_RSV2[4] 02_338 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PMA_RSV2[5] 03_338 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PMA_RSV2[6] 02_339 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PMA_RSV2[7] 03_339 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PMA_RSV2[8] 02_340 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PMA_RSV2[9] 03_340 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PMA_RSV2[10] 02_341 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PMA_RSV2[11] 03_341 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PMA_RSV2[12] 02_342 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PMA_RSV2[13] 03_342 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PMA_RSV2[14] 02_343 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PMA_RSV2[15] 03_343 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PMA_RSV2[16] 02_344 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PMA_RSV2[17] 03_344 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PMA_RSV2[18] 02_345 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PMA_RSV2[19] 03_345 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PMA_RSV2[20] 02_346 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PMA_RSV2[21] 03_346 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PMA_RSV2[22] 02_347 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PMA_RSV2[23] 03_347 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PMA_RSV2[24] 02_348 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PMA_RSV2[25] 03_348 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PMA_RSV2[26] 02_349 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PMA_RSV2[27] 03_349 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PMA_RSV2[28] 02_350 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PMA_RSV2[29] 03_350 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PMA_RSV2[30] 02_351 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PMA_RSV2[31] 03_351 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PMA_RSV3[0] 02_288 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PMA_RSV3[1] 03_288 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PMA_RSV4[0] 02_156 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PMA_RSV4[1] 03_156 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PMA_RSV4[2] 02_157 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PMA_RSV4[3] 03_157 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PMA_RSV5[0] 03_159 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PMA_RSV6[0] 02_303 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PMA_RSV7[0] 03_303 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_BIAS_CFG[0] 02_112 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_BIAS_CFG[1] 03_112 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_BIAS_CFG[2] 02_113 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_BIAS_CFG[3] 03_113 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_BIAS_CFG[4] 02_114 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_BIAS_CFG[5] 03_114 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_BIAS_CFG[6] 02_115 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_BIAS_CFG[7] 03_115 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_BIAS_CFG[8] 02_116 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_BIAS_CFG[9] 03_116 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_BIAS_CFG[10] 02_117 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_BIAS_CFG[11] 03_117 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_BIAS_CFG[12] 02_118 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_BIAS_CFG[13] 03_118 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_BIAS_CFG[14] 02_119 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_BIAS_CFG[15] 03_119 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_BUFFER_CFG[0] 02_536 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_BUFFER_CFG[1] 03_536 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_BUFFER_CFG[2] 02_537 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_BUFFER_CFG[3] 03_537 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_BUFFER_CFG[4] 02_538 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_BUFFER_CFG[5] 03_538 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_CLKMUX_EN[0] 02_128 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_CM_SEL[0] 00_138 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_CM_SEL[1] 01_138 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_CM_TRIM[0] 02_304 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_CM_TRIM[1] 03_304 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_CM_TRIM[2] 02_305 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_CM_TRIM[3] 03_305 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_DATA_WIDTH[0] 01_141 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_DATA_WIDTH[1] 00_142 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_DATA_WIDTH[2] 01_142 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_DDI_SEL[0] 00_696 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_DDI_SEL[1] 01_696 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_DDI_SEL[2] 00_697 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_DDI_SEL[3] 01_697 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_DDI_SEL[4] 00_698 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_DDI_SEL[5] 01_698 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_DEBUG_CFG[0] 02_616 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_DEBUG_CFG[1] 03_616 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_DEBUG_CFG[2] 02_617 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_DEBUG_CFG[3] 03_617 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_DEBUG_CFG[4] 02_618 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_DEBUG_CFG[5] 03_618 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_DEBUG_CFG[6] 02_619 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_DEBUG_CFG[7] 03_619 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_DEBUG_CFG[8] 02_620 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_DEBUG_CFG[9] 03_620 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_DEBUG_CFG[10] 02_621 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_DEBUG_CFG[11] 03_621 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_DEBUG_CFG[12] 02_622 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_DEBUG_CFG[13] 03_622 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_DEFER_RESET_BUF_EN 02_552 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_DISPERR_SEQ_MATCH 01_495 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_OS_CFG[0] 00_288 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_OS_CFG[1] 01_288 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_OS_CFG[2] 00_289 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_OS_CFG[3] 01_289 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_OS_CFG[4] 00_290 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_OS_CFG[5] 01_290 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_OS_CFG[6] 00_291 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_OS_CFG[7] 01_291 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_OS_CFG[8] 00_292 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_OS_CFG[9] 01_292 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_OS_CFG[10] 00_293 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_OS_CFG[11] 01_293 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_OS_CFG[12] 00_294 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_SIG_VALID_DLY[0] 00_524 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_SIG_VALID_DLY[1] 01_524 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_SIG_VALID_DLY[2] 00_525 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_SIG_VALID_DLY[3] 01_525 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_SIG_VALID_DLY[4] 00_526 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_XCLK_SEL.RXUSR 00_143 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_CLK25_DIV[0] 00_139 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_CLK25_DIV[1] 01_139 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_CLK25_DIV[2] 00_140 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_CLK25_DIV[3] 01_140 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_CLK25_DIV[4] 00_141 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXBUF_ADDR_MODE.FAST 03_555 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXBUF_EIDLE_HI_CNT[0] 02_558 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXBUF_EIDLE_HI_CNT[1] 03_558 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXBUF_EIDLE_HI_CNT[2] 02_559 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXBUF_EIDLE_HI_CNT[3] 03_559 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXBUF_EIDLE_LO_CNT[0] 02_556 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXBUF_EIDLE_LO_CNT[1] 03_556 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXBUF_EIDLE_LO_CNT[2] 02_557 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXBUF_EIDLE_LO_CNT[3] 03_557 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXBUF_EN 02_11 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXBUF_RESET_ON_CB_CHANGE 02_560 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXBUF_RESET_ON_COMMAALIGN 02_561 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXBUF_RESET_ON_EIDLE 02_547 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXBUF_RESET_ON_RATE_CHANGE 03_560 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXBUF_THRESH_OVFLW[0] 03_552 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXBUF_THRESH_OVFLW[1] 02_553 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXBUF_THRESH_OVFLW[2] 03_553 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXBUF_THRESH_OVFLW[3] 02_554 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXBUF_THRESH_OVFLW[4] 03_554 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXBUF_THRESH_OVFLW[5] 02_555 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXBUF_THRESH_OVRD 02_548 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXBUF_THRESH_UNDFLW[0] 02_544 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXBUF_THRESH_UNDFLW[1] 03_544 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXBUF_THRESH_UNDFLW[2] 02_545 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXBUF_THRESH_UNDFLW[3] 03_545 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXBUF_THRESH_UNDFLW[4] 02_546 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXBUF_THRESH_UNDFLW[5] 03_546 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXBUFRESET_TIME[0] 01_101 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXBUFRESET_TIME[1] 00_102 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXBUFRESET_TIME[2] 01_102 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXBUFRESET_TIME[3] 00_103 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXBUFRESET_TIME[4] 01_103 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[0] 02_640 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[1] 03_640 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[2] 02_641 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[3] 03_641 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[4] 02_642 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[5] 03_642 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[6] 02_643 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[7] 03_643 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[8] 02_644 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[9] 03_644 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[10] 02_645 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[11] 03_645 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[12] 02_646 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[13] 03_646 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[14] 02_647 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[15] 03_647 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[16] 02_648 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[17] 03_648 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[18] 02_649 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[19] 03_649 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[20] 02_650 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[21] 03_650 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[22] 02_651 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[23] 03_651 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[24] 02_652 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[25] 03_652 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[26] 02_653 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[27] 03_653 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[28] 02_654 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[29] 03_654 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[30] 02_655 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[31] 03_655 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[32] 02_656 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[33] 03_656 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[34] 02_657 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[35] 03_657 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[36] 02_658 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[37] 03_658 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[38] 02_659 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[39] 03_659 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[40] 02_660 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[41] 03_660 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[42] 02_661 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[43] 03_661 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[44] 02_662 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[45] 03_662 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[46] 02_663 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[47] 03_663 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[48] 02_664 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[49] 03_664 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[50] 02_665 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[51] 03_665 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[52] 02_666 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[53] 03_666 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[54] 02_667 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[55] 03_667 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[56] 02_668 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[57] 03_668 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[58] 02_669 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[59] 03_669 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[60] 02_670 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[61] 03_670 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[62] 02_671 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[63] 03_671 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[64] 02_672 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[65] 03_672 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[66] 02_673 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[67] 03_673 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[68] 02_674 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[69] 03_674 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[70] 02_675 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[71] 03_675 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[72] 02_676 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[73] 03_676 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[74] 02_677 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[75] 03_677 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[76] 02_678 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[77] 03_678 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[78] 02_679 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[79] 03_679 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[80] 02_680 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[81] 03_680 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[82] 02_681 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_FR_RESET_ON_EIDLE[0] 02_638 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_HOLD_DURING_EIDLE[0] 03_637 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_LOCK_CFG[0] 02_632 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_LOCK_CFG[1] 03_632 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_LOCK_CFG[2] 02_633 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_LOCK_CFG[3] 03_633 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_LOCK_CFG[4] 02_634 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_LOCK_CFG[5] 03_634 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_PH_RESET_ON_EIDLE[0] 03_638 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDRFREQRESET_TIME[0] 01_106 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDRFREQRESET_TIME[1] 00_107 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDRFREQRESET_TIME[2] 01_107 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDRFREQRESET_TIME[3] 00_108 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDRFREQRESET_TIME[4] 01_108 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDRPHRESET_TIME[0] 00_109 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDRPHRESET_TIME[1] 01_109 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDRPHRESET_TIME[2] 00_110 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDRPHRESET_TIME[3] 01_110 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDRPHRESET_TIME[4] 00_111 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXDLY_CFG[0] 00_680 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXDLY_CFG[1] 01_680 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXDLY_CFG[2] 00_681 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXDLY_CFG[3] 01_681 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXDLY_CFG[4] 00_682 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXDLY_CFG[5] 01_682 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXDLY_CFG[6] 00_683 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXDLY_CFG[7] 01_683 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXDLY_CFG[8] 00_684 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXDLY_CFG[9] 01_684 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXDLY_CFG[10] 00_685 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXDLY_CFG[11] 01_685 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXDLY_CFG[12] 00_686 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXDLY_CFG[13] 01_686 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXDLY_CFG[14] 00_687 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXDLY_CFG[15] 01_687 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXDLY_LCFG[0] 02_576 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXDLY_LCFG[1] 03_576 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXDLY_LCFG[2] 02_577 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXDLY_LCFG[3] 03_577 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXDLY_LCFG[4] 02_578 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXDLY_LCFG[5] 03_578 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXDLY_LCFG[6] 02_579 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXDLY_LCFG[7] 03_579 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXDLY_LCFG[8] 02_580 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXDLY_TAP_CFG[0] 00_672 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXDLY_TAP_CFG[1] 01_672 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXDLY_TAP_CFG[2] 00_673 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXDLY_TAP_CFG[3] 01_673 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXDLY_TAP_CFG[4] 00_674 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXDLY_TAP_CFG[5] 01_674 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXDLY_TAP_CFG[6] 00_675 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXDLY_TAP_CFG[7] 01_675 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXDLY_TAP_CFG[8] 00_676 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXDLY_TAP_CFG[9] 01_676 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXDLY_TAP_CFG[10] 00_677 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXDLY_TAP_CFG[11] 01_677 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXDLY_TAP_CFG[12] 00_678 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXDLY_TAP_CFG[13] 01_678 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXDLY_TAP_CFG[14] 00_679 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXDLY_TAP_CFG[15] 01_679 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXGEARBOX_EN 01_607 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXISCANRESET_TIME[0] 01_123 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXISCANRESET_TIME[1] 00_124 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXISCANRESET_TIME[2] 01_124 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXISCANRESET_TIME[3] 00_125 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXISCANRESET_TIME[4] 01_125 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPM_BIAS_STARTUP_DISABLE[0] 03_391 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPM_CFG[0] 02_328 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPM_CFG[1] 03_328 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPM_CFG[2] 02_329 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPM_CFG[3] 03_329 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPM_CM_CFG[0] 02_430 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPM_GC_CFG[0] 02_432 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPM_GC_CFG[1] 03_432 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPM_GC_CFG[2] 02_433 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPM_GC_CFG[3] 03_433 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPM_GC_CFG[4] 02_434 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPM_GC_CFG[5] 03_434 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPM_GC_CFG[6] 02_435 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPM_GC_CFG[7] 03_435 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPM_GC_CFG[8] 02_436 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPM_GC_CFG2[0] 03_442 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPM_GC_CFG2[1] 02_443 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPM_GC_CFG2[2] 03_443 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPM_HF_CFG[0] 00_336 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPM_HF_CFG[1] 01_336 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPM_HF_CFG[2] 00_337 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPM_HF_CFG[3] 01_337 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPM_HF_CFG[4] 00_338 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPM_HF_CFG[5] 01_338 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPM_HF_CFG[6] 00_339 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPM_HF_CFG[7] 01_339 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPM_HF_CFG[8] 00_340 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPM_HF_CFG[9] 01_340 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPM_HF_CFG[10] 00_341 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPM_HF_CFG[11] 01_341 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPM_HF_CFG[12] 00_342 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPM_HF_CFG[13] 01_342 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPM_HF_CFG2[0] 02_424 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPM_HF_CFG2[1] 03_424 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPM_HF_CFG2[2] 02_425 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPM_HF_CFG2[3] 03_425 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPM_HF_CFG2[4] 02_426 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPM_HF_CFG3[0] 03_389 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPM_HF_CFG3[1] 02_390 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPM_HF_CFG3[2] 03_390 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPM_HF_CFG3[3] 02_391 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPM_HOLD_DURING_EIDLE[0] 00_247 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPM_INCM_CFG[0] 02_439 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPM_IPCM_CFG[0] 03_439 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPM_LF_CFG[0] 00_344 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPM_LF_CFG[1] 01_344 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPM_LF_CFG[2] 00_345 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPM_LF_CFG[3] 01_345 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPM_LF_CFG[4] 00_346 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPM_LF_CFG[5] 01_346 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPM_LF_CFG[6] 00_347 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPM_LF_CFG[7] 01_347 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPM_LF_CFG[8] 00_348 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPM_LF_CFG[9] 01_348 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPM_LF_CFG[10] 00_349 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPM_LF_CFG[11] 01_349 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPM_LF_CFG[12] 00_350 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPM_LF_CFG[13] 01_350 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPM_LF_CFG[14] 00_351 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPM_LF_CFG[15] 01_351 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPM_LF_CFG[16] 00_343 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPM_LF_CFG[17] 01_343 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPM_LF_CFG2[0] 03_426 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPM_LF_CFG2[1] 02_427 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPM_LF_CFG2[2] 03_427 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPM_LF_CFG2[3] 02_428 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPM_LF_CFG2[4] 03_428 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPM_OSINT_CFG[0] 02_440 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPM_OSINT_CFG[1] 03_440 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPM_OSINT_CFG[2] 02_441 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPM_CFG1[0] 02_330 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPMRESET_TIME[0] 00_112 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPMRESET_TIME[1] 01_112 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPMRESET_TIME[2] 00_113 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPMRESET_TIME[3] 01_113 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPMRESET_TIME[4] 00_114 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPMRESET_TIME[5] 01_114 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPMRESET_TIME[6] 00_115 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXOOB_CFG[0] 00_144 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXOOB_CFG[1] 01_144 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXOOB_CFG[2] 00_145 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXOOB_CFG[3] 01_145 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXOOB_CFG[4] 00_146 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXOOB_CFG[5] 01_146 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXOOB_CFG[6] 00_147 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXOOB_CLK_CFG.FABRIC 03_129 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXOSCALRESET_TIME[0] 00_187 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXOSCALRESET_TIME[1] 01_187 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXOSCALRESET_TIME[2] 00_188 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXOSCALRESET_TIME[3] 01_188 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXOSCALRESET_TIME[4] 00_189 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXOSCALRESET_TIMEOUT[0] 01_189 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXOSCALRESET_TIMEOUT[1] 00_190 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXOSCALRESET_TIMEOUT[2] 01_190 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXOSCALRESET_TIMEOUT[3] 00_191 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXOSCALRESET_TIMEOUT[4] 01_191 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXOUT_DIV[0] 02_384 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXOUT_DIV[1] 03_384 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXPCSRESET_TIME[0] 01_115 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXPCSRESET_TIME[1] 00_116 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXPCSRESET_TIME[2] 01_116 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXPCSRESET_TIME[3] 00_117 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXPCSRESET_TIME[4] 01_117 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXPH_CFG[0] 02_584 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXPH_CFG[1] 03_584 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXPH_CFG[2] 02_585 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXPH_CFG[3] 03_585 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXPH_CFG[4] 02_586 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXPH_CFG[5] 03_586 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXPH_CFG[6] 02_587 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXPH_CFG[7] 03_587 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXPH_CFG[8] 02_588 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXPH_CFG[9] 03_588 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXPH_CFG[10] 02_589 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXPH_CFG[11] 03_589 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXPH_CFG[12] 02_590 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXPH_CFG[13] 03_590 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXPH_CFG[14] 02_591 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXPH_CFG[15] 03_591 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXPH_CFG[16] 02_592 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXPH_CFG[17] 03_592 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXPH_CFG[18] 02_593 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXPH_CFG[19] 03_593 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXPH_CFG[20] 02_594 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXPH_CFG[21] 03_594 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXPH_CFG[22] 02_595 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXPH_CFG[23] 03_595 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXPH_MONITOR_SEL[0] 00_700 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXPH_MONITOR_SEL[1] 01_700 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXPH_MONITOR_SEL[2] 00_701 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXPH_MONITOR_SEL[3] 01_701 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXPH_MONITOR_SEL[4] 00_702 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXPHDLY_CFG[0] 02_600 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXPHDLY_CFG[1] 03_600 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXPHDLY_CFG[2] 02_601 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXPHDLY_CFG[3] 03_601 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXPHDLY_CFG[4] 02_602 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXPHDLY_CFG[5] 03_602 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXPHDLY_CFG[6] 02_603 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXPHDLY_CFG[7] 03_603 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXPHDLY_CFG[8] 02_604 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXPHDLY_CFG[9] 03_604 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXPHDLY_CFG[10] 02_605 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXPHDLY_CFG[11] 03_605 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXPHDLY_CFG[12] 02_606 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXPHDLY_CFG[13] 03_606 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXPHDLY_CFG[14] 02_607 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXPHDLY_CFG[15] 03_607 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXPHDLY_CFG[16] 02_608 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXPHDLY_CFG[17] 03_608 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXPHDLY_CFG[18] 02_609 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXPHDLY_CFG[19] 03_609 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXPHDLY_CFG[20] 02_610 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXPHDLY_CFG[21] 03_610 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXPHDLY_CFG[22] 02_611 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXPHDLY_CFG[23] 03_611 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXPI_CFG0[0] 03_430 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXPI_CFG0[1] 02_431 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXPI_CFG0[2] 03_431 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXPI_CFG1[0] 02_442 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXPI_CFG2[0] 03_441 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXPMARESET_TIME[0] 00_104 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXPMARESET_TIME[1] 01_104 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXPMARESET_TIME[2] 00_105 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXPMARESET_TIME[3] 01_105 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXPMARESET_TIME[4] 00_106 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXPRBS_ERR_LOOPBACK[0] 00_136 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXSLIDE_AUTO_WAIT[0] 00_520 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXSLIDE_AUTO_WAIT[1] 01_520 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXSLIDE_AUTO_WAIT[2] 00_521 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXSLIDE_AUTO_WAIT[3] 01_521 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXSLIDE_MODE.AUTO 00_519 !01_519 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXSLIDE_MODE.PCS !00_519 01_519 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXSLIDE_MODE.PMA 00_519 01_519 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXSYNC_MULTILANE[0] 00_133 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXSYNC_OVRD[0] 01_135 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXSYNC_SKIP_DA[0] 01_134 -GTP_CHANNEL_3_MID_LEFT.GTPE2.SAS_MAX_COM[0] 00_171 -GTP_CHANNEL_3_MID_LEFT.GTPE2.SAS_MAX_COM[1] 01_171 -GTP_CHANNEL_3_MID_LEFT.GTPE2.SAS_MAX_COM[2] 00_172 -GTP_CHANNEL_3_MID_LEFT.GTPE2.SAS_MAX_COM[3] 01_172 -GTP_CHANNEL_3_MID_LEFT.GTPE2.SAS_MAX_COM[4] 00_173 -GTP_CHANNEL_3_MID_LEFT.GTPE2.SAS_MAX_COM[5] 01_173 -GTP_CHANNEL_3_MID_LEFT.GTPE2.SAS_MAX_COM[6] 00_174 -GTP_CHANNEL_3_MID_LEFT.GTPE2.SAS_MIN_COM[0] 01_156 -GTP_CHANNEL_3_MID_LEFT.GTPE2.SAS_MIN_COM[1] 00_157 -GTP_CHANNEL_3_MID_LEFT.GTPE2.SAS_MIN_COM[2] 01_157 -GTP_CHANNEL_3_MID_LEFT.GTPE2.SAS_MIN_COM[3] 00_158 -GTP_CHANNEL_3_MID_LEFT.GTPE2.SAS_MIN_COM[4] 01_158 -GTP_CHANNEL_3_MID_LEFT.GTPE2.SAS_MIN_COM[5] 00_159 -GTP_CHANNEL_3_MID_LEFT.GTPE2.SATA_BURST_SEQ_LEN[0] 00_150 -GTP_CHANNEL_3_MID_LEFT.GTPE2.SATA_BURST_SEQ_LEN[1] 01_150 -GTP_CHANNEL_3_MID_LEFT.GTPE2.SATA_BURST_SEQ_LEN[2] 00_151 -GTP_CHANNEL_3_MID_LEFT.GTPE2.SATA_BURST_SEQ_LEN[3] 01_151 -GTP_CHANNEL_3_MID_LEFT.GTPE2.SATA_BURST_VAL[0] 01_147 -GTP_CHANNEL_3_MID_LEFT.GTPE2.SATA_BURST_VAL[1] 00_148 -GTP_CHANNEL_3_MID_LEFT.GTPE2.SATA_BURST_VAL[2] 01_148 -GTP_CHANNEL_3_MID_LEFT.GTPE2.SATA_EIDLE_VAL[0] 00_152 -GTP_CHANNEL_3_MID_LEFT.GTPE2.SATA_EIDLE_VAL[1] 01_152 -GTP_CHANNEL_3_MID_LEFT.GTPE2.SATA_EIDLE_VAL[2] 00_153 -GTP_CHANNEL_3_MID_LEFT.GTPE2.SATA_MAX_BURST[0] 00_168 -GTP_CHANNEL_3_MID_LEFT.GTPE2.SATA_MAX_BURST[1] 01_168 -GTP_CHANNEL_3_MID_LEFT.GTPE2.SATA_MAX_BURST[2] 00_169 -GTP_CHANNEL_3_MID_LEFT.GTPE2.SATA_MAX_BURST[3] 01_169 -GTP_CHANNEL_3_MID_LEFT.GTPE2.SATA_MAX_BURST[4] 00_170 -GTP_CHANNEL_3_MID_LEFT.GTPE2.SATA_MAX_BURST[5] 01_170 -GTP_CHANNEL_3_MID_LEFT.GTPE2.SATA_MAX_INIT[0] 00_176 -GTP_CHANNEL_3_MID_LEFT.GTPE2.SATA_MAX_INIT[1] 01_176 -GTP_CHANNEL_3_MID_LEFT.GTPE2.SATA_MAX_INIT[2] 00_177 -GTP_CHANNEL_3_MID_LEFT.GTPE2.SATA_MAX_INIT[3] 01_177 -GTP_CHANNEL_3_MID_LEFT.GTPE2.SATA_MAX_INIT[4] 00_178 -GTP_CHANNEL_3_MID_LEFT.GTPE2.SATA_MAX_INIT[5] 01_178 -GTP_CHANNEL_3_MID_LEFT.GTPE2.SATA_MAX_WAKE[0] 00_179 -GTP_CHANNEL_3_MID_LEFT.GTPE2.SATA_MAX_WAKE[1] 01_179 -GTP_CHANNEL_3_MID_LEFT.GTPE2.SATA_MAX_WAKE[2] 00_180 -GTP_CHANNEL_3_MID_LEFT.GTPE2.SATA_MAX_WAKE[3] 01_180 -GTP_CHANNEL_3_MID_LEFT.GTPE2.SATA_MAX_WAKE[4] 00_181 -GTP_CHANNEL_3_MID_LEFT.GTPE2.SATA_MAX_WAKE[5] 01_181 -GTP_CHANNEL_3_MID_LEFT.GTPE2.SATA_MIN_BURST[0] 01_153 -GTP_CHANNEL_3_MID_LEFT.GTPE2.SATA_MIN_BURST[1] 00_154 -GTP_CHANNEL_3_MID_LEFT.GTPE2.SATA_MIN_BURST[2] 01_154 -GTP_CHANNEL_3_MID_LEFT.GTPE2.SATA_MIN_BURST[3] 00_155 -GTP_CHANNEL_3_MID_LEFT.GTPE2.SATA_MIN_BURST[4] 01_155 -GTP_CHANNEL_3_MID_LEFT.GTPE2.SATA_MIN_BURST[5] 00_156 -GTP_CHANNEL_3_MID_LEFT.GTPE2.SATA_MIN_INIT[0] 00_160 -GTP_CHANNEL_3_MID_LEFT.GTPE2.SATA_MIN_INIT[1] 01_160 -GTP_CHANNEL_3_MID_LEFT.GTPE2.SATA_MIN_INIT[2] 00_161 -GTP_CHANNEL_3_MID_LEFT.GTPE2.SATA_MIN_INIT[3] 01_161 -GTP_CHANNEL_3_MID_LEFT.GTPE2.SATA_MIN_INIT[4] 00_162 -GTP_CHANNEL_3_MID_LEFT.GTPE2.SATA_MIN_INIT[5] 01_162 -GTP_CHANNEL_3_MID_LEFT.GTPE2.SATA_MIN_WAKE[0] 00_163 -GTP_CHANNEL_3_MID_LEFT.GTPE2.SATA_MIN_WAKE[1] 01_163 -GTP_CHANNEL_3_MID_LEFT.GTPE2.SATA_MIN_WAKE[2] 00_164 -GTP_CHANNEL_3_MID_LEFT.GTPE2.SATA_MIN_WAKE[3] 01_164 -GTP_CHANNEL_3_MID_LEFT.GTPE2.SATA_MIN_WAKE[4] 00_165 -GTP_CHANNEL_3_MID_LEFT.GTPE2.SATA_MIN_WAKE[5] 01_165 -GTP_CHANNEL_3_MID_LEFT.GTPE2.SATA_PLL_CFG.VCO_1500MHZ 02_55 -GTP_CHANNEL_3_MID_LEFT.GTPE2.SATA_PLL_CFG.VCO_750MHZ 03_55 -GTP_CHANNEL_3_MID_LEFT.GTPE2.SHOW_REALIGN_COMMA 01_522 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TERM_RCAL_CFG[0] 02_136 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TERM_RCAL_CFG[1] 03_136 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TERM_RCAL_CFG[2] 02_137 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TERM_RCAL_CFG[3] 03_137 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TERM_RCAL_CFG[4] 02_138 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TERM_RCAL_CFG[5] 03_138 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TERM_RCAL_CFG[6] 02_139 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TERM_RCAL_CFG[7] 03_139 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TERM_RCAL_CFG[8] 02_140 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TERM_RCAL_CFG[9] 03_140 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TERM_RCAL_CFG[10] 02_141 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TERM_RCAL_CFG[11] 03_141 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TERM_RCAL_CFG[12] 02_142 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TERM_RCAL_CFG[13] 03_142 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TERM_RCAL_CFG[14] 02_143 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TERM_RCAL_OVRD[0] 03_150 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TERM_RCAL_OVRD[1] 02_151 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TERM_RCAL_OVRD[2] 03_151 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TRANS_TIME_RATE[0] 00_192 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TRANS_TIME_RATE[1] 01_192 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TRANS_TIME_RATE[2] 00_193 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TRANS_TIME_RATE[3] 01_193 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TRANS_TIME_RATE[4] 00_194 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TRANS_TIME_RATE[5] 01_194 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TRANS_TIME_RATE[6] 00_195 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TRANS_TIME_RATE[7] 01_195 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TST_RSV[0] 02_504 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TST_RSV[1] 03_504 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TST_RSV[2] 02_505 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TST_RSV[3] 03_505 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TST_RSV[4] 02_506 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TST_RSV[5] 03_506 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TST_RSV[6] 02_507 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TST_RSV[7] 03_507 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TST_RSV[8] 02_508 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TST_RSV[9] 03_508 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TST_RSV[10] 02_509 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TST_RSV[11] 03_509 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TST_RSV[12] 02_510 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TST_RSV[13] 03_510 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TST_RSV[14] 02_511 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TST_RSV[15] 03_511 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TST_RSV[16] 02_512 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TST_RSV[17] 03_512 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TST_RSV[18] 02_513 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TST_RSV[19] 03_513 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TST_RSV[20] 02_514 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TST_RSV[21] 03_514 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TST_RSV[22] 02_515 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TST_RSV[23] 03_515 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TST_RSV[24] 02_516 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TST_RSV[25] 03_516 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TST_RSV[26] 02_517 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TST_RSV[27] 03_517 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TST_RSV[28] 02_518 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TST_RSV[29] 03_518 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TST_RSV[30] 02_519 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TST_RSV[31] 03_519 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_CLKMUX_EN[0] 03_128 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_DATA_WIDTH[0] 02_152 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_DATA_WIDTH[1] 03_152 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_DATA_WIDTH[2] 02_153 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_DRIVE_MODE.PIPE 00_200 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_EIDLE_ASSERT_DELAY[0] 00_203 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_EIDLE_ASSERT_DELAY[1] 01_203 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_EIDLE_ASSERT_DELAY[2] 00_204 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_EIDLE_DEASSERT_DELAY[0] 01_204 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_EIDLE_DEASSERT_DELAY[1] 00_205 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_EIDLE_DEASSERT_DELAY[2] 01_205 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_LOOPBACK_DRIVE_HIZ 01_202 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_MAINCURSOR_SEL[0] 03_289 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_MARGIN_FULL_0[0] 02_232 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_MARGIN_FULL_0[1] 03_232 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_MARGIN_FULL_0[2] 02_233 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_MARGIN_FULL_0[3] 03_233 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_MARGIN_FULL_0[4] 02_234 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_MARGIN_FULL_0[5] 03_234 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_MARGIN_FULL_0[6] 02_235 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_MARGIN_FULL_1[0] 02_236 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_MARGIN_FULL_1[1] 03_236 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_MARGIN_FULL_1[2] 02_237 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_MARGIN_FULL_1[3] 03_237 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_MARGIN_FULL_1[4] 02_238 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_MARGIN_FULL_1[5] 03_238 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_MARGIN_FULL_1[6] 02_239 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_MARGIN_FULL_2[0] 02_240 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_MARGIN_FULL_2[1] 03_240 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_MARGIN_FULL_2[2] 02_241 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_MARGIN_FULL_2[3] 03_241 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_MARGIN_FULL_2[4] 02_242 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_MARGIN_FULL_2[5] 03_242 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_MARGIN_FULL_2[6] 02_243 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_MARGIN_FULL_3[0] 02_244 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_MARGIN_FULL_3[1] 03_244 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_MARGIN_FULL_3[2] 02_245 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_MARGIN_FULL_3[3] 03_245 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_MARGIN_FULL_3[4] 02_246 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_MARGIN_FULL_3[5] 03_246 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_MARGIN_FULL_3[6] 02_247 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_MARGIN_FULL_4[0] 02_248 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_MARGIN_FULL_4[1] 03_248 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_MARGIN_FULL_4[2] 02_249 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_MARGIN_FULL_4[3] 03_249 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_MARGIN_FULL_4[4] 02_250 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_MARGIN_FULL_4[5] 03_250 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_MARGIN_FULL_4[6] 02_251 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_MARGIN_LOW_0[0] 02_252 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_MARGIN_LOW_0[1] 03_252 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_MARGIN_LOW_0[2] 02_253 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_MARGIN_LOW_0[3] 03_253 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_MARGIN_LOW_0[4] 02_254 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_MARGIN_LOW_0[5] 03_254 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_MARGIN_LOW_0[6] 02_255 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_MARGIN_LOW_1[0] 02_256 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_MARGIN_LOW_1[1] 03_256 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_MARGIN_LOW_1[2] 02_257 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_MARGIN_LOW_1[3] 03_257 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_MARGIN_LOW_1[4] 02_258 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_MARGIN_LOW_1[5] 03_258 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_MARGIN_LOW_1[6] 02_259 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_MARGIN_LOW_2[0] 02_260 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_MARGIN_LOW_2[1] 03_260 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_MARGIN_LOW_2[2] 02_261 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_MARGIN_LOW_2[3] 03_261 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_MARGIN_LOW_2[4] 02_262 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_MARGIN_LOW_2[5] 03_262 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_MARGIN_LOW_2[6] 02_263 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_MARGIN_LOW_3[0] 02_264 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_MARGIN_LOW_3[1] 03_264 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_MARGIN_LOW_3[2] 02_265 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_MARGIN_LOW_3[3] 03_265 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_MARGIN_LOW_3[4] 02_266 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_MARGIN_LOW_3[5] 03_266 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_MARGIN_LOW_3[6] 02_267 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_MARGIN_LOW_4[0] 02_268 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_MARGIN_LOW_4[1] 03_268 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_MARGIN_LOW_4[2] 02_269 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_MARGIN_LOW_4[3] 03_269 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_MARGIN_LOW_4[4] 02_270 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_MARGIN_LOW_4[5] 03_270 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_MARGIN_LOW_4[6] 02_271 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_PREDRIVER_MODE[0] 00_206 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_RXDETECT_CFG[0] 02_296 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_RXDETECT_CFG[1] 03_296 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_RXDETECT_CFG[2] 02_297 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_RXDETECT_CFG[3] 03_297 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_RXDETECT_CFG[4] 02_298 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_RXDETECT_CFG[5] 03_298 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_RXDETECT_CFG[6] 02_299 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_RXDETECT_CFG[7] 03_299 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_RXDETECT_CFG[8] 02_300 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_RXDETECT_CFG[9] 03_300 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_RXDETECT_CFG[10] 02_301 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_RXDETECT_CFG[11] 03_301 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_RXDETECT_CFG[12] 02_302 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_RXDETECT_CFG[13] 03_302 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_RXDETECT_REF[0] 02_292 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_RXDETECT_REF[1] 03_292 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_RXDETECT_REF[2] 02_293 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_XCLK_SEL.TXUSR 03_11 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_CLK25_DIV[0] 02_144 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_CLK25_DIV[1] 03_144 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_CLK25_DIV[2] 02_145 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_CLK25_DIV[3] 03_145 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_CLK25_DIV[4] 02_146 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_DEEMPH0[0] 02_272 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_DEEMPH0[1] 03_272 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_DEEMPH0[2] 02_273 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_DEEMPH0[3] 03_273 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_DEEMPH0[4] 02_274 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_DEEMPH0[5] 03_274 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_DEEMPH1[0] 02_276 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_DEEMPH1[1] 03_276 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_DEEMPH1[2] 02_277 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_DEEMPH1[3] 03_277 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_DEEMPH1[4] 02_278 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_DEEMPH1[5] 03_278 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXBUF_EN 00_231 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXBUF_RESET_ON_RATE_CHANGE 01_231 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXDLY_CFG[0] 02_80 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXDLY_CFG[1] 03_80 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXDLY_CFG[2] 02_81 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXDLY_CFG[3] 03_81 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXDLY_CFG[4] 02_82 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXDLY_CFG[5] 03_82 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXDLY_CFG[6] 02_83 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXDLY_CFG[7] 03_83 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXDLY_CFG[8] 02_84 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXDLY_CFG[9] 03_84 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXDLY_CFG[10] 02_85 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXDLY_CFG[11] 03_85 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXDLY_CFG[12] 02_86 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXDLY_CFG[13] 03_86 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXDLY_CFG[14] 02_87 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXDLY_CFG[15] 03_87 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXDLY_LCFG[0] 02_568 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXDLY_LCFG[1] 03_568 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXDLY_LCFG[2] 02_569 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXDLY_LCFG[3] 03_569 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXDLY_LCFG[4] 02_570 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXDLY_LCFG[5] 03_570 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXDLY_LCFG[6] 02_571 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXDLY_LCFG[7] 03_571 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXDLY_LCFG[8] 02_572 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXDLY_TAP_CFG[0] 02_88 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXDLY_TAP_CFG[1] 03_88 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXDLY_TAP_CFG[2] 02_89 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXDLY_TAP_CFG[3] 03_89 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXDLY_TAP_CFG[4] 02_90 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXDLY_TAP_CFG[5] 03_90 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXDLY_TAP_CFG[6] 02_91 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXDLY_TAP_CFG[7] 03_91 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXDLY_TAP_CFG[8] 02_92 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXDLY_TAP_CFG[9] 03_92 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXDLY_TAP_CFG[10] 02_93 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXDLY_TAP_CFG[11] 03_93 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXDLY_TAP_CFG[12] 02_94 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXDLY_TAP_CFG[13] 03_94 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXDLY_TAP_CFG[14] 02_95 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXDLY_TAP_CFG[15] 03_95 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXGEARBOX_EN 01_226 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXOOB_CFG[0] 03_20 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXOUT_DIV[0] 02_386 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXOUT_DIV[1] 03_386 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPCSRESET_TIME[0] 01_130 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPCSRESET_TIME[1] 00_131 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPCSRESET_TIME[2] 01_131 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPCSRESET_TIME[3] 00_132 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPCSRESET_TIME[4] 01_132 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPH_CFG[0] 02_96 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPH_CFG[1] 03_96 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPH_CFG[2] 02_97 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPH_CFG[3] 03_97 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPH_CFG[4] 02_98 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPH_CFG[5] 03_98 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPH_CFG[6] 02_99 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPH_CFG[7] 03_99 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPH_CFG[8] 02_100 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPH_CFG[9] 03_100 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPH_CFG[10] 02_101 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPH_CFG[11] 03_101 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPH_CFG[12] 02_102 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPH_CFG[13] 03_102 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPH_CFG[14] 02_103 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPH_CFG[15] 03_103 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPH_MONITOR_SEL[0] 02_108 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPH_MONITOR_SEL[1] 03_108 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPH_MONITOR_SEL[2] 02_109 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPH_MONITOR_SEL[3] 03_109 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPH_MONITOR_SEL[4] 02_110 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPHDLY_CFG[0] 02_64 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPHDLY_CFG[1] 03_64 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPHDLY_CFG[2] 02_65 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPHDLY_CFG[3] 03_65 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPHDLY_CFG[4] 02_66 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPHDLY_CFG[5] 03_66 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPHDLY_CFG[6] 02_67 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPHDLY_CFG[7] 03_67 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPHDLY_CFG[8] 02_68 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPHDLY_CFG[9] 03_68 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPHDLY_CFG[10] 02_69 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPHDLY_CFG[11] 03_69 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPHDLY_CFG[12] 02_70 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPHDLY_CFG[13] 03_70 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPHDLY_CFG[14] 02_71 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPHDLY_CFG[15] 03_71 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPHDLY_CFG[16] 02_72 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPHDLY_CFG[17] 03_72 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPHDLY_CFG[18] 02_73 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPHDLY_CFG[19] 03_73 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPHDLY_CFG[20] 02_74 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPHDLY_CFG[21] 03_74 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPHDLY_CFG[22] 02_75 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPHDLY_CFG[23] 03_75 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPI_GREY_SEL[0] 03_498 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPI_INVSTROBE_SEL[0] 02_498 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPI_PPM_CFG[0] 02_488 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPI_PPM_CFG[1] 03_488 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPI_PPM_CFG[2] 02_489 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPI_PPM_CFG[3] 03_489 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPI_PPM_CFG[4] 02_490 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPI_PPM_CFG[5] 03_490 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPI_PPM_CFG[6] 02_491 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPI_PPM_CFG[7] 03_491 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPI_PPMCLK_SEL.TXUSRCLK2 03_497 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPI_SYNFREQ_PPM[0] 02_496 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPI_SYNFREQ_PPM[1] 03_496 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPI_SYNFREQ_PPM[2] 02_497 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPI_CFG0[0] 02_40 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPI_CFG0[1] 03_40 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPI_CFG1[0] 02_41 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPI_CFG1[1] 03_41 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPI_CFG2[0] 02_42 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPI_CFG2[1] 03_42 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPI_CFG3[0] 02_43 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPI_CFG4[0] 03_43 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPI_CFG5[0] 02_44 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPI_CFG5[1] 03_44 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPI_CFG5[2] 02_45 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPMARESET_TIME[0] 00_128 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPMARESET_TIME[1] 01_128 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPMARESET_TIME[2] 00_129 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPMARESET_TIME[3] 01_129 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPMARESET_TIME[4] 00_130 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXSYNC_MULTILANE[0] 01_133 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXSYNC_OVRD[0] 00_135 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXSYNC_SKIP_DA[0] 00_134 -GTP_CHANNEL_3_MID_LEFT.GTPE2.UCODEER_CLR[0] 01_00 -GTP_CHANNEL_3_MID_LEFT.GTPE2.USE_PCS_CLK_PHASE_SEL[0] 02_463 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ZINV_DMONITORCLK 02_13 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ZINV_DRPCLK 02_00 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ZINV_RXUSRCLK 03_01 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ZINV_SIGVALIDCLK 03_13 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ZINV_TXPHDLYTSTCLK 02_03 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ZINV_TXUSRCLK 03_04 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ZINV_CLKRSVD0 02_23 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ZINV_CLKRSVD1 03_23 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ZINV_RXUSRCLK2 02_02 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ZINV_TXUSRCLK2 02_05 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ACJTAG_DEBUG_MODE[0] 00_07 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ACJTAG_MODE[0] 01_06 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ACJTAG_RESET[0] 01_07 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[0] 02_464 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[1] 03_464 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[2] 02_465 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[3] 03_465 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[4] 02_466 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[5] 03_466 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[6] 02_467 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[7] 03_467 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[8] 02_468 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[9] 03_468 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[10] 02_469 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[11] 03_469 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[12] 02_470 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[13] 03_470 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[14] 02_471 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[15] 03_471 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[16] 02_472 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[17] 03_472 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[18] 02_473 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[19] 03_473 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ALIGN_COMMA_DOUBLE 00_522 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[0] 00_496 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[1] 01_496 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[2] 00_497 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[3] 01_497 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[4] 00_498 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[5] 01_498 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[6] 00_499 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[7] 01_499 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[8] 00_500 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[9] 01_500 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ALIGN_COMMA_WORD[0] 01_526 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ALIGN_COMMA_WORD[1] 00_527 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ALIGN_MCOMMA_DET 00_523 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[0] 00_504 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[1] 01_504 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[2] 00_505 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[3] 01_505 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[4] 00_506 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[5] 01_506 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[6] 00_507 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[7] 01_507 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[8] 00_508 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[9] 01_508 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ALIGN_PCOMMA_DET 01_523 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[0] 00_512 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[1] 01_512 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[2] 00_513 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[3] 01_513 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[4] 00_514 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[5] 01_514 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[6] 00_515 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[7] 01_515 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[8] 00_516 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[9] 01_516 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CBCC_DATA_SOURCE_SEL.DECODED 01_661 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[0] 02_392 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[1] 03_392 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[2] 02_393 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[3] 03_393 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[4] 02_394 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[5] 03_394 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[6] 02_395 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[7] 03_395 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[8] 02_396 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[9] 03_396 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[10] 02_397 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[11] 03_397 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[12] 02_398 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[13] 03_398 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[14] 02_399 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[15] 03_399 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[16] 02_400 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[17] 03_400 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[18] 02_401 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[19] 03_401 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[20] 02_402 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[21] 03_402 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[22] 02_403 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[23] 03_403 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[24] 02_404 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[25] 03_404 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[26] 02_405 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[27] 03_405 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[28] 02_406 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[29] 03_406 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[30] 02_407 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[31] 03_407 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[32] 02_408 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[33] 03_408 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[34] 02_409 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[35] 03_409 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[36] 02_410 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[37] 03_410 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[38] 02_411 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[39] 03_411 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[40] 02_412 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[41] 03_412 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[42] 02_413 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG2[0] 02_459 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG2[1] 03_459 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG2[2] 02_460 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG2[3] 03_460 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG2[4] 02_461 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG2[5] 03_461 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG2[6] 02_462 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG3[0] 02_416 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG3[1] 03_416 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG3[2] 02_417 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG3[3] 03_417 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG3[4] 02_418 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG3[5] 03_418 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG3[6] 02_419 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG4[0] 03_438 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG5[0] 02_429 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG5[1] 03_429 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG6[0] 03_436 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG6[1] 02_437 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG6[2] 03_437 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG6[3] 02_438 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_KEEP_ALIGN 01_631 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_MAX_SKEW[0] 00_670 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_MAX_SKEW[1] 01_670 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_MAX_SKEW[2] 00_671 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_MAX_SKEW[3] 01_671 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[0] 00_608 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[1] 01_608 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[2] 00_609 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[3] 01_609 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[4] 00_610 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[5] 01_610 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[6] 00_611 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[7] 01_611 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[8] 00_612 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[9] 01_612 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[0] 00_616 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[1] 01_616 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[2] 00_617 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[3] 01_617 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[4] 00_618 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[5] 01_618 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[6] 00_619 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[7] 01_619 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[8] 00_620 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[9] 01_620 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[0] 00_624 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[1] 01_624 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[2] 00_625 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[3] 01_625 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[4] 00_626 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[5] 01_626 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[6] 00_627 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[7] 01_627 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[8] 00_628 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[9] 01_628 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[0] 00_632 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[1] 01_632 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[2] 00_633 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[3] 01_633 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[4] 00_634 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[5] 01_634 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[6] 00_635 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[7] 01_635 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[8] 00_636 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[9] 01_636 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_ENABLE[0] 00_614 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_ENABLE[1] 01_614 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_ENABLE[2] 00_615 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_ENABLE[3] 01_615 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[0] 00_640 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[1] 01_640 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[2] 00_641 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[3] 01_641 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[4] 00_642 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[5] 01_642 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[6] 00_643 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[7] 01_643 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[8] 00_644 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[9] 01_644 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[0] 00_648 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[1] 01_648 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[2] 00_649 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[3] 01_649 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[4] 00_650 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[5] 01_650 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[6] 00_651 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[7] 01_651 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[8] 00_652 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[9] 01_652 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[0] 00_656 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[1] 01_656 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[2] 00_657 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[3] 01_657 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[4] 00_658 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[5] 01_658 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[6] 00_659 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[7] 01_659 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[8] 00_660 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[9] 01_660 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[0] 00_664 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[1] 01_664 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[2] 00_665 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[3] 01_665 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[4] 00_666 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[5] 01_666 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[6] 00_667 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[7] 01_667 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[8] 00_668 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[9] 01_668 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_ENABLE[0] 00_646 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_ENABLE[1] 01_646 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_ENABLE[2] 00_647 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_ENABLE[3] 01_647 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_USE 01_645 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_LEN[0] 00_623 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_LEN[1] 01_623 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COMMON_SWING[0] 03_311 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_KEEP_IDLE 00_591 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_MAX_LAT[0] 00_557 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_MAX_LAT[1] 01_557 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_MAX_LAT[2] 00_558 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_MAX_LAT[3] 01_558 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_MAX_LAT[4] 00_559 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_MAX_LAT[5] 01_559 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_MIN_LAT[0] 00_565 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_MIN_LAT[1] 01_565 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_MIN_LAT[2] 00_566 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_MIN_LAT[3] 01_566 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_MIN_LAT[4] 00_567 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_MIN_LAT[5] 01_567 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_PRECEDENCE 00_590 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_REPEAT_WAIT[0] 00_573 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_REPEAT_WAIT[1] 01_573 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_REPEAT_WAIT[2] 00_574 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_REPEAT_WAIT[3] 01_574 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_REPEAT_WAIT[4] 00_575 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[0] 00_544 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[1] 01_544 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[2] 00_545 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[3] 01_545 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[4] 00_546 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[5] 01_546 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[6] 00_547 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[7] 01_547 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[8] 00_548 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[9] 01_548 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[0] 00_552 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[1] 01_552 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[2] 00_553 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[3] 01_553 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[4] 00_554 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[5] 01_554 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[6] 00_555 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[7] 01_555 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[8] 00_556 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[9] 01_556 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[0] 00_560 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[1] 01_560 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[2] 00_561 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[3] 01_561 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[4] 00_562 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[5] 01_562 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[6] 00_563 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[7] 01_563 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[8] 00_564 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[9] 01_564 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[0] 00_568 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[1] 01_568 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[2] 00_569 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[3] 01_569 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[4] 00_570 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[5] 01_570 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[6] 00_571 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[7] 01_571 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[8] 00_572 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[9] 01_572 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_ENABLE[0] 00_549 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_ENABLE[1] 01_549 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_ENABLE[2] 00_550 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_ENABLE[3] 01_550 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[0] 00_576 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[1] 01_576 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[2] 00_577 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[3] 01_577 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[4] 00_578 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[5] 01_578 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[6] 00_579 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[7] 01_579 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[8] 00_580 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[9] 01_580 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[0] 00_584 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[1] 01_584 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[2] 00_585 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[3] 01_585 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[4] 00_586 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[5] 01_586 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[6] 00_587 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[7] 01_587 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[8] 00_588 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[9] 01_588 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[0] 00_592 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[1] 01_592 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[2] 00_593 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[3] 01_593 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[4] 00_594 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[5] 01_594 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[6] 00_595 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[7] 01_595 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[8] 00_596 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[9] 01_596 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[0] 00_600 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[1] 01_600 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[2] 00_601 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[3] 01_601 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[4] 00_602 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[5] 01_602 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[6] 00_603 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[7] 01_603 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[8] 00_604 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[9] 01_604 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_ENABLE[0] 00_581 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_ENABLE[1] 01_581 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_ENABLE[2] 00_582 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_ENABLE[3] 01_582 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_USE 00_583 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_LEN[0] 00_589 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_LEN[1] 01_589 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_CORRECT_USE 00_551 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.DEC_MCOMMA_DETECT 01_494 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.DEC_PCOMMA_DETECT 00_495 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.DEC_VALID_COMMA_ONLY 00_494 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[0] 02_368 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[1] 03_368 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[2] 02_369 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[3] 03_369 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[4] 02_370 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[5] 03_370 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[6] 02_371 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[7] 03_371 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[8] 02_372 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[9] 03_372 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[10] 02_373 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[11] 03_373 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[12] 02_374 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[13] 03_374 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[14] 02_375 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[15] 03_375 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[16] 02_376 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[17] 03_376 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[18] 02_377 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[19] 03_377 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[20] 02_378 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[21] 03_378 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[22] 02_379 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[23] 03_379 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_CLK_PHASE_SEL[0] 03_463 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_CONTROL[0] 00_488 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_CONTROL[1] 01_488 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_CONTROL[2] 00_489 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_CONTROL[3] 01_489 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_CONTROL[4] 00_490 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_CONTROL[5] 01_490 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_ERRDET_EN 01_492 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_EYE_SCAN_EN 00_492 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_HORZ_OFFSET[0] 00_480 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_HORZ_OFFSET[1] 01_480 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_HORZ_OFFSET[2] 00_481 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_HORZ_OFFSET[3] 01_481 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_HORZ_OFFSET[4] 00_482 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_HORZ_OFFSET[5] 01_482 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_HORZ_OFFSET[6] 00_483 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_HORZ_OFFSET[7] 01_483 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_HORZ_OFFSET[8] 00_484 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_HORZ_OFFSET[9] 01_484 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_HORZ_OFFSET[10] 00_485 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_HORZ_OFFSET[11] 01_485 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_PMA_CFG[0] 02_624 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_PMA_CFG[1] 03_624 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_PMA_CFG[2] 02_625 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_PMA_CFG[3] 03_625 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_PMA_CFG[4] 02_626 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_PMA_CFG[5] 03_626 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_PMA_CFG[6] 02_627 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_PMA_CFG[7] 03_627 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_PMA_CFG[8] 02_628 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_PMA_CFG[9] 03_628 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_PRESCALE[0] 01_477 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_PRESCALE[1] 00_478 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_PRESCALE[2] 01_478 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_PRESCALE[3] 00_479 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_PRESCALE[4] 01_479 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[0] 00_392 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[1] 01_392 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[2] 00_393 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[3] 01_393 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[4] 00_394 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[5] 01_394 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[6] 00_395 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[7] 01_395 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[8] 00_396 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[9] 01_396 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[10] 00_397 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[11] 01_397 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[12] 00_398 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[13] 01_398 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[14] 00_399 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[15] 01_399 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[16] 00_400 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[17] 01_400 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[18] 00_401 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[19] 01_401 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[20] 00_402 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[21] 01_402 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[22] 00_403 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[23] 01_403 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[24] 00_404 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[25] 01_404 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[26] 00_405 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[27] 01_405 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[28] 00_406 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[29] 01_406 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[30] 00_407 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[31] 01_407 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[32] 00_408 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[33] 01_408 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[34] 00_409 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[35] 01_409 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[36] 00_410 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[37] 01_410 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[38] 00_411 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[39] 01_411 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[40] 00_412 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[41] 01_412 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[42] 00_413 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[43] 01_413 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[44] 00_414 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[45] 01_414 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[46] 00_415 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[47] 01_415 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[48] 00_416 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[49] 01_416 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[50] 00_417 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[51] 01_417 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[52] 00_418 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[53] 01_418 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[54] 00_419 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[55] 01_419 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[56] 00_420 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[57] 01_420 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[58] 00_421 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[59] 01_421 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[60] 00_422 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[61] 01_422 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[62] 00_423 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[63] 01_423 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[64] 00_424 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[65] 01_424 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[66] 00_425 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[67] 01_425 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[68] 00_426 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[69] 01_426 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[70] 00_427 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[71] 01_427 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[72] 00_428 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[73] 01_428 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[74] 00_429 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[75] 01_429 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[76] 00_430 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[77] 01_430 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[78] 00_431 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[79] 01_431 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[0] 00_352 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[1] 01_352 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[2] 00_353 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[3] 01_353 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[4] 00_354 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[5] 01_354 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[6] 00_355 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[7] 01_355 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[8] 00_356 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[9] 01_356 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[10] 00_357 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[11] 01_357 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[12] 00_358 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[13] 01_358 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[14] 00_359 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[15] 01_359 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[16] 00_360 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[17] 01_360 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[18] 00_361 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[19] 01_361 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[20] 00_362 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[21] 01_362 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[22] 00_363 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[23] 01_363 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[24] 00_364 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[25] 01_364 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[26] 00_365 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[27] 01_365 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[28] 00_366 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[29] 01_366 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[30] 00_367 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[31] 01_367 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[32] 00_368 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[33] 01_368 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[34] 00_369 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[35] 01_369 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[36] 00_370 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[37] 01_370 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[38] 00_371 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[39] 01_371 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[40] 00_372 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[41] 01_372 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[42] 00_373 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[43] 01_373 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[44] 00_374 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[45] 01_374 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[46] 00_375 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[47] 01_375 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[48] 00_376 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[49] 01_376 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[50] 00_377 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[51] 01_377 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[52] 00_378 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[53] 01_378 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[54] 00_379 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[55] 01_379 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[56] 00_380 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[57] 01_380 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[58] 00_381 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[59] 01_381 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[60] 00_382 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[61] 01_382 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[62] 00_383 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[63] 01_383 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[64] 00_384 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[65] 01_384 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[66] 00_385 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[67] 01_385 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[68] 00_386 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[69] 01_386 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[70] 00_387 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[71] 01_387 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[72] 00_388 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[73] 01_388 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[74] 00_389 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[75] 01_389 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[76] 00_390 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[77] 01_390 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[78] 00_391 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[79] 01_391 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[0] 00_432 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[1] 01_432 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[2] 00_433 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[3] 01_433 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[4] 00_434 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[5] 01_434 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[6] 00_435 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[7] 01_435 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[8] 00_436 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[9] 01_436 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[10] 00_437 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[11] 01_437 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[12] 00_438 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[13] 01_438 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[14] 00_439 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[15] 01_439 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[16] 00_440 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[17] 01_440 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[18] 00_441 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[19] 01_441 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[20] 00_442 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[21] 01_442 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[22] 00_443 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[23] 01_443 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[24] 00_444 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[25] 01_444 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[26] 00_445 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[27] 01_445 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[28] 00_446 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[29] 01_446 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[30] 00_447 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[31] 01_447 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[32] 00_448 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[33] 01_448 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[34] 00_449 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[35] 01_449 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[36] 00_450 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[37] 01_450 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[38] 00_451 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[39] 01_451 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[40] 00_452 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[41] 01_452 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[42] 00_453 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[43] 01_453 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[44] 00_454 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[45] 01_454 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[46] 00_455 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[47] 01_455 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[48] 00_456 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[49] 01_456 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[50] 00_457 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[51] 01_457 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[52] 00_458 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[53] 01_458 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[54] 00_459 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[55] 01_459 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[56] 00_460 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[57] 01_460 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[58] 00_461 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[59] 01_461 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[60] 00_462 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[61] 01_462 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[62] 00_463 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[63] 01_463 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[64] 00_464 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[65] 01_464 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[66] 00_465 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[67] 01_465 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[68] 00_466 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[69] 01_466 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[70] 00_467 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[71] 01_467 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[72] 00_468 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[73] 01_468 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[74] 00_469 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[75] 01_469 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[76] 00_470 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[77] 01_470 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[78] 00_471 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[79] 01_471 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_VERT_OFFSET[0] 00_472 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_VERT_OFFSET[1] 01_472 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_VERT_OFFSET[2] 00_473 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_VERT_OFFSET[3] 01_473 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_VERT_OFFSET[4] 00_474 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_VERT_OFFSET[5] 01_474 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_VERT_OFFSET[6] 00_475 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_VERT_OFFSET[7] 01_475 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_VERT_OFFSET[8] 00_476 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.FTS_DESKEW_SEQ_ENABLE[0] 00_662 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.FTS_DESKEW_SEQ_ENABLE[1] 01_662 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.FTS_DESKEW_SEQ_ENABLE[2] 00_663 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.FTS_DESKEW_SEQ_ENABLE[3] 01_663 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.FTS_LANE_DESKEW_CFG[0] 00_654 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.FTS_LANE_DESKEW_CFG[1] 01_654 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.FTS_LANE_DESKEW_CFG[2] 00_655 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.FTS_LANE_DESKEW_CFG[3] 01_655 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.FTS_LANE_DESKEW_EN 01_653 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.GEARBOX_MODE[0] 00_224 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.GEARBOX_MODE[1] 01_224 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.GEARBOX_MODE[2] 00_225 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.IN_USE 00_00 00_01 00_47 00_52 00_53 00_65 01_01 01_47 02_129 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.INV_DMONITORCLK 02_13 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.INV_DRPCLK 02_00 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.INV_RXUSRCLK 03_01 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.INV_SIGVALIDCLK 03_13 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.INV_TXPHDLYTSTCLK 02_03 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.INV_TXUSRCLK 03_04 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.INV_CLKRSVD0 02_23 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.INV_CLKRSVD1 03_23 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.INV_RXUSRCLK2 02_02 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.INV_TXUSRCLK2 02_05 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.LOOPBACK_CFG[0] 02_20 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.OUTREFCLK_SEL_INV[0] 00_149 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.OUTREFCLK_SEL_INV[1] 01_149 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PCS_PCIE_EN 00_216 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[0] 02_184 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[1] 03_184 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[2] 02_185 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[3] 03_185 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[4] 02_186 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[5] 03_186 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[6] 02_187 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[7] 03_187 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[8] 02_188 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[9] 03_188 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[10] 02_189 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[11] 03_189 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[12] 02_190 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[13] 03_190 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[14] 02_191 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[15] 03_191 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[16] 02_192 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[17] 03_192 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[18] 02_193 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[19] 03_193 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[20] 02_194 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[21] 03_194 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[22] 02_195 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[23] 03_195 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[24] 02_196 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[25] 03_196 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[26] 02_197 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[27] 03_197 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[28] 02_198 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[29] 03_198 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[30] 02_199 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[31] 03_199 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[32] 02_200 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[33] 03_200 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[34] 02_201 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[35] 03_201 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[36] 02_202 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[37] 03_202 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[38] 02_203 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[39] 03_203 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[40] 02_204 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[41] 03_204 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[42] 02_205 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[43] 03_205 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[44] 02_206 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[45] 03_206 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[46] 02_207 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[47] 03_207 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[0] 01_216 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[1] 00_217 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[2] 01_217 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[3] 00_218 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[4] 01_218 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[5] 00_219 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[6] 01_219 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[7] 00_220 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[8] 01_220 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[9] 00_221 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[10] 01_221 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[11] 00_222 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[0] 00_208 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[1] 01_208 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[2] 00_209 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[3] 01_209 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[4] 00_210 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[5] 01_210 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[6] 00_211 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[7] 01_211 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[0] 00_212 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[1] 01_212 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[2] 00_213 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[3] 01_213 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[4] 00_214 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[5] 01_214 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[6] 00_215 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[7] 01_215 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PMA_LOOPBACK_CFG[0] 01_207 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[0] 02_520 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[1] 03_520 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[2] 02_521 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[3] 03_521 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[4] 02_522 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[5] 03_522 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[6] 02_523 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[7] 03_523 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[8] 02_524 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[9] 03_524 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[10] 02_525 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[11] 03_525 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[12] 02_526 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[13] 03_526 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[14] 02_527 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[15] 03_527 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[16] 02_528 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[17] 03_528 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[18] 02_529 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[19] 03_529 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[20] 02_530 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[21] 03_530 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[22] 02_531 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[23] 03_531 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[24] 02_532 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[25] 03_532 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[26] 02_533 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[27] 03_533 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[28] 02_534 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[29] 03_534 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[30] 02_535 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[31] 03_535 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[0] 02_336 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[1] 03_336 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[2] 02_337 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[3] 03_337 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[4] 02_338 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[5] 03_338 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[6] 02_339 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[7] 03_339 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[8] 02_340 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[9] 03_340 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[10] 02_341 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[11] 03_341 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[12] 02_342 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[13] 03_342 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[14] 02_343 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[15] 03_343 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[16] 02_344 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[17] 03_344 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[18] 02_345 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[19] 03_345 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[20] 02_346 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[21] 03_346 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[22] 02_347 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[23] 03_347 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[24] 02_348 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[25] 03_348 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[26] 02_349 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[27] 03_349 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[28] 02_350 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[29] 03_350 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[30] 02_351 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[31] 03_351 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PMA_RSV3[0] 02_288 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PMA_RSV3[1] 03_288 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PMA_RSV4[0] 02_156 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PMA_RSV4[1] 03_156 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PMA_RSV4[2] 02_157 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PMA_RSV4[3] 03_157 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PMA_RSV5[0] 03_159 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PMA_RSV6[0] 02_303 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PMA_RSV7[0] 03_303 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_BIAS_CFG[0] 02_112 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_BIAS_CFG[1] 03_112 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_BIAS_CFG[2] 02_113 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_BIAS_CFG[3] 03_113 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_BIAS_CFG[4] 02_114 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_BIAS_CFG[5] 03_114 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_BIAS_CFG[6] 02_115 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_BIAS_CFG[7] 03_115 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_BIAS_CFG[8] 02_116 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_BIAS_CFG[9] 03_116 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_BIAS_CFG[10] 02_117 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_BIAS_CFG[11] 03_117 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_BIAS_CFG[12] 02_118 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_BIAS_CFG[13] 03_118 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_BIAS_CFG[14] 02_119 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_BIAS_CFG[15] 03_119 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_BUFFER_CFG[0] 02_536 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_BUFFER_CFG[1] 03_536 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_BUFFER_CFG[2] 02_537 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_BUFFER_CFG[3] 03_537 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_BUFFER_CFG[4] 02_538 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_BUFFER_CFG[5] 03_538 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_CLKMUX_EN[0] 02_128 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_CM_SEL[0] 00_138 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_CM_SEL[1] 01_138 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_CM_TRIM[0] 02_304 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_CM_TRIM[1] 03_304 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_CM_TRIM[2] 02_305 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_CM_TRIM[3] 03_305 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_DATA_WIDTH[0] 01_141 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_DATA_WIDTH[1] 00_142 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_DATA_WIDTH[2] 01_142 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_DDI_SEL[0] 00_696 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_DDI_SEL[1] 01_696 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_DDI_SEL[2] 00_697 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_DDI_SEL[3] 01_697 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_DDI_SEL[4] 00_698 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_DDI_SEL[5] 01_698 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_DEBUG_CFG[0] 02_616 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_DEBUG_CFG[1] 03_616 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_DEBUG_CFG[2] 02_617 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_DEBUG_CFG[3] 03_617 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_DEBUG_CFG[4] 02_618 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_DEBUG_CFG[5] 03_618 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_DEBUG_CFG[6] 02_619 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_DEBUG_CFG[7] 03_619 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_DEBUG_CFG[8] 02_620 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_DEBUG_CFG[9] 03_620 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_DEBUG_CFG[10] 02_621 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_DEBUG_CFG[11] 03_621 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_DEBUG_CFG[12] 02_622 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_DEBUG_CFG[13] 03_622 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_DEFER_RESET_BUF_EN 02_552 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_DISPERR_SEQ_MATCH 01_495 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_OS_CFG[0] 00_288 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_OS_CFG[1] 01_288 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_OS_CFG[2] 00_289 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_OS_CFG[3] 01_289 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_OS_CFG[4] 00_290 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_OS_CFG[5] 01_290 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_OS_CFG[6] 00_291 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_OS_CFG[7] 01_291 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_OS_CFG[8] 00_292 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_OS_CFG[9] 01_292 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_OS_CFG[10] 00_293 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_OS_CFG[11] 01_293 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_OS_CFG[12] 00_294 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_SIG_VALID_DLY[0] 00_524 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_SIG_VALID_DLY[1] 01_524 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_SIG_VALID_DLY[2] 00_525 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_SIG_VALID_DLY[3] 01_525 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_SIG_VALID_DLY[4] 00_526 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_XCLK_SEL.RXUSR 00_143 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_CLK25_DIV[0] 00_139 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_CLK25_DIV[1] 01_139 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_CLK25_DIV[2] 00_140 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_CLK25_DIV[3] 01_140 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_CLK25_DIV[4] 00_141 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXBUF_ADDR_MODE.FAST 03_555 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXBUF_EIDLE_HI_CNT[0] 02_558 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXBUF_EIDLE_HI_CNT[1] 03_558 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXBUF_EIDLE_HI_CNT[2] 02_559 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXBUF_EIDLE_HI_CNT[3] 03_559 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXBUF_EIDLE_LO_CNT[0] 02_556 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXBUF_EIDLE_LO_CNT[1] 03_556 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXBUF_EIDLE_LO_CNT[2] 02_557 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXBUF_EIDLE_LO_CNT[3] 03_557 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXBUF_EN 02_11 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXBUF_RESET_ON_CB_CHANGE 02_560 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXBUF_RESET_ON_COMMAALIGN 02_561 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXBUF_RESET_ON_EIDLE 02_547 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXBUF_RESET_ON_RATE_CHANGE 03_560 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXBUF_THRESH_OVFLW[0] 03_552 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXBUF_THRESH_OVFLW[1] 02_553 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXBUF_THRESH_OVFLW[2] 03_553 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXBUF_THRESH_OVFLW[3] 02_554 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXBUF_THRESH_OVFLW[4] 03_554 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXBUF_THRESH_OVFLW[5] 02_555 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXBUF_THRESH_OVRD 02_548 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXBUF_THRESH_UNDFLW[0] 02_544 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXBUF_THRESH_UNDFLW[1] 03_544 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXBUF_THRESH_UNDFLW[2] 02_545 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXBUF_THRESH_UNDFLW[3] 03_545 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXBUF_THRESH_UNDFLW[4] 02_546 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXBUF_THRESH_UNDFLW[5] 03_546 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXBUFRESET_TIME[0] 01_101 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXBUFRESET_TIME[1] 00_102 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXBUFRESET_TIME[2] 01_102 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXBUFRESET_TIME[3] 00_103 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXBUFRESET_TIME[4] 01_103 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[0] 02_640 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[1] 03_640 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[2] 02_641 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[3] 03_641 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[4] 02_642 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[5] 03_642 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[6] 02_643 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[7] 03_643 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[8] 02_644 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[9] 03_644 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[10] 02_645 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[11] 03_645 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[12] 02_646 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[13] 03_646 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[14] 02_647 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[15] 03_647 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[16] 02_648 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[17] 03_648 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[18] 02_649 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[19] 03_649 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[20] 02_650 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[21] 03_650 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[22] 02_651 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[23] 03_651 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[24] 02_652 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[25] 03_652 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[26] 02_653 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[27] 03_653 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[28] 02_654 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[29] 03_654 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[30] 02_655 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[31] 03_655 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[32] 02_656 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[33] 03_656 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[34] 02_657 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[35] 03_657 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[36] 02_658 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[37] 03_658 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[38] 02_659 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[39] 03_659 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[40] 02_660 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[41] 03_660 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[42] 02_661 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[43] 03_661 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[44] 02_662 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[45] 03_662 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[46] 02_663 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[47] 03_663 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[48] 02_664 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[49] 03_664 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[50] 02_665 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[51] 03_665 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[52] 02_666 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[53] 03_666 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[54] 02_667 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[55] 03_667 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[56] 02_668 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[57] 03_668 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[58] 02_669 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[59] 03_669 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[60] 02_670 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[61] 03_670 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[62] 02_671 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[63] 03_671 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[64] 02_672 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[65] 03_672 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[66] 02_673 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[67] 03_673 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[68] 02_674 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[69] 03_674 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[70] 02_675 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[71] 03_675 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[72] 02_676 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[73] 03_676 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[74] 02_677 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[75] 03_677 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[76] 02_678 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[77] 03_678 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[78] 02_679 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[79] 03_679 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[80] 02_680 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[81] 03_680 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[82] 02_681 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_FR_RESET_ON_EIDLE[0] 02_638 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_HOLD_DURING_EIDLE[0] 03_637 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_LOCK_CFG[0] 02_632 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_LOCK_CFG[1] 03_632 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_LOCK_CFG[2] 02_633 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_LOCK_CFG[3] 03_633 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_LOCK_CFG[4] 02_634 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_LOCK_CFG[5] 03_634 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_PH_RESET_ON_EIDLE[0] 03_638 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDRFREQRESET_TIME[0] 01_106 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDRFREQRESET_TIME[1] 00_107 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDRFREQRESET_TIME[2] 01_107 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDRFREQRESET_TIME[3] 00_108 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDRFREQRESET_TIME[4] 01_108 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDRPHRESET_TIME[0] 00_109 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDRPHRESET_TIME[1] 01_109 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDRPHRESET_TIME[2] 00_110 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDRPHRESET_TIME[3] 01_110 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDRPHRESET_TIME[4] 00_111 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXDLY_CFG[0] 00_680 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXDLY_CFG[1] 01_680 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXDLY_CFG[2] 00_681 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXDLY_CFG[3] 01_681 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXDLY_CFG[4] 00_682 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXDLY_CFG[5] 01_682 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXDLY_CFG[6] 00_683 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXDLY_CFG[7] 01_683 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXDLY_CFG[8] 00_684 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXDLY_CFG[9] 01_684 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXDLY_CFG[10] 00_685 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXDLY_CFG[11] 01_685 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXDLY_CFG[12] 00_686 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXDLY_CFG[13] 01_686 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXDLY_CFG[14] 00_687 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXDLY_CFG[15] 01_687 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXDLY_LCFG[0] 02_576 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXDLY_LCFG[1] 03_576 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXDLY_LCFG[2] 02_577 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXDLY_LCFG[3] 03_577 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXDLY_LCFG[4] 02_578 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXDLY_LCFG[5] 03_578 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXDLY_LCFG[6] 02_579 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXDLY_LCFG[7] 03_579 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXDLY_LCFG[8] 02_580 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXDLY_TAP_CFG[0] 00_672 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXDLY_TAP_CFG[1] 01_672 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXDLY_TAP_CFG[2] 00_673 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXDLY_TAP_CFG[3] 01_673 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXDLY_TAP_CFG[4] 00_674 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXDLY_TAP_CFG[5] 01_674 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXDLY_TAP_CFG[6] 00_675 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXDLY_TAP_CFG[7] 01_675 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXDLY_TAP_CFG[8] 00_676 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXDLY_TAP_CFG[9] 01_676 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXDLY_TAP_CFG[10] 00_677 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXDLY_TAP_CFG[11] 01_677 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXDLY_TAP_CFG[12] 00_678 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXDLY_TAP_CFG[13] 01_678 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXDLY_TAP_CFG[14] 00_679 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXDLY_TAP_CFG[15] 01_679 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXGEARBOX_EN 01_607 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXISCANRESET_TIME[0] 01_123 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXISCANRESET_TIME[1] 00_124 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXISCANRESET_TIME[2] 01_124 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXISCANRESET_TIME[3] 00_125 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXISCANRESET_TIME[4] 01_125 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPM_BIAS_STARTUP_DISABLE[0] 03_391 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPM_CFG[0] 02_328 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPM_CFG[1] 03_328 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPM_CFG[2] 02_329 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPM_CFG[3] 03_329 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPM_CM_CFG[0] 02_430 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPM_GC_CFG[0] 02_432 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPM_GC_CFG[1] 03_432 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPM_GC_CFG[2] 02_433 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPM_GC_CFG[3] 03_433 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPM_GC_CFG[4] 02_434 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPM_GC_CFG[5] 03_434 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPM_GC_CFG[6] 02_435 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPM_GC_CFG[7] 03_435 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPM_GC_CFG[8] 02_436 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPM_GC_CFG2[0] 03_442 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPM_GC_CFG2[1] 02_443 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPM_GC_CFG2[2] 03_443 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG[0] 00_336 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG[1] 01_336 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG[2] 00_337 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG[3] 01_337 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG[4] 00_338 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG[5] 01_338 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG[6] 00_339 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG[7] 01_339 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG[8] 00_340 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG[9] 01_340 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG[10] 00_341 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG[11] 01_341 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG[12] 00_342 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG[13] 01_342 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG2[0] 02_424 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG2[1] 03_424 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG2[2] 02_425 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG2[3] 03_425 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG2[4] 02_426 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG3[0] 03_389 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG3[1] 02_390 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG3[2] 03_390 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG3[3] 02_391 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPM_HOLD_DURING_EIDLE[0] 00_247 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPM_INCM_CFG[0] 02_439 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPM_IPCM_CFG[0] 03_439 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG[0] 00_344 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG[1] 01_344 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG[2] 00_345 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG[3] 01_345 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG[4] 00_346 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG[5] 01_346 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG[6] 00_347 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG[7] 01_347 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG[8] 00_348 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG[9] 01_348 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG[10] 00_349 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG[11] 01_349 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG[12] 00_350 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG[13] 01_350 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG[14] 00_351 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG[15] 01_351 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG[16] 00_343 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG[17] 01_343 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG2[0] 03_426 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG2[1] 02_427 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG2[2] 03_427 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG2[3] 02_428 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG2[4] 03_428 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPM_OSINT_CFG[0] 02_440 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPM_OSINT_CFG[1] 03_440 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPM_OSINT_CFG[2] 02_441 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPM_CFG1[0] 02_330 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPMRESET_TIME[0] 00_112 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPMRESET_TIME[1] 01_112 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPMRESET_TIME[2] 00_113 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPMRESET_TIME[3] 01_113 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPMRESET_TIME[4] 00_114 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPMRESET_TIME[5] 01_114 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPMRESET_TIME[6] 00_115 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXOOB_CFG[0] 00_144 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXOOB_CFG[1] 01_144 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXOOB_CFG[2] 00_145 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXOOB_CFG[3] 01_145 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXOOB_CFG[4] 00_146 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXOOB_CFG[5] 01_146 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXOOB_CFG[6] 00_147 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXOOB_CLK_CFG.FABRIC 03_129 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXOSCALRESET_TIME[0] 00_187 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXOSCALRESET_TIME[1] 01_187 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXOSCALRESET_TIME[2] 00_188 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXOSCALRESET_TIME[3] 01_188 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXOSCALRESET_TIME[4] 00_189 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXOSCALRESET_TIMEOUT[0] 01_189 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXOSCALRESET_TIMEOUT[1] 00_190 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXOSCALRESET_TIMEOUT[2] 01_190 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXOSCALRESET_TIMEOUT[3] 00_191 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXOSCALRESET_TIMEOUT[4] 01_191 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXOUT_DIV[0] 02_384 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXOUT_DIV[1] 03_384 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXPCSRESET_TIME[0] 01_115 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXPCSRESET_TIME[1] 00_116 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXPCSRESET_TIME[2] 01_116 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXPCSRESET_TIME[3] 00_117 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXPCSRESET_TIME[4] 01_117 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[0] 02_584 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[1] 03_584 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[2] 02_585 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[3] 03_585 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[4] 02_586 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[5] 03_586 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[6] 02_587 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[7] 03_587 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[8] 02_588 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[9] 03_588 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[10] 02_589 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[11] 03_589 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[12] 02_590 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[13] 03_590 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[14] 02_591 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[15] 03_591 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[16] 02_592 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[17] 03_592 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[18] 02_593 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[19] 03_593 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[20] 02_594 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[21] 03_594 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[22] 02_595 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[23] 03_595 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXPH_MONITOR_SEL[0] 00_700 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXPH_MONITOR_SEL[1] 01_700 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXPH_MONITOR_SEL[2] 00_701 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXPH_MONITOR_SEL[3] 01_701 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXPH_MONITOR_SEL[4] 00_702 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[0] 02_600 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[1] 03_600 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[2] 02_601 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[3] 03_601 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[4] 02_602 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[5] 03_602 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[6] 02_603 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[7] 03_603 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[8] 02_604 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[9] 03_604 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[10] 02_605 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[11] 03_605 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[12] 02_606 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[13] 03_606 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[14] 02_607 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[15] 03_607 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[16] 02_608 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[17] 03_608 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[18] 02_609 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[19] 03_609 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[20] 02_610 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[21] 03_610 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[22] 02_611 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[23] 03_611 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXPI_CFG0[0] 03_430 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXPI_CFG0[1] 02_431 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXPI_CFG0[2] 03_431 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXPI_CFG1[0] 02_442 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXPI_CFG2[0] 03_441 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXPMARESET_TIME[0] 00_104 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXPMARESET_TIME[1] 01_104 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXPMARESET_TIME[2] 00_105 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXPMARESET_TIME[3] 01_105 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXPMARESET_TIME[4] 00_106 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXPRBS_ERR_LOOPBACK[0] 00_136 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXSLIDE_AUTO_WAIT[0] 00_520 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXSLIDE_AUTO_WAIT[1] 01_520 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXSLIDE_AUTO_WAIT[2] 00_521 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXSLIDE_AUTO_WAIT[3] 01_521 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXSLIDE_MODE.AUTO 00_519 !01_519 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXSLIDE_MODE.PCS !00_519 01_519 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXSLIDE_MODE.PMA 00_519 01_519 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXSYNC_MULTILANE[0] 00_133 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXSYNC_OVRD[0] 01_135 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXSYNC_SKIP_DA[0] 01_134 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.SAS_MAX_COM[0] 00_171 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.SAS_MAX_COM[1] 01_171 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.SAS_MAX_COM[2] 00_172 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.SAS_MAX_COM[3] 01_172 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.SAS_MAX_COM[4] 00_173 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.SAS_MAX_COM[5] 01_173 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.SAS_MAX_COM[6] 00_174 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.SAS_MIN_COM[0] 01_156 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.SAS_MIN_COM[1] 00_157 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.SAS_MIN_COM[2] 01_157 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.SAS_MIN_COM[3] 00_158 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.SAS_MIN_COM[4] 01_158 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.SAS_MIN_COM[5] 00_159 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.SATA_BURST_SEQ_LEN[0] 00_150 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.SATA_BURST_SEQ_LEN[1] 01_150 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.SATA_BURST_SEQ_LEN[2] 00_151 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.SATA_BURST_SEQ_LEN[3] 01_151 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.SATA_BURST_VAL[0] 01_147 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.SATA_BURST_VAL[1] 00_148 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.SATA_BURST_VAL[2] 01_148 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.SATA_EIDLE_VAL[0] 00_152 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.SATA_EIDLE_VAL[1] 01_152 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.SATA_EIDLE_VAL[2] 00_153 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.SATA_MAX_BURST[0] 00_168 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.SATA_MAX_BURST[1] 01_168 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.SATA_MAX_BURST[2] 00_169 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.SATA_MAX_BURST[3] 01_169 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.SATA_MAX_BURST[4] 00_170 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.SATA_MAX_BURST[5] 01_170 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.SATA_MAX_INIT[0] 00_176 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.SATA_MAX_INIT[1] 01_176 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.SATA_MAX_INIT[2] 00_177 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.SATA_MAX_INIT[3] 01_177 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.SATA_MAX_INIT[4] 00_178 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.SATA_MAX_INIT[5] 01_178 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.SATA_MAX_WAKE[0] 00_179 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.SATA_MAX_WAKE[1] 01_179 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.SATA_MAX_WAKE[2] 00_180 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.SATA_MAX_WAKE[3] 01_180 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.SATA_MAX_WAKE[4] 00_181 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.SATA_MAX_WAKE[5] 01_181 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.SATA_MIN_BURST[0] 01_153 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.SATA_MIN_BURST[1] 00_154 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.SATA_MIN_BURST[2] 01_154 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.SATA_MIN_BURST[3] 00_155 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.SATA_MIN_BURST[4] 01_155 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.SATA_MIN_BURST[5] 00_156 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.SATA_MIN_INIT[0] 00_160 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.SATA_MIN_INIT[1] 01_160 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.SATA_MIN_INIT[2] 00_161 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.SATA_MIN_INIT[3] 01_161 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.SATA_MIN_INIT[4] 00_162 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.SATA_MIN_INIT[5] 01_162 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.SATA_MIN_WAKE[0] 00_163 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.SATA_MIN_WAKE[1] 01_163 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.SATA_MIN_WAKE[2] 00_164 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.SATA_MIN_WAKE[3] 01_164 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.SATA_MIN_WAKE[4] 00_165 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.SATA_MIN_WAKE[5] 01_165 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.SATA_PLL_CFG.VCO_1500MHZ 02_55 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.SATA_PLL_CFG.VCO_750MHZ 03_55 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.SHOW_REALIGN_COMMA 01_522 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TERM_RCAL_CFG[0] 02_136 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TERM_RCAL_CFG[1] 03_136 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TERM_RCAL_CFG[2] 02_137 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TERM_RCAL_CFG[3] 03_137 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TERM_RCAL_CFG[4] 02_138 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TERM_RCAL_CFG[5] 03_138 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TERM_RCAL_CFG[6] 02_139 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TERM_RCAL_CFG[7] 03_139 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TERM_RCAL_CFG[8] 02_140 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TERM_RCAL_CFG[9] 03_140 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TERM_RCAL_CFG[10] 02_141 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TERM_RCAL_CFG[11] 03_141 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TERM_RCAL_CFG[12] 02_142 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TERM_RCAL_CFG[13] 03_142 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TERM_RCAL_CFG[14] 02_143 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TERM_RCAL_OVRD[0] 03_150 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TERM_RCAL_OVRD[1] 02_151 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TERM_RCAL_OVRD[2] 03_151 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TRANS_TIME_RATE[0] 00_192 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TRANS_TIME_RATE[1] 01_192 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TRANS_TIME_RATE[2] 00_193 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TRANS_TIME_RATE[3] 01_193 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TRANS_TIME_RATE[4] 00_194 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TRANS_TIME_RATE[5] 01_194 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TRANS_TIME_RATE[6] 00_195 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TRANS_TIME_RATE[7] 01_195 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TST_RSV[0] 02_504 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TST_RSV[1] 03_504 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TST_RSV[2] 02_505 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TST_RSV[3] 03_505 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TST_RSV[4] 02_506 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TST_RSV[5] 03_506 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TST_RSV[6] 02_507 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TST_RSV[7] 03_507 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TST_RSV[8] 02_508 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TST_RSV[9] 03_508 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TST_RSV[10] 02_509 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TST_RSV[11] 03_509 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TST_RSV[12] 02_510 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TST_RSV[13] 03_510 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TST_RSV[14] 02_511 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TST_RSV[15] 03_511 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TST_RSV[16] 02_512 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TST_RSV[17] 03_512 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TST_RSV[18] 02_513 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TST_RSV[19] 03_513 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TST_RSV[20] 02_514 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TST_RSV[21] 03_514 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TST_RSV[22] 02_515 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TST_RSV[23] 03_515 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TST_RSV[24] 02_516 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TST_RSV[25] 03_516 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TST_RSV[26] 02_517 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TST_RSV[27] 03_517 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TST_RSV[28] 02_518 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TST_RSV[29] 03_518 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TST_RSV[30] 02_519 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TST_RSV[31] 03_519 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_CLKMUX_EN[0] 03_128 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_DATA_WIDTH[0] 02_152 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_DATA_WIDTH[1] 03_152 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_DATA_WIDTH[2] 02_153 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_DRIVE_MODE.PIPE 00_200 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_EIDLE_ASSERT_DELAY[0] 00_203 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_EIDLE_ASSERT_DELAY[1] 01_203 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_EIDLE_ASSERT_DELAY[2] 00_204 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_EIDLE_DEASSERT_DELAY[0] 01_204 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_EIDLE_DEASSERT_DELAY[1] 00_205 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_EIDLE_DEASSERT_DELAY[2] 01_205 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_LOOPBACK_DRIVE_HIZ 01_202 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_MAINCURSOR_SEL[0] 03_289 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_0[0] 02_232 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_0[1] 03_232 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_0[2] 02_233 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_0[3] 03_233 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_0[4] 02_234 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_0[5] 03_234 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_0[6] 02_235 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_1[0] 02_236 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_1[1] 03_236 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_1[2] 02_237 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_1[3] 03_237 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_1[4] 02_238 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_1[5] 03_238 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_1[6] 02_239 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_2[0] 02_240 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_2[1] 03_240 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_2[2] 02_241 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_2[3] 03_241 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_2[4] 02_242 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_2[5] 03_242 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_2[6] 02_243 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_3[0] 02_244 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_3[1] 03_244 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_3[2] 02_245 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_3[3] 03_245 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_3[4] 02_246 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_3[5] 03_246 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_3[6] 02_247 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_4[0] 02_248 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_4[1] 03_248 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_4[2] 02_249 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_4[3] 03_249 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_4[4] 02_250 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_4[5] 03_250 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_4[6] 02_251 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_0[0] 02_252 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_0[1] 03_252 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_0[2] 02_253 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_0[3] 03_253 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_0[4] 02_254 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_0[5] 03_254 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_0[6] 02_255 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_1[0] 02_256 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_1[1] 03_256 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_1[2] 02_257 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_1[3] 03_257 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_1[4] 02_258 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_1[5] 03_258 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_1[6] 02_259 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_2[0] 02_260 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_2[1] 03_260 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_2[2] 02_261 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_2[3] 03_261 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_2[4] 02_262 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_2[5] 03_262 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_2[6] 02_263 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_3[0] 02_264 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_3[1] 03_264 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_3[2] 02_265 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_3[3] 03_265 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_3[4] 02_266 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_3[5] 03_266 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_3[6] 02_267 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_4[0] 02_268 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_4[1] 03_268 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_4[2] 02_269 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_4[3] 03_269 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_4[4] 02_270 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_4[5] 03_270 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_4[6] 02_271 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_PREDRIVER_MODE[0] 00_206 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_RXDETECT_CFG[0] 02_296 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_RXDETECT_CFG[1] 03_296 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_RXDETECT_CFG[2] 02_297 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_RXDETECT_CFG[3] 03_297 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_RXDETECT_CFG[4] 02_298 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_RXDETECT_CFG[5] 03_298 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_RXDETECT_CFG[6] 02_299 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_RXDETECT_CFG[7] 03_299 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_RXDETECT_CFG[8] 02_300 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_RXDETECT_CFG[9] 03_300 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_RXDETECT_CFG[10] 02_301 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_RXDETECT_CFG[11] 03_301 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_RXDETECT_CFG[12] 02_302 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_RXDETECT_CFG[13] 03_302 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_RXDETECT_REF[0] 02_292 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_RXDETECT_REF[1] 03_292 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_RXDETECT_REF[2] 02_293 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_XCLK_SEL.TXUSR 03_11 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_CLK25_DIV[0] 02_144 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_CLK25_DIV[1] 03_144 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_CLK25_DIV[2] 02_145 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_CLK25_DIV[3] 03_145 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_CLK25_DIV[4] 02_146 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_DEEMPH0[0] 02_272 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_DEEMPH0[1] 03_272 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_DEEMPH0[2] 02_273 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_DEEMPH0[3] 03_273 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_DEEMPH0[4] 02_274 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_DEEMPH0[5] 03_274 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_DEEMPH1[0] 02_276 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_DEEMPH1[1] 03_276 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_DEEMPH1[2] 02_277 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_DEEMPH1[3] 03_277 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_DEEMPH1[4] 02_278 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_DEEMPH1[5] 03_278 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXBUF_EN 00_231 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXBUF_RESET_ON_RATE_CHANGE 01_231 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXDLY_CFG[0] 02_80 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXDLY_CFG[1] 03_80 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXDLY_CFG[2] 02_81 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXDLY_CFG[3] 03_81 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXDLY_CFG[4] 02_82 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXDLY_CFG[5] 03_82 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXDLY_CFG[6] 02_83 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXDLY_CFG[7] 03_83 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXDLY_CFG[8] 02_84 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXDLY_CFG[9] 03_84 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXDLY_CFG[10] 02_85 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXDLY_CFG[11] 03_85 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXDLY_CFG[12] 02_86 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXDLY_CFG[13] 03_86 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXDLY_CFG[14] 02_87 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXDLY_CFG[15] 03_87 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXDLY_LCFG[0] 02_568 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXDLY_LCFG[1] 03_568 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXDLY_LCFG[2] 02_569 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXDLY_LCFG[3] 03_569 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXDLY_LCFG[4] 02_570 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXDLY_LCFG[5] 03_570 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXDLY_LCFG[6] 02_571 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXDLY_LCFG[7] 03_571 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXDLY_LCFG[8] 02_572 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXDLY_TAP_CFG[0] 02_88 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXDLY_TAP_CFG[1] 03_88 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXDLY_TAP_CFG[2] 02_89 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXDLY_TAP_CFG[3] 03_89 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXDLY_TAP_CFG[4] 02_90 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXDLY_TAP_CFG[5] 03_90 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXDLY_TAP_CFG[6] 02_91 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXDLY_TAP_CFG[7] 03_91 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXDLY_TAP_CFG[8] 02_92 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXDLY_TAP_CFG[9] 03_92 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXDLY_TAP_CFG[10] 02_93 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXDLY_TAP_CFG[11] 03_93 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXDLY_TAP_CFG[12] 02_94 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXDLY_TAP_CFG[13] 03_94 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXDLY_TAP_CFG[14] 02_95 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXDLY_TAP_CFG[15] 03_95 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXGEARBOX_EN 01_226 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXOOB_CFG[0] 03_20 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXOUT_DIV[0] 02_386 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXOUT_DIV[1] 03_386 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPCSRESET_TIME[0] 01_130 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPCSRESET_TIME[1] 00_131 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPCSRESET_TIME[2] 01_131 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPCSRESET_TIME[3] 00_132 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPCSRESET_TIME[4] 01_132 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPH_CFG[0] 02_96 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPH_CFG[1] 03_96 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPH_CFG[2] 02_97 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPH_CFG[3] 03_97 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPH_CFG[4] 02_98 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPH_CFG[5] 03_98 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPH_CFG[6] 02_99 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPH_CFG[7] 03_99 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPH_CFG[8] 02_100 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPH_CFG[9] 03_100 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPH_CFG[10] 02_101 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPH_CFG[11] 03_101 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPH_CFG[12] 02_102 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPH_CFG[13] 03_102 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPH_CFG[14] 02_103 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPH_CFG[15] 03_103 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPH_MONITOR_SEL[0] 02_108 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPH_MONITOR_SEL[1] 03_108 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPH_MONITOR_SEL[2] 02_109 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPH_MONITOR_SEL[3] 03_109 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPH_MONITOR_SEL[4] 02_110 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[0] 02_64 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[1] 03_64 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[2] 02_65 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[3] 03_65 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[4] 02_66 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[5] 03_66 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[6] 02_67 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[7] 03_67 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[8] 02_68 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[9] 03_68 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[10] 02_69 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[11] 03_69 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[12] 02_70 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[13] 03_70 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[14] 02_71 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[15] 03_71 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[16] 02_72 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[17] 03_72 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[18] 02_73 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[19] 03_73 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[20] 02_74 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[21] 03_74 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[22] 02_75 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[23] 03_75 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPI_GREY_SEL[0] 03_498 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPI_INVSTROBE_SEL[0] 02_498 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPI_PPM_CFG[0] 02_488 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPI_PPM_CFG[1] 03_488 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPI_PPM_CFG[2] 02_489 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPI_PPM_CFG[3] 03_489 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPI_PPM_CFG[4] 02_490 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPI_PPM_CFG[5] 03_490 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPI_PPM_CFG[6] 02_491 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPI_PPM_CFG[7] 03_491 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPI_PPMCLK_SEL.TXUSRCLK2 03_497 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPI_SYNFREQ_PPM[0] 02_496 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPI_SYNFREQ_PPM[1] 03_496 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPI_SYNFREQ_PPM[2] 02_497 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPI_CFG0[0] 02_40 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPI_CFG0[1] 03_40 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPI_CFG1[0] 02_41 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPI_CFG1[1] 03_41 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPI_CFG2[0] 02_42 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPI_CFG2[1] 03_42 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPI_CFG3[0] 02_43 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPI_CFG4[0] 03_43 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPI_CFG5[0] 02_44 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPI_CFG5[1] 03_44 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPI_CFG5[2] 02_45 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPMARESET_TIME[0] 00_128 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPMARESET_TIME[1] 01_128 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPMARESET_TIME[2] 00_129 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPMARESET_TIME[3] 01_129 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPMARESET_TIME[4] 00_130 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXSYNC_MULTILANE[0] 01_133 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXSYNC_OVRD[0] 00_135 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXSYNC_SKIP_DA[0] 00_134 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.UCODEER_CLR[0] 01_00 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.USE_PCS_CLK_PHASE_SEL[0] 02_463 diff --git a/artix7/segbits_gtp_channel_3_mid_left.origin_info.db b/artix7/segbits_gtp_channel_3_mid_left.origin_info.db index 66d9271..f4462d4 100644 --- a/artix7/segbits_gtp_channel_3_mid_left.origin_info.db +++ b/artix7/segbits_gtp_channel_3_mid_left.origin_info.db @@ -1,1627 +1,1627 @@ -GTP_CHANNEL_3_MID_LEFT.GTPE2.ACJTAG_DEBUG_MODE[0] origin:064-gtp-channel-conf 00_07 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ACJTAG_MODE[0] origin:064-gtp-channel-conf 01_06 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ACJTAG_RESET[0] origin:064-gtp-channel-conf 01_07 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ADAPT_CFG0[0] origin:064-gtp-channel-conf 02_464 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ADAPT_CFG0[1] origin:064-gtp-channel-conf 03_464 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ADAPT_CFG0[2] origin:064-gtp-channel-conf 02_465 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ADAPT_CFG0[3] origin:064-gtp-channel-conf 03_465 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ADAPT_CFG0[4] origin:064-gtp-channel-conf 02_466 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ADAPT_CFG0[5] origin:064-gtp-channel-conf 03_466 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ADAPT_CFG0[6] origin:064-gtp-channel-conf 02_467 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ADAPT_CFG0[7] origin:064-gtp-channel-conf 03_467 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ADAPT_CFG0[8] origin:064-gtp-channel-conf 02_468 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ADAPT_CFG0[9] origin:064-gtp-channel-conf 03_468 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ADAPT_CFG0[10] origin:064-gtp-channel-conf 02_469 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ADAPT_CFG0[11] origin:064-gtp-channel-conf 03_469 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ADAPT_CFG0[12] origin:064-gtp-channel-conf 02_470 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ADAPT_CFG0[13] origin:064-gtp-channel-conf 03_470 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ADAPT_CFG0[14] origin:064-gtp-channel-conf 02_471 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ADAPT_CFG0[15] origin:064-gtp-channel-conf 03_471 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ADAPT_CFG0[16] origin:064-gtp-channel-conf 02_472 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ADAPT_CFG0[17] origin:064-gtp-channel-conf 03_472 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ADAPT_CFG0[18] origin:064-gtp-channel-conf 02_473 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ADAPT_CFG0[19] origin:064-gtp-channel-conf 03_473 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ALIGN_COMMA_DOUBLE origin:064-gtp-channel-conf 00_522 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ALIGN_COMMA_ENABLE[0] origin:064-gtp-channel-conf 00_496 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ALIGN_COMMA_ENABLE[1] origin:064-gtp-channel-conf 01_496 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ALIGN_COMMA_ENABLE[2] origin:064-gtp-channel-conf 00_497 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ALIGN_COMMA_ENABLE[3] origin:064-gtp-channel-conf 01_497 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ALIGN_COMMA_ENABLE[4] origin:064-gtp-channel-conf 00_498 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ALIGN_COMMA_ENABLE[5] origin:064-gtp-channel-conf 01_498 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ALIGN_COMMA_ENABLE[6] origin:064-gtp-channel-conf 00_499 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ALIGN_COMMA_ENABLE[7] origin:064-gtp-channel-conf 01_499 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ALIGN_COMMA_ENABLE[8] origin:064-gtp-channel-conf 00_500 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ALIGN_COMMA_ENABLE[9] origin:064-gtp-channel-conf 01_500 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ALIGN_COMMA_WORD[0] origin:064-gtp-channel-conf 01_526 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ALIGN_COMMA_WORD[1] origin:064-gtp-channel-conf 00_527 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ALIGN_MCOMMA_DET origin:064-gtp-channel-conf 00_523 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ALIGN_MCOMMA_VALUE[0] origin:064-gtp-channel-conf 00_504 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ALIGN_MCOMMA_VALUE[1] origin:064-gtp-channel-conf 01_504 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ALIGN_MCOMMA_VALUE[2] origin:064-gtp-channel-conf 00_505 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ALIGN_MCOMMA_VALUE[3] origin:064-gtp-channel-conf 01_505 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ALIGN_MCOMMA_VALUE[4] origin:064-gtp-channel-conf 00_506 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ALIGN_MCOMMA_VALUE[5] origin:064-gtp-channel-conf 01_506 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ALIGN_MCOMMA_VALUE[6] origin:064-gtp-channel-conf 00_507 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ALIGN_MCOMMA_VALUE[7] origin:064-gtp-channel-conf 01_507 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ALIGN_MCOMMA_VALUE[8] origin:064-gtp-channel-conf 00_508 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ALIGN_MCOMMA_VALUE[9] origin:064-gtp-channel-conf 01_508 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ALIGN_PCOMMA_DET origin:064-gtp-channel-conf 01_523 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ALIGN_PCOMMA_VALUE[0] origin:064-gtp-channel-conf 00_512 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ALIGN_PCOMMA_VALUE[1] origin:064-gtp-channel-conf 01_512 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ALIGN_PCOMMA_VALUE[2] origin:064-gtp-channel-conf 00_513 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ALIGN_PCOMMA_VALUE[3] origin:064-gtp-channel-conf 01_513 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ALIGN_PCOMMA_VALUE[4] origin:064-gtp-channel-conf 00_514 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ALIGN_PCOMMA_VALUE[5] origin:064-gtp-channel-conf 01_514 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ALIGN_PCOMMA_VALUE[6] origin:064-gtp-channel-conf 00_515 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ALIGN_PCOMMA_VALUE[7] origin:064-gtp-channel-conf 01_515 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ALIGN_PCOMMA_VALUE[8] origin:064-gtp-channel-conf 00_516 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ALIGN_PCOMMA_VALUE[9] origin:064-gtp-channel-conf 01_516 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CBCC_DATA_SOURCE_SEL.DECODED origin:064-gtp-channel-conf 01_661 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CFOK_CFG[0] origin:064-gtp-channel-conf 02_392 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CFOK_CFG[1] origin:064-gtp-channel-conf 03_392 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CFOK_CFG[2] origin:064-gtp-channel-conf 02_393 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CFOK_CFG[3] origin:064-gtp-channel-conf 03_393 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CFOK_CFG[4] origin:064-gtp-channel-conf 02_394 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CFOK_CFG[5] origin:064-gtp-channel-conf 03_394 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CFOK_CFG[6] origin:064-gtp-channel-conf 02_395 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CFOK_CFG[7] origin:064-gtp-channel-conf 03_395 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CFOK_CFG[8] origin:064-gtp-channel-conf 02_396 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CFOK_CFG[9] origin:064-gtp-channel-conf 03_396 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CFOK_CFG[10] origin:064-gtp-channel-conf 02_397 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CFOK_CFG[11] origin:064-gtp-channel-conf 03_397 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CFOK_CFG[12] origin:064-gtp-channel-conf 02_398 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CFOK_CFG[13] origin:064-gtp-channel-conf 03_398 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CFOK_CFG[14] origin:064-gtp-channel-conf 02_399 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CFOK_CFG[15] origin:064-gtp-channel-conf 03_399 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CFOK_CFG[16] origin:064-gtp-channel-conf 02_400 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CFOK_CFG[17] origin:064-gtp-channel-conf 03_400 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CFOK_CFG[18] origin:064-gtp-channel-conf 02_401 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CFOK_CFG[19] origin:064-gtp-channel-conf 03_401 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CFOK_CFG[20] origin:064-gtp-channel-conf 02_402 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CFOK_CFG[21] origin:064-gtp-channel-conf 03_402 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CFOK_CFG[22] origin:064-gtp-channel-conf 02_403 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CFOK_CFG[23] origin:064-gtp-channel-conf 03_403 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CFOK_CFG[24] origin:064-gtp-channel-conf 02_404 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CFOK_CFG[25] origin:064-gtp-channel-conf 03_404 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CFOK_CFG[26] origin:064-gtp-channel-conf 02_405 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CFOK_CFG[27] origin:064-gtp-channel-conf 03_405 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CFOK_CFG[28] origin:064-gtp-channel-conf 02_406 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CFOK_CFG[29] origin:064-gtp-channel-conf 03_406 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CFOK_CFG[30] origin:064-gtp-channel-conf 02_407 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CFOK_CFG[31] origin:064-gtp-channel-conf 03_407 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CFOK_CFG[32] origin:064-gtp-channel-conf 02_408 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CFOK_CFG[33] origin:064-gtp-channel-conf 03_408 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CFOK_CFG[34] origin:064-gtp-channel-conf 02_409 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CFOK_CFG[35] origin:064-gtp-channel-conf 03_409 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CFOK_CFG[36] origin:064-gtp-channel-conf 02_410 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CFOK_CFG[37] origin:064-gtp-channel-conf 03_410 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CFOK_CFG[38] origin:064-gtp-channel-conf 02_411 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CFOK_CFG[39] origin:064-gtp-channel-conf 03_411 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CFOK_CFG[40] origin:064-gtp-channel-conf 02_412 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CFOK_CFG[41] origin:064-gtp-channel-conf 03_412 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CFOK_CFG[42] origin:064-gtp-channel-conf 02_413 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CFOK_CFG2[0] origin:064-gtp-channel-conf 02_459 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CFOK_CFG2[1] origin:064-gtp-channel-conf 03_459 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CFOK_CFG2[2] origin:064-gtp-channel-conf 02_460 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CFOK_CFG2[3] origin:064-gtp-channel-conf 03_460 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CFOK_CFG2[4] origin:064-gtp-channel-conf 02_461 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CFOK_CFG2[5] origin:064-gtp-channel-conf 03_461 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CFOK_CFG2[6] origin:064-gtp-channel-conf 02_462 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CFOK_CFG3[0] origin:064-gtp-channel-conf 02_416 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CFOK_CFG3[1] origin:064-gtp-channel-conf 03_416 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CFOK_CFG3[2] origin:064-gtp-channel-conf 02_417 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CFOK_CFG3[3] origin:064-gtp-channel-conf 03_417 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CFOK_CFG3[4] origin:064-gtp-channel-conf 02_418 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CFOK_CFG3[5] origin:064-gtp-channel-conf 03_418 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CFOK_CFG3[6] origin:064-gtp-channel-conf 02_419 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CFOK_CFG4[0] origin:064-gtp-channel-conf 03_438 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CFOK_CFG5[0] origin:064-gtp-channel-conf 02_429 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CFOK_CFG5[1] origin:064-gtp-channel-conf 03_429 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CFOK_CFG6[0] origin:064-gtp-channel-conf 03_436 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CFOK_CFG6[1] origin:064-gtp-channel-conf 02_437 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CFOK_CFG6[2] origin:064-gtp-channel-conf 03_437 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CFOK_CFG6[3] origin:064-gtp-channel-conf 02_438 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_KEEP_ALIGN origin:064-gtp-channel-conf 01_631 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_MAX_SKEW[0] origin:064-gtp-channel-conf 00_670 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_MAX_SKEW[1] origin:064-gtp-channel-conf 01_670 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_MAX_SKEW[2] origin:064-gtp-channel-conf 00_671 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_MAX_SKEW[3] origin:064-gtp-channel-conf 01_671 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_1[0] origin:064-gtp-channel-conf 00_608 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_1[1] origin:064-gtp-channel-conf 01_608 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_1[2] origin:064-gtp-channel-conf 00_609 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_1[3] origin:064-gtp-channel-conf 01_609 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_1[4] origin:064-gtp-channel-conf 00_610 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_1[5] origin:064-gtp-channel-conf 01_610 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_1[6] origin:064-gtp-channel-conf 00_611 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_1[7] origin:064-gtp-channel-conf 01_611 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_1[8] origin:064-gtp-channel-conf 00_612 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_1[9] origin:064-gtp-channel-conf 01_612 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_2[0] origin:064-gtp-channel-conf 00_616 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_2[1] origin:064-gtp-channel-conf 01_616 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_2[2] origin:064-gtp-channel-conf 00_617 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_2[3] origin:064-gtp-channel-conf 01_617 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_2[4] origin:064-gtp-channel-conf 00_618 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_2[5] origin:064-gtp-channel-conf 01_618 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_2[6] origin:064-gtp-channel-conf 00_619 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_2[7] origin:064-gtp-channel-conf 01_619 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_2[8] origin:064-gtp-channel-conf 00_620 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_2[9] origin:064-gtp-channel-conf 01_620 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_3[0] origin:064-gtp-channel-conf 00_624 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_3[1] origin:064-gtp-channel-conf 01_624 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_3[2] origin:064-gtp-channel-conf 00_625 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_3[3] origin:064-gtp-channel-conf 01_625 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_3[4] origin:064-gtp-channel-conf 00_626 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_3[5] origin:064-gtp-channel-conf 01_626 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_3[6] origin:064-gtp-channel-conf 00_627 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_3[7] origin:064-gtp-channel-conf 01_627 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_3[8] origin:064-gtp-channel-conf 00_628 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_3[9] origin:064-gtp-channel-conf 01_628 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_4[0] origin:064-gtp-channel-conf 00_632 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_4[1] origin:064-gtp-channel-conf 01_632 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_4[2] origin:064-gtp-channel-conf 00_633 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_4[3] origin:064-gtp-channel-conf 01_633 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_4[4] origin:064-gtp-channel-conf 00_634 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_4[5] origin:064-gtp-channel-conf 01_634 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_4[6] origin:064-gtp-channel-conf 00_635 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_4[7] origin:064-gtp-channel-conf 01_635 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_4[8] origin:064-gtp-channel-conf 00_636 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_4[9] origin:064-gtp-channel-conf 01_636 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_ENABLE[0] origin:064-gtp-channel-conf 00_614 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_ENABLE[1] origin:064-gtp-channel-conf 01_614 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_ENABLE[2] origin:064-gtp-channel-conf 00_615 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_1_ENABLE[3] origin:064-gtp-channel-conf 01_615 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_1[0] origin:064-gtp-channel-conf 00_640 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_1[1] origin:064-gtp-channel-conf 01_640 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_1[2] origin:064-gtp-channel-conf 00_641 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_1[3] origin:064-gtp-channel-conf 01_641 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_1[4] origin:064-gtp-channel-conf 00_642 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_1[5] origin:064-gtp-channel-conf 01_642 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_1[6] origin:064-gtp-channel-conf 00_643 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_1[7] origin:064-gtp-channel-conf 01_643 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_1[8] origin:064-gtp-channel-conf 00_644 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_1[9] origin:064-gtp-channel-conf 01_644 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_2[0] origin:064-gtp-channel-conf 00_648 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_2[1] origin:064-gtp-channel-conf 01_648 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_2[2] origin:064-gtp-channel-conf 00_649 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_2[3] origin:064-gtp-channel-conf 01_649 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_2[4] origin:064-gtp-channel-conf 00_650 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_2[5] origin:064-gtp-channel-conf 01_650 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_2[6] origin:064-gtp-channel-conf 00_651 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_2[7] origin:064-gtp-channel-conf 01_651 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_2[8] origin:064-gtp-channel-conf 00_652 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_2[9] origin:064-gtp-channel-conf 01_652 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_3[0] origin:064-gtp-channel-conf 00_656 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_3[1] origin:064-gtp-channel-conf 01_656 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_3[2] origin:064-gtp-channel-conf 00_657 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_3[3] origin:064-gtp-channel-conf 01_657 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_3[4] origin:064-gtp-channel-conf 00_658 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_3[5] origin:064-gtp-channel-conf 01_658 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_3[6] origin:064-gtp-channel-conf 00_659 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_3[7] origin:064-gtp-channel-conf 01_659 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_3[8] origin:064-gtp-channel-conf 00_660 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_3[9] origin:064-gtp-channel-conf 01_660 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_4[0] origin:064-gtp-channel-conf 00_664 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_4[1] origin:064-gtp-channel-conf 01_664 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_4[2] origin:064-gtp-channel-conf 00_665 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_4[3] origin:064-gtp-channel-conf 01_665 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_4[4] origin:064-gtp-channel-conf 00_666 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_4[5] origin:064-gtp-channel-conf 01_666 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_4[6] origin:064-gtp-channel-conf 00_667 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_4[7] origin:064-gtp-channel-conf 01_667 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_4[8] origin:064-gtp-channel-conf 00_668 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_4[9] origin:064-gtp-channel-conf 01_668 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_ENABLE[0] origin:064-gtp-channel-conf 00_646 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_ENABLE[1] origin:064-gtp-channel-conf 01_646 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_ENABLE[2] origin:064-gtp-channel-conf 00_647 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_ENABLE[3] origin:064-gtp-channel-conf 01_647 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_2_USE origin:064-gtp-channel-conf 01_645 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_LEN[0] origin:064-gtp-channel-conf 00_623 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CHAN_BOND_SEQ_LEN[1] origin:064-gtp-channel-conf 01_623 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COMMON_SWING[0] origin:064-gtp-channel-conf 03_311 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_KEEP_IDLE origin:064-gtp-channel-conf 00_591 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_MAX_LAT[0] origin:064-gtp-channel-conf 00_557 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_MAX_LAT[1] origin:064-gtp-channel-conf 01_557 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_MAX_LAT[2] origin:064-gtp-channel-conf 00_558 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_MAX_LAT[3] origin:064-gtp-channel-conf 01_558 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_MAX_LAT[4] origin:064-gtp-channel-conf 00_559 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_MAX_LAT[5] origin:064-gtp-channel-conf 01_559 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_MIN_LAT[0] origin:064-gtp-channel-conf 00_565 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_MIN_LAT[1] origin:064-gtp-channel-conf 01_565 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_MIN_LAT[2] origin:064-gtp-channel-conf 00_566 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_MIN_LAT[3] origin:064-gtp-channel-conf 01_566 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_MIN_LAT[4] origin:064-gtp-channel-conf 00_567 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_MIN_LAT[5] origin:064-gtp-channel-conf 01_567 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_PRECEDENCE origin:064-gtp-channel-conf 00_590 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_REPEAT_WAIT[0] origin:064-gtp-channel-conf 00_573 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_REPEAT_WAIT[1] origin:064-gtp-channel-conf 01_573 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_REPEAT_WAIT[2] origin:064-gtp-channel-conf 00_574 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_REPEAT_WAIT[3] origin:064-gtp-channel-conf 01_574 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_REPEAT_WAIT[4] origin:064-gtp-channel-conf 00_575 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_1_1[0] origin:064-gtp-channel-conf 00_544 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_1_1[1] origin:064-gtp-channel-conf 01_544 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_1_1[2] origin:064-gtp-channel-conf 00_545 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_1_1[3] origin:064-gtp-channel-conf 01_545 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_1_1[4] origin:064-gtp-channel-conf 00_546 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_1_1[5] origin:064-gtp-channel-conf 01_546 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_1_1[6] origin:064-gtp-channel-conf 00_547 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_1_1[7] origin:064-gtp-channel-conf 01_547 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_1_1[8] origin:064-gtp-channel-conf 00_548 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_1_1[9] origin:064-gtp-channel-conf 01_548 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_1_2[0] origin:064-gtp-channel-conf 00_552 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_1_2[1] origin:064-gtp-channel-conf 01_552 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_1_2[2] origin:064-gtp-channel-conf 00_553 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_1_2[3] origin:064-gtp-channel-conf 01_553 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_1_2[4] origin:064-gtp-channel-conf 00_554 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_1_2[5] origin:064-gtp-channel-conf 01_554 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_1_2[6] origin:064-gtp-channel-conf 00_555 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_1_2[7] origin:064-gtp-channel-conf 01_555 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_1_2[8] origin:064-gtp-channel-conf 00_556 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_1_2[9] origin:064-gtp-channel-conf 01_556 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_1_3[0] origin:064-gtp-channel-conf 00_560 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_1_3[1] origin:064-gtp-channel-conf 01_560 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_1_3[2] origin:064-gtp-channel-conf 00_561 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_1_3[3] origin:064-gtp-channel-conf 01_561 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_1_3[4] origin:064-gtp-channel-conf 00_562 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_1_3[5] origin:064-gtp-channel-conf 01_562 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_1_3[6] origin:064-gtp-channel-conf 00_563 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_1_3[7] origin:064-gtp-channel-conf 01_563 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_1_3[8] origin:064-gtp-channel-conf 00_564 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_1_3[9] origin:064-gtp-channel-conf 01_564 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_1_4[0] origin:064-gtp-channel-conf 00_568 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_1_4[1] origin:064-gtp-channel-conf 01_568 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_1_4[2] origin:064-gtp-channel-conf 00_569 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_1_4[3] origin:064-gtp-channel-conf 01_569 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_1_4[4] origin:064-gtp-channel-conf 00_570 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_1_4[5] origin:064-gtp-channel-conf 01_570 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_1_4[6] origin:064-gtp-channel-conf 00_571 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_1_4[7] origin:064-gtp-channel-conf 01_571 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_1_4[8] origin:064-gtp-channel-conf 00_572 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_1_4[9] origin:064-gtp-channel-conf 01_572 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_1_ENABLE[0] origin:064-gtp-channel-conf 00_549 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_1_ENABLE[1] origin:064-gtp-channel-conf 01_549 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_1_ENABLE[2] origin:064-gtp-channel-conf 00_550 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_1_ENABLE[3] origin:064-gtp-channel-conf 01_550 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_2_1[0] origin:064-gtp-channel-conf 00_576 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_2_1[1] origin:064-gtp-channel-conf 01_576 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_2_1[2] origin:064-gtp-channel-conf 00_577 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_2_1[3] origin:064-gtp-channel-conf 01_577 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_2_1[4] origin:064-gtp-channel-conf 00_578 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_2_1[5] origin:064-gtp-channel-conf 01_578 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_2_1[6] origin:064-gtp-channel-conf 00_579 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_2_1[7] origin:064-gtp-channel-conf 01_579 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_2_1[8] origin:064-gtp-channel-conf 00_580 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_2_1[9] origin:064-gtp-channel-conf 01_580 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_2_2[0] origin:064-gtp-channel-conf 00_584 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_2_2[1] origin:064-gtp-channel-conf 01_584 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_2_2[2] origin:064-gtp-channel-conf 00_585 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_2_2[3] origin:064-gtp-channel-conf 01_585 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_2_2[4] origin:064-gtp-channel-conf 00_586 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_2_2[5] origin:064-gtp-channel-conf 01_586 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_2_2[6] origin:064-gtp-channel-conf 00_587 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_2_2[7] origin:064-gtp-channel-conf 01_587 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_2_2[8] origin:064-gtp-channel-conf 00_588 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_2_2[9] origin:064-gtp-channel-conf 01_588 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_2_3[0] origin:064-gtp-channel-conf 00_592 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_2_3[1] origin:064-gtp-channel-conf 01_592 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_2_3[2] origin:064-gtp-channel-conf 00_593 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_2_3[3] origin:064-gtp-channel-conf 01_593 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_2_3[4] origin:064-gtp-channel-conf 00_594 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_2_3[5] origin:064-gtp-channel-conf 01_594 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_2_3[6] origin:064-gtp-channel-conf 00_595 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_2_3[7] origin:064-gtp-channel-conf 01_595 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_2_3[8] origin:064-gtp-channel-conf 00_596 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_2_3[9] origin:064-gtp-channel-conf 01_596 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_2_4[0] origin:064-gtp-channel-conf 00_600 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_2_4[1] origin:064-gtp-channel-conf 01_600 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_2_4[2] origin:064-gtp-channel-conf 00_601 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_2_4[3] origin:064-gtp-channel-conf 01_601 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_2_4[4] origin:064-gtp-channel-conf 00_602 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_2_4[5] origin:064-gtp-channel-conf 01_602 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_2_4[6] origin:064-gtp-channel-conf 00_603 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_2_4[7] origin:064-gtp-channel-conf 01_603 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_2_4[8] origin:064-gtp-channel-conf 00_604 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_2_4[9] origin:064-gtp-channel-conf 01_604 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_2_ENABLE[0] origin:064-gtp-channel-conf 00_581 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_2_ENABLE[1] origin:064-gtp-channel-conf 01_581 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_2_ENABLE[2] origin:064-gtp-channel-conf 00_582 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_2_ENABLE[3] origin:064-gtp-channel-conf 01_582 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_2_USE origin:064-gtp-channel-conf 00_583 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_LEN[0] origin:064-gtp-channel-conf 00_589 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_COR_SEQ_LEN[1] origin:064-gtp-channel-conf 01_589 -GTP_CHANNEL_3_MID_LEFT.GTPE2.CLK_CORRECT_USE origin:064-gtp-channel-conf 00_551 -GTP_CHANNEL_3_MID_LEFT.GTPE2.DEC_MCOMMA_DETECT origin:064-gtp-channel-conf 01_494 -GTP_CHANNEL_3_MID_LEFT.GTPE2.DEC_PCOMMA_DETECT origin:064-gtp-channel-conf 00_495 -GTP_CHANNEL_3_MID_LEFT.GTPE2.DEC_VALID_COMMA_ONLY origin:064-gtp-channel-conf 00_494 -GTP_CHANNEL_3_MID_LEFT.GTPE2.DMONITOR_CFG[0] origin:064-gtp-channel-conf 02_368 -GTP_CHANNEL_3_MID_LEFT.GTPE2.DMONITOR_CFG[1] origin:064-gtp-channel-conf 03_368 -GTP_CHANNEL_3_MID_LEFT.GTPE2.DMONITOR_CFG[2] origin:064-gtp-channel-conf 02_369 -GTP_CHANNEL_3_MID_LEFT.GTPE2.DMONITOR_CFG[3] origin:064-gtp-channel-conf 03_369 -GTP_CHANNEL_3_MID_LEFT.GTPE2.DMONITOR_CFG[4] origin:064-gtp-channel-conf 02_370 -GTP_CHANNEL_3_MID_LEFT.GTPE2.DMONITOR_CFG[5] origin:064-gtp-channel-conf 03_370 -GTP_CHANNEL_3_MID_LEFT.GTPE2.DMONITOR_CFG[6] origin:064-gtp-channel-conf 02_371 -GTP_CHANNEL_3_MID_LEFT.GTPE2.DMONITOR_CFG[7] origin:064-gtp-channel-conf 03_371 -GTP_CHANNEL_3_MID_LEFT.GTPE2.DMONITOR_CFG[8] origin:064-gtp-channel-conf 02_372 -GTP_CHANNEL_3_MID_LEFT.GTPE2.DMONITOR_CFG[9] origin:064-gtp-channel-conf 03_372 -GTP_CHANNEL_3_MID_LEFT.GTPE2.DMONITOR_CFG[10] origin:064-gtp-channel-conf 02_373 -GTP_CHANNEL_3_MID_LEFT.GTPE2.DMONITOR_CFG[11] origin:064-gtp-channel-conf 03_373 -GTP_CHANNEL_3_MID_LEFT.GTPE2.DMONITOR_CFG[12] origin:064-gtp-channel-conf 02_374 -GTP_CHANNEL_3_MID_LEFT.GTPE2.DMONITOR_CFG[13] origin:064-gtp-channel-conf 03_374 -GTP_CHANNEL_3_MID_LEFT.GTPE2.DMONITOR_CFG[14] origin:064-gtp-channel-conf 02_375 -GTP_CHANNEL_3_MID_LEFT.GTPE2.DMONITOR_CFG[15] origin:064-gtp-channel-conf 03_375 -GTP_CHANNEL_3_MID_LEFT.GTPE2.DMONITOR_CFG[16] origin:064-gtp-channel-conf 02_376 -GTP_CHANNEL_3_MID_LEFT.GTPE2.DMONITOR_CFG[17] origin:064-gtp-channel-conf 03_376 -GTP_CHANNEL_3_MID_LEFT.GTPE2.DMONITOR_CFG[18] origin:064-gtp-channel-conf 02_377 -GTP_CHANNEL_3_MID_LEFT.GTPE2.DMONITOR_CFG[19] origin:064-gtp-channel-conf 03_377 -GTP_CHANNEL_3_MID_LEFT.GTPE2.DMONITOR_CFG[20] origin:064-gtp-channel-conf 02_378 -GTP_CHANNEL_3_MID_LEFT.GTPE2.DMONITOR_CFG[21] origin:064-gtp-channel-conf 03_378 -GTP_CHANNEL_3_MID_LEFT.GTPE2.DMONITOR_CFG[22] origin:064-gtp-channel-conf 02_379 -GTP_CHANNEL_3_MID_LEFT.GTPE2.DMONITOR_CFG[23] origin:064-gtp-channel-conf 03_379 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_CLK_PHASE_SEL[0] origin:064-gtp-channel-conf 03_463 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_CONTROL[0] origin:064-gtp-channel-conf 00_488 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_CONTROL[1] origin:064-gtp-channel-conf 01_488 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_CONTROL[2] origin:064-gtp-channel-conf 00_489 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_CONTROL[3] origin:064-gtp-channel-conf 01_489 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_CONTROL[4] origin:064-gtp-channel-conf 00_490 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_CONTROL[5] origin:064-gtp-channel-conf 01_490 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_ERRDET_EN origin:064-gtp-channel-conf 01_492 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_EYE_SCAN_EN origin:064-gtp-channel-conf 00_492 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_HORZ_OFFSET[0] origin:064-gtp-channel-conf 00_480 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_HORZ_OFFSET[1] origin:064-gtp-channel-conf 01_480 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_HORZ_OFFSET[2] origin:064-gtp-channel-conf 00_481 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_HORZ_OFFSET[3] origin:064-gtp-channel-conf 01_481 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_HORZ_OFFSET[4] origin:064-gtp-channel-conf 00_482 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_HORZ_OFFSET[5] origin:064-gtp-channel-conf 01_482 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_HORZ_OFFSET[6] origin:064-gtp-channel-conf 00_483 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_HORZ_OFFSET[7] origin:064-gtp-channel-conf 01_483 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_HORZ_OFFSET[8] origin:064-gtp-channel-conf 00_484 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_HORZ_OFFSET[9] origin:064-gtp-channel-conf 01_484 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_HORZ_OFFSET[10] origin:064-gtp-channel-conf 00_485 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_HORZ_OFFSET[11] origin:064-gtp-channel-conf 01_485 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_PMA_CFG[0] origin:064-gtp-channel-conf 02_624 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_PMA_CFG[1] origin:064-gtp-channel-conf 03_624 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_PMA_CFG[2] origin:064-gtp-channel-conf 02_625 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_PMA_CFG[3] origin:064-gtp-channel-conf 03_625 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_PMA_CFG[4] origin:064-gtp-channel-conf 02_626 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_PMA_CFG[5] origin:064-gtp-channel-conf 03_626 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_PMA_CFG[6] origin:064-gtp-channel-conf 02_627 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_PMA_CFG[7] origin:064-gtp-channel-conf 03_627 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_PMA_CFG[8] origin:064-gtp-channel-conf 02_628 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_PMA_CFG[9] origin:064-gtp-channel-conf 03_628 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_PRESCALE[0] origin:064-gtp-channel-conf 01_477 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_PRESCALE[1] origin:064-gtp-channel-conf 00_478 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_PRESCALE[2] origin:064-gtp-channel-conf 01_478 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_PRESCALE[3] origin:064-gtp-channel-conf 00_479 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_PRESCALE[4] origin:064-gtp-channel-conf 01_479 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[0] origin:064-gtp-channel-conf 00_392 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[1] origin:064-gtp-channel-conf 01_392 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[2] origin:064-gtp-channel-conf 00_393 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[3] origin:064-gtp-channel-conf 01_393 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[4] origin:064-gtp-channel-conf 00_394 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[5] origin:064-gtp-channel-conf 01_394 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[6] origin:064-gtp-channel-conf 00_395 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[7] origin:064-gtp-channel-conf 01_395 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[8] origin:064-gtp-channel-conf 00_396 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[9] origin:064-gtp-channel-conf 01_396 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[10] origin:064-gtp-channel-conf 00_397 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[11] origin:064-gtp-channel-conf 01_397 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[12] origin:064-gtp-channel-conf 00_398 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[13] origin:064-gtp-channel-conf 01_398 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[14] origin:064-gtp-channel-conf 00_399 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[15] origin:064-gtp-channel-conf 01_399 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[16] origin:064-gtp-channel-conf 00_400 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[17] origin:064-gtp-channel-conf 01_400 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[18] origin:064-gtp-channel-conf 00_401 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[19] origin:064-gtp-channel-conf 01_401 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[20] origin:064-gtp-channel-conf 00_402 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[21] origin:064-gtp-channel-conf 01_402 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[22] origin:064-gtp-channel-conf 00_403 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[23] origin:064-gtp-channel-conf 01_403 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[24] origin:064-gtp-channel-conf 00_404 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[25] origin:064-gtp-channel-conf 01_404 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[26] origin:064-gtp-channel-conf 00_405 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[27] origin:064-gtp-channel-conf 01_405 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[28] origin:064-gtp-channel-conf 00_406 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[29] origin:064-gtp-channel-conf 01_406 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[30] origin:064-gtp-channel-conf 00_407 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[31] origin:064-gtp-channel-conf 01_407 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[32] origin:064-gtp-channel-conf 00_408 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[33] origin:064-gtp-channel-conf 01_408 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[34] origin:064-gtp-channel-conf 00_409 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[35] origin:064-gtp-channel-conf 01_409 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[36] origin:064-gtp-channel-conf 00_410 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[37] origin:064-gtp-channel-conf 01_410 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[38] origin:064-gtp-channel-conf 00_411 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[39] origin:064-gtp-channel-conf 01_411 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[40] origin:064-gtp-channel-conf 00_412 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[41] origin:064-gtp-channel-conf 01_412 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[42] origin:064-gtp-channel-conf 00_413 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[43] origin:064-gtp-channel-conf 01_413 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[44] origin:064-gtp-channel-conf 00_414 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[45] origin:064-gtp-channel-conf 01_414 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[46] origin:064-gtp-channel-conf 00_415 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[47] origin:064-gtp-channel-conf 01_415 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[48] origin:064-gtp-channel-conf 00_416 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[49] origin:064-gtp-channel-conf 01_416 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[50] origin:064-gtp-channel-conf 00_417 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[51] origin:064-gtp-channel-conf 01_417 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[52] origin:064-gtp-channel-conf 00_418 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[53] origin:064-gtp-channel-conf 01_418 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[54] origin:064-gtp-channel-conf 00_419 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[55] origin:064-gtp-channel-conf 01_419 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[56] origin:064-gtp-channel-conf 00_420 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[57] origin:064-gtp-channel-conf 01_420 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[58] origin:064-gtp-channel-conf 00_421 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[59] origin:064-gtp-channel-conf 01_421 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[60] origin:064-gtp-channel-conf 00_422 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[61] origin:064-gtp-channel-conf 01_422 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[62] origin:064-gtp-channel-conf 00_423 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[63] origin:064-gtp-channel-conf 01_423 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[64] origin:064-gtp-channel-conf 00_424 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[65] origin:064-gtp-channel-conf 01_424 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[66] origin:064-gtp-channel-conf 00_425 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[67] origin:064-gtp-channel-conf 01_425 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[68] origin:064-gtp-channel-conf 00_426 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[69] origin:064-gtp-channel-conf 01_426 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[70] origin:064-gtp-channel-conf 00_427 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[71] origin:064-gtp-channel-conf 01_427 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[72] origin:064-gtp-channel-conf 00_428 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[73] origin:064-gtp-channel-conf 01_428 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[74] origin:064-gtp-channel-conf 00_429 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[75] origin:064-gtp-channel-conf 01_429 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[76] origin:064-gtp-channel-conf 00_430 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[77] origin:064-gtp-channel-conf 01_430 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[78] origin:064-gtp-channel-conf 00_431 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUAL_MASK[79] origin:064-gtp-channel-conf 01_431 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[0] origin:064-gtp-channel-conf 00_352 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[1] origin:064-gtp-channel-conf 01_352 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[2] origin:064-gtp-channel-conf 00_353 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[3] origin:064-gtp-channel-conf 01_353 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[4] origin:064-gtp-channel-conf 00_354 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[5] origin:064-gtp-channel-conf 01_354 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[6] origin:064-gtp-channel-conf 00_355 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[7] origin:064-gtp-channel-conf 01_355 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[8] origin:064-gtp-channel-conf 00_356 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[9] origin:064-gtp-channel-conf 01_356 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[10] origin:064-gtp-channel-conf 00_357 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[11] origin:064-gtp-channel-conf 01_357 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[12] origin:064-gtp-channel-conf 00_358 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[13] origin:064-gtp-channel-conf 01_358 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[14] origin:064-gtp-channel-conf 00_359 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[15] origin:064-gtp-channel-conf 01_359 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[16] origin:064-gtp-channel-conf 00_360 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[17] origin:064-gtp-channel-conf 01_360 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[18] origin:064-gtp-channel-conf 00_361 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[19] origin:064-gtp-channel-conf 01_361 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[20] origin:064-gtp-channel-conf 00_362 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[21] origin:064-gtp-channel-conf 01_362 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[22] origin:064-gtp-channel-conf 00_363 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[23] origin:064-gtp-channel-conf 01_363 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[24] origin:064-gtp-channel-conf 00_364 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[25] origin:064-gtp-channel-conf 01_364 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[26] origin:064-gtp-channel-conf 00_365 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[27] origin:064-gtp-channel-conf 01_365 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[28] origin:064-gtp-channel-conf 00_366 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[29] origin:064-gtp-channel-conf 01_366 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[30] origin:064-gtp-channel-conf 00_367 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[31] origin:064-gtp-channel-conf 01_367 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[32] origin:064-gtp-channel-conf 00_368 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[33] origin:064-gtp-channel-conf 01_368 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[34] origin:064-gtp-channel-conf 00_369 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[35] origin:064-gtp-channel-conf 01_369 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[36] origin:064-gtp-channel-conf 00_370 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[37] origin:064-gtp-channel-conf 01_370 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[38] origin:064-gtp-channel-conf 00_371 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[39] origin:064-gtp-channel-conf 01_371 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[40] origin:064-gtp-channel-conf 00_372 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[41] origin:064-gtp-channel-conf 01_372 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[42] origin:064-gtp-channel-conf 00_373 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[43] origin:064-gtp-channel-conf 01_373 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[44] origin:064-gtp-channel-conf 00_374 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[45] origin:064-gtp-channel-conf 01_374 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[46] origin:064-gtp-channel-conf 00_375 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[47] origin:064-gtp-channel-conf 01_375 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[48] origin:064-gtp-channel-conf 00_376 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[49] origin:064-gtp-channel-conf 01_376 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[50] origin:064-gtp-channel-conf 00_377 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[51] origin:064-gtp-channel-conf 01_377 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[52] origin:064-gtp-channel-conf 00_378 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[53] origin:064-gtp-channel-conf 01_378 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[54] origin:064-gtp-channel-conf 00_379 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[55] origin:064-gtp-channel-conf 01_379 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[56] origin:064-gtp-channel-conf 00_380 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[57] origin:064-gtp-channel-conf 01_380 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[58] origin:064-gtp-channel-conf 00_381 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[59] origin:064-gtp-channel-conf 01_381 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[60] origin:064-gtp-channel-conf 00_382 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[61] origin:064-gtp-channel-conf 01_382 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[62] origin:064-gtp-channel-conf 00_383 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[63] origin:064-gtp-channel-conf 01_383 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[64] origin:064-gtp-channel-conf 00_384 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[65] origin:064-gtp-channel-conf 01_384 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[66] origin:064-gtp-channel-conf 00_385 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[67] origin:064-gtp-channel-conf 01_385 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[68] origin:064-gtp-channel-conf 00_386 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[69] origin:064-gtp-channel-conf 01_386 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[70] origin:064-gtp-channel-conf 00_387 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[71] origin:064-gtp-channel-conf 01_387 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[72] origin:064-gtp-channel-conf 00_388 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[73] origin:064-gtp-channel-conf 01_388 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[74] origin:064-gtp-channel-conf 00_389 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[75] origin:064-gtp-channel-conf 01_389 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[76] origin:064-gtp-channel-conf 00_390 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[77] origin:064-gtp-channel-conf 01_390 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[78] origin:064-gtp-channel-conf 00_391 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_QUALIFIER[79] origin:064-gtp-channel-conf 01_391 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[0] origin:064-gtp-channel-conf 00_432 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[1] origin:064-gtp-channel-conf 01_432 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[2] origin:064-gtp-channel-conf 00_433 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[3] origin:064-gtp-channel-conf 01_433 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[4] origin:064-gtp-channel-conf 00_434 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[5] origin:064-gtp-channel-conf 01_434 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[6] origin:064-gtp-channel-conf 00_435 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[7] origin:064-gtp-channel-conf 01_435 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[8] origin:064-gtp-channel-conf 00_436 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[9] origin:064-gtp-channel-conf 01_436 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[10] origin:064-gtp-channel-conf 00_437 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[11] origin:064-gtp-channel-conf 01_437 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[12] origin:064-gtp-channel-conf 00_438 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[13] origin:064-gtp-channel-conf 01_438 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[14] origin:064-gtp-channel-conf 00_439 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[15] origin:064-gtp-channel-conf 01_439 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[16] origin:064-gtp-channel-conf 00_440 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[17] origin:064-gtp-channel-conf 01_440 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[18] origin:064-gtp-channel-conf 00_441 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[19] origin:064-gtp-channel-conf 01_441 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[20] origin:064-gtp-channel-conf 00_442 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[21] origin:064-gtp-channel-conf 01_442 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[22] origin:064-gtp-channel-conf 00_443 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[23] origin:064-gtp-channel-conf 01_443 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[24] origin:064-gtp-channel-conf 00_444 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[25] origin:064-gtp-channel-conf 01_444 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[26] origin:064-gtp-channel-conf 00_445 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[27] origin:064-gtp-channel-conf 01_445 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[28] origin:064-gtp-channel-conf 00_446 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[29] origin:064-gtp-channel-conf 01_446 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[30] origin:064-gtp-channel-conf 00_447 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[31] origin:064-gtp-channel-conf 01_447 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[32] origin:064-gtp-channel-conf 00_448 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[33] origin:064-gtp-channel-conf 01_448 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[34] origin:064-gtp-channel-conf 00_449 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[35] origin:064-gtp-channel-conf 01_449 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[36] origin:064-gtp-channel-conf 00_450 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[37] origin:064-gtp-channel-conf 01_450 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[38] origin:064-gtp-channel-conf 00_451 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[39] origin:064-gtp-channel-conf 01_451 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[40] origin:064-gtp-channel-conf 00_452 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[41] origin:064-gtp-channel-conf 01_452 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[42] origin:064-gtp-channel-conf 00_453 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[43] origin:064-gtp-channel-conf 01_453 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[44] origin:064-gtp-channel-conf 00_454 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[45] origin:064-gtp-channel-conf 01_454 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[46] origin:064-gtp-channel-conf 00_455 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[47] origin:064-gtp-channel-conf 01_455 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[48] origin:064-gtp-channel-conf 00_456 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[49] origin:064-gtp-channel-conf 01_456 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[50] origin:064-gtp-channel-conf 00_457 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[51] origin:064-gtp-channel-conf 01_457 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[52] origin:064-gtp-channel-conf 00_458 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[53] origin:064-gtp-channel-conf 01_458 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[54] origin:064-gtp-channel-conf 00_459 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[55] origin:064-gtp-channel-conf 01_459 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[56] origin:064-gtp-channel-conf 00_460 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[57] origin:064-gtp-channel-conf 01_460 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[58] origin:064-gtp-channel-conf 00_461 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[59] origin:064-gtp-channel-conf 01_461 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[60] origin:064-gtp-channel-conf 00_462 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[61] origin:064-gtp-channel-conf 01_462 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[62] origin:064-gtp-channel-conf 00_463 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[63] origin:064-gtp-channel-conf 01_463 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[64] origin:064-gtp-channel-conf 00_464 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[65] origin:064-gtp-channel-conf 01_464 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[66] origin:064-gtp-channel-conf 00_465 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[67] origin:064-gtp-channel-conf 01_465 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[68] origin:064-gtp-channel-conf 00_466 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[69] origin:064-gtp-channel-conf 01_466 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[70] origin:064-gtp-channel-conf 00_467 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[71] origin:064-gtp-channel-conf 01_467 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[72] origin:064-gtp-channel-conf 00_468 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[73] origin:064-gtp-channel-conf 01_468 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[74] origin:064-gtp-channel-conf 00_469 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[75] origin:064-gtp-channel-conf 01_469 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[76] origin:064-gtp-channel-conf 00_470 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[77] origin:064-gtp-channel-conf 01_470 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[78] origin:064-gtp-channel-conf 00_471 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_SDATA_MASK[79] origin:064-gtp-channel-conf 01_471 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_VERT_OFFSET[0] origin:064-gtp-channel-conf 00_472 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_VERT_OFFSET[1] origin:064-gtp-channel-conf 01_472 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_VERT_OFFSET[2] origin:064-gtp-channel-conf 00_473 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_VERT_OFFSET[3] origin:064-gtp-channel-conf 01_473 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_VERT_OFFSET[4] origin:064-gtp-channel-conf 00_474 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_VERT_OFFSET[5] origin:064-gtp-channel-conf 01_474 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_VERT_OFFSET[6] origin:064-gtp-channel-conf 00_475 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_VERT_OFFSET[7] origin:064-gtp-channel-conf 01_475 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ES_VERT_OFFSET[8] origin:064-gtp-channel-conf 00_476 -GTP_CHANNEL_3_MID_LEFT.GTPE2.FTS_DESKEW_SEQ_ENABLE[0] origin:064-gtp-channel-conf 00_662 -GTP_CHANNEL_3_MID_LEFT.GTPE2.FTS_DESKEW_SEQ_ENABLE[1] origin:064-gtp-channel-conf 01_662 -GTP_CHANNEL_3_MID_LEFT.GTPE2.FTS_DESKEW_SEQ_ENABLE[2] origin:064-gtp-channel-conf 00_663 -GTP_CHANNEL_3_MID_LEFT.GTPE2.FTS_DESKEW_SEQ_ENABLE[3] origin:064-gtp-channel-conf 01_663 -GTP_CHANNEL_3_MID_LEFT.GTPE2.FTS_LANE_DESKEW_CFG[0] origin:064-gtp-channel-conf 00_654 -GTP_CHANNEL_3_MID_LEFT.GTPE2.FTS_LANE_DESKEW_CFG[1] origin:064-gtp-channel-conf 01_654 -GTP_CHANNEL_3_MID_LEFT.GTPE2.FTS_LANE_DESKEW_CFG[2] origin:064-gtp-channel-conf 00_655 -GTP_CHANNEL_3_MID_LEFT.GTPE2.FTS_LANE_DESKEW_CFG[3] origin:064-gtp-channel-conf 01_655 -GTP_CHANNEL_3_MID_LEFT.GTPE2.FTS_LANE_DESKEW_EN origin:064-gtp-channel-conf 01_653 -GTP_CHANNEL_3_MID_LEFT.GTPE2.GEARBOX_MODE[0] origin:064-gtp-channel-conf 00_224 -GTP_CHANNEL_3_MID_LEFT.GTPE2.GEARBOX_MODE[1] origin:064-gtp-channel-conf 01_224 -GTP_CHANNEL_3_MID_LEFT.GTPE2.GEARBOX_MODE[2] origin:064-gtp-channel-conf 00_225 -GTP_CHANNEL_3_MID_LEFT.GTPE2.IN_USE origin:064-gtp-channel-conf 00_00 00_01 00_47 00_52 00_53 00_65 01_01 01_47 02_129 -GTP_CHANNEL_3_MID_LEFT.GTPE2.LOOPBACK_CFG[0] origin:064-gtp-channel-conf 02_20 -GTP_CHANNEL_3_MID_LEFT.GTPE2.OUTREFCLK_SEL_INV[0] origin:064-gtp-channel-conf 00_149 -GTP_CHANNEL_3_MID_LEFT.GTPE2.OUTREFCLK_SEL_INV[1] origin:064-gtp-channel-conf 01_149 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PCS_PCIE_EN origin:064-gtp-channel-conf 00_216 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PCS_RSVD_ATTR[0] origin:064-gtp-channel-conf 02_184 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PCS_RSVD_ATTR[1] origin:064-gtp-channel-conf 03_184 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PCS_RSVD_ATTR[2] origin:064-gtp-channel-conf 02_185 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PCS_RSVD_ATTR[3] origin:064-gtp-channel-conf 03_185 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PCS_RSVD_ATTR[4] origin:064-gtp-channel-conf 02_186 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PCS_RSVD_ATTR[5] origin:064-gtp-channel-conf 03_186 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PCS_RSVD_ATTR[6] origin:064-gtp-channel-conf 02_187 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PCS_RSVD_ATTR[7] origin:064-gtp-channel-conf 03_187 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PCS_RSVD_ATTR[8] origin:064-gtp-channel-conf 02_188 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PCS_RSVD_ATTR[9] origin:064-gtp-channel-conf 03_188 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PCS_RSVD_ATTR[10] origin:064-gtp-channel-conf 02_189 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PCS_RSVD_ATTR[11] origin:064-gtp-channel-conf 03_189 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PCS_RSVD_ATTR[12] origin:064-gtp-channel-conf 02_190 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PCS_RSVD_ATTR[13] origin:064-gtp-channel-conf 03_190 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PCS_RSVD_ATTR[14] origin:064-gtp-channel-conf 02_191 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PCS_RSVD_ATTR[15] origin:064-gtp-channel-conf 03_191 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PCS_RSVD_ATTR[16] origin:064-gtp-channel-conf 02_192 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PCS_RSVD_ATTR[17] origin:064-gtp-channel-conf 03_192 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PCS_RSVD_ATTR[18] origin:064-gtp-channel-conf 02_193 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PCS_RSVD_ATTR[19] origin:064-gtp-channel-conf 03_193 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PCS_RSVD_ATTR[20] origin:064-gtp-channel-conf 02_194 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PCS_RSVD_ATTR[21] origin:064-gtp-channel-conf 03_194 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PCS_RSVD_ATTR[22] origin:064-gtp-channel-conf 02_195 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PCS_RSVD_ATTR[23] origin:064-gtp-channel-conf 03_195 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PCS_RSVD_ATTR[24] origin:064-gtp-channel-conf 02_196 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PCS_RSVD_ATTR[25] origin:064-gtp-channel-conf 03_196 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PCS_RSVD_ATTR[26] origin:064-gtp-channel-conf 02_197 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PCS_RSVD_ATTR[27] origin:064-gtp-channel-conf 03_197 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PCS_RSVD_ATTR[28] origin:064-gtp-channel-conf 02_198 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PCS_RSVD_ATTR[29] origin:064-gtp-channel-conf 03_198 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PCS_RSVD_ATTR[30] origin:064-gtp-channel-conf 02_199 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PCS_RSVD_ATTR[31] origin:064-gtp-channel-conf 03_199 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PCS_RSVD_ATTR[32] origin:064-gtp-channel-conf 02_200 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PCS_RSVD_ATTR[33] origin:064-gtp-channel-conf 03_200 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PCS_RSVD_ATTR[34] origin:064-gtp-channel-conf 02_201 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PCS_RSVD_ATTR[35] origin:064-gtp-channel-conf 03_201 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PCS_RSVD_ATTR[36] origin:064-gtp-channel-conf 02_202 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PCS_RSVD_ATTR[37] origin:064-gtp-channel-conf 03_202 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PCS_RSVD_ATTR[38] origin:064-gtp-channel-conf 02_203 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PCS_RSVD_ATTR[39] origin:064-gtp-channel-conf 03_203 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PCS_RSVD_ATTR[40] origin:064-gtp-channel-conf 02_204 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PCS_RSVD_ATTR[41] origin:064-gtp-channel-conf 03_204 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PCS_RSVD_ATTR[42] origin:064-gtp-channel-conf 02_205 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PCS_RSVD_ATTR[43] origin:064-gtp-channel-conf 03_205 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PCS_RSVD_ATTR[44] origin:064-gtp-channel-conf 02_206 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PCS_RSVD_ATTR[45] origin:064-gtp-channel-conf 03_206 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PCS_RSVD_ATTR[46] origin:064-gtp-channel-conf 02_207 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PCS_RSVD_ATTR[47] origin:064-gtp-channel-conf 03_207 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PD_TRANS_TIME_FROM_P2[0] origin:064-gtp-channel-conf 01_216 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PD_TRANS_TIME_FROM_P2[1] origin:064-gtp-channel-conf 00_217 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PD_TRANS_TIME_FROM_P2[2] origin:064-gtp-channel-conf 01_217 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PD_TRANS_TIME_FROM_P2[3] origin:064-gtp-channel-conf 00_218 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PD_TRANS_TIME_FROM_P2[4] origin:064-gtp-channel-conf 01_218 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PD_TRANS_TIME_FROM_P2[5] origin:064-gtp-channel-conf 00_219 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PD_TRANS_TIME_FROM_P2[6] origin:064-gtp-channel-conf 01_219 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PD_TRANS_TIME_FROM_P2[7] origin:064-gtp-channel-conf 00_220 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PD_TRANS_TIME_FROM_P2[8] origin:064-gtp-channel-conf 01_220 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PD_TRANS_TIME_FROM_P2[9] origin:064-gtp-channel-conf 00_221 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PD_TRANS_TIME_FROM_P2[10] origin:064-gtp-channel-conf 01_221 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PD_TRANS_TIME_FROM_P2[11] origin:064-gtp-channel-conf 00_222 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PD_TRANS_TIME_NONE_P2[0] origin:064-gtp-channel-conf 00_208 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PD_TRANS_TIME_NONE_P2[1] origin:064-gtp-channel-conf 01_208 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PD_TRANS_TIME_NONE_P2[2] origin:064-gtp-channel-conf 00_209 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PD_TRANS_TIME_NONE_P2[3] origin:064-gtp-channel-conf 01_209 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PD_TRANS_TIME_NONE_P2[4] origin:064-gtp-channel-conf 00_210 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PD_TRANS_TIME_NONE_P2[5] origin:064-gtp-channel-conf 01_210 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PD_TRANS_TIME_NONE_P2[6] origin:064-gtp-channel-conf 00_211 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PD_TRANS_TIME_NONE_P2[7] origin:064-gtp-channel-conf 01_211 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PD_TRANS_TIME_TO_P2[0] origin:064-gtp-channel-conf 00_212 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PD_TRANS_TIME_TO_P2[1] origin:064-gtp-channel-conf 01_212 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PD_TRANS_TIME_TO_P2[2] origin:064-gtp-channel-conf 00_213 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PD_TRANS_TIME_TO_P2[3] origin:064-gtp-channel-conf 01_213 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PD_TRANS_TIME_TO_P2[4] origin:064-gtp-channel-conf 00_214 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PD_TRANS_TIME_TO_P2[5] origin:064-gtp-channel-conf 01_214 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PD_TRANS_TIME_TO_P2[6] origin:064-gtp-channel-conf 00_215 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PD_TRANS_TIME_TO_P2[7] origin:064-gtp-channel-conf 01_215 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PMA_LOOPBACK_CFG[0] origin:064-gtp-channel-conf 01_207 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PMA_RSV[0] origin:064-gtp-channel-conf 02_520 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PMA_RSV[1] origin:064-gtp-channel-conf 03_520 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PMA_RSV[2] origin:064-gtp-channel-conf 02_521 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PMA_RSV[3] origin:064-gtp-channel-conf 03_521 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PMA_RSV[4] origin:064-gtp-channel-conf 02_522 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PMA_RSV[5] origin:064-gtp-channel-conf 03_522 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PMA_RSV[6] origin:064-gtp-channel-conf 02_523 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PMA_RSV[7] origin:064-gtp-channel-conf 03_523 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PMA_RSV[8] origin:064-gtp-channel-conf 02_524 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PMA_RSV[9] origin:064-gtp-channel-conf 03_524 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PMA_RSV[10] origin:064-gtp-channel-conf 02_525 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PMA_RSV[11] origin:064-gtp-channel-conf 03_525 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PMA_RSV[12] origin:064-gtp-channel-conf 02_526 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PMA_RSV[13] origin:064-gtp-channel-conf 03_526 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PMA_RSV[14] origin:064-gtp-channel-conf 02_527 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PMA_RSV[15] origin:064-gtp-channel-conf 03_527 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PMA_RSV[16] origin:064-gtp-channel-conf 02_528 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PMA_RSV[17] origin:064-gtp-channel-conf 03_528 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PMA_RSV[18] origin:064-gtp-channel-conf 02_529 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PMA_RSV[19] origin:064-gtp-channel-conf 03_529 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PMA_RSV[20] origin:064-gtp-channel-conf 02_530 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PMA_RSV[21] origin:064-gtp-channel-conf 03_530 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PMA_RSV[22] origin:064-gtp-channel-conf 02_531 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PMA_RSV[23] origin:064-gtp-channel-conf 03_531 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PMA_RSV[24] origin:064-gtp-channel-conf 02_532 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PMA_RSV[25] origin:064-gtp-channel-conf 03_532 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PMA_RSV[26] origin:064-gtp-channel-conf 02_533 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PMA_RSV[27] origin:064-gtp-channel-conf 03_533 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PMA_RSV[28] origin:064-gtp-channel-conf 02_534 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PMA_RSV[29] origin:064-gtp-channel-conf 03_534 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PMA_RSV[30] origin:064-gtp-channel-conf 02_535 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PMA_RSV[31] origin:064-gtp-channel-conf 03_535 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PMA_RSV2[0] origin:064-gtp-channel-conf 02_336 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PMA_RSV2[1] origin:064-gtp-channel-conf 03_336 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PMA_RSV2[2] origin:064-gtp-channel-conf 02_337 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PMA_RSV2[3] origin:064-gtp-channel-conf 03_337 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PMA_RSV2[4] origin:064-gtp-channel-conf 02_338 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PMA_RSV2[5] origin:064-gtp-channel-conf 03_338 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PMA_RSV2[6] origin:064-gtp-channel-conf 02_339 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PMA_RSV2[7] origin:064-gtp-channel-conf 03_339 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PMA_RSV2[8] origin:064-gtp-channel-conf 02_340 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PMA_RSV2[9] origin:064-gtp-channel-conf 03_340 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PMA_RSV2[10] origin:064-gtp-channel-conf 02_341 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PMA_RSV2[11] origin:064-gtp-channel-conf 03_341 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PMA_RSV2[12] origin:064-gtp-channel-conf 02_342 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PMA_RSV2[13] origin:064-gtp-channel-conf 03_342 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PMA_RSV2[14] origin:064-gtp-channel-conf 02_343 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PMA_RSV2[15] origin:064-gtp-channel-conf 03_343 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PMA_RSV2[16] origin:064-gtp-channel-conf 02_344 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PMA_RSV2[17] origin:064-gtp-channel-conf 03_344 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PMA_RSV2[18] origin:064-gtp-channel-conf 02_345 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PMA_RSV2[19] origin:064-gtp-channel-conf 03_345 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PMA_RSV2[20] origin:064-gtp-channel-conf 02_346 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PMA_RSV2[21] origin:064-gtp-channel-conf 03_346 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PMA_RSV2[22] origin:064-gtp-channel-conf 02_347 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PMA_RSV2[23] origin:064-gtp-channel-conf 03_347 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PMA_RSV2[24] origin:064-gtp-channel-conf 02_348 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PMA_RSV2[25] origin:064-gtp-channel-conf 03_348 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PMA_RSV2[26] origin:064-gtp-channel-conf 02_349 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PMA_RSV2[27] origin:064-gtp-channel-conf 03_349 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PMA_RSV2[28] origin:064-gtp-channel-conf 02_350 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PMA_RSV2[29] origin:064-gtp-channel-conf 03_350 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PMA_RSV2[30] origin:064-gtp-channel-conf 02_351 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PMA_RSV2[31] origin:064-gtp-channel-conf 03_351 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PMA_RSV3[0] origin:064-gtp-channel-conf 02_288 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PMA_RSV3[1] origin:064-gtp-channel-conf 03_288 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PMA_RSV4[0] origin:064-gtp-channel-conf 02_156 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PMA_RSV4[1] origin:064-gtp-channel-conf 03_156 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PMA_RSV4[2] origin:064-gtp-channel-conf 02_157 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PMA_RSV4[3] origin:064-gtp-channel-conf 03_157 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PMA_RSV5[0] origin:064-gtp-channel-conf 03_159 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PMA_RSV6[0] origin:064-gtp-channel-conf 02_303 -GTP_CHANNEL_3_MID_LEFT.GTPE2.PMA_RSV7[0] origin:064-gtp-channel-conf 03_303 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_BIAS_CFG[0] origin:064-gtp-channel-conf 02_112 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_BIAS_CFG[1] origin:064-gtp-channel-conf 03_112 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_BIAS_CFG[2] origin:064-gtp-channel-conf 02_113 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_BIAS_CFG[3] origin:064-gtp-channel-conf 03_113 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_BIAS_CFG[4] origin:064-gtp-channel-conf 02_114 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_BIAS_CFG[5] origin:064-gtp-channel-conf 03_114 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_BIAS_CFG[6] origin:064-gtp-channel-conf 02_115 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_BIAS_CFG[7] origin:064-gtp-channel-conf 03_115 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_BIAS_CFG[8] origin:064-gtp-channel-conf 02_116 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_BIAS_CFG[9] origin:064-gtp-channel-conf 03_116 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_BIAS_CFG[10] origin:064-gtp-channel-conf 02_117 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_BIAS_CFG[11] origin:064-gtp-channel-conf 03_117 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_BIAS_CFG[12] origin:064-gtp-channel-conf 02_118 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_BIAS_CFG[13] origin:064-gtp-channel-conf 03_118 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_BIAS_CFG[14] origin:064-gtp-channel-conf 02_119 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_BIAS_CFG[15] origin:064-gtp-channel-conf 03_119 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_BUFFER_CFG[0] origin:064-gtp-channel-conf 02_536 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_BUFFER_CFG[1] origin:064-gtp-channel-conf 03_536 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_BUFFER_CFG[2] origin:064-gtp-channel-conf 02_537 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_BUFFER_CFG[3] origin:064-gtp-channel-conf 03_537 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_BUFFER_CFG[4] origin:064-gtp-channel-conf 02_538 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_BUFFER_CFG[5] origin:064-gtp-channel-conf 03_538 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_CLKMUX_EN[0] origin:064-gtp-channel-conf 02_128 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_CM_SEL[0] origin:064-gtp-channel-conf 00_138 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_CM_SEL[1] origin:064-gtp-channel-conf 01_138 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_CM_TRIM[0] origin:064-gtp-channel-conf 02_304 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_CM_TRIM[1] origin:064-gtp-channel-conf 03_304 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_CM_TRIM[2] origin:064-gtp-channel-conf 02_305 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_CM_TRIM[3] origin:064-gtp-channel-conf 03_305 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_DATA_WIDTH[0] origin:064-gtp-channel-conf 01_141 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_DATA_WIDTH[1] origin:064-gtp-channel-conf 00_142 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_DATA_WIDTH[2] origin:064-gtp-channel-conf 01_142 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_DDI_SEL[0] origin:064-gtp-channel-conf 00_696 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_DDI_SEL[1] origin:064-gtp-channel-conf 01_696 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_DDI_SEL[2] origin:064-gtp-channel-conf 00_697 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_DDI_SEL[3] origin:064-gtp-channel-conf 01_697 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_DDI_SEL[4] origin:064-gtp-channel-conf 00_698 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_DDI_SEL[5] origin:064-gtp-channel-conf 01_698 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_DEBUG_CFG[0] origin:064-gtp-channel-conf 02_616 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_DEBUG_CFG[1] origin:064-gtp-channel-conf 03_616 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_DEBUG_CFG[2] origin:064-gtp-channel-conf 02_617 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_DEBUG_CFG[3] origin:064-gtp-channel-conf 03_617 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_DEBUG_CFG[4] origin:064-gtp-channel-conf 02_618 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_DEBUG_CFG[5] origin:064-gtp-channel-conf 03_618 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_DEBUG_CFG[6] origin:064-gtp-channel-conf 02_619 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_DEBUG_CFG[7] origin:064-gtp-channel-conf 03_619 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_DEBUG_CFG[8] origin:064-gtp-channel-conf 02_620 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_DEBUG_CFG[9] origin:064-gtp-channel-conf 03_620 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_DEBUG_CFG[10] origin:064-gtp-channel-conf 02_621 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_DEBUG_CFG[11] origin:064-gtp-channel-conf 03_621 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_DEBUG_CFG[12] origin:064-gtp-channel-conf 02_622 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_DEBUG_CFG[13] origin:064-gtp-channel-conf 03_622 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_DEFER_RESET_BUF_EN origin:064-gtp-channel-conf 02_552 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_DISPERR_SEQ_MATCH origin:064-gtp-channel-conf 01_495 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_OS_CFG[0] origin:064-gtp-channel-conf 00_288 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_OS_CFG[1] origin:064-gtp-channel-conf 01_288 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_OS_CFG[2] origin:064-gtp-channel-conf 00_289 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_OS_CFG[3] origin:064-gtp-channel-conf 01_289 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_OS_CFG[4] origin:064-gtp-channel-conf 00_290 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_OS_CFG[5] origin:064-gtp-channel-conf 01_290 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_OS_CFG[6] origin:064-gtp-channel-conf 00_291 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_OS_CFG[7] origin:064-gtp-channel-conf 01_291 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_OS_CFG[8] origin:064-gtp-channel-conf 00_292 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_OS_CFG[9] origin:064-gtp-channel-conf 01_292 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_OS_CFG[10] origin:064-gtp-channel-conf 00_293 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_OS_CFG[11] origin:064-gtp-channel-conf 01_293 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_OS_CFG[12] origin:064-gtp-channel-conf 00_294 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_SIG_VALID_DLY[0] origin:064-gtp-channel-conf 00_524 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_SIG_VALID_DLY[1] origin:064-gtp-channel-conf 01_524 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_SIG_VALID_DLY[2] origin:064-gtp-channel-conf 00_525 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_SIG_VALID_DLY[3] origin:064-gtp-channel-conf 01_525 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_SIG_VALID_DLY[4] origin:064-gtp-channel-conf 00_526 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_XCLK_SEL.RXUSR origin:064-gtp-channel-conf 00_143 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_CLK25_DIV[0] origin:064-gtp-channel-conf 00_139 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_CLK25_DIV[1] origin:064-gtp-channel-conf 01_139 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_CLK25_DIV[2] origin:064-gtp-channel-conf 00_140 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_CLK25_DIV[3] origin:064-gtp-channel-conf 01_140 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RX_CLK25_DIV[4] origin:064-gtp-channel-conf 00_141 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXBUF_ADDR_MODE.FAST origin:064-gtp-channel-conf 03_555 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXBUF_EIDLE_HI_CNT[0] origin:064-gtp-channel-conf 02_558 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXBUF_EIDLE_HI_CNT[1] origin:064-gtp-channel-conf 03_558 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXBUF_EIDLE_HI_CNT[2] origin:064-gtp-channel-conf 02_559 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXBUF_EIDLE_HI_CNT[3] origin:064-gtp-channel-conf 03_559 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXBUF_EIDLE_LO_CNT[0] origin:064-gtp-channel-conf 02_556 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXBUF_EIDLE_LO_CNT[1] origin:064-gtp-channel-conf 03_556 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXBUF_EIDLE_LO_CNT[2] origin:064-gtp-channel-conf 02_557 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXBUF_EIDLE_LO_CNT[3] origin:064-gtp-channel-conf 03_557 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXBUF_EN origin:064-gtp-channel-conf 02_11 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXBUF_RESET_ON_CB_CHANGE origin:064-gtp-channel-conf 02_560 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXBUF_RESET_ON_COMMAALIGN origin:064-gtp-channel-conf 02_561 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXBUF_RESET_ON_EIDLE origin:064-gtp-channel-conf 02_547 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXBUF_RESET_ON_RATE_CHANGE origin:064-gtp-channel-conf 03_560 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXBUF_THRESH_OVFLW[0] origin:064-gtp-channel-conf 03_552 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXBUF_THRESH_OVFLW[1] origin:064-gtp-channel-conf 02_553 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXBUF_THRESH_OVFLW[2] origin:064-gtp-channel-conf 03_553 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXBUF_THRESH_OVFLW[3] origin:064-gtp-channel-conf 02_554 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXBUF_THRESH_OVFLW[4] origin:064-gtp-channel-conf 03_554 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXBUF_THRESH_OVFLW[5] origin:064-gtp-channel-conf 02_555 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXBUF_THRESH_OVRD origin:064-gtp-channel-conf 02_548 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXBUF_THRESH_UNDFLW[0] origin:064-gtp-channel-conf 02_544 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXBUF_THRESH_UNDFLW[1] origin:064-gtp-channel-conf 03_544 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXBUF_THRESH_UNDFLW[2] origin:064-gtp-channel-conf 02_545 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXBUF_THRESH_UNDFLW[3] origin:064-gtp-channel-conf 03_545 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXBUF_THRESH_UNDFLW[4] origin:064-gtp-channel-conf 02_546 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXBUF_THRESH_UNDFLW[5] origin:064-gtp-channel-conf 03_546 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXBUFRESET_TIME[0] origin:064-gtp-channel-conf 01_101 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXBUFRESET_TIME[1] origin:064-gtp-channel-conf 00_102 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXBUFRESET_TIME[2] origin:064-gtp-channel-conf 01_102 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXBUFRESET_TIME[3] origin:064-gtp-channel-conf 00_103 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXBUFRESET_TIME[4] origin:064-gtp-channel-conf 01_103 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[0] origin:064-gtp-channel-conf 02_640 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[1] origin:064-gtp-channel-conf 03_640 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[2] origin:064-gtp-channel-conf 02_641 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[3] origin:064-gtp-channel-conf 03_641 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[4] origin:064-gtp-channel-conf 02_642 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[5] origin:064-gtp-channel-conf 03_642 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[6] origin:064-gtp-channel-conf 02_643 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[7] origin:064-gtp-channel-conf 03_643 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[8] origin:064-gtp-channel-conf 02_644 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[9] origin:064-gtp-channel-conf 03_644 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[10] origin:064-gtp-channel-conf 02_645 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[11] origin:064-gtp-channel-conf 03_645 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[12] origin:064-gtp-channel-conf 02_646 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[13] origin:064-gtp-channel-conf 03_646 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[14] origin:064-gtp-channel-conf 02_647 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[15] origin:064-gtp-channel-conf 03_647 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[16] origin:064-gtp-channel-conf 02_648 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[17] origin:064-gtp-channel-conf 03_648 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[18] origin:064-gtp-channel-conf 02_649 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[19] origin:064-gtp-channel-conf 03_649 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[20] origin:064-gtp-channel-conf 02_650 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[21] origin:064-gtp-channel-conf 03_650 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[22] origin:064-gtp-channel-conf 02_651 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[23] origin:064-gtp-channel-conf 03_651 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[24] origin:064-gtp-channel-conf 02_652 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[25] origin:064-gtp-channel-conf 03_652 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[26] origin:064-gtp-channel-conf 02_653 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[27] origin:064-gtp-channel-conf 03_653 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[28] origin:064-gtp-channel-conf 02_654 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[29] origin:064-gtp-channel-conf 03_654 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[30] origin:064-gtp-channel-conf 02_655 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[31] origin:064-gtp-channel-conf 03_655 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[32] origin:064-gtp-channel-conf 02_656 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[33] origin:064-gtp-channel-conf 03_656 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[34] origin:064-gtp-channel-conf 02_657 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[35] origin:064-gtp-channel-conf 03_657 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[36] origin:064-gtp-channel-conf 02_658 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[37] origin:064-gtp-channel-conf 03_658 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[38] origin:064-gtp-channel-conf 02_659 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[39] origin:064-gtp-channel-conf 03_659 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[40] origin:064-gtp-channel-conf 02_660 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[41] origin:064-gtp-channel-conf 03_660 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[42] origin:064-gtp-channel-conf 02_661 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[43] origin:064-gtp-channel-conf 03_661 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[44] origin:064-gtp-channel-conf 02_662 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[45] origin:064-gtp-channel-conf 03_662 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[46] origin:064-gtp-channel-conf 02_663 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[47] origin:064-gtp-channel-conf 03_663 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[48] origin:064-gtp-channel-conf 02_664 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[49] origin:064-gtp-channel-conf 03_664 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[50] origin:064-gtp-channel-conf 02_665 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[51] origin:064-gtp-channel-conf 03_665 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[52] origin:064-gtp-channel-conf 02_666 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[53] origin:064-gtp-channel-conf 03_666 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[54] origin:064-gtp-channel-conf 02_667 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[55] origin:064-gtp-channel-conf 03_667 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[56] origin:064-gtp-channel-conf 02_668 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[57] origin:064-gtp-channel-conf 03_668 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[58] origin:064-gtp-channel-conf 02_669 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[59] origin:064-gtp-channel-conf 03_669 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[60] origin:064-gtp-channel-conf 02_670 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[61] origin:064-gtp-channel-conf 03_670 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[62] origin:064-gtp-channel-conf 02_671 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[63] origin:064-gtp-channel-conf 03_671 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[64] origin:064-gtp-channel-conf 02_672 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[65] origin:064-gtp-channel-conf 03_672 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[66] origin:064-gtp-channel-conf 02_673 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[67] origin:064-gtp-channel-conf 03_673 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[68] origin:064-gtp-channel-conf 02_674 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[69] origin:064-gtp-channel-conf 03_674 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[70] origin:064-gtp-channel-conf 02_675 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[71] origin:064-gtp-channel-conf 03_675 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[72] origin:064-gtp-channel-conf 02_676 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[73] origin:064-gtp-channel-conf 03_676 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[74] origin:064-gtp-channel-conf 02_677 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[75] origin:064-gtp-channel-conf 03_677 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[76] origin:064-gtp-channel-conf 02_678 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[77] origin:064-gtp-channel-conf 03_678 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[78] origin:064-gtp-channel-conf 02_679 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[79] origin:064-gtp-channel-conf 03_679 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[80] origin:064-gtp-channel-conf 02_680 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[81] origin:064-gtp-channel-conf 03_680 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_CFG[82] origin:064-gtp-channel-conf 02_681 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_FR_RESET_ON_EIDLE[0] origin:064-gtp-channel-conf 02_638 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_HOLD_DURING_EIDLE[0] origin:064-gtp-channel-conf 03_637 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_LOCK_CFG[0] origin:064-gtp-channel-conf 02_632 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_LOCK_CFG[1] origin:064-gtp-channel-conf 03_632 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_LOCK_CFG[2] origin:064-gtp-channel-conf 02_633 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_LOCK_CFG[3] origin:064-gtp-channel-conf 03_633 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_LOCK_CFG[4] origin:064-gtp-channel-conf 02_634 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_LOCK_CFG[5] origin:064-gtp-channel-conf 03_634 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDR_PH_RESET_ON_EIDLE[0] origin:064-gtp-channel-conf 03_638 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDRFREQRESET_TIME[0] origin:064-gtp-channel-conf 01_106 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDRFREQRESET_TIME[1] origin:064-gtp-channel-conf 00_107 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDRFREQRESET_TIME[2] origin:064-gtp-channel-conf 01_107 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDRFREQRESET_TIME[3] origin:064-gtp-channel-conf 00_108 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDRFREQRESET_TIME[4] origin:064-gtp-channel-conf 01_108 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDRPHRESET_TIME[0] origin:064-gtp-channel-conf 00_109 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDRPHRESET_TIME[1] origin:064-gtp-channel-conf 01_109 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDRPHRESET_TIME[2] origin:064-gtp-channel-conf 00_110 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDRPHRESET_TIME[3] origin:064-gtp-channel-conf 01_110 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXCDRPHRESET_TIME[4] origin:064-gtp-channel-conf 00_111 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXDLY_CFG[0] origin:064-gtp-channel-conf 00_680 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXDLY_CFG[1] origin:064-gtp-channel-conf 01_680 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXDLY_CFG[2] origin:064-gtp-channel-conf 00_681 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXDLY_CFG[3] origin:064-gtp-channel-conf 01_681 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXDLY_CFG[4] origin:064-gtp-channel-conf 00_682 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXDLY_CFG[5] origin:064-gtp-channel-conf 01_682 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXDLY_CFG[6] origin:064-gtp-channel-conf 00_683 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXDLY_CFG[7] origin:064-gtp-channel-conf 01_683 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXDLY_CFG[8] origin:064-gtp-channel-conf 00_684 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXDLY_CFG[9] origin:064-gtp-channel-conf 01_684 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXDLY_CFG[10] origin:064-gtp-channel-conf 00_685 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXDLY_CFG[11] origin:064-gtp-channel-conf 01_685 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXDLY_CFG[12] origin:064-gtp-channel-conf 00_686 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXDLY_CFG[13] origin:064-gtp-channel-conf 01_686 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXDLY_CFG[14] origin:064-gtp-channel-conf 00_687 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXDLY_CFG[15] origin:064-gtp-channel-conf 01_687 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXDLY_LCFG[0] origin:064-gtp-channel-conf 02_576 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXDLY_LCFG[1] origin:064-gtp-channel-conf 03_576 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXDLY_LCFG[2] origin:064-gtp-channel-conf 02_577 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXDLY_LCFG[3] origin:064-gtp-channel-conf 03_577 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXDLY_LCFG[4] origin:064-gtp-channel-conf 02_578 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXDLY_LCFG[5] origin:064-gtp-channel-conf 03_578 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXDLY_LCFG[6] origin:064-gtp-channel-conf 02_579 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXDLY_LCFG[7] origin:064-gtp-channel-conf 03_579 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXDLY_LCFG[8] origin:064-gtp-channel-conf 02_580 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXDLY_TAP_CFG[0] origin:064-gtp-channel-conf 00_672 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXDLY_TAP_CFG[1] origin:064-gtp-channel-conf 01_672 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXDLY_TAP_CFG[2] origin:064-gtp-channel-conf 00_673 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXDLY_TAP_CFG[3] origin:064-gtp-channel-conf 01_673 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXDLY_TAP_CFG[4] origin:064-gtp-channel-conf 00_674 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXDLY_TAP_CFG[5] origin:064-gtp-channel-conf 01_674 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXDLY_TAP_CFG[6] origin:064-gtp-channel-conf 00_675 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXDLY_TAP_CFG[7] origin:064-gtp-channel-conf 01_675 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXDLY_TAP_CFG[8] origin:064-gtp-channel-conf 00_676 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXDLY_TAP_CFG[9] origin:064-gtp-channel-conf 01_676 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXDLY_TAP_CFG[10] origin:064-gtp-channel-conf 00_677 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXDLY_TAP_CFG[11] origin:064-gtp-channel-conf 01_677 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXDLY_TAP_CFG[12] origin:064-gtp-channel-conf 00_678 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXDLY_TAP_CFG[13] origin:064-gtp-channel-conf 01_678 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXDLY_TAP_CFG[14] origin:064-gtp-channel-conf 00_679 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXDLY_TAP_CFG[15] origin:064-gtp-channel-conf 01_679 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXGEARBOX_EN origin:064-gtp-channel-conf 01_607 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXISCANRESET_TIME[0] origin:064-gtp-channel-conf 01_123 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXISCANRESET_TIME[1] origin:064-gtp-channel-conf 00_124 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXISCANRESET_TIME[2] origin:064-gtp-channel-conf 01_124 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXISCANRESET_TIME[3] origin:064-gtp-channel-conf 00_125 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXISCANRESET_TIME[4] origin:064-gtp-channel-conf 01_125 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPM_BIAS_STARTUP_DISABLE[0] origin:064-gtp-channel-conf 03_391 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPM_CFG[0] origin:064-gtp-channel-conf 02_328 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPM_CFG[1] origin:064-gtp-channel-conf 03_328 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPM_CFG[2] origin:064-gtp-channel-conf 02_329 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPM_CFG[3] origin:064-gtp-channel-conf 03_329 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPM_CM_CFG[0] origin:064-gtp-channel-conf 02_430 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPM_GC_CFG[0] origin:064-gtp-channel-conf 02_432 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPM_GC_CFG[1] origin:064-gtp-channel-conf 03_432 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPM_GC_CFG[2] origin:064-gtp-channel-conf 02_433 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPM_GC_CFG[3] origin:064-gtp-channel-conf 03_433 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPM_GC_CFG[4] origin:064-gtp-channel-conf 02_434 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPM_GC_CFG[5] origin:064-gtp-channel-conf 03_434 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPM_GC_CFG[6] origin:064-gtp-channel-conf 02_435 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPM_GC_CFG[7] origin:064-gtp-channel-conf 03_435 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPM_GC_CFG[8] origin:064-gtp-channel-conf 02_436 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPM_GC_CFG2[0] origin:064-gtp-channel-conf 03_442 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPM_GC_CFG2[1] origin:064-gtp-channel-conf 02_443 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPM_GC_CFG2[2] origin:064-gtp-channel-conf 03_443 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPM_HF_CFG[0] origin:064-gtp-channel-conf 00_336 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPM_HF_CFG[1] origin:064-gtp-channel-conf 01_336 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPM_HF_CFG[2] origin:064-gtp-channel-conf 00_337 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPM_HF_CFG[3] origin:064-gtp-channel-conf 01_337 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPM_HF_CFG[4] origin:064-gtp-channel-conf 00_338 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPM_HF_CFG[5] origin:064-gtp-channel-conf 01_338 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPM_HF_CFG[6] origin:064-gtp-channel-conf 00_339 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPM_HF_CFG[7] origin:064-gtp-channel-conf 01_339 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPM_HF_CFG[8] origin:064-gtp-channel-conf 00_340 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPM_HF_CFG[9] origin:064-gtp-channel-conf 01_340 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPM_HF_CFG[10] origin:064-gtp-channel-conf 00_341 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPM_HF_CFG[11] origin:064-gtp-channel-conf 01_341 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPM_HF_CFG[12] origin:064-gtp-channel-conf 00_342 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPM_HF_CFG[13] origin:064-gtp-channel-conf 01_342 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPM_HF_CFG2[0] origin:064-gtp-channel-conf 02_424 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPM_HF_CFG2[1] origin:064-gtp-channel-conf 03_424 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPM_HF_CFG2[2] origin:064-gtp-channel-conf 02_425 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPM_HF_CFG2[3] origin:064-gtp-channel-conf 03_425 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPM_HF_CFG2[4] origin:064-gtp-channel-conf 02_426 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPM_HF_CFG3[0] origin:064-gtp-channel-conf 03_389 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPM_HF_CFG3[1] origin:064-gtp-channel-conf 02_390 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPM_HF_CFG3[2] origin:064-gtp-channel-conf 03_390 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPM_HF_CFG3[3] origin:064-gtp-channel-conf 02_391 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPM_HOLD_DURING_EIDLE[0] origin:064-gtp-channel-conf 00_247 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPM_INCM_CFG[0] origin:064-gtp-channel-conf 02_439 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPM_IPCM_CFG[0] origin:064-gtp-channel-conf 03_439 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPM_LF_CFG[0] origin:064-gtp-channel-conf 00_344 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPM_LF_CFG[1] origin:064-gtp-channel-conf 01_344 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPM_LF_CFG[2] origin:064-gtp-channel-conf 00_345 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPM_LF_CFG[3] origin:064-gtp-channel-conf 01_345 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPM_LF_CFG[4] origin:064-gtp-channel-conf 00_346 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPM_LF_CFG[5] origin:064-gtp-channel-conf 01_346 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPM_LF_CFG[6] origin:064-gtp-channel-conf 00_347 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPM_LF_CFG[7] origin:064-gtp-channel-conf 01_347 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPM_LF_CFG[8] origin:064-gtp-channel-conf 00_348 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPM_LF_CFG[9] origin:064-gtp-channel-conf 01_348 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPM_LF_CFG[10] origin:064-gtp-channel-conf 00_349 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPM_LF_CFG[11] origin:064-gtp-channel-conf 01_349 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPM_LF_CFG[12] origin:064-gtp-channel-conf 00_350 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPM_LF_CFG[13] origin:064-gtp-channel-conf 01_350 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPM_LF_CFG[14] origin:064-gtp-channel-conf 00_351 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPM_LF_CFG[15] origin:064-gtp-channel-conf 01_351 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPM_LF_CFG[16] origin:064-gtp-channel-conf 00_343 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPM_LF_CFG[17] origin:064-gtp-channel-conf 01_343 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPM_LF_CFG2[0] origin:064-gtp-channel-conf 03_426 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPM_LF_CFG2[1] origin:064-gtp-channel-conf 02_427 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPM_LF_CFG2[2] origin:064-gtp-channel-conf 03_427 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPM_LF_CFG2[3] origin:064-gtp-channel-conf 02_428 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPM_LF_CFG2[4] origin:064-gtp-channel-conf 03_428 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPM_OSINT_CFG[0] origin:064-gtp-channel-conf 02_440 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPM_OSINT_CFG[1] origin:064-gtp-channel-conf 03_440 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPM_OSINT_CFG[2] origin:064-gtp-channel-conf 02_441 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPM_CFG1[0] origin:064-gtp-channel-conf 02_330 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPMRESET_TIME[0] origin:064-gtp-channel-conf 00_112 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPMRESET_TIME[1] origin:064-gtp-channel-conf 01_112 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPMRESET_TIME[2] origin:064-gtp-channel-conf 00_113 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPMRESET_TIME[3] origin:064-gtp-channel-conf 01_113 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPMRESET_TIME[4] origin:064-gtp-channel-conf 00_114 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPMRESET_TIME[5] origin:064-gtp-channel-conf 01_114 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXLPMRESET_TIME[6] origin:064-gtp-channel-conf 00_115 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXOOB_CFG[0] origin:064-gtp-channel-conf 00_144 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXOOB_CFG[1] origin:064-gtp-channel-conf 01_144 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXOOB_CFG[2] origin:064-gtp-channel-conf 00_145 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXOOB_CFG[3] origin:064-gtp-channel-conf 01_145 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXOOB_CFG[4] origin:064-gtp-channel-conf 00_146 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXOOB_CFG[5] origin:064-gtp-channel-conf 01_146 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXOOB_CFG[6] origin:064-gtp-channel-conf 00_147 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXOOB_CLK_CFG.FABRIC origin:064-gtp-channel-conf 03_129 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXOSCALRESET_TIME[0] origin:064-gtp-channel-conf 00_187 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXOSCALRESET_TIME[1] origin:064-gtp-channel-conf 01_187 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXOSCALRESET_TIME[2] origin:064-gtp-channel-conf 00_188 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXOSCALRESET_TIME[3] origin:064-gtp-channel-conf 01_188 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXOSCALRESET_TIME[4] origin:064-gtp-channel-conf 00_189 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXOSCALRESET_TIMEOUT[0] origin:064-gtp-channel-conf 01_189 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXOSCALRESET_TIMEOUT[1] origin:064-gtp-channel-conf 00_190 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXOSCALRESET_TIMEOUT[2] origin:064-gtp-channel-conf 01_190 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXOSCALRESET_TIMEOUT[3] origin:064-gtp-channel-conf 00_191 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXOSCALRESET_TIMEOUT[4] origin:064-gtp-channel-conf 01_191 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXOUT_DIV[0] origin:064-gtp-channel-conf 02_384 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXOUT_DIV[1] origin:064-gtp-channel-conf 03_384 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXPCSRESET_TIME[0] origin:064-gtp-channel-conf 01_115 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXPCSRESET_TIME[1] origin:064-gtp-channel-conf 00_116 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXPCSRESET_TIME[2] origin:064-gtp-channel-conf 01_116 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXPCSRESET_TIME[3] origin:064-gtp-channel-conf 00_117 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXPCSRESET_TIME[4] origin:064-gtp-channel-conf 01_117 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXPH_CFG[0] origin:064-gtp-channel-conf 02_584 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXPH_CFG[1] origin:064-gtp-channel-conf 03_584 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXPH_CFG[2] origin:064-gtp-channel-conf 02_585 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXPH_CFG[3] origin:064-gtp-channel-conf 03_585 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXPH_CFG[4] origin:064-gtp-channel-conf 02_586 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXPH_CFG[5] origin:064-gtp-channel-conf 03_586 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXPH_CFG[6] origin:064-gtp-channel-conf 02_587 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXPH_CFG[7] origin:064-gtp-channel-conf 03_587 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXPH_CFG[8] origin:064-gtp-channel-conf 02_588 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXPH_CFG[9] origin:064-gtp-channel-conf 03_588 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXPH_CFG[10] origin:064-gtp-channel-conf 02_589 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXPH_CFG[11] origin:064-gtp-channel-conf 03_589 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXPH_CFG[12] origin:064-gtp-channel-conf 02_590 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXPH_CFG[13] origin:064-gtp-channel-conf 03_590 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXPH_CFG[14] origin:064-gtp-channel-conf 02_591 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXPH_CFG[15] origin:064-gtp-channel-conf 03_591 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXPH_CFG[16] origin:064-gtp-channel-conf 02_592 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXPH_CFG[17] origin:064-gtp-channel-conf 03_592 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXPH_CFG[18] origin:064-gtp-channel-conf 02_593 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXPH_CFG[19] origin:064-gtp-channel-conf 03_593 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXPH_CFG[20] origin:064-gtp-channel-conf 02_594 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXPH_CFG[21] origin:064-gtp-channel-conf 03_594 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXPH_CFG[22] origin:064-gtp-channel-conf 02_595 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXPH_CFG[23] origin:064-gtp-channel-conf 03_595 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXPH_MONITOR_SEL[0] origin:064-gtp-channel-conf 00_700 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXPH_MONITOR_SEL[1] origin:064-gtp-channel-conf 01_700 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXPH_MONITOR_SEL[2] origin:064-gtp-channel-conf 00_701 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXPH_MONITOR_SEL[3] origin:064-gtp-channel-conf 01_701 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXPH_MONITOR_SEL[4] origin:064-gtp-channel-conf 00_702 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXPHDLY_CFG[0] origin:064-gtp-channel-conf 02_600 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXPHDLY_CFG[1] origin:064-gtp-channel-conf 03_600 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXPHDLY_CFG[2] origin:064-gtp-channel-conf 02_601 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXPHDLY_CFG[3] origin:064-gtp-channel-conf 03_601 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXPHDLY_CFG[4] origin:064-gtp-channel-conf 02_602 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXPHDLY_CFG[5] origin:064-gtp-channel-conf 03_602 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXPHDLY_CFG[6] origin:064-gtp-channel-conf 02_603 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXPHDLY_CFG[7] origin:064-gtp-channel-conf 03_603 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXPHDLY_CFG[8] origin:064-gtp-channel-conf 02_604 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXPHDLY_CFG[9] origin:064-gtp-channel-conf 03_604 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXPHDLY_CFG[10] origin:064-gtp-channel-conf 02_605 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXPHDLY_CFG[11] origin:064-gtp-channel-conf 03_605 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXPHDLY_CFG[12] origin:064-gtp-channel-conf 02_606 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXPHDLY_CFG[13] origin:064-gtp-channel-conf 03_606 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXPHDLY_CFG[14] origin:064-gtp-channel-conf 02_607 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXPHDLY_CFG[15] origin:064-gtp-channel-conf 03_607 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXPHDLY_CFG[16] origin:064-gtp-channel-conf 02_608 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXPHDLY_CFG[17] origin:064-gtp-channel-conf 03_608 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXPHDLY_CFG[18] origin:064-gtp-channel-conf 02_609 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXPHDLY_CFG[19] origin:064-gtp-channel-conf 03_609 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXPHDLY_CFG[20] origin:064-gtp-channel-conf 02_610 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXPHDLY_CFG[21] origin:064-gtp-channel-conf 03_610 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXPHDLY_CFG[22] origin:064-gtp-channel-conf 02_611 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXPHDLY_CFG[23] origin:064-gtp-channel-conf 03_611 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXPI_CFG0[0] origin:064-gtp-channel-conf 03_430 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXPI_CFG0[1] origin:064-gtp-channel-conf 02_431 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXPI_CFG0[2] origin:064-gtp-channel-conf 03_431 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXPI_CFG1[0] origin:064-gtp-channel-conf 02_442 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXPI_CFG2[0] origin:064-gtp-channel-conf 03_441 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXPMARESET_TIME[0] origin:064-gtp-channel-conf 00_104 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXPMARESET_TIME[1] origin:064-gtp-channel-conf 01_104 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXPMARESET_TIME[2] origin:064-gtp-channel-conf 00_105 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXPMARESET_TIME[3] origin:064-gtp-channel-conf 01_105 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXPMARESET_TIME[4] origin:064-gtp-channel-conf 00_106 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXPRBS_ERR_LOOPBACK[0] origin:064-gtp-channel-conf 00_136 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXSLIDE_AUTO_WAIT[0] origin:064-gtp-channel-conf 00_520 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXSLIDE_AUTO_WAIT[1] origin:064-gtp-channel-conf 01_520 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXSLIDE_AUTO_WAIT[2] origin:064-gtp-channel-conf 00_521 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXSLIDE_AUTO_WAIT[3] origin:064-gtp-channel-conf 01_521 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXSLIDE_MODE.AUTO origin:064-gtp-channel-conf !01_519 00_519 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXSLIDE_MODE.PCS origin:064-gtp-channel-conf !00_519 01_519 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXSLIDE_MODE.PMA origin:064-gtp-channel-conf 00_519 01_519 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXSYNC_MULTILANE[0] origin:064-gtp-channel-conf 00_133 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXSYNC_OVRD[0] origin:064-gtp-channel-conf 01_135 -GTP_CHANNEL_3_MID_LEFT.GTPE2.RXSYNC_SKIP_DA[0] origin:064-gtp-channel-conf 01_134 -GTP_CHANNEL_3_MID_LEFT.GTPE2.SAS_MAX_COM[0] origin:064-gtp-channel-conf 00_171 -GTP_CHANNEL_3_MID_LEFT.GTPE2.SAS_MAX_COM[1] origin:064-gtp-channel-conf 01_171 -GTP_CHANNEL_3_MID_LEFT.GTPE2.SAS_MAX_COM[2] origin:064-gtp-channel-conf 00_172 -GTP_CHANNEL_3_MID_LEFT.GTPE2.SAS_MAX_COM[3] origin:064-gtp-channel-conf 01_172 -GTP_CHANNEL_3_MID_LEFT.GTPE2.SAS_MAX_COM[4] origin:064-gtp-channel-conf 00_173 -GTP_CHANNEL_3_MID_LEFT.GTPE2.SAS_MAX_COM[5] origin:064-gtp-channel-conf 01_173 -GTP_CHANNEL_3_MID_LEFT.GTPE2.SAS_MAX_COM[6] origin:064-gtp-channel-conf 00_174 -GTP_CHANNEL_3_MID_LEFT.GTPE2.SAS_MIN_COM[0] origin:064-gtp-channel-conf 01_156 -GTP_CHANNEL_3_MID_LEFT.GTPE2.SAS_MIN_COM[1] origin:064-gtp-channel-conf 00_157 -GTP_CHANNEL_3_MID_LEFT.GTPE2.SAS_MIN_COM[2] origin:064-gtp-channel-conf 01_157 -GTP_CHANNEL_3_MID_LEFT.GTPE2.SAS_MIN_COM[3] origin:064-gtp-channel-conf 00_158 -GTP_CHANNEL_3_MID_LEFT.GTPE2.SAS_MIN_COM[4] origin:064-gtp-channel-conf 01_158 -GTP_CHANNEL_3_MID_LEFT.GTPE2.SAS_MIN_COM[5] origin:064-gtp-channel-conf 00_159 -GTP_CHANNEL_3_MID_LEFT.GTPE2.SATA_BURST_SEQ_LEN[0] origin:064-gtp-channel-conf 00_150 -GTP_CHANNEL_3_MID_LEFT.GTPE2.SATA_BURST_SEQ_LEN[1] origin:064-gtp-channel-conf 01_150 -GTP_CHANNEL_3_MID_LEFT.GTPE2.SATA_BURST_SEQ_LEN[2] origin:064-gtp-channel-conf 00_151 -GTP_CHANNEL_3_MID_LEFT.GTPE2.SATA_BURST_SEQ_LEN[3] origin:064-gtp-channel-conf 01_151 -GTP_CHANNEL_3_MID_LEFT.GTPE2.SATA_BURST_VAL[0] origin:064-gtp-channel-conf 01_147 -GTP_CHANNEL_3_MID_LEFT.GTPE2.SATA_BURST_VAL[1] origin:064-gtp-channel-conf 00_148 -GTP_CHANNEL_3_MID_LEFT.GTPE2.SATA_BURST_VAL[2] origin:064-gtp-channel-conf 01_148 -GTP_CHANNEL_3_MID_LEFT.GTPE2.SATA_EIDLE_VAL[0] origin:064-gtp-channel-conf 00_152 -GTP_CHANNEL_3_MID_LEFT.GTPE2.SATA_EIDLE_VAL[1] origin:064-gtp-channel-conf 01_152 -GTP_CHANNEL_3_MID_LEFT.GTPE2.SATA_EIDLE_VAL[2] origin:064-gtp-channel-conf 00_153 -GTP_CHANNEL_3_MID_LEFT.GTPE2.SATA_MAX_BURST[0] origin:064-gtp-channel-conf 00_168 -GTP_CHANNEL_3_MID_LEFT.GTPE2.SATA_MAX_BURST[1] origin:064-gtp-channel-conf 01_168 -GTP_CHANNEL_3_MID_LEFT.GTPE2.SATA_MAX_BURST[2] origin:064-gtp-channel-conf 00_169 -GTP_CHANNEL_3_MID_LEFT.GTPE2.SATA_MAX_BURST[3] origin:064-gtp-channel-conf 01_169 -GTP_CHANNEL_3_MID_LEFT.GTPE2.SATA_MAX_BURST[4] origin:064-gtp-channel-conf 00_170 -GTP_CHANNEL_3_MID_LEFT.GTPE2.SATA_MAX_BURST[5] origin:064-gtp-channel-conf 01_170 -GTP_CHANNEL_3_MID_LEFT.GTPE2.SATA_MAX_INIT[0] origin:064-gtp-channel-conf 00_176 -GTP_CHANNEL_3_MID_LEFT.GTPE2.SATA_MAX_INIT[1] origin:064-gtp-channel-conf 01_176 -GTP_CHANNEL_3_MID_LEFT.GTPE2.SATA_MAX_INIT[2] origin:064-gtp-channel-conf 00_177 -GTP_CHANNEL_3_MID_LEFT.GTPE2.SATA_MAX_INIT[3] origin:064-gtp-channel-conf 01_177 -GTP_CHANNEL_3_MID_LEFT.GTPE2.SATA_MAX_INIT[4] origin:064-gtp-channel-conf 00_178 -GTP_CHANNEL_3_MID_LEFT.GTPE2.SATA_MAX_INIT[5] origin:064-gtp-channel-conf 01_178 -GTP_CHANNEL_3_MID_LEFT.GTPE2.SATA_MAX_WAKE[0] origin:064-gtp-channel-conf 00_179 -GTP_CHANNEL_3_MID_LEFT.GTPE2.SATA_MAX_WAKE[1] origin:064-gtp-channel-conf 01_179 -GTP_CHANNEL_3_MID_LEFT.GTPE2.SATA_MAX_WAKE[2] origin:064-gtp-channel-conf 00_180 -GTP_CHANNEL_3_MID_LEFT.GTPE2.SATA_MAX_WAKE[3] origin:064-gtp-channel-conf 01_180 -GTP_CHANNEL_3_MID_LEFT.GTPE2.SATA_MAX_WAKE[4] origin:064-gtp-channel-conf 00_181 -GTP_CHANNEL_3_MID_LEFT.GTPE2.SATA_MAX_WAKE[5] origin:064-gtp-channel-conf 01_181 -GTP_CHANNEL_3_MID_LEFT.GTPE2.SATA_MIN_BURST[0] origin:064-gtp-channel-conf 01_153 -GTP_CHANNEL_3_MID_LEFT.GTPE2.SATA_MIN_BURST[1] origin:064-gtp-channel-conf 00_154 -GTP_CHANNEL_3_MID_LEFT.GTPE2.SATA_MIN_BURST[2] origin:064-gtp-channel-conf 01_154 -GTP_CHANNEL_3_MID_LEFT.GTPE2.SATA_MIN_BURST[3] origin:064-gtp-channel-conf 00_155 -GTP_CHANNEL_3_MID_LEFT.GTPE2.SATA_MIN_BURST[4] origin:064-gtp-channel-conf 01_155 -GTP_CHANNEL_3_MID_LEFT.GTPE2.SATA_MIN_BURST[5] origin:064-gtp-channel-conf 00_156 -GTP_CHANNEL_3_MID_LEFT.GTPE2.SATA_MIN_INIT[0] origin:064-gtp-channel-conf 00_160 -GTP_CHANNEL_3_MID_LEFT.GTPE2.SATA_MIN_INIT[1] origin:064-gtp-channel-conf 01_160 -GTP_CHANNEL_3_MID_LEFT.GTPE2.SATA_MIN_INIT[2] origin:064-gtp-channel-conf 00_161 -GTP_CHANNEL_3_MID_LEFT.GTPE2.SATA_MIN_INIT[3] origin:064-gtp-channel-conf 01_161 -GTP_CHANNEL_3_MID_LEFT.GTPE2.SATA_MIN_INIT[4] origin:064-gtp-channel-conf 00_162 -GTP_CHANNEL_3_MID_LEFT.GTPE2.SATA_MIN_INIT[5] origin:064-gtp-channel-conf 01_162 -GTP_CHANNEL_3_MID_LEFT.GTPE2.SATA_MIN_WAKE[0] origin:064-gtp-channel-conf 00_163 -GTP_CHANNEL_3_MID_LEFT.GTPE2.SATA_MIN_WAKE[1] origin:064-gtp-channel-conf 01_163 -GTP_CHANNEL_3_MID_LEFT.GTPE2.SATA_MIN_WAKE[2] origin:064-gtp-channel-conf 00_164 -GTP_CHANNEL_3_MID_LEFT.GTPE2.SATA_MIN_WAKE[3] origin:064-gtp-channel-conf 01_164 -GTP_CHANNEL_3_MID_LEFT.GTPE2.SATA_MIN_WAKE[4] origin:064-gtp-channel-conf 00_165 -GTP_CHANNEL_3_MID_LEFT.GTPE2.SATA_MIN_WAKE[5] origin:064-gtp-channel-conf 01_165 -GTP_CHANNEL_3_MID_LEFT.GTPE2.SATA_PLL_CFG.VCO_1500MHZ origin:064-gtp-channel-conf 02_55 -GTP_CHANNEL_3_MID_LEFT.GTPE2.SATA_PLL_CFG.VCO_750MHZ origin:064-gtp-channel-conf 03_55 -GTP_CHANNEL_3_MID_LEFT.GTPE2.SHOW_REALIGN_COMMA origin:064-gtp-channel-conf 01_522 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TERM_RCAL_CFG[0] origin:064-gtp-channel-conf 02_136 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TERM_RCAL_CFG[1] origin:064-gtp-channel-conf 03_136 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TERM_RCAL_CFG[2] origin:064-gtp-channel-conf 02_137 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TERM_RCAL_CFG[3] origin:064-gtp-channel-conf 03_137 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TERM_RCAL_CFG[4] origin:064-gtp-channel-conf 02_138 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TERM_RCAL_CFG[5] origin:064-gtp-channel-conf 03_138 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TERM_RCAL_CFG[6] origin:064-gtp-channel-conf 02_139 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TERM_RCAL_CFG[7] origin:064-gtp-channel-conf 03_139 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TERM_RCAL_CFG[8] origin:064-gtp-channel-conf 02_140 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TERM_RCAL_CFG[9] origin:064-gtp-channel-conf 03_140 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TERM_RCAL_CFG[10] origin:064-gtp-channel-conf 02_141 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TERM_RCAL_CFG[11] origin:064-gtp-channel-conf 03_141 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TERM_RCAL_CFG[12] origin:064-gtp-channel-conf 02_142 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TERM_RCAL_CFG[13] origin:064-gtp-channel-conf 03_142 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TERM_RCAL_CFG[14] origin:064-gtp-channel-conf 02_143 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TERM_RCAL_OVRD[0] origin:064-gtp-channel-conf 03_150 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TERM_RCAL_OVRD[1] origin:064-gtp-channel-conf 02_151 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TERM_RCAL_OVRD[2] origin:064-gtp-channel-conf 03_151 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TRANS_TIME_RATE[0] origin:064-gtp-channel-conf 00_192 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TRANS_TIME_RATE[1] origin:064-gtp-channel-conf 01_192 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TRANS_TIME_RATE[2] origin:064-gtp-channel-conf 00_193 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TRANS_TIME_RATE[3] origin:064-gtp-channel-conf 01_193 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TRANS_TIME_RATE[4] origin:064-gtp-channel-conf 00_194 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TRANS_TIME_RATE[5] origin:064-gtp-channel-conf 01_194 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TRANS_TIME_RATE[6] origin:064-gtp-channel-conf 00_195 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TRANS_TIME_RATE[7] origin:064-gtp-channel-conf 01_195 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TST_RSV[0] origin:064-gtp-channel-conf 02_504 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TST_RSV[1] origin:064-gtp-channel-conf 03_504 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TST_RSV[2] origin:064-gtp-channel-conf 02_505 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TST_RSV[3] origin:064-gtp-channel-conf 03_505 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TST_RSV[4] origin:064-gtp-channel-conf 02_506 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TST_RSV[5] origin:064-gtp-channel-conf 03_506 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TST_RSV[6] origin:064-gtp-channel-conf 02_507 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TST_RSV[7] origin:064-gtp-channel-conf 03_507 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TST_RSV[8] origin:064-gtp-channel-conf 02_508 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TST_RSV[9] origin:064-gtp-channel-conf 03_508 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TST_RSV[10] origin:064-gtp-channel-conf 02_509 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TST_RSV[11] origin:064-gtp-channel-conf 03_509 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TST_RSV[12] origin:064-gtp-channel-conf 02_510 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TST_RSV[13] origin:064-gtp-channel-conf 03_510 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TST_RSV[14] origin:064-gtp-channel-conf 02_511 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TST_RSV[15] origin:064-gtp-channel-conf 03_511 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TST_RSV[16] origin:064-gtp-channel-conf 02_512 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TST_RSV[17] origin:064-gtp-channel-conf 03_512 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TST_RSV[18] origin:064-gtp-channel-conf 02_513 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TST_RSV[19] origin:064-gtp-channel-conf 03_513 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TST_RSV[20] origin:064-gtp-channel-conf 02_514 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TST_RSV[21] origin:064-gtp-channel-conf 03_514 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TST_RSV[22] origin:064-gtp-channel-conf 02_515 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TST_RSV[23] origin:064-gtp-channel-conf 03_515 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TST_RSV[24] origin:064-gtp-channel-conf 02_516 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TST_RSV[25] origin:064-gtp-channel-conf 03_516 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TST_RSV[26] origin:064-gtp-channel-conf 02_517 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TST_RSV[27] origin:064-gtp-channel-conf 03_517 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TST_RSV[28] origin:064-gtp-channel-conf 02_518 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TST_RSV[29] origin:064-gtp-channel-conf 03_518 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TST_RSV[30] origin:064-gtp-channel-conf 02_519 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TST_RSV[31] origin:064-gtp-channel-conf 03_519 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_CLKMUX_EN[0] origin:064-gtp-channel-conf 03_128 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_DATA_WIDTH[0] origin:064-gtp-channel-conf 02_152 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_DATA_WIDTH[1] origin:064-gtp-channel-conf 03_152 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_DATA_WIDTH[2] origin:064-gtp-channel-conf 02_153 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_DRIVE_MODE.PIPE origin:064-gtp-channel-conf 00_200 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_EIDLE_ASSERT_DELAY[0] origin:064-gtp-channel-conf 00_203 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_EIDLE_ASSERT_DELAY[1] origin:064-gtp-channel-conf 01_203 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_EIDLE_ASSERT_DELAY[2] origin:064-gtp-channel-conf 00_204 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_EIDLE_DEASSERT_DELAY[0] origin:064-gtp-channel-conf 01_204 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_EIDLE_DEASSERT_DELAY[1] origin:064-gtp-channel-conf 00_205 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_EIDLE_DEASSERT_DELAY[2] origin:064-gtp-channel-conf 01_205 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_LOOPBACK_DRIVE_HIZ origin:064-gtp-channel-conf 01_202 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_MAINCURSOR_SEL[0] origin:064-gtp-channel-conf 03_289 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_MARGIN_FULL_0[0] origin:064-gtp-channel-conf 02_232 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_MARGIN_FULL_0[1] origin:064-gtp-channel-conf 03_232 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_MARGIN_FULL_0[2] origin:064-gtp-channel-conf 02_233 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_MARGIN_FULL_0[3] origin:064-gtp-channel-conf 03_233 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_MARGIN_FULL_0[4] origin:064-gtp-channel-conf 02_234 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_MARGIN_FULL_0[5] origin:064-gtp-channel-conf 03_234 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_MARGIN_FULL_0[6] origin:064-gtp-channel-conf 02_235 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_MARGIN_FULL_1[0] origin:064-gtp-channel-conf 02_236 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_MARGIN_FULL_1[1] origin:064-gtp-channel-conf 03_236 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_MARGIN_FULL_1[2] origin:064-gtp-channel-conf 02_237 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_MARGIN_FULL_1[3] origin:064-gtp-channel-conf 03_237 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_MARGIN_FULL_1[4] origin:064-gtp-channel-conf 02_238 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_MARGIN_FULL_1[5] origin:064-gtp-channel-conf 03_238 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_MARGIN_FULL_1[6] origin:064-gtp-channel-conf 02_239 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_MARGIN_FULL_2[0] origin:064-gtp-channel-conf 02_240 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_MARGIN_FULL_2[1] origin:064-gtp-channel-conf 03_240 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_MARGIN_FULL_2[2] origin:064-gtp-channel-conf 02_241 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_MARGIN_FULL_2[3] origin:064-gtp-channel-conf 03_241 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_MARGIN_FULL_2[4] origin:064-gtp-channel-conf 02_242 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_MARGIN_FULL_2[5] origin:064-gtp-channel-conf 03_242 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_MARGIN_FULL_2[6] origin:064-gtp-channel-conf 02_243 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_MARGIN_FULL_3[0] origin:064-gtp-channel-conf 02_244 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_MARGIN_FULL_3[1] origin:064-gtp-channel-conf 03_244 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_MARGIN_FULL_3[2] origin:064-gtp-channel-conf 02_245 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_MARGIN_FULL_3[3] origin:064-gtp-channel-conf 03_245 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_MARGIN_FULL_3[4] origin:064-gtp-channel-conf 02_246 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_MARGIN_FULL_3[5] origin:064-gtp-channel-conf 03_246 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_MARGIN_FULL_3[6] origin:064-gtp-channel-conf 02_247 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_MARGIN_FULL_4[0] origin:064-gtp-channel-conf 02_248 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_MARGIN_FULL_4[1] origin:064-gtp-channel-conf 03_248 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_MARGIN_FULL_4[2] origin:064-gtp-channel-conf 02_249 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_MARGIN_FULL_4[3] origin:064-gtp-channel-conf 03_249 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_MARGIN_FULL_4[4] origin:064-gtp-channel-conf 02_250 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_MARGIN_FULL_4[5] origin:064-gtp-channel-conf 03_250 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_MARGIN_FULL_4[6] origin:064-gtp-channel-conf 02_251 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_MARGIN_LOW_0[0] origin:064-gtp-channel-conf 02_252 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_MARGIN_LOW_0[1] origin:064-gtp-channel-conf 03_252 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_MARGIN_LOW_0[2] origin:064-gtp-channel-conf 02_253 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_MARGIN_LOW_0[3] origin:064-gtp-channel-conf 03_253 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_MARGIN_LOW_0[4] origin:064-gtp-channel-conf 02_254 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_MARGIN_LOW_0[5] origin:064-gtp-channel-conf 03_254 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_MARGIN_LOW_0[6] origin:064-gtp-channel-conf 02_255 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_MARGIN_LOW_1[0] origin:064-gtp-channel-conf 02_256 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_MARGIN_LOW_1[1] origin:064-gtp-channel-conf 03_256 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_MARGIN_LOW_1[2] origin:064-gtp-channel-conf 02_257 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_MARGIN_LOW_1[3] origin:064-gtp-channel-conf 03_257 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_MARGIN_LOW_1[4] origin:064-gtp-channel-conf 02_258 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_MARGIN_LOW_1[5] origin:064-gtp-channel-conf 03_258 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_MARGIN_LOW_1[6] origin:064-gtp-channel-conf 02_259 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_MARGIN_LOW_2[0] origin:064-gtp-channel-conf 02_260 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_MARGIN_LOW_2[1] origin:064-gtp-channel-conf 03_260 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_MARGIN_LOW_2[2] origin:064-gtp-channel-conf 02_261 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_MARGIN_LOW_2[3] origin:064-gtp-channel-conf 03_261 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_MARGIN_LOW_2[4] origin:064-gtp-channel-conf 02_262 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_MARGIN_LOW_2[5] origin:064-gtp-channel-conf 03_262 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_MARGIN_LOW_2[6] origin:064-gtp-channel-conf 02_263 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_MARGIN_LOW_3[0] origin:064-gtp-channel-conf 02_264 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_MARGIN_LOW_3[1] origin:064-gtp-channel-conf 03_264 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_MARGIN_LOW_3[2] origin:064-gtp-channel-conf 02_265 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_MARGIN_LOW_3[3] origin:064-gtp-channel-conf 03_265 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_MARGIN_LOW_3[4] origin:064-gtp-channel-conf 02_266 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_MARGIN_LOW_3[5] origin:064-gtp-channel-conf 03_266 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_MARGIN_LOW_3[6] origin:064-gtp-channel-conf 02_267 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_MARGIN_LOW_4[0] origin:064-gtp-channel-conf 02_268 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_MARGIN_LOW_4[1] origin:064-gtp-channel-conf 03_268 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_MARGIN_LOW_4[2] origin:064-gtp-channel-conf 02_269 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_MARGIN_LOW_4[3] origin:064-gtp-channel-conf 03_269 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_MARGIN_LOW_4[4] origin:064-gtp-channel-conf 02_270 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_MARGIN_LOW_4[5] origin:064-gtp-channel-conf 03_270 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_MARGIN_LOW_4[6] origin:064-gtp-channel-conf 02_271 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_PREDRIVER_MODE[0] origin:064-gtp-channel-conf 00_206 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_RXDETECT_CFG[0] origin:064-gtp-channel-conf 02_296 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_RXDETECT_CFG[1] origin:064-gtp-channel-conf 03_296 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_RXDETECT_CFG[2] origin:064-gtp-channel-conf 02_297 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_RXDETECT_CFG[3] origin:064-gtp-channel-conf 03_297 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_RXDETECT_CFG[4] origin:064-gtp-channel-conf 02_298 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_RXDETECT_CFG[5] origin:064-gtp-channel-conf 03_298 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_RXDETECT_CFG[6] origin:064-gtp-channel-conf 02_299 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_RXDETECT_CFG[7] origin:064-gtp-channel-conf 03_299 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_RXDETECT_CFG[8] origin:064-gtp-channel-conf 02_300 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_RXDETECT_CFG[9] origin:064-gtp-channel-conf 03_300 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_RXDETECT_CFG[10] origin:064-gtp-channel-conf 02_301 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_RXDETECT_CFG[11] origin:064-gtp-channel-conf 03_301 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_RXDETECT_CFG[12] origin:064-gtp-channel-conf 02_302 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_RXDETECT_CFG[13] origin:064-gtp-channel-conf 03_302 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_RXDETECT_REF[0] origin:064-gtp-channel-conf 02_292 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_RXDETECT_REF[1] origin:064-gtp-channel-conf 03_292 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_RXDETECT_REF[2] origin:064-gtp-channel-conf 02_293 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_XCLK_SEL.TXUSR origin:064-gtp-channel-conf 03_11 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_CLK25_DIV[0] origin:064-gtp-channel-conf 02_144 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_CLK25_DIV[1] origin:064-gtp-channel-conf 03_144 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_CLK25_DIV[2] origin:064-gtp-channel-conf 02_145 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_CLK25_DIV[3] origin:064-gtp-channel-conf 03_145 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_CLK25_DIV[4] origin:064-gtp-channel-conf 02_146 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_DEEMPH0[0] origin:064-gtp-channel-conf 02_272 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_DEEMPH0[1] origin:064-gtp-channel-conf 03_272 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_DEEMPH0[2] origin:064-gtp-channel-conf 02_273 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_DEEMPH0[3] origin:064-gtp-channel-conf 03_273 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_DEEMPH0[4] origin:064-gtp-channel-conf 02_274 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_DEEMPH0[5] origin:064-gtp-channel-conf 03_274 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_DEEMPH1[0] origin:064-gtp-channel-conf 02_276 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_DEEMPH1[1] origin:064-gtp-channel-conf 03_276 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_DEEMPH1[2] origin:064-gtp-channel-conf 02_277 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_DEEMPH1[3] origin:064-gtp-channel-conf 03_277 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_DEEMPH1[4] origin:064-gtp-channel-conf 02_278 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TX_DEEMPH1[5] origin:064-gtp-channel-conf 03_278 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXBUF_EN origin:064-gtp-channel-conf 00_231 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXBUF_RESET_ON_RATE_CHANGE origin:064-gtp-channel-conf 01_231 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXDLY_CFG[0] origin:064-gtp-channel-conf 02_80 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXDLY_CFG[1] origin:064-gtp-channel-conf 03_80 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXDLY_CFG[2] origin:064-gtp-channel-conf 02_81 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXDLY_CFG[3] origin:064-gtp-channel-conf 03_81 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXDLY_CFG[4] origin:064-gtp-channel-conf 02_82 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXDLY_CFG[5] origin:064-gtp-channel-conf 03_82 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXDLY_CFG[6] origin:064-gtp-channel-conf 02_83 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXDLY_CFG[7] origin:064-gtp-channel-conf 03_83 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXDLY_CFG[8] origin:064-gtp-channel-conf 02_84 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXDLY_CFG[9] origin:064-gtp-channel-conf 03_84 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXDLY_CFG[10] origin:064-gtp-channel-conf 02_85 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXDLY_CFG[11] origin:064-gtp-channel-conf 03_85 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXDLY_CFG[12] origin:064-gtp-channel-conf 02_86 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXDLY_CFG[13] origin:064-gtp-channel-conf 03_86 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXDLY_CFG[14] origin:064-gtp-channel-conf 02_87 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXDLY_CFG[15] origin:064-gtp-channel-conf 03_87 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXDLY_LCFG[0] origin:064-gtp-channel-conf 02_568 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXDLY_LCFG[1] origin:064-gtp-channel-conf 03_568 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXDLY_LCFG[2] origin:064-gtp-channel-conf 02_569 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXDLY_LCFG[3] origin:064-gtp-channel-conf 03_569 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXDLY_LCFG[4] origin:064-gtp-channel-conf 02_570 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXDLY_LCFG[5] origin:064-gtp-channel-conf 03_570 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXDLY_LCFG[6] origin:064-gtp-channel-conf 02_571 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXDLY_LCFG[7] origin:064-gtp-channel-conf 03_571 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXDLY_LCFG[8] origin:064-gtp-channel-conf 02_572 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXDLY_TAP_CFG[0] origin:064-gtp-channel-conf 02_88 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXDLY_TAP_CFG[1] origin:064-gtp-channel-conf 03_88 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXDLY_TAP_CFG[2] origin:064-gtp-channel-conf 02_89 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXDLY_TAP_CFG[3] origin:064-gtp-channel-conf 03_89 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXDLY_TAP_CFG[4] origin:064-gtp-channel-conf 02_90 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXDLY_TAP_CFG[5] origin:064-gtp-channel-conf 03_90 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXDLY_TAP_CFG[6] origin:064-gtp-channel-conf 02_91 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXDLY_TAP_CFG[7] origin:064-gtp-channel-conf 03_91 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXDLY_TAP_CFG[8] origin:064-gtp-channel-conf 02_92 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXDLY_TAP_CFG[9] origin:064-gtp-channel-conf 03_92 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXDLY_TAP_CFG[10] origin:064-gtp-channel-conf 02_93 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXDLY_TAP_CFG[11] origin:064-gtp-channel-conf 03_93 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXDLY_TAP_CFG[12] origin:064-gtp-channel-conf 02_94 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXDLY_TAP_CFG[13] origin:064-gtp-channel-conf 03_94 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXDLY_TAP_CFG[14] origin:064-gtp-channel-conf 02_95 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXDLY_TAP_CFG[15] origin:064-gtp-channel-conf 03_95 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXGEARBOX_EN origin:064-gtp-channel-conf 01_226 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXOOB_CFG[0] origin:064-gtp-channel-conf 03_20 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXOUT_DIV[0] origin:064-gtp-channel-conf 02_386 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXOUT_DIV[1] origin:064-gtp-channel-conf 03_386 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPCSRESET_TIME[0] origin:064-gtp-channel-conf 01_130 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPCSRESET_TIME[1] origin:064-gtp-channel-conf 00_131 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPCSRESET_TIME[2] origin:064-gtp-channel-conf 01_131 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPCSRESET_TIME[3] origin:064-gtp-channel-conf 00_132 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPCSRESET_TIME[4] origin:064-gtp-channel-conf 01_132 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPH_CFG[0] origin:064-gtp-channel-conf 02_96 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPH_CFG[1] origin:064-gtp-channel-conf 03_96 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPH_CFG[2] origin:064-gtp-channel-conf 02_97 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPH_CFG[3] origin:064-gtp-channel-conf 03_97 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPH_CFG[4] origin:064-gtp-channel-conf 02_98 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPH_CFG[5] origin:064-gtp-channel-conf 03_98 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPH_CFG[6] origin:064-gtp-channel-conf 02_99 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPH_CFG[7] origin:064-gtp-channel-conf 03_99 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPH_CFG[8] origin:064-gtp-channel-conf 02_100 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPH_CFG[9] origin:064-gtp-channel-conf 03_100 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPH_CFG[10] origin:064-gtp-channel-conf 02_101 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPH_CFG[11] origin:064-gtp-channel-conf 03_101 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPH_CFG[12] origin:064-gtp-channel-conf 02_102 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPH_CFG[13] origin:064-gtp-channel-conf 03_102 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPH_CFG[14] origin:064-gtp-channel-conf 02_103 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPH_CFG[15] origin:064-gtp-channel-conf 03_103 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPH_MONITOR_SEL[0] origin:064-gtp-channel-conf 02_108 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPH_MONITOR_SEL[1] origin:064-gtp-channel-conf 03_108 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPH_MONITOR_SEL[2] origin:064-gtp-channel-conf 02_109 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPH_MONITOR_SEL[3] origin:064-gtp-channel-conf 03_109 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPH_MONITOR_SEL[4] origin:064-gtp-channel-conf 02_110 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPHDLY_CFG[0] origin:064-gtp-channel-conf 02_64 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPHDLY_CFG[1] origin:064-gtp-channel-conf 03_64 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPHDLY_CFG[2] origin:064-gtp-channel-conf 02_65 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPHDLY_CFG[3] origin:064-gtp-channel-conf 03_65 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPHDLY_CFG[4] origin:064-gtp-channel-conf 02_66 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPHDLY_CFG[5] origin:064-gtp-channel-conf 03_66 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPHDLY_CFG[6] origin:064-gtp-channel-conf 02_67 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPHDLY_CFG[7] origin:064-gtp-channel-conf 03_67 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPHDLY_CFG[8] origin:064-gtp-channel-conf 02_68 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPHDLY_CFG[9] origin:064-gtp-channel-conf 03_68 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPHDLY_CFG[10] origin:064-gtp-channel-conf 02_69 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPHDLY_CFG[11] origin:064-gtp-channel-conf 03_69 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPHDLY_CFG[12] origin:064-gtp-channel-conf 02_70 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPHDLY_CFG[13] origin:064-gtp-channel-conf 03_70 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPHDLY_CFG[14] origin:064-gtp-channel-conf 02_71 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPHDLY_CFG[15] origin:064-gtp-channel-conf 03_71 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPHDLY_CFG[16] origin:064-gtp-channel-conf 02_72 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPHDLY_CFG[17] origin:064-gtp-channel-conf 03_72 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPHDLY_CFG[18] origin:064-gtp-channel-conf 02_73 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPHDLY_CFG[19] origin:064-gtp-channel-conf 03_73 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPHDLY_CFG[20] origin:064-gtp-channel-conf 02_74 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPHDLY_CFG[21] origin:064-gtp-channel-conf 03_74 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPHDLY_CFG[22] origin:064-gtp-channel-conf 02_75 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPHDLY_CFG[23] origin:064-gtp-channel-conf 03_75 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPI_GREY_SEL[0] origin:064-gtp-channel-conf 03_498 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPI_INVSTROBE_SEL[0] origin:064-gtp-channel-conf 02_498 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPI_PPM_CFG[0] origin:064-gtp-channel-conf 02_488 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPI_PPM_CFG[1] origin:064-gtp-channel-conf 03_488 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPI_PPM_CFG[2] origin:064-gtp-channel-conf 02_489 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPI_PPM_CFG[3] origin:064-gtp-channel-conf 03_489 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPI_PPM_CFG[4] origin:064-gtp-channel-conf 02_490 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPI_PPM_CFG[5] origin:064-gtp-channel-conf 03_490 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPI_PPM_CFG[6] origin:064-gtp-channel-conf 02_491 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPI_PPM_CFG[7] origin:064-gtp-channel-conf 03_491 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPI_PPMCLK_SEL.TXUSRCLK2 origin:064-gtp-channel-conf 03_497 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPI_SYNFREQ_PPM[0] origin:064-gtp-channel-conf 02_496 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPI_SYNFREQ_PPM[1] origin:064-gtp-channel-conf 03_496 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPI_SYNFREQ_PPM[2] origin:064-gtp-channel-conf 02_497 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPI_CFG0[0] origin:064-gtp-channel-conf 02_40 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPI_CFG0[1] origin:064-gtp-channel-conf 03_40 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPI_CFG1[0] origin:064-gtp-channel-conf 02_41 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPI_CFG1[1] origin:064-gtp-channel-conf 03_41 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPI_CFG2[0] origin:064-gtp-channel-conf 02_42 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPI_CFG2[1] origin:064-gtp-channel-conf 03_42 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPI_CFG3[0] origin:064-gtp-channel-conf 02_43 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPI_CFG4[0] origin:064-gtp-channel-conf 03_43 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPI_CFG5[0] origin:064-gtp-channel-conf 02_44 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPI_CFG5[1] origin:064-gtp-channel-conf 03_44 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPI_CFG5[2] origin:064-gtp-channel-conf 02_45 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPMARESET_TIME[0] origin:064-gtp-channel-conf 00_128 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPMARESET_TIME[1] origin:064-gtp-channel-conf 01_128 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPMARESET_TIME[2] origin:064-gtp-channel-conf 00_129 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPMARESET_TIME[3] origin:064-gtp-channel-conf 01_129 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXPMARESET_TIME[4] origin:064-gtp-channel-conf 00_130 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXSYNC_MULTILANE[0] origin:064-gtp-channel-conf 01_133 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXSYNC_OVRD[0] origin:064-gtp-channel-conf 00_135 -GTP_CHANNEL_3_MID_LEFT.GTPE2.TXSYNC_SKIP_DA[0] origin:064-gtp-channel-conf 00_134 -GTP_CHANNEL_3_MID_LEFT.GTPE2.UCODEER_CLR[0] origin:064-gtp-channel-conf 01_00 -GTP_CHANNEL_3_MID_LEFT.GTPE2.USE_PCS_CLK_PHASE_SEL[0] origin:064-gtp-channel-conf 02_463 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ZINV_DMONITORCLK origin:064-gtp-channel-conf 02_13 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ZINV_DRPCLK origin:064-gtp-channel-conf 02_00 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ZINV_RXUSRCLK origin:064-gtp-channel-conf 03_01 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ZINV_SIGVALIDCLK origin:064-gtp-channel-conf 03_13 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ZINV_TXPHDLYTSTCLK origin:064-gtp-channel-conf 02_03 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ZINV_TXUSRCLK origin:064-gtp-channel-conf 03_04 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ZINV_CLKRSVD0 origin:064-gtp-channel-conf 02_23 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ZINV_CLKRSVD1 origin:064-gtp-channel-conf 03_23 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ZINV_RXUSRCLK2 origin:064-gtp-channel-conf 02_02 -GTP_CHANNEL_3_MID_LEFT.GTPE2.ZINV_TXUSRCLK2 origin:064-gtp-channel-conf 02_05 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ACJTAG_DEBUG_MODE[0] origin:064-gtp-channel-conf 00_07 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ACJTAG_MODE[0] origin:064-gtp-channel-conf 01_06 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ACJTAG_RESET[0] origin:064-gtp-channel-conf 01_07 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[0] origin:064-gtp-channel-conf 02_464 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[1] origin:064-gtp-channel-conf 03_464 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[2] origin:064-gtp-channel-conf 02_465 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[3] origin:064-gtp-channel-conf 03_465 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[4] origin:064-gtp-channel-conf 02_466 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[5] origin:064-gtp-channel-conf 03_466 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[6] origin:064-gtp-channel-conf 02_467 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[7] origin:064-gtp-channel-conf 03_467 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[8] origin:064-gtp-channel-conf 02_468 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[9] origin:064-gtp-channel-conf 03_468 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[10] origin:064-gtp-channel-conf 02_469 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[11] origin:064-gtp-channel-conf 03_469 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[12] origin:064-gtp-channel-conf 02_470 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[13] origin:064-gtp-channel-conf 03_470 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[14] origin:064-gtp-channel-conf 02_471 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[15] origin:064-gtp-channel-conf 03_471 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[16] origin:064-gtp-channel-conf 02_472 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[17] origin:064-gtp-channel-conf 03_472 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[18] origin:064-gtp-channel-conf 02_473 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ADAPT_CFG0[19] origin:064-gtp-channel-conf 03_473 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ALIGN_COMMA_DOUBLE origin:064-gtp-channel-conf 00_522 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[0] origin:064-gtp-channel-conf 00_496 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[1] origin:064-gtp-channel-conf 01_496 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[2] origin:064-gtp-channel-conf 00_497 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[3] origin:064-gtp-channel-conf 01_497 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[4] origin:064-gtp-channel-conf 00_498 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[5] origin:064-gtp-channel-conf 01_498 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[6] origin:064-gtp-channel-conf 00_499 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[7] origin:064-gtp-channel-conf 01_499 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[8] origin:064-gtp-channel-conf 00_500 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[9] origin:064-gtp-channel-conf 01_500 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ALIGN_COMMA_WORD[0] origin:064-gtp-channel-conf 01_526 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ALIGN_COMMA_WORD[1] origin:064-gtp-channel-conf 00_527 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ALIGN_MCOMMA_DET origin:064-gtp-channel-conf 00_523 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[0] origin:064-gtp-channel-conf 00_504 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[1] origin:064-gtp-channel-conf 01_504 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[2] origin:064-gtp-channel-conf 00_505 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[3] origin:064-gtp-channel-conf 01_505 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[4] origin:064-gtp-channel-conf 00_506 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[5] origin:064-gtp-channel-conf 01_506 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[6] origin:064-gtp-channel-conf 00_507 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[7] origin:064-gtp-channel-conf 01_507 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[8] origin:064-gtp-channel-conf 00_508 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[9] origin:064-gtp-channel-conf 01_508 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ALIGN_PCOMMA_DET origin:064-gtp-channel-conf 01_523 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[0] origin:064-gtp-channel-conf 00_512 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[1] origin:064-gtp-channel-conf 01_512 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[2] origin:064-gtp-channel-conf 00_513 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[3] origin:064-gtp-channel-conf 01_513 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[4] origin:064-gtp-channel-conf 00_514 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[5] origin:064-gtp-channel-conf 01_514 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[6] origin:064-gtp-channel-conf 00_515 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[7] origin:064-gtp-channel-conf 01_515 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[8] origin:064-gtp-channel-conf 00_516 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[9] origin:064-gtp-channel-conf 01_516 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CBCC_DATA_SOURCE_SEL.DECODED origin:064-gtp-channel-conf 01_661 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[0] origin:064-gtp-channel-conf 02_392 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[1] origin:064-gtp-channel-conf 03_392 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[2] origin:064-gtp-channel-conf 02_393 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[3] origin:064-gtp-channel-conf 03_393 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[4] origin:064-gtp-channel-conf 02_394 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[5] origin:064-gtp-channel-conf 03_394 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[6] origin:064-gtp-channel-conf 02_395 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[7] origin:064-gtp-channel-conf 03_395 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[8] origin:064-gtp-channel-conf 02_396 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[9] origin:064-gtp-channel-conf 03_396 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[10] origin:064-gtp-channel-conf 02_397 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[11] origin:064-gtp-channel-conf 03_397 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[12] origin:064-gtp-channel-conf 02_398 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[13] origin:064-gtp-channel-conf 03_398 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[14] origin:064-gtp-channel-conf 02_399 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[15] origin:064-gtp-channel-conf 03_399 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[16] origin:064-gtp-channel-conf 02_400 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[17] origin:064-gtp-channel-conf 03_400 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[18] origin:064-gtp-channel-conf 02_401 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[19] origin:064-gtp-channel-conf 03_401 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[20] origin:064-gtp-channel-conf 02_402 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[21] origin:064-gtp-channel-conf 03_402 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[22] origin:064-gtp-channel-conf 02_403 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[23] origin:064-gtp-channel-conf 03_403 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[24] origin:064-gtp-channel-conf 02_404 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[25] origin:064-gtp-channel-conf 03_404 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[26] origin:064-gtp-channel-conf 02_405 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[27] origin:064-gtp-channel-conf 03_405 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[28] origin:064-gtp-channel-conf 02_406 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[29] origin:064-gtp-channel-conf 03_406 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[30] origin:064-gtp-channel-conf 02_407 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[31] origin:064-gtp-channel-conf 03_407 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[32] origin:064-gtp-channel-conf 02_408 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[33] origin:064-gtp-channel-conf 03_408 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[34] origin:064-gtp-channel-conf 02_409 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[35] origin:064-gtp-channel-conf 03_409 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[36] origin:064-gtp-channel-conf 02_410 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[37] origin:064-gtp-channel-conf 03_410 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[38] origin:064-gtp-channel-conf 02_411 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[39] origin:064-gtp-channel-conf 03_411 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[40] origin:064-gtp-channel-conf 02_412 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[41] origin:064-gtp-channel-conf 03_412 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG[42] origin:064-gtp-channel-conf 02_413 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG2[0] origin:064-gtp-channel-conf 02_459 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG2[1] origin:064-gtp-channel-conf 03_459 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG2[2] origin:064-gtp-channel-conf 02_460 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG2[3] origin:064-gtp-channel-conf 03_460 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG2[4] origin:064-gtp-channel-conf 02_461 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG2[5] origin:064-gtp-channel-conf 03_461 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG2[6] origin:064-gtp-channel-conf 02_462 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG3[0] origin:064-gtp-channel-conf 02_416 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG3[1] origin:064-gtp-channel-conf 03_416 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG3[2] origin:064-gtp-channel-conf 02_417 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG3[3] origin:064-gtp-channel-conf 03_417 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG3[4] origin:064-gtp-channel-conf 02_418 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG3[5] origin:064-gtp-channel-conf 03_418 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG3[6] origin:064-gtp-channel-conf 02_419 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG4[0] origin:064-gtp-channel-conf 03_438 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG5[0] origin:064-gtp-channel-conf 02_429 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG5[1] origin:064-gtp-channel-conf 03_429 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG6[0] origin:064-gtp-channel-conf 03_436 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG6[1] origin:064-gtp-channel-conf 02_437 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG6[2] origin:064-gtp-channel-conf 03_437 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CFOK_CFG6[3] origin:064-gtp-channel-conf 02_438 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_KEEP_ALIGN origin:064-gtp-channel-conf 01_631 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_MAX_SKEW[0] origin:064-gtp-channel-conf 00_670 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_MAX_SKEW[1] origin:064-gtp-channel-conf 01_670 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_MAX_SKEW[2] origin:064-gtp-channel-conf 00_671 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_MAX_SKEW[3] origin:064-gtp-channel-conf 01_671 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[0] origin:064-gtp-channel-conf 00_608 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[1] origin:064-gtp-channel-conf 01_608 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[2] origin:064-gtp-channel-conf 00_609 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[3] origin:064-gtp-channel-conf 01_609 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[4] origin:064-gtp-channel-conf 00_610 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[5] origin:064-gtp-channel-conf 01_610 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[6] origin:064-gtp-channel-conf 00_611 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[7] origin:064-gtp-channel-conf 01_611 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[8] origin:064-gtp-channel-conf 00_612 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[9] origin:064-gtp-channel-conf 01_612 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[0] origin:064-gtp-channel-conf 00_616 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[1] origin:064-gtp-channel-conf 01_616 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[2] origin:064-gtp-channel-conf 00_617 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[3] origin:064-gtp-channel-conf 01_617 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[4] origin:064-gtp-channel-conf 00_618 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[5] origin:064-gtp-channel-conf 01_618 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[6] origin:064-gtp-channel-conf 00_619 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[7] origin:064-gtp-channel-conf 01_619 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[8] origin:064-gtp-channel-conf 00_620 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[9] origin:064-gtp-channel-conf 01_620 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[0] origin:064-gtp-channel-conf 00_624 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[1] origin:064-gtp-channel-conf 01_624 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[2] origin:064-gtp-channel-conf 00_625 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[3] origin:064-gtp-channel-conf 01_625 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[4] origin:064-gtp-channel-conf 00_626 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[5] origin:064-gtp-channel-conf 01_626 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[6] origin:064-gtp-channel-conf 00_627 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[7] origin:064-gtp-channel-conf 01_627 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[8] origin:064-gtp-channel-conf 00_628 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[9] origin:064-gtp-channel-conf 01_628 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[0] origin:064-gtp-channel-conf 00_632 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[1] origin:064-gtp-channel-conf 01_632 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[2] origin:064-gtp-channel-conf 00_633 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[3] origin:064-gtp-channel-conf 01_633 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[4] origin:064-gtp-channel-conf 00_634 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[5] origin:064-gtp-channel-conf 01_634 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[6] origin:064-gtp-channel-conf 00_635 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[7] origin:064-gtp-channel-conf 01_635 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[8] origin:064-gtp-channel-conf 00_636 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[9] origin:064-gtp-channel-conf 01_636 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_ENABLE[0] origin:064-gtp-channel-conf 00_614 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_ENABLE[1] origin:064-gtp-channel-conf 01_614 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_ENABLE[2] origin:064-gtp-channel-conf 00_615 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_ENABLE[3] origin:064-gtp-channel-conf 01_615 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[0] origin:064-gtp-channel-conf 00_640 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[1] origin:064-gtp-channel-conf 01_640 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[2] origin:064-gtp-channel-conf 00_641 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[3] origin:064-gtp-channel-conf 01_641 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[4] origin:064-gtp-channel-conf 00_642 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[5] origin:064-gtp-channel-conf 01_642 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[6] origin:064-gtp-channel-conf 00_643 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[7] origin:064-gtp-channel-conf 01_643 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[8] origin:064-gtp-channel-conf 00_644 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[9] origin:064-gtp-channel-conf 01_644 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[0] origin:064-gtp-channel-conf 00_648 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[1] origin:064-gtp-channel-conf 01_648 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[2] origin:064-gtp-channel-conf 00_649 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[3] origin:064-gtp-channel-conf 01_649 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[4] origin:064-gtp-channel-conf 00_650 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[5] origin:064-gtp-channel-conf 01_650 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[6] origin:064-gtp-channel-conf 00_651 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[7] origin:064-gtp-channel-conf 01_651 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[8] origin:064-gtp-channel-conf 00_652 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[9] origin:064-gtp-channel-conf 01_652 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[0] origin:064-gtp-channel-conf 00_656 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[1] origin:064-gtp-channel-conf 01_656 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[2] origin:064-gtp-channel-conf 00_657 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[3] origin:064-gtp-channel-conf 01_657 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[4] origin:064-gtp-channel-conf 00_658 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[5] origin:064-gtp-channel-conf 01_658 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[6] origin:064-gtp-channel-conf 00_659 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[7] origin:064-gtp-channel-conf 01_659 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[8] origin:064-gtp-channel-conf 00_660 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[9] origin:064-gtp-channel-conf 01_660 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[0] origin:064-gtp-channel-conf 00_664 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[1] origin:064-gtp-channel-conf 01_664 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[2] origin:064-gtp-channel-conf 00_665 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[3] origin:064-gtp-channel-conf 01_665 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[4] origin:064-gtp-channel-conf 00_666 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[5] origin:064-gtp-channel-conf 01_666 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[6] origin:064-gtp-channel-conf 00_667 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[7] origin:064-gtp-channel-conf 01_667 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[8] origin:064-gtp-channel-conf 00_668 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[9] origin:064-gtp-channel-conf 01_668 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_ENABLE[0] origin:064-gtp-channel-conf 00_646 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_ENABLE[1] origin:064-gtp-channel-conf 01_646 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_ENABLE[2] origin:064-gtp-channel-conf 00_647 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_ENABLE[3] origin:064-gtp-channel-conf 01_647 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_USE origin:064-gtp-channel-conf 01_645 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_LEN[0] origin:064-gtp-channel-conf 00_623 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CHAN_BOND_SEQ_LEN[1] origin:064-gtp-channel-conf 01_623 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COMMON_SWING[0] origin:064-gtp-channel-conf 03_311 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_KEEP_IDLE origin:064-gtp-channel-conf 00_591 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_MAX_LAT[0] origin:064-gtp-channel-conf 00_557 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_MAX_LAT[1] origin:064-gtp-channel-conf 01_557 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_MAX_LAT[2] origin:064-gtp-channel-conf 00_558 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_MAX_LAT[3] origin:064-gtp-channel-conf 01_558 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_MAX_LAT[4] origin:064-gtp-channel-conf 00_559 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_MAX_LAT[5] origin:064-gtp-channel-conf 01_559 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_MIN_LAT[0] origin:064-gtp-channel-conf 00_565 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_MIN_LAT[1] origin:064-gtp-channel-conf 01_565 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_MIN_LAT[2] origin:064-gtp-channel-conf 00_566 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_MIN_LAT[3] origin:064-gtp-channel-conf 01_566 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_MIN_LAT[4] origin:064-gtp-channel-conf 00_567 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_MIN_LAT[5] origin:064-gtp-channel-conf 01_567 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_PRECEDENCE origin:064-gtp-channel-conf 00_590 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_REPEAT_WAIT[0] origin:064-gtp-channel-conf 00_573 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_REPEAT_WAIT[1] origin:064-gtp-channel-conf 01_573 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_REPEAT_WAIT[2] origin:064-gtp-channel-conf 00_574 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_REPEAT_WAIT[3] origin:064-gtp-channel-conf 01_574 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_REPEAT_WAIT[4] origin:064-gtp-channel-conf 00_575 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[0] origin:064-gtp-channel-conf 00_544 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[1] origin:064-gtp-channel-conf 01_544 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[2] origin:064-gtp-channel-conf 00_545 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[3] origin:064-gtp-channel-conf 01_545 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[4] origin:064-gtp-channel-conf 00_546 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[5] origin:064-gtp-channel-conf 01_546 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[6] origin:064-gtp-channel-conf 00_547 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[7] origin:064-gtp-channel-conf 01_547 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[8] origin:064-gtp-channel-conf 00_548 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[9] origin:064-gtp-channel-conf 01_548 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[0] origin:064-gtp-channel-conf 00_552 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[1] origin:064-gtp-channel-conf 01_552 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[2] origin:064-gtp-channel-conf 00_553 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[3] origin:064-gtp-channel-conf 01_553 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[4] origin:064-gtp-channel-conf 00_554 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[5] origin:064-gtp-channel-conf 01_554 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[6] origin:064-gtp-channel-conf 00_555 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[7] origin:064-gtp-channel-conf 01_555 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[8] origin:064-gtp-channel-conf 00_556 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[9] origin:064-gtp-channel-conf 01_556 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[0] origin:064-gtp-channel-conf 00_560 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[1] origin:064-gtp-channel-conf 01_560 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[2] origin:064-gtp-channel-conf 00_561 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[3] origin:064-gtp-channel-conf 01_561 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[4] origin:064-gtp-channel-conf 00_562 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[5] origin:064-gtp-channel-conf 01_562 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[6] origin:064-gtp-channel-conf 00_563 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[7] origin:064-gtp-channel-conf 01_563 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[8] origin:064-gtp-channel-conf 00_564 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[9] origin:064-gtp-channel-conf 01_564 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[0] origin:064-gtp-channel-conf 00_568 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[1] origin:064-gtp-channel-conf 01_568 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[2] origin:064-gtp-channel-conf 00_569 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[3] origin:064-gtp-channel-conf 01_569 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[4] origin:064-gtp-channel-conf 00_570 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[5] origin:064-gtp-channel-conf 01_570 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[6] origin:064-gtp-channel-conf 00_571 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[7] origin:064-gtp-channel-conf 01_571 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[8] origin:064-gtp-channel-conf 00_572 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[9] origin:064-gtp-channel-conf 01_572 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_ENABLE[0] origin:064-gtp-channel-conf 00_549 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_ENABLE[1] origin:064-gtp-channel-conf 01_549 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_ENABLE[2] origin:064-gtp-channel-conf 00_550 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_1_ENABLE[3] origin:064-gtp-channel-conf 01_550 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[0] origin:064-gtp-channel-conf 00_576 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[1] origin:064-gtp-channel-conf 01_576 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[2] origin:064-gtp-channel-conf 00_577 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[3] origin:064-gtp-channel-conf 01_577 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[4] origin:064-gtp-channel-conf 00_578 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[5] origin:064-gtp-channel-conf 01_578 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[6] origin:064-gtp-channel-conf 00_579 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[7] origin:064-gtp-channel-conf 01_579 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[8] origin:064-gtp-channel-conf 00_580 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[9] origin:064-gtp-channel-conf 01_580 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[0] origin:064-gtp-channel-conf 00_584 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[1] origin:064-gtp-channel-conf 01_584 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[2] origin:064-gtp-channel-conf 00_585 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[3] origin:064-gtp-channel-conf 01_585 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[4] origin:064-gtp-channel-conf 00_586 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[5] origin:064-gtp-channel-conf 01_586 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[6] origin:064-gtp-channel-conf 00_587 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[7] origin:064-gtp-channel-conf 01_587 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[8] origin:064-gtp-channel-conf 00_588 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[9] origin:064-gtp-channel-conf 01_588 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[0] origin:064-gtp-channel-conf 00_592 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[1] origin:064-gtp-channel-conf 01_592 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[2] origin:064-gtp-channel-conf 00_593 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[3] origin:064-gtp-channel-conf 01_593 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[4] origin:064-gtp-channel-conf 00_594 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[5] origin:064-gtp-channel-conf 01_594 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[6] origin:064-gtp-channel-conf 00_595 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[7] origin:064-gtp-channel-conf 01_595 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[8] origin:064-gtp-channel-conf 00_596 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[9] origin:064-gtp-channel-conf 01_596 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[0] origin:064-gtp-channel-conf 00_600 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[1] origin:064-gtp-channel-conf 01_600 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[2] origin:064-gtp-channel-conf 00_601 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[3] origin:064-gtp-channel-conf 01_601 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[4] origin:064-gtp-channel-conf 00_602 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[5] origin:064-gtp-channel-conf 01_602 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[6] origin:064-gtp-channel-conf 00_603 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[7] origin:064-gtp-channel-conf 01_603 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[8] origin:064-gtp-channel-conf 00_604 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[9] origin:064-gtp-channel-conf 01_604 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_ENABLE[0] origin:064-gtp-channel-conf 00_581 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_ENABLE[1] origin:064-gtp-channel-conf 01_581 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_ENABLE[2] origin:064-gtp-channel-conf 00_582 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_ENABLE[3] origin:064-gtp-channel-conf 01_582 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_2_USE origin:064-gtp-channel-conf 00_583 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_LEN[0] origin:064-gtp-channel-conf 00_589 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_COR_SEQ_LEN[1] origin:064-gtp-channel-conf 01_589 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.CLK_CORRECT_USE origin:064-gtp-channel-conf 00_551 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.DEC_MCOMMA_DETECT origin:064-gtp-channel-conf 01_494 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.DEC_PCOMMA_DETECT origin:064-gtp-channel-conf 00_495 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.DEC_VALID_COMMA_ONLY origin:064-gtp-channel-conf 00_494 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[0] origin:064-gtp-channel-conf 02_368 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[1] origin:064-gtp-channel-conf 03_368 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[2] origin:064-gtp-channel-conf 02_369 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[3] origin:064-gtp-channel-conf 03_369 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[4] origin:064-gtp-channel-conf 02_370 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[5] origin:064-gtp-channel-conf 03_370 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[6] origin:064-gtp-channel-conf 02_371 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[7] origin:064-gtp-channel-conf 03_371 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[8] origin:064-gtp-channel-conf 02_372 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[9] origin:064-gtp-channel-conf 03_372 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[10] origin:064-gtp-channel-conf 02_373 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[11] origin:064-gtp-channel-conf 03_373 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[12] origin:064-gtp-channel-conf 02_374 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[13] origin:064-gtp-channel-conf 03_374 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[14] origin:064-gtp-channel-conf 02_375 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[15] origin:064-gtp-channel-conf 03_375 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[16] origin:064-gtp-channel-conf 02_376 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[17] origin:064-gtp-channel-conf 03_376 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[18] origin:064-gtp-channel-conf 02_377 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[19] origin:064-gtp-channel-conf 03_377 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[20] origin:064-gtp-channel-conf 02_378 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[21] origin:064-gtp-channel-conf 03_378 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[22] origin:064-gtp-channel-conf 02_379 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.DMONITOR_CFG[23] origin:064-gtp-channel-conf 03_379 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_CLK_PHASE_SEL[0] origin:064-gtp-channel-conf 03_463 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_CONTROL[0] origin:064-gtp-channel-conf 00_488 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_CONTROL[1] origin:064-gtp-channel-conf 01_488 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_CONTROL[2] origin:064-gtp-channel-conf 00_489 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_CONTROL[3] origin:064-gtp-channel-conf 01_489 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_CONTROL[4] origin:064-gtp-channel-conf 00_490 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_CONTROL[5] origin:064-gtp-channel-conf 01_490 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_ERRDET_EN origin:064-gtp-channel-conf 01_492 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_EYE_SCAN_EN origin:064-gtp-channel-conf 00_492 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_HORZ_OFFSET[0] origin:064-gtp-channel-conf 00_480 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_HORZ_OFFSET[1] origin:064-gtp-channel-conf 01_480 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_HORZ_OFFSET[2] origin:064-gtp-channel-conf 00_481 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_HORZ_OFFSET[3] origin:064-gtp-channel-conf 01_481 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_HORZ_OFFSET[4] origin:064-gtp-channel-conf 00_482 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_HORZ_OFFSET[5] origin:064-gtp-channel-conf 01_482 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_HORZ_OFFSET[6] origin:064-gtp-channel-conf 00_483 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_HORZ_OFFSET[7] origin:064-gtp-channel-conf 01_483 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_HORZ_OFFSET[8] origin:064-gtp-channel-conf 00_484 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_HORZ_OFFSET[9] origin:064-gtp-channel-conf 01_484 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_HORZ_OFFSET[10] origin:064-gtp-channel-conf 00_485 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_HORZ_OFFSET[11] origin:064-gtp-channel-conf 01_485 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_PMA_CFG[0] origin:064-gtp-channel-conf 02_624 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_PMA_CFG[1] origin:064-gtp-channel-conf 03_624 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_PMA_CFG[2] origin:064-gtp-channel-conf 02_625 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_PMA_CFG[3] origin:064-gtp-channel-conf 03_625 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_PMA_CFG[4] origin:064-gtp-channel-conf 02_626 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_PMA_CFG[5] origin:064-gtp-channel-conf 03_626 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_PMA_CFG[6] origin:064-gtp-channel-conf 02_627 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_PMA_CFG[7] origin:064-gtp-channel-conf 03_627 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_PMA_CFG[8] origin:064-gtp-channel-conf 02_628 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_PMA_CFG[9] origin:064-gtp-channel-conf 03_628 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_PRESCALE[0] origin:064-gtp-channel-conf 01_477 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_PRESCALE[1] origin:064-gtp-channel-conf 00_478 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_PRESCALE[2] origin:064-gtp-channel-conf 01_478 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_PRESCALE[3] origin:064-gtp-channel-conf 00_479 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_PRESCALE[4] origin:064-gtp-channel-conf 01_479 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[0] origin:064-gtp-channel-conf 00_392 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[1] origin:064-gtp-channel-conf 01_392 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[2] origin:064-gtp-channel-conf 00_393 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[3] origin:064-gtp-channel-conf 01_393 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[4] origin:064-gtp-channel-conf 00_394 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[5] origin:064-gtp-channel-conf 01_394 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[6] origin:064-gtp-channel-conf 00_395 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[7] origin:064-gtp-channel-conf 01_395 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[8] origin:064-gtp-channel-conf 00_396 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[9] origin:064-gtp-channel-conf 01_396 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[10] origin:064-gtp-channel-conf 00_397 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[11] origin:064-gtp-channel-conf 01_397 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[12] origin:064-gtp-channel-conf 00_398 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[13] origin:064-gtp-channel-conf 01_398 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[14] origin:064-gtp-channel-conf 00_399 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[15] origin:064-gtp-channel-conf 01_399 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[16] origin:064-gtp-channel-conf 00_400 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[17] origin:064-gtp-channel-conf 01_400 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[18] origin:064-gtp-channel-conf 00_401 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[19] origin:064-gtp-channel-conf 01_401 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[20] origin:064-gtp-channel-conf 00_402 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[21] origin:064-gtp-channel-conf 01_402 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[22] origin:064-gtp-channel-conf 00_403 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[23] origin:064-gtp-channel-conf 01_403 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[24] origin:064-gtp-channel-conf 00_404 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[25] origin:064-gtp-channel-conf 01_404 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[26] origin:064-gtp-channel-conf 00_405 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[27] origin:064-gtp-channel-conf 01_405 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[28] origin:064-gtp-channel-conf 00_406 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[29] origin:064-gtp-channel-conf 01_406 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[30] origin:064-gtp-channel-conf 00_407 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[31] origin:064-gtp-channel-conf 01_407 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[32] origin:064-gtp-channel-conf 00_408 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[33] origin:064-gtp-channel-conf 01_408 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[34] origin:064-gtp-channel-conf 00_409 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[35] origin:064-gtp-channel-conf 01_409 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[36] origin:064-gtp-channel-conf 00_410 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[37] origin:064-gtp-channel-conf 01_410 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[38] origin:064-gtp-channel-conf 00_411 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[39] origin:064-gtp-channel-conf 01_411 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[40] origin:064-gtp-channel-conf 00_412 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[41] origin:064-gtp-channel-conf 01_412 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[42] origin:064-gtp-channel-conf 00_413 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[43] origin:064-gtp-channel-conf 01_413 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[44] origin:064-gtp-channel-conf 00_414 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[45] origin:064-gtp-channel-conf 01_414 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[46] origin:064-gtp-channel-conf 00_415 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[47] origin:064-gtp-channel-conf 01_415 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[48] origin:064-gtp-channel-conf 00_416 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[49] origin:064-gtp-channel-conf 01_416 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[50] origin:064-gtp-channel-conf 00_417 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[51] origin:064-gtp-channel-conf 01_417 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[52] origin:064-gtp-channel-conf 00_418 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[53] origin:064-gtp-channel-conf 01_418 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[54] origin:064-gtp-channel-conf 00_419 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[55] origin:064-gtp-channel-conf 01_419 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[56] origin:064-gtp-channel-conf 00_420 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[57] origin:064-gtp-channel-conf 01_420 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[58] origin:064-gtp-channel-conf 00_421 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[59] origin:064-gtp-channel-conf 01_421 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[60] origin:064-gtp-channel-conf 00_422 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[61] origin:064-gtp-channel-conf 01_422 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[62] origin:064-gtp-channel-conf 00_423 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[63] origin:064-gtp-channel-conf 01_423 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[64] origin:064-gtp-channel-conf 00_424 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[65] origin:064-gtp-channel-conf 01_424 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[66] origin:064-gtp-channel-conf 00_425 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[67] origin:064-gtp-channel-conf 01_425 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[68] origin:064-gtp-channel-conf 00_426 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[69] origin:064-gtp-channel-conf 01_426 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[70] origin:064-gtp-channel-conf 00_427 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[71] origin:064-gtp-channel-conf 01_427 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[72] origin:064-gtp-channel-conf 00_428 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[73] origin:064-gtp-channel-conf 01_428 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[74] origin:064-gtp-channel-conf 00_429 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[75] origin:064-gtp-channel-conf 01_429 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[76] origin:064-gtp-channel-conf 00_430 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[77] origin:064-gtp-channel-conf 01_430 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[78] origin:064-gtp-channel-conf 00_431 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUAL_MASK[79] origin:064-gtp-channel-conf 01_431 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[0] origin:064-gtp-channel-conf 00_352 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[1] origin:064-gtp-channel-conf 01_352 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[2] origin:064-gtp-channel-conf 00_353 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[3] origin:064-gtp-channel-conf 01_353 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[4] origin:064-gtp-channel-conf 00_354 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[5] origin:064-gtp-channel-conf 01_354 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[6] origin:064-gtp-channel-conf 00_355 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[7] origin:064-gtp-channel-conf 01_355 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[8] origin:064-gtp-channel-conf 00_356 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[9] origin:064-gtp-channel-conf 01_356 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[10] origin:064-gtp-channel-conf 00_357 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[11] origin:064-gtp-channel-conf 01_357 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[12] origin:064-gtp-channel-conf 00_358 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[13] origin:064-gtp-channel-conf 01_358 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[14] origin:064-gtp-channel-conf 00_359 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[15] origin:064-gtp-channel-conf 01_359 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[16] origin:064-gtp-channel-conf 00_360 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[17] origin:064-gtp-channel-conf 01_360 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[18] origin:064-gtp-channel-conf 00_361 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[19] origin:064-gtp-channel-conf 01_361 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[20] origin:064-gtp-channel-conf 00_362 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[21] origin:064-gtp-channel-conf 01_362 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[22] origin:064-gtp-channel-conf 00_363 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[23] origin:064-gtp-channel-conf 01_363 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[24] origin:064-gtp-channel-conf 00_364 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[25] origin:064-gtp-channel-conf 01_364 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[26] origin:064-gtp-channel-conf 00_365 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[27] origin:064-gtp-channel-conf 01_365 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[28] origin:064-gtp-channel-conf 00_366 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[29] origin:064-gtp-channel-conf 01_366 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[30] origin:064-gtp-channel-conf 00_367 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[31] origin:064-gtp-channel-conf 01_367 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[32] origin:064-gtp-channel-conf 00_368 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[33] origin:064-gtp-channel-conf 01_368 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[34] origin:064-gtp-channel-conf 00_369 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[35] origin:064-gtp-channel-conf 01_369 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[36] origin:064-gtp-channel-conf 00_370 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[37] origin:064-gtp-channel-conf 01_370 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[38] origin:064-gtp-channel-conf 00_371 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[39] origin:064-gtp-channel-conf 01_371 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[40] origin:064-gtp-channel-conf 00_372 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[41] origin:064-gtp-channel-conf 01_372 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[42] origin:064-gtp-channel-conf 00_373 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[43] origin:064-gtp-channel-conf 01_373 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[44] origin:064-gtp-channel-conf 00_374 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[45] origin:064-gtp-channel-conf 01_374 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[46] origin:064-gtp-channel-conf 00_375 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[47] origin:064-gtp-channel-conf 01_375 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[48] origin:064-gtp-channel-conf 00_376 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[49] origin:064-gtp-channel-conf 01_376 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[50] origin:064-gtp-channel-conf 00_377 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[51] origin:064-gtp-channel-conf 01_377 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[52] origin:064-gtp-channel-conf 00_378 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[53] origin:064-gtp-channel-conf 01_378 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[54] origin:064-gtp-channel-conf 00_379 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[55] origin:064-gtp-channel-conf 01_379 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[56] origin:064-gtp-channel-conf 00_380 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[57] origin:064-gtp-channel-conf 01_380 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[58] origin:064-gtp-channel-conf 00_381 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[59] origin:064-gtp-channel-conf 01_381 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[60] origin:064-gtp-channel-conf 00_382 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[61] origin:064-gtp-channel-conf 01_382 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[62] origin:064-gtp-channel-conf 00_383 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[63] origin:064-gtp-channel-conf 01_383 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[64] origin:064-gtp-channel-conf 00_384 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[65] origin:064-gtp-channel-conf 01_384 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[66] origin:064-gtp-channel-conf 00_385 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[67] origin:064-gtp-channel-conf 01_385 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[68] origin:064-gtp-channel-conf 00_386 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[69] origin:064-gtp-channel-conf 01_386 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[70] origin:064-gtp-channel-conf 00_387 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[71] origin:064-gtp-channel-conf 01_387 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[72] origin:064-gtp-channel-conf 00_388 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[73] origin:064-gtp-channel-conf 01_388 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[74] origin:064-gtp-channel-conf 00_389 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[75] origin:064-gtp-channel-conf 01_389 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[76] origin:064-gtp-channel-conf 00_390 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[77] origin:064-gtp-channel-conf 01_390 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[78] origin:064-gtp-channel-conf 00_391 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_QUALIFIER[79] origin:064-gtp-channel-conf 01_391 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[0] origin:064-gtp-channel-conf 00_432 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[1] origin:064-gtp-channel-conf 01_432 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[2] origin:064-gtp-channel-conf 00_433 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[3] origin:064-gtp-channel-conf 01_433 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[4] origin:064-gtp-channel-conf 00_434 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[5] origin:064-gtp-channel-conf 01_434 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[6] origin:064-gtp-channel-conf 00_435 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[7] origin:064-gtp-channel-conf 01_435 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[8] origin:064-gtp-channel-conf 00_436 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[9] origin:064-gtp-channel-conf 01_436 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[10] origin:064-gtp-channel-conf 00_437 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[11] origin:064-gtp-channel-conf 01_437 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[12] origin:064-gtp-channel-conf 00_438 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[13] origin:064-gtp-channel-conf 01_438 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[14] origin:064-gtp-channel-conf 00_439 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[15] origin:064-gtp-channel-conf 01_439 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[16] origin:064-gtp-channel-conf 00_440 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[17] origin:064-gtp-channel-conf 01_440 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[18] origin:064-gtp-channel-conf 00_441 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[19] origin:064-gtp-channel-conf 01_441 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[20] origin:064-gtp-channel-conf 00_442 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[21] origin:064-gtp-channel-conf 01_442 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[22] origin:064-gtp-channel-conf 00_443 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[23] origin:064-gtp-channel-conf 01_443 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[24] origin:064-gtp-channel-conf 00_444 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[25] origin:064-gtp-channel-conf 01_444 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[26] origin:064-gtp-channel-conf 00_445 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[27] origin:064-gtp-channel-conf 01_445 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[28] origin:064-gtp-channel-conf 00_446 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[29] origin:064-gtp-channel-conf 01_446 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[30] origin:064-gtp-channel-conf 00_447 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[31] origin:064-gtp-channel-conf 01_447 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[32] origin:064-gtp-channel-conf 00_448 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[33] origin:064-gtp-channel-conf 01_448 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[34] origin:064-gtp-channel-conf 00_449 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[35] origin:064-gtp-channel-conf 01_449 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[36] origin:064-gtp-channel-conf 00_450 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[37] origin:064-gtp-channel-conf 01_450 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[38] origin:064-gtp-channel-conf 00_451 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[39] origin:064-gtp-channel-conf 01_451 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[40] origin:064-gtp-channel-conf 00_452 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[41] origin:064-gtp-channel-conf 01_452 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[42] origin:064-gtp-channel-conf 00_453 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[43] origin:064-gtp-channel-conf 01_453 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[44] origin:064-gtp-channel-conf 00_454 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[45] origin:064-gtp-channel-conf 01_454 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[46] origin:064-gtp-channel-conf 00_455 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[47] origin:064-gtp-channel-conf 01_455 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[48] origin:064-gtp-channel-conf 00_456 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[49] origin:064-gtp-channel-conf 01_456 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[50] origin:064-gtp-channel-conf 00_457 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[51] origin:064-gtp-channel-conf 01_457 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[52] origin:064-gtp-channel-conf 00_458 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[53] origin:064-gtp-channel-conf 01_458 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[54] origin:064-gtp-channel-conf 00_459 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[55] origin:064-gtp-channel-conf 01_459 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[56] origin:064-gtp-channel-conf 00_460 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[57] origin:064-gtp-channel-conf 01_460 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[58] origin:064-gtp-channel-conf 00_461 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[59] origin:064-gtp-channel-conf 01_461 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[60] origin:064-gtp-channel-conf 00_462 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[61] origin:064-gtp-channel-conf 01_462 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[62] origin:064-gtp-channel-conf 00_463 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[63] origin:064-gtp-channel-conf 01_463 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[64] origin:064-gtp-channel-conf 00_464 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[65] origin:064-gtp-channel-conf 01_464 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[66] origin:064-gtp-channel-conf 00_465 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[67] origin:064-gtp-channel-conf 01_465 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[68] origin:064-gtp-channel-conf 00_466 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[69] origin:064-gtp-channel-conf 01_466 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[70] origin:064-gtp-channel-conf 00_467 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[71] origin:064-gtp-channel-conf 01_467 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[72] origin:064-gtp-channel-conf 00_468 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[73] origin:064-gtp-channel-conf 01_468 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[74] origin:064-gtp-channel-conf 00_469 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[75] origin:064-gtp-channel-conf 01_469 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[76] origin:064-gtp-channel-conf 00_470 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[77] origin:064-gtp-channel-conf 01_470 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[78] origin:064-gtp-channel-conf 00_471 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_SDATA_MASK[79] origin:064-gtp-channel-conf 01_471 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_VERT_OFFSET[0] origin:064-gtp-channel-conf 00_472 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_VERT_OFFSET[1] origin:064-gtp-channel-conf 01_472 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_VERT_OFFSET[2] origin:064-gtp-channel-conf 00_473 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_VERT_OFFSET[3] origin:064-gtp-channel-conf 01_473 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_VERT_OFFSET[4] origin:064-gtp-channel-conf 00_474 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_VERT_OFFSET[5] origin:064-gtp-channel-conf 01_474 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_VERT_OFFSET[6] origin:064-gtp-channel-conf 00_475 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_VERT_OFFSET[7] origin:064-gtp-channel-conf 01_475 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.ES_VERT_OFFSET[8] origin:064-gtp-channel-conf 00_476 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.FTS_DESKEW_SEQ_ENABLE[0] origin:064-gtp-channel-conf 00_662 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.FTS_DESKEW_SEQ_ENABLE[1] origin:064-gtp-channel-conf 01_662 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.FTS_DESKEW_SEQ_ENABLE[2] origin:064-gtp-channel-conf 00_663 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.FTS_DESKEW_SEQ_ENABLE[3] origin:064-gtp-channel-conf 01_663 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.FTS_LANE_DESKEW_CFG[0] origin:064-gtp-channel-conf 00_654 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.FTS_LANE_DESKEW_CFG[1] origin:064-gtp-channel-conf 01_654 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.FTS_LANE_DESKEW_CFG[2] origin:064-gtp-channel-conf 00_655 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.FTS_LANE_DESKEW_CFG[3] origin:064-gtp-channel-conf 01_655 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.FTS_LANE_DESKEW_EN origin:064-gtp-channel-conf 01_653 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.GEARBOX_MODE[0] origin:064-gtp-channel-conf 00_224 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.GEARBOX_MODE[1] origin:064-gtp-channel-conf 01_224 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.GEARBOX_MODE[2] origin:064-gtp-channel-conf 00_225 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.IN_USE origin:064-gtp-channel-conf 00_00 00_01 00_47 00_52 00_53 00_65 01_01 01_47 02_129 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.INV_DMONITORCLK origin:064-gtp-channel-conf 02_13 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.INV_DRPCLK origin:064-gtp-channel-conf 02_00 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.INV_RXUSRCLK origin:064-gtp-channel-conf 03_01 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.INV_SIGVALIDCLK origin:064-gtp-channel-conf 03_13 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.INV_TXPHDLYTSTCLK origin:064-gtp-channel-conf 02_03 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.INV_TXUSRCLK origin:064-gtp-channel-conf 03_04 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.INV_CLKRSVD0 origin:064-gtp-channel-conf 02_23 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.INV_CLKRSVD1 origin:064-gtp-channel-conf 03_23 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.INV_RXUSRCLK2 origin:064-gtp-channel-conf 02_02 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.INV_TXUSRCLK2 origin:064-gtp-channel-conf 02_05 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.LOOPBACK_CFG[0] origin:064-gtp-channel-conf 02_20 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.OUTREFCLK_SEL_INV[0] origin:064-gtp-channel-conf 00_149 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.OUTREFCLK_SEL_INV[1] origin:064-gtp-channel-conf 01_149 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PCS_PCIE_EN origin:064-gtp-channel-conf 00_216 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[0] origin:064-gtp-channel-conf 02_184 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[1] origin:064-gtp-channel-conf 03_184 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[2] origin:064-gtp-channel-conf 02_185 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[3] origin:064-gtp-channel-conf 03_185 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[4] origin:064-gtp-channel-conf 02_186 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[5] origin:064-gtp-channel-conf 03_186 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[6] origin:064-gtp-channel-conf 02_187 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[7] origin:064-gtp-channel-conf 03_187 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[8] origin:064-gtp-channel-conf 02_188 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[9] origin:064-gtp-channel-conf 03_188 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[10] origin:064-gtp-channel-conf 02_189 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[11] origin:064-gtp-channel-conf 03_189 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[12] origin:064-gtp-channel-conf 02_190 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[13] origin:064-gtp-channel-conf 03_190 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[14] origin:064-gtp-channel-conf 02_191 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[15] origin:064-gtp-channel-conf 03_191 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[16] origin:064-gtp-channel-conf 02_192 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[17] origin:064-gtp-channel-conf 03_192 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[18] origin:064-gtp-channel-conf 02_193 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[19] origin:064-gtp-channel-conf 03_193 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[20] origin:064-gtp-channel-conf 02_194 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[21] origin:064-gtp-channel-conf 03_194 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[22] origin:064-gtp-channel-conf 02_195 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[23] origin:064-gtp-channel-conf 03_195 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[24] origin:064-gtp-channel-conf 02_196 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[25] origin:064-gtp-channel-conf 03_196 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[26] origin:064-gtp-channel-conf 02_197 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[27] origin:064-gtp-channel-conf 03_197 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[28] origin:064-gtp-channel-conf 02_198 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[29] origin:064-gtp-channel-conf 03_198 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[30] origin:064-gtp-channel-conf 02_199 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[31] origin:064-gtp-channel-conf 03_199 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[32] origin:064-gtp-channel-conf 02_200 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[33] origin:064-gtp-channel-conf 03_200 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[34] origin:064-gtp-channel-conf 02_201 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[35] origin:064-gtp-channel-conf 03_201 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[36] origin:064-gtp-channel-conf 02_202 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[37] origin:064-gtp-channel-conf 03_202 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[38] origin:064-gtp-channel-conf 02_203 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[39] origin:064-gtp-channel-conf 03_203 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[40] origin:064-gtp-channel-conf 02_204 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[41] origin:064-gtp-channel-conf 03_204 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[42] origin:064-gtp-channel-conf 02_205 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[43] origin:064-gtp-channel-conf 03_205 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[44] origin:064-gtp-channel-conf 02_206 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[45] origin:064-gtp-channel-conf 03_206 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[46] origin:064-gtp-channel-conf 02_207 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PCS_RSVD_ATTR[47] origin:064-gtp-channel-conf 03_207 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[0] origin:064-gtp-channel-conf 01_216 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[1] origin:064-gtp-channel-conf 00_217 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[2] origin:064-gtp-channel-conf 01_217 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[3] origin:064-gtp-channel-conf 00_218 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[4] origin:064-gtp-channel-conf 01_218 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[5] origin:064-gtp-channel-conf 00_219 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[6] origin:064-gtp-channel-conf 01_219 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[7] origin:064-gtp-channel-conf 00_220 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[8] origin:064-gtp-channel-conf 01_220 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[9] origin:064-gtp-channel-conf 00_221 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[10] origin:064-gtp-channel-conf 01_221 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[11] origin:064-gtp-channel-conf 00_222 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[0] origin:064-gtp-channel-conf 00_208 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[1] origin:064-gtp-channel-conf 01_208 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[2] origin:064-gtp-channel-conf 00_209 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[3] origin:064-gtp-channel-conf 01_209 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[4] origin:064-gtp-channel-conf 00_210 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[5] origin:064-gtp-channel-conf 01_210 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[6] origin:064-gtp-channel-conf 00_211 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[7] origin:064-gtp-channel-conf 01_211 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[0] origin:064-gtp-channel-conf 00_212 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[1] origin:064-gtp-channel-conf 01_212 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[2] origin:064-gtp-channel-conf 00_213 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[3] origin:064-gtp-channel-conf 01_213 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[4] origin:064-gtp-channel-conf 00_214 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[5] origin:064-gtp-channel-conf 01_214 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[6] origin:064-gtp-channel-conf 00_215 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[7] origin:064-gtp-channel-conf 01_215 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PMA_LOOPBACK_CFG[0] origin:064-gtp-channel-conf 01_207 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[0] origin:064-gtp-channel-conf 02_520 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[1] origin:064-gtp-channel-conf 03_520 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[2] origin:064-gtp-channel-conf 02_521 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[3] origin:064-gtp-channel-conf 03_521 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[4] origin:064-gtp-channel-conf 02_522 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[5] origin:064-gtp-channel-conf 03_522 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[6] origin:064-gtp-channel-conf 02_523 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[7] origin:064-gtp-channel-conf 03_523 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[8] origin:064-gtp-channel-conf 02_524 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[9] origin:064-gtp-channel-conf 03_524 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[10] origin:064-gtp-channel-conf 02_525 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[11] origin:064-gtp-channel-conf 03_525 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[12] origin:064-gtp-channel-conf 02_526 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[13] origin:064-gtp-channel-conf 03_526 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[14] origin:064-gtp-channel-conf 02_527 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[15] origin:064-gtp-channel-conf 03_527 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[16] origin:064-gtp-channel-conf 02_528 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[17] origin:064-gtp-channel-conf 03_528 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[18] origin:064-gtp-channel-conf 02_529 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[19] origin:064-gtp-channel-conf 03_529 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[20] origin:064-gtp-channel-conf 02_530 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[21] origin:064-gtp-channel-conf 03_530 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[22] origin:064-gtp-channel-conf 02_531 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[23] origin:064-gtp-channel-conf 03_531 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[24] origin:064-gtp-channel-conf 02_532 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[25] origin:064-gtp-channel-conf 03_532 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[26] origin:064-gtp-channel-conf 02_533 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[27] origin:064-gtp-channel-conf 03_533 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[28] origin:064-gtp-channel-conf 02_534 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[29] origin:064-gtp-channel-conf 03_534 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[30] origin:064-gtp-channel-conf 02_535 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PMA_RSV[31] origin:064-gtp-channel-conf 03_535 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[0] origin:064-gtp-channel-conf 02_336 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[1] origin:064-gtp-channel-conf 03_336 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[2] origin:064-gtp-channel-conf 02_337 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[3] origin:064-gtp-channel-conf 03_337 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[4] origin:064-gtp-channel-conf 02_338 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[5] origin:064-gtp-channel-conf 03_338 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[6] origin:064-gtp-channel-conf 02_339 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[7] origin:064-gtp-channel-conf 03_339 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[8] origin:064-gtp-channel-conf 02_340 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[9] origin:064-gtp-channel-conf 03_340 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[10] origin:064-gtp-channel-conf 02_341 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[11] origin:064-gtp-channel-conf 03_341 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[12] origin:064-gtp-channel-conf 02_342 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[13] origin:064-gtp-channel-conf 03_342 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[14] origin:064-gtp-channel-conf 02_343 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[15] origin:064-gtp-channel-conf 03_343 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[16] origin:064-gtp-channel-conf 02_344 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[17] origin:064-gtp-channel-conf 03_344 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[18] origin:064-gtp-channel-conf 02_345 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[19] origin:064-gtp-channel-conf 03_345 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[20] origin:064-gtp-channel-conf 02_346 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[21] origin:064-gtp-channel-conf 03_346 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[22] origin:064-gtp-channel-conf 02_347 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[23] origin:064-gtp-channel-conf 03_347 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[24] origin:064-gtp-channel-conf 02_348 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[25] origin:064-gtp-channel-conf 03_348 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[26] origin:064-gtp-channel-conf 02_349 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[27] origin:064-gtp-channel-conf 03_349 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[28] origin:064-gtp-channel-conf 02_350 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[29] origin:064-gtp-channel-conf 03_350 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[30] origin:064-gtp-channel-conf 02_351 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PMA_RSV2[31] origin:064-gtp-channel-conf 03_351 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PMA_RSV3[0] origin:064-gtp-channel-conf 02_288 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PMA_RSV3[1] origin:064-gtp-channel-conf 03_288 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PMA_RSV4[0] origin:064-gtp-channel-conf 02_156 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PMA_RSV4[1] origin:064-gtp-channel-conf 03_156 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PMA_RSV4[2] origin:064-gtp-channel-conf 02_157 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PMA_RSV4[3] origin:064-gtp-channel-conf 03_157 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PMA_RSV5[0] origin:064-gtp-channel-conf 03_159 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PMA_RSV6[0] origin:064-gtp-channel-conf 02_303 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.PMA_RSV7[0] origin:064-gtp-channel-conf 03_303 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_BIAS_CFG[0] origin:064-gtp-channel-conf 02_112 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_BIAS_CFG[1] origin:064-gtp-channel-conf 03_112 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_BIAS_CFG[2] origin:064-gtp-channel-conf 02_113 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_BIAS_CFG[3] origin:064-gtp-channel-conf 03_113 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_BIAS_CFG[4] origin:064-gtp-channel-conf 02_114 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_BIAS_CFG[5] origin:064-gtp-channel-conf 03_114 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_BIAS_CFG[6] origin:064-gtp-channel-conf 02_115 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_BIAS_CFG[7] origin:064-gtp-channel-conf 03_115 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_BIAS_CFG[8] origin:064-gtp-channel-conf 02_116 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_BIAS_CFG[9] origin:064-gtp-channel-conf 03_116 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_BIAS_CFG[10] origin:064-gtp-channel-conf 02_117 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_BIAS_CFG[11] origin:064-gtp-channel-conf 03_117 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_BIAS_CFG[12] origin:064-gtp-channel-conf 02_118 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_BIAS_CFG[13] origin:064-gtp-channel-conf 03_118 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_BIAS_CFG[14] origin:064-gtp-channel-conf 02_119 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_BIAS_CFG[15] origin:064-gtp-channel-conf 03_119 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_BUFFER_CFG[0] origin:064-gtp-channel-conf 02_536 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_BUFFER_CFG[1] origin:064-gtp-channel-conf 03_536 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_BUFFER_CFG[2] origin:064-gtp-channel-conf 02_537 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_BUFFER_CFG[3] origin:064-gtp-channel-conf 03_537 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_BUFFER_CFG[4] origin:064-gtp-channel-conf 02_538 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_BUFFER_CFG[5] origin:064-gtp-channel-conf 03_538 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_CLKMUX_EN[0] origin:064-gtp-channel-conf 02_128 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_CM_SEL[0] origin:064-gtp-channel-conf 00_138 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_CM_SEL[1] origin:064-gtp-channel-conf 01_138 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_CM_TRIM[0] origin:064-gtp-channel-conf 02_304 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_CM_TRIM[1] origin:064-gtp-channel-conf 03_304 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_CM_TRIM[2] origin:064-gtp-channel-conf 02_305 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_CM_TRIM[3] origin:064-gtp-channel-conf 03_305 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_DATA_WIDTH[0] origin:064-gtp-channel-conf 01_141 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_DATA_WIDTH[1] origin:064-gtp-channel-conf 00_142 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_DATA_WIDTH[2] origin:064-gtp-channel-conf 01_142 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_DDI_SEL[0] origin:064-gtp-channel-conf 00_696 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_DDI_SEL[1] origin:064-gtp-channel-conf 01_696 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_DDI_SEL[2] origin:064-gtp-channel-conf 00_697 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_DDI_SEL[3] origin:064-gtp-channel-conf 01_697 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_DDI_SEL[4] origin:064-gtp-channel-conf 00_698 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_DDI_SEL[5] origin:064-gtp-channel-conf 01_698 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_DEBUG_CFG[0] origin:064-gtp-channel-conf 02_616 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_DEBUG_CFG[1] origin:064-gtp-channel-conf 03_616 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_DEBUG_CFG[2] origin:064-gtp-channel-conf 02_617 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_DEBUG_CFG[3] origin:064-gtp-channel-conf 03_617 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_DEBUG_CFG[4] origin:064-gtp-channel-conf 02_618 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_DEBUG_CFG[5] origin:064-gtp-channel-conf 03_618 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_DEBUG_CFG[6] origin:064-gtp-channel-conf 02_619 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_DEBUG_CFG[7] origin:064-gtp-channel-conf 03_619 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_DEBUG_CFG[8] origin:064-gtp-channel-conf 02_620 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_DEBUG_CFG[9] origin:064-gtp-channel-conf 03_620 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_DEBUG_CFG[10] origin:064-gtp-channel-conf 02_621 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_DEBUG_CFG[11] origin:064-gtp-channel-conf 03_621 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_DEBUG_CFG[12] origin:064-gtp-channel-conf 02_622 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_DEBUG_CFG[13] origin:064-gtp-channel-conf 03_622 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_DEFER_RESET_BUF_EN origin:064-gtp-channel-conf 02_552 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_DISPERR_SEQ_MATCH origin:064-gtp-channel-conf 01_495 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_OS_CFG[0] origin:064-gtp-channel-conf 00_288 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_OS_CFG[1] origin:064-gtp-channel-conf 01_288 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_OS_CFG[2] origin:064-gtp-channel-conf 00_289 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_OS_CFG[3] origin:064-gtp-channel-conf 01_289 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_OS_CFG[4] origin:064-gtp-channel-conf 00_290 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_OS_CFG[5] origin:064-gtp-channel-conf 01_290 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_OS_CFG[6] origin:064-gtp-channel-conf 00_291 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_OS_CFG[7] origin:064-gtp-channel-conf 01_291 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_OS_CFG[8] origin:064-gtp-channel-conf 00_292 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_OS_CFG[9] origin:064-gtp-channel-conf 01_292 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_OS_CFG[10] origin:064-gtp-channel-conf 00_293 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_OS_CFG[11] origin:064-gtp-channel-conf 01_293 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_OS_CFG[12] origin:064-gtp-channel-conf 00_294 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_SIG_VALID_DLY[0] origin:064-gtp-channel-conf 00_524 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_SIG_VALID_DLY[1] origin:064-gtp-channel-conf 01_524 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_SIG_VALID_DLY[2] origin:064-gtp-channel-conf 00_525 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_SIG_VALID_DLY[3] origin:064-gtp-channel-conf 01_525 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_SIG_VALID_DLY[4] origin:064-gtp-channel-conf 00_526 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_XCLK_SEL.RXUSR origin:064-gtp-channel-conf 00_143 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_CLK25_DIV[0] origin:064-gtp-channel-conf 00_139 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_CLK25_DIV[1] origin:064-gtp-channel-conf 01_139 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_CLK25_DIV[2] origin:064-gtp-channel-conf 00_140 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_CLK25_DIV[3] origin:064-gtp-channel-conf 01_140 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RX_CLK25_DIV[4] origin:064-gtp-channel-conf 00_141 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXBUF_ADDR_MODE.FAST origin:064-gtp-channel-conf 03_555 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXBUF_EIDLE_HI_CNT[0] origin:064-gtp-channel-conf 02_558 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXBUF_EIDLE_HI_CNT[1] origin:064-gtp-channel-conf 03_558 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXBUF_EIDLE_HI_CNT[2] origin:064-gtp-channel-conf 02_559 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXBUF_EIDLE_HI_CNT[3] origin:064-gtp-channel-conf 03_559 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXBUF_EIDLE_LO_CNT[0] origin:064-gtp-channel-conf 02_556 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXBUF_EIDLE_LO_CNT[1] origin:064-gtp-channel-conf 03_556 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXBUF_EIDLE_LO_CNT[2] origin:064-gtp-channel-conf 02_557 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXBUF_EIDLE_LO_CNT[3] origin:064-gtp-channel-conf 03_557 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXBUF_EN origin:064-gtp-channel-conf 02_11 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXBUF_RESET_ON_CB_CHANGE origin:064-gtp-channel-conf 02_560 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXBUF_RESET_ON_COMMAALIGN origin:064-gtp-channel-conf 02_561 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXBUF_RESET_ON_EIDLE origin:064-gtp-channel-conf 02_547 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXBUF_RESET_ON_RATE_CHANGE origin:064-gtp-channel-conf 03_560 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXBUF_THRESH_OVFLW[0] origin:064-gtp-channel-conf 03_552 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXBUF_THRESH_OVFLW[1] origin:064-gtp-channel-conf 02_553 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXBUF_THRESH_OVFLW[2] origin:064-gtp-channel-conf 03_553 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXBUF_THRESH_OVFLW[3] origin:064-gtp-channel-conf 02_554 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXBUF_THRESH_OVFLW[4] origin:064-gtp-channel-conf 03_554 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXBUF_THRESH_OVFLW[5] origin:064-gtp-channel-conf 02_555 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXBUF_THRESH_OVRD origin:064-gtp-channel-conf 02_548 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXBUF_THRESH_UNDFLW[0] origin:064-gtp-channel-conf 02_544 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXBUF_THRESH_UNDFLW[1] origin:064-gtp-channel-conf 03_544 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXBUF_THRESH_UNDFLW[2] origin:064-gtp-channel-conf 02_545 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXBUF_THRESH_UNDFLW[3] origin:064-gtp-channel-conf 03_545 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXBUF_THRESH_UNDFLW[4] origin:064-gtp-channel-conf 02_546 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXBUF_THRESH_UNDFLW[5] origin:064-gtp-channel-conf 03_546 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXBUFRESET_TIME[0] origin:064-gtp-channel-conf 01_101 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXBUFRESET_TIME[1] origin:064-gtp-channel-conf 00_102 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXBUFRESET_TIME[2] origin:064-gtp-channel-conf 01_102 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXBUFRESET_TIME[3] origin:064-gtp-channel-conf 00_103 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXBUFRESET_TIME[4] origin:064-gtp-channel-conf 01_103 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[0] origin:064-gtp-channel-conf 02_640 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[1] origin:064-gtp-channel-conf 03_640 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[2] origin:064-gtp-channel-conf 02_641 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[3] origin:064-gtp-channel-conf 03_641 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[4] origin:064-gtp-channel-conf 02_642 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[5] origin:064-gtp-channel-conf 03_642 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[6] origin:064-gtp-channel-conf 02_643 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[7] origin:064-gtp-channel-conf 03_643 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[8] origin:064-gtp-channel-conf 02_644 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[9] origin:064-gtp-channel-conf 03_644 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[10] origin:064-gtp-channel-conf 02_645 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[11] origin:064-gtp-channel-conf 03_645 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[12] origin:064-gtp-channel-conf 02_646 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[13] origin:064-gtp-channel-conf 03_646 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[14] origin:064-gtp-channel-conf 02_647 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[15] origin:064-gtp-channel-conf 03_647 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[16] origin:064-gtp-channel-conf 02_648 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[17] origin:064-gtp-channel-conf 03_648 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[18] origin:064-gtp-channel-conf 02_649 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[19] origin:064-gtp-channel-conf 03_649 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[20] origin:064-gtp-channel-conf 02_650 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[21] origin:064-gtp-channel-conf 03_650 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[22] origin:064-gtp-channel-conf 02_651 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[23] origin:064-gtp-channel-conf 03_651 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[24] origin:064-gtp-channel-conf 02_652 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[25] origin:064-gtp-channel-conf 03_652 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[26] origin:064-gtp-channel-conf 02_653 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[27] origin:064-gtp-channel-conf 03_653 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[28] origin:064-gtp-channel-conf 02_654 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[29] origin:064-gtp-channel-conf 03_654 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[30] origin:064-gtp-channel-conf 02_655 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[31] origin:064-gtp-channel-conf 03_655 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[32] origin:064-gtp-channel-conf 02_656 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[33] origin:064-gtp-channel-conf 03_656 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[34] origin:064-gtp-channel-conf 02_657 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[35] origin:064-gtp-channel-conf 03_657 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[36] origin:064-gtp-channel-conf 02_658 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[37] origin:064-gtp-channel-conf 03_658 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[38] origin:064-gtp-channel-conf 02_659 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[39] origin:064-gtp-channel-conf 03_659 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[40] origin:064-gtp-channel-conf 02_660 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[41] origin:064-gtp-channel-conf 03_660 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[42] origin:064-gtp-channel-conf 02_661 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[43] origin:064-gtp-channel-conf 03_661 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[44] origin:064-gtp-channel-conf 02_662 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[45] origin:064-gtp-channel-conf 03_662 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[46] origin:064-gtp-channel-conf 02_663 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[47] origin:064-gtp-channel-conf 03_663 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[48] origin:064-gtp-channel-conf 02_664 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[49] origin:064-gtp-channel-conf 03_664 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[50] origin:064-gtp-channel-conf 02_665 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[51] origin:064-gtp-channel-conf 03_665 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[52] origin:064-gtp-channel-conf 02_666 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[53] origin:064-gtp-channel-conf 03_666 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[54] origin:064-gtp-channel-conf 02_667 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[55] origin:064-gtp-channel-conf 03_667 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[56] origin:064-gtp-channel-conf 02_668 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[57] origin:064-gtp-channel-conf 03_668 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[58] origin:064-gtp-channel-conf 02_669 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[59] origin:064-gtp-channel-conf 03_669 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[60] origin:064-gtp-channel-conf 02_670 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[61] origin:064-gtp-channel-conf 03_670 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[62] origin:064-gtp-channel-conf 02_671 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[63] origin:064-gtp-channel-conf 03_671 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[64] origin:064-gtp-channel-conf 02_672 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[65] origin:064-gtp-channel-conf 03_672 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[66] origin:064-gtp-channel-conf 02_673 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[67] origin:064-gtp-channel-conf 03_673 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[68] origin:064-gtp-channel-conf 02_674 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[69] origin:064-gtp-channel-conf 03_674 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[70] origin:064-gtp-channel-conf 02_675 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[71] origin:064-gtp-channel-conf 03_675 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[72] origin:064-gtp-channel-conf 02_676 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[73] origin:064-gtp-channel-conf 03_676 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[74] origin:064-gtp-channel-conf 02_677 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[75] origin:064-gtp-channel-conf 03_677 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[76] origin:064-gtp-channel-conf 02_678 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[77] origin:064-gtp-channel-conf 03_678 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[78] origin:064-gtp-channel-conf 02_679 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[79] origin:064-gtp-channel-conf 03_679 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[80] origin:064-gtp-channel-conf 02_680 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[81] origin:064-gtp-channel-conf 03_680 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_CFG[82] origin:064-gtp-channel-conf 02_681 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_FR_RESET_ON_EIDLE[0] origin:064-gtp-channel-conf 02_638 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_HOLD_DURING_EIDLE[0] origin:064-gtp-channel-conf 03_637 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_LOCK_CFG[0] origin:064-gtp-channel-conf 02_632 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_LOCK_CFG[1] origin:064-gtp-channel-conf 03_632 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_LOCK_CFG[2] origin:064-gtp-channel-conf 02_633 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_LOCK_CFG[3] origin:064-gtp-channel-conf 03_633 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_LOCK_CFG[4] origin:064-gtp-channel-conf 02_634 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_LOCK_CFG[5] origin:064-gtp-channel-conf 03_634 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDR_PH_RESET_ON_EIDLE[0] origin:064-gtp-channel-conf 03_638 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDRFREQRESET_TIME[0] origin:064-gtp-channel-conf 01_106 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDRFREQRESET_TIME[1] origin:064-gtp-channel-conf 00_107 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDRFREQRESET_TIME[2] origin:064-gtp-channel-conf 01_107 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDRFREQRESET_TIME[3] origin:064-gtp-channel-conf 00_108 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDRFREQRESET_TIME[4] origin:064-gtp-channel-conf 01_108 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDRPHRESET_TIME[0] origin:064-gtp-channel-conf 00_109 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDRPHRESET_TIME[1] origin:064-gtp-channel-conf 01_109 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDRPHRESET_TIME[2] origin:064-gtp-channel-conf 00_110 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDRPHRESET_TIME[3] origin:064-gtp-channel-conf 01_110 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXCDRPHRESET_TIME[4] origin:064-gtp-channel-conf 00_111 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXDLY_CFG[0] origin:064-gtp-channel-conf 00_680 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXDLY_CFG[1] origin:064-gtp-channel-conf 01_680 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXDLY_CFG[2] origin:064-gtp-channel-conf 00_681 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXDLY_CFG[3] origin:064-gtp-channel-conf 01_681 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXDLY_CFG[4] origin:064-gtp-channel-conf 00_682 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXDLY_CFG[5] origin:064-gtp-channel-conf 01_682 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXDLY_CFG[6] origin:064-gtp-channel-conf 00_683 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXDLY_CFG[7] origin:064-gtp-channel-conf 01_683 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXDLY_CFG[8] origin:064-gtp-channel-conf 00_684 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXDLY_CFG[9] origin:064-gtp-channel-conf 01_684 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXDLY_CFG[10] origin:064-gtp-channel-conf 00_685 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXDLY_CFG[11] origin:064-gtp-channel-conf 01_685 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXDLY_CFG[12] origin:064-gtp-channel-conf 00_686 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXDLY_CFG[13] origin:064-gtp-channel-conf 01_686 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXDLY_CFG[14] origin:064-gtp-channel-conf 00_687 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXDLY_CFG[15] origin:064-gtp-channel-conf 01_687 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXDLY_LCFG[0] origin:064-gtp-channel-conf 02_576 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXDLY_LCFG[1] origin:064-gtp-channel-conf 03_576 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXDLY_LCFG[2] origin:064-gtp-channel-conf 02_577 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXDLY_LCFG[3] origin:064-gtp-channel-conf 03_577 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXDLY_LCFG[4] origin:064-gtp-channel-conf 02_578 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXDLY_LCFG[5] origin:064-gtp-channel-conf 03_578 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXDLY_LCFG[6] origin:064-gtp-channel-conf 02_579 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXDLY_LCFG[7] origin:064-gtp-channel-conf 03_579 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXDLY_LCFG[8] origin:064-gtp-channel-conf 02_580 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXDLY_TAP_CFG[0] origin:064-gtp-channel-conf 00_672 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXDLY_TAP_CFG[1] origin:064-gtp-channel-conf 01_672 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXDLY_TAP_CFG[2] origin:064-gtp-channel-conf 00_673 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXDLY_TAP_CFG[3] origin:064-gtp-channel-conf 01_673 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXDLY_TAP_CFG[4] origin:064-gtp-channel-conf 00_674 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXDLY_TAP_CFG[5] origin:064-gtp-channel-conf 01_674 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXDLY_TAP_CFG[6] origin:064-gtp-channel-conf 00_675 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXDLY_TAP_CFG[7] origin:064-gtp-channel-conf 01_675 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXDLY_TAP_CFG[8] origin:064-gtp-channel-conf 00_676 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXDLY_TAP_CFG[9] origin:064-gtp-channel-conf 01_676 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXDLY_TAP_CFG[10] origin:064-gtp-channel-conf 00_677 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXDLY_TAP_CFG[11] origin:064-gtp-channel-conf 01_677 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXDLY_TAP_CFG[12] origin:064-gtp-channel-conf 00_678 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXDLY_TAP_CFG[13] origin:064-gtp-channel-conf 01_678 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXDLY_TAP_CFG[14] origin:064-gtp-channel-conf 00_679 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXDLY_TAP_CFG[15] origin:064-gtp-channel-conf 01_679 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXGEARBOX_EN origin:064-gtp-channel-conf 01_607 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXISCANRESET_TIME[0] origin:064-gtp-channel-conf 01_123 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXISCANRESET_TIME[1] origin:064-gtp-channel-conf 00_124 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXISCANRESET_TIME[2] origin:064-gtp-channel-conf 01_124 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXISCANRESET_TIME[3] origin:064-gtp-channel-conf 00_125 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXISCANRESET_TIME[4] origin:064-gtp-channel-conf 01_125 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPM_BIAS_STARTUP_DISABLE[0] origin:064-gtp-channel-conf 03_391 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPM_CFG[0] origin:064-gtp-channel-conf 02_328 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPM_CFG[1] origin:064-gtp-channel-conf 03_328 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPM_CFG[2] origin:064-gtp-channel-conf 02_329 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPM_CFG[3] origin:064-gtp-channel-conf 03_329 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPM_CM_CFG[0] origin:064-gtp-channel-conf 02_430 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPM_GC_CFG[0] origin:064-gtp-channel-conf 02_432 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPM_GC_CFG[1] origin:064-gtp-channel-conf 03_432 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPM_GC_CFG[2] origin:064-gtp-channel-conf 02_433 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPM_GC_CFG[3] origin:064-gtp-channel-conf 03_433 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPM_GC_CFG[4] origin:064-gtp-channel-conf 02_434 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPM_GC_CFG[5] origin:064-gtp-channel-conf 03_434 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPM_GC_CFG[6] origin:064-gtp-channel-conf 02_435 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPM_GC_CFG[7] origin:064-gtp-channel-conf 03_435 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPM_GC_CFG[8] origin:064-gtp-channel-conf 02_436 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPM_GC_CFG2[0] origin:064-gtp-channel-conf 03_442 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPM_GC_CFG2[1] origin:064-gtp-channel-conf 02_443 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPM_GC_CFG2[2] origin:064-gtp-channel-conf 03_443 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG[0] origin:064-gtp-channel-conf 00_336 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG[1] origin:064-gtp-channel-conf 01_336 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG[2] origin:064-gtp-channel-conf 00_337 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG[3] origin:064-gtp-channel-conf 01_337 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG[4] origin:064-gtp-channel-conf 00_338 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG[5] origin:064-gtp-channel-conf 01_338 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG[6] origin:064-gtp-channel-conf 00_339 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG[7] origin:064-gtp-channel-conf 01_339 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG[8] origin:064-gtp-channel-conf 00_340 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG[9] origin:064-gtp-channel-conf 01_340 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG[10] origin:064-gtp-channel-conf 00_341 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG[11] origin:064-gtp-channel-conf 01_341 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG[12] origin:064-gtp-channel-conf 00_342 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG[13] origin:064-gtp-channel-conf 01_342 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG2[0] origin:064-gtp-channel-conf 02_424 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG2[1] origin:064-gtp-channel-conf 03_424 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG2[2] origin:064-gtp-channel-conf 02_425 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG2[3] origin:064-gtp-channel-conf 03_425 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG2[4] origin:064-gtp-channel-conf 02_426 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG3[0] origin:064-gtp-channel-conf 03_389 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG3[1] origin:064-gtp-channel-conf 02_390 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG3[2] origin:064-gtp-channel-conf 03_390 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPM_HF_CFG3[3] origin:064-gtp-channel-conf 02_391 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPM_HOLD_DURING_EIDLE[0] origin:064-gtp-channel-conf 00_247 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPM_INCM_CFG[0] origin:064-gtp-channel-conf 02_439 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPM_IPCM_CFG[0] origin:064-gtp-channel-conf 03_439 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG[0] origin:064-gtp-channel-conf 00_344 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG[1] origin:064-gtp-channel-conf 01_344 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG[2] origin:064-gtp-channel-conf 00_345 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG[3] origin:064-gtp-channel-conf 01_345 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG[4] origin:064-gtp-channel-conf 00_346 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG[5] origin:064-gtp-channel-conf 01_346 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG[6] origin:064-gtp-channel-conf 00_347 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG[7] origin:064-gtp-channel-conf 01_347 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG[8] origin:064-gtp-channel-conf 00_348 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG[9] origin:064-gtp-channel-conf 01_348 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG[10] origin:064-gtp-channel-conf 00_349 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG[11] origin:064-gtp-channel-conf 01_349 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG[12] origin:064-gtp-channel-conf 00_350 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG[13] origin:064-gtp-channel-conf 01_350 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG[14] origin:064-gtp-channel-conf 00_351 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG[15] origin:064-gtp-channel-conf 01_351 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG[16] origin:064-gtp-channel-conf 00_343 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG[17] origin:064-gtp-channel-conf 01_343 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG2[0] origin:064-gtp-channel-conf 03_426 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG2[1] origin:064-gtp-channel-conf 02_427 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG2[2] origin:064-gtp-channel-conf 03_427 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG2[3] origin:064-gtp-channel-conf 02_428 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPM_LF_CFG2[4] origin:064-gtp-channel-conf 03_428 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPM_OSINT_CFG[0] origin:064-gtp-channel-conf 02_440 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPM_OSINT_CFG[1] origin:064-gtp-channel-conf 03_440 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPM_OSINT_CFG[2] origin:064-gtp-channel-conf 02_441 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPM_CFG1[0] origin:064-gtp-channel-conf 02_330 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPMRESET_TIME[0] origin:064-gtp-channel-conf 00_112 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPMRESET_TIME[1] origin:064-gtp-channel-conf 01_112 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPMRESET_TIME[2] origin:064-gtp-channel-conf 00_113 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPMRESET_TIME[3] origin:064-gtp-channel-conf 01_113 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPMRESET_TIME[4] origin:064-gtp-channel-conf 00_114 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPMRESET_TIME[5] origin:064-gtp-channel-conf 01_114 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXLPMRESET_TIME[6] origin:064-gtp-channel-conf 00_115 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXOOB_CFG[0] origin:064-gtp-channel-conf 00_144 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXOOB_CFG[1] origin:064-gtp-channel-conf 01_144 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXOOB_CFG[2] origin:064-gtp-channel-conf 00_145 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXOOB_CFG[3] origin:064-gtp-channel-conf 01_145 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXOOB_CFG[4] origin:064-gtp-channel-conf 00_146 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXOOB_CFG[5] origin:064-gtp-channel-conf 01_146 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXOOB_CFG[6] origin:064-gtp-channel-conf 00_147 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXOOB_CLK_CFG.FABRIC origin:064-gtp-channel-conf 03_129 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXOSCALRESET_TIME[0] origin:064-gtp-channel-conf 00_187 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXOSCALRESET_TIME[1] origin:064-gtp-channel-conf 01_187 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXOSCALRESET_TIME[2] origin:064-gtp-channel-conf 00_188 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXOSCALRESET_TIME[3] origin:064-gtp-channel-conf 01_188 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXOSCALRESET_TIME[4] origin:064-gtp-channel-conf 00_189 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXOSCALRESET_TIMEOUT[0] origin:064-gtp-channel-conf 01_189 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXOSCALRESET_TIMEOUT[1] origin:064-gtp-channel-conf 00_190 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXOSCALRESET_TIMEOUT[2] origin:064-gtp-channel-conf 01_190 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXOSCALRESET_TIMEOUT[3] origin:064-gtp-channel-conf 00_191 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXOSCALRESET_TIMEOUT[4] origin:064-gtp-channel-conf 01_191 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXOUT_DIV[0] origin:064-gtp-channel-conf 02_384 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXOUT_DIV[1] origin:064-gtp-channel-conf 03_384 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXPCSRESET_TIME[0] origin:064-gtp-channel-conf 01_115 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXPCSRESET_TIME[1] origin:064-gtp-channel-conf 00_116 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXPCSRESET_TIME[2] origin:064-gtp-channel-conf 01_116 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXPCSRESET_TIME[3] origin:064-gtp-channel-conf 00_117 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXPCSRESET_TIME[4] origin:064-gtp-channel-conf 01_117 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[0] origin:064-gtp-channel-conf 02_584 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[1] origin:064-gtp-channel-conf 03_584 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[2] origin:064-gtp-channel-conf 02_585 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[3] origin:064-gtp-channel-conf 03_585 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[4] origin:064-gtp-channel-conf 02_586 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[5] origin:064-gtp-channel-conf 03_586 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[6] origin:064-gtp-channel-conf 02_587 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[7] origin:064-gtp-channel-conf 03_587 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[8] origin:064-gtp-channel-conf 02_588 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[9] origin:064-gtp-channel-conf 03_588 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[10] origin:064-gtp-channel-conf 02_589 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[11] origin:064-gtp-channel-conf 03_589 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[12] origin:064-gtp-channel-conf 02_590 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[13] origin:064-gtp-channel-conf 03_590 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[14] origin:064-gtp-channel-conf 02_591 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[15] origin:064-gtp-channel-conf 03_591 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[16] origin:064-gtp-channel-conf 02_592 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[17] origin:064-gtp-channel-conf 03_592 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[18] origin:064-gtp-channel-conf 02_593 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[19] origin:064-gtp-channel-conf 03_593 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[20] origin:064-gtp-channel-conf 02_594 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[21] origin:064-gtp-channel-conf 03_594 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[22] origin:064-gtp-channel-conf 02_595 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXPH_CFG[23] origin:064-gtp-channel-conf 03_595 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXPH_MONITOR_SEL[0] origin:064-gtp-channel-conf 00_700 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXPH_MONITOR_SEL[1] origin:064-gtp-channel-conf 01_700 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXPH_MONITOR_SEL[2] origin:064-gtp-channel-conf 00_701 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXPH_MONITOR_SEL[3] origin:064-gtp-channel-conf 01_701 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXPH_MONITOR_SEL[4] origin:064-gtp-channel-conf 00_702 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[0] origin:064-gtp-channel-conf 02_600 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[1] origin:064-gtp-channel-conf 03_600 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[2] origin:064-gtp-channel-conf 02_601 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[3] origin:064-gtp-channel-conf 03_601 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[4] origin:064-gtp-channel-conf 02_602 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[5] origin:064-gtp-channel-conf 03_602 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[6] origin:064-gtp-channel-conf 02_603 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[7] origin:064-gtp-channel-conf 03_603 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[8] origin:064-gtp-channel-conf 02_604 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[9] origin:064-gtp-channel-conf 03_604 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[10] origin:064-gtp-channel-conf 02_605 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[11] origin:064-gtp-channel-conf 03_605 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[12] origin:064-gtp-channel-conf 02_606 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[13] origin:064-gtp-channel-conf 03_606 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[14] origin:064-gtp-channel-conf 02_607 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[15] origin:064-gtp-channel-conf 03_607 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[16] origin:064-gtp-channel-conf 02_608 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[17] origin:064-gtp-channel-conf 03_608 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[18] origin:064-gtp-channel-conf 02_609 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[19] origin:064-gtp-channel-conf 03_609 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[20] origin:064-gtp-channel-conf 02_610 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[21] origin:064-gtp-channel-conf 03_610 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[22] origin:064-gtp-channel-conf 02_611 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXPHDLY_CFG[23] origin:064-gtp-channel-conf 03_611 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXPI_CFG0[0] origin:064-gtp-channel-conf 03_430 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXPI_CFG0[1] origin:064-gtp-channel-conf 02_431 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXPI_CFG0[2] origin:064-gtp-channel-conf 03_431 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXPI_CFG1[0] origin:064-gtp-channel-conf 02_442 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXPI_CFG2[0] origin:064-gtp-channel-conf 03_441 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXPMARESET_TIME[0] origin:064-gtp-channel-conf 00_104 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXPMARESET_TIME[1] origin:064-gtp-channel-conf 01_104 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXPMARESET_TIME[2] origin:064-gtp-channel-conf 00_105 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXPMARESET_TIME[3] origin:064-gtp-channel-conf 01_105 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXPMARESET_TIME[4] origin:064-gtp-channel-conf 00_106 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXPRBS_ERR_LOOPBACK[0] origin:064-gtp-channel-conf 00_136 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXSLIDE_AUTO_WAIT[0] origin:064-gtp-channel-conf 00_520 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXSLIDE_AUTO_WAIT[1] origin:064-gtp-channel-conf 01_520 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXSLIDE_AUTO_WAIT[2] origin:064-gtp-channel-conf 00_521 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXSLIDE_AUTO_WAIT[3] origin:064-gtp-channel-conf 01_521 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXSLIDE_MODE.AUTO origin:064-gtp-channel-conf !01_519 00_519 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXSLIDE_MODE.PCS origin:064-gtp-channel-conf !00_519 01_519 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXSLIDE_MODE.PMA origin:064-gtp-channel-conf 00_519 01_519 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXSYNC_MULTILANE[0] origin:064-gtp-channel-conf 00_133 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXSYNC_OVRD[0] origin:064-gtp-channel-conf 01_135 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.RXSYNC_SKIP_DA[0] origin:064-gtp-channel-conf 01_134 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.SAS_MAX_COM[0] origin:064-gtp-channel-conf 00_171 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.SAS_MAX_COM[1] origin:064-gtp-channel-conf 01_171 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.SAS_MAX_COM[2] origin:064-gtp-channel-conf 00_172 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.SAS_MAX_COM[3] origin:064-gtp-channel-conf 01_172 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.SAS_MAX_COM[4] origin:064-gtp-channel-conf 00_173 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.SAS_MAX_COM[5] origin:064-gtp-channel-conf 01_173 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.SAS_MAX_COM[6] origin:064-gtp-channel-conf 00_174 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.SAS_MIN_COM[0] origin:064-gtp-channel-conf 01_156 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.SAS_MIN_COM[1] origin:064-gtp-channel-conf 00_157 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.SAS_MIN_COM[2] origin:064-gtp-channel-conf 01_157 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.SAS_MIN_COM[3] origin:064-gtp-channel-conf 00_158 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.SAS_MIN_COM[4] origin:064-gtp-channel-conf 01_158 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.SAS_MIN_COM[5] origin:064-gtp-channel-conf 00_159 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.SATA_BURST_SEQ_LEN[0] origin:064-gtp-channel-conf 00_150 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.SATA_BURST_SEQ_LEN[1] origin:064-gtp-channel-conf 01_150 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.SATA_BURST_SEQ_LEN[2] origin:064-gtp-channel-conf 00_151 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.SATA_BURST_SEQ_LEN[3] origin:064-gtp-channel-conf 01_151 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.SATA_BURST_VAL[0] origin:064-gtp-channel-conf 01_147 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.SATA_BURST_VAL[1] origin:064-gtp-channel-conf 00_148 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.SATA_BURST_VAL[2] origin:064-gtp-channel-conf 01_148 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.SATA_EIDLE_VAL[0] origin:064-gtp-channel-conf 00_152 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.SATA_EIDLE_VAL[1] origin:064-gtp-channel-conf 01_152 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.SATA_EIDLE_VAL[2] origin:064-gtp-channel-conf 00_153 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.SATA_MAX_BURST[0] origin:064-gtp-channel-conf 00_168 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.SATA_MAX_BURST[1] origin:064-gtp-channel-conf 01_168 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.SATA_MAX_BURST[2] origin:064-gtp-channel-conf 00_169 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.SATA_MAX_BURST[3] origin:064-gtp-channel-conf 01_169 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.SATA_MAX_BURST[4] origin:064-gtp-channel-conf 00_170 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.SATA_MAX_BURST[5] origin:064-gtp-channel-conf 01_170 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.SATA_MAX_INIT[0] origin:064-gtp-channel-conf 00_176 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.SATA_MAX_INIT[1] origin:064-gtp-channel-conf 01_176 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.SATA_MAX_INIT[2] origin:064-gtp-channel-conf 00_177 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.SATA_MAX_INIT[3] origin:064-gtp-channel-conf 01_177 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.SATA_MAX_INIT[4] origin:064-gtp-channel-conf 00_178 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.SATA_MAX_INIT[5] origin:064-gtp-channel-conf 01_178 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.SATA_MAX_WAKE[0] origin:064-gtp-channel-conf 00_179 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.SATA_MAX_WAKE[1] origin:064-gtp-channel-conf 01_179 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.SATA_MAX_WAKE[2] origin:064-gtp-channel-conf 00_180 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.SATA_MAX_WAKE[3] origin:064-gtp-channel-conf 01_180 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.SATA_MAX_WAKE[4] origin:064-gtp-channel-conf 00_181 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.SATA_MAX_WAKE[5] origin:064-gtp-channel-conf 01_181 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.SATA_MIN_BURST[0] origin:064-gtp-channel-conf 01_153 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.SATA_MIN_BURST[1] origin:064-gtp-channel-conf 00_154 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.SATA_MIN_BURST[2] origin:064-gtp-channel-conf 01_154 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.SATA_MIN_BURST[3] origin:064-gtp-channel-conf 00_155 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.SATA_MIN_BURST[4] origin:064-gtp-channel-conf 01_155 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.SATA_MIN_BURST[5] origin:064-gtp-channel-conf 00_156 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.SATA_MIN_INIT[0] origin:064-gtp-channel-conf 00_160 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.SATA_MIN_INIT[1] origin:064-gtp-channel-conf 01_160 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.SATA_MIN_INIT[2] origin:064-gtp-channel-conf 00_161 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.SATA_MIN_INIT[3] origin:064-gtp-channel-conf 01_161 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.SATA_MIN_INIT[4] origin:064-gtp-channel-conf 00_162 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.SATA_MIN_INIT[5] origin:064-gtp-channel-conf 01_162 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.SATA_MIN_WAKE[0] origin:064-gtp-channel-conf 00_163 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.SATA_MIN_WAKE[1] origin:064-gtp-channel-conf 01_163 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.SATA_MIN_WAKE[2] origin:064-gtp-channel-conf 00_164 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.SATA_MIN_WAKE[3] origin:064-gtp-channel-conf 01_164 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.SATA_MIN_WAKE[4] origin:064-gtp-channel-conf 00_165 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.SATA_MIN_WAKE[5] origin:064-gtp-channel-conf 01_165 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.SATA_PLL_CFG.VCO_1500MHZ origin:064-gtp-channel-conf 02_55 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.SATA_PLL_CFG.VCO_750MHZ origin:064-gtp-channel-conf 03_55 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.SHOW_REALIGN_COMMA origin:064-gtp-channel-conf 01_522 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TERM_RCAL_CFG[0] origin:064-gtp-channel-conf 02_136 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TERM_RCAL_CFG[1] origin:064-gtp-channel-conf 03_136 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TERM_RCAL_CFG[2] origin:064-gtp-channel-conf 02_137 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TERM_RCAL_CFG[3] origin:064-gtp-channel-conf 03_137 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TERM_RCAL_CFG[4] origin:064-gtp-channel-conf 02_138 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TERM_RCAL_CFG[5] origin:064-gtp-channel-conf 03_138 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TERM_RCAL_CFG[6] origin:064-gtp-channel-conf 02_139 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TERM_RCAL_CFG[7] origin:064-gtp-channel-conf 03_139 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TERM_RCAL_CFG[8] origin:064-gtp-channel-conf 02_140 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TERM_RCAL_CFG[9] origin:064-gtp-channel-conf 03_140 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TERM_RCAL_CFG[10] origin:064-gtp-channel-conf 02_141 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TERM_RCAL_CFG[11] origin:064-gtp-channel-conf 03_141 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TERM_RCAL_CFG[12] origin:064-gtp-channel-conf 02_142 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TERM_RCAL_CFG[13] origin:064-gtp-channel-conf 03_142 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TERM_RCAL_CFG[14] origin:064-gtp-channel-conf 02_143 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TERM_RCAL_OVRD[0] origin:064-gtp-channel-conf 03_150 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TERM_RCAL_OVRD[1] origin:064-gtp-channel-conf 02_151 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TERM_RCAL_OVRD[2] origin:064-gtp-channel-conf 03_151 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TRANS_TIME_RATE[0] origin:064-gtp-channel-conf 00_192 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TRANS_TIME_RATE[1] origin:064-gtp-channel-conf 01_192 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TRANS_TIME_RATE[2] origin:064-gtp-channel-conf 00_193 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TRANS_TIME_RATE[3] origin:064-gtp-channel-conf 01_193 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TRANS_TIME_RATE[4] origin:064-gtp-channel-conf 00_194 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TRANS_TIME_RATE[5] origin:064-gtp-channel-conf 01_194 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TRANS_TIME_RATE[6] origin:064-gtp-channel-conf 00_195 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TRANS_TIME_RATE[7] origin:064-gtp-channel-conf 01_195 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TST_RSV[0] origin:064-gtp-channel-conf 02_504 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TST_RSV[1] origin:064-gtp-channel-conf 03_504 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TST_RSV[2] origin:064-gtp-channel-conf 02_505 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TST_RSV[3] origin:064-gtp-channel-conf 03_505 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TST_RSV[4] origin:064-gtp-channel-conf 02_506 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TST_RSV[5] origin:064-gtp-channel-conf 03_506 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TST_RSV[6] origin:064-gtp-channel-conf 02_507 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TST_RSV[7] origin:064-gtp-channel-conf 03_507 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TST_RSV[8] origin:064-gtp-channel-conf 02_508 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TST_RSV[9] origin:064-gtp-channel-conf 03_508 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TST_RSV[10] origin:064-gtp-channel-conf 02_509 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TST_RSV[11] origin:064-gtp-channel-conf 03_509 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TST_RSV[12] origin:064-gtp-channel-conf 02_510 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TST_RSV[13] origin:064-gtp-channel-conf 03_510 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TST_RSV[14] origin:064-gtp-channel-conf 02_511 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TST_RSV[15] origin:064-gtp-channel-conf 03_511 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TST_RSV[16] origin:064-gtp-channel-conf 02_512 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TST_RSV[17] origin:064-gtp-channel-conf 03_512 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TST_RSV[18] origin:064-gtp-channel-conf 02_513 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TST_RSV[19] origin:064-gtp-channel-conf 03_513 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TST_RSV[20] origin:064-gtp-channel-conf 02_514 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TST_RSV[21] origin:064-gtp-channel-conf 03_514 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TST_RSV[22] origin:064-gtp-channel-conf 02_515 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TST_RSV[23] origin:064-gtp-channel-conf 03_515 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TST_RSV[24] origin:064-gtp-channel-conf 02_516 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TST_RSV[25] origin:064-gtp-channel-conf 03_516 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TST_RSV[26] origin:064-gtp-channel-conf 02_517 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TST_RSV[27] origin:064-gtp-channel-conf 03_517 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TST_RSV[28] origin:064-gtp-channel-conf 02_518 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TST_RSV[29] origin:064-gtp-channel-conf 03_518 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TST_RSV[30] origin:064-gtp-channel-conf 02_519 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TST_RSV[31] origin:064-gtp-channel-conf 03_519 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_CLKMUX_EN[0] origin:064-gtp-channel-conf 03_128 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_DATA_WIDTH[0] origin:064-gtp-channel-conf 02_152 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_DATA_WIDTH[1] origin:064-gtp-channel-conf 03_152 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_DATA_WIDTH[2] origin:064-gtp-channel-conf 02_153 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_DRIVE_MODE.PIPE origin:064-gtp-channel-conf 00_200 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_EIDLE_ASSERT_DELAY[0] origin:064-gtp-channel-conf 00_203 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_EIDLE_ASSERT_DELAY[1] origin:064-gtp-channel-conf 01_203 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_EIDLE_ASSERT_DELAY[2] origin:064-gtp-channel-conf 00_204 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_EIDLE_DEASSERT_DELAY[0] origin:064-gtp-channel-conf 01_204 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_EIDLE_DEASSERT_DELAY[1] origin:064-gtp-channel-conf 00_205 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_EIDLE_DEASSERT_DELAY[2] origin:064-gtp-channel-conf 01_205 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_LOOPBACK_DRIVE_HIZ origin:064-gtp-channel-conf 01_202 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_MAINCURSOR_SEL[0] origin:064-gtp-channel-conf 03_289 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_0[0] origin:064-gtp-channel-conf 02_232 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_0[1] origin:064-gtp-channel-conf 03_232 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_0[2] origin:064-gtp-channel-conf 02_233 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_0[3] origin:064-gtp-channel-conf 03_233 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_0[4] origin:064-gtp-channel-conf 02_234 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_0[5] origin:064-gtp-channel-conf 03_234 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_0[6] origin:064-gtp-channel-conf 02_235 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_1[0] origin:064-gtp-channel-conf 02_236 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_1[1] origin:064-gtp-channel-conf 03_236 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_1[2] origin:064-gtp-channel-conf 02_237 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_1[3] origin:064-gtp-channel-conf 03_237 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_1[4] origin:064-gtp-channel-conf 02_238 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_1[5] origin:064-gtp-channel-conf 03_238 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_1[6] origin:064-gtp-channel-conf 02_239 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_2[0] origin:064-gtp-channel-conf 02_240 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_2[1] origin:064-gtp-channel-conf 03_240 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_2[2] origin:064-gtp-channel-conf 02_241 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_2[3] origin:064-gtp-channel-conf 03_241 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_2[4] origin:064-gtp-channel-conf 02_242 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_2[5] origin:064-gtp-channel-conf 03_242 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_2[6] origin:064-gtp-channel-conf 02_243 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_3[0] origin:064-gtp-channel-conf 02_244 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_3[1] origin:064-gtp-channel-conf 03_244 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_3[2] origin:064-gtp-channel-conf 02_245 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_3[3] origin:064-gtp-channel-conf 03_245 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_3[4] origin:064-gtp-channel-conf 02_246 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_3[5] origin:064-gtp-channel-conf 03_246 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_3[6] origin:064-gtp-channel-conf 02_247 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_4[0] origin:064-gtp-channel-conf 02_248 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_4[1] origin:064-gtp-channel-conf 03_248 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_4[2] origin:064-gtp-channel-conf 02_249 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_4[3] origin:064-gtp-channel-conf 03_249 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_4[4] origin:064-gtp-channel-conf 02_250 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_4[5] origin:064-gtp-channel-conf 03_250 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_FULL_4[6] origin:064-gtp-channel-conf 02_251 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_0[0] origin:064-gtp-channel-conf 02_252 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_0[1] origin:064-gtp-channel-conf 03_252 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_0[2] origin:064-gtp-channel-conf 02_253 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_0[3] origin:064-gtp-channel-conf 03_253 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_0[4] origin:064-gtp-channel-conf 02_254 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_0[5] origin:064-gtp-channel-conf 03_254 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_0[6] origin:064-gtp-channel-conf 02_255 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_1[0] origin:064-gtp-channel-conf 02_256 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_1[1] origin:064-gtp-channel-conf 03_256 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_1[2] origin:064-gtp-channel-conf 02_257 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_1[3] origin:064-gtp-channel-conf 03_257 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_1[4] origin:064-gtp-channel-conf 02_258 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_1[5] origin:064-gtp-channel-conf 03_258 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_1[6] origin:064-gtp-channel-conf 02_259 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_2[0] origin:064-gtp-channel-conf 02_260 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_2[1] origin:064-gtp-channel-conf 03_260 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_2[2] origin:064-gtp-channel-conf 02_261 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_2[3] origin:064-gtp-channel-conf 03_261 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_2[4] origin:064-gtp-channel-conf 02_262 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_2[5] origin:064-gtp-channel-conf 03_262 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_2[6] origin:064-gtp-channel-conf 02_263 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_3[0] origin:064-gtp-channel-conf 02_264 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_3[1] origin:064-gtp-channel-conf 03_264 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_3[2] origin:064-gtp-channel-conf 02_265 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_3[3] origin:064-gtp-channel-conf 03_265 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_3[4] origin:064-gtp-channel-conf 02_266 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_3[5] origin:064-gtp-channel-conf 03_266 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_3[6] origin:064-gtp-channel-conf 02_267 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_4[0] origin:064-gtp-channel-conf 02_268 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_4[1] origin:064-gtp-channel-conf 03_268 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_4[2] origin:064-gtp-channel-conf 02_269 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_4[3] origin:064-gtp-channel-conf 03_269 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_4[4] origin:064-gtp-channel-conf 02_270 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_4[5] origin:064-gtp-channel-conf 03_270 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_MARGIN_LOW_4[6] origin:064-gtp-channel-conf 02_271 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_PREDRIVER_MODE[0] origin:064-gtp-channel-conf 00_206 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_RXDETECT_CFG[0] origin:064-gtp-channel-conf 02_296 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_RXDETECT_CFG[1] origin:064-gtp-channel-conf 03_296 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_RXDETECT_CFG[2] origin:064-gtp-channel-conf 02_297 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_RXDETECT_CFG[3] origin:064-gtp-channel-conf 03_297 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_RXDETECT_CFG[4] origin:064-gtp-channel-conf 02_298 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_RXDETECT_CFG[5] origin:064-gtp-channel-conf 03_298 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_RXDETECT_CFG[6] origin:064-gtp-channel-conf 02_299 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_RXDETECT_CFG[7] origin:064-gtp-channel-conf 03_299 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_RXDETECT_CFG[8] origin:064-gtp-channel-conf 02_300 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_RXDETECT_CFG[9] origin:064-gtp-channel-conf 03_300 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_RXDETECT_CFG[10] origin:064-gtp-channel-conf 02_301 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_RXDETECT_CFG[11] origin:064-gtp-channel-conf 03_301 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_RXDETECT_CFG[12] origin:064-gtp-channel-conf 02_302 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_RXDETECT_CFG[13] origin:064-gtp-channel-conf 03_302 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_RXDETECT_REF[0] origin:064-gtp-channel-conf 02_292 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_RXDETECT_REF[1] origin:064-gtp-channel-conf 03_292 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_RXDETECT_REF[2] origin:064-gtp-channel-conf 02_293 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_XCLK_SEL.TXUSR origin:064-gtp-channel-conf 03_11 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_CLK25_DIV[0] origin:064-gtp-channel-conf 02_144 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_CLK25_DIV[1] origin:064-gtp-channel-conf 03_144 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_CLK25_DIV[2] origin:064-gtp-channel-conf 02_145 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_CLK25_DIV[3] origin:064-gtp-channel-conf 03_145 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_CLK25_DIV[4] origin:064-gtp-channel-conf 02_146 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_DEEMPH0[0] origin:064-gtp-channel-conf 02_272 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_DEEMPH0[1] origin:064-gtp-channel-conf 03_272 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_DEEMPH0[2] origin:064-gtp-channel-conf 02_273 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_DEEMPH0[3] origin:064-gtp-channel-conf 03_273 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_DEEMPH0[4] origin:064-gtp-channel-conf 02_274 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_DEEMPH0[5] origin:064-gtp-channel-conf 03_274 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_DEEMPH1[0] origin:064-gtp-channel-conf 02_276 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_DEEMPH1[1] origin:064-gtp-channel-conf 03_276 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_DEEMPH1[2] origin:064-gtp-channel-conf 02_277 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_DEEMPH1[3] origin:064-gtp-channel-conf 03_277 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_DEEMPH1[4] origin:064-gtp-channel-conf 02_278 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TX_DEEMPH1[5] origin:064-gtp-channel-conf 03_278 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXBUF_EN origin:064-gtp-channel-conf 00_231 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXBUF_RESET_ON_RATE_CHANGE origin:064-gtp-channel-conf 01_231 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXDLY_CFG[0] origin:064-gtp-channel-conf 02_80 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXDLY_CFG[1] origin:064-gtp-channel-conf 03_80 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXDLY_CFG[2] origin:064-gtp-channel-conf 02_81 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXDLY_CFG[3] origin:064-gtp-channel-conf 03_81 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXDLY_CFG[4] origin:064-gtp-channel-conf 02_82 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXDLY_CFG[5] origin:064-gtp-channel-conf 03_82 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXDLY_CFG[6] origin:064-gtp-channel-conf 02_83 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXDLY_CFG[7] origin:064-gtp-channel-conf 03_83 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXDLY_CFG[8] origin:064-gtp-channel-conf 02_84 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXDLY_CFG[9] origin:064-gtp-channel-conf 03_84 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXDLY_CFG[10] origin:064-gtp-channel-conf 02_85 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXDLY_CFG[11] origin:064-gtp-channel-conf 03_85 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXDLY_CFG[12] origin:064-gtp-channel-conf 02_86 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXDLY_CFG[13] origin:064-gtp-channel-conf 03_86 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXDLY_CFG[14] origin:064-gtp-channel-conf 02_87 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXDLY_CFG[15] origin:064-gtp-channel-conf 03_87 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXDLY_LCFG[0] origin:064-gtp-channel-conf 02_568 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXDLY_LCFG[1] origin:064-gtp-channel-conf 03_568 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXDLY_LCFG[2] origin:064-gtp-channel-conf 02_569 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXDLY_LCFG[3] origin:064-gtp-channel-conf 03_569 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXDLY_LCFG[4] origin:064-gtp-channel-conf 02_570 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXDLY_LCFG[5] origin:064-gtp-channel-conf 03_570 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXDLY_LCFG[6] origin:064-gtp-channel-conf 02_571 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXDLY_LCFG[7] origin:064-gtp-channel-conf 03_571 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXDLY_LCFG[8] origin:064-gtp-channel-conf 02_572 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXDLY_TAP_CFG[0] origin:064-gtp-channel-conf 02_88 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXDLY_TAP_CFG[1] origin:064-gtp-channel-conf 03_88 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXDLY_TAP_CFG[2] origin:064-gtp-channel-conf 02_89 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXDLY_TAP_CFG[3] origin:064-gtp-channel-conf 03_89 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXDLY_TAP_CFG[4] origin:064-gtp-channel-conf 02_90 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXDLY_TAP_CFG[5] origin:064-gtp-channel-conf 03_90 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXDLY_TAP_CFG[6] origin:064-gtp-channel-conf 02_91 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXDLY_TAP_CFG[7] origin:064-gtp-channel-conf 03_91 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXDLY_TAP_CFG[8] origin:064-gtp-channel-conf 02_92 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXDLY_TAP_CFG[9] origin:064-gtp-channel-conf 03_92 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXDLY_TAP_CFG[10] origin:064-gtp-channel-conf 02_93 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXDLY_TAP_CFG[11] origin:064-gtp-channel-conf 03_93 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXDLY_TAP_CFG[12] origin:064-gtp-channel-conf 02_94 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXDLY_TAP_CFG[13] origin:064-gtp-channel-conf 03_94 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXDLY_TAP_CFG[14] origin:064-gtp-channel-conf 02_95 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXDLY_TAP_CFG[15] origin:064-gtp-channel-conf 03_95 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXGEARBOX_EN origin:064-gtp-channel-conf 01_226 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXOOB_CFG[0] origin:064-gtp-channel-conf 03_20 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXOUT_DIV[0] origin:064-gtp-channel-conf 02_386 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXOUT_DIV[1] origin:064-gtp-channel-conf 03_386 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPCSRESET_TIME[0] origin:064-gtp-channel-conf 01_130 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPCSRESET_TIME[1] origin:064-gtp-channel-conf 00_131 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPCSRESET_TIME[2] origin:064-gtp-channel-conf 01_131 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPCSRESET_TIME[3] origin:064-gtp-channel-conf 00_132 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPCSRESET_TIME[4] origin:064-gtp-channel-conf 01_132 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPH_CFG[0] origin:064-gtp-channel-conf 02_96 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPH_CFG[1] origin:064-gtp-channel-conf 03_96 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPH_CFG[2] origin:064-gtp-channel-conf 02_97 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPH_CFG[3] origin:064-gtp-channel-conf 03_97 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPH_CFG[4] origin:064-gtp-channel-conf 02_98 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPH_CFG[5] origin:064-gtp-channel-conf 03_98 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPH_CFG[6] origin:064-gtp-channel-conf 02_99 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPH_CFG[7] origin:064-gtp-channel-conf 03_99 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPH_CFG[8] origin:064-gtp-channel-conf 02_100 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPH_CFG[9] origin:064-gtp-channel-conf 03_100 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPH_CFG[10] origin:064-gtp-channel-conf 02_101 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPH_CFG[11] origin:064-gtp-channel-conf 03_101 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPH_CFG[12] origin:064-gtp-channel-conf 02_102 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPH_CFG[13] origin:064-gtp-channel-conf 03_102 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPH_CFG[14] origin:064-gtp-channel-conf 02_103 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPH_CFG[15] origin:064-gtp-channel-conf 03_103 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPH_MONITOR_SEL[0] origin:064-gtp-channel-conf 02_108 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPH_MONITOR_SEL[1] origin:064-gtp-channel-conf 03_108 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPH_MONITOR_SEL[2] origin:064-gtp-channel-conf 02_109 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPH_MONITOR_SEL[3] origin:064-gtp-channel-conf 03_109 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPH_MONITOR_SEL[4] origin:064-gtp-channel-conf 02_110 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[0] origin:064-gtp-channel-conf 02_64 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[1] origin:064-gtp-channel-conf 03_64 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[2] origin:064-gtp-channel-conf 02_65 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[3] origin:064-gtp-channel-conf 03_65 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[4] origin:064-gtp-channel-conf 02_66 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[5] origin:064-gtp-channel-conf 03_66 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[6] origin:064-gtp-channel-conf 02_67 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[7] origin:064-gtp-channel-conf 03_67 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[8] origin:064-gtp-channel-conf 02_68 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[9] origin:064-gtp-channel-conf 03_68 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[10] origin:064-gtp-channel-conf 02_69 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[11] origin:064-gtp-channel-conf 03_69 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[12] origin:064-gtp-channel-conf 02_70 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[13] origin:064-gtp-channel-conf 03_70 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[14] origin:064-gtp-channel-conf 02_71 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[15] origin:064-gtp-channel-conf 03_71 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[16] origin:064-gtp-channel-conf 02_72 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[17] origin:064-gtp-channel-conf 03_72 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[18] origin:064-gtp-channel-conf 02_73 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[19] origin:064-gtp-channel-conf 03_73 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[20] origin:064-gtp-channel-conf 02_74 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[21] origin:064-gtp-channel-conf 03_74 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[22] origin:064-gtp-channel-conf 02_75 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPHDLY_CFG[23] origin:064-gtp-channel-conf 03_75 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPI_GREY_SEL[0] origin:064-gtp-channel-conf 03_498 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPI_INVSTROBE_SEL[0] origin:064-gtp-channel-conf 02_498 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPI_PPM_CFG[0] origin:064-gtp-channel-conf 02_488 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPI_PPM_CFG[1] origin:064-gtp-channel-conf 03_488 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPI_PPM_CFG[2] origin:064-gtp-channel-conf 02_489 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPI_PPM_CFG[3] origin:064-gtp-channel-conf 03_489 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPI_PPM_CFG[4] origin:064-gtp-channel-conf 02_490 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPI_PPM_CFG[5] origin:064-gtp-channel-conf 03_490 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPI_PPM_CFG[6] origin:064-gtp-channel-conf 02_491 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPI_PPM_CFG[7] origin:064-gtp-channel-conf 03_491 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPI_PPMCLK_SEL.TXUSRCLK2 origin:064-gtp-channel-conf 03_497 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPI_SYNFREQ_PPM[0] origin:064-gtp-channel-conf 02_496 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPI_SYNFREQ_PPM[1] origin:064-gtp-channel-conf 03_496 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPI_SYNFREQ_PPM[2] origin:064-gtp-channel-conf 02_497 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPI_CFG0[0] origin:064-gtp-channel-conf 02_40 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPI_CFG0[1] origin:064-gtp-channel-conf 03_40 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPI_CFG1[0] origin:064-gtp-channel-conf 02_41 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPI_CFG1[1] origin:064-gtp-channel-conf 03_41 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPI_CFG2[0] origin:064-gtp-channel-conf 02_42 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPI_CFG2[1] origin:064-gtp-channel-conf 03_42 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPI_CFG3[0] origin:064-gtp-channel-conf 02_43 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPI_CFG4[0] origin:064-gtp-channel-conf 03_43 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPI_CFG5[0] origin:064-gtp-channel-conf 02_44 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPI_CFG5[1] origin:064-gtp-channel-conf 03_44 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPI_CFG5[2] origin:064-gtp-channel-conf 02_45 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPMARESET_TIME[0] origin:064-gtp-channel-conf 00_128 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPMARESET_TIME[1] origin:064-gtp-channel-conf 01_128 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPMARESET_TIME[2] origin:064-gtp-channel-conf 00_129 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPMARESET_TIME[3] origin:064-gtp-channel-conf 01_129 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXPMARESET_TIME[4] origin:064-gtp-channel-conf 00_130 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXSYNC_MULTILANE[0] origin:064-gtp-channel-conf 01_133 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXSYNC_OVRD[0] origin:064-gtp-channel-conf 00_135 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.TXSYNC_SKIP_DA[0] origin:064-gtp-channel-conf 00_134 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.UCODEER_CLR[0] origin:064-gtp-channel-conf 01_00 +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL.USE_PCS_CLK_PHASE_SEL[0] origin:064-gtp-channel-conf 02_463 diff --git a/artix7/segbits_gtp_channel_3_mid_right.db b/artix7/segbits_gtp_channel_3_mid_right.db index 4e8db78..d5f19af 100644 --- a/artix7/segbits_gtp_channel_3_mid_right.db +++ b/artix7/segbits_gtp_channel_3_mid_right.db @@ -1,1627 +1,1627 @@ -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ACJTAG_DEBUG_MODE[0] 00_07 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ACJTAG_MODE[0] 01_06 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ACJTAG_RESET[0] 01_07 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ADAPT_CFG0[0] 02_464 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ADAPT_CFG0[1] 03_464 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ADAPT_CFG0[2] 02_465 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ADAPT_CFG0[3] 03_465 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ADAPT_CFG0[4] 02_466 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ADAPT_CFG0[5] 03_466 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ADAPT_CFG0[6] 02_467 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ADAPT_CFG0[7] 03_467 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ADAPT_CFG0[8] 02_468 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ADAPT_CFG0[9] 03_468 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ADAPT_CFG0[10] 02_469 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ADAPT_CFG0[11] 03_469 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ADAPT_CFG0[12] 02_470 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ADAPT_CFG0[13] 03_470 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ADAPT_CFG0[14] 02_471 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ADAPT_CFG0[15] 03_471 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ADAPT_CFG0[16] 02_472 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ADAPT_CFG0[17] 03_472 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ADAPT_CFG0[18] 02_473 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ADAPT_CFG0[19] 03_473 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ALIGN_COMMA_DOUBLE 00_522 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ALIGN_COMMA_ENABLE[0] 00_496 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ALIGN_COMMA_ENABLE[1] 01_496 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ALIGN_COMMA_ENABLE[2] 00_497 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ALIGN_COMMA_ENABLE[3] 01_497 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ALIGN_COMMA_ENABLE[4] 00_498 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ALIGN_COMMA_ENABLE[5] 01_498 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ALIGN_COMMA_ENABLE[6] 00_499 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ALIGN_COMMA_ENABLE[7] 01_499 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ALIGN_COMMA_ENABLE[8] 00_500 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ALIGN_COMMA_ENABLE[9] 01_500 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ALIGN_COMMA_WORD[0] 01_526 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ALIGN_COMMA_WORD[1] 00_527 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ALIGN_MCOMMA_DET 00_523 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ALIGN_MCOMMA_VALUE[0] 00_504 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ALIGN_MCOMMA_VALUE[1] 01_504 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ALIGN_MCOMMA_VALUE[2] 00_505 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ALIGN_MCOMMA_VALUE[3] 01_505 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ALIGN_MCOMMA_VALUE[4] 00_506 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ALIGN_MCOMMA_VALUE[5] 01_506 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ALIGN_MCOMMA_VALUE[6] 00_507 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ALIGN_MCOMMA_VALUE[7] 01_507 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ALIGN_MCOMMA_VALUE[8] 00_508 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ALIGN_MCOMMA_VALUE[9] 01_508 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ALIGN_PCOMMA_DET 01_523 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ALIGN_PCOMMA_VALUE[0] 00_512 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ALIGN_PCOMMA_VALUE[1] 01_512 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ALIGN_PCOMMA_VALUE[2] 00_513 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ALIGN_PCOMMA_VALUE[3] 01_513 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ALIGN_PCOMMA_VALUE[4] 00_514 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ALIGN_PCOMMA_VALUE[5] 01_514 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ALIGN_PCOMMA_VALUE[6] 00_515 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ALIGN_PCOMMA_VALUE[7] 01_515 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ALIGN_PCOMMA_VALUE[8] 00_516 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ALIGN_PCOMMA_VALUE[9] 01_516 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CBCC_DATA_SOURCE_SEL.DECODED 01_661 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CFOK_CFG[0] 02_392 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CFOK_CFG[1] 03_392 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CFOK_CFG[2] 02_393 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CFOK_CFG[3] 03_393 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CFOK_CFG[4] 02_394 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CFOK_CFG[5] 03_394 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CFOK_CFG[6] 02_395 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CFOK_CFG[7] 03_395 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CFOK_CFG[8] 02_396 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CFOK_CFG[9] 03_396 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CFOK_CFG[10] 02_397 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CFOK_CFG[11] 03_397 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CFOK_CFG[12] 02_398 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CFOK_CFG[13] 03_398 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CFOK_CFG[14] 02_399 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CFOK_CFG[15] 03_399 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CFOK_CFG[16] 02_400 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CFOK_CFG[17] 03_400 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CFOK_CFG[18] 02_401 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CFOK_CFG[19] 03_401 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CFOK_CFG[20] 02_402 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CFOK_CFG[21] 03_402 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CFOK_CFG[22] 02_403 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CFOK_CFG[23] 03_403 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CFOK_CFG[24] 02_404 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CFOK_CFG[25] 03_404 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CFOK_CFG[26] 02_405 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CFOK_CFG[27] 03_405 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CFOK_CFG[28] 02_406 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CFOK_CFG[29] 03_406 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CFOK_CFG[30] 02_407 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CFOK_CFG[31] 03_407 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CFOK_CFG[32] 02_408 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CFOK_CFG[33] 03_408 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CFOK_CFG[34] 02_409 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CFOK_CFG[35] 03_409 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CFOK_CFG[36] 02_410 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CFOK_CFG[37] 03_410 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CFOK_CFG[38] 02_411 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CFOK_CFG[39] 03_411 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CFOK_CFG[40] 02_412 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CFOK_CFG[41] 03_412 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CFOK_CFG[42] 02_413 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CFOK_CFG2[0] 02_459 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CFOK_CFG2[1] 03_459 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CFOK_CFG2[2] 02_460 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CFOK_CFG2[3] 03_460 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CFOK_CFG2[4] 02_461 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CFOK_CFG2[5] 03_461 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CFOK_CFG2[6] 02_462 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CFOK_CFG3[0] 02_416 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CFOK_CFG3[1] 03_416 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CFOK_CFG3[2] 02_417 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CFOK_CFG3[3] 03_417 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CFOK_CFG3[4] 02_418 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CFOK_CFG3[5] 03_418 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CFOK_CFG3[6] 02_419 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CFOK_CFG4[0] 03_438 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CFOK_CFG5[0] 02_429 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CFOK_CFG5[1] 03_429 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CFOK_CFG6[0] 03_436 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CFOK_CFG6[1] 02_437 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CFOK_CFG6[2] 03_437 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CFOK_CFG6[3] 02_438 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_KEEP_ALIGN 01_631 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_MAX_SKEW[0] 00_670 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_MAX_SKEW[1] 01_670 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_MAX_SKEW[2] 00_671 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_MAX_SKEW[3] 01_671 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_1[0] 00_608 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_1[1] 01_608 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_1[2] 00_609 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_1[3] 01_609 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_1[4] 00_610 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_1[5] 01_610 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_1[6] 00_611 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_1[7] 01_611 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_1[8] 00_612 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_1[9] 01_612 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_2[0] 00_616 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_2[1] 01_616 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_2[2] 00_617 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_2[3] 01_617 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_2[4] 00_618 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_2[5] 01_618 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_2[6] 00_619 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_2[7] 01_619 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_2[8] 00_620 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_2[9] 01_620 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_3[0] 00_624 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_3[1] 01_624 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_3[2] 00_625 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_3[3] 01_625 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_3[4] 00_626 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_3[5] 01_626 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_3[6] 00_627 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_3[7] 01_627 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_3[8] 00_628 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_3[9] 01_628 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_4[0] 00_632 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_4[1] 01_632 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_4[2] 00_633 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_4[3] 01_633 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_4[4] 00_634 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_4[5] 01_634 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_4[6] 00_635 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_4[7] 01_635 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_4[8] 00_636 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_4[9] 01_636 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_ENABLE[0] 00_614 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_ENABLE[1] 01_614 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_ENABLE[2] 00_615 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_ENABLE[3] 01_615 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_1[0] 00_640 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_1[1] 01_640 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_1[2] 00_641 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_1[3] 01_641 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_1[4] 00_642 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_1[5] 01_642 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_1[6] 00_643 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_1[7] 01_643 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_1[8] 00_644 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_1[9] 01_644 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_2[0] 00_648 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_2[1] 01_648 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_2[2] 00_649 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_2[3] 01_649 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_2[4] 00_650 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_2[5] 01_650 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_2[6] 00_651 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_2[7] 01_651 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_2[8] 00_652 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_2[9] 01_652 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_3[0] 00_656 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_3[1] 01_656 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_3[2] 00_657 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_3[3] 01_657 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_3[4] 00_658 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_3[5] 01_658 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_3[6] 00_659 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_3[7] 01_659 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_3[8] 00_660 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_3[9] 01_660 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_4[0] 00_664 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_4[1] 01_664 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_4[2] 00_665 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_4[3] 01_665 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_4[4] 00_666 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_4[5] 01_666 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_4[6] 00_667 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_4[7] 01_667 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_4[8] 00_668 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_4[9] 01_668 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_ENABLE[0] 00_646 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_ENABLE[1] 01_646 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_ENABLE[2] 00_647 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_ENABLE[3] 01_647 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_USE 01_645 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_LEN[0] 00_623 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_LEN[1] 01_623 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COMMON_SWING[0] 03_311 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_KEEP_IDLE 00_591 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_MAX_LAT[0] 00_557 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_MAX_LAT[1] 01_557 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_MAX_LAT[2] 00_558 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_MAX_LAT[3] 01_558 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_MAX_LAT[4] 00_559 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_MAX_LAT[5] 01_559 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_MIN_LAT[0] 00_565 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_MIN_LAT[1] 01_565 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_MIN_LAT[2] 00_566 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_MIN_LAT[3] 01_566 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_MIN_LAT[4] 00_567 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_MIN_LAT[5] 01_567 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_PRECEDENCE 00_590 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_REPEAT_WAIT[0] 00_573 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_REPEAT_WAIT[1] 01_573 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_REPEAT_WAIT[2] 00_574 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_REPEAT_WAIT[3] 01_574 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_REPEAT_WAIT[4] 00_575 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_1[0] 00_544 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_1[1] 01_544 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_1[2] 00_545 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_1[3] 01_545 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_1[4] 00_546 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_1[5] 01_546 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_1[6] 00_547 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_1[7] 01_547 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_1[8] 00_548 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_1[9] 01_548 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_2[0] 00_552 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_2[1] 01_552 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_2[2] 00_553 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_2[3] 01_553 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_2[4] 00_554 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_2[5] 01_554 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_2[6] 00_555 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_2[7] 01_555 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_2[8] 00_556 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_2[9] 01_556 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_3[0] 00_560 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_3[1] 01_560 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_3[2] 00_561 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_3[3] 01_561 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_3[4] 00_562 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_3[5] 01_562 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_3[6] 00_563 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_3[7] 01_563 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_3[8] 00_564 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_3[9] 01_564 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_4[0] 00_568 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_4[1] 01_568 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_4[2] 00_569 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_4[3] 01_569 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_4[4] 00_570 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_4[5] 01_570 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_4[6] 00_571 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_4[7] 01_571 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_4[8] 00_572 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_4[9] 01_572 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_ENABLE[0] 00_549 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_ENABLE[1] 01_549 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_ENABLE[2] 00_550 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_ENABLE[3] 01_550 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_1[0] 00_576 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_1[1] 01_576 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_1[2] 00_577 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_1[3] 01_577 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_1[4] 00_578 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_1[5] 01_578 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_1[6] 00_579 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_1[7] 01_579 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_1[8] 00_580 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_1[9] 01_580 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_2[0] 00_584 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_2[1] 01_584 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_2[2] 00_585 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_2[3] 01_585 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_2[4] 00_586 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_2[5] 01_586 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_2[6] 00_587 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_2[7] 01_587 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_2[8] 00_588 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_2[9] 01_588 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_3[0] 00_592 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_3[1] 01_592 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_3[2] 00_593 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_3[3] 01_593 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_3[4] 00_594 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_3[5] 01_594 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_3[6] 00_595 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_3[7] 01_595 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_3[8] 00_596 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_3[9] 01_596 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_4[0] 00_600 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_4[1] 01_600 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_4[2] 00_601 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_4[3] 01_601 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_4[4] 00_602 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_4[5] 01_602 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_4[6] 00_603 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_4[7] 01_603 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_4[8] 00_604 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_4[9] 01_604 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_ENABLE[0] 00_581 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_ENABLE[1] 01_581 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_ENABLE[2] 00_582 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_ENABLE[3] 01_582 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_USE 00_583 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_LEN[0] 00_589 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_LEN[1] 01_589 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_CORRECT_USE 00_551 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.DEC_MCOMMA_DETECT 01_494 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.DEC_PCOMMA_DETECT 00_495 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.DEC_VALID_COMMA_ONLY 00_494 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.DMONITOR_CFG[0] 02_368 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.DMONITOR_CFG[1] 03_368 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.DMONITOR_CFG[2] 02_369 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.DMONITOR_CFG[3] 03_369 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.DMONITOR_CFG[4] 02_370 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.DMONITOR_CFG[5] 03_370 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.DMONITOR_CFG[6] 02_371 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.DMONITOR_CFG[7] 03_371 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.DMONITOR_CFG[8] 02_372 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.DMONITOR_CFG[9] 03_372 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.DMONITOR_CFG[10] 02_373 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.DMONITOR_CFG[11] 03_373 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.DMONITOR_CFG[12] 02_374 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.DMONITOR_CFG[13] 03_374 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.DMONITOR_CFG[14] 02_375 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.DMONITOR_CFG[15] 03_375 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.DMONITOR_CFG[16] 02_376 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.DMONITOR_CFG[17] 03_376 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.DMONITOR_CFG[18] 02_377 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.DMONITOR_CFG[19] 03_377 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.DMONITOR_CFG[20] 02_378 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.DMONITOR_CFG[21] 03_378 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.DMONITOR_CFG[22] 02_379 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.DMONITOR_CFG[23] 03_379 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_CLK_PHASE_SEL[0] 03_463 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_CONTROL[0] 00_488 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_CONTROL[1] 01_488 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_CONTROL[2] 00_489 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_CONTROL[3] 01_489 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_CONTROL[4] 00_490 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_CONTROL[5] 01_490 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_ERRDET_EN 01_492 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_EYE_SCAN_EN 00_492 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_HORZ_OFFSET[0] 00_480 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_HORZ_OFFSET[1] 01_480 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_HORZ_OFFSET[2] 00_481 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_HORZ_OFFSET[3] 01_481 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_HORZ_OFFSET[4] 00_482 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_HORZ_OFFSET[5] 01_482 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_HORZ_OFFSET[6] 00_483 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_HORZ_OFFSET[7] 01_483 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_HORZ_OFFSET[8] 00_484 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_HORZ_OFFSET[9] 01_484 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_HORZ_OFFSET[10] 00_485 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_HORZ_OFFSET[11] 01_485 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_PMA_CFG[0] 02_624 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_PMA_CFG[1] 03_624 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_PMA_CFG[2] 02_625 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_PMA_CFG[3] 03_625 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_PMA_CFG[4] 02_626 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_PMA_CFG[5] 03_626 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_PMA_CFG[6] 02_627 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_PMA_CFG[7] 03_627 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_PMA_CFG[8] 02_628 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_PMA_CFG[9] 03_628 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_PRESCALE[0] 01_477 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_PRESCALE[1] 00_478 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_PRESCALE[2] 01_478 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_PRESCALE[3] 00_479 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_PRESCALE[4] 01_479 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[0] 00_392 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[1] 01_392 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[2] 00_393 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[3] 01_393 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[4] 00_394 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[5] 01_394 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[6] 00_395 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[7] 01_395 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[8] 00_396 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[9] 01_396 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[10] 00_397 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[11] 01_397 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[12] 00_398 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[13] 01_398 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[14] 00_399 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[15] 01_399 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[16] 00_400 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[17] 01_400 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[18] 00_401 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[19] 01_401 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[20] 00_402 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[21] 01_402 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[22] 00_403 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[23] 01_403 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[24] 00_404 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[25] 01_404 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[26] 00_405 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[27] 01_405 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[28] 00_406 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[29] 01_406 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[30] 00_407 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[31] 01_407 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[32] 00_408 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[33] 01_408 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[34] 00_409 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[35] 01_409 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[36] 00_410 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[37] 01_410 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[38] 00_411 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[39] 01_411 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[40] 00_412 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[41] 01_412 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[42] 00_413 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[43] 01_413 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[44] 00_414 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[45] 01_414 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[46] 00_415 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[47] 01_415 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[48] 00_416 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[49] 01_416 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[50] 00_417 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[51] 01_417 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[52] 00_418 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[53] 01_418 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[54] 00_419 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[55] 01_419 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[56] 00_420 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[57] 01_420 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[58] 00_421 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[59] 01_421 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[60] 00_422 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[61] 01_422 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[62] 00_423 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[63] 01_423 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[64] 00_424 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[65] 01_424 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[66] 00_425 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[67] 01_425 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[68] 00_426 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[69] 01_426 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[70] 00_427 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[71] 01_427 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[72] 00_428 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[73] 01_428 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[74] 00_429 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[75] 01_429 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[76] 00_430 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[77] 01_430 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[78] 00_431 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[79] 01_431 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[0] 00_352 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[1] 01_352 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[2] 00_353 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[3] 01_353 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[4] 00_354 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[5] 01_354 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[6] 00_355 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[7] 01_355 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[8] 00_356 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[9] 01_356 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[10] 00_357 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[11] 01_357 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[12] 00_358 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[13] 01_358 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[14] 00_359 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[15] 01_359 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[16] 00_360 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[17] 01_360 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[18] 00_361 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[19] 01_361 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[20] 00_362 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[21] 01_362 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[22] 00_363 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[23] 01_363 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[24] 00_364 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[25] 01_364 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[26] 00_365 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[27] 01_365 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[28] 00_366 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[29] 01_366 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[30] 00_367 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[31] 01_367 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[32] 00_368 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[33] 01_368 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[34] 00_369 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[35] 01_369 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[36] 00_370 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[37] 01_370 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[38] 00_371 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[39] 01_371 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[40] 00_372 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[41] 01_372 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[42] 00_373 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[43] 01_373 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[44] 00_374 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[45] 01_374 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[46] 00_375 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[47] 01_375 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[48] 00_376 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[49] 01_376 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[50] 00_377 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[51] 01_377 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[52] 00_378 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[53] 01_378 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[54] 00_379 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[55] 01_379 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[56] 00_380 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[57] 01_380 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[58] 00_381 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[59] 01_381 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[60] 00_382 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[61] 01_382 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[62] 00_383 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[63] 01_383 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[64] 00_384 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[65] 01_384 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[66] 00_385 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[67] 01_385 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[68] 00_386 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[69] 01_386 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[70] 00_387 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[71] 01_387 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[72] 00_388 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[73] 01_388 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[74] 00_389 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[75] 01_389 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[76] 00_390 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[77] 01_390 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[78] 00_391 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[79] 01_391 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[0] 00_432 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[1] 01_432 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[2] 00_433 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[3] 01_433 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[4] 00_434 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[5] 01_434 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[6] 00_435 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[7] 01_435 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[8] 00_436 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[9] 01_436 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[10] 00_437 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[11] 01_437 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[12] 00_438 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[13] 01_438 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[14] 00_439 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[15] 01_439 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[16] 00_440 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[17] 01_440 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[18] 00_441 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[19] 01_441 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[20] 00_442 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[21] 01_442 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[22] 00_443 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[23] 01_443 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[24] 00_444 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[25] 01_444 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[26] 00_445 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[27] 01_445 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[28] 00_446 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[29] 01_446 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[30] 00_447 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[31] 01_447 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[32] 00_448 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[33] 01_448 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[34] 00_449 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[35] 01_449 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[36] 00_450 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[37] 01_450 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[38] 00_451 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[39] 01_451 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[40] 00_452 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[41] 01_452 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[42] 00_453 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[43] 01_453 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[44] 00_454 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[45] 01_454 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[46] 00_455 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[47] 01_455 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[48] 00_456 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[49] 01_456 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[50] 00_457 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[51] 01_457 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[52] 00_458 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[53] 01_458 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[54] 00_459 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[55] 01_459 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[56] 00_460 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[57] 01_460 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[58] 00_461 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[59] 01_461 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[60] 00_462 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[61] 01_462 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[62] 00_463 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[63] 01_463 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[64] 00_464 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[65] 01_464 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[66] 00_465 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[67] 01_465 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[68] 00_466 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[69] 01_466 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[70] 00_467 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[71] 01_467 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[72] 00_468 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[73] 01_468 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[74] 00_469 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[75] 01_469 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[76] 00_470 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[77] 01_470 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[78] 00_471 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[79] 01_471 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_VERT_OFFSET[0] 00_472 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_VERT_OFFSET[1] 01_472 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_VERT_OFFSET[2] 00_473 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_VERT_OFFSET[3] 01_473 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_VERT_OFFSET[4] 00_474 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_VERT_OFFSET[5] 01_474 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_VERT_OFFSET[6] 00_475 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_VERT_OFFSET[7] 01_475 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_VERT_OFFSET[8] 00_476 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.FTS_DESKEW_SEQ_ENABLE[0] 00_662 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.FTS_DESKEW_SEQ_ENABLE[1] 01_662 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.FTS_DESKEW_SEQ_ENABLE[2] 00_663 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.FTS_DESKEW_SEQ_ENABLE[3] 01_663 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.FTS_LANE_DESKEW_CFG[0] 00_654 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.FTS_LANE_DESKEW_CFG[1] 01_654 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.FTS_LANE_DESKEW_CFG[2] 00_655 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.FTS_LANE_DESKEW_CFG[3] 01_655 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.FTS_LANE_DESKEW_EN 01_653 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.GEARBOX_MODE[0] 00_224 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.GEARBOX_MODE[1] 01_224 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.GEARBOX_MODE[2] 00_225 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.IN_USE 00_00 00_01 00_47 00_52 00_53 00_65 01_01 01_47 02_129 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.LOOPBACK_CFG[0] 02_20 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.OUTREFCLK_SEL_INV[0] 00_149 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.OUTREFCLK_SEL_INV[1] 01_149 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PCS_PCIE_EN 00_216 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[0] 02_184 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[1] 03_184 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[2] 02_185 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[3] 03_185 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[4] 02_186 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[5] 03_186 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[6] 02_187 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[7] 03_187 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[8] 02_188 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[9] 03_188 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[10] 02_189 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[11] 03_189 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[12] 02_190 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[13] 03_190 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[14] 02_191 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[15] 03_191 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[16] 02_192 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[17] 03_192 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[18] 02_193 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[19] 03_193 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[20] 02_194 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[21] 03_194 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[22] 02_195 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[23] 03_195 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[24] 02_196 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[25] 03_196 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[26] 02_197 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[27] 03_197 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[28] 02_198 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[29] 03_198 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[30] 02_199 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[31] 03_199 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[32] 02_200 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[33] 03_200 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[34] 02_201 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[35] 03_201 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[36] 02_202 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[37] 03_202 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[38] 02_203 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[39] 03_203 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[40] 02_204 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[41] 03_204 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[42] 02_205 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[43] 03_205 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[44] 02_206 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[45] 03_206 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[46] 02_207 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[47] 03_207 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PD_TRANS_TIME_FROM_P2[0] 01_216 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PD_TRANS_TIME_FROM_P2[1] 00_217 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PD_TRANS_TIME_FROM_P2[2] 01_217 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PD_TRANS_TIME_FROM_P2[3] 00_218 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PD_TRANS_TIME_FROM_P2[4] 01_218 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PD_TRANS_TIME_FROM_P2[5] 00_219 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PD_TRANS_TIME_FROM_P2[6] 01_219 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PD_TRANS_TIME_FROM_P2[7] 00_220 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PD_TRANS_TIME_FROM_P2[8] 01_220 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PD_TRANS_TIME_FROM_P2[9] 00_221 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PD_TRANS_TIME_FROM_P2[10] 01_221 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PD_TRANS_TIME_FROM_P2[11] 00_222 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PD_TRANS_TIME_NONE_P2[0] 00_208 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PD_TRANS_TIME_NONE_P2[1] 01_208 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PD_TRANS_TIME_NONE_P2[2] 00_209 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PD_TRANS_TIME_NONE_P2[3] 01_209 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PD_TRANS_TIME_NONE_P2[4] 00_210 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PD_TRANS_TIME_NONE_P2[5] 01_210 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PD_TRANS_TIME_NONE_P2[6] 00_211 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PD_TRANS_TIME_NONE_P2[7] 01_211 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PD_TRANS_TIME_TO_P2[0] 00_212 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PD_TRANS_TIME_TO_P2[1] 01_212 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PD_TRANS_TIME_TO_P2[2] 00_213 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PD_TRANS_TIME_TO_P2[3] 01_213 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PD_TRANS_TIME_TO_P2[4] 00_214 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PD_TRANS_TIME_TO_P2[5] 01_214 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PD_TRANS_TIME_TO_P2[6] 00_215 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PD_TRANS_TIME_TO_P2[7] 01_215 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PMA_LOOPBACK_CFG[0] 01_207 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PMA_RSV[0] 02_520 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PMA_RSV[1] 03_520 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PMA_RSV[2] 02_521 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PMA_RSV[3] 03_521 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PMA_RSV[4] 02_522 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PMA_RSV[5] 03_522 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PMA_RSV[6] 02_523 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PMA_RSV[7] 03_523 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PMA_RSV[8] 02_524 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PMA_RSV[9] 03_524 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PMA_RSV[10] 02_525 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PMA_RSV[11] 03_525 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PMA_RSV[12] 02_526 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PMA_RSV[13] 03_526 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PMA_RSV[14] 02_527 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PMA_RSV[15] 03_527 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PMA_RSV[16] 02_528 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PMA_RSV[17] 03_528 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PMA_RSV[18] 02_529 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PMA_RSV[19] 03_529 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PMA_RSV[20] 02_530 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PMA_RSV[21] 03_530 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PMA_RSV[22] 02_531 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PMA_RSV[23] 03_531 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PMA_RSV[24] 02_532 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PMA_RSV[25] 03_532 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PMA_RSV[26] 02_533 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PMA_RSV[27] 03_533 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PMA_RSV[28] 02_534 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PMA_RSV[29] 03_534 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PMA_RSV[30] 02_535 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PMA_RSV[31] 03_535 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PMA_RSV2[0] 02_336 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PMA_RSV2[1] 03_336 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PMA_RSV2[2] 02_337 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PMA_RSV2[3] 03_337 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PMA_RSV2[4] 02_338 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PMA_RSV2[5] 03_338 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PMA_RSV2[6] 02_339 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PMA_RSV2[7] 03_339 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PMA_RSV2[8] 02_340 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PMA_RSV2[9] 03_340 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PMA_RSV2[10] 02_341 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PMA_RSV2[11] 03_341 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PMA_RSV2[12] 02_342 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PMA_RSV2[13] 03_342 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PMA_RSV2[14] 02_343 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PMA_RSV2[15] 03_343 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PMA_RSV2[16] 02_344 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PMA_RSV2[17] 03_344 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PMA_RSV2[18] 02_345 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PMA_RSV2[19] 03_345 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PMA_RSV2[20] 02_346 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PMA_RSV2[21] 03_346 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PMA_RSV2[22] 02_347 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PMA_RSV2[23] 03_347 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PMA_RSV2[24] 02_348 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PMA_RSV2[25] 03_348 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PMA_RSV2[26] 02_349 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PMA_RSV2[27] 03_349 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PMA_RSV2[28] 02_350 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PMA_RSV2[29] 03_350 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PMA_RSV2[30] 02_351 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PMA_RSV2[31] 03_351 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PMA_RSV3[0] 02_288 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PMA_RSV3[1] 03_288 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PMA_RSV4[0] 02_156 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PMA_RSV4[1] 03_156 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PMA_RSV4[2] 02_157 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PMA_RSV4[3] 03_157 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PMA_RSV5[0] 03_159 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PMA_RSV6[0] 02_303 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PMA_RSV7[0] 03_303 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_BIAS_CFG[0] 02_112 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_BIAS_CFG[1] 03_112 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_BIAS_CFG[2] 02_113 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_BIAS_CFG[3] 03_113 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_BIAS_CFG[4] 02_114 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_BIAS_CFG[5] 03_114 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_BIAS_CFG[6] 02_115 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_BIAS_CFG[7] 03_115 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_BIAS_CFG[8] 02_116 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_BIAS_CFG[9] 03_116 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_BIAS_CFG[10] 02_117 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_BIAS_CFG[11] 03_117 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_BIAS_CFG[12] 02_118 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_BIAS_CFG[13] 03_118 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_BIAS_CFG[14] 02_119 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_BIAS_CFG[15] 03_119 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_BUFFER_CFG[0] 02_536 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_BUFFER_CFG[1] 03_536 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_BUFFER_CFG[2] 02_537 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_BUFFER_CFG[3] 03_537 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_BUFFER_CFG[4] 02_538 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_BUFFER_CFG[5] 03_538 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_CLKMUX_EN[0] 02_128 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_CM_SEL[0] 00_138 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_CM_SEL[1] 01_138 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_CM_TRIM[0] 02_304 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_CM_TRIM[1] 03_304 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_CM_TRIM[2] 02_305 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_CM_TRIM[3] 03_305 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_DATA_WIDTH[0] 01_141 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_DATA_WIDTH[1] 00_142 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_DATA_WIDTH[2] 01_142 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_DDI_SEL[0] 00_696 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_DDI_SEL[1] 01_696 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_DDI_SEL[2] 00_697 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_DDI_SEL[3] 01_697 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_DDI_SEL[4] 00_698 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_DDI_SEL[5] 01_698 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_DEBUG_CFG[0] 02_616 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_DEBUG_CFG[1] 03_616 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_DEBUG_CFG[2] 02_617 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_DEBUG_CFG[3] 03_617 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_DEBUG_CFG[4] 02_618 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_DEBUG_CFG[5] 03_618 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_DEBUG_CFG[6] 02_619 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_DEBUG_CFG[7] 03_619 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_DEBUG_CFG[8] 02_620 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_DEBUG_CFG[9] 03_620 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_DEBUG_CFG[10] 02_621 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_DEBUG_CFG[11] 03_621 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_DEBUG_CFG[12] 02_622 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_DEBUG_CFG[13] 03_622 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_DEFER_RESET_BUF_EN 02_552 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_DISPERR_SEQ_MATCH 01_495 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_OS_CFG[0] 00_288 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_OS_CFG[1] 01_288 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_OS_CFG[2] 00_289 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_OS_CFG[3] 01_289 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_OS_CFG[4] 00_290 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_OS_CFG[5] 01_290 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_OS_CFG[6] 00_291 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_OS_CFG[7] 01_291 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_OS_CFG[8] 00_292 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_OS_CFG[9] 01_292 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_OS_CFG[10] 00_293 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_OS_CFG[11] 01_293 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_OS_CFG[12] 00_294 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_SIG_VALID_DLY[0] 00_524 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_SIG_VALID_DLY[1] 01_524 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_SIG_VALID_DLY[2] 00_525 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_SIG_VALID_DLY[3] 01_525 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_SIG_VALID_DLY[4] 00_526 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_XCLK_SEL.RXUSR 00_143 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_CLK25_DIV[0] 00_139 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_CLK25_DIV[1] 01_139 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_CLK25_DIV[2] 00_140 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_CLK25_DIV[3] 01_140 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_CLK25_DIV[4] 00_141 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXBUF_ADDR_MODE.FAST 03_555 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXBUF_EIDLE_HI_CNT[0] 02_558 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXBUF_EIDLE_HI_CNT[1] 03_558 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXBUF_EIDLE_HI_CNT[2] 02_559 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXBUF_EIDLE_HI_CNT[3] 03_559 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXBUF_EIDLE_LO_CNT[0] 02_556 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXBUF_EIDLE_LO_CNT[1] 03_556 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXBUF_EIDLE_LO_CNT[2] 02_557 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXBUF_EIDLE_LO_CNT[3] 03_557 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXBUF_EN 02_11 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXBUF_RESET_ON_CB_CHANGE 02_560 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXBUF_RESET_ON_COMMAALIGN 02_561 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXBUF_RESET_ON_EIDLE 02_547 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXBUF_RESET_ON_RATE_CHANGE 03_560 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXBUF_THRESH_OVFLW[0] 03_552 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXBUF_THRESH_OVFLW[1] 02_553 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXBUF_THRESH_OVFLW[2] 03_553 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXBUF_THRESH_OVFLW[3] 02_554 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXBUF_THRESH_OVFLW[4] 03_554 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXBUF_THRESH_OVFLW[5] 02_555 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXBUF_THRESH_OVRD 02_548 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXBUF_THRESH_UNDFLW[0] 02_544 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXBUF_THRESH_UNDFLW[1] 03_544 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXBUF_THRESH_UNDFLW[2] 02_545 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXBUF_THRESH_UNDFLW[3] 03_545 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXBUF_THRESH_UNDFLW[4] 02_546 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXBUF_THRESH_UNDFLW[5] 03_546 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXBUFRESET_TIME[0] 01_101 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXBUFRESET_TIME[1] 00_102 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXBUFRESET_TIME[2] 01_102 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXBUFRESET_TIME[3] 00_103 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXBUFRESET_TIME[4] 01_103 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[0] 02_640 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[1] 03_640 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[2] 02_641 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[3] 03_641 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[4] 02_642 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[5] 03_642 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[6] 02_643 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[7] 03_643 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[8] 02_644 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[9] 03_644 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[10] 02_645 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[11] 03_645 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[12] 02_646 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[13] 03_646 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[14] 02_647 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[15] 03_647 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[16] 02_648 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[17] 03_648 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[18] 02_649 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[19] 03_649 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[20] 02_650 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[21] 03_650 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[22] 02_651 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[23] 03_651 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[24] 02_652 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[25] 03_652 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[26] 02_653 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[27] 03_653 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[28] 02_654 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[29] 03_654 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[30] 02_655 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[31] 03_655 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[32] 02_656 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[33] 03_656 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[34] 02_657 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[35] 03_657 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[36] 02_658 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[37] 03_658 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[38] 02_659 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[39] 03_659 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[40] 02_660 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[41] 03_660 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[42] 02_661 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[43] 03_661 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[44] 02_662 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[45] 03_662 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[46] 02_663 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[47] 03_663 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[48] 02_664 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[49] 03_664 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[50] 02_665 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[51] 03_665 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[52] 02_666 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[53] 03_666 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[54] 02_667 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[55] 03_667 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[56] 02_668 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[57] 03_668 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[58] 02_669 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[59] 03_669 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[60] 02_670 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[61] 03_670 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[62] 02_671 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[63] 03_671 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[64] 02_672 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[65] 03_672 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[66] 02_673 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[67] 03_673 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[68] 02_674 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[69] 03_674 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[70] 02_675 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[71] 03_675 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[72] 02_676 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[73] 03_676 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[74] 02_677 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[75] 03_677 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[76] 02_678 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[77] 03_678 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[78] 02_679 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[79] 03_679 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[80] 02_680 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[81] 03_680 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[82] 02_681 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_FR_RESET_ON_EIDLE[0] 02_638 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_HOLD_DURING_EIDLE[0] 03_637 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_LOCK_CFG[0] 02_632 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_LOCK_CFG[1] 03_632 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_LOCK_CFG[2] 02_633 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_LOCK_CFG[3] 03_633 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_LOCK_CFG[4] 02_634 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_LOCK_CFG[5] 03_634 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_PH_RESET_ON_EIDLE[0] 03_638 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDRFREQRESET_TIME[0] 01_106 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDRFREQRESET_TIME[1] 00_107 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDRFREQRESET_TIME[2] 01_107 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDRFREQRESET_TIME[3] 00_108 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDRFREQRESET_TIME[4] 01_108 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDRPHRESET_TIME[0] 00_109 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDRPHRESET_TIME[1] 01_109 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDRPHRESET_TIME[2] 00_110 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDRPHRESET_TIME[3] 01_110 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDRPHRESET_TIME[4] 00_111 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXDLY_CFG[0] 00_680 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXDLY_CFG[1] 01_680 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXDLY_CFG[2] 00_681 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXDLY_CFG[3] 01_681 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXDLY_CFG[4] 00_682 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXDLY_CFG[5] 01_682 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXDLY_CFG[6] 00_683 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXDLY_CFG[7] 01_683 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXDLY_CFG[8] 00_684 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXDLY_CFG[9] 01_684 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXDLY_CFG[10] 00_685 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXDLY_CFG[11] 01_685 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXDLY_CFG[12] 00_686 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXDLY_CFG[13] 01_686 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXDLY_CFG[14] 00_687 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXDLY_CFG[15] 01_687 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXDLY_LCFG[0] 02_576 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXDLY_LCFG[1] 03_576 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXDLY_LCFG[2] 02_577 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXDLY_LCFG[3] 03_577 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXDLY_LCFG[4] 02_578 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXDLY_LCFG[5] 03_578 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXDLY_LCFG[6] 02_579 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXDLY_LCFG[7] 03_579 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXDLY_LCFG[8] 02_580 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXDLY_TAP_CFG[0] 00_672 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXDLY_TAP_CFG[1] 01_672 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXDLY_TAP_CFG[2] 00_673 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXDLY_TAP_CFG[3] 01_673 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXDLY_TAP_CFG[4] 00_674 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXDLY_TAP_CFG[5] 01_674 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXDLY_TAP_CFG[6] 00_675 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXDLY_TAP_CFG[7] 01_675 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXDLY_TAP_CFG[8] 00_676 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXDLY_TAP_CFG[9] 01_676 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXDLY_TAP_CFG[10] 00_677 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXDLY_TAP_CFG[11] 01_677 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXDLY_TAP_CFG[12] 00_678 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXDLY_TAP_CFG[13] 01_678 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXDLY_TAP_CFG[14] 00_679 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXDLY_TAP_CFG[15] 01_679 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXGEARBOX_EN 01_607 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXISCANRESET_TIME[0] 01_123 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXISCANRESET_TIME[1] 00_124 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXISCANRESET_TIME[2] 01_124 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXISCANRESET_TIME[3] 00_125 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXISCANRESET_TIME[4] 01_125 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPM_BIAS_STARTUP_DISABLE[0] 03_391 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPM_CFG[0] 02_328 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPM_CFG[1] 03_328 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPM_CFG[2] 02_329 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPM_CFG[3] 03_329 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPM_CM_CFG[0] 02_430 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPM_GC_CFG[0] 02_432 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPM_GC_CFG[1] 03_432 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPM_GC_CFG[2] 02_433 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPM_GC_CFG[3] 03_433 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPM_GC_CFG[4] 02_434 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPM_GC_CFG[5] 03_434 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPM_GC_CFG[6] 02_435 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPM_GC_CFG[7] 03_435 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPM_GC_CFG[8] 02_436 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPM_GC_CFG2[0] 03_442 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPM_GC_CFG2[1] 02_443 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPM_GC_CFG2[2] 03_443 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPM_HF_CFG[0] 00_336 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPM_HF_CFG[1] 01_336 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPM_HF_CFG[2] 00_337 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPM_HF_CFG[3] 01_337 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPM_HF_CFG[4] 00_338 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPM_HF_CFG[5] 01_338 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPM_HF_CFG[6] 00_339 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPM_HF_CFG[7] 01_339 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPM_HF_CFG[8] 00_340 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPM_HF_CFG[9] 01_340 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPM_HF_CFG[10] 00_341 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPM_HF_CFG[11] 01_341 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPM_HF_CFG[12] 00_342 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPM_HF_CFG[13] 01_342 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPM_HF_CFG2[0] 02_424 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPM_HF_CFG2[1] 03_424 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPM_HF_CFG2[2] 02_425 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPM_HF_CFG2[3] 03_425 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPM_HF_CFG2[4] 02_426 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPM_HF_CFG3[0] 03_389 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPM_HF_CFG3[1] 02_390 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPM_HF_CFG3[2] 03_390 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPM_HF_CFG3[3] 02_391 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPM_HOLD_DURING_EIDLE[0] 00_247 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPM_INCM_CFG[0] 02_439 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPM_IPCM_CFG[0] 03_439 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPM_LF_CFG[0] 00_344 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPM_LF_CFG[1] 01_344 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPM_LF_CFG[2] 00_345 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPM_LF_CFG[3] 01_345 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPM_LF_CFG[4] 00_346 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPM_LF_CFG[5] 01_346 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPM_LF_CFG[6] 00_347 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPM_LF_CFG[7] 01_347 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPM_LF_CFG[8] 00_348 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPM_LF_CFG[9] 01_348 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPM_LF_CFG[10] 00_349 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPM_LF_CFG[11] 01_349 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPM_LF_CFG[12] 00_350 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPM_LF_CFG[13] 01_350 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPM_LF_CFG[14] 00_351 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPM_LF_CFG[15] 01_351 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPM_LF_CFG[16] 00_343 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPM_LF_CFG[17] 01_343 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPM_LF_CFG2[0] 03_426 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPM_LF_CFG2[1] 02_427 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPM_LF_CFG2[2] 03_427 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPM_LF_CFG2[3] 02_428 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPM_LF_CFG2[4] 03_428 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPM_OSINT_CFG[0] 02_440 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPM_OSINT_CFG[1] 03_440 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPM_OSINT_CFG[2] 02_441 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPM_CFG1[0] 02_330 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPMRESET_TIME[0] 00_112 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPMRESET_TIME[1] 01_112 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPMRESET_TIME[2] 00_113 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPMRESET_TIME[3] 01_113 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPMRESET_TIME[4] 00_114 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPMRESET_TIME[5] 01_114 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPMRESET_TIME[6] 00_115 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXOOB_CFG[0] 00_144 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXOOB_CFG[1] 01_144 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXOOB_CFG[2] 00_145 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXOOB_CFG[3] 01_145 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXOOB_CFG[4] 00_146 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXOOB_CFG[5] 01_146 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXOOB_CFG[6] 00_147 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXOOB_CLK_CFG.FABRIC 03_129 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXOSCALRESET_TIME[0] 00_187 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXOSCALRESET_TIME[1] 01_187 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXOSCALRESET_TIME[2] 00_188 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXOSCALRESET_TIME[3] 01_188 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXOSCALRESET_TIME[4] 00_189 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXOSCALRESET_TIMEOUT[0] 01_189 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXOSCALRESET_TIMEOUT[1] 00_190 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXOSCALRESET_TIMEOUT[2] 01_190 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXOSCALRESET_TIMEOUT[3] 00_191 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXOSCALRESET_TIMEOUT[4] 01_191 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXOUT_DIV[0] 02_384 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXOUT_DIV[1] 03_384 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXPCSRESET_TIME[0] 01_115 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXPCSRESET_TIME[1] 00_116 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXPCSRESET_TIME[2] 01_116 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXPCSRESET_TIME[3] 00_117 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXPCSRESET_TIME[4] 01_117 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXPH_CFG[0] 02_584 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXPH_CFG[1] 03_584 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXPH_CFG[2] 02_585 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXPH_CFG[3] 03_585 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXPH_CFG[4] 02_586 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXPH_CFG[5] 03_586 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXPH_CFG[6] 02_587 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXPH_CFG[7] 03_587 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXPH_CFG[8] 02_588 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXPH_CFG[9] 03_588 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXPH_CFG[10] 02_589 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXPH_CFG[11] 03_589 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXPH_CFG[12] 02_590 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXPH_CFG[13] 03_590 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXPH_CFG[14] 02_591 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXPH_CFG[15] 03_591 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXPH_CFG[16] 02_592 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXPH_CFG[17] 03_592 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXPH_CFG[18] 02_593 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXPH_CFG[19] 03_593 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXPH_CFG[20] 02_594 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXPH_CFG[21] 03_594 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXPH_CFG[22] 02_595 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXPH_CFG[23] 03_595 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXPH_MONITOR_SEL[0] 00_700 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXPH_MONITOR_SEL[1] 01_700 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXPH_MONITOR_SEL[2] 00_701 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXPH_MONITOR_SEL[3] 01_701 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXPH_MONITOR_SEL[4] 00_702 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXPHDLY_CFG[0] 02_600 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXPHDLY_CFG[1] 03_600 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXPHDLY_CFG[2] 02_601 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXPHDLY_CFG[3] 03_601 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXPHDLY_CFG[4] 02_602 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXPHDLY_CFG[5] 03_602 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXPHDLY_CFG[6] 02_603 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXPHDLY_CFG[7] 03_603 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXPHDLY_CFG[8] 02_604 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXPHDLY_CFG[9] 03_604 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXPHDLY_CFG[10] 02_605 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXPHDLY_CFG[11] 03_605 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXPHDLY_CFG[12] 02_606 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXPHDLY_CFG[13] 03_606 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXPHDLY_CFG[14] 02_607 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXPHDLY_CFG[15] 03_607 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXPHDLY_CFG[16] 02_608 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXPHDLY_CFG[17] 03_608 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXPHDLY_CFG[18] 02_609 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXPHDLY_CFG[19] 03_609 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXPHDLY_CFG[20] 02_610 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXPHDLY_CFG[21] 03_610 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXPHDLY_CFG[22] 02_611 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXPHDLY_CFG[23] 03_611 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXPI_CFG0[0] 03_430 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXPI_CFG0[1] 02_431 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXPI_CFG0[2] 03_431 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXPI_CFG1[0] 02_442 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXPI_CFG2[0] 03_441 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXPMARESET_TIME[0] 00_104 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXPMARESET_TIME[1] 01_104 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXPMARESET_TIME[2] 00_105 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXPMARESET_TIME[3] 01_105 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXPMARESET_TIME[4] 00_106 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXPRBS_ERR_LOOPBACK[0] 00_136 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXSLIDE_AUTO_WAIT[0] 00_520 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXSLIDE_AUTO_WAIT[1] 01_520 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXSLIDE_AUTO_WAIT[2] 00_521 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXSLIDE_AUTO_WAIT[3] 01_521 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXSLIDE_MODE.AUTO 00_519 !01_519 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXSLIDE_MODE.PCS !00_519 01_519 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXSLIDE_MODE.PMA 00_519 01_519 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXSYNC_MULTILANE[0] 00_133 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXSYNC_OVRD[0] 01_135 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXSYNC_SKIP_DA[0] 01_134 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.SAS_MAX_COM[0] 00_171 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.SAS_MAX_COM[1] 01_171 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.SAS_MAX_COM[2] 00_172 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.SAS_MAX_COM[3] 01_172 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.SAS_MAX_COM[4] 00_173 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.SAS_MAX_COM[5] 01_173 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.SAS_MAX_COM[6] 00_174 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.SAS_MIN_COM[0] 01_156 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.SAS_MIN_COM[1] 00_157 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.SAS_MIN_COM[2] 01_157 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.SAS_MIN_COM[3] 00_158 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.SAS_MIN_COM[4] 01_158 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.SAS_MIN_COM[5] 00_159 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.SATA_BURST_SEQ_LEN[0] 00_150 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.SATA_BURST_SEQ_LEN[1] 01_150 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.SATA_BURST_SEQ_LEN[2] 00_151 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.SATA_BURST_SEQ_LEN[3] 01_151 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.SATA_BURST_VAL[0] 01_147 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.SATA_BURST_VAL[1] 00_148 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.SATA_BURST_VAL[2] 01_148 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.SATA_EIDLE_VAL[0] 00_152 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.SATA_EIDLE_VAL[1] 01_152 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.SATA_EIDLE_VAL[2] 00_153 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.SATA_MAX_BURST[0] 00_168 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.SATA_MAX_BURST[1] 01_168 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.SATA_MAX_BURST[2] 00_169 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.SATA_MAX_BURST[3] 01_169 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.SATA_MAX_BURST[4] 00_170 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.SATA_MAX_BURST[5] 01_170 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.SATA_MAX_INIT[0] 00_176 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.SATA_MAX_INIT[1] 01_176 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.SATA_MAX_INIT[2] 00_177 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.SATA_MAX_INIT[3] 01_177 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.SATA_MAX_INIT[4] 00_178 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.SATA_MAX_INIT[5] 01_178 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.SATA_MAX_WAKE[0] 00_179 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.SATA_MAX_WAKE[1] 01_179 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.SATA_MAX_WAKE[2] 00_180 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.SATA_MAX_WAKE[3] 01_180 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.SATA_MAX_WAKE[4] 00_181 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.SATA_MAX_WAKE[5] 01_181 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.SATA_MIN_BURST[0] 01_153 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.SATA_MIN_BURST[1] 00_154 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.SATA_MIN_BURST[2] 01_154 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.SATA_MIN_BURST[3] 00_155 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.SATA_MIN_BURST[4] 01_155 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.SATA_MIN_BURST[5] 00_156 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.SATA_MIN_INIT[0] 00_160 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.SATA_MIN_INIT[1] 01_160 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.SATA_MIN_INIT[2] 00_161 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.SATA_MIN_INIT[3] 01_161 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.SATA_MIN_INIT[4] 00_162 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.SATA_MIN_INIT[5] 01_162 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.SATA_MIN_WAKE[0] 00_163 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.SATA_MIN_WAKE[1] 01_163 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.SATA_MIN_WAKE[2] 00_164 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.SATA_MIN_WAKE[3] 01_164 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.SATA_MIN_WAKE[4] 00_165 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.SATA_MIN_WAKE[5] 01_165 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.SATA_PLL_CFG.VCO_1500MHZ 02_55 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.SATA_PLL_CFG.VCO_750MHZ 03_55 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.SHOW_REALIGN_COMMA 01_522 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TERM_RCAL_CFG[0] 02_136 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TERM_RCAL_CFG[1] 03_136 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TERM_RCAL_CFG[2] 02_137 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TERM_RCAL_CFG[3] 03_137 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TERM_RCAL_CFG[4] 02_138 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TERM_RCAL_CFG[5] 03_138 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TERM_RCAL_CFG[6] 02_139 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TERM_RCAL_CFG[7] 03_139 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TERM_RCAL_CFG[8] 02_140 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TERM_RCAL_CFG[9] 03_140 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TERM_RCAL_CFG[10] 02_141 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TERM_RCAL_CFG[11] 03_141 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TERM_RCAL_CFG[12] 02_142 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TERM_RCAL_CFG[13] 03_142 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TERM_RCAL_CFG[14] 02_143 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TERM_RCAL_OVRD[0] 03_150 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TERM_RCAL_OVRD[1] 02_151 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TERM_RCAL_OVRD[2] 03_151 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TRANS_TIME_RATE[0] 00_192 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TRANS_TIME_RATE[1] 01_192 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TRANS_TIME_RATE[2] 00_193 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TRANS_TIME_RATE[3] 01_193 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TRANS_TIME_RATE[4] 00_194 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TRANS_TIME_RATE[5] 01_194 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TRANS_TIME_RATE[6] 00_195 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TRANS_TIME_RATE[7] 01_195 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TST_RSV[0] 02_504 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TST_RSV[1] 03_504 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TST_RSV[2] 02_505 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TST_RSV[3] 03_505 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TST_RSV[4] 02_506 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TST_RSV[5] 03_506 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TST_RSV[6] 02_507 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TST_RSV[7] 03_507 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TST_RSV[8] 02_508 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TST_RSV[9] 03_508 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TST_RSV[10] 02_509 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TST_RSV[11] 03_509 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TST_RSV[12] 02_510 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TST_RSV[13] 03_510 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TST_RSV[14] 02_511 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TST_RSV[15] 03_511 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TST_RSV[16] 02_512 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TST_RSV[17] 03_512 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TST_RSV[18] 02_513 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TST_RSV[19] 03_513 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TST_RSV[20] 02_514 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TST_RSV[21] 03_514 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TST_RSV[22] 02_515 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TST_RSV[23] 03_515 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TST_RSV[24] 02_516 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TST_RSV[25] 03_516 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TST_RSV[26] 02_517 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TST_RSV[27] 03_517 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TST_RSV[28] 02_518 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TST_RSV[29] 03_518 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TST_RSV[30] 02_519 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TST_RSV[31] 03_519 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_CLKMUX_EN[0] 03_128 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_DATA_WIDTH[0] 02_152 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_DATA_WIDTH[1] 03_152 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_DATA_WIDTH[2] 02_153 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_DRIVE_MODE.PIPE 00_200 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_EIDLE_ASSERT_DELAY[0] 00_203 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_EIDLE_ASSERT_DELAY[1] 01_203 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_EIDLE_ASSERT_DELAY[2] 00_204 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_EIDLE_DEASSERT_DELAY[0] 01_204 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_EIDLE_DEASSERT_DELAY[1] 00_205 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_EIDLE_DEASSERT_DELAY[2] 01_205 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_LOOPBACK_DRIVE_HIZ 01_202 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_MAINCURSOR_SEL[0] 03_289 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_MARGIN_FULL_0[0] 02_232 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_MARGIN_FULL_0[1] 03_232 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_MARGIN_FULL_0[2] 02_233 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_MARGIN_FULL_0[3] 03_233 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_MARGIN_FULL_0[4] 02_234 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_MARGIN_FULL_0[5] 03_234 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_MARGIN_FULL_0[6] 02_235 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_MARGIN_FULL_1[0] 02_236 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_MARGIN_FULL_1[1] 03_236 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_MARGIN_FULL_1[2] 02_237 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_MARGIN_FULL_1[3] 03_237 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_MARGIN_FULL_1[4] 02_238 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_MARGIN_FULL_1[5] 03_238 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_MARGIN_FULL_1[6] 02_239 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_MARGIN_FULL_2[0] 02_240 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_MARGIN_FULL_2[1] 03_240 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_MARGIN_FULL_2[2] 02_241 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_MARGIN_FULL_2[3] 03_241 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_MARGIN_FULL_2[4] 02_242 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_MARGIN_FULL_2[5] 03_242 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_MARGIN_FULL_2[6] 02_243 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_MARGIN_FULL_3[0] 02_244 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_MARGIN_FULL_3[1] 03_244 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_MARGIN_FULL_3[2] 02_245 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_MARGIN_FULL_3[3] 03_245 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_MARGIN_FULL_3[4] 02_246 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_MARGIN_FULL_3[5] 03_246 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_MARGIN_FULL_3[6] 02_247 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_MARGIN_FULL_4[0] 02_248 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_MARGIN_FULL_4[1] 03_248 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_MARGIN_FULL_4[2] 02_249 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_MARGIN_FULL_4[3] 03_249 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_MARGIN_FULL_4[4] 02_250 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_MARGIN_FULL_4[5] 03_250 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_MARGIN_FULL_4[6] 02_251 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_MARGIN_LOW_0[0] 02_252 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_MARGIN_LOW_0[1] 03_252 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_MARGIN_LOW_0[2] 02_253 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_MARGIN_LOW_0[3] 03_253 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_MARGIN_LOW_0[4] 02_254 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_MARGIN_LOW_0[5] 03_254 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_MARGIN_LOW_0[6] 02_255 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_MARGIN_LOW_1[0] 02_256 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_MARGIN_LOW_1[1] 03_256 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_MARGIN_LOW_1[2] 02_257 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_MARGIN_LOW_1[3] 03_257 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_MARGIN_LOW_1[4] 02_258 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_MARGIN_LOW_1[5] 03_258 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_MARGIN_LOW_1[6] 02_259 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_MARGIN_LOW_2[0] 02_260 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_MARGIN_LOW_2[1] 03_260 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_MARGIN_LOW_2[2] 02_261 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_MARGIN_LOW_2[3] 03_261 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_MARGIN_LOW_2[4] 02_262 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_MARGIN_LOW_2[5] 03_262 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_MARGIN_LOW_2[6] 02_263 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_MARGIN_LOW_3[0] 02_264 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_MARGIN_LOW_3[1] 03_264 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_MARGIN_LOW_3[2] 02_265 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_MARGIN_LOW_3[3] 03_265 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_MARGIN_LOW_3[4] 02_266 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_MARGIN_LOW_3[5] 03_266 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_MARGIN_LOW_3[6] 02_267 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_MARGIN_LOW_4[0] 02_268 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_MARGIN_LOW_4[1] 03_268 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_MARGIN_LOW_4[2] 02_269 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_MARGIN_LOW_4[3] 03_269 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_MARGIN_LOW_4[4] 02_270 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_MARGIN_LOW_4[5] 03_270 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_MARGIN_LOW_4[6] 02_271 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_PREDRIVER_MODE[0] 00_206 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_RXDETECT_CFG[0] 02_296 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_RXDETECT_CFG[1] 03_296 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_RXDETECT_CFG[2] 02_297 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_RXDETECT_CFG[3] 03_297 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_RXDETECT_CFG[4] 02_298 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_RXDETECT_CFG[5] 03_298 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_RXDETECT_CFG[6] 02_299 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_RXDETECT_CFG[7] 03_299 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_RXDETECT_CFG[8] 02_300 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_RXDETECT_CFG[9] 03_300 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_RXDETECT_CFG[10] 02_301 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_RXDETECT_CFG[11] 03_301 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_RXDETECT_CFG[12] 02_302 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_RXDETECT_CFG[13] 03_302 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_RXDETECT_REF[0] 02_292 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_RXDETECT_REF[1] 03_292 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_RXDETECT_REF[2] 02_293 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_XCLK_SEL.TXUSR 03_11 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_CLK25_DIV[0] 02_144 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_CLK25_DIV[1] 03_144 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_CLK25_DIV[2] 02_145 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_CLK25_DIV[3] 03_145 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_CLK25_DIV[4] 02_146 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_DEEMPH0[0] 02_272 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_DEEMPH0[1] 03_272 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_DEEMPH0[2] 02_273 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_DEEMPH0[3] 03_273 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_DEEMPH0[4] 02_274 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_DEEMPH0[5] 03_274 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_DEEMPH1[0] 02_276 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_DEEMPH1[1] 03_276 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_DEEMPH1[2] 02_277 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_DEEMPH1[3] 03_277 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_DEEMPH1[4] 02_278 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_DEEMPH1[5] 03_278 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXBUF_EN 00_231 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXBUF_RESET_ON_RATE_CHANGE 01_231 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXDLY_CFG[0] 02_80 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXDLY_CFG[1] 03_80 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXDLY_CFG[2] 02_81 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXDLY_CFG[3] 03_81 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXDLY_CFG[4] 02_82 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXDLY_CFG[5] 03_82 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXDLY_CFG[6] 02_83 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXDLY_CFG[7] 03_83 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXDLY_CFG[8] 02_84 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXDLY_CFG[9] 03_84 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXDLY_CFG[10] 02_85 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXDLY_CFG[11] 03_85 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXDLY_CFG[12] 02_86 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXDLY_CFG[13] 03_86 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXDLY_CFG[14] 02_87 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXDLY_CFG[15] 03_87 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXDLY_LCFG[0] 02_568 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXDLY_LCFG[1] 03_568 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXDLY_LCFG[2] 02_569 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXDLY_LCFG[3] 03_569 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXDLY_LCFG[4] 02_570 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXDLY_LCFG[5] 03_570 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXDLY_LCFG[6] 02_571 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXDLY_LCFG[7] 03_571 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXDLY_LCFG[8] 02_572 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXDLY_TAP_CFG[0] 02_88 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXDLY_TAP_CFG[1] 03_88 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXDLY_TAP_CFG[2] 02_89 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXDLY_TAP_CFG[3] 03_89 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXDLY_TAP_CFG[4] 02_90 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXDLY_TAP_CFG[5] 03_90 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXDLY_TAP_CFG[6] 02_91 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXDLY_TAP_CFG[7] 03_91 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXDLY_TAP_CFG[8] 02_92 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXDLY_TAP_CFG[9] 03_92 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXDLY_TAP_CFG[10] 02_93 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXDLY_TAP_CFG[11] 03_93 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXDLY_TAP_CFG[12] 02_94 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXDLY_TAP_CFG[13] 03_94 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXDLY_TAP_CFG[14] 02_95 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXDLY_TAP_CFG[15] 03_95 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXGEARBOX_EN 01_226 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXOOB_CFG[0] 03_20 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXOUT_DIV[0] 02_386 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXOUT_DIV[1] 03_386 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPCSRESET_TIME[0] 01_130 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPCSRESET_TIME[1] 00_131 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPCSRESET_TIME[2] 01_131 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPCSRESET_TIME[3] 00_132 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPCSRESET_TIME[4] 01_132 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPH_CFG[0] 02_96 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPH_CFG[1] 03_96 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPH_CFG[2] 02_97 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPH_CFG[3] 03_97 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPH_CFG[4] 02_98 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPH_CFG[5] 03_98 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPH_CFG[6] 02_99 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPH_CFG[7] 03_99 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPH_CFG[8] 02_100 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPH_CFG[9] 03_100 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPH_CFG[10] 02_101 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPH_CFG[11] 03_101 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPH_CFG[12] 02_102 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPH_CFG[13] 03_102 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPH_CFG[14] 02_103 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPH_CFG[15] 03_103 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPH_MONITOR_SEL[0] 02_108 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPH_MONITOR_SEL[1] 03_108 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPH_MONITOR_SEL[2] 02_109 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPH_MONITOR_SEL[3] 03_109 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPH_MONITOR_SEL[4] 02_110 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPHDLY_CFG[0] 02_64 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPHDLY_CFG[1] 03_64 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPHDLY_CFG[2] 02_65 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPHDLY_CFG[3] 03_65 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPHDLY_CFG[4] 02_66 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPHDLY_CFG[5] 03_66 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPHDLY_CFG[6] 02_67 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPHDLY_CFG[7] 03_67 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPHDLY_CFG[8] 02_68 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPHDLY_CFG[9] 03_68 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPHDLY_CFG[10] 02_69 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPHDLY_CFG[11] 03_69 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPHDLY_CFG[12] 02_70 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPHDLY_CFG[13] 03_70 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPHDLY_CFG[14] 02_71 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPHDLY_CFG[15] 03_71 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPHDLY_CFG[16] 02_72 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPHDLY_CFG[17] 03_72 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPHDLY_CFG[18] 02_73 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPHDLY_CFG[19] 03_73 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPHDLY_CFG[20] 02_74 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPHDLY_CFG[21] 03_74 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPHDLY_CFG[22] 02_75 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPHDLY_CFG[23] 03_75 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPI_GREY_SEL[0] 03_498 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPI_INVSTROBE_SEL[0] 02_498 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPI_PPM_CFG[0] 02_488 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPI_PPM_CFG[1] 03_488 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPI_PPM_CFG[2] 02_489 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPI_PPM_CFG[3] 03_489 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPI_PPM_CFG[4] 02_490 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPI_PPM_CFG[5] 03_490 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPI_PPM_CFG[6] 02_491 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPI_PPM_CFG[7] 03_491 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPI_PPMCLK_SEL.TXUSRCLK2 03_497 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPI_SYNFREQ_PPM[0] 02_496 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPI_SYNFREQ_PPM[1] 03_496 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPI_SYNFREQ_PPM[2] 02_497 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPI_CFG0[0] 02_40 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPI_CFG0[1] 03_40 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPI_CFG1[0] 02_41 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPI_CFG1[1] 03_41 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPI_CFG2[0] 02_42 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPI_CFG2[1] 03_42 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPI_CFG3[0] 02_43 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPI_CFG4[0] 03_43 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPI_CFG5[0] 02_44 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPI_CFG5[1] 03_44 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPI_CFG5[2] 02_45 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPMARESET_TIME[0] 00_128 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPMARESET_TIME[1] 01_128 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPMARESET_TIME[2] 00_129 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPMARESET_TIME[3] 01_129 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPMARESET_TIME[4] 00_130 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXSYNC_MULTILANE[0] 01_133 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXSYNC_OVRD[0] 00_135 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXSYNC_SKIP_DA[0] 00_134 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.UCODEER_CLR[0] 01_00 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.USE_PCS_CLK_PHASE_SEL[0] 02_463 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ZINV_DMONITORCLK 02_13 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ZINV_DRPCLK 02_00 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ZINV_RXUSRCLK 03_01 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ZINV_SIGVALIDCLK 03_13 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ZINV_TXPHDLYTSTCLK 02_03 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ZINV_TXUSRCLK 03_04 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ZINV_CLKRSVD0 02_23 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ZINV_CLKRSVD1 03_23 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ZINV_RXUSRCLK2 02_02 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ZINV_TXUSRCLK2 02_05 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ACJTAG_DEBUG_MODE[0] 00_07 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ACJTAG_MODE[0] 01_06 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ACJTAG_RESET[0] 01_07 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[0] 02_464 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[1] 03_464 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[2] 02_465 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[3] 03_465 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[4] 02_466 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[5] 03_466 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[6] 02_467 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[7] 03_467 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[8] 02_468 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[9] 03_468 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[10] 02_469 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[11] 03_469 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[12] 02_470 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[13] 03_470 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[14] 02_471 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[15] 03_471 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[16] 02_472 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[17] 03_472 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[18] 02_473 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[19] 03_473 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ALIGN_COMMA_DOUBLE 00_522 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[0] 00_496 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[1] 01_496 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[2] 00_497 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[3] 01_497 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[4] 00_498 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[5] 01_498 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[6] 00_499 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[7] 01_499 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[8] 00_500 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[9] 01_500 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ALIGN_COMMA_WORD[0] 01_526 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ALIGN_COMMA_WORD[1] 00_527 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ALIGN_MCOMMA_DET 00_523 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[0] 00_504 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[1] 01_504 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[2] 00_505 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[3] 01_505 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[4] 00_506 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[5] 01_506 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[6] 00_507 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[7] 01_507 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[8] 00_508 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[9] 01_508 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ALIGN_PCOMMA_DET 01_523 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[0] 00_512 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[1] 01_512 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[2] 00_513 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[3] 01_513 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[4] 00_514 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[5] 01_514 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[6] 00_515 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[7] 01_515 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[8] 00_516 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[9] 01_516 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CBCC_DATA_SOURCE_SEL.DECODED 01_661 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[0] 02_392 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[1] 03_392 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[2] 02_393 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[3] 03_393 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[4] 02_394 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[5] 03_394 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[6] 02_395 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[7] 03_395 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[8] 02_396 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[9] 03_396 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[10] 02_397 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[11] 03_397 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[12] 02_398 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[13] 03_398 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[14] 02_399 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[15] 03_399 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[16] 02_400 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[17] 03_400 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[18] 02_401 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[19] 03_401 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[20] 02_402 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[21] 03_402 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[22] 02_403 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[23] 03_403 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[24] 02_404 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[25] 03_404 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[26] 02_405 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[27] 03_405 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[28] 02_406 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[29] 03_406 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[30] 02_407 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[31] 03_407 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[32] 02_408 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[33] 03_408 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[34] 02_409 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[35] 03_409 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[36] 02_410 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[37] 03_410 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[38] 02_411 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[39] 03_411 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[40] 02_412 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[41] 03_412 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[42] 02_413 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG2[0] 02_459 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG2[1] 03_459 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG2[2] 02_460 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG2[3] 03_460 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG2[4] 02_461 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG2[5] 03_461 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG2[6] 02_462 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG3[0] 02_416 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG3[1] 03_416 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG3[2] 02_417 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG3[3] 03_417 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG3[4] 02_418 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG3[5] 03_418 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG3[6] 02_419 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG4[0] 03_438 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG5[0] 02_429 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG5[1] 03_429 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG6[0] 03_436 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG6[1] 02_437 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG6[2] 03_437 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG6[3] 02_438 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_KEEP_ALIGN 01_631 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_MAX_SKEW[0] 00_670 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_MAX_SKEW[1] 01_670 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_MAX_SKEW[2] 00_671 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_MAX_SKEW[3] 01_671 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[0] 00_608 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[1] 01_608 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[2] 00_609 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[3] 01_609 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[4] 00_610 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[5] 01_610 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[6] 00_611 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[7] 01_611 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[8] 00_612 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[9] 01_612 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[0] 00_616 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[1] 01_616 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[2] 00_617 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[3] 01_617 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[4] 00_618 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[5] 01_618 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[6] 00_619 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[7] 01_619 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[8] 00_620 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[9] 01_620 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[0] 00_624 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[1] 01_624 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[2] 00_625 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[3] 01_625 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[4] 00_626 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[5] 01_626 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[6] 00_627 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[7] 01_627 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[8] 00_628 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[9] 01_628 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[0] 00_632 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[1] 01_632 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[2] 00_633 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[3] 01_633 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[4] 00_634 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[5] 01_634 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[6] 00_635 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[7] 01_635 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[8] 00_636 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[9] 01_636 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_ENABLE[0] 00_614 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_ENABLE[1] 01_614 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_ENABLE[2] 00_615 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_ENABLE[3] 01_615 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[0] 00_640 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[1] 01_640 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[2] 00_641 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[3] 01_641 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[4] 00_642 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[5] 01_642 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[6] 00_643 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[7] 01_643 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[8] 00_644 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[9] 01_644 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[0] 00_648 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[1] 01_648 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[2] 00_649 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[3] 01_649 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[4] 00_650 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[5] 01_650 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[6] 00_651 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[7] 01_651 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[8] 00_652 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[9] 01_652 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[0] 00_656 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[1] 01_656 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[2] 00_657 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[3] 01_657 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[4] 00_658 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[5] 01_658 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[6] 00_659 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[7] 01_659 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[8] 00_660 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[9] 01_660 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[0] 00_664 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[1] 01_664 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[2] 00_665 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[3] 01_665 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[4] 00_666 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[5] 01_666 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[6] 00_667 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[7] 01_667 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[8] 00_668 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[9] 01_668 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_ENABLE[0] 00_646 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_ENABLE[1] 01_646 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_ENABLE[2] 00_647 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_ENABLE[3] 01_647 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_USE 01_645 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_LEN[0] 00_623 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_LEN[1] 01_623 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COMMON_SWING[0] 03_311 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_KEEP_IDLE 00_591 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_MAX_LAT[0] 00_557 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_MAX_LAT[1] 01_557 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_MAX_LAT[2] 00_558 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_MAX_LAT[3] 01_558 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_MAX_LAT[4] 00_559 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_MAX_LAT[5] 01_559 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_MIN_LAT[0] 00_565 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_MIN_LAT[1] 01_565 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_MIN_LAT[2] 00_566 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_MIN_LAT[3] 01_566 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_MIN_LAT[4] 00_567 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_MIN_LAT[5] 01_567 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_PRECEDENCE 00_590 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_REPEAT_WAIT[0] 00_573 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_REPEAT_WAIT[1] 01_573 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_REPEAT_WAIT[2] 00_574 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_REPEAT_WAIT[3] 01_574 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_REPEAT_WAIT[4] 00_575 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[0] 00_544 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[1] 01_544 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[2] 00_545 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[3] 01_545 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[4] 00_546 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[5] 01_546 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[6] 00_547 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[7] 01_547 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[8] 00_548 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[9] 01_548 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[0] 00_552 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[1] 01_552 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[2] 00_553 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[3] 01_553 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[4] 00_554 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[5] 01_554 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[6] 00_555 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[7] 01_555 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[8] 00_556 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[9] 01_556 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[0] 00_560 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[1] 01_560 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[2] 00_561 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[3] 01_561 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[4] 00_562 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[5] 01_562 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[6] 00_563 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[7] 01_563 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[8] 00_564 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[9] 01_564 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[0] 00_568 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[1] 01_568 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[2] 00_569 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[3] 01_569 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[4] 00_570 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[5] 01_570 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[6] 00_571 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[7] 01_571 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[8] 00_572 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[9] 01_572 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_ENABLE[0] 00_549 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_ENABLE[1] 01_549 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_ENABLE[2] 00_550 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_ENABLE[3] 01_550 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[0] 00_576 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[1] 01_576 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[2] 00_577 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[3] 01_577 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[4] 00_578 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[5] 01_578 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[6] 00_579 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[7] 01_579 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[8] 00_580 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[9] 01_580 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[0] 00_584 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[1] 01_584 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[2] 00_585 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[3] 01_585 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[4] 00_586 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[5] 01_586 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[6] 00_587 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[7] 01_587 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[8] 00_588 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[9] 01_588 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[0] 00_592 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[1] 01_592 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[2] 00_593 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[3] 01_593 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[4] 00_594 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[5] 01_594 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[6] 00_595 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[7] 01_595 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[8] 00_596 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[9] 01_596 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[0] 00_600 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[1] 01_600 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[2] 00_601 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[3] 01_601 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[4] 00_602 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[5] 01_602 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[6] 00_603 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[7] 01_603 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[8] 00_604 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[9] 01_604 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_ENABLE[0] 00_581 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_ENABLE[1] 01_581 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_ENABLE[2] 00_582 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_ENABLE[3] 01_582 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_USE 00_583 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_LEN[0] 00_589 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_LEN[1] 01_589 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_CORRECT_USE 00_551 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.DEC_MCOMMA_DETECT 01_494 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.DEC_PCOMMA_DETECT 00_495 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.DEC_VALID_COMMA_ONLY 00_494 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[0] 02_368 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[1] 03_368 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[2] 02_369 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[3] 03_369 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[4] 02_370 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[5] 03_370 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[6] 02_371 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[7] 03_371 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[8] 02_372 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[9] 03_372 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[10] 02_373 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[11] 03_373 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[12] 02_374 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[13] 03_374 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[14] 02_375 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[15] 03_375 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[16] 02_376 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[17] 03_376 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[18] 02_377 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[19] 03_377 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[20] 02_378 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[21] 03_378 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[22] 02_379 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[23] 03_379 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_CLK_PHASE_SEL[0] 03_463 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_CONTROL[0] 00_488 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_CONTROL[1] 01_488 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_CONTROL[2] 00_489 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_CONTROL[3] 01_489 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_CONTROL[4] 00_490 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_CONTROL[5] 01_490 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_ERRDET_EN 01_492 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_EYE_SCAN_EN 00_492 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_HORZ_OFFSET[0] 00_480 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_HORZ_OFFSET[1] 01_480 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_HORZ_OFFSET[2] 00_481 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_HORZ_OFFSET[3] 01_481 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_HORZ_OFFSET[4] 00_482 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_HORZ_OFFSET[5] 01_482 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_HORZ_OFFSET[6] 00_483 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_HORZ_OFFSET[7] 01_483 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_HORZ_OFFSET[8] 00_484 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_HORZ_OFFSET[9] 01_484 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_HORZ_OFFSET[10] 00_485 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_HORZ_OFFSET[11] 01_485 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_PMA_CFG[0] 02_624 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_PMA_CFG[1] 03_624 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_PMA_CFG[2] 02_625 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_PMA_CFG[3] 03_625 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_PMA_CFG[4] 02_626 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_PMA_CFG[5] 03_626 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_PMA_CFG[6] 02_627 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_PMA_CFG[7] 03_627 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_PMA_CFG[8] 02_628 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_PMA_CFG[9] 03_628 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_PRESCALE[0] 01_477 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_PRESCALE[1] 00_478 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_PRESCALE[2] 01_478 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_PRESCALE[3] 00_479 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_PRESCALE[4] 01_479 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[0] 00_392 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[1] 01_392 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[2] 00_393 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[3] 01_393 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[4] 00_394 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[5] 01_394 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[6] 00_395 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[7] 01_395 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[8] 00_396 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[9] 01_396 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[10] 00_397 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[11] 01_397 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[12] 00_398 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[13] 01_398 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[14] 00_399 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[15] 01_399 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[16] 00_400 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[17] 01_400 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[18] 00_401 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[19] 01_401 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[20] 00_402 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[21] 01_402 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[22] 00_403 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[23] 01_403 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[24] 00_404 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[25] 01_404 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[26] 00_405 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[27] 01_405 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[28] 00_406 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[29] 01_406 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[30] 00_407 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[31] 01_407 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[32] 00_408 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[33] 01_408 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[34] 00_409 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[35] 01_409 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[36] 00_410 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[37] 01_410 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[38] 00_411 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[39] 01_411 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[40] 00_412 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[41] 01_412 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[42] 00_413 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[43] 01_413 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[44] 00_414 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[45] 01_414 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[46] 00_415 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[47] 01_415 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[48] 00_416 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[49] 01_416 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[50] 00_417 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[51] 01_417 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[52] 00_418 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[53] 01_418 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[54] 00_419 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[55] 01_419 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[56] 00_420 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[57] 01_420 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[58] 00_421 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[59] 01_421 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[60] 00_422 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[61] 01_422 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[62] 00_423 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[63] 01_423 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[64] 00_424 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[65] 01_424 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[66] 00_425 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[67] 01_425 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[68] 00_426 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[69] 01_426 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[70] 00_427 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[71] 01_427 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[72] 00_428 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[73] 01_428 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[74] 00_429 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[75] 01_429 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[76] 00_430 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[77] 01_430 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[78] 00_431 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[79] 01_431 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[0] 00_352 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[1] 01_352 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[2] 00_353 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[3] 01_353 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[4] 00_354 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[5] 01_354 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[6] 00_355 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[7] 01_355 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[8] 00_356 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[9] 01_356 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[10] 00_357 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[11] 01_357 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[12] 00_358 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[13] 01_358 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[14] 00_359 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[15] 01_359 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[16] 00_360 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[17] 01_360 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[18] 00_361 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[19] 01_361 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[20] 00_362 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[21] 01_362 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[22] 00_363 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[23] 01_363 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[24] 00_364 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[25] 01_364 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[26] 00_365 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[27] 01_365 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[28] 00_366 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[29] 01_366 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[30] 00_367 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[31] 01_367 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[32] 00_368 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[33] 01_368 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[34] 00_369 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[35] 01_369 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[36] 00_370 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[37] 01_370 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[38] 00_371 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[39] 01_371 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[40] 00_372 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[41] 01_372 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[42] 00_373 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[43] 01_373 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[44] 00_374 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[45] 01_374 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[46] 00_375 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[47] 01_375 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[48] 00_376 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[49] 01_376 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[50] 00_377 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[51] 01_377 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[52] 00_378 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[53] 01_378 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[54] 00_379 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[55] 01_379 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[56] 00_380 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[57] 01_380 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[58] 00_381 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[59] 01_381 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[60] 00_382 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[61] 01_382 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[62] 00_383 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[63] 01_383 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[64] 00_384 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[65] 01_384 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[66] 00_385 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[67] 01_385 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[68] 00_386 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[69] 01_386 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[70] 00_387 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[71] 01_387 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[72] 00_388 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[73] 01_388 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[74] 00_389 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[75] 01_389 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[76] 00_390 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[77] 01_390 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[78] 00_391 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[79] 01_391 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[0] 00_432 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[1] 01_432 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[2] 00_433 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[3] 01_433 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[4] 00_434 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[5] 01_434 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[6] 00_435 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[7] 01_435 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[8] 00_436 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[9] 01_436 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[10] 00_437 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[11] 01_437 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[12] 00_438 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[13] 01_438 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[14] 00_439 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[15] 01_439 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[16] 00_440 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[17] 01_440 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[18] 00_441 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[19] 01_441 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[20] 00_442 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[21] 01_442 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[22] 00_443 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[23] 01_443 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[24] 00_444 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[25] 01_444 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[26] 00_445 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[27] 01_445 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[28] 00_446 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[29] 01_446 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[30] 00_447 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[31] 01_447 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[32] 00_448 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[33] 01_448 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[34] 00_449 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[35] 01_449 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[36] 00_450 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[37] 01_450 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[38] 00_451 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[39] 01_451 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[40] 00_452 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[41] 01_452 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[42] 00_453 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[43] 01_453 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[44] 00_454 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[45] 01_454 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[46] 00_455 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[47] 01_455 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[48] 00_456 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[49] 01_456 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[50] 00_457 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[51] 01_457 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[52] 00_458 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[53] 01_458 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[54] 00_459 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[55] 01_459 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[56] 00_460 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[57] 01_460 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[58] 00_461 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[59] 01_461 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[60] 00_462 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[61] 01_462 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[62] 00_463 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[63] 01_463 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[64] 00_464 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[65] 01_464 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[66] 00_465 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[67] 01_465 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[68] 00_466 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[69] 01_466 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[70] 00_467 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[71] 01_467 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[72] 00_468 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[73] 01_468 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[74] 00_469 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[75] 01_469 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[76] 00_470 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[77] 01_470 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[78] 00_471 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[79] 01_471 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_VERT_OFFSET[0] 00_472 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_VERT_OFFSET[1] 01_472 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_VERT_OFFSET[2] 00_473 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_VERT_OFFSET[3] 01_473 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_VERT_OFFSET[4] 00_474 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_VERT_OFFSET[5] 01_474 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_VERT_OFFSET[6] 00_475 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_VERT_OFFSET[7] 01_475 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_VERT_OFFSET[8] 00_476 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.FTS_DESKEW_SEQ_ENABLE[0] 00_662 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.FTS_DESKEW_SEQ_ENABLE[1] 01_662 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.FTS_DESKEW_SEQ_ENABLE[2] 00_663 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.FTS_DESKEW_SEQ_ENABLE[3] 01_663 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.FTS_LANE_DESKEW_CFG[0] 00_654 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.FTS_LANE_DESKEW_CFG[1] 01_654 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.FTS_LANE_DESKEW_CFG[2] 00_655 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.FTS_LANE_DESKEW_CFG[3] 01_655 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.FTS_LANE_DESKEW_EN 01_653 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.GEARBOX_MODE[0] 00_224 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.GEARBOX_MODE[1] 01_224 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.GEARBOX_MODE[2] 00_225 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.IN_USE 00_00 00_01 00_47 00_52 00_53 00_65 01_01 01_47 02_129 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.INV_DMONITORCLK 02_13 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.INV_DRPCLK 02_00 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.INV_RXUSRCLK 03_01 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.INV_SIGVALIDCLK 03_13 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.INV_TXPHDLYTSTCLK 02_03 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.INV_TXUSRCLK 03_04 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.INV_CLKRSVD0 02_23 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.INV_CLKRSVD1 03_23 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.INV_RXUSRCLK2 02_02 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.INV_TXUSRCLK2 02_05 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.LOOPBACK_CFG[0] 02_20 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.OUTREFCLK_SEL_INV[0] 00_149 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.OUTREFCLK_SEL_INV[1] 01_149 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PCS_PCIE_EN 00_216 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[0] 02_184 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[1] 03_184 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[2] 02_185 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[3] 03_185 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[4] 02_186 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[5] 03_186 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[6] 02_187 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[7] 03_187 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[8] 02_188 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[9] 03_188 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[10] 02_189 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[11] 03_189 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[12] 02_190 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[13] 03_190 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[14] 02_191 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[15] 03_191 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[16] 02_192 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[17] 03_192 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[18] 02_193 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[19] 03_193 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[20] 02_194 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[21] 03_194 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[22] 02_195 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[23] 03_195 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[24] 02_196 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[25] 03_196 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[26] 02_197 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[27] 03_197 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[28] 02_198 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[29] 03_198 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[30] 02_199 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[31] 03_199 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[32] 02_200 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[33] 03_200 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[34] 02_201 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[35] 03_201 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[36] 02_202 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[37] 03_202 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[38] 02_203 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[39] 03_203 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[40] 02_204 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[41] 03_204 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[42] 02_205 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[43] 03_205 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[44] 02_206 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[45] 03_206 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[46] 02_207 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[47] 03_207 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[0] 01_216 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[1] 00_217 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[2] 01_217 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[3] 00_218 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[4] 01_218 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[5] 00_219 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[6] 01_219 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[7] 00_220 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[8] 01_220 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[9] 00_221 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[10] 01_221 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[11] 00_222 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[0] 00_208 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[1] 01_208 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[2] 00_209 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[3] 01_209 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[4] 00_210 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[5] 01_210 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[6] 00_211 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[7] 01_211 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[0] 00_212 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[1] 01_212 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[2] 00_213 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[3] 01_213 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[4] 00_214 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[5] 01_214 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[6] 00_215 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[7] 01_215 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PMA_LOOPBACK_CFG[0] 01_207 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[0] 02_520 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[1] 03_520 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[2] 02_521 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[3] 03_521 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[4] 02_522 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[5] 03_522 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[6] 02_523 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[7] 03_523 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[8] 02_524 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[9] 03_524 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[10] 02_525 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[11] 03_525 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[12] 02_526 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[13] 03_526 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[14] 02_527 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[15] 03_527 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[16] 02_528 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[17] 03_528 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[18] 02_529 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[19] 03_529 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[20] 02_530 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[21] 03_530 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[22] 02_531 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[23] 03_531 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[24] 02_532 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[25] 03_532 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[26] 02_533 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[27] 03_533 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[28] 02_534 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[29] 03_534 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[30] 02_535 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[31] 03_535 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[0] 02_336 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[1] 03_336 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[2] 02_337 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[3] 03_337 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[4] 02_338 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[5] 03_338 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[6] 02_339 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[7] 03_339 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[8] 02_340 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[9] 03_340 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[10] 02_341 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[11] 03_341 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[12] 02_342 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[13] 03_342 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[14] 02_343 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[15] 03_343 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[16] 02_344 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[17] 03_344 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[18] 02_345 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[19] 03_345 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[20] 02_346 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[21] 03_346 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[22] 02_347 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[23] 03_347 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[24] 02_348 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[25] 03_348 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[26] 02_349 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[27] 03_349 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[28] 02_350 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[29] 03_350 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[30] 02_351 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[31] 03_351 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV3[0] 02_288 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV3[1] 03_288 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV4[0] 02_156 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV4[1] 03_156 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV4[2] 02_157 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV4[3] 03_157 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV5[0] 03_159 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV6[0] 02_303 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV7[0] 03_303 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_BIAS_CFG[0] 02_112 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_BIAS_CFG[1] 03_112 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_BIAS_CFG[2] 02_113 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_BIAS_CFG[3] 03_113 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_BIAS_CFG[4] 02_114 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_BIAS_CFG[5] 03_114 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_BIAS_CFG[6] 02_115 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_BIAS_CFG[7] 03_115 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_BIAS_CFG[8] 02_116 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_BIAS_CFG[9] 03_116 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_BIAS_CFG[10] 02_117 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_BIAS_CFG[11] 03_117 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_BIAS_CFG[12] 02_118 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_BIAS_CFG[13] 03_118 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_BIAS_CFG[14] 02_119 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_BIAS_CFG[15] 03_119 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_BUFFER_CFG[0] 02_536 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_BUFFER_CFG[1] 03_536 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_BUFFER_CFG[2] 02_537 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_BUFFER_CFG[3] 03_537 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_BUFFER_CFG[4] 02_538 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_BUFFER_CFG[5] 03_538 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_CLKMUX_EN[0] 02_128 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_CM_SEL[0] 00_138 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_CM_SEL[1] 01_138 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_CM_TRIM[0] 02_304 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_CM_TRIM[1] 03_304 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_CM_TRIM[2] 02_305 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_CM_TRIM[3] 03_305 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_DATA_WIDTH[0] 01_141 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_DATA_WIDTH[1] 00_142 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_DATA_WIDTH[2] 01_142 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_DDI_SEL[0] 00_696 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_DDI_SEL[1] 01_696 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_DDI_SEL[2] 00_697 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_DDI_SEL[3] 01_697 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_DDI_SEL[4] 00_698 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_DDI_SEL[5] 01_698 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_DEBUG_CFG[0] 02_616 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_DEBUG_CFG[1] 03_616 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_DEBUG_CFG[2] 02_617 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_DEBUG_CFG[3] 03_617 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_DEBUG_CFG[4] 02_618 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_DEBUG_CFG[5] 03_618 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_DEBUG_CFG[6] 02_619 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_DEBUG_CFG[7] 03_619 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_DEBUG_CFG[8] 02_620 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_DEBUG_CFG[9] 03_620 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_DEBUG_CFG[10] 02_621 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_DEBUG_CFG[11] 03_621 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_DEBUG_CFG[12] 02_622 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_DEBUG_CFG[13] 03_622 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_DEFER_RESET_BUF_EN 02_552 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_DISPERR_SEQ_MATCH 01_495 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_OS_CFG[0] 00_288 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_OS_CFG[1] 01_288 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_OS_CFG[2] 00_289 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_OS_CFG[3] 01_289 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_OS_CFG[4] 00_290 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_OS_CFG[5] 01_290 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_OS_CFG[6] 00_291 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_OS_CFG[7] 01_291 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_OS_CFG[8] 00_292 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_OS_CFG[9] 01_292 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_OS_CFG[10] 00_293 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_OS_CFG[11] 01_293 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_OS_CFG[12] 00_294 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_SIG_VALID_DLY[0] 00_524 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_SIG_VALID_DLY[1] 01_524 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_SIG_VALID_DLY[2] 00_525 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_SIG_VALID_DLY[3] 01_525 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_SIG_VALID_DLY[4] 00_526 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_XCLK_SEL.RXUSR 00_143 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_CLK25_DIV[0] 00_139 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_CLK25_DIV[1] 01_139 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_CLK25_DIV[2] 00_140 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_CLK25_DIV[3] 01_140 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_CLK25_DIV[4] 00_141 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXBUF_ADDR_MODE.FAST 03_555 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXBUF_EIDLE_HI_CNT[0] 02_558 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXBUF_EIDLE_HI_CNT[1] 03_558 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXBUF_EIDLE_HI_CNT[2] 02_559 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXBUF_EIDLE_HI_CNT[3] 03_559 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXBUF_EIDLE_LO_CNT[0] 02_556 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXBUF_EIDLE_LO_CNT[1] 03_556 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXBUF_EIDLE_LO_CNT[2] 02_557 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXBUF_EIDLE_LO_CNT[3] 03_557 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXBUF_EN 02_11 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXBUF_RESET_ON_CB_CHANGE 02_560 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXBUF_RESET_ON_COMMAALIGN 02_561 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXBUF_RESET_ON_EIDLE 02_547 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXBUF_RESET_ON_RATE_CHANGE 03_560 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXBUF_THRESH_OVFLW[0] 03_552 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXBUF_THRESH_OVFLW[1] 02_553 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXBUF_THRESH_OVFLW[2] 03_553 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXBUF_THRESH_OVFLW[3] 02_554 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXBUF_THRESH_OVFLW[4] 03_554 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXBUF_THRESH_OVFLW[5] 02_555 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXBUF_THRESH_OVRD 02_548 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXBUF_THRESH_UNDFLW[0] 02_544 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXBUF_THRESH_UNDFLW[1] 03_544 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXBUF_THRESH_UNDFLW[2] 02_545 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXBUF_THRESH_UNDFLW[3] 03_545 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXBUF_THRESH_UNDFLW[4] 02_546 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXBUF_THRESH_UNDFLW[5] 03_546 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXBUFRESET_TIME[0] 01_101 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXBUFRESET_TIME[1] 00_102 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXBUFRESET_TIME[2] 01_102 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXBUFRESET_TIME[3] 00_103 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXBUFRESET_TIME[4] 01_103 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[0] 02_640 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[1] 03_640 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[2] 02_641 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[3] 03_641 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[4] 02_642 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[5] 03_642 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[6] 02_643 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[7] 03_643 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[8] 02_644 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[9] 03_644 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[10] 02_645 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[11] 03_645 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[12] 02_646 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[13] 03_646 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[14] 02_647 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[15] 03_647 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[16] 02_648 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[17] 03_648 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[18] 02_649 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[19] 03_649 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[20] 02_650 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[21] 03_650 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[22] 02_651 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[23] 03_651 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[24] 02_652 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[25] 03_652 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[26] 02_653 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[27] 03_653 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[28] 02_654 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[29] 03_654 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[30] 02_655 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[31] 03_655 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[32] 02_656 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[33] 03_656 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[34] 02_657 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[35] 03_657 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[36] 02_658 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[37] 03_658 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[38] 02_659 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[39] 03_659 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[40] 02_660 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[41] 03_660 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[42] 02_661 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[43] 03_661 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[44] 02_662 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[45] 03_662 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[46] 02_663 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[47] 03_663 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[48] 02_664 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[49] 03_664 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[50] 02_665 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[51] 03_665 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[52] 02_666 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[53] 03_666 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[54] 02_667 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[55] 03_667 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[56] 02_668 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[57] 03_668 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[58] 02_669 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[59] 03_669 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[60] 02_670 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[61] 03_670 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[62] 02_671 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[63] 03_671 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[64] 02_672 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[65] 03_672 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[66] 02_673 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[67] 03_673 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[68] 02_674 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[69] 03_674 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[70] 02_675 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[71] 03_675 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[72] 02_676 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[73] 03_676 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[74] 02_677 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[75] 03_677 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[76] 02_678 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[77] 03_678 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[78] 02_679 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[79] 03_679 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[80] 02_680 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[81] 03_680 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[82] 02_681 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_FR_RESET_ON_EIDLE[0] 02_638 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_HOLD_DURING_EIDLE[0] 03_637 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_LOCK_CFG[0] 02_632 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_LOCK_CFG[1] 03_632 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_LOCK_CFG[2] 02_633 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_LOCK_CFG[3] 03_633 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_LOCK_CFG[4] 02_634 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_LOCK_CFG[5] 03_634 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_PH_RESET_ON_EIDLE[0] 03_638 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDRFREQRESET_TIME[0] 01_106 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDRFREQRESET_TIME[1] 00_107 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDRFREQRESET_TIME[2] 01_107 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDRFREQRESET_TIME[3] 00_108 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDRFREQRESET_TIME[4] 01_108 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDRPHRESET_TIME[0] 00_109 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDRPHRESET_TIME[1] 01_109 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDRPHRESET_TIME[2] 00_110 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDRPHRESET_TIME[3] 01_110 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDRPHRESET_TIME[4] 00_111 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXDLY_CFG[0] 00_680 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXDLY_CFG[1] 01_680 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXDLY_CFG[2] 00_681 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXDLY_CFG[3] 01_681 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXDLY_CFG[4] 00_682 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXDLY_CFG[5] 01_682 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXDLY_CFG[6] 00_683 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXDLY_CFG[7] 01_683 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXDLY_CFG[8] 00_684 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXDLY_CFG[9] 01_684 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXDLY_CFG[10] 00_685 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXDLY_CFG[11] 01_685 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXDLY_CFG[12] 00_686 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXDLY_CFG[13] 01_686 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXDLY_CFG[14] 00_687 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXDLY_CFG[15] 01_687 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXDLY_LCFG[0] 02_576 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXDLY_LCFG[1] 03_576 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXDLY_LCFG[2] 02_577 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXDLY_LCFG[3] 03_577 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXDLY_LCFG[4] 02_578 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXDLY_LCFG[5] 03_578 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXDLY_LCFG[6] 02_579 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXDLY_LCFG[7] 03_579 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXDLY_LCFG[8] 02_580 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXDLY_TAP_CFG[0] 00_672 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXDLY_TAP_CFG[1] 01_672 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXDLY_TAP_CFG[2] 00_673 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXDLY_TAP_CFG[3] 01_673 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXDLY_TAP_CFG[4] 00_674 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXDLY_TAP_CFG[5] 01_674 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXDLY_TAP_CFG[6] 00_675 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXDLY_TAP_CFG[7] 01_675 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXDLY_TAP_CFG[8] 00_676 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXDLY_TAP_CFG[9] 01_676 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXDLY_TAP_CFG[10] 00_677 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXDLY_TAP_CFG[11] 01_677 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXDLY_TAP_CFG[12] 00_678 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXDLY_TAP_CFG[13] 01_678 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXDLY_TAP_CFG[14] 00_679 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXDLY_TAP_CFG[15] 01_679 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXGEARBOX_EN 01_607 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXISCANRESET_TIME[0] 01_123 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXISCANRESET_TIME[1] 00_124 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXISCANRESET_TIME[2] 01_124 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXISCANRESET_TIME[3] 00_125 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXISCANRESET_TIME[4] 01_125 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPM_BIAS_STARTUP_DISABLE[0] 03_391 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPM_CFG[0] 02_328 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPM_CFG[1] 03_328 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPM_CFG[2] 02_329 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPM_CFG[3] 03_329 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPM_CM_CFG[0] 02_430 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPM_GC_CFG[0] 02_432 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPM_GC_CFG[1] 03_432 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPM_GC_CFG[2] 02_433 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPM_GC_CFG[3] 03_433 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPM_GC_CFG[4] 02_434 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPM_GC_CFG[5] 03_434 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPM_GC_CFG[6] 02_435 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPM_GC_CFG[7] 03_435 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPM_GC_CFG[8] 02_436 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPM_GC_CFG2[0] 03_442 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPM_GC_CFG2[1] 02_443 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPM_GC_CFG2[2] 03_443 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG[0] 00_336 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG[1] 01_336 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG[2] 00_337 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG[3] 01_337 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG[4] 00_338 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG[5] 01_338 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG[6] 00_339 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG[7] 01_339 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG[8] 00_340 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG[9] 01_340 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG[10] 00_341 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG[11] 01_341 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG[12] 00_342 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG[13] 01_342 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG2[0] 02_424 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG2[1] 03_424 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG2[2] 02_425 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG2[3] 03_425 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG2[4] 02_426 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG3[0] 03_389 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG3[1] 02_390 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG3[2] 03_390 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG3[3] 02_391 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HOLD_DURING_EIDLE[0] 00_247 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPM_INCM_CFG[0] 02_439 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPM_IPCM_CFG[0] 03_439 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG[0] 00_344 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG[1] 01_344 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG[2] 00_345 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG[3] 01_345 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG[4] 00_346 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG[5] 01_346 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG[6] 00_347 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG[7] 01_347 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG[8] 00_348 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG[9] 01_348 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG[10] 00_349 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG[11] 01_349 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG[12] 00_350 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG[13] 01_350 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG[14] 00_351 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG[15] 01_351 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG[16] 00_343 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG[17] 01_343 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG2[0] 03_426 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG2[1] 02_427 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG2[2] 03_427 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG2[3] 02_428 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG2[4] 03_428 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPM_OSINT_CFG[0] 02_440 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPM_OSINT_CFG[1] 03_440 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPM_OSINT_CFG[2] 02_441 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPM_CFG1[0] 02_330 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPMRESET_TIME[0] 00_112 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPMRESET_TIME[1] 01_112 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPMRESET_TIME[2] 00_113 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPMRESET_TIME[3] 01_113 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPMRESET_TIME[4] 00_114 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPMRESET_TIME[5] 01_114 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPMRESET_TIME[6] 00_115 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXOOB_CFG[0] 00_144 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXOOB_CFG[1] 01_144 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXOOB_CFG[2] 00_145 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXOOB_CFG[3] 01_145 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXOOB_CFG[4] 00_146 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXOOB_CFG[5] 01_146 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXOOB_CFG[6] 00_147 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXOOB_CLK_CFG.FABRIC 03_129 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXOSCALRESET_TIME[0] 00_187 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXOSCALRESET_TIME[1] 01_187 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXOSCALRESET_TIME[2] 00_188 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXOSCALRESET_TIME[3] 01_188 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXOSCALRESET_TIME[4] 00_189 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXOSCALRESET_TIMEOUT[0] 01_189 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXOSCALRESET_TIMEOUT[1] 00_190 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXOSCALRESET_TIMEOUT[2] 01_190 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXOSCALRESET_TIMEOUT[3] 00_191 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXOSCALRESET_TIMEOUT[4] 01_191 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXOUT_DIV[0] 02_384 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXOUT_DIV[1] 03_384 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXPCSRESET_TIME[0] 01_115 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXPCSRESET_TIME[1] 00_116 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXPCSRESET_TIME[2] 01_116 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXPCSRESET_TIME[3] 00_117 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXPCSRESET_TIME[4] 01_117 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[0] 02_584 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[1] 03_584 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[2] 02_585 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[3] 03_585 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[4] 02_586 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[5] 03_586 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[6] 02_587 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[7] 03_587 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[8] 02_588 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[9] 03_588 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[10] 02_589 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[11] 03_589 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[12] 02_590 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[13] 03_590 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[14] 02_591 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[15] 03_591 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[16] 02_592 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[17] 03_592 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[18] 02_593 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[19] 03_593 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[20] 02_594 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[21] 03_594 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[22] 02_595 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[23] 03_595 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXPH_MONITOR_SEL[0] 00_700 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXPH_MONITOR_SEL[1] 01_700 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXPH_MONITOR_SEL[2] 00_701 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXPH_MONITOR_SEL[3] 01_701 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXPH_MONITOR_SEL[4] 00_702 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[0] 02_600 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[1] 03_600 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[2] 02_601 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[3] 03_601 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[4] 02_602 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[5] 03_602 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[6] 02_603 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[7] 03_603 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[8] 02_604 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[9] 03_604 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[10] 02_605 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[11] 03_605 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[12] 02_606 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[13] 03_606 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[14] 02_607 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[15] 03_607 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[16] 02_608 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[17] 03_608 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[18] 02_609 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[19] 03_609 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[20] 02_610 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[21] 03_610 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[22] 02_611 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[23] 03_611 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXPI_CFG0[0] 03_430 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXPI_CFG0[1] 02_431 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXPI_CFG0[2] 03_431 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXPI_CFG1[0] 02_442 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXPI_CFG2[0] 03_441 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXPMARESET_TIME[0] 00_104 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXPMARESET_TIME[1] 01_104 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXPMARESET_TIME[2] 00_105 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXPMARESET_TIME[3] 01_105 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXPMARESET_TIME[4] 00_106 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXPRBS_ERR_LOOPBACK[0] 00_136 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXSLIDE_AUTO_WAIT[0] 00_520 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXSLIDE_AUTO_WAIT[1] 01_520 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXSLIDE_AUTO_WAIT[2] 00_521 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXSLIDE_AUTO_WAIT[3] 01_521 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXSLIDE_MODE.AUTO 00_519 !01_519 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXSLIDE_MODE.PCS !00_519 01_519 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXSLIDE_MODE.PMA 00_519 01_519 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXSYNC_MULTILANE[0] 00_133 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXSYNC_OVRD[0] 01_135 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXSYNC_SKIP_DA[0] 01_134 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.SAS_MAX_COM[0] 00_171 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.SAS_MAX_COM[1] 01_171 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.SAS_MAX_COM[2] 00_172 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.SAS_MAX_COM[3] 01_172 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.SAS_MAX_COM[4] 00_173 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.SAS_MAX_COM[5] 01_173 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.SAS_MAX_COM[6] 00_174 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.SAS_MIN_COM[0] 01_156 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.SAS_MIN_COM[1] 00_157 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.SAS_MIN_COM[2] 01_157 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.SAS_MIN_COM[3] 00_158 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.SAS_MIN_COM[4] 01_158 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.SAS_MIN_COM[5] 00_159 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.SATA_BURST_SEQ_LEN[0] 00_150 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.SATA_BURST_SEQ_LEN[1] 01_150 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.SATA_BURST_SEQ_LEN[2] 00_151 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.SATA_BURST_SEQ_LEN[3] 01_151 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.SATA_BURST_VAL[0] 01_147 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.SATA_BURST_VAL[1] 00_148 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.SATA_BURST_VAL[2] 01_148 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.SATA_EIDLE_VAL[0] 00_152 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.SATA_EIDLE_VAL[1] 01_152 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.SATA_EIDLE_VAL[2] 00_153 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.SATA_MAX_BURST[0] 00_168 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.SATA_MAX_BURST[1] 01_168 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.SATA_MAX_BURST[2] 00_169 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.SATA_MAX_BURST[3] 01_169 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.SATA_MAX_BURST[4] 00_170 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.SATA_MAX_BURST[5] 01_170 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.SATA_MAX_INIT[0] 00_176 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.SATA_MAX_INIT[1] 01_176 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.SATA_MAX_INIT[2] 00_177 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.SATA_MAX_INIT[3] 01_177 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.SATA_MAX_INIT[4] 00_178 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.SATA_MAX_INIT[5] 01_178 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.SATA_MAX_WAKE[0] 00_179 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.SATA_MAX_WAKE[1] 01_179 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.SATA_MAX_WAKE[2] 00_180 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.SATA_MAX_WAKE[3] 01_180 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.SATA_MAX_WAKE[4] 00_181 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.SATA_MAX_WAKE[5] 01_181 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.SATA_MIN_BURST[0] 01_153 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.SATA_MIN_BURST[1] 00_154 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.SATA_MIN_BURST[2] 01_154 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.SATA_MIN_BURST[3] 00_155 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.SATA_MIN_BURST[4] 01_155 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.SATA_MIN_BURST[5] 00_156 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.SATA_MIN_INIT[0] 00_160 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.SATA_MIN_INIT[1] 01_160 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.SATA_MIN_INIT[2] 00_161 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.SATA_MIN_INIT[3] 01_161 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.SATA_MIN_INIT[4] 00_162 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.SATA_MIN_INIT[5] 01_162 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.SATA_MIN_WAKE[0] 00_163 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.SATA_MIN_WAKE[1] 01_163 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.SATA_MIN_WAKE[2] 00_164 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.SATA_MIN_WAKE[3] 01_164 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.SATA_MIN_WAKE[4] 00_165 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.SATA_MIN_WAKE[5] 01_165 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.SATA_PLL_CFG.VCO_1500MHZ 02_55 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.SATA_PLL_CFG.VCO_750MHZ 03_55 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.SHOW_REALIGN_COMMA 01_522 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TERM_RCAL_CFG[0] 02_136 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TERM_RCAL_CFG[1] 03_136 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TERM_RCAL_CFG[2] 02_137 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TERM_RCAL_CFG[3] 03_137 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TERM_RCAL_CFG[4] 02_138 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TERM_RCAL_CFG[5] 03_138 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TERM_RCAL_CFG[6] 02_139 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TERM_RCAL_CFG[7] 03_139 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TERM_RCAL_CFG[8] 02_140 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TERM_RCAL_CFG[9] 03_140 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TERM_RCAL_CFG[10] 02_141 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TERM_RCAL_CFG[11] 03_141 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TERM_RCAL_CFG[12] 02_142 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TERM_RCAL_CFG[13] 03_142 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TERM_RCAL_CFG[14] 02_143 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TERM_RCAL_OVRD[0] 03_150 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TERM_RCAL_OVRD[1] 02_151 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TERM_RCAL_OVRD[2] 03_151 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TRANS_TIME_RATE[0] 00_192 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TRANS_TIME_RATE[1] 01_192 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TRANS_TIME_RATE[2] 00_193 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TRANS_TIME_RATE[3] 01_193 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TRANS_TIME_RATE[4] 00_194 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TRANS_TIME_RATE[5] 01_194 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TRANS_TIME_RATE[6] 00_195 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TRANS_TIME_RATE[7] 01_195 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[0] 02_504 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[1] 03_504 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[2] 02_505 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[3] 03_505 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[4] 02_506 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[5] 03_506 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[6] 02_507 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[7] 03_507 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[8] 02_508 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[9] 03_508 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[10] 02_509 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[11] 03_509 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[12] 02_510 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[13] 03_510 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[14] 02_511 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[15] 03_511 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[16] 02_512 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[17] 03_512 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[18] 02_513 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[19] 03_513 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[20] 02_514 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[21] 03_514 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[22] 02_515 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[23] 03_515 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[24] 02_516 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[25] 03_516 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[26] 02_517 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[27] 03_517 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[28] 02_518 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[29] 03_518 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[30] 02_519 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[31] 03_519 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_CLKMUX_EN[0] 03_128 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_DATA_WIDTH[0] 02_152 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_DATA_WIDTH[1] 03_152 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_DATA_WIDTH[2] 02_153 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_DRIVE_MODE.PIPE 00_200 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_EIDLE_ASSERT_DELAY[0] 00_203 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_EIDLE_ASSERT_DELAY[1] 01_203 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_EIDLE_ASSERT_DELAY[2] 00_204 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_EIDLE_DEASSERT_DELAY[0] 01_204 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_EIDLE_DEASSERT_DELAY[1] 00_205 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_EIDLE_DEASSERT_DELAY[2] 01_205 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_LOOPBACK_DRIVE_HIZ 01_202 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_MAINCURSOR_SEL[0] 03_289 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_0[0] 02_232 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_0[1] 03_232 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_0[2] 02_233 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_0[3] 03_233 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_0[4] 02_234 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_0[5] 03_234 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_0[6] 02_235 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_1[0] 02_236 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_1[1] 03_236 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_1[2] 02_237 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_1[3] 03_237 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_1[4] 02_238 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_1[5] 03_238 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_1[6] 02_239 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_2[0] 02_240 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_2[1] 03_240 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_2[2] 02_241 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_2[3] 03_241 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_2[4] 02_242 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_2[5] 03_242 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_2[6] 02_243 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_3[0] 02_244 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_3[1] 03_244 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_3[2] 02_245 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_3[3] 03_245 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_3[4] 02_246 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_3[5] 03_246 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_3[6] 02_247 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_4[0] 02_248 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_4[1] 03_248 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_4[2] 02_249 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_4[3] 03_249 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_4[4] 02_250 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_4[5] 03_250 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_4[6] 02_251 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_0[0] 02_252 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_0[1] 03_252 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_0[2] 02_253 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_0[3] 03_253 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_0[4] 02_254 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_0[5] 03_254 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_0[6] 02_255 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_1[0] 02_256 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_1[1] 03_256 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_1[2] 02_257 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_1[3] 03_257 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_1[4] 02_258 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_1[5] 03_258 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_1[6] 02_259 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_2[0] 02_260 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_2[1] 03_260 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_2[2] 02_261 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_2[3] 03_261 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_2[4] 02_262 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_2[5] 03_262 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_2[6] 02_263 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_3[0] 02_264 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_3[1] 03_264 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_3[2] 02_265 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_3[3] 03_265 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_3[4] 02_266 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_3[5] 03_266 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_3[6] 02_267 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_4[0] 02_268 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_4[1] 03_268 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_4[2] 02_269 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_4[3] 03_269 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_4[4] 02_270 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_4[5] 03_270 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_4[6] 02_271 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_PREDRIVER_MODE[0] 00_206 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_RXDETECT_CFG[0] 02_296 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_RXDETECT_CFG[1] 03_296 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_RXDETECT_CFG[2] 02_297 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_RXDETECT_CFG[3] 03_297 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_RXDETECT_CFG[4] 02_298 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_RXDETECT_CFG[5] 03_298 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_RXDETECT_CFG[6] 02_299 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_RXDETECT_CFG[7] 03_299 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_RXDETECT_CFG[8] 02_300 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_RXDETECT_CFG[9] 03_300 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_RXDETECT_CFG[10] 02_301 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_RXDETECT_CFG[11] 03_301 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_RXDETECT_CFG[12] 02_302 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_RXDETECT_CFG[13] 03_302 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_RXDETECT_REF[0] 02_292 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_RXDETECT_REF[1] 03_292 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_RXDETECT_REF[2] 02_293 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_XCLK_SEL.TXUSR 03_11 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_CLK25_DIV[0] 02_144 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_CLK25_DIV[1] 03_144 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_CLK25_DIV[2] 02_145 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_CLK25_DIV[3] 03_145 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_CLK25_DIV[4] 02_146 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_DEEMPH0[0] 02_272 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_DEEMPH0[1] 03_272 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_DEEMPH0[2] 02_273 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_DEEMPH0[3] 03_273 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_DEEMPH0[4] 02_274 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_DEEMPH0[5] 03_274 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_DEEMPH1[0] 02_276 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_DEEMPH1[1] 03_276 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_DEEMPH1[2] 02_277 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_DEEMPH1[3] 03_277 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_DEEMPH1[4] 02_278 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_DEEMPH1[5] 03_278 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXBUF_EN 00_231 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXBUF_RESET_ON_RATE_CHANGE 01_231 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXDLY_CFG[0] 02_80 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXDLY_CFG[1] 03_80 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXDLY_CFG[2] 02_81 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXDLY_CFG[3] 03_81 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXDLY_CFG[4] 02_82 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXDLY_CFG[5] 03_82 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXDLY_CFG[6] 02_83 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXDLY_CFG[7] 03_83 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXDLY_CFG[8] 02_84 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXDLY_CFG[9] 03_84 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXDLY_CFG[10] 02_85 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXDLY_CFG[11] 03_85 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXDLY_CFG[12] 02_86 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXDLY_CFG[13] 03_86 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXDLY_CFG[14] 02_87 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXDLY_CFG[15] 03_87 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXDLY_LCFG[0] 02_568 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXDLY_LCFG[1] 03_568 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXDLY_LCFG[2] 02_569 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXDLY_LCFG[3] 03_569 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXDLY_LCFG[4] 02_570 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXDLY_LCFG[5] 03_570 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXDLY_LCFG[6] 02_571 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXDLY_LCFG[7] 03_571 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXDLY_LCFG[8] 02_572 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXDLY_TAP_CFG[0] 02_88 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXDLY_TAP_CFG[1] 03_88 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXDLY_TAP_CFG[2] 02_89 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXDLY_TAP_CFG[3] 03_89 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXDLY_TAP_CFG[4] 02_90 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXDLY_TAP_CFG[5] 03_90 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXDLY_TAP_CFG[6] 02_91 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXDLY_TAP_CFG[7] 03_91 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXDLY_TAP_CFG[8] 02_92 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXDLY_TAP_CFG[9] 03_92 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXDLY_TAP_CFG[10] 02_93 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXDLY_TAP_CFG[11] 03_93 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXDLY_TAP_CFG[12] 02_94 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXDLY_TAP_CFG[13] 03_94 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXDLY_TAP_CFG[14] 02_95 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXDLY_TAP_CFG[15] 03_95 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXGEARBOX_EN 01_226 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXOOB_CFG[0] 03_20 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXOUT_DIV[0] 02_386 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXOUT_DIV[1] 03_386 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPCSRESET_TIME[0] 01_130 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPCSRESET_TIME[1] 00_131 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPCSRESET_TIME[2] 01_131 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPCSRESET_TIME[3] 00_132 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPCSRESET_TIME[4] 01_132 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPH_CFG[0] 02_96 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPH_CFG[1] 03_96 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPH_CFG[2] 02_97 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPH_CFG[3] 03_97 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPH_CFG[4] 02_98 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPH_CFG[5] 03_98 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPH_CFG[6] 02_99 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPH_CFG[7] 03_99 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPH_CFG[8] 02_100 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPH_CFG[9] 03_100 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPH_CFG[10] 02_101 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPH_CFG[11] 03_101 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPH_CFG[12] 02_102 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPH_CFG[13] 03_102 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPH_CFG[14] 02_103 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPH_CFG[15] 03_103 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPH_MONITOR_SEL[0] 02_108 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPH_MONITOR_SEL[1] 03_108 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPH_MONITOR_SEL[2] 02_109 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPH_MONITOR_SEL[3] 03_109 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPH_MONITOR_SEL[4] 02_110 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[0] 02_64 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[1] 03_64 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[2] 02_65 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[3] 03_65 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[4] 02_66 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[5] 03_66 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[6] 02_67 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[7] 03_67 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[8] 02_68 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[9] 03_68 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[10] 02_69 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[11] 03_69 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[12] 02_70 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[13] 03_70 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[14] 02_71 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[15] 03_71 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[16] 02_72 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[17] 03_72 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[18] 02_73 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[19] 03_73 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[20] 02_74 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[21] 03_74 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[22] 02_75 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[23] 03_75 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPI_GREY_SEL[0] 03_498 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPI_INVSTROBE_SEL[0] 02_498 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPI_PPM_CFG[0] 02_488 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPI_PPM_CFG[1] 03_488 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPI_PPM_CFG[2] 02_489 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPI_PPM_CFG[3] 03_489 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPI_PPM_CFG[4] 02_490 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPI_PPM_CFG[5] 03_490 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPI_PPM_CFG[6] 02_491 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPI_PPM_CFG[7] 03_491 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPI_PPMCLK_SEL.TXUSRCLK2 03_497 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPI_SYNFREQ_PPM[0] 02_496 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPI_SYNFREQ_PPM[1] 03_496 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPI_SYNFREQ_PPM[2] 02_497 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPI_CFG0[0] 02_40 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPI_CFG0[1] 03_40 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPI_CFG1[0] 02_41 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPI_CFG1[1] 03_41 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPI_CFG2[0] 02_42 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPI_CFG2[1] 03_42 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPI_CFG3[0] 02_43 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPI_CFG4[0] 03_43 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPI_CFG5[0] 02_44 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPI_CFG5[1] 03_44 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPI_CFG5[2] 02_45 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPMARESET_TIME[0] 00_128 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPMARESET_TIME[1] 01_128 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPMARESET_TIME[2] 00_129 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPMARESET_TIME[3] 01_129 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPMARESET_TIME[4] 00_130 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXSYNC_MULTILANE[0] 01_133 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXSYNC_OVRD[0] 00_135 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXSYNC_SKIP_DA[0] 00_134 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.UCODEER_CLR[0] 01_00 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.USE_PCS_CLK_PHASE_SEL[0] 02_463 diff --git a/artix7/segbits_gtp_channel_3_mid_right.origin_info.db b/artix7/segbits_gtp_channel_3_mid_right.origin_info.db index c6760f3..cc52ef8 100644 --- a/artix7/segbits_gtp_channel_3_mid_right.origin_info.db +++ b/artix7/segbits_gtp_channel_3_mid_right.origin_info.db @@ -1,1627 +1,1627 @@ -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ACJTAG_DEBUG_MODE[0] origin:064-gtp-channel-conf 00_07 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ACJTAG_MODE[0] origin:064-gtp-channel-conf 01_06 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ACJTAG_RESET[0] origin:064-gtp-channel-conf 01_07 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ADAPT_CFG0[0] origin:064-gtp-channel-conf 02_464 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ADAPT_CFG0[1] origin:064-gtp-channel-conf 03_464 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ADAPT_CFG0[2] origin:064-gtp-channel-conf 02_465 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ADAPT_CFG0[3] origin:064-gtp-channel-conf 03_465 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ADAPT_CFG0[4] origin:064-gtp-channel-conf 02_466 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ADAPT_CFG0[5] origin:064-gtp-channel-conf 03_466 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ADAPT_CFG0[6] origin:064-gtp-channel-conf 02_467 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ADAPT_CFG0[7] origin:064-gtp-channel-conf 03_467 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ADAPT_CFG0[8] origin:064-gtp-channel-conf 02_468 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ADAPT_CFG0[9] origin:064-gtp-channel-conf 03_468 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ADAPT_CFG0[10] origin:064-gtp-channel-conf 02_469 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ADAPT_CFG0[11] origin:064-gtp-channel-conf 03_469 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ADAPT_CFG0[12] origin:064-gtp-channel-conf 02_470 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ADAPT_CFG0[13] origin:064-gtp-channel-conf 03_470 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ADAPT_CFG0[14] origin:064-gtp-channel-conf 02_471 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ADAPT_CFG0[15] origin:064-gtp-channel-conf 03_471 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ADAPT_CFG0[16] origin:064-gtp-channel-conf 02_472 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ADAPT_CFG0[17] origin:064-gtp-channel-conf 03_472 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ADAPT_CFG0[18] origin:064-gtp-channel-conf 02_473 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ADAPT_CFG0[19] origin:064-gtp-channel-conf 03_473 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ALIGN_COMMA_DOUBLE origin:064-gtp-channel-conf 00_522 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ALIGN_COMMA_ENABLE[0] origin:064-gtp-channel-conf 00_496 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ALIGN_COMMA_ENABLE[1] origin:064-gtp-channel-conf 01_496 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ALIGN_COMMA_ENABLE[2] origin:064-gtp-channel-conf 00_497 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ALIGN_COMMA_ENABLE[3] origin:064-gtp-channel-conf 01_497 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ALIGN_COMMA_ENABLE[4] origin:064-gtp-channel-conf 00_498 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ALIGN_COMMA_ENABLE[5] origin:064-gtp-channel-conf 01_498 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ALIGN_COMMA_ENABLE[6] origin:064-gtp-channel-conf 00_499 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ALIGN_COMMA_ENABLE[7] origin:064-gtp-channel-conf 01_499 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ALIGN_COMMA_ENABLE[8] origin:064-gtp-channel-conf 00_500 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ALIGN_COMMA_ENABLE[9] origin:064-gtp-channel-conf 01_500 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ALIGN_COMMA_WORD[0] origin:064-gtp-channel-conf 01_526 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ALIGN_COMMA_WORD[1] origin:064-gtp-channel-conf 00_527 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ALIGN_MCOMMA_DET origin:064-gtp-channel-conf 00_523 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ALIGN_MCOMMA_VALUE[0] origin:064-gtp-channel-conf 00_504 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ALIGN_MCOMMA_VALUE[1] origin:064-gtp-channel-conf 01_504 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ALIGN_MCOMMA_VALUE[2] origin:064-gtp-channel-conf 00_505 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ALIGN_MCOMMA_VALUE[3] origin:064-gtp-channel-conf 01_505 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ALIGN_MCOMMA_VALUE[4] origin:064-gtp-channel-conf 00_506 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ALIGN_MCOMMA_VALUE[5] origin:064-gtp-channel-conf 01_506 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ALIGN_MCOMMA_VALUE[6] origin:064-gtp-channel-conf 00_507 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ALIGN_MCOMMA_VALUE[7] origin:064-gtp-channel-conf 01_507 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ALIGN_MCOMMA_VALUE[8] origin:064-gtp-channel-conf 00_508 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ALIGN_MCOMMA_VALUE[9] origin:064-gtp-channel-conf 01_508 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ALIGN_PCOMMA_DET origin:064-gtp-channel-conf 01_523 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ALIGN_PCOMMA_VALUE[0] origin:064-gtp-channel-conf 00_512 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ALIGN_PCOMMA_VALUE[1] origin:064-gtp-channel-conf 01_512 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ALIGN_PCOMMA_VALUE[2] origin:064-gtp-channel-conf 00_513 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ALIGN_PCOMMA_VALUE[3] origin:064-gtp-channel-conf 01_513 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ALIGN_PCOMMA_VALUE[4] origin:064-gtp-channel-conf 00_514 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ALIGN_PCOMMA_VALUE[5] origin:064-gtp-channel-conf 01_514 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ALIGN_PCOMMA_VALUE[6] origin:064-gtp-channel-conf 00_515 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ALIGN_PCOMMA_VALUE[7] origin:064-gtp-channel-conf 01_515 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ALIGN_PCOMMA_VALUE[8] origin:064-gtp-channel-conf 00_516 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ALIGN_PCOMMA_VALUE[9] origin:064-gtp-channel-conf 01_516 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CBCC_DATA_SOURCE_SEL.DECODED origin:064-gtp-channel-conf 01_661 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CFOK_CFG[0] origin:064-gtp-channel-conf 02_392 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CFOK_CFG[1] origin:064-gtp-channel-conf 03_392 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CFOK_CFG[2] origin:064-gtp-channel-conf 02_393 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CFOK_CFG[3] origin:064-gtp-channel-conf 03_393 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CFOK_CFG[4] origin:064-gtp-channel-conf 02_394 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CFOK_CFG[5] origin:064-gtp-channel-conf 03_394 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CFOK_CFG[6] origin:064-gtp-channel-conf 02_395 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CFOK_CFG[7] origin:064-gtp-channel-conf 03_395 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CFOK_CFG[8] origin:064-gtp-channel-conf 02_396 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CFOK_CFG[9] origin:064-gtp-channel-conf 03_396 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CFOK_CFG[10] origin:064-gtp-channel-conf 02_397 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CFOK_CFG[11] origin:064-gtp-channel-conf 03_397 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CFOK_CFG[12] origin:064-gtp-channel-conf 02_398 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CFOK_CFG[13] origin:064-gtp-channel-conf 03_398 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CFOK_CFG[14] origin:064-gtp-channel-conf 02_399 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CFOK_CFG[15] origin:064-gtp-channel-conf 03_399 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CFOK_CFG[16] origin:064-gtp-channel-conf 02_400 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CFOK_CFG[17] origin:064-gtp-channel-conf 03_400 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CFOK_CFG[18] origin:064-gtp-channel-conf 02_401 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CFOK_CFG[19] origin:064-gtp-channel-conf 03_401 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CFOK_CFG[20] origin:064-gtp-channel-conf 02_402 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CFOK_CFG[21] origin:064-gtp-channel-conf 03_402 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CFOK_CFG[22] origin:064-gtp-channel-conf 02_403 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CFOK_CFG[23] origin:064-gtp-channel-conf 03_403 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CFOK_CFG[24] origin:064-gtp-channel-conf 02_404 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CFOK_CFG[25] origin:064-gtp-channel-conf 03_404 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CFOK_CFG[26] origin:064-gtp-channel-conf 02_405 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CFOK_CFG[27] origin:064-gtp-channel-conf 03_405 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CFOK_CFG[28] origin:064-gtp-channel-conf 02_406 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CFOK_CFG[29] origin:064-gtp-channel-conf 03_406 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CFOK_CFG[30] origin:064-gtp-channel-conf 02_407 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CFOK_CFG[31] origin:064-gtp-channel-conf 03_407 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CFOK_CFG[32] origin:064-gtp-channel-conf 02_408 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CFOK_CFG[33] origin:064-gtp-channel-conf 03_408 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CFOK_CFG[34] origin:064-gtp-channel-conf 02_409 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CFOK_CFG[35] origin:064-gtp-channel-conf 03_409 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CFOK_CFG[36] origin:064-gtp-channel-conf 02_410 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CFOK_CFG[37] origin:064-gtp-channel-conf 03_410 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CFOK_CFG[38] origin:064-gtp-channel-conf 02_411 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CFOK_CFG[39] origin:064-gtp-channel-conf 03_411 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CFOK_CFG[40] origin:064-gtp-channel-conf 02_412 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CFOK_CFG[41] origin:064-gtp-channel-conf 03_412 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CFOK_CFG[42] origin:064-gtp-channel-conf 02_413 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CFOK_CFG2[0] origin:064-gtp-channel-conf 02_459 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CFOK_CFG2[1] origin:064-gtp-channel-conf 03_459 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CFOK_CFG2[2] origin:064-gtp-channel-conf 02_460 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CFOK_CFG2[3] origin:064-gtp-channel-conf 03_460 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CFOK_CFG2[4] origin:064-gtp-channel-conf 02_461 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CFOK_CFG2[5] origin:064-gtp-channel-conf 03_461 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CFOK_CFG2[6] origin:064-gtp-channel-conf 02_462 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CFOK_CFG3[0] origin:064-gtp-channel-conf 02_416 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CFOK_CFG3[1] origin:064-gtp-channel-conf 03_416 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CFOK_CFG3[2] origin:064-gtp-channel-conf 02_417 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CFOK_CFG3[3] origin:064-gtp-channel-conf 03_417 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CFOK_CFG3[4] origin:064-gtp-channel-conf 02_418 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CFOK_CFG3[5] origin:064-gtp-channel-conf 03_418 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CFOK_CFG3[6] origin:064-gtp-channel-conf 02_419 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CFOK_CFG4[0] origin:064-gtp-channel-conf 03_438 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CFOK_CFG5[0] origin:064-gtp-channel-conf 02_429 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CFOK_CFG5[1] origin:064-gtp-channel-conf 03_429 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CFOK_CFG6[0] origin:064-gtp-channel-conf 03_436 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CFOK_CFG6[1] origin:064-gtp-channel-conf 02_437 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CFOK_CFG6[2] origin:064-gtp-channel-conf 03_437 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CFOK_CFG6[3] origin:064-gtp-channel-conf 02_438 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_KEEP_ALIGN origin:064-gtp-channel-conf 01_631 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_MAX_SKEW[0] origin:064-gtp-channel-conf 00_670 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_MAX_SKEW[1] origin:064-gtp-channel-conf 01_670 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_MAX_SKEW[2] origin:064-gtp-channel-conf 00_671 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_MAX_SKEW[3] origin:064-gtp-channel-conf 01_671 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_1[0] origin:064-gtp-channel-conf 00_608 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_1[1] origin:064-gtp-channel-conf 01_608 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_1[2] origin:064-gtp-channel-conf 00_609 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_1[3] origin:064-gtp-channel-conf 01_609 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_1[4] origin:064-gtp-channel-conf 00_610 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_1[5] origin:064-gtp-channel-conf 01_610 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_1[6] origin:064-gtp-channel-conf 00_611 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_1[7] origin:064-gtp-channel-conf 01_611 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_1[8] origin:064-gtp-channel-conf 00_612 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_1[9] origin:064-gtp-channel-conf 01_612 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_2[0] origin:064-gtp-channel-conf 00_616 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_2[1] origin:064-gtp-channel-conf 01_616 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_2[2] origin:064-gtp-channel-conf 00_617 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_2[3] origin:064-gtp-channel-conf 01_617 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_2[4] origin:064-gtp-channel-conf 00_618 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_2[5] origin:064-gtp-channel-conf 01_618 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_2[6] origin:064-gtp-channel-conf 00_619 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_2[7] origin:064-gtp-channel-conf 01_619 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_2[8] origin:064-gtp-channel-conf 00_620 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_2[9] origin:064-gtp-channel-conf 01_620 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_3[0] origin:064-gtp-channel-conf 00_624 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_3[1] origin:064-gtp-channel-conf 01_624 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_3[2] origin:064-gtp-channel-conf 00_625 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_3[3] origin:064-gtp-channel-conf 01_625 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_3[4] origin:064-gtp-channel-conf 00_626 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_3[5] origin:064-gtp-channel-conf 01_626 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_3[6] origin:064-gtp-channel-conf 00_627 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_3[7] origin:064-gtp-channel-conf 01_627 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_3[8] origin:064-gtp-channel-conf 00_628 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_3[9] origin:064-gtp-channel-conf 01_628 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_4[0] origin:064-gtp-channel-conf 00_632 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_4[1] origin:064-gtp-channel-conf 01_632 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_4[2] origin:064-gtp-channel-conf 00_633 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_4[3] origin:064-gtp-channel-conf 01_633 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_4[4] origin:064-gtp-channel-conf 00_634 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_4[5] origin:064-gtp-channel-conf 01_634 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_4[6] origin:064-gtp-channel-conf 00_635 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_4[7] origin:064-gtp-channel-conf 01_635 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_4[8] origin:064-gtp-channel-conf 00_636 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_4[9] origin:064-gtp-channel-conf 01_636 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_ENABLE[0] origin:064-gtp-channel-conf 00_614 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_ENABLE[1] origin:064-gtp-channel-conf 01_614 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_ENABLE[2] origin:064-gtp-channel-conf 00_615 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_1_ENABLE[3] origin:064-gtp-channel-conf 01_615 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_1[0] origin:064-gtp-channel-conf 00_640 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_1[1] origin:064-gtp-channel-conf 01_640 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_1[2] origin:064-gtp-channel-conf 00_641 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_1[3] origin:064-gtp-channel-conf 01_641 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_1[4] origin:064-gtp-channel-conf 00_642 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_1[5] origin:064-gtp-channel-conf 01_642 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_1[6] origin:064-gtp-channel-conf 00_643 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_1[7] origin:064-gtp-channel-conf 01_643 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_1[8] origin:064-gtp-channel-conf 00_644 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_1[9] origin:064-gtp-channel-conf 01_644 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_2[0] origin:064-gtp-channel-conf 00_648 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_2[1] origin:064-gtp-channel-conf 01_648 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_2[2] origin:064-gtp-channel-conf 00_649 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_2[3] origin:064-gtp-channel-conf 01_649 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_2[4] origin:064-gtp-channel-conf 00_650 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_2[5] origin:064-gtp-channel-conf 01_650 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_2[6] origin:064-gtp-channel-conf 00_651 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_2[7] origin:064-gtp-channel-conf 01_651 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_2[8] origin:064-gtp-channel-conf 00_652 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_2[9] origin:064-gtp-channel-conf 01_652 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_3[0] origin:064-gtp-channel-conf 00_656 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_3[1] origin:064-gtp-channel-conf 01_656 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_3[2] origin:064-gtp-channel-conf 00_657 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_3[3] origin:064-gtp-channel-conf 01_657 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_3[4] origin:064-gtp-channel-conf 00_658 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_3[5] origin:064-gtp-channel-conf 01_658 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_3[6] origin:064-gtp-channel-conf 00_659 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_3[7] origin:064-gtp-channel-conf 01_659 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_3[8] origin:064-gtp-channel-conf 00_660 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_3[9] origin:064-gtp-channel-conf 01_660 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_4[0] origin:064-gtp-channel-conf 00_664 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_4[1] origin:064-gtp-channel-conf 01_664 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_4[2] origin:064-gtp-channel-conf 00_665 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_4[3] origin:064-gtp-channel-conf 01_665 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_4[4] origin:064-gtp-channel-conf 00_666 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_4[5] origin:064-gtp-channel-conf 01_666 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_4[6] origin:064-gtp-channel-conf 00_667 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_4[7] origin:064-gtp-channel-conf 01_667 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_4[8] origin:064-gtp-channel-conf 00_668 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_4[9] origin:064-gtp-channel-conf 01_668 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_ENABLE[0] origin:064-gtp-channel-conf 00_646 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_ENABLE[1] origin:064-gtp-channel-conf 01_646 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_ENABLE[2] origin:064-gtp-channel-conf 00_647 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_ENABLE[3] origin:064-gtp-channel-conf 01_647 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_2_USE origin:064-gtp-channel-conf 01_645 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_LEN[0] origin:064-gtp-channel-conf 00_623 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CHAN_BOND_SEQ_LEN[1] origin:064-gtp-channel-conf 01_623 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COMMON_SWING[0] origin:064-gtp-channel-conf 03_311 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_KEEP_IDLE origin:064-gtp-channel-conf 00_591 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_MAX_LAT[0] origin:064-gtp-channel-conf 00_557 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_MAX_LAT[1] origin:064-gtp-channel-conf 01_557 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_MAX_LAT[2] origin:064-gtp-channel-conf 00_558 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_MAX_LAT[3] origin:064-gtp-channel-conf 01_558 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_MAX_LAT[4] origin:064-gtp-channel-conf 00_559 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_MAX_LAT[5] origin:064-gtp-channel-conf 01_559 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_MIN_LAT[0] origin:064-gtp-channel-conf 00_565 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_MIN_LAT[1] origin:064-gtp-channel-conf 01_565 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_MIN_LAT[2] origin:064-gtp-channel-conf 00_566 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_MIN_LAT[3] origin:064-gtp-channel-conf 01_566 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_MIN_LAT[4] origin:064-gtp-channel-conf 00_567 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_MIN_LAT[5] origin:064-gtp-channel-conf 01_567 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_PRECEDENCE origin:064-gtp-channel-conf 00_590 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_REPEAT_WAIT[0] origin:064-gtp-channel-conf 00_573 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_REPEAT_WAIT[1] origin:064-gtp-channel-conf 01_573 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_REPEAT_WAIT[2] origin:064-gtp-channel-conf 00_574 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_REPEAT_WAIT[3] origin:064-gtp-channel-conf 01_574 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_REPEAT_WAIT[4] origin:064-gtp-channel-conf 00_575 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_1[0] origin:064-gtp-channel-conf 00_544 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_1[1] origin:064-gtp-channel-conf 01_544 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_1[2] origin:064-gtp-channel-conf 00_545 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_1[3] origin:064-gtp-channel-conf 01_545 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_1[4] origin:064-gtp-channel-conf 00_546 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_1[5] origin:064-gtp-channel-conf 01_546 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_1[6] origin:064-gtp-channel-conf 00_547 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_1[7] origin:064-gtp-channel-conf 01_547 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_1[8] origin:064-gtp-channel-conf 00_548 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_1[9] origin:064-gtp-channel-conf 01_548 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_2[0] origin:064-gtp-channel-conf 00_552 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_2[1] origin:064-gtp-channel-conf 01_552 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_2[2] origin:064-gtp-channel-conf 00_553 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_2[3] origin:064-gtp-channel-conf 01_553 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_2[4] origin:064-gtp-channel-conf 00_554 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_2[5] origin:064-gtp-channel-conf 01_554 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_2[6] origin:064-gtp-channel-conf 00_555 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_2[7] origin:064-gtp-channel-conf 01_555 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_2[8] origin:064-gtp-channel-conf 00_556 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_2[9] origin:064-gtp-channel-conf 01_556 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_3[0] origin:064-gtp-channel-conf 00_560 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_3[1] origin:064-gtp-channel-conf 01_560 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_3[2] origin:064-gtp-channel-conf 00_561 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_3[3] origin:064-gtp-channel-conf 01_561 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_3[4] origin:064-gtp-channel-conf 00_562 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_3[5] origin:064-gtp-channel-conf 01_562 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_3[6] origin:064-gtp-channel-conf 00_563 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_3[7] origin:064-gtp-channel-conf 01_563 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_3[8] origin:064-gtp-channel-conf 00_564 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_3[9] origin:064-gtp-channel-conf 01_564 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_4[0] origin:064-gtp-channel-conf 00_568 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_4[1] origin:064-gtp-channel-conf 01_568 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_4[2] origin:064-gtp-channel-conf 00_569 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_4[3] origin:064-gtp-channel-conf 01_569 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_4[4] origin:064-gtp-channel-conf 00_570 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_4[5] origin:064-gtp-channel-conf 01_570 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_4[6] origin:064-gtp-channel-conf 00_571 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_4[7] origin:064-gtp-channel-conf 01_571 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_4[8] origin:064-gtp-channel-conf 00_572 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_4[9] origin:064-gtp-channel-conf 01_572 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_ENABLE[0] origin:064-gtp-channel-conf 00_549 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_ENABLE[1] origin:064-gtp-channel-conf 01_549 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_ENABLE[2] origin:064-gtp-channel-conf 00_550 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_1_ENABLE[3] origin:064-gtp-channel-conf 01_550 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_1[0] origin:064-gtp-channel-conf 00_576 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_1[1] origin:064-gtp-channel-conf 01_576 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_1[2] origin:064-gtp-channel-conf 00_577 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_1[3] origin:064-gtp-channel-conf 01_577 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_1[4] origin:064-gtp-channel-conf 00_578 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_1[5] origin:064-gtp-channel-conf 01_578 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_1[6] origin:064-gtp-channel-conf 00_579 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_1[7] origin:064-gtp-channel-conf 01_579 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_1[8] origin:064-gtp-channel-conf 00_580 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_1[9] origin:064-gtp-channel-conf 01_580 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_2[0] origin:064-gtp-channel-conf 00_584 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_2[1] origin:064-gtp-channel-conf 01_584 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_2[2] origin:064-gtp-channel-conf 00_585 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_2[3] origin:064-gtp-channel-conf 01_585 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_2[4] origin:064-gtp-channel-conf 00_586 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_2[5] origin:064-gtp-channel-conf 01_586 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_2[6] origin:064-gtp-channel-conf 00_587 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_2[7] origin:064-gtp-channel-conf 01_587 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_2[8] origin:064-gtp-channel-conf 00_588 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_2[9] origin:064-gtp-channel-conf 01_588 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_3[0] origin:064-gtp-channel-conf 00_592 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_3[1] origin:064-gtp-channel-conf 01_592 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_3[2] origin:064-gtp-channel-conf 00_593 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_3[3] origin:064-gtp-channel-conf 01_593 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_3[4] origin:064-gtp-channel-conf 00_594 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_3[5] origin:064-gtp-channel-conf 01_594 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_3[6] origin:064-gtp-channel-conf 00_595 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_3[7] origin:064-gtp-channel-conf 01_595 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_3[8] origin:064-gtp-channel-conf 00_596 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_3[9] origin:064-gtp-channel-conf 01_596 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_4[0] origin:064-gtp-channel-conf 00_600 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_4[1] origin:064-gtp-channel-conf 01_600 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_4[2] origin:064-gtp-channel-conf 00_601 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_4[3] origin:064-gtp-channel-conf 01_601 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_4[4] origin:064-gtp-channel-conf 00_602 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_4[5] origin:064-gtp-channel-conf 01_602 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_4[6] origin:064-gtp-channel-conf 00_603 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_4[7] origin:064-gtp-channel-conf 01_603 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_4[8] origin:064-gtp-channel-conf 00_604 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_4[9] origin:064-gtp-channel-conf 01_604 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_ENABLE[0] origin:064-gtp-channel-conf 00_581 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_ENABLE[1] origin:064-gtp-channel-conf 01_581 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_ENABLE[2] origin:064-gtp-channel-conf 00_582 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_ENABLE[3] origin:064-gtp-channel-conf 01_582 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_2_USE origin:064-gtp-channel-conf 00_583 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_LEN[0] origin:064-gtp-channel-conf 00_589 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_COR_SEQ_LEN[1] origin:064-gtp-channel-conf 01_589 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.CLK_CORRECT_USE origin:064-gtp-channel-conf 00_551 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.DEC_MCOMMA_DETECT origin:064-gtp-channel-conf 01_494 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.DEC_PCOMMA_DETECT origin:064-gtp-channel-conf 00_495 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.DEC_VALID_COMMA_ONLY origin:064-gtp-channel-conf 00_494 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.DMONITOR_CFG[0] origin:064-gtp-channel-conf 02_368 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.DMONITOR_CFG[1] origin:064-gtp-channel-conf 03_368 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.DMONITOR_CFG[2] origin:064-gtp-channel-conf 02_369 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.DMONITOR_CFG[3] origin:064-gtp-channel-conf 03_369 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.DMONITOR_CFG[4] origin:064-gtp-channel-conf 02_370 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.DMONITOR_CFG[5] origin:064-gtp-channel-conf 03_370 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.DMONITOR_CFG[6] origin:064-gtp-channel-conf 02_371 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.DMONITOR_CFG[7] origin:064-gtp-channel-conf 03_371 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.DMONITOR_CFG[8] origin:064-gtp-channel-conf 02_372 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.DMONITOR_CFG[9] origin:064-gtp-channel-conf 03_372 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.DMONITOR_CFG[10] origin:064-gtp-channel-conf 02_373 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.DMONITOR_CFG[11] origin:064-gtp-channel-conf 03_373 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.DMONITOR_CFG[12] origin:064-gtp-channel-conf 02_374 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.DMONITOR_CFG[13] origin:064-gtp-channel-conf 03_374 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.DMONITOR_CFG[14] origin:064-gtp-channel-conf 02_375 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.DMONITOR_CFG[15] origin:064-gtp-channel-conf 03_375 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.DMONITOR_CFG[16] origin:064-gtp-channel-conf 02_376 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.DMONITOR_CFG[17] origin:064-gtp-channel-conf 03_376 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.DMONITOR_CFG[18] origin:064-gtp-channel-conf 02_377 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.DMONITOR_CFG[19] origin:064-gtp-channel-conf 03_377 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.DMONITOR_CFG[20] origin:064-gtp-channel-conf 02_378 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.DMONITOR_CFG[21] origin:064-gtp-channel-conf 03_378 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.DMONITOR_CFG[22] origin:064-gtp-channel-conf 02_379 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.DMONITOR_CFG[23] origin:064-gtp-channel-conf 03_379 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_CLK_PHASE_SEL[0] origin:064-gtp-channel-conf 03_463 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_CONTROL[0] origin:064-gtp-channel-conf 00_488 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_CONTROL[1] origin:064-gtp-channel-conf 01_488 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_CONTROL[2] origin:064-gtp-channel-conf 00_489 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_CONTROL[3] origin:064-gtp-channel-conf 01_489 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_CONTROL[4] origin:064-gtp-channel-conf 00_490 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_CONTROL[5] origin:064-gtp-channel-conf 01_490 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_ERRDET_EN origin:064-gtp-channel-conf 01_492 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_EYE_SCAN_EN origin:064-gtp-channel-conf 00_492 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_HORZ_OFFSET[0] origin:064-gtp-channel-conf 00_480 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_HORZ_OFFSET[1] origin:064-gtp-channel-conf 01_480 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_HORZ_OFFSET[2] origin:064-gtp-channel-conf 00_481 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_HORZ_OFFSET[3] origin:064-gtp-channel-conf 01_481 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_HORZ_OFFSET[4] origin:064-gtp-channel-conf 00_482 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_HORZ_OFFSET[5] origin:064-gtp-channel-conf 01_482 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_HORZ_OFFSET[6] origin:064-gtp-channel-conf 00_483 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_HORZ_OFFSET[7] origin:064-gtp-channel-conf 01_483 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_HORZ_OFFSET[8] origin:064-gtp-channel-conf 00_484 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_HORZ_OFFSET[9] origin:064-gtp-channel-conf 01_484 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_HORZ_OFFSET[10] origin:064-gtp-channel-conf 00_485 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_HORZ_OFFSET[11] origin:064-gtp-channel-conf 01_485 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_PMA_CFG[0] origin:064-gtp-channel-conf 02_624 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_PMA_CFG[1] origin:064-gtp-channel-conf 03_624 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_PMA_CFG[2] origin:064-gtp-channel-conf 02_625 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_PMA_CFG[3] origin:064-gtp-channel-conf 03_625 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_PMA_CFG[4] origin:064-gtp-channel-conf 02_626 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_PMA_CFG[5] origin:064-gtp-channel-conf 03_626 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_PMA_CFG[6] origin:064-gtp-channel-conf 02_627 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_PMA_CFG[7] origin:064-gtp-channel-conf 03_627 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_PMA_CFG[8] origin:064-gtp-channel-conf 02_628 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_PMA_CFG[9] origin:064-gtp-channel-conf 03_628 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_PRESCALE[0] origin:064-gtp-channel-conf 01_477 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_PRESCALE[1] origin:064-gtp-channel-conf 00_478 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_PRESCALE[2] origin:064-gtp-channel-conf 01_478 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_PRESCALE[3] origin:064-gtp-channel-conf 00_479 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_PRESCALE[4] origin:064-gtp-channel-conf 01_479 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[0] origin:064-gtp-channel-conf 00_392 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[1] origin:064-gtp-channel-conf 01_392 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[2] origin:064-gtp-channel-conf 00_393 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[3] origin:064-gtp-channel-conf 01_393 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[4] origin:064-gtp-channel-conf 00_394 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[5] origin:064-gtp-channel-conf 01_394 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[6] origin:064-gtp-channel-conf 00_395 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[7] origin:064-gtp-channel-conf 01_395 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[8] origin:064-gtp-channel-conf 00_396 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[9] origin:064-gtp-channel-conf 01_396 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[10] origin:064-gtp-channel-conf 00_397 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[11] origin:064-gtp-channel-conf 01_397 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[12] origin:064-gtp-channel-conf 00_398 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[13] origin:064-gtp-channel-conf 01_398 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[14] origin:064-gtp-channel-conf 00_399 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[15] origin:064-gtp-channel-conf 01_399 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[16] origin:064-gtp-channel-conf 00_400 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[17] origin:064-gtp-channel-conf 01_400 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[18] origin:064-gtp-channel-conf 00_401 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[19] origin:064-gtp-channel-conf 01_401 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[20] origin:064-gtp-channel-conf 00_402 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[21] origin:064-gtp-channel-conf 01_402 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[22] origin:064-gtp-channel-conf 00_403 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[23] origin:064-gtp-channel-conf 01_403 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[24] origin:064-gtp-channel-conf 00_404 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[25] origin:064-gtp-channel-conf 01_404 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[26] origin:064-gtp-channel-conf 00_405 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[27] origin:064-gtp-channel-conf 01_405 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[28] origin:064-gtp-channel-conf 00_406 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[29] origin:064-gtp-channel-conf 01_406 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[30] origin:064-gtp-channel-conf 00_407 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[31] origin:064-gtp-channel-conf 01_407 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[32] origin:064-gtp-channel-conf 00_408 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[33] origin:064-gtp-channel-conf 01_408 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[34] origin:064-gtp-channel-conf 00_409 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[35] origin:064-gtp-channel-conf 01_409 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[36] origin:064-gtp-channel-conf 00_410 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[37] origin:064-gtp-channel-conf 01_410 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[38] origin:064-gtp-channel-conf 00_411 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[39] origin:064-gtp-channel-conf 01_411 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[40] origin:064-gtp-channel-conf 00_412 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[41] origin:064-gtp-channel-conf 01_412 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[42] origin:064-gtp-channel-conf 00_413 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[43] origin:064-gtp-channel-conf 01_413 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[44] origin:064-gtp-channel-conf 00_414 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[45] origin:064-gtp-channel-conf 01_414 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[46] origin:064-gtp-channel-conf 00_415 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[47] origin:064-gtp-channel-conf 01_415 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[48] origin:064-gtp-channel-conf 00_416 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[49] origin:064-gtp-channel-conf 01_416 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[50] origin:064-gtp-channel-conf 00_417 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[51] origin:064-gtp-channel-conf 01_417 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[52] origin:064-gtp-channel-conf 00_418 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[53] origin:064-gtp-channel-conf 01_418 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[54] origin:064-gtp-channel-conf 00_419 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[55] origin:064-gtp-channel-conf 01_419 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[56] origin:064-gtp-channel-conf 00_420 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[57] origin:064-gtp-channel-conf 01_420 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[58] origin:064-gtp-channel-conf 00_421 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[59] origin:064-gtp-channel-conf 01_421 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[60] origin:064-gtp-channel-conf 00_422 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[61] origin:064-gtp-channel-conf 01_422 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[62] origin:064-gtp-channel-conf 00_423 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[63] origin:064-gtp-channel-conf 01_423 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[64] origin:064-gtp-channel-conf 00_424 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[65] origin:064-gtp-channel-conf 01_424 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[66] origin:064-gtp-channel-conf 00_425 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[67] origin:064-gtp-channel-conf 01_425 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[68] origin:064-gtp-channel-conf 00_426 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[69] origin:064-gtp-channel-conf 01_426 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[70] origin:064-gtp-channel-conf 00_427 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[71] origin:064-gtp-channel-conf 01_427 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[72] origin:064-gtp-channel-conf 00_428 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[73] origin:064-gtp-channel-conf 01_428 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[74] origin:064-gtp-channel-conf 00_429 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[75] origin:064-gtp-channel-conf 01_429 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[76] origin:064-gtp-channel-conf 00_430 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[77] origin:064-gtp-channel-conf 01_430 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[78] origin:064-gtp-channel-conf 00_431 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUAL_MASK[79] origin:064-gtp-channel-conf 01_431 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[0] origin:064-gtp-channel-conf 00_352 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[1] origin:064-gtp-channel-conf 01_352 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[2] origin:064-gtp-channel-conf 00_353 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[3] origin:064-gtp-channel-conf 01_353 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[4] origin:064-gtp-channel-conf 00_354 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[5] origin:064-gtp-channel-conf 01_354 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[6] origin:064-gtp-channel-conf 00_355 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[7] origin:064-gtp-channel-conf 01_355 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[8] origin:064-gtp-channel-conf 00_356 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[9] origin:064-gtp-channel-conf 01_356 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[10] origin:064-gtp-channel-conf 00_357 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[11] origin:064-gtp-channel-conf 01_357 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[12] origin:064-gtp-channel-conf 00_358 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[13] origin:064-gtp-channel-conf 01_358 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[14] origin:064-gtp-channel-conf 00_359 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[15] origin:064-gtp-channel-conf 01_359 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[16] origin:064-gtp-channel-conf 00_360 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[17] origin:064-gtp-channel-conf 01_360 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[18] origin:064-gtp-channel-conf 00_361 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[19] origin:064-gtp-channel-conf 01_361 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[20] origin:064-gtp-channel-conf 00_362 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[21] origin:064-gtp-channel-conf 01_362 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[22] origin:064-gtp-channel-conf 00_363 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[23] origin:064-gtp-channel-conf 01_363 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[24] origin:064-gtp-channel-conf 00_364 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[25] origin:064-gtp-channel-conf 01_364 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[26] origin:064-gtp-channel-conf 00_365 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[27] origin:064-gtp-channel-conf 01_365 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[28] origin:064-gtp-channel-conf 00_366 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[29] origin:064-gtp-channel-conf 01_366 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[30] origin:064-gtp-channel-conf 00_367 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[31] origin:064-gtp-channel-conf 01_367 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[32] origin:064-gtp-channel-conf 00_368 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[33] origin:064-gtp-channel-conf 01_368 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[34] origin:064-gtp-channel-conf 00_369 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[35] origin:064-gtp-channel-conf 01_369 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[36] origin:064-gtp-channel-conf 00_370 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[37] origin:064-gtp-channel-conf 01_370 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[38] origin:064-gtp-channel-conf 00_371 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[39] origin:064-gtp-channel-conf 01_371 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[40] origin:064-gtp-channel-conf 00_372 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[41] origin:064-gtp-channel-conf 01_372 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[42] origin:064-gtp-channel-conf 00_373 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[43] origin:064-gtp-channel-conf 01_373 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[44] origin:064-gtp-channel-conf 00_374 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[45] origin:064-gtp-channel-conf 01_374 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[46] origin:064-gtp-channel-conf 00_375 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[47] origin:064-gtp-channel-conf 01_375 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[48] origin:064-gtp-channel-conf 00_376 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[49] origin:064-gtp-channel-conf 01_376 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[50] origin:064-gtp-channel-conf 00_377 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[51] origin:064-gtp-channel-conf 01_377 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[52] origin:064-gtp-channel-conf 00_378 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[53] origin:064-gtp-channel-conf 01_378 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[54] origin:064-gtp-channel-conf 00_379 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[55] origin:064-gtp-channel-conf 01_379 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[56] origin:064-gtp-channel-conf 00_380 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[57] origin:064-gtp-channel-conf 01_380 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[58] origin:064-gtp-channel-conf 00_381 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[59] origin:064-gtp-channel-conf 01_381 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[60] origin:064-gtp-channel-conf 00_382 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[61] origin:064-gtp-channel-conf 01_382 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[62] origin:064-gtp-channel-conf 00_383 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[63] origin:064-gtp-channel-conf 01_383 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[64] origin:064-gtp-channel-conf 00_384 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[65] origin:064-gtp-channel-conf 01_384 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[66] origin:064-gtp-channel-conf 00_385 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[67] origin:064-gtp-channel-conf 01_385 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[68] origin:064-gtp-channel-conf 00_386 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[69] origin:064-gtp-channel-conf 01_386 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[70] origin:064-gtp-channel-conf 00_387 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[71] origin:064-gtp-channel-conf 01_387 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[72] origin:064-gtp-channel-conf 00_388 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[73] origin:064-gtp-channel-conf 01_388 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[74] origin:064-gtp-channel-conf 00_389 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[75] origin:064-gtp-channel-conf 01_389 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[76] origin:064-gtp-channel-conf 00_390 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[77] origin:064-gtp-channel-conf 01_390 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[78] origin:064-gtp-channel-conf 00_391 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_QUALIFIER[79] origin:064-gtp-channel-conf 01_391 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[0] origin:064-gtp-channel-conf 00_432 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[1] origin:064-gtp-channel-conf 01_432 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[2] origin:064-gtp-channel-conf 00_433 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[3] origin:064-gtp-channel-conf 01_433 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[4] origin:064-gtp-channel-conf 00_434 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[5] origin:064-gtp-channel-conf 01_434 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[6] origin:064-gtp-channel-conf 00_435 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[7] origin:064-gtp-channel-conf 01_435 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[8] origin:064-gtp-channel-conf 00_436 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[9] origin:064-gtp-channel-conf 01_436 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[10] origin:064-gtp-channel-conf 00_437 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[11] origin:064-gtp-channel-conf 01_437 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[12] origin:064-gtp-channel-conf 00_438 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[13] origin:064-gtp-channel-conf 01_438 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[14] origin:064-gtp-channel-conf 00_439 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[15] origin:064-gtp-channel-conf 01_439 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[16] origin:064-gtp-channel-conf 00_440 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[17] origin:064-gtp-channel-conf 01_440 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[18] origin:064-gtp-channel-conf 00_441 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[19] origin:064-gtp-channel-conf 01_441 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[20] origin:064-gtp-channel-conf 00_442 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[21] origin:064-gtp-channel-conf 01_442 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[22] origin:064-gtp-channel-conf 00_443 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[23] origin:064-gtp-channel-conf 01_443 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[24] origin:064-gtp-channel-conf 00_444 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[25] origin:064-gtp-channel-conf 01_444 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[26] origin:064-gtp-channel-conf 00_445 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[27] origin:064-gtp-channel-conf 01_445 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[28] origin:064-gtp-channel-conf 00_446 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[29] origin:064-gtp-channel-conf 01_446 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[30] origin:064-gtp-channel-conf 00_447 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[31] origin:064-gtp-channel-conf 01_447 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[32] origin:064-gtp-channel-conf 00_448 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[33] origin:064-gtp-channel-conf 01_448 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[34] origin:064-gtp-channel-conf 00_449 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[35] origin:064-gtp-channel-conf 01_449 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[36] origin:064-gtp-channel-conf 00_450 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[37] origin:064-gtp-channel-conf 01_450 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[38] origin:064-gtp-channel-conf 00_451 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[39] origin:064-gtp-channel-conf 01_451 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[40] origin:064-gtp-channel-conf 00_452 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[41] origin:064-gtp-channel-conf 01_452 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[42] origin:064-gtp-channel-conf 00_453 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[43] origin:064-gtp-channel-conf 01_453 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[44] origin:064-gtp-channel-conf 00_454 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[45] origin:064-gtp-channel-conf 01_454 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[46] origin:064-gtp-channel-conf 00_455 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[47] origin:064-gtp-channel-conf 01_455 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[48] origin:064-gtp-channel-conf 00_456 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[49] origin:064-gtp-channel-conf 01_456 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[50] origin:064-gtp-channel-conf 00_457 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[51] origin:064-gtp-channel-conf 01_457 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[52] origin:064-gtp-channel-conf 00_458 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[53] origin:064-gtp-channel-conf 01_458 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[54] origin:064-gtp-channel-conf 00_459 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[55] origin:064-gtp-channel-conf 01_459 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[56] origin:064-gtp-channel-conf 00_460 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[57] origin:064-gtp-channel-conf 01_460 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[58] origin:064-gtp-channel-conf 00_461 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[59] origin:064-gtp-channel-conf 01_461 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[60] origin:064-gtp-channel-conf 00_462 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[61] origin:064-gtp-channel-conf 01_462 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[62] origin:064-gtp-channel-conf 00_463 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[63] origin:064-gtp-channel-conf 01_463 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[64] origin:064-gtp-channel-conf 00_464 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[65] origin:064-gtp-channel-conf 01_464 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[66] origin:064-gtp-channel-conf 00_465 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[67] origin:064-gtp-channel-conf 01_465 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[68] origin:064-gtp-channel-conf 00_466 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[69] origin:064-gtp-channel-conf 01_466 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[70] origin:064-gtp-channel-conf 00_467 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[71] origin:064-gtp-channel-conf 01_467 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[72] origin:064-gtp-channel-conf 00_468 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[73] origin:064-gtp-channel-conf 01_468 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[74] origin:064-gtp-channel-conf 00_469 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[75] origin:064-gtp-channel-conf 01_469 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[76] origin:064-gtp-channel-conf 00_470 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[77] origin:064-gtp-channel-conf 01_470 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[78] origin:064-gtp-channel-conf 00_471 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_SDATA_MASK[79] origin:064-gtp-channel-conf 01_471 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_VERT_OFFSET[0] origin:064-gtp-channel-conf 00_472 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_VERT_OFFSET[1] origin:064-gtp-channel-conf 01_472 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_VERT_OFFSET[2] origin:064-gtp-channel-conf 00_473 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_VERT_OFFSET[3] origin:064-gtp-channel-conf 01_473 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_VERT_OFFSET[4] origin:064-gtp-channel-conf 00_474 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_VERT_OFFSET[5] origin:064-gtp-channel-conf 01_474 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_VERT_OFFSET[6] origin:064-gtp-channel-conf 00_475 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_VERT_OFFSET[7] origin:064-gtp-channel-conf 01_475 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ES_VERT_OFFSET[8] origin:064-gtp-channel-conf 00_476 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.FTS_DESKEW_SEQ_ENABLE[0] origin:064-gtp-channel-conf 00_662 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.FTS_DESKEW_SEQ_ENABLE[1] origin:064-gtp-channel-conf 01_662 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.FTS_DESKEW_SEQ_ENABLE[2] origin:064-gtp-channel-conf 00_663 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.FTS_DESKEW_SEQ_ENABLE[3] origin:064-gtp-channel-conf 01_663 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.FTS_LANE_DESKEW_CFG[0] origin:064-gtp-channel-conf 00_654 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.FTS_LANE_DESKEW_CFG[1] origin:064-gtp-channel-conf 01_654 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.FTS_LANE_DESKEW_CFG[2] origin:064-gtp-channel-conf 00_655 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.FTS_LANE_DESKEW_CFG[3] origin:064-gtp-channel-conf 01_655 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.FTS_LANE_DESKEW_EN origin:064-gtp-channel-conf 01_653 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.GEARBOX_MODE[0] origin:064-gtp-channel-conf 00_224 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.GEARBOX_MODE[1] origin:064-gtp-channel-conf 01_224 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.GEARBOX_MODE[2] origin:064-gtp-channel-conf 00_225 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.IN_USE origin:064-gtp-channel-conf 00_00 00_01 00_47 00_52 00_53 00_65 01_01 01_47 02_129 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.LOOPBACK_CFG[0] origin:064-gtp-channel-conf 02_20 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.OUTREFCLK_SEL_INV[0] origin:064-gtp-channel-conf 00_149 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.OUTREFCLK_SEL_INV[1] origin:064-gtp-channel-conf 01_149 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PCS_PCIE_EN origin:064-gtp-channel-conf 00_216 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[0] origin:064-gtp-channel-conf 02_184 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[1] origin:064-gtp-channel-conf 03_184 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[2] origin:064-gtp-channel-conf 02_185 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[3] origin:064-gtp-channel-conf 03_185 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[4] origin:064-gtp-channel-conf 02_186 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[5] origin:064-gtp-channel-conf 03_186 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[6] origin:064-gtp-channel-conf 02_187 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[7] origin:064-gtp-channel-conf 03_187 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[8] origin:064-gtp-channel-conf 02_188 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[9] origin:064-gtp-channel-conf 03_188 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[10] origin:064-gtp-channel-conf 02_189 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[11] origin:064-gtp-channel-conf 03_189 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[12] origin:064-gtp-channel-conf 02_190 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[13] origin:064-gtp-channel-conf 03_190 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[14] origin:064-gtp-channel-conf 02_191 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[15] origin:064-gtp-channel-conf 03_191 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[16] origin:064-gtp-channel-conf 02_192 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[17] origin:064-gtp-channel-conf 03_192 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[18] origin:064-gtp-channel-conf 02_193 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[19] origin:064-gtp-channel-conf 03_193 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[20] origin:064-gtp-channel-conf 02_194 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[21] origin:064-gtp-channel-conf 03_194 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[22] origin:064-gtp-channel-conf 02_195 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[23] origin:064-gtp-channel-conf 03_195 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[24] origin:064-gtp-channel-conf 02_196 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[25] origin:064-gtp-channel-conf 03_196 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[26] origin:064-gtp-channel-conf 02_197 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[27] origin:064-gtp-channel-conf 03_197 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[28] origin:064-gtp-channel-conf 02_198 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[29] origin:064-gtp-channel-conf 03_198 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[30] origin:064-gtp-channel-conf 02_199 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[31] origin:064-gtp-channel-conf 03_199 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[32] origin:064-gtp-channel-conf 02_200 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[33] origin:064-gtp-channel-conf 03_200 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[34] origin:064-gtp-channel-conf 02_201 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[35] origin:064-gtp-channel-conf 03_201 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[36] origin:064-gtp-channel-conf 02_202 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[37] origin:064-gtp-channel-conf 03_202 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[38] origin:064-gtp-channel-conf 02_203 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[39] origin:064-gtp-channel-conf 03_203 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[40] origin:064-gtp-channel-conf 02_204 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[41] origin:064-gtp-channel-conf 03_204 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[42] origin:064-gtp-channel-conf 02_205 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[43] origin:064-gtp-channel-conf 03_205 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[44] origin:064-gtp-channel-conf 02_206 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[45] origin:064-gtp-channel-conf 03_206 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[46] origin:064-gtp-channel-conf 02_207 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PCS_RSVD_ATTR[47] origin:064-gtp-channel-conf 03_207 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PD_TRANS_TIME_FROM_P2[0] origin:064-gtp-channel-conf 01_216 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PD_TRANS_TIME_FROM_P2[1] origin:064-gtp-channel-conf 00_217 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PD_TRANS_TIME_FROM_P2[2] origin:064-gtp-channel-conf 01_217 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PD_TRANS_TIME_FROM_P2[3] origin:064-gtp-channel-conf 00_218 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PD_TRANS_TIME_FROM_P2[4] origin:064-gtp-channel-conf 01_218 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PD_TRANS_TIME_FROM_P2[5] origin:064-gtp-channel-conf 00_219 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PD_TRANS_TIME_FROM_P2[6] origin:064-gtp-channel-conf 01_219 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PD_TRANS_TIME_FROM_P2[7] origin:064-gtp-channel-conf 00_220 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PD_TRANS_TIME_FROM_P2[8] origin:064-gtp-channel-conf 01_220 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PD_TRANS_TIME_FROM_P2[9] origin:064-gtp-channel-conf 00_221 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PD_TRANS_TIME_FROM_P2[10] origin:064-gtp-channel-conf 01_221 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PD_TRANS_TIME_FROM_P2[11] origin:064-gtp-channel-conf 00_222 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PD_TRANS_TIME_NONE_P2[0] origin:064-gtp-channel-conf 00_208 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PD_TRANS_TIME_NONE_P2[1] origin:064-gtp-channel-conf 01_208 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PD_TRANS_TIME_NONE_P2[2] origin:064-gtp-channel-conf 00_209 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PD_TRANS_TIME_NONE_P2[3] origin:064-gtp-channel-conf 01_209 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PD_TRANS_TIME_NONE_P2[4] origin:064-gtp-channel-conf 00_210 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PD_TRANS_TIME_NONE_P2[5] origin:064-gtp-channel-conf 01_210 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PD_TRANS_TIME_NONE_P2[6] origin:064-gtp-channel-conf 00_211 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PD_TRANS_TIME_NONE_P2[7] origin:064-gtp-channel-conf 01_211 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PD_TRANS_TIME_TO_P2[0] origin:064-gtp-channel-conf 00_212 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PD_TRANS_TIME_TO_P2[1] origin:064-gtp-channel-conf 01_212 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PD_TRANS_TIME_TO_P2[2] origin:064-gtp-channel-conf 00_213 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PD_TRANS_TIME_TO_P2[3] origin:064-gtp-channel-conf 01_213 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PD_TRANS_TIME_TO_P2[4] origin:064-gtp-channel-conf 00_214 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PD_TRANS_TIME_TO_P2[5] origin:064-gtp-channel-conf 01_214 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PD_TRANS_TIME_TO_P2[6] origin:064-gtp-channel-conf 00_215 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PD_TRANS_TIME_TO_P2[7] origin:064-gtp-channel-conf 01_215 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PMA_LOOPBACK_CFG[0] origin:064-gtp-channel-conf 01_207 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PMA_RSV[0] origin:064-gtp-channel-conf 02_520 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PMA_RSV[1] origin:064-gtp-channel-conf 03_520 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PMA_RSV[2] origin:064-gtp-channel-conf 02_521 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PMA_RSV[3] origin:064-gtp-channel-conf 03_521 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PMA_RSV[4] origin:064-gtp-channel-conf 02_522 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PMA_RSV[5] origin:064-gtp-channel-conf 03_522 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PMA_RSV[6] origin:064-gtp-channel-conf 02_523 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PMA_RSV[7] origin:064-gtp-channel-conf 03_523 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PMA_RSV[8] origin:064-gtp-channel-conf 02_524 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PMA_RSV[9] origin:064-gtp-channel-conf 03_524 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PMA_RSV[10] origin:064-gtp-channel-conf 02_525 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PMA_RSV[11] origin:064-gtp-channel-conf 03_525 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PMA_RSV[12] origin:064-gtp-channel-conf 02_526 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PMA_RSV[13] origin:064-gtp-channel-conf 03_526 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PMA_RSV[14] origin:064-gtp-channel-conf 02_527 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PMA_RSV[15] origin:064-gtp-channel-conf 03_527 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PMA_RSV[16] origin:064-gtp-channel-conf 02_528 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PMA_RSV[17] origin:064-gtp-channel-conf 03_528 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PMA_RSV[18] origin:064-gtp-channel-conf 02_529 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PMA_RSV[19] origin:064-gtp-channel-conf 03_529 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PMA_RSV[20] origin:064-gtp-channel-conf 02_530 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PMA_RSV[21] origin:064-gtp-channel-conf 03_530 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PMA_RSV[22] origin:064-gtp-channel-conf 02_531 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PMA_RSV[23] origin:064-gtp-channel-conf 03_531 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PMA_RSV[24] origin:064-gtp-channel-conf 02_532 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PMA_RSV[25] origin:064-gtp-channel-conf 03_532 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PMA_RSV[26] origin:064-gtp-channel-conf 02_533 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PMA_RSV[27] origin:064-gtp-channel-conf 03_533 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PMA_RSV[28] origin:064-gtp-channel-conf 02_534 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PMA_RSV[29] origin:064-gtp-channel-conf 03_534 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PMA_RSV[30] origin:064-gtp-channel-conf 02_535 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PMA_RSV[31] origin:064-gtp-channel-conf 03_535 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PMA_RSV2[0] origin:064-gtp-channel-conf 02_336 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PMA_RSV2[1] origin:064-gtp-channel-conf 03_336 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PMA_RSV2[2] origin:064-gtp-channel-conf 02_337 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PMA_RSV2[3] origin:064-gtp-channel-conf 03_337 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PMA_RSV2[4] origin:064-gtp-channel-conf 02_338 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PMA_RSV2[5] origin:064-gtp-channel-conf 03_338 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PMA_RSV2[6] origin:064-gtp-channel-conf 02_339 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PMA_RSV2[7] origin:064-gtp-channel-conf 03_339 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PMA_RSV2[8] origin:064-gtp-channel-conf 02_340 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PMA_RSV2[9] origin:064-gtp-channel-conf 03_340 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PMA_RSV2[10] origin:064-gtp-channel-conf 02_341 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PMA_RSV2[11] origin:064-gtp-channel-conf 03_341 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PMA_RSV2[12] origin:064-gtp-channel-conf 02_342 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PMA_RSV2[13] origin:064-gtp-channel-conf 03_342 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PMA_RSV2[14] origin:064-gtp-channel-conf 02_343 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PMA_RSV2[15] origin:064-gtp-channel-conf 03_343 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PMA_RSV2[16] origin:064-gtp-channel-conf 02_344 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PMA_RSV2[17] origin:064-gtp-channel-conf 03_344 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PMA_RSV2[18] origin:064-gtp-channel-conf 02_345 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PMA_RSV2[19] origin:064-gtp-channel-conf 03_345 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PMA_RSV2[20] origin:064-gtp-channel-conf 02_346 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PMA_RSV2[21] origin:064-gtp-channel-conf 03_346 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PMA_RSV2[22] origin:064-gtp-channel-conf 02_347 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PMA_RSV2[23] origin:064-gtp-channel-conf 03_347 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PMA_RSV2[24] origin:064-gtp-channel-conf 02_348 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PMA_RSV2[25] origin:064-gtp-channel-conf 03_348 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PMA_RSV2[26] origin:064-gtp-channel-conf 02_349 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PMA_RSV2[27] origin:064-gtp-channel-conf 03_349 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PMA_RSV2[28] origin:064-gtp-channel-conf 02_350 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PMA_RSV2[29] origin:064-gtp-channel-conf 03_350 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PMA_RSV2[30] origin:064-gtp-channel-conf 02_351 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PMA_RSV2[31] origin:064-gtp-channel-conf 03_351 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PMA_RSV3[0] origin:064-gtp-channel-conf 02_288 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PMA_RSV3[1] origin:064-gtp-channel-conf 03_288 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PMA_RSV4[0] origin:064-gtp-channel-conf 02_156 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PMA_RSV4[1] origin:064-gtp-channel-conf 03_156 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PMA_RSV4[2] origin:064-gtp-channel-conf 02_157 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PMA_RSV4[3] origin:064-gtp-channel-conf 03_157 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PMA_RSV5[0] origin:064-gtp-channel-conf 03_159 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PMA_RSV6[0] origin:064-gtp-channel-conf 02_303 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.PMA_RSV7[0] origin:064-gtp-channel-conf 03_303 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_BIAS_CFG[0] origin:064-gtp-channel-conf 02_112 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_BIAS_CFG[1] origin:064-gtp-channel-conf 03_112 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_BIAS_CFG[2] origin:064-gtp-channel-conf 02_113 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_BIAS_CFG[3] origin:064-gtp-channel-conf 03_113 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_BIAS_CFG[4] origin:064-gtp-channel-conf 02_114 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_BIAS_CFG[5] origin:064-gtp-channel-conf 03_114 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_BIAS_CFG[6] origin:064-gtp-channel-conf 02_115 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_BIAS_CFG[7] origin:064-gtp-channel-conf 03_115 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_BIAS_CFG[8] origin:064-gtp-channel-conf 02_116 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_BIAS_CFG[9] origin:064-gtp-channel-conf 03_116 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_BIAS_CFG[10] origin:064-gtp-channel-conf 02_117 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_BIAS_CFG[11] origin:064-gtp-channel-conf 03_117 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_BIAS_CFG[12] origin:064-gtp-channel-conf 02_118 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_BIAS_CFG[13] origin:064-gtp-channel-conf 03_118 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_BIAS_CFG[14] origin:064-gtp-channel-conf 02_119 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_BIAS_CFG[15] origin:064-gtp-channel-conf 03_119 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_BUFFER_CFG[0] origin:064-gtp-channel-conf 02_536 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_BUFFER_CFG[1] origin:064-gtp-channel-conf 03_536 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_BUFFER_CFG[2] origin:064-gtp-channel-conf 02_537 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_BUFFER_CFG[3] origin:064-gtp-channel-conf 03_537 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_BUFFER_CFG[4] origin:064-gtp-channel-conf 02_538 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_BUFFER_CFG[5] origin:064-gtp-channel-conf 03_538 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_CLKMUX_EN[0] origin:064-gtp-channel-conf 02_128 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_CM_SEL[0] origin:064-gtp-channel-conf 00_138 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_CM_SEL[1] origin:064-gtp-channel-conf 01_138 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_CM_TRIM[0] origin:064-gtp-channel-conf 02_304 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_CM_TRIM[1] origin:064-gtp-channel-conf 03_304 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_CM_TRIM[2] origin:064-gtp-channel-conf 02_305 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_CM_TRIM[3] origin:064-gtp-channel-conf 03_305 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_DATA_WIDTH[0] origin:064-gtp-channel-conf 01_141 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_DATA_WIDTH[1] origin:064-gtp-channel-conf 00_142 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_DATA_WIDTH[2] origin:064-gtp-channel-conf 01_142 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_DDI_SEL[0] origin:064-gtp-channel-conf 00_696 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_DDI_SEL[1] origin:064-gtp-channel-conf 01_696 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_DDI_SEL[2] origin:064-gtp-channel-conf 00_697 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_DDI_SEL[3] origin:064-gtp-channel-conf 01_697 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_DDI_SEL[4] origin:064-gtp-channel-conf 00_698 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_DDI_SEL[5] origin:064-gtp-channel-conf 01_698 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_DEBUG_CFG[0] origin:064-gtp-channel-conf 02_616 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_DEBUG_CFG[1] origin:064-gtp-channel-conf 03_616 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_DEBUG_CFG[2] origin:064-gtp-channel-conf 02_617 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_DEBUG_CFG[3] origin:064-gtp-channel-conf 03_617 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_DEBUG_CFG[4] origin:064-gtp-channel-conf 02_618 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_DEBUG_CFG[5] origin:064-gtp-channel-conf 03_618 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_DEBUG_CFG[6] origin:064-gtp-channel-conf 02_619 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_DEBUG_CFG[7] origin:064-gtp-channel-conf 03_619 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_DEBUG_CFG[8] origin:064-gtp-channel-conf 02_620 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_DEBUG_CFG[9] origin:064-gtp-channel-conf 03_620 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_DEBUG_CFG[10] origin:064-gtp-channel-conf 02_621 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_DEBUG_CFG[11] origin:064-gtp-channel-conf 03_621 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_DEBUG_CFG[12] origin:064-gtp-channel-conf 02_622 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_DEBUG_CFG[13] origin:064-gtp-channel-conf 03_622 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_DEFER_RESET_BUF_EN origin:064-gtp-channel-conf 02_552 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_DISPERR_SEQ_MATCH origin:064-gtp-channel-conf 01_495 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_OS_CFG[0] origin:064-gtp-channel-conf 00_288 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_OS_CFG[1] origin:064-gtp-channel-conf 01_288 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_OS_CFG[2] origin:064-gtp-channel-conf 00_289 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_OS_CFG[3] origin:064-gtp-channel-conf 01_289 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_OS_CFG[4] origin:064-gtp-channel-conf 00_290 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_OS_CFG[5] origin:064-gtp-channel-conf 01_290 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_OS_CFG[6] origin:064-gtp-channel-conf 00_291 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_OS_CFG[7] origin:064-gtp-channel-conf 01_291 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_OS_CFG[8] origin:064-gtp-channel-conf 00_292 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_OS_CFG[9] origin:064-gtp-channel-conf 01_292 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_OS_CFG[10] origin:064-gtp-channel-conf 00_293 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_OS_CFG[11] origin:064-gtp-channel-conf 01_293 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_OS_CFG[12] origin:064-gtp-channel-conf 00_294 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_SIG_VALID_DLY[0] origin:064-gtp-channel-conf 00_524 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_SIG_VALID_DLY[1] origin:064-gtp-channel-conf 01_524 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_SIG_VALID_DLY[2] origin:064-gtp-channel-conf 00_525 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_SIG_VALID_DLY[3] origin:064-gtp-channel-conf 01_525 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_SIG_VALID_DLY[4] origin:064-gtp-channel-conf 00_526 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_XCLK_SEL.RXUSR origin:064-gtp-channel-conf 00_143 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_CLK25_DIV[0] origin:064-gtp-channel-conf 00_139 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_CLK25_DIV[1] origin:064-gtp-channel-conf 01_139 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_CLK25_DIV[2] origin:064-gtp-channel-conf 00_140 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_CLK25_DIV[3] origin:064-gtp-channel-conf 01_140 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RX_CLK25_DIV[4] origin:064-gtp-channel-conf 00_141 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXBUF_ADDR_MODE.FAST origin:064-gtp-channel-conf 03_555 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXBUF_EIDLE_HI_CNT[0] origin:064-gtp-channel-conf 02_558 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXBUF_EIDLE_HI_CNT[1] origin:064-gtp-channel-conf 03_558 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXBUF_EIDLE_HI_CNT[2] origin:064-gtp-channel-conf 02_559 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXBUF_EIDLE_HI_CNT[3] origin:064-gtp-channel-conf 03_559 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXBUF_EIDLE_LO_CNT[0] origin:064-gtp-channel-conf 02_556 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXBUF_EIDLE_LO_CNT[1] origin:064-gtp-channel-conf 03_556 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXBUF_EIDLE_LO_CNT[2] origin:064-gtp-channel-conf 02_557 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXBUF_EIDLE_LO_CNT[3] origin:064-gtp-channel-conf 03_557 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXBUF_EN origin:064-gtp-channel-conf 02_11 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXBUF_RESET_ON_CB_CHANGE origin:064-gtp-channel-conf 02_560 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXBUF_RESET_ON_COMMAALIGN origin:064-gtp-channel-conf 02_561 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXBUF_RESET_ON_EIDLE origin:064-gtp-channel-conf 02_547 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXBUF_RESET_ON_RATE_CHANGE origin:064-gtp-channel-conf 03_560 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXBUF_THRESH_OVFLW[0] origin:064-gtp-channel-conf 03_552 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXBUF_THRESH_OVFLW[1] origin:064-gtp-channel-conf 02_553 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXBUF_THRESH_OVFLW[2] origin:064-gtp-channel-conf 03_553 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXBUF_THRESH_OVFLW[3] origin:064-gtp-channel-conf 02_554 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXBUF_THRESH_OVFLW[4] origin:064-gtp-channel-conf 03_554 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXBUF_THRESH_OVFLW[5] origin:064-gtp-channel-conf 02_555 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXBUF_THRESH_OVRD origin:064-gtp-channel-conf 02_548 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXBUF_THRESH_UNDFLW[0] origin:064-gtp-channel-conf 02_544 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXBUF_THRESH_UNDFLW[1] origin:064-gtp-channel-conf 03_544 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXBUF_THRESH_UNDFLW[2] origin:064-gtp-channel-conf 02_545 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXBUF_THRESH_UNDFLW[3] origin:064-gtp-channel-conf 03_545 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXBUF_THRESH_UNDFLW[4] origin:064-gtp-channel-conf 02_546 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXBUF_THRESH_UNDFLW[5] origin:064-gtp-channel-conf 03_546 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXBUFRESET_TIME[0] origin:064-gtp-channel-conf 01_101 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXBUFRESET_TIME[1] origin:064-gtp-channel-conf 00_102 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXBUFRESET_TIME[2] origin:064-gtp-channel-conf 01_102 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXBUFRESET_TIME[3] origin:064-gtp-channel-conf 00_103 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXBUFRESET_TIME[4] origin:064-gtp-channel-conf 01_103 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[0] origin:064-gtp-channel-conf 02_640 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[1] origin:064-gtp-channel-conf 03_640 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[2] origin:064-gtp-channel-conf 02_641 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[3] origin:064-gtp-channel-conf 03_641 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[4] origin:064-gtp-channel-conf 02_642 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[5] origin:064-gtp-channel-conf 03_642 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[6] origin:064-gtp-channel-conf 02_643 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[7] origin:064-gtp-channel-conf 03_643 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[8] origin:064-gtp-channel-conf 02_644 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[9] origin:064-gtp-channel-conf 03_644 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[10] origin:064-gtp-channel-conf 02_645 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[11] origin:064-gtp-channel-conf 03_645 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[12] origin:064-gtp-channel-conf 02_646 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[13] origin:064-gtp-channel-conf 03_646 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[14] origin:064-gtp-channel-conf 02_647 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[15] origin:064-gtp-channel-conf 03_647 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[16] origin:064-gtp-channel-conf 02_648 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[17] origin:064-gtp-channel-conf 03_648 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[18] origin:064-gtp-channel-conf 02_649 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[19] origin:064-gtp-channel-conf 03_649 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[20] origin:064-gtp-channel-conf 02_650 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[21] origin:064-gtp-channel-conf 03_650 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[22] origin:064-gtp-channel-conf 02_651 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[23] origin:064-gtp-channel-conf 03_651 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[24] origin:064-gtp-channel-conf 02_652 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[25] origin:064-gtp-channel-conf 03_652 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[26] origin:064-gtp-channel-conf 02_653 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[27] origin:064-gtp-channel-conf 03_653 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[28] origin:064-gtp-channel-conf 02_654 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[29] origin:064-gtp-channel-conf 03_654 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[30] origin:064-gtp-channel-conf 02_655 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[31] origin:064-gtp-channel-conf 03_655 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[32] origin:064-gtp-channel-conf 02_656 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[33] origin:064-gtp-channel-conf 03_656 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[34] origin:064-gtp-channel-conf 02_657 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[35] origin:064-gtp-channel-conf 03_657 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[36] origin:064-gtp-channel-conf 02_658 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[37] origin:064-gtp-channel-conf 03_658 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[38] origin:064-gtp-channel-conf 02_659 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[39] origin:064-gtp-channel-conf 03_659 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[40] origin:064-gtp-channel-conf 02_660 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[41] origin:064-gtp-channel-conf 03_660 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[42] origin:064-gtp-channel-conf 02_661 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[43] origin:064-gtp-channel-conf 03_661 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[44] origin:064-gtp-channel-conf 02_662 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[45] origin:064-gtp-channel-conf 03_662 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[46] origin:064-gtp-channel-conf 02_663 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[47] origin:064-gtp-channel-conf 03_663 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[48] origin:064-gtp-channel-conf 02_664 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[49] origin:064-gtp-channel-conf 03_664 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[50] origin:064-gtp-channel-conf 02_665 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[51] origin:064-gtp-channel-conf 03_665 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[52] origin:064-gtp-channel-conf 02_666 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[53] origin:064-gtp-channel-conf 03_666 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[54] origin:064-gtp-channel-conf 02_667 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[55] origin:064-gtp-channel-conf 03_667 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[56] origin:064-gtp-channel-conf 02_668 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[57] origin:064-gtp-channel-conf 03_668 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[58] origin:064-gtp-channel-conf 02_669 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[59] origin:064-gtp-channel-conf 03_669 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[60] origin:064-gtp-channel-conf 02_670 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[61] origin:064-gtp-channel-conf 03_670 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[62] origin:064-gtp-channel-conf 02_671 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[63] origin:064-gtp-channel-conf 03_671 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[64] origin:064-gtp-channel-conf 02_672 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[65] origin:064-gtp-channel-conf 03_672 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[66] origin:064-gtp-channel-conf 02_673 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[67] origin:064-gtp-channel-conf 03_673 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[68] origin:064-gtp-channel-conf 02_674 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[69] origin:064-gtp-channel-conf 03_674 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[70] origin:064-gtp-channel-conf 02_675 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[71] origin:064-gtp-channel-conf 03_675 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[72] origin:064-gtp-channel-conf 02_676 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[73] origin:064-gtp-channel-conf 03_676 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[74] origin:064-gtp-channel-conf 02_677 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[75] origin:064-gtp-channel-conf 03_677 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[76] origin:064-gtp-channel-conf 02_678 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[77] origin:064-gtp-channel-conf 03_678 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[78] origin:064-gtp-channel-conf 02_679 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[79] origin:064-gtp-channel-conf 03_679 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[80] origin:064-gtp-channel-conf 02_680 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[81] origin:064-gtp-channel-conf 03_680 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_CFG[82] origin:064-gtp-channel-conf 02_681 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_FR_RESET_ON_EIDLE[0] origin:064-gtp-channel-conf 02_638 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_HOLD_DURING_EIDLE[0] origin:064-gtp-channel-conf 03_637 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_LOCK_CFG[0] origin:064-gtp-channel-conf 02_632 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_LOCK_CFG[1] origin:064-gtp-channel-conf 03_632 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_LOCK_CFG[2] origin:064-gtp-channel-conf 02_633 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_LOCK_CFG[3] origin:064-gtp-channel-conf 03_633 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_LOCK_CFG[4] origin:064-gtp-channel-conf 02_634 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_LOCK_CFG[5] origin:064-gtp-channel-conf 03_634 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDR_PH_RESET_ON_EIDLE[0] origin:064-gtp-channel-conf 03_638 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDRFREQRESET_TIME[0] origin:064-gtp-channel-conf 01_106 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDRFREQRESET_TIME[1] origin:064-gtp-channel-conf 00_107 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDRFREQRESET_TIME[2] origin:064-gtp-channel-conf 01_107 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDRFREQRESET_TIME[3] origin:064-gtp-channel-conf 00_108 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDRFREQRESET_TIME[4] origin:064-gtp-channel-conf 01_108 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDRPHRESET_TIME[0] origin:064-gtp-channel-conf 00_109 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDRPHRESET_TIME[1] origin:064-gtp-channel-conf 01_109 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDRPHRESET_TIME[2] origin:064-gtp-channel-conf 00_110 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDRPHRESET_TIME[3] origin:064-gtp-channel-conf 01_110 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXCDRPHRESET_TIME[4] origin:064-gtp-channel-conf 00_111 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXDLY_CFG[0] origin:064-gtp-channel-conf 00_680 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXDLY_CFG[1] origin:064-gtp-channel-conf 01_680 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXDLY_CFG[2] origin:064-gtp-channel-conf 00_681 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXDLY_CFG[3] origin:064-gtp-channel-conf 01_681 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXDLY_CFG[4] origin:064-gtp-channel-conf 00_682 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXDLY_CFG[5] origin:064-gtp-channel-conf 01_682 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXDLY_CFG[6] origin:064-gtp-channel-conf 00_683 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXDLY_CFG[7] origin:064-gtp-channel-conf 01_683 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXDLY_CFG[8] origin:064-gtp-channel-conf 00_684 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXDLY_CFG[9] origin:064-gtp-channel-conf 01_684 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXDLY_CFG[10] origin:064-gtp-channel-conf 00_685 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXDLY_CFG[11] origin:064-gtp-channel-conf 01_685 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXDLY_CFG[12] origin:064-gtp-channel-conf 00_686 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXDLY_CFG[13] origin:064-gtp-channel-conf 01_686 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXDLY_CFG[14] origin:064-gtp-channel-conf 00_687 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXDLY_CFG[15] origin:064-gtp-channel-conf 01_687 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXDLY_LCFG[0] origin:064-gtp-channel-conf 02_576 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXDLY_LCFG[1] origin:064-gtp-channel-conf 03_576 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXDLY_LCFG[2] origin:064-gtp-channel-conf 02_577 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXDLY_LCFG[3] origin:064-gtp-channel-conf 03_577 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXDLY_LCFG[4] origin:064-gtp-channel-conf 02_578 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXDLY_LCFG[5] origin:064-gtp-channel-conf 03_578 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXDLY_LCFG[6] origin:064-gtp-channel-conf 02_579 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXDLY_LCFG[7] origin:064-gtp-channel-conf 03_579 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXDLY_LCFG[8] origin:064-gtp-channel-conf 02_580 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXDLY_TAP_CFG[0] origin:064-gtp-channel-conf 00_672 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXDLY_TAP_CFG[1] origin:064-gtp-channel-conf 01_672 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXDLY_TAP_CFG[2] origin:064-gtp-channel-conf 00_673 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXDLY_TAP_CFG[3] origin:064-gtp-channel-conf 01_673 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXDLY_TAP_CFG[4] origin:064-gtp-channel-conf 00_674 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXDLY_TAP_CFG[5] origin:064-gtp-channel-conf 01_674 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXDLY_TAP_CFG[6] origin:064-gtp-channel-conf 00_675 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXDLY_TAP_CFG[7] origin:064-gtp-channel-conf 01_675 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXDLY_TAP_CFG[8] origin:064-gtp-channel-conf 00_676 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXDLY_TAP_CFG[9] origin:064-gtp-channel-conf 01_676 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXDLY_TAP_CFG[10] origin:064-gtp-channel-conf 00_677 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXDLY_TAP_CFG[11] origin:064-gtp-channel-conf 01_677 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXDLY_TAP_CFG[12] origin:064-gtp-channel-conf 00_678 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXDLY_TAP_CFG[13] origin:064-gtp-channel-conf 01_678 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXDLY_TAP_CFG[14] origin:064-gtp-channel-conf 00_679 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXDLY_TAP_CFG[15] origin:064-gtp-channel-conf 01_679 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXGEARBOX_EN origin:064-gtp-channel-conf 01_607 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXISCANRESET_TIME[0] origin:064-gtp-channel-conf 01_123 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXISCANRESET_TIME[1] origin:064-gtp-channel-conf 00_124 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXISCANRESET_TIME[2] origin:064-gtp-channel-conf 01_124 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXISCANRESET_TIME[3] origin:064-gtp-channel-conf 00_125 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXISCANRESET_TIME[4] origin:064-gtp-channel-conf 01_125 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPM_BIAS_STARTUP_DISABLE[0] origin:064-gtp-channel-conf 03_391 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPM_CFG[0] origin:064-gtp-channel-conf 02_328 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPM_CFG[1] origin:064-gtp-channel-conf 03_328 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPM_CFG[2] origin:064-gtp-channel-conf 02_329 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPM_CFG[3] origin:064-gtp-channel-conf 03_329 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPM_CM_CFG[0] origin:064-gtp-channel-conf 02_430 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPM_GC_CFG[0] origin:064-gtp-channel-conf 02_432 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPM_GC_CFG[1] origin:064-gtp-channel-conf 03_432 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPM_GC_CFG[2] origin:064-gtp-channel-conf 02_433 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPM_GC_CFG[3] origin:064-gtp-channel-conf 03_433 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPM_GC_CFG[4] origin:064-gtp-channel-conf 02_434 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPM_GC_CFG[5] origin:064-gtp-channel-conf 03_434 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPM_GC_CFG[6] origin:064-gtp-channel-conf 02_435 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPM_GC_CFG[7] origin:064-gtp-channel-conf 03_435 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPM_GC_CFG[8] origin:064-gtp-channel-conf 02_436 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPM_GC_CFG2[0] origin:064-gtp-channel-conf 03_442 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPM_GC_CFG2[1] origin:064-gtp-channel-conf 02_443 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPM_GC_CFG2[2] origin:064-gtp-channel-conf 03_443 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPM_HF_CFG[0] origin:064-gtp-channel-conf 00_336 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPM_HF_CFG[1] origin:064-gtp-channel-conf 01_336 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPM_HF_CFG[2] origin:064-gtp-channel-conf 00_337 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPM_HF_CFG[3] origin:064-gtp-channel-conf 01_337 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPM_HF_CFG[4] origin:064-gtp-channel-conf 00_338 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPM_HF_CFG[5] origin:064-gtp-channel-conf 01_338 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPM_HF_CFG[6] origin:064-gtp-channel-conf 00_339 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPM_HF_CFG[7] origin:064-gtp-channel-conf 01_339 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPM_HF_CFG[8] origin:064-gtp-channel-conf 00_340 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPM_HF_CFG[9] origin:064-gtp-channel-conf 01_340 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPM_HF_CFG[10] origin:064-gtp-channel-conf 00_341 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPM_HF_CFG[11] origin:064-gtp-channel-conf 01_341 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPM_HF_CFG[12] origin:064-gtp-channel-conf 00_342 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPM_HF_CFG[13] origin:064-gtp-channel-conf 01_342 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPM_HF_CFG2[0] origin:064-gtp-channel-conf 02_424 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPM_HF_CFG2[1] origin:064-gtp-channel-conf 03_424 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPM_HF_CFG2[2] origin:064-gtp-channel-conf 02_425 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPM_HF_CFG2[3] origin:064-gtp-channel-conf 03_425 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPM_HF_CFG2[4] origin:064-gtp-channel-conf 02_426 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPM_HF_CFG3[0] origin:064-gtp-channel-conf 03_389 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPM_HF_CFG3[1] origin:064-gtp-channel-conf 02_390 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPM_HF_CFG3[2] origin:064-gtp-channel-conf 03_390 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPM_HF_CFG3[3] origin:064-gtp-channel-conf 02_391 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPM_HOLD_DURING_EIDLE[0] origin:064-gtp-channel-conf 00_247 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPM_INCM_CFG[0] origin:064-gtp-channel-conf 02_439 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPM_IPCM_CFG[0] origin:064-gtp-channel-conf 03_439 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPM_LF_CFG[0] origin:064-gtp-channel-conf 00_344 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPM_LF_CFG[1] origin:064-gtp-channel-conf 01_344 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPM_LF_CFG[2] origin:064-gtp-channel-conf 00_345 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPM_LF_CFG[3] origin:064-gtp-channel-conf 01_345 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPM_LF_CFG[4] origin:064-gtp-channel-conf 00_346 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPM_LF_CFG[5] origin:064-gtp-channel-conf 01_346 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPM_LF_CFG[6] origin:064-gtp-channel-conf 00_347 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPM_LF_CFG[7] origin:064-gtp-channel-conf 01_347 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPM_LF_CFG[8] origin:064-gtp-channel-conf 00_348 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPM_LF_CFG[9] origin:064-gtp-channel-conf 01_348 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPM_LF_CFG[10] origin:064-gtp-channel-conf 00_349 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPM_LF_CFG[11] origin:064-gtp-channel-conf 01_349 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPM_LF_CFG[12] origin:064-gtp-channel-conf 00_350 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPM_LF_CFG[13] origin:064-gtp-channel-conf 01_350 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPM_LF_CFG[14] origin:064-gtp-channel-conf 00_351 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPM_LF_CFG[15] origin:064-gtp-channel-conf 01_351 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPM_LF_CFG[16] origin:064-gtp-channel-conf 00_343 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPM_LF_CFG[17] origin:064-gtp-channel-conf 01_343 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPM_LF_CFG2[0] origin:064-gtp-channel-conf 03_426 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPM_LF_CFG2[1] origin:064-gtp-channel-conf 02_427 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPM_LF_CFG2[2] origin:064-gtp-channel-conf 03_427 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPM_LF_CFG2[3] origin:064-gtp-channel-conf 02_428 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPM_LF_CFG2[4] origin:064-gtp-channel-conf 03_428 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPM_OSINT_CFG[0] origin:064-gtp-channel-conf 02_440 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPM_OSINT_CFG[1] origin:064-gtp-channel-conf 03_440 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPM_OSINT_CFG[2] origin:064-gtp-channel-conf 02_441 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPM_CFG1[0] origin:064-gtp-channel-conf 02_330 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPMRESET_TIME[0] origin:064-gtp-channel-conf 00_112 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPMRESET_TIME[1] origin:064-gtp-channel-conf 01_112 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPMRESET_TIME[2] origin:064-gtp-channel-conf 00_113 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPMRESET_TIME[3] origin:064-gtp-channel-conf 01_113 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPMRESET_TIME[4] origin:064-gtp-channel-conf 00_114 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPMRESET_TIME[5] origin:064-gtp-channel-conf 01_114 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXLPMRESET_TIME[6] origin:064-gtp-channel-conf 00_115 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXOOB_CFG[0] origin:064-gtp-channel-conf 00_144 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXOOB_CFG[1] origin:064-gtp-channel-conf 01_144 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXOOB_CFG[2] origin:064-gtp-channel-conf 00_145 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXOOB_CFG[3] origin:064-gtp-channel-conf 01_145 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXOOB_CFG[4] origin:064-gtp-channel-conf 00_146 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXOOB_CFG[5] origin:064-gtp-channel-conf 01_146 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXOOB_CFG[6] origin:064-gtp-channel-conf 00_147 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXOOB_CLK_CFG.FABRIC origin:064-gtp-channel-conf 03_129 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXOSCALRESET_TIME[0] origin:064-gtp-channel-conf 00_187 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXOSCALRESET_TIME[1] origin:064-gtp-channel-conf 01_187 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXOSCALRESET_TIME[2] origin:064-gtp-channel-conf 00_188 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXOSCALRESET_TIME[3] origin:064-gtp-channel-conf 01_188 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXOSCALRESET_TIME[4] origin:064-gtp-channel-conf 00_189 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXOSCALRESET_TIMEOUT[0] origin:064-gtp-channel-conf 01_189 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXOSCALRESET_TIMEOUT[1] origin:064-gtp-channel-conf 00_190 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXOSCALRESET_TIMEOUT[2] origin:064-gtp-channel-conf 01_190 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXOSCALRESET_TIMEOUT[3] origin:064-gtp-channel-conf 00_191 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXOSCALRESET_TIMEOUT[4] origin:064-gtp-channel-conf 01_191 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXOUT_DIV[0] origin:064-gtp-channel-conf 02_384 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXOUT_DIV[1] origin:064-gtp-channel-conf 03_384 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXPCSRESET_TIME[0] origin:064-gtp-channel-conf 01_115 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXPCSRESET_TIME[1] origin:064-gtp-channel-conf 00_116 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXPCSRESET_TIME[2] origin:064-gtp-channel-conf 01_116 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXPCSRESET_TIME[3] origin:064-gtp-channel-conf 00_117 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXPCSRESET_TIME[4] origin:064-gtp-channel-conf 01_117 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXPH_CFG[0] origin:064-gtp-channel-conf 02_584 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXPH_CFG[1] origin:064-gtp-channel-conf 03_584 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXPH_CFG[2] origin:064-gtp-channel-conf 02_585 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXPH_CFG[3] origin:064-gtp-channel-conf 03_585 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXPH_CFG[4] origin:064-gtp-channel-conf 02_586 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXPH_CFG[5] origin:064-gtp-channel-conf 03_586 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXPH_CFG[6] origin:064-gtp-channel-conf 02_587 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXPH_CFG[7] origin:064-gtp-channel-conf 03_587 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXPH_CFG[8] origin:064-gtp-channel-conf 02_588 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXPH_CFG[9] origin:064-gtp-channel-conf 03_588 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXPH_CFG[10] origin:064-gtp-channel-conf 02_589 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXPH_CFG[11] origin:064-gtp-channel-conf 03_589 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXPH_CFG[12] origin:064-gtp-channel-conf 02_590 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXPH_CFG[13] origin:064-gtp-channel-conf 03_590 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXPH_CFG[14] origin:064-gtp-channel-conf 02_591 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXPH_CFG[15] origin:064-gtp-channel-conf 03_591 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXPH_CFG[16] origin:064-gtp-channel-conf 02_592 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXPH_CFG[17] origin:064-gtp-channel-conf 03_592 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXPH_CFG[18] origin:064-gtp-channel-conf 02_593 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXPH_CFG[19] origin:064-gtp-channel-conf 03_593 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXPH_CFG[20] origin:064-gtp-channel-conf 02_594 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXPH_CFG[21] origin:064-gtp-channel-conf 03_594 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXPH_CFG[22] origin:064-gtp-channel-conf 02_595 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXPH_CFG[23] origin:064-gtp-channel-conf 03_595 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXPH_MONITOR_SEL[0] origin:064-gtp-channel-conf 00_700 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXPH_MONITOR_SEL[1] origin:064-gtp-channel-conf 01_700 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXPH_MONITOR_SEL[2] origin:064-gtp-channel-conf 00_701 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXPH_MONITOR_SEL[3] origin:064-gtp-channel-conf 01_701 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXPH_MONITOR_SEL[4] origin:064-gtp-channel-conf 00_702 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXPHDLY_CFG[0] origin:064-gtp-channel-conf 02_600 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXPHDLY_CFG[1] origin:064-gtp-channel-conf 03_600 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXPHDLY_CFG[2] origin:064-gtp-channel-conf 02_601 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXPHDLY_CFG[3] origin:064-gtp-channel-conf 03_601 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXPHDLY_CFG[4] origin:064-gtp-channel-conf 02_602 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXPHDLY_CFG[5] origin:064-gtp-channel-conf 03_602 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXPHDLY_CFG[6] origin:064-gtp-channel-conf 02_603 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXPHDLY_CFG[7] origin:064-gtp-channel-conf 03_603 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXPHDLY_CFG[8] origin:064-gtp-channel-conf 02_604 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXPHDLY_CFG[9] origin:064-gtp-channel-conf 03_604 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXPHDLY_CFG[10] origin:064-gtp-channel-conf 02_605 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXPHDLY_CFG[11] origin:064-gtp-channel-conf 03_605 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXPHDLY_CFG[12] origin:064-gtp-channel-conf 02_606 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXPHDLY_CFG[13] origin:064-gtp-channel-conf 03_606 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXPHDLY_CFG[14] origin:064-gtp-channel-conf 02_607 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXPHDLY_CFG[15] origin:064-gtp-channel-conf 03_607 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXPHDLY_CFG[16] origin:064-gtp-channel-conf 02_608 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXPHDLY_CFG[17] origin:064-gtp-channel-conf 03_608 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXPHDLY_CFG[18] origin:064-gtp-channel-conf 02_609 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXPHDLY_CFG[19] origin:064-gtp-channel-conf 03_609 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXPHDLY_CFG[20] origin:064-gtp-channel-conf 02_610 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXPHDLY_CFG[21] origin:064-gtp-channel-conf 03_610 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXPHDLY_CFG[22] origin:064-gtp-channel-conf 02_611 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXPHDLY_CFG[23] origin:064-gtp-channel-conf 03_611 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXPI_CFG0[0] origin:064-gtp-channel-conf 03_430 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXPI_CFG0[1] origin:064-gtp-channel-conf 02_431 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXPI_CFG0[2] origin:064-gtp-channel-conf 03_431 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXPI_CFG1[0] origin:064-gtp-channel-conf 02_442 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXPI_CFG2[0] origin:064-gtp-channel-conf 03_441 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXPMARESET_TIME[0] origin:064-gtp-channel-conf 00_104 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXPMARESET_TIME[1] origin:064-gtp-channel-conf 01_104 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXPMARESET_TIME[2] origin:064-gtp-channel-conf 00_105 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXPMARESET_TIME[3] origin:064-gtp-channel-conf 01_105 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXPMARESET_TIME[4] origin:064-gtp-channel-conf 00_106 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXPRBS_ERR_LOOPBACK[0] origin:064-gtp-channel-conf 00_136 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXSLIDE_AUTO_WAIT[0] origin:064-gtp-channel-conf 00_520 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXSLIDE_AUTO_WAIT[1] origin:064-gtp-channel-conf 01_520 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXSLIDE_AUTO_WAIT[2] origin:064-gtp-channel-conf 00_521 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXSLIDE_AUTO_WAIT[3] origin:064-gtp-channel-conf 01_521 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXSLIDE_MODE.AUTO origin:064-gtp-channel-conf !01_519 00_519 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXSLIDE_MODE.PCS origin:064-gtp-channel-conf !00_519 01_519 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXSLIDE_MODE.PMA origin:064-gtp-channel-conf 00_519 01_519 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXSYNC_MULTILANE[0] origin:064-gtp-channel-conf 00_133 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXSYNC_OVRD[0] origin:064-gtp-channel-conf 01_135 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.RXSYNC_SKIP_DA[0] origin:064-gtp-channel-conf 01_134 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.SAS_MAX_COM[0] origin:064-gtp-channel-conf 00_171 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.SAS_MAX_COM[1] origin:064-gtp-channel-conf 01_171 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.SAS_MAX_COM[2] origin:064-gtp-channel-conf 00_172 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.SAS_MAX_COM[3] origin:064-gtp-channel-conf 01_172 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.SAS_MAX_COM[4] origin:064-gtp-channel-conf 00_173 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.SAS_MAX_COM[5] origin:064-gtp-channel-conf 01_173 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.SAS_MAX_COM[6] origin:064-gtp-channel-conf 00_174 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.SAS_MIN_COM[0] origin:064-gtp-channel-conf 01_156 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.SAS_MIN_COM[1] origin:064-gtp-channel-conf 00_157 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.SAS_MIN_COM[2] origin:064-gtp-channel-conf 01_157 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.SAS_MIN_COM[3] origin:064-gtp-channel-conf 00_158 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.SAS_MIN_COM[4] origin:064-gtp-channel-conf 01_158 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.SAS_MIN_COM[5] origin:064-gtp-channel-conf 00_159 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.SATA_BURST_SEQ_LEN[0] origin:064-gtp-channel-conf 00_150 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.SATA_BURST_SEQ_LEN[1] origin:064-gtp-channel-conf 01_150 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.SATA_BURST_SEQ_LEN[2] origin:064-gtp-channel-conf 00_151 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.SATA_BURST_SEQ_LEN[3] origin:064-gtp-channel-conf 01_151 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.SATA_BURST_VAL[0] origin:064-gtp-channel-conf 01_147 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.SATA_BURST_VAL[1] origin:064-gtp-channel-conf 00_148 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.SATA_BURST_VAL[2] origin:064-gtp-channel-conf 01_148 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.SATA_EIDLE_VAL[0] origin:064-gtp-channel-conf 00_152 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.SATA_EIDLE_VAL[1] origin:064-gtp-channel-conf 01_152 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.SATA_EIDLE_VAL[2] origin:064-gtp-channel-conf 00_153 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.SATA_MAX_BURST[0] origin:064-gtp-channel-conf 00_168 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.SATA_MAX_BURST[1] origin:064-gtp-channel-conf 01_168 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.SATA_MAX_BURST[2] origin:064-gtp-channel-conf 00_169 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.SATA_MAX_BURST[3] origin:064-gtp-channel-conf 01_169 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.SATA_MAX_BURST[4] origin:064-gtp-channel-conf 00_170 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.SATA_MAX_BURST[5] origin:064-gtp-channel-conf 01_170 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.SATA_MAX_INIT[0] origin:064-gtp-channel-conf 00_176 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.SATA_MAX_INIT[1] origin:064-gtp-channel-conf 01_176 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.SATA_MAX_INIT[2] origin:064-gtp-channel-conf 00_177 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.SATA_MAX_INIT[3] origin:064-gtp-channel-conf 01_177 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.SATA_MAX_INIT[4] origin:064-gtp-channel-conf 00_178 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.SATA_MAX_INIT[5] origin:064-gtp-channel-conf 01_178 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.SATA_MAX_WAKE[0] origin:064-gtp-channel-conf 00_179 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.SATA_MAX_WAKE[1] origin:064-gtp-channel-conf 01_179 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.SATA_MAX_WAKE[2] origin:064-gtp-channel-conf 00_180 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.SATA_MAX_WAKE[3] origin:064-gtp-channel-conf 01_180 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.SATA_MAX_WAKE[4] origin:064-gtp-channel-conf 00_181 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.SATA_MAX_WAKE[5] origin:064-gtp-channel-conf 01_181 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.SATA_MIN_BURST[0] origin:064-gtp-channel-conf 01_153 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.SATA_MIN_BURST[1] origin:064-gtp-channel-conf 00_154 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.SATA_MIN_BURST[2] origin:064-gtp-channel-conf 01_154 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.SATA_MIN_BURST[3] origin:064-gtp-channel-conf 00_155 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.SATA_MIN_BURST[4] origin:064-gtp-channel-conf 01_155 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.SATA_MIN_BURST[5] origin:064-gtp-channel-conf 00_156 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.SATA_MIN_INIT[0] origin:064-gtp-channel-conf 00_160 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.SATA_MIN_INIT[1] origin:064-gtp-channel-conf 01_160 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.SATA_MIN_INIT[2] origin:064-gtp-channel-conf 00_161 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.SATA_MIN_INIT[3] origin:064-gtp-channel-conf 01_161 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.SATA_MIN_INIT[4] origin:064-gtp-channel-conf 00_162 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.SATA_MIN_INIT[5] origin:064-gtp-channel-conf 01_162 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.SATA_MIN_WAKE[0] origin:064-gtp-channel-conf 00_163 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.SATA_MIN_WAKE[1] origin:064-gtp-channel-conf 01_163 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.SATA_MIN_WAKE[2] origin:064-gtp-channel-conf 00_164 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.SATA_MIN_WAKE[3] origin:064-gtp-channel-conf 01_164 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.SATA_MIN_WAKE[4] origin:064-gtp-channel-conf 00_165 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.SATA_MIN_WAKE[5] origin:064-gtp-channel-conf 01_165 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.SATA_PLL_CFG.VCO_1500MHZ origin:064-gtp-channel-conf 02_55 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.SATA_PLL_CFG.VCO_750MHZ origin:064-gtp-channel-conf 03_55 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.SHOW_REALIGN_COMMA origin:064-gtp-channel-conf 01_522 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TERM_RCAL_CFG[0] origin:064-gtp-channel-conf 02_136 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TERM_RCAL_CFG[1] origin:064-gtp-channel-conf 03_136 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TERM_RCAL_CFG[2] origin:064-gtp-channel-conf 02_137 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TERM_RCAL_CFG[3] origin:064-gtp-channel-conf 03_137 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TERM_RCAL_CFG[4] origin:064-gtp-channel-conf 02_138 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TERM_RCAL_CFG[5] origin:064-gtp-channel-conf 03_138 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TERM_RCAL_CFG[6] origin:064-gtp-channel-conf 02_139 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TERM_RCAL_CFG[7] origin:064-gtp-channel-conf 03_139 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TERM_RCAL_CFG[8] origin:064-gtp-channel-conf 02_140 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TERM_RCAL_CFG[9] origin:064-gtp-channel-conf 03_140 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TERM_RCAL_CFG[10] origin:064-gtp-channel-conf 02_141 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TERM_RCAL_CFG[11] origin:064-gtp-channel-conf 03_141 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TERM_RCAL_CFG[12] origin:064-gtp-channel-conf 02_142 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TERM_RCAL_CFG[13] origin:064-gtp-channel-conf 03_142 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TERM_RCAL_CFG[14] origin:064-gtp-channel-conf 02_143 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TERM_RCAL_OVRD[0] origin:064-gtp-channel-conf 03_150 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TERM_RCAL_OVRD[1] origin:064-gtp-channel-conf 02_151 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TERM_RCAL_OVRD[2] origin:064-gtp-channel-conf 03_151 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TRANS_TIME_RATE[0] origin:064-gtp-channel-conf 00_192 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TRANS_TIME_RATE[1] origin:064-gtp-channel-conf 01_192 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TRANS_TIME_RATE[2] origin:064-gtp-channel-conf 00_193 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TRANS_TIME_RATE[3] origin:064-gtp-channel-conf 01_193 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TRANS_TIME_RATE[4] origin:064-gtp-channel-conf 00_194 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TRANS_TIME_RATE[5] origin:064-gtp-channel-conf 01_194 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TRANS_TIME_RATE[6] origin:064-gtp-channel-conf 00_195 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TRANS_TIME_RATE[7] origin:064-gtp-channel-conf 01_195 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TST_RSV[0] origin:064-gtp-channel-conf 02_504 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TST_RSV[1] origin:064-gtp-channel-conf 03_504 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TST_RSV[2] origin:064-gtp-channel-conf 02_505 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TST_RSV[3] origin:064-gtp-channel-conf 03_505 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TST_RSV[4] origin:064-gtp-channel-conf 02_506 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TST_RSV[5] origin:064-gtp-channel-conf 03_506 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TST_RSV[6] origin:064-gtp-channel-conf 02_507 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TST_RSV[7] origin:064-gtp-channel-conf 03_507 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TST_RSV[8] origin:064-gtp-channel-conf 02_508 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TST_RSV[9] origin:064-gtp-channel-conf 03_508 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TST_RSV[10] origin:064-gtp-channel-conf 02_509 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TST_RSV[11] origin:064-gtp-channel-conf 03_509 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TST_RSV[12] origin:064-gtp-channel-conf 02_510 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TST_RSV[13] origin:064-gtp-channel-conf 03_510 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TST_RSV[14] origin:064-gtp-channel-conf 02_511 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TST_RSV[15] origin:064-gtp-channel-conf 03_511 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TST_RSV[16] origin:064-gtp-channel-conf 02_512 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TST_RSV[17] origin:064-gtp-channel-conf 03_512 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TST_RSV[18] origin:064-gtp-channel-conf 02_513 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TST_RSV[19] origin:064-gtp-channel-conf 03_513 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TST_RSV[20] origin:064-gtp-channel-conf 02_514 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TST_RSV[21] origin:064-gtp-channel-conf 03_514 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TST_RSV[22] origin:064-gtp-channel-conf 02_515 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TST_RSV[23] origin:064-gtp-channel-conf 03_515 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TST_RSV[24] origin:064-gtp-channel-conf 02_516 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TST_RSV[25] origin:064-gtp-channel-conf 03_516 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TST_RSV[26] origin:064-gtp-channel-conf 02_517 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TST_RSV[27] origin:064-gtp-channel-conf 03_517 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TST_RSV[28] origin:064-gtp-channel-conf 02_518 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TST_RSV[29] origin:064-gtp-channel-conf 03_518 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TST_RSV[30] origin:064-gtp-channel-conf 02_519 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TST_RSV[31] origin:064-gtp-channel-conf 03_519 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_CLKMUX_EN[0] origin:064-gtp-channel-conf 03_128 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_DATA_WIDTH[0] origin:064-gtp-channel-conf 02_152 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_DATA_WIDTH[1] origin:064-gtp-channel-conf 03_152 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_DATA_WIDTH[2] origin:064-gtp-channel-conf 02_153 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_DRIVE_MODE.PIPE origin:064-gtp-channel-conf 00_200 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_EIDLE_ASSERT_DELAY[0] origin:064-gtp-channel-conf 00_203 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_EIDLE_ASSERT_DELAY[1] origin:064-gtp-channel-conf 01_203 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_EIDLE_ASSERT_DELAY[2] origin:064-gtp-channel-conf 00_204 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_EIDLE_DEASSERT_DELAY[0] origin:064-gtp-channel-conf 01_204 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_EIDLE_DEASSERT_DELAY[1] origin:064-gtp-channel-conf 00_205 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_EIDLE_DEASSERT_DELAY[2] origin:064-gtp-channel-conf 01_205 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_LOOPBACK_DRIVE_HIZ origin:064-gtp-channel-conf 01_202 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_MAINCURSOR_SEL[0] origin:064-gtp-channel-conf 03_289 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_MARGIN_FULL_0[0] origin:064-gtp-channel-conf 02_232 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_MARGIN_FULL_0[1] origin:064-gtp-channel-conf 03_232 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_MARGIN_FULL_0[2] origin:064-gtp-channel-conf 02_233 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_MARGIN_FULL_0[3] origin:064-gtp-channel-conf 03_233 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_MARGIN_FULL_0[4] origin:064-gtp-channel-conf 02_234 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_MARGIN_FULL_0[5] origin:064-gtp-channel-conf 03_234 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_MARGIN_FULL_0[6] origin:064-gtp-channel-conf 02_235 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_MARGIN_FULL_1[0] origin:064-gtp-channel-conf 02_236 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_MARGIN_FULL_1[1] origin:064-gtp-channel-conf 03_236 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_MARGIN_FULL_1[2] origin:064-gtp-channel-conf 02_237 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_MARGIN_FULL_1[3] origin:064-gtp-channel-conf 03_237 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_MARGIN_FULL_1[4] origin:064-gtp-channel-conf 02_238 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_MARGIN_FULL_1[5] origin:064-gtp-channel-conf 03_238 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_MARGIN_FULL_1[6] origin:064-gtp-channel-conf 02_239 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_MARGIN_FULL_2[0] origin:064-gtp-channel-conf 02_240 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_MARGIN_FULL_2[1] origin:064-gtp-channel-conf 03_240 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_MARGIN_FULL_2[2] origin:064-gtp-channel-conf 02_241 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_MARGIN_FULL_2[3] origin:064-gtp-channel-conf 03_241 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_MARGIN_FULL_2[4] origin:064-gtp-channel-conf 02_242 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_MARGIN_FULL_2[5] origin:064-gtp-channel-conf 03_242 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_MARGIN_FULL_2[6] origin:064-gtp-channel-conf 02_243 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_MARGIN_FULL_3[0] origin:064-gtp-channel-conf 02_244 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_MARGIN_FULL_3[1] origin:064-gtp-channel-conf 03_244 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_MARGIN_FULL_3[2] origin:064-gtp-channel-conf 02_245 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_MARGIN_FULL_3[3] origin:064-gtp-channel-conf 03_245 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_MARGIN_FULL_3[4] origin:064-gtp-channel-conf 02_246 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_MARGIN_FULL_3[5] origin:064-gtp-channel-conf 03_246 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_MARGIN_FULL_3[6] origin:064-gtp-channel-conf 02_247 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_MARGIN_FULL_4[0] origin:064-gtp-channel-conf 02_248 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_MARGIN_FULL_4[1] origin:064-gtp-channel-conf 03_248 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_MARGIN_FULL_4[2] origin:064-gtp-channel-conf 02_249 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_MARGIN_FULL_4[3] origin:064-gtp-channel-conf 03_249 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_MARGIN_FULL_4[4] origin:064-gtp-channel-conf 02_250 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_MARGIN_FULL_4[5] origin:064-gtp-channel-conf 03_250 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_MARGIN_FULL_4[6] origin:064-gtp-channel-conf 02_251 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_MARGIN_LOW_0[0] origin:064-gtp-channel-conf 02_252 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_MARGIN_LOW_0[1] origin:064-gtp-channel-conf 03_252 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_MARGIN_LOW_0[2] origin:064-gtp-channel-conf 02_253 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_MARGIN_LOW_0[3] origin:064-gtp-channel-conf 03_253 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_MARGIN_LOW_0[4] origin:064-gtp-channel-conf 02_254 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_MARGIN_LOW_0[5] origin:064-gtp-channel-conf 03_254 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_MARGIN_LOW_0[6] origin:064-gtp-channel-conf 02_255 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_MARGIN_LOW_1[0] origin:064-gtp-channel-conf 02_256 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_MARGIN_LOW_1[1] origin:064-gtp-channel-conf 03_256 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_MARGIN_LOW_1[2] origin:064-gtp-channel-conf 02_257 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_MARGIN_LOW_1[3] origin:064-gtp-channel-conf 03_257 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_MARGIN_LOW_1[4] origin:064-gtp-channel-conf 02_258 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_MARGIN_LOW_1[5] origin:064-gtp-channel-conf 03_258 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_MARGIN_LOW_1[6] origin:064-gtp-channel-conf 02_259 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_MARGIN_LOW_2[0] origin:064-gtp-channel-conf 02_260 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_MARGIN_LOW_2[1] origin:064-gtp-channel-conf 03_260 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_MARGIN_LOW_2[2] origin:064-gtp-channel-conf 02_261 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_MARGIN_LOW_2[3] origin:064-gtp-channel-conf 03_261 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_MARGIN_LOW_2[4] origin:064-gtp-channel-conf 02_262 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_MARGIN_LOW_2[5] origin:064-gtp-channel-conf 03_262 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_MARGIN_LOW_2[6] origin:064-gtp-channel-conf 02_263 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_MARGIN_LOW_3[0] origin:064-gtp-channel-conf 02_264 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_MARGIN_LOW_3[1] origin:064-gtp-channel-conf 03_264 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_MARGIN_LOW_3[2] origin:064-gtp-channel-conf 02_265 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_MARGIN_LOW_3[3] origin:064-gtp-channel-conf 03_265 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_MARGIN_LOW_3[4] origin:064-gtp-channel-conf 02_266 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_MARGIN_LOW_3[5] origin:064-gtp-channel-conf 03_266 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_MARGIN_LOW_3[6] origin:064-gtp-channel-conf 02_267 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_MARGIN_LOW_4[0] origin:064-gtp-channel-conf 02_268 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_MARGIN_LOW_4[1] origin:064-gtp-channel-conf 03_268 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_MARGIN_LOW_4[2] origin:064-gtp-channel-conf 02_269 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_MARGIN_LOW_4[3] origin:064-gtp-channel-conf 03_269 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_MARGIN_LOW_4[4] origin:064-gtp-channel-conf 02_270 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_MARGIN_LOW_4[5] origin:064-gtp-channel-conf 03_270 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_MARGIN_LOW_4[6] origin:064-gtp-channel-conf 02_271 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_PREDRIVER_MODE[0] origin:064-gtp-channel-conf 00_206 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_RXDETECT_CFG[0] origin:064-gtp-channel-conf 02_296 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_RXDETECT_CFG[1] origin:064-gtp-channel-conf 03_296 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_RXDETECT_CFG[2] origin:064-gtp-channel-conf 02_297 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_RXDETECT_CFG[3] origin:064-gtp-channel-conf 03_297 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_RXDETECT_CFG[4] origin:064-gtp-channel-conf 02_298 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_RXDETECT_CFG[5] origin:064-gtp-channel-conf 03_298 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_RXDETECT_CFG[6] origin:064-gtp-channel-conf 02_299 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_RXDETECT_CFG[7] origin:064-gtp-channel-conf 03_299 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_RXDETECT_CFG[8] origin:064-gtp-channel-conf 02_300 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_RXDETECT_CFG[9] origin:064-gtp-channel-conf 03_300 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_RXDETECT_CFG[10] origin:064-gtp-channel-conf 02_301 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_RXDETECT_CFG[11] origin:064-gtp-channel-conf 03_301 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_RXDETECT_CFG[12] origin:064-gtp-channel-conf 02_302 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_RXDETECT_CFG[13] origin:064-gtp-channel-conf 03_302 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_RXDETECT_REF[0] origin:064-gtp-channel-conf 02_292 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_RXDETECT_REF[1] origin:064-gtp-channel-conf 03_292 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_RXDETECT_REF[2] origin:064-gtp-channel-conf 02_293 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_XCLK_SEL.TXUSR origin:064-gtp-channel-conf 03_11 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_CLK25_DIV[0] origin:064-gtp-channel-conf 02_144 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_CLK25_DIV[1] origin:064-gtp-channel-conf 03_144 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_CLK25_DIV[2] origin:064-gtp-channel-conf 02_145 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_CLK25_DIV[3] origin:064-gtp-channel-conf 03_145 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_CLK25_DIV[4] origin:064-gtp-channel-conf 02_146 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_DEEMPH0[0] origin:064-gtp-channel-conf 02_272 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_DEEMPH0[1] origin:064-gtp-channel-conf 03_272 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_DEEMPH0[2] origin:064-gtp-channel-conf 02_273 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_DEEMPH0[3] origin:064-gtp-channel-conf 03_273 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_DEEMPH0[4] origin:064-gtp-channel-conf 02_274 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_DEEMPH0[5] origin:064-gtp-channel-conf 03_274 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_DEEMPH1[0] origin:064-gtp-channel-conf 02_276 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_DEEMPH1[1] origin:064-gtp-channel-conf 03_276 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_DEEMPH1[2] origin:064-gtp-channel-conf 02_277 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_DEEMPH1[3] origin:064-gtp-channel-conf 03_277 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_DEEMPH1[4] origin:064-gtp-channel-conf 02_278 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TX_DEEMPH1[5] origin:064-gtp-channel-conf 03_278 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXBUF_EN origin:064-gtp-channel-conf 00_231 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXBUF_RESET_ON_RATE_CHANGE origin:064-gtp-channel-conf 01_231 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXDLY_CFG[0] origin:064-gtp-channel-conf 02_80 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXDLY_CFG[1] origin:064-gtp-channel-conf 03_80 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXDLY_CFG[2] origin:064-gtp-channel-conf 02_81 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXDLY_CFG[3] origin:064-gtp-channel-conf 03_81 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXDLY_CFG[4] origin:064-gtp-channel-conf 02_82 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXDLY_CFG[5] origin:064-gtp-channel-conf 03_82 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXDLY_CFG[6] origin:064-gtp-channel-conf 02_83 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXDLY_CFG[7] origin:064-gtp-channel-conf 03_83 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXDLY_CFG[8] origin:064-gtp-channel-conf 02_84 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXDLY_CFG[9] origin:064-gtp-channel-conf 03_84 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXDLY_CFG[10] origin:064-gtp-channel-conf 02_85 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXDLY_CFG[11] origin:064-gtp-channel-conf 03_85 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXDLY_CFG[12] origin:064-gtp-channel-conf 02_86 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXDLY_CFG[13] origin:064-gtp-channel-conf 03_86 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXDLY_CFG[14] origin:064-gtp-channel-conf 02_87 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXDLY_CFG[15] origin:064-gtp-channel-conf 03_87 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXDLY_LCFG[0] origin:064-gtp-channel-conf 02_568 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXDLY_LCFG[1] origin:064-gtp-channel-conf 03_568 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXDLY_LCFG[2] origin:064-gtp-channel-conf 02_569 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXDLY_LCFG[3] origin:064-gtp-channel-conf 03_569 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXDLY_LCFG[4] origin:064-gtp-channel-conf 02_570 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXDLY_LCFG[5] origin:064-gtp-channel-conf 03_570 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXDLY_LCFG[6] origin:064-gtp-channel-conf 02_571 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXDLY_LCFG[7] origin:064-gtp-channel-conf 03_571 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXDLY_LCFG[8] origin:064-gtp-channel-conf 02_572 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXDLY_TAP_CFG[0] origin:064-gtp-channel-conf 02_88 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXDLY_TAP_CFG[1] origin:064-gtp-channel-conf 03_88 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXDLY_TAP_CFG[2] origin:064-gtp-channel-conf 02_89 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXDLY_TAP_CFG[3] origin:064-gtp-channel-conf 03_89 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXDLY_TAP_CFG[4] origin:064-gtp-channel-conf 02_90 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXDLY_TAP_CFG[5] origin:064-gtp-channel-conf 03_90 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXDLY_TAP_CFG[6] origin:064-gtp-channel-conf 02_91 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXDLY_TAP_CFG[7] origin:064-gtp-channel-conf 03_91 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXDLY_TAP_CFG[8] origin:064-gtp-channel-conf 02_92 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXDLY_TAP_CFG[9] origin:064-gtp-channel-conf 03_92 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXDLY_TAP_CFG[10] origin:064-gtp-channel-conf 02_93 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXDLY_TAP_CFG[11] origin:064-gtp-channel-conf 03_93 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXDLY_TAP_CFG[12] origin:064-gtp-channel-conf 02_94 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXDLY_TAP_CFG[13] origin:064-gtp-channel-conf 03_94 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXDLY_TAP_CFG[14] origin:064-gtp-channel-conf 02_95 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXDLY_TAP_CFG[15] origin:064-gtp-channel-conf 03_95 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXGEARBOX_EN origin:064-gtp-channel-conf 01_226 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXOOB_CFG[0] origin:064-gtp-channel-conf 03_20 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXOUT_DIV[0] origin:064-gtp-channel-conf 02_386 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXOUT_DIV[1] origin:064-gtp-channel-conf 03_386 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPCSRESET_TIME[0] origin:064-gtp-channel-conf 01_130 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPCSRESET_TIME[1] origin:064-gtp-channel-conf 00_131 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPCSRESET_TIME[2] origin:064-gtp-channel-conf 01_131 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPCSRESET_TIME[3] origin:064-gtp-channel-conf 00_132 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPCSRESET_TIME[4] origin:064-gtp-channel-conf 01_132 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPH_CFG[0] origin:064-gtp-channel-conf 02_96 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPH_CFG[1] origin:064-gtp-channel-conf 03_96 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPH_CFG[2] origin:064-gtp-channel-conf 02_97 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPH_CFG[3] origin:064-gtp-channel-conf 03_97 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPH_CFG[4] origin:064-gtp-channel-conf 02_98 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPH_CFG[5] origin:064-gtp-channel-conf 03_98 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPH_CFG[6] origin:064-gtp-channel-conf 02_99 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPH_CFG[7] origin:064-gtp-channel-conf 03_99 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPH_CFG[8] origin:064-gtp-channel-conf 02_100 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPH_CFG[9] origin:064-gtp-channel-conf 03_100 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPH_CFG[10] origin:064-gtp-channel-conf 02_101 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPH_CFG[11] origin:064-gtp-channel-conf 03_101 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPH_CFG[12] origin:064-gtp-channel-conf 02_102 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPH_CFG[13] origin:064-gtp-channel-conf 03_102 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPH_CFG[14] origin:064-gtp-channel-conf 02_103 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPH_CFG[15] origin:064-gtp-channel-conf 03_103 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPH_MONITOR_SEL[0] origin:064-gtp-channel-conf 02_108 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPH_MONITOR_SEL[1] origin:064-gtp-channel-conf 03_108 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPH_MONITOR_SEL[2] origin:064-gtp-channel-conf 02_109 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPH_MONITOR_SEL[3] origin:064-gtp-channel-conf 03_109 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPH_MONITOR_SEL[4] origin:064-gtp-channel-conf 02_110 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPHDLY_CFG[0] origin:064-gtp-channel-conf 02_64 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPHDLY_CFG[1] origin:064-gtp-channel-conf 03_64 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPHDLY_CFG[2] origin:064-gtp-channel-conf 02_65 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPHDLY_CFG[3] origin:064-gtp-channel-conf 03_65 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPHDLY_CFG[4] origin:064-gtp-channel-conf 02_66 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPHDLY_CFG[5] origin:064-gtp-channel-conf 03_66 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPHDLY_CFG[6] origin:064-gtp-channel-conf 02_67 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPHDLY_CFG[7] origin:064-gtp-channel-conf 03_67 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPHDLY_CFG[8] origin:064-gtp-channel-conf 02_68 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPHDLY_CFG[9] origin:064-gtp-channel-conf 03_68 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPHDLY_CFG[10] origin:064-gtp-channel-conf 02_69 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPHDLY_CFG[11] origin:064-gtp-channel-conf 03_69 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPHDLY_CFG[12] origin:064-gtp-channel-conf 02_70 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPHDLY_CFG[13] origin:064-gtp-channel-conf 03_70 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPHDLY_CFG[14] origin:064-gtp-channel-conf 02_71 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPHDLY_CFG[15] origin:064-gtp-channel-conf 03_71 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPHDLY_CFG[16] origin:064-gtp-channel-conf 02_72 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPHDLY_CFG[17] origin:064-gtp-channel-conf 03_72 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPHDLY_CFG[18] origin:064-gtp-channel-conf 02_73 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPHDLY_CFG[19] origin:064-gtp-channel-conf 03_73 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPHDLY_CFG[20] origin:064-gtp-channel-conf 02_74 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPHDLY_CFG[21] origin:064-gtp-channel-conf 03_74 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPHDLY_CFG[22] origin:064-gtp-channel-conf 02_75 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPHDLY_CFG[23] origin:064-gtp-channel-conf 03_75 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPI_GREY_SEL[0] origin:064-gtp-channel-conf 03_498 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPI_INVSTROBE_SEL[0] origin:064-gtp-channel-conf 02_498 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPI_PPM_CFG[0] origin:064-gtp-channel-conf 02_488 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPI_PPM_CFG[1] origin:064-gtp-channel-conf 03_488 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPI_PPM_CFG[2] origin:064-gtp-channel-conf 02_489 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPI_PPM_CFG[3] origin:064-gtp-channel-conf 03_489 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPI_PPM_CFG[4] origin:064-gtp-channel-conf 02_490 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPI_PPM_CFG[5] origin:064-gtp-channel-conf 03_490 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPI_PPM_CFG[6] origin:064-gtp-channel-conf 02_491 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPI_PPM_CFG[7] origin:064-gtp-channel-conf 03_491 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPI_PPMCLK_SEL.TXUSRCLK2 origin:064-gtp-channel-conf 03_497 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPI_SYNFREQ_PPM[0] origin:064-gtp-channel-conf 02_496 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPI_SYNFREQ_PPM[1] origin:064-gtp-channel-conf 03_496 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPI_SYNFREQ_PPM[2] origin:064-gtp-channel-conf 02_497 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPI_CFG0[0] origin:064-gtp-channel-conf 02_40 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPI_CFG0[1] origin:064-gtp-channel-conf 03_40 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPI_CFG1[0] origin:064-gtp-channel-conf 02_41 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPI_CFG1[1] origin:064-gtp-channel-conf 03_41 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPI_CFG2[0] origin:064-gtp-channel-conf 02_42 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPI_CFG2[1] origin:064-gtp-channel-conf 03_42 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPI_CFG3[0] origin:064-gtp-channel-conf 02_43 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPI_CFG4[0] origin:064-gtp-channel-conf 03_43 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPI_CFG5[0] origin:064-gtp-channel-conf 02_44 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPI_CFG5[1] origin:064-gtp-channel-conf 03_44 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPI_CFG5[2] origin:064-gtp-channel-conf 02_45 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPMARESET_TIME[0] origin:064-gtp-channel-conf 00_128 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPMARESET_TIME[1] origin:064-gtp-channel-conf 01_128 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPMARESET_TIME[2] origin:064-gtp-channel-conf 00_129 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPMARESET_TIME[3] origin:064-gtp-channel-conf 01_129 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXPMARESET_TIME[4] origin:064-gtp-channel-conf 00_130 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXSYNC_MULTILANE[0] origin:064-gtp-channel-conf 01_133 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXSYNC_OVRD[0] origin:064-gtp-channel-conf 00_135 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.TXSYNC_SKIP_DA[0] origin:064-gtp-channel-conf 00_134 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.UCODEER_CLR[0] origin:064-gtp-channel-conf 01_00 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.USE_PCS_CLK_PHASE_SEL[0] origin:064-gtp-channel-conf 02_463 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ZINV_DMONITORCLK origin:064-gtp-channel-conf 02_13 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ZINV_DRPCLK origin:064-gtp-channel-conf 02_00 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ZINV_RXUSRCLK origin:064-gtp-channel-conf 03_01 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ZINV_SIGVALIDCLK origin:064-gtp-channel-conf 03_13 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ZINV_TXPHDLYTSTCLK origin:064-gtp-channel-conf 02_03 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ZINV_TXUSRCLK origin:064-gtp-channel-conf 03_04 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ZINV_CLKRSVD0 origin:064-gtp-channel-conf 02_23 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ZINV_CLKRSVD1 origin:064-gtp-channel-conf 03_23 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ZINV_RXUSRCLK2 origin:064-gtp-channel-conf 02_02 -GTP_CHANNEL_3_MID_RIGHT.GTPE2.ZINV_TXUSRCLK2 origin:064-gtp-channel-conf 02_05 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ACJTAG_DEBUG_MODE[0] origin:064-gtp-channel-conf 00_07 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ACJTAG_MODE[0] origin:064-gtp-channel-conf 01_06 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ACJTAG_RESET[0] origin:064-gtp-channel-conf 01_07 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[0] origin:064-gtp-channel-conf 02_464 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[1] origin:064-gtp-channel-conf 03_464 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[2] origin:064-gtp-channel-conf 02_465 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[3] origin:064-gtp-channel-conf 03_465 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[4] origin:064-gtp-channel-conf 02_466 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[5] origin:064-gtp-channel-conf 03_466 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[6] origin:064-gtp-channel-conf 02_467 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[7] origin:064-gtp-channel-conf 03_467 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[8] origin:064-gtp-channel-conf 02_468 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[9] origin:064-gtp-channel-conf 03_468 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[10] origin:064-gtp-channel-conf 02_469 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[11] origin:064-gtp-channel-conf 03_469 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[12] origin:064-gtp-channel-conf 02_470 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[13] origin:064-gtp-channel-conf 03_470 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[14] origin:064-gtp-channel-conf 02_471 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[15] origin:064-gtp-channel-conf 03_471 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[16] origin:064-gtp-channel-conf 02_472 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[17] origin:064-gtp-channel-conf 03_472 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[18] origin:064-gtp-channel-conf 02_473 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ADAPT_CFG0[19] origin:064-gtp-channel-conf 03_473 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ALIGN_COMMA_DOUBLE origin:064-gtp-channel-conf 00_522 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[0] origin:064-gtp-channel-conf 00_496 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[1] origin:064-gtp-channel-conf 01_496 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[2] origin:064-gtp-channel-conf 00_497 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[3] origin:064-gtp-channel-conf 01_497 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[4] origin:064-gtp-channel-conf 00_498 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[5] origin:064-gtp-channel-conf 01_498 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[6] origin:064-gtp-channel-conf 00_499 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[7] origin:064-gtp-channel-conf 01_499 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[8] origin:064-gtp-channel-conf 00_500 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ALIGN_COMMA_ENABLE[9] origin:064-gtp-channel-conf 01_500 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ALIGN_COMMA_WORD[0] origin:064-gtp-channel-conf 01_526 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ALIGN_COMMA_WORD[1] origin:064-gtp-channel-conf 00_527 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ALIGN_MCOMMA_DET origin:064-gtp-channel-conf 00_523 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[0] origin:064-gtp-channel-conf 00_504 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[1] origin:064-gtp-channel-conf 01_504 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[2] origin:064-gtp-channel-conf 00_505 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[3] origin:064-gtp-channel-conf 01_505 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[4] origin:064-gtp-channel-conf 00_506 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[5] origin:064-gtp-channel-conf 01_506 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[6] origin:064-gtp-channel-conf 00_507 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[7] origin:064-gtp-channel-conf 01_507 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[8] origin:064-gtp-channel-conf 00_508 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ALIGN_MCOMMA_VALUE[9] origin:064-gtp-channel-conf 01_508 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ALIGN_PCOMMA_DET origin:064-gtp-channel-conf 01_523 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[0] origin:064-gtp-channel-conf 00_512 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[1] origin:064-gtp-channel-conf 01_512 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[2] origin:064-gtp-channel-conf 00_513 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[3] origin:064-gtp-channel-conf 01_513 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[4] origin:064-gtp-channel-conf 00_514 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[5] origin:064-gtp-channel-conf 01_514 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[6] origin:064-gtp-channel-conf 00_515 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[7] origin:064-gtp-channel-conf 01_515 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[8] origin:064-gtp-channel-conf 00_516 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ALIGN_PCOMMA_VALUE[9] origin:064-gtp-channel-conf 01_516 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CBCC_DATA_SOURCE_SEL.DECODED origin:064-gtp-channel-conf 01_661 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[0] origin:064-gtp-channel-conf 02_392 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[1] origin:064-gtp-channel-conf 03_392 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[2] origin:064-gtp-channel-conf 02_393 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[3] origin:064-gtp-channel-conf 03_393 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[4] origin:064-gtp-channel-conf 02_394 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[5] origin:064-gtp-channel-conf 03_394 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[6] origin:064-gtp-channel-conf 02_395 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[7] origin:064-gtp-channel-conf 03_395 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[8] origin:064-gtp-channel-conf 02_396 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[9] origin:064-gtp-channel-conf 03_396 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[10] origin:064-gtp-channel-conf 02_397 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[11] origin:064-gtp-channel-conf 03_397 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[12] origin:064-gtp-channel-conf 02_398 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[13] origin:064-gtp-channel-conf 03_398 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[14] origin:064-gtp-channel-conf 02_399 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[15] origin:064-gtp-channel-conf 03_399 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[16] origin:064-gtp-channel-conf 02_400 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[17] origin:064-gtp-channel-conf 03_400 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[18] origin:064-gtp-channel-conf 02_401 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[19] origin:064-gtp-channel-conf 03_401 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[20] origin:064-gtp-channel-conf 02_402 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[21] origin:064-gtp-channel-conf 03_402 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[22] origin:064-gtp-channel-conf 02_403 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[23] origin:064-gtp-channel-conf 03_403 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[24] origin:064-gtp-channel-conf 02_404 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[25] origin:064-gtp-channel-conf 03_404 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[26] origin:064-gtp-channel-conf 02_405 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[27] origin:064-gtp-channel-conf 03_405 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[28] origin:064-gtp-channel-conf 02_406 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[29] origin:064-gtp-channel-conf 03_406 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[30] origin:064-gtp-channel-conf 02_407 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[31] origin:064-gtp-channel-conf 03_407 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[32] origin:064-gtp-channel-conf 02_408 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[33] origin:064-gtp-channel-conf 03_408 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[34] origin:064-gtp-channel-conf 02_409 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[35] origin:064-gtp-channel-conf 03_409 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[36] origin:064-gtp-channel-conf 02_410 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[37] origin:064-gtp-channel-conf 03_410 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[38] origin:064-gtp-channel-conf 02_411 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[39] origin:064-gtp-channel-conf 03_411 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[40] origin:064-gtp-channel-conf 02_412 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[41] origin:064-gtp-channel-conf 03_412 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG[42] origin:064-gtp-channel-conf 02_413 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG2[0] origin:064-gtp-channel-conf 02_459 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG2[1] origin:064-gtp-channel-conf 03_459 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG2[2] origin:064-gtp-channel-conf 02_460 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG2[3] origin:064-gtp-channel-conf 03_460 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG2[4] origin:064-gtp-channel-conf 02_461 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG2[5] origin:064-gtp-channel-conf 03_461 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG2[6] origin:064-gtp-channel-conf 02_462 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG3[0] origin:064-gtp-channel-conf 02_416 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG3[1] origin:064-gtp-channel-conf 03_416 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG3[2] origin:064-gtp-channel-conf 02_417 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG3[3] origin:064-gtp-channel-conf 03_417 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG3[4] origin:064-gtp-channel-conf 02_418 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG3[5] origin:064-gtp-channel-conf 03_418 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG3[6] origin:064-gtp-channel-conf 02_419 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG4[0] origin:064-gtp-channel-conf 03_438 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG5[0] origin:064-gtp-channel-conf 02_429 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG5[1] origin:064-gtp-channel-conf 03_429 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG6[0] origin:064-gtp-channel-conf 03_436 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG6[1] origin:064-gtp-channel-conf 02_437 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG6[2] origin:064-gtp-channel-conf 03_437 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CFOK_CFG6[3] origin:064-gtp-channel-conf 02_438 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_KEEP_ALIGN origin:064-gtp-channel-conf 01_631 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_MAX_SKEW[0] origin:064-gtp-channel-conf 00_670 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_MAX_SKEW[1] origin:064-gtp-channel-conf 01_670 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_MAX_SKEW[2] origin:064-gtp-channel-conf 00_671 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_MAX_SKEW[3] origin:064-gtp-channel-conf 01_671 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[0] origin:064-gtp-channel-conf 00_608 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[1] origin:064-gtp-channel-conf 01_608 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[2] origin:064-gtp-channel-conf 00_609 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[3] origin:064-gtp-channel-conf 01_609 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[4] origin:064-gtp-channel-conf 00_610 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[5] origin:064-gtp-channel-conf 01_610 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[6] origin:064-gtp-channel-conf 00_611 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[7] origin:064-gtp-channel-conf 01_611 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[8] origin:064-gtp-channel-conf 00_612 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_1[9] origin:064-gtp-channel-conf 01_612 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[0] origin:064-gtp-channel-conf 00_616 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[1] origin:064-gtp-channel-conf 01_616 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[2] origin:064-gtp-channel-conf 00_617 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[3] origin:064-gtp-channel-conf 01_617 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[4] origin:064-gtp-channel-conf 00_618 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[5] origin:064-gtp-channel-conf 01_618 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[6] origin:064-gtp-channel-conf 00_619 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[7] origin:064-gtp-channel-conf 01_619 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[8] origin:064-gtp-channel-conf 00_620 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_2[9] origin:064-gtp-channel-conf 01_620 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[0] origin:064-gtp-channel-conf 00_624 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[1] origin:064-gtp-channel-conf 01_624 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[2] origin:064-gtp-channel-conf 00_625 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[3] origin:064-gtp-channel-conf 01_625 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[4] origin:064-gtp-channel-conf 00_626 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[5] origin:064-gtp-channel-conf 01_626 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[6] origin:064-gtp-channel-conf 00_627 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[7] origin:064-gtp-channel-conf 01_627 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[8] origin:064-gtp-channel-conf 00_628 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_3[9] origin:064-gtp-channel-conf 01_628 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[0] origin:064-gtp-channel-conf 00_632 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[1] origin:064-gtp-channel-conf 01_632 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[2] origin:064-gtp-channel-conf 00_633 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[3] origin:064-gtp-channel-conf 01_633 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[4] origin:064-gtp-channel-conf 00_634 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[5] origin:064-gtp-channel-conf 01_634 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[6] origin:064-gtp-channel-conf 00_635 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[7] origin:064-gtp-channel-conf 01_635 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[8] origin:064-gtp-channel-conf 00_636 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_4[9] origin:064-gtp-channel-conf 01_636 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_ENABLE[0] origin:064-gtp-channel-conf 00_614 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_ENABLE[1] origin:064-gtp-channel-conf 01_614 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_ENABLE[2] origin:064-gtp-channel-conf 00_615 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_1_ENABLE[3] origin:064-gtp-channel-conf 01_615 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[0] origin:064-gtp-channel-conf 00_640 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[1] origin:064-gtp-channel-conf 01_640 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[2] origin:064-gtp-channel-conf 00_641 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[3] origin:064-gtp-channel-conf 01_641 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[4] origin:064-gtp-channel-conf 00_642 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[5] origin:064-gtp-channel-conf 01_642 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[6] origin:064-gtp-channel-conf 00_643 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[7] origin:064-gtp-channel-conf 01_643 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[8] origin:064-gtp-channel-conf 00_644 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_1[9] origin:064-gtp-channel-conf 01_644 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[0] origin:064-gtp-channel-conf 00_648 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[1] origin:064-gtp-channel-conf 01_648 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[2] origin:064-gtp-channel-conf 00_649 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[3] origin:064-gtp-channel-conf 01_649 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[4] origin:064-gtp-channel-conf 00_650 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[5] origin:064-gtp-channel-conf 01_650 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[6] origin:064-gtp-channel-conf 00_651 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[7] origin:064-gtp-channel-conf 01_651 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[8] origin:064-gtp-channel-conf 00_652 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_2[9] origin:064-gtp-channel-conf 01_652 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[0] origin:064-gtp-channel-conf 00_656 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[1] origin:064-gtp-channel-conf 01_656 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[2] origin:064-gtp-channel-conf 00_657 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[3] origin:064-gtp-channel-conf 01_657 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[4] origin:064-gtp-channel-conf 00_658 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[5] origin:064-gtp-channel-conf 01_658 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[6] origin:064-gtp-channel-conf 00_659 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[7] origin:064-gtp-channel-conf 01_659 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[8] origin:064-gtp-channel-conf 00_660 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_3[9] origin:064-gtp-channel-conf 01_660 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[0] origin:064-gtp-channel-conf 00_664 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[1] origin:064-gtp-channel-conf 01_664 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[2] origin:064-gtp-channel-conf 00_665 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[3] origin:064-gtp-channel-conf 01_665 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[4] origin:064-gtp-channel-conf 00_666 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[5] origin:064-gtp-channel-conf 01_666 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[6] origin:064-gtp-channel-conf 00_667 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[7] origin:064-gtp-channel-conf 01_667 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[8] origin:064-gtp-channel-conf 00_668 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_4[9] origin:064-gtp-channel-conf 01_668 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_ENABLE[0] origin:064-gtp-channel-conf 00_646 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_ENABLE[1] origin:064-gtp-channel-conf 01_646 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_ENABLE[2] origin:064-gtp-channel-conf 00_647 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_ENABLE[3] origin:064-gtp-channel-conf 01_647 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_2_USE origin:064-gtp-channel-conf 01_645 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_LEN[0] origin:064-gtp-channel-conf 00_623 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CHAN_BOND_SEQ_LEN[1] origin:064-gtp-channel-conf 01_623 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COMMON_SWING[0] origin:064-gtp-channel-conf 03_311 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_KEEP_IDLE origin:064-gtp-channel-conf 00_591 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_MAX_LAT[0] origin:064-gtp-channel-conf 00_557 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_MAX_LAT[1] origin:064-gtp-channel-conf 01_557 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_MAX_LAT[2] origin:064-gtp-channel-conf 00_558 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_MAX_LAT[3] origin:064-gtp-channel-conf 01_558 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_MAX_LAT[4] origin:064-gtp-channel-conf 00_559 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_MAX_LAT[5] origin:064-gtp-channel-conf 01_559 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_MIN_LAT[0] origin:064-gtp-channel-conf 00_565 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_MIN_LAT[1] origin:064-gtp-channel-conf 01_565 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_MIN_LAT[2] origin:064-gtp-channel-conf 00_566 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_MIN_LAT[3] origin:064-gtp-channel-conf 01_566 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_MIN_LAT[4] origin:064-gtp-channel-conf 00_567 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_MIN_LAT[5] origin:064-gtp-channel-conf 01_567 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_PRECEDENCE origin:064-gtp-channel-conf 00_590 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_REPEAT_WAIT[0] origin:064-gtp-channel-conf 00_573 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_REPEAT_WAIT[1] origin:064-gtp-channel-conf 01_573 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_REPEAT_WAIT[2] origin:064-gtp-channel-conf 00_574 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_REPEAT_WAIT[3] origin:064-gtp-channel-conf 01_574 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_REPEAT_WAIT[4] origin:064-gtp-channel-conf 00_575 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[0] origin:064-gtp-channel-conf 00_544 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[1] origin:064-gtp-channel-conf 01_544 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[2] origin:064-gtp-channel-conf 00_545 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[3] origin:064-gtp-channel-conf 01_545 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[4] origin:064-gtp-channel-conf 00_546 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[5] origin:064-gtp-channel-conf 01_546 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[6] origin:064-gtp-channel-conf 00_547 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[7] origin:064-gtp-channel-conf 01_547 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[8] origin:064-gtp-channel-conf 00_548 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_1[9] origin:064-gtp-channel-conf 01_548 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[0] origin:064-gtp-channel-conf 00_552 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[1] origin:064-gtp-channel-conf 01_552 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[2] origin:064-gtp-channel-conf 00_553 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[3] origin:064-gtp-channel-conf 01_553 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[4] origin:064-gtp-channel-conf 00_554 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[5] origin:064-gtp-channel-conf 01_554 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[6] origin:064-gtp-channel-conf 00_555 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[7] origin:064-gtp-channel-conf 01_555 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[8] origin:064-gtp-channel-conf 00_556 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_2[9] origin:064-gtp-channel-conf 01_556 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[0] origin:064-gtp-channel-conf 00_560 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[1] origin:064-gtp-channel-conf 01_560 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[2] origin:064-gtp-channel-conf 00_561 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[3] origin:064-gtp-channel-conf 01_561 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[4] origin:064-gtp-channel-conf 00_562 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[5] origin:064-gtp-channel-conf 01_562 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[6] origin:064-gtp-channel-conf 00_563 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[7] origin:064-gtp-channel-conf 01_563 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[8] origin:064-gtp-channel-conf 00_564 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_3[9] origin:064-gtp-channel-conf 01_564 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[0] origin:064-gtp-channel-conf 00_568 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[1] origin:064-gtp-channel-conf 01_568 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[2] origin:064-gtp-channel-conf 00_569 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[3] origin:064-gtp-channel-conf 01_569 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[4] origin:064-gtp-channel-conf 00_570 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[5] origin:064-gtp-channel-conf 01_570 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[6] origin:064-gtp-channel-conf 00_571 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[7] origin:064-gtp-channel-conf 01_571 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[8] origin:064-gtp-channel-conf 00_572 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_4[9] origin:064-gtp-channel-conf 01_572 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_ENABLE[0] origin:064-gtp-channel-conf 00_549 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_ENABLE[1] origin:064-gtp-channel-conf 01_549 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_ENABLE[2] origin:064-gtp-channel-conf 00_550 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_1_ENABLE[3] origin:064-gtp-channel-conf 01_550 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[0] origin:064-gtp-channel-conf 00_576 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[1] origin:064-gtp-channel-conf 01_576 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[2] origin:064-gtp-channel-conf 00_577 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[3] origin:064-gtp-channel-conf 01_577 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[4] origin:064-gtp-channel-conf 00_578 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[5] origin:064-gtp-channel-conf 01_578 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[6] origin:064-gtp-channel-conf 00_579 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[7] origin:064-gtp-channel-conf 01_579 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[8] origin:064-gtp-channel-conf 00_580 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_1[9] origin:064-gtp-channel-conf 01_580 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[0] origin:064-gtp-channel-conf 00_584 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[1] origin:064-gtp-channel-conf 01_584 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[2] origin:064-gtp-channel-conf 00_585 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[3] origin:064-gtp-channel-conf 01_585 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[4] origin:064-gtp-channel-conf 00_586 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[5] origin:064-gtp-channel-conf 01_586 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[6] origin:064-gtp-channel-conf 00_587 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[7] origin:064-gtp-channel-conf 01_587 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[8] origin:064-gtp-channel-conf 00_588 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_2[9] origin:064-gtp-channel-conf 01_588 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[0] origin:064-gtp-channel-conf 00_592 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[1] origin:064-gtp-channel-conf 01_592 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[2] origin:064-gtp-channel-conf 00_593 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[3] origin:064-gtp-channel-conf 01_593 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[4] origin:064-gtp-channel-conf 00_594 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[5] origin:064-gtp-channel-conf 01_594 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[6] origin:064-gtp-channel-conf 00_595 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[7] origin:064-gtp-channel-conf 01_595 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[8] origin:064-gtp-channel-conf 00_596 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_3[9] origin:064-gtp-channel-conf 01_596 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[0] origin:064-gtp-channel-conf 00_600 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[1] origin:064-gtp-channel-conf 01_600 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[2] origin:064-gtp-channel-conf 00_601 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[3] origin:064-gtp-channel-conf 01_601 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[4] origin:064-gtp-channel-conf 00_602 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[5] origin:064-gtp-channel-conf 01_602 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[6] origin:064-gtp-channel-conf 00_603 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[7] origin:064-gtp-channel-conf 01_603 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[8] origin:064-gtp-channel-conf 00_604 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_4[9] origin:064-gtp-channel-conf 01_604 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_ENABLE[0] origin:064-gtp-channel-conf 00_581 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_ENABLE[1] origin:064-gtp-channel-conf 01_581 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_ENABLE[2] origin:064-gtp-channel-conf 00_582 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_ENABLE[3] origin:064-gtp-channel-conf 01_582 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_2_USE origin:064-gtp-channel-conf 00_583 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_LEN[0] origin:064-gtp-channel-conf 00_589 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_COR_SEQ_LEN[1] origin:064-gtp-channel-conf 01_589 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.CLK_CORRECT_USE origin:064-gtp-channel-conf 00_551 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.DEC_MCOMMA_DETECT origin:064-gtp-channel-conf 01_494 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.DEC_PCOMMA_DETECT origin:064-gtp-channel-conf 00_495 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.DEC_VALID_COMMA_ONLY origin:064-gtp-channel-conf 00_494 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[0] origin:064-gtp-channel-conf 02_368 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[1] origin:064-gtp-channel-conf 03_368 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[2] origin:064-gtp-channel-conf 02_369 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[3] origin:064-gtp-channel-conf 03_369 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[4] origin:064-gtp-channel-conf 02_370 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[5] origin:064-gtp-channel-conf 03_370 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[6] origin:064-gtp-channel-conf 02_371 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[7] origin:064-gtp-channel-conf 03_371 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[8] origin:064-gtp-channel-conf 02_372 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[9] origin:064-gtp-channel-conf 03_372 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[10] origin:064-gtp-channel-conf 02_373 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[11] origin:064-gtp-channel-conf 03_373 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[12] origin:064-gtp-channel-conf 02_374 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[13] origin:064-gtp-channel-conf 03_374 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[14] origin:064-gtp-channel-conf 02_375 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[15] origin:064-gtp-channel-conf 03_375 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[16] origin:064-gtp-channel-conf 02_376 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[17] origin:064-gtp-channel-conf 03_376 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[18] origin:064-gtp-channel-conf 02_377 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[19] origin:064-gtp-channel-conf 03_377 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[20] origin:064-gtp-channel-conf 02_378 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[21] origin:064-gtp-channel-conf 03_378 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[22] origin:064-gtp-channel-conf 02_379 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.DMONITOR_CFG[23] origin:064-gtp-channel-conf 03_379 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_CLK_PHASE_SEL[0] origin:064-gtp-channel-conf 03_463 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_CONTROL[0] origin:064-gtp-channel-conf 00_488 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_CONTROL[1] origin:064-gtp-channel-conf 01_488 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_CONTROL[2] origin:064-gtp-channel-conf 00_489 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_CONTROL[3] origin:064-gtp-channel-conf 01_489 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_CONTROL[4] origin:064-gtp-channel-conf 00_490 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_CONTROL[5] origin:064-gtp-channel-conf 01_490 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_ERRDET_EN origin:064-gtp-channel-conf 01_492 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_EYE_SCAN_EN origin:064-gtp-channel-conf 00_492 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_HORZ_OFFSET[0] origin:064-gtp-channel-conf 00_480 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_HORZ_OFFSET[1] origin:064-gtp-channel-conf 01_480 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_HORZ_OFFSET[2] origin:064-gtp-channel-conf 00_481 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_HORZ_OFFSET[3] origin:064-gtp-channel-conf 01_481 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_HORZ_OFFSET[4] origin:064-gtp-channel-conf 00_482 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_HORZ_OFFSET[5] origin:064-gtp-channel-conf 01_482 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_HORZ_OFFSET[6] origin:064-gtp-channel-conf 00_483 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_HORZ_OFFSET[7] origin:064-gtp-channel-conf 01_483 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_HORZ_OFFSET[8] origin:064-gtp-channel-conf 00_484 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_HORZ_OFFSET[9] origin:064-gtp-channel-conf 01_484 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_HORZ_OFFSET[10] origin:064-gtp-channel-conf 00_485 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_HORZ_OFFSET[11] origin:064-gtp-channel-conf 01_485 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_PMA_CFG[0] origin:064-gtp-channel-conf 02_624 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_PMA_CFG[1] origin:064-gtp-channel-conf 03_624 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_PMA_CFG[2] origin:064-gtp-channel-conf 02_625 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_PMA_CFG[3] origin:064-gtp-channel-conf 03_625 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_PMA_CFG[4] origin:064-gtp-channel-conf 02_626 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_PMA_CFG[5] origin:064-gtp-channel-conf 03_626 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_PMA_CFG[6] origin:064-gtp-channel-conf 02_627 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_PMA_CFG[7] origin:064-gtp-channel-conf 03_627 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_PMA_CFG[8] origin:064-gtp-channel-conf 02_628 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_PMA_CFG[9] origin:064-gtp-channel-conf 03_628 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_PRESCALE[0] origin:064-gtp-channel-conf 01_477 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_PRESCALE[1] origin:064-gtp-channel-conf 00_478 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_PRESCALE[2] origin:064-gtp-channel-conf 01_478 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_PRESCALE[3] origin:064-gtp-channel-conf 00_479 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_PRESCALE[4] origin:064-gtp-channel-conf 01_479 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[0] origin:064-gtp-channel-conf 00_392 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[1] origin:064-gtp-channel-conf 01_392 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[2] origin:064-gtp-channel-conf 00_393 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[3] origin:064-gtp-channel-conf 01_393 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[4] origin:064-gtp-channel-conf 00_394 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[5] origin:064-gtp-channel-conf 01_394 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[6] origin:064-gtp-channel-conf 00_395 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[7] origin:064-gtp-channel-conf 01_395 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[8] origin:064-gtp-channel-conf 00_396 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[9] origin:064-gtp-channel-conf 01_396 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[10] origin:064-gtp-channel-conf 00_397 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[11] origin:064-gtp-channel-conf 01_397 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[12] origin:064-gtp-channel-conf 00_398 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[13] origin:064-gtp-channel-conf 01_398 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[14] origin:064-gtp-channel-conf 00_399 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[15] origin:064-gtp-channel-conf 01_399 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[16] origin:064-gtp-channel-conf 00_400 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[17] origin:064-gtp-channel-conf 01_400 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[18] origin:064-gtp-channel-conf 00_401 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[19] origin:064-gtp-channel-conf 01_401 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[20] origin:064-gtp-channel-conf 00_402 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[21] origin:064-gtp-channel-conf 01_402 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[22] origin:064-gtp-channel-conf 00_403 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[23] origin:064-gtp-channel-conf 01_403 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[24] origin:064-gtp-channel-conf 00_404 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[25] origin:064-gtp-channel-conf 01_404 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[26] origin:064-gtp-channel-conf 00_405 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[27] origin:064-gtp-channel-conf 01_405 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[28] origin:064-gtp-channel-conf 00_406 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[29] origin:064-gtp-channel-conf 01_406 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[30] origin:064-gtp-channel-conf 00_407 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[31] origin:064-gtp-channel-conf 01_407 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[32] origin:064-gtp-channel-conf 00_408 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[33] origin:064-gtp-channel-conf 01_408 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[34] origin:064-gtp-channel-conf 00_409 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[35] origin:064-gtp-channel-conf 01_409 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[36] origin:064-gtp-channel-conf 00_410 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[37] origin:064-gtp-channel-conf 01_410 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[38] origin:064-gtp-channel-conf 00_411 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[39] origin:064-gtp-channel-conf 01_411 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[40] origin:064-gtp-channel-conf 00_412 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[41] origin:064-gtp-channel-conf 01_412 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[42] origin:064-gtp-channel-conf 00_413 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[43] origin:064-gtp-channel-conf 01_413 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[44] origin:064-gtp-channel-conf 00_414 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[45] origin:064-gtp-channel-conf 01_414 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[46] origin:064-gtp-channel-conf 00_415 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[47] origin:064-gtp-channel-conf 01_415 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[48] origin:064-gtp-channel-conf 00_416 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[49] origin:064-gtp-channel-conf 01_416 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[50] origin:064-gtp-channel-conf 00_417 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[51] origin:064-gtp-channel-conf 01_417 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[52] origin:064-gtp-channel-conf 00_418 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[53] origin:064-gtp-channel-conf 01_418 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[54] origin:064-gtp-channel-conf 00_419 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[55] origin:064-gtp-channel-conf 01_419 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[56] origin:064-gtp-channel-conf 00_420 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[57] origin:064-gtp-channel-conf 01_420 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[58] origin:064-gtp-channel-conf 00_421 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[59] origin:064-gtp-channel-conf 01_421 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[60] origin:064-gtp-channel-conf 00_422 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[61] origin:064-gtp-channel-conf 01_422 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[62] origin:064-gtp-channel-conf 00_423 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[63] origin:064-gtp-channel-conf 01_423 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[64] origin:064-gtp-channel-conf 00_424 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[65] origin:064-gtp-channel-conf 01_424 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[66] origin:064-gtp-channel-conf 00_425 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[67] origin:064-gtp-channel-conf 01_425 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[68] origin:064-gtp-channel-conf 00_426 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[69] origin:064-gtp-channel-conf 01_426 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[70] origin:064-gtp-channel-conf 00_427 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[71] origin:064-gtp-channel-conf 01_427 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[72] origin:064-gtp-channel-conf 00_428 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[73] origin:064-gtp-channel-conf 01_428 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[74] origin:064-gtp-channel-conf 00_429 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[75] origin:064-gtp-channel-conf 01_429 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[76] origin:064-gtp-channel-conf 00_430 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[77] origin:064-gtp-channel-conf 01_430 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[78] origin:064-gtp-channel-conf 00_431 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUAL_MASK[79] origin:064-gtp-channel-conf 01_431 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[0] origin:064-gtp-channel-conf 00_352 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[1] origin:064-gtp-channel-conf 01_352 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[2] origin:064-gtp-channel-conf 00_353 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[3] origin:064-gtp-channel-conf 01_353 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[4] origin:064-gtp-channel-conf 00_354 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[5] origin:064-gtp-channel-conf 01_354 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[6] origin:064-gtp-channel-conf 00_355 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[7] origin:064-gtp-channel-conf 01_355 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[8] origin:064-gtp-channel-conf 00_356 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[9] origin:064-gtp-channel-conf 01_356 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[10] origin:064-gtp-channel-conf 00_357 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[11] origin:064-gtp-channel-conf 01_357 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[12] origin:064-gtp-channel-conf 00_358 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[13] origin:064-gtp-channel-conf 01_358 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[14] origin:064-gtp-channel-conf 00_359 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[15] origin:064-gtp-channel-conf 01_359 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[16] origin:064-gtp-channel-conf 00_360 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[17] origin:064-gtp-channel-conf 01_360 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[18] origin:064-gtp-channel-conf 00_361 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[19] origin:064-gtp-channel-conf 01_361 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[20] origin:064-gtp-channel-conf 00_362 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[21] origin:064-gtp-channel-conf 01_362 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[22] origin:064-gtp-channel-conf 00_363 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[23] origin:064-gtp-channel-conf 01_363 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[24] origin:064-gtp-channel-conf 00_364 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[25] origin:064-gtp-channel-conf 01_364 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[26] origin:064-gtp-channel-conf 00_365 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[27] origin:064-gtp-channel-conf 01_365 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[28] origin:064-gtp-channel-conf 00_366 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[29] origin:064-gtp-channel-conf 01_366 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[30] origin:064-gtp-channel-conf 00_367 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[31] origin:064-gtp-channel-conf 01_367 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[32] origin:064-gtp-channel-conf 00_368 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[33] origin:064-gtp-channel-conf 01_368 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[34] origin:064-gtp-channel-conf 00_369 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[35] origin:064-gtp-channel-conf 01_369 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[36] origin:064-gtp-channel-conf 00_370 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[37] origin:064-gtp-channel-conf 01_370 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[38] origin:064-gtp-channel-conf 00_371 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[39] origin:064-gtp-channel-conf 01_371 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[40] origin:064-gtp-channel-conf 00_372 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[41] origin:064-gtp-channel-conf 01_372 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[42] origin:064-gtp-channel-conf 00_373 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[43] origin:064-gtp-channel-conf 01_373 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[44] origin:064-gtp-channel-conf 00_374 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[45] origin:064-gtp-channel-conf 01_374 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[46] origin:064-gtp-channel-conf 00_375 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[47] origin:064-gtp-channel-conf 01_375 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[48] origin:064-gtp-channel-conf 00_376 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[49] origin:064-gtp-channel-conf 01_376 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[50] origin:064-gtp-channel-conf 00_377 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[51] origin:064-gtp-channel-conf 01_377 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[52] origin:064-gtp-channel-conf 00_378 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[53] origin:064-gtp-channel-conf 01_378 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[54] origin:064-gtp-channel-conf 00_379 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[55] origin:064-gtp-channel-conf 01_379 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[56] origin:064-gtp-channel-conf 00_380 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[57] origin:064-gtp-channel-conf 01_380 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[58] origin:064-gtp-channel-conf 00_381 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[59] origin:064-gtp-channel-conf 01_381 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[60] origin:064-gtp-channel-conf 00_382 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[61] origin:064-gtp-channel-conf 01_382 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[62] origin:064-gtp-channel-conf 00_383 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[63] origin:064-gtp-channel-conf 01_383 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[64] origin:064-gtp-channel-conf 00_384 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[65] origin:064-gtp-channel-conf 01_384 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[66] origin:064-gtp-channel-conf 00_385 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[67] origin:064-gtp-channel-conf 01_385 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[68] origin:064-gtp-channel-conf 00_386 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[69] origin:064-gtp-channel-conf 01_386 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[70] origin:064-gtp-channel-conf 00_387 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[71] origin:064-gtp-channel-conf 01_387 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[72] origin:064-gtp-channel-conf 00_388 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[73] origin:064-gtp-channel-conf 01_388 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[74] origin:064-gtp-channel-conf 00_389 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[75] origin:064-gtp-channel-conf 01_389 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[76] origin:064-gtp-channel-conf 00_390 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[77] origin:064-gtp-channel-conf 01_390 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[78] origin:064-gtp-channel-conf 00_391 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_QUALIFIER[79] origin:064-gtp-channel-conf 01_391 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[0] origin:064-gtp-channel-conf 00_432 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[1] origin:064-gtp-channel-conf 01_432 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[2] origin:064-gtp-channel-conf 00_433 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[3] origin:064-gtp-channel-conf 01_433 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[4] origin:064-gtp-channel-conf 00_434 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[5] origin:064-gtp-channel-conf 01_434 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[6] origin:064-gtp-channel-conf 00_435 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[7] origin:064-gtp-channel-conf 01_435 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[8] origin:064-gtp-channel-conf 00_436 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[9] origin:064-gtp-channel-conf 01_436 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[10] origin:064-gtp-channel-conf 00_437 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[11] origin:064-gtp-channel-conf 01_437 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[12] origin:064-gtp-channel-conf 00_438 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[13] origin:064-gtp-channel-conf 01_438 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[14] origin:064-gtp-channel-conf 00_439 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[15] origin:064-gtp-channel-conf 01_439 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[16] origin:064-gtp-channel-conf 00_440 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[17] origin:064-gtp-channel-conf 01_440 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[18] origin:064-gtp-channel-conf 00_441 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[19] origin:064-gtp-channel-conf 01_441 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[20] origin:064-gtp-channel-conf 00_442 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[21] origin:064-gtp-channel-conf 01_442 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[22] origin:064-gtp-channel-conf 00_443 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[23] origin:064-gtp-channel-conf 01_443 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[24] origin:064-gtp-channel-conf 00_444 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[25] origin:064-gtp-channel-conf 01_444 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[26] origin:064-gtp-channel-conf 00_445 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[27] origin:064-gtp-channel-conf 01_445 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[28] origin:064-gtp-channel-conf 00_446 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[29] origin:064-gtp-channel-conf 01_446 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[30] origin:064-gtp-channel-conf 00_447 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[31] origin:064-gtp-channel-conf 01_447 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[32] origin:064-gtp-channel-conf 00_448 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[33] origin:064-gtp-channel-conf 01_448 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[34] origin:064-gtp-channel-conf 00_449 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[35] origin:064-gtp-channel-conf 01_449 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[36] origin:064-gtp-channel-conf 00_450 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[37] origin:064-gtp-channel-conf 01_450 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[38] origin:064-gtp-channel-conf 00_451 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[39] origin:064-gtp-channel-conf 01_451 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[40] origin:064-gtp-channel-conf 00_452 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[41] origin:064-gtp-channel-conf 01_452 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[42] origin:064-gtp-channel-conf 00_453 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[43] origin:064-gtp-channel-conf 01_453 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[44] origin:064-gtp-channel-conf 00_454 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[45] origin:064-gtp-channel-conf 01_454 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[46] origin:064-gtp-channel-conf 00_455 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[47] origin:064-gtp-channel-conf 01_455 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[48] origin:064-gtp-channel-conf 00_456 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[49] origin:064-gtp-channel-conf 01_456 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[50] origin:064-gtp-channel-conf 00_457 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[51] origin:064-gtp-channel-conf 01_457 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[52] origin:064-gtp-channel-conf 00_458 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[53] origin:064-gtp-channel-conf 01_458 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[54] origin:064-gtp-channel-conf 00_459 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[55] origin:064-gtp-channel-conf 01_459 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[56] origin:064-gtp-channel-conf 00_460 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[57] origin:064-gtp-channel-conf 01_460 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[58] origin:064-gtp-channel-conf 00_461 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[59] origin:064-gtp-channel-conf 01_461 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[60] origin:064-gtp-channel-conf 00_462 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[61] origin:064-gtp-channel-conf 01_462 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[62] origin:064-gtp-channel-conf 00_463 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[63] origin:064-gtp-channel-conf 01_463 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[64] origin:064-gtp-channel-conf 00_464 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[65] origin:064-gtp-channel-conf 01_464 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[66] origin:064-gtp-channel-conf 00_465 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[67] origin:064-gtp-channel-conf 01_465 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[68] origin:064-gtp-channel-conf 00_466 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[69] origin:064-gtp-channel-conf 01_466 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[70] origin:064-gtp-channel-conf 00_467 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[71] origin:064-gtp-channel-conf 01_467 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[72] origin:064-gtp-channel-conf 00_468 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[73] origin:064-gtp-channel-conf 01_468 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[74] origin:064-gtp-channel-conf 00_469 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[75] origin:064-gtp-channel-conf 01_469 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[76] origin:064-gtp-channel-conf 00_470 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[77] origin:064-gtp-channel-conf 01_470 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[78] origin:064-gtp-channel-conf 00_471 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_SDATA_MASK[79] origin:064-gtp-channel-conf 01_471 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_VERT_OFFSET[0] origin:064-gtp-channel-conf 00_472 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_VERT_OFFSET[1] origin:064-gtp-channel-conf 01_472 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_VERT_OFFSET[2] origin:064-gtp-channel-conf 00_473 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_VERT_OFFSET[3] origin:064-gtp-channel-conf 01_473 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_VERT_OFFSET[4] origin:064-gtp-channel-conf 00_474 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_VERT_OFFSET[5] origin:064-gtp-channel-conf 01_474 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_VERT_OFFSET[6] origin:064-gtp-channel-conf 00_475 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_VERT_OFFSET[7] origin:064-gtp-channel-conf 01_475 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.ES_VERT_OFFSET[8] origin:064-gtp-channel-conf 00_476 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.FTS_DESKEW_SEQ_ENABLE[0] origin:064-gtp-channel-conf 00_662 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.FTS_DESKEW_SEQ_ENABLE[1] origin:064-gtp-channel-conf 01_662 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.FTS_DESKEW_SEQ_ENABLE[2] origin:064-gtp-channel-conf 00_663 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.FTS_DESKEW_SEQ_ENABLE[3] origin:064-gtp-channel-conf 01_663 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.FTS_LANE_DESKEW_CFG[0] origin:064-gtp-channel-conf 00_654 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.FTS_LANE_DESKEW_CFG[1] origin:064-gtp-channel-conf 01_654 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.FTS_LANE_DESKEW_CFG[2] origin:064-gtp-channel-conf 00_655 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.FTS_LANE_DESKEW_CFG[3] origin:064-gtp-channel-conf 01_655 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.FTS_LANE_DESKEW_EN origin:064-gtp-channel-conf 01_653 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.GEARBOX_MODE[0] origin:064-gtp-channel-conf 00_224 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.GEARBOX_MODE[1] origin:064-gtp-channel-conf 01_224 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.GEARBOX_MODE[2] origin:064-gtp-channel-conf 00_225 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.IN_USE origin:064-gtp-channel-conf 00_00 00_01 00_47 00_52 00_53 00_65 01_01 01_47 02_129 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.INV_DMONITORCLK origin:064-gtp-channel-conf 02_13 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.INV_DRPCLK origin:064-gtp-channel-conf 02_00 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.INV_RXUSRCLK origin:064-gtp-channel-conf 03_01 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.INV_SIGVALIDCLK origin:064-gtp-channel-conf 03_13 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.INV_TXPHDLYTSTCLK origin:064-gtp-channel-conf 02_03 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.INV_TXUSRCLK origin:064-gtp-channel-conf 03_04 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.INV_CLKRSVD0 origin:064-gtp-channel-conf 02_23 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.INV_CLKRSVD1 origin:064-gtp-channel-conf 03_23 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.INV_RXUSRCLK2 origin:064-gtp-channel-conf 02_02 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.INV_TXUSRCLK2 origin:064-gtp-channel-conf 02_05 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.LOOPBACK_CFG[0] origin:064-gtp-channel-conf 02_20 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.OUTREFCLK_SEL_INV[0] origin:064-gtp-channel-conf 00_149 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.OUTREFCLK_SEL_INV[1] origin:064-gtp-channel-conf 01_149 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PCS_PCIE_EN origin:064-gtp-channel-conf 00_216 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[0] origin:064-gtp-channel-conf 02_184 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[1] origin:064-gtp-channel-conf 03_184 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[2] origin:064-gtp-channel-conf 02_185 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[3] origin:064-gtp-channel-conf 03_185 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[4] origin:064-gtp-channel-conf 02_186 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[5] origin:064-gtp-channel-conf 03_186 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[6] origin:064-gtp-channel-conf 02_187 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[7] origin:064-gtp-channel-conf 03_187 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[8] origin:064-gtp-channel-conf 02_188 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[9] origin:064-gtp-channel-conf 03_188 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[10] origin:064-gtp-channel-conf 02_189 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[11] origin:064-gtp-channel-conf 03_189 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[12] origin:064-gtp-channel-conf 02_190 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[13] origin:064-gtp-channel-conf 03_190 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[14] origin:064-gtp-channel-conf 02_191 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[15] origin:064-gtp-channel-conf 03_191 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[16] origin:064-gtp-channel-conf 02_192 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[17] origin:064-gtp-channel-conf 03_192 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[18] origin:064-gtp-channel-conf 02_193 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[19] origin:064-gtp-channel-conf 03_193 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[20] origin:064-gtp-channel-conf 02_194 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[21] origin:064-gtp-channel-conf 03_194 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[22] origin:064-gtp-channel-conf 02_195 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[23] origin:064-gtp-channel-conf 03_195 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[24] origin:064-gtp-channel-conf 02_196 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[25] origin:064-gtp-channel-conf 03_196 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[26] origin:064-gtp-channel-conf 02_197 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[27] origin:064-gtp-channel-conf 03_197 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[28] origin:064-gtp-channel-conf 02_198 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[29] origin:064-gtp-channel-conf 03_198 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[30] origin:064-gtp-channel-conf 02_199 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[31] origin:064-gtp-channel-conf 03_199 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[32] origin:064-gtp-channel-conf 02_200 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[33] origin:064-gtp-channel-conf 03_200 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[34] origin:064-gtp-channel-conf 02_201 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[35] origin:064-gtp-channel-conf 03_201 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[36] origin:064-gtp-channel-conf 02_202 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[37] origin:064-gtp-channel-conf 03_202 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[38] origin:064-gtp-channel-conf 02_203 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[39] origin:064-gtp-channel-conf 03_203 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[40] origin:064-gtp-channel-conf 02_204 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[41] origin:064-gtp-channel-conf 03_204 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[42] origin:064-gtp-channel-conf 02_205 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[43] origin:064-gtp-channel-conf 03_205 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[44] origin:064-gtp-channel-conf 02_206 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[45] origin:064-gtp-channel-conf 03_206 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[46] origin:064-gtp-channel-conf 02_207 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PCS_RSVD_ATTR[47] origin:064-gtp-channel-conf 03_207 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[0] origin:064-gtp-channel-conf 01_216 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[1] origin:064-gtp-channel-conf 00_217 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[2] origin:064-gtp-channel-conf 01_217 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[3] origin:064-gtp-channel-conf 00_218 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[4] origin:064-gtp-channel-conf 01_218 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[5] origin:064-gtp-channel-conf 00_219 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[6] origin:064-gtp-channel-conf 01_219 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[7] origin:064-gtp-channel-conf 00_220 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[8] origin:064-gtp-channel-conf 01_220 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[9] origin:064-gtp-channel-conf 00_221 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[10] origin:064-gtp-channel-conf 01_221 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_FROM_P2[11] origin:064-gtp-channel-conf 00_222 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[0] origin:064-gtp-channel-conf 00_208 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[1] origin:064-gtp-channel-conf 01_208 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[2] origin:064-gtp-channel-conf 00_209 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[3] origin:064-gtp-channel-conf 01_209 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[4] origin:064-gtp-channel-conf 00_210 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[5] origin:064-gtp-channel-conf 01_210 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[6] origin:064-gtp-channel-conf 00_211 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_NONE_P2[7] origin:064-gtp-channel-conf 01_211 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[0] origin:064-gtp-channel-conf 00_212 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[1] origin:064-gtp-channel-conf 01_212 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[2] origin:064-gtp-channel-conf 00_213 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[3] origin:064-gtp-channel-conf 01_213 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[4] origin:064-gtp-channel-conf 00_214 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[5] origin:064-gtp-channel-conf 01_214 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[6] origin:064-gtp-channel-conf 00_215 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PD_TRANS_TIME_TO_P2[7] origin:064-gtp-channel-conf 01_215 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PMA_LOOPBACK_CFG[0] origin:064-gtp-channel-conf 01_207 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[0] origin:064-gtp-channel-conf 02_520 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[1] origin:064-gtp-channel-conf 03_520 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[2] origin:064-gtp-channel-conf 02_521 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[3] origin:064-gtp-channel-conf 03_521 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[4] origin:064-gtp-channel-conf 02_522 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[5] origin:064-gtp-channel-conf 03_522 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[6] origin:064-gtp-channel-conf 02_523 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[7] origin:064-gtp-channel-conf 03_523 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[8] origin:064-gtp-channel-conf 02_524 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[9] origin:064-gtp-channel-conf 03_524 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[10] origin:064-gtp-channel-conf 02_525 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[11] origin:064-gtp-channel-conf 03_525 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[12] origin:064-gtp-channel-conf 02_526 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[13] origin:064-gtp-channel-conf 03_526 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[14] origin:064-gtp-channel-conf 02_527 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[15] origin:064-gtp-channel-conf 03_527 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[16] origin:064-gtp-channel-conf 02_528 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[17] origin:064-gtp-channel-conf 03_528 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[18] origin:064-gtp-channel-conf 02_529 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[19] origin:064-gtp-channel-conf 03_529 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[20] origin:064-gtp-channel-conf 02_530 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[21] origin:064-gtp-channel-conf 03_530 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[22] origin:064-gtp-channel-conf 02_531 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[23] origin:064-gtp-channel-conf 03_531 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[24] origin:064-gtp-channel-conf 02_532 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[25] origin:064-gtp-channel-conf 03_532 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[26] origin:064-gtp-channel-conf 02_533 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[27] origin:064-gtp-channel-conf 03_533 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[28] origin:064-gtp-channel-conf 02_534 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[29] origin:064-gtp-channel-conf 03_534 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[30] origin:064-gtp-channel-conf 02_535 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV[31] origin:064-gtp-channel-conf 03_535 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[0] origin:064-gtp-channel-conf 02_336 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[1] origin:064-gtp-channel-conf 03_336 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[2] origin:064-gtp-channel-conf 02_337 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[3] origin:064-gtp-channel-conf 03_337 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[4] origin:064-gtp-channel-conf 02_338 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[5] origin:064-gtp-channel-conf 03_338 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[6] origin:064-gtp-channel-conf 02_339 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[7] origin:064-gtp-channel-conf 03_339 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[8] origin:064-gtp-channel-conf 02_340 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[9] origin:064-gtp-channel-conf 03_340 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[10] origin:064-gtp-channel-conf 02_341 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[11] origin:064-gtp-channel-conf 03_341 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[12] origin:064-gtp-channel-conf 02_342 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[13] origin:064-gtp-channel-conf 03_342 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[14] origin:064-gtp-channel-conf 02_343 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[15] origin:064-gtp-channel-conf 03_343 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[16] origin:064-gtp-channel-conf 02_344 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[17] origin:064-gtp-channel-conf 03_344 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[18] origin:064-gtp-channel-conf 02_345 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[19] origin:064-gtp-channel-conf 03_345 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[20] origin:064-gtp-channel-conf 02_346 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[21] origin:064-gtp-channel-conf 03_346 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[22] origin:064-gtp-channel-conf 02_347 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[23] origin:064-gtp-channel-conf 03_347 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[24] origin:064-gtp-channel-conf 02_348 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[25] origin:064-gtp-channel-conf 03_348 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[26] origin:064-gtp-channel-conf 02_349 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[27] origin:064-gtp-channel-conf 03_349 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[28] origin:064-gtp-channel-conf 02_350 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[29] origin:064-gtp-channel-conf 03_350 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[30] origin:064-gtp-channel-conf 02_351 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV2[31] origin:064-gtp-channel-conf 03_351 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV3[0] origin:064-gtp-channel-conf 02_288 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV3[1] origin:064-gtp-channel-conf 03_288 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV4[0] origin:064-gtp-channel-conf 02_156 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV4[1] origin:064-gtp-channel-conf 03_156 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV4[2] origin:064-gtp-channel-conf 02_157 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV4[3] origin:064-gtp-channel-conf 03_157 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV5[0] origin:064-gtp-channel-conf 03_159 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV6[0] origin:064-gtp-channel-conf 02_303 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.PMA_RSV7[0] origin:064-gtp-channel-conf 03_303 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_BIAS_CFG[0] origin:064-gtp-channel-conf 02_112 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_BIAS_CFG[1] origin:064-gtp-channel-conf 03_112 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_BIAS_CFG[2] origin:064-gtp-channel-conf 02_113 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_BIAS_CFG[3] origin:064-gtp-channel-conf 03_113 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_BIAS_CFG[4] origin:064-gtp-channel-conf 02_114 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_BIAS_CFG[5] origin:064-gtp-channel-conf 03_114 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_BIAS_CFG[6] origin:064-gtp-channel-conf 02_115 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_BIAS_CFG[7] origin:064-gtp-channel-conf 03_115 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_BIAS_CFG[8] origin:064-gtp-channel-conf 02_116 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_BIAS_CFG[9] origin:064-gtp-channel-conf 03_116 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_BIAS_CFG[10] origin:064-gtp-channel-conf 02_117 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_BIAS_CFG[11] origin:064-gtp-channel-conf 03_117 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_BIAS_CFG[12] origin:064-gtp-channel-conf 02_118 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_BIAS_CFG[13] origin:064-gtp-channel-conf 03_118 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_BIAS_CFG[14] origin:064-gtp-channel-conf 02_119 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_BIAS_CFG[15] origin:064-gtp-channel-conf 03_119 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_BUFFER_CFG[0] origin:064-gtp-channel-conf 02_536 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_BUFFER_CFG[1] origin:064-gtp-channel-conf 03_536 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_BUFFER_CFG[2] origin:064-gtp-channel-conf 02_537 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_BUFFER_CFG[3] origin:064-gtp-channel-conf 03_537 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_BUFFER_CFG[4] origin:064-gtp-channel-conf 02_538 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_BUFFER_CFG[5] origin:064-gtp-channel-conf 03_538 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_CLKMUX_EN[0] origin:064-gtp-channel-conf 02_128 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_CM_SEL[0] origin:064-gtp-channel-conf 00_138 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_CM_SEL[1] origin:064-gtp-channel-conf 01_138 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_CM_TRIM[0] origin:064-gtp-channel-conf 02_304 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_CM_TRIM[1] origin:064-gtp-channel-conf 03_304 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_CM_TRIM[2] origin:064-gtp-channel-conf 02_305 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_CM_TRIM[3] origin:064-gtp-channel-conf 03_305 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_DATA_WIDTH[0] origin:064-gtp-channel-conf 01_141 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_DATA_WIDTH[1] origin:064-gtp-channel-conf 00_142 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_DATA_WIDTH[2] origin:064-gtp-channel-conf 01_142 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_DDI_SEL[0] origin:064-gtp-channel-conf 00_696 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_DDI_SEL[1] origin:064-gtp-channel-conf 01_696 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_DDI_SEL[2] origin:064-gtp-channel-conf 00_697 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_DDI_SEL[3] origin:064-gtp-channel-conf 01_697 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_DDI_SEL[4] origin:064-gtp-channel-conf 00_698 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_DDI_SEL[5] origin:064-gtp-channel-conf 01_698 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_DEBUG_CFG[0] origin:064-gtp-channel-conf 02_616 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_DEBUG_CFG[1] origin:064-gtp-channel-conf 03_616 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_DEBUG_CFG[2] origin:064-gtp-channel-conf 02_617 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_DEBUG_CFG[3] origin:064-gtp-channel-conf 03_617 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_DEBUG_CFG[4] origin:064-gtp-channel-conf 02_618 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_DEBUG_CFG[5] origin:064-gtp-channel-conf 03_618 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_DEBUG_CFG[6] origin:064-gtp-channel-conf 02_619 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_DEBUG_CFG[7] origin:064-gtp-channel-conf 03_619 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_DEBUG_CFG[8] origin:064-gtp-channel-conf 02_620 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_DEBUG_CFG[9] origin:064-gtp-channel-conf 03_620 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_DEBUG_CFG[10] origin:064-gtp-channel-conf 02_621 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_DEBUG_CFG[11] origin:064-gtp-channel-conf 03_621 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_DEBUG_CFG[12] origin:064-gtp-channel-conf 02_622 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_DEBUG_CFG[13] origin:064-gtp-channel-conf 03_622 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_DEFER_RESET_BUF_EN origin:064-gtp-channel-conf 02_552 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_DISPERR_SEQ_MATCH origin:064-gtp-channel-conf 01_495 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_OS_CFG[0] origin:064-gtp-channel-conf 00_288 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_OS_CFG[1] origin:064-gtp-channel-conf 01_288 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_OS_CFG[2] origin:064-gtp-channel-conf 00_289 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_OS_CFG[3] origin:064-gtp-channel-conf 01_289 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_OS_CFG[4] origin:064-gtp-channel-conf 00_290 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_OS_CFG[5] origin:064-gtp-channel-conf 01_290 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_OS_CFG[6] origin:064-gtp-channel-conf 00_291 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_OS_CFG[7] origin:064-gtp-channel-conf 01_291 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_OS_CFG[8] origin:064-gtp-channel-conf 00_292 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_OS_CFG[9] origin:064-gtp-channel-conf 01_292 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_OS_CFG[10] origin:064-gtp-channel-conf 00_293 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_OS_CFG[11] origin:064-gtp-channel-conf 01_293 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_OS_CFG[12] origin:064-gtp-channel-conf 00_294 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_SIG_VALID_DLY[0] origin:064-gtp-channel-conf 00_524 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_SIG_VALID_DLY[1] origin:064-gtp-channel-conf 01_524 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_SIG_VALID_DLY[2] origin:064-gtp-channel-conf 00_525 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_SIG_VALID_DLY[3] origin:064-gtp-channel-conf 01_525 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_SIG_VALID_DLY[4] origin:064-gtp-channel-conf 00_526 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_XCLK_SEL.RXUSR origin:064-gtp-channel-conf 00_143 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_CLK25_DIV[0] origin:064-gtp-channel-conf 00_139 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_CLK25_DIV[1] origin:064-gtp-channel-conf 01_139 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_CLK25_DIV[2] origin:064-gtp-channel-conf 00_140 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_CLK25_DIV[3] origin:064-gtp-channel-conf 01_140 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RX_CLK25_DIV[4] origin:064-gtp-channel-conf 00_141 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXBUF_ADDR_MODE.FAST origin:064-gtp-channel-conf 03_555 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXBUF_EIDLE_HI_CNT[0] origin:064-gtp-channel-conf 02_558 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXBUF_EIDLE_HI_CNT[1] origin:064-gtp-channel-conf 03_558 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXBUF_EIDLE_HI_CNT[2] origin:064-gtp-channel-conf 02_559 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXBUF_EIDLE_HI_CNT[3] origin:064-gtp-channel-conf 03_559 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXBUF_EIDLE_LO_CNT[0] origin:064-gtp-channel-conf 02_556 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXBUF_EIDLE_LO_CNT[1] origin:064-gtp-channel-conf 03_556 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXBUF_EIDLE_LO_CNT[2] origin:064-gtp-channel-conf 02_557 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXBUF_EIDLE_LO_CNT[3] origin:064-gtp-channel-conf 03_557 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXBUF_EN origin:064-gtp-channel-conf 02_11 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXBUF_RESET_ON_CB_CHANGE origin:064-gtp-channel-conf 02_560 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXBUF_RESET_ON_COMMAALIGN origin:064-gtp-channel-conf 02_561 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXBUF_RESET_ON_EIDLE origin:064-gtp-channel-conf 02_547 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXBUF_RESET_ON_RATE_CHANGE origin:064-gtp-channel-conf 03_560 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXBUF_THRESH_OVFLW[0] origin:064-gtp-channel-conf 03_552 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXBUF_THRESH_OVFLW[1] origin:064-gtp-channel-conf 02_553 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXBUF_THRESH_OVFLW[2] origin:064-gtp-channel-conf 03_553 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXBUF_THRESH_OVFLW[3] origin:064-gtp-channel-conf 02_554 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXBUF_THRESH_OVFLW[4] origin:064-gtp-channel-conf 03_554 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXBUF_THRESH_OVFLW[5] origin:064-gtp-channel-conf 02_555 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXBUF_THRESH_OVRD origin:064-gtp-channel-conf 02_548 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXBUF_THRESH_UNDFLW[0] origin:064-gtp-channel-conf 02_544 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXBUF_THRESH_UNDFLW[1] origin:064-gtp-channel-conf 03_544 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXBUF_THRESH_UNDFLW[2] origin:064-gtp-channel-conf 02_545 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXBUF_THRESH_UNDFLW[3] origin:064-gtp-channel-conf 03_545 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXBUF_THRESH_UNDFLW[4] origin:064-gtp-channel-conf 02_546 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXBUF_THRESH_UNDFLW[5] origin:064-gtp-channel-conf 03_546 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXBUFRESET_TIME[0] origin:064-gtp-channel-conf 01_101 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXBUFRESET_TIME[1] origin:064-gtp-channel-conf 00_102 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXBUFRESET_TIME[2] origin:064-gtp-channel-conf 01_102 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXBUFRESET_TIME[3] origin:064-gtp-channel-conf 00_103 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXBUFRESET_TIME[4] origin:064-gtp-channel-conf 01_103 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[0] origin:064-gtp-channel-conf 02_640 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[1] origin:064-gtp-channel-conf 03_640 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[2] origin:064-gtp-channel-conf 02_641 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[3] origin:064-gtp-channel-conf 03_641 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[4] origin:064-gtp-channel-conf 02_642 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[5] origin:064-gtp-channel-conf 03_642 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[6] origin:064-gtp-channel-conf 02_643 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[7] origin:064-gtp-channel-conf 03_643 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[8] origin:064-gtp-channel-conf 02_644 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[9] origin:064-gtp-channel-conf 03_644 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[10] origin:064-gtp-channel-conf 02_645 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[11] origin:064-gtp-channel-conf 03_645 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[12] origin:064-gtp-channel-conf 02_646 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[13] origin:064-gtp-channel-conf 03_646 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[14] origin:064-gtp-channel-conf 02_647 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[15] origin:064-gtp-channel-conf 03_647 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[16] origin:064-gtp-channel-conf 02_648 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[17] origin:064-gtp-channel-conf 03_648 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[18] origin:064-gtp-channel-conf 02_649 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[19] origin:064-gtp-channel-conf 03_649 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[20] origin:064-gtp-channel-conf 02_650 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[21] origin:064-gtp-channel-conf 03_650 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[22] origin:064-gtp-channel-conf 02_651 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[23] origin:064-gtp-channel-conf 03_651 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[24] origin:064-gtp-channel-conf 02_652 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[25] origin:064-gtp-channel-conf 03_652 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[26] origin:064-gtp-channel-conf 02_653 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[27] origin:064-gtp-channel-conf 03_653 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[28] origin:064-gtp-channel-conf 02_654 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[29] origin:064-gtp-channel-conf 03_654 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[30] origin:064-gtp-channel-conf 02_655 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[31] origin:064-gtp-channel-conf 03_655 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[32] origin:064-gtp-channel-conf 02_656 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[33] origin:064-gtp-channel-conf 03_656 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[34] origin:064-gtp-channel-conf 02_657 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[35] origin:064-gtp-channel-conf 03_657 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[36] origin:064-gtp-channel-conf 02_658 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[37] origin:064-gtp-channel-conf 03_658 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[38] origin:064-gtp-channel-conf 02_659 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[39] origin:064-gtp-channel-conf 03_659 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[40] origin:064-gtp-channel-conf 02_660 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[41] origin:064-gtp-channel-conf 03_660 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[42] origin:064-gtp-channel-conf 02_661 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[43] origin:064-gtp-channel-conf 03_661 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[44] origin:064-gtp-channel-conf 02_662 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[45] origin:064-gtp-channel-conf 03_662 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[46] origin:064-gtp-channel-conf 02_663 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[47] origin:064-gtp-channel-conf 03_663 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[48] origin:064-gtp-channel-conf 02_664 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[49] origin:064-gtp-channel-conf 03_664 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[50] origin:064-gtp-channel-conf 02_665 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[51] origin:064-gtp-channel-conf 03_665 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[52] origin:064-gtp-channel-conf 02_666 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[53] origin:064-gtp-channel-conf 03_666 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[54] origin:064-gtp-channel-conf 02_667 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[55] origin:064-gtp-channel-conf 03_667 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[56] origin:064-gtp-channel-conf 02_668 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[57] origin:064-gtp-channel-conf 03_668 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[58] origin:064-gtp-channel-conf 02_669 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[59] origin:064-gtp-channel-conf 03_669 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[60] origin:064-gtp-channel-conf 02_670 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[61] origin:064-gtp-channel-conf 03_670 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[62] origin:064-gtp-channel-conf 02_671 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[63] origin:064-gtp-channel-conf 03_671 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[64] origin:064-gtp-channel-conf 02_672 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[65] origin:064-gtp-channel-conf 03_672 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[66] origin:064-gtp-channel-conf 02_673 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[67] origin:064-gtp-channel-conf 03_673 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[68] origin:064-gtp-channel-conf 02_674 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[69] origin:064-gtp-channel-conf 03_674 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[70] origin:064-gtp-channel-conf 02_675 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[71] origin:064-gtp-channel-conf 03_675 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[72] origin:064-gtp-channel-conf 02_676 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[73] origin:064-gtp-channel-conf 03_676 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[74] origin:064-gtp-channel-conf 02_677 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[75] origin:064-gtp-channel-conf 03_677 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[76] origin:064-gtp-channel-conf 02_678 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[77] origin:064-gtp-channel-conf 03_678 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[78] origin:064-gtp-channel-conf 02_679 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[79] origin:064-gtp-channel-conf 03_679 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[80] origin:064-gtp-channel-conf 02_680 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[81] origin:064-gtp-channel-conf 03_680 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_CFG[82] origin:064-gtp-channel-conf 02_681 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_FR_RESET_ON_EIDLE[0] origin:064-gtp-channel-conf 02_638 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_HOLD_DURING_EIDLE[0] origin:064-gtp-channel-conf 03_637 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_LOCK_CFG[0] origin:064-gtp-channel-conf 02_632 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_LOCK_CFG[1] origin:064-gtp-channel-conf 03_632 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_LOCK_CFG[2] origin:064-gtp-channel-conf 02_633 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_LOCK_CFG[3] origin:064-gtp-channel-conf 03_633 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_LOCK_CFG[4] origin:064-gtp-channel-conf 02_634 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_LOCK_CFG[5] origin:064-gtp-channel-conf 03_634 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDR_PH_RESET_ON_EIDLE[0] origin:064-gtp-channel-conf 03_638 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDRFREQRESET_TIME[0] origin:064-gtp-channel-conf 01_106 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDRFREQRESET_TIME[1] origin:064-gtp-channel-conf 00_107 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDRFREQRESET_TIME[2] origin:064-gtp-channel-conf 01_107 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDRFREQRESET_TIME[3] origin:064-gtp-channel-conf 00_108 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDRFREQRESET_TIME[4] origin:064-gtp-channel-conf 01_108 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDRPHRESET_TIME[0] origin:064-gtp-channel-conf 00_109 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDRPHRESET_TIME[1] origin:064-gtp-channel-conf 01_109 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDRPHRESET_TIME[2] origin:064-gtp-channel-conf 00_110 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDRPHRESET_TIME[3] origin:064-gtp-channel-conf 01_110 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXCDRPHRESET_TIME[4] origin:064-gtp-channel-conf 00_111 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXDLY_CFG[0] origin:064-gtp-channel-conf 00_680 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXDLY_CFG[1] origin:064-gtp-channel-conf 01_680 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXDLY_CFG[2] origin:064-gtp-channel-conf 00_681 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXDLY_CFG[3] origin:064-gtp-channel-conf 01_681 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXDLY_CFG[4] origin:064-gtp-channel-conf 00_682 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXDLY_CFG[5] origin:064-gtp-channel-conf 01_682 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXDLY_CFG[6] origin:064-gtp-channel-conf 00_683 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXDLY_CFG[7] origin:064-gtp-channel-conf 01_683 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXDLY_CFG[8] origin:064-gtp-channel-conf 00_684 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXDLY_CFG[9] origin:064-gtp-channel-conf 01_684 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXDLY_CFG[10] origin:064-gtp-channel-conf 00_685 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXDLY_CFG[11] origin:064-gtp-channel-conf 01_685 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXDLY_CFG[12] origin:064-gtp-channel-conf 00_686 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXDLY_CFG[13] origin:064-gtp-channel-conf 01_686 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXDLY_CFG[14] origin:064-gtp-channel-conf 00_687 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXDLY_CFG[15] origin:064-gtp-channel-conf 01_687 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXDLY_LCFG[0] origin:064-gtp-channel-conf 02_576 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXDLY_LCFG[1] origin:064-gtp-channel-conf 03_576 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXDLY_LCFG[2] origin:064-gtp-channel-conf 02_577 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXDLY_LCFG[3] origin:064-gtp-channel-conf 03_577 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXDLY_LCFG[4] origin:064-gtp-channel-conf 02_578 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXDLY_LCFG[5] origin:064-gtp-channel-conf 03_578 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXDLY_LCFG[6] origin:064-gtp-channel-conf 02_579 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXDLY_LCFG[7] origin:064-gtp-channel-conf 03_579 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXDLY_LCFG[8] origin:064-gtp-channel-conf 02_580 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXDLY_TAP_CFG[0] origin:064-gtp-channel-conf 00_672 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXDLY_TAP_CFG[1] origin:064-gtp-channel-conf 01_672 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXDLY_TAP_CFG[2] origin:064-gtp-channel-conf 00_673 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXDLY_TAP_CFG[3] origin:064-gtp-channel-conf 01_673 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXDLY_TAP_CFG[4] origin:064-gtp-channel-conf 00_674 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXDLY_TAP_CFG[5] origin:064-gtp-channel-conf 01_674 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXDLY_TAP_CFG[6] origin:064-gtp-channel-conf 00_675 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXDLY_TAP_CFG[7] origin:064-gtp-channel-conf 01_675 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXDLY_TAP_CFG[8] origin:064-gtp-channel-conf 00_676 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXDLY_TAP_CFG[9] origin:064-gtp-channel-conf 01_676 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXDLY_TAP_CFG[10] origin:064-gtp-channel-conf 00_677 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXDLY_TAP_CFG[11] origin:064-gtp-channel-conf 01_677 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXDLY_TAP_CFG[12] origin:064-gtp-channel-conf 00_678 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXDLY_TAP_CFG[13] origin:064-gtp-channel-conf 01_678 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXDLY_TAP_CFG[14] origin:064-gtp-channel-conf 00_679 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXDLY_TAP_CFG[15] origin:064-gtp-channel-conf 01_679 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXGEARBOX_EN origin:064-gtp-channel-conf 01_607 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXISCANRESET_TIME[0] origin:064-gtp-channel-conf 01_123 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXISCANRESET_TIME[1] origin:064-gtp-channel-conf 00_124 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXISCANRESET_TIME[2] origin:064-gtp-channel-conf 01_124 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXISCANRESET_TIME[3] origin:064-gtp-channel-conf 00_125 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXISCANRESET_TIME[4] origin:064-gtp-channel-conf 01_125 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPM_BIAS_STARTUP_DISABLE[0] origin:064-gtp-channel-conf 03_391 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPM_CFG[0] origin:064-gtp-channel-conf 02_328 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPM_CFG[1] origin:064-gtp-channel-conf 03_328 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPM_CFG[2] origin:064-gtp-channel-conf 02_329 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPM_CFG[3] origin:064-gtp-channel-conf 03_329 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPM_CM_CFG[0] origin:064-gtp-channel-conf 02_430 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPM_GC_CFG[0] origin:064-gtp-channel-conf 02_432 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPM_GC_CFG[1] origin:064-gtp-channel-conf 03_432 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPM_GC_CFG[2] origin:064-gtp-channel-conf 02_433 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPM_GC_CFG[3] origin:064-gtp-channel-conf 03_433 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPM_GC_CFG[4] origin:064-gtp-channel-conf 02_434 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPM_GC_CFG[5] origin:064-gtp-channel-conf 03_434 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPM_GC_CFG[6] origin:064-gtp-channel-conf 02_435 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPM_GC_CFG[7] origin:064-gtp-channel-conf 03_435 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPM_GC_CFG[8] origin:064-gtp-channel-conf 02_436 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPM_GC_CFG2[0] origin:064-gtp-channel-conf 03_442 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPM_GC_CFG2[1] origin:064-gtp-channel-conf 02_443 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPM_GC_CFG2[2] origin:064-gtp-channel-conf 03_443 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG[0] origin:064-gtp-channel-conf 00_336 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG[1] origin:064-gtp-channel-conf 01_336 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG[2] origin:064-gtp-channel-conf 00_337 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG[3] origin:064-gtp-channel-conf 01_337 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG[4] origin:064-gtp-channel-conf 00_338 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG[5] origin:064-gtp-channel-conf 01_338 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG[6] origin:064-gtp-channel-conf 00_339 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG[7] origin:064-gtp-channel-conf 01_339 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG[8] origin:064-gtp-channel-conf 00_340 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG[9] origin:064-gtp-channel-conf 01_340 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG[10] origin:064-gtp-channel-conf 00_341 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG[11] origin:064-gtp-channel-conf 01_341 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG[12] origin:064-gtp-channel-conf 00_342 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG[13] origin:064-gtp-channel-conf 01_342 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG2[0] origin:064-gtp-channel-conf 02_424 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG2[1] origin:064-gtp-channel-conf 03_424 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG2[2] origin:064-gtp-channel-conf 02_425 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG2[3] origin:064-gtp-channel-conf 03_425 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG2[4] origin:064-gtp-channel-conf 02_426 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG3[0] origin:064-gtp-channel-conf 03_389 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG3[1] origin:064-gtp-channel-conf 02_390 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG3[2] origin:064-gtp-channel-conf 03_390 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HF_CFG3[3] origin:064-gtp-channel-conf 02_391 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPM_HOLD_DURING_EIDLE[0] origin:064-gtp-channel-conf 00_247 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPM_INCM_CFG[0] origin:064-gtp-channel-conf 02_439 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPM_IPCM_CFG[0] origin:064-gtp-channel-conf 03_439 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG[0] origin:064-gtp-channel-conf 00_344 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG[1] origin:064-gtp-channel-conf 01_344 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG[2] origin:064-gtp-channel-conf 00_345 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG[3] origin:064-gtp-channel-conf 01_345 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG[4] origin:064-gtp-channel-conf 00_346 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG[5] origin:064-gtp-channel-conf 01_346 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG[6] origin:064-gtp-channel-conf 00_347 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG[7] origin:064-gtp-channel-conf 01_347 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG[8] origin:064-gtp-channel-conf 00_348 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG[9] origin:064-gtp-channel-conf 01_348 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG[10] origin:064-gtp-channel-conf 00_349 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG[11] origin:064-gtp-channel-conf 01_349 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG[12] origin:064-gtp-channel-conf 00_350 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG[13] origin:064-gtp-channel-conf 01_350 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG[14] origin:064-gtp-channel-conf 00_351 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG[15] origin:064-gtp-channel-conf 01_351 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG[16] origin:064-gtp-channel-conf 00_343 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG[17] origin:064-gtp-channel-conf 01_343 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG2[0] origin:064-gtp-channel-conf 03_426 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG2[1] origin:064-gtp-channel-conf 02_427 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG2[2] origin:064-gtp-channel-conf 03_427 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG2[3] origin:064-gtp-channel-conf 02_428 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPM_LF_CFG2[4] origin:064-gtp-channel-conf 03_428 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPM_OSINT_CFG[0] origin:064-gtp-channel-conf 02_440 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPM_OSINT_CFG[1] origin:064-gtp-channel-conf 03_440 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPM_OSINT_CFG[2] origin:064-gtp-channel-conf 02_441 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPM_CFG1[0] origin:064-gtp-channel-conf 02_330 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPMRESET_TIME[0] origin:064-gtp-channel-conf 00_112 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPMRESET_TIME[1] origin:064-gtp-channel-conf 01_112 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPMRESET_TIME[2] origin:064-gtp-channel-conf 00_113 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPMRESET_TIME[3] origin:064-gtp-channel-conf 01_113 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPMRESET_TIME[4] origin:064-gtp-channel-conf 00_114 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPMRESET_TIME[5] origin:064-gtp-channel-conf 01_114 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXLPMRESET_TIME[6] origin:064-gtp-channel-conf 00_115 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXOOB_CFG[0] origin:064-gtp-channel-conf 00_144 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXOOB_CFG[1] origin:064-gtp-channel-conf 01_144 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXOOB_CFG[2] origin:064-gtp-channel-conf 00_145 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXOOB_CFG[3] origin:064-gtp-channel-conf 01_145 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXOOB_CFG[4] origin:064-gtp-channel-conf 00_146 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXOOB_CFG[5] origin:064-gtp-channel-conf 01_146 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXOOB_CFG[6] origin:064-gtp-channel-conf 00_147 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXOOB_CLK_CFG.FABRIC origin:064-gtp-channel-conf 03_129 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXOSCALRESET_TIME[0] origin:064-gtp-channel-conf 00_187 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXOSCALRESET_TIME[1] origin:064-gtp-channel-conf 01_187 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXOSCALRESET_TIME[2] origin:064-gtp-channel-conf 00_188 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXOSCALRESET_TIME[3] origin:064-gtp-channel-conf 01_188 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXOSCALRESET_TIME[4] origin:064-gtp-channel-conf 00_189 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXOSCALRESET_TIMEOUT[0] origin:064-gtp-channel-conf 01_189 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXOSCALRESET_TIMEOUT[1] origin:064-gtp-channel-conf 00_190 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXOSCALRESET_TIMEOUT[2] origin:064-gtp-channel-conf 01_190 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXOSCALRESET_TIMEOUT[3] origin:064-gtp-channel-conf 00_191 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXOSCALRESET_TIMEOUT[4] origin:064-gtp-channel-conf 01_191 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXOUT_DIV[0] origin:064-gtp-channel-conf 02_384 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXOUT_DIV[1] origin:064-gtp-channel-conf 03_384 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXPCSRESET_TIME[0] origin:064-gtp-channel-conf 01_115 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXPCSRESET_TIME[1] origin:064-gtp-channel-conf 00_116 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXPCSRESET_TIME[2] origin:064-gtp-channel-conf 01_116 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXPCSRESET_TIME[3] origin:064-gtp-channel-conf 00_117 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXPCSRESET_TIME[4] origin:064-gtp-channel-conf 01_117 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[0] origin:064-gtp-channel-conf 02_584 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[1] origin:064-gtp-channel-conf 03_584 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[2] origin:064-gtp-channel-conf 02_585 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[3] origin:064-gtp-channel-conf 03_585 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[4] origin:064-gtp-channel-conf 02_586 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[5] origin:064-gtp-channel-conf 03_586 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[6] origin:064-gtp-channel-conf 02_587 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[7] origin:064-gtp-channel-conf 03_587 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[8] origin:064-gtp-channel-conf 02_588 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[9] origin:064-gtp-channel-conf 03_588 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[10] origin:064-gtp-channel-conf 02_589 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[11] origin:064-gtp-channel-conf 03_589 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[12] origin:064-gtp-channel-conf 02_590 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[13] origin:064-gtp-channel-conf 03_590 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[14] origin:064-gtp-channel-conf 02_591 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[15] origin:064-gtp-channel-conf 03_591 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[16] origin:064-gtp-channel-conf 02_592 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[17] origin:064-gtp-channel-conf 03_592 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[18] origin:064-gtp-channel-conf 02_593 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[19] origin:064-gtp-channel-conf 03_593 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[20] origin:064-gtp-channel-conf 02_594 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[21] origin:064-gtp-channel-conf 03_594 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[22] origin:064-gtp-channel-conf 02_595 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXPH_CFG[23] origin:064-gtp-channel-conf 03_595 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXPH_MONITOR_SEL[0] origin:064-gtp-channel-conf 00_700 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXPH_MONITOR_SEL[1] origin:064-gtp-channel-conf 01_700 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXPH_MONITOR_SEL[2] origin:064-gtp-channel-conf 00_701 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXPH_MONITOR_SEL[3] origin:064-gtp-channel-conf 01_701 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXPH_MONITOR_SEL[4] origin:064-gtp-channel-conf 00_702 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[0] origin:064-gtp-channel-conf 02_600 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[1] origin:064-gtp-channel-conf 03_600 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[2] origin:064-gtp-channel-conf 02_601 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[3] origin:064-gtp-channel-conf 03_601 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[4] origin:064-gtp-channel-conf 02_602 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[5] origin:064-gtp-channel-conf 03_602 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[6] origin:064-gtp-channel-conf 02_603 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[7] origin:064-gtp-channel-conf 03_603 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[8] origin:064-gtp-channel-conf 02_604 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[9] origin:064-gtp-channel-conf 03_604 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[10] origin:064-gtp-channel-conf 02_605 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[11] origin:064-gtp-channel-conf 03_605 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[12] origin:064-gtp-channel-conf 02_606 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[13] origin:064-gtp-channel-conf 03_606 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[14] origin:064-gtp-channel-conf 02_607 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[15] origin:064-gtp-channel-conf 03_607 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[16] origin:064-gtp-channel-conf 02_608 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[17] origin:064-gtp-channel-conf 03_608 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[18] origin:064-gtp-channel-conf 02_609 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[19] origin:064-gtp-channel-conf 03_609 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[20] origin:064-gtp-channel-conf 02_610 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[21] origin:064-gtp-channel-conf 03_610 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[22] origin:064-gtp-channel-conf 02_611 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXPHDLY_CFG[23] origin:064-gtp-channel-conf 03_611 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXPI_CFG0[0] origin:064-gtp-channel-conf 03_430 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXPI_CFG0[1] origin:064-gtp-channel-conf 02_431 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXPI_CFG0[2] origin:064-gtp-channel-conf 03_431 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXPI_CFG1[0] origin:064-gtp-channel-conf 02_442 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXPI_CFG2[0] origin:064-gtp-channel-conf 03_441 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXPMARESET_TIME[0] origin:064-gtp-channel-conf 00_104 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXPMARESET_TIME[1] origin:064-gtp-channel-conf 01_104 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXPMARESET_TIME[2] origin:064-gtp-channel-conf 00_105 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXPMARESET_TIME[3] origin:064-gtp-channel-conf 01_105 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXPMARESET_TIME[4] origin:064-gtp-channel-conf 00_106 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXPRBS_ERR_LOOPBACK[0] origin:064-gtp-channel-conf 00_136 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXSLIDE_AUTO_WAIT[0] origin:064-gtp-channel-conf 00_520 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXSLIDE_AUTO_WAIT[1] origin:064-gtp-channel-conf 01_520 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXSLIDE_AUTO_WAIT[2] origin:064-gtp-channel-conf 00_521 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXSLIDE_AUTO_WAIT[3] origin:064-gtp-channel-conf 01_521 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXSLIDE_MODE.AUTO origin:064-gtp-channel-conf !01_519 00_519 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXSLIDE_MODE.PCS origin:064-gtp-channel-conf !00_519 01_519 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXSLIDE_MODE.PMA origin:064-gtp-channel-conf 00_519 01_519 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXSYNC_MULTILANE[0] origin:064-gtp-channel-conf 00_133 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXSYNC_OVRD[0] origin:064-gtp-channel-conf 01_135 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.RXSYNC_SKIP_DA[0] origin:064-gtp-channel-conf 01_134 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.SAS_MAX_COM[0] origin:064-gtp-channel-conf 00_171 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.SAS_MAX_COM[1] origin:064-gtp-channel-conf 01_171 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.SAS_MAX_COM[2] origin:064-gtp-channel-conf 00_172 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.SAS_MAX_COM[3] origin:064-gtp-channel-conf 01_172 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.SAS_MAX_COM[4] origin:064-gtp-channel-conf 00_173 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.SAS_MAX_COM[5] origin:064-gtp-channel-conf 01_173 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.SAS_MAX_COM[6] origin:064-gtp-channel-conf 00_174 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.SAS_MIN_COM[0] origin:064-gtp-channel-conf 01_156 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.SAS_MIN_COM[1] origin:064-gtp-channel-conf 00_157 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.SAS_MIN_COM[2] origin:064-gtp-channel-conf 01_157 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.SAS_MIN_COM[3] origin:064-gtp-channel-conf 00_158 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.SAS_MIN_COM[4] origin:064-gtp-channel-conf 01_158 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.SAS_MIN_COM[5] origin:064-gtp-channel-conf 00_159 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.SATA_BURST_SEQ_LEN[0] origin:064-gtp-channel-conf 00_150 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.SATA_BURST_SEQ_LEN[1] origin:064-gtp-channel-conf 01_150 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.SATA_BURST_SEQ_LEN[2] origin:064-gtp-channel-conf 00_151 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.SATA_BURST_SEQ_LEN[3] origin:064-gtp-channel-conf 01_151 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.SATA_BURST_VAL[0] origin:064-gtp-channel-conf 01_147 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.SATA_BURST_VAL[1] origin:064-gtp-channel-conf 00_148 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.SATA_BURST_VAL[2] origin:064-gtp-channel-conf 01_148 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.SATA_EIDLE_VAL[0] origin:064-gtp-channel-conf 00_152 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.SATA_EIDLE_VAL[1] origin:064-gtp-channel-conf 01_152 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.SATA_EIDLE_VAL[2] origin:064-gtp-channel-conf 00_153 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.SATA_MAX_BURST[0] origin:064-gtp-channel-conf 00_168 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.SATA_MAX_BURST[1] origin:064-gtp-channel-conf 01_168 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.SATA_MAX_BURST[2] origin:064-gtp-channel-conf 00_169 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.SATA_MAX_BURST[3] origin:064-gtp-channel-conf 01_169 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.SATA_MAX_BURST[4] origin:064-gtp-channel-conf 00_170 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.SATA_MAX_BURST[5] origin:064-gtp-channel-conf 01_170 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.SATA_MAX_INIT[0] origin:064-gtp-channel-conf 00_176 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.SATA_MAX_INIT[1] origin:064-gtp-channel-conf 01_176 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.SATA_MAX_INIT[2] origin:064-gtp-channel-conf 00_177 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.SATA_MAX_INIT[3] origin:064-gtp-channel-conf 01_177 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.SATA_MAX_INIT[4] origin:064-gtp-channel-conf 00_178 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.SATA_MAX_INIT[5] origin:064-gtp-channel-conf 01_178 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.SATA_MAX_WAKE[0] origin:064-gtp-channel-conf 00_179 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.SATA_MAX_WAKE[1] origin:064-gtp-channel-conf 01_179 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.SATA_MAX_WAKE[2] origin:064-gtp-channel-conf 00_180 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.SATA_MAX_WAKE[3] origin:064-gtp-channel-conf 01_180 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.SATA_MAX_WAKE[4] origin:064-gtp-channel-conf 00_181 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.SATA_MAX_WAKE[5] origin:064-gtp-channel-conf 01_181 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.SATA_MIN_BURST[0] origin:064-gtp-channel-conf 01_153 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.SATA_MIN_BURST[1] origin:064-gtp-channel-conf 00_154 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.SATA_MIN_BURST[2] origin:064-gtp-channel-conf 01_154 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.SATA_MIN_BURST[3] origin:064-gtp-channel-conf 00_155 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.SATA_MIN_BURST[4] origin:064-gtp-channel-conf 01_155 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.SATA_MIN_BURST[5] origin:064-gtp-channel-conf 00_156 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.SATA_MIN_INIT[0] origin:064-gtp-channel-conf 00_160 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.SATA_MIN_INIT[1] origin:064-gtp-channel-conf 01_160 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.SATA_MIN_INIT[2] origin:064-gtp-channel-conf 00_161 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.SATA_MIN_INIT[3] origin:064-gtp-channel-conf 01_161 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.SATA_MIN_INIT[4] origin:064-gtp-channel-conf 00_162 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.SATA_MIN_INIT[5] origin:064-gtp-channel-conf 01_162 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.SATA_MIN_WAKE[0] origin:064-gtp-channel-conf 00_163 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.SATA_MIN_WAKE[1] origin:064-gtp-channel-conf 01_163 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.SATA_MIN_WAKE[2] origin:064-gtp-channel-conf 00_164 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.SATA_MIN_WAKE[3] origin:064-gtp-channel-conf 01_164 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.SATA_MIN_WAKE[4] origin:064-gtp-channel-conf 00_165 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.SATA_MIN_WAKE[5] origin:064-gtp-channel-conf 01_165 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.SATA_PLL_CFG.VCO_1500MHZ origin:064-gtp-channel-conf 02_55 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.SATA_PLL_CFG.VCO_750MHZ origin:064-gtp-channel-conf 03_55 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.SHOW_REALIGN_COMMA origin:064-gtp-channel-conf 01_522 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TERM_RCAL_CFG[0] origin:064-gtp-channel-conf 02_136 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TERM_RCAL_CFG[1] origin:064-gtp-channel-conf 03_136 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TERM_RCAL_CFG[2] origin:064-gtp-channel-conf 02_137 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TERM_RCAL_CFG[3] origin:064-gtp-channel-conf 03_137 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TERM_RCAL_CFG[4] origin:064-gtp-channel-conf 02_138 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TERM_RCAL_CFG[5] origin:064-gtp-channel-conf 03_138 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TERM_RCAL_CFG[6] origin:064-gtp-channel-conf 02_139 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TERM_RCAL_CFG[7] origin:064-gtp-channel-conf 03_139 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TERM_RCAL_CFG[8] origin:064-gtp-channel-conf 02_140 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TERM_RCAL_CFG[9] origin:064-gtp-channel-conf 03_140 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TERM_RCAL_CFG[10] origin:064-gtp-channel-conf 02_141 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TERM_RCAL_CFG[11] origin:064-gtp-channel-conf 03_141 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TERM_RCAL_CFG[12] origin:064-gtp-channel-conf 02_142 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TERM_RCAL_CFG[13] origin:064-gtp-channel-conf 03_142 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TERM_RCAL_CFG[14] origin:064-gtp-channel-conf 02_143 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TERM_RCAL_OVRD[0] origin:064-gtp-channel-conf 03_150 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TERM_RCAL_OVRD[1] origin:064-gtp-channel-conf 02_151 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TERM_RCAL_OVRD[2] origin:064-gtp-channel-conf 03_151 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TRANS_TIME_RATE[0] origin:064-gtp-channel-conf 00_192 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TRANS_TIME_RATE[1] origin:064-gtp-channel-conf 01_192 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TRANS_TIME_RATE[2] origin:064-gtp-channel-conf 00_193 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TRANS_TIME_RATE[3] origin:064-gtp-channel-conf 01_193 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TRANS_TIME_RATE[4] origin:064-gtp-channel-conf 00_194 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TRANS_TIME_RATE[5] origin:064-gtp-channel-conf 01_194 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TRANS_TIME_RATE[6] origin:064-gtp-channel-conf 00_195 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TRANS_TIME_RATE[7] origin:064-gtp-channel-conf 01_195 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[0] origin:064-gtp-channel-conf 02_504 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[1] origin:064-gtp-channel-conf 03_504 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[2] origin:064-gtp-channel-conf 02_505 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[3] origin:064-gtp-channel-conf 03_505 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[4] origin:064-gtp-channel-conf 02_506 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[5] origin:064-gtp-channel-conf 03_506 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[6] origin:064-gtp-channel-conf 02_507 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[7] origin:064-gtp-channel-conf 03_507 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[8] origin:064-gtp-channel-conf 02_508 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[9] origin:064-gtp-channel-conf 03_508 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[10] origin:064-gtp-channel-conf 02_509 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[11] origin:064-gtp-channel-conf 03_509 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[12] origin:064-gtp-channel-conf 02_510 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[13] origin:064-gtp-channel-conf 03_510 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[14] origin:064-gtp-channel-conf 02_511 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[15] origin:064-gtp-channel-conf 03_511 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[16] origin:064-gtp-channel-conf 02_512 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[17] origin:064-gtp-channel-conf 03_512 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[18] origin:064-gtp-channel-conf 02_513 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[19] origin:064-gtp-channel-conf 03_513 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[20] origin:064-gtp-channel-conf 02_514 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[21] origin:064-gtp-channel-conf 03_514 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[22] origin:064-gtp-channel-conf 02_515 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[23] origin:064-gtp-channel-conf 03_515 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[24] origin:064-gtp-channel-conf 02_516 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[25] origin:064-gtp-channel-conf 03_516 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[26] origin:064-gtp-channel-conf 02_517 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[27] origin:064-gtp-channel-conf 03_517 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[28] origin:064-gtp-channel-conf 02_518 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[29] origin:064-gtp-channel-conf 03_518 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[30] origin:064-gtp-channel-conf 02_519 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TST_RSV[31] origin:064-gtp-channel-conf 03_519 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_CLKMUX_EN[0] origin:064-gtp-channel-conf 03_128 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_DATA_WIDTH[0] origin:064-gtp-channel-conf 02_152 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_DATA_WIDTH[1] origin:064-gtp-channel-conf 03_152 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_DATA_WIDTH[2] origin:064-gtp-channel-conf 02_153 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_DRIVE_MODE.PIPE origin:064-gtp-channel-conf 00_200 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_EIDLE_ASSERT_DELAY[0] origin:064-gtp-channel-conf 00_203 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_EIDLE_ASSERT_DELAY[1] origin:064-gtp-channel-conf 01_203 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_EIDLE_ASSERT_DELAY[2] origin:064-gtp-channel-conf 00_204 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_EIDLE_DEASSERT_DELAY[0] origin:064-gtp-channel-conf 01_204 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_EIDLE_DEASSERT_DELAY[1] origin:064-gtp-channel-conf 00_205 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_EIDLE_DEASSERT_DELAY[2] origin:064-gtp-channel-conf 01_205 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_LOOPBACK_DRIVE_HIZ origin:064-gtp-channel-conf 01_202 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_MAINCURSOR_SEL[0] origin:064-gtp-channel-conf 03_289 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_0[0] origin:064-gtp-channel-conf 02_232 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_0[1] origin:064-gtp-channel-conf 03_232 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_0[2] origin:064-gtp-channel-conf 02_233 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_0[3] origin:064-gtp-channel-conf 03_233 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_0[4] origin:064-gtp-channel-conf 02_234 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_0[5] origin:064-gtp-channel-conf 03_234 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_0[6] origin:064-gtp-channel-conf 02_235 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_1[0] origin:064-gtp-channel-conf 02_236 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_1[1] origin:064-gtp-channel-conf 03_236 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_1[2] origin:064-gtp-channel-conf 02_237 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_1[3] origin:064-gtp-channel-conf 03_237 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_1[4] origin:064-gtp-channel-conf 02_238 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_1[5] origin:064-gtp-channel-conf 03_238 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_1[6] origin:064-gtp-channel-conf 02_239 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_2[0] origin:064-gtp-channel-conf 02_240 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_2[1] origin:064-gtp-channel-conf 03_240 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_2[2] origin:064-gtp-channel-conf 02_241 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_2[3] origin:064-gtp-channel-conf 03_241 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_2[4] origin:064-gtp-channel-conf 02_242 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_2[5] origin:064-gtp-channel-conf 03_242 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_2[6] origin:064-gtp-channel-conf 02_243 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_3[0] origin:064-gtp-channel-conf 02_244 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_3[1] origin:064-gtp-channel-conf 03_244 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_3[2] origin:064-gtp-channel-conf 02_245 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_3[3] origin:064-gtp-channel-conf 03_245 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_3[4] origin:064-gtp-channel-conf 02_246 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_3[5] origin:064-gtp-channel-conf 03_246 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_3[6] origin:064-gtp-channel-conf 02_247 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_4[0] origin:064-gtp-channel-conf 02_248 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_4[1] origin:064-gtp-channel-conf 03_248 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_4[2] origin:064-gtp-channel-conf 02_249 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_4[3] origin:064-gtp-channel-conf 03_249 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_4[4] origin:064-gtp-channel-conf 02_250 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_4[5] origin:064-gtp-channel-conf 03_250 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_FULL_4[6] origin:064-gtp-channel-conf 02_251 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_0[0] origin:064-gtp-channel-conf 02_252 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_0[1] origin:064-gtp-channel-conf 03_252 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_0[2] origin:064-gtp-channel-conf 02_253 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_0[3] origin:064-gtp-channel-conf 03_253 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_0[4] origin:064-gtp-channel-conf 02_254 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_0[5] origin:064-gtp-channel-conf 03_254 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_0[6] origin:064-gtp-channel-conf 02_255 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_1[0] origin:064-gtp-channel-conf 02_256 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_1[1] origin:064-gtp-channel-conf 03_256 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_1[2] origin:064-gtp-channel-conf 02_257 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_1[3] origin:064-gtp-channel-conf 03_257 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_1[4] origin:064-gtp-channel-conf 02_258 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_1[5] origin:064-gtp-channel-conf 03_258 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_1[6] origin:064-gtp-channel-conf 02_259 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_2[0] origin:064-gtp-channel-conf 02_260 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_2[1] origin:064-gtp-channel-conf 03_260 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_2[2] origin:064-gtp-channel-conf 02_261 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_2[3] origin:064-gtp-channel-conf 03_261 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_2[4] origin:064-gtp-channel-conf 02_262 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_2[5] origin:064-gtp-channel-conf 03_262 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_2[6] origin:064-gtp-channel-conf 02_263 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_3[0] origin:064-gtp-channel-conf 02_264 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_3[1] origin:064-gtp-channel-conf 03_264 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_3[2] origin:064-gtp-channel-conf 02_265 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_3[3] origin:064-gtp-channel-conf 03_265 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_3[4] origin:064-gtp-channel-conf 02_266 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_3[5] origin:064-gtp-channel-conf 03_266 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_3[6] origin:064-gtp-channel-conf 02_267 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_4[0] origin:064-gtp-channel-conf 02_268 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_4[1] origin:064-gtp-channel-conf 03_268 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_4[2] origin:064-gtp-channel-conf 02_269 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_4[3] origin:064-gtp-channel-conf 03_269 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_4[4] origin:064-gtp-channel-conf 02_270 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_4[5] origin:064-gtp-channel-conf 03_270 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_MARGIN_LOW_4[6] origin:064-gtp-channel-conf 02_271 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_PREDRIVER_MODE[0] origin:064-gtp-channel-conf 00_206 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_RXDETECT_CFG[0] origin:064-gtp-channel-conf 02_296 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_RXDETECT_CFG[1] origin:064-gtp-channel-conf 03_296 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_RXDETECT_CFG[2] origin:064-gtp-channel-conf 02_297 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_RXDETECT_CFG[3] origin:064-gtp-channel-conf 03_297 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_RXDETECT_CFG[4] origin:064-gtp-channel-conf 02_298 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_RXDETECT_CFG[5] origin:064-gtp-channel-conf 03_298 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_RXDETECT_CFG[6] origin:064-gtp-channel-conf 02_299 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_RXDETECT_CFG[7] origin:064-gtp-channel-conf 03_299 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_RXDETECT_CFG[8] origin:064-gtp-channel-conf 02_300 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_RXDETECT_CFG[9] origin:064-gtp-channel-conf 03_300 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_RXDETECT_CFG[10] origin:064-gtp-channel-conf 02_301 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_RXDETECT_CFG[11] origin:064-gtp-channel-conf 03_301 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_RXDETECT_CFG[12] origin:064-gtp-channel-conf 02_302 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_RXDETECT_CFG[13] origin:064-gtp-channel-conf 03_302 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_RXDETECT_REF[0] origin:064-gtp-channel-conf 02_292 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_RXDETECT_REF[1] origin:064-gtp-channel-conf 03_292 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_RXDETECT_REF[2] origin:064-gtp-channel-conf 02_293 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_XCLK_SEL.TXUSR origin:064-gtp-channel-conf 03_11 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_CLK25_DIV[0] origin:064-gtp-channel-conf 02_144 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_CLK25_DIV[1] origin:064-gtp-channel-conf 03_144 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_CLK25_DIV[2] origin:064-gtp-channel-conf 02_145 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_CLK25_DIV[3] origin:064-gtp-channel-conf 03_145 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_CLK25_DIV[4] origin:064-gtp-channel-conf 02_146 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_DEEMPH0[0] origin:064-gtp-channel-conf 02_272 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_DEEMPH0[1] origin:064-gtp-channel-conf 03_272 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_DEEMPH0[2] origin:064-gtp-channel-conf 02_273 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_DEEMPH0[3] origin:064-gtp-channel-conf 03_273 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_DEEMPH0[4] origin:064-gtp-channel-conf 02_274 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_DEEMPH0[5] origin:064-gtp-channel-conf 03_274 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_DEEMPH1[0] origin:064-gtp-channel-conf 02_276 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_DEEMPH1[1] origin:064-gtp-channel-conf 03_276 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_DEEMPH1[2] origin:064-gtp-channel-conf 02_277 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_DEEMPH1[3] origin:064-gtp-channel-conf 03_277 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_DEEMPH1[4] origin:064-gtp-channel-conf 02_278 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TX_DEEMPH1[5] origin:064-gtp-channel-conf 03_278 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXBUF_EN origin:064-gtp-channel-conf 00_231 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXBUF_RESET_ON_RATE_CHANGE origin:064-gtp-channel-conf 01_231 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXDLY_CFG[0] origin:064-gtp-channel-conf 02_80 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXDLY_CFG[1] origin:064-gtp-channel-conf 03_80 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXDLY_CFG[2] origin:064-gtp-channel-conf 02_81 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXDLY_CFG[3] origin:064-gtp-channel-conf 03_81 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXDLY_CFG[4] origin:064-gtp-channel-conf 02_82 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXDLY_CFG[5] origin:064-gtp-channel-conf 03_82 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXDLY_CFG[6] origin:064-gtp-channel-conf 02_83 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXDLY_CFG[7] origin:064-gtp-channel-conf 03_83 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXDLY_CFG[8] origin:064-gtp-channel-conf 02_84 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXDLY_CFG[9] origin:064-gtp-channel-conf 03_84 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXDLY_CFG[10] origin:064-gtp-channel-conf 02_85 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXDLY_CFG[11] origin:064-gtp-channel-conf 03_85 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXDLY_CFG[12] origin:064-gtp-channel-conf 02_86 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXDLY_CFG[13] origin:064-gtp-channel-conf 03_86 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXDLY_CFG[14] origin:064-gtp-channel-conf 02_87 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXDLY_CFG[15] origin:064-gtp-channel-conf 03_87 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXDLY_LCFG[0] origin:064-gtp-channel-conf 02_568 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXDLY_LCFG[1] origin:064-gtp-channel-conf 03_568 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXDLY_LCFG[2] origin:064-gtp-channel-conf 02_569 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXDLY_LCFG[3] origin:064-gtp-channel-conf 03_569 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXDLY_LCFG[4] origin:064-gtp-channel-conf 02_570 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXDLY_LCFG[5] origin:064-gtp-channel-conf 03_570 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXDLY_LCFG[6] origin:064-gtp-channel-conf 02_571 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXDLY_LCFG[7] origin:064-gtp-channel-conf 03_571 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXDLY_LCFG[8] origin:064-gtp-channel-conf 02_572 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXDLY_TAP_CFG[0] origin:064-gtp-channel-conf 02_88 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXDLY_TAP_CFG[1] origin:064-gtp-channel-conf 03_88 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXDLY_TAP_CFG[2] origin:064-gtp-channel-conf 02_89 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXDLY_TAP_CFG[3] origin:064-gtp-channel-conf 03_89 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXDLY_TAP_CFG[4] origin:064-gtp-channel-conf 02_90 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXDLY_TAP_CFG[5] origin:064-gtp-channel-conf 03_90 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXDLY_TAP_CFG[6] origin:064-gtp-channel-conf 02_91 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXDLY_TAP_CFG[7] origin:064-gtp-channel-conf 03_91 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXDLY_TAP_CFG[8] origin:064-gtp-channel-conf 02_92 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXDLY_TAP_CFG[9] origin:064-gtp-channel-conf 03_92 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXDLY_TAP_CFG[10] origin:064-gtp-channel-conf 02_93 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXDLY_TAP_CFG[11] origin:064-gtp-channel-conf 03_93 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXDLY_TAP_CFG[12] origin:064-gtp-channel-conf 02_94 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXDLY_TAP_CFG[13] origin:064-gtp-channel-conf 03_94 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXDLY_TAP_CFG[14] origin:064-gtp-channel-conf 02_95 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXDLY_TAP_CFG[15] origin:064-gtp-channel-conf 03_95 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXGEARBOX_EN origin:064-gtp-channel-conf 01_226 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXOOB_CFG[0] origin:064-gtp-channel-conf 03_20 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXOUT_DIV[0] origin:064-gtp-channel-conf 02_386 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXOUT_DIV[1] origin:064-gtp-channel-conf 03_386 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPCSRESET_TIME[0] origin:064-gtp-channel-conf 01_130 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPCSRESET_TIME[1] origin:064-gtp-channel-conf 00_131 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPCSRESET_TIME[2] origin:064-gtp-channel-conf 01_131 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPCSRESET_TIME[3] origin:064-gtp-channel-conf 00_132 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPCSRESET_TIME[4] origin:064-gtp-channel-conf 01_132 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPH_CFG[0] origin:064-gtp-channel-conf 02_96 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPH_CFG[1] origin:064-gtp-channel-conf 03_96 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPH_CFG[2] origin:064-gtp-channel-conf 02_97 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPH_CFG[3] origin:064-gtp-channel-conf 03_97 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPH_CFG[4] origin:064-gtp-channel-conf 02_98 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPH_CFG[5] origin:064-gtp-channel-conf 03_98 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPH_CFG[6] origin:064-gtp-channel-conf 02_99 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPH_CFG[7] origin:064-gtp-channel-conf 03_99 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPH_CFG[8] origin:064-gtp-channel-conf 02_100 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPH_CFG[9] origin:064-gtp-channel-conf 03_100 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPH_CFG[10] origin:064-gtp-channel-conf 02_101 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPH_CFG[11] origin:064-gtp-channel-conf 03_101 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPH_CFG[12] origin:064-gtp-channel-conf 02_102 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPH_CFG[13] origin:064-gtp-channel-conf 03_102 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPH_CFG[14] origin:064-gtp-channel-conf 02_103 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPH_CFG[15] origin:064-gtp-channel-conf 03_103 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPH_MONITOR_SEL[0] origin:064-gtp-channel-conf 02_108 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPH_MONITOR_SEL[1] origin:064-gtp-channel-conf 03_108 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPH_MONITOR_SEL[2] origin:064-gtp-channel-conf 02_109 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPH_MONITOR_SEL[3] origin:064-gtp-channel-conf 03_109 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPH_MONITOR_SEL[4] origin:064-gtp-channel-conf 02_110 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[0] origin:064-gtp-channel-conf 02_64 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[1] origin:064-gtp-channel-conf 03_64 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[2] origin:064-gtp-channel-conf 02_65 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[3] origin:064-gtp-channel-conf 03_65 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[4] origin:064-gtp-channel-conf 02_66 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[5] origin:064-gtp-channel-conf 03_66 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[6] origin:064-gtp-channel-conf 02_67 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[7] origin:064-gtp-channel-conf 03_67 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[8] origin:064-gtp-channel-conf 02_68 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[9] origin:064-gtp-channel-conf 03_68 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[10] origin:064-gtp-channel-conf 02_69 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[11] origin:064-gtp-channel-conf 03_69 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[12] origin:064-gtp-channel-conf 02_70 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[13] origin:064-gtp-channel-conf 03_70 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[14] origin:064-gtp-channel-conf 02_71 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[15] origin:064-gtp-channel-conf 03_71 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[16] origin:064-gtp-channel-conf 02_72 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[17] origin:064-gtp-channel-conf 03_72 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[18] origin:064-gtp-channel-conf 02_73 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[19] origin:064-gtp-channel-conf 03_73 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[20] origin:064-gtp-channel-conf 02_74 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[21] origin:064-gtp-channel-conf 03_74 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[22] origin:064-gtp-channel-conf 02_75 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPHDLY_CFG[23] origin:064-gtp-channel-conf 03_75 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPI_GREY_SEL[0] origin:064-gtp-channel-conf 03_498 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPI_INVSTROBE_SEL[0] origin:064-gtp-channel-conf 02_498 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPI_PPM_CFG[0] origin:064-gtp-channel-conf 02_488 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPI_PPM_CFG[1] origin:064-gtp-channel-conf 03_488 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPI_PPM_CFG[2] origin:064-gtp-channel-conf 02_489 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPI_PPM_CFG[3] origin:064-gtp-channel-conf 03_489 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPI_PPM_CFG[4] origin:064-gtp-channel-conf 02_490 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPI_PPM_CFG[5] origin:064-gtp-channel-conf 03_490 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPI_PPM_CFG[6] origin:064-gtp-channel-conf 02_491 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPI_PPM_CFG[7] origin:064-gtp-channel-conf 03_491 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPI_PPMCLK_SEL.TXUSRCLK2 origin:064-gtp-channel-conf 03_497 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPI_SYNFREQ_PPM[0] origin:064-gtp-channel-conf 02_496 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPI_SYNFREQ_PPM[1] origin:064-gtp-channel-conf 03_496 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPI_SYNFREQ_PPM[2] origin:064-gtp-channel-conf 02_497 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPI_CFG0[0] origin:064-gtp-channel-conf 02_40 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPI_CFG0[1] origin:064-gtp-channel-conf 03_40 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPI_CFG1[0] origin:064-gtp-channel-conf 02_41 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPI_CFG1[1] origin:064-gtp-channel-conf 03_41 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPI_CFG2[0] origin:064-gtp-channel-conf 02_42 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPI_CFG2[1] origin:064-gtp-channel-conf 03_42 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPI_CFG3[0] origin:064-gtp-channel-conf 02_43 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPI_CFG4[0] origin:064-gtp-channel-conf 03_43 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPI_CFG5[0] origin:064-gtp-channel-conf 02_44 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPI_CFG5[1] origin:064-gtp-channel-conf 03_44 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPI_CFG5[2] origin:064-gtp-channel-conf 02_45 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPMARESET_TIME[0] origin:064-gtp-channel-conf 00_128 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPMARESET_TIME[1] origin:064-gtp-channel-conf 01_128 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPMARESET_TIME[2] origin:064-gtp-channel-conf 00_129 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPMARESET_TIME[3] origin:064-gtp-channel-conf 01_129 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXPMARESET_TIME[4] origin:064-gtp-channel-conf 00_130 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXSYNC_MULTILANE[0] origin:064-gtp-channel-conf 01_133 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXSYNC_OVRD[0] origin:064-gtp-channel-conf 00_135 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.TXSYNC_SKIP_DA[0] origin:064-gtp-channel-conf 00_134 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.UCODEER_CLR[0] origin:064-gtp-channel-conf 01_00 +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL.USE_PCS_CLK_PHASE_SEL[0] origin:064-gtp-channel-conf 02_463 diff --git a/artix7/segbits_gtp_common.db b/artix7/segbits_gtp_common.db index a872d54..0b9dbb1 100644 --- a/artix7/segbits_gtp_common.db +++ b/artix7/segbits_gtp_common.db @@ -1,284 +1,284 @@ -GTP_COMMON.ENABLE_DRP 24_1613 25_1613 -GTP_COMMON.IBUFDS_GTE2.CLKCM_CFG[0] 29_1581 -GTP_COMMON.IBUFDS_GTE2.CLKCM_CFG[1] 28_1582 GTP_COMMON.IBUFDS_GTE2_Y0.CLKCM_CFG 28_1580 GTP_COMMON.IBUFDS_GTE2_Y0.CLKRCV_TRST 28_1576 GTP_COMMON.IBUFDS_GTE2_Y0.IN_USE 28_1578 GTP_COMMON.IBUFDS_GTE2_Y1.CLKCM_CFG 29_1580 GTP_COMMON.IBUFDS_GTE2_Y1.CLKRCV_TRST 29_1576 GTP_COMMON.IBUFDS_GTE2_Y1.IN_USE 28_1579 -GTP_COMMON.GTPE2.BIAS_CFG[0] 28_1640 -GTP_COMMON.GTPE2.BIAS_CFG[1] 29_1640 -GTP_COMMON.GTPE2.BIAS_CFG[2] 28_1641 -GTP_COMMON.GTPE2.BIAS_CFG[3] 29_1641 -GTP_COMMON.GTPE2.BIAS_CFG[4] 28_1642 -GTP_COMMON.GTPE2.BIAS_CFG[5] 29_1642 -GTP_COMMON.GTPE2.BIAS_CFG[6] 28_1643 -GTP_COMMON.GTPE2.BIAS_CFG[7] 29_1643 -GTP_COMMON.GTPE2.BIAS_CFG[8] 28_1644 -GTP_COMMON.GTPE2.BIAS_CFG[9] 29_1644 -GTP_COMMON.GTPE2.BIAS_CFG[10] 28_1645 -GTP_COMMON.GTPE2.BIAS_CFG[11] 29_1645 -GTP_COMMON.GTPE2.BIAS_CFG[12] 28_1646 -GTP_COMMON.GTPE2.BIAS_CFG[13] 29_1646 -GTP_COMMON.GTPE2.BIAS_CFG[14] 28_1647 -GTP_COMMON.GTPE2.BIAS_CFG[15] 29_1647 -GTP_COMMON.GTPE2.BIAS_CFG[16] 28_1648 -GTP_COMMON.GTPE2.BIAS_CFG[17] 29_1648 -GTP_COMMON.GTPE2.BIAS_CFG[18] 28_1649 -GTP_COMMON.GTPE2.BIAS_CFG[19] 29_1649 -GTP_COMMON.GTPE2.BIAS_CFG[20] 28_1650 -GTP_COMMON.GTPE2.BIAS_CFG[21] 29_1650 -GTP_COMMON.GTPE2.BIAS_CFG[22] 28_1651 -GTP_COMMON.GTPE2.BIAS_CFG[23] 29_1651 -GTP_COMMON.GTPE2.BIAS_CFG[24] 28_1652 -GTP_COMMON.GTPE2.BIAS_CFG[25] 29_1652 -GTP_COMMON.GTPE2.BIAS_CFG[26] 28_1653 -GTP_COMMON.GTPE2.BIAS_CFG[27] 29_1653 -GTP_COMMON.GTPE2.BIAS_CFG[28] 28_1654 -GTP_COMMON.GTPE2.BIAS_CFG[29] 29_1654 -GTP_COMMON.GTPE2.BIAS_CFG[30] 28_1655 -GTP_COMMON.GTPE2.BIAS_CFG[31] 29_1655 -GTP_COMMON.GTPE2.BIAS_CFG[32] 28_1656 -GTP_COMMON.GTPE2.BIAS_CFG[33] 29_1656 -GTP_COMMON.GTPE2.BIAS_CFG[34] 28_1657 -GTP_COMMON.GTPE2.BIAS_CFG[35] 29_1657 -GTP_COMMON.GTPE2.BIAS_CFG[36] 28_1658 -GTP_COMMON.GTPE2.BIAS_CFG[37] 29_1658 -GTP_COMMON.GTPE2.BIAS_CFG[38] 28_1659 -GTP_COMMON.GTPE2.BIAS_CFG[39] 29_1659 -GTP_COMMON.GTPE2.BIAS_CFG[40] 28_1660 -GTP_COMMON.GTPE2.BIAS_CFG[41] 29_1660 -GTP_COMMON.GTPE2.BIAS_CFG[42] 28_1661 -GTP_COMMON.GTPE2.BIAS_CFG[43] 29_1661 -GTP_COMMON.GTPE2.BIAS_CFG[44] 28_1662 -GTP_COMMON.GTPE2.BIAS_CFG[45] 29_1662 -GTP_COMMON.GTPE2.BIAS_CFG[46] 28_1663 -GTP_COMMON.GTPE2.BIAS_CFG[47] 29_1663 -GTP_COMMON.GTPE2.BIAS_CFG[48] 28_1664 -GTP_COMMON.GTPE2.BIAS_CFG[49] 29_1664 -GTP_COMMON.GTPE2.BIAS_CFG[50] 28_1665 -GTP_COMMON.GTPE2.BIAS_CFG[51] 29_1665 -GTP_COMMON.GTPE2.BIAS_CFG[52] 28_1666 -GTP_COMMON.GTPE2.BIAS_CFG[53] 29_1666 -GTP_COMMON.GTPE2.BIAS_CFG[54] 28_1667 -GTP_COMMON.GTPE2.BIAS_CFG[55] 29_1667 -GTP_COMMON.GTPE2.BIAS_CFG[56] 28_1668 -GTP_COMMON.GTPE2.BIAS_CFG[57] 29_1668 -GTP_COMMON.GTPE2.BIAS_CFG[58] 28_1669 -GTP_COMMON.GTPE2.BIAS_CFG[59] 29_1669 -GTP_COMMON.GTPE2.BIAS_CFG[60] 28_1670 -GTP_COMMON.GTPE2.BIAS_CFG[61] 29_1670 -GTP_COMMON.GTPE2.BIAS_CFG[62] 28_1671 -GTP_COMMON.GTPE2.BIAS_CFG[63] 29_1671 -GTP_COMMON.GTPE2.BOTH_GTREFCLK_USED 29_1439 29_1807 -GTP_COMMON.GTPE2.COMMON_CFG[0] 28_1544 -GTP_COMMON.GTPE2.COMMON_CFG[1] 29_1544 -GTP_COMMON.GTPE2.COMMON_CFG[2] 28_1545 -GTP_COMMON.GTPE2.COMMON_CFG[3] 29_1545 -GTP_COMMON.GTPE2.COMMON_CFG[4] 28_1546 -GTP_COMMON.GTPE2.COMMON_CFG[5] 29_1546 -GTP_COMMON.GTPE2.COMMON_CFG[6] 28_1547 -GTP_COMMON.GTPE2.COMMON_CFG[7] 29_1547 -GTP_COMMON.GTPE2.COMMON_CFG[8] 28_1548 -GTP_COMMON.GTPE2.COMMON_CFG[9] 29_1548 -GTP_COMMON.GTPE2.COMMON_CFG[10] 28_1549 -GTP_COMMON.GTPE2.COMMON_CFG[11] 29_1549 -GTP_COMMON.GTPE2.COMMON_CFG[12] 28_1550 -GTP_COMMON.GTPE2.COMMON_CFG[13] 29_1550 -GTP_COMMON.GTPE2.COMMON_CFG[14] 28_1551 -GTP_COMMON.GTPE2.COMMON_CFG[15] 29_1551 -GTP_COMMON.GTPE2.COMMON_CFG[16] 28_1552 -GTP_COMMON.GTPE2.COMMON_CFG[17] 29_1552 -GTP_COMMON.GTPE2.COMMON_CFG[18] 28_1553 -GTP_COMMON.GTPE2.COMMON_CFG[19] 29_1553 -GTP_COMMON.GTPE2.COMMON_CFG[20] 28_1554 -GTP_COMMON.GTPE2.COMMON_CFG[21] 29_1554 -GTP_COMMON.GTPE2.COMMON_CFG[22] 28_1555 -GTP_COMMON.GTPE2.COMMON_CFG[23] 29_1555 -GTP_COMMON.GTPE2.COMMON_CFG[24] 28_1556 -GTP_COMMON.GTPE2.COMMON_CFG[25] 29_1556 -GTP_COMMON.GTPE2.COMMON_CFG[26] 28_1557 -GTP_COMMON.GTPE2.COMMON_CFG[27] 29_1557 -GTP_COMMON.GTPE2.COMMON_CFG[28] 28_1558 -GTP_COMMON.GTPE2.COMMON_CFG[29] 29_1558 -GTP_COMMON.GTPE2.COMMON_CFG[30] 28_1559 -GTP_COMMON.GTPE2.COMMON_CFG[31] 29_1559 -GTP_COMMON.GTPE2.IN_USE 28_1584 -GTP_COMMON.GTPE2.PLL_CLKOUT_CFG[0] 28_1560 -GTP_COMMON.GTPE2.PLL_CLKOUT_CFG[1] 29_1560 -GTP_COMMON.GTPE2.PLL_CLKOUT_CFG[2] 28_1561 -GTP_COMMON.GTPE2.PLL_CLKOUT_CFG[3] 29_1561 -GTP_COMMON.GTPE2.PLL_CLKOUT_CFG[4] 28_1562 -GTP_COMMON.GTPE2.PLL_CLKOUT_CFG[5] 29_1562 -GTP_COMMON.GTPE2.PLL_CLKOUT_CFG[6] 28_1563 -GTP_COMMON.GTPE2.PLL_CLKOUT_CFG[7] 29_1563 -GTP_COMMON.GTPE2.RSVD_ATTR0[0] 28_1488 -GTP_COMMON.GTPE2.RSVD_ATTR0[1] 29_1488 -GTP_COMMON.GTPE2.RSVD_ATTR0[2] 28_1489 -GTP_COMMON.GTPE2.RSVD_ATTR0[3] 29_1489 -GTP_COMMON.GTPE2.RSVD_ATTR0[4] 28_1490 -GTP_COMMON.GTPE2.RSVD_ATTR0[5] 29_1490 -GTP_COMMON.GTPE2.RSVD_ATTR0[6] 28_1491 -GTP_COMMON.GTPE2.RSVD_ATTR0[7] 29_1491 -GTP_COMMON.GTPE2.RSVD_ATTR0[8] 28_1492 -GTP_COMMON.GTPE2.RSVD_ATTR0[9] 29_1492 -GTP_COMMON.GTPE2.RSVD_ATTR0[10] 28_1493 -GTP_COMMON.GTPE2.RSVD_ATTR0[11] 29_1493 -GTP_COMMON.GTPE2.RSVD_ATTR0[12] 28_1494 -GTP_COMMON.GTPE2.RSVD_ATTR0[13] 29_1494 -GTP_COMMON.GTPE2.RSVD_ATTR0[14] 28_1495 -GTP_COMMON.GTPE2.RSVD_ATTR0[15] 29_1495 -GTP_COMMON.GTPE2.RSVD_ATTR1[0] 28_1728 -GTP_COMMON.GTPE2.RSVD_ATTR1[1] 29_1728 -GTP_COMMON.GTPE2.RSVD_ATTR1[2] 28_1729 -GTP_COMMON.GTPE2.RSVD_ATTR1[3] 29_1729 -GTP_COMMON.GTPE2.RSVD_ATTR1[4] 28_1730 -GTP_COMMON.GTPE2.RSVD_ATTR1[5] 29_1730 -GTP_COMMON.GTPE2.RSVD_ATTR1[6] 28_1731 -GTP_COMMON.GTPE2.RSVD_ATTR1[7] 29_1731 -GTP_COMMON.GTPE2.RSVD_ATTR1[8] 28_1732 -GTP_COMMON.GTPE2.RSVD_ATTR1[9] 29_1732 -GTP_COMMON.GTPE2.RSVD_ATTR1[10] 28_1733 -GTP_COMMON.GTPE2.RSVD_ATTR1[11] 29_1733 -GTP_COMMON.GTPE2.RSVD_ATTR1[12] 28_1734 -GTP_COMMON.GTPE2.RSVD_ATTR1[13] 29_1734 -GTP_COMMON.GTPE2.RSVD_ATTR1[14] 28_1735 -GTP_COMMON.GTPE2.RSVD_ATTR1[15] 29_1735 -GTP_COMMON.GTPE2.ZINV_DRPCLK 28_1516 -GTP_COMMON.GTPE2.ZINV_PLL0LOCKDETCLK 29_1512 -GTP_COMMON.GTPE2.ZINV_PLL1LOCKDETCLK 28_1512 -GTP_COMMON.GTPE2.GTREFCLK0_USED 28_1438 28_1806 -GTP_COMMON.GTPE2.GTREFCLK1_USED 29_1438 29_1806 -GTP_COMMON.GTPE2.PLL0_CFG[0] 28_1424 -GTP_COMMON.GTPE2.PLL0_CFG[1] 29_1424 -GTP_COMMON.GTPE2.PLL0_CFG[2] 28_1425 -GTP_COMMON.GTPE2.PLL0_CFG[3] 29_1425 -GTP_COMMON.GTPE2.PLL0_CFG[4] 28_1426 -GTP_COMMON.GTPE2.PLL0_CFG[5] 29_1426 -GTP_COMMON.GTPE2.PLL0_CFG[6] 28_1427 -GTP_COMMON.GTPE2.PLL0_CFG[7] 29_1427 -GTP_COMMON.GTPE2.PLL0_CFG[8] 28_1428 -GTP_COMMON.GTPE2.PLL0_CFG[9] 29_1428 -GTP_COMMON.GTPE2.PLL0_CFG[10] 28_1429 -GTP_COMMON.GTPE2.PLL0_CFG[11] 29_1429 -GTP_COMMON.GTPE2.PLL0_CFG[12] 28_1430 -GTP_COMMON.GTPE2.PLL0_CFG[13] 29_1430 -GTP_COMMON.GTPE2.PLL0_CFG[14] 28_1431 -GTP_COMMON.GTPE2.PLL0_CFG[15] 29_1431 -GTP_COMMON.GTPE2.PLL0_CFG[16] 28_1432 -GTP_COMMON.GTPE2.PLL0_CFG[17] 29_1432 -GTP_COMMON.GTPE2.PLL0_CFG[18] 28_1433 -GTP_COMMON.GTPE2.PLL0_CFG[19] 29_1433 -GTP_COMMON.GTPE2.PLL0_CFG[20] 28_1434 -GTP_COMMON.GTPE2.PLL0_CFG[21] 29_1434 -GTP_COMMON.GTPE2.PLL0_CFG[22] 28_1435 -GTP_COMMON.GTPE2.PLL0_CFG[23] 29_1435 -GTP_COMMON.GTPE2.PLL0_CFG[24] 28_1436 -GTP_COMMON.GTPE2.PLL0_CFG[25] 29_1436 -GTP_COMMON.GTPE2.PLL0_CFG[26] 28_1437 -GTP_COMMON.GTPE2.PLL0_DMON_CFG[0] 28_1528 -GTP_COMMON.GTPE2.PLL0_FBDIV[0] 28_1440 -GTP_COMMON.GTPE2.PLL0_FBDIV[1] 29_1440 -GTP_COMMON.GTPE2.PLL0_FBDIV[4] 28_1442 -GTP_COMMON.GTPE2.PLL0_FBDIV_45[0] 29_1443 -GTP_COMMON.GTPE2.PLL0_INIT_CFG[0] 28_1456 -GTP_COMMON.GTPE2.PLL0_INIT_CFG[1] 29_1456 -GTP_COMMON.GTPE2.PLL0_INIT_CFG[2] 28_1457 -GTP_COMMON.GTPE2.PLL0_INIT_CFG[3] 29_1457 -GTP_COMMON.GTPE2.PLL0_INIT_CFG[4] 28_1458 -GTP_COMMON.GTPE2.PLL0_INIT_CFG[5] 29_1458 -GTP_COMMON.GTPE2.PLL0_INIT_CFG[6] 28_1459 -GTP_COMMON.GTPE2.PLL0_INIT_CFG[7] 29_1459 -GTP_COMMON.GTPE2.PLL0_INIT_CFG[8] 28_1460 -GTP_COMMON.GTPE2.PLL0_INIT_CFG[9] 29_1460 -GTP_COMMON.GTPE2.PLL0_INIT_CFG[10] 28_1461 -GTP_COMMON.GTPE2.PLL0_INIT_CFG[11] 29_1461 -GTP_COMMON.GTPE2.PLL0_INIT_CFG[12] 28_1462 -GTP_COMMON.GTPE2.PLL0_INIT_CFG[13] 29_1462 -GTP_COMMON.GTPE2.PLL0_INIT_CFG[14] 28_1463 -GTP_COMMON.GTPE2.PLL0_INIT_CFG[15] 29_1463 -GTP_COMMON.GTPE2.PLL0_INIT_CFG[16] 28_1464 -GTP_COMMON.GTPE2.PLL0_INIT_CFG[17] 29_1464 -GTP_COMMON.GTPE2.PLL0_INIT_CFG[18] 28_1465 -GTP_COMMON.GTPE2.PLL0_INIT_CFG[19] 29_1465 -GTP_COMMON.GTPE2.PLL0_INIT_CFG[20] 28_1466 -GTP_COMMON.GTPE2.PLL0_INIT_CFG[21] 29_1466 -GTP_COMMON.GTPE2.PLL0_INIT_CFG[22] 28_1467 -GTP_COMMON.GTPE2.PLL0_INIT_CFG[23] 29_1467 -GTP_COMMON.GTPE2.PLL0_LOCK_CFG[0] 28_1448 -GTP_COMMON.GTPE2.PLL0_LOCK_CFG[1] 29_1448 -GTP_COMMON.GTPE2.PLL0_LOCK_CFG[2] 28_1449 -GTP_COMMON.GTPE2.PLL0_LOCK_CFG[3] 29_1449 -GTP_COMMON.GTPE2.PLL0_LOCK_CFG[4] 28_1450 -GTP_COMMON.GTPE2.PLL0_LOCK_CFG[5] 29_1450 -GTP_COMMON.GTPE2.PLL0_LOCK_CFG[6] 28_1451 -GTP_COMMON.GTPE2.PLL0_LOCK_CFG[7] 29_1451 -GTP_COMMON.GTPE2.PLL0_LOCK_CFG[8] 28_1452 -GTP_COMMON.GTPE2.PLL0_REFCLK_DIV[4] 29_1446 -GTP_COMMON.GTPE2.PLL1_CFG[0] 28_1792 -GTP_COMMON.GTPE2.PLL1_CFG[1] 29_1792 -GTP_COMMON.GTPE2.PLL1_CFG[2] 28_1793 -GTP_COMMON.GTPE2.PLL1_CFG[3] 29_1793 -GTP_COMMON.GTPE2.PLL1_CFG[4] 28_1794 -GTP_COMMON.GTPE2.PLL1_CFG[5] 29_1794 -GTP_COMMON.GTPE2.PLL1_CFG[6] 28_1795 -GTP_COMMON.GTPE2.PLL1_CFG[7] 29_1795 -GTP_COMMON.GTPE2.PLL1_CFG[8] 28_1796 -GTP_COMMON.GTPE2.PLL1_CFG[9] 29_1796 -GTP_COMMON.GTPE2.PLL1_CFG[10] 28_1797 -GTP_COMMON.GTPE2.PLL1_CFG[11] 29_1797 -GTP_COMMON.GTPE2.PLL1_CFG[12] 28_1798 -GTP_COMMON.GTPE2.PLL1_CFG[13] 29_1798 -GTP_COMMON.GTPE2.PLL1_CFG[14] 28_1799 -GTP_COMMON.GTPE2.PLL1_CFG[15] 29_1799 -GTP_COMMON.GTPE2.PLL1_CFG[16] 28_1800 -GTP_COMMON.GTPE2.PLL1_CFG[17] 29_1800 -GTP_COMMON.GTPE2.PLL1_CFG[18] 28_1801 -GTP_COMMON.GTPE2.PLL1_CFG[19] 29_1801 -GTP_COMMON.GTPE2.PLL1_CFG[20] 28_1802 -GTP_COMMON.GTPE2.PLL1_CFG[21] 29_1802 -GTP_COMMON.GTPE2.PLL1_CFG[22] 28_1803 -GTP_COMMON.GTPE2.PLL1_CFG[23] 29_1803 -GTP_COMMON.GTPE2.PLL1_CFG[24] 28_1804 -GTP_COMMON.GTPE2.PLL1_CFG[25] 29_1804 -GTP_COMMON.GTPE2.PLL1_CFG[26] 28_1805 -GTP_COMMON.GTPE2.PLL1_DMON_CFG[0] 29_1528 -GTP_COMMON.GTPE2.PLL1_FBDIV[0] 28_1784 -GTP_COMMON.GTPE2.PLL1_FBDIV[1] 29_1784 -GTP_COMMON.GTPE2.PLL1_FBDIV[4] 28_1786 -GTP_COMMON.GTPE2.PLL1_FBDIV_45[0] 29_1787 -GTP_COMMON.GTPE2.PLL1_INIT_CFG[0] 28_1760 -GTP_COMMON.GTPE2.PLL1_INIT_CFG[1] 29_1760 -GTP_COMMON.GTPE2.PLL1_INIT_CFG[2] 28_1761 -GTP_COMMON.GTPE2.PLL1_INIT_CFG[3] 29_1761 -GTP_COMMON.GTPE2.PLL1_INIT_CFG[4] 28_1762 -GTP_COMMON.GTPE2.PLL1_INIT_CFG[5] 29_1762 -GTP_COMMON.GTPE2.PLL1_INIT_CFG[6] 28_1763 -GTP_COMMON.GTPE2.PLL1_INIT_CFG[7] 29_1763 -GTP_COMMON.GTPE2.PLL1_INIT_CFG[8] 28_1764 -GTP_COMMON.GTPE2.PLL1_INIT_CFG[9] 29_1764 -GTP_COMMON.GTPE2.PLL1_INIT_CFG[10] 28_1765 -GTP_COMMON.GTPE2.PLL1_INIT_CFG[11] 29_1765 -GTP_COMMON.GTPE2.PLL1_INIT_CFG[12] 28_1766 -GTP_COMMON.GTPE2.PLL1_INIT_CFG[13] 29_1766 -GTP_COMMON.GTPE2.PLL1_INIT_CFG[14] 28_1767 -GTP_COMMON.GTPE2.PLL1_INIT_CFG[15] 29_1767 -GTP_COMMON.GTPE2.PLL1_INIT_CFG[16] 28_1768 -GTP_COMMON.GTPE2.PLL1_INIT_CFG[17] 29_1768 -GTP_COMMON.GTPE2.PLL1_INIT_CFG[18] 28_1769 -GTP_COMMON.GTPE2.PLL1_INIT_CFG[19] 29_1769 -GTP_COMMON.GTPE2.PLL1_INIT_CFG[20] 28_1770 -GTP_COMMON.GTPE2.PLL1_INIT_CFG[21] 29_1770 -GTP_COMMON.GTPE2.PLL1_INIT_CFG[22] 28_1771 -GTP_COMMON.GTPE2.PLL1_INIT_CFG[23] 29_1771 -GTP_COMMON.GTPE2.PLL1_LOCK_CFG[0] 28_1776 -GTP_COMMON.GTPE2.PLL1_LOCK_CFG[1] 29_1776 -GTP_COMMON.GTPE2.PLL1_LOCK_CFG[2] 28_1777 -GTP_COMMON.GTPE2.PLL1_LOCK_CFG[3] 29_1777 -GTP_COMMON.GTPE2.PLL1_LOCK_CFG[4] 28_1778 -GTP_COMMON.GTPE2.PLL1_LOCK_CFG[5] 29_1778 -GTP_COMMON.GTPE2.PLL1_LOCK_CFG[6] 28_1779 -GTP_COMMON.GTPE2.PLL1_LOCK_CFG[7] 29_1779 -GTP_COMMON.GTPE2.PLL1_LOCK_CFG[8] 28_1780 -GTP_COMMON.GTPE2.PLL1_REFCLK_DIV[4] 29_1790 +GTP_COMMON.GTPE2_COMMON.BIAS_CFG[0] 28_1640 +GTP_COMMON.GTPE2_COMMON.BIAS_CFG[1] 29_1640 +GTP_COMMON.GTPE2_COMMON.BIAS_CFG[2] 28_1641 +GTP_COMMON.GTPE2_COMMON.BIAS_CFG[3] 29_1641 +GTP_COMMON.GTPE2_COMMON.BIAS_CFG[4] 28_1642 +GTP_COMMON.GTPE2_COMMON.BIAS_CFG[5] 29_1642 +GTP_COMMON.GTPE2_COMMON.BIAS_CFG[6] 28_1643 +GTP_COMMON.GTPE2_COMMON.BIAS_CFG[7] 29_1643 +GTP_COMMON.GTPE2_COMMON.BIAS_CFG[8] 28_1644 +GTP_COMMON.GTPE2_COMMON.BIAS_CFG[9] 29_1644 +GTP_COMMON.GTPE2_COMMON.BIAS_CFG[10] 28_1645 +GTP_COMMON.GTPE2_COMMON.BIAS_CFG[11] 29_1645 +GTP_COMMON.GTPE2_COMMON.BIAS_CFG[12] 28_1646 +GTP_COMMON.GTPE2_COMMON.BIAS_CFG[13] 29_1646 +GTP_COMMON.GTPE2_COMMON.BIAS_CFG[14] 28_1647 +GTP_COMMON.GTPE2_COMMON.BIAS_CFG[15] 29_1647 +GTP_COMMON.GTPE2_COMMON.BIAS_CFG[16] 28_1648 +GTP_COMMON.GTPE2_COMMON.BIAS_CFG[17] 29_1648 +GTP_COMMON.GTPE2_COMMON.BIAS_CFG[18] 28_1649 +GTP_COMMON.GTPE2_COMMON.BIAS_CFG[19] 29_1649 +GTP_COMMON.GTPE2_COMMON.BIAS_CFG[20] 28_1650 +GTP_COMMON.GTPE2_COMMON.BIAS_CFG[21] 29_1650 +GTP_COMMON.GTPE2_COMMON.BIAS_CFG[22] 28_1651 +GTP_COMMON.GTPE2_COMMON.BIAS_CFG[23] 29_1651 +GTP_COMMON.GTPE2_COMMON.BIAS_CFG[24] 28_1652 +GTP_COMMON.GTPE2_COMMON.BIAS_CFG[25] 29_1652 +GTP_COMMON.GTPE2_COMMON.BIAS_CFG[26] 28_1653 +GTP_COMMON.GTPE2_COMMON.BIAS_CFG[27] 29_1653 +GTP_COMMON.GTPE2_COMMON.BIAS_CFG[28] 28_1654 +GTP_COMMON.GTPE2_COMMON.BIAS_CFG[29] 29_1654 +GTP_COMMON.GTPE2_COMMON.BIAS_CFG[30] 28_1655 +GTP_COMMON.GTPE2_COMMON.BIAS_CFG[31] 29_1655 +GTP_COMMON.GTPE2_COMMON.BIAS_CFG[32] 28_1656 +GTP_COMMON.GTPE2_COMMON.BIAS_CFG[33] 29_1656 +GTP_COMMON.GTPE2_COMMON.BIAS_CFG[34] 28_1657 +GTP_COMMON.GTPE2_COMMON.BIAS_CFG[35] 29_1657 +GTP_COMMON.GTPE2_COMMON.BIAS_CFG[36] 28_1658 +GTP_COMMON.GTPE2_COMMON.BIAS_CFG[37] 29_1658 +GTP_COMMON.GTPE2_COMMON.BIAS_CFG[38] 28_1659 +GTP_COMMON.GTPE2_COMMON.BIAS_CFG[39] 29_1659 +GTP_COMMON.GTPE2_COMMON.BIAS_CFG[40] 28_1660 +GTP_COMMON.GTPE2_COMMON.BIAS_CFG[41] 29_1660 +GTP_COMMON.GTPE2_COMMON.BIAS_CFG[42] 28_1661 +GTP_COMMON.GTPE2_COMMON.BIAS_CFG[43] 29_1661 +GTP_COMMON.GTPE2_COMMON.BIAS_CFG[44] 28_1662 +GTP_COMMON.GTPE2_COMMON.BIAS_CFG[45] 29_1662 +GTP_COMMON.GTPE2_COMMON.BIAS_CFG[46] 28_1663 +GTP_COMMON.GTPE2_COMMON.BIAS_CFG[47] 29_1663 +GTP_COMMON.GTPE2_COMMON.BIAS_CFG[48] 28_1664 +GTP_COMMON.GTPE2_COMMON.BIAS_CFG[49] 29_1664 +GTP_COMMON.GTPE2_COMMON.BIAS_CFG[50] 28_1665 +GTP_COMMON.GTPE2_COMMON.BIAS_CFG[51] 29_1665 +GTP_COMMON.GTPE2_COMMON.BIAS_CFG[52] 28_1666 +GTP_COMMON.GTPE2_COMMON.BIAS_CFG[53] 29_1666 +GTP_COMMON.GTPE2_COMMON.BIAS_CFG[54] 28_1667 +GTP_COMMON.GTPE2_COMMON.BIAS_CFG[55] 29_1667 +GTP_COMMON.GTPE2_COMMON.BIAS_CFG[56] 28_1668 +GTP_COMMON.GTPE2_COMMON.BIAS_CFG[57] 29_1668 +GTP_COMMON.GTPE2_COMMON.BIAS_CFG[58] 28_1669 +GTP_COMMON.GTPE2_COMMON.BIAS_CFG[59] 29_1669 +GTP_COMMON.GTPE2_COMMON.BIAS_CFG[60] 28_1670 +GTP_COMMON.GTPE2_COMMON.BIAS_CFG[61] 29_1670 +GTP_COMMON.GTPE2_COMMON.BIAS_CFG[62] 28_1671 +GTP_COMMON.GTPE2_COMMON.BIAS_CFG[63] 29_1671 +GTP_COMMON.GTPE2_COMMON.BOTH_GTREFCLK_USED 29_1439 29_1807 +GTP_COMMON.GTPE2_COMMON.COMMON_CFG[0] 28_1544 +GTP_COMMON.GTPE2_COMMON.COMMON_CFG[1] 29_1544 +GTP_COMMON.GTPE2_COMMON.COMMON_CFG[2] 28_1545 +GTP_COMMON.GTPE2_COMMON.COMMON_CFG[3] 29_1545 +GTP_COMMON.GTPE2_COMMON.COMMON_CFG[4] 28_1546 +GTP_COMMON.GTPE2_COMMON.COMMON_CFG[5] 29_1546 +GTP_COMMON.GTPE2_COMMON.COMMON_CFG[6] 28_1547 +GTP_COMMON.GTPE2_COMMON.COMMON_CFG[7] 29_1547 +GTP_COMMON.GTPE2_COMMON.COMMON_CFG[8] 28_1548 +GTP_COMMON.GTPE2_COMMON.COMMON_CFG[9] 29_1548 +GTP_COMMON.GTPE2_COMMON.COMMON_CFG[10] 28_1549 +GTP_COMMON.GTPE2_COMMON.COMMON_CFG[11] 29_1549 +GTP_COMMON.GTPE2_COMMON.COMMON_CFG[12] 28_1550 +GTP_COMMON.GTPE2_COMMON.COMMON_CFG[13] 29_1550 +GTP_COMMON.GTPE2_COMMON.COMMON_CFG[14] 28_1551 +GTP_COMMON.GTPE2_COMMON.COMMON_CFG[15] 29_1551 +GTP_COMMON.GTPE2_COMMON.COMMON_CFG[16] 28_1552 +GTP_COMMON.GTPE2_COMMON.COMMON_CFG[17] 29_1552 +GTP_COMMON.GTPE2_COMMON.COMMON_CFG[18] 28_1553 +GTP_COMMON.GTPE2_COMMON.COMMON_CFG[19] 29_1553 +GTP_COMMON.GTPE2_COMMON.COMMON_CFG[20] 28_1554 +GTP_COMMON.GTPE2_COMMON.COMMON_CFG[21] 29_1554 +GTP_COMMON.GTPE2_COMMON.COMMON_CFG[22] 28_1555 +GTP_COMMON.GTPE2_COMMON.COMMON_CFG[23] 29_1555 +GTP_COMMON.GTPE2_COMMON.COMMON_CFG[24] 28_1556 +GTP_COMMON.GTPE2_COMMON.COMMON_CFG[25] 29_1556 +GTP_COMMON.GTPE2_COMMON.COMMON_CFG[26] 28_1557 +GTP_COMMON.GTPE2_COMMON.COMMON_CFG[27] 29_1557 +GTP_COMMON.GTPE2_COMMON.COMMON_CFG[28] 28_1558 +GTP_COMMON.GTPE2_COMMON.COMMON_CFG[29] 29_1558 +GTP_COMMON.GTPE2_COMMON.COMMON_CFG[30] 28_1559 +GTP_COMMON.GTPE2_COMMON.COMMON_CFG[31] 29_1559 +GTP_COMMON.GTPE2_COMMON.ENABLE_DRP 24_1613 25_1613 +GTP_COMMON.GTPE2_COMMON.IBUFDS_GTE2.CLKSWING_CFG[0] 29_1581 +GTP_COMMON.GTPE2_COMMON.IBUFDS_GTE2.CLKSWING_CFG[1] 28_1582 +GTP_COMMON.GTPE2_COMMON.IN_USE 28_1584 +GTP_COMMON.GTPE2_COMMON.INV_DRPCLK 28_1516 +GTP_COMMON.GTPE2_COMMON.INV_PLL0LOCKDETCLK 29_1512 +GTP_COMMON.GTPE2_COMMON.INV_PLL1LOCKDETCLK 28_1512 +GTP_COMMON.GTPE2_COMMON.PLL_CLKOUT_CFG[0] 28_1560 +GTP_COMMON.GTPE2_COMMON.PLL_CLKOUT_CFG[1] 29_1560 +GTP_COMMON.GTPE2_COMMON.PLL_CLKOUT_CFG[2] 28_1561 +GTP_COMMON.GTPE2_COMMON.PLL_CLKOUT_CFG[3] 29_1561 +GTP_COMMON.GTPE2_COMMON.PLL_CLKOUT_CFG[4] 28_1562 +GTP_COMMON.GTPE2_COMMON.PLL_CLKOUT_CFG[5] 29_1562 +GTP_COMMON.GTPE2_COMMON.PLL_CLKOUT_CFG[6] 28_1563 +GTP_COMMON.GTPE2_COMMON.PLL_CLKOUT_CFG[7] 29_1563 +GTP_COMMON.GTPE2_COMMON.RSVD_ATTR0[0] 28_1488 +GTP_COMMON.GTPE2_COMMON.RSVD_ATTR0[1] 29_1488 +GTP_COMMON.GTPE2_COMMON.RSVD_ATTR0[2] 28_1489 +GTP_COMMON.GTPE2_COMMON.RSVD_ATTR0[3] 29_1489 +GTP_COMMON.GTPE2_COMMON.RSVD_ATTR0[4] 28_1490 +GTP_COMMON.GTPE2_COMMON.RSVD_ATTR0[5] 29_1490 +GTP_COMMON.GTPE2_COMMON.RSVD_ATTR0[6] 28_1491 +GTP_COMMON.GTPE2_COMMON.RSVD_ATTR0[7] 29_1491 +GTP_COMMON.GTPE2_COMMON.RSVD_ATTR0[8] 28_1492 +GTP_COMMON.GTPE2_COMMON.RSVD_ATTR0[9] 29_1492 +GTP_COMMON.GTPE2_COMMON.RSVD_ATTR0[10] 28_1493 +GTP_COMMON.GTPE2_COMMON.RSVD_ATTR0[11] 29_1493 +GTP_COMMON.GTPE2_COMMON.RSVD_ATTR0[12] 28_1494 +GTP_COMMON.GTPE2_COMMON.RSVD_ATTR0[13] 29_1494 +GTP_COMMON.GTPE2_COMMON.RSVD_ATTR0[14] 28_1495 +GTP_COMMON.GTPE2_COMMON.RSVD_ATTR0[15] 29_1495 +GTP_COMMON.GTPE2_COMMON.RSVD_ATTR1[0] 28_1728 +GTP_COMMON.GTPE2_COMMON.RSVD_ATTR1[1] 29_1728 +GTP_COMMON.GTPE2_COMMON.RSVD_ATTR1[2] 28_1729 +GTP_COMMON.GTPE2_COMMON.RSVD_ATTR1[3] 29_1729 +GTP_COMMON.GTPE2_COMMON.RSVD_ATTR1[4] 28_1730 +GTP_COMMON.GTPE2_COMMON.RSVD_ATTR1[5] 29_1730 +GTP_COMMON.GTPE2_COMMON.RSVD_ATTR1[6] 28_1731 +GTP_COMMON.GTPE2_COMMON.RSVD_ATTR1[7] 29_1731 +GTP_COMMON.GTPE2_COMMON.RSVD_ATTR1[8] 28_1732 +GTP_COMMON.GTPE2_COMMON.RSVD_ATTR1[9] 29_1732 +GTP_COMMON.GTPE2_COMMON.RSVD_ATTR1[10] 28_1733 +GTP_COMMON.GTPE2_COMMON.RSVD_ATTR1[11] 29_1733 +GTP_COMMON.GTPE2_COMMON.RSVD_ATTR1[12] 28_1734 +GTP_COMMON.GTPE2_COMMON.RSVD_ATTR1[13] 29_1734 +GTP_COMMON.GTPE2_COMMON.RSVD_ATTR1[14] 28_1735 +GTP_COMMON.GTPE2_COMMON.RSVD_ATTR1[15] 29_1735 +GTP_COMMON.GTPE2_COMMON.GTREFCLK0_USED 28_1438 28_1806 +GTP_COMMON.GTPE2_COMMON.GTREFCLK1_USED 29_1438 29_1806 +GTP_COMMON.GTPE2_COMMON.PLL0_CFG[0] 28_1424 +GTP_COMMON.GTPE2_COMMON.PLL0_CFG[1] 29_1424 +GTP_COMMON.GTPE2_COMMON.PLL0_CFG[2] 28_1425 +GTP_COMMON.GTPE2_COMMON.PLL0_CFG[3] 29_1425 +GTP_COMMON.GTPE2_COMMON.PLL0_CFG[4] 28_1426 +GTP_COMMON.GTPE2_COMMON.PLL0_CFG[5] 29_1426 +GTP_COMMON.GTPE2_COMMON.PLL0_CFG[6] 28_1427 +GTP_COMMON.GTPE2_COMMON.PLL0_CFG[7] 29_1427 +GTP_COMMON.GTPE2_COMMON.PLL0_CFG[8] 28_1428 +GTP_COMMON.GTPE2_COMMON.PLL0_CFG[9] 29_1428 +GTP_COMMON.GTPE2_COMMON.PLL0_CFG[10] 28_1429 +GTP_COMMON.GTPE2_COMMON.PLL0_CFG[11] 29_1429 +GTP_COMMON.GTPE2_COMMON.PLL0_CFG[12] 28_1430 +GTP_COMMON.GTPE2_COMMON.PLL0_CFG[13] 29_1430 +GTP_COMMON.GTPE2_COMMON.PLL0_CFG[14] 28_1431 +GTP_COMMON.GTPE2_COMMON.PLL0_CFG[15] 29_1431 +GTP_COMMON.GTPE2_COMMON.PLL0_CFG[16] 28_1432 +GTP_COMMON.GTPE2_COMMON.PLL0_CFG[17] 29_1432 +GTP_COMMON.GTPE2_COMMON.PLL0_CFG[18] 28_1433 +GTP_COMMON.GTPE2_COMMON.PLL0_CFG[19] 29_1433 +GTP_COMMON.GTPE2_COMMON.PLL0_CFG[20] 28_1434 +GTP_COMMON.GTPE2_COMMON.PLL0_CFG[21] 29_1434 +GTP_COMMON.GTPE2_COMMON.PLL0_CFG[22] 28_1435 +GTP_COMMON.GTPE2_COMMON.PLL0_CFG[23] 29_1435 +GTP_COMMON.GTPE2_COMMON.PLL0_CFG[24] 28_1436 +GTP_COMMON.GTPE2_COMMON.PLL0_CFG[25] 29_1436 +GTP_COMMON.GTPE2_COMMON.PLL0_CFG[26] 28_1437 +GTP_COMMON.GTPE2_COMMON.PLL0_DMON_CFG[0] 28_1528 +GTP_COMMON.GTPE2_COMMON.PLL0_FBDIV[0] 28_1440 +GTP_COMMON.GTPE2_COMMON.PLL0_FBDIV[1] 29_1440 +GTP_COMMON.GTPE2_COMMON.PLL0_FBDIV[4] 28_1442 +GTP_COMMON.GTPE2_COMMON.PLL0_FBDIV_45[0] 29_1443 +GTP_COMMON.GTPE2_COMMON.PLL0_INIT_CFG[0] 28_1456 +GTP_COMMON.GTPE2_COMMON.PLL0_INIT_CFG[1] 29_1456 +GTP_COMMON.GTPE2_COMMON.PLL0_INIT_CFG[2] 28_1457 +GTP_COMMON.GTPE2_COMMON.PLL0_INIT_CFG[3] 29_1457 +GTP_COMMON.GTPE2_COMMON.PLL0_INIT_CFG[4] 28_1458 +GTP_COMMON.GTPE2_COMMON.PLL0_INIT_CFG[5] 29_1458 +GTP_COMMON.GTPE2_COMMON.PLL0_INIT_CFG[6] 28_1459 +GTP_COMMON.GTPE2_COMMON.PLL0_INIT_CFG[7] 29_1459 +GTP_COMMON.GTPE2_COMMON.PLL0_INIT_CFG[8] 28_1460 +GTP_COMMON.GTPE2_COMMON.PLL0_INIT_CFG[9] 29_1460 +GTP_COMMON.GTPE2_COMMON.PLL0_INIT_CFG[10] 28_1461 +GTP_COMMON.GTPE2_COMMON.PLL0_INIT_CFG[11] 29_1461 +GTP_COMMON.GTPE2_COMMON.PLL0_INIT_CFG[12] 28_1462 +GTP_COMMON.GTPE2_COMMON.PLL0_INIT_CFG[13] 29_1462 +GTP_COMMON.GTPE2_COMMON.PLL0_INIT_CFG[14] 28_1463 +GTP_COMMON.GTPE2_COMMON.PLL0_INIT_CFG[15] 29_1463 +GTP_COMMON.GTPE2_COMMON.PLL0_INIT_CFG[16] 28_1464 +GTP_COMMON.GTPE2_COMMON.PLL0_INIT_CFG[17] 29_1464 +GTP_COMMON.GTPE2_COMMON.PLL0_INIT_CFG[18] 28_1465 +GTP_COMMON.GTPE2_COMMON.PLL0_INIT_CFG[19] 29_1465 +GTP_COMMON.GTPE2_COMMON.PLL0_INIT_CFG[20] 28_1466 +GTP_COMMON.GTPE2_COMMON.PLL0_INIT_CFG[21] 29_1466 +GTP_COMMON.GTPE2_COMMON.PLL0_INIT_CFG[22] 28_1467 +GTP_COMMON.GTPE2_COMMON.PLL0_INIT_CFG[23] 29_1467 +GTP_COMMON.GTPE2_COMMON.PLL0_LOCK_CFG[0] 28_1448 +GTP_COMMON.GTPE2_COMMON.PLL0_LOCK_CFG[1] 29_1448 +GTP_COMMON.GTPE2_COMMON.PLL0_LOCK_CFG[2] 28_1449 +GTP_COMMON.GTPE2_COMMON.PLL0_LOCK_CFG[3] 29_1449 +GTP_COMMON.GTPE2_COMMON.PLL0_LOCK_CFG[4] 28_1450 +GTP_COMMON.GTPE2_COMMON.PLL0_LOCK_CFG[5] 29_1450 +GTP_COMMON.GTPE2_COMMON.PLL0_LOCK_CFG[6] 28_1451 +GTP_COMMON.GTPE2_COMMON.PLL0_LOCK_CFG[7] 29_1451 +GTP_COMMON.GTPE2_COMMON.PLL0_LOCK_CFG[8] 28_1452 +GTP_COMMON.GTPE2_COMMON.PLL0_REFCLK_DIV[4] 29_1446 +GTP_COMMON.GTPE2_COMMON.PLL1_CFG[0] 28_1792 +GTP_COMMON.GTPE2_COMMON.PLL1_CFG[1] 29_1792 +GTP_COMMON.GTPE2_COMMON.PLL1_CFG[2] 28_1793 +GTP_COMMON.GTPE2_COMMON.PLL1_CFG[3] 29_1793 +GTP_COMMON.GTPE2_COMMON.PLL1_CFG[4] 28_1794 +GTP_COMMON.GTPE2_COMMON.PLL1_CFG[5] 29_1794 +GTP_COMMON.GTPE2_COMMON.PLL1_CFG[6] 28_1795 +GTP_COMMON.GTPE2_COMMON.PLL1_CFG[7] 29_1795 +GTP_COMMON.GTPE2_COMMON.PLL1_CFG[8] 28_1796 +GTP_COMMON.GTPE2_COMMON.PLL1_CFG[9] 29_1796 +GTP_COMMON.GTPE2_COMMON.PLL1_CFG[10] 28_1797 +GTP_COMMON.GTPE2_COMMON.PLL1_CFG[11] 29_1797 +GTP_COMMON.GTPE2_COMMON.PLL1_CFG[12] 28_1798 +GTP_COMMON.GTPE2_COMMON.PLL1_CFG[13] 29_1798 +GTP_COMMON.GTPE2_COMMON.PLL1_CFG[14] 28_1799 +GTP_COMMON.GTPE2_COMMON.PLL1_CFG[15] 29_1799 +GTP_COMMON.GTPE2_COMMON.PLL1_CFG[16] 28_1800 +GTP_COMMON.GTPE2_COMMON.PLL1_CFG[17] 29_1800 +GTP_COMMON.GTPE2_COMMON.PLL1_CFG[18] 28_1801 +GTP_COMMON.GTPE2_COMMON.PLL1_CFG[19] 29_1801 +GTP_COMMON.GTPE2_COMMON.PLL1_CFG[20] 28_1802 +GTP_COMMON.GTPE2_COMMON.PLL1_CFG[21] 29_1802 +GTP_COMMON.GTPE2_COMMON.PLL1_CFG[22] 28_1803 +GTP_COMMON.GTPE2_COMMON.PLL1_CFG[23] 29_1803 +GTP_COMMON.GTPE2_COMMON.PLL1_CFG[24] 28_1804 +GTP_COMMON.GTPE2_COMMON.PLL1_CFG[25] 29_1804 +GTP_COMMON.GTPE2_COMMON.PLL1_CFG[26] 28_1805 +GTP_COMMON.GTPE2_COMMON.PLL1_DMON_CFG[0] 29_1528 +GTP_COMMON.GTPE2_COMMON.PLL1_FBDIV[0] 28_1784 +GTP_COMMON.GTPE2_COMMON.PLL1_FBDIV[1] 29_1784 +GTP_COMMON.GTPE2_COMMON.PLL1_FBDIV[4] 28_1786 +GTP_COMMON.GTPE2_COMMON.PLL1_FBDIV_45[0] 29_1787 +GTP_COMMON.GTPE2_COMMON.PLL1_INIT_CFG[0] 28_1760 +GTP_COMMON.GTPE2_COMMON.PLL1_INIT_CFG[1] 29_1760 +GTP_COMMON.GTPE2_COMMON.PLL1_INIT_CFG[2] 28_1761 +GTP_COMMON.GTPE2_COMMON.PLL1_INIT_CFG[3] 29_1761 +GTP_COMMON.GTPE2_COMMON.PLL1_INIT_CFG[4] 28_1762 +GTP_COMMON.GTPE2_COMMON.PLL1_INIT_CFG[5] 29_1762 +GTP_COMMON.GTPE2_COMMON.PLL1_INIT_CFG[6] 28_1763 +GTP_COMMON.GTPE2_COMMON.PLL1_INIT_CFG[7] 29_1763 +GTP_COMMON.GTPE2_COMMON.PLL1_INIT_CFG[8] 28_1764 +GTP_COMMON.GTPE2_COMMON.PLL1_INIT_CFG[9] 29_1764 +GTP_COMMON.GTPE2_COMMON.PLL1_INIT_CFG[10] 28_1765 +GTP_COMMON.GTPE2_COMMON.PLL1_INIT_CFG[11] 29_1765 +GTP_COMMON.GTPE2_COMMON.PLL1_INIT_CFG[12] 28_1766 +GTP_COMMON.GTPE2_COMMON.PLL1_INIT_CFG[13] 29_1766 +GTP_COMMON.GTPE2_COMMON.PLL1_INIT_CFG[14] 28_1767 +GTP_COMMON.GTPE2_COMMON.PLL1_INIT_CFG[15] 29_1767 +GTP_COMMON.GTPE2_COMMON.PLL1_INIT_CFG[16] 28_1768 +GTP_COMMON.GTPE2_COMMON.PLL1_INIT_CFG[17] 29_1768 +GTP_COMMON.GTPE2_COMMON.PLL1_INIT_CFG[18] 28_1769 +GTP_COMMON.GTPE2_COMMON.PLL1_INIT_CFG[19] 29_1769 +GTP_COMMON.GTPE2_COMMON.PLL1_INIT_CFG[20] 28_1770 +GTP_COMMON.GTPE2_COMMON.PLL1_INIT_CFG[21] 29_1770 +GTP_COMMON.GTPE2_COMMON.PLL1_INIT_CFG[22] 28_1771 +GTP_COMMON.GTPE2_COMMON.PLL1_INIT_CFG[23] 29_1771 +GTP_COMMON.GTPE2_COMMON.PLL1_LOCK_CFG[0] 28_1776 +GTP_COMMON.GTPE2_COMMON.PLL1_LOCK_CFG[1] 29_1776 +GTP_COMMON.GTPE2_COMMON.PLL1_LOCK_CFG[2] 28_1777 +GTP_COMMON.GTPE2_COMMON.PLL1_LOCK_CFG[3] 29_1777 +GTP_COMMON.GTPE2_COMMON.PLL1_LOCK_CFG[4] 28_1778 +GTP_COMMON.GTPE2_COMMON.PLL1_LOCK_CFG[5] 29_1778 +GTP_COMMON.GTPE2_COMMON.PLL1_LOCK_CFG[6] 28_1779 +GTP_COMMON.GTPE2_COMMON.PLL1_LOCK_CFG[7] 29_1779 +GTP_COMMON.GTPE2_COMMON.PLL1_LOCK_CFG[8] 28_1780 +GTP_COMMON.GTPE2_COMMON.PLL1_REFCLK_DIV[4] 29_1790 diff --git a/artix7/segbits_gtp_common.origin_info.db b/artix7/segbits_gtp_common.origin_info.db index 3a8bd76..4fd9e9a 100644 --- a/artix7/segbits_gtp_common.origin_info.db +++ b/artix7/segbits_gtp_common.origin_info.db @@ -1,284 +1,284 @@ -GTP_COMMON.ENABLE_DRP origin:063-gtp-common-conf 24_1613 25_1613 -GTP_COMMON.IBUFDS_GTE2.CLKCM_CFG[0] origin:063-gtp-common-conf 29_1581 -GTP_COMMON.IBUFDS_GTE2.CLKCM_CFG[1] origin:063-gtp-common-conf 28_1582 GTP_COMMON.IBUFDS_GTE2_Y0.CLKCM_CFG origin:063-gtp-common-conf 28_1580 GTP_COMMON.IBUFDS_GTE2_Y0.CLKRCV_TRST origin:063-gtp-common-conf 28_1576 GTP_COMMON.IBUFDS_GTE2_Y0.IN_USE origin:063-gtp-common-conf 28_1578 GTP_COMMON.IBUFDS_GTE2_Y1.CLKCM_CFG origin:063-gtp-common-conf 29_1580 GTP_COMMON.IBUFDS_GTE2_Y1.CLKRCV_TRST origin:063-gtp-common-conf 29_1576 GTP_COMMON.IBUFDS_GTE2_Y1.IN_USE origin:063-gtp-common-conf 28_1579 -GTP_COMMON.GTPE2.BIAS_CFG[0] origin:063-gtp-common-conf 28_1640 -GTP_COMMON.GTPE2.BIAS_CFG[1] origin:063-gtp-common-conf 29_1640 -GTP_COMMON.GTPE2.BIAS_CFG[2] origin:063-gtp-common-conf 28_1641 -GTP_COMMON.GTPE2.BIAS_CFG[3] origin:063-gtp-common-conf 29_1641 -GTP_COMMON.GTPE2.BIAS_CFG[4] origin:063-gtp-common-conf 28_1642 -GTP_COMMON.GTPE2.BIAS_CFG[5] origin:063-gtp-common-conf 29_1642 -GTP_COMMON.GTPE2.BIAS_CFG[6] origin:063-gtp-common-conf 28_1643 -GTP_COMMON.GTPE2.BIAS_CFG[7] origin:063-gtp-common-conf 29_1643 -GTP_COMMON.GTPE2.BIAS_CFG[8] origin:063-gtp-common-conf 28_1644 -GTP_COMMON.GTPE2.BIAS_CFG[9] origin:063-gtp-common-conf 29_1644 -GTP_COMMON.GTPE2.BIAS_CFG[10] origin:063-gtp-common-conf 28_1645 -GTP_COMMON.GTPE2.BIAS_CFG[11] origin:063-gtp-common-conf 29_1645 -GTP_COMMON.GTPE2.BIAS_CFG[12] origin:063-gtp-common-conf 28_1646 -GTP_COMMON.GTPE2.BIAS_CFG[13] origin:063-gtp-common-conf 29_1646 -GTP_COMMON.GTPE2.BIAS_CFG[14] origin:063-gtp-common-conf 28_1647 -GTP_COMMON.GTPE2.BIAS_CFG[15] origin:063-gtp-common-conf 29_1647 -GTP_COMMON.GTPE2.BIAS_CFG[16] origin:063-gtp-common-conf 28_1648 -GTP_COMMON.GTPE2.BIAS_CFG[17] origin:063-gtp-common-conf 29_1648 -GTP_COMMON.GTPE2.BIAS_CFG[18] origin:063-gtp-common-conf 28_1649 -GTP_COMMON.GTPE2.BIAS_CFG[19] origin:063-gtp-common-conf 29_1649 -GTP_COMMON.GTPE2.BIAS_CFG[20] origin:063-gtp-common-conf 28_1650 -GTP_COMMON.GTPE2.BIAS_CFG[21] origin:063-gtp-common-conf 29_1650 -GTP_COMMON.GTPE2.BIAS_CFG[22] origin:063-gtp-common-conf 28_1651 -GTP_COMMON.GTPE2.BIAS_CFG[23] origin:063-gtp-common-conf 29_1651 -GTP_COMMON.GTPE2.BIAS_CFG[24] origin:063-gtp-common-conf 28_1652 -GTP_COMMON.GTPE2.BIAS_CFG[25] origin:063-gtp-common-conf 29_1652 -GTP_COMMON.GTPE2.BIAS_CFG[26] origin:063-gtp-common-conf 28_1653 -GTP_COMMON.GTPE2.BIAS_CFG[27] origin:063-gtp-common-conf 29_1653 -GTP_COMMON.GTPE2.BIAS_CFG[28] origin:063-gtp-common-conf 28_1654 -GTP_COMMON.GTPE2.BIAS_CFG[29] origin:063-gtp-common-conf 29_1654 -GTP_COMMON.GTPE2.BIAS_CFG[30] origin:063-gtp-common-conf 28_1655 -GTP_COMMON.GTPE2.BIAS_CFG[31] origin:063-gtp-common-conf 29_1655 -GTP_COMMON.GTPE2.BIAS_CFG[32] origin:063-gtp-common-conf 28_1656 -GTP_COMMON.GTPE2.BIAS_CFG[33] origin:063-gtp-common-conf 29_1656 -GTP_COMMON.GTPE2.BIAS_CFG[34] origin:063-gtp-common-conf 28_1657 -GTP_COMMON.GTPE2.BIAS_CFG[35] origin:063-gtp-common-conf 29_1657 -GTP_COMMON.GTPE2.BIAS_CFG[36] origin:063-gtp-common-conf 28_1658 -GTP_COMMON.GTPE2.BIAS_CFG[37] origin:063-gtp-common-conf 29_1658 -GTP_COMMON.GTPE2.BIAS_CFG[38] origin:063-gtp-common-conf 28_1659 -GTP_COMMON.GTPE2.BIAS_CFG[39] origin:063-gtp-common-conf 29_1659 -GTP_COMMON.GTPE2.BIAS_CFG[40] origin:063-gtp-common-conf 28_1660 -GTP_COMMON.GTPE2.BIAS_CFG[41] origin:063-gtp-common-conf 29_1660 -GTP_COMMON.GTPE2.BIAS_CFG[42] origin:063-gtp-common-conf 28_1661 -GTP_COMMON.GTPE2.BIAS_CFG[43] origin:063-gtp-common-conf 29_1661 -GTP_COMMON.GTPE2.BIAS_CFG[44] origin:063-gtp-common-conf 28_1662 -GTP_COMMON.GTPE2.BIAS_CFG[45] origin:063-gtp-common-conf 29_1662 -GTP_COMMON.GTPE2.BIAS_CFG[46] origin:063-gtp-common-conf 28_1663 -GTP_COMMON.GTPE2.BIAS_CFG[47] origin:063-gtp-common-conf 29_1663 -GTP_COMMON.GTPE2.BIAS_CFG[48] origin:063-gtp-common-conf 28_1664 -GTP_COMMON.GTPE2.BIAS_CFG[49] origin:063-gtp-common-conf 29_1664 -GTP_COMMON.GTPE2.BIAS_CFG[50] origin:063-gtp-common-conf 28_1665 -GTP_COMMON.GTPE2.BIAS_CFG[51] origin:063-gtp-common-conf 29_1665 -GTP_COMMON.GTPE2.BIAS_CFG[52] origin:063-gtp-common-conf 28_1666 -GTP_COMMON.GTPE2.BIAS_CFG[53] origin:063-gtp-common-conf 29_1666 -GTP_COMMON.GTPE2.BIAS_CFG[54] origin:063-gtp-common-conf 28_1667 -GTP_COMMON.GTPE2.BIAS_CFG[55] origin:063-gtp-common-conf 29_1667 -GTP_COMMON.GTPE2.BIAS_CFG[56] origin:063-gtp-common-conf 28_1668 -GTP_COMMON.GTPE2.BIAS_CFG[57] origin:063-gtp-common-conf 29_1668 -GTP_COMMON.GTPE2.BIAS_CFG[58] origin:063-gtp-common-conf 28_1669 -GTP_COMMON.GTPE2.BIAS_CFG[59] origin:063-gtp-common-conf 29_1669 -GTP_COMMON.GTPE2.BIAS_CFG[60] origin:063-gtp-common-conf 28_1670 -GTP_COMMON.GTPE2.BIAS_CFG[61] origin:063-gtp-common-conf 29_1670 -GTP_COMMON.GTPE2.BIAS_CFG[62] origin:063-gtp-common-conf 28_1671 -GTP_COMMON.GTPE2.BIAS_CFG[63] origin:063-gtp-common-conf 29_1671 -GTP_COMMON.GTPE2.BOTH_GTREFCLK_USED origin:063-gtp-common-conf 29_1439 29_1807 -GTP_COMMON.GTPE2.COMMON_CFG[0] origin:063-gtp-common-conf 28_1544 -GTP_COMMON.GTPE2.COMMON_CFG[1] origin:063-gtp-common-conf 29_1544 -GTP_COMMON.GTPE2.COMMON_CFG[2] origin:063-gtp-common-conf 28_1545 -GTP_COMMON.GTPE2.COMMON_CFG[3] origin:063-gtp-common-conf 29_1545 -GTP_COMMON.GTPE2.COMMON_CFG[4] origin:063-gtp-common-conf 28_1546 -GTP_COMMON.GTPE2.COMMON_CFG[5] origin:063-gtp-common-conf 29_1546 -GTP_COMMON.GTPE2.COMMON_CFG[6] origin:063-gtp-common-conf 28_1547 -GTP_COMMON.GTPE2.COMMON_CFG[7] origin:063-gtp-common-conf 29_1547 -GTP_COMMON.GTPE2.COMMON_CFG[8] origin:063-gtp-common-conf 28_1548 -GTP_COMMON.GTPE2.COMMON_CFG[9] origin:063-gtp-common-conf 29_1548 -GTP_COMMON.GTPE2.COMMON_CFG[10] origin:063-gtp-common-conf 28_1549 -GTP_COMMON.GTPE2.COMMON_CFG[11] origin:063-gtp-common-conf 29_1549 -GTP_COMMON.GTPE2.COMMON_CFG[12] origin:063-gtp-common-conf 28_1550 -GTP_COMMON.GTPE2.COMMON_CFG[13] origin:063-gtp-common-conf 29_1550 -GTP_COMMON.GTPE2.COMMON_CFG[14] origin:063-gtp-common-conf 28_1551 -GTP_COMMON.GTPE2.COMMON_CFG[15] origin:063-gtp-common-conf 29_1551 -GTP_COMMON.GTPE2.COMMON_CFG[16] origin:063-gtp-common-conf 28_1552 -GTP_COMMON.GTPE2.COMMON_CFG[17] origin:063-gtp-common-conf 29_1552 -GTP_COMMON.GTPE2.COMMON_CFG[18] origin:063-gtp-common-conf 28_1553 -GTP_COMMON.GTPE2.COMMON_CFG[19] origin:063-gtp-common-conf 29_1553 -GTP_COMMON.GTPE2.COMMON_CFG[20] origin:063-gtp-common-conf 28_1554 -GTP_COMMON.GTPE2.COMMON_CFG[21] origin:063-gtp-common-conf 29_1554 -GTP_COMMON.GTPE2.COMMON_CFG[22] origin:063-gtp-common-conf 28_1555 -GTP_COMMON.GTPE2.COMMON_CFG[23] origin:063-gtp-common-conf 29_1555 -GTP_COMMON.GTPE2.COMMON_CFG[24] origin:063-gtp-common-conf 28_1556 -GTP_COMMON.GTPE2.COMMON_CFG[25] origin:063-gtp-common-conf 29_1556 -GTP_COMMON.GTPE2.COMMON_CFG[26] origin:063-gtp-common-conf 28_1557 -GTP_COMMON.GTPE2.COMMON_CFG[27] origin:063-gtp-common-conf 29_1557 -GTP_COMMON.GTPE2.COMMON_CFG[28] origin:063-gtp-common-conf 28_1558 -GTP_COMMON.GTPE2.COMMON_CFG[29] origin:063-gtp-common-conf 29_1558 -GTP_COMMON.GTPE2.COMMON_CFG[30] origin:063-gtp-common-conf 28_1559 -GTP_COMMON.GTPE2.COMMON_CFG[31] origin:063-gtp-common-conf 29_1559 -GTP_COMMON.GTPE2.IN_USE origin:063-gtp-common-conf 28_1584 -GTP_COMMON.GTPE2.PLL_CLKOUT_CFG[0] origin:063-gtp-common-conf 28_1560 -GTP_COMMON.GTPE2.PLL_CLKOUT_CFG[1] origin:063-gtp-common-conf 29_1560 -GTP_COMMON.GTPE2.PLL_CLKOUT_CFG[2] origin:063-gtp-common-conf 28_1561 -GTP_COMMON.GTPE2.PLL_CLKOUT_CFG[3] origin:063-gtp-common-conf 29_1561 -GTP_COMMON.GTPE2.PLL_CLKOUT_CFG[4] origin:063-gtp-common-conf 28_1562 -GTP_COMMON.GTPE2.PLL_CLKOUT_CFG[5] origin:063-gtp-common-conf 29_1562 -GTP_COMMON.GTPE2.PLL_CLKOUT_CFG[6] origin:063-gtp-common-conf 28_1563 -GTP_COMMON.GTPE2.PLL_CLKOUT_CFG[7] origin:063-gtp-common-conf 29_1563 -GTP_COMMON.GTPE2.RSVD_ATTR0[0] origin:063-gtp-common-conf 28_1488 -GTP_COMMON.GTPE2.RSVD_ATTR0[1] origin:063-gtp-common-conf 29_1488 -GTP_COMMON.GTPE2.RSVD_ATTR0[2] origin:063-gtp-common-conf 28_1489 -GTP_COMMON.GTPE2.RSVD_ATTR0[3] origin:063-gtp-common-conf 29_1489 -GTP_COMMON.GTPE2.RSVD_ATTR0[4] origin:063-gtp-common-conf 28_1490 -GTP_COMMON.GTPE2.RSVD_ATTR0[5] origin:063-gtp-common-conf 29_1490 -GTP_COMMON.GTPE2.RSVD_ATTR0[6] origin:063-gtp-common-conf 28_1491 -GTP_COMMON.GTPE2.RSVD_ATTR0[7] origin:063-gtp-common-conf 29_1491 -GTP_COMMON.GTPE2.RSVD_ATTR0[8] origin:063-gtp-common-conf 28_1492 -GTP_COMMON.GTPE2.RSVD_ATTR0[9] origin:063-gtp-common-conf 29_1492 -GTP_COMMON.GTPE2.RSVD_ATTR0[10] origin:063-gtp-common-conf 28_1493 -GTP_COMMON.GTPE2.RSVD_ATTR0[11] origin:063-gtp-common-conf 29_1493 -GTP_COMMON.GTPE2.RSVD_ATTR0[12] origin:063-gtp-common-conf 28_1494 -GTP_COMMON.GTPE2.RSVD_ATTR0[13] origin:063-gtp-common-conf 29_1494 -GTP_COMMON.GTPE2.RSVD_ATTR0[14] origin:063-gtp-common-conf 28_1495 -GTP_COMMON.GTPE2.RSVD_ATTR0[15] origin:063-gtp-common-conf 29_1495 -GTP_COMMON.GTPE2.RSVD_ATTR1[0] origin:063-gtp-common-conf 28_1728 -GTP_COMMON.GTPE2.RSVD_ATTR1[1] origin:063-gtp-common-conf 29_1728 -GTP_COMMON.GTPE2.RSVD_ATTR1[2] origin:063-gtp-common-conf 28_1729 -GTP_COMMON.GTPE2.RSVD_ATTR1[3] origin:063-gtp-common-conf 29_1729 -GTP_COMMON.GTPE2.RSVD_ATTR1[4] origin:063-gtp-common-conf 28_1730 -GTP_COMMON.GTPE2.RSVD_ATTR1[5] origin:063-gtp-common-conf 29_1730 -GTP_COMMON.GTPE2.RSVD_ATTR1[6] origin:063-gtp-common-conf 28_1731 -GTP_COMMON.GTPE2.RSVD_ATTR1[7] origin:063-gtp-common-conf 29_1731 -GTP_COMMON.GTPE2.RSVD_ATTR1[8] origin:063-gtp-common-conf 28_1732 -GTP_COMMON.GTPE2.RSVD_ATTR1[9] origin:063-gtp-common-conf 29_1732 -GTP_COMMON.GTPE2.RSVD_ATTR1[10] origin:063-gtp-common-conf 28_1733 -GTP_COMMON.GTPE2.RSVD_ATTR1[11] origin:063-gtp-common-conf 29_1733 -GTP_COMMON.GTPE2.RSVD_ATTR1[12] origin:063-gtp-common-conf 28_1734 -GTP_COMMON.GTPE2.RSVD_ATTR1[13] origin:063-gtp-common-conf 29_1734 -GTP_COMMON.GTPE2.RSVD_ATTR1[14] origin:063-gtp-common-conf 28_1735 -GTP_COMMON.GTPE2.RSVD_ATTR1[15] origin:063-gtp-common-conf 29_1735 -GTP_COMMON.GTPE2.ZINV_DRPCLK origin:063-gtp-common-conf 28_1516 -GTP_COMMON.GTPE2.ZINV_PLL0LOCKDETCLK origin:063-gtp-common-conf 29_1512 -GTP_COMMON.GTPE2.ZINV_PLL1LOCKDETCLK origin:063-gtp-common-conf 28_1512 -GTP_COMMON.GTPE2.GTREFCLK0_USED origin:063-gtp-common-conf 28_1438 28_1806 -GTP_COMMON.GTPE2.GTREFCLK1_USED origin:063-gtp-common-conf 29_1438 29_1806 -GTP_COMMON.GTPE2.PLL0_CFG[0] origin:063-gtp-common-conf 28_1424 -GTP_COMMON.GTPE2.PLL0_CFG[1] origin:063-gtp-common-conf 29_1424 -GTP_COMMON.GTPE2.PLL0_CFG[2] origin:063-gtp-common-conf 28_1425 -GTP_COMMON.GTPE2.PLL0_CFG[3] origin:063-gtp-common-conf 29_1425 -GTP_COMMON.GTPE2.PLL0_CFG[4] origin:063-gtp-common-conf 28_1426 -GTP_COMMON.GTPE2.PLL0_CFG[5] origin:063-gtp-common-conf 29_1426 -GTP_COMMON.GTPE2.PLL0_CFG[6] origin:063-gtp-common-conf 28_1427 -GTP_COMMON.GTPE2.PLL0_CFG[7] origin:063-gtp-common-conf 29_1427 -GTP_COMMON.GTPE2.PLL0_CFG[8] origin:063-gtp-common-conf 28_1428 -GTP_COMMON.GTPE2.PLL0_CFG[9] origin:063-gtp-common-conf 29_1428 -GTP_COMMON.GTPE2.PLL0_CFG[10] origin:063-gtp-common-conf 28_1429 -GTP_COMMON.GTPE2.PLL0_CFG[11] origin:063-gtp-common-conf 29_1429 -GTP_COMMON.GTPE2.PLL0_CFG[12] origin:063-gtp-common-conf 28_1430 -GTP_COMMON.GTPE2.PLL0_CFG[13] origin:063-gtp-common-conf 29_1430 -GTP_COMMON.GTPE2.PLL0_CFG[14] origin:063-gtp-common-conf 28_1431 -GTP_COMMON.GTPE2.PLL0_CFG[15] origin:063-gtp-common-conf 29_1431 -GTP_COMMON.GTPE2.PLL0_CFG[16] origin:063-gtp-common-conf 28_1432 -GTP_COMMON.GTPE2.PLL0_CFG[17] origin:063-gtp-common-conf 29_1432 -GTP_COMMON.GTPE2.PLL0_CFG[18] origin:063-gtp-common-conf 28_1433 -GTP_COMMON.GTPE2.PLL0_CFG[19] origin:063-gtp-common-conf 29_1433 -GTP_COMMON.GTPE2.PLL0_CFG[20] origin:063-gtp-common-conf 28_1434 -GTP_COMMON.GTPE2.PLL0_CFG[21] origin:063-gtp-common-conf 29_1434 -GTP_COMMON.GTPE2.PLL0_CFG[22] origin:063-gtp-common-conf 28_1435 -GTP_COMMON.GTPE2.PLL0_CFG[23] origin:063-gtp-common-conf 29_1435 -GTP_COMMON.GTPE2.PLL0_CFG[24] origin:063-gtp-common-conf 28_1436 -GTP_COMMON.GTPE2.PLL0_CFG[25] origin:063-gtp-common-conf 29_1436 -GTP_COMMON.GTPE2.PLL0_CFG[26] origin:063-gtp-common-conf 28_1437 -GTP_COMMON.GTPE2.PLL0_DMON_CFG[0] origin:063-gtp-common-conf 28_1528 -GTP_COMMON.GTPE2.PLL0_FBDIV[0] origin:063-gtp-common-conf 28_1440 -GTP_COMMON.GTPE2.PLL0_FBDIV[1] origin:063-gtp-common-conf 29_1440 -GTP_COMMON.GTPE2.PLL0_FBDIV[4] origin:063-gtp-common-conf 28_1442 -GTP_COMMON.GTPE2.PLL0_FBDIV_45[0] origin:063-gtp-common-conf 29_1443 -GTP_COMMON.GTPE2.PLL0_INIT_CFG[0] origin:063-gtp-common-conf 28_1456 -GTP_COMMON.GTPE2.PLL0_INIT_CFG[1] origin:063-gtp-common-conf 29_1456 -GTP_COMMON.GTPE2.PLL0_INIT_CFG[2] origin:063-gtp-common-conf 28_1457 -GTP_COMMON.GTPE2.PLL0_INIT_CFG[3] origin:063-gtp-common-conf 29_1457 -GTP_COMMON.GTPE2.PLL0_INIT_CFG[4] origin:063-gtp-common-conf 28_1458 -GTP_COMMON.GTPE2.PLL0_INIT_CFG[5] origin:063-gtp-common-conf 29_1458 -GTP_COMMON.GTPE2.PLL0_INIT_CFG[6] origin:063-gtp-common-conf 28_1459 -GTP_COMMON.GTPE2.PLL0_INIT_CFG[7] origin:063-gtp-common-conf 29_1459 -GTP_COMMON.GTPE2.PLL0_INIT_CFG[8] origin:063-gtp-common-conf 28_1460 -GTP_COMMON.GTPE2.PLL0_INIT_CFG[9] origin:063-gtp-common-conf 29_1460 -GTP_COMMON.GTPE2.PLL0_INIT_CFG[10] origin:063-gtp-common-conf 28_1461 -GTP_COMMON.GTPE2.PLL0_INIT_CFG[11] origin:063-gtp-common-conf 29_1461 -GTP_COMMON.GTPE2.PLL0_INIT_CFG[12] origin:063-gtp-common-conf 28_1462 -GTP_COMMON.GTPE2.PLL0_INIT_CFG[13] origin:063-gtp-common-conf 29_1462 -GTP_COMMON.GTPE2.PLL0_INIT_CFG[14] origin:063-gtp-common-conf 28_1463 -GTP_COMMON.GTPE2.PLL0_INIT_CFG[15] origin:063-gtp-common-conf 29_1463 -GTP_COMMON.GTPE2.PLL0_INIT_CFG[16] origin:063-gtp-common-conf 28_1464 -GTP_COMMON.GTPE2.PLL0_INIT_CFG[17] origin:063-gtp-common-conf 29_1464 -GTP_COMMON.GTPE2.PLL0_INIT_CFG[18] origin:063-gtp-common-conf 28_1465 -GTP_COMMON.GTPE2.PLL0_INIT_CFG[19] origin:063-gtp-common-conf 29_1465 -GTP_COMMON.GTPE2.PLL0_INIT_CFG[20] origin:063-gtp-common-conf 28_1466 -GTP_COMMON.GTPE2.PLL0_INIT_CFG[21] origin:063-gtp-common-conf 29_1466 -GTP_COMMON.GTPE2.PLL0_INIT_CFG[22] origin:063-gtp-common-conf 28_1467 -GTP_COMMON.GTPE2.PLL0_INIT_CFG[23] origin:063-gtp-common-conf 29_1467 -GTP_COMMON.GTPE2.PLL0_LOCK_CFG[0] origin:063-gtp-common-conf 28_1448 -GTP_COMMON.GTPE2.PLL0_LOCK_CFG[1] origin:063-gtp-common-conf 29_1448 -GTP_COMMON.GTPE2.PLL0_LOCK_CFG[2] origin:063-gtp-common-conf 28_1449 -GTP_COMMON.GTPE2.PLL0_LOCK_CFG[3] origin:063-gtp-common-conf 29_1449 -GTP_COMMON.GTPE2.PLL0_LOCK_CFG[4] origin:063-gtp-common-conf 28_1450 -GTP_COMMON.GTPE2.PLL0_LOCK_CFG[5] origin:063-gtp-common-conf 29_1450 -GTP_COMMON.GTPE2.PLL0_LOCK_CFG[6] origin:063-gtp-common-conf 28_1451 -GTP_COMMON.GTPE2.PLL0_LOCK_CFG[7] origin:063-gtp-common-conf 29_1451 -GTP_COMMON.GTPE2.PLL0_LOCK_CFG[8] origin:063-gtp-common-conf 28_1452 -GTP_COMMON.GTPE2.PLL0_REFCLK_DIV[4] origin:063-gtp-common-conf 29_1446 -GTP_COMMON.GTPE2.PLL1_CFG[0] origin:063-gtp-common-conf 28_1792 -GTP_COMMON.GTPE2.PLL1_CFG[1] origin:063-gtp-common-conf 29_1792 -GTP_COMMON.GTPE2.PLL1_CFG[2] origin:063-gtp-common-conf 28_1793 -GTP_COMMON.GTPE2.PLL1_CFG[3] origin:063-gtp-common-conf 29_1793 -GTP_COMMON.GTPE2.PLL1_CFG[4] origin:063-gtp-common-conf 28_1794 -GTP_COMMON.GTPE2.PLL1_CFG[5] origin:063-gtp-common-conf 29_1794 -GTP_COMMON.GTPE2.PLL1_CFG[6] origin:063-gtp-common-conf 28_1795 -GTP_COMMON.GTPE2.PLL1_CFG[7] origin:063-gtp-common-conf 29_1795 -GTP_COMMON.GTPE2.PLL1_CFG[8] origin:063-gtp-common-conf 28_1796 -GTP_COMMON.GTPE2.PLL1_CFG[9] origin:063-gtp-common-conf 29_1796 -GTP_COMMON.GTPE2.PLL1_CFG[10] origin:063-gtp-common-conf 28_1797 -GTP_COMMON.GTPE2.PLL1_CFG[11] origin:063-gtp-common-conf 29_1797 -GTP_COMMON.GTPE2.PLL1_CFG[12] origin:063-gtp-common-conf 28_1798 -GTP_COMMON.GTPE2.PLL1_CFG[13] origin:063-gtp-common-conf 29_1798 -GTP_COMMON.GTPE2.PLL1_CFG[14] origin:063-gtp-common-conf 28_1799 -GTP_COMMON.GTPE2.PLL1_CFG[15] origin:063-gtp-common-conf 29_1799 -GTP_COMMON.GTPE2.PLL1_CFG[16] origin:063-gtp-common-conf 28_1800 -GTP_COMMON.GTPE2.PLL1_CFG[17] origin:063-gtp-common-conf 29_1800 -GTP_COMMON.GTPE2.PLL1_CFG[18] origin:063-gtp-common-conf 28_1801 -GTP_COMMON.GTPE2.PLL1_CFG[19] origin:063-gtp-common-conf 29_1801 -GTP_COMMON.GTPE2.PLL1_CFG[20] origin:063-gtp-common-conf 28_1802 -GTP_COMMON.GTPE2.PLL1_CFG[21] origin:063-gtp-common-conf 29_1802 -GTP_COMMON.GTPE2.PLL1_CFG[22] origin:063-gtp-common-conf 28_1803 -GTP_COMMON.GTPE2.PLL1_CFG[23] origin:063-gtp-common-conf 29_1803 -GTP_COMMON.GTPE2.PLL1_CFG[24] origin:063-gtp-common-conf 28_1804 -GTP_COMMON.GTPE2.PLL1_CFG[25] origin:063-gtp-common-conf 29_1804 -GTP_COMMON.GTPE2.PLL1_CFG[26] origin:063-gtp-common-conf 28_1805 -GTP_COMMON.GTPE2.PLL1_DMON_CFG[0] origin:063-gtp-common-conf 29_1528 -GTP_COMMON.GTPE2.PLL1_FBDIV[0] origin:063-gtp-common-conf 28_1784 -GTP_COMMON.GTPE2.PLL1_FBDIV[1] origin:063-gtp-common-conf 29_1784 -GTP_COMMON.GTPE2.PLL1_FBDIV[4] origin:063-gtp-common-conf 28_1786 -GTP_COMMON.GTPE2.PLL1_FBDIV_45[0] origin:063-gtp-common-conf 29_1787 -GTP_COMMON.GTPE2.PLL1_INIT_CFG[0] origin:063-gtp-common-conf 28_1760 -GTP_COMMON.GTPE2.PLL1_INIT_CFG[1] origin:063-gtp-common-conf 29_1760 -GTP_COMMON.GTPE2.PLL1_INIT_CFG[2] origin:063-gtp-common-conf 28_1761 -GTP_COMMON.GTPE2.PLL1_INIT_CFG[3] origin:063-gtp-common-conf 29_1761 -GTP_COMMON.GTPE2.PLL1_INIT_CFG[4] origin:063-gtp-common-conf 28_1762 -GTP_COMMON.GTPE2.PLL1_INIT_CFG[5] origin:063-gtp-common-conf 29_1762 -GTP_COMMON.GTPE2.PLL1_INIT_CFG[6] origin:063-gtp-common-conf 28_1763 -GTP_COMMON.GTPE2.PLL1_INIT_CFG[7] origin:063-gtp-common-conf 29_1763 -GTP_COMMON.GTPE2.PLL1_INIT_CFG[8] origin:063-gtp-common-conf 28_1764 -GTP_COMMON.GTPE2.PLL1_INIT_CFG[9] origin:063-gtp-common-conf 29_1764 -GTP_COMMON.GTPE2.PLL1_INIT_CFG[10] origin:063-gtp-common-conf 28_1765 -GTP_COMMON.GTPE2.PLL1_INIT_CFG[11] origin:063-gtp-common-conf 29_1765 -GTP_COMMON.GTPE2.PLL1_INIT_CFG[12] origin:063-gtp-common-conf 28_1766 -GTP_COMMON.GTPE2.PLL1_INIT_CFG[13] origin:063-gtp-common-conf 29_1766 -GTP_COMMON.GTPE2.PLL1_INIT_CFG[14] origin:063-gtp-common-conf 28_1767 -GTP_COMMON.GTPE2.PLL1_INIT_CFG[15] origin:063-gtp-common-conf 29_1767 -GTP_COMMON.GTPE2.PLL1_INIT_CFG[16] origin:063-gtp-common-conf 28_1768 -GTP_COMMON.GTPE2.PLL1_INIT_CFG[17] origin:063-gtp-common-conf 29_1768 -GTP_COMMON.GTPE2.PLL1_INIT_CFG[18] origin:063-gtp-common-conf 28_1769 -GTP_COMMON.GTPE2.PLL1_INIT_CFG[19] origin:063-gtp-common-conf 29_1769 -GTP_COMMON.GTPE2.PLL1_INIT_CFG[20] origin:063-gtp-common-conf 28_1770 -GTP_COMMON.GTPE2.PLL1_INIT_CFG[21] origin:063-gtp-common-conf 29_1770 -GTP_COMMON.GTPE2.PLL1_INIT_CFG[22] origin:063-gtp-common-conf 28_1771 -GTP_COMMON.GTPE2.PLL1_INIT_CFG[23] origin:063-gtp-common-conf 29_1771 -GTP_COMMON.GTPE2.PLL1_LOCK_CFG[0] origin:063-gtp-common-conf 28_1776 -GTP_COMMON.GTPE2.PLL1_LOCK_CFG[1] origin:063-gtp-common-conf 29_1776 -GTP_COMMON.GTPE2.PLL1_LOCK_CFG[2] origin:063-gtp-common-conf 28_1777 -GTP_COMMON.GTPE2.PLL1_LOCK_CFG[3] origin:063-gtp-common-conf 29_1777 -GTP_COMMON.GTPE2.PLL1_LOCK_CFG[4] origin:063-gtp-common-conf 28_1778 -GTP_COMMON.GTPE2.PLL1_LOCK_CFG[5] origin:063-gtp-common-conf 29_1778 -GTP_COMMON.GTPE2.PLL1_LOCK_CFG[6] origin:063-gtp-common-conf 28_1779 -GTP_COMMON.GTPE2.PLL1_LOCK_CFG[7] origin:063-gtp-common-conf 29_1779 -GTP_COMMON.GTPE2.PLL1_LOCK_CFG[8] origin:063-gtp-common-conf 28_1780 -GTP_COMMON.GTPE2.PLL1_REFCLK_DIV[4] origin:063-gtp-common-conf 29_1790 +GTP_COMMON.GTPE2_COMMON.BIAS_CFG[0] origin:063-gtp-common-conf 28_1640 +GTP_COMMON.GTPE2_COMMON.BIAS_CFG[1] origin:063-gtp-common-conf 29_1640 +GTP_COMMON.GTPE2_COMMON.BIAS_CFG[2] origin:063-gtp-common-conf 28_1641 +GTP_COMMON.GTPE2_COMMON.BIAS_CFG[3] origin:063-gtp-common-conf 29_1641 +GTP_COMMON.GTPE2_COMMON.BIAS_CFG[4] origin:063-gtp-common-conf 28_1642 +GTP_COMMON.GTPE2_COMMON.BIAS_CFG[5] origin:063-gtp-common-conf 29_1642 +GTP_COMMON.GTPE2_COMMON.BIAS_CFG[6] origin:063-gtp-common-conf 28_1643 +GTP_COMMON.GTPE2_COMMON.BIAS_CFG[7] origin:063-gtp-common-conf 29_1643 +GTP_COMMON.GTPE2_COMMON.BIAS_CFG[8] origin:063-gtp-common-conf 28_1644 +GTP_COMMON.GTPE2_COMMON.BIAS_CFG[9] origin:063-gtp-common-conf 29_1644 +GTP_COMMON.GTPE2_COMMON.BIAS_CFG[10] origin:063-gtp-common-conf 28_1645 +GTP_COMMON.GTPE2_COMMON.BIAS_CFG[11] origin:063-gtp-common-conf 29_1645 +GTP_COMMON.GTPE2_COMMON.BIAS_CFG[12] origin:063-gtp-common-conf 28_1646 +GTP_COMMON.GTPE2_COMMON.BIAS_CFG[13] origin:063-gtp-common-conf 29_1646 +GTP_COMMON.GTPE2_COMMON.BIAS_CFG[14] origin:063-gtp-common-conf 28_1647 +GTP_COMMON.GTPE2_COMMON.BIAS_CFG[15] origin:063-gtp-common-conf 29_1647 +GTP_COMMON.GTPE2_COMMON.BIAS_CFG[16] origin:063-gtp-common-conf 28_1648 +GTP_COMMON.GTPE2_COMMON.BIAS_CFG[17] origin:063-gtp-common-conf 29_1648 +GTP_COMMON.GTPE2_COMMON.BIAS_CFG[18] origin:063-gtp-common-conf 28_1649 +GTP_COMMON.GTPE2_COMMON.BIAS_CFG[19] origin:063-gtp-common-conf 29_1649 +GTP_COMMON.GTPE2_COMMON.BIAS_CFG[20] origin:063-gtp-common-conf 28_1650 +GTP_COMMON.GTPE2_COMMON.BIAS_CFG[21] origin:063-gtp-common-conf 29_1650 +GTP_COMMON.GTPE2_COMMON.BIAS_CFG[22] origin:063-gtp-common-conf 28_1651 +GTP_COMMON.GTPE2_COMMON.BIAS_CFG[23] origin:063-gtp-common-conf 29_1651 +GTP_COMMON.GTPE2_COMMON.BIAS_CFG[24] origin:063-gtp-common-conf 28_1652 +GTP_COMMON.GTPE2_COMMON.BIAS_CFG[25] origin:063-gtp-common-conf 29_1652 +GTP_COMMON.GTPE2_COMMON.BIAS_CFG[26] origin:063-gtp-common-conf 28_1653 +GTP_COMMON.GTPE2_COMMON.BIAS_CFG[27] origin:063-gtp-common-conf 29_1653 +GTP_COMMON.GTPE2_COMMON.BIAS_CFG[28] origin:063-gtp-common-conf 28_1654 +GTP_COMMON.GTPE2_COMMON.BIAS_CFG[29] origin:063-gtp-common-conf 29_1654 +GTP_COMMON.GTPE2_COMMON.BIAS_CFG[30] origin:063-gtp-common-conf 28_1655 +GTP_COMMON.GTPE2_COMMON.BIAS_CFG[31] origin:063-gtp-common-conf 29_1655 +GTP_COMMON.GTPE2_COMMON.BIAS_CFG[32] origin:063-gtp-common-conf 28_1656 +GTP_COMMON.GTPE2_COMMON.BIAS_CFG[33] origin:063-gtp-common-conf 29_1656 +GTP_COMMON.GTPE2_COMMON.BIAS_CFG[34] origin:063-gtp-common-conf 28_1657 +GTP_COMMON.GTPE2_COMMON.BIAS_CFG[35] origin:063-gtp-common-conf 29_1657 +GTP_COMMON.GTPE2_COMMON.BIAS_CFG[36] origin:063-gtp-common-conf 28_1658 +GTP_COMMON.GTPE2_COMMON.BIAS_CFG[37] origin:063-gtp-common-conf 29_1658 +GTP_COMMON.GTPE2_COMMON.BIAS_CFG[38] origin:063-gtp-common-conf 28_1659 +GTP_COMMON.GTPE2_COMMON.BIAS_CFG[39] origin:063-gtp-common-conf 29_1659 +GTP_COMMON.GTPE2_COMMON.BIAS_CFG[40] origin:063-gtp-common-conf 28_1660 +GTP_COMMON.GTPE2_COMMON.BIAS_CFG[41] origin:063-gtp-common-conf 29_1660 +GTP_COMMON.GTPE2_COMMON.BIAS_CFG[42] origin:063-gtp-common-conf 28_1661 +GTP_COMMON.GTPE2_COMMON.BIAS_CFG[43] origin:063-gtp-common-conf 29_1661 +GTP_COMMON.GTPE2_COMMON.BIAS_CFG[44] origin:063-gtp-common-conf 28_1662 +GTP_COMMON.GTPE2_COMMON.BIAS_CFG[45] origin:063-gtp-common-conf 29_1662 +GTP_COMMON.GTPE2_COMMON.BIAS_CFG[46] origin:063-gtp-common-conf 28_1663 +GTP_COMMON.GTPE2_COMMON.BIAS_CFG[47] origin:063-gtp-common-conf 29_1663 +GTP_COMMON.GTPE2_COMMON.BIAS_CFG[48] origin:063-gtp-common-conf 28_1664 +GTP_COMMON.GTPE2_COMMON.BIAS_CFG[49] origin:063-gtp-common-conf 29_1664 +GTP_COMMON.GTPE2_COMMON.BIAS_CFG[50] origin:063-gtp-common-conf 28_1665 +GTP_COMMON.GTPE2_COMMON.BIAS_CFG[51] origin:063-gtp-common-conf 29_1665 +GTP_COMMON.GTPE2_COMMON.BIAS_CFG[52] origin:063-gtp-common-conf 28_1666 +GTP_COMMON.GTPE2_COMMON.BIAS_CFG[53] origin:063-gtp-common-conf 29_1666 +GTP_COMMON.GTPE2_COMMON.BIAS_CFG[54] origin:063-gtp-common-conf 28_1667 +GTP_COMMON.GTPE2_COMMON.BIAS_CFG[55] origin:063-gtp-common-conf 29_1667 +GTP_COMMON.GTPE2_COMMON.BIAS_CFG[56] origin:063-gtp-common-conf 28_1668 +GTP_COMMON.GTPE2_COMMON.BIAS_CFG[57] origin:063-gtp-common-conf 29_1668 +GTP_COMMON.GTPE2_COMMON.BIAS_CFG[58] origin:063-gtp-common-conf 28_1669 +GTP_COMMON.GTPE2_COMMON.BIAS_CFG[59] origin:063-gtp-common-conf 29_1669 +GTP_COMMON.GTPE2_COMMON.BIAS_CFG[60] origin:063-gtp-common-conf 28_1670 +GTP_COMMON.GTPE2_COMMON.BIAS_CFG[61] origin:063-gtp-common-conf 29_1670 +GTP_COMMON.GTPE2_COMMON.BIAS_CFG[62] origin:063-gtp-common-conf 28_1671 +GTP_COMMON.GTPE2_COMMON.BIAS_CFG[63] origin:063-gtp-common-conf 29_1671 +GTP_COMMON.GTPE2_COMMON.BOTH_GTREFCLK_USED origin:063-gtp-common-conf 29_1439 29_1807 +GTP_COMMON.GTPE2_COMMON.COMMON_CFG[0] origin:063-gtp-common-conf 28_1544 +GTP_COMMON.GTPE2_COMMON.COMMON_CFG[1] origin:063-gtp-common-conf 29_1544 +GTP_COMMON.GTPE2_COMMON.COMMON_CFG[2] origin:063-gtp-common-conf 28_1545 +GTP_COMMON.GTPE2_COMMON.COMMON_CFG[3] origin:063-gtp-common-conf 29_1545 +GTP_COMMON.GTPE2_COMMON.COMMON_CFG[4] origin:063-gtp-common-conf 28_1546 +GTP_COMMON.GTPE2_COMMON.COMMON_CFG[5] origin:063-gtp-common-conf 29_1546 +GTP_COMMON.GTPE2_COMMON.COMMON_CFG[6] origin:063-gtp-common-conf 28_1547 +GTP_COMMON.GTPE2_COMMON.COMMON_CFG[7] origin:063-gtp-common-conf 29_1547 +GTP_COMMON.GTPE2_COMMON.COMMON_CFG[8] origin:063-gtp-common-conf 28_1548 +GTP_COMMON.GTPE2_COMMON.COMMON_CFG[9] origin:063-gtp-common-conf 29_1548 +GTP_COMMON.GTPE2_COMMON.COMMON_CFG[10] origin:063-gtp-common-conf 28_1549 +GTP_COMMON.GTPE2_COMMON.COMMON_CFG[11] origin:063-gtp-common-conf 29_1549 +GTP_COMMON.GTPE2_COMMON.COMMON_CFG[12] origin:063-gtp-common-conf 28_1550 +GTP_COMMON.GTPE2_COMMON.COMMON_CFG[13] origin:063-gtp-common-conf 29_1550 +GTP_COMMON.GTPE2_COMMON.COMMON_CFG[14] origin:063-gtp-common-conf 28_1551 +GTP_COMMON.GTPE2_COMMON.COMMON_CFG[15] origin:063-gtp-common-conf 29_1551 +GTP_COMMON.GTPE2_COMMON.COMMON_CFG[16] origin:063-gtp-common-conf 28_1552 +GTP_COMMON.GTPE2_COMMON.COMMON_CFG[17] origin:063-gtp-common-conf 29_1552 +GTP_COMMON.GTPE2_COMMON.COMMON_CFG[18] origin:063-gtp-common-conf 28_1553 +GTP_COMMON.GTPE2_COMMON.COMMON_CFG[19] origin:063-gtp-common-conf 29_1553 +GTP_COMMON.GTPE2_COMMON.COMMON_CFG[20] origin:063-gtp-common-conf 28_1554 +GTP_COMMON.GTPE2_COMMON.COMMON_CFG[21] origin:063-gtp-common-conf 29_1554 +GTP_COMMON.GTPE2_COMMON.COMMON_CFG[22] origin:063-gtp-common-conf 28_1555 +GTP_COMMON.GTPE2_COMMON.COMMON_CFG[23] origin:063-gtp-common-conf 29_1555 +GTP_COMMON.GTPE2_COMMON.COMMON_CFG[24] origin:063-gtp-common-conf 28_1556 +GTP_COMMON.GTPE2_COMMON.COMMON_CFG[25] origin:063-gtp-common-conf 29_1556 +GTP_COMMON.GTPE2_COMMON.COMMON_CFG[26] origin:063-gtp-common-conf 28_1557 +GTP_COMMON.GTPE2_COMMON.COMMON_CFG[27] origin:063-gtp-common-conf 29_1557 +GTP_COMMON.GTPE2_COMMON.COMMON_CFG[28] origin:063-gtp-common-conf 28_1558 +GTP_COMMON.GTPE2_COMMON.COMMON_CFG[29] origin:063-gtp-common-conf 29_1558 +GTP_COMMON.GTPE2_COMMON.COMMON_CFG[30] origin:063-gtp-common-conf 28_1559 +GTP_COMMON.GTPE2_COMMON.COMMON_CFG[31] origin:063-gtp-common-conf 29_1559 +GTP_COMMON.GTPE2_COMMON.ENABLE_DRP origin:063-gtp-common-conf 24_1613 25_1613 +GTP_COMMON.GTPE2_COMMON.IBUFDS_GTE2.CLKSWING_CFG[0] origin:063-gtp-common-conf 29_1581 +GTP_COMMON.GTPE2_COMMON.IBUFDS_GTE2.CLKSWING_CFG[1] origin:063-gtp-common-conf 28_1582 +GTP_COMMON.GTPE2_COMMON.IN_USE origin:063-gtp-common-conf 28_1584 +GTP_COMMON.GTPE2_COMMON.INV_DRPCLK origin:063-gtp-common-conf 28_1516 +GTP_COMMON.GTPE2_COMMON.INV_PLL0LOCKDETCLK origin:063-gtp-common-conf 29_1512 +GTP_COMMON.GTPE2_COMMON.INV_PLL1LOCKDETCLK origin:063-gtp-common-conf 28_1512 +GTP_COMMON.GTPE2_COMMON.PLL_CLKOUT_CFG[0] origin:063-gtp-common-conf 28_1560 +GTP_COMMON.GTPE2_COMMON.PLL_CLKOUT_CFG[1] origin:063-gtp-common-conf 29_1560 +GTP_COMMON.GTPE2_COMMON.PLL_CLKOUT_CFG[2] origin:063-gtp-common-conf 28_1561 +GTP_COMMON.GTPE2_COMMON.PLL_CLKOUT_CFG[3] origin:063-gtp-common-conf 29_1561 +GTP_COMMON.GTPE2_COMMON.PLL_CLKOUT_CFG[4] origin:063-gtp-common-conf 28_1562 +GTP_COMMON.GTPE2_COMMON.PLL_CLKOUT_CFG[5] origin:063-gtp-common-conf 29_1562 +GTP_COMMON.GTPE2_COMMON.PLL_CLKOUT_CFG[6] origin:063-gtp-common-conf 28_1563 +GTP_COMMON.GTPE2_COMMON.PLL_CLKOUT_CFG[7] origin:063-gtp-common-conf 29_1563 +GTP_COMMON.GTPE2_COMMON.RSVD_ATTR0[0] origin:063-gtp-common-conf 28_1488 +GTP_COMMON.GTPE2_COMMON.RSVD_ATTR0[1] origin:063-gtp-common-conf 29_1488 +GTP_COMMON.GTPE2_COMMON.RSVD_ATTR0[2] origin:063-gtp-common-conf 28_1489 +GTP_COMMON.GTPE2_COMMON.RSVD_ATTR0[3] origin:063-gtp-common-conf 29_1489 +GTP_COMMON.GTPE2_COMMON.RSVD_ATTR0[4] origin:063-gtp-common-conf 28_1490 +GTP_COMMON.GTPE2_COMMON.RSVD_ATTR0[5] origin:063-gtp-common-conf 29_1490 +GTP_COMMON.GTPE2_COMMON.RSVD_ATTR0[6] origin:063-gtp-common-conf 28_1491 +GTP_COMMON.GTPE2_COMMON.RSVD_ATTR0[7] origin:063-gtp-common-conf 29_1491 +GTP_COMMON.GTPE2_COMMON.RSVD_ATTR0[8] origin:063-gtp-common-conf 28_1492 +GTP_COMMON.GTPE2_COMMON.RSVD_ATTR0[9] origin:063-gtp-common-conf 29_1492 +GTP_COMMON.GTPE2_COMMON.RSVD_ATTR0[10] origin:063-gtp-common-conf 28_1493 +GTP_COMMON.GTPE2_COMMON.RSVD_ATTR0[11] origin:063-gtp-common-conf 29_1493 +GTP_COMMON.GTPE2_COMMON.RSVD_ATTR0[12] origin:063-gtp-common-conf 28_1494 +GTP_COMMON.GTPE2_COMMON.RSVD_ATTR0[13] origin:063-gtp-common-conf 29_1494 +GTP_COMMON.GTPE2_COMMON.RSVD_ATTR0[14] origin:063-gtp-common-conf 28_1495 +GTP_COMMON.GTPE2_COMMON.RSVD_ATTR0[15] origin:063-gtp-common-conf 29_1495 +GTP_COMMON.GTPE2_COMMON.RSVD_ATTR1[0] origin:063-gtp-common-conf 28_1728 +GTP_COMMON.GTPE2_COMMON.RSVD_ATTR1[1] origin:063-gtp-common-conf 29_1728 +GTP_COMMON.GTPE2_COMMON.RSVD_ATTR1[2] origin:063-gtp-common-conf 28_1729 +GTP_COMMON.GTPE2_COMMON.RSVD_ATTR1[3] origin:063-gtp-common-conf 29_1729 +GTP_COMMON.GTPE2_COMMON.RSVD_ATTR1[4] origin:063-gtp-common-conf 28_1730 +GTP_COMMON.GTPE2_COMMON.RSVD_ATTR1[5] origin:063-gtp-common-conf 29_1730 +GTP_COMMON.GTPE2_COMMON.RSVD_ATTR1[6] origin:063-gtp-common-conf 28_1731 +GTP_COMMON.GTPE2_COMMON.RSVD_ATTR1[7] origin:063-gtp-common-conf 29_1731 +GTP_COMMON.GTPE2_COMMON.RSVD_ATTR1[8] origin:063-gtp-common-conf 28_1732 +GTP_COMMON.GTPE2_COMMON.RSVD_ATTR1[9] origin:063-gtp-common-conf 29_1732 +GTP_COMMON.GTPE2_COMMON.RSVD_ATTR1[10] origin:063-gtp-common-conf 28_1733 +GTP_COMMON.GTPE2_COMMON.RSVD_ATTR1[11] origin:063-gtp-common-conf 29_1733 +GTP_COMMON.GTPE2_COMMON.RSVD_ATTR1[12] origin:063-gtp-common-conf 28_1734 +GTP_COMMON.GTPE2_COMMON.RSVD_ATTR1[13] origin:063-gtp-common-conf 29_1734 +GTP_COMMON.GTPE2_COMMON.RSVD_ATTR1[14] origin:063-gtp-common-conf 28_1735 +GTP_COMMON.GTPE2_COMMON.RSVD_ATTR1[15] origin:063-gtp-common-conf 29_1735 +GTP_COMMON.GTPE2_COMMON.GTREFCLK0_USED origin:063-gtp-common-conf 28_1438 28_1806 +GTP_COMMON.GTPE2_COMMON.GTREFCLK1_USED origin:063-gtp-common-conf 29_1438 29_1806 +GTP_COMMON.GTPE2_COMMON.PLL0_CFG[0] origin:063-gtp-common-conf 28_1424 +GTP_COMMON.GTPE2_COMMON.PLL0_CFG[1] origin:063-gtp-common-conf 29_1424 +GTP_COMMON.GTPE2_COMMON.PLL0_CFG[2] origin:063-gtp-common-conf 28_1425 +GTP_COMMON.GTPE2_COMMON.PLL0_CFG[3] origin:063-gtp-common-conf 29_1425 +GTP_COMMON.GTPE2_COMMON.PLL0_CFG[4] origin:063-gtp-common-conf 28_1426 +GTP_COMMON.GTPE2_COMMON.PLL0_CFG[5] origin:063-gtp-common-conf 29_1426 +GTP_COMMON.GTPE2_COMMON.PLL0_CFG[6] origin:063-gtp-common-conf 28_1427 +GTP_COMMON.GTPE2_COMMON.PLL0_CFG[7] origin:063-gtp-common-conf 29_1427 +GTP_COMMON.GTPE2_COMMON.PLL0_CFG[8] origin:063-gtp-common-conf 28_1428 +GTP_COMMON.GTPE2_COMMON.PLL0_CFG[9] origin:063-gtp-common-conf 29_1428 +GTP_COMMON.GTPE2_COMMON.PLL0_CFG[10] origin:063-gtp-common-conf 28_1429 +GTP_COMMON.GTPE2_COMMON.PLL0_CFG[11] origin:063-gtp-common-conf 29_1429 +GTP_COMMON.GTPE2_COMMON.PLL0_CFG[12] origin:063-gtp-common-conf 28_1430 +GTP_COMMON.GTPE2_COMMON.PLL0_CFG[13] origin:063-gtp-common-conf 29_1430 +GTP_COMMON.GTPE2_COMMON.PLL0_CFG[14] origin:063-gtp-common-conf 28_1431 +GTP_COMMON.GTPE2_COMMON.PLL0_CFG[15] origin:063-gtp-common-conf 29_1431 +GTP_COMMON.GTPE2_COMMON.PLL0_CFG[16] origin:063-gtp-common-conf 28_1432 +GTP_COMMON.GTPE2_COMMON.PLL0_CFG[17] origin:063-gtp-common-conf 29_1432 +GTP_COMMON.GTPE2_COMMON.PLL0_CFG[18] origin:063-gtp-common-conf 28_1433 +GTP_COMMON.GTPE2_COMMON.PLL0_CFG[19] origin:063-gtp-common-conf 29_1433 +GTP_COMMON.GTPE2_COMMON.PLL0_CFG[20] origin:063-gtp-common-conf 28_1434 +GTP_COMMON.GTPE2_COMMON.PLL0_CFG[21] origin:063-gtp-common-conf 29_1434 +GTP_COMMON.GTPE2_COMMON.PLL0_CFG[22] origin:063-gtp-common-conf 28_1435 +GTP_COMMON.GTPE2_COMMON.PLL0_CFG[23] origin:063-gtp-common-conf 29_1435 +GTP_COMMON.GTPE2_COMMON.PLL0_CFG[24] origin:063-gtp-common-conf 28_1436 +GTP_COMMON.GTPE2_COMMON.PLL0_CFG[25] origin:063-gtp-common-conf 29_1436 +GTP_COMMON.GTPE2_COMMON.PLL0_CFG[26] origin:063-gtp-common-conf 28_1437 +GTP_COMMON.GTPE2_COMMON.PLL0_DMON_CFG[0] origin:063-gtp-common-conf 28_1528 +GTP_COMMON.GTPE2_COMMON.PLL0_FBDIV[0] origin:063-gtp-common-conf 28_1440 +GTP_COMMON.GTPE2_COMMON.PLL0_FBDIV[1] origin:063-gtp-common-conf 29_1440 +GTP_COMMON.GTPE2_COMMON.PLL0_FBDIV[4] origin:063-gtp-common-conf 28_1442 +GTP_COMMON.GTPE2_COMMON.PLL0_FBDIV_45[0] origin:063-gtp-common-conf 29_1443 +GTP_COMMON.GTPE2_COMMON.PLL0_INIT_CFG[0] origin:063-gtp-common-conf 28_1456 +GTP_COMMON.GTPE2_COMMON.PLL0_INIT_CFG[1] origin:063-gtp-common-conf 29_1456 +GTP_COMMON.GTPE2_COMMON.PLL0_INIT_CFG[2] origin:063-gtp-common-conf 28_1457 +GTP_COMMON.GTPE2_COMMON.PLL0_INIT_CFG[3] origin:063-gtp-common-conf 29_1457 +GTP_COMMON.GTPE2_COMMON.PLL0_INIT_CFG[4] origin:063-gtp-common-conf 28_1458 +GTP_COMMON.GTPE2_COMMON.PLL0_INIT_CFG[5] origin:063-gtp-common-conf 29_1458 +GTP_COMMON.GTPE2_COMMON.PLL0_INIT_CFG[6] origin:063-gtp-common-conf 28_1459 +GTP_COMMON.GTPE2_COMMON.PLL0_INIT_CFG[7] origin:063-gtp-common-conf 29_1459 +GTP_COMMON.GTPE2_COMMON.PLL0_INIT_CFG[8] origin:063-gtp-common-conf 28_1460 +GTP_COMMON.GTPE2_COMMON.PLL0_INIT_CFG[9] origin:063-gtp-common-conf 29_1460 +GTP_COMMON.GTPE2_COMMON.PLL0_INIT_CFG[10] origin:063-gtp-common-conf 28_1461 +GTP_COMMON.GTPE2_COMMON.PLL0_INIT_CFG[11] origin:063-gtp-common-conf 29_1461 +GTP_COMMON.GTPE2_COMMON.PLL0_INIT_CFG[12] origin:063-gtp-common-conf 28_1462 +GTP_COMMON.GTPE2_COMMON.PLL0_INIT_CFG[13] origin:063-gtp-common-conf 29_1462 +GTP_COMMON.GTPE2_COMMON.PLL0_INIT_CFG[14] origin:063-gtp-common-conf 28_1463 +GTP_COMMON.GTPE2_COMMON.PLL0_INIT_CFG[15] origin:063-gtp-common-conf 29_1463 +GTP_COMMON.GTPE2_COMMON.PLL0_INIT_CFG[16] origin:063-gtp-common-conf 28_1464 +GTP_COMMON.GTPE2_COMMON.PLL0_INIT_CFG[17] origin:063-gtp-common-conf 29_1464 +GTP_COMMON.GTPE2_COMMON.PLL0_INIT_CFG[18] origin:063-gtp-common-conf 28_1465 +GTP_COMMON.GTPE2_COMMON.PLL0_INIT_CFG[19] origin:063-gtp-common-conf 29_1465 +GTP_COMMON.GTPE2_COMMON.PLL0_INIT_CFG[20] origin:063-gtp-common-conf 28_1466 +GTP_COMMON.GTPE2_COMMON.PLL0_INIT_CFG[21] origin:063-gtp-common-conf 29_1466 +GTP_COMMON.GTPE2_COMMON.PLL0_INIT_CFG[22] origin:063-gtp-common-conf 28_1467 +GTP_COMMON.GTPE2_COMMON.PLL0_INIT_CFG[23] origin:063-gtp-common-conf 29_1467 +GTP_COMMON.GTPE2_COMMON.PLL0_LOCK_CFG[0] origin:063-gtp-common-conf 28_1448 +GTP_COMMON.GTPE2_COMMON.PLL0_LOCK_CFG[1] origin:063-gtp-common-conf 29_1448 +GTP_COMMON.GTPE2_COMMON.PLL0_LOCK_CFG[2] origin:063-gtp-common-conf 28_1449 +GTP_COMMON.GTPE2_COMMON.PLL0_LOCK_CFG[3] origin:063-gtp-common-conf 29_1449 +GTP_COMMON.GTPE2_COMMON.PLL0_LOCK_CFG[4] origin:063-gtp-common-conf 28_1450 +GTP_COMMON.GTPE2_COMMON.PLL0_LOCK_CFG[5] origin:063-gtp-common-conf 29_1450 +GTP_COMMON.GTPE2_COMMON.PLL0_LOCK_CFG[6] origin:063-gtp-common-conf 28_1451 +GTP_COMMON.GTPE2_COMMON.PLL0_LOCK_CFG[7] origin:063-gtp-common-conf 29_1451 +GTP_COMMON.GTPE2_COMMON.PLL0_LOCK_CFG[8] origin:063-gtp-common-conf 28_1452 +GTP_COMMON.GTPE2_COMMON.PLL0_REFCLK_DIV[4] origin:063-gtp-common-conf 29_1446 +GTP_COMMON.GTPE2_COMMON.PLL1_CFG[0] origin:063-gtp-common-conf 28_1792 +GTP_COMMON.GTPE2_COMMON.PLL1_CFG[1] origin:063-gtp-common-conf 29_1792 +GTP_COMMON.GTPE2_COMMON.PLL1_CFG[2] origin:063-gtp-common-conf 28_1793 +GTP_COMMON.GTPE2_COMMON.PLL1_CFG[3] origin:063-gtp-common-conf 29_1793 +GTP_COMMON.GTPE2_COMMON.PLL1_CFG[4] origin:063-gtp-common-conf 28_1794 +GTP_COMMON.GTPE2_COMMON.PLL1_CFG[5] origin:063-gtp-common-conf 29_1794 +GTP_COMMON.GTPE2_COMMON.PLL1_CFG[6] origin:063-gtp-common-conf 28_1795 +GTP_COMMON.GTPE2_COMMON.PLL1_CFG[7] origin:063-gtp-common-conf 29_1795 +GTP_COMMON.GTPE2_COMMON.PLL1_CFG[8] origin:063-gtp-common-conf 28_1796 +GTP_COMMON.GTPE2_COMMON.PLL1_CFG[9] origin:063-gtp-common-conf 29_1796 +GTP_COMMON.GTPE2_COMMON.PLL1_CFG[10] origin:063-gtp-common-conf 28_1797 +GTP_COMMON.GTPE2_COMMON.PLL1_CFG[11] origin:063-gtp-common-conf 29_1797 +GTP_COMMON.GTPE2_COMMON.PLL1_CFG[12] origin:063-gtp-common-conf 28_1798 +GTP_COMMON.GTPE2_COMMON.PLL1_CFG[13] origin:063-gtp-common-conf 29_1798 +GTP_COMMON.GTPE2_COMMON.PLL1_CFG[14] origin:063-gtp-common-conf 28_1799 +GTP_COMMON.GTPE2_COMMON.PLL1_CFG[15] origin:063-gtp-common-conf 29_1799 +GTP_COMMON.GTPE2_COMMON.PLL1_CFG[16] origin:063-gtp-common-conf 28_1800 +GTP_COMMON.GTPE2_COMMON.PLL1_CFG[17] origin:063-gtp-common-conf 29_1800 +GTP_COMMON.GTPE2_COMMON.PLL1_CFG[18] origin:063-gtp-common-conf 28_1801 +GTP_COMMON.GTPE2_COMMON.PLL1_CFG[19] origin:063-gtp-common-conf 29_1801 +GTP_COMMON.GTPE2_COMMON.PLL1_CFG[20] origin:063-gtp-common-conf 28_1802 +GTP_COMMON.GTPE2_COMMON.PLL1_CFG[21] origin:063-gtp-common-conf 29_1802 +GTP_COMMON.GTPE2_COMMON.PLL1_CFG[22] origin:063-gtp-common-conf 28_1803 +GTP_COMMON.GTPE2_COMMON.PLL1_CFG[23] origin:063-gtp-common-conf 29_1803 +GTP_COMMON.GTPE2_COMMON.PLL1_CFG[24] origin:063-gtp-common-conf 28_1804 +GTP_COMMON.GTPE2_COMMON.PLL1_CFG[25] origin:063-gtp-common-conf 29_1804 +GTP_COMMON.GTPE2_COMMON.PLL1_CFG[26] origin:063-gtp-common-conf 28_1805 +GTP_COMMON.GTPE2_COMMON.PLL1_DMON_CFG[0] origin:063-gtp-common-conf 29_1528 +GTP_COMMON.GTPE2_COMMON.PLL1_FBDIV[0] origin:063-gtp-common-conf 28_1784 +GTP_COMMON.GTPE2_COMMON.PLL1_FBDIV[1] origin:063-gtp-common-conf 29_1784 +GTP_COMMON.GTPE2_COMMON.PLL1_FBDIV[4] origin:063-gtp-common-conf 28_1786 +GTP_COMMON.GTPE2_COMMON.PLL1_FBDIV_45[0] origin:063-gtp-common-conf 29_1787 +GTP_COMMON.GTPE2_COMMON.PLL1_INIT_CFG[0] origin:063-gtp-common-conf 28_1760 +GTP_COMMON.GTPE2_COMMON.PLL1_INIT_CFG[1] origin:063-gtp-common-conf 29_1760 +GTP_COMMON.GTPE2_COMMON.PLL1_INIT_CFG[2] origin:063-gtp-common-conf 28_1761 +GTP_COMMON.GTPE2_COMMON.PLL1_INIT_CFG[3] origin:063-gtp-common-conf 29_1761 +GTP_COMMON.GTPE2_COMMON.PLL1_INIT_CFG[4] origin:063-gtp-common-conf 28_1762 +GTP_COMMON.GTPE2_COMMON.PLL1_INIT_CFG[5] origin:063-gtp-common-conf 29_1762 +GTP_COMMON.GTPE2_COMMON.PLL1_INIT_CFG[6] origin:063-gtp-common-conf 28_1763 +GTP_COMMON.GTPE2_COMMON.PLL1_INIT_CFG[7] origin:063-gtp-common-conf 29_1763 +GTP_COMMON.GTPE2_COMMON.PLL1_INIT_CFG[8] origin:063-gtp-common-conf 28_1764 +GTP_COMMON.GTPE2_COMMON.PLL1_INIT_CFG[9] origin:063-gtp-common-conf 29_1764 +GTP_COMMON.GTPE2_COMMON.PLL1_INIT_CFG[10] origin:063-gtp-common-conf 28_1765 +GTP_COMMON.GTPE2_COMMON.PLL1_INIT_CFG[11] origin:063-gtp-common-conf 29_1765 +GTP_COMMON.GTPE2_COMMON.PLL1_INIT_CFG[12] origin:063-gtp-common-conf 28_1766 +GTP_COMMON.GTPE2_COMMON.PLL1_INIT_CFG[13] origin:063-gtp-common-conf 29_1766 +GTP_COMMON.GTPE2_COMMON.PLL1_INIT_CFG[14] origin:063-gtp-common-conf 28_1767 +GTP_COMMON.GTPE2_COMMON.PLL1_INIT_CFG[15] origin:063-gtp-common-conf 29_1767 +GTP_COMMON.GTPE2_COMMON.PLL1_INIT_CFG[16] origin:063-gtp-common-conf 28_1768 +GTP_COMMON.GTPE2_COMMON.PLL1_INIT_CFG[17] origin:063-gtp-common-conf 29_1768 +GTP_COMMON.GTPE2_COMMON.PLL1_INIT_CFG[18] origin:063-gtp-common-conf 28_1769 +GTP_COMMON.GTPE2_COMMON.PLL1_INIT_CFG[19] origin:063-gtp-common-conf 29_1769 +GTP_COMMON.GTPE2_COMMON.PLL1_INIT_CFG[20] origin:063-gtp-common-conf 28_1770 +GTP_COMMON.GTPE2_COMMON.PLL1_INIT_CFG[21] origin:063-gtp-common-conf 29_1770 +GTP_COMMON.GTPE2_COMMON.PLL1_INIT_CFG[22] origin:063-gtp-common-conf 28_1771 +GTP_COMMON.GTPE2_COMMON.PLL1_INIT_CFG[23] origin:063-gtp-common-conf 29_1771 +GTP_COMMON.GTPE2_COMMON.PLL1_LOCK_CFG[0] origin:063-gtp-common-conf 28_1776 +GTP_COMMON.GTPE2_COMMON.PLL1_LOCK_CFG[1] origin:063-gtp-common-conf 29_1776 +GTP_COMMON.GTPE2_COMMON.PLL1_LOCK_CFG[2] origin:063-gtp-common-conf 28_1777 +GTP_COMMON.GTPE2_COMMON.PLL1_LOCK_CFG[3] origin:063-gtp-common-conf 29_1777 +GTP_COMMON.GTPE2_COMMON.PLL1_LOCK_CFG[4] origin:063-gtp-common-conf 28_1778 +GTP_COMMON.GTPE2_COMMON.PLL1_LOCK_CFG[5] origin:063-gtp-common-conf 29_1778 +GTP_COMMON.GTPE2_COMMON.PLL1_LOCK_CFG[6] origin:063-gtp-common-conf 28_1779 +GTP_COMMON.GTPE2_COMMON.PLL1_LOCK_CFG[7] origin:063-gtp-common-conf 29_1779 +GTP_COMMON.GTPE2_COMMON.PLL1_LOCK_CFG[8] origin:063-gtp-common-conf 28_1780 +GTP_COMMON.GTPE2_COMMON.PLL1_REFCLK_DIV[4] origin:063-gtp-common-conf 29_1790 diff --git a/artix7/segbits_gtp_common_mid_left.db b/artix7/segbits_gtp_common_mid_left.db index 6fcfe87..625760e 100644 --- a/artix7/segbits_gtp_common_mid_left.db +++ b/artix7/segbits_gtp_common_mid_left.db @@ -1,4 +1,3 @@ -GTP_COMMON_MID_LEFT.ENABLE_DRP 00_1613 01_1613 GTP_COMMON_MID_LEFT.HCLK_GTP_CK_IN0.HCLK_GTP_CK_MUX0 02_1614 03_1617 03_1622 GTP_COMMON_MID_LEFT.HCLK_GTP_CK_IN0.HCLK_GTP_CK_MUX1 02_1614 02_1622 03_1616 GTP_COMMON_MID_LEFT.HCLK_GTP_CK_IN0.IBUFDS_GTPE2_0_MGTCLKOUT_MUX 02_1615 03_1617 @@ -167,8 +166,6 @@ GTP_COMMON_MID_LEFT.HCLK_GTP_CK_IN13.GTPE2_COMMON_TXOUTCLK_MUX_0 06_1623 07_1617 GTP_COMMON_MID_LEFT.HCLK_GTP_CK_IN13.GTPE2_COMMON_TXOUTCLK_MUX_1 06_1620 07_1617 GTP_COMMON_MID_LEFT.HCLK_GTP_CK_IN13.GTPE2_COMMON_TXOUTCLK_MUX_2 06_1623 07_1616 GTP_COMMON_MID_LEFT.HCLK_GTP_CK_IN13.GTPE2_COMMON_TXOUTCLK_MUX_3 06_1620 07_1616 -GTP_COMMON_MID_LEFT.IBUFDS_GTE2.CLKCM_CFG[0] 01_1581 -GTP_COMMON_MID_LEFT.IBUFDS_GTE2.CLKCM_CFG[1] 00_1582 GTP_COMMON_MID_LEFT.IBUFDS_GTE2_Y0.CLKCM_CFG 00_1580 GTP_COMMON_MID_LEFT.IBUFDS_GTE2_Y0.CLKRCV_TRST 00_1576 GTP_COMMON_MID_LEFT.IBUFDS_GTE2_Y0.IN_USE 00_1578 @@ -177,103 +174,150 @@ GTP_COMMON_MID_LEFT.IBUFDS_GTE2_Y1.CLKRCV_TRST 01_1576 GTP_COMMON_MID_LEFT.IBUFDS_GTE2_Y1.IN_USE 00_1579 GTP_COMMON_MID_LEFT.IBUFDS_GTPE2_0_MGTCLKOUT_MUX.IBUFDS_GTPE2_0_MGTCLKOUT 07_1629 GTP_COMMON_MID_LEFT.IBUFDS_GTPE2_1_MGTCLKOUT_MUX.IBUFDS_GTPE2_1_MGTCLKOUT 06_1627 -GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[0] 00_1640 -GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[1] 01_1640 -GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[2] 00_1641 -GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[3] 01_1641 -GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[4] 00_1642 -GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[5] 01_1642 -GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[6] 00_1643 -GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[7] 01_1643 -GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[8] 00_1644 -GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[9] 01_1644 -GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[10] 00_1645 -GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[11] 01_1645 -GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[12] 00_1646 -GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[13] 01_1646 -GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[14] 00_1647 -GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[15] 01_1647 -GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[16] 00_1648 -GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[17] 01_1648 -GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[18] 00_1649 -GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[19] 01_1649 -GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[20] 00_1650 -GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[21] 01_1650 -GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[22] 00_1651 -GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[23] 01_1651 -GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[24] 00_1652 -GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[25] 01_1652 -GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[26] 00_1653 -GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[27] 01_1653 -GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[28] 00_1654 -GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[29] 01_1654 -GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[30] 00_1655 -GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[31] 01_1655 -GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[32] 00_1656 -GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[33] 01_1656 -GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[34] 00_1657 -GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[35] 01_1657 -GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[36] 00_1658 -GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[37] 01_1658 -GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[38] 00_1659 -GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[39] 01_1659 -GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[40] 00_1660 -GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[41] 01_1660 -GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[42] 00_1661 -GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[43] 01_1661 -GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[44] 00_1662 -GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[45] 01_1662 -GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[46] 00_1663 -GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[47] 01_1663 -GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[48] 00_1664 -GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[49] 01_1664 -GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[50] 00_1665 -GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[51] 01_1665 -GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[52] 00_1666 -GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[53] 01_1666 -GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[54] 00_1667 -GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[55] 01_1667 -GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[56] 00_1668 -GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[57] 01_1668 -GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[58] 00_1669 -GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[59] 01_1669 -GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[60] 00_1670 -GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[61] 01_1670 -GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[62] 00_1671 -GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[63] 01_1671 -GTP_COMMON_MID_LEFT.GTPE2.BOTH_GTREFCLK_USED 01_1439 01_1807 -GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[0] 00_1544 -GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[1] 01_1544 -GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[2] 00_1545 -GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[3] 01_1545 -GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[4] 00_1546 -GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[5] 01_1546 -GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[6] 00_1547 -GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[7] 01_1547 -GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[8] 00_1548 -GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[9] 01_1548 -GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[10] 00_1549 -GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[11] 01_1549 -GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[12] 00_1550 -GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[13] 01_1550 -GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[14] 00_1551 -GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[15] 01_1551 -GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[16] 00_1552 -GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[17] 01_1552 -GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[18] 00_1553 -GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[19] 01_1553 -GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[20] 00_1554 -GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[21] 01_1554 -GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[22] 00_1555 -GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[23] 01_1555 -GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[24] 00_1556 -GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[25] 01_1556 -GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[26] 00_1557 -GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[27] 01_1557 -GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[28] 00_1558 -GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[29] 01_1558 -GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[30] 00_1559 -GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[31] 01_1559 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[0] 00_1640 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[1] 01_1640 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[2] 00_1641 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[3] 01_1641 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[4] 00_1642 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[5] 01_1642 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[6] 00_1643 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[7] 01_1643 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[8] 00_1644 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[9] 01_1644 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[10] 00_1645 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[11] 01_1645 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[12] 00_1646 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[13] 01_1646 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[14] 00_1647 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[15] 01_1647 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[16] 00_1648 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[17] 01_1648 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[18] 00_1649 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[19] 01_1649 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[20] 00_1650 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[21] 01_1650 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[22] 00_1651 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[23] 01_1651 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[24] 00_1652 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[25] 01_1652 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[26] 00_1653 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[27] 01_1653 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[28] 00_1654 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[29] 01_1654 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[30] 00_1655 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[31] 01_1655 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[32] 00_1656 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[33] 01_1656 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[34] 00_1657 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[35] 01_1657 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[36] 00_1658 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[37] 01_1658 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[38] 00_1659 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[39] 01_1659 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[40] 00_1660 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[41] 01_1660 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[42] 00_1661 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[43] 01_1661 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[44] 00_1662 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[45] 01_1662 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[46] 00_1663 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[47] 01_1663 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[48] 00_1664 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[49] 01_1664 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[50] 00_1665 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[51] 01_1665 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[52] 00_1666 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[53] 01_1666 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[54] 00_1667 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[55] 01_1667 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[56] 00_1668 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[57] 01_1668 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[58] 00_1669 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[59] 01_1669 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[60] 00_1670 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[61] 01_1670 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[62] 00_1671 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[63] 01_1671 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.BOTH_GTREFCLK_USED 01_1439 01_1807 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.COMMON_CFG[0] 00_1544 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.COMMON_CFG[1] 01_1544 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.COMMON_CFG[2] 00_1545 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.COMMON_CFG[3] 01_1545 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.COMMON_CFG[4] 00_1546 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.COMMON_CFG[5] 01_1546 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.COMMON_CFG[6] 00_1547 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.COMMON_CFG[7] 01_1547 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.COMMON_CFG[8] 00_1548 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.COMMON_CFG[9] 01_1548 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.COMMON_CFG[10] 00_1549 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.COMMON_CFG[11] 01_1549 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.COMMON_CFG[12] 00_1550 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.COMMON_CFG[13] 01_1550 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.COMMON_CFG[14] 00_1551 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.COMMON_CFG[15] 01_1551 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.COMMON_CFG[16] 00_1552 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.COMMON_CFG[17] 01_1552 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.COMMON_CFG[18] 00_1553 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.COMMON_CFG[19] 01_1553 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.COMMON_CFG[20] 00_1554 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.COMMON_CFG[21] 01_1554 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.COMMON_CFG[22] 00_1555 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.COMMON_CFG[23] 01_1555 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.COMMON_CFG[24] 00_1556 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.COMMON_CFG[25] 01_1556 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.COMMON_CFG[26] 00_1557 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.COMMON_CFG[27] 01_1557 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.COMMON_CFG[28] 00_1558 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.COMMON_CFG[29] 01_1558 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.COMMON_CFG[30] 00_1559 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.COMMON_CFG[31] 01_1559 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.ENABLE_DRP 00_1613 01_1613 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.IBUFDS_GTE2.CLKSWING_CFG[0] 01_1581 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.IBUFDS_GTE2.CLKSWING_CFG[1] 00_1582 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.IN_USE 00_1584 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.INV_DRPCLK 00_1516 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.INV_PLL0LOCKDETCLK 01_1512 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.INV_PLL1LOCKDETCLK 00_1512 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL_CLKOUT_CFG[0] 00_1560 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL_CLKOUT_CFG[1] 01_1560 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL_CLKOUT_CFG[2] 00_1561 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL_CLKOUT_CFG[3] 01_1561 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL_CLKOUT_CFG[4] 00_1562 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL_CLKOUT_CFG[5] 01_1562 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL_CLKOUT_CFG[6] 00_1563 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL_CLKOUT_CFG[7] 01_1563 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.RSVD_ATTR0[0] 00_1488 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.RSVD_ATTR0[1] 01_1488 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.RSVD_ATTR0[2] 00_1489 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.RSVD_ATTR0[3] 01_1489 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.RSVD_ATTR0[4] 00_1490 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.RSVD_ATTR0[5] 01_1490 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.RSVD_ATTR0[6] 00_1491 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.RSVD_ATTR0[7] 01_1491 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.RSVD_ATTR0[8] 00_1492 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.RSVD_ATTR0[9] 01_1492 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.RSVD_ATTR0[10] 00_1493 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.RSVD_ATTR0[11] 01_1493 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.RSVD_ATTR0[12] 00_1494 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.RSVD_ATTR0[13] 01_1494 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.RSVD_ATTR0[14] 00_1495 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.RSVD_ATTR0[15] 01_1495 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.RSVD_ATTR1[0] 00_1728 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.RSVD_ATTR1[1] 01_1728 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.RSVD_ATTR1[2] 00_1729 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.RSVD_ATTR1[3] 01_1729 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.RSVD_ATTR1[4] 00_1730 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.RSVD_ATTR1[5] 01_1730 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.RSVD_ATTR1[6] 00_1731 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.RSVD_ATTR1[7] 01_1731 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.RSVD_ATTR1[8] 00_1732 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.RSVD_ATTR1[9] 01_1732 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.RSVD_ATTR1[10] 00_1733 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.RSVD_ATTR1[11] 01_1733 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.RSVD_ATTR1[12] 00_1734 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.RSVD_ATTR1[13] 01_1734 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.RSVD_ATTR1[14] 00_1735 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.RSVD_ATTR1[15] 01_1735 GTP_COMMON_MID_LEFT.GTPE2_COMMON_RXOUTCLK_MUX_0.GTPE2_COMMON_RXOUTCLK_0 06_1628 GTP_COMMON_MID_LEFT.GTPE2_COMMON_RXOUTCLK_MUX_1.GTPE2_COMMON_RXOUTCLK_1 07_1627 GTP_COMMON_MID_LEFT.GTPE2_COMMON_RXOUTCLK_MUX_2.GTPE2_COMMON_RXOUTCLK_2 07_1630 @@ -282,181 +326,137 @@ GTP_COMMON_MID_LEFT.GTPE2_COMMON_TXOUTCLK_MUX_0.GTPE2_COMMON_TXOUTCLK_0 06_1629 GTP_COMMON_MID_LEFT.GTPE2_COMMON_TXOUTCLK_MUX_1.GTPE2_COMMON_TXOUTCLK_1 07_1628 GTP_COMMON_MID_LEFT.GTPE2_COMMON_TXOUTCLK_MUX_2.GTPE2_COMMON_TXOUTCLK_2 07_1631 GTP_COMMON_MID_LEFT.GTPE2_COMMON_TXOUTCLK_MUX_3.GTPE2_COMMON_TXOUTCLK_3 06_1631 -GTP_COMMON_MID_LEFT.GTPE2.IN_USE 00_1584 -GTP_COMMON_MID_LEFT.GTPE2.PLL_CLKOUT_CFG[0] 00_1560 -GTP_COMMON_MID_LEFT.GTPE2.PLL_CLKOUT_CFG[1] 01_1560 -GTP_COMMON_MID_LEFT.GTPE2.PLL_CLKOUT_CFG[2] 00_1561 -GTP_COMMON_MID_LEFT.GTPE2.PLL_CLKOUT_CFG[3] 01_1561 -GTP_COMMON_MID_LEFT.GTPE2.PLL_CLKOUT_CFG[4] 00_1562 -GTP_COMMON_MID_LEFT.GTPE2.PLL_CLKOUT_CFG[5] 01_1562 -GTP_COMMON_MID_LEFT.GTPE2.PLL_CLKOUT_CFG[6] 00_1563 -GTP_COMMON_MID_LEFT.GTPE2.PLL_CLKOUT_CFG[7] 01_1563 -GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR0[0] 00_1488 -GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR0[1] 01_1488 -GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR0[2] 00_1489 -GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR0[3] 01_1489 -GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR0[4] 00_1490 -GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR0[5] 01_1490 -GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR0[6] 00_1491 -GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR0[7] 01_1491 -GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR0[8] 00_1492 -GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR0[9] 01_1492 -GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR0[10] 00_1493 -GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR0[11] 01_1493 -GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR0[12] 00_1494 -GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR0[13] 01_1494 -GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR0[14] 00_1495 -GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR0[15] 01_1495 -GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR1[0] 00_1728 -GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR1[1] 01_1728 -GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR1[2] 00_1729 -GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR1[3] 01_1729 -GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR1[4] 00_1730 -GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR1[5] 01_1730 -GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR1[6] 00_1731 -GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR1[7] 01_1731 -GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR1[8] 00_1732 -GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR1[9] 01_1732 -GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR1[10] 00_1733 -GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR1[11] 01_1733 -GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR1[12] 00_1734 -GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR1[13] 01_1734 -GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR1[14] 00_1735 -GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR1[15] 01_1735 -GTP_COMMON_MID_LEFT.GTPE2.ZINV_DRPCLK 00_1516 -GTP_COMMON_MID_LEFT.GTPE2.ZINV_PLL0LOCKDETCLK 01_1512 -GTP_COMMON_MID_LEFT.GTPE2.ZINV_PLL1LOCKDETCLK 00_1512 -GTP_COMMON_MID_LEFT.GTPE2.GTREFCLK0_USED 00_1438 00_1806 -GTP_COMMON_MID_LEFT.GTPE2.GTREFCLK1_USED 01_1438 01_1806 -GTP_COMMON_MID_LEFT.GTPE2.PLL0_CFG[0] 00_1424 -GTP_COMMON_MID_LEFT.GTPE2.PLL0_CFG[1] 01_1424 -GTP_COMMON_MID_LEFT.GTPE2.PLL0_CFG[2] 00_1425 -GTP_COMMON_MID_LEFT.GTPE2.PLL0_CFG[3] 01_1425 -GTP_COMMON_MID_LEFT.GTPE2.PLL0_CFG[4] 00_1426 -GTP_COMMON_MID_LEFT.GTPE2.PLL0_CFG[5] 01_1426 -GTP_COMMON_MID_LEFT.GTPE2.PLL0_CFG[6] 00_1427 -GTP_COMMON_MID_LEFT.GTPE2.PLL0_CFG[7] 01_1427 -GTP_COMMON_MID_LEFT.GTPE2.PLL0_CFG[8] 00_1428 -GTP_COMMON_MID_LEFT.GTPE2.PLL0_CFG[9] 01_1428 -GTP_COMMON_MID_LEFT.GTPE2.PLL0_CFG[10] 00_1429 -GTP_COMMON_MID_LEFT.GTPE2.PLL0_CFG[11] 01_1429 -GTP_COMMON_MID_LEFT.GTPE2.PLL0_CFG[12] 00_1430 -GTP_COMMON_MID_LEFT.GTPE2.PLL0_CFG[13] 01_1430 -GTP_COMMON_MID_LEFT.GTPE2.PLL0_CFG[14] 00_1431 -GTP_COMMON_MID_LEFT.GTPE2.PLL0_CFG[15] 01_1431 -GTP_COMMON_MID_LEFT.GTPE2.PLL0_CFG[16] 00_1432 -GTP_COMMON_MID_LEFT.GTPE2.PLL0_CFG[17] 01_1432 -GTP_COMMON_MID_LEFT.GTPE2.PLL0_CFG[18] 00_1433 -GTP_COMMON_MID_LEFT.GTPE2.PLL0_CFG[19] 01_1433 -GTP_COMMON_MID_LEFT.GTPE2.PLL0_CFG[20] 00_1434 -GTP_COMMON_MID_LEFT.GTPE2.PLL0_CFG[21] 01_1434 -GTP_COMMON_MID_LEFT.GTPE2.PLL0_CFG[22] 00_1435 -GTP_COMMON_MID_LEFT.GTPE2.PLL0_CFG[23] 01_1435 -GTP_COMMON_MID_LEFT.GTPE2.PLL0_CFG[24] 00_1436 -GTP_COMMON_MID_LEFT.GTPE2.PLL0_CFG[25] 01_1436 -GTP_COMMON_MID_LEFT.GTPE2.PLL0_CFG[26] 00_1437 -GTP_COMMON_MID_LEFT.GTPE2.PLL0_DMON_CFG[0] 00_1528 -GTP_COMMON_MID_LEFT.GTPE2.PLL0_FBDIV[0] 00_1440 -GTP_COMMON_MID_LEFT.GTPE2.PLL0_FBDIV[1] 01_1440 -GTP_COMMON_MID_LEFT.GTPE2.PLL0_FBDIV[4] 00_1442 -GTP_COMMON_MID_LEFT.GTPE2.PLL0_FBDIV_45[0] 01_1443 -GTP_COMMON_MID_LEFT.GTPE2.PLL0_INIT_CFG[0] 00_1456 -GTP_COMMON_MID_LEFT.GTPE2.PLL0_INIT_CFG[1] 01_1456 -GTP_COMMON_MID_LEFT.GTPE2.PLL0_INIT_CFG[2] 00_1457 -GTP_COMMON_MID_LEFT.GTPE2.PLL0_INIT_CFG[3] 01_1457 -GTP_COMMON_MID_LEFT.GTPE2.PLL0_INIT_CFG[4] 00_1458 -GTP_COMMON_MID_LEFT.GTPE2.PLL0_INIT_CFG[5] 01_1458 -GTP_COMMON_MID_LEFT.GTPE2.PLL0_INIT_CFG[6] 00_1459 -GTP_COMMON_MID_LEFT.GTPE2.PLL0_INIT_CFG[7] 01_1459 -GTP_COMMON_MID_LEFT.GTPE2.PLL0_INIT_CFG[8] 00_1460 -GTP_COMMON_MID_LEFT.GTPE2.PLL0_INIT_CFG[9] 01_1460 -GTP_COMMON_MID_LEFT.GTPE2.PLL0_INIT_CFG[10] 00_1461 -GTP_COMMON_MID_LEFT.GTPE2.PLL0_INIT_CFG[11] 01_1461 -GTP_COMMON_MID_LEFT.GTPE2.PLL0_INIT_CFG[12] 00_1462 -GTP_COMMON_MID_LEFT.GTPE2.PLL0_INIT_CFG[13] 01_1462 -GTP_COMMON_MID_LEFT.GTPE2.PLL0_INIT_CFG[14] 00_1463 -GTP_COMMON_MID_LEFT.GTPE2.PLL0_INIT_CFG[15] 01_1463 -GTP_COMMON_MID_LEFT.GTPE2.PLL0_INIT_CFG[16] 00_1464 -GTP_COMMON_MID_LEFT.GTPE2.PLL0_INIT_CFG[17] 01_1464 -GTP_COMMON_MID_LEFT.GTPE2.PLL0_INIT_CFG[18] 00_1465 -GTP_COMMON_MID_LEFT.GTPE2.PLL0_INIT_CFG[19] 01_1465 -GTP_COMMON_MID_LEFT.GTPE2.PLL0_INIT_CFG[20] 00_1466 -GTP_COMMON_MID_LEFT.GTPE2.PLL0_INIT_CFG[21] 01_1466 -GTP_COMMON_MID_LEFT.GTPE2.PLL0_INIT_CFG[22] 00_1467 -GTP_COMMON_MID_LEFT.GTPE2.PLL0_INIT_CFG[23] 01_1467 -GTP_COMMON_MID_LEFT.GTPE2.PLL0_LOCK_CFG[0] 00_1448 -GTP_COMMON_MID_LEFT.GTPE2.PLL0_LOCK_CFG[1] 01_1448 -GTP_COMMON_MID_LEFT.GTPE2.PLL0_LOCK_CFG[2] 00_1449 -GTP_COMMON_MID_LEFT.GTPE2.PLL0_LOCK_CFG[3] 01_1449 -GTP_COMMON_MID_LEFT.GTPE2.PLL0_LOCK_CFG[4] 00_1450 -GTP_COMMON_MID_LEFT.GTPE2.PLL0_LOCK_CFG[5] 01_1450 -GTP_COMMON_MID_LEFT.GTPE2.PLL0_LOCK_CFG[6] 00_1451 -GTP_COMMON_MID_LEFT.GTPE2.PLL0_LOCK_CFG[7] 01_1451 -GTP_COMMON_MID_LEFT.GTPE2.PLL0_LOCK_CFG[8] 00_1452 -GTP_COMMON_MID_LEFT.GTPE2.PLL0_REFCLK_DIV[4] 01_1446 -GTP_COMMON_MID_LEFT.GTPE2.PLL1_CFG[0] 00_1792 -GTP_COMMON_MID_LEFT.GTPE2.PLL1_CFG[1] 01_1792 -GTP_COMMON_MID_LEFT.GTPE2.PLL1_CFG[2] 00_1793 -GTP_COMMON_MID_LEFT.GTPE2.PLL1_CFG[3] 01_1793 -GTP_COMMON_MID_LEFT.GTPE2.PLL1_CFG[4] 00_1794 -GTP_COMMON_MID_LEFT.GTPE2.PLL1_CFG[5] 01_1794 -GTP_COMMON_MID_LEFT.GTPE2.PLL1_CFG[6] 00_1795 -GTP_COMMON_MID_LEFT.GTPE2.PLL1_CFG[7] 01_1795 -GTP_COMMON_MID_LEFT.GTPE2.PLL1_CFG[8] 00_1796 -GTP_COMMON_MID_LEFT.GTPE2.PLL1_CFG[9] 01_1796 -GTP_COMMON_MID_LEFT.GTPE2.PLL1_CFG[10] 00_1797 -GTP_COMMON_MID_LEFT.GTPE2.PLL1_CFG[11] 01_1797 -GTP_COMMON_MID_LEFT.GTPE2.PLL1_CFG[12] 00_1798 -GTP_COMMON_MID_LEFT.GTPE2.PLL1_CFG[13] 01_1798 -GTP_COMMON_MID_LEFT.GTPE2.PLL1_CFG[14] 00_1799 -GTP_COMMON_MID_LEFT.GTPE2.PLL1_CFG[15] 01_1799 -GTP_COMMON_MID_LEFT.GTPE2.PLL1_CFG[16] 00_1800 -GTP_COMMON_MID_LEFT.GTPE2.PLL1_CFG[17] 01_1800 -GTP_COMMON_MID_LEFT.GTPE2.PLL1_CFG[18] 00_1801 -GTP_COMMON_MID_LEFT.GTPE2.PLL1_CFG[19] 01_1801 -GTP_COMMON_MID_LEFT.GTPE2.PLL1_CFG[20] 00_1802 -GTP_COMMON_MID_LEFT.GTPE2.PLL1_CFG[21] 01_1802 -GTP_COMMON_MID_LEFT.GTPE2.PLL1_CFG[22] 00_1803 -GTP_COMMON_MID_LEFT.GTPE2.PLL1_CFG[23] 01_1803 -GTP_COMMON_MID_LEFT.GTPE2.PLL1_CFG[24] 00_1804 -GTP_COMMON_MID_LEFT.GTPE2.PLL1_CFG[25] 01_1804 -GTP_COMMON_MID_LEFT.GTPE2.PLL1_CFG[26] 00_1805 -GTP_COMMON_MID_LEFT.GTPE2.PLL1_DMON_CFG[0] 01_1528 -GTP_COMMON_MID_LEFT.GTPE2.PLL1_FBDIV[0] 00_1784 -GTP_COMMON_MID_LEFT.GTPE2.PLL1_FBDIV[1] 01_1784 -GTP_COMMON_MID_LEFT.GTPE2.PLL1_FBDIV[4] 00_1786 -GTP_COMMON_MID_LEFT.GTPE2.PLL1_FBDIV_45[0] 01_1787 -GTP_COMMON_MID_LEFT.GTPE2.PLL1_INIT_CFG[0] 00_1760 -GTP_COMMON_MID_LEFT.GTPE2.PLL1_INIT_CFG[1] 01_1760 -GTP_COMMON_MID_LEFT.GTPE2.PLL1_INIT_CFG[2] 00_1761 -GTP_COMMON_MID_LEFT.GTPE2.PLL1_INIT_CFG[3] 01_1761 -GTP_COMMON_MID_LEFT.GTPE2.PLL1_INIT_CFG[4] 00_1762 -GTP_COMMON_MID_LEFT.GTPE2.PLL1_INIT_CFG[5] 01_1762 -GTP_COMMON_MID_LEFT.GTPE2.PLL1_INIT_CFG[6] 00_1763 -GTP_COMMON_MID_LEFT.GTPE2.PLL1_INIT_CFG[7] 01_1763 -GTP_COMMON_MID_LEFT.GTPE2.PLL1_INIT_CFG[8] 00_1764 -GTP_COMMON_MID_LEFT.GTPE2.PLL1_INIT_CFG[9] 01_1764 -GTP_COMMON_MID_LEFT.GTPE2.PLL1_INIT_CFG[10] 00_1765 -GTP_COMMON_MID_LEFT.GTPE2.PLL1_INIT_CFG[11] 01_1765 -GTP_COMMON_MID_LEFT.GTPE2.PLL1_INIT_CFG[12] 00_1766 -GTP_COMMON_MID_LEFT.GTPE2.PLL1_INIT_CFG[13] 01_1766 -GTP_COMMON_MID_LEFT.GTPE2.PLL1_INIT_CFG[14] 00_1767 -GTP_COMMON_MID_LEFT.GTPE2.PLL1_INIT_CFG[15] 01_1767 -GTP_COMMON_MID_LEFT.GTPE2.PLL1_INIT_CFG[16] 00_1768 -GTP_COMMON_MID_LEFT.GTPE2.PLL1_INIT_CFG[17] 01_1768 -GTP_COMMON_MID_LEFT.GTPE2.PLL1_INIT_CFG[18] 00_1769 -GTP_COMMON_MID_LEFT.GTPE2.PLL1_INIT_CFG[19] 01_1769 -GTP_COMMON_MID_LEFT.GTPE2.PLL1_INIT_CFG[20] 00_1770 -GTP_COMMON_MID_LEFT.GTPE2.PLL1_INIT_CFG[21] 01_1770 -GTP_COMMON_MID_LEFT.GTPE2.PLL1_INIT_CFG[22] 00_1771 -GTP_COMMON_MID_LEFT.GTPE2.PLL1_INIT_CFG[23] 01_1771 -GTP_COMMON_MID_LEFT.GTPE2.PLL1_LOCK_CFG[0] 00_1776 -GTP_COMMON_MID_LEFT.GTPE2.PLL1_LOCK_CFG[1] 01_1776 -GTP_COMMON_MID_LEFT.GTPE2.PLL1_LOCK_CFG[2] 00_1777 -GTP_COMMON_MID_LEFT.GTPE2.PLL1_LOCK_CFG[3] 01_1777 -GTP_COMMON_MID_LEFT.GTPE2.PLL1_LOCK_CFG[4] 00_1778 -GTP_COMMON_MID_LEFT.GTPE2.PLL1_LOCK_CFG[5] 01_1778 -GTP_COMMON_MID_LEFT.GTPE2.PLL1_LOCK_CFG[6] 00_1779 -GTP_COMMON_MID_LEFT.GTPE2.PLL1_LOCK_CFG[7] 01_1779 -GTP_COMMON_MID_LEFT.GTPE2.PLL1_LOCK_CFG[8] 00_1780 -GTP_COMMON_MID_LEFT.GTPE2.PLL1_REFCLK_DIV[4] 01_1790 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.GTREFCLK0_USED 00_1438 00_1806 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.GTREFCLK1_USED 01_1438 01_1806 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_CFG[0] 00_1424 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_CFG[1] 01_1424 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_CFG[2] 00_1425 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_CFG[3] 01_1425 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_CFG[4] 00_1426 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_CFG[5] 01_1426 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_CFG[6] 00_1427 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_CFG[7] 01_1427 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_CFG[8] 00_1428 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_CFG[9] 01_1428 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_CFG[10] 00_1429 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_CFG[11] 01_1429 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_CFG[12] 00_1430 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_CFG[13] 01_1430 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_CFG[14] 00_1431 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_CFG[15] 01_1431 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_CFG[16] 00_1432 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_CFG[17] 01_1432 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_CFG[18] 00_1433 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_CFG[19] 01_1433 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_CFG[20] 00_1434 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_CFG[21] 01_1434 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_CFG[22] 00_1435 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_CFG[23] 01_1435 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_CFG[24] 00_1436 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_CFG[25] 01_1436 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_CFG[26] 00_1437 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_DMON_CFG[0] 00_1528 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_FBDIV[0] 00_1440 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_FBDIV[1] 01_1440 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_FBDIV[4] 00_1442 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_FBDIV_45[0] 01_1443 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_INIT_CFG[0] 00_1456 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_INIT_CFG[1] 01_1456 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_INIT_CFG[2] 00_1457 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_INIT_CFG[3] 01_1457 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_INIT_CFG[4] 00_1458 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_INIT_CFG[5] 01_1458 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_INIT_CFG[6] 00_1459 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_INIT_CFG[7] 01_1459 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_INIT_CFG[8] 00_1460 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_INIT_CFG[9] 01_1460 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_INIT_CFG[10] 00_1461 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_INIT_CFG[11] 01_1461 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_INIT_CFG[12] 00_1462 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_INIT_CFG[13] 01_1462 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_INIT_CFG[14] 00_1463 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_INIT_CFG[15] 01_1463 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_INIT_CFG[16] 00_1464 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_INIT_CFG[17] 01_1464 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_INIT_CFG[18] 00_1465 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_INIT_CFG[19] 01_1465 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_INIT_CFG[20] 00_1466 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_INIT_CFG[21] 01_1466 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_INIT_CFG[22] 00_1467 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_INIT_CFG[23] 01_1467 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_LOCK_CFG[0] 00_1448 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_LOCK_CFG[1] 01_1448 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_LOCK_CFG[2] 00_1449 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_LOCK_CFG[3] 01_1449 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_LOCK_CFG[4] 00_1450 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_LOCK_CFG[5] 01_1450 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_LOCK_CFG[6] 00_1451 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_LOCK_CFG[7] 01_1451 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_LOCK_CFG[8] 00_1452 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_REFCLK_DIV[4] 01_1446 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_CFG[0] 00_1792 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_CFG[1] 01_1792 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_CFG[2] 00_1793 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_CFG[3] 01_1793 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_CFG[4] 00_1794 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_CFG[5] 01_1794 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_CFG[6] 00_1795 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_CFG[7] 01_1795 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_CFG[8] 00_1796 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_CFG[9] 01_1796 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_CFG[10] 00_1797 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_CFG[11] 01_1797 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_CFG[12] 00_1798 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_CFG[13] 01_1798 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_CFG[14] 00_1799 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_CFG[15] 01_1799 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_CFG[16] 00_1800 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_CFG[17] 01_1800 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_CFG[18] 00_1801 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_CFG[19] 01_1801 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_CFG[20] 00_1802 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_CFG[21] 01_1802 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_CFG[22] 00_1803 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_CFG[23] 01_1803 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_CFG[24] 00_1804 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_CFG[25] 01_1804 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_CFG[26] 00_1805 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_DMON_CFG[0] 01_1528 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_FBDIV[0] 00_1784 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_FBDIV[1] 01_1784 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_FBDIV[4] 00_1786 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_FBDIV_45[0] 01_1787 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_INIT_CFG[0] 00_1760 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_INIT_CFG[1] 01_1760 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_INIT_CFG[2] 00_1761 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_INIT_CFG[3] 01_1761 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_INIT_CFG[4] 00_1762 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_INIT_CFG[5] 01_1762 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_INIT_CFG[6] 00_1763 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_INIT_CFG[7] 01_1763 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_INIT_CFG[8] 00_1764 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_INIT_CFG[9] 01_1764 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_INIT_CFG[10] 00_1765 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_INIT_CFG[11] 01_1765 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_INIT_CFG[12] 00_1766 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_INIT_CFG[13] 01_1766 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_INIT_CFG[14] 00_1767 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_INIT_CFG[15] 01_1767 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_INIT_CFG[16] 00_1768 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_INIT_CFG[17] 01_1768 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_INIT_CFG[18] 00_1769 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_INIT_CFG[19] 01_1769 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_INIT_CFG[20] 00_1770 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_INIT_CFG[21] 01_1770 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_INIT_CFG[22] 00_1771 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_INIT_CFG[23] 01_1771 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_LOCK_CFG[0] 00_1776 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_LOCK_CFG[1] 01_1776 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_LOCK_CFG[2] 00_1777 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_LOCK_CFG[3] 01_1777 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_LOCK_CFG[4] 00_1778 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_LOCK_CFG[5] 01_1778 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_LOCK_CFG[6] 00_1779 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_LOCK_CFG[7] 01_1779 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_LOCK_CFG[8] 00_1780 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_REFCLK_DIV[4] 01_1790 diff --git a/artix7/segbits_gtp_common_mid_left.origin_info.db b/artix7/segbits_gtp_common_mid_left.origin_info.db index ed63878..b46ce75 100644 --- a/artix7/segbits_gtp_common_mid_left.origin_info.db +++ b/artix7/segbits_gtp_common_mid_left.origin_info.db @@ -1,4 +1,3 @@ -GTP_COMMON_MID_LEFT.ENABLE_DRP origin:063-gtp-common-conf 00_1613 01_1613 GTP_COMMON_MID_LEFT.HCLK_GTP_CK_IN0.HCLK_GTP_CK_MUX0 origin:065b-gtp-common-pips 02_1614 03_1617 03_1622 GTP_COMMON_MID_LEFT.HCLK_GTP_CK_IN0.HCLK_GTP_CK_MUX1 origin:065b-gtp-common-pips 02_1614 02_1622 03_1616 GTP_COMMON_MID_LEFT.HCLK_GTP_CK_IN0.IBUFDS_GTPE2_0_MGTCLKOUT_MUX origin:065-gtp-common-pips 02_1615 03_1617 @@ -167,8 +166,6 @@ GTP_COMMON_MID_LEFT.HCLK_GTP_CK_IN13.GTPE2_COMMON_TXOUTCLK_MUX_0 origin:065-gtp- GTP_COMMON_MID_LEFT.HCLK_GTP_CK_IN13.GTPE2_COMMON_TXOUTCLK_MUX_1 origin:065-gtp-common-pips 06_1620 07_1617 GTP_COMMON_MID_LEFT.HCLK_GTP_CK_IN13.GTPE2_COMMON_TXOUTCLK_MUX_2 origin:065-gtp-common-pips 06_1623 07_1616 GTP_COMMON_MID_LEFT.HCLK_GTP_CK_IN13.GTPE2_COMMON_TXOUTCLK_MUX_3 origin:065-gtp-common-pips 06_1620 07_1616 -GTP_COMMON_MID_LEFT.IBUFDS_GTE2.CLKCM_CFG[0] origin:063-gtp-common-conf 01_1581 -GTP_COMMON_MID_LEFT.IBUFDS_GTE2.CLKCM_CFG[1] origin:063-gtp-common-conf 00_1582 GTP_COMMON_MID_LEFT.IBUFDS_GTE2_Y0.CLKCM_CFG origin:063-gtp-common-conf 00_1580 GTP_COMMON_MID_LEFT.IBUFDS_GTE2_Y0.CLKRCV_TRST origin:063-gtp-common-conf 00_1576 GTP_COMMON_MID_LEFT.IBUFDS_GTE2_Y0.IN_USE origin:063-gtp-common-conf 00_1578 @@ -177,103 +174,150 @@ GTP_COMMON_MID_LEFT.IBUFDS_GTE2_Y1.CLKRCV_TRST origin:063-gtp-common-conf 01_157 GTP_COMMON_MID_LEFT.IBUFDS_GTE2_Y1.IN_USE origin:063-gtp-common-conf 00_1579 GTP_COMMON_MID_LEFT.IBUFDS_GTPE2_0_MGTCLKOUT_MUX.IBUFDS_GTPE2_0_MGTCLKOUT origin:065-gtp-common-pips 07_1629 GTP_COMMON_MID_LEFT.IBUFDS_GTPE2_1_MGTCLKOUT_MUX.IBUFDS_GTPE2_1_MGTCLKOUT origin:065-gtp-common-pips 06_1627 -GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[0] origin:063-gtp-common-conf 00_1640 -GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[1] origin:063-gtp-common-conf 01_1640 -GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[2] origin:063-gtp-common-conf 00_1641 -GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[3] origin:063-gtp-common-conf 01_1641 -GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[4] origin:063-gtp-common-conf 00_1642 -GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[5] origin:063-gtp-common-conf 01_1642 -GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[6] origin:063-gtp-common-conf 00_1643 -GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[7] origin:063-gtp-common-conf 01_1643 -GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[8] origin:063-gtp-common-conf 00_1644 -GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[9] origin:063-gtp-common-conf 01_1644 -GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[10] origin:063-gtp-common-conf 00_1645 -GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[11] origin:063-gtp-common-conf 01_1645 -GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[12] origin:063-gtp-common-conf 00_1646 -GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[13] origin:063-gtp-common-conf 01_1646 -GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[14] origin:063-gtp-common-conf 00_1647 -GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[15] origin:063-gtp-common-conf 01_1647 -GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[16] origin:063-gtp-common-conf 00_1648 -GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[17] origin:063-gtp-common-conf 01_1648 -GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[18] origin:063-gtp-common-conf 00_1649 -GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[19] origin:063-gtp-common-conf 01_1649 -GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[20] origin:063-gtp-common-conf 00_1650 -GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[21] origin:063-gtp-common-conf 01_1650 -GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[22] origin:063-gtp-common-conf 00_1651 -GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[23] origin:063-gtp-common-conf 01_1651 -GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[24] origin:063-gtp-common-conf 00_1652 -GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[25] origin:063-gtp-common-conf 01_1652 -GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[26] origin:063-gtp-common-conf 00_1653 -GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[27] origin:063-gtp-common-conf 01_1653 -GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[28] origin:063-gtp-common-conf 00_1654 -GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[29] origin:063-gtp-common-conf 01_1654 -GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[30] origin:063-gtp-common-conf 00_1655 -GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[31] origin:063-gtp-common-conf 01_1655 -GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[32] origin:063-gtp-common-conf 00_1656 -GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[33] origin:063-gtp-common-conf 01_1656 -GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[34] origin:063-gtp-common-conf 00_1657 -GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[35] origin:063-gtp-common-conf 01_1657 -GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[36] origin:063-gtp-common-conf 00_1658 -GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[37] origin:063-gtp-common-conf 01_1658 -GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[38] origin:063-gtp-common-conf 00_1659 -GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[39] origin:063-gtp-common-conf 01_1659 -GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[40] origin:063-gtp-common-conf 00_1660 -GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[41] origin:063-gtp-common-conf 01_1660 -GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[42] origin:063-gtp-common-conf 00_1661 -GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[43] origin:063-gtp-common-conf 01_1661 -GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[44] origin:063-gtp-common-conf 00_1662 -GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[45] origin:063-gtp-common-conf 01_1662 -GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[46] origin:063-gtp-common-conf 00_1663 -GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[47] origin:063-gtp-common-conf 01_1663 -GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[48] origin:063-gtp-common-conf 00_1664 -GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[49] origin:063-gtp-common-conf 01_1664 -GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[50] origin:063-gtp-common-conf 00_1665 -GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[51] origin:063-gtp-common-conf 01_1665 -GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[52] origin:063-gtp-common-conf 00_1666 -GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[53] origin:063-gtp-common-conf 01_1666 -GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[54] origin:063-gtp-common-conf 00_1667 -GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[55] origin:063-gtp-common-conf 01_1667 -GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[56] origin:063-gtp-common-conf 00_1668 -GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[57] origin:063-gtp-common-conf 01_1668 -GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[58] origin:063-gtp-common-conf 00_1669 -GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[59] origin:063-gtp-common-conf 01_1669 -GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[60] origin:063-gtp-common-conf 00_1670 -GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[61] origin:063-gtp-common-conf 01_1670 -GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[62] origin:063-gtp-common-conf 00_1671 -GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[63] origin:063-gtp-common-conf 01_1671 -GTP_COMMON_MID_LEFT.GTPE2.BOTH_GTREFCLK_USED origin:063-gtp-common-conf 01_1439 01_1807 -GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[0] origin:063-gtp-common-conf 00_1544 -GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[1] origin:063-gtp-common-conf 01_1544 -GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[2] origin:063-gtp-common-conf 00_1545 -GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[3] origin:063-gtp-common-conf 01_1545 -GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[4] origin:063-gtp-common-conf 00_1546 -GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[5] origin:063-gtp-common-conf 01_1546 -GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[6] origin:063-gtp-common-conf 00_1547 -GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[7] origin:063-gtp-common-conf 01_1547 -GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[8] origin:063-gtp-common-conf 00_1548 -GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[9] origin:063-gtp-common-conf 01_1548 -GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[10] origin:063-gtp-common-conf 00_1549 -GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[11] origin:063-gtp-common-conf 01_1549 -GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[12] origin:063-gtp-common-conf 00_1550 -GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[13] origin:063-gtp-common-conf 01_1550 -GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[14] origin:063-gtp-common-conf 00_1551 -GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[15] origin:063-gtp-common-conf 01_1551 -GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[16] origin:063-gtp-common-conf 00_1552 -GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[17] origin:063-gtp-common-conf 01_1552 -GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[18] origin:063-gtp-common-conf 00_1553 -GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[19] origin:063-gtp-common-conf 01_1553 -GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[20] origin:063-gtp-common-conf 00_1554 -GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[21] origin:063-gtp-common-conf 01_1554 -GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[22] origin:063-gtp-common-conf 00_1555 -GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[23] origin:063-gtp-common-conf 01_1555 -GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[24] origin:063-gtp-common-conf 00_1556 -GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[25] origin:063-gtp-common-conf 01_1556 -GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[26] origin:063-gtp-common-conf 00_1557 -GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[27] origin:063-gtp-common-conf 01_1557 -GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[28] origin:063-gtp-common-conf 00_1558 -GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[29] origin:063-gtp-common-conf 01_1558 -GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[30] origin:063-gtp-common-conf 00_1559 -GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[31] origin:063-gtp-common-conf 01_1559 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[0] origin:063-gtp-common-conf 00_1640 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[1] origin:063-gtp-common-conf 01_1640 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[2] origin:063-gtp-common-conf 00_1641 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[3] origin:063-gtp-common-conf 01_1641 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[4] origin:063-gtp-common-conf 00_1642 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[5] origin:063-gtp-common-conf 01_1642 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[6] origin:063-gtp-common-conf 00_1643 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[7] origin:063-gtp-common-conf 01_1643 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[8] origin:063-gtp-common-conf 00_1644 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[9] origin:063-gtp-common-conf 01_1644 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[10] origin:063-gtp-common-conf 00_1645 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[11] origin:063-gtp-common-conf 01_1645 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[12] origin:063-gtp-common-conf 00_1646 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[13] origin:063-gtp-common-conf 01_1646 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[14] origin:063-gtp-common-conf 00_1647 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[15] origin:063-gtp-common-conf 01_1647 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[16] origin:063-gtp-common-conf 00_1648 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[17] origin:063-gtp-common-conf 01_1648 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[18] origin:063-gtp-common-conf 00_1649 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[19] origin:063-gtp-common-conf 01_1649 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[20] origin:063-gtp-common-conf 00_1650 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[21] origin:063-gtp-common-conf 01_1650 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[22] origin:063-gtp-common-conf 00_1651 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[23] origin:063-gtp-common-conf 01_1651 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[24] origin:063-gtp-common-conf 00_1652 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[25] origin:063-gtp-common-conf 01_1652 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[26] origin:063-gtp-common-conf 00_1653 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[27] origin:063-gtp-common-conf 01_1653 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[28] origin:063-gtp-common-conf 00_1654 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[29] origin:063-gtp-common-conf 01_1654 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[30] origin:063-gtp-common-conf 00_1655 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[31] origin:063-gtp-common-conf 01_1655 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[32] origin:063-gtp-common-conf 00_1656 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[33] origin:063-gtp-common-conf 01_1656 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[34] origin:063-gtp-common-conf 00_1657 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[35] origin:063-gtp-common-conf 01_1657 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[36] origin:063-gtp-common-conf 00_1658 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[37] origin:063-gtp-common-conf 01_1658 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[38] origin:063-gtp-common-conf 00_1659 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[39] origin:063-gtp-common-conf 01_1659 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[40] origin:063-gtp-common-conf 00_1660 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[41] origin:063-gtp-common-conf 01_1660 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[42] origin:063-gtp-common-conf 00_1661 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[43] origin:063-gtp-common-conf 01_1661 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[44] origin:063-gtp-common-conf 00_1662 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[45] origin:063-gtp-common-conf 01_1662 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[46] origin:063-gtp-common-conf 00_1663 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[47] origin:063-gtp-common-conf 01_1663 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[48] origin:063-gtp-common-conf 00_1664 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[49] origin:063-gtp-common-conf 01_1664 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[50] origin:063-gtp-common-conf 00_1665 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[51] origin:063-gtp-common-conf 01_1665 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[52] origin:063-gtp-common-conf 00_1666 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[53] origin:063-gtp-common-conf 01_1666 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[54] origin:063-gtp-common-conf 00_1667 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[55] origin:063-gtp-common-conf 01_1667 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[56] origin:063-gtp-common-conf 00_1668 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[57] origin:063-gtp-common-conf 01_1668 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[58] origin:063-gtp-common-conf 00_1669 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[59] origin:063-gtp-common-conf 01_1669 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[60] origin:063-gtp-common-conf 00_1670 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[61] origin:063-gtp-common-conf 01_1670 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[62] origin:063-gtp-common-conf 00_1671 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.BIAS_CFG[63] origin:063-gtp-common-conf 01_1671 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.BOTH_GTREFCLK_USED origin:063-gtp-common-conf 01_1439 01_1807 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.COMMON_CFG[0] origin:063-gtp-common-conf 00_1544 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.COMMON_CFG[1] origin:063-gtp-common-conf 01_1544 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.COMMON_CFG[2] origin:063-gtp-common-conf 00_1545 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.COMMON_CFG[3] origin:063-gtp-common-conf 01_1545 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.COMMON_CFG[4] origin:063-gtp-common-conf 00_1546 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.COMMON_CFG[5] origin:063-gtp-common-conf 01_1546 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.COMMON_CFG[6] origin:063-gtp-common-conf 00_1547 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.COMMON_CFG[7] origin:063-gtp-common-conf 01_1547 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.COMMON_CFG[8] origin:063-gtp-common-conf 00_1548 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.COMMON_CFG[9] origin:063-gtp-common-conf 01_1548 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.COMMON_CFG[10] origin:063-gtp-common-conf 00_1549 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.COMMON_CFG[11] origin:063-gtp-common-conf 01_1549 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.COMMON_CFG[12] origin:063-gtp-common-conf 00_1550 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.COMMON_CFG[13] origin:063-gtp-common-conf 01_1550 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.COMMON_CFG[14] origin:063-gtp-common-conf 00_1551 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.COMMON_CFG[15] origin:063-gtp-common-conf 01_1551 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.COMMON_CFG[16] origin:063-gtp-common-conf 00_1552 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.COMMON_CFG[17] origin:063-gtp-common-conf 01_1552 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.COMMON_CFG[18] origin:063-gtp-common-conf 00_1553 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.COMMON_CFG[19] origin:063-gtp-common-conf 01_1553 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.COMMON_CFG[20] origin:063-gtp-common-conf 00_1554 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.COMMON_CFG[21] origin:063-gtp-common-conf 01_1554 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.COMMON_CFG[22] origin:063-gtp-common-conf 00_1555 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.COMMON_CFG[23] origin:063-gtp-common-conf 01_1555 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.COMMON_CFG[24] origin:063-gtp-common-conf 00_1556 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.COMMON_CFG[25] origin:063-gtp-common-conf 01_1556 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.COMMON_CFG[26] origin:063-gtp-common-conf 00_1557 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.COMMON_CFG[27] origin:063-gtp-common-conf 01_1557 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.COMMON_CFG[28] origin:063-gtp-common-conf 00_1558 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.COMMON_CFG[29] origin:063-gtp-common-conf 01_1558 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.COMMON_CFG[30] origin:063-gtp-common-conf 00_1559 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.COMMON_CFG[31] origin:063-gtp-common-conf 01_1559 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.ENABLE_DRP origin:063-gtp-common-conf 00_1613 01_1613 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.IBUFDS_GTE2.CLKSWING_CFG[0] origin:063-gtp-common-conf 01_1581 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.IBUFDS_GTE2.CLKSWING_CFG[1] origin:063-gtp-common-conf 00_1582 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.IN_USE origin:063-gtp-common-conf 00_1584 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.INV_DRPCLK origin:063-gtp-common-conf 00_1516 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.INV_PLL0LOCKDETCLK origin:063-gtp-common-conf 01_1512 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.INV_PLL1LOCKDETCLK origin:063-gtp-common-conf 00_1512 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL_CLKOUT_CFG[0] origin:063-gtp-common-conf 00_1560 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL_CLKOUT_CFG[1] origin:063-gtp-common-conf 01_1560 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL_CLKOUT_CFG[2] origin:063-gtp-common-conf 00_1561 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL_CLKOUT_CFG[3] origin:063-gtp-common-conf 01_1561 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL_CLKOUT_CFG[4] origin:063-gtp-common-conf 00_1562 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL_CLKOUT_CFG[5] origin:063-gtp-common-conf 01_1562 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL_CLKOUT_CFG[6] origin:063-gtp-common-conf 00_1563 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL_CLKOUT_CFG[7] origin:063-gtp-common-conf 01_1563 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.RSVD_ATTR0[0] origin:063-gtp-common-conf 00_1488 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.RSVD_ATTR0[1] origin:063-gtp-common-conf 01_1488 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.RSVD_ATTR0[2] origin:063-gtp-common-conf 00_1489 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.RSVD_ATTR0[3] origin:063-gtp-common-conf 01_1489 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.RSVD_ATTR0[4] origin:063-gtp-common-conf 00_1490 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.RSVD_ATTR0[5] origin:063-gtp-common-conf 01_1490 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.RSVD_ATTR0[6] origin:063-gtp-common-conf 00_1491 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.RSVD_ATTR0[7] origin:063-gtp-common-conf 01_1491 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.RSVD_ATTR0[8] origin:063-gtp-common-conf 00_1492 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.RSVD_ATTR0[9] origin:063-gtp-common-conf 01_1492 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.RSVD_ATTR0[10] origin:063-gtp-common-conf 00_1493 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.RSVD_ATTR0[11] origin:063-gtp-common-conf 01_1493 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.RSVD_ATTR0[12] origin:063-gtp-common-conf 00_1494 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.RSVD_ATTR0[13] origin:063-gtp-common-conf 01_1494 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.RSVD_ATTR0[14] origin:063-gtp-common-conf 00_1495 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.RSVD_ATTR0[15] origin:063-gtp-common-conf 01_1495 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.RSVD_ATTR1[0] origin:063-gtp-common-conf 00_1728 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.RSVD_ATTR1[1] origin:063-gtp-common-conf 01_1728 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.RSVD_ATTR1[2] origin:063-gtp-common-conf 00_1729 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.RSVD_ATTR1[3] origin:063-gtp-common-conf 01_1729 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.RSVD_ATTR1[4] origin:063-gtp-common-conf 00_1730 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.RSVD_ATTR1[5] origin:063-gtp-common-conf 01_1730 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.RSVD_ATTR1[6] origin:063-gtp-common-conf 00_1731 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.RSVD_ATTR1[7] origin:063-gtp-common-conf 01_1731 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.RSVD_ATTR1[8] origin:063-gtp-common-conf 00_1732 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.RSVD_ATTR1[9] origin:063-gtp-common-conf 01_1732 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.RSVD_ATTR1[10] origin:063-gtp-common-conf 00_1733 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.RSVD_ATTR1[11] origin:063-gtp-common-conf 01_1733 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.RSVD_ATTR1[12] origin:063-gtp-common-conf 00_1734 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.RSVD_ATTR1[13] origin:063-gtp-common-conf 01_1734 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.RSVD_ATTR1[14] origin:063-gtp-common-conf 00_1735 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.RSVD_ATTR1[15] origin:063-gtp-common-conf 01_1735 GTP_COMMON_MID_LEFT.GTPE2_COMMON_RXOUTCLK_MUX_0.GTPE2_COMMON_RXOUTCLK_0 origin:065-gtp-common-pips 06_1628 GTP_COMMON_MID_LEFT.GTPE2_COMMON_RXOUTCLK_MUX_1.GTPE2_COMMON_RXOUTCLK_1 origin:065-gtp-common-pips 07_1627 GTP_COMMON_MID_LEFT.GTPE2_COMMON_RXOUTCLK_MUX_2.GTPE2_COMMON_RXOUTCLK_2 origin:065-gtp-common-pips 07_1630 @@ -282,181 +326,137 @@ GTP_COMMON_MID_LEFT.GTPE2_COMMON_TXOUTCLK_MUX_0.GTPE2_COMMON_TXOUTCLK_0 origin:0 GTP_COMMON_MID_LEFT.GTPE2_COMMON_TXOUTCLK_MUX_1.GTPE2_COMMON_TXOUTCLK_1 origin:065-gtp-common-pips 07_1628 GTP_COMMON_MID_LEFT.GTPE2_COMMON_TXOUTCLK_MUX_2.GTPE2_COMMON_TXOUTCLK_2 origin:065-gtp-common-pips 07_1631 GTP_COMMON_MID_LEFT.GTPE2_COMMON_TXOUTCLK_MUX_3.GTPE2_COMMON_TXOUTCLK_3 origin:065-gtp-common-pips 06_1631 -GTP_COMMON_MID_LEFT.GTPE2.IN_USE origin:063-gtp-common-conf 00_1584 -GTP_COMMON_MID_LEFT.GTPE2.PLL_CLKOUT_CFG[0] origin:063-gtp-common-conf 00_1560 -GTP_COMMON_MID_LEFT.GTPE2.PLL_CLKOUT_CFG[1] origin:063-gtp-common-conf 01_1560 -GTP_COMMON_MID_LEFT.GTPE2.PLL_CLKOUT_CFG[2] origin:063-gtp-common-conf 00_1561 -GTP_COMMON_MID_LEFT.GTPE2.PLL_CLKOUT_CFG[3] origin:063-gtp-common-conf 01_1561 -GTP_COMMON_MID_LEFT.GTPE2.PLL_CLKOUT_CFG[4] origin:063-gtp-common-conf 00_1562 -GTP_COMMON_MID_LEFT.GTPE2.PLL_CLKOUT_CFG[5] origin:063-gtp-common-conf 01_1562 -GTP_COMMON_MID_LEFT.GTPE2.PLL_CLKOUT_CFG[6] origin:063-gtp-common-conf 00_1563 -GTP_COMMON_MID_LEFT.GTPE2.PLL_CLKOUT_CFG[7] origin:063-gtp-common-conf 01_1563 -GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR0[0] origin:063-gtp-common-conf 00_1488 -GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR0[1] origin:063-gtp-common-conf 01_1488 -GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR0[2] origin:063-gtp-common-conf 00_1489 -GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR0[3] origin:063-gtp-common-conf 01_1489 -GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR0[4] origin:063-gtp-common-conf 00_1490 -GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR0[5] origin:063-gtp-common-conf 01_1490 -GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR0[6] origin:063-gtp-common-conf 00_1491 -GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR0[7] origin:063-gtp-common-conf 01_1491 -GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR0[8] origin:063-gtp-common-conf 00_1492 -GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR0[9] origin:063-gtp-common-conf 01_1492 -GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR0[10] origin:063-gtp-common-conf 00_1493 -GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR0[11] origin:063-gtp-common-conf 01_1493 -GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR0[12] origin:063-gtp-common-conf 00_1494 -GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR0[13] origin:063-gtp-common-conf 01_1494 -GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR0[14] origin:063-gtp-common-conf 00_1495 -GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR0[15] origin:063-gtp-common-conf 01_1495 -GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR1[0] origin:063-gtp-common-conf 00_1728 -GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR1[1] origin:063-gtp-common-conf 01_1728 -GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR1[2] origin:063-gtp-common-conf 00_1729 -GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR1[3] origin:063-gtp-common-conf 01_1729 -GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR1[4] origin:063-gtp-common-conf 00_1730 -GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR1[5] origin:063-gtp-common-conf 01_1730 -GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR1[6] origin:063-gtp-common-conf 00_1731 -GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR1[7] origin:063-gtp-common-conf 01_1731 -GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR1[8] origin:063-gtp-common-conf 00_1732 -GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR1[9] origin:063-gtp-common-conf 01_1732 -GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR1[10] origin:063-gtp-common-conf 00_1733 -GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR1[11] origin:063-gtp-common-conf 01_1733 -GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR1[12] origin:063-gtp-common-conf 00_1734 -GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR1[13] origin:063-gtp-common-conf 01_1734 -GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR1[14] origin:063-gtp-common-conf 00_1735 -GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR1[15] origin:063-gtp-common-conf 01_1735 -GTP_COMMON_MID_LEFT.GTPE2.ZINV_DRPCLK origin:063-gtp-common-conf 00_1516 -GTP_COMMON_MID_LEFT.GTPE2.ZINV_PLL0LOCKDETCLK origin:063-gtp-common-conf 01_1512 -GTP_COMMON_MID_LEFT.GTPE2.ZINV_PLL1LOCKDETCLK origin:063-gtp-common-conf 00_1512 -GTP_COMMON_MID_LEFT.GTPE2.GTREFCLK0_USED origin:063-gtp-common-conf 00_1438 00_1806 -GTP_COMMON_MID_LEFT.GTPE2.GTREFCLK1_USED origin:063-gtp-common-conf 01_1438 01_1806 -GTP_COMMON_MID_LEFT.GTPE2.PLL0_CFG[0] origin:063-gtp-common-conf 00_1424 -GTP_COMMON_MID_LEFT.GTPE2.PLL0_CFG[1] origin:063-gtp-common-conf 01_1424 -GTP_COMMON_MID_LEFT.GTPE2.PLL0_CFG[2] origin:063-gtp-common-conf 00_1425 -GTP_COMMON_MID_LEFT.GTPE2.PLL0_CFG[3] origin:063-gtp-common-conf 01_1425 -GTP_COMMON_MID_LEFT.GTPE2.PLL0_CFG[4] origin:063-gtp-common-conf 00_1426 -GTP_COMMON_MID_LEFT.GTPE2.PLL0_CFG[5] origin:063-gtp-common-conf 01_1426 -GTP_COMMON_MID_LEFT.GTPE2.PLL0_CFG[6] origin:063-gtp-common-conf 00_1427 -GTP_COMMON_MID_LEFT.GTPE2.PLL0_CFG[7] origin:063-gtp-common-conf 01_1427 -GTP_COMMON_MID_LEFT.GTPE2.PLL0_CFG[8] origin:063-gtp-common-conf 00_1428 -GTP_COMMON_MID_LEFT.GTPE2.PLL0_CFG[9] origin:063-gtp-common-conf 01_1428 -GTP_COMMON_MID_LEFT.GTPE2.PLL0_CFG[10] origin:063-gtp-common-conf 00_1429 -GTP_COMMON_MID_LEFT.GTPE2.PLL0_CFG[11] origin:063-gtp-common-conf 01_1429 -GTP_COMMON_MID_LEFT.GTPE2.PLL0_CFG[12] origin:063-gtp-common-conf 00_1430 -GTP_COMMON_MID_LEFT.GTPE2.PLL0_CFG[13] origin:063-gtp-common-conf 01_1430 -GTP_COMMON_MID_LEFT.GTPE2.PLL0_CFG[14] origin:063-gtp-common-conf 00_1431 -GTP_COMMON_MID_LEFT.GTPE2.PLL0_CFG[15] origin:063-gtp-common-conf 01_1431 -GTP_COMMON_MID_LEFT.GTPE2.PLL0_CFG[16] origin:063-gtp-common-conf 00_1432 -GTP_COMMON_MID_LEFT.GTPE2.PLL0_CFG[17] origin:063-gtp-common-conf 01_1432 -GTP_COMMON_MID_LEFT.GTPE2.PLL0_CFG[18] origin:063-gtp-common-conf 00_1433 -GTP_COMMON_MID_LEFT.GTPE2.PLL0_CFG[19] origin:063-gtp-common-conf 01_1433 -GTP_COMMON_MID_LEFT.GTPE2.PLL0_CFG[20] origin:063-gtp-common-conf 00_1434 -GTP_COMMON_MID_LEFT.GTPE2.PLL0_CFG[21] origin:063-gtp-common-conf 01_1434 -GTP_COMMON_MID_LEFT.GTPE2.PLL0_CFG[22] origin:063-gtp-common-conf 00_1435 -GTP_COMMON_MID_LEFT.GTPE2.PLL0_CFG[23] origin:063-gtp-common-conf 01_1435 -GTP_COMMON_MID_LEFT.GTPE2.PLL0_CFG[24] origin:063-gtp-common-conf 00_1436 -GTP_COMMON_MID_LEFT.GTPE2.PLL0_CFG[25] origin:063-gtp-common-conf 01_1436 -GTP_COMMON_MID_LEFT.GTPE2.PLL0_CFG[26] origin:063-gtp-common-conf 00_1437 -GTP_COMMON_MID_LEFT.GTPE2.PLL0_DMON_CFG[0] origin:063-gtp-common-conf 00_1528 -GTP_COMMON_MID_LEFT.GTPE2.PLL0_FBDIV[0] origin:063-gtp-common-conf 00_1440 -GTP_COMMON_MID_LEFT.GTPE2.PLL0_FBDIV[1] origin:063-gtp-common-conf 01_1440 -GTP_COMMON_MID_LEFT.GTPE2.PLL0_FBDIV[4] origin:063-gtp-common-conf 00_1442 -GTP_COMMON_MID_LEFT.GTPE2.PLL0_FBDIV_45[0] origin:063-gtp-common-conf 01_1443 -GTP_COMMON_MID_LEFT.GTPE2.PLL0_INIT_CFG[0] origin:063-gtp-common-conf 00_1456 -GTP_COMMON_MID_LEFT.GTPE2.PLL0_INIT_CFG[1] origin:063-gtp-common-conf 01_1456 -GTP_COMMON_MID_LEFT.GTPE2.PLL0_INIT_CFG[2] origin:063-gtp-common-conf 00_1457 -GTP_COMMON_MID_LEFT.GTPE2.PLL0_INIT_CFG[3] origin:063-gtp-common-conf 01_1457 -GTP_COMMON_MID_LEFT.GTPE2.PLL0_INIT_CFG[4] origin:063-gtp-common-conf 00_1458 -GTP_COMMON_MID_LEFT.GTPE2.PLL0_INIT_CFG[5] origin:063-gtp-common-conf 01_1458 -GTP_COMMON_MID_LEFT.GTPE2.PLL0_INIT_CFG[6] origin:063-gtp-common-conf 00_1459 -GTP_COMMON_MID_LEFT.GTPE2.PLL0_INIT_CFG[7] origin:063-gtp-common-conf 01_1459 -GTP_COMMON_MID_LEFT.GTPE2.PLL0_INIT_CFG[8] origin:063-gtp-common-conf 00_1460 -GTP_COMMON_MID_LEFT.GTPE2.PLL0_INIT_CFG[9] origin:063-gtp-common-conf 01_1460 -GTP_COMMON_MID_LEFT.GTPE2.PLL0_INIT_CFG[10] origin:063-gtp-common-conf 00_1461 -GTP_COMMON_MID_LEFT.GTPE2.PLL0_INIT_CFG[11] origin:063-gtp-common-conf 01_1461 -GTP_COMMON_MID_LEFT.GTPE2.PLL0_INIT_CFG[12] origin:063-gtp-common-conf 00_1462 -GTP_COMMON_MID_LEFT.GTPE2.PLL0_INIT_CFG[13] origin:063-gtp-common-conf 01_1462 -GTP_COMMON_MID_LEFT.GTPE2.PLL0_INIT_CFG[14] origin:063-gtp-common-conf 00_1463 -GTP_COMMON_MID_LEFT.GTPE2.PLL0_INIT_CFG[15] origin:063-gtp-common-conf 01_1463 -GTP_COMMON_MID_LEFT.GTPE2.PLL0_INIT_CFG[16] origin:063-gtp-common-conf 00_1464 -GTP_COMMON_MID_LEFT.GTPE2.PLL0_INIT_CFG[17] origin:063-gtp-common-conf 01_1464 -GTP_COMMON_MID_LEFT.GTPE2.PLL0_INIT_CFG[18] origin:063-gtp-common-conf 00_1465 -GTP_COMMON_MID_LEFT.GTPE2.PLL0_INIT_CFG[19] origin:063-gtp-common-conf 01_1465 -GTP_COMMON_MID_LEFT.GTPE2.PLL0_INIT_CFG[20] origin:063-gtp-common-conf 00_1466 -GTP_COMMON_MID_LEFT.GTPE2.PLL0_INIT_CFG[21] origin:063-gtp-common-conf 01_1466 -GTP_COMMON_MID_LEFT.GTPE2.PLL0_INIT_CFG[22] origin:063-gtp-common-conf 00_1467 -GTP_COMMON_MID_LEFT.GTPE2.PLL0_INIT_CFG[23] origin:063-gtp-common-conf 01_1467 -GTP_COMMON_MID_LEFT.GTPE2.PLL0_LOCK_CFG[0] origin:063-gtp-common-conf 00_1448 -GTP_COMMON_MID_LEFT.GTPE2.PLL0_LOCK_CFG[1] origin:063-gtp-common-conf 01_1448 -GTP_COMMON_MID_LEFT.GTPE2.PLL0_LOCK_CFG[2] origin:063-gtp-common-conf 00_1449 -GTP_COMMON_MID_LEFT.GTPE2.PLL0_LOCK_CFG[3] origin:063-gtp-common-conf 01_1449 -GTP_COMMON_MID_LEFT.GTPE2.PLL0_LOCK_CFG[4] origin:063-gtp-common-conf 00_1450 -GTP_COMMON_MID_LEFT.GTPE2.PLL0_LOCK_CFG[5] origin:063-gtp-common-conf 01_1450 -GTP_COMMON_MID_LEFT.GTPE2.PLL0_LOCK_CFG[6] origin:063-gtp-common-conf 00_1451 -GTP_COMMON_MID_LEFT.GTPE2.PLL0_LOCK_CFG[7] origin:063-gtp-common-conf 01_1451 -GTP_COMMON_MID_LEFT.GTPE2.PLL0_LOCK_CFG[8] origin:063-gtp-common-conf 00_1452 -GTP_COMMON_MID_LEFT.GTPE2.PLL0_REFCLK_DIV[4] origin:063-gtp-common-conf 01_1446 -GTP_COMMON_MID_LEFT.GTPE2.PLL1_CFG[0] origin:063-gtp-common-conf 00_1792 -GTP_COMMON_MID_LEFT.GTPE2.PLL1_CFG[1] origin:063-gtp-common-conf 01_1792 -GTP_COMMON_MID_LEFT.GTPE2.PLL1_CFG[2] origin:063-gtp-common-conf 00_1793 -GTP_COMMON_MID_LEFT.GTPE2.PLL1_CFG[3] origin:063-gtp-common-conf 01_1793 -GTP_COMMON_MID_LEFT.GTPE2.PLL1_CFG[4] origin:063-gtp-common-conf 00_1794 -GTP_COMMON_MID_LEFT.GTPE2.PLL1_CFG[5] origin:063-gtp-common-conf 01_1794 -GTP_COMMON_MID_LEFT.GTPE2.PLL1_CFG[6] origin:063-gtp-common-conf 00_1795 -GTP_COMMON_MID_LEFT.GTPE2.PLL1_CFG[7] origin:063-gtp-common-conf 01_1795 -GTP_COMMON_MID_LEFT.GTPE2.PLL1_CFG[8] origin:063-gtp-common-conf 00_1796 -GTP_COMMON_MID_LEFT.GTPE2.PLL1_CFG[9] origin:063-gtp-common-conf 01_1796 -GTP_COMMON_MID_LEFT.GTPE2.PLL1_CFG[10] origin:063-gtp-common-conf 00_1797 -GTP_COMMON_MID_LEFT.GTPE2.PLL1_CFG[11] origin:063-gtp-common-conf 01_1797 -GTP_COMMON_MID_LEFT.GTPE2.PLL1_CFG[12] origin:063-gtp-common-conf 00_1798 -GTP_COMMON_MID_LEFT.GTPE2.PLL1_CFG[13] origin:063-gtp-common-conf 01_1798 -GTP_COMMON_MID_LEFT.GTPE2.PLL1_CFG[14] origin:063-gtp-common-conf 00_1799 -GTP_COMMON_MID_LEFT.GTPE2.PLL1_CFG[15] origin:063-gtp-common-conf 01_1799 -GTP_COMMON_MID_LEFT.GTPE2.PLL1_CFG[16] origin:063-gtp-common-conf 00_1800 -GTP_COMMON_MID_LEFT.GTPE2.PLL1_CFG[17] origin:063-gtp-common-conf 01_1800 -GTP_COMMON_MID_LEFT.GTPE2.PLL1_CFG[18] origin:063-gtp-common-conf 00_1801 -GTP_COMMON_MID_LEFT.GTPE2.PLL1_CFG[19] origin:063-gtp-common-conf 01_1801 -GTP_COMMON_MID_LEFT.GTPE2.PLL1_CFG[20] origin:063-gtp-common-conf 00_1802 -GTP_COMMON_MID_LEFT.GTPE2.PLL1_CFG[21] origin:063-gtp-common-conf 01_1802 -GTP_COMMON_MID_LEFT.GTPE2.PLL1_CFG[22] origin:063-gtp-common-conf 00_1803 -GTP_COMMON_MID_LEFT.GTPE2.PLL1_CFG[23] origin:063-gtp-common-conf 01_1803 -GTP_COMMON_MID_LEFT.GTPE2.PLL1_CFG[24] origin:063-gtp-common-conf 00_1804 -GTP_COMMON_MID_LEFT.GTPE2.PLL1_CFG[25] origin:063-gtp-common-conf 01_1804 -GTP_COMMON_MID_LEFT.GTPE2.PLL1_CFG[26] origin:063-gtp-common-conf 00_1805 -GTP_COMMON_MID_LEFT.GTPE2.PLL1_DMON_CFG[0] origin:063-gtp-common-conf 01_1528 -GTP_COMMON_MID_LEFT.GTPE2.PLL1_FBDIV[0] origin:063-gtp-common-conf 00_1784 -GTP_COMMON_MID_LEFT.GTPE2.PLL1_FBDIV[1] origin:063-gtp-common-conf 01_1784 -GTP_COMMON_MID_LEFT.GTPE2.PLL1_FBDIV[4] origin:063-gtp-common-conf 00_1786 -GTP_COMMON_MID_LEFT.GTPE2.PLL1_FBDIV_45[0] origin:063-gtp-common-conf 01_1787 -GTP_COMMON_MID_LEFT.GTPE2.PLL1_INIT_CFG[0] origin:063-gtp-common-conf 00_1760 -GTP_COMMON_MID_LEFT.GTPE2.PLL1_INIT_CFG[1] origin:063-gtp-common-conf 01_1760 -GTP_COMMON_MID_LEFT.GTPE2.PLL1_INIT_CFG[2] origin:063-gtp-common-conf 00_1761 -GTP_COMMON_MID_LEFT.GTPE2.PLL1_INIT_CFG[3] origin:063-gtp-common-conf 01_1761 -GTP_COMMON_MID_LEFT.GTPE2.PLL1_INIT_CFG[4] origin:063-gtp-common-conf 00_1762 -GTP_COMMON_MID_LEFT.GTPE2.PLL1_INIT_CFG[5] origin:063-gtp-common-conf 01_1762 -GTP_COMMON_MID_LEFT.GTPE2.PLL1_INIT_CFG[6] origin:063-gtp-common-conf 00_1763 -GTP_COMMON_MID_LEFT.GTPE2.PLL1_INIT_CFG[7] origin:063-gtp-common-conf 01_1763 -GTP_COMMON_MID_LEFT.GTPE2.PLL1_INIT_CFG[8] origin:063-gtp-common-conf 00_1764 -GTP_COMMON_MID_LEFT.GTPE2.PLL1_INIT_CFG[9] origin:063-gtp-common-conf 01_1764 -GTP_COMMON_MID_LEFT.GTPE2.PLL1_INIT_CFG[10] origin:063-gtp-common-conf 00_1765 -GTP_COMMON_MID_LEFT.GTPE2.PLL1_INIT_CFG[11] origin:063-gtp-common-conf 01_1765 -GTP_COMMON_MID_LEFT.GTPE2.PLL1_INIT_CFG[12] origin:063-gtp-common-conf 00_1766 -GTP_COMMON_MID_LEFT.GTPE2.PLL1_INIT_CFG[13] origin:063-gtp-common-conf 01_1766 -GTP_COMMON_MID_LEFT.GTPE2.PLL1_INIT_CFG[14] origin:063-gtp-common-conf 00_1767 -GTP_COMMON_MID_LEFT.GTPE2.PLL1_INIT_CFG[15] origin:063-gtp-common-conf 01_1767 -GTP_COMMON_MID_LEFT.GTPE2.PLL1_INIT_CFG[16] origin:063-gtp-common-conf 00_1768 -GTP_COMMON_MID_LEFT.GTPE2.PLL1_INIT_CFG[17] origin:063-gtp-common-conf 01_1768 -GTP_COMMON_MID_LEFT.GTPE2.PLL1_INIT_CFG[18] origin:063-gtp-common-conf 00_1769 -GTP_COMMON_MID_LEFT.GTPE2.PLL1_INIT_CFG[19] origin:063-gtp-common-conf 01_1769 -GTP_COMMON_MID_LEFT.GTPE2.PLL1_INIT_CFG[20] origin:063-gtp-common-conf 00_1770 -GTP_COMMON_MID_LEFT.GTPE2.PLL1_INIT_CFG[21] origin:063-gtp-common-conf 01_1770 -GTP_COMMON_MID_LEFT.GTPE2.PLL1_INIT_CFG[22] origin:063-gtp-common-conf 00_1771 -GTP_COMMON_MID_LEFT.GTPE2.PLL1_INIT_CFG[23] origin:063-gtp-common-conf 01_1771 -GTP_COMMON_MID_LEFT.GTPE2.PLL1_LOCK_CFG[0] origin:063-gtp-common-conf 00_1776 -GTP_COMMON_MID_LEFT.GTPE2.PLL1_LOCK_CFG[1] origin:063-gtp-common-conf 01_1776 -GTP_COMMON_MID_LEFT.GTPE2.PLL1_LOCK_CFG[2] origin:063-gtp-common-conf 00_1777 -GTP_COMMON_MID_LEFT.GTPE2.PLL1_LOCK_CFG[3] origin:063-gtp-common-conf 01_1777 -GTP_COMMON_MID_LEFT.GTPE2.PLL1_LOCK_CFG[4] origin:063-gtp-common-conf 00_1778 -GTP_COMMON_MID_LEFT.GTPE2.PLL1_LOCK_CFG[5] origin:063-gtp-common-conf 01_1778 -GTP_COMMON_MID_LEFT.GTPE2.PLL1_LOCK_CFG[6] origin:063-gtp-common-conf 00_1779 -GTP_COMMON_MID_LEFT.GTPE2.PLL1_LOCK_CFG[7] origin:063-gtp-common-conf 01_1779 -GTP_COMMON_MID_LEFT.GTPE2.PLL1_LOCK_CFG[8] origin:063-gtp-common-conf 00_1780 -GTP_COMMON_MID_LEFT.GTPE2.PLL1_REFCLK_DIV[4] origin:063-gtp-common-conf 01_1790 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.GTREFCLK0_USED origin:063-gtp-common-conf 00_1438 00_1806 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.GTREFCLK1_USED origin:063-gtp-common-conf 01_1438 01_1806 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_CFG[0] origin:063-gtp-common-conf 00_1424 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_CFG[1] origin:063-gtp-common-conf 01_1424 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_CFG[2] origin:063-gtp-common-conf 00_1425 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_CFG[3] origin:063-gtp-common-conf 01_1425 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_CFG[4] origin:063-gtp-common-conf 00_1426 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_CFG[5] origin:063-gtp-common-conf 01_1426 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_CFG[6] origin:063-gtp-common-conf 00_1427 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_CFG[7] origin:063-gtp-common-conf 01_1427 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_CFG[8] origin:063-gtp-common-conf 00_1428 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_CFG[9] origin:063-gtp-common-conf 01_1428 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_CFG[10] origin:063-gtp-common-conf 00_1429 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_CFG[11] origin:063-gtp-common-conf 01_1429 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_CFG[12] origin:063-gtp-common-conf 00_1430 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_CFG[13] origin:063-gtp-common-conf 01_1430 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_CFG[14] origin:063-gtp-common-conf 00_1431 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_CFG[15] origin:063-gtp-common-conf 01_1431 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_CFG[16] origin:063-gtp-common-conf 00_1432 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_CFG[17] origin:063-gtp-common-conf 01_1432 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_CFG[18] origin:063-gtp-common-conf 00_1433 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_CFG[19] origin:063-gtp-common-conf 01_1433 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_CFG[20] origin:063-gtp-common-conf 00_1434 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_CFG[21] origin:063-gtp-common-conf 01_1434 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_CFG[22] origin:063-gtp-common-conf 00_1435 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_CFG[23] origin:063-gtp-common-conf 01_1435 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_CFG[24] origin:063-gtp-common-conf 00_1436 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_CFG[25] origin:063-gtp-common-conf 01_1436 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_CFG[26] origin:063-gtp-common-conf 00_1437 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_DMON_CFG[0] origin:063-gtp-common-conf 00_1528 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_FBDIV[0] origin:063-gtp-common-conf 00_1440 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_FBDIV[1] origin:063-gtp-common-conf 01_1440 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_FBDIV[4] origin:063-gtp-common-conf 00_1442 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_FBDIV_45[0] origin:063-gtp-common-conf 01_1443 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_INIT_CFG[0] origin:063-gtp-common-conf 00_1456 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_INIT_CFG[1] origin:063-gtp-common-conf 01_1456 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_INIT_CFG[2] origin:063-gtp-common-conf 00_1457 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_INIT_CFG[3] origin:063-gtp-common-conf 01_1457 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_INIT_CFG[4] origin:063-gtp-common-conf 00_1458 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_INIT_CFG[5] origin:063-gtp-common-conf 01_1458 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_INIT_CFG[6] origin:063-gtp-common-conf 00_1459 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_INIT_CFG[7] origin:063-gtp-common-conf 01_1459 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_INIT_CFG[8] origin:063-gtp-common-conf 00_1460 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_INIT_CFG[9] origin:063-gtp-common-conf 01_1460 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_INIT_CFG[10] origin:063-gtp-common-conf 00_1461 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_INIT_CFG[11] origin:063-gtp-common-conf 01_1461 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_INIT_CFG[12] origin:063-gtp-common-conf 00_1462 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_INIT_CFG[13] origin:063-gtp-common-conf 01_1462 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_INIT_CFG[14] origin:063-gtp-common-conf 00_1463 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_INIT_CFG[15] origin:063-gtp-common-conf 01_1463 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_INIT_CFG[16] origin:063-gtp-common-conf 00_1464 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_INIT_CFG[17] origin:063-gtp-common-conf 01_1464 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_INIT_CFG[18] origin:063-gtp-common-conf 00_1465 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_INIT_CFG[19] origin:063-gtp-common-conf 01_1465 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_INIT_CFG[20] origin:063-gtp-common-conf 00_1466 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_INIT_CFG[21] origin:063-gtp-common-conf 01_1466 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_INIT_CFG[22] origin:063-gtp-common-conf 00_1467 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_INIT_CFG[23] origin:063-gtp-common-conf 01_1467 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_LOCK_CFG[0] origin:063-gtp-common-conf 00_1448 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_LOCK_CFG[1] origin:063-gtp-common-conf 01_1448 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_LOCK_CFG[2] origin:063-gtp-common-conf 00_1449 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_LOCK_CFG[3] origin:063-gtp-common-conf 01_1449 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_LOCK_CFG[4] origin:063-gtp-common-conf 00_1450 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_LOCK_CFG[5] origin:063-gtp-common-conf 01_1450 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_LOCK_CFG[6] origin:063-gtp-common-conf 00_1451 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_LOCK_CFG[7] origin:063-gtp-common-conf 01_1451 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_LOCK_CFG[8] origin:063-gtp-common-conf 00_1452 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL0_REFCLK_DIV[4] origin:063-gtp-common-conf 01_1446 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_CFG[0] origin:063-gtp-common-conf 00_1792 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_CFG[1] origin:063-gtp-common-conf 01_1792 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_CFG[2] origin:063-gtp-common-conf 00_1793 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_CFG[3] origin:063-gtp-common-conf 01_1793 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_CFG[4] origin:063-gtp-common-conf 00_1794 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_CFG[5] origin:063-gtp-common-conf 01_1794 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_CFG[6] origin:063-gtp-common-conf 00_1795 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_CFG[7] origin:063-gtp-common-conf 01_1795 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_CFG[8] origin:063-gtp-common-conf 00_1796 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_CFG[9] origin:063-gtp-common-conf 01_1796 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_CFG[10] origin:063-gtp-common-conf 00_1797 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_CFG[11] origin:063-gtp-common-conf 01_1797 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_CFG[12] origin:063-gtp-common-conf 00_1798 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_CFG[13] origin:063-gtp-common-conf 01_1798 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_CFG[14] origin:063-gtp-common-conf 00_1799 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_CFG[15] origin:063-gtp-common-conf 01_1799 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_CFG[16] origin:063-gtp-common-conf 00_1800 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_CFG[17] origin:063-gtp-common-conf 01_1800 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_CFG[18] origin:063-gtp-common-conf 00_1801 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_CFG[19] origin:063-gtp-common-conf 01_1801 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_CFG[20] origin:063-gtp-common-conf 00_1802 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_CFG[21] origin:063-gtp-common-conf 01_1802 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_CFG[22] origin:063-gtp-common-conf 00_1803 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_CFG[23] origin:063-gtp-common-conf 01_1803 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_CFG[24] origin:063-gtp-common-conf 00_1804 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_CFG[25] origin:063-gtp-common-conf 01_1804 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_CFG[26] origin:063-gtp-common-conf 00_1805 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_DMON_CFG[0] origin:063-gtp-common-conf 01_1528 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_FBDIV[0] origin:063-gtp-common-conf 00_1784 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_FBDIV[1] origin:063-gtp-common-conf 01_1784 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_FBDIV[4] origin:063-gtp-common-conf 00_1786 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_FBDIV_45[0] origin:063-gtp-common-conf 01_1787 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_INIT_CFG[0] origin:063-gtp-common-conf 00_1760 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_INIT_CFG[1] origin:063-gtp-common-conf 01_1760 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_INIT_CFG[2] origin:063-gtp-common-conf 00_1761 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_INIT_CFG[3] origin:063-gtp-common-conf 01_1761 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_INIT_CFG[4] origin:063-gtp-common-conf 00_1762 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_INIT_CFG[5] origin:063-gtp-common-conf 01_1762 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_INIT_CFG[6] origin:063-gtp-common-conf 00_1763 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_INIT_CFG[7] origin:063-gtp-common-conf 01_1763 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_INIT_CFG[8] origin:063-gtp-common-conf 00_1764 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_INIT_CFG[9] origin:063-gtp-common-conf 01_1764 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_INIT_CFG[10] origin:063-gtp-common-conf 00_1765 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_INIT_CFG[11] origin:063-gtp-common-conf 01_1765 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_INIT_CFG[12] origin:063-gtp-common-conf 00_1766 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_INIT_CFG[13] origin:063-gtp-common-conf 01_1766 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_INIT_CFG[14] origin:063-gtp-common-conf 00_1767 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_INIT_CFG[15] origin:063-gtp-common-conf 01_1767 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_INIT_CFG[16] origin:063-gtp-common-conf 00_1768 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_INIT_CFG[17] origin:063-gtp-common-conf 01_1768 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_INIT_CFG[18] origin:063-gtp-common-conf 00_1769 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_INIT_CFG[19] origin:063-gtp-common-conf 01_1769 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_INIT_CFG[20] origin:063-gtp-common-conf 00_1770 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_INIT_CFG[21] origin:063-gtp-common-conf 01_1770 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_INIT_CFG[22] origin:063-gtp-common-conf 00_1771 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_INIT_CFG[23] origin:063-gtp-common-conf 01_1771 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_LOCK_CFG[0] origin:063-gtp-common-conf 00_1776 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_LOCK_CFG[1] origin:063-gtp-common-conf 01_1776 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_LOCK_CFG[2] origin:063-gtp-common-conf 00_1777 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_LOCK_CFG[3] origin:063-gtp-common-conf 01_1777 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_LOCK_CFG[4] origin:063-gtp-common-conf 00_1778 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_LOCK_CFG[5] origin:063-gtp-common-conf 01_1778 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_LOCK_CFG[6] origin:063-gtp-common-conf 00_1779 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_LOCK_CFG[7] origin:063-gtp-common-conf 01_1779 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_LOCK_CFG[8] origin:063-gtp-common-conf 00_1780 +GTP_COMMON_MID_LEFT.GTPE2_COMMON.PLL1_REFCLK_DIV[4] origin:063-gtp-common-conf 01_1790 diff --git a/artix7/segbits_gtp_common_mid_right.db b/artix7/segbits_gtp_common_mid_right.db index 9c70cff..4c9036a 100644 --- a/artix7/segbits_gtp_common_mid_right.db +++ b/artix7/segbits_gtp_common_mid_right.db @@ -1,4 +1,3 @@ -GTP_COMMON_MID_RIGHT.ENABLE_DRP 00_1613 01_1613 GTP_COMMON_MID_RIGHT.HCLK_GTP_CK_IN0.HCLK_GTP_CK_MUX0 02_1614 03_1617 03_1622 GTP_COMMON_MID_RIGHT.HCLK_GTP_CK_IN0.HCLK_GTP_CK_MUX1 02_1614 02_1622 03_1616 GTP_COMMON_MID_RIGHT.HCLK_GTP_CK_IN0.IBUFDS_GTPE2_0_MGTCLKOUT_MUX 02_1615 03_1617 @@ -167,8 +166,6 @@ GTP_COMMON_MID_RIGHT.HCLK_GTP_CK_IN13.GTPE2_COMMON_TXOUTCLK_MUX_0 06_1623 07_161 GTP_COMMON_MID_RIGHT.HCLK_GTP_CK_IN13.GTPE2_COMMON_TXOUTCLK_MUX_1 06_1620 07_1617 GTP_COMMON_MID_RIGHT.HCLK_GTP_CK_IN13.GTPE2_COMMON_TXOUTCLK_MUX_2 06_1623 07_1616 GTP_COMMON_MID_RIGHT.HCLK_GTP_CK_IN13.GTPE2_COMMON_TXOUTCLK_MUX_3 06_1620 07_1616 -GTP_COMMON_MID_RIGHT.IBUFDS_GTE2.CLKCM_CFG[0] 01_1581 -GTP_COMMON_MID_RIGHT.IBUFDS_GTE2.CLKCM_CFG[1] 00_1582 GTP_COMMON_MID_RIGHT.IBUFDS_GTE2_Y0.CLKCM_CFG 00_1580 GTP_COMMON_MID_RIGHT.IBUFDS_GTE2_Y0.CLKRCV_TRST 00_1576 GTP_COMMON_MID_RIGHT.IBUFDS_GTE2_Y0.IN_USE 00_1578 @@ -177,103 +174,150 @@ GTP_COMMON_MID_RIGHT.IBUFDS_GTE2_Y1.CLKRCV_TRST 01_1576 GTP_COMMON_MID_RIGHT.IBUFDS_GTE2_Y1.IN_USE 00_1579 GTP_COMMON_MID_RIGHT.IBUFDS_GTPE2_0_MGTCLKOUT_MUX.IBUFDS_GTPE2_0_MGTCLKOUT 07_1629 GTP_COMMON_MID_RIGHT.IBUFDS_GTPE2_1_MGTCLKOUT_MUX.IBUFDS_GTPE2_1_MGTCLKOUT 06_1627 -GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[0] 00_1640 -GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[1] 01_1640 -GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[2] 00_1641 -GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[3] 01_1641 -GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[4] 00_1642 -GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[5] 01_1642 -GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[6] 00_1643 -GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[7] 01_1643 -GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[8] 00_1644 -GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[9] 01_1644 -GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[10] 00_1645 -GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[11] 01_1645 -GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[12] 00_1646 -GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[13] 01_1646 -GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[14] 00_1647 -GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[15] 01_1647 -GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[16] 00_1648 -GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[17] 01_1648 -GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[18] 00_1649 -GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[19] 01_1649 -GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[20] 00_1650 -GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[21] 01_1650 -GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[22] 00_1651 -GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[23] 01_1651 -GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[24] 00_1652 -GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[25] 01_1652 -GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[26] 00_1653 -GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[27] 01_1653 -GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[28] 00_1654 -GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[29] 01_1654 -GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[30] 00_1655 -GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[31] 01_1655 -GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[32] 00_1656 -GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[33] 01_1656 -GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[34] 00_1657 -GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[35] 01_1657 -GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[36] 00_1658 -GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[37] 01_1658 -GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[38] 00_1659 -GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[39] 01_1659 -GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[40] 00_1660 -GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[41] 01_1660 -GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[42] 00_1661 -GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[43] 01_1661 -GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[44] 00_1662 -GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[45] 01_1662 -GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[46] 00_1663 -GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[47] 01_1663 -GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[48] 00_1664 -GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[49] 01_1664 -GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[50] 00_1665 -GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[51] 01_1665 -GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[52] 00_1666 -GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[53] 01_1666 -GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[54] 00_1667 -GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[55] 01_1667 -GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[56] 00_1668 -GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[57] 01_1668 -GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[58] 00_1669 -GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[59] 01_1669 -GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[60] 00_1670 -GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[61] 01_1670 -GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[62] 00_1671 -GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[63] 01_1671 -GTP_COMMON_MID_RIGHT.GTPE2.BOTH_GTREFCLK_USED 01_1439 01_1807 -GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[0] 00_1544 -GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[1] 01_1544 -GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[2] 00_1545 -GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[3] 01_1545 -GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[4] 00_1546 -GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[5] 01_1546 -GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[6] 00_1547 -GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[7] 01_1547 -GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[8] 00_1548 -GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[9] 01_1548 -GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[10] 00_1549 -GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[11] 01_1549 -GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[12] 00_1550 -GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[13] 01_1550 -GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[14] 00_1551 -GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[15] 01_1551 -GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[16] 00_1552 -GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[17] 01_1552 -GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[18] 00_1553 -GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[19] 01_1553 -GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[20] 00_1554 -GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[21] 01_1554 -GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[22] 00_1555 -GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[23] 01_1555 -GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[24] 00_1556 -GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[25] 01_1556 -GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[26] 00_1557 -GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[27] 01_1557 -GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[28] 00_1558 -GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[29] 01_1558 -GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[30] 00_1559 -GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[31] 01_1559 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[0] 00_1640 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[1] 01_1640 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[2] 00_1641 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[3] 01_1641 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[4] 00_1642 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[5] 01_1642 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[6] 00_1643 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[7] 01_1643 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[8] 00_1644 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[9] 01_1644 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[10] 00_1645 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[11] 01_1645 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[12] 00_1646 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[13] 01_1646 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[14] 00_1647 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[15] 01_1647 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[16] 00_1648 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[17] 01_1648 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[18] 00_1649 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[19] 01_1649 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[20] 00_1650 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[21] 01_1650 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[22] 00_1651 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[23] 01_1651 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[24] 00_1652 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[25] 01_1652 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[26] 00_1653 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[27] 01_1653 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[28] 00_1654 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[29] 01_1654 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[30] 00_1655 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[31] 01_1655 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[32] 00_1656 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[33] 01_1656 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[34] 00_1657 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[35] 01_1657 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[36] 00_1658 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[37] 01_1658 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[38] 00_1659 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[39] 01_1659 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[40] 00_1660 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[41] 01_1660 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[42] 00_1661 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[43] 01_1661 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[44] 00_1662 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[45] 01_1662 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[46] 00_1663 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[47] 01_1663 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[48] 00_1664 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[49] 01_1664 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[50] 00_1665 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[51] 01_1665 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[52] 00_1666 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[53] 01_1666 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[54] 00_1667 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[55] 01_1667 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[56] 00_1668 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[57] 01_1668 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[58] 00_1669 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[59] 01_1669 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[60] 00_1670 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[61] 01_1670 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[62] 00_1671 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[63] 01_1671 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BOTH_GTREFCLK_USED 01_1439 01_1807 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.COMMON_CFG[0] 00_1544 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.COMMON_CFG[1] 01_1544 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.COMMON_CFG[2] 00_1545 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.COMMON_CFG[3] 01_1545 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.COMMON_CFG[4] 00_1546 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.COMMON_CFG[5] 01_1546 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.COMMON_CFG[6] 00_1547 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.COMMON_CFG[7] 01_1547 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.COMMON_CFG[8] 00_1548 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.COMMON_CFG[9] 01_1548 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.COMMON_CFG[10] 00_1549 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.COMMON_CFG[11] 01_1549 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.COMMON_CFG[12] 00_1550 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.COMMON_CFG[13] 01_1550 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.COMMON_CFG[14] 00_1551 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.COMMON_CFG[15] 01_1551 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.COMMON_CFG[16] 00_1552 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.COMMON_CFG[17] 01_1552 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.COMMON_CFG[18] 00_1553 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.COMMON_CFG[19] 01_1553 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.COMMON_CFG[20] 00_1554 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.COMMON_CFG[21] 01_1554 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.COMMON_CFG[22] 00_1555 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.COMMON_CFG[23] 01_1555 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.COMMON_CFG[24] 00_1556 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.COMMON_CFG[25] 01_1556 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.COMMON_CFG[26] 00_1557 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.COMMON_CFG[27] 01_1557 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.COMMON_CFG[28] 00_1558 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.COMMON_CFG[29] 01_1558 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.COMMON_CFG[30] 00_1559 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.COMMON_CFG[31] 01_1559 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.ENABLE_DRP 00_1613 01_1613 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.IBUFDS_GTE2.CLKSWING_CFG[0] 01_1581 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.IBUFDS_GTE2.CLKSWING_CFG[1] 00_1582 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.IN_USE 00_1584 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.INV_DRPCLK 00_1516 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.INV_PLL0LOCKDETCLK 01_1512 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.INV_PLL1LOCKDETCLK 00_1512 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL_CLKOUT_CFG[0] 00_1560 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL_CLKOUT_CFG[1] 01_1560 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL_CLKOUT_CFG[2] 00_1561 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL_CLKOUT_CFG[3] 01_1561 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL_CLKOUT_CFG[4] 00_1562 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL_CLKOUT_CFG[5] 01_1562 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL_CLKOUT_CFG[6] 00_1563 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL_CLKOUT_CFG[7] 01_1563 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.RSVD_ATTR0[0] 00_1488 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.RSVD_ATTR0[1] 01_1488 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.RSVD_ATTR0[2] 00_1489 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.RSVD_ATTR0[3] 01_1489 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.RSVD_ATTR0[4] 00_1490 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.RSVD_ATTR0[5] 01_1490 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.RSVD_ATTR0[6] 00_1491 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.RSVD_ATTR0[7] 01_1491 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.RSVD_ATTR0[8] 00_1492 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.RSVD_ATTR0[9] 01_1492 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.RSVD_ATTR0[10] 00_1493 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.RSVD_ATTR0[11] 01_1493 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.RSVD_ATTR0[12] 00_1494 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.RSVD_ATTR0[13] 01_1494 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.RSVD_ATTR0[14] 00_1495 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.RSVD_ATTR0[15] 01_1495 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.RSVD_ATTR1[0] 00_1728 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.RSVD_ATTR1[1] 01_1728 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.RSVD_ATTR1[2] 00_1729 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.RSVD_ATTR1[3] 01_1729 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.RSVD_ATTR1[4] 00_1730 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.RSVD_ATTR1[5] 01_1730 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.RSVD_ATTR1[6] 00_1731 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.RSVD_ATTR1[7] 01_1731 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.RSVD_ATTR1[8] 00_1732 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.RSVD_ATTR1[9] 01_1732 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.RSVD_ATTR1[10] 00_1733 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.RSVD_ATTR1[11] 01_1733 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.RSVD_ATTR1[12] 00_1734 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.RSVD_ATTR1[13] 01_1734 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.RSVD_ATTR1[14] 00_1735 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.RSVD_ATTR1[15] 01_1735 GTP_COMMON_MID_RIGHT.GTPE2_COMMON_RXOUTCLK_MUX_0.GTPE2_COMMON_RXOUTCLK_0 06_1628 GTP_COMMON_MID_RIGHT.GTPE2_COMMON_RXOUTCLK_MUX_1.GTPE2_COMMON_RXOUTCLK_1 07_1627 GTP_COMMON_MID_RIGHT.GTPE2_COMMON_RXOUTCLK_MUX_2.GTPE2_COMMON_RXOUTCLK_2 07_1630 @@ -282,181 +326,137 @@ GTP_COMMON_MID_RIGHT.GTPE2_COMMON_TXOUTCLK_MUX_0.GTPE2_COMMON_TXOUTCLK_0 06_1629 GTP_COMMON_MID_RIGHT.GTPE2_COMMON_TXOUTCLK_MUX_1.GTPE2_COMMON_TXOUTCLK_1 07_1628 GTP_COMMON_MID_RIGHT.GTPE2_COMMON_TXOUTCLK_MUX_2.GTPE2_COMMON_TXOUTCLK_2 07_1631 GTP_COMMON_MID_RIGHT.GTPE2_COMMON_TXOUTCLK_MUX_3.GTPE2_COMMON_TXOUTCLK_3 06_1631 -GTP_COMMON_MID_RIGHT.GTPE2.IN_USE 00_1584 -GTP_COMMON_MID_RIGHT.GTPE2.PLL_CLKOUT_CFG[0] 00_1560 -GTP_COMMON_MID_RIGHT.GTPE2.PLL_CLKOUT_CFG[1] 01_1560 -GTP_COMMON_MID_RIGHT.GTPE2.PLL_CLKOUT_CFG[2] 00_1561 -GTP_COMMON_MID_RIGHT.GTPE2.PLL_CLKOUT_CFG[3] 01_1561 -GTP_COMMON_MID_RIGHT.GTPE2.PLL_CLKOUT_CFG[4] 00_1562 -GTP_COMMON_MID_RIGHT.GTPE2.PLL_CLKOUT_CFG[5] 01_1562 -GTP_COMMON_MID_RIGHT.GTPE2.PLL_CLKOUT_CFG[6] 00_1563 -GTP_COMMON_MID_RIGHT.GTPE2.PLL_CLKOUT_CFG[7] 01_1563 -GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR0[0] 00_1488 -GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR0[1] 01_1488 -GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR0[2] 00_1489 -GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR0[3] 01_1489 -GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR0[4] 00_1490 -GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR0[5] 01_1490 -GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR0[6] 00_1491 -GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR0[7] 01_1491 -GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR0[8] 00_1492 -GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR0[9] 01_1492 -GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR0[10] 00_1493 -GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR0[11] 01_1493 -GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR0[12] 00_1494 -GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR0[13] 01_1494 -GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR0[14] 00_1495 -GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR0[15] 01_1495 -GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR1[0] 00_1728 -GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR1[1] 01_1728 -GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR1[2] 00_1729 -GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR1[3] 01_1729 -GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR1[4] 00_1730 -GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR1[5] 01_1730 -GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR1[6] 00_1731 -GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR1[7] 01_1731 -GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR1[8] 00_1732 -GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR1[9] 01_1732 -GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR1[10] 00_1733 -GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR1[11] 01_1733 -GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR1[12] 00_1734 -GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR1[13] 01_1734 -GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR1[14] 00_1735 -GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR1[15] 01_1735 -GTP_COMMON_MID_RIGHT.GTPE2.ZINV_DRPCLK 00_1516 -GTP_COMMON_MID_RIGHT.GTPE2.ZINV_PLL0LOCKDETCLK 01_1512 -GTP_COMMON_MID_RIGHT.GTPE2.ZINV_PLL1LOCKDETCLK 00_1512 -GTP_COMMON_MID_RIGHT.GTPE2.GTREFCLK0_USED 00_1438 00_1806 -GTP_COMMON_MID_RIGHT.GTPE2.GTREFCLK1_USED 01_1438 01_1806 -GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[0] 00_1424 -GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[1] 01_1424 -GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[2] 00_1425 -GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[3] 01_1425 -GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[4] 00_1426 -GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[5] 01_1426 -GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[6] 00_1427 -GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[7] 01_1427 -GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[8] 00_1428 -GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[9] 01_1428 -GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[10] 00_1429 -GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[11] 01_1429 -GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[12] 00_1430 -GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[13] 01_1430 -GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[14] 00_1431 -GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[15] 01_1431 -GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[16] 00_1432 -GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[17] 01_1432 -GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[18] 00_1433 -GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[19] 01_1433 -GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[20] 00_1434 -GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[21] 01_1434 -GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[22] 00_1435 -GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[23] 01_1435 -GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[24] 00_1436 -GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[25] 01_1436 -GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[26] 00_1437 -GTP_COMMON_MID_RIGHT.GTPE2.PLL0_DMON_CFG[0] 00_1528 -GTP_COMMON_MID_RIGHT.GTPE2.PLL0_FBDIV[0] 00_1440 -GTP_COMMON_MID_RIGHT.GTPE2.PLL0_FBDIV[1] 01_1440 -GTP_COMMON_MID_RIGHT.GTPE2.PLL0_FBDIV[4] 00_1442 -GTP_COMMON_MID_RIGHT.GTPE2.PLL0_FBDIV_45[0] 01_1443 -GTP_COMMON_MID_RIGHT.GTPE2.PLL0_INIT_CFG[0] 00_1456 -GTP_COMMON_MID_RIGHT.GTPE2.PLL0_INIT_CFG[1] 01_1456 -GTP_COMMON_MID_RIGHT.GTPE2.PLL0_INIT_CFG[2] 00_1457 -GTP_COMMON_MID_RIGHT.GTPE2.PLL0_INIT_CFG[3] 01_1457 -GTP_COMMON_MID_RIGHT.GTPE2.PLL0_INIT_CFG[4] 00_1458 -GTP_COMMON_MID_RIGHT.GTPE2.PLL0_INIT_CFG[5] 01_1458 -GTP_COMMON_MID_RIGHT.GTPE2.PLL0_INIT_CFG[6] 00_1459 -GTP_COMMON_MID_RIGHT.GTPE2.PLL0_INIT_CFG[7] 01_1459 -GTP_COMMON_MID_RIGHT.GTPE2.PLL0_INIT_CFG[8] 00_1460 -GTP_COMMON_MID_RIGHT.GTPE2.PLL0_INIT_CFG[9] 01_1460 -GTP_COMMON_MID_RIGHT.GTPE2.PLL0_INIT_CFG[10] 00_1461 -GTP_COMMON_MID_RIGHT.GTPE2.PLL0_INIT_CFG[11] 01_1461 -GTP_COMMON_MID_RIGHT.GTPE2.PLL0_INIT_CFG[12] 00_1462 -GTP_COMMON_MID_RIGHT.GTPE2.PLL0_INIT_CFG[13] 01_1462 -GTP_COMMON_MID_RIGHT.GTPE2.PLL0_INIT_CFG[14] 00_1463 -GTP_COMMON_MID_RIGHT.GTPE2.PLL0_INIT_CFG[15] 01_1463 -GTP_COMMON_MID_RIGHT.GTPE2.PLL0_INIT_CFG[16] 00_1464 -GTP_COMMON_MID_RIGHT.GTPE2.PLL0_INIT_CFG[17] 01_1464 -GTP_COMMON_MID_RIGHT.GTPE2.PLL0_INIT_CFG[18] 00_1465 -GTP_COMMON_MID_RIGHT.GTPE2.PLL0_INIT_CFG[19] 01_1465 -GTP_COMMON_MID_RIGHT.GTPE2.PLL0_INIT_CFG[20] 00_1466 -GTP_COMMON_MID_RIGHT.GTPE2.PLL0_INIT_CFG[21] 01_1466 -GTP_COMMON_MID_RIGHT.GTPE2.PLL0_INIT_CFG[22] 00_1467 -GTP_COMMON_MID_RIGHT.GTPE2.PLL0_INIT_CFG[23] 01_1467 -GTP_COMMON_MID_RIGHT.GTPE2.PLL0_LOCK_CFG[0] 00_1448 -GTP_COMMON_MID_RIGHT.GTPE2.PLL0_LOCK_CFG[1] 01_1448 -GTP_COMMON_MID_RIGHT.GTPE2.PLL0_LOCK_CFG[2] 00_1449 -GTP_COMMON_MID_RIGHT.GTPE2.PLL0_LOCK_CFG[3] 01_1449 -GTP_COMMON_MID_RIGHT.GTPE2.PLL0_LOCK_CFG[4] 00_1450 -GTP_COMMON_MID_RIGHT.GTPE2.PLL0_LOCK_CFG[5] 01_1450 -GTP_COMMON_MID_RIGHT.GTPE2.PLL0_LOCK_CFG[6] 00_1451 -GTP_COMMON_MID_RIGHT.GTPE2.PLL0_LOCK_CFG[7] 01_1451 -GTP_COMMON_MID_RIGHT.GTPE2.PLL0_LOCK_CFG[8] 00_1452 -GTP_COMMON_MID_RIGHT.GTPE2.PLL0_REFCLK_DIV[4] 01_1446 -GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[0] 00_1792 -GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[1] 01_1792 -GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[2] 00_1793 -GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[3] 01_1793 -GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[4] 00_1794 -GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[5] 01_1794 -GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[6] 00_1795 -GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[7] 01_1795 -GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[8] 00_1796 -GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[9] 01_1796 -GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[10] 00_1797 -GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[11] 01_1797 -GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[12] 00_1798 -GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[13] 01_1798 -GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[14] 00_1799 -GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[15] 01_1799 -GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[16] 00_1800 -GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[17] 01_1800 -GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[18] 00_1801 -GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[19] 01_1801 -GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[20] 00_1802 -GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[21] 01_1802 -GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[22] 00_1803 -GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[23] 01_1803 -GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[24] 00_1804 -GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[25] 01_1804 -GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[26] 00_1805 -GTP_COMMON_MID_RIGHT.GTPE2.PLL1_DMON_CFG[0] 01_1528 -GTP_COMMON_MID_RIGHT.GTPE2.PLL1_FBDIV[0] 00_1784 -GTP_COMMON_MID_RIGHT.GTPE2.PLL1_FBDIV[1] 01_1784 -GTP_COMMON_MID_RIGHT.GTPE2.PLL1_FBDIV[4] 00_1786 -GTP_COMMON_MID_RIGHT.GTPE2.PLL1_FBDIV_45[0] 01_1787 -GTP_COMMON_MID_RIGHT.GTPE2.PLL1_INIT_CFG[0] 00_1760 -GTP_COMMON_MID_RIGHT.GTPE2.PLL1_INIT_CFG[1] 01_1760 -GTP_COMMON_MID_RIGHT.GTPE2.PLL1_INIT_CFG[2] 00_1761 -GTP_COMMON_MID_RIGHT.GTPE2.PLL1_INIT_CFG[3] 01_1761 -GTP_COMMON_MID_RIGHT.GTPE2.PLL1_INIT_CFG[4] 00_1762 -GTP_COMMON_MID_RIGHT.GTPE2.PLL1_INIT_CFG[5] 01_1762 -GTP_COMMON_MID_RIGHT.GTPE2.PLL1_INIT_CFG[6] 00_1763 -GTP_COMMON_MID_RIGHT.GTPE2.PLL1_INIT_CFG[7] 01_1763 -GTP_COMMON_MID_RIGHT.GTPE2.PLL1_INIT_CFG[8] 00_1764 -GTP_COMMON_MID_RIGHT.GTPE2.PLL1_INIT_CFG[9] 01_1764 -GTP_COMMON_MID_RIGHT.GTPE2.PLL1_INIT_CFG[10] 00_1765 -GTP_COMMON_MID_RIGHT.GTPE2.PLL1_INIT_CFG[11] 01_1765 -GTP_COMMON_MID_RIGHT.GTPE2.PLL1_INIT_CFG[12] 00_1766 -GTP_COMMON_MID_RIGHT.GTPE2.PLL1_INIT_CFG[13] 01_1766 -GTP_COMMON_MID_RIGHT.GTPE2.PLL1_INIT_CFG[14] 00_1767 -GTP_COMMON_MID_RIGHT.GTPE2.PLL1_INIT_CFG[15] 01_1767 -GTP_COMMON_MID_RIGHT.GTPE2.PLL1_INIT_CFG[16] 00_1768 -GTP_COMMON_MID_RIGHT.GTPE2.PLL1_INIT_CFG[17] 01_1768 -GTP_COMMON_MID_RIGHT.GTPE2.PLL1_INIT_CFG[18] 00_1769 -GTP_COMMON_MID_RIGHT.GTPE2.PLL1_INIT_CFG[19] 01_1769 -GTP_COMMON_MID_RIGHT.GTPE2.PLL1_INIT_CFG[20] 00_1770 -GTP_COMMON_MID_RIGHT.GTPE2.PLL1_INIT_CFG[21] 01_1770 -GTP_COMMON_MID_RIGHT.GTPE2.PLL1_INIT_CFG[22] 00_1771 -GTP_COMMON_MID_RIGHT.GTPE2.PLL1_INIT_CFG[23] 01_1771 -GTP_COMMON_MID_RIGHT.GTPE2.PLL1_LOCK_CFG[0] 00_1776 -GTP_COMMON_MID_RIGHT.GTPE2.PLL1_LOCK_CFG[1] 01_1776 -GTP_COMMON_MID_RIGHT.GTPE2.PLL1_LOCK_CFG[2] 00_1777 -GTP_COMMON_MID_RIGHT.GTPE2.PLL1_LOCK_CFG[3] 01_1777 -GTP_COMMON_MID_RIGHT.GTPE2.PLL1_LOCK_CFG[4] 00_1778 -GTP_COMMON_MID_RIGHT.GTPE2.PLL1_LOCK_CFG[5] 01_1778 -GTP_COMMON_MID_RIGHT.GTPE2.PLL1_LOCK_CFG[6] 00_1779 -GTP_COMMON_MID_RIGHT.GTPE2.PLL1_LOCK_CFG[7] 01_1779 -GTP_COMMON_MID_RIGHT.GTPE2.PLL1_LOCK_CFG[8] 00_1780 -GTP_COMMON_MID_RIGHT.GTPE2.PLL1_REFCLK_DIV[4] 01_1790 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.GTREFCLK0_USED 00_1438 00_1806 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.GTREFCLK1_USED 01_1438 01_1806 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_CFG[0] 00_1424 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_CFG[1] 01_1424 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_CFG[2] 00_1425 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_CFG[3] 01_1425 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_CFG[4] 00_1426 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_CFG[5] 01_1426 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_CFG[6] 00_1427 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_CFG[7] 01_1427 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_CFG[8] 00_1428 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_CFG[9] 01_1428 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_CFG[10] 00_1429 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_CFG[11] 01_1429 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_CFG[12] 00_1430 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_CFG[13] 01_1430 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_CFG[14] 00_1431 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_CFG[15] 01_1431 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_CFG[16] 00_1432 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_CFG[17] 01_1432 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_CFG[18] 00_1433 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_CFG[19] 01_1433 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_CFG[20] 00_1434 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_CFG[21] 01_1434 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_CFG[22] 00_1435 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_CFG[23] 01_1435 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_CFG[24] 00_1436 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_CFG[25] 01_1436 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_CFG[26] 00_1437 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_DMON_CFG[0] 00_1528 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_FBDIV[0] 00_1440 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_FBDIV[1] 01_1440 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_FBDIV[4] 00_1442 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_FBDIV_45[0] 01_1443 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_INIT_CFG[0] 00_1456 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_INIT_CFG[1] 01_1456 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_INIT_CFG[2] 00_1457 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_INIT_CFG[3] 01_1457 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_INIT_CFG[4] 00_1458 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_INIT_CFG[5] 01_1458 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_INIT_CFG[6] 00_1459 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_INIT_CFG[7] 01_1459 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_INIT_CFG[8] 00_1460 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_INIT_CFG[9] 01_1460 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_INIT_CFG[10] 00_1461 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_INIT_CFG[11] 01_1461 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_INIT_CFG[12] 00_1462 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_INIT_CFG[13] 01_1462 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_INIT_CFG[14] 00_1463 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_INIT_CFG[15] 01_1463 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_INIT_CFG[16] 00_1464 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_INIT_CFG[17] 01_1464 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_INIT_CFG[18] 00_1465 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_INIT_CFG[19] 01_1465 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_INIT_CFG[20] 00_1466 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_INIT_CFG[21] 01_1466 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_INIT_CFG[22] 00_1467 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_INIT_CFG[23] 01_1467 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_LOCK_CFG[0] 00_1448 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_LOCK_CFG[1] 01_1448 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_LOCK_CFG[2] 00_1449 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_LOCK_CFG[3] 01_1449 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_LOCK_CFG[4] 00_1450 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_LOCK_CFG[5] 01_1450 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_LOCK_CFG[6] 00_1451 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_LOCK_CFG[7] 01_1451 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_LOCK_CFG[8] 00_1452 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_REFCLK_DIV[4] 01_1446 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_CFG[0] 00_1792 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_CFG[1] 01_1792 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_CFG[2] 00_1793 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_CFG[3] 01_1793 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_CFG[4] 00_1794 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_CFG[5] 01_1794 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_CFG[6] 00_1795 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_CFG[7] 01_1795 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_CFG[8] 00_1796 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_CFG[9] 01_1796 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_CFG[10] 00_1797 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_CFG[11] 01_1797 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_CFG[12] 00_1798 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_CFG[13] 01_1798 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_CFG[14] 00_1799 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_CFG[15] 01_1799 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_CFG[16] 00_1800 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_CFG[17] 01_1800 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_CFG[18] 00_1801 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_CFG[19] 01_1801 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_CFG[20] 00_1802 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_CFG[21] 01_1802 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_CFG[22] 00_1803 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_CFG[23] 01_1803 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_CFG[24] 00_1804 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_CFG[25] 01_1804 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_CFG[26] 00_1805 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_DMON_CFG[0] 01_1528 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_FBDIV[0] 00_1784 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_FBDIV[1] 01_1784 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_FBDIV[4] 00_1786 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_FBDIV_45[0] 01_1787 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_INIT_CFG[0] 00_1760 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_INIT_CFG[1] 01_1760 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_INIT_CFG[2] 00_1761 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_INIT_CFG[3] 01_1761 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_INIT_CFG[4] 00_1762 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_INIT_CFG[5] 01_1762 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_INIT_CFG[6] 00_1763 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_INIT_CFG[7] 01_1763 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_INIT_CFG[8] 00_1764 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_INIT_CFG[9] 01_1764 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_INIT_CFG[10] 00_1765 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_INIT_CFG[11] 01_1765 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_INIT_CFG[12] 00_1766 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_INIT_CFG[13] 01_1766 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_INIT_CFG[14] 00_1767 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_INIT_CFG[15] 01_1767 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_INIT_CFG[16] 00_1768 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_INIT_CFG[17] 01_1768 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_INIT_CFG[18] 00_1769 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_INIT_CFG[19] 01_1769 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_INIT_CFG[20] 00_1770 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_INIT_CFG[21] 01_1770 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_INIT_CFG[22] 00_1771 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_INIT_CFG[23] 01_1771 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_LOCK_CFG[0] 00_1776 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_LOCK_CFG[1] 01_1776 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_LOCK_CFG[2] 00_1777 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_LOCK_CFG[3] 01_1777 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_LOCK_CFG[4] 00_1778 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_LOCK_CFG[5] 01_1778 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_LOCK_CFG[6] 00_1779 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_LOCK_CFG[7] 01_1779 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_LOCK_CFG[8] 00_1780 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_REFCLK_DIV[4] 01_1790 diff --git a/artix7/segbits_gtp_common_mid_right.origin_info.db b/artix7/segbits_gtp_common_mid_right.origin_info.db index d4f434c..4c8e4b1 100644 --- a/artix7/segbits_gtp_common_mid_right.origin_info.db +++ b/artix7/segbits_gtp_common_mid_right.origin_info.db @@ -1,4 +1,3 @@ -GTP_COMMON_MID_RIGHT.ENABLE_DRP origin:063-gtp-common-conf 00_1613 01_1613 GTP_COMMON_MID_RIGHT.HCLK_GTP_CK_IN0.HCLK_GTP_CK_MUX0 origin:065b-gtp-common-pips 02_1614 03_1617 03_1622 GTP_COMMON_MID_RIGHT.HCLK_GTP_CK_IN0.HCLK_GTP_CK_MUX1 origin:065b-gtp-common-pips 02_1614 02_1622 03_1616 GTP_COMMON_MID_RIGHT.HCLK_GTP_CK_IN0.IBUFDS_GTPE2_0_MGTCLKOUT_MUX origin:065-gtp-common-pips 02_1615 03_1617 @@ -167,8 +166,6 @@ GTP_COMMON_MID_RIGHT.HCLK_GTP_CK_IN13.GTPE2_COMMON_TXOUTCLK_MUX_0 origin:065-gtp GTP_COMMON_MID_RIGHT.HCLK_GTP_CK_IN13.GTPE2_COMMON_TXOUTCLK_MUX_1 origin:065-gtp-common-pips 06_1620 07_1617 GTP_COMMON_MID_RIGHT.HCLK_GTP_CK_IN13.GTPE2_COMMON_TXOUTCLK_MUX_2 origin:065-gtp-common-pips 06_1623 07_1616 GTP_COMMON_MID_RIGHT.HCLK_GTP_CK_IN13.GTPE2_COMMON_TXOUTCLK_MUX_3 origin:065-gtp-common-pips 06_1620 07_1616 -GTP_COMMON_MID_RIGHT.IBUFDS_GTE2.CLKCM_CFG[0] origin:063-gtp-common-conf 01_1581 -GTP_COMMON_MID_RIGHT.IBUFDS_GTE2.CLKCM_CFG[1] origin:063-gtp-common-conf 00_1582 GTP_COMMON_MID_RIGHT.IBUFDS_GTE2_Y0.CLKCM_CFG origin:063-gtp-common-conf 00_1580 GTP_COMMON_MID_RIGHT.IBUFDS_GTE2_Y0.CLKRCV_TRST origin:063-gtp-common-conf 00_1576 GTP_COMMON_MID_RIGHT.IBUFDS_GTE2_Y0.IN_USE origin:063-gtp-common-conf 00_1578 @@ -177,103 +174,150 @@ GTP_COMMON_MID_RIGHT.IBUFDS_GTE2_Y1.CLKRCV_TRST origin:063-gtp-common-conf 01_15 GTP_COMMON_MID_RIGHT.IBUFDS_GTE2_Y1.IN_USE origin:063-gtp-common-conf 00_1579 GTP_COMMON_MID_RIGHT.IBUFDS_GTPE2_0_MGTCLKOUT_MUX.IBUFDS_GTPE2_0_MGTCLKOUT origin:065-gtp-common-pips 07_1629 GTP_COMMON_MID_RIGHT.IBUFDS_GTPE2_1_MGTCLKOUT_MUX.IBUFDS_GTPE2_1_MGTCLKOUT origin:065-gtp-common-pips 06_1627 -GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[0] origin:063-gtp-common-conf 00_1640 -GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[1] origin:063-gtp-common-conf 01_1640 -GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[2] origin:063-gtp-common-conf 00_1641 -GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[3] origin:063-gtp-common-conf 01_1641 -GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[4] origin:063-gtp-common-conf 00_1642 -GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[5] origin:063-gtp-common-conf 01_1642 -GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[6] origin:063-gtp-common-conf 00_1643 -GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[7] origin:063-gtp-common-conf 01_1643 -GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[8] origin:063-gtp-common-conf 00_1644 -GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[9] origin:063-gtp-common-conf 01_1644 -GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[10] origin:063-gtp-common-conf 00_1645 -GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[11] origin:063-gtp-common-conf 01_1645 -GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[12] origin:063-gtp-common-conf 00_1646 -GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[13] origin:063-gtp-common-conf 01_1646 -GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[14] origin:063-gtp-common-conf 00_1647 -GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[15] origin:063-gtp-common-conf 01_1647 -GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[16] origin:063-gtp-common-conf 00_1648 -GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[17] origin:063-gtp-common-conf 01_1648 -GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[18] origin:063-gtp-common-conf 00_1649 -GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[19] origin:063-gtp-common-conf 01_1649 -GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[20] origin:063-gtp-common-conf 00_1650 -GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[21] origin:063-gtp-common-conf 01_1650 -GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[22] origin:063-gtp-common-conf 00_1651 -GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[23] origin:063-gtp-common-conf 01_1651 -GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[24] origin:063-gtp-common-conf 00_1652 -GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[25] origin:063-gtp-common-conf 01_1652 -GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[26] origin:063-gtp-common-conf 00_1653 -GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[27] origin:063-gtp-common-conf 01_1653 -GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[28] origin:063-gtp-common-conf 00_1654 -GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[29] origin:063-gtp-common-conf 01_1654 -GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[30] origin:063-gtp-common-conf 00_1655 -GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[31] origin:063-gtp-common-conf 01_1655 -GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[32] origin:063-gtp-common-conf 00_1656 -GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[33] origin:063-gtp-common-conf 01_1656 -GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[34] origin:063-gtp-common-conf 00_1657 -GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[35] origin:063-gtp-common-conf 01_1657 -GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[36] origin:063-gtp-common-conf 00_1658 -GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[37] origin:063-gtp-common-conf 01_1658 -GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[38] origin:063-gtp-common-conf 00_1659 -GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[39] origin:063-gtp-common-conf 01_1659 -GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[40] origin:063-gtp-common-conf 00_1660 -GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[41] origin:063-gtp-common-conf 01_1660 -GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[42] origin:063-gtp-common-conf 00_1661 -GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[43] origin:063-gtp-common-conf 01_1661 -GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[44] origin:063-gtp-common-conf 00_1662 -GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[45] origin:063-gtp-common-conf 01_1662 -GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[46] origin:063-gtp-common-conf 00_1663 -GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[47] origin:063-gtp-common-conf 01_1663 -GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[48] origin:063-gtp-common-conf 00_1664 -GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[49] origin:063-gtp-common-conf 01_1664 -GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[50] origin:063-gtp-common-conf 00_1665 -GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[51] origin:063-gtp-common-conf 01_1665 -GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[52] origin:063-gtp-common-conf 00_1666 -GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[53] origin:063-gtp-common-conf 01_1666 -GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[54] origin:063-gtp-common-conf 00_1667 -GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[55] origin:063-gtp-common-conf 01_1667 -GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[56] origin:063-gtp-common-conf 00_1668 -GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[57] origin:063-gtp-common-conf 01_1668 -GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[58] origin:063-gtp-common-conf 00_1669 -GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[59] origin:063-gtp-common-conf 01_1669 -GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[60] origin:063-gtp-common-conf 00_1670 -GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[61] origin:063-gtp-common-conf 01_1670 -GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[62] origin:063-gtp-common-conf 00_1671 -GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[63] origin:063-gtp-common-conf 01_1671 -GTP_COMMON_MID_RIGHT.GTPE2.BOTH_GTREFCLK_USED origin:063-gtp-common-conf 01_1439 01_1807 -GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[0] origin:063-gtp-common-conf 00_1544 -GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[1] origin:063-gtp-common-conf 01_1544 -GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[2] origin:063-gtp-common-conf 00_1545 -GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[3] origin:063-gtp-common-conf 01_1545 -GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[4] origin:063-gtp-common-conf 00_1546 -GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[5] origin:063-gtp-common-conf 01_1546 -GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[6] origin:063-gtp-common-conf 00_1547 -GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[7] origin:063-gtp-common-conf 01_1547 -GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[8] origin:063-gtp-common-conf 00_1548 -GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[9] origin:063-gtp-common-conf 01_1548 -GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[10] origin:063-gtp-common-conf 00_1549 -GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[11] origin:063-gtp-common-conf 01_1549 -GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[12] origin:063-gtp-common-conf 00_1550 -GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[13] origin:063-gtp-common-conf 01_1550 -GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[14] origin:063-gtp-common-conf 00_1551 -GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[15] origin:063-gtp-common-conf 01_1551 -GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[16] origin:063-gtp-common-conf 00_1552 -GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[17] origin:063-gtp-common-conf 01_1552 -GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[18] origin:063-gtp-common-conf 00_1553 -GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[19] origin:063-gtp-common-conf 01_1553 -GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[20] origin:063-gtp-common-conf 00_1554 -GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[21] origin:063-gtp-common-conf 01_1554 -GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[22] origin:063-gtp-common-conf 00_1555 -GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[23] origin:063-gtp-common-conf 01_1555 -GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[24] origin:063-gtp-common-conf 00_1556 -GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[25] origin:063-gtp-common-conf 01_1556 -GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[26] origin:063-gtp-common-conf 00_1557 -GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[27] origin:063-gtp-common-conf 01_1557 -GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[28] origin:063-gtp-common-conf 00_1558 -GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[29] origin:063-gtp-common-conf 01_1558 -GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[30] origin:063-gtp-common-conf 00_1559 -GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[31] origin:063-gtp-common-conf 01_1559 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[0] origin:063-gtp-common-conf 00_1640 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[1] origin:063-gtp-common-conf 01_1640 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[2] origin:063-gtp-common-conf 00_1641 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[3] origin:063-gtp-common-conf 01_1641 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[4] origin:063-gtp-common-conf 00_1642 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[5] origin:063-gtp-common-conf 01_1642 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[6] origin:063-gtp-common-conf 00_1643 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[7] origin:063-gtp-common-conf 01_1643 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[8] origin:063-gtp-common-conf 00_1644 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[9] origin:063-gtp-common-conf 01_1644 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[10] origin:063-gtp-common-conf 00_1645 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[11] origin:063-gtp-common-conf 01_1645 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[12] origin:063-gtp-common-conf 00_1646 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[13] origin:063-gtp-common-conf 01_1646 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[14] origin:063-gtp-common-conf 00_1647 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[15] origin:063-gtp-common-conf 01_1647 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[16] origin:063-gtp-common-conf 00_1648 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[17] origin:063-gtp-common-conf 01_1648 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[18] origin:063-gtp-common-conf 00_1649 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[19] origin:063-gtp-common-conf 01_1649 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[20] origin:063-gtp-common-conf 00_1650 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[21] origin:063-gtp-common-conf 01_1650 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[22] origin:063-gtp-common-conf 00_1651 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[23] origin:063-gtp-common-conf 01_1651 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[24] origin:063-gtp-common-conf 00_1652 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[25] origin:063-gtp-common-conf 01_1652 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[26] origin:063-gtp-common-conf 00_1653 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[27] origin:063-gtp-common-conf 01_1653 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[28] origin:063-gtp-common-conf 00_1654 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[29] origin:063-gtp-common-conf 01_1654 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[30] origin:063-gtp-common-conf 00_1655 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[31] origin:063-gtp-common-conf 01_1655 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[32] origin:063-gtp-common-conf 00_1656 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[33] origin:063-gtp-common-conf 01_1656 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[34] origin:063-gtp-common-conf 00_1657 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[35] origin:063-gtp-common-conf 01_1657 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[36] origin:063-gtp-common-conf 00_1658 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[37] origin:063-gtp-common-conf 01_1658 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[38] origin:063-gtp-common-conf 00_1659 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[39] origin:063-gtp-common-conf 01_1659 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[40] origin:063-gtp-common-conf 00_1660 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[41] origin:063-gtp-common-conf 01_1660 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[42] origin:063-gtp-common-conf 00_1661 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[43] origin:063-gtp-common-conf 01_1661 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[44] origin:063-gtp-common-conf 00_1662 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[45] origin:063-gtp-common-conf 01_1662 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[46] origin:063-gtp-common-conf 00_1663 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[47] origin:063-gtp-common-conf 01_1663 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[48] origin:063-gtp-common-conf 00_1664 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[49] origin:063-gtp-common-conf 01_1664 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[50] origin:063-gtp-common-conf 00_1665 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[51] origin:063-gtp-common-conf 01_1665 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[52] origin:063-gtp-common-conf 00_1666 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[53] origin:063-gtp-common-conf 01_1666 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[54] origin:063-gtp-common-conf 00_1667 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[55] origin:063-gtp-common-conf 01_1667 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[56] origin:063-gtp-common-conf 00_1668 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[57] origin:063-gtp-common-conf 01_1668 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[58] origin:063-gtp-common-conf 00_1669 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[59] origin:063-gtp-common-conf 01_1669 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[60] origin:063-gtp-common-conf 00_1670 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[61] origin:063-gtp-common-conf 01_1670 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[62] origin:063-gtp-common-conf 00_1671 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BIAS_CFG[63] origin:063-gtp-common-conf 01_1671 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.BOTH_GTREFCLK_USED origin:063-gtp-common-conf 01_1439 01_1807 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.COMMON_CFG[0] origin:063-gtp-common-conf 00_1544 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.COMMON_CFG[1] origin:063-gtp-common-conf 01_1544 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.COMMON_CFG[2] origin:063-gtp-common-conf 00_1545 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.COMMON_CFG[3] origin:063-gtp-common-conf 01_1545 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.COMMON_CFG[4] origin:063-gtp-common-conf 00_1546 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.COMMON_CFG[5] origin:063-gtp-common-conf 01_1546 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.COMMON_CFG[6] origin:063-gtp-common-conf 00_1547 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.COMMON_CFG[7] origin:063-gtp-common-conf 01_1547 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.COMMON_CFG[8] origin:063-gtp-common-conf 00_1548 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.COMMON_CFG[9] origin:063-gtp-common-conf 01_1548 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.COMMON_CFG[10] origin:063-gtp-common-conf 00_1549 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.COMMON_CFG[11] origin:063-gtp-common-conf 01_1549 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.COMMON_CFG[12] origin:063-gtp-common-conf 00_1550 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.COMMON_CFG[13] origin:063-gtp-common-conf 01_1550 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.COMMON_CFG[14] origin:063-gtp-common-conf 00_1551 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.COMMON_CFG[15] origin:063-gtp-common-conf 01_1551 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.COMMON_CFG[16] origin:063-gtp-common-conf 00_1552 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.COMMON_CFG[17] origin:063-gtp-common-conf 01_1552 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.COMMON_CFG[18] origin:063-gtp-common-conf 00_1553 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.COMMON_CFG[19] origin:063-gtp-common-conf 01_1553 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.COMMON_CFG[20] origin:063-gtp-common-conf 00_1554 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.COMMON_CFG[21] origin:063-gtp-common-conf 01_1554 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.COMMON_CFG[22] origin:063-gtp-common-conf 00_1555 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.COMMON_CFG[23] origin:063-gtp-common-conf 01_1555 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.COMMON_CFG[24] origin:063-gtp-common-conf 00_1556 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.COMMON_CFG[25] origin:063-gtp-common-conf 01_1556 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.COMMON_CFG[26] origin:063-gtp-common-conf 00_1557 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.COMMON_CFG[27] origin:063-gtp-common-conf 01_1557 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.COMMON_CFG[28] origin:063-gtp-common-conf 00_1558 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.COMMON_CFG[29] origin:063-gtp-common-conf 01_1558 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.COMMON_CFG[30] origin:063-gtp-common-conf 00_1559 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.COMMON_CFG[31] origin:063-gtp-common-conf 01_1559 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.ENABLE_DRP origin:063-gtp-common-conf 00_1613 01_1613 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.IBUFDS_GTE2.CLKSWING_CFG[0] origin:063-gtp-common-conf 01_1581 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.IBUFDS_GTE2.CLKSWING_CFG[1] origin:063-gtp-common-conf 00_1582 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.IN_USE origin:063-gtp-common-conf 00_1584 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.INV_DRPCLK origin:063-gtp-common-conf 00_1516 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.INV_PLL0LOCKDETCLK origin:063-gtp-common-conf 01_1512 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.INV_PLL1LOCKDETCLK origin:063-gtp-common-conf 00_1512 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL_CLKOUT_CFG[0] origin:063-gtp-common-conf 00_1560 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL_CLKOUT_CFG[1] origin:063-gtp-common-conf 01_1560 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL_CLKOUT_CFG[2] origin:063-gtp-common-conf 00_1561 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL_CLKOUT_CFG[3] origin:063-gtp-common-conf 01_1561 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL_CLKOUT_CFG[4] origin:063-gtp-common-conf 00_1562 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL_CLKOUT_CFG[5] origin:063-gtp-common-conf 01_1562 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL_CLKOUT_CFG[6] origin:063-gtp-common-conf 00_1563 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL_CLKOUT_CFG[7] origin:063-gtp-common-conf 01_1563 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.RSVD_ATTR0[0] origin:063-gtp-common-conf 00_1488 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.RSVD_ATTR0[1] origin:063-gtp-common-conf 01_1488 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.RSVD_ATTR0[2] origin:063-gtp-common-conf 00_1489 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.RSVD_ATTR0[3] origin:063-gtp-common-conf 01_1489 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.RSVD_ATTR0[4] origin:063-gtp-common-conf 00_1490 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.RSVD_ATTR0[5] origin:063-gtp-common-conf 01_1490 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.RSVD_ATTR0[6] origin:063-gtp-common-conf 00_1491 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.RSVD_ATTR0[7] origin:063-gtp-common-conf 01_1491 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.RSVD_ATTR0[8] origin:063-gtp-common-conf 00_1492 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.RSVD_ATTR0[9] origin:063-gtp-common-conf 01_1492 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.RSVD_ATTR0[10] origin:063-gtp-common-conf 00_1493 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.RSVD_ATTR0[11] origin:063-gtp-common-conf 01_1493 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.RSVD_ATTR0[12] origin:063-gtp-common-conf 00_1494 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.RSVD_ATTR0[13] origin:063-gtp-common-conf 01_1494 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.RSVD_ATTR0[14] origin:063-gtp-common-conf 00_1495 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.RSVD_ATTR0[15] origin:063-gtp-common-conf 01_1495 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.RSVD_ATTR1[0] origin:063-gtp-common-conf 00_1728 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.RSVD_ATTR1[1] origin:063-gtp-common-conf 01_1728 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.RSVD_ATTR1[2] origin:063-gtp-common-conf 00_1729 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.RSVD_ATTR1[3] origin:063-gtp-common-conf 01_1729 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.RSVD_ATTR1[4] origin:063-gtp-common-conf 00_1730 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.RSVD_ATTR1[5] origin:063-gtp-common-conf 01_1730 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.RSVD_ATTR1[6] origin:063-gtp-common-conf 00_1731 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.RSVD_ATTR1[7] origin:063-gtp-common-conf 01_1731 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.RSVD_ATTR1[8] origin:063-gtp-common-conf 00_1732 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.RSVD_ATTR1[9] origin:063-gtp-common-conf 01_1732 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.RSVD_ATTR1[10] origin:063-gtp-common-conf 00_1733 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.RSVD_ATTR1[11] origin:063-gtp-common-conf 01_1733 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.RSVD_ATTR1[12] origin:063-gtp-common-conf 00_1734 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.RSVD_ATTR1[13] origin:063-gtp-common-conf 01_1734 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.RSVD_ATTR1[14] origin:063-gtp-common-conf 00_1735 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.RSVD_ATTR1[15] origin:063-gtp-common-conf 01_1735 GTP_COMMON_MID_RIGHT.GTPE2_COMMON_RXOUTCLK_MUX_0.GTPE2_COMMON_RXOUTCLK_0 origin:065-gtp-common-pips 06_1628 GTP_COMMON_MID_RIGHT.GTPE2_COMMON_RXOUTCLK_MUX_1.GTPE2_COMMON_RXOUTCLK_1 origin:065-gtp-common-pips 07_1627 GTP_COMMON_MID_RIGHT.GTPE2_COMMON_RXOUTCLK_MUX_2.GTPE2_COMMON_RXOUTCLK_2 origin:065-gtp-common-pips 07_1630 @@ -282,181 +326,137 @@ GTP_COMMON_MID_RIGHT.GTPE2_COMMON_TXOUTCLK_MUX_0.GTPE2_COMMON_TXOUTCLK_0 origin: GTP_COMMON_MID_RIGHT.GTPE2_COMMON_TXOUTCLK_MUX_1.GTPE2_COMMON_TXOUTCLK_1 origin:065-gtp-common-pips 07_1628 GTP_COMMON_MID_RIGHT.GTPE2_COMMON_TXOUTCLK_MUX_2.GTPE2_COMMON_TXOUTCLK_2 origin:065-gtp-common-pips 07_1631 GTP_COMMON_MID_RIGHT.GTPE2_COMMON_TXOUTCLK_MUX_3.GTPE2_COMMON_TXOUTCLK_3 origin:065-gtp-common-pips 06_1631 -GTP_COMMON_MID_RIGHT.GTPE2.IN_USE origin:063-gtp-common-conf 00_1584 -GTP_COMMON_MID_RIGHT.GTPE2.PLL_CLKOUT_CFG[0] origin:063-gtp-common-conf 00_1560 -GTP_COMMON_MID_RIGHT.GTPE2.PLL_CLKOUT_CFG[1] origin:063-gtp-common-conf 01_1560 -GTP_COMMON_MID_RIGHT.GTPE2.PLL_CLKOUT_CFG[2] origin:063-gtp-common-conf 00_1561 -GTP_COMMON_MID_RIGHT.GTPE2.PLL_CLKOUT_CFG[3] origin:063-gtp-common-conf 01_1561 -GTP_COMMON_MID_RIGHT.GTPE2.PLL_CLKOUT_CFG[4] origin:063-gtp-common-conf 00_1562 -GTP_COMMON_MID_RIGHT.GTPE2.PLL_CLKOUT_CFG[5] origin:063-gtp-common-conf 01_1562 -GTP_COMMON_MID_RIGHT.GTPE2.PLL_CLKOUT_CFG[6] origin:063-gtp-common-conf 00_1563 -GTP_COMMON_MID_RIGHT.GTPE2.PLL_CLKOUT_CFG[7] origin:063-gtp-common-conf 01_1563 -GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR0[0] origin:063-gtp-common-conf 00_1488 -GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR0[1] origin:063-gtp-common-conf 01_1488 -GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR0[2] origin:063-gtp-common-conf 00_1489 -GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR0[3] origin:063-gtp-common-conf 01_1489 -GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR0[4] origin:063-gtp-common-conf 00_1490 -GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR0[5] origin:063-gtp-common-conf 01_1490 -GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR0[6] origin:063-gtp-common-conf 00_1491 -GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR0[7] origin:063-gtp-common-conf 01_1491 -GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR0[8] origin:063-gtp-common-conf 00_1492 -GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR0[9] origin:063-gtp-common-conf 01_1492 -GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR0[10] origin:063-gtp-common-conf 00_1493 -GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR0[11] origin:063-gtp-common-conf 01_1493 -GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR0[12] origin:063-gtp-common-conf 00_1494 -GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR0[13] origin:063-gtp-common-conf 01_1494 -GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR0[14] origin:063-gtp-common-conf 00_1495 -GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR0[15] origin:063-gtp-common-conf 01_1495 -GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR1[0] origin:063-gtp-common-conf 00_1728 -GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR1[1] origin:063-gtp-common-conf 01_1728 -GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR1[2] origin:063-gtp-common-conf 00_1729 -GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR1[3] origin:063-gtp-common-conf 01_1729 -GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR1[4] origin:063-gtp-common-conf 00_1730 -GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR1[5] origin:063-gtp-common-conf 01_1730 -GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR1[6] origin:063-gtp-common-conf 00_1731 -GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR1[7] origin:063-gtp-common-conf 01_1731 -GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR1[8] origin:063-gtp-common-conf 00_1732 -GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR1[9] origin:063-gtp-common-conf 01_1732 -GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR1[10] origin:063-gtp-common-conf 00_1733 -GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR1[11] origin:063-gtp-common-conf 01_1733 -GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR1[12] origin:063-gtp-common-conf 00_1734 -GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR1[13] origin:063-gtp-common-conf 01_1734 -GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR1[14] origin:063-gtp-common-conf 00_1735 -GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR1[15] origin:063-gtp-common-conf 01_1735 -GTP_COMMON_MID_RIGHT.GTPE2.ZINV_DRPCLK origin:063-gtp-common-conf 00_1516 -GTP_COMMON_MID_RIGHT.GTPE2.ZINV_PLL0LOCKDETCLK origin:063-gtp-common-conf 01_1512 -GTP_COMMON_MID_RIGHT.GTPE2.ZINV_PLL1LOCKDETCLK origin:063-gtp-common-conf 00_1512 -GTP_COMMON_MID_RIGHT.GTPE2.GTREFCLK0_USED origin:063-gtp-common-conf 00_1438 00_1806 -GTP_COMMON_MID_RIGHT.GTPE2.GTREFCLK1_USED origin:063-gtp-common-conf 01_1438 01_1806 -GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[0] origin:063-gtp-common-conf 00_1424 -GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[1] origin:063-gtp-common-conf 01_1424 -GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[2] origin:063-gtp-common-conf 00_1425 -GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[3] origin:063-gtp-common-conf 01_1425 -GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[4] origin:063-gtp-common-conf 00_1426 -GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[5] origin:063-gtp-common-conf 01_1426 -GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[6] origin:063-gtp-common-conf 00_1427 -GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[7] origin:063-gtp-common-conf 01_1427 -GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[8] origin:063-gtp-common-conf 00_1428 -GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[9] origin:063-gtp-common-conf 01_1428 -GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[10] origin:063-gtp-common-conf 00_1429 -GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[11] origin:063-gtp-common-conf 01_1429 -GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[12] origin:063-gtp-common-conf 00_1430 -GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[13] origin:063-gtp-common-conf 01_1430 -GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[14] origin:063-gtp-common-conf 00_1431 -GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[15] origin:063-gtp-common-conf 01_1431 -GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[16] origin:063-gtp-common-conf 00_1432 -GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[17] origin:063-gtp-common-conf 01_1432 -GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[18] origin:063-gtp-common-conf 00_1433 -GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[19] origin:063-gtp-common-conf 01_1433 -GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[20] origin:063-gtp-common-conf 00_1434 -GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[21] origin:063-gtp-common-conf 01_1434 -GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[22] origin:063-gtp-common-conf 00_1435 -GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[23] origin:063-gtp-common-conf 01_1435 -GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[24] origin:063-gtp-common-conf 00_1436 -GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[25] origin:063-gtp-common-conf 01_1436 -GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[26] origin:063-gtp-common-conf 00_1437 -GTP_COMMON_MID_RIGHT.GTPE2.PLL0_DMON_CFG[0] origin:063-gtp-common-conf 00_1528 -GTP_COMMON_MID_RIGHT.GTPE2.PLL0_FBDIV[0] origin:063-gtp-common-conf 00_1440 -GTP_COMMON_MID_RIGHT.GTPE2.PLL0_FBDIV[1] origin:063-gtp-common-conf 01_1440 -GTP_COMMON_MID_RIGHT.GTPE2.PLL0_FBDIV[4] origin:063-gtp-common-conf 00_1442 -GTP_COMMON_MID_RIGHT.GTPE2.PLL0_FBDIV_45[0] origin:063-gtp-common-conf 01_1443 -GTP_COMMON_MID_RIGHT.GTPE2.PLL0_INIT_CFG[0] origin:063-gtp-common-conf 00_1456 -GTP_COMMON_MID_RIGHT.GTPE2.PLL0_INIT_CFG[1] origin:063-gtp-common-conf 01_1456 -GTP_COMMON_MID_RIGHT.GTPE2.PLL0_INIT_CFG[2] origin:063-gtp-common-conf 00_1457 -GTP_COMMON_MID_RIGHT.GTPE2.PLL0_INIT_CFG[3] origin:063-gtp-common-conf 01_1457 -GTP_COMMON_MID_RIGHT.GTPE2.PLL0_INIT_CFG[4] origin:063-gtp-common-conf 00_1458 -GTP_COMMON_MID_RIGHT.GTPE2.PLL0_INIT_CFG[5] origin:063-gtp-common-conf 01_1458 -GTP_COMMON_MID_RIGHT.GTPE2.PLL0_INIT_CFG[6] origin:063-gtp-common-conf 00_1459 -GTP_COMMON_MID_RIGHT.GTPE2.PLL0_INIT_CFG[7] origin:063-gtp-common-conf 01_1459 -GTP_COMMON_MID_RIGHT.GTPE2.PLL0_INIT_CFG[8] origin:063-gtp-common-conf 00_1460 -GTP_COMMON_MID_RIGHT.GTPE2.PLL0_INIT_CFG[9] origin:063-gtp-common-conf 01_1460 -GTP_COMMON_MID_RIGHT.GTPE2.PLL0_INIT_CFG[10] origin:063-gtp-common-conf 00_1461 -GTP_COMMON_MID_RIGHT.GTPE2.PLL0_INIT_CFG[11] origin:063-gtp-common-conf 01_1461 -GTP_COMMON_MID_RIGHT.GTPE2.PLL0_INIT_CFG[12] origin:063-gtp-common-conf 00_1462 -GTP_COMMON_MID_RIGHT.GTPE2.PLL0_INIT_CFG[13] origin:063-gtp-common-conf 01_1462 -GTP_COMMON_MID_RIGHT.GTPE2.PLL0_INIT_CFG[14] origin:063-gtp-common-conf 00_1463 -GTP_COMMON_MID_RIGHT.GTPE2.PLL0_INIT_CFG[15] origin:063-gtp-common-conf 01_1463 -GTP_COMMON_MID_RIGHT.GTPE2.PLL0_INIT_CFG[16] origin:063-gtp-common-conf 00_1464 -GTP_COMMON_MID_RIGHT.GTPE2.PLL0_INIT_CFG[17] origin:063-gtp-common-conf 01_1464 -GTP_COMMON_MID_RIGHT.GTPE2.PLL0_INIT_CFG[18] origin:063-gtp-common-conf 00_1465 -GTP_COMMON_MID_RIGHT.GTPE2.PLL0_INIT_CFG[19] origin:063-gtp-common-conf 01_1465 -GTP_COMMON_MID_RIGHT.GTPE2.PLL0_INIT_CFG[20] origin:063-gtp-common-conf 00_1466 -GTP_COMMON_MID_RIGHT.GTPE2.PLL0_INIT_CFG[21] origin:063-gtp-common-conf 01_1466 -GTP_COMMON_MID_RIGHT.GTPE2.PLL0_INIT_CFG[22] origin:063-gtp-common-conf 00_1467 -GTP_COMMON_MID_RIGHT.GTPE2.PLL0_INIT_CFG[23] origin:063-gtp-common-conf 01_1467 -GTP_COMMON_MID_RIGHT.GTPE2.PLL0_LOCK_CFG[0] origin:063-gtp-common-conf 00_1448 -GTP_COMMON_MID_RIGHT.GTPE2.PLL0_LOCK_CFG[1] origin:063-gtp-common-conf 01_1448 -GTP_COMMON_MID_RIGHT.GTPE2.PLL0_LOCK_CFG[2] origin:063-gtp-common-conf 00_1449 -GTP_COMMON_MID_RIGHT.GTPE2.PLL0_LOCK_CFG[3] origin:063-gtp-common-conf 01_1449 -GTP_COMMON_MID_RIGHT.GTPE2.PLL0_LOCK_CFG[4] origin:063-gtp-common-conf 00_1450 -GTP_COMMON_MID_RIGHT.GTPE2.PLL0_LOCK_CFG[5] origin:063-gtp-common-conf 01_1450 -GTP_COMMON_MID_RIGHT.GTPE2.PLL0_LOCK_CFG[6] origin:063-gtp-common-conf 00_1451 -GTP_COMMON_MID_RIGHT.GTPE2.PLL0_LOCK_CFG[7] origin:063-gtp-common-conf 01_1451 -GTP_COMMON_MID_RIGHT.GTPE2.PLL0_LOCK_CFG[8] origin:063-gtp-common-conf 00_1452 -GTP_COMMON_MID_RIGHT.GTPE2.PLL0_REFCLK_DIV[4] origin:063-gtp-common-conf 01_1446 -GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[0] origin:063-gtp-common-conf 00_1792 -GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[1] origin:063-gtp-common-conf 01_1792 -GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[2] origin:063-gtp-common-conf 00_1793 -GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[3] origin:063-gtp-common-conf 01_1793 -GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[4] origin:063-gtp-common-conf 00_1794 -GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[5] origin:063-gtp-common-conf 01_1794 -GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[6] origin:063-gtp-common-conf 00_1795 -GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[7] origin:063-gtp-common-conf 01_1795 -GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[8] origin:063-gtp-common-conf 00_1796 -GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[9] origin:063-gtp-common-conf 01_1796 -GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[10] origin:063-gtp-common-conf 00_1797 -GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[11] origin:063-gtp-common-conf 01_1797 -GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[12] origin:063-gtp-common-conf 00_1798 -GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[13] origin:063-gtp-common-conf 01_1798 -GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[14] origin:063-gtp-common-conf 00_1799 -GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[15] origin:063-gtp-common-conf 01_1799 -GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[16] origin:063-gtp-common-conf 00_1800 -GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[17] origin:063-gtp-common-conf 01_1800 -GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[18] origin:063-gtp-common-conf 00_1801 -GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[19] origin:063-gtp-common-conf 01_1801 -GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[20] origin:063-gtp-common-conf 00_1802 -GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[21] origin:063-gtp-common-conf 01_1802 -GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[22] origin:063-gtp-common-conf 00_1803 -GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[23] origin:063-gtp-common-conf 01_1803 -GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[24] origin:063-gtp-common-conf 00_1804 -GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[25] origin:063-gtp-common-conf 01_1804 -GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[26] origin:063-gtp-common-conf 00_1805 -GTP_COMMON_MID_RIGHT.GTPE2.PLL1_DMON_CFG[0] origin:063-gtp-common-conf 01_1528 -GTP_COMMON_MID_RIGHT.GTPE2.PLL1_FBDIV[0] origin:063-gtp-common-conf 00_1784 -GTP_COMMON_MID_RIGHT.GTPE2.PLL1_FBDIV[1] origin:063-gtp-common-conf 01_1784 -GTP_COMMON_MID_RIGHT.GTPE2.PLL1_FBDIV[4] origin:063-gtp-common-conf 00_1786 -GTP_COMMON_MID_RIGHT.GTPE2.PLL1_FBDIV_45[0] origin:063-gtp-common-conf 01_1787 -GTP_COMMON_MID_RIGHT.GTPE2.PLL1_INIT_CFG[0] origin:063-gtp-common-conf 00_1760 -GTP_COMMON_MID_RIGHT.GTPE2.PLL1_INIT_CFG[1] origin:063-gtp-common-conf 01_1760 -GTP_COMMON_MID_RIGHT.GTPE2.PLL1_INIT_CFG[2] origin:063-gtp-common-conf 00_1761 -GTP_COMMON_MID_RIGHT.GTPE2.PLL1_INIT_CFG[3] origin:063-gtp-common-conf 01_1761 -GTP_COMMON_MID_RIGHT.GTPE2.PLL1_INIT_CFG[4] origin:063-gtp-common-conf 00_1762 -GTP_COMMON_MID_RIGHT.GTPE2.PLL1_INIT_CFG[5] origin:063-gtp-common-conf 01_1762 -GTP_COMMON_MID_RIGHT.GTPE2.PLL1_INIT_CFG[6] origin:063-gtp-common-conf 00_1763 -GTP_COMMON_MID_RIGHT.GTPE2.PLL1_INIT_CFG[7] origin:063-gtp-common-conf 01_1763 -GTP_COMMON_MID_RIGHT.GTPE2.PLL1_INIT_CFG[8] origin:063-gtp-common-conf 00_1764 -GTP_COMMON_MID_RIGHT.GTPE2.PLL1_INIT_CFG[9] origin:063-gtp-common-conf 01_1764 -GTP_COMMON_MID_RIGHT.GTPE2.PLL1_INIT_CFG[10] origin:063-gtp-common-conf 00_1765 -GTP_COMMON_MID_RIGHT.GTPE2.PLL1_INIT_CFG[11] origin:063-gtp-common-conf 01_1765 -GTP_COMMON_MID_RIGHT.GTPE2.PLL1_INIT_CFG[12] origin:063-gtp-common-conf 00_1766 -GTP_COMMON_MID_RIGHT.GTPE2.PLL1_INIT_CFG[13] origin:063-gtp-common-conf 01_1766 -GTP_COMMON_MID_RIGHT.GTPE2.PLL1_INIT_CFG[14] origin:063-gtp-common-conf 00_1767 -GTP_COMMON_MID_RIGHT.GTPE2.PLL1_INIT_CFG[15] origin:063-gtp-common-conf 01_1767 -GTP_COMMON_MID_RIGHT.GTPE2.PLL1_INIT_CFG[16] origin:063-gtp-common-conf 00_1768 -GTP_COMMON_MID_RIGHT.GTPE2.PLL1_INIT_CFG[17] origin:063-gtp-common-conf 01_1768 -GTP_COMMON_MID_RIGHT.GTPE2.PLL1_INIT_CFG[18] origin:063-gtp-common-conf 00_1769 -GTP_COMMON_MID_RIGHT.GTPE2.PLL1_INIT_CFG[19] origin:063-gtp-common-conf 01_1769 -GTP_COMMON_MID_RIGHT.GTPE2.PLL1_INIT_CFG[20] origin:063-gtp-common-conf 00_1770 -GTP_COMMON_MID_RIGHT.GTPE2.PLL1_INIT_CFG[21] origin:063-gtp-common-conf 01_1770 -GTP_COMMON_MID_RIGHT.GTPE2.PLL1_INIT_CFG[22] origin:063-gtp-common-conf 00_1771 -GTP_COMMON_MID_RIGHT.GTPE2.PLL1_INIT_CFG[23] origin:063-gtp-common-conf 01_1771 -GTP_COMMON_MID_RIGHT.GTPE2.PLL1_LOCK_CFG[0] origin:063-gtp-common-conf 00_1776 -GTP_COMMON_MID_RIGHT.GTPE2.PLL1_LOCK_CFG[1] origin:063-gtp-common-conf 01_1776 -GTP_COMMON_MID_RIGHT.GTPE2.PLL1_LOCK_CFG[2] origin:063-gtp-common-conf 00_1777 -GTP_COMMON_MID_RIGHT.GTPE2.PLL1_LOCK_CFG[3] origin:063-gtp-common-conf 01_1777 -GTP_COMMON_MID_RIGHT.GTPE2.PLL1_LOCK_CFG[4] origin:063-gtp-common-conf 00_1778 -GTP_COMMON_MID_RIGHT.GTPE2.PLL1_LOCK_CFG[5] origin:063-gtp-common-conf 01_1778 -GTP_COMMON_MID_RIGHT.GTPE2.PLL1_LOCK_CFG[6] origin:063-gtp-common-conf 00_1779 -GTP_COMMON_MID_RIGHT.GTPE2.PLL1_LOCK_CFG[7] origin:063-gtp-common-conf 01_1779 -GTP_COMMON_MID_RIGHT.GTPE2.PLL1_LOCK_CFG[8] origin:063-gtp-common-conf 00_1780 -GTP_COMMON_MID_RIGHT.GTPE2.PLL1_REFCLK_DIV[4] origin:063-gtp-common-conf 01_1790 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.GTREFCLK0_USED origin:063-gtp-common-conf 00_1438 00_1806 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.GTREFCLK1_USED origin:063-gtp-common-conf 01_1438 01_1806 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_CFG[0] origin:063-gtp-common-conf 00_1424 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_CFG[1] origin:063-gtp-common-conf 01_1424 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_CFG[2] origin:063-gtp-common-conf 00_1425 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_CFG[3] origin:063-gtp-common-conf 01_1425 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_CFG[4] origin:063-gtp-common-conf 00_1426 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_CFG[5] origin:063-gtp-common-conf 01_1426 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_CFG[6] origin:063-gtp-common-conf 00_1427 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_CFG[7] origin:063-gtp-common-conf 01_1427 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_CFG[8] origin:063-gtp-common-conf 00_1428 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_CFG[9] origin:063-gtp-common-conf 01_1428 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_CFG[10] origin:063-gtp-common-conf 00_1429 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_CFG[11] origin:063-gtp-common-conf 01_1429 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_CFG[12] origin:063-gtp-common-conf 00_1430 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_CFG[13] origin:063-gtp-common-conf 01_1430 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_CFG[14] origin:063-gtp-common-conf 00_1431 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_CFG[15] origin:063-gtp-common-conf 01_1431 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_CFG[16] origin:063-gtp-common-conf 00_1432 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_CFG[17] origin:063-gtp-common-conf 01_1432 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_CFG[18] origin:063-gtp-common-conf 00_1433 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_CFG[19] origin:063-gtp-common-conf 01_1433 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_CFG[20] origin:063-gtp-common-conf 00_1434 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_CFG[21] origin:063-gtp-common-conf 01_1434 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_CFG[22] origin:063-gtp-common-conf 00_1435 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_CFG[23] origin:063-gtp-common-conf 01_1435 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_CFG[24] origin:063-gtp-common-conf 00_1436 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_CFG[25] origin:063-gtp-common-conf 01_1436 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_CFG[26] origin:063-gtp-common-conf 00_1437 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_DMON_CFG[0] origin:063-gtp-common-conf 00_1528 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_FBDIV[0] origin:063-gtp-common-conf 00_1440 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_FBDIV[1] origin:063-gtp-common-conf 01_1440 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_FBDIV[4] origin:063-gtp-common-conf 00_1442 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_FBDIV_45[0] origin:063-gtp-common-conf 01_1443 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_INIT_CFG[0] origin:063-gtp-common-conf 00_1456 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_INIT_CFG[1] origin:063-gtp-common-conf 01_1456 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_INIT_CFG[2] origin:063-gtp-common-conf 00_1457 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_INIT_CFG[3] origin:063-gtp-common-conf 01_1457 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_INIT_CFG[4] origin:063-gtp-common-conf 00_1458 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_INIT_CFG[5] origin:063-gtp-common-conf 01_1458 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_INIT_CFG[6] origin:063-gtp-common-conf 00_1459 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_INIT_CFG[7] origin:063-gtp-common-conf 01_1459 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_INIT_CFG[8] origin:063-gtp-common-conf 00_1460 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_INIT_CFG[9] origin:063-gtp-common-conf 01_1460 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_INIT_CFG[10] origin:063-gtp-common-conf 00_1461 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_INIT_CFG[11] origin:063-gtp-common-conf 01_1461 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_INIT_CFG[12] origin:063-gtp-common-conf 00_1462 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_INIT_CFG[13] origin:063-gtp-common-conf 01_1462 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_INIT_CFG[14] origin:063-gtp-common-conf 00_1463 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_INIT_CFG[15] origin:063-gtp-common-conf 01_1463 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_INIT_CFG[16] origin:063-gtp-common-conf 00_1464 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_INIT_CFG[17] origin:063-gtp-common-conf 01_1464 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_INIT_CFG[18] origin:063-gtp-common-conf 00_1465 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_INIT_CFG[19] origin:063-gtp-common-conf 01_1465 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_INIT_CFG[20] origin:063-gtp-common-conf 00_1466 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_INIT_CFG[21] origin:063-gtp-common-conf 01_1466 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_INIT_CFG[22] origin:063-gtp-common-conf 00_1467 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_INIT_CFG[23] origin:063-gtp-common-conf 01_1467 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_LOCK_CFG[0] origin:063-gtp-common-conf 00_1448 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_LOCK_CFG[1] origin:063-gtp-common-conf 01_1448 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_LOCK_CFG[2] origin:063-gtp-common-conf 00_1449 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_LOCK_CFG[3] origin:063-gtp-common-conf 01_1449 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_LOCK_CFG[4] origin:063-gtp-common-conf 00_1450 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_LOCK_CFG[5] origin:063-gtp-common-conf 01_1450 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_LOCK_CFG[6] origin:063-gtp-common-conf 00_1451 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_LOCK_CFG[7] origin:063-gtp-common-conf 01_1451 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_LOCK_CFG[8] origin:063-gtp-common-conf 00_1452 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL0_REFCLK_DIV[4] origin:063-gtp-common-conf 01_1446 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_CFG[0] origin:063-gtp-common-conf 00_1792 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_CFG[1] origin:063-gtp-common-conf 01_1792 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_CFG[2] origin:063-gtp-common-conf 00_1793 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_CFG[3] origin:063-gtp-common-conf 01_1793 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_CFG[4] origin:063-gtp-common-conf 00_1794 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_CFG[5] origin:063-gtp-common-conf 01_1794 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_CFG[6] origin:063-gtp-common-conf 00_1795 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_CFG[7] origin:063-gtp-common-conf 01_1795 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_CFG[8] origin:063-gtp-common-conf 00_1796 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_CFG[9] origin:063-gtp-common-conf 01_1796 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_CFG[10] origin:063-gtp-common-conf 00_1797 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_CFG[11] origin:063-gtp-common-conf 01_1797 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_CFG[12] origin:063-gtp-common-conf 00_1798 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_CFG[13] origin:063-gtp-common-conf 01_1798 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_CFG[14] origin:063-gtp-common-conf 00_1799 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_CFG[15] origin:063-gtp-common-conf 01_1799 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_CFG[16] origin:063-gtp-common-conf 00_1800 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_CFG[17] origin:063-gtp-common-conf 01_1800 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_CFG[18] origin:063-gtp-common-conf 00_1801 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_CFG[19] origin:063-gtp-common-conf 01_1801 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_CFG[20] origin:063-gtp-common-conf 00_1802 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_CFG[21] origin:063-gtp-common-conf 01_1802 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_CFG[22] origin:063-gtp-common-conf 00_1803 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_CFG[23] origin:063-gtp-common-conf 01_1803 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_CFG[24] origin:063-gtp-common-conf 00_1804 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_CFG[25] origin:063-gtp-common-conf 01_1804 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_CFG[26] origin:063-gtp-common-conf 00_1805 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_DMON_CFG[0] origin:063-gtp-common-conf 01_1528 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_FBDIV[0] origin:063-gtp-common-conf 00_1784 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_FBDIV[1] origin:063-gtp-common-conf 01_1784 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_FBDIV[4] origin:063-gtp-common-conf 00_1786 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_FBDIV_45[0] origin:063-gtp-common-conf 01_1787 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_INIT_CFG[0] origin:063-gtp-common-conf 00_1760 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_INIT_CFG[1] origin:063-gtp-common-conf 01_1760 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_INIT_CFG[2] origin:063-gtp-common-conf 00_1761 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_INIT_CFG[3] origin:063-gtp-common-conf 01_1761 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_INIT_CFG[4] origin:063-gtp-common-conf 00_1762 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_INIT_CFG[5] origin:063-gtp-common-conf 01_1762 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_INIT_CFG[6] origin:063-gtp-common-conf 00_1763 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_INIT_CFG[7] origin:063-gtp-common-conf 01_1763 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_INIT_CFG[8] origin:063-gtp-common-conf 00_1764 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_INIT_CFG[9] origin:063-gtp-common-conf 01_1764 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_INIT_CFG[10] origin:063-gtp-common-conf 00_1765 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_INIT_CFG[11] origin:063-gtp-common-conf 01_1765 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_INIT_CFG[12] origin:063-gtp-common-conf 00_1766 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_INIT_CFG[13] origin:063-gtp-common-conf 01_1766 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_INIT_CFG[14] origin:063-gtp-common-conf 00_1767 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_INIT_CFG[15] origin:063-gtp-common-conf 01_1767 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_INIT_CFG[16] origin:063-gtp-common-conf 00_1768 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_INIT_CFG[17] origin:063-gtp-common-conf 01_1768 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_INIT_CFG[18] origin:063-gtp-common-conf 00_1769 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_INIT_CFG[19] origin:063-gtp-common-conf 01_1769 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_INIT_CFG[20] origin:063-gtp-common-conf 00_1770 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_INIT_CFG[21] origin:063-gtp-common-conf 01_1770 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_INIT_CFG[22] origin:063-gtp-common-conf 00_1771 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_INIT_CFG[23] origin:063-gtp-common-conf 01_1771 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_LOCK_CFG[0] origin:063-gtp-common-conf 00_1776 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_LOCK_CFG[1] origin:063-gtp-common-conf 01_1776 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_LOCK_CFG[2] origin:063-gtp-common-conf 00_1777 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_LOCK_CFG[3] origin:063-gtp-common-conf 01_1777 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_LOCK_CFG[4] origin:063-gtp-common-conf 00_1778 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_LOCK_CFG[5] origin:063-gtp-common-conf 01_1778 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_LOCK_CFG[6] origin:063-gtp-common-conf 00_1779 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_LOCK_CFG[7] origin:063-gtp-common-conf 01_1779 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_LOCK_CFG[8] origin:063-gtp-common-conf 00_1780 +GTP_COMMON_MID_RIGHT.GTPE2_COMMON.PLL1_REFCLK_DIV[4] origin:063-gtp-common-conf 01_1790 diff --git a/artix7/segbits_int_l.origin_info.db b/artix7/segbits_int_l.origin_info.db index adb181a..79c24d8 100644 --- a/artix7/segbits_int_l.origin_info.db +++ b/artix7/segbits_int_l.origin_info.db @@ -1877,7 +1877,7 @@ INT_L.EE4BEG0.SE6END0 origin:050-pip-seed 03_09 06_08 INT_L.EE4BEG0.SS2END0 origin:050-pip-seed 03_08 05_11 INT_L.EE4BEG0.SS6END0 origin:050-pip-seed 05_11 06_08 INT_L.EE4BEG0.SW2END0 origin:050-pip-seed 02_09 05_11 -INT_L.EE4BEG0.SW6END0 origin:050-pip-seed 05_08 05_11 +INT_L.EE4BEG0.SW6END0 origin:056-pip-rem 05_08 05_11 INT_L.EE4BEG1.LOGIC_OUTS_L1 origin:050-pip-seed 02_25 07_25 INT_L.EE4BEG1.LOGIC_OUTS_L5 origin:050-pip-seed 02_25 04_26 INT_L.EE4BEG1.LOGIC_OUTS_L9 origin:050-pip-seed 03_24 04_26 @@ -2253,7 +2253,7 @@ INT_L.NE6BEG2.NW6END2 origin:050-pip-seed 04_37 06_36 INT_L.NE6BEG2.SE2END2 origin:050-pip-seed 02_37 05_39 INT_L.NE6BEG2.SE6END2 origin:050-pip-seed 05_39 06_36 INT_L.NE6BEG2.WW2END1 origin:050-pip-seed 03_36 04_37 -INT_L.NE6BEG2.WW4END2 origin:050-pip-seed 04_37 05_36 +INT_L.NE6BEG2.WW4END2 origin:056-pip-rem 04_37 05_36 INT_L.NE6BEG3.LOGIC_OUTS_L3 origin:050-pip-seed 02_53 04_54 INT_L.NE6BEG3.LOGIC_OUTS_L7 origin:050-pip-seed 02_53 07_53 INT_L.NE6BEG3.LOGIC_OUTS_L11 origin:050-pip-seed 03_52 07_53 @@ -2662,7 +2662,7 @@ INT_L.NW6BEG0.LOGIC_OUTS_L18 origin:050-pip-seed 05_01 07_03 INT_L.NW6BEG0.LOGIC_OUTS_L22 origin:050-pip-seed 06_02 07_03 INT_L.NW6BEG0.LV_L0 origin:056-pip-rem 04_03 06_02 INT_L.NW6BEG0.SS2END_N0_3 origin:050-pip-seed 02_03 04_00 -INT_L.NW6BEG0.SS6END_N0_3 origin:056-pip-rem 04_00 07_03 +INT_L.NW6BEG0.SS6END_N0_3 origin:050-pip-seed 04_00 07_03 INT_L.NW6BEG0.SW2END_N0_3 origin:050-pip-seed 03_02 04_00 INT_L.NW6BEG0.SW6END_N0_3 origin:050-pip-seed 04_00 04_03 INT_L.NW6BEG0.WW2END_N0_3 origin:050-pip-seed 02_02 02_03 @@ -2887,7 +2887,7 @@ INT_L.SE6BEG3.LH0 origin:056-pip-rem 04_59 06_58 INT_L.SE6BEG3.NE2END3 origin:050-pip-seed 03_58 04_56 INT_L.SE6BEG3.NE6END3 origin:050-pip-seed 04_56 04_59 INT_L.SE6BEG3.NN2END3 origin:050-pip-seed 02_59 04_56 -INT_L.SE6BEG3.NN6END3 origin:050-pip-seed 04_56 07_59 +INT_L.SE6BEG3.NN6END3 origin:056-pip-rem 04_56 07_59 INT_L.SE6BEG3.SE2END3 origin:050-pip-seed 02_58 03_58 INT_L.SE6BEG3.SE6END3 origin:050-pip-seed 02_58 07_59 INT_L.SE6BEG3.SS2END3 origin:050-pip-seed 02_59 05_58 @@ -3302,7 +3302,7 @@ INT_L.SW6BEG1.LOGIC_OUTS_L19 origin:050-pip-seed 06_28 07_29 INT_L.SW6BEG1.LOGIC_OUTS_L23 origin:050-pip-seed 04_30 06_28 INT_L.SW6BEG1.LV_L9 origin:056-pip-rem 04_30 05_28 INT_L.SW6BEG1.EE2END1 origin:050-pip-seed 03_28 04_29 -INT_L.SW6BEG1.EE4END1 origin:056-pip-rem 04_29 05_28 +INT_L.SW6BEG1.EE4END1 origin:050-pip-seed 04_29 05_28 INT_L.SW6BEG1.LH6 origin:056-pip-rem 05_28 07_29 INT_L.SW6BEG1.NW2END2 origin:050-pip-seed 02_29 05_31 INT_L.SW6BEG1.NW6END2 origin:050-pip-seed 05_31 06_28 @@ -3323,7 +3323,7 @@ INT_L.SW6BEG2.LOGIC_OUTS_L20 origin:050-pip-seed 06_44 07_45 INT_L.SW6BEG2.LVB_L0 origin:056-pip-rem 04_46 05_44 INT_L.SW6BEG2.LVB_L12 origin:056-pip-rem 05_44 07_45 INT_L.SW6BEG2.EE2END2 origin:050-pip-seed 03_44 04_45 -INT_L.SW6BEG2.EE4END2 origin:050-pip-seed 04_45 05_44 +INT_L.SW6BEG2.EE4END2 origin:056-pip-rem 04_45 05_44 INT_L.SW6BEG2.NW2END3 origin:050-pip-seed 02_45 05_47 INT_L.SW6BEG2.NW6END3 origin:050-pip-seed 05_47 06_44 INT_L.SW6BEG2.SE2END2 origin:050-pip-seed 02_45 04_45 @@ -3568,7 +3568,7 @@ INT_L.WW4BEG0.SW6END_N0_3 origin:050-pip-seed 04_01 05_00 INT_L.WW4BEG0.WW2END_N0_3 origin:050-pip-seed 03_00 03_01 INT_L.WW4BEG0.LH12 origin:056-pip-rem 05_00 07_01 INT_L.WW4BEG0.NE2END0 origin:050-pip-seed 02_01 05_03 -INT_L.WW4BEG0.NE6END0 origin:050-pip-seed 05_00 05_03 +INT_L.WW4BEG0.NE6END0 origin:056-pip-rem 05_00 05_03 INT_L.WW4BEG0.NN2END0 origin:050-pip-seed 03_00 05_03 INT_L.WW4BEG0.NN6END0 origin:050-pip-seed 05_03 06_00 INT_L.WW4BEG0.NW2END0 origin:050-pip-seed 02_01 03_01 diff --git a/artix7/segbits_int_r.origin_info.db b/artix7/segbits_int_r.origin_info.db index ff8d7a3..a41b859 100644 --- a/artix7/segbits_int_r.origin_info.db +++ b/artix7/segbits_int_r.origin_info.db @@ -665,7 +665,7 @@ INT_R.EE4BEG0.SE6END0 origin:050-pip-seed 03_09 06_08 INT_R.EE4BEG0.SS2END0 origin:050-pip-seed 03_08 05_11 INT_R.EE4BEG0.SS6END0 origin:050-pip-seed 05_11 06_08 INT_R.EE4BEG0.SW2END0 origin:050-pip-seed 02_09 05_11 -INT_R.EE4BEG0.SW6END0 origin:050-pip-seed 05_08 05_11 +INT_R.EE4BEG0.SW6END0 origin:056-pip-rem 05_08 05_11 INT_R.EE4BEG1.LOGIC_OUTS1 origin:050-pip-seed 02_25 07_25 INT_R.EE4BEG1.LOGIC_OUTS5 origin:050-pip-seed 02_25 04_26 INT_R.EE4BEG1.LOGIC_OUTS9 origin:050-pip-seed 03_24 04_26 @@ -705,7 +705,7 @@ INT_R.EE4BEG2.SE6END2 origin:050-pip-seed 03_41 06_40 INT_R.EE4BEG2.SS2END2 origin:050-pip-seed 03_40 05_43 INT_R.EE4BEG2.SS6END2 origin:050-pip-seed 05_43 06_40 INT_R.EE4BEG2.SW2END2 origin:050-pip-seed 02_41 05_43 -INT_R.EE4BEG2.SW6END2 origin:056-pip-rem 05_40 05_43 +INT_R.EE4BEG2.SW6END2 origin:050-pip-seed 05_40 05_43 INT_R.EE4BEG3.LOGIC_OUTS3 origin:050-pip-seed 02_57 07_57 INT_R.EE4BEG3.LOGIC_OUTS7 origin:050-pip-seed 02_57 04_58 INT_R.EE4BEG3.LOGIC_OUTS11 origin:050-pip-seed 03_56 04_58 @@ -725,7 +725,7 @@ INT_R.EE4BEG3.SE6END3 origin:050-pip-seed 03_57 06_56 INT_R.EE4BEG3.SS2END3 origin:050-pip-seed 03_56 05_59 INT_R.EE4BEG3.SS6END3 origin:050-pip-seed 05_59 06_56 INT_R.EE4BEG3.SW2END3 origin:050-pip-seed 02_57 05_59 -INT_R.EE4BEG3.SW6END3 origin:056-pip-rem 05_56 05_59 +INT_R.EE4BEG3.SW6END3 origin:050-pip-seed 05_56 05_59 INT_R.EL1BEG0.LOGIC_OUTS1 origin:050-pip-seed 07_20 14_21 INT_R.EL1BEG0.LOGIC_OUTS5 origin:050-pip-seed 11_21 14_21 INT_R.EL1BEG0.LOGIC_OUTS9 origin:050-pip-seed 10_21 13_21 @@ -3321,7 +3321,7 @@ INT_R.SW6BEG2.LOGIC_OUTS14 origin:050-pip-seed 03_44 07_45 INT_R.SW6BEG2.LOGIC_OUTS16 origin:050-pip-seed 04_46 06_44 INT_R.SW6BEG2.LOGIC_OUTS20 origin:050-pip-seed 06_44 07_45 INT_R.SW6BEG2.EE2END2 origin:050-pip-seed 03_44 04_45 -INT_R.SW6BEG2.EE4END2 origin:050-pip-seed 04_45 05_44 +INT_R.SW6BEG2.EE4END2 origin:056-pip-rem 04_45 05_44 INT_R.SW6BEG2.LVB0 origin:056-pip-rem 04_46 05_44 INT_R.SW6BEG2.LVB12 origin:056-pip-rem 05_44 07_45 INT_R.SW6BEG2.NW2END3 origin:050-pip-seed 02_45 05_47 @@ -3568,7 +3568,7 @@ INT_R.WW4BEG0.WW2END_N0_3 origin:050-pip-seed 03_00 03_01 INT_R.WW4BEG0.LH12 origin:056-pip-rem 05_00 07_01 INT_R.WW4BEG0.LV0 origin:056-pip-rem 04_02 05_00 INT_R.WW4BEG0.NE2END0 origin:050-pip-seed 02_01 05_03 -INT_R.WW4BEG0.NE6END0 origin:050-pip-seed 05_00 05_03 +INT_R.WW4BEG0.NE6END0 origin:056-pip-rem 05_00 05_03 INT_R.WW4BEG0.NN2END0 origin:050-pip-seed 03_00 05_03 INT_R.WW4BEG0.NN6END0 origin:050-pip-seed 05_03 06_00 INT_R.WW4BEG0.NW2END0 origin:050-pip-seed 02_01 03_01 @@ -3623,7 +3623,7 @@ INT_R.WW4BEG3.LOGIC_OUTS21 origin:050-pip-seed 06_48 07_49 INT_R.WW4BEG3.LH0 origin:056-pip-rem 04_50 05_48 INT_R.WW4BEG3.LV18 origin:056-pip-rem 05_48 07_49 INT_R.WW4BEG3.NE2END3 origin:050-pip-seed 02_49 05_51 -INT_R.WW4BEG3.NE6END3 origin:056-pip-rem 05_48 05_51 +INT_R.WW4BEG3.NE6END3 origin:050-pip-seed 05_48 05_51 INT_R.WW4BEG3.NN2END3 origin:050-pip-seed 03_48 05_51 INT_R.WW4BEG3.NN6END3 origin:050-pip-seed 05_51 06_48 INT_R.WW4BEG3.NW2END3 origin:050-pip-seed 02_49 03_49 diff --git a/artix7/segbits_liob33.db b/artix7/segbits_liob33.db index 4d9f02a..e5c2ee6 100644 --- a/artix7/segbits_liob33.db +++ b/artix7/segbits_liob33.db @@ -48,6 +48,7 @@ LIOB33.IOB_Y1.IN_TERM.UNTUNED_SPLIT_40 38_04 38_06 39_05 39_07 LIOB33.IOB_Y1.IN_TERM.UNTUNED_SPLIT_50 38_04 !38_06 39_05 39_07 LIOB33.IOB_Y1.IN_TERM.UNTUNED_SPLIT_60 38_04 !38_06 !39_05 39_07 LIOB33.IOB_Y1.INTERMDISABLE.I 38_38 +LIOB33.IOB_Y1.LVDS_25_SSTL135_SSTL15.IN_DIFF 38_40 !38_42 39_41 LIOB33.IOB_Y1.LVTTL.DRIVE.I24 !38_00 !38_02 38_08 38_10 38_62 39_01 !39_09 !39_15 39_63 LIOB33.IOB_Y1.PULLTYPE.KEEPER !38_34 39_33 39_35 LIOB33.IOB_Y1.PULLTYPE.NONE !38_34 39_33 !39_35 @@ -57,8 +58,8 @@ LIOB33.IOB_Y1.ZIBUF_LOW_PWR 39_43 LIOB33.IOB_Y1.LVCMOS12.DRIVE.I4 !38_00 38_02 !38_08 !38_10 38_14 38_62 39_01 39_09 39_15 39_63 LIOB33.IOB_Y1.LVCMOS12.DRIVE.I12 38_00 !38_02 !38_08 !38_10 38_14 38_62 39_01 !39_09 39_15 39_63 LIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18.IN !38_40 38_42 39_41 +LIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVDS_25_LVTTL_SSTL135_SSTL15_TMDS_33.IN_ONLY !38_00 38_02 38_08 !38_10 38_14 !38_62 !39_01 39_09 !39_15 !39_63 LIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST !38_16 !38_18 !38_20 !38_22 !39_17 !39_21 -LIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.IN_ONLY !38_00 38_02 38_08 !38_10 38_14 !38_62 !39_01 39_09 !39_15 !39_63 LIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.SLEW.SLOW !38_16 38_18 !38_20 38_22 39_17 39_21 LIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_SSTL135_SSTL15.STEPDOWN 38_32 LIOB33.IOB_Y1.LVCMOS12_LVCMOS25.DRIVE.I8 !38_00 !38_02 38_08 !38_10 38_14 38_62 !39_01 !39_09 39_15 39_63 @@ -78,6 +79,5 @@ LIOB33.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I12_I8 !38_00 38_02 38_08 !38_10 38_62 39_01 LIOB33.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I12_I16 38_00 38_02 !38_08 !38_10 38_62 39_01 !39_09 !39_15 39_63 LIOB33.IOB_Y1.SSTL135.DRIVE.I_FIXED 38_00 !38_02 38_08 38_10 38_14 38_62 39_01 39_09 39_15 39_63 LIOB33.IOB_Y1.SSTL135_SSTL15.IN 38_40 !38_42 !39_41 -LIOB33.IOB_Y1.SSTL135_SSTL15.IN_DIFF 38_40 !38_42 39_41 LIOB33.IOB_Y1.SSTL135_SSTL15.SLEW.FAST 38_16 38_18 38_20 38_22 39_17 !39_21 LIOB33.OUT_DIFF 39_59 39_61 diff --git a/artix7/segbits_liob33.origin_info.db b/artix7/segbits_liob33.origin_info.db index 022593c..5c43c07 100644 --- a/artix7/segbits_liob33.origin_info.db +++ b/artix7/segbits_liob33.origin_info.db @@ -48,6 +48,7 @@ LIOB33.IOB_Y1.IN_TERM.UNTUNED_SPLIT_40 origin:030-iob 38_04 38_06 39_05 39_07 LIOB33.IOB_Y1.IN_TERM.UNTUNED_SPLIT_50 origin:030-iob !38_06 38_04 39_05 39_07 LIOB33.IOB_Y1.IN_TERM.UNTUNED_SPLIT_60 origin:030-iob !38_06 !39_05 38_04 39_07 LIOB33.IOB_Y1.INTERMDISABLE.I origin:030-iob 38_38 +LIOB33.IOB_Y1.LVDS_25_SSTL135_SSTL15.IN_DIFF origin:030-iob !38_42 38_40 39_41 LIOB33.IOB_Y1.LVTTL.DRIVE.I24 origin:030-iob !38_00 !38_02 !39_09 !39_15 38_08 38_10 38_62 39_01 39_63 LIOB33.IOB_Y1.PULLTYPE.KEEPER origin:030-iob !38_34 39_33 39_35 LIOB33.IOB_Y1.PULLTYPE.NONE origin:030-iob !38_34 !39_35 39_33 @@ -57,8 +58,8 @@ LIOB33.IOB_Y1.ZIBUF_LOW_PWR origin:030-iob 39_43 LIOB33.IOB_Y1.LVCMOS12.DRIVE.I4 origin:030-iob !38_00 !38_08 !38_10 38_02 38_14 38_62 39_01 39_09 39_15 39_63 LIOB33.IOB_Y1.LVCMOS12.DRIVE.I12 origin:030-iob !38_02 !38_08 !38_10 !39_09 38_00 38_14 38_62 39_01 39_15 39_63 LIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18.IN origin:030-iob !38_40 38_42 39_41 +LIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVDS_25_LVTTL_SSTL135_SSTL15_TMDS_33.IN_ONLY origin:030-iob !38_00 !38_10 !38_62 !39_01 !39_15 !39_63 38_02 38_08 38_14 39_09 LIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST origin:030-iob !38_16 !38_18 !38_20 !38_22 !39_17 !39_21 -LIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.IN_ONLY origin:030-iob !38_00 !38_10 !38_62 !39_01 !39_15 !39_63 38_02 38_08 38_14 39_09 LIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.SLEW.SLOW origin:030-iob !38_16 !38_20 38_18 38_22 39_17 39_21 LIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_SSTL135_SSTL15.STEPDOWN origin:030-iob 38_32 LIOB33.IOB_Y1.LVCMOS12_LVCMOS25.DRIVE.I8 origin:030-iob !38_00 !38_02 !38_10 !39_01 !39_09 38_08 38_14 38_62 39_15 39_63 @@ -78,6 +79,5 @@ LIOB33.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I12_I8 origin:030-iob !38_00 !38_10 !39_09 !3 LIOB33.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I12_I16 origin:030-iob !38_08 !38_10 !39_09 !39_15 38_00 38_02 38_62 39_01 39_63 LIOB33.IOB_Y1.SSTL135.DRIVE.I_FIXED origin:030-iob !38_02 38_00 38_08 38_10 38_14 38_62 39_01 39_09 39_15 39_63 LIOB33.IOB_Y1.SSTL135_SSTL15.IN origin:030-iob !38_42 !39_41 38_40 -LIOB33.IOB_Y1.SSTL135_SSTL15.IN_DIFF origin:030-iob !38_42 38_40 39_41 LIOB33.IOB_Y1.SSTL135_SSTL15.SLEW.FAST origin:030-iob !39_21 38_16 38_18 38_20 38_22 39_17 LIOB33.OUT_DIFF origin:030-iob 39_59 39_61 diff --git a/artix7/segbits_riob33.db b/artix7/segbits_riob33.db index a4b4403..bf489d5 100644 --- a/artix7/segbits_riob33.db +++ b/artix7/segbits_riob33.db @@ -48,6 +48,7 @@ RIOB33.IOB_Y1.IN_TERM.UNTUNED_SPLIT_40 38_04 38_06 39_05 39_07 RIOB33.IOB_Y1.IN_TERM.UNTUNED_SPLIT_50 38_04 !38_06 39_05 39_07 RIOB33.IOB_Y1.IN_TERM.UNTUNED_SPLIT_60 38_04 !38_06 !39_05 39_07 RIOB33.IOB_Y1.INTERMDISABLE.I 38_38 +RIOB33.IOB_Y1.LVDS_25_SSTL135_SSTL15.IN_DIFF 38_40 !38_42 39_41 RIOB33.IOB_Y1.LVTTL.DRIVE.I24 !38_00 !38_02 38_08 38_10 38_62 39_01 !39_09 !39_15 39_63 RIOB33.IOB_Y1.PULLTYPE.KEEPER !38_34 39_33 39_35 RIOB33.IOB_Y1.PULLTYPE.NONE !38_34 39_33 !39_35 @@ -57,8 +58,8 @@ RIOB33.IOB_Y1.ZIBUF_LOW_PWR 39_43 RIOB33.IOB_Y1.LVCMOS12.DRIVE.I4 !38_00 38_02 !38_08 !38_10 38_14 38_62 39_01 39_09 39_15 39_63 RIOB33.IOB_Y1.LVCMOS12.DRIVE.I12 38_00 !38_02 !38_08 !38_10 38_14 38_62 39_01 !39_09 39_15 39_63 RIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18.IN !38_40 38_42 39_41 +RIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVDS_25_LVTTL_SSTL135_SSTL15_TMDS_33.IN_ONLY !38_00 38_02 38_08 !38_10 38_14 !38_62 !39_01 39_09 !39_15 !39_63 RIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST !38_16 !38_18 !38_20 !38_22 !39_17 !39_21 -RIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.IN_ONLY !38_00 38_02 38_08 !38_10 38_14 !38_62 !39_01 39_09 !39_15 !39_63 RIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.SLEW.SLOW !38_16 38_18 !38_20 38_22 39_17 39_21 RIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_SSTL135_SSTL15.STEPDOWN 38_32 RIOB33.IOB_Y1.LVCMOS12_LVCMOS25.DRIVE.I8 !38_00 !38_02 38_08 !38_10 38_14 38_62 !39_01 !39_09 39_15 39_63 @@ -78,6 +79,5 @@ RIOB33.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I12_I8 !38_00 38_02 38_08 !38_10 38_62 39_01 RIOB33.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I12_I16 38_00 38_02 !38_08 !38_10 38_62 39_01 !39_09 !39_15 39_63 RIOB33.IOB_Y1.SSTL135.DRIVE.I_FIXED 38_00 !38_02 38_08 38_10 38_14 38_62 39_01 39_09 39_15 39_63 RIOB33.IOB_Y1.SSTL135_SSTL15.IN 38_40 !38_42 !39_41 -RIOB33.IOB_Y1.SSTL135_SSTL15.IN_DIFF 38_40 !38_42 39_41 RIOB33.IOB_Y1.SSTL135_SSTL15.SLEW.FAST 38_16 38_18 38_20 38_22 39_17 !39_21 RIOB33.OUT_DIFF 39_59 39_61 diff --git a/artix7/segbits_riob33.origin_info.db b/artix7/segbits_riob33.origin_info.db index 95c9159..cee7b38 100644 --- a/artix7/segbits_riob33.origin_info.db +++ b/artix7/segbits_riob33.origin_info.db @@ -48,6 +48,7 @@ RIOB33.IOB_Y1.IN_TERM.UNTUNED_SPLIT_40 origin:030-iob 38_04 38_06 39_05 39_07 RIOB33.IOB_Y1.IN_TERM.UNTUNED_SPLIT_50 origin:030-iob !38_06 38_04 39_05 39_07 RIOB33.IOB_Y1.IN_TERM.UNTUNED_SPLIT_60 origin:030-iob !38_06 !39_05 38_04 39_07 RIOB33.IOB_Y1.INTERMDISABLE.I origin:030-iob 38_38 +RIOB33.IOB_Y1.LVDS_25_SSTL135_SSTL15.IN_DIFF origin:030-iob !38_42 38_40 39_41 RIOB33.IOB_Y1.LVTTL.DRIVE.I24 origin:030-iob !38_00 !38_02 !39_09 !39_15 38_08 38_10 38_62 39_01 39_63 RIOB33.IOB_Y1.PULLTYPE.KEEPER origin:030-iob !38_34 39_33 39_35 RIOB33.IOB_Y1.PULLTYPE.NONE origin:030-iob !38_34 !39_35 39_33 @@ -57,8 +58,8 @@ RIOB33.IOB_Y1.ZIBUF_LOW_PWR origin:030-iob 39_43 RIOB33.IOB_Y1.LVCMOS12.DRIVE.I4 origin:030-iob !38_00 !38_08 !38_10 38_02 38_14 38_62 39_01 39_09 39_15 39_63 RIOB33.IOB_Y1.LVCMOS12.DRIVE.I12 origin:030-iob !38_02 !38_08 !38_10 !39_09 38_00 38_14 38_62 39_01 39_15 39_63 RIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18.IN origin:030-iob !38_40 38_42 39_41 +RIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVDS_25_LVTTL_SSTL135_SSTL15_TMDS_33.IN_ONLY origin:030-iob !38_00 !38_10 !38_62 !39_01 !39_15 !39_63 38_02 38_08 38_14 39_09 RIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST origin:030-iob !38_16 !38_18 !38_20 !38_22 !39_17 !39_21 -RIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.IN_ONLY origin:030-iob !38_00 !38_10 !38_62 !39_01 !39_15 !39_63 38_02 38_08 38_14 39_09 RIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.SLEW.SLOW origin:030-iob !38_16 !38_20 38_18 38_22 39_17 39_21 RIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_SSTL135_SSTL15.STEPDOWN origin:030-iob 38_32 RIOB33.IOB_Y1.LVCMOS12_LVCMOS25.DRIVE.I8 origin:030-iob !38_00 !38_02 !38_10 !39_01 !39_09 38_08 38_14 38_62 39_15 39_63 @@ -78,6 +79,5 @@ RIOB33.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I12_I8 origin:030-iob !38_00 !38_10 !39_09 !3 RIOB33.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I12_I16 origin:030-iob !38_08 !38_10 !39_09 !39_15 38_00 38_02 38_62 39_01 39_63 RIOB33.IOB_Y1.SSTL135.DRIVE.I_FIXED origin:030-iob !38_02 38_00 38_08 38_10 38_14 38_62 39_01 39_09 39_15 39_63 RIOB33.IOB_Y1.SSTL135_SSTL15.IN origin:030-iob !38_42 !39_41 38_40 -RIOB33.IOB_Y1.SSTL135_SSTL15.IN_DIFF origin:030-iob !38_42 38_40 39_41 RIOB33.IOB_Y1.SSTL135_SSTL15.SLEW.FAST origin:030-iob !39_21 38_16 38_18 38_20 38_22 39_17 RIOB33.OUT_DIFF origin:030-iob 39_59 39_61 diff --git a/artix7/xc7a100t/tilegrid.json b/artix7/xc7a100t/tilegrid.json index c55e7c1..a5235d1 100644 --- a/artix7/xc7a100t/tilegrid.json +++ b/artix7/xc7a100t/tilegrid.json @@ -176660,7 +176660,7 @@ "bits": { "CLB_IO_CLK": { "baseaddr": "0x00421980", - "frames": 42, + "frames": 32, "offset": 0, "words": 101 } @@ -176690,7 +176690,7 @@ "bits": { "CLB_IO_CLK": { "baseaddr": "0x00021980", - "frames": 42, + "frames": 32, "offset": 0, "words": 101 } diff --git a/artix7/xc7a200t/tilegrid.json b/artix7/xc7a200t/tilegrid.json index 2068ee2..ff18272 100644 --- a/artix7/xc7a200t/tilegrid.json +++ b/artix7/xc7a200t/tilegrid.json @@ -382173,7 +382173,7 @@ "bits": { "CLB_IO_CLK": { "baseaddr": "0x00441200", - "frames": 42, + "frames": 32, "offset": 0, "words": 101 } @@ -382203,7 +382203,7 @@ "bits": { "CLB_IO_CLK": { "baseaddr": "0x00021200", - "frames": 42, + "frames": 32, "offset": 0, "words": 101 } @@ -382233,7 +382233,7 @@ "bits": { "CLB_IO_CLK": { "baseaddr": "0x00442480", - "frames": 42, + "frames": 32, "offset": 0, "words": 101 } @@ -382263,7 +382263,7 @@ "bits": { "CLB_IO_CLK": { "baseaddr": "0x00022480", - "frames": 42, + "frames": 32, "offset": 0, "words": 101 } diff --git a/artix7/xc7a50t/tilegrid.json b/artix7/xc7a50t/tilegrid.json index 2e13c08..3161ad1 100644 --- a/artix7/xc7a50t/tilegrid.json +++ b/artix7/xc7a50t/tilegrid.json @@ -91864,7 +91864,7 @@ "bits": { "CLB_IO_CLK": { "baseaddr": "0x00021280", - "frames": 42, + "frames": 32, "offset": 0, "words": 101 } diff --git a/kintex7/ppips_pcie_bot.db b/kintex7/ppips_pcie_bot.db new file mode 100644 index 0000000..f2a0989 --- /dev/null +++ b/kintex7/ppips_pcie_bot.db @@ -0,0 +1,1736 @@ +PCIE_BOT.PCIE_CFGERRACSN.PCIE_IMUX12_R_16 always +PCIE_BOT.PCIE_CFGERRATOMICEGRESSBLOCKEDN.PCIE_IMUX13_R_17 always +PCIE_BOT.PCIE_CFGERRCORN.PCIE_IMUX9_R_15 always +PCIE_BOT.PCIE_CFGERRCPLABORTN.PCIE_IMUX9_R_16 always +PCIE_BOT.PCIE_CFGERRCPLTIMEOUTN.PCIE_IMUX12_R_15 always +PCIE_BOT.PCIE_CFGERRCPLUNEXPECTN.PCIE_IMUX10_R_16 always +PCIE_BOT.PCIE_CFGERRECRCN.PCIE_IMUX11_R_15 always +PCIE_BOT.PCIE_CFGERRINTERNALCORN.PCIE_IMUX17_R_17 always +PCIE_BOT.PCIE_CFGERRINTERNALUNCORN.PCIE_IMUX15_R_17 always +PCIE_BOT.PCIE_CFGERRMALFORMEDN.PCIE_IMUX8_R_14 always +PCIE_BOT.PCIE_CFGERRMCBLOCKEDN.PCIE_IMUX14_R_17 always +PCIE_BOT.PCIE_CFGERRPOISONEDN.PCIE_IMUX11_R_16 always +PCIE_BOT.PCIE_CFGERRPOSTEDN.PCIE_IMUX17_R_18 always +PCIE_BOT.PCIE_CFGERRURN.PCIE_IMUX10_R_15 always +PCIE_BOT.PCIE_CFGFORCECOMMONCLOCKOFF.PCIE_IMUX9_L_5 always +PCIE_BOT.PCIE_CFGFORCEEXTENDEDSYNCON.PCIE_IMUX10_L_5 always +PCIE_BOT.PCIE_CFGINTERRUPTASSERTN.PCIE_IMUX16_R_13 always +PCIE_BOT.PCIE_CFGINTERRUPTSTATN.PCIE_IMUX13_R_12 always +PCIE_BOT.PCIE_CFGMGMTRDENN.PCIE_IMUX7_R_14 always +PCIE_BOT.PCIE_CFGMGMTWRENN.PCIE_IMUX6_R_14 always +PCIE_BOT.PCIE_CFGMGMTWRREADONLYN.PCIE_IMUX5_R_14 always +PCIE_BOT.PCIE_CFGMGMTWRRW1CASRWN.PCIE_IMUX8_R_13 always +PCIE_BOT.PCIE_CFGPMFORCESTATEENN.PCIE_IMUX10_L_1 always +PCIE_BOT.PCIE_CFGPMHALTASPML0SN.PCIE_IMUX8_L_1 always +PCIE_BOT.PCIE_CFGPMHALTASPML1N.PCIE_IMUX9_L_1 always +PCIE_BOT.PCIE_CFGPMSENDPMETON.PCIE_IMUX11_L_2 always +PCIE_BOT.PCIE_CFGPMTURNOFFOKN.PCIE_IMUX10_L_2 always +PCIE_BOT.PCIE_CFGPMWAKEN.PCIE_IMUX9_L_2 always +PCIE_BOT.PCIE_CFGTRNPENDINGN.PCIE_IMUX9_L_4 always +PCIE_BOT.PCIE_CMRSTN.PCIE_CTRL1_R_0 always +PCIE_BOT.PCIE_CMSTICKYRSTN.PCIE_CTRL0_R_1 always +PCIE_BOT.PCIE_DBGSUBMODE.PCIE_IMUX21_R_12 always +PCIE_BOT.PCIE_DLRSTN.PCIE_CTRL1_R_2 always +PCIE_BOT.PCIE_DRPCLK.PCIE_CLK1_R_11 always +PCIE_BOT.PCIE_DRPEN.PCIE_IMUX13_L_16 always +PCIE_BOT.PCIE_DRPWE.PCIE_IMUX12_L_17 always +PCIE_BOT.PCIE_FUNCLVLRSTN.PCIE_CTRL1_R_1 always +PCIE_BOT.PCIE_LOGIC_OUTS_B0_L_0.PCIE_PIPETX3DATA12 always +PCIE_BOT.PCIE_LOGIC_OUTS_B0_L_1.PCIE_PLRXPMSTATE0 always +PCIE_BOT.PCIE_LOGIC_OUTS_B0_L_2.PCIE_PIPETX3DATA4 always +PCIE_BOT.PCIE_LOGIC_OUTS_B0_L_3.PCIE_PLDIRECTEDCHANGEDONE always +PCIE_BOT.PCIE_LOGIC_OUTS_B0_L_4.PCIE_PIPETX1DATA12 always +PCIE_BOT.PCIE_LOGIC_OUTS_B0_L_5.PCIE_TRNTCFGREQ always +PCIE_BOT.PCIE_LOGIC_OUTS_B0_L_6.PCIE_PIPETX1DATA4 always +PCIE_BOT.PCIE_LOGIC_OUTS_B0_L_7.PCIE_TRNRD7 always +PCIE_BOT.PCIE_LOGIC_OUTS_B0_L_8.PCIE_TRNRD11 always +PCIE_BOT.PCIE_LOGIC_OUTS_B0_L_9.PCIE_TRNRD15 always +PCIE_BOT.PCIE_LOGIC_OUTS_B0_L_10.PCIE_TRNRD19 always +PCIE_BOT.PCIE_LOGIC_OUTS_B0_L_11.PCIE_PIPETX2DATA12 always +PCIE_BOT.PCIE_LOGIC_OUTS_B0_L_12.PCIE_TRNRD27 always +PCIE_BOT.PCIE_LOGIC_OUTS_B0_L_13.PCIE_PIPETX2DATA4 always +PCIE_BOT.PCIE_LOGIC_OUTS_B0_L_14.PCIE_TRNRD35 always +PCIE_BOT.PCIE_LOGIC_OUTS_B0_L_15.PCIE_PIPETX0DATA12 always +PCIE_BOT.PCIE_LOGIC_OUTS_B0_L_16.PCIE_TRNRD43 always +PCIE_BOT.PCIE_LOGIC_OUTS_B0_L_17.PCIE_PIPETX0DATA4 always +PCIE_BOT.PCIE_LOGIC_OUTS_B0_L_18.PCIE_TRNRD51 always +PCIE_BOT.PCIE_LOGIC_OUTS_B0_L_19.PCIE_TRNRD55 always +PCIE_BOT.PCIE_LOGIC_OUTS_B0_R_0.PCIE_PIPETX7DATA12 always +PCIE_BOT.PCIE_LOGIC_OUTS_B0_R_1.PCIE_TRNFCPD2 always +PCIE_BOT.PCIE_LOGIC_OUTS_B0_R_2.PCIE_PIPETX7DATA4 always +PCIE_BOT.PCIE_LOGIC_OUTS_B0_R_3.PCIE_TRNFCPH6 always +PCIE_BOT.PCIE_LOGIC_OUTS_B0_R_4.PCIE_PIPETX5DATA12 always +PCIE_BOT.PCIE_LOGIC_OUTS_B0_R_5.PCIE_MIMTXWDATA20 always +PCIE_BOT.PCIE_LOGIC_OUTS_B0_R_6.PCIE_PIPETX5DATA4 always +PCIE_BOT.PCIE_LOGIC_OUTS_B0_R_7.PCIE_TRNLNKUP always +PCIE_BOT.PCIE_LOGIC_OUTS_B0_R_8.PCIE_PIPETXDEEMPH always +PCIE_BOT.PCIE_LOGIC_OUTS_B0_R_9.PCIE_TRNRBARHIT0 always +PCIE_BOT.PCIE_LOGIC_OUTS_B0_R_10.PCIE_TRNRSRCRDY always +PCIE_BOT.PCIE_LOGIC_OUTS_B0_R_11.PCIE_PIPETX6DATA12 always +PCIE_BOT.PCIE_LOGIC_OUTS_B0_R_12.PCIE_TRNRD124 always +PCIE_BOT.PCIE_LOGIC_OUTS_B0_R_13.PCIE_PIPETX6DATA4 always +PCIE_BOT.PCIE_LOGIC_OUTS_B0_R_14.PCIE_TRNRD116 always +PCIE_BOT.PCIE_LOGIC_OUTS_B0_R_15.PCIE_PIPETX4DATA12 always +PCIE_BOT.PCIE_LOGIC_OUTS_B0_R_16.PCIE_TRNRD110 always +PCIE_BOT.PCIE_LOGIC_OUTS_B0_R_17.PCIE_PIPETX4DATA4 always +PCIE_BOT.PCIE_LOGIC_OUTS_B0_R_18.PCIE_TRNRD103 always +PCIE_BOT.PCIE_LOGIC_OUTS_B0_R_19.PCIE_MIMRXWDATA16 always +PCIE_BOT.PCIE_LOGIC_OUTS_B1_L_0.PCIE_PLSELLNKRATE always +PCIE_BOT.PCIE_LOGIC_OUTS_B1_L_1.PCIE_PLRXPMSTATE1 always +PCIE_BOT.PCIE_LOGIC_OUTS_B1_L_2.PCIE_PIPETX3POWERDOWN0 always +PCIE_BOT.PCIE_LOGIC_OUTS_B1_L_3.PCIE_PIPERX3POLARITY always +PCIE_BOT.PCIE_LOGIC_OUTS_B1_L_4.PCIE_TRNTBUFAV2 always +PCIE_BOT.PCIE_LOGIC_OUTS_B1_L_5.PCIE_TRNRD0 always +PCIE_BOT.PCIE_LOGIC_OUTS_B1_L_6.PCIE_PIPETX1POWERDOWN0 always +PCIE_BOT.PCIE_LOGIC_OUTS_B1_L_7.PCIE_PIPERX1POLARITY always +PCIE_BOT.PCIE_LOGIC_OUTS_B1_L_8.PCIE_TRNRD12 always +PCIE_BOT.PCIE_LOGIC_OUTS_B1_L_9.PCIE_TRNRD16 always +PCIE_BOT.PCIE_LOGIC_OUTS_B1_L_10.PCIE_TRNRD20 always +PCIE_BOT.PCIE_LOGIC_OUTS_B1_L_11.PCIE_TRNRD23 always +PCIE_BOT.PCIE_LOGIC_OUTS_B1_L_12.PCIE_TRNRD28 always +PCIE_BOT.PCIE_LOGIC_OUTS_B1_L_13.PCIE_PIPETX2POWERDOWN0 always +PCIE_BOT.PCIE_LOGIC_OUTS_B1_L_14.PCIE_PIPERX2POLARITY always +PCIE_BOT.PCIE_LOGIC_OUTS_B1_L_15.PCIE_TRNRD39 always +PCIE_BOT.PCIE_LOGIC_OUTS_B1_L_16.PCIE_TRNRD44 always +PCIE_BOT.PCIE_LOGIC_OUTS_B1_L_17.PCIE_PIPETX0POWERDOWN0 always +PCIE_BOT.PCIE_LOGIC_OUTS_B1_L_18.PCIE_PIPERX0POLARITY always +PCIE_BOT.PCIE_LOGIC_OUTS_B1_L_19.PCIE_TRNRD56 always +PCIE_BOT.PCIE_LOGIC_OUTS_B1_R_0.PCIE_MIMTXWDATA40 always +PCIE_BOT.PCIE_LOGIC_OUTS_B1_R_1.PCIE_TRNFCPD3 always +PCIE_BOT.PCIE_LOGIC_OUTS_B1_R_2.PCIE_PIPETX7POWERDOWN0 always +PCIE_BOT.PCIE_LOGIC_OUTS_B1_R_3.PCIE_PIPERX7POLARITY always +PCIE_BOT.PCIE_LOGIC_OUTS_B1_R_4.PCIE_MIMTXWDATA16 always +PCIE_BOT.PCIE_LOGIC_OUTS_B1_R_5.PCIE_MIMTXWDATA18 always +PCIE_BOT.PCIE_LOGIC_OUTS_B1_R_6.PCIE_PIPETX5POWERDOWN0 always +PCIE_BOT.PCIE_LOGIC_OUTS_B1_R_7.PCIE_PIPERX5POLARITY always +PCIE_BOT.PCIE_LOGIC_OUTS_B1_R_8.PCIE_TRNRBARHIT4 always +PCIE_BOT.PCIE_LOGIC_OUTS_B1_R_9.PCIE_TRNRBARHIT1 always +PCIE_BOT.PCIE_LOGIC_OUTS_B1_R_10.PCIE_TRNTDSTRDY0 always +PCIE_BOT.PCIE_LOGIC_OUTS_B1_R_11.PCIE_TRNRREM0 always +PCIE_BOT.PCIE_LOGIC_OUTS_B1_R_12.PCIE_TRNRD125 always +PCIE_BOT.PCIE_LOGIC_OUTS_B1_R_13.PCIE_PIPETX6POWERDOWN0 always +PCIE_BOT.PCIE_LOGIC_OUTS_B1_R_14.PCIE_PIPERX6POLARITY always +PCIE_BOT.PCIE_LOGIC_OUTS_B1_R_15.PCIE_TRNTDSTRDY1 always +PCIE_BOT.PCIE_LOGIC_OUTS_B1_R_16.PCIE_TRNRD111 always +PCIE_BOT.PCIE_LOGIC_OUTS_B1_R_17.PCIE_PIPETX4POWERDOWN0 always +PCIE_BOT.PCIE_LOGIC_OUTS_B1_R_18.PCIE_PIPERX4POLARITY always +PCIE_BOT.PCIE_LOGIC_OUTS_B1_R_19.PCIE_TRNRD99 always +PCIE_BOT.PCIE_LOGIC_OUTS_B2_L_0.PCIE_PIPETX3DATA14 always +PCIE_BOT.PCIE_LOGIC_OUTS_B2_L_1.PCIE_PLLINKUPCFGCAP always +PCIE_BOT.PCIE_LOGIC_OUTS_B2_L_2.PCIE_PIPETX3DATA6 always +PCIE_BOT.PCIE_LOGIC_OUTS_B2_L_3.PCIE_TRNTERRDROP always +PCIE_BOT.PCIE_LOGIC_OUTS_B2_L_4.PCIE_PIPETX1DATA14 always +PCIE_BOT.PCIE_LOGIC_OUTS_B2_L_5.PCIE_TRNRD1 always +PCIE_BOT.PCIE_LOGIC_OUTS_B2_L_6.PCIE_PIPETX1DATA6 always +PCIE_BOT.PCIE_LOGIC_OUTS_B2_L_7.PCIE_TRNRD8 always +PCIE_BOT.PCIE_LOGIC_OUTS_B2_L_8.PCIE_TRNRD13 always +PCIE_BOT.PCIE_LOGIC_OUTS_B2_L_9.PCIE_TRNRD17 always +PCIE_BOT.PCIE_LOGIC_OUTS_B2_L_10.PCIE_TRNRD21 always +PCIE_BOT.PCIE_LOGIC_OUTS_B2_L_11.PCIE_PIPETX2DATA14 always +PCIE_BOT.PCIE_LOGIC_OUTS_B2_L_12.PCIE_TRNRD29 always +PCIE_BOT.PCIE_LOGIC_OUTS_B2_L_13.PCIE_PIPETX2DATA6 always +PCIE_BOT.PCIE_LOGIC_OUTS_B2_L_14.PCIE_TRNRD36 always +PCIE_BOT.PCIE_LOGIC_OUTS_B2_L_15.PCIE_PIPETX0DATA14 always +PCIE_BOT.PCIE_LOGIC_OUTS_B2_L_16.PCIE_TRNRD45 always +PCIE_BOT.PCIE_LOGIC_OUTS_B2_L_17.PCIE_PIPETX0DATA6 always +PCIE_BOT.PCIE_LOGIC_OUTS_B2_L_18.PCIE_TRNRD52 always +PCIE_BOT.PCIE_LOGIC_OUTS_B2_L_19.PCIE_TRNRD57 always +PCIE_BOT.PCIE_LOGIC_OUTS_B2_R_0.PCIE_PIPETX7DATA14 always +PCIE_BOT.PCIE_LOGIC_OUTS_B2_R_1.PCIE_TRNFCPD4 always +PCIE_BOT.PCIE_LOGIC_OUTS_B2_R_2.PCIE_PIPETX7DATA6 always +PCIE_BOT.PCIE_LOGIC_OUTS_B2_R_3.PCIE_MIMTXWADDR11 always +PCIE_BOT.PCIE_LOGIC_OUTS_B2_R_4.PCIE_PIPETX5DATA14 always +PCIE_BOT.PCIE_LOGIC_OUTS_B2_R_5.PCIE_TRNFCPH2 always +PCIE_BOT.PCIE_LOGIC_OUTS_B2_R_6.PCIE_PIPETX5DATA6 always +PCIE_BOT.PCIE_LOGIC_OUTS_B2_R_7.PCIE_TRNFCPH0 always +PCIE_BOT.PCIE_LOGIC_OUTS_B2_R_8.PCIE_TRNRBARHIT5 always +PCIE_BOT.PCIE_LOGIC_OUTS_B2_R_9.PCIE_TRNRBARHIT2 always +PCIE_BOT.PCIE_LOGIC_OUTS_B2_R_10.PCIE_MIMTXWDATA29 always +PCIE_BOT.PCIE_LOGIC_OUTS_B2_R_11.PCIE_PIPETX6DATA14 always +PCIE_BOT.PCIE_LOGIC_OUTS_B2_R_12.PCIE_TRNRD126 always +PCIE_BOT.PCIE_LOGIC_OUTS_B2_R_13.PCIE_PIPETX6DATA6 always +PCIE_BOT.PCIE_LOGIC_OUTS_B2_R_14.PCIE_TRNRD117 always +PCIE_BOT.PCIE_LOGIC_OUTS_B2_R_15.PCIE_PIPETX4DATA14 always +PCIE_BOT.PCIE_LOGIC_OUTS_B2_R_16.PCIE_DBGVECA32 always +PCIE_BOT.PCIE_LOGIC_OUTS_B2_R_17.PCIE_PIPETX4DATA6 always +PCIE_BOT.PCIE_LOGIC_OUTS_B2_R_18.PCIE_TRNRD104 always +PCIE_BOT.PCIE_LOGIC_OUTS_B2_R_19.PCIE_MIMRXWDATA18 always +PCIE_BOT.PCIE_LOGIC_OUTS_B3_L_0.PCIE_PLSELLNKWIDTH0 always +PCIE_BOT.PCIE_LOGIC_OUTS_B3_L_1.PCIE_PLLINKGEN2CAP always +PCIE_BOT.PCIE_LOGIC_OUTS_B3_L_2.PCIE_PIPETX3ELECIDLE always +PCIE_BOT.PCIE_LOGIC_OUTS_B3_L_3.PCIE_PIPETX3COMPLIANCE always +PCIE_BOT.PCIE_LOGIC_OUTS_B3_L_4.PCIE_TRNTBUFAV3 always +PCIE_BOT.PCIE_LOGIC_OUTS_B3_L_5.PCIE_TRNRD2 always +PCIE_BOT.PCIE_LOGIC_OUTS_B3_L_6.PCIE_PIPETX1ELECIDLE always +PCIE_BOT.PCIE_LOGIC_OUTS_B3_L_7.PCIE_PIPETX1COMPLIANCE always +PCIE_BOT.PCIE_LOGIC_OUTS_B3_L_8.PCIE_TRNRD14 always +PCIE_BOT.PCIE_LOGIC_OUTS_B3_L_9.PCIE_TRNRD18 always +PCIE_BOT.PCIE_LOGIC_OUTS_B3_L_10.PCIE_TRNRD22 always +PCIE_BOT.PCIE_LOGIC_OUTS_B3_L_11.PCIE_TRNRD24 always +PCIE_BOT.PCIE_LOGIC_OUTS_B3_L_12.PCIE_TRNRD30 always +PCIE_BOT.PCIE_LOGIC_OUTS_B3_L_13.PCIE_PIPETX2ELECIDLE always +PCIE_BOT.PCIE_LOGIC_OUTS_B3_L_14.PCIE_PIPETX2COMPLIANCE always +PCIE_BOT.PCIE_LOGIC_OUTS_B3_L_15.PCIE_TRNRD40 always +PCIE_BOT.PCIE_LOGIC_OUTS_B3_L_16.PCIE_TRNRD46 always +PCIE_BOT.PCIE_LOGIC_OUTS_B3_L_17.PCIE_PIPETX0ELECIDLE always +PCIE_BOT.PCIE_LOGIC_OUTS_B3_L_18.PCIE_PIPETX0COMPLIANCE always +PCIE_BOT.PCIE_LOGIC_OUTS_B3_L_19.PCIE_TRNRD58 always +PCIE_BOT.PCIE_LOGIC_OUTS_B3_R_0.PCIE_TRNTDSTRDY2 always +PCIE_BOT.PCIE_LOGIC_OUTS_B3_R_1.PCIE_TRNFCPD5 always +PCIE_BOT.PCIE_LOGIC_OUTS_B3_R_2.PCIE_PIPETX7ELECIDLE always +PCIE_BOT.PCIE_LOGIC_OUTS_B3_R_3.PCIE_PIPETX7COMPLIANCE always +PCIE_BOT.PCIE_LOGIC_OUTS_B3_R_4.PCIE_MIMTXRADDR9 always +PCIE_BOT.PCIE_LOGIC_OUTS_B3_R_5.PCIE_TRNFCPH3 always +PCIE_BOT.PCIE_LOGIC_OUTS_B3_R_6.PCIE_PIPETX5ELECIDLE always +PCIE_BOT.PCIE_LOGIC_OUTS_B3_R_7.PCIE_PIPETX5COMPLIANCE always +PCIE_BOT.PCIE_LOGIC_OUTS_B3_R_8.PCIE_TRNRBARHIT6 always +PCIE_BOT.PCIE_LOGIC_OUTS_B3_R_9.PCIE_TRNRBARHIT3 always +PCIE_BOT.PCIE_LOGIC_OUTS_B3_R_10.PCIE_TRNRSRCDSC always +PCIE_BOT.PCIE_LOGIC_OUTS_B3_R_11.PCIE_TRNRREM1 always +PCIE_BOT.PCIE_LOGIC_OUTS_B3_R_12.PCIE_TRNRD127 always +PCIE_BOT.PCIE_LOGIC_OUTS_B3_R_13.PCIE_PIPETX6ELECIDLE always +PCIE_BOT.PCIE_LOGIC_OUTS_B3_R_14.PCIE_PIPETX6COMPLIANCE always +PCIE_BOT.PCIE_LOGIC_OUTS_B3_R_15.PCIE_TRNRD112 always +PCIE_BOT.PCIE_LOGIC_OUTS_B3_R_16.PCIE_LL2LINKSTATUS2 always +PCIE_BOT.PCIE_LOGIC_OUTS_B3_R_17.PCIE_PIPETX4ELECIDLE always +PCIE_BOT.PCIE_LOGIC_OUTS_B3_R_18.PCIE_PIPETX4COMPLIANCE always +PCIE_BOT.PCIE_LOGIC_OUTS_B3_R_19.PCIE_TRNRD100 always +PCIE_BOT.PCIE_LOGIC_OUTS_B4_L_0.PCIE_PIPETX3DATA13 always +PCIE_BOT.PCIE_LOGIC_OUTS_B4_L_1.PCIE_TRNFCPD9 always +PCIE_BOT.PCIE_LOGIC_OUTS_B4_L_2.PCIE_PIPETX3DATA5 always +PCIE_BOT.PCIE_LOGIC_OUTS_B4_L_3.PCIE_TRNTBUFAV0 always +PCIE_BOT.PCIE_LOGIC_OUTS_B4_L_4.PCIE_PIPETX1DATA13 always +PCIE_BOT.PCIE_LOGIC_OUTS_B4_L_5.PCIE_TRNFCNPD5 always +PCIE_BOT.PCIE_LOGIC_OUTS_B4_L_6.PCIE_PIPETX1DATA5 always +PCIE_BOT.PCIE_LOGIC_OUTS_B4_L_7.PCIE_TRNRD9 always +PCIE_BOT.PCIE_LOGIC_OUTS_B4_L_8.PCIE_TRNFCCPLH5 always +PCIE_BOT.PCIE_LOGIC_OUTS_B4_L_9.PCIE_TRNFCCPLD1 always +PCIE_BOT.PCIE_LOGIC_OUTS_B4_L_10.PCIE_TRNFCCPLD5 always +PCIE_BOT.PCIE_LOGIC_OUTS_B4_L_11.PCIE_PIPETX2DATA13 always +PCIE_BOT.PCIE_LOGIC_OUTS_B4_L_12.PCIE_TRNRDLLPDATA0 always +PCIE_BOT.PCIE_LOGIC_OUTS_B4_L_13.PCIE_PIPETX2DATA5 always +PCIE_BOT.PCIE_LOGIC_OUTS_B4_L_14.PCIE_TRNRD37 always +PCIE_BOT.PCIE_LOGIC_OUTS_B4_L_15.PCIE_PIPETX0DATA13 always +PCIE_BOT.PCIE_LOGIC_OUTS_B4_L_16.PCIE_TRNRDLLPDATA16 always +PCIE_BOT.PCIE_LOGIC_OUTS_B4_L_17.PCIE_PIPETX0DATA5 always +PCIE_BOT.PCIE_LOGIC_OUTS_B4_L_18.PCIE_TRNRD53 always +PCIE_BOT.PCIE_LOGIC_OUTS_B4_L_19.PCIE_TRNRDLLPDATA28 always +PCIE_BOT.PCIE_LOGIC_OUTS_B4_R_0.PCIE_PIPETX7DATA13 always +PCIE_BOT.PCIE_LOGIC_OUTS_B4_R_1.PCIE_TL2ERRHDR18 always +PCIE_BOT.PCIE_LOGIC_OUTS_B4_R_2.PCIE_PIPETX7DATA5 always +PCIE_BOT.PCIE_LOGIC_OUTS_B4_R_3.PCIE_TRNFCPH7 always +PCIE_BOT.PCIE_LOGIC_OUTS_B4_R_4.PCIE_PIPETX5DATA13 always +PCIE_BOT.PCIE_LOGIC_OUTS_B4_R_5.PCIE_TRNFCPH4 always +PCIE_BOT.PCIE_LOGIC_OUTS_B4_R_6.PCIE_PIPETX5DATA5 always +PCIE_BOT.PCIE_LOGIC_OUTS_B4_R_7.PCIE_MIMTXWDATA33 always +PCIE_BOT.PCIE_LOGIC_OUTS_B4_R_8.PCIE_MIMTXWDATA19 always +PCIE_BOT.PCIE_LOGIC_OUTS_B4_R_9.PCIE_MIMTXWDATA5 always +PCIE_BOT.PCIE_LOGIC_OUTS_B4_R_10.PCIE_TRNRECRCERR always +PCIE_BOT.PCIE_LOGIC_OUTS_B4_R_11.PCIE_PIPETX6DATA13 always +PCIE_BOT.PCIE_LOGIC_OUTS_B4_R_12.PCIE_LL2REPLAYROERR always +PCIE_BOT.PCIE_LOGIC_OUTS_B4_R_13.PCIE_PIPETX6DATA5 always +PCIE_BOT.PCIE_LOGIC_OUTS_B4_R_14.PCIE_TRNRD118 always +PCIE_BOT.PCIE_LOGIC_OUTS_B4_R_15.PCIE_PIPETX4DATA13 always +PCIE_BOT.PCIE_LOGIC_OUTS_B4_R_16.PCIE_LL2LINKSTATUS3 always +PCIE_BOT.PCIE_LOGIC_OUTS_B4_R_17.PCIE_PIPETX4DATA5 always +PCIE_BOT.PCIE_LOGIC_OUTS_B4_R_18.PCIE_MIMRXWDATA14 always +PCIE_BOT.PCIE_LOGIC_OUTS_B4_R_19.PCIE_TRNRD101 always +PCIE_BOT.PCIE_LOGIC_OUTS_B5_L_0.PCIE_PLSELLNKWIDTH1 always +PCIE_BOT.PCIE_LOGIC_OUTS_B5_L_1.PCIE_TRNFCPD10 always +PCIE_BOT.PCIE_LOGIC_OUTS_B5_L_2.PCIE_PLLINKPARTNERGEN2SUPPORTED always +PCIE_BOT.PCIE_LOGIC_OUTS_B5_L_3.PCIE_TRNTBUFAV1 always +PCIE_BOT.PCIE_LOGIC_OUTS_B5_L_4.PCIE_TRNTBUFAV4 always +PCIE_BOT.PCIE_LOGIC_OUTS_B5_L_5.PCIE_TRNFCNPD6 always +PCIE_BOT.PCIE_LOGIC_OUTS_B5_L_6.PCIE_TRNRD3 always +PCIE_BOT.PCIE_LOGIC_OUTS_B5_L_7.PCIE_TRNRD10 always +PCIE_BOT.PCIE_LOGIC_OUTS_B5_L_8.PCIE_TRNFCCPLH6 always +PCIE_BOT.PCIE_LOGIC_OUTS_B5_L_9.PCIE_TRNFCCPLD2 always +PCIE_BOT.PCIE_LOGIC_OUTS_B5_L_10.PCIE_TRNFCCPLD6 always +PCIE_BOT.PCIE_LOGIC_OUTS_B5_L_11.PCIE_TRNRD25 always +PCIE_BOT.PCIE_LOGIC_OUTS_B5_L_12.PCIE_TRNRDLLPDATA1 always +PCIE_BOT.PCIE_LOGIC_OUTS_B5_L_13.PCIE_TRNRD31 always +PCIE_BOT.PCIE_LOGIC_OUTS_B5_L_14.PCIE_TRNRD38 always +PCIE_BOT.PCIE_LOGIC_OUTS_B5_L_15.PCIE_TRNRD41 always +PCIE_BOT.PCIE_LOGIC_OUTS_B5_L_16.PCIE_TRNRDLLPDATA17 always +PCIE_BOT.PCIE_LOGIC_OUTS_B5_L_17.PCIE_TRNRD47 always +PCIE_BOT.PCIE_LOGIC_OUTS_B5_L_18.PCIE_TRNRD54 always +PCIE_BOT.PCIE_LOGIC_OUTS_B5_L_19.PCIE_TRNRDLLPDATA29 always +PCIE_BOT.PCIE_LOGIC_OUTS_B5_R_0.PCIE_TRNFCPD6 always +PCIE_BOT.PCIE_LOGIC_OUTS_B5_R_1.PCIE_MIMTXWDATA62 always +PCIE_BOT.PCIE_LOGIC_OUTS_B5_R_2.PCIE_MIMTXWDATA68 always +PCIE_BOT.PCIE_LOGIC_OUTS_B5_R_3.PCIE_TRNFCPD0 always +PCIE_BOT.PCIE_LOGIC_OUTS_B5_R_4.PCIE_TRNFCPH5 always +PCIE_BOT.PCIE_LOGIC_OUTS_B5_R_5.PCIE_MIMTXWDATA4 always +PCIE_BOT.PCIE_LOGIC_OUTS_B5_R_6.PCIE_MIMTXWDATA26 always +PCIE_BOT.PCIE_LOGIC_OUTS_B5_R_7.PCIE_MIMTXWDATA17 always +PCIE_BOT.PCIE_LOGIC_OUTS_B5_R_8.PCIE_MIMTXWDATA21 always +PCIE_BOT.PCIE_LOGIC_OUTS_B5_R_9.PCIE_MIMTXWDATA13 always +PCIE_BOT.PCIE_LOGIC_OUTS_B5_R_10.PCIE_TRNRERRFWD always +PCIE_BOT.PCIE_LOGIC_OUTS_B5_R_11.PCIE_TRNRSOF always +PCIE_BOT.PCIE_LOGIC_OUTS_B5_R_12.PCIE_LL2REPLAYTOERR always +PCIE_BOT.PCIE_LOGIC_OUTS_B5_R_13.PCIE_TRNRD120 always +PCIE_BOT.PCIE_LOGIC_OUTS_B5_R_14.PCIE_TRNRD119 always +PCIE_BOT.PCIE_LOGIC_OUTS_B5_R_15.PCIE_TRNRD113 always +PCIE_BOT.PCIE_LOGIC_OUTS_B5_R_16.PCIE_MIMRXWDATA54 always +PCIE_BOT.PCIE_LOGIC_OUTS_B5_R_17.PCIE_TRNRD106 always +PCIE_BOT.PCIE_LOGIC_OUTS_B5_R_18.PCIE_TRNRD105 always +PCIE_BOT.PCIE_LOGIC_OUTS_B5_R_19.PCIE_MIMRXWDATA57 always +PCIE_BOT.PCIE_LOGIC_OUTS_B6_L_0.PCIE_PIPETX3DATA15 always +PCIE_BOT.PCIE_LOGIC_OUTS_B6_L_1.PCIE_TRNFCPD11 always +PCIE_BOT.PCIE_LOGIC_OUTS_B6_L_2.PCIE_PIPETX3DATA7 always +PCIE_BOT.PCIE_LOGIC_OUTS_B6_L_3.PCIE_TRNFCNPH5 always +PCIE_BOT.PCIE_LOGIC_OUTS_B6_L_4.PCIE_PIPETX1DATA15 always +PCIE_BOT.PCIE_LOGIC_OUTS_B6_L_5.PCIE_TRNFCNPD7 always +PCIE_BOT.PCIE_LOGIC_OUTS_B6_L_6.PCIE_PIPETX1DATA7 always +PCIE_BOT.PCIE_LOGIC_OUTS_B6_L_7.PCIE_TRNFCCPLH1 always +PCIE_BOT.PCIE_LOGIC_OUTS_B6_L_8.PCIE_TRNFCCPLH7 always +PCIE_BOT.PCIE_LOGIC_OUTS_B6_L_9.PCIE_TRNFCCPLD3 always +PCIE_BOT.PCIE_LOGIC_OUTS_B6_L_10.PCIE_TRNFCCPLD7 always +PCIE_BOT.PCIE_LOGIC_OUTS_B6_L_11.PCIE_PIPETX2DATA15 always +PCIE_BOT.PCIE_LOGIC_OUTS_B6_L_12.PCIE_TRNRDLLPDATA2 always +PCIE_BOT.PCIE_LOGIC_OUTS_B6_L_13.PCIE_PIPETX2DATA7 always +PCIE_BOT.PCIE_LOGIC_OUTS_B6_L_14.PCIE_TRNRDLLPDATA8 always +PCIE_BOT.PCIE_LOGIC_OUTS_B6_L_15.PCIE_PIPETX0DATA15 always +PCIE_BOT.PCIE_LOGIC_OUTS_B6_L_16.PCIE_TRNRDLLPDATA18 always +PCIE_BOT.PCIE_LOGIC_OUTS_B6_L_17.PCIE_PIPETX0DATA7 always +PCIE_BOT.PCIE_LOGIC_OUTS_B6_L_18.PCIE_TRNRDLLPDATA24 always +PCIE_BOT.PCIE_LOGIC_OUTS_B6_L_19.PCIE_TRNRDLLPDATA30 always +PCIE_BOT.PCIE_LOGIC_OUTS_B6_R_0.PCIE_PIPETX7DATA15 always +PCIE_BOT.PCIE_LOGIC_OUTS_B6_R_1.PCIE_MIMTXWADDR1 always +PCIE_BOT.PCIE_LOGIC_OUTS_B6_R_2.PCIE_PIPETX7DATA7 always +PCIE_BOT.PCIE_LOGIC_OUTS_B6_R_3.PCIE_MIMTXWDATA61 always +PCIE_BOT.PCIE_LOGIC_OUTS_B6_R_4.PCIE_PIPETX5DATA15 always +PCIE_BOT.PCIE_LOGIC_OUTS_B6_R_5.PCIE_DBGVECB18 always +PCIE_BOT.PCIE_LOGIC_OUTS_B6_R_6.PCIE_PIPETX5DATA7 always +PCIE_BOT.PCIE_LOGIC_OUTS_B6_R_7.PCIE_TRNFCPH1 always +PCIE_BOT.PCIE_LOGIC_OUTS_B6_R_8.PCIE_TRNRBARHIT7 always +PCIE_BOT.PCIE_LOGIC_OUTS_B6_R_9.PCIE_TL2ERRHDR10 always +PCIE_BOT.PCIE_LOGIC_OUTS_B6_R_10.PCIE_TL2ERRHDR6 always +PCIE_BOT.PCIE_LOGIC_OUTS_B6_R_11.PCIE_PIPETX6DATA15 always +PCIE_BOT.PCIE_LOGIC_OUTS_B6_R_12.PCIE_TL2ERRHDR0 always +PCIE_BOT.PCIE_LOGIC_OUTS_B6_R_13.PCIE_PIPETX6DATA7 always +PCIE_BOT.PCIE_LOGIC_OUTS_B6_R_14.PCIE_TL2ASPMSUSPENDREQ always +PCIE_BOT.PCIE_LOGIC_OUTS_B6_R_15.PCIE_PIPETX4DATA15 always +PCIE_BOT.PCIE_LOGIC_OUTS_B6_R_16.PCIE_MIMRXWDATA56 always +PCIE_BOT.PCIE_LOGIC_OUTS_B6_R_17.PCIE_PIPETX4DATA7 always +PCIE_BOT.PCIE_LOGIC_OUTS_B6_R_18.PCIE_MIMRXWDATA60 always +PCIE_BOT.PCIE_LOGIC_OUTS_B6_R_19.PCIE_TRNRD102 always +PCIE_BOT.PCIE_LOGIC_OUTS_B7_L_0.PCIE_PLLTSSMSTATE0 always +PCIE_BOT.PCIE_LOGIC_OUTS_B7_L_1.PCIE_TRNFCNPH0 always +PCIE_BOT.PCIE_LOGIC_OUTS_B7_L_2.PCIE_PIPETX3POWERDOWN1 always +PCIE_BOT.PCIE_LOGIC_OUTS_B7_L_3.PCIE_TRNFCNPH6 always +PCIE_BOT.PCIE_LOGIC_OUTS_B7_L_4.PCIE_TRNTBUFAV5 always +PCIE_BOT.PCIE_LOGIC_OUTS_B7_L_5.PCIE_TRNFCNPD8 always +PCIE_BOT.PCIE_LOGIC_OUTS_B7_L_6.PCIE_PIPETX1POWERDOWN1 always +PCIE_BOT.PCIE_LOGIC_OUTS_B7_L_7.PCIE_TRNFCCPLH2 always +PCIE_BOT.PCIE_LOGIC_OUTS_B7_L_8.PCIE_TRNFCCPLD0 always +PCIE_BOT.PCIE_LOGIC_OUTS_B7_L_9.PCIE_TRNFCCPLD4 always +PCIE_BOT.PCIE_LOGIC_OUTS_B7_L_10.PCIE_TRNFCCPLD8 always +PCIE_BOT.PCIE_LOGIC_OUTS_B7_L_11.PCIE_TRNRD26 always +PCIE_BOT.PCIE_LOGIC_OUTS_B7_L_12.PCIE_TRNRDLLPDATA3 always +PCIE_BOT.PCIE_LOGIC_OUTS_B7_L_13.PCIE_PIPETX2POWERDOWN1 always +PCIE_BOT.PCIE_LOGIC_OUTS_B7_L_14.PCIE_TRNRDLLPDATA9 always +PCIE_BOT.PCIE_LOGIC_OUTS_B7_L_15.PCIE_TRNRD42 always +PCIE_BOT.PCIE_LOGIC_OUTS_B7_L_16.PCIE_TRNRDLLPDATA19 always +PCIE_BOT.PCIE_LOGIC_OUTS_B7_L_17.PCIE_PIPETX0POWERDOWN1 always +PCIE_BOT.PCIE_LOGIC_OUTS_B7_L_18.PCIE_TRNRDLLPDATA25 always +PCIE_BOT.PCIE_LOGIC_OUTS_B7_L_19.PCIE_TRNRDLLPDATA31 always +PCIE_BOT.PCIE_LOGIC_OUTS_B7_R_0.PCIE_TRNFCPD7 always +PCIE_BOT.PCIE_LOGIC_OUTS_B7_R_1.PCIE_MIMTXWDATA50 always +PCIE_BOT.PCIE_LOGIC_OUTS_B7_R_2.PCIE_PIPETX7POWERDOWN1 always +PCIE_BOT.PCIE_LOGIC_OUTS_B7_R_3.PCIE_DBGVECB26 always +PCIE_BOT.PCIE_LOGIC_OUTS_B7_R_4.PCIE_DBGVECB22 always +PCIE_BOT.PCIE_LOGIC_OUTS_B7_R_5.PCIE_DBGVECB19 always +PCIE_BOT.PCIE_LOGIC_OUTS_B7_R_6.PCIE_PIPETX5POWERDOWN1 always +PCIE_BOT.PCIE_LOGIC_OUTS_B7_R_7.PCIE_MIMTXWDATA3 always +PCIE_BOT.PCIE_LOGIC_OUTS_B7_R_8.PCIE_TL2ERRHDR14 always +PCIE_BOT.PCIE_LOGIC_OUTS_B7_R_9.PCIE_MIMTXWDATA31 always +PCIE_BOT.PCIE_LOGIC_OUTS_B7_R_10.PCIE_TL2ERRHDR7 always +PCIE_BOT.PCIE_LOGIC_OUTS_B7_R_11.PCIE_TRNREOF always +PCIE_BOT.PCIE_LOGIC_OUTS_B7_R_12.PCIE_TL2ERRHDR1 always +PCIE_BOT.PCIE_LOGIC_OUTS_B7_R_13.PCIE_PIPETX6POWERDOWN1 always +PCIE_BOT.PCIE_LOGIC_OUTS_B7_R_14.PCIE_TL2ASPMSUSPENDCREDITCHECKOK always +PCIE_BOT.PCIE_LOGIC_OUTS_B7_R_15.PCIE_TRNRD114 always +PCIE_BOT.PCIE_LOGIC_OUTS_B7_R_16.PCIE_MIMRXWADDR3 always +PCIE_BOT.PCIE_LOGIC_OUTS_B7_R_17.PCIE_PIPETX4POWERDOWN1 always +PCIE_BOT.PCIE_LOGIC_OUTS_B7_R_18.PCIE_DBGVECA25 always +PCIE_BOT.PCIE_LOGIC_OUTS_B7_R_19.PCIE_PL2RXELECIDLE always +PCIE_BOT.PCIE_LOGIC_OUTS_B8_L_0.PCIE_PLLTSSMSTATE1 always +PCIE_BOT.PCIE_LOGIC_OUTS_B8_L_1.PCIE_TL2ERRHDR19 always +PCIE_BOT.PCIE_LOGIC_OUTS_B8_L_2.PCIE_PLINITIALLINKWIDTH0 always +PCIE_BOT.PCIE_LOGIC_OUTS_B8_L_3.PCIE_TRNFCNPH7 always +PCIE_BOT.PCIE_LOGIC_OUTS_B8_L_4.PCIE_TRNFCNPD1 always +PCIE_BOT.PCIE_LOGIC_OUTS_B8_L_5.PCIE_TL2ERRHDR33 always +PCIE_BOT.PCIE_LOGIC_OUTS_B8_L_6.PCIE_TRNRD4 always +PCIE_BOT.PCIE_LOGIC_OUTS_B8_L_7.PCIE_TRNFCCPLH3 always +PCIE_BOT.PCIE_LOGIC_OUTS_B8_L_8.PCIE_TL2ERRHDR43 always +PCIE_BOT.PCIE_LOGIC_OUTS_B8_L_9.PCIE_TL2ERRHDR47 always +PCIE_BOT.PCIE_LOGIC_OUTS_B8_L_10.PCIE_TL2ERRHDR51 always +PCIE_BOT.PCIE_LOGIC_OUTS_B8_L_11.PCIE_TRNFCCPLD9 always +PCIE_BOT.PCIE_LOGIC_OUTS_B8_L_12.PCIE_TL2ERRHDR59 always +PCIE_BOT.PCIE_LOGIC_OUTS_B8_L_13.PCIE_TRNRD32 always +PCIE_BOT.PCIE_LOGIC_OUTS_B8_L_14.PCIE_TRNRDLLPDATA10 always +PCIE_BOT.PCIE_LOGIC_OUTS_B8_L_15.PCIE_TRNRDLLPDATA12 always +PCIE_BOT.PCIE_LOGIC_OUTS_B8_L_16.PCIE_CFGMSGRECEIVEDERRFATAL always +PCIE_BOT.PCIE_LOGIC_OUTS_B8_L_17.PCIE_TRNRD48 always +PCIE_BOT.PCIE_LOGIC_OUTS_B8_L_18.PCIE_TRNRDLLPDATA26 always +PCIE_BOT.PCIE_LOGIC_OUTS_B8_L_19.PCIE_CFGMSGRECEIVEDSETSLOTPOWERLIMIT always +PCIE_BOT.PCIE_LOGIC_OUTS_B8_R_0.PCIE_TRNFCPD8 always +PCIE_BOT.PCIE_LOGIC_OUTS_B8_R_1.PCIE_MIMTXWDATA44 always +PCIE_BOT.PCIE_LOGIC_OUTS_B8_R_2.PCIE_TRNFCPD1 always +PCIE_BOT.PCIE_LOGIC_OUTS_B8_R_3.PCIE_DBGVECB27 always +PCIE_BOT.PCIE_LOGIC_OUTS_B8_R_4.PCIE_DBGVECB23 always +PCIE_BOT.PCIE_LOGIC_OUTS_B8_R_5.PCIE_MIMTXRADDR11 always +PCIE_BOT.PCIE_LOGIC_OUTS_B8_R_6.PCIE_MIMTXREN always +PCIE_BOT.PCIE_LOGIC_OUTS_B8_R_7.PCIE_MIMTXRADDR12 always +PCIE_BOT.PCIE_LOGIC_OUTS_B8_R_8.PCIE_TL2ERRHDR15 always +PCIE_BOT.PCIE_LOGIC_OUTS_B8_R_9.PCIE_MIMTXRADDR10 always +PCIE_BOT.PCIE_LOGIC_OUTS_B8_R_10.PCIE_TL2ERRHDR8 always +PCIE_BOT.PCIE_LOGIC_OUTS_B8_R_11.PCIE_TL2ERRHDR2 always +PCIE_BOT.PCIE_LOGIC_OUTS_B8_R_12.PCIE_CFGMGMTDO6 always +PCIE_BOT.PCIE_LOGIC_OUTS_B8_R_13.PCIE_TRNRD121 always +PCIE_BOT.PCIE_LOGIC_OUTS_B8_R_14.PCIE_PL2LINKUP always +PCIE_BOT.PCIE_LOGIC_OUTS_B8_R_15.PCIE_TRNRD115 always +PCIE_BOT.PCIE_LOGIC_OUTS_B8_R_16.PCIE_MIMRXWADDR8 always +PCIE_BOT.PCIE_LOGIC_OUTS_B8_R_17.PCIE_TRNRD107 always +PCIE_BOT.PCIE_LOGIC_OUTS_B8_R_18.PCIE_DBGVECA26 always +PCIE_BOT.PCIE_LOGIC_OUTS_B8_R_19.PCIE_MIMRXRADDR5 always +PCIE_BOT.PCIE_LOGIC_OUTS_B9_L_0.PCIE_PLLTSSMSTATE2 always +PCIE_BOT.PCIE_LOGIC_OUTS_B9_L_1.PCIE_PIPETX3DATA8 always +PCIE_BOT.PCIE_LOGIC_OUTS_B9_L_2.PCIE_PLINITIALLINKWIDTH1 always +PCIE_BOT.PCIE_LOGIC_OUTS_B9_L_3.PCIE_PIPETX3DATA0 always +PCIE_BOT.PCIE_LOGIC_OUTS_B9_L_4.PCIE_TRNFCNPD2 always +PCIE_BOT.PCIE_LOGIC_OUTS_B9_L_5.PCIE_PIPETX1DATA8 always +PCIE_BOT.PCIE_LOGIC_OUTS_B9_L_6.PCIE_TRNRD5 always +PCIE_BOT.PCIE_LOGIC_OUTS_B9_L_7.PCIE_PIPETX1DATA0 always +PCIE_BOT.PCIE_LOGIC_OUTS_B9_L_8.PCIE_TL2ERRHDR44 always +PCIE_BOT.PCIE_LOGIC_OUTS_B9_L_9.PCIE_TL2ERRHDR48 always +PCIE_BOT.PCIE_LOGIC_OUTS_B9_L_10.PCIE_TL2ERRHDR52 always +PCIE_BOT.PCIE_LOGIC_OUTS_B9_L_11.PCIE_TRNFCCPLD10 always +PCIE_BOT.PCIE_LOGIC_OUTS_B9_L_12.PCIE_PIPETX2DATA8 always +PCIE_BOT.PCIE_LOGIC_OUTS_B9_L_13.PCIE_TRNRD33 always +PCIE_BOT.PCIE_LOGIC_OUTS_B9_L_14.PCIE_PIPETX2DATA0 always +PCIE_BOT.PCIE_LOGIC_OUTS_B9_L_15.PCIE_TRNRDLLPDATA13 always +PCIE_BOT.PCIE_LOGIC_OUTS_B9_L_16.PCIE_PIPETX0DATA8 always +PCIE_BOT.PCIE_LOGIC_OUTS_B9_L_17.PCIE_TRNRD49 always +PCIE_BOT.PCIE_LOGIC_OUTS_B9_L_18.PCIE_PIPETX0DATA0 always +PCIE_BOT.PCIE_LOGIC_OUTS_B9_L_19.PCIE_CFGMSGRECEIVEDUNLOCK always +PCIE_BOT.PCIE_LOGIC_OUTS_B9_R_0.PCIE_MIMTXWDATA37 always +PCIE_BOT.PCIE_LOGIC_OUTS_B9_R_1.PCIE_PIPETX7DATA8 always +PCIE_BOT.PCIE_LOGIC_OUTS_B9_R_3.PCIE_PIPETX7DATA0 always +PCIE_BOT.PCIE_LOGIC_OUTS_B9_R_4.PCIE_MIMTXWDATA57 always +PCIE_BOT.PCIE_LOGIC_OUTS_B9_R_5.PCIE_PIPETX5DATA8 always +PCIE_BOT.PCIE_LOGIC_OUTS_B9_R_6.PCIE_DBGVECB16 always +PCIE_BOT.PCIE_LOGIC_OUTS_B9_R_7.PCIE_PIPETX5DATA0 always +PCIE_BOT.PCIE_LOGIC_OUTS_B9_R_8.PCIE_TL2ERRHDR16 always +PCIE_BOT.PCIE_LOGIC_OUTS_B9_R_9.PCIE_TL2ERRHDR11 always +PCIE_BOT.PCIE_LOGIC_OUTS_B9_R_10.PCIE_TL2ERRHDR9 always +PCIE_BOT.PCIE_LOGIC_OUTS_B9_R_11.PCIE_PIPETXRESET always +PCIE_BOT.PCIE_LOGIC_OUTS_B9_R_12.PCIE_PIPETX6DATA8 always +PCIE_BOT.PCIE_LOGIC_OUTS_B9_R_13.PCIE_TRNRD122 always +PCIE_BOT.PCIE_LOGIC_OUTS_B9_R_14.PCIE_PIPETX6DATA0 always +PCIE_BOT.PCIE_LOGIC_OUTS_B9_R_15.PCIE_MIMRXWDATA37 always +PCIE_BOT.PCIE_LOGIC_OUTS_B9_R_16.PCIE_PIPETX4DATA8 always +PCIE_BOT.PCIE_LOGIC_OUTS_B9_R_17.PCIE_TRNRD108 always +PCIE_BOT.PCIE_LOGIC_OUTS_B9_R_18.PCIE_PIPETX4DATA0 always +PCIE_BOT.PCIE_LOGIC_OUTS_B9_R_19.PCIE_MIMRXRADDR6 always +PCIE_BOT.PCIE_LOGIC_OUTS_B10_L_0.PCIE_PLLTSSMSTATE3 always +PCIE_BOT.PCIE_LOGIC_OUTS_B10_L_1.PCIE_TL2ERRHDR20 always +PCIE_BOT.PCIE_LOGIC_OUTS_B10_L_2.PCIE_PLINITIALLINKWIDTH2 always +PCIE_BOT.PCIE_LOGIC_OUTS_B10_L_3.PCIE_TRNFCNPD0 always +PCIE_BOT.PCIE_LOGIC_OUTS_B10_L_4.PCIE_TRNFCNPD3 always +PCIE_BOT.PCIE_LOGIC_OUTS_B10_L_5.PCIE_TL2ERRHDR34 always +PCIE_BOT.PCIE_LOGIC_OUTS_B10_L_6.PCIE_TRNRD6 always +PCIE_BOT.PCIE_LOGIC_OUTS_B10_L_7.PCIE_TRNFCCPLH4 always +PCIE_BOT.PCIE_LOGIC_OUTS_B10_L_8.PCIE_TL2ERRHDR45 always +PCIE_BOT.PCIE_LOGIC_OUTS_B10_L_9.PCIE_TL2ERRHDR49 always +PCIE_BOT.PCIE_LOGIC_OUTS_B10_L_10.PCIE_TL2ERRHDR53 always +PCIE_BOT.PCIE_LOGIC_OUTS_B10_L_11.PCIE_TRNFCCPLD11 always +PCIE_BOT.PCIE_LOGIC_OUTS_B10_L_12.PCIE_TL2ERRHDR60 always +PCIE_BOT.PCIE_LOGIC_OUTS_B10_L_13.PCIE_TRNRD34 always +PCIE_BOT.PCIE_LOGIC_OUTS_B10_L_14.PCIE_TRNRDLLPDATA11 always +PCIE_BOT.PCIE_LOGIC_OUTS_B10_L_15.PCIE_TRNRDLLPDATA14 always +PCIE_BOT.PCIE_LOGIC_OUTS_B10_L_16.PCIE_CFGMSGRECEIVEDASSERTINTA always +PCIE_BOT.PCIE_LOGIC_OUTS_B10_L_17.PCIE_TRNRD50 always +PCIE_BOT.PCIE_LOGIC_OUTS_B10_L_18.PCIE_TRNRDLLPDATA27 always +PCIE_BOT.PCIE_LOGIC_OUTS_B10_L_19.PCIE_CFGMSGRECEIVEDPMASNAK always +PCIE_BOT.PCIE_LOGIC_OUTS_B10_R_0.PCIE_MIMTXWDATA56 always +PCIE_BOT.PCIE_LOGIC_OUTS_B10_R_1.PCIE_MIMTXWADDR12 always +PCIE_BOT.PCIE_LOGIC_OUTS_B10_R_2.PCIE_MIMTXRADDR3 always +PCIE_BOT.PCIE_LOGIC_OUTS_B10_R_3.PCIE_MIMTXWDATA63 always +PCIE_BOT.PCIE_LOGIC_OUTS_B10_R_4.PCIE_MIMTXWADDR4 always +PCIE_BOT.PCIE_LOGIC_OUTS_B10_R_5.PCIE_MIMTXWDATA65 always +PCIE_BOT.PCIE_LOGIC_OUTS_B10_R_6.PCIE_MIMTXWDATA12 always +PCIE_BOT.PCIE_LOGIC_OUTS_B10_R_7.PCIE_DBGVECB12 always +PCIE_BOT.PCIE_LOGIC_OUTS_B10_R_8.PCIE_MIMTXWDATA25 always +PCIE_BOT.PCIE_LOGIC_OUTS_B10_R_9.PCIE_TL2ERRHDR12 always +PCIE_BOT.PCIE_LOGIC_OUTS_B10_R_10.PCIE_LNKCLKEN always +PCIE_BOT.PCIE_LOGIC_OUTS_B10_R_11.PCIE_TL2ERRHDR3 always +PCIE_BOT.PCIE_LOGIC_OUTS_B10_R_12.PCIE_CFGMGMTDO7 always +PCIE_BOT.PCIE_LOGIC_OUTS_B10_R_13.PCIE_TRNRD123 always +PCIE_BOT.PCIE_LOGIC_OUTS_B10_R_14.PCIE_PL2RECEIVERERR always +PCIE_BOT.PCIE_LOGIC_OUTS_B10_R_15.PCIE_DBGVECA34 always +PCIE_BOT.PCIE_LOGIC_OUTS_B10_R_16.PCIE_MIMRXWDATA64 always +PCIE_BOT.PCIE_LOGIC_OUTS_B10_R_17.PCIE_TRNRD109 always +PCIE_BOT.PCIE_LOGIC_OUTS_B10_R_18.PCIE_MIMRXWDATA63 always +PCIE_BOT.PCIE_LOGIC_OUTS_B10_R_19.PCIE_MIMRXWDATA65 always +PCIE_BOT.PCIE_LOGIC_OUTS_B11_L_0.PCIE_PLLTSSMSTATE4 always +PCIE_BOT.PCIE_LOGIC_OUTS_B11_L_1.PCIE_PIPETX3DATA10 always +PCIE_BOT.PCIE_LOGIC_OUTS_B11_L_2.PCIE_TRNFCNPH1 always +PCIE_BOT.PCIE_LOGIC_OUTS_B11_L_3.PCIE_PIPETX3DATA2 always +PCIE_BOT.PCIE_LOGIC_OUTS_B11_L_4.PCIE_TRNFCNPD4 always +PCIE_BOT.PCIE_LOGIC_OUTS_B11_L_5.PCIE_PIPETX1DATA10 always +PCIE_BOT.PCIE_LOGIC_OUTS_B11_L_6.PCIE_TRNFCNPD9 always +PCIE_BOT.PCIE_LOGIC_OUTS_B11_L_7.PCIE_PIPETX1DATA2 always +PCIE_BOT.PCIE_LOGIC_OUTS_B11_L_8.PCIE_TL2ERRHDR46 always +PCIE_BOT.PCIE_LOGIC_OUTS_B11_L_9.PCIE_TL2ERRHDR50 always +PCIE_BOT.PCIE_LOGIC_OUTS_B11_L_10.PCIE_TL2ERRHDR54 always +PCIE_BOT.PCIE_LOGIC_OUTS_B11_L_11.PCIE_TRNTDLLPDSTRDY always +PCIE_BOT.PCIE_LOGIC_OUTS_B11_L_12.PCIE_PIPETX2DATA10 always +PCIE_BOT.PCIE_LOGIC_OUTS_B11_L_13.PCIE_TRNRDLLPDATA4 always +PCIE_BOT.PCIE_LOGIC_OUTS_B11_L_14.PCIE_PIPETX2DATA2 always +PCIE_BOT.PCIE_LOGIC_OUTS_B11_L_15.PCIE_TRNRDLLPDATA15 always +PCIE_BOT.PCIE_LOGIC_OUTS_B11_L_16.PCIE_PIPETX0DATA10 always +PCIE_BOT.PCIE_LOGIC_OUTS_B11_L_17.PCIE_TRNRDLLPDATA20 always +PCIE_BOT.PCIE_LOGIC_OUTS_B11_L_18.PCIE_PIPETX0DATA2 always +PCIE_BOT.PCIE_LOGIC_OUTS_B11_L_19.PCIE_CFGPCIELINKSTATE0 always +PCIE_BOT.PCIE_LOGIC_OUTS_B11_R_0.PCIE_MIMTXWDATA36 always +PCIE_BOT.PCIE_LOGIC_OUTS_B11_R_1.PCIE_PIPETX7DATA10 always +PCIE_BOT.PCIE_LOGIC_OUTS_B11_R_2.PCIE_MIMTXWADDR6 always +PCIE_BOT.PCIE_LOGIC_OUTS_B11_R_3.PCIE_PIPETX7DATA2 always +PCIE_BOT.PCIE_LOGIC_OUTS_B11_R_4.PCIE_MIMTXWDATA59 always +PCIE_BOT.PCIE_LOGIC_OUTS_B11_R_5.PCIE_PIPETX5DATA10 always +PCIE_BOT.PCIE_LOGIC_OUTS_B11_R_6.PCIE_MIMTXRADDR1 always +PCIE_BOT.PCIE_LOGIC_OUTS_B11_R_7.PCIE_PIPETX5DATA2 always +PCIE_BOT.PCIE_LOGIC_OUTS_B11_R_8.PCIE_TL2ERRHDR17 always +PCIE_BOT.PCIE_LOGIC_OUTS_B11_R_9.PCIE_TL2ERRHDR13 always +PCIE_BOT.PCIE_LOGIC_OUTS_B11_R_10.PCIE_CFGMGMTDO0 always +PCIE_BOT.PCIE_LOGIC_OUTS_B11_R_11.PCIE_TL2ERRHDR4 always +PCIE_BOT.PCIE_LOGIC_OUTS_B11_R_12.PCIE_PIPETX6DATA10 always +PCIE_BOT.PCIE_LOGIC_OUTS_B11_R_13.PCIE_LL2RECEIVERERR always +PCIE_BOT.PCIE_LOGIC_OUTS_B11_R_14.PCIE_PIPETX6DATA2 always +PCIE_BOT.PCIE_LOGIC_OUTS_B11_R_15.PCIE_DBGVECA35 always +PCIE_BOT.PCIE_LOGIC_OUTS_B11_R_16.PCIE_PIPETX4DATA10 always +PCIE_BOT.PCIE_LOGIC_OUTS_B11_R_17.PCIE_MIMRXWDATA53 always +PCIE_BOT.PCIE_LOGIC_OUTS_B11_R_18.PCIE_PIPETX4DATA2 always +PCIE_BOT.PCIE_LOGIC_OUTS_B11_R_19.PCIE_MIMRXWADDR7 always +PCIE_BOT.PCIE_LOGIC_OUTS_B12_L_0.PCIE_PLLTSSMSTATE5 always +PCIE_BOT.PCIE_LOGIC_OUTS_B12_L_1.PCIE_TL2ERRHDR21 always +PCIE_BOT.PCIE_LOGIC_OUTS_B12_L_2.PCIE_TRNFCNPH2 always +PCIE_BOT.PCIE_LOGIC_OUTS_B12_L_3.PCIE_TL2ERRHDR25 always +PCIE_BOT.PCIE_LOGIC_OUTS_B12_L_4.PCIE_TL2ERRHDR29 always +PCIE_BOT.PCIE_LOGIC_OUTS_B12_L_5.PCIE_TL2ERRHDR35 always +PCIE_BOT.PCIE_LOGIC_OUTS_B12_L_6.PCIE_TRNFCNPD10 always +PCIE_BOT.PCIE_LOGIC_OUTS_B12_L_7.PCIE_TL2ERRHDR39 always +PCIE_BOT.PCIE_LOGIC_OUTS_B12_L_8.PCIE_CFGINTERRUPTDO1 always +PCIE_BOT.PCIE_LOGIC_OUTS_B12_L_9.PCIE_CFGINTERRUPTDO5 always +PCIE_BOT.PCIE_LOGIC_OUTS_B12_L_10.PCIE_CFGMSGDATA0 always +PCIE_BOT.PCIE_LOGIC_OUTS_B12_L_11.PCIE_TL2ERRHDR55 always +PCIE_BOT.PCIE_LOGIC_OUTS_B12_L_12.PCIE_TL2ERRHDR61 always +PCIE_BOT.PCIE_LOGIC_OUTS_B12_L_13.PCIE_TRNRDLLPDATA5 always +PCIE_BOT.PCIE_LOGIC_OUTS_B12_L_14.PCIE_CFGMSGDATA10 always +PCIE_BOT.PCIE_LOGIC_OUTS_B12_L_15.PCIE_CFGMSGDATA14 always +PCIE_BOT.PCIE_LOGIC_OUTS_B12_L_16.PCIE_CFGMSGRECEIVEDDEASSERTINTA always +PCIE_BOT.PCIE_LOGIC_OUTS_B12_L_17.PCIE_TRNRDLLPDATA21 always +PCIE_BOT.PCIE_LOGIC_OUTS_B12_L_18.PCIE_CFGMSGRECEIVEDDEASSERTINTD always +PCIE_BOT.PCIE_LOGIC_OUTS_B12_L_19.PCIE_CFGLINKSTATUSDLLACTIVE always +PCIE_BOT.PCIE_LOGIC_OUTS_B12_R_0.PCIE_MIMTXWDATA52 always +PCIE_BOT.PCIE_LOGIC_OUTS_B12_R_1.PCIE_MIMTXWDATA60 always +PCIE_BOT.PCIE_LOGIC_OUTS_B12_R_2.PCIE_DBGVECB30 always +PCIE_BOT.PCIE_LOGIC_OUTS_B12_R_3.PCIE_MIMTXWADDR8 always +PCIE_BOT.PCIE_LOGIC_OUTS_B12_R_4.PCIE_DBGVECB24 always +PCIE_BOT.PCIE_LOGIC_OUTS_B12_R_5.PCIE_MIMTXWDATA2 always +PCIE_BOT.PCIE_LOGIC_OUTS_B12_R_6.PCIE_MIMTXWEN always +PCIE_BOT.PCIE_LOGIC_OUTS_B12_R_7.PCIE_MIMTXWADDR2 always +PCIE_BOT.PCIE_LOGIC_OUTS_B12_R_8.PCIE_USERRSTN always +PCIE_BOT.PCIE_LOGIC_OUTS_B12_R_9.PCIE_RECEIVEDFUNCLVLRSTN always +PCIE_BOT.PCIE_LOGIC_OUTS_B12_R_10.PCIE_CFGMGMTDO1 always +PCIE_BOT.PCIE_LOGIC_OUTS_B12_R_11.PCIE_TL2ERRHDR5 always +PCIE_BOT.PCIE_LOGIC_OUTS_B12_R_12.PCIE_CFGMGMTDO8 always +PCIE_BOT.PCIE_LOGIC_OUTS_B12_R_13.PCIE_LL2PROTOCOLERR always +PCIE_BOT.PCIE_LOGIC_OUTS_B12_R_14.PCIE_CFGMGMTDO12 always +PCIE_BOT.PCIE_LOGIC_OUTS_B12_R_15.PCIE_MIMRXWDATA38 always +PCIE_BOT.PCIE_LOGIC_OUTS_B12_R_16.PCIE_MIMRXWADDR10 always +PCIE_BOT.PCIE_LOGIC_OUTS_B12_R_17.PCIE_LL2SUSPENDOK always +PCIE_BOT.PCIE_LOGIC_OUTS_B12_R_18.PCIE_MIMRXWDATA55 always +PCIE_BOT.PCIE_LOGIC_OUTS_B12_R_19.PCIE_MIMRXWDATA61 always +PCIE_BOT.PCIE_LOGIC_OUTS_B13_L_0.PCIE_PLLANEREVERSALMODE0 always +PCIE_BOT.PCIE_LOGIC_OUTS_B13_L_1.PCIE_PIPETX3DATA9 always +PCIE_BOT.PCIE_LOGIC_OUTS_B13_L_2.PCIE_TRNFCNPH3 always +PCIE_BOT.PCIE_LOGIC_OUTS_B13_L_3.PCIE_PIPETX3DATA1 always +PCIE_BOT.PCIE_LOGIC_OUTS_B13_L_4.PCIE_TL2ERRHDR30 always +PCIE_BOT.PCIE_LOGIC_OUTS_B13_L_5.PCIE_PIPETX1DATA9 always +PCIE_BOT.PCIE_LOGIC_OUTS_B13_L_6.PCIE_TRNFCNPD11 always +PCIE_BOT.PCIE_LOGIC_OUTS_B13_L_7.PCIE_PIPETX1DATA1 always +PCIE_BOT.PCIE_LOGIC_OUTS_B13_L_8.PCIE_CFGINTERRUPTDO2 always +PCIE_BOT.PCIE_LOGIC_OUTS_B13_L_9.PCIE_CFGINTERRUPTDO6 always +PCIE_BOT.PCIE_LOGIC_OUTS_B13_L_10.PCIE_CFGMSGDATA1 always +PCIE_BOT.PCIE_LOGIC_OUTS_B13_L_11.PCIE_TL2ERRHDR56 always +PCIE_BOT.PCIE_LOGIC_OUTS_B13_L_12.PCIE_PIPETX2DATA9 always +PCIE_BOT.PCIE_LOGIC_OUTS_B13_L_13.PCIE_TRNRDLLPDATA6 always +PCIE_BOT.PCIE_LOGIC_OUTS_B13_L_14.PCIE_PIPETX2DATA1 always +PCIE_BOT.PCIE_LOGIC_OUTS_B13_L_15.PCIE_CFGMSGDATA15 always +PCIE_BOT.PCIE_LOGIC_OUTS_B13_L_16.PCIE_PIPETX0DATA9 always +PCIE_BOT.PCIE_LOGIC_OUTS_B13_L_17.PCIE_TRNRDLLPDATA22 always +PCIE_BOT.PCIE_LOGIC_OUTS_B13_L_18.PCIE_PIPETX0DATA1 always +PCIE_BOT.PCIE_LOGIC_OUTS_B13_L_19.PCIE_CFGLINKSTATUSBANDWIDTHSTATUS always +PCIE_BOT.PCIE_LOGIC_OUTS_B13_R_0.PCIE_MIMTXWDATA54 always +PCIE_BOT.PCIE_LOGIC_OUTS_B13_R_1.PCIE_PIPETX7DATA9 always +PCIE_BOT.PCIE_LOGIC_OUTS_B13_R_2.PCIE_DBGVECB31 always +PCIE_BOT.PCIE_LOGIC_OUTS_B13_R_3.PCIE_PIPETX7DATA1 always +PCIE_BOT.PCIE_LOGIC_OUTS_B13_R_4.PCIE_MIMTXWDATA49 always +PCIE_BOT.PCIE_LOGIC_OUTS_B13_R_5.PCIE_PIPETX5DATA9 always +PCIE_BOT.PCIE_LOGIC_OUTS_B13_R_6.PCIE_DBGVECB17 always +PCIE_BOT.PCIE_LOGIC_OUTS_B13_R_7.PCIE_PIPETX5DATA1 always +PCIE_BOT.PCIE_LOGIC_OUTS_B13_R_8.PCIE_PLRECEIVEDHOTRST always +PCIE_BOT.PCIE_LOGIC_OUTS_B13_R_9.PCIE_MIMTXWDATA27 always +PCIE_BOT.PCIE_LOGIC_OUTS_B13_R_10.PCIE_CFGMGMTDO2 always +PCIE_BOT.PCIE_LOGIC_OUTS_B13_R_11.PCIE_CFGMGMTDO3 always +PCIE_BOT.PCIE_LOGIC_OUTS_B13_R_12.PCIE_PIPETX6DATA9 always +PCIE_BOT.PCIE_LOGIC_OUTS_B13_R_13.PCIE_LL2BADTLPERR always +PCIE_BOT.PCIE_LOGIC_OUTS_B13_R_14.PCIE_PIPETX6DATA1 always +PCIE_BOT.PCIE_LOGIC_OUTS_B13_R_15.PCIE_MIMRXWDATA40 always +PCIE_BOT.PCIE_LOGIC_OUTS_B13_R_16.PCIE_PIPETX4DATA9 always +PCIE_BOT.PCIE_LOGIC_OUTS_B13_R_17.PCIE_LL2TXIDLE always +PCIE_BOT.PCIE_LOGIC_OUTS_B13_R_18.PCIE_PIPETX4DATA1 always +PCIE_BOT.PCIE_LOGIC_OUTS_B13_R_19.PCIE_PL2RXPMSTATE0 always +PCIE_BOT.PCIE_LOGIC_OUTS_B14_L_0.PCIE_PLLANEREVERSALMODE1 always +PCIE_BOT.PCIE_LOGIC_OUTS_B14_L_1.PCIE_TL2ERRHDR22 always +PCIE_BOT.PCIE_LOGIC_OUTS_B14_L_2.PCIE_TRNFCNPH4 always +PCIE_BOT.PCIE_LOGIC_OUTS_B14_L_3.PCIE_TL2ERRHDR26 always +PCIE_BOT.PCIE_LOGIC_OUTS_B14_L_4.PCIE_TL2ERRHDR31 always +PCIE_BOT.PCIE_LOGIC_OUTS_B14_L_5.PCIE_TL2ERRHDR36 always +PCIE_BOT.PCIE_LOGIC_OUTS_B14_L_6.PCIE_TRNFCCPLH0 always +PCIE_BOT.PCIE_LOGIC_OUTS_B14_L_7.PCIE_TL2ERRHDR40 always +PCIE_BOT.PCIE_LOGIC_OUTS_B14_L_8.PCIE_CFGINTERRUPTDO3 always +PCIE_BOT.PCIE_LOGIC_OUTS_B14_L_9.PCIE_CFGINTERRUPTDO7 always +PCIE_BOT.PCIE_LOGIC_OUTS_B14_L_10.PCIE_CFGMSGDATA2 always +PCIE_BOT.PCIE_LOGIC_OUTS_B14_L_11.PCIE_TL2ERRHDR57 always +PCIE_BOT.PCIE_LOGIC_OUTS_B14_L_12.PCIE_TL2ERRHDR62 always +PCIE_BOT.PCIE_LOGIC_OUTS_B14_L_13.PCIE_TRNRDLLPDATA7 always +PCIE_BOT.PCIE_LOGIC_OUTS_B14_L_14.PCIE_CFGMSGDATA11 always +PCIE_BOT.PCIE_LOGIC_OUTS_B14_L_15.PCIE_CFGMSGRECEIVEDERRCOR always +PCIE_BOT.PCIE_LOGIC_OUTS_B14_L_16.PCIE_CFGMSGRECEIVEDASSERTINTB always +PCIE_BOT.PCIE_LOGIC_OUTS_B14_L_17.PCIE_TRNRDLLPDATA23 always +PCIE_BOT.PCIE_LOGIC_OUTS_B14_L_18.PCIE_CFGMSGRECEIVEDPMPME always +PCIE_BOT.PCIE_LOGIC_OUTS_B14_L_19.PCIE_CFGLINKSTATUSAUTOBANDWIDTHSTATUS always +PCIE_BOT.PCIE_LOGIC_OUTS_B14_R_0.PCIE_MIMTXWDATA42 always +PCIE_BOT.PCIE_LOGIC_OUTS_B14_R_1.PCIE_MIMTXWDATA48 always +PCIE_BOT.PCIE_LOGIC_OUTS_B14_R_2.PCIE_MIMTXWDATA67 always +PCIE_BOT.PCIE_LOGIC_OUTS_B14_R_3.PCIE_MIMTXWADDR5 always +PCIE_BOT.PCIE_LOGIC_OUTS_B14_R_4.PCIE_MIMTXRADDR4 always +PCIE_BOT.PCIE_LOGIC_OUTS_B14_R_5.PCIE_MIMTXWDATA51 always +PCIE_BOT.PCIE_LOGIC_OUTS_B14_R_7.PCIE_DBGVECB13 always +PCIE_BOT.PCIE_LOGIC_OUTS_B14_R_8.PCIE_DBGVECA62 always +PCIE_BOT.PCIE_LOGIC_OUTS_B14_R_9.PCIE_DBGVECA58 always +PCIE_BOT.PCIE_LOGIC_OUTS_B14_R_10.PCIE_CFGERRCPLRDYN always +PCIE_BOT.PCIE_LOGIC_OUTS_B14_R_11.PCIE_CFGMGMTDO4 always +PCIE_BOT.PCIE_LOGIC_OUTS_B14_R_12.PCIE_CFGMGMTDO9 always +PCIE_BOT.PCIE_LOGIC_OUTS_B14_R_13.PCIE_LL2BADDLLPERR always +PCIE_BOT.PCIE_LOGIC_OUTS_B14_R_14.PCIE_CFGMGMTDO13 always +PCIE_BOT.PCIE_LOGIC_OUTS_B14_R_15.PCIE_MIMRXWDATA42 always +PCIE_BOT.PCIE_LOGIC_OUTS_B14_R_16.PCIE_MIMRXWADDR11 always +PCIE_BOT.PCIE_LOGIC_OUTS_B14_R_17.PCIE_MIMRXWDATA67 always +PCIE_BOT.PCIE_LOGIC_OUTS_B14_R_18.PCIE_MIMRXWDATA59 always +PCIE_BOT.PCIE_LOGIC_OUTS_B14_R_19.PCIE_MIMRXWADDR0 always +PCIE_BOT.PCIE_LOGIC_OUTS_B15_L_0.PCIE_PLPHYLNKUPN always +PCIE_BOT.PCIE_LOGIC_OUTS_B15_L_1.PCIE_PIPETX3DATA11 always +PCIE_BOT.PCIE_LOGIC_OUTS_B15_L_2.PCIE_TL2ERRHDR23 always +PCIE_BOT.PCIE_LOGIC_OUTS_B15_L_3.PCIE_PIPETX3DATA3 always +PCIE_BOT.PCIE_LOGIC_OUTS_B15_L_4.PCIE_TL2ERRHDR32 always +PCIE_BOT.PCIE_LOGIC_OUTS_B15_L_5.PCIE_PIPETX1DATA11 always +PCIE_BOT.PCIE_LOGIC_OUTS_B15_L_6.PCIE_TL2ERRHDR37 always +PCIE_BOT.PCIE_LOGIC_OUTS_B15_L_7.PCIE_PIPETX1DATA3 always +PCIE_BOT.PCIE_LOGIC_OUTS_B15_L_8.PCIE_CFGINTERRUPTDO4 always +PCIE_BOT.PCIE_LOGIC_OUTS_B15_L_9.PCIE_CFGMSGRECEIVED always +PCIE_BOT.PCIE_LOGIC_OUTS_B15_L_10.PCIE_CFGMSGDATA3 always +PCIE_BOT.PCIE_LOGIC_OUTS_B15_L_11.PCIE_TL2ERRHDR58 always +PCIE_BOT.PCIE_LOGIC_OUTS_B15_L_12.PCIE_PIPETX2DATA11 always +PCIE_BOT.PCIE_LOGIC_OUTS_B15_L_13.PCIE_TL2ERRHDR63 always +PCIE_BOT.PCIE_LOGIC_OUTS_B15_L_14.PCIE_PIPETX2DATA3 always +PCIE_BOT.PCIE_LOGIC_OUTS_B15_L_15.PCIE_CFGMSGRECEIVEDERRNONFATAL always +PCIE_BOT.PCIE_LOGIC_OUTS_B15_L_16.PCIE_PIPETX0DATA11 always +PCIE_BOT.PCIE_LOGIC_OUTS_B15_L_17.PCIE_CFGMSGRECEIVEDDEASSERTINTB always +PCIE_BOT.PCIE_LOGIC_OUTS_B15_L_18.PCIE_PIPETX0DATA3 always +PCIE_BOT.PCIE_LOGIC_OUTS_B15_L_19.PCIE_CFGLINKCONTROLASPMCONTROL0 always +PCIE_BOT.PCIE_LOGIC_OUTS_B15_R_1.PCIE_PIPETX7DATA11 always +PCIE_BOT.PCIE_LOGIC_OUTS_B15_R_2.PCIE_DBGVECB32 always +PCIE_BOT.PCIE_LOGIC_OUTS_B15_R_3.PCIE_PIPETX7DATA3 always +PCIE_BOT.PCIE_LOGIC_OUTS_B15_R_4.PCIE_MIMTXWADDR7 always +PCIE_BOT.PCIE_LOGIC_OUTS_B15_R_5.PCIE_PIPETX5DATA11 always +PCIE_BOT.PCIE_LOGIC_OUTS_B15_R_6.PCIE_MIMTXWDATA34 always +PCIE_BOT.PCIE_LOGIC_OUTS_B15_R_7.PCIE_PIPETX5DATA3 always +PCIE_BOT.PCIE_LOGIC_OUTS_B15_R_8.PCIE_DBGVECA63 always +PCIE_BOT.PCIE_LOGIC_OUTS_B15_R_9.PCIE_PIPETXRCVRDET always +PCIE_BOT.PCIE_LOGIC_OUTS_B15_R_10.PCIE_CFGINTERRUPTRDYN always +PCIE_BOT.PCIE_LOGIC_OUTS_B15_R_11.PCIE_CFGMGMTDO5 always +PCIE_BOT.PCIE_LOGIC_OUTS_B15_R_12.PCIE_PIPETX6DATA11 always +PCIE_BOT.PCIE_LOGIC_OUTS_B15_R_13.PCIE_CFGMGMTDO10 always +PCIE_BOT.PCIE_LOGIC_OUTS_B15_R_14.PCIE_PIPETX6DATA3 always +PCIE_BOT.PCIE_LOGIC_OUTS_B15_R_15.PCIE_MIMRXWDATA58 always +PCIE_BOT.PCIE_LOGIC_OUTS_B15_R_16.PCIE_PIPETX4DATA11 always +PCIE_BOT.PCIE_LOGIC_OUTS_B15_R_17.PCIE_LL2LINKSTATUS0 always +PCIE_BOT.PCIE_LOGIC_OUTS_B15_R_18.PCIE_PIPETX4DATA3 always +PCIE_BOT.PCIE_LOGIC_OUTS_B15_R_19.PCIE_MIMRXRADDR7 always +PCIE_BOT.PCIE_LOGIC_OUTS_B16_L_0.PCIE_PIPETX3CHARISK1 always +PCIE_BOT.PCIE_LOGIC_OUTS_B16_L_1.PCIE_CFGINTERRUPTMMENABLE2 always +PCIE_BOT.PCIE_LOGIC_OUTS_B16_L_2.PCIE_PIPETX3CHARISK0 always +PCIE_BOT.PCIE_LOGIC_OUTS_B16_L_3.PCIE_TL2ERRHDR27 always +PCIE_BOT.PCIE_LOGIC_OUTS_B16_L_4.PCIE_PIPETX1CHARISK1 always +PCIE_BOT.PCIE_LOGIC_OUTS_B16_L_5.PCIE_CFGINTERRUPTMSIXFM always +PCIE_BOT.PCIE_LOGIC_OUTS_B16_L_6.PCIE_PIPETX1CHARISK0 always +PCIE_BOT.PCIE_LOGIC_OUTS_B16_L_7.PCIE_TL2ERRHDR41 always +PCIE_BOT.PCIE_LOGIC_OUTS_B16_L_8.PCIE_CFGCOMMANDSERREN always +PCIE_BOT.PCIE_LOGIC_OUTS_B16_L_9.PCIE_CFGDEVSTATUSCORRERRDETECTED always +PCIE_BOT.PCIE_LOGIC_OUTS_B16_L_10.PCIE_CFGDEVSTATUSFATALERRDETECTED always +PCIE_BOT.PCIE_LOGIC_OUTS_B16_L_11.PCIE_PIPETX2CHARISK1 always +PCIE_BOT.PCIE_LOGIC_OUTS_B16_L_12.PCIE_CFGMSGDATA6 always +PCIE_BOT.PCIE_LOGIC_OUTS_B16_L_13.PCIE_PIPETX2CHARISK0 always +PCIE_BOT.PCIE_LOGIC_OUTS_B16_L_14.PCIE_CFGMSGDATA12 always +PCIE_BOT.PCIE_LOGIC_OUTS_B16_L_15.PCIE_PIPETX0CHARISK1 always +PCIE_BOT.PCIE_LOGIC_OUTS_B16_L_16.PCIE_CFGDEVCONTROLMAXREADREQ0 always +PCIE_BOT.PCIE_LOGIC_OUTS_B16_L_17.PCIE_PIPETX0CHARISK0 always +PCIE_BOT.PCIE_LOGIC_OUTS_B16_L_18.PCIE_CFGMSGRECEIVEDPMETOACK always +PCIE_BOT.PCIE_LOGIC_OUTS_B16_L_19.PCIE_CFGROOTCONTROLPMEINTEN always +PCIE_BOT.PCIE_LOGIC_OUTS_B16_R_0.PCIE_PIPETX7CHARISK1 always +PCIE_BOT.PCIE_LOGIC_OUTS_B16_R_1.PCIE_MIMTXWDATA64 always +PCIE_BOT.PCIE_LOGIC_OUTS_B16_R_2.PCIE_PIPETX7CHARISK0 always +PCIE_BOT.PCIE_LOGIC_OUTS_B16_R_3.PCIE_DBGVECB28 always +PCIE_BOT.PCIE_LOGIC_OUTS_B16_R_4.PCIE_PIPETX5CHARISK1 always +PCIE_BOT.PCIE_LOGIC_OUTS_B16_R_5.PCIE_DBGVECB20 always +PCIE_BOT.PCIE_LOGIC_OUTS_B16_R_6.PCIE_PIPETX5CHARISK0 always +PCIE_BOT.PCIE_LOGIC_OUTS_B16_R_7.PCIE_MIMTXWDATA28 always +PCIE_BOT.PCIE_LOGIC_OUTS_B16_R_8.PCIE_DBGVECB0 always +PCIE_BOT.PCIE_LOGIC_OUTS_B16_R_9.PCIE_MIMTXWDATA15 always +PCIE_BOT.PCIE_LOGIC_OUTS_B16_R_10.PCIE_CFGINTERRUPTMMENABLE0 always +PCIE_BOT.PCIE_LOGIC_OUTS_B16_R_11.PCIE_PIPETX6CHARISK1 always +PCIE_BOT.PCIE_LOGIC_OUTS_B16_R_12.PCIE_CFGMGMTRDWRDONEN always +PCIE_BOT.PCIE_LOGIC_OUTS_B16_R_13.PCIE_PIPETX6CHARISK0 always +PCIE_BOT.PCIE_LOGIC_OUTS_B16_R_14.PCIE_CFGMGMTDO14 always +PCIE_BOT.PCIE_LOGIC_OUTS_B16_R_15.PCIE_PIPETX4CHARISK1 always +PCIE_BOT.PCIE_LOGIC_OUTS_B16_R_16.PCIE_MIMRXWDATA48 always +PCIE_BOT.PCIE_LOGIC_OUTS_B16_R_17.PCIE_PIPETX4CHARISK0 always +PCIE_BOT.PCIE_LOGIC_OUTS_B16_R_18.PCIE_MIMRXRADDR3 always +PCIE_BOT.PCIE_LOGIC_OUTS_B16_R_19.PCIE_MIMRXWADDR4 always +PCIE_BOT.PCIE_LOGIC_OUTS_B17_L_0.PCIE_PLTXPMSTATE0 always +PCIE_BOT.PCIE_LOGIC_OUTS_B17_L_1.PCIE_CFGINTERRUPTMSIENABLE always +PCIE_BOT.PCIE_LOGIC_OUTS_B17_L_2.PCIE_TL2ERRHDR24 always +PCIE_BOT.PCIE_LOGIC_OUTS_B17_L_3.PCIE_TL2ERRHDR28 always +PCIE_BOT.PCIE_LOGIC_OUTS_B17_L_4.PCIE_CFGINTERRUPTMSIXENABLE always +PCIE_BOT.PCIE_LOGIC_OUTS_B17_L_5.PCIE_CFGINTERRUPTDO0 always +PCIE_BOT.PCIE_LOGIC_OUTS_B17_L_6.PCIE_TL2ERRHDR38 always +PCIE_BOT.PCIE_LOGIC_OUTS_B17_L_7.PCIE_TL2ERRHDR42 always +PCIE_BOT.PCIE_LOGIC_OUTS_B17_L_8.PCIE_CFGBRIDGESERREN always +PCIE_BOT.PCIE_LOGIC_OUTS_B17_L_9.PCIE_CFGDEVSTATUSNONFATALERRDETECTED always +PCIE_BOT.PCIE_LOGIC_OUTS_B17_L_10.PCIE_CFGDEVSTATUSURDETECTED always +PCIE_BOT.PCIE_LOGIC_OUTS_B17_L_11.PCIE_CFGMSGDATA4 always +PCIE_BOT.PCIE_LOGIC_OUTS_B17_L_12.PCIE_CFGMSGDATA7 always +PCIE_BOT.PCIE_LOGIC_OUTS_B17_L_13.PCIE_TL2ERRMALFORMED always +PCIE_BOT.PCIE_LOGIC_OUTS_B17_L_14.PCIE_CFGMSGDATA13 always +PCIE_BOT.PCIE_LOGIC_OUTS_B17_L_15.PCIE_CFGDEVCONTROLEXTTAGEN always +PCIE_BOT.PCIE_LOGIC_OUTS_B17_L_16.PCIE_CFGDEVCONTROLMAXREADREQ1 always +PCIE_BOT.PCIE_LOGIC_OUTS_B17_L_17.PCIE_CFGMSGRECEIVEDASSERTINTC always +PCIE_BOT.PCIE_LOGIC_OUTS_B17_L_18.PCIE_CFGMSGRECEIVEDPMETO always +PCIE_BOT.PCIE_LOGIC_OUTS_B17_L_19.PCIE_CFGAERECRCCHECKEN always +PCIE_BOT.PCIE_LOGIC_OUTS_B17_R_0.PCIE_MIMTXWDATA58 always +PCIE_BOT.PCIE_LOGIC_OUTS_B17_R_2.PCIE_MIMTXRADDR6 always +PCIE_BOT.PCIE_LOGIC_OUTS_B17_R_3.PCIE_MIMTXWDATA45 always +PCIE_BOT.PCIE_LOGIC_OUTS_B17_R_4.PCIE_MIMTXRADDR7 always +PCIE_BOT.PCIE_LOGIC_OUTS_B17_R_5.PCIE_MIMTXWDATA0 always +PCIE_BOT.PCIE_LOGIC_OUTS_B17_R_6.PCIE_MIMTXWDATA22 always +PCIE_BOT.PCIE_LOGIC_OUTS_B17_R_7.PCIE_DBGVECB14 always +PCIE_BOT.PCIE_LOGIC_OUTS_B17_R_8.PCIE_DBGVECB1 always +PCIE_BOT.PCIE_LOGIC_OUTS_B17_R_9.PCIE_MIMTXWDATA35 always +PCIE_BOT.PCIE_LOGIC_OUTS_B17_R_10.PCIE_CFGINTERRUPTMMENABLE1 always +PCIE_BOT.PCIE_LOGIC_OUTS_B17_R_11.PCIE_DBGVECA50 always +PCIE_BOT.PCIE_LOGIC_OUTS_B17_R_12.PCIE_CFGERRAERHEADERLOGSETN always +PCIE_BOT.PCIE_LOGIC_OUTS_B17_R_13.PCIE_CFGMGMTDO11 always +PCIE_BOT.PCIE_LOGIC_OUTS_B17_R_14.PCIE_CFGMGMTDO15 always +PCIE_BOT.PCIE_LOGIC_OUTS_B17_R_15.PCIE_MIMRXWDATA36 always +PCIE_BOT.PCIE_LOGIC_OUTS_B17_R_16.PCIE_MIMRXWDATA50 always +PCIE_BOT.PCIE_LOGIC_OUTS_B17_R_17.PCIE_MIMRXWADDR6 always +PCIE_BOT.PCIE_LOGIC_OUTS_B17_R_18.PCIE_MIMRXWDATA45 always +PCIE_BOT.PCIE_LOGIC_OUTS_B17_R_19.PCIE_MIMRXWADDR9 always +PCIE_BOT.PCIE_LOGIC_OUTS_B18_L_0.PCIE_PLTXPMSTATE1 always +PCIE_BOT.PCIE_LOGIC_OUTS_B18_L_1.PCIE_DBGVECB39 always +PCIE_BOT.PCIE_LOGIC_OUTS_B18_L_2.PCIE_DBGVECB43 always +PCIE_BOT.PCIE_LOGIC_OUTS_B18_L_3.PCIE_DBGVECB47 always +PCIE_BOT.PCIE_LOGIC_OUTS_B18_L_4.PCIE_DBGVECB51 always +PCIE_BOT.PCIE_LOGIC_OUTS_B18_L_5.PCIE_DBGVECB55 always +PCIE_BOT.PCIE_LOGIC_OUTS_B18_L_6.PCIE_DBGVECB59 always +PCIE_BOT.PCIE_LOGIC_OUTS_B18_L_7.PCIE_DBGVECB63 always +PCIE_BOT.PCIE_LOGIC_OUTS_B18_L_8.PCIE_DBGVECC3 always +PCIE_BOT.PCIE_LOGIC_OUTS_B18_L_9.PCIE_DBGVECC7 always +PCIE_BOT.PCIE_LOGIC_OUTS_B18_L_10.PCIE_DBGVECC11 always +PCIE_BOT.PCIE_LOGIC_OUTS_B18_L_11.PCIE_CFGMSGDATA5 always +PCIE_BOT.PCIE_LOGIC_OUTS_B18_L_12.PCIE_CFGMSGDATA8 always +PCIE_BOT.PCIE_LOGIC_OUTS_B18_L_13.PCIE_TL2ERRRXOVERFLOW always +PCIE_BOT.PCIE_LOGIC_OUTS_B18_L_14.PCIE_CFGDEVCONTROLENABLERO always +PCIE_BOT.PCIE_LOGIC_OUTS_B18_L_15.PCIE_CFGDEVCONTROLPHANTOMEN always +PCIE_BOT.PCIE_LOGIC_OUTS_B18_L_16.PCIE_CFGDEVCONTROLMAXREADREQ2 always +PCIE_BOT.PCIE_LOGIC_OUTS_B18_L_17.PCIE_CFGMSGRECEIVEDDEASSERTINTC always +PCIE_BOT.PCIE_LOGIC_OUTS_B18_L_18.PCIE_CFGLINKSTATUSNEGOTIATEDWIDTH1 always +PCIE_BOT.PCIE_LOGIC_OUTS_B18_L_19.PCIE_CFGAERECRCGENEN always +PCIE_BOT.PCIE_LOGIC_OUTS_B18_R_0.PCIE_MIMTXWDATA38 always +PCIE_BOT.PCIE_LOGIC_OUTS_B18_R_2.PCIE_MIMTXWDATA66 always +PCIE_BOT.PCIE_LOGIC_OUTS_B18_R_3.PCIE_MIMTXWDATA41 always +PCIE_BOT.PCIE_LOGIC_OUTS_B18_R_4.PCIE_MIMTXWDATA47 always +PCIE_BOT.PCIE_LOGIC_OUTS_B18_R_5.PCIE_DBGVECB21 always +PCIE_BOT.PCIE_LOGIC_OUTS_B18_R_6.PCIE_MIMTXWDATA24 always +PCIE_BOT.PCIE_LOGIC_OUTS_B18_R_7.PCIE_DBGVECB15 always +PCIE_BOT.PCIE_LOGIC_OUTS_B18_R_8.PCIE_DBGVECB11 always +PCIE_BOT.PCIE_LOGIC_OUTS_B18_R_9.PCIE_MIMTXWDATA11 always +PCIE_BOT.PCIE_LOGIC_OUTS_B18_R_10.PCIE_DBGVECA54 always +PCIE_BOT.PCIE_LOGIC_OUTS_B18_R_11.PCIE_DBGVECA51 always +PCIE_BOT.PCIE_LOGIC_OUTS_B18_R_12.PCIE_DBGVECA46 always +PCIE_BOT.PCIE_LOGIC_OUTS_B18_R_13.PCIE_DBGVECA42 always +PCIE_BOT.PCIE_LOGIC_OUTS_B18_R_14.PCIE_CFGMGMTDO31 always +PCIE_BOT.PCIE_LOGIC_OUTS_B18_R_15.PCIE_MIMRXWDATA52 always +PCIE_BOT.PCIE_LOGIC_OUTS_B18_R_16.PCIE_MIMRXWDATA44 always +PCIE_BOT.PCIE_LOGIC_OUTS_B18_R_17.PCIE_MIMRXWDATA66 always +PCIE_BOT.PCIE_LOGIC_OUTS_B18_R_18.PCIE_MIMRXWDATA41 always +PCIE_BOT.PCIE_LOGIC_OUTS_B18_R_19.PCIE_MIMRXWDATA47 always +PCIE_BOT.PCIE_LOGIC_OUTS_B19_L_0.PCIE_PLTXPMSTATE2 always +PCIE_BOT.PCIE_LOGIC_OUTS_B19_L_1.PCIE_DBGVECB40 always +PCIE_BOT.PCIE_LOGIC_OUTS_B19_L_2.PCIE_DBGVECB44 always +PCIE_BOT.PCIE_LOGIC_OUTS_B19_L_3.PCIE_DBGVECB48 always +PCIE_BOT.PCIE_LOGIC_OUTS_B19_L_4.PCIE_DBGVECB52 always +PCIE_BOT.PCIE_LOGIC_OUTS_B19_L_5.PCIE_DBGVECB56 always +PCIE_BOT.PCIE_LOGIC_OUTS_B19_L_6.PCIE_DBGVECB60 always +PCIE_BOT.PCIE_LOGIC_OUTS_B19_L_7.PCIE_DBGVECC0 always +PCIE_BOT.PCIE_LOGIC_OUTS_B19_L_8.PCIE_DBGVECC4 always +PCIE_BOT.PCIE_LOGIC_OUTS_B19_L_9.PCIE_DBGVECC8 always +PCIE_BOT.PCIE_LOGIC_OUTS_B19_L_10.PCIE_DBGSCLRA always +PCIE_BOT.PCIE_LOGIC_OUTS_B19_L_11.PCIE_DBGSCLRD always +PCIE_BOT.PCIE_LOGIC_OUTS_B19_L_12.PCIE_CFGMSGDATA9 always +PCIE_BOT.PCIE_LOGIC_OUTS_B19_L_13.PCIE_TL2ERRFCPE always +PCIE_BOT.PCIE_LOGIC_OUTS_B19_L_14.PCIE_CFGDEVCONTROLMAXPAYLOAD0 always +PCIE_BOT.PCIE_LOGIC_OUTS_B19_L_15.PCIE_CFGDEVCONTROLAUXPOWEREN always +PCIE_BOT.PCIE_LOGIC_OUTS_B19_L_16.PCIE_CFGLINKSTATUSCURRENTSPEED0 always +PCIE_BOT.PCIE_LOGIC_OUTS_B19_L_17.PCIE_CFGMSGRECEIVEDASSERTINTD always +PCIE_BOT.PCIE_LOGIC_OUTS_B19_L_18.PCIE_CFGLINKSTATUSNEGOTIATEDWIDTH2 always +PCIE_BOT.PCIE_LOGIC_OUTS_B19_L_19.PCIE_CFGAERROOTERRCORRERRREPORTINGEN always +PCIE_BOT.PCIE_LOGIC_OUTS_B19_R_1.PCIE_MIMTXWDATA46 always +PCIE_BOT.PCIE_LOGIC_OUTS_B19_R_2.PCIE_MIMTXWDATA53 always +PCIE_BOT.PCIE_LOGIC_OUTS_B19_R_3.PCIE_MIMTXWDATA43 always +PCIE_BOT.PCIE_LOGIC_OUTS_B19_R_4.PCIE_DBGVECB25 always +PCIE_BOT.PCIE_LOGIC_OUTS_B19_R_5.PCIE_MIMTXWDATA1 always +PCIE_BOT.PCIE_LOGIC_OUTS_B19_R_6.PCIE_MIMTXRADDR5 always +PCIE_BOT.PCIE_LOGIC_OUTS_B19_R_7.PCIE_MIMTXWDATA32 always +PCIE_BOT.PCIE_LOGIC_OUTS_B19_R_8.PCIE_MIMTXWDATA7 always +PCIE_BOT.PCIE_LOGIC_OUTS_B19_R_9.PCIE_DBGVECA59 always +PCIE_BOT.PCIE_LOGIC_OUTS_B19_R_10.PCIE_DBGVECA55 always +PCIE_BOT.PCIE_LOGIC_OUTS_B19_R_11.PCIE_PIPETXRATE always +PCIE_BOT.PCIE_LOGIC_OUTS_B19_R_12.PCIE_DBGVECA47 always +PCIE_BOT.PCIE_LOGIC_OUTS_B19_R_13.PCIE_DBGVECA43 always +PCIE_BOT.PCIE_LOGIC_OUTS_B19_R_14.PCIE_DBGVECA38 always +PCIE_BOT.PCIE_LOGIC_OUTS_B19_R_15.PCIE_DBGVECA36 always +PCIE_BOT.PCIE_LOGIC_OUTS_B19_R_16.PCIE_MIMRXWDATA62 always +PCIE_BOT.PCIE_LOGIC_OUTS_B19_R_17.PCIE_LL2LINKSTATUS1 always +PCIE_BOT.PCIE_LOGIC_OUTS_B19_R_18.PCIE_MIMRXWDATA43 always +PCIE_BOT.PCIE_LOGIC_OUTS_B19_R_19.PCIE_PL2RXPMSTATE1 always +PCIE_BOT.PCIE_LOGIC_OUTS_B20_L_0.PCIE_DBGVECB36 always +PCIE_BOT.PCIE_LOGIC_OUTS_B20_L_1.PCIE_DBGVECB41 always +PCIE_BOT.PCIE_LOGIC_OUTS_B20_L_2.PCIE_DBGVECB45 always +PCIE_BOT.PCIE_LOGIC_OUTS_B20_L_3.PCIE_DBGVECB49 always +PCIE_BOT.PCIE_LOGIC_OUTS_B20_L_4.PCIE_DBGVECB53 always +PCIE_BOT.PCIE_LOGIC_OUTS_B20_L_5.PCIE_DBGVECB57 always +PCIE_BOT.PCIE_LOGIC_OUTS_B20_L_6.PCIE_DBGVECB61 always +PCIE_BOT.PCIE_LOGIC_OUTS_B20_L_7.PCIE_DBGVECC1 always +PCIE_BOT.PCIE_LOGIC_OUTS_B20_L_8.PCIE_DBGVECC5 always +PCIE_BOT.PCIE_LOGIC_OUTS_B20_L_9.PCIE_DBGVECC9 always +PCIE_BOT.PCIE_LOGIC_OUTS_B20_L_10.PCIE_DBGSCLRB always +PCIE_BOT.PCIE_LOGIC_OUTS_B20_L_11.PCIE_DBGSCLRE always +PCIE_BOT.PCIE_LOGIC_OUTS_B20_L_12.PCIE_CFGDEVCONTROLCORRERRREPORTINGEN always +PCIE_BOT.PCIE_LOGIC_OUTS_B20_L_13.PCIE_CFGDEVCONTROLFATALERRREPORTINGEN always +PCIE_BOT.PCIE_LOGIC_OUTS_B20_L_14.PCIE_CFGDEVCONTROLMAXPAYLOAD1 always +PCIE_BOT.PCIE_LOGIC_OUTS_B20_L_15.PCIE_CFGDEVCONTROLNOSNOOPEN always +PCIE_BOT.PCIE_LOGIC_OUTS_B20_L_16.PCIE_CFGROOTCONTROLSYSERRCORRERREN always +PCIE_BOT.PCIE_LOGIC_OUTS_B20_L_17.PCIE_CFGLINKSTATUSCURRENTSPEED1 always +PCIE_BOT.PCIE_LOGIC_OUTS_B20_L_18.PCIE_CFGLINKSTATUSNEGOTIATEDWIDTH3 always +PCIE_BOT.PCIE_LOGIC_OUTS_B20_L_19.PCIE_DRPDO7 always +PCIE_BOT.PCIE_LOGIC_OUTS_B20_R_2.PCIE_MIMTXWDATA55 always +PCIE_BOT.PCIE_LOGIC_OUTS_B20_R_3.PCIE_DBGVECB29 always +PCIE_BOT.PCIE_LOGIC_OUTS_B20_R_4.PCIE_MIMTXRADDR0 always +PCIE_BOT.PCIE_LOGIC_OUTS_B20_R_5.PCIE_MIMTXWDATA6 always +PCIE_BOT.PCIE_LOGIC_OUTS_B20_R_6.PCIE_MIMTXWDATA30 always +PCIE_BOT.PCIE_LOGIC_OUTS_B20_R_7.PCIE_PLDBGVEC9 always +PCIE_BOT.PCIE_LOGIC_OUTS_B20_R_8.PCIE_MIMTXWDATA23 always +PCIE_BOT.PCIE_LOGIC_OUTS_B20_R_9.PCIE_DBGVECA60 always +PCIE_BOT.PCIE_LOGIC_OUTS_B20_R_10.PCIE_DBGVECA56 always +PCIE_BOT.PCIE_LOGIC_OUTS_B20_R_11.PCIE_DBGVECA52 always +PCIE_BOT.PCIE_LOGIC_OUTS_B20_R_12.PCIE_DBGVECA48 always +PCIE_BOT.PCIE_LOGIC_OUTS_B20_R_13.PCIE_DBGVECA44 always +PCIE_BOT.PCIE_LOGIC_OUTS_B20_R_14.PCIE_DBGVECA39 always +PCIE_BOT.PCIE_LOGIC_OUTS_B20_R_15.PCIE_DBGVECA37 always +PCIE_BOT.PCIE_LOGIC_OUTS_B20_R_16.PCIE_LL2LINKSTATUS4 always +PCIE_BOT.PCIE_LOGIC_OUTS_B20_R_17.PCIE_DBGVECA29 always +PCIE_BOT.PCIE_LOGIC_OUTS_B20_R_18.PCIE_DBGVECA27 always +PCIE_BOT.PCIE_LOGIC_OUTS_B20_R_19.PCIE_PL2L0REQ always +PCIE_BOT.PCIE_LOGIC_OUTS_B21_L_0.PCIE_DBGVECB37 always +PCIE_BOT.PCIE_LOGIC_OUTS_B21_L_1.PCIE_DBGVECB42 always +PCIE_BOT.PCIE_LOGIC_OUTS_B21_L_2.PCIE_DBGVECB46 always +PCIE_BOT.PCIE_LOGIC_OUTS_B21_L_3.PCIE_DBGVECB50 always +PCIE_BOT.PCIE_LOGIC_OUTS_B21_L_4.PCIE_DBGVECB54 always +PCIE_BOT.PCIE_LOGIC_OUTS_B21_L_5.PCIE_DBGVECB58 always +PCIE_BOT.PCIE_LOGIC_OUTS_B21_L_6.PCIE_DBGVECB62 always +PCIE_BOT.PCIE_LOGIC_OUTS_B21_L_7.PCIE_DBGVECC2 always +PCIE_BOT.PCIE_LOGIC_OUTS_B21_L_8.PCIE_DBGVECC6 always +PCIE_BOT.PCIE_LOGIC_OUTS_B21_L_9.PCIE_DBGVECC10 always +PCIE_BOT.PCIE_LOGIC_OUTS_B21_L_10.PCIE_DBGSCLRC always +PCIE_BOT.PCIE_LOGIC_OUTS_B21_L_11.PCIE_DBGSCLRF always +PCIE_BOT.PCIE_LOGIC_OUTS_B21_L_12.PCIE_CFGDEVCONTROLNONFATALREPORTINGEN always +PCIE_BOT.PCIE_LOGIC_OUTS_B21_L_13.PCIE_CFGDEVCONTROLURERRREPORTINGEN always +PCIE_BOT.PCIE_LOGIC_OUTS_B21_L_14.PCIE_CFGDEVCONTROLMAXPAYLOAD2 always +PCIE_BOT.PCIE_LOGIC_OUTS_B21_L_15.PCIE_CFGDEVCONTROL2TLPPREFIXBLOCK always +PCIE_BOT.PCIE_LOGIC_OUTS_B21_L_16.PCIE_CFGROOTCONTROLSYSERRNONFATALERREN always +PCIE_BOT.PCIE_LOGIC_OUTS_B21_L_17.PCIE_CFGLINKSTATUSNEGOTIATEDWIDTH0 always +PCIE_BOT.PCIE_LOGIC_OUTS_B21_L_18.PCIE_CFGLINKSTATUSLINKTRAINING always +PCIE_BOT.PCIE_LOGIC_OUTS_B21_L_19.PCIE_DRPDO8 always +PCIE_BOT.PCIE_LOGIC_OUTS_B21_R_2.PCIE_MIMTXWDATA39 always +PCIE_BOT.PCIE_LOGIC_OUTS_B21_R_4.PCIE_MIMTXWADDR9 always +PCIE_BOT.PCIE_LOGIC_OUTS_B21_R_5.PCIE_PLDBGVEC10 always +PCIE_BOT.PCIE_LOGIC_OUTS_B21_R_6.PCIE_MIMTXWDATA14 always +PCIE_BOT.PCIE_LOGIC_OUTS_B21_R_8.PCIE_MIMTXWDATA9 always +PCIE_BOT.PCIE_LOGIC_OUTS_B21_R_9.PCIE_DBGVECA61 always +PCIE_BOT.PCIE_LOGIC_OUTS_B21_R_10.PCIE_DBGVECA57 always +PCIE_BOT.PCIE_LOGIC_OUTS_B21_R_11.PCIE_DBGVECA53 always +PCIE_BOT.PCIE_LOGIC_OUTS_B21_R_12.PCIE_DBGVECA49 always +PCIE_BOT.PCIE_LOGIC_OUTS_B21_R_13.PCIE_DBGVECA45 always +PCIE_BOT.PCIE_LOGIC_OUTS_B21_R_14.PCIE_DBGVECA40 always +PCIE_BOT.PCIE_LOGIC_OUTS_B21_R_15.PCIE_MIMRXRADDR12 always +PCIE_BOT.PCIE_LOGIC_OUTS_B21_R_16.PCIE_TL2PPMSUSPENDOK always +PCIE_BOT.PCIE_LOGIC_OUTS_B21_R_17.PCIE_DBGVECA30 always +PCIE_BOT.PCIE_LOGIC_OUTS_B21_R_18.PCIE_DBGVECA28 always +PCIE_BOT.PCIE_LOGIC_OUTS_B21_R_19.PCIE_DBGVECA22 always +PCIE_BOT.PCIE_LOGIC_OUTS_B22_L_0.PCIE_DBGVECB38 always +PCIE_BOT.PCIE_LOGIC_OUTS_B22_L_11.PCIE_DBGSCLRG always +PCIE_BOT.PCIE_LOGIC_OUTS_B22_L_12.PCIE_DBGSCLRH always +PCIE_BOT.PCIE_LOGIC_OUTS_B22_L_13.PCIE_DBGSCLRJ always +PCIE_BOT.PCIE_LOGIC_OUTS_B22_L_14.PCIE_PLDBGVEC0 always +PCIE_BOT.PCIE_LOGIC_OUTS_B22_L_15.PCIE_CFGSLOTCONTROLELECTROMECHILCTLPULSE always +PCIE_BOT.PCIE_LOGIC_OUTS_B22_L_16.PCIE_PLDBGVEC3 always +PCIE_BOT.PCIE_LOGIC_OUTS_B22_L_17.PCIE_PLDBGVEC5 always +PCIE_BOT.PCIE_LOGIC_OUTS_B22_L_18.PCIE_CFGROOTCONTROLSYSERRFATALERREN always +PCIE_BOT.PCIE_LOGIC_OUTS_B22_L_19.PCIE_DRPDO9 always +PCIE_BOT.PCIE_LOGIC_OUTS_B22_R_0.PCIE_DBGVECB35 always +PCIE_BOT.PCIE_LOGIC_OUTS_B22_R_1.PCIE_DBGVECB34 always +PCIE_BOT.PCIE_LOGIC_OUTS_B22_R_2.PCIE_DBGVECB33 always +PCIE_BOT.PCIE_LOGIC_OUTS_B22_R_3.PCIE_MIMTXRADDR8 always +PCIE_BOT.PCIE_LOGIC_OUTS_B22_R_4.PCIE_PLDBGVEC11 always +PCIE_BOT.PCIE_LOGIC_OUTS_B22_R_6.PCIE_MIMTXWDATA8 always +PCIE_BOT.PCIE_LOGIC_OUTS_B22_R_7.PCIE_MIMTXRADDR2 always +PCIE_BOT.PCIE_LOGIC_OUTS_B22_R_9.PCIE_DBGVECB2 always +PCIE_BOT.PCIE_LOGIC_OUTS_B22_R_10.PCIE_DBGVECB3 always +PCIE_BOT.PCIE_LOGIC_OUTS_B22_R_11.PCIE_DBGVECB4 always +PCIE_BOT.PCIE_LOGIC_OUTS_B22_R_12.PCIE_DBGVECB5 always +PCIE_BOT.PCIE_LOGIC_OUTS_B22_R_13.PCIE_DBGVECB6 always +PCIE_BOT.PCIE_LOGIC_OUTS_B22_R_14.PCIE_DBGVECA41 always +PCIE_BOT.PCIE_LOGIC_OUTS_B22_R_15.PCIE_DBGVECB8 always +PCIE_BOT.PCIE_LOGIC_OUTS_B22_R_16.PCIE_DBGVECA33 always +PCIE_BOT.PCIE_LOGIC_OUTS_B22_R_17.PCIE_DBGVECA31 always +PCIE_BOT.PCIE_LOGIC_OUTS_B22_R_18.PCIE_DBGVECB9 always +PCIE_BOT.PCIE_LOGIC_OUTS_B22_R_19.PCIE_DBGVECA23 always +PCIE_BOT.PCIE_LOGIC_OUTS_B23_L_12.PCIE_DBGSCLRI always +PCIE_BOT.PCIE_LOGIC_OUTS_B23_L_13.PCIE_DBGSCLRK always +PCIE_BOT.PCIE_LOGIC_OUTS_B23_L_14.PCIE_PLDBGVEC1 always +PCIE_BOT.PCIE_LOGIC_OUTS_B23_L_15.PCIE_PLDBGVEC2 always +PCIE_BOT.PCIE_LOGIC_OUTS_B23_L_16.PCIE_PLDBGVEC4 always +PCIE_BOT.PCIE_LOGIC_OUTS_B23_L_17.PCIE_PLDBGVEC6 always +PCIE_BOT.PCIE_LOGIC_OUTS_B23_L_18.PCIE_PLDBGVEC7 always +PCIE_BOT.PCIE_LOGIC_OUTS_B23_L_19.PCIE_DRPDO10 always +PCIE_BOT.PCIE_LOGIC_OUTS_B23_R_5.PCIE_MIMTXWADDR3 always +PCIE_BOT.PCIE_LOGIC_OUTS_B23_R_6.PCIE_MIMTXWDATA10 always +PCIE_BOT.PCIE_LOGIC_OUTS_B23_R_7.PCIE_MIMTXWADDR0 always +PCIE_BOT.PCIE_LOGIC_OUTS_B23_R_8.PCIE_MIMTXWADDR10 always +PCIE_BOT.PCIE_LOGIC_OUTS_B23_R_14.PCIE_DBGVECB7 always +PCIE_BOT.PCIE_LOGIC_OUTS_B23_R_16.PCIE_MIMRXWDATA46 always +PCIE_BOT.PCIE_LOGIC_OUTS_B23_R_17.PCIE_MIMRXWDATA39 always +PCIE_BOT.PCIE_LOGIC_OUTS_B23_R_19.PCIE_DBGVECA24 always +PCIE_BOT.PCIE_PIPECLK.PCIE_CLK0_R_11 always +PCIE_BOT.PCIE_PIPERX0ELECIDLE.PCIE_IMUX34_L_19 always +PCIE_BOT.PCIE_PIPERX1CHANISALIGNED.PCIE_IMUX33_L_9 always +PCIE_BOT.PCIE_PIPERX1ELECIDLE.PCIE_IMUX34_L_8 always +PCIE_BOT.PCIE_PIPERX1PHYSTATUS.PCIE_IMUX37_L_9 always +PCIE_BOT.PCIE_PIPERX1VALID.PCIE_IMUX36_L_9 always +PCIE_BOT.PCIE_PIPERX2CHANISALIGNED.PCIE_IMUX33_L_16 always +PCIE_BOT.PCIE_PIPERX2ELECIDLE.PCIE_IMUX34_L_15 always +PCIE_BOT.PCIE_PIPERX2PHYSTATUS.PCIE_IMUX37_L_16 always +PCIE_BOT.PCIE_PIPERX2VALID.PCIE_IMUX36_L_16 always +PCIE_BOT.PCIE_PIPERX3CHANISALIGNED.PCIE_IMUX33_L_5 always +PCIE_BOT.PCIE_PIPERX3ELECIDLE.PCIE_IMUX34_L_4 always +PCIE_BOT.PCIE_PIPERX3PHYSTATUS.PCIE_IMUX37_L_5 always +PCIE_BOT.PCIE_PIPERX3VALID.PCIE_IMUX36_L_5 always +PCIE_BOT.PCIE_PIPERX4ELECIDLE.PCIE_IMUX34_R_19 always +PCIE_BOT.PCIE_PIPERX5CHANISALIGNED.PCIE_IMUX33_R_9 always +PCIE_BOT.PCIE_PIPERX5ELECIDLE.PCIE_IMUX34_R_8 always +PCIE_BOT.PCIE_PIPERX5PHYSTATUS.PCIE_IMUX37_R_9 always +PCIE_BOT.PCIE_PIPERX5VALID.PCIE_IMUX36_R_9 always +PCIE_BOT.PCIE_PIPERX6CHANISALIGNED.PCIE_IMUX33_R_16 always +PCIE_BOT.PCIE_PIPERX6ELECIDLE.PCIE_IMUX34_R_15 always +PCIE_BOT.PCIE_PIPERX6PHYSTATUS.PCIE_IMUX37_R_16 always +PCIE_BOT.PCIE_PIPERX6VALID.PCIE_IMUX36_R_16 always +PCIE_BOT.PCIE_PIPERX7CHANISALIGNED.PCIE_IMUX33_R_5 always +PCIE_BOT.PCIE_PIPERX7ELECIDLE.PCIE_IMUX34_R_4 always +PCIE_BOT.PCIE_PIPERX7PHYSTATUS.PCIE_IMUX37_R_5 always +PCIE_BOT.PCIE_PIPERX7VALID.PCIE_IMUX36_R_5 always +PCIE_BOT.PCIE_PLDIRECTEDLINKAUTON.PCIE_IMUX5_L_0 always +PCIE_BOT.PCIE_PLDIRECTEDLINKSPEED.PCIE_IMUX4_L_0 always +PCIE_BOT.PCIE_PLDIRECTEDLTSSMNEWVLD.PCIE_IMUX8_L_0 always +PCIE_BOT.PCIE_PLDIRECTEDLTSSMSTALL.PCIE_IMUX2_L_1 always +PCIE_BOT.PCIE_PLDOWNSTREAMDEEMPHSOURCE.PCIE_IMUX7_L_0 always +PCIE_BOT.PCIE_PLRSTN.PCIE_CTRL0_R_3 always +PCIE_BOT.PCIE_PLTRANSMITHOTRST.PCIE_IMUX12_R_2 always +PCIE_BOT.PCIE_PLUPSTREAMPREFERDEEMPH.PCIE_IMUX6_L_0 always +PCIE_BOT.PCIE_SYSRSTN.PCIE_CTRL0_R_0 always +PCIE_BOT.PCIE_TLRSTN.PCIE_CTRL0_R_2 always +PCIE_BOT.PCIE_TRNRDSTRDY.PCIE_IMUX2_L_13 always +PCIE_BOT.PCIE_TRNRFCPRET.PCIE_IMUX0_L_14 always +PCIE_BOT.PCIE_TRNRNPOK.PCIE_IMUX1_L_14 always +PCIE_BOT.PCIE_TRNRNPREQ.PCIE_IMUX3_L_13 always +PCIE_BOT.PCIE_TRNTCFGGNT.PCIE_IMUX1_L_13 always +PCIE_BOT.PCIE_TRNTECRCGEN.PCIE_IMUX3_L_12 always +PCIE_BOT.PCIE_TRNTEOF.PCIE_IMUX3_L_11 always +PCIE_BOT.PCIE_TRNTERRFWD.PCIE_IMUX2_L_12 always +PCIE_BOT.PCIE_TRNTSOF.PCIE_IMUX2_L_11 always +PCIE_BOT.PCIE_TRNTSRCDSC.PCIE_IMUX1_L_12 always +PCIE_BOT.PCIE_TRNTSRCRDY.PCIE_IMUX0_L_12 always +PCIE_BOT.PCIE_TRNTSTR.PCIE_IMUX0_L_13 always +PCIE_BOT.PCIE_USERCLK.PCIE_CLK0_R_12 always +PCIE_BOT.PCIE_CFGAERINTERRUPTMSGNUM0.PCIE_IMUX12_L_14 always +PCIE_BOT.PCIE_CFGAERINTERRUPTMSGNUM1.PCIE_IMUX13_L_14 always +PCIE_BOT.PCIE_CFGAERINTERRUPTMSGNUM2.PCIE_IMUX14_L_14 always +PCIE_BOT.PCIE_CFGAERINTERRUPTMSGNUM3.PCIE_IMUX15_L_14 always +PCIE_BOT.PCIE_CFGAERINTERRUPTMSGNUM4.PCIE_IMUX12_L_16 always +PCIE_BOT.PCIE_CFGDSBUSNUMBER0.PCIE_IMUX14_R_12 always +PCIE_BOT.PCIE_CFGDSBUSNUMBER1.PCIE_IMUX15_R_12 always +PCIE_BOT.PCIE_CFGDSBUSNUMBER2.PCIE_IMUX16_R_12 always +PCIE_BOT.PCIE_CFGDSBUSNUMBER3.PCIE_IMUX13_R_11 always +PCIE_BOT.PCIE_CFGDSBUSNUMBER4.PCIE_IMUX14_R_11 always +PCIE_BOT.PCIE_CFGDSBUSNUMBER5.PCIE_IMUX15_R_11 always +PCIE_BOT.PCIE_CFGDSBUSNUMBER6.PCIE_IMUX16_R_11 always +PCIE_BOT.PCIE_CFGDSBUSNUMBER7.PCIE_IMUX13_R_10 always +PCIE_BOT.PCIE_CFGDSDEVICENUMBER0.PCIE_IMUX14_R_10 always +PCIE_BOT.PCIE_CFGDSDEVICENUMBER1.PCIE_IMUX15_R_10 always +PCIE_BOT.PCIE_CFGDSDEVICENUMBER2.PCIE_IMUX17_R_10 always +PCIE_BOT.PCIE_CFGDSDEVICENUMBER3.PCIE_IMUX20_R_2 always +PCIE_BOT.PCIE_CFGDSDEVICENUMBER4.PCIE_IMUX16_R_1 always +PCIE_BOT.PCIE_CFGDSFUNCTIONNUMBER0.PCIE_IMUX17_R_1 always +PCIE_BOT.PCIE_CFGDSFUNCTIONNUMBER1.PCIE_IMUX18_R_1 always +PCIE_BOT.PCIE_CFGDSFUNCTIONNUMBER2.PCIE_IMUX19_R_1 always +PCIE_BOT.PCIE_CFGDSN0.PCIE_IMUX11_L_5 always +PCIE_BOT.PCIE_CFGDSN1.PCIE_IMUX8_L_6 always +PCIE_BOT.PCIE_CFGDSN2.PCIE_IMUX9_L_6 always +PCIE_BOT.PCIE_CFGDSN3.PCIE_IMUX10_L_6 always +PCIE_BOT.PCIE_CFGDSN4.PCIE_IMUX11_L_6 always +PCIE_BOT.PCIE_CFGDSN5.PCIE_IMUX8_L_7 always +PCIE_BOT.PCIE_CFGDSN6.PCIE_IMUX9_L_7 always +PCIE_BOT.PCIE_CFGDSN7.PCIE_IMUX10_L_7 always +PCIE_BOT.PCIE_CFGDSN8.PCIE_IMUX11_L_7 always +PCIE_BOT.PCIE_CFGDSN9.PCIE_IMUX8_L_8 always +PCIE_BOT.PCIE_CFGDSN10.PCIE_IMUX9_L_8 always +PCIE_BOT.PCIE_CFGDSN11.PCIE_IMUX10_L_8 always +PCIE_BOT.PCIE_CFGDSN12.PCIE_IMUX11_L_8 always +PCIE_BOT.PCIE_CFGDSN13.PCIE_IMUX8_L_9 always +PCIE_BOT.PCIE_CFGDSN14.PCIE_IMUX9_L_9 always +PCIE_BOT.PCIE_CFGDSN15.PCIE_IMUX10_L_9 always +PCIE_BOT.PCIE_CFGDSN16.PCIE_IMUX11_L_9 always +PCIE_BOT.PCIE_CFGDSN17.PCIE_IMUX8_L_10 always +PCIE_BOT.PCIE_CFGDSN18.PCIE_IMUX9_L_10 always +PCIE_BOT.PCIE_CFGDSN19.PCIE_IMUX10_L_10 always +PCIE_BOT.PCIE_CFGDSN20.PCIE_IMUX11_L_10 always +PCIE_BOT.PCIE_CFGDSN21.PCIE_IMUX8_L_11 always +PCIE_BOT.PCIE_CFGDSN22.PCIE_IMUX9_L_11 always +PCIE_BOT.PCIE_CFGDSN23.PCIE_IMUX10_L_11 always +PCIE_BOT.PCIE_CFGDSN24.PCIE_IMUX11_L_11 always +PCIE_BOT.PCIE_CFGDSN25.PCIE_IMUX8_L_12 always +PCIE_BOT.PCIE_CFGDSN26.PCIE_IMUX9_L_12 always +PCIE_BOT.PCIE_CFGDSN27.PCIE_IMUX10_L_12 always +PCIE_BOT.PCIE_CFGDSN28.PCIE_IMUX11_L_12 always +PCIE_BOT.PCIE_CFGDSN29.PCIE_IMUX8_L_13 always +PCIE_BOT.PCIE_CFGDSN30.PCIE_IMUX9_L_13 always +PCIE_BOT.PCIE_CFGDSN31.PCIE_IMUX10_L_13 always +PCIE_BOT.PCIE_CFGDSN32.PCIE_IMUX11_L_13 always +PCIE_BOT.PCIE_CFGDSN33.PCIE_IMUX8_L_14 always +PCIE_BOT.PCIE_CFGDSN34.PCIE_IMUX9_L_14 always +PCIE_BOT.PCIE_CFGDSN35.PCIE_IMUX10_L_14 always +PCIE_BOT.PCIE_CFGDSN36.PCIE_IMUX11_L_14 always +PCIE_BOT.PCIE_CFGDSN37.PCIE_IMUX8_L_15 always +PCIE_BOT.PCIE_CFGDSN38.PCIE_IMUX9_L_15 always +PCIE_BOT.PCIE_CFGDSN39.PCIE_IMUX10_L_15 always +PCIE_BOT.PCIE_CFGDSN40.PCIE_IMUX11_L_15 always +PCIE_BOT.PCIE_CFGDSN41.PCIE_IMUX8_L_16 always +PCIE_BOT.PCIE_CFGDSN42.PCIE_IMUX9_L_16 always +PCIE_BOT.PCIE_CFGDSN43.PCIE_IMUX10_L_16 always +PCIE_BOT.PCIE_CFGDSN44.PCIE_IMUX11_L_16 always +PCIE_BOT.PCIE_CFGDSN45.PCIE_IMUX8_L_17 always +PCIE_BOT.PCIE_CFGDSN46.PCIE_IMUX9_L_17 always +PCIE_BOT.PCIE_CFGDSN47.PCIE_IMUX10_L_17 always +PCIE_BOT.PCIE_CFGDSN48.PCIE_IMUX11_L_17 always +PCIE_BOT.PCIE_CFGDSN49.PCIE_IMUX8_L_18 always +PCIE_BOT.PCIE_CFGDSN50.PCIE_IMUX9_L_18 always +PCIE_BOT.PCIE_CFGDSN51.PCIE_IMUX10_L_18 always +PCIE_BOT.PCIE_CFGDSN52.PCIE_IMUX11_L_18 always +PCIE_BOT.PCIE_CFGDSN53.PCIE_IMUX8_L_19 always +PCIE_BOT.PCIE_CFGDSN54.PCIE_IMUX9_L_19 always +PCIE_BOT.PCIE_CFGDSN55.PCIE_IMUX10_L_19 always +PCIE_BOT.PCIE_CFGDSN56.PCIE_IMUX11_L_19 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG12.PCIE_IMUX13_R_16 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG13.PCIE_IMUX14_R_16 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG14.PCIE_IMUX9_R_14 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG15.PCIE_IMUX10_R_14 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG16.PCIE_IMUX11_R_14 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG17.PCIE_IMUX12_R_14 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG18.PCIE_IMUX9_R_13 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG19.PCIE_IMUX10_R_13 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG20.PCIE_IMUX11_R_13 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG21.PCIE_IMUX12_R_13 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG22.PCIE_IMUX9_R_12 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG23.PCIE_IMUX10_R_12 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG24.PCIE_IMUX11_R_12 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG25.PCIE_IMUX12_R_12 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG26.PCIE_IMUX9_R_11 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG27.PCIE_IMUX10_R_11 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG28.PCIE_IMUX11_R_11 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG29.PCIE_IMUX12_R_11 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG30.PCIE_IMUX9_R_10 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG31.PCIE_IMUX10_R_10 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG32.PCIE_IMUX11_R_10 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG33.PCIE_IMUX12_R_10 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG34.PCIE_IMUX11_R_9 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG35.PCIE_IMUX12_R_9 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG36.PCIE_IMUX13_R_9 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG37.PCIE_IMUX14_R_9 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG38.PCIE_IMUX9_R_8 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG39.PCIE_IMUX10_R_8 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG40.PCIE_IMUX11_R_8 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG41.PCIE_IMUX12_R_8 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG42.PCIE_IMUX14_R_7 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG43.PCIE_IMUX15_R_7 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG44.PCIE_IMUX16_R_7 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG45.PCIE_IMUX17_R_7 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG46.PCIE_IMUX13_R_6 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG47.PCIE_IMUX14_R_6 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG48.PCIE_IMUX15_R_6 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG49.PCIE_IMUX17_R_6 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG50.PCIE_IMUX11_R_5 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG51.PCIE_IMUX12_R_5 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG52.PCIE_IMUX13_R_5 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG53.PCIE_IMUX14_R_5 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG54.PCIE_IMUX8_R_4 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG55.PCIE_IMUX9_R_4 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG56.PCIE_IMUX10_R_4 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG57.PCIE_IMUX11_R_4 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG58.PCIE_IMUX13_R_3 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG59.PCIE_IMUX14_R_3 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG60.PCIE_IMUX15_R_3 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG61.PCIE_IMUX16_R_3 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG62.PCIE_IMUX16_R_2 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG63.PCIE_IMUX17_R_2 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG64.PCIE_IMUX18_R_2 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG65.PCIE_IMUX19_R_2 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG66.PCIE_IMUX12_R_1 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG67.PCIE_IMUX13_R_1 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG68.PCIE_IMUX14_R_1 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG69.PCIE_IMUX15_R_1 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG70.PCIE_IMUX12_R_0 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG71.PCIE_IMUX13_R_0 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG72.PCIE_IMUX14_R_0 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG73.PCIE_IMUX15_R_0 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG74.PCIE_IMUX13_L_0 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG75.PCIE_IMUX14_L_0 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG76.PCIE_IMUX15_L_0 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG77.PCIE_IMUX16_L_0 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG78.PCIE_IMUX4_L_1 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG79.PCIE_IMUX5_L_1 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG80.PCIE_IMUX6_L_1 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG81.PCIE_IMUX7_L_1 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG82.PCIE_IMUX4_L_2 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG83.PCIE_IMUX5_L_2 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG84.PCIE_IMUX6_L_2 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG85.PCIE_IMUX7_L_2 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG86.PCIE_IMUX4_L_3 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG87.PCIE_IMUX5_L_3 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG88.PCIE_IMUX6_L_3 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG89.PCIE_IMUX7_L_3 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG90.PCIE_IMUX4_L_4 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG91.PCIE_IMUX5_L_4 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG92.PCIE_IMUX6_L_4 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG93.PCIE_IMUX7_L_4 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG94.PCIE_IMUX4_L_5 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG95.PCIE_IMUX5_L_5 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG96.PCIE_IMUX6_L_5 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG97.PCIE_IMUX7_L_5 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG98.PCIE_IMUX4_L_6 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG99.PCIE_IMUX5_L_6 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG100.PCIE_IMUX6_L_6 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG101.PCIE_IMUX7_L_6 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG102.PCIE_IMUX4_L_7 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG103.PCIE_IMUX5_L_7 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG104.PCIE_IMUX6_L_7 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG105.PCIE_IMUX7_L_7 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG106.PCIE_IMUX4_L_8 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG107.PCIE_IMUX5_L_8 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG108.PCIE_IMUX6_L_8 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG109.PCIE_IMUX7_L_8 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG110.PCIE_IMUX4_L_9 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG111.PCIE_IMUX5_L_9 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG112.PCIE_IMUX6_L_9 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG113.PCIE_IMUX7_L_9 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG114.PCIE_IMUX4_L_10 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG115.PCIE_IMUX5_L_10 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG116.PCIE_IMUX6_L_10 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG117.PCIE_IMUX7_L_10 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG118.PCIE_IMUX4_L_11 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG119.PCIE_IMUX5_L_11 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG120.PCIE_IMUX6_L_11 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG121.PCIE_IMUX7_L_11 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG122.PCIE_IMUX4_L_12 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG123.PCIE_IMUX5_L_12 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG124.PCIE_IMUX6_L_12 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG125.PCIE_IMUX7_L_12 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG126.PCIE_IMUX4_L_13 always +PCIE_BOT.PCIE_CFGERRAERHEADERLOG127.PCIE_IMUX5_L_13 always +PCIE_BOT.PCIE_CFGERRTLPCPLHEADER0.PCIE_IMUX6_L_13 always +PCIE_BOT.PCIE_CFGERRTLPCPLHEADER1.PCIE_IMUX7_L_13 always +PCIE_BOT.PCIE_CFGERRTLPCPLHEADER2.PCIE_IMUX4_L_14 always +PCIE_BOT.PCIE_CFGERRTLPCPLHEADER3.PCIE_IMUX5_L_14 always +PCIE_BOT.PCIE_CFGERRTLPCPLHEADER4.PCIE_IMUX6_L_14 always +PCIE_BOT.PCIE_CFGERRTLPCPLHEADER5.PCIE_IMUX7_L_14 always +PCIE_BOT.PCIE_CFGERRTLPCPLHEADER6.PCIE_IMUX4_L_15 always +PCIE_BOT.PCIE_CFGERRTLPCPLHEADER7.PCIE_IMUX5_L_15 always +PCIE_BOT.PCIE_CFGERRTLPCPLHEADER8.PCIE_IMUX6_L_15 always +PCIE_BOT.PCIE_CFGERRTLPCPLHEADER9.PCIE_IMUX7_L_15 always +PCIE_BOT.PCIE_CFGERRTLPCPLHEADER10.PCIE_IMUX4_L_16 always +PCIE_BOT.PCIE_CFGERRTLPCPLHEADER11.PCIE_IMUX5_L_16 always +PCIE_BOT.PCIE_CFGERRTLPCPLHEADER12.PCIE_IMUX6_L_16 always +PCIE_BOT.PCIE_CFGERRTLPCPLHEADER13.PCIE_IMUX7_L_16 always +PCIE_BOT.PCIE_CFGERRTLPCPLHEADER14.PCIE_IMUX4_L_17 always +PCIE_BOT.PCIE_CFGERRTLPCPLHEADER15.PCIE_IMUX5_L_17 always +PCIE_BOT.PCIE_CFGERRTLPCPLHEADER16.PCIE_IMUX6_L_17 always +PCIE_BOT.PCIE_CFGERRTLPCPLHEADER17.PCIE_IMUX7_L_17 always +PCIE_BOT.PCIE_CFGERRTLPCPLHEADER18.PCIE_IMUX4_L_18 always +PCIE_BOT.PCIE_CFGERRTLPCPLHEADER19.PCIE_IMUX5_L_18 always +PCIE_BOT.PCIE_CFGERRTLPCPLHEADER20.PCIE_IMUX6_L_18 always +PCIE_BOT.PCIE_CFGERRTLPCPLHEADER21.PCIE_IMUX7_L_18 always +PCIE_BOT.PCIE_CFGERRTLPCPLHEADER22.PCIE_IMUX4_L_19 always +PCIE_BOT.PCIE_CFGERRTLPCPLHEADER23.PCIE_IMUX5_L_19 always +PCIE_BOT.PCIE_CFGERRTLPCPLHEADER24.PCIE_IMUX6_L_19 always +PCIE_BOT.PCIE_CFGERRTLPCPLHEADER25.PCIE_IMUX7_L_19 always +PCIE_BOT.PCIE_CFGFORCEMPS0.PCIE_IMUX10_L_4 always +PCIE_BOT.PCIE_CFGFORCEMPS1.PCIE_IMUX11_L_4 always +PCIE_BOT.PCIE_CFGFORCEMPS2.PCIE_IMUX8_L_5 always +PCIE_BOT.PCIE_CFGINTERRUPTDI1.PCIE_IMUX13_R_14 always +PCIE_BOT.PCIE_CFGINTERRUPTDI2.PCIE_IMUX14_R_14 always +PCIE_BOT.PCIE_CFGINTERRUPTDI3.PCIE_IMUX15_R_14 always +PCIE_BOT.PCIE_CFGINTERRUPTDI4.PCIE_IMUX16_R_14 always +PCIE_BOT.PCIE_CFGINTERRUPTDI5.PCIE_IMUX13_R_13 always +PCIE_BOT.PCIE_CFGINTERRUPTDI6.PCIE_IMUX14_R_13 always +PCIE_BOT.PCIE_CFGINTERRUPTDI7.PCIE_IMUX15_R_13 always +PCIE_BOT.PCIE_CFGMGMTBYTEENN0.PCIE_IMUX6_R_10 always +PCIE_BOT.PCIE_CFGMGMTBYTEENN1.PCIE_IMUX7_R_10 always +PCIE_BOT.PCIE_CFGMGMTBYTEENN2.PCIE_IMUX8_R_10 always +PCIE_BOT.PCIE_CFGMGMTBYTEENN3.PCIE_IMUX5_R_11 always +PCIE_BOT.PCIE_CFGMGMTDI0.PCIE_IMUX13_R_2 always +PCIE_BOT.PCIE_CFGMGMTDI1.PCIE_IMUX14_R_2 always +PCIE_BOT.PCIE_CFGMGMTDI2.PCIE_IMUX15_R_2 always +PCIE_BOT.PCIE_CFGMGMTDI3.PCIE_IMUX9_R_3 always +PCIE_BOT.PCIE_CFGMGMTDI4.PCIE_IMUX10_R_3 always +PCIE_BOT.PCIE_CFGMGMTDI5.PCIE_IMUX11_R_3 always +PCIE_BOT.PCIE_CFGMGMTDI6.PCIE_IMUX12_R_3 always +PCIE_BOT.PCIE_CFGMGMTDI7.PCIE_IMUX4_R_4 always +PCIE_BOT.PCIE_CFGMGMTDI8.PCIE_IMUX5_R_4 always +PCIE_BOT.PCIE_CFGMGMTDI9.PCIE_IMUX6_R_4 always +PCIE_BOT.PCIE_CFGMGMTDI10.PCIE_IMUX7_R_4 always +PCIE_BOT.PCIE_CFGMGMTDI11.PCIE_IMUX7_R_5 always +PCIE_BOT.PCIE_CFGMGMTDI12.PCIE_IMUX8_R_5 always +PCIE_BOT.PCIE_CFGMGMTDI13.PCIE_IMUX9_R_5 always +PCIE_BOT.PCIE_CFGMGMTDI14.PCIE_IMUX10_R_5 always +PCIE_BOT.PCIE_CFGMGMTDI15.PCIE_IMUX9_R_6 always +PCIE_BOT.PCIE_CFGMGMTDI16.PCIE_IMUX10_R_6 always +PCIE_BOT.PCIE_CFGMGMTDI17.PCIE_IMUX11_R_6 always +PCIE_BOT.PCIE_CFGMGMTDI18.PCIE_IMUX12_R_6 always +PCIE_BOT.PCIE_CFGMGMTDI19.PCIE_IMUX10_R_7 always +PCIE_BOT.PCIE_CFGMGMTDI20.PCIE_IMUX11_R_7 always +PCIE_BOT.PCIE_CFGMGMTDI21.PCIE_IMUX12_R_7 always +PCIE_BOT.PCIE_CFGMGMTDI22.PCIE_IMUX13_R_7 always +PCIE_BOT.PCIE_CFGMGMTDI23.PCIE_IMUX5_R_8 always +PCIE_BOT.PCIE_CFGMGMTDI24.PCIE_IMUX6_R_8 always +PCIE_BOT.PCIE_CFGMGMTDI25.PCIE_IMUX7_R_8 always +PCIE_BOT.PCIE_CFGMGMTDI26.PCIE_IMUX8_R_8 always +PCIE_BOT.PCIE_CFGMGMTDI27.PCIE_IMUX7_R_9 always +PCIE_BOT.PCIE_CFGMGMTDI28.PCIE_IMUX8_R_9 always +PCIE_BOT.PCIE_CFGMGMTDI29.PCIE_IMUX9_R_9 always +PCIE_BOT.PCIE_CFGMGMTDI30.PCIE_IMUX10_R_9 always +PCIE_BOT.PCIE_CFGMGMTDI31.PCIE_IMUX5_R_10 always +PCIE_BOT.PCIE_CFGMGMTDWADDR0.PCIE_IMUX6_R_11 always +PCIE_BOT.PCIE_CFGMGMTDWADDR1.PCIE_IMUX7_R_11 always +PCIE_BOT.PCIE_CFGMGMTDWADDR2.PCIE_IMUX8_R_11 always +PCIE_BOT.PCIE_CFGMGMTDWADDR3.PCIE_IMUX5_R_12 always +PCIE_BOT.PCIE_CFGMGMTDWADDR4.PCIE_IMUX6_R_12 always +PCIE_BOT.PCIE_CFGMGMTDWADDR5.PCIE_IMUX7_R_12 always +PCIE_BOT.PCIE_CFGMGMTDWADDR6.PCIE_IMUX8_R_12 always +PCIE_BOT.PCIE_CFGMGMTDWADDR7.PCIE_IMUX5_R_13 always +PCIE_BOT.PCIE_CFGMGMTDWADDR8.PCIE_IMUX6_R_13 always +PCIE_BOT.PCIE_CFGMGMTDWADDR9.PCIE_IMUX7_R_13 always +PCIE_BOT.PCIE_CFGPCIECAPINTERRUPTMSGNUM0.PCIE_IMUX8_L_3 always +PCIE_BOT.PCIE_CFGPCIECAPINTERRUPTMSGNUM1.PCIE_IMUX9_L_3 always +PCIE_BOT.PCIE_CFGPCIECAPINTERRUPTMSGNUM2.PCIE_IMUX10_L_3 always +PCIE_BOT.PCIE_CFGPCIECAPINTERRUPTMSGNUM3.PCIE_IMUX11_L_3 always +PCIE_BOT.PCIE_CFGPCIECAPINTERRUPTMSGNUM4.PCIE_IMUX8_L_4 always +PCIE_BOT.PCIE_CFGPMFORCESTATE0.PCIE_IMUX11_L_1 always +PCIE_BOT.PCIE_CFGPMFORCESTATE1.PCIE_IMUX8_L_2 always +PCIE_BOT.PCIE_CFGPORTNUMBER0.PCIE_IMUX16_R_0 always +PCIE_BOT.PCIE_CFGPORTNUMBER1.PCIE_IMUX17_R_0 always +PCIE_BOT.PCIE_CFGPORTNUMBER2.PCIE_IMUX18_R_0 always +PCIE_BOT.PCIE_CFGPORTNUMBER3.PCIE_IMUX19_R_0 always +PCIE_BOT.PCIE_CFGPORTNUMBER4.PCIE_IMUX17_L_0 always +PCIE_BOT.PCIE_CFGPORTNUMBER5.PCIE_IMUX18_L_0 always +PCIE_BOT.PCIE_CFGPORTNUMBER6.PCIE_IMUX19_L_0 always +PCIE_BOT.PCIE_CFGPORTNUMBER7.PCIE_IMUX20_L_0 always +PCIE_BOT.PCIE_CFGREVID0.PCIE_IMUX12_L_1 always +PCIE_BOT.PCIE_CFGREVID1.PCIE_IMUX13_L_1 always +PCIE_BOT.PCIE_CFGREVID2.PCIE_IMUX14_L_1 always +PCIE_BOT.PCIE_CFGREVID3.PCIE_IMUX15_L_1 always +PCIE_BOT.PCIE_CFGREVID4.PCIE_IMUX12_L_2 always +PCIE_BOT.PCIE_CFGREVID5.PCIE_IMUX13_L_2 always +PCIE_BOT.PCIE_CFGREVID6.PCIE_IMUX14_L_2 always +PCIE_BOT.PCIE_CFGREVID7.PCIE_IMUX15_L_2 always +PCIE_BOT.PCIE_CFGSUBSYSID0.PCIE_IMUX12_L_3 always +PCIE_BOT.PCIE_CFGSUBSYSID1.PCIE_IMUX13_L_3 always +PCIE_BOT.PCIE_CFGSUBSYSID2.PCIE_IMUX14_L_3 always +PCIE_BOT.PCIE_CFGSUBSYSID3.PCIE_IMUX15_L_3 always +PCIE_BOT.PCIE_CFGSUBSYSID4.PCIE_IMUX12_L_5 always +PCIE_BOT.PCIE_CFGSUBSYSID5.PCIE_IMUX13_L_5 always +PCIE_BOT.PCIE_CFGSUBSYSID6.PCIE_IMUX12_L_6 always +PCIE_BOT.PCIE_CFGSUBSYSID7.PCIE_IMUX13_L_6 always +PCIE_BOT.PCIE_CFGSUBSYSID8.PCIE_IMUX14_L_6 always +PCIE_BOT.PCIE_CFGSUBSYSID9.PCIE_IMUX15_L_6 always +PCIE_BOT.PCIE_CFGSUBSYSID10.PCIE_IMUX12_L_7 always +PCIE_BOT.PCIE_CFGSUBSYSID11.PCIE_IMUX13_L_7 always +PCIE_BOT.PCIE_CFGSUBSYSID12.PCIE_IMUX14_L_7 always +PCIE_BOT.PCIE_CFGSUBSYSID13.PCIE_IMUX15_L_7 always +PCIE_BOT.PCIE_CFGSUBSYSID14.PCIE_IMUX12_L_9 always +PCIE_BOT.PCIE_CFGSUBSYSID15.PCIE_IMUX13_L_9 always +PCIE_BOT.PCIE_CFGSUBSYSVENDID0.PCIE_IMUX12_L_10 always +PCIE_BOT.PCIE_CFGSUBSYSVENDID1.PCIE_IMUX13_L_10 always +PCIE_BOT.PCIE_CFGSUBSYSVENDID2.PCIE_IMUX14_L_10 always +PCIE_BOT.PCIE_CFGSUBSYSVENDID3.PCIE_IMUX15_L_10 always +PCIE_BOT.PCIE_CFGSUBSYSVENDID4.PCIE_IMUX12_L_11 always +PCIE_BOT.PCIE_CFGSUBSYSVENDID5.PCIE_IMUX13_L_11 always +PCIE_BOT.PCIE_CFGSUBSYSVENDID6.PCIE_IMUX14_L_11 always +PCIE_BOT.PCIE_CFGSUBSYSVENDID7.PCIE_IMUX15_L_11 always +PCIE_BOT.PCIE_CFGSUBSYSVENDID8.PCIE_IMUX12_L_12 always +PCIE_BOT.PCIE_CFGSUBSYSVENDID9.PCIE_IMUX13_L_12 always +PCIE_BOT.PCIE_CFGSUBSYSVENDID10.PCIE_IMUX14_L_12 always +PCIE_BOT.PCIE_CFGSUBSYSVENDID11.PCIE_IMUX15_L_12 always +PCIE_BOT.PCIE_CFGSUBSYSVENDID12.PCIE_IMUX12_L_13 always +PCIE_BOT.PCIE_CFGSUBSYSVENDID13.PCIE_IMUX13_L_13 always +PCIE_BOT.PCIE_CFGSUBSYSVENDID14.PCIE_IMUX14_L_13 always +PCIE_BOT.PCIE_CFGSUBSYSVENDID15.PCIE_IMUX15_L_13 always +PCIE_BOT.PCIE_CFGVENDID1.PCIE_IMUX17_R_14 always +PCIE_BOT.PCIE_CFGVENDID2.PCIE_IMUX17_R_13 always +PCIE_BOT.PCIE_CFGVENDID3.PCIE_IMUX18_R_13 always +PCIE_BOT.PCIE_CFGVENDID4.PCIE_IMUX19_R_13 always +PCIE_BOT.PCIE_CFGVENDID5.PCIE_IMUX20_R_13 always +PCIE_BOT.PCIE_CFGVENDID6.PCIE_IMUX17_R_12 always +PCIE_BOT.PCIE_CFGVENDID7.PCIE_IMUX18_R_12 always +PCIE_BOT.PCIE_CFGVENDID8.PCIE_IMUX19_R_12 always +PCIE_BOT.PCIE_CFGVENDID9.PCIE_IMUX20_R_12 always +PCIE_BOT.PCIE_CFGVENDID10.PCIE_IMUX17_R_11 always +PCIE_BOT.PCIE_CFGVENDID11.PCIE_IMUX18_R_11 always +PCIE_BOT.PCIE_CFGVENDID12.PCIE_IMUX19_R_11 always +PCIE_BOT.PCIE_CFGVENDID13.PCIE_IMUX20_R_11 always +PCIE_BOT.PCIE_CFGVENDID14.PCIE_IMUX20_R_1 always +PCIE_BOT.PCIE_CFGVENDID15.PCIE_IMUX20_R_0 always +PCIE_BOT.PCIE_DBGMODE1.PCIE_IMUX21_R_13 always +PCIE_BOT.PCIE_DRPADDR0.PCIE_IMUX13_L_17 always +PCIE_BOT.PCIE_DRPADDR1.PCIE_IMUX14_L_17 always +PCIE_BOT.PCIE_DRPADDR2.PCIE_IMUX15_L_17 always +PCIE_BOT.PCIE_DRPADDR3.PCIE_IMUX12_L_18 always +PCIE_BOT.PCIE_DRPADDR4.PCIE_IMUX13_L_18 always +PCIE_BOT.PCIE_DRPADDR5.PCIE_IMUX14_L_18 always +PCIE_BOT.PCIE_DRPADDR6.PCIE_IMUX15_L_18 always +PCIE_BOT.PCIE_MIMRXRDATA0.PCIE_IMUX0_R_15 always +PCIE_BOT.PCIE_MIMRXRDATA1.PCIE_IMUX1_R_15 always +PCIE_BOT.PCIE_MIMRXRDATA2.PCIE_IMUX2_R_15 always +PCIE_BOT.PCIE_MIMRXRDATA3.PCIE_IMUX3_R_15 always +PCIE_BOT.PCIE_MIMRXRDATA4.PCIE_IMUX0_R_16 always +PCIE_BOT.PCIE_MIMRXRDATA5.PCIE_IMUX1_R_16 always +PCIE_BOT.PCIE_MIMRXRDATA6.PCIE_IMUX2_R_16 always +PCIE_BOT.PCIE_MIMRXRDATA7.PCIE_IMUX3_R_16 always +PCIE_BOT.PCIE_MIMRXRDATA8.PCIE_IMUX0_R_17 always +PCIE_BOT.PCIE_MIMRXRDATA9.PCIE_IMUX1_R_17 always +PCIE_BOT.PCIE_MIMRXRDATA10.PCIE_IMUX2_R_17 always +PCIE_BOT.PCIE_MIMRXRDATA11.PCIE_IMUX3_R_17 always +PCIE_BOT.PCIE_MIMRXRDATA12.PCIE_IMUX0_R_18 always +PCIE_BOT.PCIE_MIMRXRDATA13.PCIE_IMUX1_R_18 always +PCIE_BOT.PCIE_MIMRXRDATA14.PCIE_IMUX2_R_18 always +PCIE_BOT.PCIE_MIMRXRDATA15.PCIE_IMUX3_R_18 always +PCIE_BOT.PCIE_MIMRXRDATA16.PCIE_IMUX0_R_19 always +PCIE_BOT.PCIE_MIMRXRDATA17.PCIE_IMUX1_R_19 always +PCIE_BOT.PCIE_MIMRXRDATA18.PCIE_IMUX2_R_19 always +PCIE_BOT.PCIE_MIMRXRDATA19.PCIE_IMUX3_R_19 always +PCIE_BOT.PCIE_MIMRXRDATA56.PCIE_IMUX4_R_19 always +PCIE_BOT.PCIE_MIMRXRDATA57.PCIE_IMUX5_R_19 always +PCIE_BOT.PCIE_MIMRXRDATA58.PCIE_IMUX6_R_19 always +PCIE_BOT.PCIE_MIMRXRDATA59.PCIE_IMUX7_R_19 always +PCIE_BOT.PCIE_MIMRXRDATA60.PCIE_IMUX4_R_18 always +PCIE_BOT.PCIE_MIMRXRDATA61.PCIE_IMUX5_R_18 always +PCIE_BOT.PCIE_MIMRXRDATA62.PCIE_IMUX6_R_18 always +PCIE_BOT.PCIE_MIMRXRDATA63.PCIE_IMUX7_R_18 always +PCIE_BOT.PCIE_MIMRXRDATA64.PCIE_IMUX4_R_17 always +PCIE_BOT.PCIE_MIMRXRDATA65.PCIE_IMUX5_R_17 always +PCIE_BOT.PCIE_MIMRXRDATA66.PCIE_IMUX6_R_17 always +PCIE_BOT.PCIE_MIMRXRDATA67.PCIE_IMUX7_R_17 always +PCIE_BOT.PCIE_MIMTXRDATA0.PCIE_IMUX0_R_0 always +PCIE_BOT.PCIE_MIMTXRDATA1.PCIE_IMUX1_R_0 always +PCIE_BOT.PCIE_MIMTXRDATA2.PCIE_IMUX2_R_0 always +PCIE_BOT.PCIE_MIMTXRDATA3.PCIE_IMUX3_R_0 always +PCIE_BOT.PCIE_MIMTXRDATA4.PCIE_IMUX0_R_1 always +PCIE_BOT.PCIE_MIMTXRDATA5.PCIE_IMUX1_R_1 always +PCIE_BOT.PCIE_MIMTXRDATA6.PCIE_IMUX2_R_1 always +PCIE_BOT.PCIE_MIMTXRDATA7.PCIE_IMUX3_R_1 always +PCIE_BOT.PCIE_MIMTXRDATA8.PCIE_IMUX0_R_2 always +PCIE_BOT.PCIE_MIMTXRDATA9.PCIE_IMUX1_R_2 always +PCIE_BOT.PCIE_MIMTXRDATA10.PCIE_IMUX2_R_2 always +PCIE_BOT.PCIE_MIMTXRDATA11.PCIE_IMUX3_R_2 always +PCIE_BOT.PCIE_MIMTXRDATA12.PCIE_IMUX0_R_3 always +PCIE_BOT.PCIE_MIMTXRDATA13.PCIE_IMUX1_R_3 always +PCIE_BOT.PCIE_MIMTXRDATA14.PCIE_IMUX2_R_3 always +PCIE_BOT.PCIE_MIMTXRDATA15.PCIE_IMUX3_R_3 always +PCIE_BOT.PCIE_MIMTXRDATA16.PCIE_IMUX0_R_4 always +PCIE_BOT.PCIE_MIMTXRDATA17.PCIE_IMUX1_R_4 always +PCIE_BOT.PCIE_MIMTXRDATA18.PCIE_IMUX2_R_4 always +PCIE_BOT.PCIE_MIMTXRDATA19.PCIE_IMUX3_R_4 always +PCIE_BOT.PCIE_MIMTXRDATA20.PCIE_IMUX0_R_5 always +PCIE_BOT.PCIE_MIMTXRDATA21.PCIE_IMUX1_R_5 always +PCIE_BOT.PCIE_MIMTXRDATA22.PCIE_IMUX2_R_5 always +PCIE_BOT.PCIE_MIMTXRDATA23.PCIE_IMUX3_R_5 always +PCIE_BOT.PCIE_MIMTXRDATA24.PCIE_IMUX0_R_6 always +PCIE_BOT.PCIE_MIMTXRDATA25.PCIE_IMUX1_R_6 always +PCIE_BOT.PCIE_MIMTXRDATA26.PCIE_IMUX2_R_6 always +PCIE_BOT.PCIE_MIMTXRDATA27.PCIE_IMUX3_R_6 always +PCIE_BOT.PCIE_MIMTXRDATA28.PCIE_IMUX0_R_7 always +PCIE_BOT.PCIE_MIMTXRDATA29.PCIE_IMUX1_R_7 always +PCIE_BOT.PCIE_MIMTXRDATA30.PCIE_IMUX2_R_7 always +PCIE_BOT.PCIE_MIMTXRDATA31.PCIE_IMUX3_R_7 always +PCIE_BOT.PCIE_MIMTXRDATA32.PCIE_IMUX0_R_8 always +PCIE_BOT.PCIE_MIMTXRDATA33.PCIE_IMUX1_R_8 always +PCIE_BOT.PCIE_MIMTXRDATA34.PCIE_IMUX2_R_8 always +PCIE_BOT.PCIE_MIMTXRDATA35.PCIE_IMUX3_R_8 always +PCIE_BOT.PCIE_MIMTXRDATA36.PCIE_IMUX0_R_9 always +PCIE_BOT.PCIE_MIMTXRDATA37.PCIE_IMUX1_R_9 always +PCIE_BOT.PCIE_MIMTXRDATA38.PCIE_IMUX2_R_9 always +PCIE_BOT.PCIE_MIMTXRDATA39.PCIE_IMUX3_R_9 always +PCIE_BOT.PCIE_MIMTXRDATA40.PCIE_IMUX4_R_7 always +PCIE_BOT.PCIE_MIMTXRDATA41.PCIE_IMUX5_R_7 always +PCIE_BOT.PCIE_MIMTXRDATA42.PCIE_IMUX6_R_7 always +PCIE_BOT.PCIE_MIMTXRDATA43.PCIE_IMUX7_R_7 always +PCIE_BOT.PCIE_MIMTXRDATA44.PCIE_IMUX4_R_6 always +PCIE_BOT.PCIE_MIMTXRDATA45.PCIE_IMUX5_R_6 always +PCIE_BOT.PCIE_MIMTXRDATA46.PCIE_IMUX6_R_6 always +PCIE_BOT.PCIE_MIMTXRDATA47.PCIE_IMUX7_R_6 always +PCIE_BOT.PCIE_MIMTXRDATA48.PCIE_IMUX4_R_5 always +PCIE_BOT.PCIE_MIMTXRDATA49.PCIE_IMUX5_R_5 always +PCIE_BOT.PCIE_MIMTXRDATA50.PCIE_IMUX4_R_3 always +PCIE_BOT.PCIE_MIMTXRDATA51.PCIE_IMUX5_R_3 always +PCIE_BOT.PCIE_MIMTXRDATA52.PCIE_IMUX6_R_3 always +PCIE_BOT.PCIE_MIMTXRDATA53.PCIE_IMUX7_R_3 always +PCIE_BOT.PCIE_MIMTXRDATA54.PCIE_IMUX4_R_2 always +PCIE_BOT.PCIE_MIMTXRDATA55.PCIE_IMUX5_R_2 always +PCIE_BOT.PCIE_MIMTXRDATA56.PCIE_IMUX6_R_2 always +PCIE_BOT.PCIE_MIMTXRDATA57.PCIE_IMUX7_R_2 always +PCIE_BOT.PCIE_MIMTXRDATA58.PCIE_IMUX4_R_1 always +PCIE_BOT.PCIE_MIMTXRDATA59.PCIE_IMUX5_R_1 always +PCIE_BOT.PCIE_MIMTXRDATA60.PCIE_IMUX6_R_1 always +PCIE_BOT.PCIE_MIMTXRDATA61.PCIE_IMUX7_R_1 always +PCIE_BOT.PCIE_MIMTXRDATA62.PCIE_IMUX4_R_0 always +PCIE_BOT.PCIE_MIMTXRDATA63.PCIE_IMUX5_R_0 always +PCIE_BOT.PCIE_MIMTXRDATA64.PCIE_IMUX6_R_0 always +PCIE_BOT.PCIE_MIMTXRDATA65.PCIE_IMUX7_R_0 always +PCIE_BOT.PCIE_MIMTXRDATA66.PCIE_IMUX4_R_9 always +PCIE_BOT.PCIE_MIMTXRDATA67.PCIE_IMUX5_R_9 always +PCIE_BOT.PCIE_MIMTXRDATA68.PCIE_IMUX8_R_7 always +PCIE_BOT.PCIE_PIPERX0CHARISK1.PCIE_IMUX16_L_19 always +PCIE_BOT.PCIE_PIPERX0DATA8.PCIE_IMUX37_L_19 always +PCIE_BOT.PCIE_PIPERX0DATA9.PCIE_IMUX36_L_19 always +PCIE_BOT.PCIE_PIPERX0DATA10.PCIE_IMUX33_L_19 always +PCIE_BOT.PCIE_PIPERX0DATA11.PCIE_IMUX32_L_19 always +PCIE_BOT.PCIE_PIPERX0DATA12.PCIE_IMUX39_L_18 always +PCIE_BOT.PCIE_PIPERX0DATA13.PCIE_IMUX38_L_18 always +PCIE_BOT.PCIE_PIPERX0DATA14.PCIE_IMUX35_L_18 always +PCIE_BOT.PCIE_PIPERX0DATA15.PCIE_IMUX34_L_18 always +PCIE_BOT.PCIE_PIPERX0STATUS0.PCIE_IMUX39_L_19 always +PCIE_BOT.PCIE_PIPERX0STATUS1.PCIE_IMUX38_L_19 always +PCIE_BOT.PCIE_PIPERX0STATUS2.PCIE_IMUX35_L_19 always +PCIE_BOT.PCIE_PIPERX1CHARISK0.PCIE_IMUX16_L_10 always +PCIE_BOT.PCIE_PIPERX1CHARISK1.PCIE_IMUX16_L_8 always +PCIE_BOT.PCIE_PIPERX1DATA0.PCIE_IMUX37_L_10 always +PCIE_BOT.PCIE_PIPERX1DATA1.PCIE_IMUX36_L_10 always +PCIE_BOT.PCIE_PIPERX1DATA2.PCIE_IMUX33_L_10 always +PCIE_BOT.PCIE_PIPERX1DATA3.PCIE_IMUX32_L_10 always +PCIE_BOT.PCIE_PIPERX1DATA4.PCIE_IMUX39_L_9 always +PCIE_BOT.PCIE_PIPERX1DATA5.PCIE_IMUX38_L_9 always +PCIE_BOT.PCIE_PIPERX1DATA6.PCIE_IMUX35_L_9 always +PCIE_BOT.PCIE_PIPERX1DATA7.PCIE_IMUX34_L_9 always +PCIE_BOT.PCIE_PIPERX1DATA8.PCIE_IMUX37_L_8 always +PCIE_BOT.PCIE_PIPERX1DATA9.PCIE_IMUX36_L_8 always +PCIE_BOT.PCIE_PIPERX1DATA10.PCIE_IMUX33_L_8 always +PCIE_BOT.PCIE_PIPERX1DATA11.PCIE_IMUX32_L_8 always +PCIE_BOT.PCIE_PIPERX1DATA12.PCIE_IMUX39_L_7 always +PCIE_BOT.PCIE_PIPERX1DATA13.PCIE_IMUX38_L_7 always +PCIE_BOT.PCIE_PIPERX1DATA14.PCIE_IMUX35_L_7 always +PCIE_BOT.PCIE_PIPERX1DATA15.PCIE_IMUX34_L_7 always +PCIE_BOT.PCIE_PIPERX1STATUS0.PCIE_IMUX39_L_8 always +PCIE_BOT.PCIE_PIPERX1STATUS1.PCIE_IMUX38_L_8 always +PCIE_BOT.PCIE_PIPERX1STATUS2.PCIE_IMUX35_L_8 always +PCIE_BOT.PCIE_PIPERX2CHARISK0.PCIE_IMUX16_L_17 always +PCIE_BOT.PCIE_PIPERX2CHARISK1.PCIE_IMUX16_L_15 always +PCIE_BOT.PCIE_PIPERX2DATA0.PCIE_IMUX37_L_17 always +PCIE_BOT.PCIE_PIPERX2DATA1.PCIE_IMUX36_L_17 always +PCIE_BOT.PCIE_PIPERX2DATA2.PCIE_IMUX33_L_17 always +PCIE_BOT.PCIE_PIPERX2DATA3.PCIE_IMUX32_L_17 always +PCIE_BOT.PCIE_PIPERX2DATA4.PCIE_IMUX39_L_16 always +PCIE_BOT.PCIE_PIPERX2DATA5.PCIE_IMUX38_L_16 always +PCIE_BOT.PCIE_PIPERX2DATA6.PCIE_IMUX35_L_16 always +PCIE_BOT.PCIE_PIPERX2DATA7.PCIE_IMUX34_L_16 always +PCIE_BOT.PCIE_PIPERX2DATA8.PCIE_IMUX37_L_15 always +PCIE_BOT.PCIE_PIPERX2DATA9.PCIE_IMUX36_L_15 always +PCIE_BOT.PCIE_PIPERX2DATA10.PCIE_IMUX33_L_15 always +PCIE_BOT.PCIE_PIPERX2DATA11.PCIE_IMUX32_L_15 always +PCIE_BOT.PCIE_PIPERX2DATA12.PCIE_IMUX39_L_14 always +PCIE_BOT.PCIE_PIPERX2DATA13.PCIE_IMUX38_L_14 always +PCIE_BOT.PCIE_PIPERX2DATA14.PCIE_IMUX35_L_14 always +PCIE_BOT.PCIE_PIPERX2DATA15.PCIE_IMUX34_L_14 always +PCIE_BOT.PCIE_PIPERX2STATUS0.PCIE_IMUX39_L_15 always +PCIE_BOT.PCIE_PIPERX2STATUS1.PCIE_IMUX38_L_15 always +PCIE_BOT.PCIE_PIPERX2STATUS2.PCIE_IMUX35_L_15 always +PCIE_BOT.PCIE_PIPERX3CHARISK0.PCIE_IMUX16_L_6 always +PCIE_BOT.PCIE_PIPERX3CHARISK1.PCIE_IMUX16_L_4 always +PCIE_BOT.PCIE_PIPERX3DATA0.PCIE_IMUX37_L_6 always +PCIE_BOT.PCIE_PIPERX3DATA1.PCIE_IMUX36_L_6 always +PCIE_BOT.PCIE_PIPERX3DATA2.PCIE_IMUX33_L_6 always +PCIE_BOT.PCIE_PIPERX3DATA3.PCIE_IMUX32_L_6 always +PCIE_BOT.PCIE_PIPERX3DATA4.PCIE_IMUX39_L_5 always +PCIE_BOT.PCIE_PIPERX3DATA5.PCIE_IMUX38_L_5 always +PCIE_BOT.PCIE_PIPERX3DATA6.PCIE_IMUX35_L_5 always +PCIE_BOT.PCIE_PIPERX3DATA7.PCIE_IMUX34_L_5 always +PCIE_BOT.PCIE_PIPERX3DATA8.PCIE_IMUX37_L_4 always +PCIE_BOT.PCIE_PIPERX3DATA9.PCIE_IMUX36_L_4 always +PCIE_BOT.PCIE_PIPERX3DATA10.PCIE_IMUX33_L_4 always +PCIE_BOT.PCIE_PIPERX3DATA11.PCIE_IMUX32_L_4 always +PCIE_BOT.PCIE_PIPERX3DATA12.PCIE_IMUX39_L_3 always +PCIE_BOT.PCIE_PIPERX3DATA13.PCIE_IMUX38_L_3 always +PCIE_BOT.PCIE_PIPERX3DATA14.PCIE_IMUX35_L_3 always +PCIE_BOT.PCIE_PIPERX3DATA15.PCIE_IMUX34_L_3 always +PCIE_BOT.PCIE_PIPERX3STATUS0.PCIE_IMUX39_L_4 always +PCIE_BOT.PCIE_PIPERX3STATUS1.PCIE_IMUX38_L_4 always +PCIE_BOT.PCIE_PIPERX3STATUS2.PCIE_IMUX35_L_4 always +PCIE_BOT.PCIE_PIPERX4CHARISK1.PCIE_IMUX16_R_19 always +PCIE_BOT.PCIE_PIPERX4DATA8.PCIE_IMUX37_R_19 always +PCIE_BOT.PCIE_PIPERX4DATA9.PCIE_IMUX36_R_19 always +PCIE_BOT.PCIE_PIPERX4DATA10.PCIE_IMUX33_R_19 always +PCIE_BOT.PCIE_PIPERX4DATA11.PCIE_IMUX32_R_19 always +PCIE_BOT.PCIE_PIPERX4DATA12.PCIE_IMUX39_R_18 always +PCIE_BOT.PCIE_PIPERX4DATA13.PCIE_IMUX38_R_18 always +PCIE_BOT.PCIE_PIPERX4DATA14.PCIE_IMUX35_R_18 always +PCIE_BOT.PCIE_PIPERX4DATA15.PCIE_IMUX34_R_18 always +PCIE_BOT.PCIE_PIPERX4STATUS0.PCIE_IMUX39_R_19 always +PCIE_BOT.PCIE_PIPERX4STATUS1.PCIE_IMUX38_R_19 always +PCIE_BOT.PCIE_PIPERX4STATUS2.PCIE_IMUX35_R_19 always +PCIE_BOT.PCIE_PIPERX5CHARISK0.PCIE_IMUX16_R_10 always +PCIE_BOT.PCIE_PIPERX5CHARISK1.PCIE_IMUX16_R_8 always +PCIE_BOT.PCIE_PIPERX5DATA0.PCIE_IMUX37_R_10 always +PCIE_BOT.PCIE_PIPERX5DATA1.PCIE_IMUX36_R_10 always +PCIE_BOT.PCIE_PIPERX5DATA2.PCIE_IMUX33_R_10 always +PCIE_BOT.PCIE_PIPERX5DATA3.PCIE_IMUX32_R_10 always +PCIE_BOT.PCIE_PIPERX5DATA4.PCIE_IMUX39_R_9 always +PCIE_BOT.PCIE_PIPERX5DATA5.PCIE_IMUX38_R_9 always +PCIE_BOT.PCIE_PIPERX5DATA6.PCIE_IMUX35_R_9 always +PCIE_BOT.PCIE_PIPERX5DATA7.PCIE_IMUX34_R_9 always +PCIE_BOT.PCIE_PIPERX5DATA8.PCIE_IMUX37_R_8 always +PCIE_BOT.PCIE_PIPERX5DATA9.PCIE_IMUX36_R_8 always +PCIE_BOT.PCIE_PIPERX5DATA10.PCIE_IMUX33_R_8 always +PCIE_BOT.PCIE_PIPERX5DATA11.PCIE_IMUX32_R_8 always +PCIE_BOT.PCIE_PIPERX5DATA12.PCIE_IMUX39_R_7 always +PCIE_BOT.PCIE_PIPERX5DATA13.PCIE_IMUX38_R_7 always +PCIE_BOT.PCIE_PIPERX5DATA14.PCIE_IMUX35_R_7 always +PCIE_BOT.PCIE_PIPERX5DATA15.PCIE_IMUX34_R_7 always +PCIE_BOT.PCIE_PIPERX5STATUS0.PCIE_IMUX39_R_8 always +PCIE_BOT.PCIE_PIPERX5STATUS1.PCIE_IMUX38_R_8 always +PCIE_BOT.PCIE_PIPERX5STATUS2.PCIE_IMUX35_R_8 always +PCIE_BOT.PCIE_PIPERX6CHARISK0.PCIE_IMUX16_R_17 always +PCIE_BOT.PCIE_PIPERX6CHARISK1.PCIE_IMUX16_R_15 always +PCIE_BOT.PCIE_PIPERX6DATA0.PCIE_IMUX37_R_17 always +PCIE_BOT.PCIE_PIPERX6DATA1.PCIE_IMUX36_R_17 always +PCIE_BOT.PCIE_PIPERX6DATA2.PCIE_IMUX33_R_17 always +PCIE_BOT.PCIE_PIPERX6DATA3.PCIE_IMUX32_R_17 always +PCIE_BOT.PCIE_PIPERX6DATA4.PCIE_IMUX39_R_16 always +PCIE_BOT.PCIE_PIPERX6DATA5.PCIE_IMUX38_R_16 always +PCIE_BOT.PCIE_PIPERX6DATA6.PCIE_IMUX35_R_16 always +PCIE_BOT.PCIE_PIPERX6DATA7.PCIE_IMUX34_R_16 always +PCIE_BOT.PCIE_PIPERX6DATA8.PCIE_IMUX37_R_15 always +PCIE_BOT.PCIE_PIPERX6DATA9.PCIE_IMUX36_R_15 always +PCIE_BOT.PCIE_PIPERX6DATA10.PCIE_IMUX33_R_15 always +PCIE_BOT.PCIE_PIPERX6DATA11.PCIE_IMUX32_R_15 always +PCIE_BOT.PCIE_PIPERX6DATA12.PCIE_IMUX39_R_14 always +PCIE_BOT.PCIE_PIPERX6DATA13.PCIE_IMUX38_R_14 always +PCIE_BOT.PCIE_PIPERX6DATA14.PCIE_IMUX35_R_14 always +PCIE_BOT.PCIE_PIPERX6DATA15.PCIE_IMUX34_R_14 always +PCIE_BOT.PCIE_PIPERX6STATUS0.PCIE_IMUX39_R_15 always +PCIE_BOT.PCIE_PIPERX6STATUS1.PCIE_IMUX38_R_15 always +PCIE_BOT.PCIE_PIPERX6STATUS2.PCIE_IMUX35_R_15 always +PCIE_BOT.PCIE_PIPERX7CHARISK0.PCIE_IMUX16_R_6 always +PCIE_BOT.PCIE_PIPERX7CHARISK1.PCIE_IMUX16_R_4 always +PCIE_BOT.PCIE_PIPERX7DATA0.PCIE_IMUX37_R_6 always +PCIE_BOT.PCIE_PIPERX7DATA1.PCIE_IMUX36_R_6 always +PCIE_BOT.PCIE_PIPERX7DATA2.PCIE_IMUX33_R_6 always +PCIE_BOT.PCIE_PIPERX7DATA3.PCIE_IMUX32_R_6 always +PCIE_BOT.PCIE_PIPERX7DATA4.PCIE_IMUX39_R_5 always +PCIE_BOT.PCIE_PIPERX7DATA5.PCIE_IMUX38_R_5 always +PCIE_BOT.PCIE_PIPERX7DATA6.PCIE_IMUX35_R_5 always +PCIE_BOT.PCIE_PIPERX7DATA7.PCIE_IMUX34_R_5 always +PCIE_BOT.PCIE_PIPERX7DATA8.PCIE_IMUX37_R_4 always +PCIE_BOT.PCIE_PIPERX7DATA9.PCIE_IMUX36_R_4 always +PCIE_BOT.PCIE_PIPERX7DATA10.PCIE_IMUX33_R_4 always +PCIE_BOT.PCIE_PIPERX7DATA11.PCIE_IMUX32_R_4 always +PCIE_BOT.PCIE_PIPERX7DATA12.PCIE_IMUX39_R_3 always +PCIE_BOT.PCIE_PIPERX7DATA13.PCIE_IMUX38_R_3 always +PCIE_BOT.PCIE_PIPERX7DATA14.PCIE_IMUX35_R_3 always +PCIE_BOT.PCIE_PIPERX7DATA15.PCIE_IMUX34_R_3 always +PCIE_BOT.PCIE_PIPERX7STATUS0.PCIE_IMUX39_R_4 always +PCIE_BOT.PCIE_PIPERX7STATUS1.PCIE_IMUX38_R_4 always +PCIE_BOT.PCIE_PIPERX7STATUS2.PCIE_IMUX35_R_4 always +PCIE_BOT.PCIE_PLDBGMODE0.PCIE_IMUX21_R_11 always +PCIE_BOT.PCIE_PLDBGMODE1.PCIE_IMUX16_L_1 always +PCIE_BOT.PCIE_PLDBGMODE2.PCIE_IMUX17_L_1 always +PCIE_BOT.PCIE_PLDIRECTEDLINKCHANGE0.PCIE_IMUX0_L_0 always +PCIE_BOT.PCIE_PLDIRECTEDLINKCHANGE1.PCIE_IMUX1_L_0 always +PCIE_BOT.PCIE_PLDIRECTEDLINKWIDTH0.PCIE_IMUX2_L_0 always +PCIE_BOT.PCIE_PLDIRECTEDLINKWIDTH1.PCIE_IMUX3_L_0 always +PCIE_BOT.PCIE_PLDIRECTEDLTSSMNEW0.PCIE_IMUX9_L_0 always +PCIE_BOT.PCIE_PLDIRECTEDLTSSMNEW1.PCIE_IMUX10_L_0 always +PCIE_BOT.PCIE_PLDIRECTEDLTSSMNEW2.PCIE_IMUX11_L_0 always +PCIE_BOT.PCIE_PLDIRECTEDLTSSMNEW3.PCIE_IMUX12_L_0 always +PCIE_BOT.PCIE_PLDIRECTEDLTSSMNEW4.PCIE_IMUX0_L_1 always +PCIE_BOT.PCIE_PLDIRECTEDLTSSMNEW5.PCIE_IMUX1_L_1 always +PCIE_BOT.PCIE_TRNFCSEL0.PCIE_IMUX2_L_14 always +PCIE_BOT.PCIE_TRNFCSEL1.PCIE_IMUX3_L_14 always +PCIE_BOT.PCIE_TRNFCSEL2.PCIE_IMUX0_L_15 always +PCIE_BOT.PCIE_TRNTD0.PCIE_IMUX8_R_18 always +PCIE_BOT.PCIE_TRNTD1.PCIE_IMUX9_R_18 always +PCIE_BOT.PCIE_TRNTD2.PCIE_IMUX10_R_18 always +PCIE_BOT.PCIE_TRNTD3.PCIE_IMUX11_R_18 always +PCIE_BOT.PCIE_TRNTD4.PCIE_IMUX8_R_19 always +PCIE_BOT.PCIE_TRNTD5.PCIE_IMUX9_R_19 always +PCIE_BOT.PCIE_TRNTD6.PCIE_IMUX10_R_19 always +PCIE_BOT.PCIE_TRNTD7.PCIE_IMUX11_R_19 always +PCIE_BOT.PCIE_TRNTD42.PCIE_IMUX12_R_18 always +PCIE_BOT.PCIE_TRNTD43.PCIE_IMUX13_R_18 always +PCIE_BOT.PCIE_TRNTD44.PCIE_IMUX14_R_18 always +PCIE_BOT.PCIE_TRNTD45.PCIE_IMUX15_R_18 always +PCIE_BOT.PCIE_TRNTD46.PCIE_IMUX8_R_17 always +PCIE_BOT.PCIE_TRNTD47.PCIE_IMUX9_R_17 always +PCIE_BOT.PCIE_TRNTD48.PCIE_IMUX10_R_17 always +PCIE_BOT.PCIE_TRNTD49.PCIE_IMUX11_R_17 always +PCIE_BOT.PCIE_TRNTD50.PCIE_IMUX4_R_16 always +PCIE_BOT.PCIE_TRNTD51.PCIE_IMUX5_R_16 always +PCIE_BOT.PCIE_TRNTD52.PCIE_IMUX6_R_16 always +PCIE_BOT.PCIE_TRNTD53.PCIE_IMUX7_R_16 always +PCIE_BOT.PCIE_TRNTD54.PCIE_IMUX4_R_15 always +PCIE_BOT.PCIE_TRNTD55.PCIE_IMUX5_R_15 always +PCIE_BOT.PCIE_TRNTD56.PCIE_IMUX6_R_15 always +PCIE_BOT.PCIE_TRNTD57.PCIE_IMUX7_R_15 always +PCIE_BOT.PCIE_TRNTD58.PCIE_IMUX0_R_14 always +PCIE_BOT.PCIE_TRNTD59.PCIE_IMUX1_R_14 always +PCIE_BOT.PCIE_TRNTD60.PCIE_IMUX2_R_14 always +PCIE_BOT.PCIE_TRNTD61.PCIE_IMUX3_R_14 always +PCIE_BOT.PCIE_TRNTD62.PCIE_IMUX0_R_13 always +PCIE_BOT.PCIE_TRNTD63.PCIE_IMUX1_R_13 always +PCIE_BOT.PCIE_TRNTD64.PCIE_IMUX2_R_13 always +PCIE_BOT.PCIE_TRNTD65.PCIE_IMUX3_R_13 always +PCIE_BOT.PCIE_TRNTD66.PCIE_IMUX0_R_12 always +PCIE_BOT.PCIE_TRNTD67.PCIE_IMUX1_R_12 always +PCIE_BOT.PCIE_TRNTD68.PCIE_IMUX2_R_12 always +PCIE_BOT.PCIE_TRNTD69.PCIE_IMUX3_R_12 always +PCIE_BOT.PCIE_TRNTD70.PCIE_IMUX0_R_11 always +PCIE_BOT.PCIE_TRNTD71.PCIE_IMUX1_R_11 always +PCIE_BOT.PCIE_TRNTD72.PCIE_IMUX2_R_11 always +PCIE_BOT.PCIE_TRNTD73.PCIE_IMUX3_R_11 always +PCIE_BOT.PCIE_TRNTD74.PCIE_IMUX0_R_10 always +PCIE_BOT.PCIE_TRNTD75.PCIE_IMUX1_R_10 always +PCIE_BOT.PCIE_TRNTD76.PCIE_IMUX2_R_10 always +PCIE_BOT.PCIE_TRNTD77.PCIE_IMUX3_R_10 always +PCIE_BOT.PCIE_TRNTD78.PCIE_IMUX8_R_3 always +PCIE_BOT.PCIE_TRNTD79.PCIE_IMUX8_R_2 always +PCIE_BOT.PCIE_TRNTD80.PCIE_IMUX9_R_2 always +PCIE_BOT.PCIE_TRNTD81.PCIE_IMUX10_R_2 always +PCIE_BOT.PCIE_TRNTD82.PCIE_IMUX11_R_2 always +PCIE_BOT.PCIE_TRNTD83.PCIE_IMUX8_R_1 always +PCIE_BOT.PCIE_TRNTD84.PCIE_IMUX9_R_1 always +PCIE_BOT.PCIE_TRNTD85.PCIE_IMUX10_R_1 always +PCIE_BOT.PCIE_TRNTD86.PCIE_IMUX11_R_1 always +PCIE_BOT.PCIE_TRNTD87.PCIE_IMUX8_R_0 always +PCIE_BOT.PCIE_TRNTD88.PCIE_IMUX9_R_0 always +PCIE_BOT.PCIE_TRNTD89.PCIE_IMUX10_R_0 always +PCIE_BOT.PCIE_TRNTD90.PCIE_IMUX11_R_0 always +PCIE_BOT.PCIE_TRNTD91.PCIE_IMUX3_L_1 always +PCIE_BOT.PCIE_TRNTD92.PCIE_IMUX0_L_2 always +PCIE_BOT.PCIE_TRNTD93.PCIE_IMUX1_L_2 always +PCIE_BOT.PCIE_TRNTD94.PCIE_IMUX2_L_2 always +PCIE_BOT.PCIE_TRNTD95.PCIE_IMUX3_L_2 always +PCIE_BOT.PCIE_TRNTD96.PCIE_IMUX0_L_3 always +PCIE_BOT.PCIE_TRNTD97.PCIE_IMUX1_L_3 always +PCIE_BOT.PCIE_TRNTD98.PCIE_IMUX2_L_3 always +PCIE_BOT.PCIE_TRNTD99.PCIE_IMUX3_L_3 always +PCIE_BOT.PCIE_TRNTD100.PCIE_IMUX0_L_4 always +PCIE_BOT.PCIE_TRNTD101.PCIE_IMUX1_L_4 always +PCIE_BOT.PCIE_TRNTD102.PCIE_IMUX2_L_4 always +PCIE_BOT.PCIE_TRNTD103.PCIE_IMUX3_L_4 always +PCIE_BOT.PCIE_TRNTD104.PCIE_IMUX0_L_5 always +PCIE_BOT.PCIE_TRNTD105.PCIE_IMUX1_L_5 always +PCIE_BOT.PCIE_TRNTD106.PCIE_IMUX2_L_5 always +PCIE_BOT.PCIE_TRNTD107.PCIE_IMUX3_L_5 always +PCIE_BOT.PCIE_TRNTD108.PCIE_IMUX0_L_6 always +PCIE_BOT.PCIE_TRNTD109.PCIE_IMUX1_L_6 always +PCIE_BOT.PCIE_TRNTD110.PCIE_IMUX2_L_6 always +PCIE_BOT.PCIE_TRNTD111.PCIE_IMUX3_L_6 always +PCIE_BOT.PCIE_TRNTD112.PCIE_IMUX0_L_7 always +PCIE_BOT.PCIE_TRNTD113.PCIE_IMUX1_L_7 always +PCIE_BOT.PCIE_TRNTD114.PCIE_IMUX2_L_7 always +PCIE_BOT.PCIE_TRNTD115.PCIE_IMUX3_L_7 always +PCIE_BOT.PCIE_TRNTD116.PCIE_IMUX0_L_8 always +PCIE_BOT.PCIE_TRNTD117.PCIE_IMUX1_L_8 always +PCIE_BOT.PCIE_TRNTD118.PCIE_IMUX2_L_8 always +PCIE_BOT.PCIE_TRNTD119.PCIE_IMUX3_L_8 always +PCIE_BOT.PCIE_TRNTD120.PCIE_IMUX0_L_9 always +PCIE_BOT.PCIE_TRNTD121.PCIE_IMUX1_L_9 always +PCIE_BOT.PCIE_TRNTD122.PCIE_IMUX2_L_9 always +PCIE_BOT.PCIE_TRNTD123.PCIE_IMUX3_L_9 always +PCIE_BOT.PCIE_TRNTD124.PCIE_IMUX0_L_10 always +PCIE_BOT.PCIE_TRNTD125.PCIE_IMUX1_L_10 always +PCIE_BOT.PCIE_TRNTD126.PCIE_IMUX2_L_10 always +PCIE_BOT.PCIE_TRNTD127.PCIE_IMUX3_L_10 always +PCIE_BOT.PCIE_TRNTDLLPDATA0.PCIE_IMUX1_L_15 always +PCIE_BOT.PCIE_TRNTDLLPDATA1.PCIE_IMUX2_L_15 always +PCIE_BOT.PCIE_TRNTDLLPDATA2.PCIE_IMUX3_L_15 always +PCIE_BOT.PCIE_TRNTDLLPDATA3.PCIE_IMUX0_L_16 always +PCIE_BOT.PCIE_TRNTDLLPDATA4.PCIE_IMUX1_L_16 always +PCIE_BOT.PCIE_TRNTDLLPDATA5.PCIE_IMUX2_L_16 always +PCIE_BOT.PCIE_TRNTDLLPDATA6.PCIE_IMUX3_L_16 always +PCIE_BOT.PCIE_TRNTDLLPDATA7.PCIE_IMUX0_L_17 always +PCIE_BOT.PCIE_TRNTDLLPDATA8.PCIE_IMUX1_L_17 always +PCIE_BOT.PCIE_TRNTDLLPDATA9.PCIE_IMUX2_L_17 always +PCIE_BOT.PCIE_TRNTDLLPDATA10.PCIE_IMUX3_L_17 always +PCIE_BOT.PCIE_TRNTDLLPDATA11.PCIE_IMUX0_L_18 always +PCIE_BOT.PCIE_TRNTDLLPDATA12.PCIE_IMUX1_L_18 always +PCIE_BOT.PCIE_TRNTDLLPDATA13.PCIE_IMUX2_L_18 always +PCIE_BOT.PCIE_TRNTDLLPDATA14.PCIE_IMUX3_L_18 always +PCIE_BOT.PCIE_TRNTDLLPDATA15.PCIE_IMUX0_L_19 always +PCIE_BOT.PCIE_TRNTDLLPDATA16.PCIE_IMUX1_L_19 always +PCIE_BOT.PCIE_TRNTDLLPDATA17.PCIE_IMUX2_L_19 always +PCIE_BOT.PCIE_TRNTDLLPDATA18.PCIE_IMUX3_L_19 always +PCIE_BOT.PCIE_TRNTREM0.PCIE_IMUX0_L_11 always +PCIE_BOT.PCIE_TRNTREM1.PCIE_IMUX1_L_11 always +PCIE_BOT.PCIE_USERCLK2.PCIE_CLK1_R_12 always diff --git a/kintex7/ppips_pcie_int_interface_l.db b/kintex7/ppips_pcie_int_interface_l.db new file mode 100644 index 0000000..d0f9c55 --- /dev/null +++ b/kintex7/ppips_pcie_int_interface_l.db @@ -0,0 +1,120 @@ +PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L0.INT_INTERFACE_LOGIC_OUTS_L_B0 always +PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L1.INT_INTERFACE_LOGIC_OUTS_L_B1 always +PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L2.INT_INTERFACE_LOGIC_OUTS_L_B2 always +PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L3.INT_INTERFACE_LOGIC_OUTS_L_B3 always +PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L4.INT_INTERFACE_LOGIC_OUTS_L_B4 always +PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L5.INT_INTERFACE_LOGIC_OUTS_L_B5 always +PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L6.INT_INTERFACE_LOGIC_OUTS_L_B6 always +PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L7.INT_INTERFACE_LOGIC_OUTS_L_B7 always +PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L8.INT_INTERFACE_LOGIC_OUTS_L_B8 always +PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L9.INT_INTERFACE_LOGIC_OUTS_L_B9 always +PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L10.INT_INTERFACE_LOGIC_OUTS_L_B10 always +PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L11.INT_INTERFACE_LOGIC_OUTS_L_B11 always +PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L12.INT_INTERFACE_LOGIC_OUTS_L_B12 always +PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L13.INT_INTERFACE_LOGIC_OUTS_L_B13 always +PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L14.INT_INTERFACE_LOGIC_OUTS_L_B14 always +PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L15.INT_INTERFACE_LOGIC_OUTS_L_B15 always +PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L16.INT_INTERFACE_LOGIC_OUTS_L_B16 always +PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L17.INT_INTERFACE_LOGIC_OUTS_L_B17 always +PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L18.INT_INTERFACE_LOGIC_OUTS_L_B18 always +PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L19.INT_INTERFACE_LOGIC_OUTS_L_B19 always +PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L20.INT_INTERFACE_LOGIC_OUTS_L_B20 always +PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L21.INT_INTERFACE_LOGIC_OUTS_L_B21 always +PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L22.INT_INTERFACE_LOGIC_OUTS_L_B22 always +PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L23.INT_INTERFACE_LOGIC_OUTS_L_B23 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT0.PCIE_INT_INTERFACE_IMUX_L_DELAY0 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT0.PCIE_INT_INTERFACE_IMUX_L0 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT1.PCIE_INT_INTERFACE_IMUX_L_DELAY1 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT1.PCIE_INT_INTERFACE_IMUX_L1 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT2.PCIE_INT_INTERFACE_IMUX_L_DELAY2 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT2.PCIE_INT_INTERFACE_IMUX_L2 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT3.PCIE_INT_INTERFACE_IMUX_L_DELAY3 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT3.PCIE_INT_INTERFACE_IMUX_L3 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT4.PCIE_INT_INTERFACE_IMUX_L_DELAY4 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT4.PCIE_INT_INTERFACE_IMUX_L4 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT5.PCIE_INT_INTERFACE_IMUX_L_DELAY5 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT5.PCIE_INT_INTERFACE_IMUX_L5 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT6.PCIE_INT_INTERFACE_IMUX_L_DELAY6 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT6.PCIE_INT_INTERFACE_IMUX_L6 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT7.PCIE_INT_INTERFACE_IMUX_L_DELAY7 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT7.PCIE_INT_INTERFACE_IMUX_L7 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT8.PCIE_INT_INTERFACE_IMUX_L_DELAY8 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT8.PCIE_INT_INTERFACE_IMUX_L8 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT9.PCIE_INT_INTERFACE_IMUX_L_DELAY9 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT9.PCIE_INT_INTERFACE_IMUX_L9 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT10.PCIE_INT_INTERFACE_IMUX_L_DELAY10 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT10.PCIE_INT_INTERFACE_IMUX_L10 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT11.PCIE_INT_INTERFACE_IMUX_L_DELAY11 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT11.PCIE_INT_INTERFACE_IMUX_L11 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT12.PCIE_INT_INTERFACE_IMUX_L_DELAY12 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT12.PCIE_INT_INTERFACE_IMUX_L12 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT13.PCIE_INT_INTERFACE_IMUX_L_DELAY13 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT13.PCIE_INT_INTERFACE_IMUX_L13 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT14.PCIE_INT_INTERFACE_IMUX_L_DELAY14 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT14.PCIE_INT_INTERFACE_IMUX_L14 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT15.PCIE_INT_INTERFACE_IMUX_L_DELAY15 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT15.PCIE_INT_INTERFACE_IMUX_L15 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT16.PCIE_INT_INTERFACE_IMUX_L_DELAY16 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT16.PCIE_INT_INTERFACE_IMUX_L16 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT17.PCIE_INT_INTERFACE_IMUX_L_DELAY17 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT17.PCIE_INT_INTERFACE_IMUX_L17 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT18.PCIE_INT_INTERFACE_IMUX_L_DELAY18 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT18.PCIE_INT_INTERFACE_IMUX_L18 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT19.PCIE_INT_INTERFACE_IMUX_L_DELAY19 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT19.PCIE_INT_INTERFACE_IMUX_L19 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT20.PCIE_INT_INTERFACE_IMUX_L_DELAY20 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT20.PCIE_INT_INTERFACE_IMUX_L20 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT21.PCIE_INT_INTERFACE_IMUX_L_DELAY21 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT21.PCIE_INT_INTERFACE_IMUX_L21 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT22.PCIE_INT_INTERFACE_IMUX_L_DELAY22 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT22.PCIE_INT_INTERFACE_IMUX_L22 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT23.PCIE_INT_INTERFACE_IMUX_L_DELAY23 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT23.PCIE_INT_INTERFACE_IMUX_L23 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT24.PCIE_INT_INTERFACE_IMUX_L_DELAY24 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT24.PCIE_INT_INTERFACE_IMUX_L24 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT25.PCIE_INT_INTERFACE_IMUX_L_DELAY25 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT25.PCIE_INT_INTERFACE_IMUX_L25 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT26.PCIE_INT_INTERFACE_IMUX_L_DELAY26 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT26.PCIE_INT_INTERFACE_IMUX_L26 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT27.PCIE_INT_INTERFACE_IMUX_L_DELAY27 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT27.PCIE_INT_INTERFACE_IMUX_L27 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT28.PCIE_INT_INTERFACE_IMUX_L_DELAY28 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT28.PCIE_INT_INTERFACE_IMUX_L28 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT29.PCIE_INT_INTERFACE_IMUX_L_DELAY29 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT29.PCIE_INT_INTERFACE_IMUX_L29 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT30.PCIE_INT_INTERFACE_IMUX_L_DELAY30 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT30.PCIE_INT_INTERFACE_IMUX_L30 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT31.PCIE_INT_INTERFACE_IMUX_L_DELAY31 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT31.PCIE_INT_INTERFACE_IMUX_L31 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT32.PCIE_INT_INTERFACE_IMUX_L_DELAY32 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT32.PCIE_INT_INTERFACE_IMUX_L32 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT33.PCIE_INT_INTERFACE_IMUX_L_DELAY33 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT33.PCIE_INT_INTERFACE_IMUX_L33 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT34.PCIE_INT_INTERFACE_IMUX_L_DELAY34 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT34.PCIE_INT_INTERFACE_IMUX_L34 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT35.PCIE_INT_INTERFACE_IMUX_L_DELAY35 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT35.PCIE_INT_INTERFACE_IMUX_L35 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT36.PCIE_INT_INTERFACE_IMUX_L_DELAY36 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT36.PCIE_INT_INTERFACE_IMUX_L36 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT37.PCIE_INT_INTERFACE_IMUX_L_DELAY37 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT37.PCIE_INT_INTERFACE_IMUX_L37 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT38.PCIE_INT_INTERFACE_IMUX_L_DELAY38 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT38.PCIE_INT_INTERFACE_IMUX_L38 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT39.PCIE_INT_INTERFACE_IMUX_L_DELAY39 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT39.PCIE_INT_INTERFACE_IMUX_L39 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT40.PCIE_INT_INTERFACE_IMUX_L_DELAY40 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT40.PCIE_INT_INTERFACE_IMUX_L40 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT41.PCIE_INT_INTERFACE_IMUX_L_DELAY41 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT41.PCIE_INT_INTERFACE_IMUX_L41 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT42.PCIE_INT_INTERFACE_IMUX_L_DELAY42 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT42.PCIE_INT_INTERFACE_IMUX_L42 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT43.PCIE_INT_INTERFACE_IMUX_L_DELAY43 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT43.PCIE_INT_INTERFACE_IMUX_L43 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT44.PCIE_INT_INTERFACE_IMUX_L_DELAY44 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT44.PCIE_INT_INTERFACE_IMUX_L44 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT45.PCIE_INT_INTERFACE_IMUX_L_DELAY45 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT45.PCIE_INT_INTERFACE_IMUX_L45 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT46.PCIE_INT_INTERFACE_IMUX_L_DELAY46 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT46.PCIE_INT_INTERFACE_IMUX_L46 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT47.PCIE_INT_INTERFACE_IMUX_L_DELAY47 always +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT47.PCIE_INT_INTERFACE_IMUX_L47 always diff --git a/kintex7/ppips_pcie_int_interface_r.db b/kintex7/ppips_pcie_int_interface_r.db new file mode 100644 index 0000000..013f200 --- /dev/null +++ b/kintex7/ppips_pcie_int_interface_r.db @@ -0,0 +1,120 @@ +PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS0.INT_INTERFACE_LOGIC_OUTS_B0 always +PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS1.INT_INTERFACE_LOGIC_OUTS_B1 always +PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS2.INT_INTERFACE_LOGIC_OUTS_B2 always +PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS3.INT_INTERFACE_LOGIC_OUTS_B3 always +PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS4.INT_INTERFACE_LOGIC_OUTS_B4 always +PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS5.INT_INTERFACE_LOGIC_OUTS_B5 always +PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS6.INT_INTERFACE_LOGIC_OUTS_B6 always +PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS7.INT_INTERFACE_LOGIC_OUTS_B7 always +PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS8.INT_INTERFACE_LOGIC_OUTS_B8 always +PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS9.INT_INTERFACE_LOGIC_OUTS_B9 always +PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS10.INT_INTERFACE_LOGIC_OUTS_B10 always +PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS11.INT_INTERFACE_LOGIC_OUTS_B11 always +PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS12.INT_INTERFACE_LOGIC_OUTS_B12 always +PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS13.INT_INTERFACE_LOGIC_OUTS_B13 always +PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS14.INT_INTERFACE_LOGIC_OUTS_B14 always +PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS15.INT_INTERFACE_LOGIC_OUTS_B15 always +PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS16.INT_INTERFACE_LOGIC_OUTS_B16 always +PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS17.INT_INTERFACE_LOGIC_OUTS_B17 always +PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS18.INT_INTERFACE_LOGIC_OUTS_B18 always +PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS19.INT_INTERFACE_LOGIC_OUTS_B19 always +PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS20.INT_INTERFACE_LOGIC_OUTS_B20 always +PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS21.INT_INTERFACE_LOGIC_OUTS_B21 always +PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS22.INT_INTERFACE_LOGIC_OUTS_B22 always +PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS23.INT_INTERFACE_LOGIC_OUTS_B23 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT0.PCIE_INT_INTERFACE_IMUX_DELAY0 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT0.PCIE_INT_INTERFACE_IMUX0 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT1.PCIE_INT_INTERFACE_IMUX_DELAY1 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT1.PCIE_INT_INTERFACE_IMUX1 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT2.PCIE_INT_INTERFACE_IMUX_DELAY2 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT2.PCIE_INT_INTERFACE_IMUX2 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT3.PCIE_INT_INTERFACE_IMUX_DELAY3 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT3.PCIE_INT_INTERFACE_IMUX3 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT4.PCIE_INT_INTERFACE_IMUX_DELAY4 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT4.PCIE_INT_INTERFACE_IMUX4 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT5.PCIE_INT_INTERFACE_IMUX_DELAY5 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT5.PCIE_INT_INTERFACE_IMUX5 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT6.PCIE_INT_INTERFACE_IMUX_DELAY6 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT6.PCIE_INT_INTERFACE_IMUX6 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT7.PCIE_INT_INTERFACE_IMUX_DELAY7 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT7.PCIE_INT_INTERFACE_IMUX7 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT8.PCIE_INT_INTERFACE_IMUX_DELAY8 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT8.PCIE_INT_INTERFACE_IMUX8 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT9.PCIE_INT_INTERFACE_IMUX_DELAY9 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT9.PCIE_INT_INTERFACE_IMUX9 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT10.PCIE_INT_INTERFACE_IMUX_DELAY10 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT10.PCIE_INT_INTERFACE_IMUX10 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT11.PCIE_INT_INTERFACE_IMUX_DELAY11 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT11.PCIE_INT_INTERFACE_IMUX11 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT12.PCIE_INT_INTERFACE_IMUX_DELAY12 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT12.PCIE_INT_INTERFACE_IMUX12 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT13.PCIE_INT_INTERFACE_IMUX_DELAY13 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT13.PCIE_INT_INTERFACE_IMUX13 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT14.PCIE_INT_INTERFACE_IMUX_DELAY14 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT14.PCIE_INT_INTERFACE_IMUX14 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT15.PCIE_INT_INTERFACE_IMUX_DELAY15 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT15.PCIE_INT_INTERFACE_IMUX15 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT16.PCIE_INT_INTERFACE_IMUX_DELAY16 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT16.PCIE_INT_INTERFACE_IMUX16 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT17.PCIE_INT_INTERFACE_IMUX_DELAY17 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT17.PCIE_INT_INTERFACE_IMUX17 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT18.PCIE_INT_INTERFACE_IMUX_DELAY18 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT18.PCIE_INT_INTERFACE_IMUX18 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT19.PCIE_INT_INTERFACE_IMUX_DELAY19 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT19.PCIE_INT_INTERFACE_IMUX19 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT20.PCIE_INT_INTERFACE_IMUX_DELAY20 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT20.PCIE_INT_INTERFACE_IMUX20 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT21.PCIE_INT_INTERFACE_IMUX_DELAY21 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT21.PCIE_INT_INTERFACE_IMUX21 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT22.PCIE_INT_INTERFACE_IMUX_DELAY22 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT22.PCIE_INT_INTERFACE_IMUX22 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT23.PCIE_INT_INTERFACE_IMUX_DELAY23 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT23.PCIE_INT_INTERFACE_IMUX23 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT24.PCIE_INT_INTERFACE_IMUX_DELAY24 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT24.PCIE_INT_INTERFACE_IMUX24 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT25.PCIE_INT_INTERFACE_IMUX_DELAY25 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT25.PCIE_INT_INTERFACE_IMUX25 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT26.PCIE_INT_INTERFACE_IMUX_DELAY26 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT26.PCIE_INT_INTERFACE_IMUX26 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT27.PCIE_INT_INTERFACE_IMUX_DELAY27 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT27.PCIE_INT_INTERFACE_IMUX27 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT28.PCIE_INT_INTERFACE_IMUX_DELAY28 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT28.PCIE_INT_INTERFACE_IMUX28 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT29.PCIE_INT_INTERFACE_IMUX_DELAY29 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT29.PCIE_INT_INTERFACE_IMUX29 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT30.PCIE_INT_INTERFACE_IMUX_DELAY30 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT30.PCIE_INT_INTERFACE_IMUX30 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT31.PCIE_INT_INTERFACE_IMUX_DELAY31 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT31.PCIE_INT_INTERFACE_IMUX31 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT32.PCIE_INT_INTERFACE_IMUX_DELAY32 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT32.PCIE_INT_INTERFACE_IMUX32 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT33.PCIE_INT_INTERFACE_IMUX_DELAY33 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT33.PCIE_INT_INTERFACE_IMUX33 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT34.PCIE_INT_INTERFACE_IMUX_DELAY34 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT34.PCIE_INT_INTERFACE_IMUX34 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT35.PCIE_INT_INTERFACE_IMUX_DELAY35 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT35.PCIE_INT_INTERFACE_IMUX35 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT36.PCIE_INT_INTERFACE_IMUX_DELAY36 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT36.PCIE_INT_INTERFACE_IMUX36 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT37.PCIE_INT_INTERFACE_IMUX_DELAY37 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT37.PCIE_INT_INTERFACE_IMUX37 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT38.PCIE_INT_INTERFACE_IMUX_DELAY38 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT38.PCIE_INT_INTERFACE_IMUX38 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT39.PCIE_INT_INTERFACE_IMUX_DELAY39 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT39.PCIE_INT_INTERFACE_IMUX39 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT40.PCIE_INT_INTERFACE_IMUX_DELAY40 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT40.PCIE_INT_INTERFACE_IMUX40 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT41.PCIE_INT_INTERFACE_IMUX_DELAY41 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT41.PCIE_INT_INTERFACE_IMUX41 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT42.PCIE_INT_INTERFACE_IMUX_DELAY42 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT42.PCIE_INT_INTERFACE_IMUX42 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT43.PCIE_INT_INTERFACE_IMUX_DELAY43 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT43.PCIE_INT_INTERFACE_IMUX43 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT44.PCIE_INT_INTERFACE_IMUX_DELAY44 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT44.PCIE_INT_INTERFACE_IMUX44 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT45.PCIE_INT_INTERFACE_IMUX_DELAY45 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT45.PCIE_INT_INTERFACE_IMUX45 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT46.PCIE_INT_INTERFACE_IMUX_DELAY46 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT46.PCIE_INT_INTERFACE_IMUX46 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT47.PCIE_INT_INTERFACE_IMUX_DELAY47 always +PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT47.PCIE_INT_INTERFACE_IMUX47 always diff --git a/kintex7/ppips_pcie_top.db b/kintex7/ppips_pcie_top.db new file mode 100644 index 0000000..2870e76 --- /dev/null +++ b/kintex7/ppips_pcie_top.db @@ -0,0 +1,441 @@ +PCIE_TOP.PCIE_LOGIC_OUTS_B0_L_0.PCIE_TOP_TRNRD59 always +PCIE_TOP.PCIE_LOGIC_OUTS_B0_L_1.PCIE_TOP_TRNRD63 always +PCIE_TOP.PCIE_LOGIC_OUTS_B0_L_2.PCIE_TOP_TRNRD67 always +PCIE_TOP.PCIE_LOGIC_OUTS_B0_L_3.PCIE_TOP_TRNRD71 always +PCIE_TOP.PCIE_LOGIC_OUTS_B0_L_4.PCIE_TOP_TRNRD75 always +PCIE_TOP.PCIE_LOGIC_OUTS_B0_R_0.PCIE_TOP_MIMRXWDATA20 always +PCIE_TOP.PCIE_LOGIC_OUTS_B0_R_1.PCIE_TOP_MIMRXWDATA24 always +PCIE_TOP.PCIE_LOGIC_OUTS_B0_R_2.PCIE_TOP_MIMRXWADDR2 always +PCIE_TOP.PCIE_LOGIC_OUTS_B0_R_3.PCIE_TOP_TRNRD83 always +PCIE_TOP.PCIE_LOGIC_OUTS_B0_R_4.PCIE_TOP_TRNRD79 always +PCIE_TOP.PCIE_LOGIC_OUTS_B1_L_0.PCIE_TOP_TRNRD60 always +PCIE_TOP.PCIE_LOGIC_OUTS_B1_L_1.PCIE_TOP_TRNRD64 always +PCIE_TOP.PCIE_LOGIC_OUTS_B1_L_2.PCIE_TOP_TRNRD68 always +PCIE_TOP.PCIE_LOGIC_OUTS_B1_L_3.PCIE_TOP_TRNRD72 always +PCIE_TOP.PCIE_LOGIC_OUTS_B1_L_4.PCIE_TOP_TRNRD76 always +PCIE_TOP.PCIE_LOGIC_OUTS_B1_R_0.PCIE_TOP_MIMRXWADDR12 always +PCIE_TOP.PCIE_LOGIC_OUTS_B1_R_1.PCIE_TOP_TRNRD91 always +PCIE_TOP.PCIE_LOGIC_OUTS_B1_R_2.PCIE_TOP_MIMRXWDATA32 always +PCIE_TOP.PCIE_LOGIC_OUTS_B1_R_3.PCIE_TOP_TRNRD84 always +PCIE_TOP.PCIE_LOGIC_OUTS_B1_R_4.PCIE_TOP_TRNTDSTRDY3 always +PCIE_TOP.PCIE_LOGIC_OUTS_B2_L_0.PCIE_TOP_TRNRD61 always +PCIE_TOP.PCIE_LOGIC_OUTS_B2_L_1.PCIE_TOP_TRNRD65 always +PCIE_TOP.PCIE_LOGIC_OUTS_B2_L_2.PCIE_TOP_TRNRD69 always +PCIE_TOP.PCIE_LOGIC_OUTS_B2_L_3.PCIE_TOP_TRNRD73 always +PCIE_TOP.PCIE_LOGIC_OUTS_B2_L_4.PCIE_TOP_TRNRD77 always +PCIE_TOP.PCIE_LOGIC_OUTS_B2_R_0.PCIE_TOP_TRNRD95 always +PCIE_TOP.PCIE_LOGIC_OUTS_B2_R_1.PCIE_TOP_MIMRXWDATA12 always +PCIE_TOP.PCIE_LOGIC_OUTS_B2_R_2.PCIE_TOP_TRNRD87 always +PCIE_TOP.PCIE_LOGIC_OUTS_B2_R_3.PCIE_TOP_TRNRD85 always +PCIE_TOP.PCIE_LOGIC_OUTS_B2_R_4.PCIE_TOP_TRNRD80 always +PCIE_TOP.PCIE_LOGIC_OUTS_B3_L_0.PCIE_TOP_TRNRD62 always +PCIE_TOP.PCIE_LOGIC_OUTS_B3_L_1.PCIE_TOP_TRNRD66 always +PCIE_TOP.PCIE_LOGIC_OUTS_B3_L_2.PCIE_TOP_TRNRD70 always +PCIE_TOP.PCIE_LOGIC_OUTS_B3_L_3.PCIE_TOP_TRNRD74 always +PCIE_TOP.PCIE_LOGIC_OUTS_B3_L_4.PCIE_TOP_TRNRD78 always +PCIE_TOP.PCIE_LOGIC_OUTS_B3_R_0.PCIE_TOP_MIMRXRADDR10 always +PCIE_TOP.PCIE_LOGIC_OUTS_B3_R_1.PCIE_TOP_TRNRD92 always +PCIE_TOP.PCIE_LOGIC_OUTS_B3_R_2.PCIE_TOP_TRNRD88 always +PCIE_TOP.PCIE_LOGIC_OUTS_B3_R_3.PCIE_TOP_MIMRXWDATA9 always +PCIE_TOP.PCIE_LOGIC_OUTS_B3_R_4.PCIE_TOP_TRNRD81 always +PCIE_TOP.PCIE_LOGIC_OUTS_B4_L_0.PCIE_TOP_TRNRDLLPDATA32 always +PCIE_TOP.PCIE_LOGIC_OUTS_B4_L_1.PCIE_TOP_TRNRDLLPDATA36 always +PCIE_TOP.PCIE_LOGIC_OUTS_B4_L_2.PCIE_TOP_TRNRDLLPDATA40 always +PCIE_TOP.PCIE_LOGIC_OUTS_B4_L_3.PCIE_TOP_TRNRDLLPDATA44 always +PCIE_TOP.PCIE_LOGIC_OUTS_B4_L_4.PCIE_TOP_TRNRDLLPDATA48 always +PCIE_TOP.PCIE_LOGIC_OUTS_B4_R_0.PCIE_TOP_TRNRD96 always +PCIE_TOP.PCIE_LOGIC_OUTS_B4_R_1.PCIE_TOP_TRNRD93 always +PCIE_TOP.PCIE_LOGIC_OUTS_B4_R_2.PCIE_TOP_TRNRD89 always +PCIE_TOP.PCIE_LOGIC_OUTS_B4_R_3.PCIE_TOP_TRNRD86 always +PCIE_TOP.PCIE_LOGIC_OUTS_B4_R_4.PCIE_TOP_TRNRD82 always +PCIE_TOP.PCIE_LOGIC_OUTS_B5_L_0.PCIE_TOP_TRNRDLLPDATA33 always +PCIE_TOP.PCIE_LOGIC_OUTS_B5_L_1.PCIE_TOP_TRNRDLLPDATA37 always +PCIE_TOP.PCIE_LOGIC_OUTS_B5_L_2.PCIE_TOP_TRNRDLLPDATA41 always +PCIE_TOP.PCIE_LOGIC_OUTS_B5_L_3.PCIE_TOP_TRNRDLLPDATA45 always +PCIE_TOP.PCIE_LOGIC_OUTS_B5_L_4.PCIE_TOP_TRNRDLLPDATA49 always +PCIE_TOP.PCIE_LOGIC_OUTS_B5_R_0.PCIE_TOP_TRNRD97 always +PCIE_TOP.PCIE_LOGIC_OUTS_B5_R_1.PCIE_TOP_MIMRXWDATA49 always +PCIE_TOP.PCIE_LOGIC_OUTS_B5_R_2.PCIE_TOP_MIMRXRADDR4 always +PCIE_TOP.PCIE_LOGIC_OUTS_B5_R_3.PCIE_TOP_TRNRDLLPDATA56 always +PCIE_TOP.PCIE_LOGIC_OUTS_B5_R_4.PCIE_TOP_TRNRDLLPDATA52 always +PCIE_TOP.PCIE_LOGIC_OUTS_B6_L_0.PCIE_TOP_PIPETXMARGIN2 always +PCIE_TOP.PCIE_LOGIC_OUTS_B6_L_1.PCIE_TOP_TRNRDLLPDATA38 always +PCIE_TOP.PCIE_LOGIC_OUTS_B6_L_2.PCIE_TOP_TRNRDLLPDATA42 always +PCIE_TOP.PCIE_LOGIC_OUTS_B6_L_3.PCIE_TOP_TRNRDLLPDATA46 always +PCIE_TOP.PCIE_LOGIC_OUTS_B6_L_4.PCIE_TOP_TRNRDLLPDATA50 always +PCIE_TOP.PCIE_LOGIC_OUTS_B6_R_0.PCIE_TOP_TRNRD98 always +PCIE_TOP.PCIE_LOGIC_OUTS_B6_R_1.PCIE_TOP_TRNRD94 always +PCIE_TOP.PCIE_LOGIC_OUTS_B6_R_2.PCIE_TOP_TRNRD90 always +PCIE_TOP.PCIE_LOGIC_OUTS_B6_R_3.PCIE_TOP_TRNRDLLPDATA57 always +PCIE_TOP.PCIE_LOGIC_OUTS_B6_R_4.PCIE_TOP_TRNRDLLPDATA53 always +PCIE_TOP.PCIE_LOGIC_OUTS_B7_L_0.PCIE_TOP_TRNRDLLPDATA34 always +PCIE_TOP.PCIE_LOGIC_OUTS_B7_L_1.PCIE_TOP_TRNRDLLPDATA39 always +PCIE_TOP.PCIE_LOGIC_OUTS_B7_L_2.PCIE_TOP_TRNRDLLPDATA43 always +PCIE_TOP.PCIE_LOGIC_OUTS_B7_L_3.PCIE_TOP_TRNRDLLPDATA47 always +PCIE_TOP.PCIE_LOGIC_OUTS_B7_L_4.PCIE_TOP_TRNRDLLPDATA51 always +PCIE_TOP.PCIE_LOGIC_OUTS_B7_R_0.PCIE_TOP_PL2SUSPENDOK always +PCIE_TOP.PCIE_LOGIC_OUTS_B7_R_1.PCIE_TOP_MIMRXWDATA51 always +PCIE_TOP.PCIE_LOGIC_OUTS_B7_R_2.PCIE_TOP_TRNRDLLPDATA60 always +PCIE_TOP.PCIE_LOGIC_OUTS_B7_R_3.PCIE_TOP_TRNRDLLPDATA58 always +PCIE_TOP.PCIE_LOGIC_OUTS_B7_R_4.PCIE_TOP_TRNRDLLPDATA54 always +PCIE_TOP.PCIE_LOGIC_OUTS_B8_L_0.PCIE_TOP_TRNRDLLPDATA35 always +PCIE_TOP.PCIE_LOGIC_OUTS_B8_L_1.PCIE_TOP_CFGPMRCVENTERL23N always +PCIE_TOP.PCIE_LOGIC_OUTS_B8_L_2.PCIE_TOP_CFGPMCSRPMEEN always +PCIE_TOP.PCIE_LOGIC_OUTS_B8_L_3.PCIE_TOP_CFGTRANSACTIONADDR0 always +PCIE_TOP.PCIE_LOGIC_OUTS_B8_L_4.PCIE_TOP_CFGTRANSACTIONADDR4 always +PCIE_TOP.PCIE_LOGIC_OUTS_B8_R_0.PCIE_TOP_MIMRXRADDR9 always +PCIE_TOP.PCIE_LOGIC_OUTS_B8_R_1.PCIE_TOP_MIMRXWDATA8 always +PCIE_TOP.PCIE_LOGIC_OUTS_B8_R_2.PCIE_TOP_TRNRDLLPDATA61 always +PCIE_TOP.PCIE_LOGIC_OUTS_B8_R_3.PCIE_TOP_MIMRXWDATA19 always +PCIE_TOP.PCIE_LOGIC_OUTS_B8_R_4.PCIE_TOP_MIMRXWDATA29 always +PCIE_TOP.PCIE_LOGIC_OUTS_B9_L_0.PCIE_TOP_CFGPCIELINKSTATE1 always +PCIE_TOP.PCIE_LOGIC_OUTS_B9_L_1.PCIE_TOP_CFGPMRCVREQACKN always +PCIE_TOP.PCIE_LOGIC_OUTS_B9_L_2.PCIE_TOP_CFGPMCSRPMESTATUS always +PCIE_TOP.PCIE_LOGIC_OUTS_B9_L_3.PCIE_TOP_CFGTRANSACTIONADDR1 always +PCIE_TOP.PCIE_LOGIC_OUTS_B9_L_4.PCIE_TOP_CFGTRANSACTIONADDR5 always +PCIE_TOP.PCIE_LOGIC_OUTS_B9_R_0.PCIE_TOP_MIMRXWDATA4 always +PCIE_TOP.PCIE_LOGIC_OUTS_B9_R_1.PCIE_TOP_MIMRXWADDR5 always +PCIE_TOP.PCIE_LOGIC_OUTS_B9_R_2.PCIE_TOP_MIMRXWDATA17 always +PCIE_TOP.PCIE_LOGIC_OUTS_B9_R_3.PCIE_TOP_TRNRDLLPDATA59 always +PCIE_TOP.PCIE_LOGIC_OUTS_B9_R_4.PCIE_TOP_MIMRXWDATA13 always +PCIE_TOP.PCIE_LOGIC_OUTS_B10_L_0.PCIE_TOP_CFGPCIELINKSTATE2 always +PCIE_TOP.PCIE_LOGIC_OUTS_B10_L_1.PCIE_TOP_CFGPMCSRPOWERSTATE0 always +PCIE_TOP.PCIE_LOGIC_OUTS_B10_L_2.PCIE_TOP_CFGTRANSACTION always +PCIE_TOP.PCIE_LOGIC_OUTS_B10_L_3.PCIE_TOP_CFGTRANSACTIONADDR2 always +PCIE_TOP.PCIE_LOGIC_OUTS_B10_L_4.PCIE_TOP_CFGTRANSACTIONADDR6 always +PCIE_TOP.PCIE_LOGIC_OUTS_B10_R_0.PCIE_TOP_MIMRXRADDR11 always +PCIE_TOP.PCIE_LOGIC_OUTS_B10_R_1.PCIE_TOP_TRNRDLLPSRCRDY0 always +PCIE_TOP.PCIE_LOGIC_OUTS_B10_R_2.PCIE_TOP_TRNRDLLPDATA62 always +PCIE_TOP.PCIE_LOGIC_OUTS_B10_R_3.PCIE_TOP_MIMRXWDATA25 always +PCIE_TOP.PCIE_LOGIC_OUTS_B10_R_4.PCIE_TOP_MIMRXWDATA15 always +PCIE_TOP.PCIE_LOGIC_OUTS_B11_L_0.PCIE_TOP_CFGPMRCVASREQL1N always +PCIE_TOP.PCIE_LOGIC_OUTS_B11_L_1.PCIE_TOP_CFGPMCSRPOWERSTATE1 always +PCIE_TOP.PCIE_LOGIC_OUTS_B11_L_2.PCIE_TOP_CFGTRANSACTIONTYPE always +PCIE_TOP.PCIE_LOGIC_OUTS_B11_L_3.PCIE_TOP_CFGTRANSACTIONADDR3 always +PCIE_TOP.PCIE_LOGIC_OUTS_B11_L_4.PCIE_TOP_CFGCOMMANDIOENABLE always +PCIE_TOP.PCIE_LOGIC_OUTS_B11_R_0.PCIE_TOP_MIMRXWDATA0 always +PCIE_TOP.PCIE_LOGIC_OUTS_B11_R_1.PCIE_TOP_MIMRXRADDR1 always +PCIE_TOP.PCIE_LOGIC_OUTS_B11_R_2.PCIE_TOP_TRNRDLLPDATA63 always +PCIE_TOP.PCIE_LOGIC_OUTS_B11_R_3.PCIE_TOP_CFGMGMTDO20 always +PCIE_TOP.PCIE_LOGIC_OUTS_B11_R_4.PCIE_TOP_MIMRXWDATA35 always +PCIE_TOP.PCIE_LOGIC_OUTS_B12_L_0.PCIE_TOP_CFGPMRCVENTERL1N always +PCIE_TOP.PCIE_LOGIC_OUTS_B12_L_1.PCIE_TOP_CFGLINKCONTROLCOMMONCLOCK always +PCIE_TOP.PCIE_LOGIC_OUTS_B12_L_2.PCIE_TOP_CFGLINKCONTROLBANDWIDTHINTEN always +PCIE_TOP.PCIE_LOGIC_OUTS_B12_L_3.PCIE_TOP_CFGDEVCONTROL2CPLTIMEOUTVAL2 always +PCIE_TOP.PCIE_LOGIC_OUTS_B12_L_4.PCIE_TOP_CFGDEVCONTROL2ATOMICREQUESTEREN always +PCIE_TOP.PCIE_LOGIC_OUTS_B12_R_0.PCIE_TOP_PL2RECOVERY always +PCIE_TOP.PCIE_LOGIC_OUTS_B12_R_1.PCIE_TOP_MIMRXREN always +PCIE_TOP.PCIE_LOGIC_OUTS_B12_R_2.PCIE_TOP_MIMRXRADDR2 always +PCIE_TOP.PCIE_LOGIC_OUTS_B12_R_3.PCIE_TOP_CFGMGMTDO21 always +PCIE_TOP.PCIE_LOGIC_OUTS_B12_R_4.PCIE_TOP_TRNRDLLPDATA55 always +PCIE_TOP.PCIE_LOGIC_OUTS_B13_L_0.PCIE_TOP_CFGLINKCONTROLASPMCONTROL1 always +PCIE_TOP.PCIE_LOGIC_OUTS_B13_L_1.PCIE_TOP_CFGLINKCONTROLEXTENDEDSYNC always +PCIE_TOP.PCIE_LOGIC_OUTS_B13_L_2.PCIE_TOP_CFGLINKCONTROLAUTOBANDWIDTHINTEN always +PCIE_TOP.PCIE_LOGIC_OUTS_B13_L_3.PCIE_TOP_CFGDEVCONTROL2CPLTIMEOUTVAL3 always +PCIE_TOP.PCIE_LOGIC_OUTS_B13_L_4.PCIE_TOP_CFGDEVCONTROL2ATOMICEGRESSBLOCK always +PCIE_TOP.PCIE_LOGIC_OUTS_B13_R_0.PCIE_TOP_MIMRXWDATA1 always +PCIE_TOP.PCIE_LOGIC_OUTS_B13_R_1.PCIE_TOP_MIMRXWDATA26 always +PCIE_TOP.PCIE_LOGIC_OUTS_B13_R_2.PCIE_TOP_MIMRXRADDR0 always +PCIE_TOP.PCIE_LOGIC_OUTS_B13_R_3.PCIE_TOP_CFGMGMTDO22 always +PCIE_TOP.PCIE_LOGIC_OUTS_B13_R_4.PCIE_TOP_CFGMGMTDO24 always +PCIE_TOP.PCIE_LOGIC_OUTS_B14_L_0.PCIE_TOP_CFGLINKCONTROLRCB always +PCIE_TOP.PCIE_LOGIC_OUTS_B14_L_1.PCIE_TOP_CFGLINKCONTROLCLOCKPMEN always +PCIE_TOP.PCIE_LOGIC_OUTS_B14_L_2.PCIE_TOP_CFGDEVCONTROL2CPLTIMEOUTVAL0 always +PCIE_TOP.PCIE_LOGIC_OUTS_B14_L_3.PCIE_TOP_CFGDEVCONTROL2CPLTIMEOUTDIS always +PCIE_TOP.PCIE_LOGIC_OUTS_B14_L_4.PCIE_TOP_CFGDEVCONTROL2IDOREQEN always +PCIE_TOP.PCIE_LOGIC_OUTS_B14_R_0.PCIE_TOP_DBGVECA18 always +PCIE_TOP.PCIE_LOGIC_OUTS_B14_R_1.PCIE_TOP_TRNRDLLPSRCRDY1 always +PCIE_TOP.PCIE_LOGIC_OUTS_B14_R_2.PCIE_TOP_MIMRXWDATA28 always +PCIE_TOP.PCIE_LOGIC_OUTS_B14_R_3.PCIE_TOP_MIMRXWDATA23 always +PCIE_TOP.PCIE_LOGIC_OUTS_B14_R_4.PCIE_TOP_CFGMGMTDO25 always +PCIE_TOP.PCIE_LOGIC_OUTS_B15_L_0.PCIE_TOP_CFGLINKCONTROLLINKDISABLE always +PCIE_TOP.PCIE_LOGIC_OUTS_B15_L_1.PCIE_TOP_CFGLINKCONTROLHWAUTOWIDTHDIS always +PCIE_TOP.PCIE_LOGIC_OUTS_B15_L_2.PCIE_TOP_CFGDEVCONTROL2CPLTIMEOUTVAL1 always +PCIE_TOP.PCIE_LOGIC_OUTS_B15_L_3.PCIE_TOP_CFGDEVCONTROL2ARIFORWARDEN always +PCIE_TOP.PCIE_LOGIC_OUTS_B15_L_4.PCIE_TOP_CFGDEVCONTROL2IDOCPLEN always +PCIE_TOP.PCIE_LOGIC_OUTS_B15_R_0.PCIE_TOP_MIMRXWDATA22 always +PCIE_TOP.PCIE_LOGIC_OUTS_B15_R_1.PCIE_TOP_MIMRXWADDR1 always +PCIE_TOP.PCIE_LOGIC_OUTS_B15_R_2.PCIE_TOP_MIMRXWDATA3 always +PCIE_TOP.PCIE_LOGIC_OUTS_B15_R_3.PCIE_TOP_CFGMGMTDO23 always +PCIE_TOP.PCIE_LOGIC_OUTS_B15_R_4.PCIE_TOP_CFGMGMTDO26 always +PCIE_TOP.PCIE_LOGIC_OUTS_B16_L_0.PCIE_TOP_PIPETXMARGIN1 always +PCIE_TOP.PCIE_LOGIC_OUTS_B16_L_1.PCIE_TOP_CFGAERROOTERRFATALERRRECEIVED always +PCIE_TOP.PCIE_LOGIC_OUTS_B16_L_2.PCIE_TOP_CFGVCTCVCMAP3 always +PCIE_TOP.PCIE_LOGIC_OUTS_B16_L_3.PCIE_TOP_DRPRDY always +PCIE_TOP.PCIE_LOGIC_OUTS_B16_L_4.PCIE_TOP_DRPDO3 always +PCIE_TOP.PCIE_LOGIC_OUTS_B16_R_0.PCIE_TOP_MIMRXWDATA6 always +PCIE_TOP.PCIE_LOGIC_OUTS_B16_R_1.PCIE_TOP_LL2TFCINIT1SEQ always +PCIE_TOP.PCIE_LOGIC_OUTS_B16_R_2.PCIE_TOP_CFGMGMTDO17 always +PCIE_TOP.PCIE_LOGIC_OUTS_B16_R_3.PCIE_TOP_CFGMGMTDO28 always +PCIE_TOP.PCIE_LOGIC_OUTS_B16_R_4.PCIE_TOP_CFGMGMTDO27 always +PCIE_TOP.PCIE_LOGIC_OUTS_B17_L_0.PCIE_TOP_CFGLINKCONTROLRETRAINLINK always +PCIE_TOP.PCIE_LOGIC_OUTS_B17_L_1.PCIE_TOP_CFGVCTCVCMAP0 always +PCIE_TOP.PCIE_LOGIC_OUTS_B17_L_2.PCIE_TOP_CFGVCTCVCMAP4 always +PCIE_TOP.PCIE_LOGIC_OUTS_B17_L_3.PCIE_TOP_DRPDO0 always +PCIE_TOP.PCIE_LOGIC_OUTS_B17_L_4.PCIE_TOP_DRPDO4 always +PCIE_TOP.PCIE_LOGIC_OUTS_B17_R_0.PCIE_TOP_MIMRXRADDR8 always +PCIE_TOP.PCIE_LOGIC_OUTS_B17_R_1.PCIE_TOP_MIMRXWDATA34 always +PCIE_TOP.PCIE_LOGIC_OUTS_B17_R_2.PCIE_TOP_CFGMGMTDO18 always +PCIE_TOP.PCIE_LOGIC_OUTS_B17_R_3.PCIE_TOP_CFGMGMTDO29 always +PCIE_TOP.PCIE_LOGIC_OUTS_B17_R_4.PCIE_TOP_CFGCOMMANDMEMENABLE always +PCIE_TOP.PCIE_LOGIC_OUTS_B18_L_0.PCIE_TOP_PIPETXMARGIN0 always +PCIE_TOP.PCIE_LOGIC_OUTS_B18_L_1.PCIE_TOP_CFGVCTCVCMAP1 always +PCIE_TOP.PCIE_LOGIC_OUTS_B18_L_2.PCIE_TOP_CFGVCTCVCMAP5 always +PCIE_TOP.PCIE_LOGIC_OUTS_B18_L_3.PCIE_TOP_DRPDO1 always +PCIE_TOP.PCIE_LOGIC_OUTS_B18_L_4.PCIE_TOP_DRPDO5 always +PCIE_TOP.PCIE_LOGIC_OUTS_B18_R_0.PCIE_TOP_MIMRXWDATA2 always +PCIE_TOP.PCIE_LOGIC_OUTS_B18_R_1.PCIE_TOP_MIMRXWEN always +PCIE_TOP.PCIE_LOGIC_OUTS_B18_R_2.PCIE_TOP_MIMRXWDATA30 always +PCIE_TOP.PCIE_LOGIC_OUTS_B18_R_3.PCIE_TOP_CFGMGMTDO30 always +PCIE_TOP.PCIE_LOGIC_OUTS_B18_R_4.PCIE_TOP_MIMRXWDATA11 always +PCIE_TOP.PCIE_LOGIC_OUTS_B19_L_0.PCIE_TOP_CFGAERROOTERRNONFATALERRREPORTINGEN always +PCIE_TOP.PCIE_LOGIC_OUTS_B19_L_1.PCIE_TOP_CFGVCTCVCMAP2 always +PCIE_TOP.PCIE_LOGIC_OUTS_B19_L_2.PCIE_TOP_CFGVCTCVCMAP6 always +PCIE_TOP.PCIE_LOGIC_OUTS_B19_L_3.PCIE_TOP_DRPDO2 always +PCIE_TOP.PCIE_LOGIC_OUTS_B19_L_4.PCIE_TOP_DRPDO6 always +PCIE_TOP.PCIE_LOGIC_OUTS_B19_R_0.PCIE_TOP_DBGVECA19 always +PCIE_TOP.PCIE_LOGIC_OUTS_B19_R_1.PCIE_TOP_MIMRXWDATA10 always +PCIE_TOP.PCIE_LOGIC_OUTS_B19_R_2.PCIE_TOP_CFGMGMTDO19 always +PCIE_TOP.PCIE_LOGIC_OUTS_B19_R_3.PCIE_TOP_MIMRXWDATA21 always +PCIE_TOP.PCIE_LOGIC_OUTS_B19_R_4.PCIE_TOP_MIMRXWDATA27 always +PCIE_TOP.PCIE_LOGIC_OUTS_B20_L_0.PCIE_TOP_CFGAERROOTERRFATALERRREPORTINGEN always +PCIE_TOP.PCIE_LOGIC_OUTS_B20_L_1.PCIE_TOP_DRPDO11 always +PCIE_TOP.PCIE_LOGIC_OUTS_B20_L_2.PCIE_TOP_DRPDO15 always +PCIE_TOP.PCIE_LOGIC_OUTS_B20_L_3.PCIE_TOP_DBGVECA3 always +PCIE_TOP.PCIE_LOGIC_OUTS_B20_L_4.PCIE_TOP_DBGVECA7 always +PCIE_TOP.PCIE_LOGIC_OUTS_B20_R_0.PCIE_TOP_DBGVECA20 always +PCIE_TOP.PCIE_LOGIC_OUTS_B20_R_1.PCIE_TOP_LL2TFCINIT2SEQ always +PCIE_TOP.PCIE_LOGIC_OUTS_B20_R_2.PCIE_TOP_DBGVECA14 always +PCIE_TOP.PCIE_LOGIC_OUTS_B20_R_3.PCIE_TOP_DBGVECA12 always +PCIE_TOP.PCIE_LOGIC_OUTS_B20_R_4.PCIE_TOP_CFGCOMMANDBUSMASTERENABLE always +PCIE_TOP.PCIE_LOGIC_OUTS_B21_L_0.PCIE_TOP_CFGAERROOTERRCORRERRRECEIVED always +PCIE_TOP.PCIE_LOGIC_OUTS_B21_L_1.PCIE_TOP_DRPDO12 always +PCIE_TOP.PCIE_LOGIC_OUTS_B21_L_2.PCIE_TOP_DBGVECA0 always +PCIE_TOP.PCIE_LOGIC_OUTS_B21_L_3.PCIE_TOP_DBGVECA4 always +PCIE_TOP.PCIE_LOGIC_OUTS_B21_L_4.PCIE_TOP_DBGVECA8 always +PCIE_TOP.PCIE_LOGIC_OUTS_B21_R_0.PCIE_TOP_DBGVECA21 always +PCIE_TOP.PCIE_LOGIC_OUTS_B21_R_1.PCIE_TOP_CFGMGMTDO16 always +PCIE_TOP.PCIE_LOGIC_OUTS_B21_R_2.PCIE_TOP_MIMRXWDATA31 always +PCIE_TOP.PCIE_LOGIC_OUTS_B21_R_3.PCIE_TOP_DBGVECA13 always +PCIE_TOP.PCIE_LOGIC_OUTS_B21_R_4.PCIE_TOP_CFGCOMMANDINTERRUPTDISABLE always +PCIE_TOP.PCIE_LOGIC_OUTS_B22_L_0.PCIE_TOP_CFGAERROOTERRNONFATALERRRECEIVED always +PCIE_TOP.PCIE_LOGIC_OUTS_B22_L_1.PCIE_TOP_DRPDO13 always +PCIE_TOP.PCIE_LOGIC_OUTS_B22_L_2.PCIE_TOP_DBGVECA1 always +PCIE_TOP.PCIE_LOGIC_OUTS_B22_L_3.PCIE_TOP_DBGVECA5 always +PCIE_TOP.PCIE_LOGIC_OUTS_B22_L_4.PCIE_TOP_DBGVECA9 always +PCIE_TOP.PCIE_LOGIC_OUTS_B22_R_0.PCIE_TOP_DBGVECB10 always +PCIE_TOP.PCIE_LOGIC_OUTS_B22_R_1.PCIE_TOP_DBGVECA16 always +PCIE_TOP.PCIE_LOGIC_OUTS_B22_R_2.PCIE_TOP_MIMRXWDATA33 always +PCIE_TOP.PCIE_LOGIC_OUTS_B22_R_3.PCIE_TOP_MIMRXWDATA5 always +PCIE_TOP.PCIE_LOGIC_OUTS_B22_R_4.PCIE_TOP_DBGVECA11 always +PCIE_TOP.PCIE_LOGIC_OUTS_B23_L_0.PCIE_TOP_PLDBGVEC8 always +PCIE_TOP.PCIE_LOGIC_OUTS_B23_L_1.PCIE_TOP_DRPDO14 always +PCIE_TOP.PCIE_LOGIC_OUTS_B23_L_2.PCIE_TOP_DBGVECA2 always +PCIE_TOP.PCIE_LOGIC_OUTS_B23_L_3.PCIE_TOP_DBGVECA6 always +PCIE_TOP.PCIE_LOGIC_OUTS_B23_L_4.PCIE_TOP_DBGVECA10 always +PCIE_TOP.PCIE_LOGIC_OUTS_B23_R_1.PCIE_TOP_DBGVECA17 always +PCIE_TOP.PCIE_LOGIC_OUTS_B23_R_2.PCIE_TOP_DBGVECA15 always +PCIE_TOP.PCIE_LOGIC_OUTS_B23_R_3.PCIE_TOP_MIMRXWDATA7 always +PCIE_TOP.PCIE_LOGIC_OUTS_B23_R_4.PCIE_TOP_CFGDEVCONTROL2LTREN always +PCIE_TOP.PCIE_TOP_CFGERRLOCKEDN.PCIE_IMUX17_R_2 always +PCIE_TOP.PCIE_TOP_CFGERRNORECOVERYN.PCIE_IMUX18_R_2 always +PCIE_TOP.PCIE_TOP_CFGINTERRUPTN.PCIE_IMUX19_R_4 always +PCIE_TOP.PCIE_TOP_LL2SENDPMACK.PCIE_IMUX2_L_4 always +PCIE_TOP.PCIE_TOP_LL2SUSPENDNOW.PCIE_IMUX16_R_3 always +PCIE_TOP.PCIE_TOP_LL2TLPRCV.PCIE_IMUX2_L_3 always +PCIE_TOP.PCIE_TOP_PIPERX0CHANISALIGNED.PCIE_IMUX33_L_0 always +PCIE_TOP.PCIE_TOP_PIPERX0PHYSTATUS.PCIE_IMUX37_L_0 always +PCIE_TOP.PCIE_TOP_PIPERX0VALID.PCIE_IMUX36_L_0 always +PCIE_TOP.PCIE_TOP_PIPERX4CHANISALIGNED.PCIE_IMUX33_R_0 always +PCIE_TOP.PCIE_TOP_PIPERX4PHYSTATUS.PCIE_IMUX37_R_0 always +PCIE_TOP.PCIE_TOP_PIPERX4VALID.PCIE_IMUX36_R_0 always +PCIE_TOP.PCIE_TOP_TL2ASPMSUSPENDCREDITCHECK.PCIE_IMUX18_R_3 always +PCIE_TOP.PCIE_TOP_TL2PPMSUSPENDREQ.PCIE_IMUX17_R_3 always +PCIE_TOP.PCIE_TOP_TRNTDLLPSRCRDY.PCIE_IMUX1_L_3 always +PCIE_TOP.PCIE_TOP_CFGDEVID0.PCIE_IMUX11_L_1 always +PCIE_TOP.PCIE_TOP_CFGDEVID1.PCIE_IMUX8_L_2 always +PCIE_TOP.PCIE_TOP_CFGDEVID2.PCIE_IMUX9_L_2 always +PCIE_TOP.PCIE_TOP_CFGDEVID3.PCIE_IMUX10_L_2 always +PCIE_TOP.PCIE_TOP_CFGDEVID4.PCIE_IMUX11_L_2 always +PCIE_TOP.PCIE_TOP_CFGDEVID5.PCIE_IMUX8_L_3 always +PCIE_TOP.PCIE_TOP_CFGDEVID6.PCIE_IMUX9_L_3 always +PCIE_TOP.PCIE_TOP_CFGDEVID7.PCIE_IMUX10_L_3 always +PCIE_TOP.PCIE_TOP_CFGDEVID8.PCIE_IMUX11_L_3 always +PCIE_TOP.PCIE_TOP_CFGDEVID9.PCIE_IMUX8_L_4 always +PCIE_TOP.PCIE_TOP_CFGDEVID10.PCIE_IMUX9_L_4 always +PCIE_TOP.PCIE_TOP_CFGDEVID11.PCIE_IMUX10_L_4 always +PCIE_TOP.PCIE_TOP_CFGDEVID12.PCIE_IMUX11_L_4 always +PCIE_TOP.PCIE_TOP_CFGDEVID13.PCIE_IMUX21_R_4 always +PCIE_TOP.PCIE_TOP_CFGDEVID14.PCIE_IMUX22_R_4 always +PCIE_TOP.PCIE_TOP_CFGDEVID15.PCIE_IMUX23_R_4 always +PCIE_TOP.PCIE_TOP_CFGDSN57.PCIE_IMUX8_L_0 always +PCIE_TOP.PCIE_TOP_CFGDSN58.PCIE_IMUX9_L_0 always +PCIE_TOP.PCIE_TOP_CFGDSN59.PCIE_IMUX10_L_0 always +PCIE_TOP.PCIE_TOP_CFGDSN60.PCIE_IMUX11_L_0 always +PCIE_TOP.PCIE_TOP_CFGDSN61.PCIE_IMUX8_L_1 always +PCIE_TOP.PCIE_TOP_CFGDSN62.PCIE_IMUX9_L_1 always +PCIE_TOP.PCIE_TOP_CFGDSN63.PCIE_IMUX10_L_1 always +PCIE_TOP.PCIE_TOP_CFGERRAERHEADERLOG0.PCIE_IMUX19_R_2 always +PCIE_TOP.PCIE_TOP_CFGERRAERHEADERLOG1.PCIE_IMUX20_R_2 always +PCIE_TOP.PCIE_TOP_CFGERRAERHEADERLOG2.PCIE_IMUX20_R_3 always +PCIE_TOP.PCIE_TOP_CFGERRAERHEADERLOG3.PCIE_IMUX21_R_3 always +PCIE_TOP.PCIE_TOP_CFGERRAERHEADERLOG4.PCIE_IMUX22_R_3 always +PCIE_TOP.PCIE_TOP_CFGERRAERHEADERLOG5.PCIE_IMUX23_R_3 always +PCIE_TOP.PCIE_TOP_CFGERRAERHEADERLOG6.PCIE_IMUX13_R_4 always +PCIE_TOP.PCIE_TOP_CFGERRAERHEADERLOG7.PCIE_IMUX14_R_4 always +PCIE_TOP.PCIE_TOP_CFGERRAERHEADERLOG8.PCIE_IMUX15_R_4 always +PCIE_TOP.PCIE_TOP_CFGERRAERHEADERLOG9.PCIE_IMUX16_R_4 always +PCIE_TOP.PCIE_TOP_CFGERRAERHEADERLOG10.PCIE_IMUX24_R_3 always +PCIE_TOP.PCIE_TOP_CFGERRAERHEADERLOG11.PCIE_IMUX21_R_2 always +PCIE_TOP.PCIE_TOP_CFGERRTLPCPLHEADER26.PCIE_IMUX4_L_0 always +PCIE_TOP.PCIE_TOP_CFGERRTLPCPLHEADER27.PCIE_IMUX5_L_0 always +PCIE_TOP.PCIE_TOP_CFGERRTLPCPLHEADER28.PCIE_IMUX6_L_0 always +PCIE_TOP.PCIE_TOP_CFGERRTLPCPLHEADER29.PCIE_IMUX7_L_0 always +PCIE_TOP.PCIE_TOP_CFGERRTLPCPLHEADER30.PCIE_IMUX4_L_1 always +PCIE_TOP.PCIE_TOP_CFGERRTLPCPLHEADER31.PCIE_IMUX5_L_1 always +PCIE_TOP.PCIE_TOP_CFGERRTLPCPLHEADER32.PCIE_IMUX6_L_1 always +PCIE_TOP.PCIE_TOP_CFGERRTLPCPLHEADER33.PCIE_IMUX7_L_1 always +PCIE_TOP.PCIE_TOP_CFGERRTLPCPLHEADER34.PCIE_IMUX4_L_2 always +PCIE_TOP.PCIE_TOP_CFGERRTLPCPLHEADER35.PCIE_IMUX5_L_2 always +PCIE_TOP.PCIE_TOP_CFGERRTLPCPLHEADER36.PCIE_IMUX6_L_2 always +PCIE_TOP.PCIE_TOP_CFGERRTLPCPLHEADER37.PCIE_IMUX7_L_2 always +PCIE_TOP.PCIE_TOP_CFGERRTLPCPLHEADER38.PCIE_IMUX4_L_3 always +PCIE_TOP.PCIE_TOP_CFGERRTLPCPLHEADER39.PCIE_IMUX5_L_3 always +PCIE_TOP.PCIE_TOP_CFGERRTLPCPLHEADER40.PCIE_IMUX6_L_3 always +PCIE_TOP.PCIE_TOP_CFGERRTLPCPLHEADER41.PCIE_IMUX7_L_3 always +PCIE_TOP.PCIE_TOP_CFGERRTLPCPLHEADER42.PCIE_IMUX4_L_4 always +PCIE_TOP.PCIE_TOP_CFGERRTLPCPLHEADER43.PCIE_IMUX5_L_4 always +PCIE_TOP.PCIE_TOP_CFGERRTLPCPLHEADER44.PCIE_IMUX6_L_4 always +PCIE_TOP.PCIE_TOP_CFGERRTLPCPLHEADER45.PCIE_IMUX7_L_4 always +PCIE_TOP.PCIE_TOP_CFGERRTLPCPLHEADER46.PCIE_IMUX17_R_4 always +PCIE_TOP.PCIE_TOP_CFGERRTLPCPLHEADER47.PCIE_IMUX18_R_4 always +PCIE_TOP.PCIE_TOP_CFGINTERRUPTDI0.PCIE_IMUX20_R_4 always +PCIE_TOP.PCIE_TOP_CFGVENDID0.PCIE_IMUX24_R_4 always +PCIE_TOP.PCIE_TOP_DBGMODE0.PCIE_IMUX25_R_4 always +PCIE_TOP.PCIE_TOP_DRPADDR7.PCIE_IMUX12_L_0 always +PCIE_TOP.PCIE_TOP_DRPADDR8.PCIE_IMUX13_L_0 always +PCIE_TOP.PCIE_TOP_DRPDI0.PCIE_IMUX12_L_1 always +PCIE_TOP.PCIE_TOP_DRPDI1.PCIE_IMUX13_L_1 always +PCIE_TOP.PCIE_TOP_DRPDI2.PCIE_IMUX14_L_1 always +PCIE_TOP.PCIE_TOP_DRPDI3.PCIE_IMUX15_L_1 always +PCIE_TOP.PCIE_TOP_DRPDI4.PCIE_IMUX12_L_2 always +PCIE_TOP.PCIE_TOP_DRPDI5.PCIE_IMUX13_L_2 always +PCIE_TOP.PCIE_TOP_DRPDI6.PCIE_IMUX14_L_2 always +PCIE_TOP.PCIE_TOP_DRPDI7.PCIE_IMUX15_L_2 always +PCIE_TOP.PCIE_TOP_DRPDI8.PCIE_IMUX12_L_3 always +PCIE_TOP.PCIE_TOP_DRPDI9.PCIE_IMUX13_L_3 always +PCIE_TOP.PCIE_TOP_DRPDI10.PCIE_IMUX14_L_3 always +PCIE_TOP.PCIE_TOP_DRPDI11.PCIE_IMUX15_L_3 always +PCIE_TOP.PCIE_TOP_DRPDI12.PCIE_IMUX12_L_4 always +PCIE_TOP.PCIE_TOP_DRPDI13.PCIE_IMUX13_L_4 always +PCIE_TOP.PCIE_TOP_DRPDI14.PCIE_IMUX14_L_4 always +PCIE_TOP.PCIE_TOP_DRPDI15.PCIE_IMUX15_L_4 always +PCIE_TOP.PCIE_TOP_LL2SENDASREQL1.PCIE_IMUX1_L_4 always +PCIE_TOP.PCIE_TOP_LL2SENDENTERL1.PCIE_IMUX3_L_3 always +PCIE_TOP.PCIE_TOP_LL2SENDENTERL23.PCIE_IMUX0_L_4 always +PCIE_TOP.PCIE_TOP_MIMRXRDATA20.PCIE_IMUX0_R_0 always +PCIE_TOP.PCIE_TOP_MIMRXRDATA21.PCIE_IMUX1_R_0 always +PCIE_TOP.PCIE_TOP_MIMRXRDATA22.PCIE_IMUX2_R_0 always +PCIE_TOP.PCIE_TOP_MIMRXRDATA23.PCIE_IMUX3_R_0 always +PCIE_TOP.PCIE_TOP_MIMRXRDATA24.PCIE_IMUX0_R_1 always +PCIE_TOP.PCIE_TOP_MIMRXRDATA25.PCIE_IMUX1_R_1 always +PCIE_TOP.PCIE_TOP_MIMRXRDATA26.PCIE_IMUX2_R_1 always +PCIE_TOP.PCIE_TOP_MIMRXRDATA27.PCIE_IMUX3_R_1 always +PCIE_TOP.PCIE_TOP_MIMRXRDATA28.PCIE_IMUX0_R_2 always +PCIE_TOP.PCIE_TOP_MIMRXRDATA29.PCIE_IMUX1_R_2 always +PCIE_TOP.PCIE_TOP_MIMRXRDATA30.PCIE_IMUX2_R_2 always +PCIE_TOP.PCIE_TOP_MIMRXRDATA31.PCIE_IMUX3_R_2 always +PCIE_TOP.PCIE_TOP_MIMRXRDATA32.PCIE_IMUX0_R_3 always +PCIE_TOP.PCIE_TOP_MIMRXRDATA33.PCIE_IMUX1_R_3 always +PCIE_TOP.PCIE_TOP_MIMRXRDATA34.PCIE_IMUX2_R_3 always +PCIE_TOP.PCIE_TOP_MIMRXRDATA35.PCIE_IMUX3_R_3 always +PCIE_TOP.PCIE_TOP_MIMRXRDATA36.PCIE_IMUX0_R_4 always +PCIE_TOP.PCIE_TOP_MIMRXRDATA37.PCIE_IMUX1_R_4 always +PCIE_TOP.PCIE_TOP_MIMRXRDATA38.PCIE_IMUX2_R_4 always +PCIE_TOP.PCIE_TOP_MIMRXRDATA39.PCIE_IMUX3_R_4 always +PCIE_TOP.PCIE_TOP_MIMRXRDATA40.PCIE_IMUX4_R_3 always +PCIE_TOP.PCIE_TOP_MIMRXRDATA41.PCIE_IMUX5_R_3 always +PCIE_TOP.PCIE_TOP_MIMRXRDATA42.PCIE_IMUX6_R_3 always +PCIE_TOP.PCIE_TOP_MIMRXRDATA43.PCIE_IMUX7_R_3 always +PCIE_TOP.PCIE_TOP_MIMRXRDATA44.PCIE_IMUX4_R_2 always +PCIE_TOP.PCIE_TOP_MIMRXRDATA45.PCIE_IMUX5_R_2 always +PCIE_TOP.PCIE_TOP_MIMRXRDATA46.PCIE_IMUX6_R_2 always +PCIE_TOP.PCIE_TOP_MIMRXRDATA47.PCIE_IMUX7_R_2 always +PCIE_TOP.PCIE_TOP_MIMRXRDATA48.PCIE_IMUX4_R_1 always +PCIE_TOP.PCIE_TOP_MIMRXRDATA49.PCIE_IMUX5_R_1 always +PCIE_TOP.PCIE_TOP_MIMRXRDATA50.PCIE_IMUX6_R_1 always +PCIE_TOP.PCIE_TOP_MIMRXRDATA51.PCIE_IMUX7_R_1 always +PCIE_TOP.PCIE_TOP_MIMRXRDATA52.PCIE_IMUX4_R_0 always +PCIE_TOP.PCIE_TOP_MIMRXRDATA53.PCIE_IMUX5_R_0 always +PCIE_TOP.PCIE_TOP_MIMRXRDATA54.PCIE_IMUX6_R_0 always +PCIE_TOP.PCIE_TOP_MIMRXRDATA55.PCIE_IMUX7_R_0 always +PCIE_TOP.PCIE_TOP_PIPERX0CHARISK0.PCIE_IMUX16_L_1 always +PCIE_TOP.PCIE_TOP_PIPERX0DATA0.PCIE_IMUX37_L_1 always +PCIE_TOP.PCIE_TOP_PIPERX0DATA1.PCIE_IMUX36_L_1 always +PCIE_TOP.PCIE_TOP_PIPERX0DATA2.PCIE_IMUX33_L_1 always +PCIE_TOP.PCIE_TOP_PIPERX0DATA3.PCIE_IMUX32_L_1 always +PCIE_TOP.PCIE_TOP_PIPERX0DATA4.PCIE_IMUX39_L_0 always +PCIE_TOP.PCIE_TOP_PIPERX0DATA5.PCIE_IMUX38_L_0 always +PCIE_TOP.PCIE_TOP_PIPERX0DATA6.PCIE_IMUX35_L_0 always +PCIE_TOP.PCIE_TOP_PIPERX0DATA7.PCIE_IMUX34_L_0 always +PCIE_TOP.PCIE_TOP_PIPERX4CHARISK0.PCIE_IMUX16_R_1 always +PCIE_TOP.PCIE_TOP_PIPERX4DATA0.PCIE_IMUX37_R_1 always +PCIE_TOP.PCIE_TOP_PIPERX4DATA1.PCIE_IMUX36_R_1 always +PCIE_TOP.PCIE_TOP_PIPERX4DATA2.PCIE_IMUX33_R_1 always +PCIE_TOP.PCIE_TOP_PIPERX4DATA3.PCIE_IMUX32_R_1 always +PCIE_TOP.PCIE_TOP_PIPERX4DATA4.PCIE_IMUX39_R_0 always +PCIE_TOP.PCIE_TOP_PIPERX4DATA5.PCIE_IMUX38_R_0 always +PCIE_TOP.PCIE_TOP_PIPERX4DATA6.PCIE_IMUX35_R_0 always +PCIE_TOP.PCIE_TOP_PIPERX4DATA7.PCIE_IMUX34_R_0 always +PCIE_TOP.PCIE_TOP_PL2DIRECTEDLSTATE0.PCIE_IMUX3_L_4 always +PCIE_TOP.PCIE_TOP_PL2DIRECTEDLSTATE1.PCIE_IMUX8_R_4 always +PCIE_TOP.PCIE_TOP_PL2DIRECTEDLSTATE2.PCIE_IMUX9_R_4 always +PCIE_TOP.PCIE_TOP_PL2DIRECTEDLSTATE3.PCIE_IMUX10_R_4 always +PCIE_TOP.PCIE_TOP_PL2DIRECTEDLSTATE4.PCIE_IMUX11_R_4 always +PCIE_TOP.PCIE_TOP_TRNTD8.PCIE_IMUX8_R_0 always +PCIE_TOP.PCIE_TOP_TRNTD9.PCIE_IMUX9_R_0 always +PCIE_TOP.PCIE_TOP_TRNTD10.PCIE_IMUX10_R_0 always +PCIE_TOP.PCIE_TOP_TRNTD11.PCIE_IMUX11_R_0 always +PCIE_TOP.PCIE_TOP_TRNTD12.PCIE_IMUX8_R_1 always +PCIE_TOP.PCIE_TOP_TRNTD13.PCIE_IMUX9_R_1 always +PCIE_TOP.PCIE_TOP_TRNTD14.PCIE_IMUX10_R_1 always +PCIE_TOP.PCIE_TOP_TRNTD15.PCIE_IMUX11_R_1 always +PCIE_TOP.PCIE_TOP_TRNTD16.PCIE_IMUX8_R_2 always +PCIE_TOP.PCIE_TOP_TRNTD17.PCIE_IMUX9_R_2 always +PCIE_TOP.PCIE_TOP_TRNTD18.PCIE_IMUX10_R_2 always +PCIE_TOP.PCIE_TOP_TRNTD19.PCIE_IMUX11_R_2 always +PCIE_TOP.PCIE_TOP_TRNTD20.PCIE_IMUX8_R_3 always +PCIE_TOP.PCIE_TOP_TRNTD21.PCIE_IMUX9_R_3 always +PCIE_TOP.PCIE_TOP_TRNTD22.PCIE_IMUX10_R_3 always +PCIE_TOP.PCIE_TOP_TRNTD23.PCIE_IMUX11_R_3 always +PCIE_TOP.PCIE_TOP_TRNTD24.PCIE_IMUX4_R_4 always +PCIE_TOP.PCIE_TOP_TRNTD25.PCIE_IMUX5_R_4 always +PCIE_TOP.PCIE_TOP_TRNTD26.PCIE_IMUX6_R_4 always +PCIE_TOP.PCIE_TOP_TRNTD27.PCIE_IMUX7_R_4 always +PCIE_TOP.PCIE_TOP_TRNTD28.PCIE_IMUX12_R_3 always +PCIE_TOP.PCIE_TOP_TRNTD29.PCIE_IMUX13_R_3 always +PCIE_TOP.PCIE_TOP_TRNTD30.PCIE_IMUX14_R_3 always +PCIE_TOP.PCIE_TOP_TRNTD31.PCIE_IMUX15_R_3 always +PCIE_TOP.PCIE_TOP_TRNTD32.PCIE_IMUX12_R_2 always +PCIE_TOP.PCIE_TOP_TRNTD33.PCIE_IMUX13_R_2 always +PCIE_TOP.PCIE_TOP_TRNTD34.PCIE_IMUX14_R_2 always +PCIE_TOP.PCIE_TOP_TRNTD35.PCIE_IMUX15_R_2 always +PCIE_TOP.PCIE_TOP_TRNTD36.PCIE_IMUX12_R_1 always +PCIE_TOP.PCIE_TOP_TRNTD37.PCIE_IMUX13_R_1 always +PCIE_TOP.PCIE_TOP_TRNTD38.PCIE_IMUX14_R_1 always +PCIE_TOP.PCIE_TOP_TRNTD39.PCIE_IMUX15_R_1 always +PCIE_TOP.PCIE_TOP_TRNTD40.PCIE_IMUX12_R_0 always +PCIE_TOP.PCIE_TOP_TRNTD41.PCIE_IMUX13_R_0 always +PCIE_TOP.PCIE_TOP_TRNTDLLPDATA19.PCIE_IMUX0_L_0 always +PCIE_TOP.PCIE_TOP_TRNTDLLPDATA20.PCIE_IMUX1_L_0 always +PCIE_TOP.PCIE_TOP_TRNTDLLPDATA21.PCIE_IMUX2_L_0 always +PCIE_TOP.PCIE_TOP_TRNTDLLPDATA22.PCIE_IMUX3_L_0 always +PCIE_TOP.PCIE_TOP_TRNTDLLPDATA23.PCIE_IMUX0_L_1 always +PCIE_TOP.PCIE_TOP_TRNTDLLPDATA24.PCIE_IMUX1_L_1 always +PCIE_TOP.PCIE_TOP_TRNTDLLPDATA25.PCIE_IMUX2_L_1 always +PCIE_TOP.PCIE_TOP_TRNTDLLPDATA26.PCIE_IMUX3_L_1 always +PCIE_TOP.PCIE_TOP_TRNTDLLPDATA27.PCIE_IMUX0_L_2 always +PCIE_TOP.PCIE_TOP_TRNTDLLPDATA28.PCIE_IMUX1_L_2 always +PCIE_TOP.PCIE_TOP_TRNTDLLPDATA29.PCIE_IMUX2_L_2 always +PCIE_TOP.PCIE_TOP_TRNTDLLPDATA30.PCIE_IMUX3_L_2 always +PCIE_TOP.PCIE_TOP_TRNTDLLPDATA31.PCIE_IMUX0_L_3 always diff --git a/kintex7/segbits_cmt_top_l_lower_b.db b/kintex7/segbits_cmt_top_l_lower_b.db index b7af7a2..335ac39 100644 --- a/kintex7/segbits_cmt_top_l_lower_b.db +++ b/kintex7/segbits_cmt_top_l_lower_b.db @@ -25,381 +25,381 @@ CMT_TOP_L_LOWER_B.MMCM_CLK_FREQ_BB_NS2_ACTIVE 28_1068 28_1076 29_1057 CMT_TOP_L_LOWER_B.MMCM_CLK_FREQ_BB_NS2.MMCM_CLK_FREQ_BB_REBUF2_NS 28_1072 29_1067 29_1075 29_1079 CMT_TOP_L_LOWER_B.MMCM_CLK_FREQ_BB_NS3_ACTIVE 28_1058 28_1069 28_1077 CMT_TOP_L_LOWER_B.MMCM_CLK_FREQ_BB_NS3.MMCM_CLK_FREQ_BB_REBUF3_NS 28_1073 29_1068 29_1076 29_1080 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[0] 29_860 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[1] 28_860 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[2] 29_859 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[3] 28_859 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[4] 29_858 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[5] 28_858 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[0] 29_863 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[1] 28_863 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[2] 29_862 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[3] 28_862 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[4] 29_861 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[5] 28_861 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE[0] 29_857 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_PHASE_MUX[0] 28_857 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_PHASE_MUX[1] 29_856 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_PHASE_MUX[2] 28_856 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[0] 29_855 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[1] 28_855 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[2] 29_854 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[3] 28_854 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[4] 29_853 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[5] 28_853 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_EDGE[0] 28_852 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC[0] 29_849 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC[1] 28_849 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC[2] 29_848 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC_EN[0] 28_850 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC_WF_R[0] 29_850 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_MX[0] 29_851 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_MX[1] 28_851 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_NO_COUNT[0] 29_852 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_RESERVED[0] 28_848 -CMT_TOP_L_LOWER_B.MMCME2.COMP.Z_ZHOLD 28_979 28_1020 -CMT_TOP_L_LOWER_B.MMCME2.COMP.ZHOLD 28_1019 29_982 -CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_EDGE[0] 28_841 -CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[0] 29_844 -CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[1] 28_844 -CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[2] 29_843 -CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[3] 28_843 -CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[4] 29_842 -CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[5] 28_842 -CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[0] 29_847 -CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[1] 28_847 -CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[2] 29_846 -CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[3] 28_846 -CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[4] 29_845 -CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[5] 28_845 -CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_NO_COUNT[0] 29_841 -CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_RESERVED[0] 29_840 -CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_RESERVED[1] 28_840 -CMT_TOP_L_LOWER_B.MMCME2.IN_USE 28_18 28_21 28_22 28_23 28_24 28_25 28_27 28_28 28_31 28_32 28_33 28_34 28_36 28_37 28_38 28_39 28_40 28_44 28_46 28_47 28_48 28_49 28_50 28_51 28_52 28_54 28_63 28_65 28_66 28_70 28_72 28_73 28_75 28_77 28_78 28_428 28_429 28_430 28_433 28_434 28_466 28_488 28_492 28_772 28_773 28_774 28_787 28_976 28_978 28_989 28_991 28_1007 29_16 29_18 29_22 29_25 29_28 29_31 29_34 29_35 29_36 29_37 29_39 29_40 29_41 29_42 29_44 29_45 29_46 29_47 29_48 29_51 29_52 29_56 29_57 29_60 29_64 29_65 29_66 29_67 29_68 29_70 29_71 29_72 29_73 29_75 29_76 29_77 29_78 29_95 29_427 29_428 29_431 29_432 29_433 29_463 29_771 29_772 29_775 29_789 29_833 29_836 29_839 29_977 29_981 29_987 29_990 29_991 29_1007 29_1018 -CMT_TOP_L_LOWER_B.MMCME2.INV_CLKINSEL 29_109 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[0] 29_823 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[1] 28_823 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[2] 29_822 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[3] 28_822 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[4] 29_821 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[5] 28_821 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[6] 29_820 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[7] 28_820 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[8] 29_819 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[9] 28_819 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[10] 29_815 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[11] 28_815 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[12] 29_814 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[13] 28_814 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[14] 29_813 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[15] 28_813 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[16] 29_812 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[17] 28_812 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[18] 29_811 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[19] 28_811 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[20] 29_831 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[21] 28_831 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[22] 29_830 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[23] 28_830 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[24] 29_829 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[25] 28_829 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[26] 29_828 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[27] 28_828 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[28] 29_827 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[29] 28_827 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[30] 29_818 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[31] 28_818 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[32] 29_817 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[33] 28_817 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[34] 29_816 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[35] 29_810 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[36] 28_810 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[37] 29_809 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[38] 28_809 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[39] 29_808 -CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[0] 29_703 -CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[1] 28_703 -CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[2] 29_702 -CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[3] 28_702 -CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[4] 29_701 -CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[5] 28_701 -CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[6] 29_700 -CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[7] 28_700 -CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[8] 29_699 -CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[9] 28_699 -CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[10] 29_698 -CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[11] 28_698 -CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[12] 29_697 -CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[13] 28_697 -CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[14] 29_696 -CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[15] 28_696 -CMT_TOP_L_LOWER_B.MMCME2.SS_EN 28_95 28_388 28_696 28_698 28_700 28_702 28_850 28_915 29_389 29_697 29_701 29_703 -CMT_TOP_L_LOWER_B.MMCME2.STARTUP_WAIT 29_94 -CMT_TOP_L_LOWER_B.MMCME2.TABLE[0] 29_389 -CMT_TOP_L_LOWER_B.MMCME2.TABLE[1] 28_388 -CMT_TOP_L_LOWER_B.MMCME2.TABLE[2] 29_387 -CMT_TOP_L_LOWER_B.MMCME2.TABLE[3] 28_386 -CMT_TOP_L_LOWER_B.MMCME2.TABLE[4] 29_385 -CMT_TOP_L_LOWER_B.MMCME2.TABLE[5] 28_384 -CMT_TOP_L_LOWER_B.MMCME2.TABLE[6] 29_395 -CMT_TOP_L_LOWER_B.MMCME2.TABLE[7] 28_394 -CMT_TOP_L_LOWER_B.MMCME2.TABLE[8] 29_393 -CMT_TOP_L_LOWER_B.MMCME2.TABLE[9] 28_392 -CMT_TOP_L_LOWER_B.MMCME2.ZINV_PSEN 28_110 -CMT_TOP_L_LOWER_B.MMCME2.ZINV_PSINCDEC 29_110 -CMT_TOP_L_LOWER_B.MMCME2.ZINV_PWRDWN 28_111 -CMT_TOP_L_LOWER_B.MMCME2.ZINV_RST 29_111 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[0] 29_956 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[1] 28_956 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[2] 29_955 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[3] 28_955 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[4] 29_954 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[5] 28_954 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[0] 29_959 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[1] 28_959 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[2] 29_958 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[3] 28_958 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[4] 29_957 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[5] 28_957 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_OUTPUT_ENABLE[0] 29_953 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_PHASE_MUX[0] 28_953 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_PHASE_MUX[1] 29_952 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_PHASE_MUX[2] 28_952 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[0] 29_951 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[1] 28_951 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[2] 29_950 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[3] 28_950 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[4] 29_949 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[5] 28_949 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_EDGE[0] 28_948 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC[0] 29_945 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC[1] 28_945 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC[2] 29_944 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC_EN[0] 28_946 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC_WF_R[0] 29_946 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_MX[0] 29_947 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_MX[1] 28_947 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_NO_COUNT[0] 29_948 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_RESERVED[0] 28_944 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[0] 29_940 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[1] 28_940 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[2] 29_939 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[3] 28_939 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[4] 29_938 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[5] 28_938 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[0] 29_943 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[1] 28_943 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[2] 29_942 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[3] 28_942 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[4] 29_941 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[5] 28_941 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_OUTPUT_ENABLE[0] 29_937 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_PHASE_MUX[0] 28_937 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_PHASE_MUX[1] 29_936 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_PHASE_MUX[2] 28_936 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[0] 29_935 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[1] 28_935 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[2] 29_934 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[3] 28_934 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[4] 29_933 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[5] 28_933 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_EDGE[0] 28_932 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC[0] 29_929 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC[1] 28_929 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC[2] 29_928 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC_EN[0] 28_930 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC_WF_R[0] 29_930 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_MX[0] 29_931 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_MX[1] 28_931 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_NO_COUNT[0] 29_932 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_RESERVED[0] 28_928 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[0] 29_924 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[1] 28_924 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[2] 29_923 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[3] 28_923 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[4] 29_922 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[5] 28_922 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[0] 29_927 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[1] 28_927 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[2] 29_926 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[3] 28_926 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[4] 29_925 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[5] 28_925 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_OUTPUT_ENABLE[0] 29_921 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_PHASE_MUX[0] 28_921 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_PHASE_MUX[1] 29_920 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_PHASE_MUX[2] 28_920 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[0] 29_919 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[1] 28_919 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[2] 29_918 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[3] 28_918 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[4] 29_917 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[5] 28_917 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_EDGE[0] 28_916 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC[0] 29_913 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC[1] 28_913 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC[2] 29_912 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC_EN[0] 28_914 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC_WF_R[0] 29_914 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_MX[0] 29_915 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_MX[1] 28_915 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_NO_COUNT[0] 29_916 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_RESERVED[0] 28_912 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[0] 29_908 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[1] 28_908 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[2] 29_907 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[3] 28_907 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[4] 29_906 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[5] 28_906 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[0] 29_911 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[1] 28_911 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[2] 29_910 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[3] 28_910 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[4] 29_909 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[5] 28_909 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_OUTPUT_ENABLE[0] 29_905 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_PHASE_MUX[0] 28_905 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_PHASE_MUX[1] 29_904 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_PHASE_MUX[2] 28_904 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[0] 29_903 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[1] 28_903 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[2] 29_902 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[3] 28_902 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[4] 29_901 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[5] 28_901 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_EDGE[0] 28_900 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC[0] 29_897 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC[1] 28_897 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC[2] 29_896 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC_EN[0] 28_898 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC_WF_R[0] 29_898 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_MX[0] 29_899 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_MX[1] 28_899 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_NO_COUNT[0] 29_900 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_RESERVED[0] 28_896 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[0] 29_892 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[1] 28_892 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[2] 29_891 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[3] 28_891 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[4] 29_890 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[5] 28_890 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[0] 29_895 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[1] 28_895 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[2] 29_894 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[3] 28_894 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[4] 29_893 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[5] 28_893 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_OUTPUT_ENABLE[0] 29_889 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_PHASE_MUX[0] 28_889 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_PHASE_MUX[1] 29_888 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_PHASE_MUX[2] 28_888 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[0] 29_887 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[1] 28_887 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[2] 29_886 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[3] 28_886 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[4] 29_885 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[5] 28_885 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_EDGE[0] 28_884 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC[0] 29_881 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC[1] 28_881 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC[2] 29_880 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC_EN[0] 28_882 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC_WF_R[0] 29_882 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_MX[0] 29_883 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_MX[1] 28_883 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_NO_COUNT[0] 29_884 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_RESERVED[0] 28_880 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[0] 29_972 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[1] 28_972 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[2] 29_971 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[3] 28_971 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[4] 29_970 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[5] 28_970 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[0] 29_975 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[1] 28_975 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[2] 29_974 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[3] 28_974 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[4] 29_973 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[5] 28_973 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_OUTPUT_ENABLE[0] 29_969 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_PHASE_MUX[0] 28_969 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_PHASE_MUX[1] 29_968 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_PHASE_MUX[2] 28_968 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[0] 29_967 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[1] 28_967 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[2] 29_966 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[3] 28_966 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[4] 29_965 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[5] 28_965 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_EDGE[0] 28_964 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_FRAC_WF_F[0] 29_962 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_MX[0] 29_963 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_MX[1] 28_963 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_NO_COUNT[0] 29_964 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[0] 28_962 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[1] 29_961 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[2] 28_961 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_RESERVED[0] 29_960 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_RESERVED[1] 28_960 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[0] 29_876 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[1] 28_876 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[2] 29_875 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[3] 28_875 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[4] 29_874 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[5] 28_874 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[0] 29_879 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[1] 28_879 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[2] 29_878 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[3] 28_878 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[4] 29_877 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[5] 28_877 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_OUTPUT_ENABLE[0] 29_873 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_PHASE_MUX[0] 28_873 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_PHASE_MUX[1] 29_872 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_PHASE_MUX[2] 28_872 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[0] 29_871 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[1] 28_871 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[2] 29_870 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[3] 28_870 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[4] 29_869 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[5] 28_869 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_EDGE[0] 28_868 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_FRAC_WF_F[0] 29_866 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_MX[0] 29_867 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_MX[1] 28_867 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_NO_COUNT[0] 29_868 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[0] 28_866 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[1] 29_865 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[2] 28_865 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_RESERVED[0] 29_864 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_RESERVED[1] 28_864 -CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[0] 29_399 -CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[1] 28_399 -CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[2] 29_398 -CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[3] 28_398 -CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[4] 29_397 -CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[5] 28_397 -CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[6] 29_396 -CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[7] 28_396 -CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[8] 28_395 -CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[9] 29_394 -CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[10] 28_393 -CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[11] 29_392 -CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[0] 29_391 -CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[1] 28_391 -CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[2] 29_390 -CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[3] 28_390 -CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[4] 28_389 -CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[5] 29_388 -CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[6] 28_387 -CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[7] 29_386 -CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[8] 28_385 -CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[9] 29_384 -CMT_TOP_L_LOWER_B.MMCME2.LOCKREG1_RESERVED[0] 29_826 -CMT_TOP_L_LOWER_B.MMCME2.LOCKREG1_RESERVED[1] 28_826 -CMT_TOP_L_LOWER_B.MMCME2.LOCKREG1_RESERVED[2] 29_825 -CMT_TOP_L_LOWER_B.MMCME2.LOCKREG1_RESERVED[3] 28_825 -CMT_TOP_L_LOWER_B.MMCME2.LOCKREG1_RESERVED[4] 29_824 -CMT_TOP_L_LOWER_B.MMCME2.LOCKREG1_RESERVED[5] 28_824 -CMT_TOP_L_LOWER_B.MMCME2.LOCKREG2_RESERVED[0] 28_816 -CMT_TOP_L_LOWER_B.MMCME2.LOCKREG3_RESERVED[0] 28_808 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[0] 29_860 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[1] 28_860 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[2] 29_859 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[3] 28_859 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[4] 29_858 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[5] 28_858 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[0] 29_863 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[1] 28_863 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[2] 29_862 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[3] 28_862 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[4] 29_861 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[5] 28_861 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE[0] 29_857 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_PHASE_MUX[0] 28_857 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_PHASE_MUX[1] 29_856 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_PHASE_MUX[2] 28_856 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[0] 29_855 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[1] 28_855 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[2] 29_854 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[3] 28_854 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[4] 29_853 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[5] 28_853 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_EDGE[0] 28_852 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_FRAC[0] 29_849 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_FRAC[1] 28_849 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_FRAC[2] 29_848 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_FRAC_EN[0] 28_850 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_FRAC_WF_R[0] 29_850 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_MX[0] 29_851 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_MX[1] 28_851 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_NO_COUNT[0] 29_852 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_RESERVED[0] 28_848 +CMT_TOP_L_LOWER_B.MMCME2_ADV.COMP.Z_ZHOLD 28_979 28_1020 +CMT_TOP_L_LOWER_B.MMCME2_ADV.COMP.ZHOLD 28_1019 29_982 +CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_EDGE[0] 28_841 +CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_HIGH_TIME[0] 29_844 +CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_HIGH_TIME[1] 28_844 +CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_HIGH_TIME[2] 29_843 +CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_HIGH_TIME[3] 28_843 +CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_HIGH_TIME[4] 29_842 +CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_HIGH_TIME[5] 28_842 +CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_LOW_TIME[0] 29_847 +CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_LOW_TIME[1] 28_847 +CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_LOW_TIME[2] 29_846 +CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_LOW_TIME[3] 28_846 +CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_LOW_TIME[4] 29_845 +CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_LOW_TIME[5] 28_845 +CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_NO_COUNT[0] 29_841 +CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_RESERVED[0] 29_840 +CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_RESERVED[1] 28_840 +CMT_TOP_L_LOWER_B.MMCME2_ADV.IN_USE 28_18 28_21 28_22 28_23 28_24 28_25 28_27 28_28 28_31 28_32 28_33 28_34 28_36 28_37 28_38 28_39 28_40 28_44 28_46 28_47 28_48 28_49 28_50 28_51 28_52 28_54 28_63 28_65 28_66 28_70 28_72 28_73 28_75 28_77 28_78 28_428 28_429 28_430 28_433 28_434 28_466 28_488 28_492 28_772 28_773 28_774 28_787 28_976 28_978 28_989 28_991 28_1007 29_16 29_18 29_22 29_25 29_28 29_31 29_34 29_35 29_36 29_37 29_39 29_40 29_41 29_42 29_44 29_45 29_46 29_47 29_48 29_51 29_52 29_56 29_57 29_60 29_64 29_65 29_66 29_67 29_68 29_70 29_71 29_72 29_73 29_75 29_76 29_77 29_78 29_95 29_427 29_428 29_431 29_432 29_433 29_463 29_771 29_772 29_775 29_789 29_833 29_836 29_839 29_977 29_981 29_987 29_990 29_991 29_1007 29_1018 +CMT_TOP_L_LOWER_B.MMCME2_ADV.INV_CLKINSEL 29_109 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[0] 29_823 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[1] 28_823 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[2] 29_822 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[3] 28_822 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[4] 29_821 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[5] 28_821 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[6] 29_820 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[7] 28_820 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[8] 29_819 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[9] 28_819 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[10] 29_815 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[11] 28_815 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[12] 29_814 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[13] 28_814 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[14] 29_813 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[15] 28_813 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[16] 29_812 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[17] 28_812 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[18] 29_811 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[19] 28_811 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[20] 29_831 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[21] 28_831 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[22] 29_830 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[23] 28_830 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[24] 29_829 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[25] 28_829 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[26] 29_828 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[27] 28_828 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[28] 29_827 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[29] 28_827 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[30] 29_818 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[31] 28_818 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[32] 29_817 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[33] 28_817 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[34] 29_816 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[35] 29_810 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[36] 28_810 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[37] 29_809 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[38] 28_809 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[39] 29_808 +CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[0] 29_703 +CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[1] 28_703 +CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[2] 29_702 +CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[3] 28_702 +CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[4] 29_701 +CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[5] 28_701 +CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[6] 29_700 +CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[7] 28_700 +CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[8] 29_699 +CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[9] 28_699 +CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[10] 29_698 +CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[11] 28_698 +CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[12] 29_697 +CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[13] 28_697 +CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[14] 29_696 +CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[15] 28_696 +CMT_TOP_L_LOWER_B.MMCME2_ADV.SS_EN 28_95 28_388 28_696 28_698 28_700 28_702 28_850 28_915 29_389 29_697 29_701 29_703 +CMT_TOP_L_LOWER_B.MMCME2_ADV.STARTUP_WAIT 29_94 +CMT_TOP_L_LOWER_B.MMCME2_ADV.TABLE[0] 29_389 +CMT_TOP_L_LOWER_B.MMCME2_ADV.TABLE[1] 28_388 +CMT_TOP_L_LOWER_B.MMCME2_ADV.TABLE[2] 29_387 +CMT_TOP_L_LOWER_B.MMCME2_ADV.TABLE[3] 28_386 +CMT_TOP_L_LOWER_B.MMCME2_ADV.TABLE[4] 29_385 +CMT_TOP_L_LOWER_B.MMCME2_ADV.TABLE[5] 28_384 +CMT_TOP_L_LOWER_B.MMCME2_ADV.TABLE[6] 29_395 +CMT_TOP_L_LOWER_B.MMCME2_ADV.TABLE[7] 28_394 +CMT_TOP_L_LOWER_B.MMCME2_ADV.TABLE[8] 29_393 +CMT_TOP_L_LOWER_B.MMCME2_ADV.TABLE[9] 28_392 +CMT_TOP_L_LOWER_B.MMCME2_ADV.ZINV_PSEN 28_110 +CMT_TOP_L_LOWER_B.MMCME2_ADV.ZINV_PSINCDEC 29_110 +CMT_TOP_L_LOWER_B.MMCME2_ADV.ZINV_PWRDWN 28_111 +CMT_TOP_L_LOWER_B.MMCME2_ADV.ZINV_RST 29_111 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[0] 29_956 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[1] 28_956 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[2] 29_955 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[3] 28_955 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[4] 29_954 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[5] 28_954 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[0] 29_959 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[1] 28_959 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[2] 29_958 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[3] 28_958 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[4] 29_957 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[5] 28_957 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_OUTPUT_ENABLE[0] 29_953 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_PHASE_MUX[0] 28_953 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_PHASE_MUX[1] 29_952 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_PHASE_MUX[2] 28_952 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[0] 29_951 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[1] 28_951 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[2] 29_950 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[3] 28_950 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[4] 29_949 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[5] 28_949 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_EDGE[0] 28_948 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_FRAC[0] 29_945 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_FRAC[1] 28_945 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_FRAC[2] 29_944 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_FRAC_EN[0] 28_946 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_FRAC_WF_R[0] 29_946 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_MX[0] 29_947 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_MX[1] 28_947 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_NO_COUNT[0] 29_948 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_RESERVED[0] 28_944 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[0] 29_940 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[1] 28_940 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[2] 29_939 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[3] 28_939 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[4] 29_938 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[5] 28_938 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[0] 29_943 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[1] 28_943 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[2] 29_942 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[3] 28_942 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[4] 29_941 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[5] 28_941 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_OUTPUT_ENABLE[0] 29_937 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_PHASE_MUX[0] 28_937 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_PHASE_MUX[1] 29_936 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_PHASE_MUX[2] 28_936 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[0] 29_935 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[1] 28_935 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[2] 29_934 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[3] 28_934 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[4] 29_933 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[5] 28_933 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_EDGE[0] 28_932 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_FRAC[0] 29_929 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_FRAC[1] 28_929 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_FRAC[2] 29_928 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_FRAC_EN[0] 28_930 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_FRAC_WF_R[0] 29_930 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_MX[0] 29_931 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_MX[1] 28_931 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_NO_COUNT[0] 29_932 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_RESERVED[0] 28_928 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[0] 29_924 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[1] 28_924 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[2] 29_923 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[3] 28_923 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[4] 29_922 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[5] 28_922 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[0] 29_927 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[1] 28_927 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[2] 29_926 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[3] 28_926 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[4] 29_925 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[5] 28_925 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_OUTPUT_ENABLE[0] 29_921 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_PHASE_MUX[0] 28_921 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_PHASE_MUX[1] 29_920 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_PHASE_MUX[2] 28_920 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[0] 29_919 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[1] 28_919 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[2] 29_918 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[3] 28_918 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[4] 29_917 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[5] 28_917 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_EDGE[0] 28_916 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_FRAC[0] 29_913 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_FRAC[1] 28_913 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_FRAC[2] 29_912 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_FRAC_EN[0] 28_914 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_FRAC_WF_R[0] 29_914 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_MX[0] 29_915 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_MX[1] 28_915 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_NO_COUNT[0] 29_916 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_RESERVED[0] 28_912 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[0] 29_908 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[1] 28_908 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[2] 29_907 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[3] 28_907 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[4] 29_906 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[5] 28_906 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[0] 29_911 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[1] 28_911 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[2] 29_910 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[3] 28_910 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[4] 29_909 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[5] 28_909 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_OUTPUT_ENABLE[0] 29_905 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_PHASE_MUX[0] 28_905 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_PHASE_MUX[1] 29_904 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_PHASE_MUX[2] 28_904 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[0] 29_903 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[1] 28_903 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[2] 29_902 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[3] 28_902 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[4] 29_901 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[5] 28_901 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_EDGE[0] 28_900 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_FRAC[0] 29_897 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_FRAC[1] 28_897 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_FRAC[2] 29_896 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_FRAC_EN[0] 28_898 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_FRAC_WF_R[0] 29_898 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_MX[0] 29_899 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_MX[1] 28_899 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_NO_COUNT[0] 29_900 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_RESERVED[0] 28_896 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[0] 29_892 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[1] 28_892 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[2] 29_891 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[3] 28_891 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[4] 29_890 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[5] 28_890 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[0] 29_895 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[1] 28_895 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[2] 29_894 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[3] 28_894 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[4] 29_893 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[5] 28_893 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_OUTPUT_ENABLE[0] 29_889 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_PHASE_MUX[0] 28_889 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_PHASE_MUX[1] 29_888 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_PHASE_MUX[2] 28_888 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[0] 29_887 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[1] 28_887 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[2] 29_886 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[3] 28_886 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[4] 29_885 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[5] 28_885 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_EDGE[0] 28_884 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_FRAC[0] 29_881 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_FRAC[1] 28_881 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_FRAC[2] 29_880 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_FRAC_EN[0] 28_882 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_FRAC_WF_R[0] 29_882 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_MX[0] 29_883 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_MX[1] 28_883 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_NO_COUNT[0] 29_884 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_RESERVED[0] 28_880 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[0] 29_972 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[1] 28_972 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[2] 29_971 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[3] 28_971 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[4] 29_970 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[5] 28_970 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[0] 29_975 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[1] 28_975 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[2] 29_974 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[3] 28_974 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[4] 29_973 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[5] 28_973 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_OUTPUT_ENABLE[0] 29_969 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_PHASE_MUX[0] 28_969 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_PHASE_MUX[1] 29_968 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_PHASE_MUX[2] 28_968 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[0] 29_967 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[1] 28_967 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[2] 29_966 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[3] 28_966 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[4] 29_965 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[5] 28_965 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_EDGE[0] 28_964 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_FRAC_WF_F[0] 29_962 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_MX[0] 29_963 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_MX[1] 28_963 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_NO_COUNT[0] 29_964 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[0] 28_962 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[1] 29_961 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[2] 28_961 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_RESERVED[0] 29_960 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_RESERVED[1] 28_960 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_HIGH_TIME[0] 29_876 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_HIGH_TIME[1] 28_876 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_HIGH_TIME[2] 29_875 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_HIGH_TIME[3] 28_875 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_HIGH_TIME[4] 29_874 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_HIGH_TIME[5] 28_874 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_LOW_TIME[0] 29_879 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_LOW_TIME[1] 28_879 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_LOW_TIME[2] 29_878 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_LOW_TIME[3] 28_878 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_LOW_TIME[4] 29_877 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_LOW_TIME[5] 28_877 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_OUTPUT_ENABLE[0] 29_873 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_PHASE_MUX[0] 28_873 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_PHASE_MUX[1] 29_872 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_PHASE_MUX[2] 28_872 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[0] 29_871 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[1] 28_871 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[2] 29_870 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[3] 28_870 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[4] 29_869 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[5] 28_869 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_EDGE[0] 28_868 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_FRAC_WF_F[0] 29_866 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_MX[0] 29_867 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_MX[1] 28_867 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_NO_COUNT[0] 29_868 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[0] 28_866 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[1] 29_865 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[2] 28_865 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_RESERVED[0] 29_864 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_RESERVED[1] 28_864 +CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[0] 29_399 +CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[1] 28_399 +CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[2] 29_398 +CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[3] 28_398 +CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[4] 29_397 +CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[5] 28_397 +CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[6] 29_396 +CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[7] 28_396 +CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[8] 28_395 +CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[9] 29_394 +CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[10] 28_393 +CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[11] 29_392 +CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[0] 29_391 +CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[1] 28_391 +CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[2] 29_390 +CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[3] 28_390 +CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[4] 28_389 +CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[5] 29_388 +CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[6] 28_387 +CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[7] 29_386 +CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[8] 28_385 +CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[9] 29_384 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LOCKREG1_RESERVED[0] 29_826 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LOCKREG1_RESERVED[1] 28_826 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LOCKREG1_RESERVED[2] 29_825 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LOCKREG1_RESERVED[3] 28_825 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LOCKREG1_RESERVED[4] 29_824 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LOCKREG1_RESERVED[5] 28_824 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LOCKREG2_RESERVED[0] 28_816 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LOCKREG3_RESERVED[0] 28_808 diff --git a/kintex7/segbits_cmt_top_l_lower_b.origin_info.db b/kintex7/segbits_cmt_top_l_lower_b.origin_info.db index 26d659a..08fbfa6 100644 --- a/kintex7/segbits_cmt_top_l_lower_b.origin_info.db +++ b/kintex7/segbits_cmt_top_l_lower_b.origin_info.db @@ -25,381 +25,381 @@ CMT_TOP_L_LOWER_B.MMCM_CLK_FREQ_BB_NS2_ACTIVE origin:034b-cmt-mmcm-pips 28_1068 CMT_TOP_L_LOWER_B.MMCM_CLK_FREQ_BB_NS2.MMCM_CLK_FREQ_BB_REBUF2_NS origin:034b-cmt-mmcm-pips 28_1072 29_1067 29_1075 29_1079 CMT_TOP_L_LOWER_B.MMCM_CLK_FREQ_BB_NS3_ACTIVE origin:034b-cmt-mmcm-pips 28_1058 28_1069 28_1077 CMT_TOP_L_LOWER_B.MMCM_CLK_FREQ_BB_NS3.MMCM_CLK_FREQ_BB_REBUF3_NS origin:034b-cmt-mmcm-pips 28_1073 29_1068 29_1076 29_1080 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_860 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_860 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_859 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_859 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_858 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_858 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_863 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_863 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_862 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_862 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_861 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_861 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_857 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_857 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_856 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_856 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_855 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_855 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_854 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_854 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_853 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_853 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_852 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_849 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_849 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_848 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_850 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_850 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_851 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_851 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_852 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_848 -CMT_TOP_L_LOWER_B.MMCME2.COMP.Z_ZHOLD origin:031-cmt-mmcm 28_1020 28_979 -CMT_TOP_L_LOWER_B.MMCME2.COMP.ZHOLD origin:031-cmt-mmcm 28_1019 29_982 -CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_EDGE[0] origin:031-cmt-mmcm 28_841 -CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[0] origin:031-cmt-mmcm 29_844 -CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[1] origin:031-cmt-mmcm 28_844 -CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[2] origin:031-cmt-mmcm 29_843 -CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[3] origin:031-cmt-mmcm 28_843 -CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[4] origin:031-cmt-mmcm 29_842 -CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[5] origin:031-cmt-mmcm 28_842 -CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[0] origin:031-cmt-mmcm 29_847 -CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[1] origin:031-cmt-mmcm 28_847 -CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[2] origin:031-cmt-mmcm 29_846 -CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[3] origin:031-cmt-mmcm 28_846 -CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[4] origin:031-cmt-mmcm 29_845 -CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[5] origin:031-cmt-mmcm 28_845 -CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_NO_COUNT[0] origin:031-cmt-mmcm 29_841 -CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_RESERVED[0] origin:031-cmt-mmcm 29_840 -CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_RESERVED[1] origin:031-cmt-mmcm 28_840 -CMT_TOP_L_LOWER_B.MMCME2.IN_USE origin:031-cmt-mmcm 28_1007 28_18 28_21 28_22 28_23 28_24 28_25 28_27 28_28 28_31 28_32 28_33 28_34 28_36 28_37 28_38 28_39 28_40 28_428 28_429 28_430 28_433 28_434 28_44 28_46 28_466 28_47 28_48 28_488 28_49 28_492 28_50 28_51 28_52 28_54 28_63 28_65 28_66 28_70 28_72 28_73 28_75 28_77 28_772 28_773 28_774 28_78 28_787 28_976 28_978 28_989 28_991 29_1007 29_1018 29_16 29_18 29_22 29_25 29_28 29_31 29_34 29_35 29_36 29_37 29_39 29_40 29_41 29_42 29_427 29_428 29_431 29_432 29_433 29_44 29_45 29_46 29_463 29_47 29_48 29_51 29_52 29_56 29_57 29_60 29_64 29_65 29_66 29_67 29_68 29_70 29_71 29_72 29_73 29_75 29_76 29_77 29_771 29_772 29_775 29_78 29_789 29_833 29_836 29_839 29_95 29_977 29_981 29_987 29_990 29_991 -CMT_TOP_L_LOWER_B.MMCME2.INV_CLKINSEL origin:031-cmt-mmcm 29_109 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[0] origin:031-cmt-mmcm 29_823 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[1] origin:031-cmt-mmcm 28_823 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[2] origin:031-cmt-mmcm 29_822 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[3] origin:031-cmt-mmcm 28_822 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[4] origin:031-cmt-mmcm 29_821 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[5] origin:031-cmt-mmcm 28_821 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[6] origin:031-cmt-mmcm 29_820 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[7] origin:031-cmt-mmcm 28_820 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[8] origin:031-cmt-mmcm 29_819 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[9] origin:031-cmt-mmcm 28_819 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[10] origin:031-cmt-mmcm 29_815 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[11] origin:031-cmt-mmcm 28_815 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[12] origin:031-cmt-mmcm 29_814 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[13] origin:031-cmt-mmcm 28_814 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[14] origin:031-cmt-mmcm 29_813 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[15] origin:031-cmt-mmcm 28_813 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[16] origin:031-cmt-mmcm 29_812 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[17] origin:031-cmt-mmcm 28_812 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[18] origin:031-cmt-mmcm 29_811 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[19] origin:031-cmt-mmcm 28_811 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[20] origin:031-cmt-mmcm 29_831 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[21] origin:031-cmt-mmcm 28_831 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[22] origin:031-cmt-mmcm 29_830 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[23] origin:031-cmt-mmcm 28_830 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[24] origin:031-cmt-mmcm 29_829 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[25] origin:031-cmt-mmcm 28_829 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[26] origin:031-cmt-mmcm 29_828 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[27] origin:031-cmt-mmcm 28_828 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[28] origin:031-cmt-mmcm 29_827 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[29] origin:031-cmt-mmcm 28_827 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[30] origin:031-cmt-mmcm 29_818 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[31] origin:031-cmt-mmcm 28_818 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[32] origin:031-cmt-mmcm 29_817 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[33] origin:031-cmt-mmcm 28_817 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[34] origin:031-cmt-mmcm 29_816 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[35] origin:031-cmt-mmcm 29_810 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[36] origin:031-cmt-mmcm 28_810 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[37] origin:031-cmt-mmcm 29_809 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[38] origin:031-cmt-mmcm 28_809 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[39] origin:031-cmt-mmcm 29_808 -CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[0] origin:031-cmt-mmcm 29_703 -CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[1] origin:031-cmt-mmcm 28_703 -CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[2] origin:031-cmt-mmcm 29_702 -CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[3] origin:031-cmt-mmcm 28_702 -CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[4] origin:031-cmt-mmcm 29_701 -CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[5] origin:031-cmt-mmcm 28_701 -CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[6] origin:031-cmt-mmcm 29_700 -CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[7] origin:031-cmt-mmcm 28_700 -CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[8] origin:031-cmt-mmcm 29_699 -CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[9] origin:031-cmt-mmcm 28_699 -CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[10] origin:031-cmt-mmcm 29_698 -CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[11] origin:031-cmt-mmcm 28_698 -CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[12] origin:031-cmt-mmcm 29_697 -CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[13] origin:031-cmt-mmcm 28_697 -CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[14] origin:031-cmt-mmcm 29_696 -CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[15] origin:031-cmt-mmcm 28_696 -CMT_TOP_L_LOWER_B.MMCME2.SS_EN origin:031-cmt-mmcm 28_388 28_696 28_698 28_700 28_702 28_850 28_915 28_95 29_389 29_697 29_701 29_703 -CMT_TOP_L_LOWER_B.MMCME2.STARTUP_WAIT origin:031-cmt-mmcm 29_94 -CMT_TOP_L_LOWER_B.MMCME2.TABLE[0] origin:031-cmt-mmcm 29_389 -CMT_TOP_L_LOWER_B.MMCME2.TABLE[1] origin:031-cmt-mmcm 28_388 -CMT_TOP_L_LOWER_B.MMCME2.TABLE[2] origin:031-cmt-mmcm 29_387 -CMT_TOP_L_LOWER_B.MMCME2.TABLE[3] origin:031-cmt-mmcm 28_386 -CMT_TOP_L_LOWER_B.MMCME2.TABLE[4] origin:031-cmt-mmcm 29_385 -CMT_TOP_L_LOWER_B.MMCME2.TABLE[5] origin:031-cmt-mmcm 28_384 -CMT_TOP_L_LOWER_B.MMCME2.TABLE[6] origin:031-cmt-mmcm 29_395 -CMT_TOP_L_LOWER_B.MMCME2.TABLE[7] origin:031-cmt-mmcm 28_394 -CMT_TOP_L_LOWER_B.MMCME2.TABLE[8] origin:031-cmt-mmcm 29_393 -CMT_TOP_L_LOWER_B.MMCME2.TABLE[9] origin:031-cmt-mmcm 28_392 -CMT_TOP_L_LOWER_B.MMCME2.ZINV_PSEN origin:031-cmt-mmcm 28_110 -CMT_TOP_L_LOWER_B.MMCME2.ZINV_PSINCDEC origin:031-cmt-mmcm 29_110 -CMT_TOP_L_LOWER_B.MMCME2.ZINV_PWRDWN origin:031-cmt-mmcm 28_111 -CMT_TOP_L_LOWER_B.MMCME2.ZINV_RST origin:031-cmt-mmcm 29_111 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_956 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_956 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_955 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_955 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_954 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_954 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_959 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_959 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_958 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_958 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_957 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_957 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_953 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_953 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_952 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_952 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_951 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_951 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_950 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_950 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_949 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_949 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_948 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_945 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_945 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_944 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_946 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_946 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_947 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_947 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_948 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_944 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_940 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_940 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_939 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_939 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_938 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_938 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_943 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_943 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_942 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_942 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_941 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_941 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_937 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_937 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_936 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_936 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_935 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_935 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_934 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_934 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_933 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_933 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_932 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_929 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_929 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_928 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_930 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_930 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_931 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_931 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_932 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_928 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_924 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_924 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_923 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_923 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_922 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_922 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_927 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_927 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_926 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_926 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_925 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_925 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_921 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_921 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_920 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_920 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_919 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_919 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_918 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_918 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_917 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_917 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_916 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_913 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_913 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_912 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_914 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_914 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_915 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_915 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_916 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_912 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_908 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_908 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_907 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_907 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_906 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_906 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_911 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_911 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_910 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_910 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_909 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_909 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_905 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_905 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_904 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_904 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_903 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_903 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_902 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_902 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_901 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_901 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_900 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_897 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_897 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_896 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_898 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_898 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_899 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_899 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_900 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_896 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_892 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_892 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_891 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_891 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_890 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_890 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_895 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_895 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_894 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_894 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_893 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_893 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_889 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_889 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_888 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_888 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_887 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_887 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_886 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_886 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_885 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_885 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_884 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_881 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_881 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_880 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_882 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_882 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_883 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_883 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_884 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_880 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_972 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_972 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_971 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_971 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_970 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_970 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_975 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_975 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_974 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_974 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_973 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_973 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_969 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_969 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_968 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_968 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[0] origin:031-cmt-mmcm 29_967 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[1] origin:031-cmt-mmcm 28_967 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[2] origin:031-cmt-mmcm 29_966 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[3] origin:031-cmt-mmcm 28_966 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[4] origin:031-cmt-mmcm 29_965 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[5] origin:031-cmt-mmcm 28_965 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_EDGE[0] origin:031-cmt-mmcm 28_964 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_FRAC_WF_F[0] origin:031-cmt-mmcm 29_962 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_MX[0] origin:031-cmt-mmcm 29_963 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_MX[1] origin:031-cmt-mmcm 28_963 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_NO_COUNT[0] origin:031-cmt-mmcm 29_964 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[0] origin:031-cmt-mmcm 28_962 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[1] origin:031-cmt-mmcm 29_961 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[2] origin:031-cmt-mmcm 28_961 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_RESERVED[0] origin:031-cmt-mmcm 29_960 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_RESERVED[1] origin:031-cmt-mmcm 28_960 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_876 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_876 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_875 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_875 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_874 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_874 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_879 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_879 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_878 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_878 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_877 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_877 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_873 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_873 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_872 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_872 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[0] origin:031-cmt-mmcm 29_871 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[1] origin:031-cmt-mmcm 28_871 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[2] origin:031-cmt-mmcm 29_870 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[3] origin:031-cmt-mmcm 28_870 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[4] origin:031-cmt-mmcm 29_869 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[5] origin:031-cmt-mmcm 28_869 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_EDGE[0] origin:031-cmt-mmcm 28_868 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_FRAC_WF_F[0] origin:031-cmt-mmcm 29_866 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_MX[0] origin:031-cmt-mmcm 29_867 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_MX[1] origin:031-cmt-mmcm 28_867 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_NO_COUNT[0] origin:031-cmt-mmcm 29_868 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[0] origin:031-cmt-mmcm 28_866 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[1] origin:031-cmt-mmcm 29_865 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[2] origin:031-cmt-mmcm 28_865 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_RESERVED[0] origin:031-cmt-mmcm 29_864 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_RESERVED[1] origin:031-cmt-mmcm 28_864 -CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[0] origin:031-cmt-mmcm 29_399 -CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[1] origin:031-cmt-mmcm 28_399 -CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[2] origin:031-cmt-mmcm 29_398 -CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[3] origin:031-cmt-mmcm 28_398 -CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[4] origin:031-cmt-mmcm 29_397 -CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[5] origin:031-cmt-mmcm 28_397 -CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[6] origin:031-cmt-mmcm 29_396 -CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[7] origin:031-cmt-mmcm 28_396 -CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[8] origin:031-cmt-mmcm 28_395 -CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[9] origin:031-cmt-mmcm 29_394 -CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[10] origin:031-cmt-mmcm 28_393 -CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[11] origin:031-cmt-mmcm 29_392 -CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[0] origin:031-cmt-mmcm 29_391 -CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[1] origin:031-cmt-mmcm 28_391 -CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[2] origin:031-cmt-mmcm 29_390 -CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[3] origin:031-cmt-mmcm 28_390 -CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[4] origin:031-cmt-mmcm 28_389 -CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[5] origin:031-cmt-mmcm 29_388 -CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[6] origin:031-cmt-mmcm 28_387 -CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[7] origin:031-cmt-mmcm 29_386 -CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[8] origin:031-cmt-mmcm 28_385 -CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[9] origin:031-cmt-mmcm 29_384 -CMT_TOP_L_LOWER_B.MMCME2.LOCKREG1_RESERVED[0] origin:031-cmt-mmcm 29_826 -CMT_TOP_L_LOWER_B.MMCME2.LOCKREG1_RESERVED[1] origin:031-cmt-mmcm 28_826 -CMT_TOP_L_LOWER_B.MMCME2.LOCKREG1_RESERVED[2] origin:031-cmt-mmcm 29_825 -CMT_TOP_L_LOWER_B.MMCME2.LOCKREG1_RESERVED[3] origin:031-cmt-mmcm 28_825 -CMT_TOP_L_LOWER_B.MMCME2.LOCKREG1_RESERVED[4] origin:031-cmt-mmcm 29_824 -CMT_TOP_L_LOWER_B.MMCME2.LOCKREG1_RESERVED[5] origin:031-cmt-mmcm 28_824 -CMT_TOP_L_LOWER_B.MMCME2.LOCKREG2_RESERVED[0] origin:031-cmt-mmcm 28_816 -CMT_TOP_L_LOWER_B.MMCME2.LOCKREG3_RESERVED[0] origin:031-cmt-mmcm 28_808 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_860 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_860 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_859 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_859 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_858 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_858 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_863 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_863 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_862 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_862 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_861 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_861 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_857 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_857 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_856 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_856 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_855 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_855 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_854 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_854 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_853 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_853 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_852 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_849 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_849 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_848 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_850 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_850 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_851 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_851 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_852 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_848 +CMT_TOP_L_LOWER_B.MMCME2_ADV.COMP.Z_ZHOLD origin:031-cmt-mmcm 28_1020 28_979 +CMT_TOP_L_LOWER_B.MMCME2_ADV.COMP.ZHOLD origin:031-cmt-mmcm 28_1019 29_982 +CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_EDGE[0] origin:031-cmt-mmcm 28_841 +CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_HIGH_TIME[0] origin:031-cmt-mmcm 29_844 +CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_HIGH_TIME[1] origin:031-cmt-mmcm 28_844 +CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_HIGH_TIME[2] origin:031-cmt-mmcm 29_843 +CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_HIGH_TIME[3] origin:031-cmt-mmcm 28_843 +CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_HIGH_TIME[4] origin:031-cmt-mmcm 29_842 +CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_HIGH_TIME[5] origin:031-cmt-mmcm 28_842 +CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_LOW_TIME[0] origin:031-cmt-mmcm 29_847 +CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_LOW_TIME[1] origin:031-cmt-mmcm 28_847 +CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_LOW_TIME[2] origin:031-cmt-mmcm 29_846 +CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_LOW_TIME[3] origin:031-cmt-mmcm 28_846 +CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_LOW_TIME[4] origin:031-cmt-mmcm 29_845 +CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_LOW_TIME[5] origin:031-cmt-mmcm 28_845 +CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_NO_COUNT[0] origin:031-cmt-mmcm 29_841 +CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_RESERVED[0] origin:031-cmt-mmcm 29_840 +CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_RESERVED[1] origin:031-cmt-mmcm 28_840 +CMT_TOP_L_LOWER_B.MMCME2_ADV.IN_USE origin:031-cmt-mmcm 28_1007 28_18 28_21 28_22 28_23 28_24 28_25 28_27 28_28 28_31 28_32 28_33 28_34 28_36 28_37 28_38 28_39 28_40 28_428 28_429 28_430 28_433 28_434 28_44 28_46 28_466 28_47 28_48 28_488 28_49 28_492 28_50 28_51 28_52 28_54 28_63 28_65 28_66 28_70 28_72 28_73 28_75 28_77 28_772 28_773 28_774 28_78 28_787 28_976 28_978 28_989 28_991 29_1007 29_1018 29_16 29_18 29_22 29_25 29_28 29_31 29_34 29_35 29_36 29_37 29_39 29_40 29_41 29_42 29_427 29_428 29_431 29_432 29_433 29_44 29_45 29_46 29_463 29_47 29_48 29_51 29_52 29_56 29_57 29_60 29_64 29_65 29_66 29_67 29_68 29_70 29_71 29_72 29_73 29_75 29_76 29_77 29_771 29_772 29_775 29_78 29_789 29_833 29_836 29_839 29_95 29_977 29_981 29_987 29_990 29_991 +CMT_TOP_L_LOWER_B.MMCME2_ADV.INV_CLKINSEL origin:031-cmt-mmcm 29_109 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[0] origin:031-cmt-mmcm 29_823 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[1] origin:031-cmt-mmcm 28_823 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[2] origin:031-cmt-mmcm 29_822 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[3] origin:031-cmt-mmcm 28_822 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[4] origin:031-cmt-mmcm 29_821 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[5] origin:031-cmt-mmcm 28_821 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[6] origin:031-cmt-mmcm 29_820 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[7] origin:031-cmt-mmcm 28_820 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[8] origin:031-cmt-mmcm 29_819 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[9] origin:031-cmt-mmcm 28_819 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[10] origin:031-cmt-mmcm 29_815 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[11] origin:031-cmt-mmcm 28_815 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[12] origin:031-cmt-mmcm 29_814 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[13] origin:031-cmt-mmcm 28_814 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[14] origin:031-cmt-mmcm 29_813 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[15] origin:031-cmt-mmcm 28_813 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[16] origin:031-cmt-mmcm 29_812 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[17] origin:031-cmt-mmcm 28_812 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[18] origin:031-cmt-mmcm 29_811 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[19] origin:031-cmt-mmcm 28_811 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[20] origin:031-cmt-mmcm 29_831 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[21] origin:031-cmt-mmcm 28_831 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[22] origin:031-cmt-mmcm 29_830 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[23] origin:031-cmt-mmcm 28_830 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[24] origin:031-cmt-mmcm 29_829 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[25] origin:031-cmt-mmcm 28_829 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[26] origin:031-cmt-mmcm 29_828 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[27] origin:031-cmt-mmcm 28_828 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[28] origin:031-cmt-mmcm 29_827 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[29] origin:031-cmt-mmcm 28_827 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[30] origin:031-cmt-mmcm 29_818 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[31] origin:031-cmt-mmcm 28_818 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[32] origin:031-cmt-mmcm 29_817 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[33] origin:031-cmt-mmcm 28_817 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[34] origin:031-cmt-mmcm 29_816 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[35] origin:031-cmt-mmcm 29_810 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[36] origin:031-cmt-mmcm 28_810 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[37] origin:031-cmt-mmcm 29_809 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[38] origin:031-cmt-mmcm 28_809 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[39] origin:031-cmt-mmcm 29_808 +CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[0] origin:031-cmt-mmcm 29_703 +CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[1] origin:031-cmt-mmcm 28_703 +CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[2] origin:031-cmt-mmcm 29_702 +CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[3] origin:031-cmt-mmcm 28_702 +CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[4] origin:031-cmt-mmcm 29_701 +CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[5] origin:031-cmt-mmcm 28_701 +CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[6] origin:031-cmt-mmcm 29_700 +CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[7] origin:031-cmt-mmcm 28_700 +CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[8] origin:031-cmt-mmcm 29_699 +CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[9] origin:031-cmt-mmcm 28_699 +CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[10] origin:031-cmt-mmcm 29_698 +CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[11] origin:031-cmt-mmcm 28_698 +CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[12] origin:031-cmt-mmcm 29_697 +CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[13] origin:031-cmt-mmcm 28_697 +CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[14] origin:031-cmt-mmcm 29_696 +CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[15] origin:031-cmt-mmcm 28_696 +CMT_TOP_L_LOWER_B.MMCME2_ADV.SS_EN origin:031-cmt-mmcm 28_388 28_696 28_698 28_700 28_702 28_850 28_915 28_95 29_389 29_697 29_701 29_703 +CMT_TOP_L_LOWER_B.MMCME2_ADV.STARTUP_WAIT origin:031-cmt-mmcm 29_94 +CMT_TOP_L_LOWER_B.MMCME2_ADV.TABLE[0] origin:031-cmt-mmcm 29_389 +CMT_TOP_L_LOWER_B.MMCME2_ADV.TABLE[1] origin:031-cmt-mmcm 28_388 +CMT_TOP_L_LOWER_B.MMCME2_ADV.TABLE[2] origin:031-cmt-mmcm 29_387 +CMT_TOP_L_LOWER_B.MMCME2_ADV.TABLE[3] origin:031-cmt-mmcm 28_386 +CMT_TOP_L_LOWER_B.MMCME2_ADV.TABLE[4] origin:031-cmt-mmcm 29_385 +CMT_TOP_L_LOWER_B.MMCME2_ADV.TABLE[5] origin:031-cmt-mmcm 28_384 +CMT_TOP_L_LOWER_B.MMCME2_ADV.TABLE[6] origin:031-cmt-mmcm 29_395 +CMT_TOP_L_LOWER_B.MMCME2_ADV.TABLE[7] origin:031-cmt-mmcm 28_394 +CMT_TOP_L_LOWER_B.MMCME2_ADV.TABLE[8] origin:031-cmt-mmcm 29_393 +CMT_TOP_L_LOWER_B.MMCME2_ADV.TABLE[9] origin:031-cmt-mmcm 28_392 +CMT_TOP_L_LOWER_B.MMCME2_ADV.ZINV_PSEN origin:031-cmt-mmcm 28_110 +CMT_TOP_L_LOWER_B.MMCME2_ADV.ZINV_PSINCDEC origin:031-cmt-mmcm 29_110 +CMT_TOP_L_LOWER_B.MMCME2_ADV.ZINV_PWRDWN origin:031-cmt-mmcm 28_111 +CMT_TOP_L_LOWER_B.MMCME2_ADV.ZINV_RST origin:031-cmt-mmcm 29_111 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_956 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_956 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_955 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_955 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_954 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_954 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_959 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_959 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_958 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_958 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_957 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_957 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_953 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_953 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_952 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_952 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_951 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_951 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_950 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_950 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_949 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_949 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_948 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_945 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_945 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_944 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_946 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_946 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_947 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_947 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_948 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_944 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_940 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_940 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_939 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_939 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_938 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_938 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_943 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_943 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_942 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_942 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_941 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_941 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_937 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_937 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_936 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_936 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_935 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_935 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_934 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_934 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_933 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_933 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_932 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_929 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_929 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_928 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_930 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_930 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_931 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_931 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_932 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_928 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_924 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_924 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_923 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_923 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_922 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_922 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_927 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_927 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_926 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_926 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_925 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_925 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_921 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_921 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_920 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_920 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_919 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_919 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_918 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_918 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_917 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_917 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_916 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_913 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_913 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_912 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_914 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_914 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_915 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_915 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_916 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_912 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_908 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_908 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_907 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_907 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_906 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_906 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_911 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_911 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_910 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_910 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_909 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_909 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_905 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_905 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_904 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_904 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_903 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_903 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_902 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_902 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_901 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_901 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_900 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_897 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_897 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_896 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_898 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_898 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_899 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_899 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_900 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_896 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_892 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_892 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_891 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_891 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_890 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_890 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_895 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_895 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_894 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_894 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_893 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_893 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_889 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_889 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_888 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_888 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_887 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_887 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_886 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_886 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_885 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_885 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_884 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_881 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_881 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_880 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_882 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_882 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_883 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_883 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_884 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_880 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_972 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_972 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_971 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_971 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_970 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_970 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_975 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_975 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_974 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_974 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_973 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_973 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_969 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_969 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_968 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_968 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[0] origin:031-cmt-mmcm 29_967 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[1] origin:031-cmt-mmcm 28_967 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[2] origin:031-cmt-mmcm 29_966 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[3] origin:031-cmt-mmcm 28_966 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[4] origin:031-cmt-mmcm 29_965 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[5] origin:031-cmt-mmcm 28_965 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_EDGE[0] origin:031-cmt-mmcm 28_964 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_FRAC_WF_F[0] origin:031-cmt-mmcm 29_962 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_MX[0] origin:031-cmt-mmcm 29_963 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_MX[1] origin:031-cmt-mmcm 28_963 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_NO_COUNT[0] origin:031-cmt-mmcm 29_964 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[0] origin:031-cmt-mmcm 28_962 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[1] origin:031-cmt-mmcm 29_961 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[2] origin:031-cmt-mmcm 28_961 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_RESERVED[0] origin:031-cmt-mmcm 29_960 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_RESERVED[1] origin:031-cmt-mmcm 28_960 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_876 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_876 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_875 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_875 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_874 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_874 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_879 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_879 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_878 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_878 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_877 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_877 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_873 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_873 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_872 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_872 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[0] origin:031-cmt-mmcm 29_871 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[1] origin:031-cmt-mmcm 28_871 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[2] origin:031-cmt-mmcm 29_870 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[3] origin:031-cmt-mmcm 28_870 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[4] origin:031-cmt-mmcm 29_869 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[5] origin:031-cmt-mmcm 28_869 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_EDGE[0] origin:031-cmt-mmcm 28_868 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_FRAC_WF_F[0] origin:031-cmt-mmcm 29_866 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_MX[0] origin:031-cmt-mmcm 29_867 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_MX[1] origin:031-cmt-mmcm 28_867 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_NO_COUNT[0] origin:031-cmt-mmcm 29_868 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[0] origin:031-cmt-mmcm 28_866 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[1] origin:031-cmt-mmcm 29_865 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[2] origin:031-cmt-mmcm 28_865 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_RESERVED[0] origin:031-cmt-mmcm 29_864 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_RESERVED[1] origin:031-cmt-mmcm 28_864 +CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[0] origin:031-cmt-mmcm 29_399 +CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[1] origin:031-cmt-mmcm 28_399 +CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[2] origin:031-cmt-mmcm 29_398 +CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[3] origin:031-cmt-mmcm 28_398 +CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[4] origin:031-cmt-mmcm 29_397 +CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[5] origin:031-cmt-mmcm 28_397 +CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[6] origin:031-cmt-mmcm 29_396 +CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[7] origin:031-cmt-mmcm 28_396 +CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[8] origin:031-cmt-mmcm 28_395 +CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[9] origin:031-cmt-mmcm 29_394 +CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[10] origin:031-cmt-mmcm 28_393 +CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[11] origin:031-cmt-mmcm 29_392 +CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[0] origin:031-cmt-mmcm 29_391 +CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[1] origin:031-cmt-mmcm 28_391 +CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[2] origin:031-cmt-mmcm 29_390 +CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[3] origin:031-cmt-mmcm 28_390 +CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[4] origin:031-cmt-mmcm 28_389 +CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[5] origin:031-cmt-mmcm 29_388 +CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[6] origin:031-cmt-mmcm 28_387 +CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[7] origin:031-cmt-mmcm 29_386 +CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[8] origin:031-cmt-mmcm 28_385 +CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[9] origin:031-cmt-mmcm 29_384 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LOCKREG1_RESERVED[0] origin:031-cmt-mmcm 29_826 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LOCKREG1_RESERVED[1] origin:031-cmt-mmcm 28_826 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LOCKREG1_RESERVED[2] origin:031-cmt-mmcm 29_825 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LOCKREG1_RESERVED[3] origin:031-cmt-mmcm 28_825 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LOCKREG1_RESERVED[4] origin:031-cmt-mmcm 29_824 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LOCKREG1_RESERVED[5] origin:031-cmt-mmcm 28_824 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LOCKREG2_RESERVED[0] origin:031-cmt-mmcm 28_816 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LOCKREG3_RESERVED[0] origin:031-cmt-mmcm 28_808 diff --git a/kintex7/segbits_cmt_top_l_upper_t.db b/kintex7/segbits_cmt_top_l_upper_t.db index 4859101..c6958a3 100644 --- a/kintex7/segbits_cmt_top_l_upper_t.db +++ b/kintex7/segbits_cmt_top_l_upper_t.db @@ -21,346 +21,346 @@ CMT_TOP_L_UPPER_T.PLL_CLK_FREQ_BB0_NS_ACTIVE 29_00 29_09 29_17 CMT_TOP_L_UPPER_T.PLL_CLK_FREQ_BB1_NS_ACTIVE 28_01 29_10 29_18 CMT_TOP_L_UPPER_T.PLL_CLK_FREQ_BB2_NS_ACTIVE 29_01 29_11 29_19 CMT_TOP_L_UPPER_T.PLL_CLK_FREQ_BB3_NS_ACTIVE 28_02 29_12 29_20 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[0] 28_195 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[1] 29_195 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[2] 28_196 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[3] 29_196 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[4] 28_197 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[5] 29_197 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[0] 28_192 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[1] 29_192 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[2] 28_193 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[3] 29_193 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[4] 28_194 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[5] 29_194 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE[0] 28_198 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[0] 29_198 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[1] 28_199 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[2] 29_199 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[0] 28_200 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[1] 29_200 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[2] 28_201 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[3] 29_201 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[4] 28_202 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[5] 29_202 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_EDGE[0] 29_203 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[0] 28_206 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[1] 29_206 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[2] 28_207 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC_EN[0] 29_205 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC_WF_R[0] 28_205 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_MX[0] 28_204 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_MX[1] 29_204 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_NO_COUNT[0] 28_203 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_RESERVED[0] 29_207 -CMT_TOP_L_UPPER_T.PLLE2.COMPENSATION.Z_ZHOLD_OR_CLKIN_BUF 29_35 29_76 -CMT_TOP_L_UPPER_T.PLLE2.COMPENSATION.ZHOLD_NO_CLKIN_BUF 28_73 29_36 -CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_EDGE[0] 29_214 -CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[0] 28_211 -CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[1] 29_211 -CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[2] 28_212 -CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[3] 29_212 -CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[4] 28_213 -CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[5] 29_213 -CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[0] 28_208 -CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[1] 29_208 -CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[2] 28_209 -CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[3] 29_209 -CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[4] 28_210 -CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[5] 29_210 -CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_NO_COUNT[0] 28_214 -CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_RESERVED[0] 28_215 -CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_RESERVED[1] 29_215 -CMT_TOP_L_UPPER_T.PLLE2.IN_USE 28_37 28_48 28_74 28_78 28_216 28_219 28_222 28_266 28_280 28_283 28_284 28_592 28_622 28_623 28_624 28_627 28_628 28_768 28_785 28_786 28_787 28_788 28_790 28_791 28_792 28_793 28_795 28_796 28_797 28_798 28_799 28_803 28_806 28_807 28_811 28_812 28_815 28_816 28_817 28_818 28_819 28_821 28_822 28_823 28_824 28_826 28_827 28_828 28_829 28_832 28_835 28_838 28_841 28_845 28_847 29_48 29_77 29_78 29_79 29_268 29_281 29_282 29_283 29_563 29_567 29_589 29_621 29_622 29_625 29_626 29_627 29_785 29_786 29_788 29_790 29_791 29_793 29_797 29_798 29_800 29_809 29_811 29_812 29_813 29_814 29_815 29_816 29_817 29_819 29_823 29_824 29_825 29_826 29_827 29_829 29_830 29_831 29_832 29_835 29_836 29_838 29_839 29_840 29_841 29_842 29_845 -CMT_TOP_L_UPPER_T.PLLE2.INV_CLKINSEL 28_754 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[0] 28_232 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[1] 29_232 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[2] 28_233 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[3] 29_233 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[4] 28_234 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[5] 29_234 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[6] 28_235 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[7] 29_235 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[8] 28_236 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[9] 29_236 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[10] 28_240 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[11] 29_240 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[12] 28_241 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[13] 29_241 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[14] 28_242 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[15] 29_242 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[16] 28_243 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[17] 29_243 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[18] 28_244 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[19] 29_244 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[20] 28_224 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[21] 29_224 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[22] 28_225 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[23] 29_225 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[24] 28_226 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[25] 29_226 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[26] 28_227 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[27] 29_227 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[28] 28_228 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[29] 29_228 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[30] 28_237 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[31] 29_237 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[32] 28_238 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[33] 29_238 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[34] 28_239 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[35] 28_245 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[36] 29_245 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[37] 28_246 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[38] 29_246 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[39] 28_247 -CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[0] 28_352 -CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[1] 29_352 -CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[2] 28_353 -CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[3] 29_353 -CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[4] 28_354 -CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[5] 29_354 -CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[6] 28_355 -CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[7] 29_355 -CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[8] 28_356 -CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[9] 29_356 -CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[10] 28_357 -CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[11] 29_357 -CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[12] 28_358 -CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[13] 29_358 -CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[14] 28_359 -CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[15] 29_359 -CMT_TOP_L_UPPER_T.PLLE2.STARTUP_WAIT 28_769 -CMT_TOP_L_UPPER_T.PLLE2.TABLE[0] 28_666 -CMT_TOP_L_UPPER_T.PLLE2.TABLE[1] 29_667 -CMT_TOP_L_UPPER_T.PLLE2.TABLE[2] 28_668 -CMT_TOP_L_UPPER_T.PLLE2.TABLE[3] 29_669 -CMT_TOP_L_UPPER_T.PLLE2.TABLE[4] 28_670 -CMT_TOP_L_UPPER_T.PLLE2.TABLE[5] 29_671 -CMT_TOP_L_UPPER_T.PLLE2.TABLE[6] 28_660 -CMT_TOP_L_UPPER_T.PLLE2.TABLE[7] 29_661 -CMT_TOP_L_UPPER_T.PLLE2.TABLE[8] 28_662 -CMT_TOP_L_UPPER_T.PLLE2.TABLE[9] 29_663 -CMT_TOP_L_UPPER_T.PLLE2.ZINV_PWRDWN 29_752 -CMT_TOP_L_UPPER_T.PLLE2.ZINV_RST 28_752 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[0] 28_99 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[1] 29_99 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[2] 28_100 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[3] 29_100 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[4] 28_101 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[5] 29_101 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[0] 28_96 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[1] 29_96 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[2] 28_97 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[3] 29_97 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[4] 28_98 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[5] 29_98 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_OUTPUT_ENABLE[0] 28_102 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[0] 29_102 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[1] 28_103 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[2] 29_103 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[0] 28_104 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[1] 29_104 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[2] 28_105 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[3] 29_105 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[4] 28_106 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[5] 29_106 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_EDGE[0] 29_107 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[0] 28_110 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[1] 29_110 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[2] 28_111 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC_EN[0] 29_109 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC_WF_R[0] 28_109 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_MX[0] 28_108 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_MX[1] 29_108 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_NO_COUNT[0] 28_107 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_RESERVED[0] 29_111 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[0] 28_115 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[1] 29_115 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[2] 28_116 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[3] 29_116 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[4] 28_117 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[5] 29_117 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[0] 28_112 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[1] 29_112 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[2] 28_113 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[3] 29_113 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[4] 28_114 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[5] 29_114 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_OUTPUT_ENABLE[0] 28_118 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[0] 29_118 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[1] 28_119 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[2] 29_119 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[0] 28_120 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[1] 29_120 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[2] 28_121 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[3] 29_121 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[4] 28_122 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[5] 29_122 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_EDGE[0] 29_123 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[0] 28_126 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[1] 29_126 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[2] 28_127 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC_EN[0] 29_125 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC_WF_R[0] 28_125 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_MX[0] 28_124 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_MX[1] 29_124 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_NO_COUNT[0] 28_123 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_RESERVED[0] 29_127 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[0] 28_131 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[1] 29_131 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[2] 28_132 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[3] 29_132 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[4] 28_133 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[5] 29_133 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[0] 28_128 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[1] 29_128 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[2] 28_129 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[3] 29_129 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[4] 28_130 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[5] 29_130 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_OUTPUT_ENABLE[0] 28_134 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[0] 29_134 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[1] 28_135 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[2] 29_135 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[0] 28_136 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[1] 29_136 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[2] 28_137 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[3] 29_137 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[4] 28_138 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[5] 29_138 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_EDGE[0] 29_139 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[0] 28_142 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[1] 29_142 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[2] 28_143 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC_EN[0] 29_141 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC_WF_R[0] 28_141 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_MX[0] 28_140 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_MX[1] 29_140 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_NO_COUNT[0] 28_139 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_RESERVED[0] 29_143 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[0] 28_147 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[1] 29_147 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[2] 28_148 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[3] 29_148 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[4] 28_149 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[5] 29_149 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[0] 28_144 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[1] 29_144 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[2] 28_145 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[3] 29_145 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[4] 28_146 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[5] 29_146 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_OUTPUT_ENABLE[0] 28_150 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[0] 29_150 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[1] 28_151 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[2] 29_151 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[0] 28_152 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[1] 29_152 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[2] 28_153 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[3] 29_153 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[4] 28_154 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[5] 29_154 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_EDGE[0] 29_155 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[0] 28_158 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[1] 29_158 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[2] 28_159 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC_EN[0] 29_157 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC_WF_R[0] 28_157 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_MX[0] 28_156 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_MX[1] 29_156 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_NO_COUNT[0] 28_155 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_RESERVED[0] 29_159 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[0] 28_163 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[1] 29_163 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[2] 28_164 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[3] 29_164 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[4] 28_165 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[5] 29_165 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[0] 28_160 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[1] 29_160 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[2] 28_161 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[3] 29_161 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[4] 28_162 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[5] 29_162 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_OUTPUT_ENABLE[0] 28_166 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[0] 29_166 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[1] 28_167 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[2] 29_167 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[0] 28_168 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[1] 29_168 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[2] 28_169 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[3] 29_169 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[4] 28_170 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[5] 29_170 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_EDGE[0] 29_171 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[0] 28_174 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[1] 29_174 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[2] 28_175 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC_EN[0] 29_173 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC_WF_R[0] 28_173 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_MX[0] 28_172 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_MX[1] 29_172 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_NO_COUNT[0] 28_171 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_RESERVED[0] 29_175 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[0] 28_83 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[1] 29_83 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[2] 28_84 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[3] 29_84 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[4] 28_85 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[5] 29_85 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[0] 28_80 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[1] 29_80 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[2] 28_81 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[3] 29_81 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[4] 28_82 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[5] 29_82 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_OUTPUT_ENABLE[0] 28_86 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[0] 29_86 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[1] 28_87 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[2] 29_87 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[0] 28_88 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[1] 29_88 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[2] 28_89 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[3] 29_89 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[4] 28_90 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[5] 29_90 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_EDGE[0] 29_91 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[0] 28_94 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[1] 29_94 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[2] 28_95 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC_EN[0] 29_93 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC_WF_R[0] 28_93 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_MX[0] 28_92 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_MX[1] 29_92 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_NO_COUNT[0] 28_91 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_RESERVED[0] 29_95 -CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[0] 28_656 -CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[1] 29_656 -CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[2] 28_657 -CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[3] 29_657 -CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[4] 28_658 -CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[5] 29_658 -CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[6] 28_659 -CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[7] 29_659 -CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[8] 29_660 -CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[9] 28_661 -CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[10] 29_662 -CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[11] 28_663 -CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[0] 28_664 -CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[1] 29_664 -CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[2] 28_665 -CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[3] 29_665 -CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[4] 29_666 -CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[5] 28_667 -CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[6] 29_668 -CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[7] 28_669 -CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[8] 29_670 -CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[9] 28_671 -CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[0] 28_229 -CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[1] 29_229 -CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[2] 28_230 -CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[3] 29_230 -CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[4] 28_231 -CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[5] 29_231 -CMT_TOP_L_UPPER_T.PLLE2.LOCKREG2_RESERVED[0] 29_239 -CMT_TOP_L_UPPER_T.PLLE2.LOCKREG3_RESERVED[0] 29_247 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[0] 28_195 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[1] 29_195 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[2] 28_196 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[3] 29_196 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[4] 28_197 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[5] 29_197 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[0] 28_192 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[1] 29_192 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[2] 28_193 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[3] 29_193 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[4] 28_194 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[5] 29_194 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE[0] 28_198 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_PHASE_MUX[0] 29_198 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_PHASE_MUX[1] 28_199 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_PHASE_MUX[2] 29_199 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[0] 28_200 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[1] 29_200 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[2] 28_201 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[3] 29_201 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[4] 28_202 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[5] 29_202 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_EDGE[0] 29_203 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_FRAC[0] 28_206 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_FRAC[1] 29_206 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_FRAC[2] 28_207 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_FRAC_EN[0] 29_205 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_FRAC_WF_R[0] 28_205 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_MX[0] 28_204 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_MX[1] 29_204 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_NO_COUNT[0] 28_203 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_RESERVED[0] 29_207 +CMT_TOP_L_UPPER_T.PLLE2_ADV.COMPENSATION.Z_ZHOLD_OR_CLKIN_BUF 29_35 29_76 +CMT_TOP_L_UPPER_T.PLLE2_ADV.COMPENSATION.ZHOLD_NO_CLKIN_BUF 28_73 29_36 +CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_EDGE[0] 29_214 +CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_HIGH_TIME[0] 28_211 +CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_HIGH_TIME[1] 29_211 +CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_HIGH_TIME[2] 28_212 +CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_HIGH_TIME[3] 29_212 +CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_HIGH_TIME[4] 28_213 +CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_HIGH_TIME[5] 29_213 +CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_LOW_TIME[0] 28_208 +CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_LOW_TIME[1] 29_208 +CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_LOW_TIME[2] 28_209 +CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_LOW_TIME[3] 29_209 +CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_LOW_TIME[4] 28_210 +CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_LOW_TIME[5] 29_210 +CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_NO_COUNT[0] 28_214 +CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_RESERVED[0] 28_215 +CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_RESERVED[1] 29_215 +CMT_TOP_L_UPPER_T.PLLE2_ADV.IN_USE 28_37 28_48 28_74 28_78 28_216 28_219 28_222 28_266 28_280 28_283 28_284 28_592 28_622 28_623 28_624 28_627 28_628 28_768 28_785 28_786 28_787 28_788 28_790 28_791 28_792 28_793 28_795 28_796 28_797 28_798 28_799 28_803 28_806 28_807 28_811 28_812 28_815 28_816 28_817 28_818 28_819 28_821 28_822 28_823 28_824 28_826 28_827 28_828 28_829 28_832 28_835 28_838 28_841 28_845 28_847 29_48 29_77 29_78 29_79 29_268 29_281 29_282 29_283 29_563 29_567 29_589 29_621 29_622 29_625 29_626 29_627 29_785 29_786 29_788 29_790 29_791 29_793 29_797 29_798 29_800 29_809 29_811 29_812 29_813 29_814 29_815 29_816 29_817 29_819 29_823 29_824 29_825 29_826 29_827 29_829 29_830 29_831 29_832 29_835 29_836 29_838 29_839 29_840 29_841 29_842 29_845 +CMT_TOP_L_UPPER_T.PLLE2_ADV.INV_CLKINSEL 28_754 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[0] 28_232 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[1] 29_232 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[2] 28_233 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[3] 29_233 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[4] 28_234 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[5] 29_234 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[6] 28_235 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[7] 29_235 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[8] 28_236 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[9] 29_236 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[10] 28_240 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[11] 29_240 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[12] 28_241 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[13] 29_241 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[14] 28_242 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[15] 29_242 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[16] 28_243 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[17] 29_243 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[18] 28_244 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[19] 29_244 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[20] 28_224 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[21] 29_224 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[22] 28_225 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[23] 29_225 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[24] 28_226 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[25] 29_226 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[26] 28_227 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[27] 29_227 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[28] 28_228 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[29] 29_228 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[30] 28_237 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[31] 29_237 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[32] 28_238 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[33] 29_238 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[34] 28_239 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[35] 28_245 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[36] 29_245 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[37] 28_246 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[38] 29_246 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[39] 28_247 +CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[0] 28_352 +CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[1] 29_352 +CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[2] 28_353 +CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[3] 29_353 +CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[4] 28_354 +CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[5] 29_354 +CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[6] 28_355 +CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[7] 29_355 +CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[8] 28_356 +CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[9] 29_356 +CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[10] 28_357 +CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[11] 29_357 +CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[12] 28_358 +CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[13] 29_358 +CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[14] 28_359 +CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[15] 29_359 +CMT_TOP_L_UPPER_T.PLLE2_ADV.STARTUP_WAIT 28_769 +CMT_TOP_L_UPPER_T.PLLE2_ADV.TABLE[0] 28_666 +CMT_TOP_L_UPPER_T.PLLE2_ADV.TABLE[1] 29_667 +CMT_TOP_L_UPPER_T.PLLE2_ADV.TABLE[2] 28_668 +CMT_TOP_L_UPPER_T.PLLE2_ADV.TABLE[3] 29_669 +CMT_TOP_L_UPPER_T.PLLE2_ADV.TABLE[4] 28_670 +CMT_TOP_L_UPPER_T.PLLE2_ADV.TABLE[5] 29_671 +CMT_TOP_L_UPPER_T.PLLE2_ADV.TABLE[6] 28_660 +CMT_TOP_L_UPPER_T.PLLE2_ADV.TABLE[7] 29_661 +CMT_TOP_L_UPPER_T.PLLE2_ADV.TABLE[8] 28_662 +CMT_TOP_L_UPPER_T.PLLE2_ADV.TABLE[9] 29_663 +CMT_TOP_L_UPPER_T.PLLE2_ADV.ZINV_PWRDWN 29_752 +CMT_TOP_L_UPPER_T.PLLE2_ADV.ZINV_RST 28_752 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[0] 28_99 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[1] 29_99 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[2] 28_100 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[3] 29_100 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[4] 28_101 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[5] 29_101 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[0] 28_96 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[1] 29_96 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[2] 28_97 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[3] 29_97 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[4] 28_98 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[5] 29_98 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_OUTPUT_ENABLE[0] 28_102 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_PHASE_MUX[0] 29_102 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_PHASE_MUX[1] 28_103 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_PHASE_MUX[2] 29_103 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[0] 28_104 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[1] 29_104 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[2] 28_105 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[3] 29_105 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[4] 28_106 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[5] 29_106 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_EDGE[0] 29_107 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_FRAC[0] 28_110 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_FRAC[1] 29_110 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_FRAC[2] 28_111 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_FRAC_EN[0] 29_109 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_FRAC_WF_R[0] 28_109 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_MX[0] 28_108 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_MX[1] 29_108 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_NO_COUNT[0] 28_107 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_RESERVED[0] 29_111 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[0] 28_115 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[1] 29_115 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[2] 28_116 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[3] 29_116 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[4] 28_117 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[5] 29_117 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[0] 28_112 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[1] 29_112 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[2] 28_113 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[3] 29_113 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[4] 28_114 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[5] 29_114 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_OUTPUT_ENABLE[0] 28_118 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_PHASE_MUX[0] 29_118 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_PHASE_MUX[1] 28_119 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_PHASE_MUX[2] 29_119 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[0] 28_120 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[1] 29_120 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[2] 28_121 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[3] 29_121 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[4] 28_122 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[5] 29_122 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_EDGE[0] 29_123 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_FRAC[0] 28_126 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_FRAC[1] 29_126 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_FRAC[2] 28_127 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_FRAC_EN[0] 29_125 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_FRAC_WF_R[0] 28_125 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_MX[0] 28_124 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_MX[1] 29_124 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_NO_COUNT[0] 28_123 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_RESERVED[0] 29_127 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[0] 28_131 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[1] 29_131 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[2] 28_132 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[3] 29_132 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[4] 28_133 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[5] 29_133 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[0] 28_128 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[1] 29_128 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[2] 28_129 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[3] 29_129 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[4] 28_130 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[5] 29_130 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_OUTPUT_ENABLE[0] 28_134 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_PHASE_MUX[0] 29_134 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_PHASE_MUX[1] 28_135 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_PHASE_MUX[2] 29_135 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[0] 28_136 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[1] 29_136 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[2] 28_137 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[3] 29_137 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[4] 28_138 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[5] 29_138 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_EDGE[0] 29_139 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_FRAC[0] 28_142 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_FRAC[1] 29_142 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_FRAC[2] 28_143 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_FRAC_EN[0] 29_141 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_FRAC_WF_R[0] 28_141 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_MX[0] 28_140 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_MX[1] 29_140 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_NO_COUNT[0] 28_139 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_RESERVED[0] 29_143 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[0] 28_147 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[1] 29_147 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[2] 28_148 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[3] 29_148 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[4] 28_149 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[5] 29_149 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[0] 28_144 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[1] 29_144 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[2] 28_145 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[3] 29_145 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[4] 28_146 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[5] 29_146 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_OUTPUT_ENABLE[0] 28_150 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_PHASE_MUX[0] 29_150 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_PHASE_MUX[1] 28_151 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_PHASE_MUX[2] 29_151 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[0] 28_152 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[1] 29_152 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[2] 28_153 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[3] 29_153 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[4] 28_154 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[5] 29_154 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_EDGE[0] 29_155 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_FRAC[0] 28_158 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_FRAC[1] 29_158 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_FRAC[2] 28_159 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_FRAC_EN[0] 29_157 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_FRAC_WF_R[0] 28_157 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_MX[0] 28_156 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_MX[1] 29_156 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_NO_COUNT[0] 28_155 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_RESERVED[0] 29_159 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[0] 28_163 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[1] 29_163 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[2] 28_164 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[3] 29_164 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[4] 28_165 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[5] 29_165 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[0] 28_160 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[1] 29_160 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[2] 28_161 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[3] 29_161 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[4] 28_162 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[5] 29_162 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_OUTPUT_ENABLE[0] 28_166 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_PHASE_MUX[0] 29_166 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_PHASE_MUX[1] 28_167 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_PHASE_MUX[2] 29_167 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[0] 28_168 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[1] 29_168 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[2] 28_169 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[3] 29_169 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[4] 28_170 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[5] 29_170 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_EDGE[0] 29_171 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_FRAC[0] 28_174 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_FRAC[1] 29_174 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_FRAC[2] 28_175 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_FRAC_EN[0] 29_173 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_FRAC_WF_R[0] 28_173 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_MX[0] 28_172 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_MX[1] 29_172 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_NO_COUNT[0] 28_171 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_RESERVED[0] 29_175 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[0] 28_83 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[1] 29_83 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[2] 28_84 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[3] 29_84 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[4] 28_85 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[5] 29_85 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[0] 28_80 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[1] 29_80 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[2] 28_81 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[3] 29_81 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[4] 28_82 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[5] 29_82 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_OUTPUT_ENABLE[0] 28_86 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_PHASE_MUX[0] 29_86 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_PHASE_MUX[1] 28_87 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_PHASE_MUX[2] 29_87 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_DELAY_TIME[0] 28_88 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_DELAY_TIME[1] 29_88 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_DELAY_TIME[2] 28_89 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_DELAY_TIME[3] 29_89 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_DELAY_TIME[4] 28_90 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_DELAY_TIME[5] 29_90 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_EDGE[0] 29_91 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_FRAC[0] 28_94 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_FRAC[1] 29_94 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_FRAC[2] 28_95 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_FRAC_EN[0] 29_93 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_FRAC_WF_R[0] 28_93 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_MX[0] 28_92 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_MX[1] 29_92 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_NO_COUNT[0] 28_91 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_RESERVED[0] 29_95 +CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[0] 28_656 +CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[1] 29_656 +CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[2] 28_657 +CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[3] 29_657 +CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[4] 28_658 +CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[5] 29_658 +CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[6] 28_659 +CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[7] 29_659 +CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[8] 29_660 +CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[9] 28_661 +CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[10] 29_662 +CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[11] 28_663 +CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[0] 28_664 +CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[1] 29_664 +CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[2] 28_665 +CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[3] 29_665 +CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[4] 29_666 +CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[5] 28_667 +CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[6] 29_668 +CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[7] 28_669 +CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[8] 29_670 +CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[9] 28_671 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LOCKREG1_RESERVED[0] 28_229 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LOCKREG1_RESERVED[1] 29_229 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LOCKREG1_RESERVED[2] 28_230 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LOCKREG1_RESERVED[3] 29_230 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LOCKREG1_RESERVED[4] 28_231 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LOCKREG1_RESERVED[5] 29_231 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LOCKREG2_RESERVED[0] 29_239 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LOCKREG3_RESERVED[0] 29_247 diff --git a/kintex7/segbits_cmt_top_l_upper_t.origin_info.db b/kintex7/segbits_cmt_top_l_upper_t.origin_info.db index bfa0faf..12b35bd 100644 --- a/kintex7/segbits_cmt_top_l_upper_t.origin_info.db +++ b/kintex7/segbits_cmt_top_l_upper_t.origin_info.db @@ -21,346 +21,346 @@ CMT_TOP_L_UPPER_T.PLL_CLK_FREQ_BB0_NS_ACTIVE origin:034-cmt-pll-pips 29_00 29_09 CMT_TOP_L_UPPER_T.PLL_CLK_FREQ_BB1_NS_ACTIVE origin:034-cmt-pll-pips 28_01 29_10 29_18 CMT_TOP_L_UPPER_T.PLL_CLK_FREQ_BB2_NS_ACTIVE origin:034-cmt-pll-pips 29_01 29_11 29_19 CMT_TOP_L_UPPER_T.PLL_CLK_FREQ_BB3_NS_ACTIVE origin:034-cmt-pll-pips 28_02 29_12 29_20 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_195 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_195 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_196 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_196 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_197 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_197 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_192 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_192 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_193 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_193 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_194 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_194 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_198 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_198 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_199 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_199 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_200 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_200 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_201 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_201 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_202 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_202 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_203 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_206 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_206 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_207 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_205 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_205 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_MX[0] origin:032-cmt-pll 28_204 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_MX[1] origin:032-cmt-pll 29_204 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_203 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_207 -CMT_TOP_L_UPPER_T.PLLE2.COMPENSATION.Z_ZHOLD_OR_CLKIN_BUF origin:032-cmt-pll 29_35 29_76 -CMT_TOP_L_UPPER_T.PLLE2.COMPENSATION.ZHOLD_NO_CLKIN_BUF origin:032-cmt-pll 28_73 29_36 -CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_EDGE[0] origin:032-cmt-pll 29_214 -CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[0] origin:032-cmt-pll 28_211 -CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[1] origin:032-cmt-pll 29_211 -CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[2] origin:032-cmt-pll 28_212 -CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[3] origin:032-cmt-pll 29_212 -CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[4] origin:032-cmt-pll 28_213 -CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[5] origin:032-cmt-pll 29_213 -CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[0] origin:032-cmt-pll 28_208 -CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[1] origin:032-cmt-pll 29_208 -CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[2] origin:032-cmt-pll 28_209 -CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[3] origin:032-cmt-pll 29_209 -CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[4] origin:032-cmt-pll 28_210 -CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[5] origin:032-cmt-pll 29_210 -CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_NO_COUNT[0] origin:032-cmt-pll 28_214 -CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_RESERVED[0] origin:032-cmt-pll 28_215 -CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_RESERVED[1] origin:032-cmt-pll 29_215 -CMT_TOP_L_UPPER_T.PLLE2.IN_USE origin:032-cmt-pll 28_216 28_219 28_222 28_266 28_280 28_283 28_284 28_37 28_48 28_592 28_622 28_623 28_624 28_627 28_628 28_74 28_768 28_78 28_785 28_786 28_787 28_788 28_790 28_791 28_792 28_793 28_795 28_796 28_797 28_798 28_799 28_803 28_806 28_807 28_811 28_812 28_815 28_816 28_817 28_818 28_819 28_821 28_822 28_823 28_824 28_826 28_827 28_828 28_829 28_832 28_835 28_838 28_841 28_845 28_847 29_268 29_281 29_282 29_283 29_48 29_563 29_567 29_589 29_621 29_622 29_625 29_626 29_627 29_77 29_78 29_785 29_786 29_788 29_79 29_790 29_791 29_793 29_797 29_798 29_800 29_809 29_811 29_812 29_813 29_814 29_815 29_816 29_817 29_819 29_823 29_824 29_825 29_826 29_827 29_829 29_830 29_831 29_832 29_835 29_836 29_838 29_839 29_840 29_841 29_842 29_845 -CMT_TOP_L_UPPER_T.PLLE2.INV_CLKINSEL origin:032-cmt-pll 28_754 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[0] origin:032-cmt-pll 28_232 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[1] origin:032-cmt-pll 29_232 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[2] origin:032-cmt-pll 28_233 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[3] origin:032-cmt-pll 29_233 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[4] origin:032-cmt-pll 28_234 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[5] origin:032-cmt-pll 29_234 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[6] origin:032-cmt-pll 28_235 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[7] origin:032-cmt-pll 29_235 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[8] origin:032-cmt-pll 28_236 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[9] origin:032-cmt-pll 29_236 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[10] origin:032-cmt-pll 28_240 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[11] origin:032-cmt-pll 29_240 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[12] origin:032-cmt-pll 28_241 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[13] origin:032-cmt-pll 29_241 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[14] origin:032-cmt-pll 28_242 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[15] origin:032-cmt-pll 29_242 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[16] origin:032-cmt-pll 28_243 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[17] origin:032-cmt-pll 29_243 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[18] origin:032-cmt-pll 28_244 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[19] origin:032-cmt-pll 29_244 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[20] origin:032-cmt-pll 28_224 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[21] origin:032-cmt-pll 29_224 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[22] origin:032-cmt-pll 28_225 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[23] origin:032-cmt-pll 29_225 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[24] origin:032-cmt-pll 28_226 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[25] origin:032-cmt-pll 29_226 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[26] origin:032-cmt-pll 28_227 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[27] origin:032-cmt-pll 29_227 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[28] origin:032-cmt-pll 28_228 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[29] origin:032-cmt-pll 29_228 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[30] origin:032-cmt-pll 28_237 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[31] origin:032-cmt-pll 29_237 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[32] origin:032-cmt-pll 28_238 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[33] origin:032-cmt-pll 29_238 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[34] origin:032-cmt-pll 28_239 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[35] origin:032-cmt-pll 28_245 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[36] origin:032-cmt-pll 29_245 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[37] origin:032-cmt-pll 28_246 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[38] origin:032-cmt-pll 29_246 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[39] origin:032-cmt-pll 28_247 -CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[0] origin:032-cmt-pll 28_352 -CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[1] origin:032-cmt-pll 29_352 -CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[2] origin:032-cmt-pll 28_353 -CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[3] origin:032-cmt-pll 29_353 -CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[4] origin:032-cmt-pll 28_354 -CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[5] origin:032-cmt-pll 29_354 -CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[6] origin:032-cmt-pll 28_355 -CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[7] origin:032-cmt-pll 29_355 -CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[8] origin:032-cmt-pll 28_356 -CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[9] origin:032-cmt-pll 29_356 -CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[10] origin:032-cmt-pll 28_357 -CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[11] origin:032-cmt-pll 29_357 -CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[12] origin:032-cmt-pll 28_358 -CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[13] origin:032-cmt-pll 29_358 -CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[14] origin:032-cmt-pll 28_359 -CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[15] origin:032-cmt-pll 29_359 -CMT_TOP_L_UPPER_T.PLLE2.STARTUP_WAIT origin:032-cmt-pll 28_769 -CMT_TOP_L_UPPER_T.PLLE2.TABLE[0] origin:032-cmt-pll 28_666 -CMT_TOP_L_UPPER_T.PLLE2.TABLE[1] origin:032-cmt-pll 29_667 -CMT_TOP_L_UPPER_T.PLLE2.TABLE[2] origin:032-cmt-pll 28_668 -CMT_TOP_L_UPPER_T.PLLE2.TABLE[3] origin:032-cmt-pll 29_669 -CMT_TOP_L_UPPER_T.PLLE2.TABLE[4] origin:032-cmt-pll 28_670 -CMT_TOP_L_UPPER_T.PLLE2.TABLE[5] origin:032-cmt-pll 29_671 -CMT_TOP_L_UPPER_T.PLLE2.TABLE[6] origin:032-cmt-pll 28_660 -CMT_TOP_L_UPPER_T.PLLE2.TABLE[7] origin:032-cmt-pll 29_661 -CMT_TOP_L_UPPER_T.PLLE2.TABLE[8] origin:032-cmt-pll 28_662 -CMT_TOP_L_UPPER_T.PLLE2.TABLE[9] origin:032-cmt-pll 29_663 -CMT_TOP_L_UPPER_T.PLLE2.ZINV_PWRDWN origin:032-cmt-pll 29_752 -CMT_TOP_L_UPPER_T.PLLE2.ZINV_RST origin:032-cmt-pll 28_752 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_99 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_99 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_100 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_100 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_101 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_101 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_96 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_96 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_97 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_97 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_98 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_98 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_102 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_102 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_103 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_103 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_104 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_104 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_105 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_105 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_106 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_106 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_107 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_110 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_110 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_111 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_109 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_109 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_MX[0] origin:032-cmt-pll 28_108 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_MX[1] origin:032-cmt-pll 29_108 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_107 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_111 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_115 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_115 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_116 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_116 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_117 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_117 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_112 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_112 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_113 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_113 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_114 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_114 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_118 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_118 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_119 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_119 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_120 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_120 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_121 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_121 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_122 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_122 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_123 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_126 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_126 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_127 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_125 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_125 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_MX[0] origin:032-cmt-pll 28_124 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_MX[1] origin:032-cmt-pll 29_124 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_123 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_127 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_131 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_131 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_132 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_132 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_133 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_133 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_128 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_128 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_129 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_129 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_130 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_130 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_134 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_134 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_135 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_135 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_136 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_136 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_137 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_137 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_138 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_138 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_139 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_142 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_142 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_143 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_141 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_141 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_MX[0] origin:032-cmt-pll 28_140 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_MX[1] origin:032-cmt-pll 29_140 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_139 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_143 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_147 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_147 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_148 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_148 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_149 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_149 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_144 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_144 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_145 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_145 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_146 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_146 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_150 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_150 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_151 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_151 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_152 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_152 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_153 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_153 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_154 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_154 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_155 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_158 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_158 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_159 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_157 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_157 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_MX[0] origin:032-cmt-pll 28_156 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_MX[1] origin:032-cmt-pll 29_156 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_155 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_159 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_163 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_163 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_164 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_164 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_165 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_165 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_160 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_160 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_161 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_161 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_162 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_162 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_166 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_166 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_167 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_167 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_168 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_168 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_169 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_169 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_170 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_170 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_171 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_174 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_174 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_175 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_173 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_173 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_MX[0] origin:032-cmt-pll 28_172 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_MX[1] origin:032-cmt-pll 29_172 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_171 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_175 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_83 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_83 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_84 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_84 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_85 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_85 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_80 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_80 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_81 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_81 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_82 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_82 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_86 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_86 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_87 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_87 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_88 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_88 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_89 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_89 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_90 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_90 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_91 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_94 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_94 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_95 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_93 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_93 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_MX[0] origin:032-cmt-pll 28_92 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_MX[1] origin:032-cmt-pll 29_92 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_91 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_95 -CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[0] origin:032-cmt-pll 28_656 -CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[1] origin:032-cmt-pll 29_656 -CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[2] origin:032-cmt-pll 28_657 -CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[3] origin:032-cmt-pll 29_657 -CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[4] origin:032-cmt-pll 28_658 -CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[5] origin:032-cmt-pll 29_658 -CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[6] origin:032-cmt-pll 28_659 -CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[7] origin:032-cmt-pll 29_659 -CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[8] origin:032-cmt-pll 29_660 -CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[9] origin:032-cmt-pll 28_661 -CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[10] origin:032-cmt-pll 29_662 -CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[11] origin:032-cmt-pll 28_663 -CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[0] origin:032-cmt-pll 28_664 -CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[1] origin:032-cmt-pll 29_664 -CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[2] origin:032-cmt-pll 28_665 -CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[3] origin:032-cmt-pll 29_665 -CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[4] origin:032-cmt-pll 29_666 -CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[5] origin:032-cmt-pll 28_667 -CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[6] origin:032-cmt-pll 29_668 -CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[7] origin:032-cmt-pll 28_669 -CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[8] origin:032-cmt-pll 29_670 -CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[9] origin:032-cmt-pll 28_671 -CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[0] origin:032-cmt-pll 28_229 -CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[1] origin:032-cmt-pll 29_229 -CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[2] origin:032-cmt-pll 28_230 -CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[3] origin:032-cmt-pll 29_230 -CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[4] origin:032-cmt-pll 28_231 -CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[5] origin:032-cmt-pll 29_231 -CMT_TOP_L_UPPER_T.PLLE2.LOCKREG2_RESERVED[0] origin:032-cmt-pll 29_239 -CMT_TOP_L_UPPER_T.PLLE2.LOCKREG3_RESERVED[0] origin:032-cmt-pll 29_247 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_195 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_195 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_196 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_196 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_197 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_197 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_192 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_192 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_193 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_193 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_194 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_194 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_198 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_198 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_199 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_199 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_200 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_200 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_201 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_201 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_202 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_202 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_203 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_206 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_206 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_207 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_205 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_205 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_MX[0] origin:032-cmt-pll 28_204 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_MX[1] origin:032-cmt-pll 29_204 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_203 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_207 +CMT_TOP_L_UPPER_T.PLLE2_ADV.COMPENSATION.Z_ZHOLD_OR_CLKIN_BUF origin:032-cmt-pll 29_35 29_76 +CMT_TOP_L_UPPER_T.PLLE2_ADV.COMPENSATION.ZHOLD_NO_CLKIN_BUF origin:032-cmt-pll 28_73 29_36 +CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_EDGE[0] origin:032-cmt-pll 29_214 +CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_HIGH_TIME[0] origin:032-cmt-pll 28_211 +CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_HIGH_TIME[1] origin:032-cmt-pll 29_211 +CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_HIGH_TIME[2] origin:032-cmt-pll 28_212 +CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_HIGH_TIME[3] origin:032-cmt-pll 29_212 +CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_HIGH_TIME[4] origin:032-cmt-pll 28_213 +CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_HIGH_TIME[5] origin:032-cmt-pll 29_213 +CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_LOW_TIME[0] origin:032-cmt-pll 28_208 +CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_LOW_TIME[1] origin:032-cmt-pll 29_208 +CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_LOW_TIME[2] origin:032-cmt-pll 28_209 +CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_LOW_TIME[3] origin:032-cmt-pll 29_209 +CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_LOW_TIME[4] origin:032-cmt-pll 28_210 +CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_LOW_TIME[5] origin:032-cmt-pll 29_210 +CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_NO_COUNT[0] origin:032-cmt-pll 28_214 +CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_RESERVED[0] origin:032-cmt-pll 28_215 +CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_RESERVED[1] origin:032-cmt-pll 29_215 +CMT_TOP_L_UPPER_T.PLLE2_ADV.IN_USE origin:032-cmt-pll 28_216 28_219 28_222 28_266 28_280 28_283 28_284 28_37 28_48 28_592 28_622 28_623 28_624 28_627 28_628 28_74 28_768 28_78 28_785 28_786 28_787 28_788 28_790 28_791 28_792 28_793 28_795 28_796 28_797 28_798 28_799 28_803 28_806 28_807 28_811 28_812 28_815 28_816 28_817 28_818 28_819 28_821 28_822 28_823 28_824 28_826 28_827 28_828 28_829 28_832 28_835 28_838 28_841 28_845 28_847 29_268 29_281 29_282 29_283 29_48 29_563 29_567 29_589 29_621 29_622 29_625 29_626 29_627 29_77 29_78 29_785 29_786 29_788 29_79 29_790 29_791 29_793 29_797 29_798 29_800 29_809 29_811 29_812 29_813 29_814 29_815 29_816 29_817 29_819 29_823 29_824 29_825 29_826 29_827 29_829 29_830 29_831 29_832 29_835 29_836 29_838 29_839 29_840 29_841 29_842 29_845 +CMT_TOP_L_UPPER_T.PLLE2_ADV.INV_CLKINSEL origin:032-cmt-pll 28_754 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[0] origin:032-cmt-pll 28_232 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[1] origin:032-cmt-pll 29_232 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[2] origin:032-cmt-pll 28_233 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[3] origin:032-cmt-pll 29_233 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[4] origin:032-cmt-pll 28_234 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[5] origin:032-cmt-pll 29_234 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[6] origin:032-cmt-pll 28_235 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[7] origin:032-cmt-pll 29_235 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[8] origin:032-cmt-pll 28_236 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[9] origin:032-cmt-pll 29_236 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[10] origin:032-cmt-pll 28_240 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[11] origin:032-cmt-pll 29_240 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[12] origin:032-cmt-pll 28_241 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[13] origin:032-cmt-pll 29_241 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[14] origin:032-cmt-pll 28_242 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[15] origin:032-cmt-pll 29_242 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[16] origin:032-cmt-pll 28_243 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[17] origin:032-cmt-pll 29_243 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[18] origin:032-cmt-pll 28_244 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[19] origin:032-cmt-pll 29_244 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[20] origin:032-cmt-pll 28_224 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[21] origin:032-cmt-pll 29_224 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[22] origin:032-cmt-pll 28_225 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[23] origin:032-cmt-pll 29_225 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[24] origin:032-cmt-pll 28_226 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[25] origin:032-cmt-pll 29_226 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[26] origin:032-cmt-pll 28_227 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[27] origin:032-cmt-pll 29_227 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[28] origin:032-cmt-pll 28_228 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[29] origin:032-cmt-pll 29_228 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[30] origin:032-cmt-pll 28_237 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[31] origin:032-cmt-pll 29_237 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[32] origin:032-cmt-pll 28_238 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[33] origin:032-cmt-pll 29_238 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[34] origin:032-cmt-pll 28_239 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[35] origin:032-cmt-pll 28_245 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[36] origin:032-cmt-pll 29_245 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[37] origin:032-cmt-pll 28_246 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[38] origin:032-cmt-pll 29_246 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[39] origin:032-cmt-pll 28_247 +CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[0] origin:032-cmt-pll 28_352 +CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[1] origin:032-cmt-pll 29_352 +CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[2] origin:032-cmt-pll 28_353 +CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[3] origin:032-cmt-pll 29_353 +CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[4] origin:032-cmt-pll 28_354 +CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[5] origin:032-cmt-pll 29_354 +CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[6] origin:032-cmt-pll 28_355 +CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[7] origin:032-cmt-pll 29_355 +CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[8] origin:032-cmt-pll 28_356 +CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[9] origin:032-cmt-pll 29_356 +CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[10] origin:032-cmt-pll 28_357 +CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[11] origin:032-cmt-pll 29_357 +CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[12] origin:032-cmt-pll 28_358 +CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[13] origin:032-cmt-pll 29_358 +CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[14] origin:032-cmt-pll 28_359 +CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[15] origin:032-cmt-pll 29_359 +CMT_TOP_L_UPPER_T.PLLE2_ADV.STARTUP_WAIT origin:032-cmt-pll 28_769 +CMT_TOP_L_UPPER_T.PLLE2_ADV.TABLE[0] origin:032-cmt-pll 28_666 +CMT_TOP_L_UPPER_T.PLLE2_ADV.TABLE[1] origin:032-cmt-pll 29_667 +CMT_TOP_L_UPPER_T.PLLE2_ADV.TABLE[2] origin:032-cmt-pll 28_668 +CMT_TOP_L_UPPER_T.PLLE2_ADV.TABLE[3] origin:032-cmt-pll 29_669 +CMT_TOP_L_UPPER_T.PLLE2_ADV.TABLE[4] origin:032-cmt-pll 28_670 +CMT_TOP_L_UPPER_T.PLLE2_ADV.TABLE[5] origin:032-cmt-pll 29_671 +CMT_TOP_L_UPPER_T.PLLE2_ADV.TABLE[6] origin:032-cmt-pll 28_660 +CMT_TOP_L_UPPER_T.PLLE2_ADV.TABLE[7] origin:032-cmt-pll 29_661 +CMT_TOP_L_UPPER_T.PLLE2_ADV.TABLE[8] origin:032-cmt-pll 28_662 +CMT_TOP_L_UPPER_T.PLLE2_ADV.TABLE[9] origin:032-cmt-pll 29_663 +CMT_TOP_L_UPPER_T.PLLE2_ADV.ZINV_PWRDWN origin:032-cmt-pll 29_752 +CMT_TOP_L_UPPER_T.PLLE2_ADV.ZINV_RST origin:032-cmt-pll 28_752 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_99 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_99 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_100 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_100 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_101 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_101 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_96 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_96 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_97 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_97 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_98 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_98 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_102 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_102 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_103 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_103 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_104 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_104 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_105 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_105 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_106 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_106 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_107 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_110 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_110 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_111 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_109 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_109 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_MX[0] origin:032-cmt-pll 28_108 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_MX[1] origin:032-cmt-pll 29_108 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_107 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_111 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_115 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_115 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_116 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_116 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_117 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_117 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_112 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_112 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_113 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_113 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_114 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_114 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_118 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_118 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_119 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_119 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_120 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_120 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_121 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_121 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_122 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_122 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_123 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_126 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_126 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_127 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_125 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_125 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_MX[0] origin:032-cmt-pll 28_124 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_MX[1] origin:032-cmt-pll 29_124 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_123 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_127 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_131 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_131 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_132 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_132 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_133 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_133 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_128 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_128 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_129 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_129 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_130 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_130 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_134 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_134 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_135 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_135 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_136 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_136 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_137 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_137 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_138 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_138 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_139 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_142 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_142 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_143 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_141 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_141 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_MX[0] origin:032-cmt-pll 28_140 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_MX[1] origin:032-cmt-pll 29_140 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_139 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_143 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_147 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_147 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_148 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_148 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_149 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_149 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_144 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_144 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_145 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_145 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_146 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_146 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_150 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_150 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_151 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_151 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_152 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_152 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_153 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_153 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_154 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_154 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_155 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_158 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_158 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_159 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_157 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_157 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_MX[0] origin:032-cmt-pll 28_156 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_MX[1] origin:032-cmt-pll 29_156 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_155 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_159 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_163 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_163 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_164 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_164 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_165 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_165 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_160 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_160 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_161 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_161 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_162 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_162 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_166 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_166 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_167 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_167 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_168 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_168 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_169 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_169 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_170 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_170 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_171 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_174 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_174 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_175 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_173 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_173 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_MX[0] origin:032-cmt-pll 28_172 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_MX[1] origin:032-cmt-pll 29_172 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_171 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_175 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_83 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_83 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_84 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_84 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_85 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_85 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_80 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_80 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_81 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_81 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_82 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_82 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_86 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_86 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_87 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_87 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_88 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_88 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_89 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_89 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_90 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_90 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_91 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_94 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_94 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_95 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_93 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_93 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_MX[0] origin:032-cmt-pll 28_92 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_MX[1] origin:032-cmt-pll 29_92 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_91 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_95 +CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[0] origin:032-cmt-pll 28_656 +CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[1] origin:032-cmt-pll 29_656 +CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[2] origin:032-cmt-pll 28_657 +CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[3] origin:032-cmt-pll 29_657 +CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[4] origin:032-cmt-pll 28_658 +CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[5] origin:032-cmt-pll 29_658 +CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[6] origin:032-cmt-pll 28_659 +CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[7] origin:032-cmt-pll 29_659 +CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[8] origin:032-cmt-pll 29_660 +CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[9] origin:032-cmt-pll 28_661 +CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[10] origin:032-cmt-pll 29_662 +CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[11] origin:032-cmt-pll 28_663 +CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[0] origin:032-cmt-pll 28_664 +CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[1] origin:032-cmt-pll 29_664 +CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[2] origin:032-cmt-pll 28_665 +CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[3] origin:032-cmt-pll 29_665 +CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[4] origin:032-cmt-pll 29_666 +CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[5] origin:032-cmt-pll 28_667 +CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[6] origin:032-cmt-pll 29_668 +CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[7] origin:032-cmt-pll 28_669 +CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[8] origin:032-cmt-pll 29_670 +CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[9] origin:032-cmt-pll 28_671 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LOCKREG1_RESERVED[0] origin:032-cmt-pll 28_229 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LOCKREG1_RESERVED[1] origin:032-cmt-pll 29_229 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LOCKREG1_RESERVED[2] origin:032-cmt-pll 28_230 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LOCKREG1_RESERVED[3] origin:032-cmt-pll 29_230 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LOCKREG1_RESERVED[4] origin:032-cmt-pll 28_231 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LOCKREG1_RESERVED[5] origin:032-cmt-pll 29_231 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LOCKREG2_RESERVED[0] origin:032-cmt-pll 29_239 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LOCKREG3_RESERVED[0] origin:032-cmt-pll 29_247 diff --git a/kintex7/segbits_cmt_top_r_lower_b.db b/kintex7/segbits_cmt_top_r_lower_b.db index c725af6..1e746e5 100644 --- a/kintex7/segbits_cmt_top_r_lower_b.db +++ b/kintex7/segbits_cmt_top_r_lower_b.db @@ -25,381 +25,381 @@ CMT_TOP_R_LOWER_B.MMCM_CLK_FREQ_BB_NS2_ACTIVE 28_1068 28_1076 29_1057 CMT_TOP_R_LOWER_B.MMCM_CLK_FREQ_BB_NS2.MMCM_CLK_FREQ_BB_REBUF2_NS 28_1072 29_1067 29_1075 29_1079 CMT_TOP_R_LOWER_B.MMCM_CLK_FREQ_BB_NS3_ACTIVE 28_1058 28_1069 28_1077 CMT_TOP_R_LOWER_B.MMCM_CLK_FREQ_BB_NS3.MMCM_CLK_FREQ_BB_REBUF3_NS 28_1073 29_1068 29_1076 29_1080 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[0] 29_860 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[1] 28_860 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[2] 29_859 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[3] 28_859 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[4] 29_858 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[5] 28_858 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[0] 29_863 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[1] 28_863 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[2] 29_862 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[3] 28_862 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[4] 29_861 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[5] 28_861 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE[0] 29_857 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_PHASE_MUX[0] 28_857 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_PHASE_MUX[1] 29_856 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_PHASE_MUX[2] 28_856 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[0] 29_855 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[1] 28_855 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[2] 29_854 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[3] 28_854 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[4] 29_853 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[5] 28_853 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_EDGE[0] 28_852 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC[0] 29_849 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC[1] 28_849 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC[2] 29_848 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC_EN[0] 28_850 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC_WF_R[0] 29_850 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_MX[0] 29_851 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_MX[1] 28_851 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_NO_COUNT[0] 29_852 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_RESERVED[0] 28_848 -CMT_TOP_R_LOWER_B.MMCME2.COMP.Z_ZHOLD 28_979 28_1020 -CMT_TOP_R_LOWER_B.MMCME2.COMP.ZHOLD 28_1019 29_982 -CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_EDGE[0] 28_841 -CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[0] 29_844 -CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[1] 28_844 -CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[2] 29_843 -CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[3] 28_843 -CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[4] 29_842 -CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[5] 28_842 -CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[0] 29_847 -CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[1] 28_847 -CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[2] 29_846 -CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[3] 28_846 -CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[4] 29_845 -CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[5] 28_845 -CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_NO_COUNT[0] 29_841 -CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_RESERVED[0] 29_840 -CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_RESERVED[1] 28_840 -CMT_TOP_R_LOWER_B.MMCME2.IN_USE 28_18 28_21 28_22 28_23 28_24 28_25 28_27 28_28 28_31 28_32 28_33 28_34 28_36 28_37 28_38 28_39 28_40 28_44 28_46 28_47 28_48 28_49 28_50 28_51 28_52 28_54 28_63 28_65 28_66 28_70 28_72 28_73 28_75 28_77 28_78 28_428 28_429 28_430 28_433 28_434 28_466 28_488 28_492 28_772 28_773 28_774 28_787 28_976 28_978 28_989 28_991 28_1007 29_16 29_18 29_22 29_25 29_28 29_31 29_34 29_35 29_36 29_37 29_39 29_40 29_41 29_42 29_44 29_45 29_46 29_47 29_48 29_51 29_52 29_56 29_57 29_60 29_64 29_65 29_66 29_67 29_68 29_70 29_71 29_72 29_73 29_75 29_76 29_77 29_78 29_95 29_427 29_428 29_431 29_432 29_433 29_463 29_771 29_772 29_775 29_789 29_833 29_836 29_839 29_977 29_981 29_987 29_990 29_991 29_1007 29_1018 -CMT_TOP_R_LOWER_B.MMCME2.INV_CLKINSEL 29_109 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[0] 29_823 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[1] 28_823 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[2] 29_822 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[3] 28_822 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[4] 29_821 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[5] 28_821 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[6] 29_820 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[7] 28_820 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[8] 29_819 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[9] 28_819 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[10] 29_815 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[11] 28_815 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[12] 29_814 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[13] 28_814 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[14] 29_813 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[15] 28_813 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[16] 29_812 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[17] 28_812 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[18] 29_811 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[19] 28_811 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[20] 29_831 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[21] 28_831 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[22] 29_830 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[23] 28_830 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[24] 29_829 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[25] 28_829 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[26] 29_828 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[27] 28_828 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[28] 29_827 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[29] 28_827 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[30] 29_818 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[31] 28_818 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[32] 29_817 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[33] 28_817 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[34] 29_816 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[35] 29_810 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[36] 28_810 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[37] 29_809 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[38] 28_809 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[39] 29_808 -CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[0] 29_703 -CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[1] 28_703 -CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[2] 29_702 -CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[3] 28_702 -CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[4] 29_701 -CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[5] 28_701 -CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[6] 29_700 -CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[7] 28_700 -CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[8] 29_699 -CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[9] 28_699 -CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[10] 29_698 -CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[11] 28_698 -CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[12] 29_697 -CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[13] 28_697 -CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[14] 29_696 -CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[15] 28_696 -CMT_TOP_R_LOWER_B.MMCME2.SS_EN 28_95 28_388 28_696 28_698 28_700 28_702 28_850 28_915 29_389 29_697 29_701 29_703 -CMT_TOP_R_LOWER_B.MMCME2.STARTUP_WAIT 29_94 -CMT_TOP_R_LOWER_B.MMCME2.TABLE[0] 29_389 -CMT_TOP_R_LOWER_B.MMCME2.TABLE[1] 28_388 -CMT_TOP_R_LOWER_B.MMCME2.TABLE[2] 29_387 -CMT_TOP_R_LOWER_B.MMCME2.TABLE[3] 28_386 -CMT_TOP_R_LOWER_B.MMCME2.TABLE[4] 29_385 -CMT_TOP_R_LOWER_B.MMCME2.TABLE[5] 28_384 -CMT_TOP_R_LOWER_B.MMCME2.TABLE[6] 29_395 -CMT_TOP_R_LOWER_B.MMCME2.TABLE[7] 28_394 -CMT_TOP_R_LOWER_B.MMCME2.TABLE[8] 29_393 -CMT_TOP_R_LOWER_B.MMCME2.TABLE[9] 28_392 -CMT_TOP_R_LOWER_B.MMCME2.ZINV_PSEN 28_110 -CMT_TOP_R_LOWER_B.MMCME2.ZINV_PSINCDEC 29_110 -CMT_TOP_R_LOWER_B.MMCME2.ZINV_PWRDWN 28_111 -CMT_TOP_R_LOWER_B.MMCME2.ZINV_RST 29_111 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[0] 29_956 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[1] 28_956 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[2] 29_955 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[3] 28_955 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[4] 29_954 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[5] 28_954 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[0] 29_959 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[1] 28_959 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[2] 29_958 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[3] 28_958 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[4] 29_957 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[5] 28_957 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_OUTPUT_ENABLE[0] 29_953 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_PHASE_MUX[0] 28_953 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_PHASE_MUX[1] 29_952 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_PHASE_MUX[2] 28_952 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[0] 29_951 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[1] 28_951 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[2] 29_950 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[3] 28_950 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[4] 29_949 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[5] 28_949 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_EDGE[0] 28_948 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC[0] 29_945 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC[1] 28_945 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC[2] 29_944 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC_EN[0] 28_946 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC_WF_R[0] 29_946 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_MX[0] 29_947 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_MX[1] 28_947 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_NO_COUNT[0] 29_948 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_RESERVED[0] 28_944 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[0] 29_940 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[1] 28_940 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[2] 29_939 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[3] 28_939 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[4] 29_938 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[5] 28_938 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[0] 29_943 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[1] 28_943 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[2] 29_942 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[3] 28_942 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[4] 29_941 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[5] 28_941 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_OUTPUT_ENABLE[0] 29_937 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_PHASE_MUX[0] 28_937 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_PHASE_MUX[1] 29_936 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_PHASE_MUX[2] 28_936 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[0] 29_935 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[1] 28_935 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[2] 29_934 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[3] 28_934 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[4] 29_933 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[5] 28_933 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_EDGE[0] 28_932 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC[0] 29_929 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC[1] 28_929 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC[2] 29_928 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC_EN[0] 28_930 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC_WF_R[0] 29_930 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_MX[0] 29_931 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_MX[1] 28_931 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_NO_COUNT[0] 29_932 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_RESERVED[0] 28_928 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[0] 29_924 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[1] 28_924 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[2] 29_923 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[3] 28_923 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[4] 29_922 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[5] 28_922 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[0] 29_927 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[1] 28_927 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[2] 29_926 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[3] 28_926 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[4] 29_925 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[5] 28_925 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_OUTPUT_ENABLE[0] 29_921 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_PHASE_MUX[0] 28_921 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_PHASE_MUX[1] 29_920 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_PHASE_MUX[2] 28_920 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[0] 29_919 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[1] 28_919 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[2] 29_918 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[3] 28_918 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[4] 29_917 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[5] 28_917 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_EDGE[0] 28_916 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC[0] 29_913 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC[1] 28_913 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC[2] 29_912 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC_EN[0] 28_914 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC_WF_R[0] 29_914 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_MX[0] 29_915 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_MX[1] 28_915 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_NO_COUNT[0] 29_916 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_RESERVED[0] 28_912 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[0] 29_908 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[1] 28_908 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[2] 29_907 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[3] 28_907 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[4] 29_906 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[5] 28_906 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[0] 29_911 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[1] 28_911 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[2] 29_910 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[3] 28_910 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[4] 29_909 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[5] 28_909 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_OUTPUT_ENABLE[0] 29_905 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_PHASE_MUX[0] 28_905 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_PHASE_MUX[1] 29_904 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_PHASE_MUX[2] 28_904 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[0] 29_903 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[1] 28_903 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[2] 29_902 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[3] 28_902 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[4] 29_901 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[5] 28_901 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_EDGE[0] 28_900 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC[0] 29_897 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC[1] 28_897 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC[2] 29_896 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC_EN[0] 28_898 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC_WF_R[0] 29_898 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_MX[0] 29_899 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_MX[1] 28_899 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_NO_COUNT[0] 29_900 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_RESERVED[0] 28_896 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[0] 29_892 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[1] 28_892 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[2] 29_891 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[3] 28_891 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[4] 29_890 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[5] 28_890 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[0] 29_895 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[1] 28_895 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[2] 29_894 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[3] 28_894 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[4] 29_893 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[5] 28_893 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_OUTPUT_ENABLE[0] 29_889 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_PHASE_MUX[0] 28_889 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_PHASE_MUX[1] 29_888 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_PHASE_MUX[2] 28_888 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[0] 29_887 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[1] 28_887 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[2] 29_886 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[3] 28_886 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[4] 29_885 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[5] 28_885 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_EDGE[0] 28_884 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC[0] 29_881 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC[1] 28_881 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC[2] 29_880 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC_EN[0] 28_882 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC_WF_R[0] 29_882 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_MX[0] 29_883 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_MX[1] 28_883 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_NO_COUNT[0] 29_884 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_RESERVED[0] 28_880 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[0] 29_972 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[1] 28_972 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[2] 29_971 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[3] 28_971 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[4] 29_970 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[5] 28_970 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[0] 29_975 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[1] 28_975 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[2] 29_974 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[3] 28_974 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[4] 29_973 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[5] 28_973 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_OUTPUT_ENABLE[0] 29_969 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_PHASE_MUX[0] 28_969 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_PHASE_MUX[1] 29_968 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_PHASE_MUX[2] 28_968 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[0] 29_967 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[1] 28_967 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[2] 29_966 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[3] 28_966 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[4] 29_965 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[5] 28_965 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_EDGE[0] 28_964 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_FRAC_WF_F[0] 29_962 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_MX[0] 29_963 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_MX[1] 28_963 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_NO_COUNT[0] 29_964 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[0] 28_962 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[1] 29_961 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[2] 28_961 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_RESERVED[0] 29_960 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_RESERVED[1] 28_960 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[0] 29_876 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[1] 28_876 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[2] 29_875 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[3] 28_875 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[4] 29_874 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[5] 28_874 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[0] 29_879 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[1] 28_879 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[2] 29_878 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[3] 28_878 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[4] 29_877 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[5] 28_877 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_OUTPUT_ENABLE[0] 29_873 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_PHASE_MUX[0] 28_873 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_PHASE_MUX[1] 29_872 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_PHASE_MUX[2] 28_872 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[0] 29_871 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[1] 28_871 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[2] 29_870 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[3] 28_870 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[4] 29_869 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[5] 28_869 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_EDGE[0] 28_868 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_FRAC_WF_F[0] 29_866 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_MX[0] 29_867 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_MX[1] 28_867 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_NO_COUNT[0] 29_868 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[0] 28_866 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[1] 29_865 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[2] 28_865 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_RESERVED[0] 29_864 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_RESERVED[1] 28_864 -CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[0] 29_399 -CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[1] 28_399 -CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[2] 29_398 -CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[3] 28_398 -CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[4] 29_397 -CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[5] 28_397 -CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[6] 29_396 -CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[7] 28_396 -CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[8] 28_395 -CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[9] 29_394 -CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[10] 28_393 -CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[11] 29_392 -CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[0] 29_391 -CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[1] 28_391 -CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[2] 29_390 -CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[3] 28_390 -CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[4] 28_389 -CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[5] 29_388 -CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[6] 28_387 -CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[7] 29_386 -CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[8] 28_385 -CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[9] 29_384 -CMT_TOP_R_LOWER_B.MMCME2.LOCKREG1_RESERVED[0] 29_826 -CMT_TOP_R_LOWER_B.MMCME2.LOCKREG1_RESERVED[1] 28_826 -CMT_TOP_R_LOWER_B.MMCME2.LOCKREG1_RESERVED[2] 29_825 -CMT_TOP_R_LOWER_B.MMCME2.LOCKREG1_RESERVED[3] 28_825 -CMT_TOP_R_LOWER_B.MMCME2.LOCKREG1_RESERVED[4] 29_824 -CMT_TOP_R_LOWER_B.MMCME2.LOCKREG1_RESERVED[5] 28_824 -CMT_TOP_R_LOWER_B.MMCME2.LOCKREG2_RESERVED[0] 28_816 -CMT_TOP_R_LOWER_B.MMCME2.LOCKREG3_RESERVED[0] 28_808 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[0] 29_860 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[1] 28_860 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[2] 29_859 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[3] 28_859 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[4] 29_858 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[5] 28_858 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[0] 29_863 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[1] 28_863 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[2] 29_862 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[3] 28_862 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[4] 29_861 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[5] 28_861 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE[0] 29_857 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_PHASE_MUX[0] 28_857 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_PHASE_MUX[1] 29_856 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_PHASE_MUX[2] 28_856 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[0] 29_855 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[1] 28_855 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[2] 29_854 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[3] 28_854 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[4] 29_853 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[5] 28_853 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_EDGE[0] 28_852 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_FRAC[0] 29_849 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_FRAC[1] 28_849 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_FRAC[2] 29_848 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_FRAC_EN[0] 28_850 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_FRAC_WF_R[0] 29_850 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_MX[0] 29_851 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_MX[1] 28_851 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_NO_COUNT[0] 29_852 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_RESERVED[0] 28_848 +CMT_TOP_R_LOWER_B.MMCME2_ADV.COMP.Z_ZHOLD 28_979 28_1020 +CMT_TOP_R_LOWER_B.MMCME2_ADV.COMP.ZHOLD 28_1019 29_982 +CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_EDGE[0] 28_841 +CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_HIGH_TIME[0] 29_844 +CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_HIGH_TIME[1] 28_844 +CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_HIGH_TIME[2] 29_843 +CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_HIGH_TIME[3] 28_843 +CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_HIGH_TIME[4] 29_842 +CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_HIGH_TIME[5] 28_842 +CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_LOW_TIME[0] 29_847 +CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_LOW_TIME[1] 28_847 +CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_LOW_TIME[2] 29_846 +CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_LOW_TIME[3] 28_846 +CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_LOW_TIME[4] 29_845 +CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_LOW_TIME[5] 28_845 +CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_NO_COUNT[0] 29_841 +CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_RESERVED[0] 29_840 +CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_RESERVED[1] 28_840 +CMT_TOP_R_LOWER_B.MMCME2_ADV.IN_USE 28_18 28_21 28_22 28_23 28_24 28_25 28_27 28_28 28_31 28_32 28_33 28_34 28_36 28_37 28_38 28_39 28_40 28_44 28_46 28_47 28_48 28_49 28_50 28_51 28_52 28_54 28_63 28_65 28_66 28_70 28_72 28_73 28_75 28_77 28_78 28_428 28_429 28_430 28_433 28_434 28_466 28_488 28_492 28_772 28_773 28_774 28_787 28_976 28_978 28_989 28_991 28_1007 29_16 29_18 29_22 29_25 29_28 29_31 29_34 29_35 29_36 29_37 29_39 29_40 29_41 29_42 29_44 29_45 29_46 29_47 29_48 29_51 29_52 29_56 29_57 29_60 29_64 29_65 29_66 29_67 29_68 29_70 29_71 29_72 29_73 29_75 29_76 29_77 29_78 29_95 29_427 29_428 29_431 29_432 29_433 29_463 29_771 29_772 29_775 29_789 29_833 29_836 29_839 29_977 29_981 29_987 29_990 29_991 29_1007 29_1018 +CMT_TOP_R_LOWER_B.MMCME2_ADV.INV_CLKINSEL 29_109 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[0] 29_823 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[1] 28_823 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[2] 29_822 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[3] 28_822 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[4] 29_821 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[5] 28_821 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[6] 29_820 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[7] 28_820 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[8] 29_819 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[9] 28_819 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[10] 29_815 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[11] 28_815 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[12] 29_814 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[13] 28_814 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[14] 29_813 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[15] 28_813 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[16] 29_812 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[17] 28_812 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[18] 29_811 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[19] 28_811 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[20] 29_831 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[21] 28_831 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[22] 29_830 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[23] 28_830 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[24] 29_829 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[25] 28_829 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[26] 29_828 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[27] 28_828 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[28] 29_827 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[29] 28_827 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[30] 29_818 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[31] 28_818 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[32] 29_817 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[33] 28_817 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[34] 29_816 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[35] 29_810 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[36] 28_810 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[37] 29_809 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[38] 28_809 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[39] 29_808 +CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[0] 29_703 +CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[1] 28_703 +CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[2] 29_702 +CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[3] 28_702 +CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[4] 29_701 +CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[5] 28_701 +CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[6] 29_700 +CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[7] 28_700 +CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[8] 29_699 +CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[9] 28_699 +CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[10] 29_698 +CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[11] 28_698 +CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[12] 29_697 +CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[13] 28_697 +CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[14] 29_696 +CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[15] 28_696 +CMT_TOP_R_LOWER_B.MMCME2_ADV.SS_EN 28_95 28_388 28_696 28_698 28_700 28_702 28_850 28_915 29_389 29_697 29_701 29_703 +CMT_TOP_R_LOWER_B.MMCME2_ADV.STARTUP_WAIT 29_94 +CMT_TOP_R_LOWER_B.MMCME2_ADV.TABLE[0] 29_389 +CMT_TOP_R_LOWER_B.MMCME2_ADV.TABLE[1] 28_388 +CMT_TOP_R_LOWER_B.MMCME2_ADV.TABLE[2] 29_387 +CMT_TOP_R_LOWER_B.MMCME2_ADV.TABLE[3] 28_386 +CMT_TOP_R_LOWER_B.MMCME2_ADV.TABLE[4] 29_385 +CMT_TOP_R_LOWER_B.MMCME2_ADV.TABLE[5] 28_384 +CMT_TOP_R_LOWER_B.MMCME2_ADV.TABLE[6] 29_395 +CMT_TOP_R_LOWER_B.MMCME2_ADV.TABLE[7] 28_394 +CMT_TOP_R_LOWER_B.MMCME2_ADV.TABLE[8] 29_393 +CMT_TOP_R_LOWER_B.MMCME2_ADV.TABLE[9] 28_392 +CMT_TOP_R_LOWER_B.MMCME2_ADV.ZINV_PSEN 28_110 +CMT_TOP_R_LOWER_B.MMCME2_ADV.ZINV_PSINCDEC 29_110 +CMT_TOP_R_LOWER_B.MMCME2_ADV.ZINV_PWRDWN 28_111 +CMT_TOP_R_LOWER_B.MMCME2_ADV.ZINV_RST 29_111 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[0] 29_956 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[1] 28_956 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[2] 29_955 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[3] 28_955 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[4] 29_954 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[5] 28_954 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[0] 29_959 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[1] 28_959 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[2] 29_958 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[3] 28_958 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[4] 29_957 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[5] 28_957 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_OUTPUT_ENABLE[0] 29_953 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_PHASE_MUX[0] 28_953 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_PHASE_MUX[1] 29_952 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_PHASE_MUX[2] 28_952 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[0] 29_951 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[1] 28_951 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[2] 29_950 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[3] 28_950 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[4] 29_949 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[5] 28_949 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_EDGE[0] 28_948 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_FRAC[0] 29_945 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_FRAC[1] 28_945 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_FRAC[2] 29_944 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_FRAC_EN[0] 28_946 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_FRAC_WF_R[0] 29_946 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_MX[0] 29_947 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_MX[1] 28_947 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_NO_COUNT[0] 29_948 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_RESERVED[0] 28_944 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[0] 29_940 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[1] 28_940 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[2] 29_939 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[3] 28_939 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[4] 29_938 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[5] 28_938 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[0] 29_943 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[1] 28_943 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[2] 29_942 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[3] 28_942 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[4] 29_941 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[5] 28_941 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_OUTPUT_ENABLE[0] 29_937 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_PHASE_MUX[0] 28_937 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_PHASE_MUX[1] 29_936 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_PHASE_MUX[2] 28_936 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[0] 29_935 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[1] 28_935 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[2] 29_934 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[3] 28_934 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[4] 29_933 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[5] 28_933 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_EDGE[0] 28_932 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_FRAC[0] 29_929 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_FRAC[1] 28_929 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_FRAC[2] 29_928 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_FRAC_EN[0] 28_930 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_FRAC_WF_R[0] 29_930 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_MX[0] 29_931 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_MX[1] 28_931 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_NO_COUNT[0] 29_932 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_RESERVED[0] 28_928 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[0] 29_924 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[1] 28_924 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[2] 29_923 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[3] 28_923 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[4] 29_922 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[5] 28_922 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[0] 29_927 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[1] 28_927 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[2] 29_926 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[3] 28_926 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[4] 29_925 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[5] 28_925 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_OUTPUT_ENABLE[0] 29_921 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_PHASE_MUX[0] 28_921 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_PHASE_MUX[1] 29_920 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_PHASE_MUX[2] 28_920 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[0] 29_919 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[1] 28_919 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[2] 29_918 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[3] 28_918 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[4] 29_917 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[5] 28_917 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_EDGE[0] 28_916 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_FRAC[0] 29_913 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_FRAC[1] 28_913 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_FRAC[2] 29_912 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_FRAC_EN[0] 28_914 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_FRAC_WF_R[0] 29_914 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_MX[0] 29_915 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_MX[1] 28_915 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_NO_COUNT[0] 29_916 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_RESERVED[0] 28_912 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[0] 29_908 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[1] 28_908 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[2] 29_907 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[3] 28_907 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[4] 29_906 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[5] 28_906 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[0] 29_911 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[1] 28_911 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[2] 29_910 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[3] 28_910 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[4] 29_909 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[5] 28_909 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_OUTPUT_ENABLE[0] 29_905 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_PHASE_MUX[0] 28_905 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_PHASE_MUX[1] 29_904 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_PHASE_MUX[2] 28_904 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[0] 29_903 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[1] 28_903 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[2] 29_902 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[3] 28_902 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[4] 29_901 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[5] 28_901 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_EDGE[0] 28_900 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_FRAC[0] 29_897 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_FRAC[1] 28_897 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_FRAC[2] 29_896 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_FRAC_EN[0] 28_898 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_FRAC_WF_R[0] 29_898 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_MX[0] 29_899 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_MX[1] 28_899 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_NO_COUNT[0] 29_900 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_RESERVED[0] 28_896 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[0] 29_892 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[1] 28_892 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[2] 29_891 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[3] 28_891 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[4] 29_890 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[5] 28_890 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[0] 29_895 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[1] 28_895 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[2] 29_894 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[3] 28_894 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[4] 29_893 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[5] 28_893 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_OUTPUT_ENABLE[0] 29_889 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_PHASE_MUX[0] 28_889 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_PHASE_MUX[1] 29_888 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_PHASE_MUX[2] 28_888 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[0] 29_887 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[1] 28_887 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[2] 29_886 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[3] 28_886 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[4] 29_885 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[5] 28_885 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_EDGE[0] 28_884 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_FRAC[0] 29_881 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_FRAC[1] 28_881 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_FRAC[2] 29_880 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_FRAC_EN[0] 28_882 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_FRAC_WF_R[0] 29_882 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_MX[0] 29_883 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_MX[1] 28_883 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_NO_COUNT[0] 29_884 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_RESERVED[0] 28_880 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[0] 29_972 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[1] 28_972 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[2] 29_971 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[3] 28_971 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[4] 29_970 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[5] 28_970 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[0] 29_975 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[1] 28_975 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[2] 29_974 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[3] 28_974 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[4] 29_973 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[5] 28_973 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_OUTPUT_ENABLE[0] 29_969 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_PHASE_MUX[0] 28_969 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_PHASE_MUX[1] 29_968 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_PHASE_MUX[2] 28_968 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[0] 29_967 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[1] 28_967 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[2] 29_966 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[3] 28_966 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[4] 29_965 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[5] 28_965 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_EDGE[0] 28_964 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_FRAC_WF_F[0] 29_962 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_MX[0] 29_963 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_MX[1] 28_963 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_NO_COUNT[0] 29_964 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[0] 28_962 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[1] 29_961 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[2] 28_961 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_RESERVED[0] 29_960 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_RESERVED[1] 28_960 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_HIGH_TIME[0] 29_876 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_HIGH_TIME[1] 28_876 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_HIGH_TIME[2] 29_875 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_HIGH_TIME[3] 28_875 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_HIGH_TIME[4] 29_874 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_HIGH_TIME[5] 28_874 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_LOW_TIME[0] 29_879 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_LOW_TIME[1] 28_879 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_LOW_TIME[2] 29_878 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_LOW_TIME[3] 28_878 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_LOW_TIME[4] 29_877 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_LOW_TIME[5] 28_877 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_OUTPUT_ENABLE[0] 29_873 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_PHASE_MUX[0] 28_873 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_PHASE_MUX[1] 29_872 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_PHASE_MUX[2] 28_872 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[0] 29_871 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[1] 28_871 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[2] 29_870 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[3] 28_870 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[4] 29_869 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[5] 28_869 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_EDGE[0] 28_868 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_FRAC_WF_F[0] 29_866 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_MX[0] 29_867 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_MX[1] 28_867 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_NO_COUNT[0] 29_868 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[0] 28_866 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[1] 29_865 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[2] 28_865 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_RESERVED[0] 29_864 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_RESERVED[1] 28_864 +CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[0] 29_399 +CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[1] 28_399 +CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[2] 29_398 +CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[3] 28_398 +CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[4] 29_397 +CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[5] 28_397 +CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[6] 29_396 +CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[7] 28_396 +CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[8] 28_395 +CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[9] 29_394 +CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[10] 28_393 +CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[11] 29_392 +CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[0] 29_391 +CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[1] 28_391 +CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[2] 29_390 +CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[3] 28_390 +CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[4] 28_389 +CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[5] 29_388 +CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[6] 28_387 +CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[7] 29_386 +CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[8] 28_385 +CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[9] 29_384 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LOCKREG1_RESERVED[0] 29_826 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LOCKREG1_RESERVED[1] 28_826 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LOCKREG1_RESERVED[2] 29_825 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LOCKREG1_RESERVED[3] 28_825 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LOCKREG1_RESERVED[4] 29_824 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LOCKREG1_RESERVED[5] 28_824 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LOCKREG2_RESERVED[0] 28_816 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LOCKREG3_RESERVED[0] 28_808 diff --git a/kintex7/segbits_cmt_top_r_lower_b.origin_info.db b/kintex7/segbits_cmt_top_r_lower_b.origin_info.db index ad25957..07d55fa 100644 --- a/kintex7/segbits_cmt_top_r_lower_b.origin_info.db +++ b/kintex7/segbits_cmt_top_r_lower_b.origin_info.db @@ -25,381 +25,381 @@ CMT_TOP_R_LOWER_B.MMCM_CLK_FREQ_BB_NS2_ACTIVE origin:034b-cmt-mmcm-pips 28_1068 CMT_TOP_R_LOWER_B.MMCM_CLK_FREQ_BB_NS2.MMCM_CLK_FREQ_BB_REBUF2_NS origin:034b-cmt-mmcm-pips 28_1072 29_1067 29_1075 29_1079 CMT_TOP_R_LOWER_B.MMCM_CLK_FREQ_BB_NS3_ACTIVE origin:034b-cmt-mmcm-pips 28_1058 28_1069 28_1077 CMT_TOP_R_LOWER_B.MMCM_CLK_FREQ_BB_NS3.MMCM_CLK_FREQ_BB_REBUF3_NS origin:034b-cmt-mmcm-pips 28_1073 29_1068 29_1076 29_1080 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_860 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_860 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_859 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_859 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_858 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_858 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_863 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_863 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_862 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_862 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_861 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_861 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_857 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_857 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_856 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_856 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_855 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_855 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_854 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_854 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_853 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_853 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_852 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_849 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_849 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_848 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_850 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_850 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_851 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_851 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_852 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_848 -CMT_TOP_R_LOWER_B.MMCME2.COMP.Z_ZHOLD origin:031-cmt-mmcm 28_1020 28_979 -CMT_TOP_R_LOWER_B.MMCME2.COMP.ZHOLD origin:031-cmt-mmcm 28_1019 29_982 -CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_EDGE[0] origin:031-cmt-mmcm 28_841 -CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[0] origin:031-cmt-mmcm 29_844 -CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[1] origin:031-cmt-mmcm 28_844 -CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[2] origin:031-cmt-mmcm 29_843 -CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[3] origin:031-cmt-mmcm 28_843 -CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[4] origin:031-cmt-mmcm 29_842 -CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[5] origin:031-cmt-mmcm 28_842 -CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[0] origin:031-cmt-mmcm 29_847 -CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[1] origin:031-cmt-mmcm 28_847 -CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[2] origin:031-cmt-mmcm 29_846 -CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[3] origin:031-cmt-mmcm 28_846 -CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[4] origin:031-cmt-mmcm 29_845 -CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[5] origin:031-cmt-mmcm 28_845 -CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_NO_COUNT[0] origin:031-cmt-mmcm 29_841 -CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_RESERVED[0] origin:031-cmt-mmcm 29_840 -CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_RESERVED[1] origin:031-cmt-mmcm 28_840 -CMT_TOP_R_LOWER_B.MMCME2.IN_USE origin:031-cmt-mmcm 28_1007 28_18 28_21 28_22 28_23 28_24 28_25 28_27 28_28 28_31 28_32 28_33 28_34 28_36 28_37 28_38 28_39 28_40 28_428 28_429 28_430 28_433 28_434 28_44 28_46 28_466 28_47 28_48 28_488 28_49 28_492 28_50 28_51 28_52 28_54 28_63 28_65 28_66 28_70 28_72 28_73 28_75 28_77 28_772 28_773 28_774 28_78 28_787 28_976 28_978 28_989 28_991 29_1007 29_1018 29_16 29_18 29_22 29_25 29_28 29_31 29_34 29_35 29_36 29_37 29_39 29_40 29_41 29_42 29_427 29_428 29_431 29_432 29_433 29_44 29_45 29_46 29_463 29_47 29_48 29_51 29_52 29_56 29_57 29_60 29_64 29_65 29_66 29_67 29_68 29_70 29_71 29_72 29_73 29_75 29_76 29_77 29_771 29_772 29_775 29_78 29_789 29_833 29_836 29_839 29_95 29_977 29_981 29_987 29_990 29_991 -CMT_TOP_R_LOWER_B.MMCME2.INV_CLKINSEL origin:031-cmt-mmcm 29_109 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[0] origin:031-cmt-mmcm 29_823 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[1] origin:031-cmt-mmcm 28_823 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[2] origin:031-cmt-mmcm 29_822 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[3] origin:031-cmt-mmcm 28_822 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[4] origin:031-cmt-mmcm 29_821 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[5] origin:031-cmt-mmcm 28_821 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[6] origin:031-cmt-mmcm 29_820 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[7] origin:031-cmt-mmcm 28_820 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[8] origin:031-cmt-mmcm 29_819 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[9] origin:031-cmt-mmcm 28_819 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[10] origin:031-cmt-mmcm 29_815 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[11] origin:031-cmt-mmcm 28_815 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[12] origin:031-cmt-mmcm 29_814 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[13] origin:031-cmt-mmcm 28_814 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[14] origin:031-cmt-mmcm 29_813 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[15] origin:031-cmt-mmcm 28_813 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[16] origin:031-cmt-mmcm 29_812 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[17] origin:031-cmt-mmcm 28_812 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[18] origin:031-cmt-mmcm 29_811 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[19] origin:031-cmt-mmcm 28_811 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[20] origin:031-cmt-mmcm 29_831 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[21] origin:031-cmt-mmcm 28_831 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[22] origin:031-cmt-mmcm 29_830 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[23] origin:031-cmt-mmcm 28_830 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[24] origin:031-cmt-mmcm 29_829 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[25] origin:031-cmt-mmcm 28_829 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[26] origin:031-cmt-mmcm 29_828 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[27] origin:031-cmt-mmcm 28_828 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[28] origin:031-cmt-mmcm 29_827 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[29] origin:031-cmt-mmcm 28_827 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[30] origin:031-cmt-mmcm 29_818 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[31] origin:031-cmt-mmcm 28_818 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[32] origin:031-cmt-mmcm 29_817 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[33] origin:031-cmt-mmcm 28_817 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[34] origin:031-cmt-mmcm 29_816 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[35] origin:031-cmt-mmcm 29_810 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[36] origin:031-cmt-mmcm 28_810 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[37] origin:031-cmt-mmcm 29_809 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[38] origin:031-cmt-mmcm 28_809 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[39] origin:031-cmt-mmcm 29_808 -CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[0] origin:031-cmt-mmcm 29_703 -CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[1] origin:031-cmt-mmcm 28_703 -CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[2] origin:031-cmt-mmcm 29_702 -CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[3] origin:031-cmt-mmcm 28_702 -CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[4] origin:031-cmt-mmcm 29_701 -CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[5] origin:031-cmt-mmcm 28_701 -CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[6] origin:031-cmt-mmcm 29_700 -CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[7] origin:031-cmt-mmcm 28_700 -CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[8] origin:031-cmt-mmcm 29_699 -CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[9] origin:031-cmt-mmcm 28_699 -CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[10] origin:031-cmt-mmcm 29_698 -CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[11] origin:031-cmt-mmcm 28_698 -CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[12] origin:031-cmt-mmcm 29_697 -CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[13] origin:031-cmt-mmcm 28_697 -CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[14] origin:031-cmt-mmcm 29_696 -CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[15] origin:031-cmt-mmcm 28_696 -CMT_TOP_R_LOWER_B.MMCME2.SS_EN origin:031-cmt-mmcm 28_388 28_696 28_698 28_700 28_702 28_850 28_915 28_95 29_389 29_697 29_701 29_703 -CMT_TOP_R_LOWER_B.MMCME2.STARTUP_WAIT origin:031-cmt-mmcm 29_94 -CMT_TOP_R_LOWER_B.MMCME2.TABLE[0] origin:031-cmt-mmcm 29_389 -CMT_TOP_R_LOWER_B.MMCME2.TABLE[1] origin:031-cmt-mmcm 28_388 -CMT_TOP_R_LOWER_B.MMCME2.TABLE[2] origin:031-cmt-mmcm 29_387 -CMT_TOP_R_LOWER_B.MMCME2.TABLE[3] origin:031-cmt-mmcm 28_386 -CMT_TOP_R_LOWER_B.MMCME2.TABLE[4] origin:031-cmt-mmcm 29_385 -CMT_TOP_R_LOWER_B.MMCME2.TABLE[5] origin:031-cmt-mmcm 28_384 -CMT_TOP_R_LOWER_B.MMCME2.TABLE[6] origin:031-cmt-mmcm 29_395 -CMT_TOP_R_LOWER_B.MMCME2.TABLE[7] origin:031-cmt-mmcm 28_394 -CMT_TOP_R_LOWER_B.MMCME2.TABLE[8] origin:031-cmt-mmcm 29_393 -CMT_TOP_R_LOWER_B.MMCME2.TABLE[9] origin:031-cmt-mmcm 28_392 -CMT_TOP_R_LOWER_B.MMCME2.ZINV_PSEN origin:031-cmt-mmcm 28_110 -CMT_TOP_R_LOWER_B.MMCME2.ZINV_PSINCDEC origin:031-cmt-mmcm 29_110 -CMT_TOP_R_LOWER_B.MMCME2.ZINV_PWRDWN origin:031-cmt-mmcm 28_111 -CMT_TOP_R_LOWER_B.MMCME2.ZINV_RST origin:031-cmt-mmcm 29_111 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_956 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_956 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_955 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_955 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_954 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_954 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_959 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_959 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_958 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_958 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_957 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_957 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_953 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_953 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_952 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_952 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_951 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_951 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_950 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_950 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_949 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_949 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_948 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_945 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_945 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_944 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_946 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_946 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_947 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_947 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_948 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_944 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_940 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_940 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_939 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_939 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_938 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_938 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_943 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_943 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_942 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_942 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_941 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_941 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_937 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_937 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_936 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_936 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_935 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_935 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_934 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_934 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_933 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_933 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_932 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_929 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_929 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_928 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_930 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_930 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_931 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_931 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_932 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_928 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_924 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_924 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_923 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_923 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_922 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_922 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_927 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_927 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_926 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_926 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_925 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_925 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_921 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_921 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_920 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_920 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_919 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_919 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_918 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_918 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_917 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_917 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_916 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_913 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_913 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_912 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_914 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_914 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_915 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_915 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_916 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_912 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_908 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_908 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_907 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_907 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_906 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_906 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_911 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_911 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_910 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_910 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_909 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_909 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_905 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_905 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_904 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_904 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_903 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_903 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_902 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_902 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_901 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_901 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_900 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_897 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_897 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_896 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_898 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_898 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_899 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_899 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_900 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_896 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_892 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_892 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_891 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_891 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_890 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_890 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_895 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_895 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_894 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_894 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_893 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_893 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_889 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_889 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_888 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_888 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_887 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_887 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_886 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_886 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_885 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_885 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_884 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_881 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_881 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_880 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_882 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_882 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_883 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_883 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_884 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_880 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_972 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_972 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_971 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_971 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_970 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_970 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_975 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_975 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_974 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_974 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_973 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_973 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_969 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_969 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_968 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_968 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[0] origin:031-cmt-mmcm 29_967 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[1] origin:031-cmt-mmcm 28_967 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[2] origin:031-cmt-mmcm 29_966 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[3] origin:031-cmt-mmcm 28_966 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[4] origin:031-cmt-mmcm 29_965 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[5] origin:031-cmt-mmcm 28_965 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_EDGE[0] origin:031-cmt-mmcm 28_964 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_FRAC_WF_F[0] origin:031-cmt-mmcm 29_962 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_MX[0] origin:031-cmt-mmcm 29_963 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_MX[1] origin:031-cmt-mmcm 28_963 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_NO_COUNT[0] origin:031-cmt-mmcm 29_964 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[0] origin:031-cmt-mmcm 28_962 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[1] origin:031-cmt-mmcm 29_961 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[2] origin:031-cmt-mmcm 28_961 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_RESERVED[0] origin:031-cmt-mmcm 29_960 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_RESERVED[1] origin:031-cmt-mmcm 28_960 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_876 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_876 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_875 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_875 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_874 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_874 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_879 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_879 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_878 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_878 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_877 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_877 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_873 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_873 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_872 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_872 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[0] origin:031-cmt-mmcm 29_871 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[1] origin:031-cmt-mmcm 28_871 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[2] origin:031-cmt-mmcm 29_870 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[3] origin:031-cmt-mmcm 28_870 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[4] origin:031-cmt-mmcm 29_869 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[5] origin:031-cmt-mmcm 28_869 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_EDGE[0] origin:031-cmt-mmcm 28_868 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_FRAC_WF_F[0] origin:031-cmt-mmcm 29_866 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_MX[0] origin:031-cmt-mmcm 29_867 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_MX[1] origin:031-cmt-mmcm 28_867 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_NO_COUNT[0] origin:031-cmt-mmcm 29_868 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[0] origin:031-cmt-mmcm 28_866 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[1] origin:031-cmt-mmcm 29_865 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[2] origin:031-cmt-mmcm 28_865 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_RESERVED[0] origin:031-cmt-mmcm 29_864 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_RESERVED[1] origin:031-cmt-mmcm 28_864 -CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[0] origin:031-cmt-mmcm 29_399 -CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[1] origin:031-cmt-mmcm 28_399 -CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[2] origin:031-cmt-mmcm 29_398 -CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[3] origin:031-cmt-mmcm 28_398 -CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[4] origin:031-cmt-mmcm 29_397 -CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[5] origin:031-cmt-mmcm 28_397 -CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[6] origin:031-cmt-mmcm 29_396 -CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[7] origin:031-cmt-mmcm 28_396 -CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[8] origin:031-cmt-mmcm 28_395 -CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[9] origin:031-cmt-mmcm 29_394 -CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[10] origin:031-cmt-mmcm 28_393 -CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[11] origin:031-cmt-mmcm 29_392 -CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[0] origin:031-cmt-mmcm 29_391 -CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[1] origin:031-cmt-mmcm 28_391 -CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[2] origin:031-cmt-mmcm 29_390 -CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[3] origin:031-cmt-mmcm 28_390 -CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[4] origin:031-cmt-mmcm 28_389 -CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[5] origin:031-cmt-mmcm 29_388 -CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[6] origin:031-cmt-mmcm 28_387 -CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[7] origin:031-cmt-mmcm 29_386 -CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[8] origin:031-cmt-mmcm 28_385 -CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[9] origin:031-cmt-mmcm 29_384 -CMT_TOP_R_LOWER_B.MMCME2.LOCKREG1_RESERVED[0] origin:031-cmt-mmcm 29_826 -CMT_TOP_R_LOWER_B.MMCME2.LOCKREG1_RESERVED[1] origin:031-cmt-mmcm 28_826 -CMT_TOP_R_LOWER_B.MMCME2.LOCKREG1_RESERVED[2] origin:031-cmt-mmcm 29_825 -CMT_TOP_R_LOWER_B.MMCME2.LOCKREG1_RESERVED[3] origin:031-cmt-mmcm 28_825 -CMT_TOP_R_LOWER_B.MMCME2.LOCKREG1_RESERVED[4] origin:031-cmt-mmcm 29_824 -CMT_TOP_R_LOWER_B.MMCME2.LOCKREG1_RESERVED[5] origin:031-cmt-mmcm 28_824 -CMT_TOP_R_LOWER_B.MMCME2.LOCKREG2_RESERVED[0] origin:031-cmt-mmcm 28_816 -CMT_TOP_R_LOWER_B.MMCME2.LOCKREG3_RESERVED[0] origin:031-cmt-mmcm 28_808 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_860 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_860 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_859 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_859 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_858 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_858 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_863 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_863 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_862 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_862 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_861 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_861 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_857 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_857 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_856 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_856 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_855 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_855 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_854 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_854 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_853 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_853 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_852 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_849 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_849 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_848 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_850 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_850 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_851 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_851 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_852 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_848 +CMT_TOP_R_LOWER_B.MMCME2_ADV.COMP.Z_ZHOLD origin:031-cmt-mmcm 28_1020 28_979 +CMT_TOP_R_LOWER_B.MMCME2_ADV.COMP.ZHOLD origin:031-cmt-mmcm 28_1019 29_982 +CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_EDGE[0] origin:031-cmt-mmcm 28_841 +CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_HIGH_TIME[0] origin:031-cmt-mmcm 29_844 +CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_HIGH_TIME[1] origin:031-cmt-mmcm 28_844 +CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_HIGH_TIME[2] origin:031-cmt-mmcm 29_843 +CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_HIGH_TIME[3] origin:031-cmt-mmcm 28_843 +CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_HIGH_TIME[4] origin:031-cmt-mmcm 29_842 +CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_HIGH_TIME[5] origin:031-cmt-mmcm 28_842 +CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_LOW_TIME[0] origin:031-cmt-mmcm 29_847 +CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_LOW_TIME[1] origin:031-cmt-mmcm 28_847 +CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_LOW_TIME[2] origin:031-cmt-mmcm 29_846 +CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_LOW_TIME[3] origin:031-cmt-mmcm 28_846 +CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_LOW_TIME[4] origin:031-cmt-mmcm 29_845 +CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_LOW_TIME[5] origin:031-cmt-mmcm 28_845 +CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_NO_COUNT[0] origin:031-cmt-mmcm 29_841 +CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_RESERVED[0] origin:031-cmt-mmcm 29_840 +CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_RESERVED[1] origin:031-cmt-mmcm 28_840 +CMT_TOP_R_LOWER_B.MMCME2_ADV.IN_USE origin:031-cmt-mmcm 28_1007 28_18 28_21 28_22 28_23 28_24 28_25 28_27 28_28 28_31 28_32 28_33 28_34 28_36 28_37 28_38 28_39 28_40 28_428 28_429 28_430 28_433 28_434 28_44 28_46 28_466 28_47 28_48 28_488 28_49 28_492 28_50 28_51 28_52 28_54 28_63 28_65 28_66 28_70 28_72 28_73 28_75 28_77 28_772 28_773 28_774 28_78 28_787 28_976 28_978 28_989 28_991 29_1007 29_1018 29_16 29_18 29_22 29_25 29_28 29_31 29_34 29_35 29_36 29_37 29_39 29_40 29_41 29_42 29_427 29_428 29_431 29_432 29_433 29_44 29_45 29_46 29_463 29_47 29_48 29_51 29_52 29_56 29_57 29_60 29_64 29_65 29_66 29_67 29_68 29_70 29_71 29_72 29_73 29_75 29_76 29_77 29_771 29_772 29_775 29_78 29_789 29_833 29_836 29_839 29_95 29_977 29_981 29_987 29_990 29_991 +CMT_TOP_R_LOWER_B.MMCME2_ADV.INV_CLKINSEL origin:031-cmt-mmcm 29_109 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[0] origin:031-cmt-mmcm 29_823 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[1] origin:031-cmt-mmcm 28_823 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[2] origin:031-cmt-mmcm 29_822 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[3] origin:031-cmt-mmcm 28_822 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[4] origin:031-cmt-mmcm 29_821 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[5] origin:031-cmt-mmcm 28_821 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[6] origin:031-cmt-mmcm 29_820 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[7] origin:031-cmt-mmcm 28_820 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[8] origin:031-cmt-mmcm 29_819 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[9] origin:031-cmt-mmcm 28_819 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[10] origin:031-cmt-mmcm 29_815 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[11] origin:031-cmt-mmcm 28_815 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[12] origin:031-cmt-mmcm 29_814 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[13] origin:031-cmt-mmcm 28_814 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[14] origin:031-cmt-mmcm 29_813 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[15] origin:031-cmt-mmcm 28_813 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[16] origin:031-cmt-mmcm 29_812 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[17] origin:031-cmt-mmcm 28_812 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[18] origin:031-cmt-mmcm 29_811 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[19] origin:031-cmt-mmcm 28_811 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[20] origin:031-cmt-mmcm 29_831 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[21] origin:031-cmt-mmcm 28_831 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[22] origin:031-cmt-mmcm 29_830 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[23] origin:031-cmt-mmcm 28_830 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[24] origin:031-cmt-mmcm 29_829 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[25] origin:031-cmt-mmcm 28_829 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[26] origin:031-cmt-mmcm 29_828 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[27] origin:031-cmt-mmcm 28_828 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[28] origin:031-cmt-mmcm 29_827 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[29] origin:031-cmt-mmcm 28_827 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[30] origin:031-cmt-mmcm 29_818 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[31] origin:031-cmt-mmcm 28_818 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[32] origin:031-cmt-mmcm 29_817 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[33] origin:031-cmt-mmcm 28_817 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[34] origin:031-cmt-mmcm 29_816 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[35] origin:031-cmt-mmcm 29_810 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[36] origin:031-cmt-mmcm 28_810 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[37] origin:031-cmt-mmcm 29_809 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[38] origin:031-cmt-mmcm 28_809 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[39] origin:031-cmt-mmcm 29_808 +CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[0] origin:031-cmt-mmcm 29_703 +CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[1] origin:031-cmt-mmcm 28_703 +CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[2] origin:031-cmt-mmcm 29_702 +CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[3] origin:031-cmt-mmcm 28_702 +CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[4] origin:031-cmt-mmcm 29_701 +CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[5] origin:031-cmt-mmcm 28_701 +CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[6] origin:031-cmt-mmcm 29_700 +CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[7] origin:031-cmt-mmcm 28_700 +CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[8] origin:031-cmt-mmcm 29_699 +CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[9] origin:031-cmt-mmcm 28_699 +CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[10] origin:031-cmt-mmcm 29_698 +CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[11] origin:031-cmt-mmcm 28_698 +CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[12] origin:031-cmt-mmcm 29_697 +CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[13] origin:031-cmt-mmcm 28_697 +CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[14] origin:031-cmt-mmcm 29_696 +CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[15] origin:031-cmt-mmcm 28_696 +CMT_TOP_R_LOWER_B.MMCME2_ADV.SS_EN origin:031-cmt-mmcm 28_388 28_696 28_698 28_700 28_702 28_850 28_915 28_95 29_389 29_697 29_701 29_703 +CMT_TOP_R_LOWER_B.MMCME2_ADV.STARTUP_WAIT origin:031-cmt-mmcm 29_94 +CMT_TOP_R_LOWER_B.MMCME2_ADV.TABLE[0] origin:031-cmt-mmcm 29_389 +CMT_TOP_R_LOWER_B.MMCME2_ADV.TABLE[1] origin:031-cmt-mmcm 28_388 +CMT_TOP_R_LOWER_B.MMCME2_ADV.TABLE[2] origin:031-cmt-mmcm 29_387 +CMT_TOP_R_LOWER_B.MMCME2_ADV.TABLE[3] origin:031-cmt-mmcm 28_386 +CMT_TOP_R_LOWER_B.MMCME2_ADV.TABLE[4] origin:031-cmt-mmcm 29_385 +CMT_TOP_R_LOWER_B.MMCME2_ADV.TABLE[5] origin:031-cmt-mmcm 28_384 +CMT_TOP_R_LOWER_B.MMCME2_ADV.TABLE[6] origin:031-cmt-mmcm 29_395 +CMT_TOP_R_LOWER_B.MMCME2_ADV.TABLE[7] origin:031-cmt-mmcm 28_394 +CMT_TOP_R_LOWER_B.MMCME2_ADV.TABLE[8] origin:031-cmt-mmcm 29_393 +CMT_TOP_R_LOWER_B.MMCME2_ADV.TABLE[9] origin:031-cmt-mmcm 28_392 +CMT_TOP_R_LOWER_B.MMCME2_ADV.ZINV_PSEN origin:031-cmt-mmcm 28_110 +CMT_TOP_R_LOWER_B.MMCME2_ADV.ZINV_PSINCDEC origin:031-cmt-mmcm 29_110 +CMT_TOP_R_LOWER_B.MMCME2_ADV.ZINV_PWRDWN origin:031-cmt-mmcm 28_111 +CMT_TOP_R_LOWER_B.MMCME2_ADV.ZINV_RST origin:031-cmt-mmcm 29_111 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_956 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_956 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_955 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_955 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_954 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_954 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_959 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_959 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_958 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_958 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_957 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_957 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_953 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_953 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_952 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_952 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_951 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_951 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_950 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_950 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_949 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_949 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_948 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_945 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_945 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_944 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_946 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_946 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_947 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_947 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_948 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_944 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_940 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_940 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_939 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_939 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_938 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_938 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_943 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_943 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_942 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_942 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_941 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_941 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_937 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_937 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_936 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_936 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_935 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_935 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_934 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_934 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_933 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_933 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_932 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_929 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_929 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_928 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_930 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_930 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_931 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_931 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_932 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_928 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_924 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_924 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_923 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_923 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_922 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_922 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_927 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_927 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_926 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_926 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_925 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_925 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_921 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_921 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_920 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_920 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_919 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_919 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_918 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_918 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_917 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_917 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_916 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_913 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_913 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_912 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_914 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_914 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_915 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_915 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_916 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_912 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_908 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_908 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_907 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_907 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_906 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_906 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_911 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_911 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_910 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_910 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_909 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_909 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_905 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_905 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_904 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_904 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_903 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_903 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_902 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_902 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_901 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_901 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_900 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_897 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_897 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_896 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_898 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_898 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_899 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_899 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_900 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_896 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_892 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_892 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_891 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_891 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_890 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_890 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_895 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_895 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_894 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_894 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_893 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_893 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_889 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_889 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_888 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_888 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_887 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_887 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_886 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_886 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_885 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_885 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_884 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_881 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_881 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_880 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_882 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_882 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_883 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_883 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_884 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_880 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_972 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_972 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_971 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_971 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_970 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_970 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_975 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_975 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_974 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_974 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_973 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_973 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_969 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_969 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_968 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_968 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[0] origin:031-cmt-mmcm 29_967 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[1] origin:031-cmt-mmcm 28_967 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[2] origin:031-cmt-mmcm 29_966 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[3] origin:031-cmt-mmcm 28_966 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[4] origin:031-cmt-mmcm 29_965 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[5] origin:031-cmt-mmcm 28_965 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_EDGE[0] origin:031-cmt-mmcm 28_964 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_FRAC_WF_F[0] origin:031-cmt-mmcm 29_962 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_MX[0] origin:031-cmt-mmcm 29_963 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_MX[1] origin:031-cmt-mmcm 28_963 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_NO_COUNT[0] origin:031-cmt-mmcm 29_964 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[0] origin:031-cmt-mmcm 28_962 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[1] origin:031-cmt-mmcm 29_961 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[2] origin:031-cmt-mmcm 28_961 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_RESERVED[0] origin:031-cmt-mmcm 29_960 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_RESERVED[1] origin:031-cmt-mmcm 28_960 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_876 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_876 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_875 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_875 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_874 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_874 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_879 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_879 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_878 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_878 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_877 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_877 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_873 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_873 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_872 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_872 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[0] origin:031-cmt-mmcm 29_871 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[1] origin:031-cmt-mmcm 28_871 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[2] origin:031-cmt-mmcm 29_870 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[3] origin:031-cmt-mmcm 28_870 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[4] origin:031-cmt-mmcm 29_869 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[5] origin:031-cmt-mmcm 28_869 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_EDGE[0] origin:031-cmt-mmcm 28_868 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_FRAC_WF_F[0] origin:031-cmt-mmcm 29_866 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_MX[0] origin:031-cmt-mmcm 29_867 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_MX[1] origin:031-cmt-mmcm 28_867 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_NO_COUNT[0] origin:031-cmt-mmcm 29_868 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[0] origin:031-cmt-mmcm 28_866 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[1] origin:031-cmt-mmcm 29_865 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[2] origin:031-cmt-mmcm 28_865 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_RESERVED[0] origin:031-cmt-mmcm 29_864 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_RESERVED[1] origin:031-cmt-mmcm 28_864 +CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[0] origin:031-cmt-mmcm 29_399 +CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[1] origin:031-cmt-mmcm 28_399 +CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[2] origin:031-cmt-mmcm 29_398 +CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[3] origin:031-cmt-mmcm 28_398 +CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[4] origin:031-cmt-mmcm 29_397 +CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[5] origin:031-cmt-mmcm 28_397 +CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[6] origin:031-cmt-mmcm 29_396 +CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[7] origin:031-cmt-mmcm 28_396 +CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[8] origin:031-cmt-mmcm 28_395 +CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[9] origin:031-cmt-mmcm 29_394 +CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[10] origin:031-cmt-mmcm 28_393 +CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[11] origin:031-cmt-mmcm 29_392 +CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[0] origin:031-cmt-mmcm 29_391 +CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[1] origin:031-cmt-mmcm 28_391 +CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[2] origin:031-cmt-mmcm 29_390 +CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[3] origin:031-cmt-mmcm 28_390 +CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[4] origin:031-cmt-mmcm 28_389 +CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[5] origin:031-cmt-mmcm 29_388 +CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[6] origin:031-cmt-mmcm 28_387 +CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[7] origin:031-cmt-mmcm 29_386 +CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[8] origin:031-cmt-mmcm 28_385 +CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[9] origin:031-cmt-mmcm 29_384 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LOCKREG1_RESERVED[0] origin:031-cmt-mmcm 29_826 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LOCKREG1_RESERVED[1] origin:031-cmt-mmcm 28_826 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LOCKREG1_RESERVED[2] origin:031-cmt-mmcm 29_825 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LOCKREG1_RESERVED[3] origin:031-cmt-mmcm 28_825 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LOCKREG1_RESERVED[4] origin:031-cmt-mmcm 29_824 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LOCKREG1_RESERVED[5] origin:031-cmt-mmcm 28_824 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LOCKREG2_RESERVED[0] origin:031-cmt-mmcm 28_816 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LOCKREG3_RESERVED[0] origin:031-cmt-mmcm 28_808 diff --git a/kintex7/segbits_cmt_top_r_upper_t.db b/kintex7/segbits_cmt_top_r_upper_t.db index 0e40593..eff93ea 100644 --- a/kintex7/segbits_cmt_top_r_upper_t.db +++ b/kintex7/segbits_cmt_top_r_upper_t.db @@ -21,346 +21,346 @@ CMT_TOP_R_UPPER_T.PLL_CLK_FREQ_BB0_NS_ACTIVE 29_00 29_09 29_17 CMT_TOP_R_UPPER_T.PLL_CLK_FREQ_BB1_NS_ACTIVE 28_01 29_10 29_18 CMT_TOP_R_UPPER_T.PLL_CLK_FREQ_BB2_NS_ACTIVE 29_01 29_11 29_19 CMT_TOP_R_UPPER_T.PLL_CLK_FREQ_BB3_NS_ACTIVE 28_02 29_12 29_20 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[0] 28_195 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[1] 29_195 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[2] 28_196 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[3] 29_196 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[4] 28_197 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[5] 29_197 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[0] 28_192 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[1] 29_192 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[2] 28_193 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[3] 29_193 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[4] 28_194 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[5] 29_194 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE[0] 28_198 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[0] 29_198 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[1] 28_199 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[2] 29_199 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[0] 28_200 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[1] 29_200 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[2] 28_201 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[3] 29_201 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[4] 28_202 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[5] 29_202 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_EDGE[0] 29_203 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[0] 28_206 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[1] 29_206 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[2] 28_207 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC_EN[0] 29_205 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC_WF_R[0] 28_205 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_MX[0] 28_204 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_MX[1] 29_204 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_NO_COUNT[0] 28_203 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_RESERVED[0] 29_207 -CMT_TOP_R_UPPER_T.PLLE2.COMPENSATION.Z_ZHOLD_OR_CLKIN_BUF 29_35 29_76 -CMT_TOP_R_UPPER_T.PLLE2.COMPENSATION.ZHOLD_NO_CLKIN_BUF 28_73 29_36 -CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_EDGE[0] 29_214 -CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[0] 28_211 -CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[1] 29_211 -CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[2] 28_212 -CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[3] 29_212 -CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[4] 28_213 -CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[5] 29_213 -CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[0] 28_208 -CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[1] 29_208 -CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[2] 28_209 -CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[3] 29_209 -CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[4] 28_210 -CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[5] 29_210 -CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_NO_COUNT[0] 28_214 -CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_RESERVED[0] 28_215 -CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_RESERVED[1] 29_215 -CMT_TOP_R_UPPER_T.PLLE2.IN_USE 28_37 28_48 28_74 28_78 28_216 28_219 28_222 28_266 28_280 28_283 28_284 28_592 28_622 28_623 28_624 28_627 28_628 28_768 28_785 28_786 28_787 28_788 28_790 28_791 28_792 28_793 28_795 28_796 28_797 28_798 28_799 28_803 28_806 28_807 28_811 28_812 28_815 28_816 28_817 28_818 28_819 28_821 28_822 28_823 28_824 28_826 28_827 28_828 28_829 28_832 28_835 28_838 28_841 28_845 28_847 29_48 29_77 29_78 29_79 29_268 29_281 29_282 29_283 29_563 29_567 29_589 29_621 29_622 29_625 29_626 29_627 29_785 29_786 29_788 29_790 29_791 29_793 29_797 29_798 29_800 29_809 29_811 29_812 29_813 29_814 29_815 29_816 29_817 29_819 29_823 29_824 29_825 29_826 29_827 29_829 29_830 29_831 29_832 29_835 29_836 29_838 29_839 29_840 29_841 29_842 29_845 -CMT_TOP_R_UPPER_T.PLLE2.INV_CLKINSEL 28_754 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[0] 28_232 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[1] 29_232 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[2] 28_233 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[3] 29_233 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[4] 28_234 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[5] 29_234 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[6] 28_235 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[7] 29_235 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[8] 28_236 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[9] 29_236 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[10] 28_240 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[11] 29_240 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[12] 28_241 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[13] 29_241 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[14] 28_242 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[15] 29_242 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[16] 28_243 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[17] 29_243 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[18] 28_244 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[19] 29_244 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[20] 28_224 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[21] 29_224 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[22] 28_225 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[23] 29_225 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[24] 28_226 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[25] 29_226 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[26] 28_227 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[27] 29_227 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[28] 28_228 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[29] 29_228 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[30] 28_237 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[31] 29_237 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[32] 28_238 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[33] 29_238 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[34] 28_239 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[35] 28_245 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[36] 29_245 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[37] 28_246 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[38] 29_246 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[39] 28_247 -CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[0] 28_352 -CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[1] 29_352 -CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[2] 28_353 -CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[3] 29_353 -CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[4] 28_354 -CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[5] 29_354 -CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[6] 28_355 -CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[7] 29_355 -CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[8] 28_356 -CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[9] 29_356 -CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[10] 28_357 -CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[11] 29_357 -CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[12] 28_358 -CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[13] 29_358 -CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[14] 28_359 -CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[15] 29_359 -CMT_TOP_R_UPPER_T.PLLE2.STARTUP_WAIT 28_769 -CMT_TOP_R_UPPER_T.PLLE2.TABLE[0] 28_666 -CMT_TOP_R_UPPER_T.PLLE2.TABLE[1] 29_667 -CMT_TOP_R_UPPER_T.PLLE2.TABLE[2] 28_668 -CMT_TOP_R_UPPER_T.PLLE2.TABLE[3] 29_669 -CMT_TOP_R_UPPER_T.PLLE2.TABLE[4] 28_670 -CMT_TOP_R_UPPER_T.PLLE2.TABLE[5] 29_671 -CMT_TOP_R_UPPER_T.PLLE2.TABLE[6] 28_660 -CMT_TOP_R_UPPER_T.PLLE2.TABLE[7] 29_661 -CMT_TOP_R_UPPER_T.PLLE2.TABLE[8] 28_662 -CMT_TOP_R_UPPER_T.PLLE2.TABLE[9] 29_663 -CMT_TOP_R_UPPER_T.PLLE2.ZINV_PWRDWN 29_752 -CMT_TOP_R_UPPER_T.PLLE2.ZINV_RST 28_752 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[0] 28_99 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[1] 29_99 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[2] 28_100 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[3] 29_100 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[4] 28_101 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[5] 29_101 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[0] 28_96 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[1] 29_96 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[2] 28_97 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[3] 29_97 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[4] 28_98 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[5] 29_98 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_OUTPUT_ENABLE[0] 28_102 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[0] 29_102 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[1] 28_103 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[2] 29_103 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[0] 28_104 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[1] 29_104 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[2] 28_105 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[3] 29_105 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[4] 28_106 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[5] 29_106 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_EDGE[0] 29_107 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[0] 28_110 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[1] 29_110 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[2] 28_111 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC_EN[0] 29_109 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC_WF_R[0] 28_109 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_MX[0] 28_108 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_MX[1] 29_108 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_NO_COUNT[0] 28_107 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_RESERVED[0] 29_111 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[0] 28_115 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[1] 29_115 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[2] 28_116 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[3] 29_116 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[4] 28_117 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[5] 29_117 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[0] 28_112 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[1] 29_112 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[2] 28_113 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[3] 29_113 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[4] 28_114 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[5] 29_114 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_OUTPUT_ENABLE[0] 28_118 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[0] 29_118 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[1] 28_119 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[2] 29_119 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[0] 28_120 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[1] 29_120 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[2] 28_121 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[3] 29_121 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[4] 28_122 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[5] 29_122 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_EDGE[0] 29_123 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[0] 28_126 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[1] 29_126 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[2] 28_127 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC_EN[0] 29_125 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC_WF_R[0] 28_125 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_MX[0] 28_124 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_MX[1] 29_124 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_NO_COUNT[0] 28_123 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_RESERVED[0] 29_127 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[0] 28_131 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[1] 29_131 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[2] 28_132 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[3] 29_132 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[4] 28_133 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[5] 29_133 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[0] 28_128 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[1] 29_128 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[2] 28_129 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[3] 29_129 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[4] 28_130 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[5] 29_130 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_OUTPUT_ENABLE[0] 28_134 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[0] 29_134 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[1] 28_135 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[2] 29_135 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[0] 28_136 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[1] 29_136 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[2] 28_137 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[3] 29_137 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[4] 28_138 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[5] 29_138 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_EDGE[0] 29_139 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[0] 28_142 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[1] 29_142 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[2] 28_143 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC_EN[0] 29_141 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC_WF_R[0] 28_141 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_MX[0] 28_140 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_MX[1] 29_140 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_NO_COUNT[0] 28_139 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_RESERVED[0] 29_143 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[0] 28_147 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[1] 29_147 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[2] 28_148 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[3] 29_148 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[4] 28_149 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[5] 29_149 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[0] 28_144 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[1] 29_144 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[2] 28_145 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[3] 29_145 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[4] 28_146 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[5] 29_146 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_OUTPUT_ENABLE[0] 28_150 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[0] 29_150 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[1] 28_151 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[2] 29_151 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[0] 28_152 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[1] 29_152 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[2] 28_153 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[3] 29_153 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[4] 28_154 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[5] 29_154 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_EDGE[0] 29_155 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[0] 28_158 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[1] 29_158 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[2] 28_159 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC_EN[0] 29_157 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC_WF_R[0] 28_157 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_MX[0] 28_156 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_MX[1] 29_156 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_NO_COUNT[0] 28_155 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_RESERVED[0] 29_159 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[0] 28_163 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[1] 29_163 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[2] 28_164 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[3] 29_164 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[4] 28_165 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[5] 29_165 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[0] 28_160 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[1] 29_160 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[2] 28_161 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[3] 29_161 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[4] 28_162 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[5] 29_162 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_OUTPUT_ENABLE[0] 28_166 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[0] 29_166 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[1] 28_167 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[2] 29_167 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[0] 28_168 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[1] 29_168 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[2] 28_169 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[3] 29_169 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[4] 28_170 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[5] 29_170 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_EDGE[0] 29_171 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[0] 28_174 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[1] 29_174 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[2] 28_175 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC_EN[0] 29_173 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC_WF_R[0] 28_173 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_MX[0] 28_172 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_MX[1] 29_172 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_NO_COUNT[0] 28_171 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_RESERVED[0] 29_175 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[0] 28_83 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[1] 29_83 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[2] 28_84 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[3] 29_84 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[4] 28_85 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[5] 29_85 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[0] 28_80 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[1] 29_80 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[2] 28_81 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[3] 29_81 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[4] 28_82 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[5] 29_82 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_OUTPUT_ENABLE[0] 28_86 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[0] 29_86 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[1] 28_87 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[2] 29_87 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[0] 28_88 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[1] 29_88 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[2] 28_89 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[3] 29_89 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[4] 28_90 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[5] 29_90 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_EDGE[0] 29_91 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[0] 28_94 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[1] 29_94 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[2] 28_95 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC_EN[0] 29_93 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC_WF_R[0] 28_93 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_MX[0] 28_92 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_MX[1] 29_92 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_NO_COUNT[0] 28_91 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_RESERVED[0] 29_95 -CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[0] 28_656 -CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[1] 29_656 -CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[2] 28_657 -CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[3] 29_657 -CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[4] 28_658 -CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[5] 29_658 -CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[6] 28_659 -CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[7] 29_659 -CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[8] 29_660 -CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[9] 28_661 -CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[10] 29_662 -CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[11] 28_663 -CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[0] 28_664 -CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[1] 29_664 -CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[2] 28_665 -CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[3] 29_665 -CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[4] 29_666 -CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[5] 28_667 -CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[6] 29_668 -CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[7] 28_669 -CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[8] 29_670 -CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[9] 28_671 -CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[0] 28_229 -CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[1] 29_229 -CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[2] 28_230 -CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[3] 29_230 -CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[4] 28_231 -CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[5] 29_231 -CMT_TOP_R_UPPER_T.PLLE2.LOCKREG2_RESERVED[0] 29_239 -CMT_TOP_R_UPPER_T.PLLE2.LOCKREG3_RESERVED[0] 29_247 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[0] 28_195 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[1] 29_195 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[2] 28_196 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[3] 29_196 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[4] 28_197 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[5] 29_197 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[0] 28_192 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[1] 29_192 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[2] 28_193 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[3] 29_193 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[4] 28_194 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[5] 29_194 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE[0] 28_198 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_PHASE_MUX[0] 29_198 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_PHASE_MUX[1] 28_199 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_PHASE_MUX[2] 29_199 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[0] 28_200 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[1] 29_200 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[2] 28_201 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[3] 29_201 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[4] 28_202 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[5] 29_202 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_EDGE[0] 29_203 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_FRAC[0] 28_206 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_FRAC[1] 29_206 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_FRAC[2] 28_207 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_FRAC_EN[0] 29_205 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_FRAC_WF_R[0] 28_205 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_MX[0] 28_204 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_MX[1] 29_204 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_NO_COUNT[0] 28_203 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_RESERVED[0] 29_207 +CMT_TOP_R_UPPER_T.PLLE2_ADV.COMPENSATION.Z_ZHOLD_OR_CLKIN_BUF 29_35 29_76 +CMT_TOP_R_UPPER_T.PLLE2_ADV.COMPENSATION.ZHOLD_NO_CLKIN_BUF 28_73 29_36 +CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_EDGE[0] 29_214 +CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_HIGH_TIME[0] 28_211 +CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_HIGH_TIME[1] 29_211 +CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_HIGH_TIME[2] 28_212 +CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_HIGH_TIME[3] 29_212 +CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_HIGH_TIME[4] 28_213 +CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_HIGH_TIME[5] 29_213 +CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_LOW_TIME[0] 28_208 +CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_LOW_TIME[1] 29_208 +CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_LOW_TIME[2] 28_209 +CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_LOW_TIME[3] 29_209 +CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_LOW_TIME[4] 28_210 +CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_LOW_TIME[5] 29_210 +CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_NO_COUNT[0] 28_214 +CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_RESERVED[0] 28_215 +CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_RESERVED[1] 29_215 +CMT_TOP_R_UPPER_T.PLLE2_ADV.IN_USE 28_37 28_48 28_74 28_78 28_216 28_219 28_222 28_266 28_280 28_283 28_284 28_592 28_622 28_623 28_624 28_627 28_628 28_768 28_785 28_786 28_787 28_788 28_790 28_791 28_792 28_793 28_795 28_796 28_797 28_798 28_799 28_803 28_806 28_807 28_811 28_812 28_815 28_816 28_817 28_818 28_819 28_821 28_822 28_823 28_824 28_826 28_827 28_828 28_829 28_832 28_835 28_838 28_841 28_845 28_847 29_48 29_77 29_78 29_79 29_268 29_281 29_282 29_283 29_563 29_567 29_589 29_621 29_622 29_625 29_626 29_627 29_785 29_786 29_788 29_790 29_791 29_793 29_797 29_798 29_800 29_809 29_811 29_812 29_813 29_814 29_815 29_816 29_817 29_819 29_823 29_824 29_825 29_826 29_827 29_829 29_830 29_831 29_832 29_835 29_836 29_838 29_839 29_840 29_841 29_842 29_845 +CMT_TOP_R_UPPER_T.PLLE2_ADV.INV_CLKINSEL 28_754 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[0] 28_232 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[1] 29_232 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[2] 28_233 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[3] 29_233 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[4] 28_234 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[5] 29_234 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[6] 28_235 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[7] 29_235 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[8] 28_236 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[9] 29_236 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[10] 28_240 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[11] 29_240 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[12] 28_241 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[13] 29_241 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[14] 28_242 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[15] 29_242 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[16] 28_243 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[17] 29_243 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[18] 28_244 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[19] 29_244 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[20] 28_224 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[21] 29_224 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[22] 28_225 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[23] 29_225 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[24] 28_226 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[25] 29_226 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[26] 28_227 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[27] 29_227 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[28] 28_228 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[29] 29_228 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[30] 28_237 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[31] 29_237 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[32] 28_238 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[33] 29_238 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[34] 28_239 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[35] 28_245 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[36] 29_245 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[37] 28_246 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[38] 29_246 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[39] 28_247 +CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[0] 28_352 +CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[1] 29_352 +CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[2] 28_353 +CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[3] 29_353 +CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[4] 28_354 +CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[5] 29_354 +CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[6] 28_355 +CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[7] 29_355 +CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[8] 28_356 +CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[9] 29_356 +CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[10] 28_357 +CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[11] 29_357 +CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[12] 28_358 +CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[13] 29_358 +CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[14] 28_359 +CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[15] 29_359 +CMT_TOP_R_UPPER_T.PLLE2_ADV.STARTUP_WAIT 28_769 +CMT_TOP_R_UPPER_T.PLLE2_ADV.TABLE[0] 28_666 +CMT_TOP_R_UPPER_T.PLLE2_ADV.TABLE[1] 29_667 +CMT_TOP_R_UPPER_T.PLLE2_ADV.TABLE[2] 28_668 +CMT_TOP_R_UPPER_T.PLLE2_ADV.TABLE[3] 29_669 +CMT_TOP_R_UPPER_T.PLLE2_ADV.TABLE[4] 28_670 +CMT_TOP_R_UPPER_T.PLLE2_ADV.TABLE[5] 29_671 +CMT_TOP_R_UPPER_T.PLLE2_ADV.TABLE[6] 28_660 +CMT_TOP_R_UPPER_T.PLLE2_ADV.TABLE[7] 29_661 +CMT_TOP_R_UPPER_T.PLLE2_ADV.TABLE[8] 28_662 +CMT_TOP_R_UPPER_T.PLLE2_ADV.TABLE[9] 29_663 +CMT_TOP_R_UPPER_T.PLLE2_ADV.ZINV_PWRDWN 29_752 +CMT_TOP_R_UPPER_T.PLLE2_ADV.ZINV_RST 28_752 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[0] 28_99 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[1] 29_99 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[2] 28_100 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[3] 29_100 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[4] 28_101 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[5] 29_101 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[0] 28_96 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[1] 29_96 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[2] 28_97 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[3] 29_97 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[4] 28_98 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[5] 29_98 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_OUTPUT_ENABLE[0] 28_102 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_PHASE_MUX[0] 29_102 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_PHASE_MUX[1] 28_103 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_PHASE_MUX[2] 29_103 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[0] 28_104 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[1] 29_104 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[2] 28_105 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[3] 29_105 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[4] 28_106 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[5] 29_106 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_EDGE[0] 29_107 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_FRAC[0] 28_110 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_FRAC[1] 29_110 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_FRAC[2] 28_111 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_FRAC_EN[0] 29_109 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_FRAC_WF_R[0] 28_109 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_MX[0] 28_108 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_MX[1] 29_108 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_NO_COUNT[0] 28_107 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_RESERVED[0] 29_111 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[0] 28_115 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[1] 29_115 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[2] 28_116 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[3] 29_116 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[4] 28_117 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[5] 29_117 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[0] 28_112 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[1] 29_112 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[2] 28_113 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[3] 29_113 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[4] 28_114 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[5] 29_114 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_OUTPUT_ENABLE[0] 28_118 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_PHASE_MUX[0] 29_118 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_PHASE_MUX[1] 28_119 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_PHASE_MUX[2] 29_119 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[0] 28_120 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[1] 29_120 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[2] 28_121 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[3] 29_121 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[4] 28_122 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[5] 29_122 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_EDGE[0] 29_123 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_FRAC[0] 28_126 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_FRAC[1] 29_126 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_FRAC[2] 28_127 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_FRAC_EN[0] 29_125 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_FRAC_WF_R[0] 28_125 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_MX[0] 28_124 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_MX[1] 29_124 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_NO_COUNT[0] 28_123 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_RESERVED[0] 29_127 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[0] 28_131 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[1] 29_131 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[2] 28_132 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[3] 29_132 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[4] 28_133 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[5] 29_133 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[0] 28_128 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[1] 29_128 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[2] 28_129 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[3] 29_129 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[4] 28_130 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[5] 29_130 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_OUTPUT_ENABLE[0] 28_134 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_PHASE_MUX[0] 29_134 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_PHASE_MUX[1] 28_135 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_PHASE_MUX[2] 29_135 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[0] 28_136 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[1] 29_136 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[2] 28_137 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[3] 29_137 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[4] 28_138 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[5] 29_138 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_EDGE[0] 29_139 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_FRAC[0] 28_142 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_FRAC[1] 29_142 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_FRAC[2] 28_143 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_FRAC_EN[0] 29_141 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_FRAC_WF_R[0] 28_141 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_MX[0] 28_140 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_MX[1] 29_140 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_NO_COUNT[0] 28_139 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_RESERVED[0] 29_143 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[0] 28_147 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[1] 29_147 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[2] 28_148 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[3] 29_148 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[4] 28_149 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[5] 29_149 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[0] 28_144 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[1] 29_144 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[2] 28_145 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[3] 29_145 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[4] 28_146 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[5] 29_146 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_OUTPUT_ENABLE[0] 28_150 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_PHASE_MUX[0] 29_150 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_PHASE_MUX[1] 28_151 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_PHASE_MUX[2] 29_151 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[0] 28_152 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[1] 29_152 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[2] 28_153 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[3] 29_153 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[4] 28_154 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[5] 29_154 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_EDGE[0] 29_155 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_FRAC[0] 28_158 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_FRAC[1] 29_158 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_FRAC[2] 28_159 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_FRAC_EN[0] 29_157 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_FRAC_WF_R[0] 28_157 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_MX[0] 28_156 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_MX[1] 29_156 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_NO_COUNT[0] 28_155 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_RESERVED[0] 29_159 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[0] 28_163 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[1] 29_163 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[2] 28_164 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[3] 29_164 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[4] 28_165 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[5] 29_165 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[0] 28_160 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[1] 29_160 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[2] 28_161 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[3] 29_161 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[4] 28_162 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[5] 29_162 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_OUTPUT_ENABLE[0] 28_166 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_PHASE_MUX[0] 29_166 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_PHASE_MUX[1] 28_167 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_PHASE_MUX[2] 29_167 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[0] 28_168 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[1] 29_168 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[2] 28_169 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[3] 29_169 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[4] 28_170 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[5] 29_170 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_EDGE[0] 29_171 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_FRAC[0] 28_174 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_FRAC[1] 29_174 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_FRAC[2] 28_175 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_FRAC_EN[0] 29_173 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_FRAC_WF_R[0] 28_173 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_MX[0] 28_172 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_MX[1] 29_172 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_NO_COUNT[0] 28_171 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_RESERVED[0] 29_175 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[0] 28_83 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[1] 29_83 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[2] 28_84 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[3] 29_84 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[4] 28_85 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[5] 29_85 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[0] 28_80 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[1] 29_80 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[2] 28_81 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[3] 29_81 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[4] 28_82 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[5] 29_82 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_OUTPUT_ENABLE[0] 28_86 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_PHASE_MUX[0] 29_86 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_PHASE_MUX[1] 28_87 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_PHASE_MUX[2] 29_87 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_DELAY_TIME[0] 28_88 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_DELAY_TIME[1] 29_88 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_DELAY_TIME[2] 28_89 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_DELAY_TIME[3] 29_89 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_DELAY_TIME[4] 28_90 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_DELAY_TIME[5] 29_90 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_EDGE[0] 29_91 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_FRAC[0] 28_94 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_FRAC[1] 29_94 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_FRAC[2] 28_95 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_FRAC_EN[0] 29_93 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_FRAC_WF_R[0] 28_93 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_MX[0] 28_92 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_MX[1] 29_92 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_NO_COUNT[0] 28_91 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_RESERVED[0] 29_95 +CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[0] 28_656 +CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[1] 29_656 +CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[2] 28_657 +CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[3] 29_657 +CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[4] 28_658 +CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[5] 29_658 +CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[6] 28_659 +CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[7] 29_659 +CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[8] 29_660 +CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[9] 28_661 +CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[10] 29_662 +CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[11] 28_663 +CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[0] 28_664 +CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[1] 29_664 +CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[2] 28_665 +CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[3] 29_665 +CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[4] 29_666 +CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[5] 28_667 +CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[6] 29_668 +CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[7] 28_669 +CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[8] 29_670 +CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[9] 28_671 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LOCKREG1_RESERVED[0] 28_229 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LOCKREG1_RESERVED[1] 29_229 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LOCKREG1_RESERVED[2] 28_230 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LOCKREG1_RESERVED[3] 29_230 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LOCKREG1_RESERVED[4] 28_231 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LOCKREG1_RESERVED[5] 29_231 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LOCKREG2_RESERVED[0] 29_239 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LOCKREG3_RESERVED[0] 29_247 diff --git a/kintex7/segbits_cmt_top_r_upper_t.origin_info.db b/kintex7/segbits_cmt_top_r_upper_t.origin_info.db index 6ee0558..7a858c2 100644 --- a/kintex7/segbits_cmt_top_r_upper_t.origin_info.db +++ b/kintex7/segbits_cmt_top_r_upper_t.origin_info.db @@ -21,346 +21,346 @@ CMT_TOP_R_UPPER_T.PLL_CLK_FREQ_BB0_NS_ACTIVE origin:034-cmt-pll-pips 29_00 29_09 CMT_TOP_R_UPPER_T.PLL_CLK_FREQ_BB1_NS_ACTIVE origin:034-cmt-pll-pips 28_01 29_10 29_18 CMT_TOP_R_UPPER_T.PLL_CLK_FREQ_BB2_NS_ACTIVE origin:034-cmt-pll-pips 29_01 29_11 29_19 CMT_TOP_R_UPPER_T.PLL_CLK_FREQ_BB3_NS_ACTIVE origin:034-cmt-pll-pips 28_02 29_12 29_20 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_195 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_195 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_196 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_196 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_197 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_197 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_192 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_192 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_193 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_193 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_194 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_194 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_198 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_198 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_199 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_199 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_200 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_200 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_201 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_201 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_202 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_202 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_203 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_206 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_206 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_207 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_205 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_205 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_MX[0] origin:032-cmt-pll 28_204 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_MX[1] origin:032-cmt-pll 29_204 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_203 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_207 -CMT_TOP_R_UPPER_T.PLLE2.COMPENSATION.Z_ZHOLD_OR_CLKIN_BUF origin:032-cmt-pll 29_35 29_76 -CMT_TOP_R_UPPER_T.PLLE2.COMPENSATION.ZHOLD_NO_CLKIN_BUF origin:032-cmt-pll 28_73 29_36 -CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_EDGE[0] origin:032-cmt-pll 29_214 -CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[0] origin:032-cmt-pll 28_211 -CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[1] origin:032-cmt-pll 29_211 -CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[2] origin:032-cmt-pll 28_212 -CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[3] origin:032-cmt-pll 29_212 -CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[4] origin:032-cmt-pll 28_213 -CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[5] origin:032-cmt-pll 29_213 -CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[0] origin:032-cmt-pll 28_208 -CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[1] origin:032-cmt-pll 29_208 -CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[2] origin:032-cmt-pll 28_209 -CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[3] origin:032-cmt-pll 29_209 -CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[4] origin:032-cmt-pll 28_210 -CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[5] origin:032-cmt-pll 29_210 -CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_NO_COUNT[0] origin:032-cmt-pll 28_214 -CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_RESERVED[0] origin:032-cmt-pll 28_215 -CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_RESERVED[1] origin:032-cmt-pll 29_215 -CMT_TOP_R_UPPER_T.PLLE2.IN_USE origin:032-cmt-pll 28_216 28_219 28_222 28_266 28_280 28_283 28_284 28_37 28_48 28_592 28_622 28_623 28_624 28_627 28_628 28_74 28_768 28_78 28_785 28_786 28_787 28_788 28_790 28_791 28_792 28_793 28_795 28_796 28_797 28_798 28_799 28_803 28_806 28_807 28_811 28_812 28_815 28_816 28_817 28_818 28_819 28_821 28_822 28_823 28_824 28_826 28_827 28_828 28_829 28_832 28_835 28_838 28_841 28_845 28_847 29_268 29_281 29_282 29_283 29_48 29_563 29_567 29_589 29_621 29_622 29_625 29_626 29_627 29_77 29_78 29_785 29_786 29_788 29_79 29_790 29_791 29_793 29_797 29_798 29_800 29_809 29_811 29_812 29_813 29_814 29_815 29_816 29_817 29_819 29_823 29_824 29_825 29_826 29_827 29_829 29_830 29_831 29_832 29_835 29_836 29_838 29_839 29_840 29_841 29_842 29_845 -CMT_TOP_R_UPPER_T.PLLE2.INV_CLKINSEL origin:032-cmt-pll 28_754 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[0] origin:032-cmt-pll 28_232 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[1] origin:032-cmt-pll 29_232 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[2] origin:032-cmt-pll 28_233 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[3] origin:032-cmt-pll 29_233 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[4] origin:032-cmt-pll 28_234 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[5] origin:032-cmt-pll 29_234 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[6] origin:032-cmt-pll 28_235 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[7] origin:032-cmt-pll 29_235 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[8] origin:032-cmt-pll 28_236 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[9] origin:032-cmt-pll 29_236 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[10] origin:032-cmt-pll 28_240 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[11] origin:032-cmt-pll 29_240 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[12] origin:032-cmt-pll 28_241 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[13] origin:032-cmt-pll 29_241 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[14] origin:032-cmt-pll 28_242 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[15] origin:032-cmt-pll 29_242 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[16] origin:032-cmt-pll 28_243 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[17] origin:032-cmt-pll 29_243 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[18] origin:032-cmt-pll 28_244 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[19] origin:032-cmt-pll 29_244 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[20] origin:032-cmt-pll 28_224 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[21] origin:032-cmt-pll 29_224 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[22] origin:032-cmt-pll 28_225 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[23] origin:032-cmt-pll 29_225 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[24] origin:032-cmt-pll 28_226 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[25] origin:032-cmt-pll 29_226 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[26] origin:032-cmt-pll 28_227 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[27] origin:032-cmt-pll 29_227 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[28] origin:032-cmt-pll 28_228 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[29] origin:032-cmt-pll 29_228 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[30] origin:032-cmt-pll 28_237 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[31] origin:032-cmt-pll 29_237 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[32] origin:032-cmt-pll 28_238 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[33] origin:032-cmt-pll 29_238 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[34] origin:032-cmt-pll 28_239 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[35] origin:032-cmt-pll 28_245 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[36] origin:032-cmt-pll 29_245 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[37] origin:032-cmt-pll 28_246 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[38] origin:032-cmt-pll 29_246 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[39] origin:032-cmt-pll 28_247 -CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[0] origin:032-cmt-pll 28_352 -CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[1] origin:032-cmt-pll 29_352 -CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[2] origin:032-cmt-pll 28_353 -CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[3] origin:032-cmt-pll 29_353 -CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[4] origin:032-cmt-pll 28_354 -CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[5] origin:032-cmt-pll 29_354 -CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[6] origin:032-cmt-pll 28_355 -CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[7] origin:032-cmt-pll 29_355 -CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[8] origin:032-cmt-pll 28_356 -CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[9] origin:032-cmt-pll 29_356 -CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[10] origin:032-cmt-pll 28_357 -CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[11] origin:032-cmt-pll 29_357 -CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[12] origin:032-cmt-pll 28_358 -CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[13] origin:032-cmt-pll 29_358 -CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[14] origin:032-cmt-pll 28_359 -CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[15] origin:032-cmt-pll 29_359 -CMT_TOP_R_UPPER_T.PLLE2.STARTUP_WAIT origin:032-cmt-pll 28_769 -CMT_TOP_R_UPPER_T.PLLE2.TABLE[0] origin:032-cmt-pll 28_666 -CMT_TOP_R_UPPER_T.PLLE2.TABLE[1] origin:032-cmt-pll 29_667 -CMT_TOP_R_UPPER_T.PLLE2.TABLE[2] origin:032-cmt-pll 28_668 -CMT_TOP_R_UPPER_T.PLLE2.TABLE[3] origin:032-cmt-pll 29_669 -CMT_TOP_R_UPPER_T.PLLE2.TABLE[4] origin:032-cmt-pll 28_670 -CMT_TOP_R_UPPER_T.PLLE2.TABLE[5] origin:032-cmt-pll 29_671 -CMT_TOP_R_UPPER_T.PLLE2.TABLE[6] origin:032-cmt-pll 28_660 -CMT_TOP_R_UPPER_T.PLLE2.TABLE[7] origin:032-cmt-pll 29_661 -CMT_TOP_R_UPPER_T.PLLE2.TABLE[8] origin:032-cmt-pll 28_662 -CMT_TOP_R_UPPER_T.PLLE2.TABLE[9] origin:032-cmt-pll 29_663 -CMT_TOP_R_UPPER_T.PLLE2.ZINV_PWRDWN origin:032-cmt-pll 29_752 -CMT_TOP_R_UPPER_T.PLLE2.ZINV_RST origin:032-cmt-pll 28_752 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_99 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_99 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_100 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_100 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_101 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_101 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_96 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_96 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_97 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_97 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_98 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_98 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_102 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_102 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_103 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_103 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_104 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_104 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_105 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_105 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_106 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_106 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_107 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_110 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_110 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_111 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_109 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_109 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_MX[0] origin:032-cmt-pll 28_108 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_MX[1] origin:032-cmt-pll 29_108 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_107 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_111 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_115 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_115 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_116 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_116 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_117 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_117 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_112 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_112 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_113 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_113 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_114 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_114 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_118 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_118 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_119 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_119 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_120 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_120 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_121 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_121 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_122 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_122 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_123 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_126 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_126 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_127 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_125 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_125 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_MX[0] origin:032-cmt-pll 28_124 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_MX[1] origin:032-cmt-pll 29_124 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_123 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_127 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_131 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_131 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_132 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_132 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_133 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_133 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_128 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_128 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_129 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_129 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_130 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_130 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_134 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_134 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_135 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_135 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_136 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_136 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_137 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_137 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_138 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_138 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_139 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_142 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_142 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_143 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_141 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_141 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_MX[0] origin:032-cmt-pll 28_140 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_MX[1] origin:032-cmt-pll 29_140 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_139 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_143 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_147 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_147 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_148 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_148 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_149 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_149 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_144 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_144 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_145 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_145 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_146 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_146 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_150 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_150 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_151 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_151 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_152 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_152 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_153 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_153 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_154 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_154 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_155 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_158 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_158 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_159 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_157 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_157 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_MX[0] origin:032-cmt-pll 28_156 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_MX[1] origin:032-cmt-pll 29_156 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_155 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_159 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_163 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_163 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_164 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_164 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_165 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_165 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_160 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_160 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_161 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_161 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_162 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_162 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_166 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_166 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_167 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_167 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_168 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_168 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_169 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_169 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_170 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_170 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_171 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_174 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_174 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_175 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_173 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_173 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_MX[0] origin:032-cmt-pll 28_172 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_MX[1] origin:032-cmt-pll 29_172 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_171 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_175 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_83 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_83 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_84 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_84 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_85 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_85 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_80 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_80 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_81 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_81 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_82 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_82 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_86 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_86 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_87 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_87 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_88 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_88 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_89 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_89 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_90 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_90 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_91 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_94 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_94 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_95 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_93 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_93 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_MX[0] origin:032-cmt-pll 28_92 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_MX[1] origin:032-cmt-pll 29_92 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_91 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_95 -CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[0] origin:032-cmt-pll 28_656 -CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[1] origin:032-cmt-pll 29_656 -CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[2] origin:032-cmt-pll 28_657 -CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[3] origin:032-cmt-pll 29_657 -CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[4] origin:032-cmt-pll 28_658 -CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[5] origin:032-cmt-pll 29_658 -CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[6] origin:032-cmt-pll 28_659 -CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[7] origin:032-cmt-pll 29_659 -CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[8] origin:032-cmt-pll 29_660 -CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[9] origin:032-cmt-pll 28_661 -CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[10] origin:032-cmt-pll 29_662 -CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[11] origin:032-cmt-pll 28_663 -CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[0] origin:032-cmt-pll 28_664 -CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[1] origin:032-cmt-pll 29_664 -CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[2] origin:032-cmt-pll 28_665 -CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[3] origin:032-cmt-pll 29_665 -CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[4] origin:032-cmt-pll 29_666 -CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[5] origin:032-cmt-pll 28_667 -CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[6] origin:032-cmt-pll 29_668 -CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[7] origin:032-cmt-pll 28_669 -CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[8] origin:032-cmt-pll 29_670 -CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[9] origin:032-cmt-pll 28_671 -CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[0] origin:032-cmt-pll 28_229 -CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[1] origin:032-cmt-pll 29_229 -CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[2] origin:032-cmt-pll 28_230 -CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[3] origin:032-cmt-pll 29_230 -CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[4] origin:032-cmt-pll 28_231 -CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[5] origin:032-cmt-pll 29_231 -CMT_TOP_R_UPPER_T.PLLE2.LOCKREG2_RESERVED[0] origin:032-cmt-pll 29_239 -CMT_TOP_R_UPPER_T.PLLE2.LOCKREG3_RESERVED[0] origin:032-cmt-pll 29_247 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_195 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_195 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_196 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_196 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_197 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_197 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_192 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_192 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_193 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_193 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_194 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_194 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_198 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_198 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_199 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_199 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_200 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_200 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_201 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_201 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_202 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_202 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_203 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_206 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_206 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_207 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_205 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_205 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_MX[0] origin:032-cmt-pll 28_204 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_MX[1] origin:032-cmt-pll 29_204 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_203 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_207 +CMT_TOP_R_UPPER_T.PLLE2_ADV.COMPENSATION.Z_ZHOLD_OR_CLKIN_BUF origin:032-cmt-pll 29_35 29_76 +CMT_TOP_R_UPPER_T.PLLE2_ADV.COMPENSATION.ZHOLD_NO_CLKIN_BUF origin:032-cmt-pll 28_73 29_36 +CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_EDGE[0] origin:032-cmt-pll 29_214 +CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_HIGH_TIME[0] origin:032-cmt-pll 28_211 +CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_HIGH_TIME[1] origin:032-cmt-pll 29_211 +CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_HIGH_TIME[2] origin:032-cmt-pll 28_212 +CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_HIGH_TIME[3] origin:032-cmt-pll 29_212 +CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_HIGH_TIME[4] origin:032-cmt-pll 28_213 +CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_HIGH_TIME[5] origin:032-cmt-pll 29_213 +CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_LOW_TIME[0] origin:032-cmt-pll 28_208 +CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_LOW_TIME[1] origin:032-cmt-pll 29_208 +CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_LOW_TIME[2] origin:032-cmt-pll 28_209 +CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_LOW_TIME[3] origin:032-cmt-pll 29_209 +CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_LOW_TIME[4] origin:032-cmt-pll 28_210 +CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_LOW_TIME[5] origin:032-cmt-pll 29_210 +CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_NO_COUNT[0] origin:032-cmt-pll 28_214 +CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_RESERVED[0] origin:032-cmt-pll 28_215 +CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_RESERVED[1] origin:032-cmt-pll 29_215 +CMT_TOP_R_UPPER_T.PLLE2_ADV.IN_USE origin:032-cmt-pll 28_216 28_219 28_222 28_266 28_280 28_283 28_284 28_37 28_48 28_592 28_622 28_623 28_624 28_627 28_628 28_74 28_768 28_78 28_785 28_786 28_787 28_788 28_790 28_791 28_792 28_793 28_795 28_796 28_797 28_798 28_799 28_803 28_806 28_807 28_811 28_812 28_815 28_816 28_817 28_818 28_819 28_821 28_822 28_823 28_824 28_826 28_827 28_828 28_829 28_832 28_835 28_838 28_841 28_845 28_847 29_268 29_281 29_282 29_283 29_48 29_563 29_567 29_589 29_621 29_622 29_625 29_626 29_627 29_77 29_78 29_785 29_786 29_788 29_79 29_790 29_791 29_793 29_797 29_798 29_800 29_809 29_811 29_812 29_813 29_814 29_815 29_816 29_817 29_819 29_823 29_824 29_825 29_826 29_827 29_829 29_830 29_831 29_832 29_835 29_836 29_838 29_839 29_840 29_841 29_842 29_845 +CMT_TOP_R_UPPER_T.PLLE2_ADV.INV_CLKINSEL origin:032-cmt-pll 28_754 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[0] origin:032-cmt-pll 28_232 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[1] origin:032-cmt-pll 29_232 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[2] origin:032-cmt-pll 28_233 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[3] origin:032-cmt-pll 29_233 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[4] origin:032-cmt-pll 28_234 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[5] origin:032-cmt-pll 29_234 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[6] origin:032-cmt-pll 28_235 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[7] origin:032-cmt-pll 29_235 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[8] origin:032-cmt-pll 28_236 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[9] origin:032-cmt-pll 29_236 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[10] origin:032-cmt-pll 28_240 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[11] origin:032-cmt-pll 29_240 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[12] origin:032-cmt-pll 28_241 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[13] origin:032-cmt-pll 29_241 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[14] origin:032-cmt-pll 28_242 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[15] origin:032-cmt-pll 29_242 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[16] origin:032-cmt-pll 28_243 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[17] origin:032-cmt-pll 29_243 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[18] origin:032-cmt-pll 28_244 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[19] origin:032-cmt-pll 29_244 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[20] origin:032-cmt-pll 28_224 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[21] origin:032-cmt-pll 29_224 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[22] origin:032-cmt-pll 28_225 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[23] origin:032-cmt-pll 29_225 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[24] origin:032-cmt-pll 28_226 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[25] origin:032-cmt-pll 29_226 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[26] origin:032-cmt-pll 28_227 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[27] origin:032-cmt-pll 29_227 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[28] origin:032-cmt-pll 28_228 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[29] origin:032-cmt-pll 29_228 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[30] origin:032-cmt-pll 28_237 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[31] origin:032-cmt-pll 29_237 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[32] origin:032-cmt-pll 28_238 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[33] origin:032-cmt-pll 29_238 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[34] origin:032-cmt-pll 28_239 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[35] origin:032-cmt-pll 28_245 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[36] origin:032-cmt-pll 29_245 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[37] origin:032-cmt-pll 28_246 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[38] origin:032-cmt-pll 29_246 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[39] origin:032-cmt-pll 28_247 +CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[0] origin:032-cmt-pll 28_352 +CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[1] origin:032-cmt-pll 29_352 +CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[2] origin:032-cmt-pll 28_353 +CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[3] origin:032-cmt-pll 29_353 +CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[4] origin:032-cmt-pll 28_354 +CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[5] origin:032-cmt-pll 29_354 +CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[6] origin:032-cmt-pll 28_355 +CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[7] origin:032-cmt-pll 29_355 +CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[8] origin:032-cmt-pll 28_356 +CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[9] origin:032-cmt-pll 29_356 +CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[10] origin:032-cmt-pll 28_357 +CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[11] origin:032-cmt-pll 29_357 +CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[12] origin:032-cmt-pll 28_358 +CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[13] origin:032-cmt-pll 29_358 +CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[14] origin:032-cmt-pll 28_359 +CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[15] origin:032-cmt-pll 29_359 +CMT_TOP_R_UPPER_T.PLLE2_ADV.STARTUP_WAIT origin:032-cmt-pll 28_769 +CMT_TOP_R_UPPER_T.PLLE2_ADV.TABLE[0] origin:032-cmt-pll 28_666 +CMT_TOP_R_UPPER_T.PLLE2_ADV.TABLE[1] origin:032-cmt-pll 29_667 +CMT_TOP_R_UPPER_T.PLLE2_ADV.TABLE[2] origin:032-cmt-pll 28_668 +CMT_TOP_R_UPPER_T.PLLE2_ADV.TABLE[3] origin:032-cmt-pll 29_669 +CMT_TOP_R_UPPER_T.PLLE2_ADV.TABLE[4] origin:032-cmt-pll 28_670 +CMT_TOP_R_UPPER_T.PLLE2_ADV.TABLE[5] origin:032-cmt-pll 29_671 +CMT_TOP_R_UPPER_T.PLLE2_ADV.TABLE[6] origin:032-cmt-pll 28_660 +CMT_TOP_R_UPPER_T.PLLE2_ADV.TABLE[7] origin:032-cmt-pll 29_661 +CMT_TOP_R_UPPER_T.PLLE2_ADV.TABLE[8] origin:032-cmt-pll 28_662 +CMT_TOP_R_UPPER_T.PLLE2_ADV.TABLE[9] origin:032-cmt-pll 29_663 +CMT_TOP_R_UPPER_T.PLLE2_ADV.ZINV_PWRDWN origin:032-cmt-pll 29_752 +CMT_TOP_R_UPPER_T.PLLE2_ADV.ZINV_RST origin:032-cmt-pll 28_752 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_99 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_99 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_100 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_100 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_101 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_101 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_96 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_96 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_97 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_97 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_98 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_98 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_102 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_102 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_103 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_103 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_104 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_104 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_105 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_105 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_106 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_106 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_107 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_110 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_110 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_111 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_109 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_109 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_MX[0] origin:032-cmt-pll 28_108 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_MX[1] origin:032-cmt-pll 29_108 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_107 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_111 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_115 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_115 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_116 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_116 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_117 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_117 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_112 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_112 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_113 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_113 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_114 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_114 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_118 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_118 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_119 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_119 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_120 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_120 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_121 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_121 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_122 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_122 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_123 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_126 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_126 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_127 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_125 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_125 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_MX[0] origin:032-cmt-pll 28_124 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_MX[1] origin:032-cmt-pll 29_124 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_123 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_127 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_131 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_131 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_132 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_132 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_133 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_133 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_128 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_128 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_129 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_129 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_130 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_130 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_134 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_134 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_135 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_135 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_136 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_136 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_137 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_137 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_138 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_138 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_139 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_142 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_142 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_143 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_141 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_141 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_MX[0] origin:032-cmt-pll 28_140 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_MX[1] origin:032-cmt-pll 29_140 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_139 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_143 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_147 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_147 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_148 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_148 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_149 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_149 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_144 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_144 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_145 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_145 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_146 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_146 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_150 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_150 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_151 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_151 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_152 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_152 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_153 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_153 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_154 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_154 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_155 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_158 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_158 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_159 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_157 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_157 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_MX[0] origin:032-cmt-pll 28_156 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_MX[1] origin:032-cmt-pll 29_156 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_155 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_159 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_163 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_163 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_164 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_164 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_165 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_165 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_160 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_160 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_161 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_161 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_162 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_162 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_166 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_166 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_167 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_167 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_168 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_168 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_169 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_169 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_170 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_170 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_171 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_174 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_174 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_175 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_173 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_173 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_MX[0] origin:032-cmt-pll 28_172 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_MX[1] origin:032-cmt-pll 29_172 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_171 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_175 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_83 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_83 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_84 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_84 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_85 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_85 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_80 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_80 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_81 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_81 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_82 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_82 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_86 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_86 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_87 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_87 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_88 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_88 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_89 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_89 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_90 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_90 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_91 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_94 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_94 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_95 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_93 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_93 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_MX[0] origin:032-cmt-pll 28_92 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_MX[1] origin:032-cmt-pll 29_92 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_91 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_95 +CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[0] origin:032-cmt-pll 28_656 +CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[1] origin:032-cmt-pll 29_656 +CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[2] origin:032-cmt-pll 28_657 +CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[3] origin:032-cmt-pll 29_657 +CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[4] origin:032-cmt-pll 28_658 +CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[5] origin:032-cmt-pll 29_658 +CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[6] origin:032-cmt-pll 28_659 +CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[7] origin:032-cmt-pll 29_659 +CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[8] origin:032-cmt-pll 29_660 +CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[9] origin:032-cmt-pll 28_661 +CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[10] origin:032-cmt-pll 29_662 +CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[11] origin:032-cmt-pll 28_663 +CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[0] origin:032-cmt-pll 28_664 +CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[1] origin:032-cmt-pll 29_664 +CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[2] origin:032-cmt-pll 28_665 +CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[3] origin:032-cmt-pll 29_665 +CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[4] origin:032-cmt-pll 29_666 +CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[5] origin:032-cmt-pll 28_667 +CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[6] origin:032-cmt-pll 29_668 +CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[7] origin:032-cmt-pll 28_669 +CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[8] origin:032-cmt-pll 29_670 +CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[9] origin:032-cmt-pll 28_671 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LOCKREG1_RESERVED[0] origin:032-cmt-pll 28_229 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LOCKREG1_RESERVED[1] origin:032-cmt-pll 29_229 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LOCKREG1_RESERVED[2] origin:032-cmt-pll 28_230 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LOCKREG1_RESERVED[3] origin:032-cmt-pll 29_230 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LOCKREG1_RESERVED[4] origin:032-cmt-pll 28_231 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LOCKREG1_RESERVED[5] origin:032-cmt-pll 29_231 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LOCKREG2_RESERVED[0] origin:032-cmt-pll 29_239 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LOCKREG3_RESERVED[0] origin:032-cmt-pll 29_247 diff --git a/kintex7/segbits_int_l.origin_info.db b/kintex7/segbits_int_l.origin_info.db index 2ce0735..d95920e 100644 --- a/kintex7/segbits_int_l.origin_info.db +++ b/kintex7/segbits_int_l.origin_info.db @@ -301,7 +301,7 @@ INT_L.FAN_ALT0.FAN_BOUNCE4 origin:050-pip-seed !22_00 20_00 23_00 24_00 25_00 INT_L.FAN_ALT0.FAN_BOUNCE6 origin:050-pip-seed !23_00 20_00 22_00 24_00 25_00 INT_L.FAN_ALT0.LOGIC_OUTS_L0 origin:050-pip-seed !23_00 21_00 22_00 24_00 25_00 INT_L.FAN_ALT0.LOGIC_OUTS_L12 origin:050-pip-seed !22_00 21_00 23_00 24_00 25_00 -INT_L.FAN_ALT0.LOGIC_OUTS_L22 origin:050-pip-seed !22_00 !23_00 !25_00 21_00 24_00 +INT_L.FAN_ALT0.LOGIC_OUTS_L22 origin:056-pip-rem !22_00 !23_00 !25_00 21_00 24_00 INT_L.FAN_ALT0.SR1END_N3_3 origin:050-pip-seed !23_00 19_01 22_00 24_00 25_00 INT_L.FAN_ALT0.SS2END_N0_3 origin:050-pip-seed !22_00 !23_00 !24_00 17_00 25_00 INT_L.FAN_ALT0.SW2END_N0_3 origin:050-pip-seed !22_00 !23_00 !25_00 17_00 24_00 @@ -393,7 +393,7 @@ INT_L.FAN_ALT3.WW2END3 origin:050-pip-seed !22_56 !23_56 !24_56 19_57 25_56 INT_L.FAN_ALT4.BYP_BOUNCE_N3_3 origin:059-pip-byp-bounce !22_08 !23_08 !24_08 20_08 25_08 INT_L.FAN_ALT4.BYP_BOUNCE_N3_7 origin:059-pip-byp-bounce !22_08 !23_08 !25_08 20_08 24_08 INT_L.FAN_ALT4.FAN_BOUNCE2 origin:050-pip-seed !23_08 20_08 22_08 24_08 25_08 -INT_L.FAN_ALT4.FAN_BOUNCE7 origin:056-pip-rem !22_08 20_08 23_08 24_08 25_08 +INT_L.FAN_ALT4.FAN_BOUNCE7 origin:050-pip-seed !22_08 20_08 23_08 24_08 25_08 INT_L.FAN_ALT4.LOGIC_OUTS_L4 origin:050-pip-seed !23_08 21_08 22_08 24_08 25_08 INT_L.FAN_ALT4.LOGIC_OUTS_L8 origin:050-pip-seed !22_08 21_08 23_08 24_08 25_08 INT_L.FAN_ALT4.LOGIC_OUTS_L18 origin:050-pip-seed !22_08 !23_08 !25_08 21_08 24_08 @@ -1917,7 +1917,7 @@ INT_L.EE4BEG2.SE6END2 origin:050-pip-seed 03_41 06_40 INT_L.EE4BEG2.SS2END2 origin:050-pip-seed 03_40 05_43 INT_L.EE4BEG2.SS6END2 origin:050-pip-seed 05_43 06_40 INT_L.EE4BEG2.SW2END2 origin:050-pip-seed 02_41 05_43 -INT_L.EE4BEG2.SW6END2 origin:056-pip-rem 05_40 05_43 +INT_L.EE4BEG2.SW6END2 origin:050-pip-seed 05_40 05_43 INT_L.EE4BEG3.LOGIC_OUTS_L3 origin:050-pip-seed 02_57 07_57 INT_L.EE4BEG3.LOGIC_OUTS_L7 origin:050-pip-seed 02_57 04_58 INT_L.EE4BEG3.LOGIC_OUTS_L11 origin:050-pip-seed 03_56 04_58 @@ -2491,7 +2491,7 @@ INT_L.NN6BEG3.NN6END3 origin:050-pip-seed 02_54 07_55 INT_L.NN6BEG3.NW2END3 origin:050-pip-seed 03_54 04_52 INT_L.NN6BEG3.NW6END3 origin:050-pip-seed 04_52 07_55 INT_L.NN6BEG3.SE2END3 origin:050-pip-seed 03_54 05_54 -INT_L.NN6BEG3.SE6END3 origin:050-pip-seed 05_54 07_55 +INT_L.NN6BEG3.SE6END3 origin:056-pip-rem 05_54 07_55 INT_L.NN6BEG3.WW2END2 origin:050-pip-seed 02_55 04_52 INT_L.NN6BEG3.WW4END3 origin:050-pip-seed 04_52 04_55 INT_L.NR1BEG0.LOGIC_OUTS_L0 origin:050-pip-seed 11_07 14_07 @@ -2662,7 +2662,7 @@ INT_L.NW6BEG0.LOGIC_OUTS_L18 origin:050-pip-seed 05_01 07_03 INT_L.NW6BEG0.LOGIC_OUTS_L22 origin:050-pip-seed 06_02 07_03 INT_L.NW6BEG0.LV_L0 origin:056-pip-rem 04_03 06_02 INT_L.NW6BEG0.SS2END_N0_3 origin:050-pip-seed 02_03 04_00 -INT_L.NW6BEG0.SS6END_N0_3 origin:056-pip-rem 04_00 07_03 +INT_L.NW6BEG0.SS6END_N0_3 origin:050-pip-seed 04_00 07_03 INT_L.NW6BEG0.SW2END_N0_3 origin:050-pip-seed 03_02 04_00 INT_L.NW6BEG0.SW6END_N0_3 origin:050-pip-seed 04_00 04_03 INT_L.NW6BEG0.WW2END_N0_3 origin:050-pip-seed 02_02 02_03 @@ -3623,7 +3623,7 @@ INT_L.WW4BEG3.LOGIC_OUTS_L21 origin:050-pip-seed 06_48 07_49 INT_L.WW4BEG3.LV_L18 origin:056-pip-rem 05_48 07_49 INT_L.WW4BEG3.LH0 origin:056-pip-rem 04_50 05_48 INT_L.WW4BEG3.NE2END3 origin:050-pip-seed 02_49 05_51 -INT_L.WW4BEG3.NE6END3 origin:056-pip-rem 05_48 05_51 +INT_L.WW4BEG3.NE6END3 origin:050-pip-seed 05_48 05_51 INT_L.WW4BEG3.NN2END3 origin:050-pip-seed 03_48 05_51 INT_L.WW4BEG3.NN6END3 origin:050-pip-seed 05_51 06_48 INT_L.WW4BEG3.NW2END3 origin:050-pip-seed 02_49 03_49 diff --git a/kintex7/segbits_int_r.origin_info.db b/kintex7/segbits_int_r.origin_info.db index a2da8b9..08afa8e 100644 --- a/kintex7/segbits_int_r.origin_info.db +++ b/kintex7/segbits_int_r.origin_info.db @@ -329,7 +329,7 @@ INT_R.FAN_ALT3.WW2END3 origin:050-pip-seed !22_56 !23_56 !24_56 19_57 25_56 INT_R.FAN_ALT4.BYP_BOUNCE_N3_3 origin:059-pip-byp-bounce !22_08 !23_08 !24_08 20_08 25_08 INT_R.FAN_ALT4.BYP_BOUNCE_N3_7 origin:059-pip-byp-bounce !22_08 !23_08 !25_08 20_08 24_08 INT_R.FAN_ALT4.FAN_BOUNCE2 origin:050-pip-seed !23_08 20_08 22_08 24_08 25_08 -INT_R.FAN_ALT4.FAN_BOUNCE7 origin:056-pip-rem !22_08 20_08 23_08 24_08 25_08 +INT_R.FAN_ALT4.FAN_BOUNCE7 origin:050-pip-seed !22_08 20_08 23_08 24_08 25_08 INT_R.FAN_ALT4.LOGIC_OUTS4 origin:050-pip-seed !23_08 21_08 22_08 24_08 25_08 INT_R.FAN_ALT4.LOGIC_OUTS8 origin:050-pip-seed !22_08 21_08 23_08 24_08 25_08 INT_R.FAN_ALT4.LOGIC_OUTS18 origin:050-pip-seed !22_08 !23_08 !25_08 21_08 24_08 @@ -685,7 +685,7 @@ INT_R.EE4BEG1.SE6END1 origin:050-pip-seed 03_25 06_24 INT_R.EE4BEG1.SS2END1 origin:050-pip-seed 03_24 05_27 INT_R.EE4BEG1.SS6END1 origin:050-pip-seed 05_27 06_24 INT_R.EE4BEG1.SW2END1 origin:050-pip-seed 02_25 05_27 -INT_R.EE4BEG1.SW6END1 origin:050-pip-seed 05_24 05_27 +INT_R.EE4BEG1.SW6END1 origin:056-pip-rem 05_24 05_27 INT_R.EE4BEG2.LOGIC_OUTS2 origin:050-pip-seed 02_41 04_42 INT_R.EE4BEG2.LOGIC_OUTS6 origin:050-pip-seed 02_41 07_41 INT_R.EE4BEG2.LOGIC_OUTS10 origin:050-pip-seed 03_40 07_41 @@ -2273,7 +2273,7 @@ INT_R.NE6BEG3.NW6END3 origin:050-pip-seed 04_53 06_52 INT_R.NE6BEG3.SE2END3 origin:050-pip-seed 02_53 05_55 INT_R.NE6BEG3.SE6END3 origin:050-pip-seed 05_55 06_52 INT_R.NE6BEG3.WW2END2 origin:050-pip-seed 03_52 04_53 -INT_R.NE6BEG3.WW4END3 origin:050-pip-seed 04_53 05_52 +INT_R.NE6BEG3.WW4END3 origin:056-pip-rem 04_53 05_52 INT_R.NL1BEG0.LOGIC_OUTS1 origin:050-pip-seed 07_16 14_17 INT_R.NL1BEG0.LOGIC_OUTS5 origin:050-pip-seed 11_17 14_17 INT_R.NL1BEG0.LOGIC_OUTS9 origin:050-pip-seed 10_17 13_17 @@ -3321,7 +3321,7 @@ INT_R.SW6BEG2.LOGIC_OUTS14 origin:050-pip-seed 03_44 07_45 INT_R.SW6BEG2.LOGIC_OUTS16 origin:050-pip-seed 04_46 06_44 INT_R.SW6BEG2.LOGIC_OUTS20 origin:050-pip-seed 06_44 07_45 INT_R.SW6BEG2.EE2END2 origin:050-pip-seed 03_44 04_45 -INT_R.SW6BEG2.EE4END2 origin:050-pip-seed 04_45 05_44 +INT_R.SW6BEG2.EE4END2 origin:056-pip-rem 04_45 05_44 INT_R.SW6BEG2.LVB0 origin:056-pip-rem 04_46 05_44 INT_R.SW6BEG2.LVB12 origin:056-pip-rem 05_44 07_45 INT_R.SW6BEG2.NW2END3 origin:050-pip-seed 02_45 05_47 @@ -3344,7 +3344,7 @@ INT_R.SW6BEG3.NW2END_S0_0 origin:050-pip-seed 02_61 05_63 INT_R.SW6BEG3.NW6END_S0_0 origin:050-pip-seed 05_63 06_60 INT_R.SW6BEG3.WW4END_S0_0 origin:050-pip-seed 05_60 05_63 INT_R.SW6BEG3.EE2END3 origin:050-pip-seed 03_60 04_61 -INT_R.SW6BEG3.EE4END3 origin:050-pip-seed 04_61 05_60 +INT_R.SW6BEG3.EE4END3 origin:056-pip-rem 04_61 05_60 INT_R.SW6BEG3.LH0 origin:056-pip-rem 04_62 05_60 INT_R.SW6BEG3.LV18 origin:056-pip-rem 05_60 07_61 INT_R.SW6BEG3.SE2END3 origin:050-pip-seed 02_61 04_61 diff --git a/kintex7/segbits_liob33.db b/kintex7/segbits_liob33.db index 4d9f02a..e5c2ee6 100644 --- a/kintex7/segbits_liob33.db +++ b/kintex7/segbits_liob33.db @@ -48,6 +48,7 @@ LIOB33.IOB_Y1.IN_TERM.UNTUNED_SPLIT_40 38_04 38_06 39_05 39_07 LIOB33.IOB_Y1.IN_TERM.UNTUNED_SPLIT_50 38_04 !38_06 39_05 39_07 LIOB33.IOB_Y1.IN_TERM.UNTUNED_SPLIT_60 38_04 !38_06 !39_05 39_07 LIOB33.IOB_Y1.INTERMDISABLE.I 38_38 +LIOB33.IOB_Y1.LVDS_25_SSTL135_SSTL15.IN_DIFF 38_40 !38_42 39_41 LIOB33.IOB_Y1.LVTTL.DRIVE.I24 !38_00 !38_02 38_08 38_10 38_62 39_01 !39_09 !39_15 39_63 LIOB33.IOB_Y1.PULLTYPE.KEEPER !38_34 39_33 39_35 LIOB33.IOB_Y1.PULLTYPE.NONE !38_34 39_33 !39_35 @@ -57,8 +58,8 @@ LIOB33.IOB_Y1.ZIBUF_LOW_PWR 39_43 LIOB33.IOB_Y1.LVCMOS12.DRIVE.I4 !38_00 38_02 !38_08 !38_10 38_14 38_62 39_01 39_09 39_15 39_63 LIOB33.IOB_Y1.LVCMOS12.DRIVE.I12 38_00 !38_02 !38_08 !38_10 38_14 38_62 39_01 !39_09 39_15 39_63 LIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18.IN !38_40 38_42 39_41 +LIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVDS_25_LVTTL_SSTL135_SSTL15_TMDS_33.IN_ONLY !38_00 38_02 38_08 !38_10 38_14 !38_62 !39_01 39_09 !39_15 !39_63 LIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST !38_16 !38_18 !38_20 !38_22 !39_17 !39_21 -LIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.IN_ONLY !38_00 38_02 38_08 !38_10 38_14 !38_62 !39_01 39_09 !39_15 !39_63 LIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.SLEW.SLOW !38_16 38_18 !38_20 38_22 39_17 39_21 LIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_SSTL135_SSTL15.STEPDOWN 38_32 LIOB33.IOB_Y1.LVCMOS12_LVCMOS25.DRIVE.I8 !38_00 !38_02 38_08 !38_10 38_14 38_62 !39_01 !39_09 39_15 39_63 @@ -78,6 +79,5 @@ LIOB33.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I12_I8 !38_00 38_02 38_08 !38_10 38_62 39_01 LIOB33.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I12_I16 38_00 38_02 !38_08 !38_10 38_62 39_01 !39_09 !39_15 39_63 LIOB33.IOB_Y1.SSTL135.DRIVE.I_FIXED 38_00 !38_02 38_08 38_10 38_14 38_62 39_01 39_09 39_15 39_63 LIOB33.IOB_Y1.SSTL135_SSTL15.IN 38_40 !38_42 !39_41 -LIOB33.IOB_Y1.SSTL135_SSTL15.IN_DIFF 38_40 !38_42 39_41 LIOB33.IOB_Y1.SSTL135_SSTL15.SLEW.FAST 38_16 38_18 38_20 38_22 39_17 !39_21 LIOB33.OUT_DIFF 39_59 39_61 diff --git a/kintex7/segbits_liob33.origin_info.db b/kintex7/segbits_liob33.origin_info.db index 022593c..5c43c07 100644 --- a/kintex7/segbits_liob33.origin_info.db +++ b/kintex7/segbits_liob33.origin_info.db @@ -48,6 +48,7 @@ LIOB33.IOB_Y1.IN_TERM.UNTUNED_SPLIT_40 origin:030-iob 38_04 38_06 39_05 39_07 LIOB33.IOB_Y1.IN_TERM.UNTUNED_SPLIT_50 origin:030-iob !38_06 38_04 39_05 39_07 LIOB33.IOB_Y1.IN_TERM.UNTUNED_SPLIT_60 origin:030-iob !38_06 !39_05 38_04 39_07 LIOB33.IOB_Y1.INTERMDISABLE.I origin:030-iob 38_38 +LIOB33.IOB_Y1.LVDS_25_SSTL135_SSTL15.IN_DIFF origin:030-iob !38_42 38_40 39_41 LIOB33.IOB_Y1.LVTTL.DRIVE.I24 origin:030-iob !38_00 !38_02 !39_09 !39_15 38_08 38_10 38_62 39_01 39_63 LIOB33.IOB_Y1.PULLTYPE.KEEPER origin:030-iob !38_34 39_33 39_35 LIOB33.IOB_Y1.PULLTYPE.NONE origin:030-iob !38_34 !39_35 39_33 @@ -57,8 +58,8 @@ LIOB33.IOB_Y1.ZIBUF_LOW_PWR origin:030-iob 39_43 LIOB33.IOB_Y1.LVCMOS12.DRIVE.I4 origin:030-iob !38_00 !38_08 !38_10 38_02 38_14 38_62 39_01 39_09 39_15 39_63 LIOB33.IOB_Y1.LVCMOS12.DRIVE.I12 origin:030-iob !38_02 !38_08 !38_10 !39_09 38_00 38_14 38_62 39_01 39_15 39_63 LIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18.IN origin:030-iob !38_40 38_42 39_41 +LIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVDS_25_LVTTL_SSTL135_SSTL15_TMDS_33.IN_ONLY origin:030-iob !38_00 !38_10 !38_62 !39_01 !39_15 !39_63 38_02 38_08 38_14 39_09 LIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST origin:030-iob !38_16 !38_18 !38_20 !38_22 !39_17 !39_21 -LIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.IN_ONLY origin:030-iob !38_00 !38_10 !38_62 !39_01 !39_15 !39_63 38_02 38_08 38_14 39_09 LIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.SLEW.SLOW origin:030-iob !38_16 !38_20 38_18 38_22 39_17 39_21 LIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_SSTL135_SSTL15.STEPDOWN origin:030-iob 38_32 LIOB33.IOB_Y1.LVCMOS12_LVCMOS25.DRIVE.I8 origin:030-iob !38_00 !38_02 !38_10 !39_01 !39_09 38_08 38_14 38_62 39_15 39_63 @@ -78,6 +79,5 @@ LIOB33.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I12_I8 origin:030-iob !38_00 !38_10 !39_09 !3 LIOB33.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I12_I16 origin:030-iob !38_08 !38_10 !39_09 !39_15 38_00 38_02 38_62 39_01 39_63 LIOB33.IOB_Y1.SSTL135.DRIVE.I_FIXED origin:030-iob !38_02 38_00 38_08 38_10 38_14 38_62 39_01 39_09 39_15 39_63 LIOB33.IOB_Y1.SSTL135_SSTL15.IN origin:030-iob !38_42 !39_41 38_40 -LIOB33.IOB_Y1.SSTL135_SSTL15.IN_DIFF origin:030-iob !38_42 38_40 39_41 LIOB33.IOB_Y1.SSTL135_SSTL15.SLEW.FAST origin:030-iob !39_21 38_16 38_18 38_20 38_22 39_17 LIOB33.OUT_DIFF origin:030-iob 39_59 39_61 diff --git a/kintex7/segbits_riob33.db b/kintex7/segbits_riob33.db index a4b4403..bf489d5 100644 --- a/kintex7/segbits_riob33.db +++ b/kintex7/segbits_riob33.db @@ -48,6 +48,7 @@ RIOB33.IOB_Y1.IN_TERM.UNTUNED_SPLIT_40 38_04 38_06 39_05 39_07 RIOB33.IOB_Y1.IN_TERM.UNTUNED_SPLIT_50 38_04 !38_06 39_05 39_07 RIOB33.IOB_Y1.IN_TERM.UNTUNED_SPLIT_60 38_04 !38_06 !39_05 39_07 RIOB33.IOB_Y1.INTERMDISABLE.I 38_38 +RIOB33.IOB_Y1.LVDS_25_SSTL135_SSTL15.IN_DIFF 38_40 !38_42 39_41 RIOB33.IOB_Y1.LVTTL.DRIVE.I24 !38_00 !38_02 38_08 38_10 38_62 39_01 !39_09 !39_15 39_63 RIOB33.IOB_Y1.PULLTYPE.KEEPER !38_34 39_33 39_35 RIOB33.IOB_Y1.PULLTYPE.NONE !38_34 39_33 !39_35 @@ -57,8 +58,8 @@ RIOB33.IOB_Y1.ZIBUF_LOW_PWR 39_43 RIOB33.IOB_Y1.LVCMOS12.DRIVE.I4 !38_00 38_02 !38_08 !38_10 38_14 38_62 39_01 39_09 39_15 39_63 RIOB33.IOB_Y1.LVCMOS12.DRIVE.I12 38_00 !38_02 !38_08 !38_10 38_14 38_62 39_01 !39_09 39_15 39_63 RIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18.IN !38_40 38_42 39_41 +RIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVDS_25_LVTTL_SSTL135_SSTL15_TMDS_33.IN_ONLY !38_00 38_02 38_08 !38_10 38_14 !38_62 !39_01 39_09 !39_15 !39_63 RIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST !38_16 !38_18 !38_20 !38_22 !39_17 !39_21 -RIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.IN_ONLY !38_00 38_02 38_08 !38_10 38_14 !38_62 !39_01 39_09 !39_15 !39_63 RIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.SLEW.SLOW !38_16 38_18 !38_20 38_22 39_17 39_21 RIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_SSTL135_SSTL15.STEPDOWN 38_32 RIOB33.IOB_Y1.LVCMOS12_LVCMOS25.DRIVE.I8 !38_00 !38_02 38_08 !38_10 38_14 38_62 !39_01 !39_09 39_15 39_63 @@ -78,6 +79,5 @@ RIOB33.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I12_I8 !38_00 38_02 38_08 !38_10 38_62 39_01 RIOB33.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I12_I16 38_00 38_02 !38_08 !38_10 38_62 39_01 !39_09 !39_15 39_63 RIOB33.IOB_Y1.SSTL135.DRIVE.I_FIXED 38_00 !38_02 38_08 38_10 38_14 38_62 39_01 39_09 39_15 39_63 RIOB33.IOB_Y1.SSTL135_SSTL15.IN 38_40 !38_42 !39_41 -RIOB33.IOB_Y1.SSTL135_SSTL15.IN_DIFF 38_40 !38_42 39_41 RIOB33.IOB_Y1.SSTL135_SSTL15.SLEW.FAST 38_16 38_18 38_20 38_22 39_17 !39_21 RIOB33.OUT_DIFF 39_59 39_61 diff --git a/kintex7/segbits_riob33.origin_info.db b/kintex7/segbits_riob33.origin_info.db index 95c9159..cee7b38 100644 --- a/kintex7/segbits_riob33.origin_info.db +++ b/kintex7/segbits_riob33.origin_info.db @@ -48,6 +48,7 @@ RIOB33.IOB_Y1.IN_TERM.UNTUNED_SPLIT_40 origin:030-iob 38_04 38_06 39_05 39_07 RIOB33.IOB_Y1.IN_TERM.UNTUNED_SPLIT_50 origin:030-iob !38_06 38_04 39_05 39_07 RIOB33.IOB_Y1.IN_TERM.UNTUNED_SPLIT_60 origin:030-iob !38_06 !39_05 38_04 39_07 RIOB33.IOB_Y1.INTERMDISABLE.I origin:030-iob 38_38 +RIOB33.IOB_Y1.LVDS_25_SSTL135_SSTL15.IN_DIFF origin:030-iob !38_42 38_40 39_41 RIOB33.IOB_Y1.LVTTL.DRIVE.I24 origin:030-iob !38_00 !38_02 !39_09 !39_15 38_08 38_10 38_62 39_01 39_63 RIOB33.IOB_Y1.PULLTYPE.KEEPER origin:030-iob !38_34 39_33 39_35 RIOB33.IOB_Y1.PULLTYPE.NONE origin:030-iob !38_34 !39_35 39_33 @@ -57,8 +58,8 @@ RIOB33.IOB_Y1.ZIBUF_LOW_PWR origin:030-iob 39_43 RIOB33.IOB_Y1.LVCMOS12.DRIVE.I4 origin:030-iob !38_00 !38_08 !38_10 38_02 38_14 38_62 39_01 39_09 39_15 39_63 RIOB33.IOB_Y1.LVCMOS12.DRIVE.I12 origin:030-iob !38_02 !38_08 !38_10 !39_09 38_00 38_14 38_62 39_01 39_15 39_63 RIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18.IN origin:030-iob !38_40 38_42 39_41 +RIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVDS_25_LVTTL_SSTL135_SSTL15_TMDS_33.IN_ONLY origin:030-iob !38_00 !38_10 !38_62 !39_01 !39_15 !39_63 38_02 38_08 38_14 39_09 RIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST origin:030-iob !38_16 !38_18 !38_20 !38_22 !39_17 !39_21 -RIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.IN_ONLY origin:030-iob !38_00 !38_10 !38_62 !39_01 !39_15 !39_63 38_02 38_08 38_14 39_09 RIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.SLEW.SLOW origin:030-iob !38_16 !38_20 38_18 38_22 39_17 39_21 RIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_SSTL135_SSTL15.STEPDOWN origin:030-iob 38_32 RIOB33.IOB_Y1.LVCMOS12_LVCMOS25.DRIVE.I8 origin:030-iob !38_00 !38_02 !38_10 !39_01 !39_09 38_08 38_14 38_62 39_15 39_63 @@ -78,6 +79,5 @@ RIOB33.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I12_I8 origin:030-iob !38_00 !38_10 !39_09 !3 RIOB33.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I12_I16 origin:030-iob !38_08 !38_10 !39_09 !39_15 38_00 38_02 38_62 39_01 39_63 RIOB33.IOB_Y1.SSTL135.DRIVE.I_FIXED origin:030-iob !38_02 38_00 38_08 38_10 38_14 38_62 39_01 39_09 39_15 39_63 RIOB33.IOB_Y1.SSTL135_SSTL15.IN origin:030-iob !38_42 !39_41 38_40 -RIOB33.IOB_Y1.SSTL135_SSTL15.IN_DIFF origin:030-iob !38_42 38_40 39_41 RIOB33.IOB_Y1.SSTL135_SSTL15.SLEW.FAST origin:030-iob !39_21 38_16 38_18 38_20 38_22 39_17 RIOB33.OUT_DIFF origin:030-iob 39_59 39_61 diff --git a/zynq7/segbits_cmt_top_l_lower_b.db b/zynq7/segbits_cmt_top_l_lower_b.db index 2dee80d..b605f51 100644 --- a/zynq7/segbits_cmt_top_l_lower_b.db +++ b/zynq7/segbits_cmt_top_l_lower_b.db @@ -23,381 +23,381 @@ CMT_TOP_L_LOWER_B.MMCM_CLK_FREQ_BB_NS2_ACTIVE 28_1068 28_1076 29_1057 CMT_TOP_L_LOWER_B.MMCM_CLK_FREQ_BB_NS2.MMCM_CLK_FREQ_BB_REBUF2_NS 28_1072 29_1067 29_1075 29_1079 CMT_TOP_L_LOWER_B.MMCM_CLK_FREQ_BB_NS3_ACTIVE 28_1058 28_1069 28_1077 CMT_TOP_L_LOWER_B.MMCM_CLK_FREQ_BB_NS3.MMCM_CLK_FREQ_BB_REBUF3_NS 28_1073 29_1068 29_1076 29_1080 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[0] 29_860 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[1] 28_860 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[2] 29_859 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[3] 28_859 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[4] 29_858 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[5] 28_858 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[0] 29_863 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[1] 28_863 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[2] 29_862 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[3] 28_862 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[4] 29_861 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[5] 28_861 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE[0] 29_857 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_PHASE_MUX[0] 28_857 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_PHASE_MUX[1] 29_856 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_PHASE_MUX[2] 28_856 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[0] 29_855 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[1] 28_855 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[2] 29_854 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[3] 28_854 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[4] 29_853 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[5] 28_853 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_EDGE[0] 28_852 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC[0] 29_849 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC[1] 28_849 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC[2] 29_848 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC_EN[0] 28_850 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC_WF_R[0] 29_850 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_MX[0] 29_851 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_MX[1] 28_851 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_NO_COUNT[0] 29_852 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_RESERVED[0] 28_848 -CMT_TOP_L_LOWER_B.MMCME2.COMP.Z_ZHOLD 28_979 28_1020 -CMT_TOP_L_LOWER_B.MMCME2.COMP.ZHOLD 28_1019 29_982 -CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_EDGE[0] 28_841 -CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[0] 29_844 -CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[1] 28_844 -CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[2] 29_843 -CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[3] 28_843 -CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[4] 29_842 -CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[5] 28_842 -CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[0] 29_847 -CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[1] 28_847 -CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[2] 29_846 -CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[3] 28_846 -CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[4] 29_845 -CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[5] 28_845 -CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_NO_COUNT[0] 29_841 -CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_RESERVED[0] 29_840 -CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_RESERVED[1] 28_840 -CMT_TOP_L_LOWER_B.MMCME2.IN_USE 28_18 28_21 28_22 28_23 28_24 28_25 28_27 28_28 28_31 28_32 28_33 28_34 28_36 28_37 28_38 28_39 28_40 28_44 28_46 28_47 28_48 28_49 28_50 28_51 28_52 28_54 28_63 28_65 28_66 28_70 28_72 28_73 28_75 28_77 28_78 28_428 28_429 28_430 28_433 28_434 28_466 28_488 28_492 28_772 28_773 28_774 28_787 28_976 28_978 28_989 28_991 28_1007 29_16 29_18 29_22 29_25 29_28 29_31 29_34 29_35 29_36 29_37 29_39 29_40 29_41 29_42 29_44 29_45 29_46 29_47 29_48 29_51 29_52 29_56 29_57 29_60 29_64 29_65 29_66 29_67 29_68 29_70 29_71 29_72 29_73 29_75 29_76 29_77 29_78 29_95 29_427 29_428 29_431 29_432 29_433 29_463 29_771 29_772 29_775 29_789 29_833 29_836 29_839 29_977 29_981 29_987 29_990 29_991 29_1007 29_1018 -CMT_TOP_L_LOWER_B.MMCME2.INV_CLKINSEL 29_109 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[0] 29_823 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[1] 28_823 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[2] 29_822 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[3] 28_822 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[4] 29_821 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[5] 28_821 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[6] 29_820 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[7] 28_820 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[8] 29_819 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[9] 28_819 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[10] 29_815 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[11] 28_815 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[12] 29_814 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[13] 28_814 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[14] 29_813 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[15] 28_813 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[16] 29_812 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[17] 28_812 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[18] 29_811 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[19] 28_811 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[20] 29_831 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[21] 28_831 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[22] 29_830 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[23] 28_830 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[24] 29_829 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[25] 28_829 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[26] 29_828 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[27] 28_828 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[28] 29_827 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[29] 28_827 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[30] 29_818 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[31] 28_818 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[32] 29_817 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[33] 28_817 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[34] 29_816 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[35] 29_810 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[36] 28_810 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[37] 29_809 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[38] 28_809 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[39] 29_808 -CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[0] 29_703 -CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[1] 28_703 -CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[2] 29_702 -CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[3] 28_702 -CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[4] 29_701 -CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[5] 28_701 -CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[6] 29_700 -CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[7] 28_700 -CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[8] 29_699 -CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[9] 28_699 -CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[10] 29_698 -CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[11] 28_698 -CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[12] 29_697 -CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[13] 28_697 -CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[14] 29_696 -CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[15] 28_696 -CMT_TOP_L_LOWER_B.MMCME2.SS_EN 28_95 28_388 28_696 28_698 28_700 28_702 28_850 28_915 29_389 29_697 29_701 29_703 -CMT_TOP_L_LOWER_B.MMCME2.STARTUP_WAIT 29_94 -CMT_TOP_L_LOWER_B.MMCME2.TABLE[0] 29_389 -CMT_TOP_L_LOWER_B.MMCME2.TABLE[1] 28_388 -CMT_TOP_L_LOWER_B.MMCME2.TABLE[2] 29_387 -CMT_TOP_L_LOWER_B.MMCME2.TABLE[3] 28_386 -CMT_TOP_L_LOWER_B.MMCME2.TABLE[4] 29_385 -CMT_TOP_L_LOWER_B.MMCME2.TABLE[5] 28_384 -CMT_TOP_L_LOWER_B.MMCME2.TABLE[6] 29_395 -CMT_TOP_L_LOWER_B.MMCME2.TABLE[7] 28_394 -CMT_TOP_L_LOWER_B.MMCME2.TABLE[8] 29_393 -CMT_TOP_L_LOWER_B.MMCME2.TABLE[9] 28_392 -CMT_TOP_L_LOWER_B.MMCME2.ZINV_PSEN 28_110 -CMT_TOP_L_LOWER_B.MMCME2.ZINV_PSINCDEC 29_110 -CMT_TOP_L_LOWER_B.MMCME2.ZINV_PWRDWN 28_111 -CMT_TOP_L_LOWER_B.MMCME2.ZINV_RST 29_111 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[0] 29_956 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[1] 28_956 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[2] 29_955 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[3] 28_955 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[4] 29_954 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[5] 28_954 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[0] 29_959 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[1] 28_959 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[2] 29_958 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[3] 28_958 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[4] 29_957 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[5] 28_957 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_OUTPUT_ENABLE[0] 29_953 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_PHASE_MUX[0] 28_953 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_PHASE_MUX[1] 29_952 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_PHASE_MUX[2] 28_952 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[0] 29_951 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[1] 28_951 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[2] 29_950 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[3] 28_950 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[4] 29_949 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[5] 28_949 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_EDGE[0] 28_948 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC[0] 29_945 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC[1] 28_945 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC[2] 29_944 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC_EN[0] 28_946 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC_WF_R[0] 29_946 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_MX[0] 29_947 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_MX[1] 28_947 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_NO_COUNT[0] 29_948 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_RESERVED[0] 28_944 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[0] 29_940 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[1] 28_940 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[2] 29_939 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[3] 28_939 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[4] 29_938 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[5] 28_938 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[0] 29_943 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[1] 28_943 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[2] 29_942 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[3] 28_942 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[4] 29_941 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[5] 28_941 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_OUTPUT_ENABLE[0] 29_937 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_PHASE_MUX[0] 28_937 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_PHASE_MUX[1] 29_936 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_PHASE_MUX[2] 28_936 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[0] 29_935 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[1] 28_935 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[2] 29_934 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[3] 28_934 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[4] 29_933 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[5] 28_933 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_EDGE[0] 28_932 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC[0] 29_929 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC[1] 28_929 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC[2] 29_928 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC_EN[0] 28_930 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC_WF_R[0] 29_930 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_MX[0] 29_931 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_MX[1] 28_931 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_NO_COUNT[0] 29_932 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_RESERVED[0] 28_928 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[0] 29_924 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[1] 28_924 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[2] 29_923 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[3] 28_923 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[4] 29_922 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[5] 28_922 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[0] 29_927 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[1] 28_927 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[2] 29_926 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[3] 28_926 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[4] 29_925 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[5] 28_925 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_OUTPUT_ENABLE[0] 29_921 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_PHASE_MUX[0] 28_921 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_PHASE_MUX[1] 29_920 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_PHASE_MUX[2] 28_920 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[0] 29_919 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[1] 28_919 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[2] 29_918 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[3] 28_918 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[4] 29_917 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[5] 28_917 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_EDGE[0] 28_916 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC[0] 29_913 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC[1] 28_913 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC[2] 29_912 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC_EN[0] 28_914 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC_WF_R[0] 29_914 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_MX[0] 29_915 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_MX[1] 28_915 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_NO_COUNT[0] 29_916 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_RESERVED[0] 28_912 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[0] 29_908 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[1] 28_908 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[2] 29_907 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[3] 28_907 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[4] 29_906 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[5] 28_906 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[0] 29_911 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[1] 28_911 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[2] 29_910 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[3] 28_910 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[4] 29_909 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[5] 28_909 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_OUTPUT_ENABLE[0] 29_905 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_PHASE_MUX[0] 28_905 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_PHASE_MUX[1] 29_904 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_PHASE_MUX[2] 28_904 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[0] 29_903 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[1] 28_903 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[2] 29_902 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[3] 28_902 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[4] 29_901 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[5] 28_901 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_EDGE[0] 28_900 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC[0] 29_897 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC[1] 28_897 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC[2] 29_896 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC_EN[0] 28_898 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC_WF_R[0] 29_898 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_MX[0] 29_899 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_MX[1] 28_899 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_NO_COUNT[0] 29_900 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_RESERVED[0] 28_896 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[0] 29_892 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[1] 28_892 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[2] 29_891 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[3] 28_891 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[4] 29_890 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[5] 28_890 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[0] 29_895 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[1] 28_895 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[2] 29_894 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[3] 28_894 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[4] 29_893 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[5] 28_893 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_OUTPUT_ENABLE[0] 29_889 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_PHASE_MUX[0] 28_889 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_PHASE_MUX[1] 29_888 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_PHASE_MUX[2] 28_888 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[0] 29_887 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[1] 28_887 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[2] 29_886 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[3] 28_886 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[4] 29_885 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[5] 28_885 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_EDGE[0] 28_884 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC[0] 29_881 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC[1] 28_881 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC[2] 29_880 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC_EN[0] 28_882 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC_WF_R[0] 29_882 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_MX[0] 29_883 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_MX[1] 28_883 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_NO_COUNT[0] 29_884 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_RESERVED[0] 28_880 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[0] 29_972 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[1] 28_972 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[2] 29_971 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[3] 28_971 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[4] 29_970 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[5] 28_970 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[0] 29_975 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[1] 28_975 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[2] 29_974 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[3] 28_974 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[4] 29_973 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[5] 28_973 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_OUTPUT_ENABLE[0] 29_969 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_PHASE_MUX[0] 28_969 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_PHASE_MUX[1] 29_968 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_PHASE_MUX[2] 28_968 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[0] 29_967 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[1] 28_967 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[2] 29_966 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[3] 28_966 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[4] 29_965 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[5] 28_965 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_EDGE[0] 28_964 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_FRAC_WF_F[0] 29_962 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_MX[0] 29_963 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_MX[1] 28_963 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_NO_COUNT[0] 29_964 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[0] 28_962 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[1] 29_961 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[2] 28_961 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_RESERVED[0] 29_960 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_RESERVED[1] 28_960 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[0] 29_876 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[1] 28_876 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[2] 29_875 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[3] 28_875 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[4] 29_874 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[5] 28_874 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[0] 29_879 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[1] 28_879 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[2] 29_878 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[3] 28_878 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[4] 29_877 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[5] 28_877 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_OUTPUT_ENABLE[0] 29_873 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_PHASE_MUX[0] 28_873 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_PHASE_MUX[1] 29_872 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_PHASE_MUX[2] 28_872 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[0] 29_871 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[1] 28_871 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[2] 29_870 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[3] 28_870 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[4] 29_869 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[5] 28_869 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_EDGE[0] 28_868 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_FRAC_WF_F[0] 29_866 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_MX[0] 29_867 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_MX[1] 28_867 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_NO_COUNT[0] 29_868 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[0] 28_866 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[1] 29_865 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[2] 28_865 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_RESERVED[0] 29_864 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_RESERVED[1] 28_864 -CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[0] 29_399 -CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[1] 28_399 -CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[2] 29_398 -CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[3] 28_398 -CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[4] 29_397 -CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[5] 28_397 -CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[6] 29_396 -CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[7] 28_396 -CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[8] 28_395 -CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[9] 29_394 -CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[10] 28_393 -CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[11] 29_392 -CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[0] 29_391 -CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[1] 28_391 -CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[2] 29_390 -CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[3] 28_390 -CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[4] 28_389 -CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[5] 29_388 -CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[6] 28_387 -CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[7] 29_386 -CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[8] 28_385 -CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[9] 29_384 -CMT_TOP_L_LOWER_B.MMCME2.LOCKREG1_RESERVED[0] 29_826 -CMT_TOP_L_LOWER_B.MMCME2.LOCKREG1_RESERVED[1] 28_826 -CMT_TOP_L_LOWER_B.MMCME2.LOCKREG1_RESERVED[2] 29_825 -CMT_TOP_L_LOWER_B.MMCME2.LOCKREG1_RESERVED[3] 28_825 -CMT_TOP_L_LOWER_B.MMCME2.LOCKREG1_RESERVED[4] 29_824 -CMT_TOP_L_LOWER_B.MMCME2.LOCKREG1_RESERVED[5] 28_824 -CMT_TOP_L_LOWER_B.MMCME2.LOCKREG2_RESERVED[0] 28_816 -CMT_TOP_L_LOWER_B.MMCME2.LOCKREG3_RESERVED[0] 28_808 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[0] 29_860 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[1] 28_860 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[2] 29_859 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[3] 28_859 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[4] 29_858 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[5] 28_858 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[0] 29_863 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[1] 28_863 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[2] 29_862 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[3] 28_862 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[4] 29_861 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[5] 28_861 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE[0] 29_857 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_PHASE_MUX[0] 28_857 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_PHASE_MUX[1] 29_856 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_PHASE_MUX[2] 28_856 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[0] 29_855 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[1] 28_855 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[2] 29_854 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[3] 28_854 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[4] 29_853 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[5] 28_853 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_EDGE[0] 28_852 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_FRAC[0] 29_849 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_FRAC[1] 28_849 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_FRAC[2] 29_848 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_FRAC_EN[0] 28_850 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_FRAC_WF_R[0] 29_850 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_MX[0] 29_851 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_MX[1] 28_851 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_NO_COUNT[0] 29_852 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_RESERVED[0] 28_848 +CMT_TOP_L_LOWER_B.MMCME2_ADV.COMP.Z_ZHOLD 28_979 28_1020 +CMT_TOP_L_LOWER_B.MMCME2_ADV.COMP.ZHOLD 28_1019 29_982 +CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_EDGE[0] 28_841 +CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_HIGH_TIME[0] 29_844 +CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_HIGH_TIME[1] 28_844 +CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_HIGH_TIME[2] 29_843 +CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_HIGH_TIME[3] 28_843 +CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_HIGH_TIME[4] 29_842 +CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_HIGH_TIME[5] 28_842 +CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_LOW_TIME[0] 29_847 +CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_LOW_TIME[1] 28_847 +CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_LOW_TIME[2] 29_846 +CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_LOW_TIME[3] 28_846 +CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_LOW_TIME[4] 29_845 +CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_LOW_TIME[5] 28_845 +CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_NO_COUNT[0] 29_841 +CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_RESERVED[0] 29_840 +CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_RESERVED[1] 28_840 +CMT_TOP_L_LOWER_B.MMCME2_ADV.IN_USE 28_18 28_21 28_22 28_23 28_24 28_25 28_27 28_28 28_31 28_32 28_33 28_34 28_36 28_37 28_38 28_39 28_40 28_44 28_46 28_47 28_48 28_49 28_50 28_51 28_52 28_54 28_63 28_65 28_66 28_70 28_72 28_73 28_75 28_77 28_78 28_428 28_429 28_430 28_433 28_434 28_466 28_488 28_492 28_772 28_773 28_774 28_787 28_976 28_978 28_989 28_991 28_1007 29_16 29_18 29_22 29_25 29_28 29_31 29_34 29_35 29_36 29_37 29_39 29_40 29_41 29_42 29_44 29_45 29_46 29_47 29_48 29_51 29_52 29_56 29_57 29_60 29_64 29_65 29_66 29_67 29_68 29_70 29_71 29_72 29_73 29_75 29_76 29_77 29_78 29_95 29_427 29_428 29_431 29_432 29_433 29_463 29_771 29_772 29_775 29_789 29_833 29_836 29_839 29_977 29_981 29_987 29_990 29_991 29_1007 29_1018 +CMT_TOP_L_LOWER_B.MMCME2_ADV.INV_CLKINSEL 29_109 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[0] 29_823 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[1] 28_823 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[2] 29_822 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[3] 28_822 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[4] 29_821 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[5] 28_821 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[6] 29_820 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[7] 28_820 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[8] 29_819 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[9] 28_819 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[10] 29_815 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[11] 28_815 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[12] 29_814 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[13] 28_814 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[14] 29_813 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[15] 28_813 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[16] 29_812 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[17] 28_812 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[18] 29_811 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[19] 28_811 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[20] 29_831 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[21] 28_831 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[22] 29_830 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[23] 28_830 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[24] 29_829 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[25] 28_829 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[26] 29_828 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[27] 28_828 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[28] 29_827 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[29] 28_827 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[30] 29_818 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[31] 28_818 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[32] 29_817 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[33] 28_817 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[34] 29_816 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[35] 29_810 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[36] 28_810 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[37] 29_809 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[38] 28_809 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[39] 29_808 +CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[0] 29_703 +CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[1] 28_703 +CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[2] 29_702 +CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[3] 28_702 +CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[4] 29_701 +CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[5] 28_701 +CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[6] 29_700 +CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[7] 28_700 +CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[8] 29_699 +CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[9] 28_699 +CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[10] 29_698 +CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[11] 28_698 +CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[12] 29_697 +CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[13] 28_697 +CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[14] 29_696 +CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[15] 28_696 +CMT_TOP_L_LOWER_B.MMCME2_ADV.SS_EN 28_95 28_388 28_696 28_698 28_700 28_702 28_850 28_915 29_389 29_697 29_701 29_703 +CMT_TOP_L_LOWER_B.MMCME2_ADV.STARTUP_WAIT 29_94 +CMT_TOP_L_LOWER_B.MMCME2_ADV.TABLE[0] 29_389 +CMT_TOP_L_LOWER_B.MMCME2_ADV.TABLE[1] 28_388 +CMT_TOP_L_LOWER_B.MMCME2_ADV.TABLE[2] 29_387 +CMT_TOP_L_LOWER_B.MMCME2_ADV.TABLE[3] 28_386 +CMT_TOP_L_LOWER_B.MMCME2_ADV.TABLE[4] 29_385 +CMT_TOP_L_LOWER_B.MMCME2_ADV.TABLE[5] 28_384 +CMT_TOP_L_LOWER_B.MMCME2_ADV.TABLE[6] 29_395 +CMT_TOP_L_LOWER_B.MMCME2_ADV.TABLE[7] 28_394 +CMT_TOP_L_LOWER_B.MMCME2_ADV.TABLE[8] 29_393 +CMT_TOP_L_LOWER_B.MMCME2_ADV.TABLE[9] 28_392 +CMT_TOP_L_LOWER_B.MMCME2_ADV.ZINV_PSEN 28_110 +CMT_TOP_L_LOWER_B.MMCME2_ADV.ZINV_PSINCDEC 29_110 +CMT_TOP_L_LOWER_B.MMCME2_ADV.ZINV_PWRDWN 28_111 +CMT_TOP_L_LOWER_B.MMCME2_ADV.ZINV_RST 29_111 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[0] 29_956 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[1] 28_956 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[2] 29_955 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[3] 28_955 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[4] 29_954 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[5] 28_954 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[0] 29_959 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[1] 28_959 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[2] 29_958 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[3] 28_958 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[4] 29_957 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[5] 28_957 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_OUTPUT_ENABLE[0] 29_953 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_PHASE_MUX[0] 28_953 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_PHASE_MUX[1] 29_952 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_PHASE_MUX[2] 28_952 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[0] 29_951 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[1] 28_951 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[2] 29_950 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[3] 28_950 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[4] 29_949 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[5] 28_949 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_EDGE[0] 28_948 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_FRAC[0] 29_945 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_FRAC[1] 28_945 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_FRAC[2] 29_944 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_FRAC_EN[0] 28_946 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_FRAC_WF_R[0] 29_946 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_MX[0] 29_947 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_MX[1] 28_947 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_NO_COUNT[0] 29_948 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_RESERVED[0] 28_944 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[0] 29_940 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[1] 28_940 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[2] 29_939 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[3] 28_939 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[4] 29_938 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[5] 28_938 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[0] 29_943 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[1] 28_943 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[2] 29_942 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[3] 28_942 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[4] 29_941 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[5] 28_941 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_OUTPUT_ENABLE[0] 29_937 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_PHASE_MUX[0] 28_937 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_PHASE_MUX[1] 29_936 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_PHASE_MUX[2] 28_936 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[0] 29_935 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[1] 28_935 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[2] 29_934 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[3] 28_934 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[4] 29_933 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[5] 28_933 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_EDGE[0] 28_932 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_FRAC[0] 29_929 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_FRAC[1] 28_929 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_FRAC[2] 29_928 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_FRAC_EN[0] 28_930 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_FRAC_WF_R[0] 29_930 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_MX[0] 29_931 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_MX[1] 28_931 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_NO_COUNT[0] 29_932 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_RESERVED[0] 28_928 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[0] 29_924 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[1] 28_924 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[2] 29_923 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[3] 28_923 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[4] 29_922 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[5] 28_922 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[0] 29_927 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[1] 28_927 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[2] 29_926 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[3] 28_926 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[4] 29_925 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[5] 28_925 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_OUTPUT_ENABLE[0] 29_921 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_PHASE_MUX[0] 28_921 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_PHASE_MUX[1] 29_920 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_PHASE_MUX[2] 28_920 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[0] 29_919 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[1] 28_919 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[2] 29_918 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[3] 28_918 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[4] 29_917 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[5] 28_917 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_EDGE[0] 28_916 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_FRAC[0] 29_913 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_FRAC[1] 28_913 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_FRAC[2] 29_912 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_FRAC_EN[0] 28_914 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_FRAC_WF_R[0] 29_914 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_MX[0] 29_915 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_MX[1] 28_915 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_NO_COUNT[0] 29_916 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_RESERVED[0] 28_912 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[0] 29_908 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[1] 28_908 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[2] 29_907 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[3] 28_907 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[4] 29_906 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[5] 28_906 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[0] 29_911 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[1] 28_911 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[2] 29_910 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[3] 28_910 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[4] 29_909 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[5] 28_909 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_OUTPUT_ENABLE[0] 29_905 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_PHASE_MUX[0] 28_905 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_PHASE_MUX[1] 29_904 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_PHASE_MUX[2] 28_904 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[0] 29_903 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[1] 28_903 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[2] 29_902 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[3] 28_902 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[4] 29_901 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[5] 28_901 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_EDGE[0] 28_900 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_FRAC[0] 29_897 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_FRAC[1] 28_897 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_FRAC[2] 29_896 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_FRAC_EN[0] 28_898 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_FRAC_WF_R[0] 29_898 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_MX[0] 29_899 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_MX[1] 28_899 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_NO_COUNT[0] 29_900 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_RESERVED[0] 28_896 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[0] 29_892 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[1] 28_892 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[2] 29_891 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[3] 28_891 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[4] 29_890 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[5] 28_890 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[0] 29_895 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[1] 28_895 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[2] 29_894 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[3] 28_894 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[4] 29_893 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[5] 28_893 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_OUTPUT_ENABLE[0] 29_889 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_PHASE_MUX[0] 28_889 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_PHASE_MUX[1] 29_888 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_PHASE_MUX[2] 28_888 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[0] 29_887 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[1] 28_887 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[2] 29_886 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[3] 28_886 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[4] 29_885 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[5] 28_885 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_EDGE[0] 28_884 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_FRAC[0] 29_881 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_FRAC[1] 28_881 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_FRAC[2] 29_880 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_FRAC_EN[0] 28_882 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_FRAC_WF_R[0] 29_882 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_MX[0] 29_883 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_MX[1] 28_883 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_NO_COUNT[0] 29_884 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_RESERVED[0] 28_880 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[0] 29_972 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[1] 28_972 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[2] 29_971 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[3] 28_971 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[4] 29_970 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[5] 28_970 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[0] 29_975 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[1] 28_975 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[2] 29_974 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[3] 28_974 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[4] 29_973 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[5] 28_973 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_OUTPUT_ENABLE[0] 29_969 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_PHASE_MUX[0] 28_969 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_PHASE_MUX[1] 29_968 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_PHASE_MUX[2] 28_968 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[0] 29_967 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[1] 28_967 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[2] 29_966 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[3] 28_966 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[4] 29_965 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[5] 28_965 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_EDGE[0] 28_964 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_FRAC_WF_F[0] 29_962 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_MX[0] 29_963 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_MX[1] 28_963 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_NO_COUNT[0] 29_964 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[0] 28_962 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[1] 29_961 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[2] 28_961 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_RESERVED[0] 29_960 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_RESERVED[1] 28_960 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_HIGH_TIME[0] 29_876 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_HIGH_TIME[1] 28_876 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_HIGH_TIME[2] 29_875 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_HIGH_TIME[3] 28_875 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_HIGH_TIME[4] 29_874 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_HIGH_TIME[5] 28_874 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_LOW_TIME[0] 29_879 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_LOW_TIME[1] 28_879 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_LOW_TIME[2] 29_878 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_LOW_TIME[3] 28_878 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_LOW_TIME[4] 29_877 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_LOW_TIME[5] 28_877 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_OUTPUT_ENABLE[0] 29_873 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_PHASE_MUX[0] 28_873 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_PHASE_MUX[1] 29_872 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_PHASE_MUX[2] 28_872 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[0] 29_871 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[1] 28_871 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[2] 29_870 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[3] 28_870 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[4] 29_869 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[5] 28_869 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_EDGE[0] 28_868 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_FRAC_WF_F[0] 29_866 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_MX[0] 29_867 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_MX[1] 28_867 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_NO_COUNT[0] 29_868 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[0] 28_866 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[1] 29_865 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[2] 28_865 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_RESERVED[0] 29_864 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_RESERVED[1] 28_864 +CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[0] 29_399 +CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[1] 28_399 +CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[2] 29_398 +CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[3] 28_398 +CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[4] 29_397 +CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[5] 28_397 +CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[6] 29_396 +CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[7] 28_396 +CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[8] 28_395 +CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[9] 29_394 +CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[10] 28_393 +CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[11] 29_392 +CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[0] 29_391 +CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[1] 28_391 +CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[2] 29_390 +CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[3] 28_390 +CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[4] 28_389 +CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[5] 29_388 +CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[6] 28_387 +CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[7] 29_386 +CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[8] 28_385 +CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[9] 29_384 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LOCKREG1_RESERVED[0] 29_826 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LOCKREG1_RESERVED[1] 28_826 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LOCKREG1_RESERVED[2] 29_825 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LOCKREG1_RESERVED[3] 28_825 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LOCKREG1_RESERVED[4] 29_824 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LOCKREG1_RESERVED[5] 28_824 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LOCKREG2_RESERVED[0] 28_816 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LOCKREG3_RESERVED[0] 28_808 diff --git a/zynq7/segbits_cmt_top_l_lower_b.origin_info.db b/zynq7/segbits_cmt_top_l_lower_b.origin_info.db index 9a3a102..c980172 100644 --- a/zynq7/segbits_cmt_top_l_lower_b.origin_info.db +++ b/zynq7/segbits_cmt_top_l_lower_b.origin_info.db @@ -23,381 +23,381 @@ CMT_TOP_L_LOWER_B.MMCM_CLK_FREQ_BB_NS2_ACTIVE origin:034b-cmt-mmcm-pips 28_1068 CMT_TOP_L_LOWER_B.MMCM_CLK_FREQ_BB_NS2.MMCM_CLK_FREQ_BB_REBUF2_NS origin:034b-cmt-mmcm-pips 28_1072 29_1067 29_1075 29_1079 CMT_TOP_L_LOWER_B.MMCM_CLK_FREQ_BB_NS3_ACTIVE origin:034b-cmt-mmcm-pips 28_1058 28_1069 28_1077 CMT_TOP_L_LOWER_B.MMCM_CLK_FREQ_BB_NS3.MMCM_CLK_FREQ_BB_REBUF3_NS origin:034b-cmt-mmcm-pips 28_1073 29_1068 29_1076 29_1080 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_860 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_860 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_859 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_859 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_858 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_858 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_863 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_863 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_862 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_862 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_861 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_861 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_857 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_857 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_856 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_856 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_855 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_855 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_854 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_854 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_853 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_853 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_852 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_849 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_849 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_848 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_850 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_850 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_851 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_851 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_852 -CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_848 -CMT_TOP_L_LOWER_B.MMCME2.COMP.Z_ZHOLD origin:031-cmt-mmcm 28_1020 28_979 -CMT_TOP_L_LOWER_B.MMCME2.COMP.ZHOLD origin:031-cmt-mmcm 28_1019 29_982 -CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_EDGE[0] origin:031-cmt-mmcm 28_841 -CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[0] origin:031-cmt-mmcm 29_844 -CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[1] origin:031-cmt-mmcm 28_844 -CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[2] origin:031-cmt-mmcm 29_843 -CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[3] origin:031-cmt-mmcm 28_843 -CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[4] origin:031-cmt-mmcm 29_842 -CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[5] origin:031-cmt-mmcm 28_842 -CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[0] origin:031-cmt-mmcm 29_847 -CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[1] origin:031-cmt-mmcm 28_847 -CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[2] origin:031-cmt-mmcm 29_846 -CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[3] origin:031-cmt-mmcm 28_846 -CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[4] origin:031-cmt-mmcm 29_845 -CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[5] origin:031-cmt-mmcm 28_845 -CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_NO_COUNT[0] origin:031-cmt-mmcm 29_841 -CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_RESERVED[0] origin:031-cmt-mmcm 29_840 -CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_RESERVED[1] origin:031-cmt-mmcm 28_840 -CMT_TOP_L_LOWER_B.MMCME2.IN_USE origin:031-cmt-mmcm 28_1007 28_18 28_21 28_22 28_23 28_24 28_25 28_27 28_28 28_31 28_32 28_33 28_34 28_36 28_37 28_38 28_39 28_40 28_428 28_429 28_430 28_433 28_434 28_44 28_46 28_466 28_47 28_48 28_488 28_49 28_492 28_50 28_51 28_52 28_54 28_63 28_65 28_66 28_70 28_72 28_73 28_75 28_77 28_772 28_773 28_774 28_78 28_787 28_976 28_978 28_989 28_991 29_1007 29_1018 29_16 29_18 29_22 29_25 29_28 29_31 29_34 29_35 29_36 29_37 29_39 29_40 29_41 29_42 29_427 29_428 29_431 29_432 29_433 29_44 29_45 29_46 29_463 29_47 29_48 29_51 29_52 29_56 29_57 29_60 29_64 29_65 29_66 29_67 29_68 29_70 29_71 29_72 29_73 29_75 29_76 29_77 29_771 29_772 29_775 29_78 29_789 29_833 29_836 29_839 29_95 29_977 29_981 29_987 29_990 29_991 -CMT_TOP_L_LOWER_B.MMCME2.INV_CLKINSEL origin:031-cmt-mmcm 29_109 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[0] origin:031-cmt-mmcm 29_823 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[1] origin:031-cmt-mmcm 28_823 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[2] origin:031-cmt-mmcm 29_822 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[3] origin:031-cmt-mmcm 28_822 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[4] origin:031-cmt-mmcm 29_821 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[5] origin:031-cmt-mmcm 28_821 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[6] origin:031-cmt-mmcm 29_820 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[7] origin:031-cmt-mmcm 28_820 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[8] origin:031-cmt-mmcm 29_819 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[9] origin:031-cmt-mmcm 28_819 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[10] origin:031-cmt-mmcm 29_815 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[11] origin:031-cmt-mmcm 28_815 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[12] origin:031-cmt-mmcm 29_814 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[13] origin:031-cmt-mmcm 28_814 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[14] origin:031-cmt-mmcm 29_813 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[15] origin:031-cmt-mmcm 28_813 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[16] origin:031-cmt-mmcm 29_812 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[17] origin:031-cmt-mmcm 28_812 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[18] origin:031-cmt-mmcm 29_811 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[19] origin:031-cmt-mmcm 28_811 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[20] origin:031-cmt-mmcm 29_831 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[21] origin:031-cmt-mmcm 28_831 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[22] origin:031-cmt-mmcm 29_830 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[23] origin:031-cmt-mmcm 28_830 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[24] origin:031-cmt-mmcm 29_829 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[25] origin:031-cmt-mmcm 28_829 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[26] origin:031-cmt-mmcm 29_828 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[27] origin:031-cmt-mmcm 28_828 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[28] origin:031-cmt-mmcm 29_827 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[29] origin:031-cmt-mmcm 28_827 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[30] origin:031-cmt-mmcm 29_818 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[31] origin:031-cmt-mmcm 28_818 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[32] origin:031-cmt-mmcm 29_817 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[33] origin:031-cmt-mmcm 28_817 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[34] origin:031-cmt-mmcm 29_816 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[35] origin:031-cmt-mmcm 29_810 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[36] origin:031-cmt-mmcm 28_810 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[37] origin:031-cmt-mmcm 29_809 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[38] origin:031-cmt-mmcm 28_809 -CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[39] origin:031-cmt-mmcm 29_808 -CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[0] origin:031-cmt-mmcm 29_703 -CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[1] origin:031-cmt-mmcm 28_703 -CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[2] origin:031-cmt-mmcm 29_702 -CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[3] origin:031-cmt-mmcm 28_702 -CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[4] origin:031-cmt-mmcm 29_701 -CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[5] origin:031-cmt-mmcm 28_701 -CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[6] origin:031-cmt-mmcm 29_700 -CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[7] origin:031-cmt-mmcm 28_700 -CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[8] origin:031-cmt-mmcm 29_699 -CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[9] origin:031-cmt-mmcm 28_699 -CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[10] origin:031-cmt-mmcm 29_698 -CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[11] origin:031-cmt-mmcm 28_698 -CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[12] origin:031-cmt-mmcm 29_697 -CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[13] origin:031-cmt-mmcm 28_697 -CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[14] origin:031-cmt-mmcm 29_696 -CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[15] origin:031-cmt-mmcm 28_696 -CMT_TOP_L_LOWER_B.MMCME2.SS_EN origin:031-cmt-mmcm 28_388 28_696 28_698 28_700 28_702 28_850 28_915 28_95 29_389 29_697 29_701 29_703 -CMT_TOP_L_LOWER_B.MMCME2.STARTUP_WAIT origin:031-cmt-mmcm 29_94 -CMT_TOP_L_LOWER_B.MMCME2.TABLE[0] origin:031-cmt-mmcm 29_389 -CMT_TOP_L_LOWER_B.MMCME2.TABLE[1] origin:031-cmt-mmcm 28_388 -CMT_TOP_L_LOWER_B.MMCME2.TABLE[2] origin:031-cmt-mmcm 29_387 -CMT_TOP_L_LOWER_B.MMCME2.TABLE[3] origin:031-cmt-mmcm 28_386 -CMT_TOP_L_LOWER_B.MMCME2.TABLE[4] origin:031-cmt-mmcm 29_385 -CMT_TOP_L_LOWER_B.MMCME2.TABLE[5] origin:031-cmt-mmcm 28_384 -CMT_TOP_L_LOWER_B.MMCME2.TABLE[6] origin:031-cmt-mmcm 29_395 -CMT_TOP_L_LOWER_B.MMCME2.TABLE[7] origin:031-cmt-mmcm 28_394 -CMT_TOP_L_LOWER_B.MMCME2.TABLE[8] origin:031-cmt-mmcm 29_393 -CMT_TOP_L_LOWER_B.MMCME2.TABLE[9] origin:031-cmt-mmcm 28_392 -CMT_TOP_L_LOWER_B.MMCME2.ZINV_PSEN origin:031-cmt-mmcm 28_110 -CMT_TOP_L_LOWER_B.MMCME2.ZINV_PSINCDEC origin:031-cmt-mmcm 29_110 -CMT_TOP_L_LOWER_B.MMCME2.ZINV_PWRDWN origin:031-cmt-mmcm 28_111 -CMT_TOP_L_LOWER_B.MMCME2.ZINV_RST origin:031-cmt-mmcm 29_111 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_956 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_956 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_955 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_955 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_954 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_954 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_959 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_959 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_958 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_958 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_957 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_957 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_953 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_953 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_952 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_952 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_951 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_951 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_950 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_950 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_949 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_949 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_948 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_945 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_945 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_944 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_946 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_946 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_947 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_947 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_948 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_944 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_940 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_940 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_939 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_939 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_938 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_938 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_943 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_943 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_942 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_942 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_941 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_941 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_937 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_937 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_936 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_936 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_935 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_935 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_934 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_934 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_933 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_933 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_932 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_929 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_929 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_928 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_930 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_930 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_931 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_931 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_932 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_928 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_924 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_924 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_923 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_923 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_922 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_922 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_927 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_927 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_926 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_926 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_925 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_925 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_921 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_921 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_920 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_920 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_919 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_919 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_918 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_918 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_917 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_917 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_916 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_913 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_913 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_912 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_914 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_914 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_915 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_915 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_916 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_912 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_908 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_908 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_907 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_907 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_906 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_906 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_911 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_911 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_910 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_910 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_909 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_909 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_905 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_905 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_904 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_904 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_903 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_903 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_902 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_902 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_901 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_901 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_900 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_897 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_897 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_896 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_898 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_898 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_899 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_899 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_900 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_896 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_892 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_892 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_891 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_891 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_890 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_890 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_895 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_895 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_894 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_894 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_893 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_893 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_889 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_889 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_888 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_888 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_887 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_887 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_886 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_886 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_885 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_885 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_884 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_881 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_881 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_880 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_882 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_882 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_883 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_883 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_884 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_880 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_972 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_972 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_971 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_971 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_970 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_970 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_975 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_975 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_974 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_974 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_973 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_973 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_969 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_969 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_968 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_968 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[0] origin:031-cmt-mmcm 29_967 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[1] origin:031-cmt-mmcm 28_967 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[2] origin:031-cmt-mmcm 29_966 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[3] origin:031-cmt-mmcm 28_966 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[4] origin:031-cmt-mmcm 29_965 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[5] origin:031-cmt-mmcm 28_965 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_EDGE[0] origin:031-cmt-mmcm 28_964 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_FRAC_WF_F[0] origin:031-cmt-mmcm 29_962 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_MX[0] origin:031-cmt-mmcm 29_963 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_MX[1] origin:031-cmt-mmcm 28_963 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_NO_COUNT[0] origin:031-cmt-mmcm 29_964 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[0] origin:031-cmt-mmcm 28_962 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[1] origin:031-cmt-mmcm 29_961 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[2] origin:031-cmt-mmcm 28_961 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_RESERVED[0] origin:031-cmt-mmcm 29_960 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_RESERVED[1] origin:031-cmt-mmcm 28_960 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_876 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_876 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_875 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_875 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_874 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_874 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_879 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_879 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_878 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_878 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_877 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_877 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_873 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_873 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_872 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_872 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[0] origin:031-cmt-mmcm 29_871 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[1] origin:031-cmt-mmcm 28_871 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[2] origin:031-cmt-mmcm 29_870 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[3] origin:031-cmt-mmcm 28_870 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[4] origin:031-cmt-mmcm 29_869 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[5] origin:031-cmt-mmcm 28_869 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_EDGE[0] origin:031-cmt-mmcm 28_868 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_FRAC_WF_F[0] origin:031-cmt-mmcm 29_866 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_MX[0] origin:031-cmt-mmcm 29_867 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_MX[1] origin:031-cmt-mmcm 28_867 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_NO_COUNT[0] origin:031-cmt-mmcm 29_868 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[0] origin:031-cmt-mmcm 28_866 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[1] origin:031-cmt-mmcm 29_865 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[2] origin:031-cmt-mmcm 28_865 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_RESERVED[0] origin:031-cmt-mmcm 29_864 -CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_RESERVED[1] origin:031-cmt-mmcm 28_864 -CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[0] origin:031-cmt-mmcm 29_399 -CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[1] origin:031-cmt-mmcm 28_399 -CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[2] origin:031-cmt-mmcm 29_398 -CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[3] origin:031-cmt-mmcm 28_398 -CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[4] origin:031-cmt-mmcm 29_397 -CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[5] origin:031-cmt-mmcm 28_397 -CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[6] origin:031-cmt-mmcm 29_396 -CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[7] origin:031-cmt-mmcm 28_396 -CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[8] origin:031-cmt-mmcm 28_395 -CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[9] origin:031-cmt-mmcm 29_394 -CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[10] origin:031-cmt-mmcm 28_393 -CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[11] origin:031-cmt-mmcm 29_392 -CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[0] origin:031-cmt-mmcm 29_391 -CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[1] origin:031-cmt-mmcm 28_391 -CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[2] origin:031-cmt-mmcm 29_390 -CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[3] origin:031-cmt-mmcm 28_390 -CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[4] origin:031-cmt-mmcm 28_389 -CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[5] origin:031-cmt-mmcm 29_388 -CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[6] origin:031-cmt-mmcm 28_387 -CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[7] origin:031-cmt-mmcm 29_386 -CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[8] origin:031-cmt-mmcm 28_385 -CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[9] origin:031-cmt-mmcm 29_384 -CMT_TOP_L_LOWER_B.MMCME2.LOCKREG1_RESERVED[0] origin:031-cmt-mmcm 29_826 -CMT_TOP_L_LOWER_B.MMCME2.LOCKREG1_RESERVED[1] origin:031-cmt-mmcm 28_826 -CMT_TOP_L_LOWER_B.MMCME2.LOCKREG1_RESERVED[2] origin:031-cmt-mmcm 29_825 -CMT_TOP_L_LOWER_B.MMCME2.LOCKREG1_RESERVED[3] origin:031-cmt-mmcm 28_825 -CMT_TOP_L_LOWER_B.MMCME2.LOCKREG1_RESERVED[4] origin:031-cmt-mmcm 29_824 -CMT_TOP_L_LOWER_B.MMCME2.LOCKREG1_RESERVED[5] origin:031-cmt-mmcm 28_824 -CMT_TOP_L_LOWER_B.MMCME2.LOCKREG2_RESERVED[0] origin:031-cmt-mmcm 28_816 -CMT_TOP_L_LOWER_B.MMCME2.LOCKREG3_RESERVED[0] origin:031-cmt-mmcm 28_808 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_860 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_860 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_859 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_859 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_858 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_858 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_863 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_863 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_862 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_862 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_861 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_861 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_857 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_857 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_856 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_856 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_855 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_855 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_854 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_854 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_853 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_853 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_852 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_849 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_849 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_848 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_850 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_850 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_851 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_851 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_852 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_848 +CMT_TOP_L_LOWER_B.MMCME2_ADV.COMP.Z_ZHOLD origin:031-cmt-mmcm 28_1020 28_979 +CMT_TOP_L_LOWER_B.MMCME2_ADV.COMP.ZHOLD origin:031-cmt-mmcm 28_1019 29_982 +CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_EDGE[0] origin:031-cmt-mmcm 28_841 +CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_HIGH_TIME[0] origin:031-cmt-mmcm 29_844 +CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_HIGH_TIME[1] origin:031-cmt-mmcm 28_844 +CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_HIGH_TIME[2] origin:031-cmt-mmcm 29_843 +CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_HIGH_TIME[3] origin:031-cmt-mmcm 28_843 +CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_HIGH_TIME[4] origin:031-cmt-mmcm 29_842 +CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_HIGH_TIME[5] origin:031-cmt-mmcm 28_842 +CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_LOW_TIME[0] origin:031-cmt-mmcm 29_847 +CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_LOW_TIME[1] origin:031-cmt-mmcm 28_847 +CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_LOW_TIME[2] origin:031-cmt-mmcm 29_846 +CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_LOW_TIME[3] origin:031-cmt-mmcm 28_846 +CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_LOW_TIME[4] origin:031-cmt-mmcm 29_845 +CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_LOW_TIME[5] origin:031-cmt-mmcm 28_845 +CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_NO_COUNT[0] origin:031-cmt-mmcm 29_841 +CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_RESERVED[0] origin:031-cmt-mmcm 29_840 +CMT_TOP_L_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_RESERVED[1] origin:031-cmt-mmcm 28_840 +CMT_TOP_L_LOWER_B.MMCME2_ADV.IN_USE origin:031-cmt-mmcm 28_1007 28_18 28_21 28_22 28_23 28_24 28_25 28_27 28_28 28_31 28_32 28_33 28_34 28_36 28_37 28_38 28_39 28_40 28_428 28_429 28_430 28_433 28_434 28_44 28_46 28_466 28_47 28_48 28_488 28_49 28_492 28_50 28_51 28_52 28_54 28_63 28_65 28_66 28_70 28_72 28_73 28_75 28_77 28_772 28_773 28_774 28_78 28_787 28_976 28_978 28_989 28_991 29_1007 29_1018 29_16 29_18 29_22 29_25 29_28 29_31 29_34 29_35 29_36 29_37 29_39 29_40 29_41 29_42 29_427 29_428 29_431 29_432 29_433 29_44 29_45 29_46 29_463 29_47 29_48 29_51 29_52 29_56 29_57 29_60 29_64 29_65 29_66 29_67 29_68 29_70 29_71 29_72 29_73 29_75 29_76 29_77 29_771 29_772 29_775 29_78 29_789 29_833 29_836 29_839 29_95 29_977 29_981 29_987 29_990 29_991 +CMT_TOP_L_LOWER_B.MMCME2_ADV.INV_CLKINSEL origin:031-cmt-mmcm 29_109 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[0] origin:031-cmt-mmcm 29_823 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[1] origin:031-cmt-mmcm 28_823 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[2] origin:031-cmt-mmcm 29_822 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[3] origin:031-cmt-mmcm 28_822 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[4] origin:031-cmt-mmcm 29_821 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[5] origin:031-cmt-mmcm 28_821 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[6] origin:031-cmt-mmcm 29_820 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[7] origin:031-cmt-mmcm 28_820 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[8] origin:031-cmt-mmcm 29_819 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[9] origin:031-cmt-mmcm 28_819 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[10] origin:031-cmt-mmcm 29_815 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[11] origin:031-cmt-mmcm 28_815 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[12] origin:031-cmt-mmcm 29_814 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[13] origin:031-cmt-mmcm 28_814 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[14] origin:031-cmt-mmcm 29_813 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[15] origin:031-cmt-mmcm 28_813 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[16] origin:031-cmt-mmcm 29_812 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[17] origin:031-cmt-mmcm 28_812 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[18] origin:031-cmt-mmcm 29_811 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[19] origin:031-cmt-mmcm 28_811 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[20] origin:031-cmt-mmcm 29_831 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[21] origin:031-cmt-mmcm 28_831 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[22] origin:031-cmt-mmcm 29_830 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[23] origin:031-cmt-mmcm 28_830 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[24] origin:031-cmt-mmcm 29_829 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[25] origin:031-cmt-mmcm 28_829 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[26] origin:031-cmt-mmcm 29_828 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[27] origin:031-cmt-mmcm 28_828 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[28] origin:031-cmt-mmcm 29_827 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[29] origin:031-cmt-mmcm 28_827 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[30] origin:031-cmt-mmcm 29_818 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[31] origin:031-cmt-mmcm 28_818 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[32] origin:031-cmt-mmcm 29_817 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[33] origin:031-cmt-mmcm 28_817 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[34] origin:031-cmt-mmcm 29_816 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[35] origin:031-cmt-mmcm 29_810 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[36] origin:031-cmt-mmcm 28_810 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[37] origin:031-cmt-mmcm 29_809 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[38] origin:031-cmt-mmcm 28_809 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LKTABLE[39] origin:031-cmt-mmcm 29_808 +CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[0] origin:031-cmt-mmcm 29_703 +CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[1] origin:031-cmt-mmcm 28_703 +CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[2] origin:031-cmt-mmcm 29_702 +CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[3] origin:031-cmt-mmcm 28_702 +CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[4] origin:031-cmt-mmcm 29_701 +CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[5] origin:031-cmt-mmcm 28_701 +CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[6] origin:031-cmt-mmcm 29_700 +CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[7] origin:031-cmt-mmcm 28_700 +CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[8] origin:031-cmt-mmcm 29_699 +CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[9] origin:031-cmt-mmcm 28_699 +CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[10] origin:031-cmt-mmcm 29_698 +CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[11] origin:031-cmt-mmcm 28_698 +CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[12] origin:031-cmt-mmcm 29_697 +CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[13] origin:031-cmt-mmcm 28_697 +CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[14] origin:031-cmt-mmcm 29_696 +CMT_TOP_L_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[15] origin:031-cmt-mmcm 28_696 +CMT_TOP_L_LOWER_B.MMCME2_ADV.SS_EN origin:031-cmt-mmcm 28_388 28_696 28_698 28_700 28_702 28_850 28_915 28_95 29_389 29_697 29_701 29_703 +CMT_TOP_L_LOWER_B.MMCME2_ADV.STARTUP_WAIT origin:031-cmt-mmcm 29_94 +CMT_TOP_L_LOWER_B.MMCME2_ADV.TABLE[0] origin:031-cmt-mmcm 29_389 +CMT_TOP_L_LOWER_B.MMCME2_ADV.TABLE[1] origin:031-cmt-mmcm 28_388 +CMT_TOP_L_LOWER_B.MMCME2_ADV.TABLE[2] origin:031-cmt-mmcm 29_387 +CMT_TOP_L_LOWER_B.MMCME2_ADV.TABLE[3] origin:031-cmt-mmcm 28_386 +CMT_TOP_L_LOWER_B.MMCME2_ADV.TABLE[4] origin:031-cmt-mmcm 29_385 +CMT_TOP_L_LOWER_B.MMCME2_ADV.TABLE[5] origin:031-cmt-mmcm 28_384 +CMT_TOP_L_LOWER_B.MMCME2_ADV.TABLE[6] origin:031-cmt-mmcm 29_395 +CMT_TOP_L_LOWER_B.MMCME2_ADV.TABLE[7] origin:031-cmt-mmcm 28_394 +CMT_TOP_L_LOWER_B.MMCME2_ADV.TABLE[8] origin:031-cmt-mmcm 29_393 +CMT_TOP_L_LOWER_B.MMCME2_ADV.TABLE[9] origin:031-cmt-mmcm 28_392 +CMT_TOP_L_LOWER_B.MMCME2_ADV.ZINV_PSEN origin:031-cmt-mmcm 28_110 +CMT_TOP_L_LOWER_B.MMCME2_ADV.ZINV_PSINCDEC origin:031-cmt-mmcm 29_110 +CMT_TOP_L_LOWER_B.MMCME2_ADV.ZINV_PWRDWN origin:031-cmt-mmcm 28_111 +CMT_TOP_L_LOWER_B.MMCME2_ADV.ZINV_RST origin:031-cmt-mmcm 29_111 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_956 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_956 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_955 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_955 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_954 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_954 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_959 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_959 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_958 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_958 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_957 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_957 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_953 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_953 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_952 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_952 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_951 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_951 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_950 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_950 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_949 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_949 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_948 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_945 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_945 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_944 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_946 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_946 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_947 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_947 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_948 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_944 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_940 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_940 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_939 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_939 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_938 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_938 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_943 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_943 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_942 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_942 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_941 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_941 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_937 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_937 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_936 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_936 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_935 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_935 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_934 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_934 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_933 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_933 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_932 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_929 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_929 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_928 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_930 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_930 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_931 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_931 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_932 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_928 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_924 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_924 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_923 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_923 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_922 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_922 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_927 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_927 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_926 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_926 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_925 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_925 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_921 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_921 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_920 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_920 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_919 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_919 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_918 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_918 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_917 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_917 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_916 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_913 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_913 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_912 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_914 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_914 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_915 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_915 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_916 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_912 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_908 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_908 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_907 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_907 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_906 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_906 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_911 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_911 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_910 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_910 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_909 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_909 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_905 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_905 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_904 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_904 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_903 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_903 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_902 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_902 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_901 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_901 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_900 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_897 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_897 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_896 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_898 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_898 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_899 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_899 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_900 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_896 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_892 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_892 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_891 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_891 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_890 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_890 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_895 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_895 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_894 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_894 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_893 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_893 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_889 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_889 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_888 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_888 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_887 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_887 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_886 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_886 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_885 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_885 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_884 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_881 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_881 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_880 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_882 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_882 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_883 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_883 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_884 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_880 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_972 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_972 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_971 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_971 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_970 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_970 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_975 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_975 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_974 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_974 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_973 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_973 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_969 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_969 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_968 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_968 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[0] origin:031-cmt-mmcm 29_967 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[1] origin:031-cmt-mmcm 28_967 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[2] origin:031-cmt-mmcm 29_966 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[3] origin:031-cmt-mmcm 28_966 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[4] origin:031-cmt-mmcm 29_965 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[5] origin:031-cmt-mmcm 28_965 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_EDGE[0] origin:031-cmt-mmcm 28_964 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_FRAC_WF_F[0] origin:031-cmt-mmcm 29_962 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_MX[0] origin:031-cmt-mmcm 29_963 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_MX[1] origin:031-cmt-mmcm 28_963 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_NO_COUNT[0] origin:031-cmt-mmcm 29_964 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[0] origin:031-cmt-mmcm 28_962 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[1] origin:031-cmt-mmcm 29_961 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[2] origin:031-cmt-mmcm 28_961 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_RESERVED[0] origin:031-cmt-mmcm 29_960 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_RESERVED[1] origin:031-cmt-mmcm 28_960 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_876 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_876 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_875 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_875 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_874 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_874 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_879 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_879 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_878 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_878 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_877 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_877 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_873 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_873 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_872 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_872 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[0] origin:031-cmt-mmcm 29_871 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[1] origin:031-cmt-mmcm 28_871 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[2] origin:031-cmt-mmcm 29_870 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[3] origin:031-cmt-mmcm 28_870 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[4] origin:031-cmt-mmcm 29_869 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[5] origin:031-cmt-mmcm 28_869 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_EDGE[0] origin:031-cmt-mmcm 28_868 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_FRAC_WF_F[0] origin:031-cmt-mmcm 29_866 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_MX[0] origin:031-cmt-mmcm 29_867 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_MX[1] origin:031-cmt-mmcm 28_867 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_NO_COUNT[0] origin:031-cmt-mmcm 29_868 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[0] origin:031-cmt-mmcm 28_866 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[1] origin:031-cmt-mmcm 29_865 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[2] origin:031-cmt-mmcm 28_865 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_RESERVED[0] origin:031-cmt-mmcm 29_864 +CMT_TOP_L_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_RESERVED[1] origin:031-cmt-mmcm 28_864 +CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[0] origin:031-cmt-mmcm 29_399 +CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[1] origin:031-cmt-mmcm 28_399 +CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[2] origin:031-cmt-mmcm 29_398 +CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[3] origin:031-cmt-mmcm 28_398 +CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[4] origin:031-cmt-mmcm 29_397 +CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[5] origin:031-cmt-mmcm 28_397 +CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[6] origin:031-cmt-mmcm 29_396 +CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[7] origin:031-cmt-mmcm 28_396 +CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[8] origin:031-cmt-mmcm 28_395 +CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[9] origin:031-cmt-mmcm 29_394 +CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[10] origin:031-cmt-mmcm 28_393 +CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[11] origin:031-cmt-mmcm 29_392 +CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[0] origin:031-cmt-mmcm 29_391 +CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[1] origin:031-cmt-mmcm 28_391 +CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[2] origin:031-cmt-mmcm 29_390 +CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[3] origin:031-cmt-mmcm 28_390 +CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[4] origin:031-cmt-mmcm 28_389 +CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[5] origin:031-cmt-mmcm 29_388 +CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[6] origin:031-cmt-mmcm 28_387 +CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[7] origin:031-cmt-mmcm 29_386 +CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[8] origin:031-cmt-mmcm 28_385 +CMT_TOP_L_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[9] origin:031-cmt-mmcm 29_384 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LOCKREG1_RESERVED[0] origin:031-cmt-mmcm 29_826 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LOCKREG1_RESERVED[1] origin:031-cmt-mmcm 28_826 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LOCKREG1_RESERVED[2] origin:031-cmt-mmcm 29_825 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LOCKREG1_RESERVED[3] origin:031-cmt-mmcm 28_825 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LOCKREG1_RESERVED[4] origin:031-cmt-mmcm 29_824 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LOCKREG1_RESERVED[5] origin:031-cmt-mmcm 28_824 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LOCKREG2_RESERVED[0] origin:031-cmt-mmcm 28_816 +CMT_TOP_L_LOWER_B.MMCME2_ADV.LOCKREG3_RESERVED[0] origin:031-cmt-mmcm 28_808 diff --git a/zynq7/segbits_cmt_top_l_upper_t.db b/zynq7/segbits_cmt_top_l_upper_t.db index 4859101..c6958a3 100644 --- a/zynq7/segbits_cmt_top_l_upper_t.db +++ b/zynq7/segbits_cmt_top_l_upper_t.db @@ -21,346 +21,346 @@ CMT_TOP_L_UPPER_T.PLL_CLK_FREQ_BB0_NS_ACTIVE 29_00 29_09 29_17 CMT_TOP_L_UPPER_T.PLL_CLK_FREQ_BB1_NS_ACTIVE 28_01 29_10 29_18 CMT_TOP_L_UPPER_T.PLL_CLK_FREQ_BB2_NS_ACTIVE 29_01 29_11 29_19 CMT_TOP_L_UPPER_T.PLL_CLK_FREQ_BB3_NS_ACTIVE 28_02 29_12 29_20 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[0] 28_195 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[1] 29_195 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[2] 28_196 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[3] 29_196 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[4] 28_197 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[5] 29_197 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[0] 28_192 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[1] 29_192 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[2] 28_193 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[3] 29_193 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[4] 28_194 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[5] 29_194 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE[0] 28_198 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[0] 29_198 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[1] 28_199 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[2] 29_199 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[0] 28_200 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[1] 29_200 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[2] 28_201 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[3] 29_201 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[4] 28_202 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[5] 29_202 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_EDGE[0] 29_203 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[0] 28_206 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[1] 29_206 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[2] 28_207 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC_EN[0] 29_205 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC_WF_R[0] 28_205 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_MX[0] 28_204 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_MX[1] 29_204 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_NO_COUNT[0] 28_203 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_RESERVED[0] 29_207 -CMT_TOP_L_UPPER_T.PLLE2.COMPENSATION.Z_ZHOLD_OR_CLKIN_BUF 29_35 29_76 -CMT_TOP_L_UPPER_T.PLLE2.COMPENSATION.ZHOLD_NO_CLKIN_BUF 28_73 29_36 -CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_EDGE[0] 29_214 -CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[0] 28_211 -CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[1] 29_211 -CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[2] 28_212 -CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[3] 29_212 -CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[4] 28_213 -CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[5] 29_213 -CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[0] 28_208 -CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[1] 29_208 -CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[2] 28_209 -CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[3] 29_209 -CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[4] 28_210 -CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[5] 29_210 -CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_NO_COUNT[0] 28_214 -CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_RESERVED[0] 28_215 -CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_RESERVED[1] 29_215 -CMT_TOP_L_UPPER_T.PLLE2.IN_USE 28_37 28_48 28_74 28_78 28_216 28_219 28_222 28_266 28_280 28_283 28_284 28_592 28_622 28_623 28_624 28_627 28_628 28_768 28_785 28_786 28_787 28_788 28_790 28_791 28_792 28_793 28_795 28_796 28_797 28_798 28_799 28_803 28_806 28_807 28_811 28_812 28_815 28_816 28_817 28_818 28_819 28_821 28_822 28_823 28_824 28_826 28_827 28_828 28_829 28_832 28_835 28_838 28_841 28_845 28_847 29_48 29_77 29_78 29_79 29_268 29_281 29_282 29_283 29_563 29_567 29_589 29_621 29_622 29_625 29_626 29_627 29_785 29_786 29_788 29_790 29_791 29_793 29_797 29_798 29_800 29_809 29_811 29_812 29_813 29_814 29_815 29_816 29_817 29_819 29_823 29_824 29_825 29_826 29_827 29_829 29_830 29_831 29_832 29_835 29_836 29_838 29_839 29_840 29_841 29_842 29_845 -CMT_TOP_L_UPPER_T.PLLE2.INV_CLKINSEL 28_754 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[0] 28_232 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[1] 29_232 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[2] 28_233 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[3] 29_233 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[4] 28_234 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[5] 29_234 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[6] 28_235 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[7] 29_235 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[8] 28_236 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[9] 29_236 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[10] 28_240 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[11] 29_240 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[12] 28_241 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[13] 29_241 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[14] 28_242 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[15] 29_242 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[16] 28_243 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[17] 29_243 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[18] 28_244 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[19] 29_244 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[20] 28_224 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[21] 29_224 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[22] 28_225 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[23] 29_225 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[24] 28_226 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[25] 29_226 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[26] 28_227 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[27] 29_227 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[28] 28_228 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[29] 29_228 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[30] 28_237 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[31] 29_237 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[32] 28_238 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[33] 29_238 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[34] 28_239 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[35] 28_245 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[36] 29_245 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[37] 28_246 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[38] 29_246 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[39] 28_247 -CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[0] 28_352 -CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[1] 29_352 -CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[2] 28_353 -CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[3] 29_353 -CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[4] 28_354 -CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[5] 29_354 -CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[6] 28_355 -CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[7] 29_355 -CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[8] 28_356 -CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[9] 29_356 -CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[10] 28_357 -CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[11] 29_357 -CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[12] 28_358 -CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[13] 29_358 -CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[14] 28_359 -CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[15] 29_359 -CMT_TOP_L_UPPER_T.PLLE2.STARTUP_WAIT 28_769 -CMT_TOP_L_UPPER_T.PLLE2.TABLE[0] 28_666 -CMT_TOP_L_UPPER_T.PLLE2.TABLE[1] 29_667 -CMT_TOP_L_UPPER_T.PLLE2.TABLE[2] 28_668 -CMT_TOP_L_UPPER_T.PLLE2.TABLE[3] 29_669 -CMT_TOP_L_UPPER_T.PLLE2.TABLE[4] 28_670 -CMT_TOP_L_UPPER_T.PLLE2.TABLE[5] 29_671 -CMT_TOP_L_UPPER_T.PLLE2.TABLE[6] 28_660 -CMT_TOP_L_UPPER_T.PLLE2.TABLE[7] 29_661 -CMT_TOP_L_UPPER_T.PLLE2.TABLE[8] 28_662 -CMT_TOP_L_UPPER_T.PLLE2.TABLE[9] 29_663 -CMT_TOP_L_UPPER_T.PLLE2.ZINV_PWRDWN 29_752 -CMT_TOP_L_UPPER_T.PLLE2.ZINV_RST 28_752 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[0] 28_99 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[1] 29_99 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[2] 28_100 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[3] 29_100 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[4] 28_101 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[5] 29_101 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[0] 28_96 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[1] 29_96 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[2] 28_97 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[3] 29_97 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[4] 28_98 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[5] 29_98 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_OUTPUT_ENABLE[0] 28_102 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[0] 29_102 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[1] 28_103 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[2] 29_103 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[0] 28_104 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[1] 29_104 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[2] 28_105 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[3] 29_105 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[4] 28_106 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[5] 29_106 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_EDGE[0] 29_107 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[0] 28_110 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[1] 29_110 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[2] 28_111 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC_EN[0] 29_109 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC_WF_R[0] 28_109 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_MX[0] 28_108 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_MX[1] 29_108 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_NO_COUNT[0] 28_107 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_RESERVED[0] 29_111 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[0] 28_115 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[1] 29_115 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[2] 28_116 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[3] 29_116 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[4] 28_117 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[5] 29_117 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[0] 28_112 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[1] 29_112 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[2] 28_113 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[3] 29_113 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[4] 28_114 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[5] 29_114 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_OUTPUT_ENABLE[0] 28_118 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[0] 29_118 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[1] 28_119 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[2] 29_119 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[0] 28_120 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[1] 29_120 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[2] 28_121 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[3] 29_121 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[4] 28_122 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[5] 29_122 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_EDGE[0] 29_123 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[0] 28_126 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[1] 29_126 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[2] 28_127 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC_EN[0] 29_125 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC_WF_R[0] 28_125 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_MX[0] 28_124 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_MX[1] 29_124 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_NO_COUNT[0] 28_123 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_RESERVED[0] 29_127 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[0] 28_131 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[1] 29_131 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[2] 28_132 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[3] 29_132 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[4] 28_133 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[5] 29_133 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[0] 28_128 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[1] 29_128 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[2] 28_129 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[3] 29_129 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[4] 28_130 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[5] 29_130 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_OUTPUT_ENABLE[0] 28_134 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[0] 29_134 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[1] 28_135 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[2] 29_135 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[0] 28_136 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[1] 29_136 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[2] 28_137 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[3] 29_137 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[4] 28_138 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[5] 29_138 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_EDGE[0] 29_139 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[0] 28_142 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[1] 29_142 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[2] 28_143 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC_EN[0] 29_141 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC_WF_R[0] 28_141 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_MX[0] 28_140 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_MX[1] 29_140 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_NO_COUNT[0] 28_139 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_RESERVED[0] 29_143 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[0] 28_147 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[1] 29_147 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[2] 28_148 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[3] 29_148 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[4] 28_149 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[5] 29_149 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[0] 28_144 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[1] 29_144 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[2] 28_145 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[3] 29_145 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[4] 28_146 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[5] 29_146 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_OUTPUT_ENABLE[0] 28_150 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[0] 29_150 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[1] 28_151 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[2] 29_151 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[0] 28_152 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[1] 29_152 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[2] 28_153 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[3] 29_153 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[4] 28_154 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[5] 29_154 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_EDGE[0] 29_155 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[0] 28_158 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[1] 29_158 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[2] 28_159 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC_EN[0] 29_157 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC_WF_R[0] 28_157 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_MX[0] 28_156 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_MX[1] 29_156 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_NO_COUNT[0] 28_155 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_RESERVED[0] 29_159 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[0] 28_163 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[1] 29_163 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[2] 28_164 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[3] 29_164 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[4] 28_165 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[5] 29_165 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[0] 28_160 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[1] 29_160 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[2] 28_161 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[3] 29_161 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[4] 28_162 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[5] 29_162 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_OUTPUT_ENABLE[0] 28_166 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[0] 29_166 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[1] 28_167 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[2] 29_167 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[0] 28_168 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[1] 29_168 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[2] 28_169 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[3] 29_169 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[4] 28_170 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[5] 29_170 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_EDGE[0] 29_171 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[0] 28_174 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[1] 29_174 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[2] 28_175 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC_EN[0] 29_173 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC_WF_R[0] 28_173 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_MX[0] 28_172 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_MX[1] 29_172 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_NO_COUNT[0] 28_171 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_RESERVED[0] 29_175 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[0] 28_83 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[1] 29_83 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[2] 28_84 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[3] 29_84 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[4] 28_85 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[5] 29_85 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[0] 28_80 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[1] 29_80 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[2] 28_81 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[3] 29_81 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[4] 28_82 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[5] 29_82 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_OUTPUT_ENABLE[0] 28_86 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[0] 29_86 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[1] 28_87 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[2] 29_87 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[0] 28_88 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[1] 29_88 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[2] 28_89 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[3] 29_89 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[4] 28_90 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[5] 29_90 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_EDGE[0] 29_91 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[0] 28_94 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[1] 29_94 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[2] 28_95 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC_EN[0] 29_93 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC_WF_R[0] 28_93 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_MX[0] 28_92 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_MX[1] 29_92 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_NO_COUNT[0] 28_91 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_RESERVED[0] 29_95 -CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[0] 28_656 -CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[1] 29_656 -CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[2] 28_657 -CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[3] 29_657 -CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[4] 28_658 -CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[5] 29_658 -CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[6] 28_659 -CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[7] 29_659 -CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[8] 29_660 -CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[9] 28_661 -CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[10] 29_662 -CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[11] 28_663 -CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[0] 28_664 -CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[1] 29_664 -CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[2] 28_665 -CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[3] 29_665 -CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[4] 29_666 -CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[5] 28_667 -CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[6] 29_668 -CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[7] 28_669 -CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[8] 29_670 -CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[9] 28_671 -CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[0] 28_229 -CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[1] 29_229 -CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[2] 28_230 -CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[3] 29_230 -CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[4] 28_231 -CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[5] 29_231 -CMT_TOP_L_UPPER_T.PLLE2.LOCKREG2_RESERVED[0] 29_239 -CMT_TOP_L_UPPER_T.PLLE2.LOCKREG3_RESERVED[0] 29_247 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[0] 28_195 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[1] 29_195 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[2] 28_196 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[3] 29_196 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[4] 28_197 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[5] 29_197 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[0] 28_192 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[1] 29_192 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[2] 28_193 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[3] 29_193 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[4] 28_194 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[5] 29_194 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE[0] 28_198 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_PHASE_MUX[0] 29_198 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_PHASE_MUX[1] 28_199 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_PHASE_MUX[2] 29_199 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[0] 28_200 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[1] 29_200 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[2] 28_201 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[3] 29_201 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[4] 28_202 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[5] 29_202 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_EDGE[0] 29_203 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_FRAC[0] 28_206 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_FRAC[1] 29_206 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_FRAC[2] 28_207 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_FRAC_EN[0] 29_205 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_FRAC_WF_R[0] 28_205 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_MX[0] 28_204 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_MX[1] 29_204 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_NO_COUNT[0] 28_203 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_RESERVED[0] 29_207 +CMT_TOP_L_UPPER_T.PLLE2_ADV.COMPENSATION.Z_ZHOLD_OR_CLKIN_BUF 29_35 29_76 +CMT_TOP_L_UPPER_T.PLLE2_ADV.COMPENSATION.ZHOLD_NO_CLKIN_BUF 28_73 29_36 +CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_EDGE[0] 29_214 +CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_HIGH_TIME[0] 28_211 +CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_HIGH_TIME[1] 29_211 +CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_HIGH_TIME[2] 28_212 +CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_HIGH_TIME[3] 29_212 +CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_HIGH_TIME[4] 28_213 +CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_HIGH_TIME[5] 29_213 +CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_LOW_TIME[0] 28_208 +CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_LOW_TIME[1] 29_208 +CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_LOW_TIME[2] 28_209 +CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_LOW_TIME[3] 29_209 +CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_LOW_TIME[4] 28_210 +CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_LOW_TIME[5] 29_210 +CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_NO_COUNT[0] 28_214 +CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_RESERVED[0] 28_215 +CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_RESERVED[1] 29_215 +CMT_TOP_L_UPPER_T.PLLE2_ADV.IN_USE 28_37 28_48 28_74 28_78 28_216 28_219 28_222 28_266 28_280 28_283 28_284 28_592 28_622 28_623 28_624 28_627 28_628 28_768 28_785 28_786 28_787 28_788 28_790 28_791 28_792 28_793 28_795 28_796 28_797 28_798 28_799 28_803 28_806 28_807 28_811 28_812 28_815 28_816 28_817 28_818 28_819 28_821 28_822 28_823 28_824 28_826 28_827 28_828 28_829 28_832 28_835 28_838 28_841 28_845 28_847 29_48 29_77 29_78 29_79 29_268 29_281 29_282 29_283 29_563 29_567 29_589 29_621 29_622 29_625 29_626 29_627 29_785 29_786 29_788 29_790 29_791 29_793 29_797 29_798 29_800 29_809 29_811 29_812 29_813 29_814 29_815 29_816 29_817 29_819 29_823 29_824 29_825 29_826 29_827 29_829 29_830 29_831 29_832 29_835 29_836 29_838 29_839 29_840 29_841 29_842 29_845 +CMT_TOP_L_UPPER_T.PLLE2_ADV.INV_CLKINSEL 28_754 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[0] 28_232 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[1] 29_232 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[2] 28_233 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[3] 29_233 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[4] 28_234 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[5] 29_234 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[6] 28_235 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[7] 29_235 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[8] 28_236 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[9] 29_236 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[10] 28_240 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[11] 29_240 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[12] 28_241 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[13] 29_241 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[14] 28_242 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[15] 29_242 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[16] 28_243 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[17] 29_243 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[18] 28_244 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[19] 29_244 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[20] 28_224 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[21] 29_224 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[22] 28_225 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[23] 29_225 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[24] 28_226 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[25] 29_226 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[26] 28_227 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[27] 29_227 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[28] 28_228 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[29] 29_228 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[30] 28_237 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[31] 29_237 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[32] 28_238 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[33] 29_238 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[34] 28_239 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[35] 28_245 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[36] 29_245 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[37] 28_246 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[38] 29_246 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[39] 28_247 +CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[0] 28_352 +CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[1] 29_352 +CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[2] 28_353 +CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[3] 29_353 +CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[4] 28_354 +CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[5] 29_354 +CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[6] 28_355 +CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[7] 29_355 +CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[8] 28_356 +CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[9] 29_356 +CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[10] 28_357 +CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[11] 29_357 +CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[12] 28_358 +CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[13] 29_358 +CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[14] 28_359 +CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[15] 29_359 +CMT_TOP_L_UPPER_T.PLLE2_ADV.STARTUP_WAIT 28_769 +CMT_TOP_L_UPPER_T.PLLE2_ADV.TABLE[0] 28_666 +CMT_TOP_L_UPPER_T.PLLE2_ADV.TABLE[1] 29_667 +CMT_TOP_L_UPPER_T.PLLE2_ADV.TABLE[2] 28_668 +CMT_TOP_L_UPPER_T.PLLE2_ADV.TABLE[3] 29_669 +CMT_TOP_L_UPPER_T.PLLE2_ADV.TABLE[4] 28_670 +CMT_TOP_L_UPPER_T.PLLE2_ADV.TABLE[5] 29_671 +CMT_TOP_L_UPPER_T.PLLE2_ADV.TABLE[6] 28_660 +CMT_TOP_L_UPPER_T.PLLE2_ADV.TABLE[7] 29_661 +CMT_TOP_L_UPPER_T.PLLE2_ADV.TABLE[8] 28_662 +CMT_TOP_L_UPPER_T.PLLE2_ADV.TABLE[9] 29_663 +CMT_TOP_L_UPPER_T.PLLE2_ADV.ZINV_PWRDWN 29_752 +CMT_TOP_L_UPPER_T.PLLE2_ADV.ZINV_RST 28_752 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[0] 28_99 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[1] 29_99 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[2] 28_100 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[3] 29_100 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[4] 28_101 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[5] 29_101 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[0] 28_96 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[1] 29_96 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[2] 28_97 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[3] 29_97 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[4] 28_98 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[5] 29_98 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_OUTPUT_ENABLE[0] 28_102 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_PHASE_MUX[0] 29_102 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_PHASE_MUX[1] 28_103 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_PHASE_MUX[2] 29_103 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[0] 28_104 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[1] 29_104 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[2] 28_105 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[3] 29_105 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[4] 28_106 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[5] 29_106 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_EDGE[0] 29_107 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_FRAC[0] 28_110 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_FRAC[1] 29_110 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_FRAC[2] 28_111 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_FRAC_EN[0] 29_109 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_FRAC_WF_R[0] 28_109 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_MX[0] 28_108 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_MX[1] 29_108 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_NO_COUNT[0] 28_107 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_RESERVED[0] 29_111 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[0] 28_115 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[1] 29_115 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[2] 28_116 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[3] 29_116 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[4] 28_117 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[5] 29_117 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[0] 28_112 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[1] 29_112 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[2] 28_113 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[3] 29_113 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[4] 28_114 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[5] 29_114 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_OUTPUT_ENABLE[0] 28_118 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_PHASE_MUX[0] 29_118 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_PHASE_MUX[1] 28_119 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_PHASE_MUX[2] 29_119 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[0] 28_120 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[1] 29_120 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[2] 28_121 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[3] 29_121 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[4] 28_122 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[5] 29_122 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_EDGE[0] 29_123 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_FRAC[0] 28_126 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_FRAC[1] 29_126 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_FRAC[2] 28_127 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_FRAC_EN[0] 29_125 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_FRAC_WF_R[0] 28_125 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_MX[0] 28_124 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_MX[1] 29_124 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_NO_COUNT[0] 28_123 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_RESERVED[0] 29_127 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[0] 28_131 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[1] 29_131 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[2] 28_132 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[3] 29_132 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[4] 28_133 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[5] 29_133 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[0] 28_128 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[1] 29_128 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[2] 28_129 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[3] 29_129 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[4] 28_130 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[5] 29_130 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_OUTPUT_ENABLE[0] 28_134 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_PHASE_MUX[0] 29_134 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_PHASE_MUX[1] 28_135 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_PHASE_MUX[2] 29_135 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[0] 28_136 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[1] 29_136 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[2] 28_137 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[3] 29_137 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[4] 28_138 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[5] 29_138 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_EDGE[0] 29_139 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_FRAC[0] 28_142 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_FRAC[1] 29_142 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_FRAC[2] 28_143 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_FRAC_EN[0] 29_141 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_FRAC_WF_R[0] 28_141 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_MX[0] 28_140 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_MX[1] 29_140 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_NO_COUNT[0] 28_139 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_RESERVED[0] 29_143 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[0] 28_147 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[1] 29_147 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[2] 28_148 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[3] 29_148 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[4] 28_149 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[5] 29_149 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[0] 28_144 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[1] 29_144 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[2] 28_145 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[3] 29_145 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[4] 28_146 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[5] 29_146 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_OUTPUT_ENABLE[0] 28_150 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_PHASE_MUX[0] 29_150 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_PHASE_MUX[1] 28_151 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_PHASE_MUX[2] 29_151 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[0] 28_152 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[1] 29_152 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[2] 28_153 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[3] 29_153 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[4] 28_154 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[5] 29_154 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_EDGE[0] 29_155 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_FRAC[0] 28_158 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_FRAC[1] 29_158 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_FRAC[2] 28_159 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_FRAC_EN[0] 29_157 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_FRAC_WF_R[0] 28_157 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_MX[0] 28_156 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_MX[1] 29_156 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_NO_COUNT[0] 28_155 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_RESERVED[0] 29_159 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[0] 28_163 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[1] 29_163 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[2] 28_164 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[3] 29_164 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[4] 28_165 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[5] 29_165 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[0] 28_160 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[1] 29_160 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[2] 28_161 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[3] 29_161 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[4] 28_162 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[5] 29_162 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_OUTPUT_ENABLE[0] 28_166 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_PHASE_MUX[0] 29_166 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_PHASE_MUX[1] 28_167 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_PHASE_MUX[2] 29_167 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[0] 28_168 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[1] 29_168 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[2] 28_169 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[3] 29_169 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[4] 28_170 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[5] 29_170 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_EDGE[0] 29_171 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_FRAC[0] 28_174 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_FRAC[1] 29_174 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_FRAC[2] 28_175 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_FRAC_EN[0] 29_173 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_FRAC_WF_R[0] 28_173 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_MX[0] 28_172 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_MX[1] 29_172 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_NO_COUNT[0] 28_171 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_RESERVED[0] 29_175 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[0] 28_83 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[1] 29_83 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[2] 28_84 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[3] 29_84 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[4] 28_85 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[5] 29_85 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[0] 28_80 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[1] 29_80 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[2] 28_81 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[3] 29_81 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[4] 28_82 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[5] 29_82 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_OUTPUT_ENABLE[0] 28_86 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_PHASE_MUX[0] 29_86 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_PHASE_MUX[1] 28_87 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_PHASE_MUX[2] 29_87 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_DELAY_TIME[0] 28_88 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_DELAY_TIME[1] 29_88 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_DELAY_TIME[2] 28_89 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_DELAY_TIME[3] 29_89 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_DELAY_TIME[4] 28_90 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_DELAY_TIME[5] 29_90 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_EDGE[0] 29_91 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_FRAC[0] 28_94 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_FRAC[1] 29_94 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_FRAC[2] 28_95 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_FRAC_EN[0] 29_93 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_FRAC_WF_R[0] 28_93 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_MX[0] 28_92 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_MX[1] 29_92 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_NO_COUNT[0] 28_91 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_RESERVED[0] 29_95 +CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[0] 28_656 +CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[1] 29_656 +CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[2] 28_657 +CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[3] 29_657 +CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[4] 28_658 +CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[5] 29_658 +CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[6] 28_659 +CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[7] 29_659 +CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[8] 29_660 +CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[9] 28_661 +CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[10] 29_662 +CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[11] 28_663 +CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[0] 28_664 +CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[1] 29_664 +CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[2] 28_665 +CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[3] 29_665 +CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[4] 29_666 +CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[5] 28_667 +CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[6] 29_668 +CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[7] 28_669 +CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[8] 29_670 +CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[9] 28_671 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LOCKREG1_RESERVED[0] 28_229 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LOCKREG1_RESERVED[1] 29_229 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LOCKREG1_RESERVED[2] 28_230 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LOCKREG1_RESERVED[3] 29_230 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LOCKREG1_RESERVED[4] 28_231 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LOCKREG1_RESERVED[5] 29_231 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LOCKREG2_RESERVED[0] 29_239 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LOCKREG3_RESERVED[0] 29_247 diff --git a/zynq7/segbits_cmt_top_l_upper_t.origin_info.db b/zynq7/segbits_cmt_top_l_upper_t.origin_info.db index bfa0faf..12b35bd 100644 --- a/zynq7/segbits_cmt_top_l_upper_t.origin_info.db +++ b/zynq7/segbits_cmt_top_l_upper_t.origin_info.db @@ -21,346 +21,346 @@ CMT_TOP_L_UPPER_T.PLL_CLK_FREQ_BB0_NS_ACTIVE origin:034-cmt-pll-pips 29_00 29_09 CMT_TOP_L_UPPER_T.PLL_CLK_FREQ_BB1_NS_ACTIVE origin:034-cmt-pll-pips 28_01 29_10 29_18 CMT_TOP_L_UPPER_T.PLL_CLK_FREQ_BB2_NS_ACTIVE origin:034-cmt-pll-pips 29_01 29_11 29_19 CMT_TOP_L_UPPER_T.PLL_CLK_FREQ_BB3_NS_ACTIVE origin:034-cmt-pll-pips 28_02 29_12 29_20 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_195 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_195 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_196 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_196 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_197 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_197 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_192 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_192 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_193 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_193 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_194 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_194 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_198 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_198 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_199 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_199 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_200 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_200 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_201 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_201 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_202 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_202 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_203 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_206 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_206 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_207 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_205 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_205 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_MX[0] origin:032-cmt-pll 28_204 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_MX[1] origin:032-cmt-pll 29_204 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_203 -CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_207 -CMT_TOP_L_UPPER_T.PLLE2.COMPENSATION.Z_ZHOLD_OR_CLKIN_BUF origin:032-cmt-pll 29_35 29_76 -CMT_TOP_L_UPPER_T.PLLE2.COMPENSATION.ZHOLD_NO_CLKIN_BUF origin:032-cmt-pll 28_73 29_36 -CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_EDGE[0] origin:032-cmt-pll 29_214 -CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[0] origin:032-cmt-pll 28_211 -CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[1] origin:032-cmt-pll 29_211 -CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[2] origin:032-cmt-pll 28_212 -CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[3] origin:032-cmt-pll 29_212 -CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[4] origin:032-cmt-pll 28_213 -CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[5] origin:032-cmt-pll 29_213 -CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[0] origin:032-cmt-pll 28_208 -CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[1] origin:032-cmt-pll 29_208 -CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[2] origin:032-cmt-pll 28_209 -CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[3] origin:032-cmt-pll 29_209 -CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[4] origin:032-cmt-pll 28_210 -CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[5] origin:032-cmt-pll 29_210 -CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_NO_COUNT[0] origin:032-cmt-pll 28_214 -CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_RESERVED[0] origin:032-cmt-pll 28_215 -CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_RESERVED[1] origin:032-cmt-pll 29_215 -CMT_TOP_L_UPPER_T.PLLE2.IN_USE origin:032-cmt-pll 28_216 28_219 28_222 28_266 28_280 28_283 28_284 28_37 28_48 28_592 28_622 28_623 28_624 28_627 28_628 28_74 28_768 28_78 28_785 28_786 28_787 28_788 28_790 28_791 28_792 28_793 28_795 28_796 28_797 28_798 28_799 28_803 28_806 28_807 28_811 28_812 28_815 28_816 28_817 28_818 28_819 28_821 28_822 28_823 28_824 28_826 28_827 28_828 28_829 28_832 28_835 28_838 28_841 28_845 28_847 29_268 29_281 29_282 29_283 29_48 29_563 29_567 29_589 29_621 29_622 29_625 29_626 29_627 29_77 29_78 29_785 29_786 29_788 29_79 29_790 29_791 29_793 29_797 29_798 29_800 29_809 29_811 29_812 29_813 29_814 29_815 29_816 29_817 29_819 29_823 29_824 29_825 29_826 29_827 29_829 29_830 29_831 29_832 29_835 29_836 29_838 29_839 29_840 29_841 29_842 29_845 -CMT_TOP_L_UPPER_T.PLLE2.INV_CLKINSEL origin:032-cmt-pll 28_754 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[0] origin:032-cmt-pll 28_232 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[1] origin:032-cmt-pll 29_232 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[2] origin:032-cmt-pll 28_233 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[3] origin:032-cmt-pll 29_233 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[4] origin:032-cmt-pll 28_234 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[5] origin:032-cmt-pll 29_234 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[6] origin:032-cmt-pll 28_235 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[7] origin:032-cmt-pll 29_235 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[8] origin:032-cmt-pll 28_236 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[9] origin:032-cmt-pll 29_236 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[10] origin:032-cmt-pll 28_240 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[11] origin:032-cmt-pll 29_240 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[12] origin:032-cmt-pll 28_241 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[13] origin:032-cmt-pll 29_241 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[14] origin:032-cmt-pll 28_242 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[15] origin:032-cmt-pll 29_242 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[16] origin:032-cmt-pll 28_243 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[17] origin:032-cmt-pll 29_243 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[18] origin:032-cmt-pll 28_244 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[19] origin:032-cmt-pll 29_244 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[20] origin:032-cmt-pll 28_224 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[21] origin:032-cmt-pll 29_224 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[22] origin:032-cmt-pll 28_225 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[23] origin:032-cmt-pll 29_225 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[24] origin:032-cmt-pll 28_226 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[25] origin:032-cmt-pll 29_226 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[26] origin:032-cmt-pll 28_227 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[27] origin:032-cmt-pll 29_227 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[28] origin:032-cmt-pll 28_228 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[29] origin:032-cmt-pll 29_228 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[30] origin:032-cmt-pll 28_237 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[31] origin:032-cmt-pll 29_237 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[32] origin:032-cmt-pll 28_238 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[33] origin:032-cmt-pll 29_238 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[34] origin:032-cmt-pll 28_239 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[35] origin:032-cmt-pll 28_245 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[36] origin:032-cmt-pll 29_245 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[37] origin:032-cmt-pll 28_246 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[38] origin:032-cmt-pll 29_246 -CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[39] origin:032-cmt-pll 28_247 -CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[0] origin:032-cmt-pll 28_352 -CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[1] origin:032-cmt-pll 29_352 -CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[2] origin:032-cmt-pll 28_353 -CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[3] origin:032-cmt-pll 29_353 -CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[4] origin:032-cmt-pll 28_354 -CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[5] origin:032-cmt-pll 29_354 -CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[6] origin:032-cmt-pll 28_355 -CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[7] origin:032-cmt-pll 29_355 -CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[8] origin:032-cmt-pll 28_356 -CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[9] origin:032-cmt-pll 29_356 -CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[10] origin:032-cmt-pll 28_357 -CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[11] origin:032-cmt-pll 29_357 -CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[12] origin:032-cmt-pll 28_358 -CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[13] origin:032-cmt-pll 29_358 -CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[14] origin:032-cmt-pll 28_359 -CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[15] origin:032-cmt-pll 29_359 -CMT_TOP_L_UPPER_T.PLLE2.STARTUP_WAIT origin:032-cmt-pll 28_769 -CMT_TOP_L_UPPER_T.PLLE2.TABLE[0] origin:032-cmt-pll 28_666 -CMT_TOP_L_UPPER_T.PLLE2.TABLE[1] origin:032-cmt-pll 29_667 -CMT_TOP_L_UPPER_T.PLLE2.TABLE[2] origin:032-cmt-pll 28_668 -CMT_TOP_L_UPPER_T.PLLE2.TABLE[3] origin:032-cmt-pll 29_669 -CMT_TOP_L_UPPER_T.PLLE2.TABLE[4] origin:032-cmt-pll 28_670 -CMT_TOP_L_UPPER_T.PLLE2.TABLE[5] origin:032-cmt-pll 29_671 -CMT_TOP_L_UPPER_T.PLLE2.TABLE[6] origin:032-cmt-pll 28_660 -CMT_TOP_L_UPPER_T.PLLE2.TABLE[7] origin:032-cmt-pll 29_661 -CMT_TOP_L_UPPER_T.PLLE2.TABLE[8] origin:032-cmt-pll 28_662 -CMT_TOP_L_UPPER_T.PLLE2.TABLE[9] origin:032-cmt-pll 29_663 -CMT_TOP_L_UPPER_T.PLLE2.ZINV_PWRDWN origin:032-cmt-pll 29_752 -CMT_TOP_L_UPPER_T.PLLE2.ZINV_RST origin:032-cmt-pll 28_752 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_99 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_99 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_100 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_100 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_101 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_101 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_96 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_96 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_97 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_97 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_98 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_98 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_102 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_102 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_103 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_103 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_104 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_104 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_105 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_105 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_106 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_106 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_107 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_110 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_110 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_111 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_109 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_109 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_MX[0] origin:032-cmt-pll 28_108 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_MX[1] origin:032-cmt-pll 29_108 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_107 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_111 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_115 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_115 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_116 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_116 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_117 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_117 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_112 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_112 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_113 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_113 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_114 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_114 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_118 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_118 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_119 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_119 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_120 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_120 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_121 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_121 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_122 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_122 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_123 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_126 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_126 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_127 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_125 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_125 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_MX[0] origin:032-cmt-pll 28_124 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_MX[1] origin:032-cmt-pll 29_124 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_123 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_127 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_131 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_131 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_132 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_132 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_133 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_133 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_128 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_128 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_129 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_129 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_130 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_130 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_134 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_134 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_135 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_135 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_136 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_136 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_137 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_137 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_138 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_138 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_139 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_142 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_142 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_143 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_141 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_141 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_MX[0] origin:032-cmt-pll 28_140 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_MX[1] origin:032-cmt-pll 29_140 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_139 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_143 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_147 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_147 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_148 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_148 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_149 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_149 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_144 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_144 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_145 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_145 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_146 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_146 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_150 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_150 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_151 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_151 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_152 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_152 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_153 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_153 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_154 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_154 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_155 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_158 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_158 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_159 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_157 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_157 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_MX[0] origin:032-cmt-pll 28_156 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_MX[1] origin:032-cmt-pll 29_156 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_155 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_159 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_163 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_163 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_164 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_164 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_165 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_165 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_160 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_160 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_161 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_161 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_162 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_162 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_166 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_166 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_167 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_167 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_168 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_168 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_169 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_169 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_170 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_170 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_171 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_174 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_174 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_175 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_173 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_173 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_MX[0] origin:032-cmt-pll 28_172 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_MX[1] origin:032-cmt-pll 29_172 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_171 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_175 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_83 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_83 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_84 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_84 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_85 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_85 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_80 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_80 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_81 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_81 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_82 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_82 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_86 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_86 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_87 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_87 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_88 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_88 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_89 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_89 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_90 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_90 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_91 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_94 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_94 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_95 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_93 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_93 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_MX[0] origin:032-cmt-pll 28_92 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_MX[1] origin:032-cmt-pll 29_92 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_91 -CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_95 -CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[0] origin:032-cmt-pll 28_656 -CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[1] origin:032-cmt-pll 29_656 -CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[2] origin:032-cmt-pll 28_657 -CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[3] origin:032-cmt-pll 29_657 -CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[4] origin:032-cmt-pll 28_658 -CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[5] origin:032-cmt-pll 29_658 -CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[6] origin:032-cmt-pll 28_659 -CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[7] origin:032-cmt-pll 29_659 -CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[8] origin:032-cmt-pll 29_660 -CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[9] origin:032-cmt-pll 28_661 -CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[10] origin:032-cmt-pll 29_662 -CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[11] origin:032-cmt-pll 28_663 -CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[0] origin:032-cmt-pll 28_664 -CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[1] origin:032-cmt-pll 29_664 -CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[2] origin:032-cmt-pll 28_665 -CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[3] origin:032-cmt-pll 29_665 -CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[4] origin:032-cmt-pll 29_666 -CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[5] origin:032-cmt-pll 28_667 -CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[6] origin:032-cmt-pll 29_668 -CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[7] origin:032-cmt-pll 28_669 -CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[8] origin:032-cmt-pll 29_670 -CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[9] origin:032-cmt-pll 28_671 -CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[0] origin:032-cmt-pll 28_229 -CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[1] origin:032-cmt-pll 29_229 -CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[2] origin:032-cmt-pll 28_230 -CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[3] origin:032-cmt-pll 29_230 -CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[4] origin:032-cmt-pll 28_231 -CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[5] origin:032-cmt-pll 29_231 -CMT_TOP_L_UPPER_T.PLLE2.LOCKREG2_RESERVED[0] origin:032-cmt-pll 29_239 -CMT_TOP_L_UPPER_T.PLLE2.LOCKREG3_RESERVED[0] origin:032-cmt-pll 29_247 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_195 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_195 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_196 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_196 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_197 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_197 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_192 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_192 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_193 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_193 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_194 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_194 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_198 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_198 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_199 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_199 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_200 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_200 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_201 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_201 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_202 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_202 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_203 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_206 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_206 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_207 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_205 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_205 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_MX[0] origin:032-cmt-pll 28_204 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_MX[1] origin:032-cmt-pll 29_204 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_203 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_207 +CMT_TOP_L_UPPER_T.PLLE2_ADV.COMPENSATION.Z_ZHOLD_OR_CLKIN_BUF origin:032-cmt-pll 29_35 29_76 +CMT_TOP_L_UPPER_T.PLLE2_ADV.COMPENSATION.ZHOLD_NO_CLKIN_BUF origin:032-cmt-pll 28_73 29_36 +CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_EDGE[0] origin:032-cmt-pll 29_214 +CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_HIGH_TIME[0] origin:032-cmt-pll 28_211 +CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_HIGH_TIME[1] origin:032-cmt-pll 29_211 +CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_HIGH_TIME[2] origin:032-cmt-pll 28_212 +CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_HIGH_TIME[3] origin:032-cmt-pll 29_212 +CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_HIGH_TIME[4] origin:032-cmt-pll 28_213 +CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_HIGH_TIME[5] origin:032-cmt-pll 29_213 +CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_LOW_TIME[0] origin:032-cmt-pll 28_208 +CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_LOW_TIME[1] origin:032-cmt-pll 29_208 +CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_LOW_TIME[2] origin:032-cmt-pll 28_209 +CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_LOW_TIME[3] origin:032-cmt-pll 29_209 +CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_LOW_TIME[4] origin:032-cmt-pll 28_210 +CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_LOW_TIME[5] origin:032-cmt-pll 29_210 +CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_NO_COUNT[0] origin:032-cmt-pll 28_214 +CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_RESERVED[0] origin:032-cmt-pll 28_215 +CMT_TOP_L_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_RESERVED[1] origin:032-cmt-pll 29_215 +CMT_TOP_L_UPPER_T.PLLE2_ADV.IN_USE origin:032-cmt-pll 28_216 28_219 28_222 28_266 28_280 28_283 28_284 28_37 28_48 28_592 28_622 28_623 28_624 28_627 28_628 28_74 28_768 28_78 28_785 28_786 28_787 28_788 28_790 28_791 28_792 28_793 28_795 28_796 28_797 28_798 28_799 28_803 28_806 28_807 28_811 28_812 28_815 28_816 28_817 28_818 28_819 28_821 28_822 28_823 28_824 28_826 28_827 28_828 28_829 28_832 28_835 28_838 28_841 28_845 28_847 29_268 29_281 29_282 29_283 29_48 29_563 29_567 29_589 29_621 29_622 29_625 29_626 29_627 29_77 29_78 29_785 29_786 29_788 29_79 29_790 29_791 29_793 29_797 29_798 29_800 29_809 29_811 29_812 29_813 29_814 29_815 29_816 29_817 29_819 29_823 29_824 29_825 29_826 29_827 29_829 29_830 29_831 29_832 29_835 29_836 29_838 29_839 29_840 29_841 29_842 29_845 +CMT_TOP_L_UPPER_T.PLLE2_ADV.INV_CLKINSEL origin:032-cmt-pll 28_754 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[0] origin:032-cmt-pll 28_232 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[1] origin:032-cmt-pll 29_232 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[2] origin:032-cmt-pll 28_233 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[3] origin:032-cmt-pll 29_233 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[4] origin:032-cmt-pll 28_234 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[5] origin:032-cmt-pll 29_234 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[6] origin:032-cmt-pll 28_235 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[7] origin:032-cmt-pll 29_235 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[8] origin:032-cmt-pll 28_236 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[9] origin:032-cmt-pll 29_236 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[10] origin:032-cmt-pll 28_240 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[11] origin:032-cmt-pll 29_240 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[12] origin:032-cmt-pll 28_241 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[13] origin:032-cmt-pll 29_241 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[14] origin:032-cmt-pll 28_242 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[15] origin:032-cmt-pll 29_242 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[16] origin:032-cmt-pll 28_243 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[17] origin:032-cmt-pll 29_243 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[18] origin:032-cmt-pll 28_244 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[19] origin:032-cmt-pll 29_244 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[20] origin:032-cmt-pll 28_224 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[21] origin:032-cmt-pll 29_224 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[22] origin:032-cmt-pll 28_225 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[23] origin:032-cmt-pll 29_225 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[24] origin:032-cmt-pll 28_226 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[25] origin:032-cmt-pll 29_226 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[26] origin:032-cmt-pll 28_227 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[27] origin:032-cmt-pll 29_227 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[28] origin:032-cmt-pll 28_228 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[29] origin:032-cmt-pll 29_228 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[30] origin:032-cmt-pll 28_237 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[31] origin:032-cmt-pll 29_237 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[32] origin:032-cmt-pll 28_238 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[33] origin:032-cmt-pll 29_238 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[34] origin:032-cmt-pll 28_239 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[35] origin:032-cmt-pll 28_245 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[36] origin:032-cmt-pll 29_245 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[37] origin:032-cmt-pll 28_246 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[38] origin:032-cmt-pll 29_246 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LKTABLE[39] origin:032-cmt-pll 28_247 +CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[0] origin:032-cmt-pll 28_352 +CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[1] origin:032-cmt-pll 29_352 +CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[2] origin:032-cmt-pll 28_353 +CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[3] origin:032-cmt-pll 29_353 +CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[4] origin:032-cmt-pll 28_354 +CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[5] origin:032-cmt-pll 29_354 +CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[6] origin:032-cmt-pll 28_355 +CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[7] origin:032-cmt-pll 29_355 +CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[8] origin:032-cmt-pll 28_356 +CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[9] origin:032-cmt-pll 29_356 +CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[10] origin:032-cmt-pll 28_357 +CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[11] origin:032-cmt-pll 29_357 +CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[12] origin:032-cmt-pll 28_358 +CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[13] origin:032-cmt-pll 29_358 +CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[14] origin:032-cmt-pll 28_359 +CMT_TOP_L_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[15] origin:032-cmt-pll 29_359 +CMT_TOP_L_UPPER_T.PLLE2_ADV.STARTUP_WAIT origin:032-cmt-pll 28_769 +CMT_TOP_L_UPPER_T.PLLE2_ADV.TABLE[0] origin:032-cmt-pll 28_666 +CMT_TOP_L_UPPER_T.PLLE2_ADV.TABLE[1] origin:032-cmt-pll 29_667 +CMT_TOP_L_UPPER_T.PLLE2_ADV.TABLE[2] origin:032-cmt-pll 28_668 +CMT_TOP_L_UPPER_T.PLLE2_ADV.TABLE[3] origin:032-cmt-pll 29_669 +CMT_TOP_L_UPPER_T.PLLE2_ADV.TABLE[4] origin:032-cmt-pll 28_670 +CMT_TOP_L_UPPER_T.PLLE2_ADV.TABLE[5] origin:032-cmt-pll 29_671 +CMT_TOP_L_UPPER_T.PLLE2_ADV.TABLE[6] origin:032-cmt-pll 28_660 +CMT_TOP_L_UPPER_T.PLLE2_ADV.TABLE[7] origin:032-cmt-pll 29_661 +CMT_TOP_L_UPPER_T.PLLE2_ADV.TABLE[8] origin:032-cmt-pll 28_662 +CMT_TOP_L_UPPER_T.PLLE2_ADV.TABLE[9] origin:032-cmt-pll 29_663 +CMT_TOP_L_UPPER_T.PLLE2_ADV.ZINV_PWRDWN origin:032-cmt-pll 29_752 +CMT_TOP_L_UPPER_T.PLLE2_ADV.ZINV_RST origin:032-cmt-pll 28_752 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_99 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_99 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_100 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_100 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_101 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_101 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_96 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_96 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_97 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_97 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_98 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_98 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_102 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_102 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_103 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_103 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_104 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_104 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_105 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_105 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_106 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_106 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_107 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_110 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_110 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_111 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_109 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_109 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_MX[0] origin:032-cmt-pll 28_108 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_MX[1] origin:032-cmt-pll 29_108 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_107 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_111 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_115 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_115 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_116 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_116 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_117 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_117 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_112 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_112 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_113 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_113 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_114 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_114 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_118 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_118 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_119 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_119 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_120 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_120 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_121 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_121 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_122 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_122 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_123 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_126 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_126 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_127 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_125 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_125 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_MX[0] origin:032-cmt-pll 28_124 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_MX[1] origin:032-cmt-pll 29_124 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_123 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_127 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_131 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_131 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_132 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_132 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_133 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_133 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_128 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_128 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_129 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_129 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_130 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_130 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_134 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_134 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_135 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_135 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_136 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_136 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_137 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_137 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_138 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_138 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_139 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_142 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_142 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_143 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_141 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_141 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_MX[0] origin:032-cmt-pll 28_140 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_MX[1] origin:032-cmt-pll 29_140 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_139 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_143 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_147 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_147 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_148 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_148 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_149 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_149 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_144 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_144 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_145 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_145 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_146 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_146 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_150 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_150 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_151 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_151 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_152 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_152 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_153 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_153 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_154 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_154 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_155 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_158 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_158 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_159 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_157 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_157 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_MX[0] origin:032-cmt-pll 28_156 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_MX[1] origin:032-cmt-pll 29_156 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_155 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_159 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_163 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_163 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_164 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_164 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_165 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_165 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_160 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_160 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_161 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_161 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_162 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_162 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_166 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_166 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_167 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_167 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_168 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_168 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_169 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_169 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_170 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_170 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_171 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_174 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_174 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_175 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_173 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_173 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_MX[0] origin:032-cmt-pll 28_172 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_MX[1] origin:032-cmt-pll 29_172 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_171 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_175 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_83 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_83 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_84 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_84 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_85 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_85 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_80 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_80 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_81 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_81 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_82 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_82 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_86 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_86 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_87 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_87 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_88 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_88 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_89 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_89 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_90 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_90 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_91 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_94 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_94 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_95 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_93 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_93 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_MX[0] origin:032-cmt-pll 28_92 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_MX[1] origin:032-cmt-pll 29_92 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_91 +CMT_TOP_L_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_95 +CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[0] origin:032-cmt-pll 28_656 +CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[1] origin:032-cmt-pll 29_656 +CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[2] origin:032-cmt-pll 28_657 +CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[3] origin:032-cmt-pll 29_657 +CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[4] origin:032-cmt-pll 28_658 +CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[5] origin:032-cmt-pll 29_658 +CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[6] origin:032-cmt-pll 28_659 +CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[7] origin:032-cmt-pll 29_659 +CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[8] origin:032-cmt-pll 29_660 +CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[9] origin:032-cmt-pll 28_661 +CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[10] origin:032-cmt-pll 29_662 +CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[11] origin:032-cmt-pll 28_663 +CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[0] origin:032-cmt-pll 28_664 +CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[1] origin:032-cmt-pll 29_664 +CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[2] origin:032-cmt-pll 28_665 +CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[3] origin:032-cmt-pll 29_665 +CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[4] origin:032-cmt-pll 29_666 +CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[5] origin:032-cmt-pll 28_667 +CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[6] origin:032-cmt-pll 29_668 +CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[7] origin:032-cmt-pll 28_669 +CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[8] origin:032-cmt-pll 29_670 +CMT_TOP_L_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[9] origin:032-cmt-pll 28_671 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LOCKREG1_RESERVED[0] origin:032-cmt-pll 28_229 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LOCKREG1_RESERVED[1] origin:032-cmt-pll 29_229 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LOCKREG1_RESERVED[2] origin:032-cmt-pll 28_230 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LOCKREG1_RESERVED[3] origin:032-cmt-pll 29_230 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LOCKREG1_RESERVED[4] origin:032-cmt-pll 28_231 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LOCKREG1_RESERVED[5] origin:032-cmt-pll 29_231 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LOCKREG2_RESERVED[0] origin:032-cmt-pll 29_239 +CMT_TOP_L_UPPER_T.PLLE2_ADV.LOCKREG3_RESERVED[0] origin:032-cmt-pll 29_247 diff --git a/zynq7/segbits_cmt_top_r_lower_b.db b/zynq7/segbits_cmt_top_r_lower_b.db index 6bc69a2..626226a 100644 --- a/zynq7/segbits_cmt_top_r_lower_b.db +++ b/zynq7/segbits_cmt_top_r_lower_b.db @@ -23,381 +23,381 @@ CMT_TOP_R_LOWER_B.MMCM_CLK_FREQ_BB_NS2_ACTIVE 28_1068 28_1076 29_1057 CMT_TOP_R_LOWER_B.MMCM_CLK_FREQ_BB_NS2.MMCM_CLK_FREQ_BB_REBUF2_NS 28_1072 29_1067 29_1075 29_1079 CMT_TOP_R_LOWER_B.MMCM_CLK_FREQ_BB_NS3_ACTIVE 28_1058 28_1069 28_1077 CMT_TOP_R_LOWER_B.MMCM_CLK_FREQ_BB_NS3.MMCM_CLK_FREQ_BB_REBUF3_NS 28_1073 29_1068 29_1076 29_1080 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[0] 29_860 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[1] 28_860 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[2] 29_859 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[3] 28_859 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[4] 29_858 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[5] 28_858 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[0] 29_863 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[1] 28_863 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[2] 29_862 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[3] 28_862 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[4] 29_861 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[5] 28_861 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE[0] 29_857 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_PHASE_MUX[0] 28_857 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_PHASE_MUX[1] 29_856 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_PHASE_MUX[2] 28_856 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[0] 29_855 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[1] 28_855 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[2] 29_854 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[3] 28_854 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[4] 29_853 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[5] 28_853 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_EDGE[0] 28_852 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC[0] 29_849 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC[1] 28_849 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC[2] 29_848 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC_EN[0] 28_850 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC_WF_R[0] 29_850 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_MX[0] 29_851 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_MX[1] 28_851 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_NO_COUNT[0] 29_852 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_RESERVED[0] 28_848 -CMT_TOP_R_LOWER_B.MMCME2.COMP.Z_ZHOLD 28_979 28_1020 -CMT_TOP_R_LOWER_B.MMCME2.COMP.ZHOLD 28_1019 29_982 -CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_EDGE[0] 28_841 -CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[0] 29_844 -CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[1] 28_844 -CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[2] 29_843 -CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[3] 28_843 -CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[4] 29_842 -CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[5] 28_842 -CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[0] 29_847 -CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[1] 28_847 -CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[2] 29_846 -CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[3] 28_846 -CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[4] 29_845 -CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[5] 28_845 -CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_NO_COUNT[0] 29_841 -CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_RESERVED[0] 29_840 -CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_RESERVED[1] 28_840 -CMT_TOP_R_LOWER_B.MMCME2.IN_USE 28_18 28_21 28_22 28_23 28_24 28_25 28_27 28_28 28_31 28_32 28_33 28_34 28_36 28_37 28_38 28_39 28_40 28_44 28_46 28_47 28_48 28_49 28_50 28_51 28_52 28_54 28_63 28_65 28_66 28_70 28_72 28_73 28_75 28_77 28_78 28_428 28_429 28_430 28_433 28_434 28_466 28_488 28_492 28_772 28_773 28_774 28_787 28_976 28_978 28_989 28_991 28_1007 29_16 29_18 29_22 29_25 29_28 29_31 29_34 29_35 29_36 29_37 29_39 29_40 29_41 29_42 29_44 29_45 29_46 29_47 29_48 29_51 29_52 29_56 29_57 29_60 29_64 29_65 29_66 29_67 29_68 29_70 29_71 29_72 29_73 29_75 29_76 29_77 29_78 29_95 29_427 29_428 29_431 29_432 29_433 29_463 29_771 29_772 29_775 29_789 29_833 29_836 29_839 29_977 29_981 29_987 29_990 29_991 29_1007 29_1018 -CMT_TOP_R_LOWER_B.MMCME2.INV_CLKINSEL 29_109 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[0] 29_823 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[1] 28_823 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[2] 29_822 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[3] 28_822 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[4] 29_821 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[5] 28_821 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[6] 29_820 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[7] 28_820 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[8] 29_819 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[9] 28_819 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[10] 29_815 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[11] 28_815 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[12] 29_814 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[13] 28_814 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[14] 29_813 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[15] 28_813 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[16] 29_812 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[17] 28_812 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[18] 29_811 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[19] 28_811 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[20] 29_831 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[21] 28_831 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[22] 29_830 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[23] 28_830 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[24] 29_829 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[25] 28_829 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[26] 29_828 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[27] 28_828 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[28] 29_827 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[29] 28_827 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[30] 29_818 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[31] 28_818 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[32] 29_817 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[33] 28_817 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[34] 29_816 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[35] 29_810 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[36] 28_810 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[37] 29_809 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[38] 28_809 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[39] 29_808 -CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[0] 29_703 -CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[1] 28_703 -CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[2] 29_702 -CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[3] 28_702 -CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[4] 29_701 -CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[5] 28_701 -CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[6] 29_700 -CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[7] 28_700 -CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[8] 29_699 -CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[9] 28_699 -CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[10] 29_698 -CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[11] 28_698 -CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[12] 29_697 -CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[13] 28_697 -CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[14] 29_696 -CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[15] 28_696 -CMT_TOP_R_LOWER_B.MMCME2.SS_EN 28_95 28_388 28_696 28_698 28_700 28_702 28_850 28_915 29_389 29_697 29_701 29_703 -CMT_TOP_R_LOWER_B.MMCME2.STARTUP_WAIT 29_94 -CMT_TOP_R_LOWER_B.MMCME2.TABLE[0] 29_389 -CMT_TOP_R_LOWER_B.MMCME2.TABLE[1] 28_388 -CMT_TOP_R_LOWER_B.MMCME2.TABLE[2] 29_387 -CMT_TOP_R_LOWER_B.MMCME2.TABLE[3] 28_386 -CMT_TOP_R_LOWER_B.MMCME2.TABLE[4] 29_385 -CMT_TOP_R_LOWER_B.MMCME2.TABLE[5] 28_384 -CMT_TOP_R_LOWER_B.MMCME2.TABLE[6] 29_395 -CMT_TOP_R_LOWER_B.MMCME2.TABLE[7] 28_394 -CMT_TOP_R_LOWER_B.MMCME2.TABLE[8] 29_393 -CMT_TOP_R_LOWER_B.MMCME2.TABLE[9] 28_392 -CMT_TOP_R_LOWER_B.MMCME2.ZINV_PSEN 28_110 -CMT_TOP_R_LOWER_B.MMCME2.ZINV_PSINCDEC 29_110 -CMT_TOP_R_LOWER_B.MMCME2.ZINV_PWRDWN 28_111 -CMT_TOP_R_LOWER_B.MMCME2.ZINV_RST 29_111 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[0] 29_956 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[1] 28_956 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[2] 29_955 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[3] 28_955 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[4] 29_954 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[5] 28_954 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[0] 29_959 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[1] 28_959 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[2] 29_958 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[3] 28_958 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[4] 29_957 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[5] 28_957 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_OUTPUT_ENABLE[0] 29_953 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_PHASE_MUX[0] 28_953 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_PHASE_MUX[1] 29_952 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_PHASE_MUX[2] 28_952 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[0] 29_951 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[1] 28_951 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[2] 29_950 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[3] 28_950 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[4] 29_949 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[5] 28_949 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_EDGE[0] 28_948 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC[0] 29_945 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC[1] 28_945 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC[2] 29_944 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC_EN[0] 28_946 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC_WF_R[0] 29_946 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_MX[0] 29_947 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_MX[1] 28_947 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_NO_COUNT[0] 29_948 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_RESERVED[0] 28_944 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[0] 29_940 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[1] 28_940 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[2] 29_939 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[3] 28_939 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[4] 29_938 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[5] 28_938 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[0] 29_943 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[1] 28_943 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[2] 29_942 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[3] 28_942 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[4] 29_941 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[5] 28_941 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_OUTPUT_ENABLE[0] 29_937 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_PHASE_MUX[0] 28_937 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_PHASE_MUX[1] 29_936 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_PHASE_MUX[2] 28_936 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[0] 29_935 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[1] 28_935 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[2] 29_934 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[3] 28_934 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[4] 29_933 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[5] 28_933 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_EDGE[0] 28_932 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC[0] 29_929 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC[1] 28_929 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC[2] 29_928 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC_EN[0] 28_930 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC_WF_R[0] 29_930 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_MX[0] 29_931 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_MX[1] 28_931 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_NO_COUNT[0] 29_932 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_RESERVED[0] 28_928 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[0] 29_924 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[1] 28_924 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[2] 29_923 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[3] 28_923 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[4] 29_922 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[5] 28_922 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[0] 29_927 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[1] 28_927 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[2] 29_926 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[3] 28_926 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[4] 29_925 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[5] 28_925 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_OUTPUT_ENABLE[0] 29_921 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_PHASE_MUX[0] 28_921 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_PHASE_MUX[1] 29_920 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_PHASE_MUX[2] 28_920 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[0] 29_919 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[1] 28_919 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[2] 29_918 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[3] 28_918 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[4] 29_917 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[5] 28_917 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_EDGE[0] 28_916 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC[0] 29_913 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC[1] 28_913 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC[2] 29_912 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC_EN[0] 28_914 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC_WF_R[0] 29_914 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_MX[0] 29_915 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_MX[1] 28_915 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_NO_COUNT[0] 29_916 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_RESERVED[0] 28_912 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[0] 29_908 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[1] 28_908 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[2] 29_907 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[3] 28_907 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[4] 29_906 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[5] 28_906 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[0] 29_911 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[1] 28_911 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[2] 29_910 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[3] 28_910 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[4] 29_909 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[5] 28_909 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_OUTPUT_ENABLE[0] 29_905 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_PHASE_MUX[0] 28_905 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_PHASE_MUX[1] 29_904 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_PHASE_MUX[2] 28_904 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[0] 29_903 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[1] 28_903 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[2] 29_902 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[3] 28_902 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[4] 29_901 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[5] 28_901 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_EDGE[0] 28_900 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC[0] 29_897 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC[1] 28_897 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC[2] 29_896 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC_EN[0] 28_898 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC_WF_R[0] 29_898 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_MX[0] 29_899 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_MX[1] 28_899 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_NO_COUNT[0] 29_900 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_RESERVED[0] 28_896 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[0] 29_892 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[1] 28_892 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[2] 29_891 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[3] 28_891 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[4] 29_890 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[5] 28_890 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[0] 29_895 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[1] 28_895 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[2] 29_894 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[3] 28_894 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[4] 29_893 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[5] 28_893 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_OUTPUT_ENABLE[0] 29_889 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_PHASE_MUX[0] 28_889 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_PHASE_MUX[1] 29_888 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_PHASE_MUX[2] 28_888 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[0] 29_887 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[1] 28_887 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[2] 29_886 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[3] 28_886 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[4] 29_885 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[5] 28_885 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_EDGE[0] 28_884 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC[0] 29_881 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC[1] 28_881 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC[2] 29_880 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC_EN[0] 28_882 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC_WF_R[0] 29_882 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_MX[0] 29_883 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_MX[1] 28_883 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_NO_COUNT[0] 29_884 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_RESERVED[0] 28_880 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[0] 29_972 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[1] 28_972 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[2] 29_971 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[3] 28_971 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[4] 29_970 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[5] 28_970 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[0] 29_975 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[1] 28_975 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[2] 29_974 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[3] 28_974 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[4] 29_973 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[5] 28_973 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_OUTPUT_ENABLE[0] 29_969 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_PHASE_MUX[0] 28_969 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_PHASE_MUX[1] 29_968 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_PHASE_MUX[2] 28_968 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[0] 29_967 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[1] 28_967 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[2] 29_966 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[3] 28_966 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[4] 29_965 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[5] 28_965 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_EDGE[0] 28_964 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_FRAC_WF_F[0] 29_962 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_MX[0] 29_963 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_MX[1] 28_963 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_NO_COUNT[0] 29_964 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[0] 28_962 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[1] 29_961 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[2] 28_961 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_RESERVED[0] 29_960 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_RESERVED[1] 28_960 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[0] 29_876 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[1] 28_876 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[2] 29_875 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[3] 28_875 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[4] 29_874 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[5] 28_874 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[0] 29_879 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[1] 28_879 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[2] 29_878 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[3] 28_878 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[4] 29_877 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[5] 28_877 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_OUTPUT_ENABLE[0] 29_873 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_PHASE_MUX[0] 28_873 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_PHASE_MUX[1] 29_872 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_PHASE_MUX[2] 28_872 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[0] 29_871 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[1] 28_871 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[2] 29_870 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[3] 28_870 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[4] 29_869 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[5] 28_869 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_EDGE[0] 28_868 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_FRAC_WF_F[0] 29_866 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_MX[0] 29_867 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_MX[1] 28_867 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_NO_COUNT[0] 29_868 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[0] 28_866 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[1] 29_865 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[2] 28_865 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_RESERVED[0] 29_864 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_RESERVED[1] 28_864 -CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[0] 29_399 -CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[1] 28_399 -CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[2] 29_398 -CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[3] 28_398 -CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[4] 29_397 -CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[5] 28_397 -CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[6] 29_396 -CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[7] 28_396 -CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[8] 28_395 -CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[9] 29_394 -CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[10] 28_393 -CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[11] 29_392 -CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[0] 29_391 -CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[1] 28_391 -CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[2] 29_390 -CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[3] 28_390 -CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[4] 28_389 -CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[5] 29_388 -CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[6] 28_387 -CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[7] 29_386 -CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[8] 28_385 -CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[9] 29_384 -CMT_TOP_R_LOWER_B.MMCME2.LOCKREG1_RESERVED[0] 29_826 -CMT_TOP_R_LOWER_B.MMCME2.LOCKREG1_RESERVED[1] 28_826 -CMT_TOP_R_LOWER_B.MMCME2.LOCKREG1_RESERVED[2] 29_825 -CMT_TOP_R_LOWER_B.MMCME2.LOCKREG1_RESERVED[3] 28_825 -CMT_TOP_R_LOWER_B.MMCME2.LOCKREG1_RESERVED[4] 29_824 -CMT_TOP_R_LOWER_B.MMCME2.LOCKREG1_RESERVED[5] 28_824 -CMT_TOP_R_LOWER_B.MMCME2.LOCKREG2_RESERVED[0] 28_816 -CMT_TOP_R_LOWER_B.MMCME2.LOCKREG3_RESERVED[0] 28_808 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[0] 29_860 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[1] 28_860 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[2] 29_859 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[3] 28_859 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[4] 29_858 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[5] 28_858 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[0] 29_863 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[1] 28_863 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[2] 29_862 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[3] 28_862 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[4] 29_861 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[5] 28_861 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE[0] 29_857 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_PHASE_MUX[0] 28_857 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_PHASE_MUX[1] 29_856 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_PHASE_MUX[2] 28_856 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[0] 29_855 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[1] 28_855 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[2] 29_854 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[3] 28_854 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[4] 29_853 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[5] 28_853 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_EDGE[0] 28_852 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_FRAC[0] 29_849 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_FRAC[1] 28_849 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_FRAC[2] 29_848 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_FRAC_EN[0] 28_850 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_FRAC_WF_R[0] 29_850 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_MX[0] 29_851 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_MX[1] 28_851 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_NO_COUNT[0] 29_852 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_RESERVED[0] 28_848 +CMT_TOP_R_LOWER_B.MMCME2_ADV.COMP.Z_ZHOLD 28_979 28_1020 +CMT_TOP_R_LOWER_B.MMCME2_ADV.COMP.ZHOLD 28_1019 29_982 +CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_EDGE[0] 28_841 +CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_HIGH_TIME[0] 29_844 +CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_HIGH_TIME[1] 28_844 +CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_HIGH_TIME[2] 29_843 +CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_HIGH_TIME[3] 28_843 +CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_HIGH_TIME[4] 29_842 +CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_HIGH_TIME[5] 28_842 +CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_LOW_TIME[0] 29_847 +CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_LOW_TIME[1] 28_847 +CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_LOW_TIME[2] 29_846 +CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_LOW_TIME[3] 28_846 +CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_LOW_TIME[4] 29_845 +CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_LOW_TIME[5] 28_845 +CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_NO_COUNT[0] 29_841 +CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_RESERVED[0] 29_840 +CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_RESERVED[1] 28_840 +CMT_TOP_R_LOWER_B.MMCME2_ADV.IN_USE 28_18 28_21 28_22 28_23 28_24 28_25 28_27 28_28 28_31 28_32 28_33 28_34 28_36 28_37 28_38 28_39 28_40 28_44 28_46 28_47 28_48 28_49 28_50 28_51 28_52 28_54 28_63 28_65 28_66 28_70 28_72 28_73 28_75 28_77 28_78 28_428 28_429 28_430 28_433 28_434 28_466 28_488 28_492 28_772 28_773 28_774 28_787 28_976 28_978 28_989 28_991 28_1007 29_16 29_18 29_22 29_25 29_28 29_31 29_34 29_35 29_36 29_37 29_39 29_40 29_41 29_42 29_44 29_45 29_46 29_47 29_48 29_51 29_52 29_56 29_57 29_60 29_64 29_65 29_66 29_67 29_68 29_70 29_71 29_72 29_73 29_75 29_76 29_77 29_78 29_95 29_427 29_428 29_431 29_432 29_433 29_463 29_771 29_772 29_775 29_789 29_833 29_836 29_839 29_977 29_981 29_987 29_990 29_991 29_1007 29_1018 +CMT_TOP_R_LOWER_B.MMCME2_ADV.INV_CLKINSEL 29_109 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[0] 29_823 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[1] 28_823 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[2] 29_822 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[3] 28_822 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[4] 29_821 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[5] 28_821 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[6] 29_820 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[7] 28_820 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[8] 29_819 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[9] 28_819 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[10] 29_815 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[11] 28_815 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[12] 29_814 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[13] 28_814 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[14] 29_813 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[15] 28_813 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[16] 29_812 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[17] 28_812 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[18] 29_811 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[19] 28_811 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[20] 29_831 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[21] 28_831 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[22] 29_830 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[23] 28_830 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[24] 29_829 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[25] 28_829 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[26] 29_828 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[27] 28_828 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[28] 29_827 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[29] 28_827 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[30] 29_818 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[31] 28_818 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[32] 29_817 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[33] 28_817 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[34] 29_816 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[35] 29_810 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[36] 28_810 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[37] 29_809 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[38] 28_809 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[39] 29_808 +CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[0] 29_703 +CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[1] 28_703 +CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[2] 29_702 +CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[3] 28_702 +CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[4] 29_701 +CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[5] 28_701 +CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[6] 29_700 +CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[7] 28_700 +CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[8] 29_699 +CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[9] 28_699 +CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[10] 29_698 +CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[11] 28_698 +CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[12] 29_697 +CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[13] 28_697 +CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[14] 29_696 +CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[15] 28_696 +CMT_TOP_R_LOWER_B.MMCME2_ADV.SS_EN 28_95 28_388 28_696 28_698 28_700 28_702 28_850 28_915 29_389 29_697 29_701 29_703 +CMT_TOP_R_LOWER_B.MMCME2_ADV.STARTUP_WAIT 29_94 +CMT_TOP_R_LOWER_B.MMCME2_ADV.TABLE[0] 29_389 +CMT_TOP_R_LOWER_B.MMCME2_ADV.TABLE[1] 28_388 +CMT_TOP_R_LOWER_B.MMCME2_ADV.TABLE[2] 29_387 +CMT_TOP_R_LOWER_B.MMCME2_ADV.TABLE[3] 28_386 +CMT_TOP_R_LOWER_B.MMCME2_ADV.TABLE[4] 29_385 +CMT_TOP_R_LOWER_B.MMCME2_ADV.TABLE[5] 28_384 +CMT_TOP_R_LOWER_B.MMCME2_ADV.TABLE[6] 29_395 +CMT_TOP_R_LOWER_B.MMCME2_ADV.TABLE[7] 28_394 +CMT_TOP_R_LOWER_B.MMCME2_ADV.TABLE[8] 29_393 +CMT_TOP_R_LOWER_B.MMCME2_ADV.TABLE[9] 28_392 +CMT_TOP_R_LOWER_B.MMCME2_ADV.ZINV_PSEN 28_110 +CMT_TOP_R_LOWER_B.MMCME2_ADV.ZINV_PSINCDEC 29_110 +CMT_TOP_R_LOWER_B.MMCME2_ADV.ZINV_PWRDWN 28_111 +CMT_TOP_R_LOWER_B.MMCME2_ADV.ZINV_RST 29_111 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[0] 29_956 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[1] 28_956 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[2] 29_955 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[3] 28_955 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[4] 29_954 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[5] 28_954 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[0] 29_959 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[1] 28_959 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[2] 29_958 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[3] 28_958 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[4] 29_957 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[5] 28_957 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_OUTPUT_ENABLE[0] 29_953 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_PHASE_MUX[0] 28_953 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_PHASE_MUX[1] 29_952 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_PHASE_MUX[2] 28_952 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[0] 29_951 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[1] 28_951 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[2] 29_950 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[3] 28_950 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[4] 29_949 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[5] 28_949 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_EDGE[0] 28_948 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_FRAC[0] 29_945 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_FRAC[1] 28_945 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_FRAC[2] 29_944 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_FRAC_EN[0] 28_946 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_FRAC_WF_R[0] 29_946 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_MX[0] 29_947 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_MX[1] 28_947 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_NO_COUNT[0] 29_948 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_RESERVED[0] 28_944 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[0] 29_940 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[1] 28_940 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[2] 29_939 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[3] 28_939 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[4] 29_938 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[5] 28_938 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[0] 29_943 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[1] 28_943 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[2] 29_942 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[3] 28_942 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[4] 29_941 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[5] 28_941 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_OUTPUT_ENABLE[0] 29_937 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_PHASE_MUX[0] 28_937 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_PHASE_MUX[1] 29_936 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_PHASE_MUX[2] 28_936 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[0] 29_935 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[1] 28_935 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[2] 29_934 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[3] 28_934 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[4] 29_933 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[5] 28_933 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_EDGE[0] 28_932 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_FRAC[0] 29_929 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_FRAC[1] 28_929 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_FRAC[2] 29_928 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_FRAC_EN[0] 28_930 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_FRAC_WF_R[0] 29_930 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_MX[0] 29_931 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_MX[1] 28_931 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_NO_COUNT[0] 29_932 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_RESERVED[0] 28_928 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[0] 29_924 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[1] 28_924 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[2] 29_923 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[3] 28_923 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[4] 29_922 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[5] 28_922 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[0] 29_927 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[1] 28_927 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[2] 29_926 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[3] 28_926 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[4] 29_925 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[5] 28_925 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_OUTPUT_ENABLE[0] 29_921 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_PHASE_MUX[0] 28_921 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_PHASE_MUX[1] 29_920 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_PHASE_MUX[2] 28_920 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[0] 29_919 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[1] 28_919 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[2] 29_918 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[3] 28_918 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[4] 29_917 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[5] 28_917 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_EDGE[0] 28_916 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_FRAC[0] 29_913 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_FRAC[1] 28_913 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_FRAC[2] 29_912 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_FRAC_EN[0] 28_914 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_FRAC_WF_R[0] 29_914 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_MX[0] 29_915 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_MX[1] 28_915 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_NO_COUNT[0] 29_916 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_RESERVED[0] 28_912 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[0] 29_908 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[1] 28_908 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[2] 29_907 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[3] 28_907 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[4] 29_906 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[5] 28_906 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[0] 29_911 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[1] 28_911 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[2] 29_910 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[3] 28_910 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[4] 29_909 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[5] 28_909 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_OUTPUT_ENABLE[0] 29_905 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_PHASE_MUX[0] 28_905 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_PHASE_MUX[1] 29_904 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_PHASE_MUX[2] 28_904 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[0] 29_903 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[1] 28_903 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[2] 29_902 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[3] 28_902 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[4] 29_901 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[5] 28_901 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_EDGE[0] 28_900 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_FRAC[0] 29_897 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_FRAC[1] 28_897 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_FRAC[2] 29_896 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_FRAC_EN[0] 28_898 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_FRAC_WF_R[0] 29_898 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_MX[0] 29_899 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_MX[1] 28_899 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_NO_COUNT[0] 29_900 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_RESERVED[0] 28_896 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[0] 29_892 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[1] 28_892 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[2] 29_891 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[3] 28_891 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[4] 29_890 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[5] 28_890 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[0] 29_895 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[1] 28_895 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[2] 29_894 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[3] 28_894 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[4] 29_893 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[5] 28_893 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_OUTPUT_ENABLE[0] 29_889 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_PHASE_MUX[0] 28_889 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_PHASE_MUX[1] 29_888 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_PHASE_MUX[2] 28_888 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[0] 29_887 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[1] 28_887 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[2] 29_886 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[3] 28_886 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[4] 29_885 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[5] 28_885 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_EDGE[0] 28_884 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_FRAC[0] 29_881 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_FRAC[1] 28_881 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_FRAC[2] 29_880 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_FRAC_EN[0] 28_882 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_FRAC_WF_R[0] 29_882 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_MX[0] 29_883 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_MX[1] 28_883 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_NO_COUNT[0] 29_884 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_RESERVED[0] 28_880 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[0] 29_972 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[1] 28_972 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[2] 29_971 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[3] 28_971 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[4] 29_970 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[5] 28_970 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[0] 29_975 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[1] 28_975 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[2] 29_974 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[3] 28_974 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[4] 29_973 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[5] 28_973 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_OUTPUT_ENABLE[0] 29_969 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_PHASE_MUX[0] 28_969 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_PHASE_MUX[1] 29_968 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_PHASE_MUX[2] 28_968 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[0] 29_967 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[1] 28_967 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[2] 29_966 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[3] 28_966 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[4] 29_965 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[5] 28_965 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_EDGE[0] 28_964 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_FRAC_WF_F[0] 29_962 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_MX[0] 29_963 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_MX[1] 28_963 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_NO_COUNT[0] 29_964 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[0] 28_962 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[1] 29_961 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[2] 28_961 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_RESERVED[0] 29_960 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_RESERVED[1] 28_960 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_HIGH_TIME[0] 29_876 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_HIGH_TIME[1] 28_876 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_HIGH_TIME[2] 29_875 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_HIGH_TIME[3] 28_875 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_HIGH_TIME[4] 29_874 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_HIGH_TIME[5] 28_874 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_LOW_TIME[0] 29_879 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_LOW_TIME[1] 28_879 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_LOW_TIME[2] 29_878 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_LOW_TIME[3] 28_878 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_LOW_TIME[4] 29_877 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_LOW_TIME[5] 28_877 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_OUTPUT_ENABLE[0] 29_873 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_PHASE_MUX[0] 28_873 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_PHASE_MUX[1] 29_872 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_PHASE_MUX[2] 28_872 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[0] 29_871 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[1] 28_871 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[2] 29_870 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[3] 28_870 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[4] 29_869 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[5] 28_869 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_EDGE[0] 28_868 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_FRAC_WF_F[0] 29_866 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_MX[0] 29_867 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_MX[1] 28_867 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_NO_COUNT[0] 29_868 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[0] 28_866 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[1] 29_865 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[2] 28_865 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_RESERVED[0] 29_864 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_RESERVED[1] 28_864 +CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[0] 29_399 +CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[1] 28_399 +CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[2] 29_398 +CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[3] 28_398 +CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[4] 29_397 +CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[5] 28_397 +CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[6] 29_396 +CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[7] 28_396 +CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[8] 28_395 +CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[9] 29_394 +CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[10] 28_393 +CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[11] 29_392 +CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[0] 29_391 +CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[1] 28_391 +CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[2] 29_390 +CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[3] 28_390 +CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[4] 28_389 +CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[5] 29_388 +CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[6] 28_387 +CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[7] 29_386 +CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[8] 28_385 +CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[9] 29_384 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LOCKREG1_RESERVED[0] 29_826 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LOCKREG1_RESERVED[1] 28_826 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LOCKREG1_RESERVED[2] 29_825 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LOCKREG1_RESERVED[3] 28_825 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LOCKREG1_RESERVED[4] 29_824 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LOCKREG1_RESERVED[5] 28_824 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LOCKREG2_RESERVED[0] 28_816 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LOCKREG3_RESERVED[0] 28_808 diff --git a/zynq7/segbits_cmt_top_r_lower_b.origin_info.db b/zynq7/segbits_cmt_top_r_lower_b.origin_info.db index cb581bc..5e51b96 100644 --- a/zynq7/segbits_cmt_top_r_lower_b.origin_info.db +++ b/zynq7/segbits_cmt_top_r_lower_b.origin_info.db @@ -23,381 +23,381 @@ CMT_TOP_R_LOWER_B.MMCM_CLK_FREQ_BB_NS2_ACTIVE origin:034b-cmt-mmcm-pips 28_1068 CMT_TOP_R_LOWER_B.MMCM_CLK_FREQ_BB_NS2.MMCM_CLK_FREQ_BB_REBUF2_NS origin:034b-cmt-mmcm-pips 28_1072 29_1067 29_1075 29_1079 CMT_TOP_R_LOWER_B.MMCM_CLK_FREQ_BB_NS3_ACTIVE origin:034b-cmt-mmcm-pips 28_1058 28_1069 28_1077 CMT_TOP_R_LOWER_B.MMCM_CLK_FREQ_BB_NS3.MMCM_CLK_FREQ_BB_REBUF3_NS origin:034b-cmt-mmcm-pips 28_1073 29_1068 29_1076 29_1080 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_860 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_860 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_859 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_859 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_858 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_858 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_863 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_863 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_862 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_862 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_861 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_861 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_857 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_857 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_856 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_856 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_855 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_855 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_854 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_854 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_853 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_853 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_852 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_849 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_849 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_848 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_850 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_850 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_851 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_851 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_852 -CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_848 -CMT_TOP_R_LOWER_B.MMCME2.COMP.Z_ZHOLD origin:031-cmt-mmcm 28_1020 28_979 -CMT_TOP_R_LOWER_B.MMCME2.COMP.ZHOLD origin:031-cmt-mmcm 28_1019 29_982 -CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_EDGE[0] origin:031-cmt-mmcm 28_841 -CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[0] origin:031-cmt-mmcm 29_844 -CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[1] origin:031-cmt-mmcm 28_844 -CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[2] origin:031-cmt-mmcm 29_843 -CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[3] origin:031-cmt-mmcm 28_843 -CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[4] origin:031-cmt-mmcm 29_842 -CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[5] origin:031-cmt-mmcm 28_842 -CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[0] origin:031-cmt-mmcm 29_847 -CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[1] origin:031-cmt-mmcm 28_847 -CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[2] origin:031-cmt-mmcm 29_846 -CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[3] origin:031-cmt-mmcm 28_846 -CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[4] origin:031-cmt-mmcm 29_845 -CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[5] origin:031-cmt-mmcm 28_845 -CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_NO_COUNT[0] origin:031-cmt-mmcm 29_841 -CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_RESERVED[0] origin:031-cmt-mmcm 29_840 -CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_RESERVED[1] origin:031-cmt-mmcm 28_840 -CMT_TOP_R_LOWER_B.MMCME2.IN_USE origin:031-cmt-mmcm 28_1007 28_18 28_21 28_22 28_23 28_24 28_25 28_27 28_28 28_31 28_32 28_33 28_34 28_36 28_37 28_38 28_39 28_40 28_428 28_429 28_430 28_433 28_434 28_44 28_46 28_466 28_47 28_48 28_488 28_49 28_492 28_50 28_51 28_52 28_54 28_63 28_65 28_66 28_70 28_72 28_73 28_75 28_77 28_772 28_773 28_774 28_78 28_787 28_976 28_978 28_989 28_991 29_1007 29_1018 29_16 29_18 29_22 29_25 29_28 29_31 29_34 29_35 29_36 29_37 29_39 29_40 29_41 29_42 29_427 29_428 29_431 29_432 29_433 29_44 29_45 29_46 29_463 29_47 29_48 29_51 29_52 29_56 29_57 29_60 29_64 29_65 29_66 29_67 29_68 29_70 29_71 29_72 29_73 29_75 29_76 29_77 29_771 29_772 29_775 29_78 29_789 29_833 29_836 29_839 29_95 29_977 29_981 29_987 29_990 29_991 -CMT_TOP_R_LOWER_B.MMCME2.INV_CLKINSEL origin:031-cmt-mmcm 29_109 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[0] origin:031-cmt-mmcm 29_823 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[1] origin:031-cmt-mmcm 28_823 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[2] origin:031-cmt-mmcm 29_822 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[3] origin:031-cmt-mmcm 28_822 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[4] origin:031-cmt-mmcm 29_821 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[5] origin:031-cmt-mmcm 28_821 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[6] origin:031-cmt-mmcm 29_820 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[7] origin:031-cmt-mmcm 28_820 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[8] origin:031-cmt-mmcm 29_819 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[9] origin:031-cmt-mmcm 28_819 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[10] origin:031-cmt-mmcm 29_815 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[11] origin:031-cmt-mmcm 28_815 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[12] origin:031-cmt-mmcm 29_814 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[13] origin:031-cmt-mmcm 28_814 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[14] origin:031-cmt-mmcm 29_813 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[15] origin:031-cmt-mmcm 28_813 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[16] origin:031-cmt-mmcm 29_812 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[17] origin:031-cmt-mmcm 28_812 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[18] origin:031-cmt-mmcm 29_811 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[19] origin:031-cmt-mmcm 28_811 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[20] origin:031-cmt-mmcm 29_831 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[21] origin:031-cmt-mmcm 28_831 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[22] origin:031-cmt-mmcm 29_830 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[23] origin:031-cmt-mmcm 28_830 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[24] origin:031-cmt-mmcm 29_829 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[25] origin:031-cmt-mmcm 28_829 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[26] origin:031-cmt-mmcm 29_828 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[27] origin:031-cmt-mmcm 28_828 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[28] origin:031-cmt-mmcm 29_827 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[29] origin:031-cmt-mmcm 28_827 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[30] origin:031-cmt-mmcm 29_818 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[31] origin:031-cmt-mmcm 28_818 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[32] origin:031-cmt-mmcm 29_817 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[33] origin:031-cmt-mmcm 28_817 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[34] origin:031-cmt-mmcm 29_816 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[35] origin:031-cmt-mmcm 29_810 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[36] origin:031-cmt-mmcm 28_810 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[37] origin:031-cmt-mmcm 29_809 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[38] origin:031-cmt-mmcm 28_809 -CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[39] origin:031-cmt-mmcm 29_808 -CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[0] origin:031-cmt-mmcm 29_703 -CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[1] origin:031-cmt-mmcm 28_703 -CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[2] origin:031-cmt-mmcm 29_702 -CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[3] origin:031-cmt-mmcm 28_702 -CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[4] origin:031-cmt-mmcm 29_701 -CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[5] origin:031-cmt-mmcm 28_701 -CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[6] origin:031-cmt-mmcm 29_700 -CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[7] origin:031-cmt-mmcm 28_700 -CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[8] origin:031-cmt-mmcm 29_699 -CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[9] origin:031-cmt-mmcm 28_699 -CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[10] origin:031-cmt-mmcm 29_698 -CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[11] origin:031-cmt-mmcm 28_698 -CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[12] origin:031-cmt-mmcm 29_697 -CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[13] origin:031-cmt-mmcm 28_697 -CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[14] origin:031-cmt-mmcm 29_696 -CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[15] origin:031-cmt-mmcm 28_696 -CMT_TOP_R_LOWER_B.MMCME2.SS_EN origin:031-cmt-mmcm 28_388 28_696 28_698 28_700 28_702 28_850 28_915 28_95 29_389 29_697 29_701 29_703 -CMT_TOP_R_LOWER_B.MMCME2.STARTUP_WAIT origin:031-cmt-mmcm 29_94 -CMT_TOP_R_LOWER_B.MMCME2.TABLE[0] origin:031-cmt-mmcm 29_389 -CMT_TOP_R_LOWER_B.MMCME2.TABLE[1] origin:031-cmt-mmcm 28_388 -CMT_TOP_R_LOWER_B.MMCME2.TABLE[2] origin:031-cmt-mmcm 29_387 -CMT_TOP_R_LOWER_B.MMCME2.TABLE[3] origin:031-cmt-mmcm 28_386 -CMT_TOP_R_LOWER_B.MMCME2.TABLE[4] origin:031-cmt-mmcm 29_385 -CMT_TOP_R_LOWER_B.MMCME2.TABLE[5] origin:031-cmt-mmcm 28_384 -CMT_TOP_R_LOWER_B.MMCME2.TABLE[6] origin:031-cmt-mmcm 29_395 -CMT_TOP_R_LOWER_B.MMCME2.TABLE[7] origin:031-cmt-mmcm 28_394 -CMT_TOP_R_LOWER_B.MMCME2.TABLE[8] origin:031-cmt-mmcm 29_393 -CMT_TOP_R_LOWER_B.MMCME2.TABLE[9] origin:031-cmt-mmcm 28_392 -CMT_TOP_R_LOWER_B.MMCME2.ZINV_PSEN origin:031-cmt-mmcm 28_110 -CMT_TOP_R_LOWER_B.MMCME2.ZINV_PSINCDEC origin:031-cmt-mmcm 29_110 -CMT_TOP_R_LOWER_B.MMCME2.ZINV_PWRDWN origin:031-cmt-mmcm 28_111 -CMT_TOP_R_LOWER_B.MMCME2.ZINV_RST origin:031-cmt-mmcm 29_111 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_956 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_956 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_955 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_955 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_954 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_954 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_959 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_959 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_958 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_958 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_957 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_957 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_953 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_953 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_952 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_952 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_951 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_951 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_950 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_950 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_949 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_949 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_948 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_945 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_945 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_944 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_946 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_946 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_947 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_947 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_948 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_944 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_940 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_940 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_939 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_939 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_938 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_938 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_943 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_943 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_942 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_942 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_941 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_941 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_937 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_937 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_936 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_936 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_935 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_935 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_934 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_934 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_933 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_933 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_932 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_929 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_929 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_928 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_930 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_930 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_931 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_931 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_932 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_928 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_924 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_924 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_923 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_923 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_922 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_922 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_927 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_927 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_926 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_926 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_925 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_925 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_921 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_921 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_920 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_920 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_919 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_919 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_918 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_918 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_917 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_917 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_916 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_913 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_913 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_912 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_914 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_914 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_915 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_915 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_916 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_912 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_908 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_908 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_907 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_907 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_906 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_906 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_911 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_911 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_910 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_910 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_909 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_909 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_905 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_905 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_904 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_904 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_903 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_903 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_902 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_902 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_901 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_901 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_900 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_897 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_897 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_896 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_898 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_898 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_899 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_899 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_900 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_896 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_892 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_892 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_891 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_891 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_890 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_890 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_895 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_895 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_894 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_894 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_893 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_893 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_889 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_889 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_888 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_888 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_887 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_887 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_886 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_886 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_885 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_885 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_884 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_881 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_881 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_880 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_882 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_882 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_883 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_883 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_884 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_880 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_972 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_972 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_971 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_971 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_970 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_970 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_975 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_975 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_974 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_974 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_973 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_973 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_969 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_969 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_968 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_968 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[0] origin:031-cmt-mmcm 29_967 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[1] origin:031-cmt-mmcm 28_967 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[2] origin:031-cmt-mmcm 29_966 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[3] origin:031-cmt-mmcm 28_966 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[4] origin:031-cmt-mmcm 29_965 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[5] origin:031-cmt-mmcm 28_965 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_EDGE[0] origin:031-cmt-mmcm 28_964 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_FRAC_WF_F[0] origin:031-cmt-mmcm 29_962 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_MX[0] origin:031-cmt-mmcm 29_963 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_MX[1] origin:031-cmt-mmcm 28_963 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_NO_COUNT[0] origin:031-cmt-mmcm 29_964 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[0] origin:031-cmt-mmcm 28_962 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[1] origin:031-cmt-mmcm 29_961 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[2] origin:031-cmt-mmcm 28_961 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_RESERVED[0] origin:031-cmt-mmcm 29_960 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_RESERVED[1] origin:031-cmt-mmcm 28_960 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_876 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_876 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_875 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_875 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_874 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_874 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_879 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_879 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_878 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_878 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_877 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_877 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_873 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_873 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_872 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_872 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[0] origin:031-cmt-mmcm 29_871 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[1] origin:031-cmt-mmcm 28_871 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[2] origin:031-cmt-mmcm 29_870 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[3] origin:031-cmt-mmcm 28_870 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[4] origin:031-cmt-mmcm 29_869 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[5] origin:031-cmt-mmcm 28_869 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_EDGE[0] origin:031-cmt-mmcm 28_868 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_FRAC_WF_F[0] origin:031-cmt-mmcm 29_866 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_MX[0] origin:031-cmt-mmcm 29_867 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_MX[1] origin:031-cmt-mmcm 28_867 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_NO_COUNT[0] origin:031-cmt-mmcm 29_868 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[0] origin:031-cmt-mmcm 28_866 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[1] origin:031-cmt-mmcm 29_865 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[2] origin:031-cmt-mmcm 28_865 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_RESERVED[0] origin:031-cmt-mmcm 29_864 -CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_RESERVED[1] origin:031-cmt-mmcm 28_864 -CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[0] origin:031-cmt-mmcm 29_399 -CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[1] origin:031-cmt-mmcm 28_399 -CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[2] origin:031-cmt-mmcm 29_398 -CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[3] origin:031-cmt-mmcm 28_398 -CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[4] origin:031-cmt-mmcm 29_397 -CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[5] origin:031-cmt-mmcm 28_397 -CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[6] origin:031-cmt-mmcm 29_396 -CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[7] origin:031-cmt-mmcm 28_396 -CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[8] origin:031-cmt-mmcm 28_395 -CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[9] origin:031-cmt-mmcm 29_394 -CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[10] origin:031-cmt-mmcm 28_393 -CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[11] origin:031-cmt-mmcm 29_392 -CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[0] origin:031-cmt-mmcm 29_391 -CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[1] origin:031-cmt-mmcm 28_391 -CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[2] origin:031-cmt-mmcm 29_390 -CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[3] origin:031-cmt-mmcm 28_390 -CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[4] origin:031-cmt-mmcm 28_389 -CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[5] origin:031-cmt-mmcm 29_388 -CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[6] origin:031-cmt-mmcm 28_387 -CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[7] origin:031-cmt-mmcm 29_386 -CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[8] origin:031-cmt-mmcm 28_385 -CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[9] origin:031-cmt-mmcm 29_384 -CMT_TOP_R_LOWER_B.MMCME2.LOCKREG1_RESERVED[0] origin:031-cmt-mmcm 29_826 -CMT_TOP_R_LOWER_B.MMCME2.LOCKREG1_RESERVED[1] origin:031-cmt-mmcm 28_826 -CMT_TOP_R_LOWER_B.MMCME2.LOCKREG1_RESERVED[2] origin:031-cmt-mmcm 29_825 -CMT_TOP_R_LOWER_B.MMCME2.LOCKREG1_RESERVED[3] origin:031-cmt-mmcm 28_825 -CMT_TOP_R_LOWER_B.MMCME2.LOCKREG1_RESERVED[4] origin:031-cmt-mmcm 29_824 -CMT_TOP_R_LOWER_B.MMCME2.LOCKREG1_RESERVED[5] origin:031-cmt-mmcm 28_824 -CMT_TOP_R_LOWER_B.MMCME2.LOCKREG2_RESERVED[0] origin:031-cmt-mmcm 28_816 -CMT_TOP_R_LOWER_B.MMCME2.LOCKREG3_RESERVED[0] origin:031-cmt-mmcm 28_808 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_860 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_860 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_859 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_859 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_858 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_858 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_863 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_863 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_862 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_862 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_861 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_861 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_857 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_857 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_856 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_856 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_855 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_855 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_854 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_854 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_853 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_853 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_852 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_849 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_849 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_848 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_850 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_850 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_851 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_851 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_852 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKFBOUT_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_848 +CMT_TOP_R_LOWER_B.MMCME2_ADV.COMP.Z_ZHOLD origin:031-cmt-mmcm 28_1020 28_979 +CMT_TOP_R_LOWER_B.MMCME2_ADV.COMP.ZHOLD origin:031-cmt-mmcm 28_1019 29_982 +CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_EDGE[0] origin:031-cmt-mmcm 28_841 +CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_HIGH_TIME[0] origin:031-cmt-mmcm 29_844 +CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_HIGH_TIME[1] origin:031-cmt-mmcm 28_844 +CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_HIGH_TIME[2] origin:031-cmt-mmcm 29_843 +CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_HIGH_TIME[3] origin:031-cmt-mmcm 28_843 +CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_HIGH_TIME[4] origin:031-cmt-mmcm 29_842 +CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_HIGH_TIME[5] origin:031-cmt-mmcm 28_842 +CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_LOW_TIME[0] origin:031-cmt-mmcm 29_847 +CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_LOW_TIME[1] origin:031-cmt-mmcm 28_847 +CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_LOW_TIME[2] origin:031-cmt-mmcm 29_846 +CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_LOW_TIME[3] origin:031-cmt-mmcm 28_846 +CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_LOW_TIME[4] origin:031-cmt-mmcm 29_845 +CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_LOW_TIME[5] origin:031-cmt-mmcm 28_845 +CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_NO_COUNT[0] origin:031-cmt-mmcm 29_841 +CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_RESERVED[0] origin:031-cmt-mmcm 29_840 +CMT_TOP_R_LOWER_B.MMCME2_ADV.DIVCLK_DIVCLK_RESERVED[1] origin:031-cmt-mmcm 28_840 +CMT_TOP_R_LOWER_B.MMCME2_ADV.IN_USE origin:031-cmt-mmcm 28_1007 28_18 28_21 28_22 28_23 28_24 28_25 28_27 28_28 28_31 28_32 28_33 28_34 28_36 28_37 28_38 28_39 28_40 28_428 28_429 28_430 28_433 28_434 28_44 28_46 28_466 28_47 28_48 28_488 28_49 28_492 28_50 28_51 28_52 28_54 28_63 28_65 28_66 28_70 28_72 28_73 28_75 28_77 28_772 28_773 28_774 28_78 28_787 28_976 28_978 28_989 28_991 29_1007 29_1018 29_16 29_18 29_22 29_25 29_28 29_31 29_34 29_35 29_36 29_37 29_39 29_40 29_41 29_42 29_427 29_428 29_431 29_432 29_433 29_44 29_45 29_46 29_463 29_47 29_48 29_51 29_52 29_56 29_57 29_60 29_64 29_65 29_66 29_67 29_68 29_70 29_71 29_72 29_73 29_75 29_76 29_77 29_771 29_772 29_775 29_78 29_789 29_833 29_836 29_839 29_95 29_977 29_981 29_987 29_990 29_991 +CMT_TOP_R_LOWER_B.MMCME2_ADV.INV_CLKINSEL origin:031-cmt-mmcm 29_109 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[0] origin:031-cmt-mmcm 29_823 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[1] origin:031-cmt-mmcm 28_823 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[2] origin:031-cmt-mmcm 29_822 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[3] origin:031-cmt-mmcm 28_822 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[4] origin:031-cmt-mmcm 29_821 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[5] origin:031-cmt-mmcm 28_821 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[6] origin:031-cmt-mmcm 29_820 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[7] origin:031-cmt-mmcm 28_820 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[8] origin:031-cmt-mmcm 29_819 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[9] origin:031-cmt-mmcm 28_819 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[10] origin:031-cmt-mmcm 29_815 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[11] origin:031-cmt-mmcm 28_815 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[12] origin:031-cmt-mmcm 29_814 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[13] origin:031-cmt-mmcm 28_814 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[14] origin:031-cmt-mmcm 29_813 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[15] origin:031-cmt-mmcm 28_813 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[16] origin:031-cmt-mmcm 29_812 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[17] origin:031-cmt-mmcm 28_812 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[18] origin:031-cmt-mmcm 29_811 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[19] origin:031-cmt-mmcm 28_811 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[20] origin:031-cmt-mmcm 29_831 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[21] origin:031-cmt-mmcm 28_831 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[22] origin:031-cmt-mmcm 29_830 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[23] origin:031-cmt-mmcm 28_830 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[24] origin:031-cmt-mmcm 29_829 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[25] origin:031-cmt-mmcm 28_829 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[26] origin:031-cmt-mmcm 29_828 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[27] origin:031-cmt-mmcm 28_828 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[28] origin:031-cmt-mmcm 29_827 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[29] origin:031-cmt-mmcm 28_827 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[30] origin:031-cmt-mmcm 29_818 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[31] origin:031-cmt-mmcm 28_818 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[32] origin:031-cmt-mmcm 29_817 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[33] origin:031-cmt-mmcm 28_817 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[34] origin:031-cmt-mmcm 29_816 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[35] origin:031-cmt-mmcm 29_810 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[36] origin:031-cmt-mmcm 28_810 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[37] origin:031-cmt-mmcm 29_809 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[38] origin:031-cmt-mmcm 28_809 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LKTABLE[39] origin:031-cmt-mmcm 29_808 +CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[0] origin:031-cmt-mmcm 29_703 +CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[1] origin:031-cmt-mmcm 28_703 +CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[2] origin:031-cmt-mmcm 29_702 +CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[3] origin:031-cmt-mmcm 28_702 +CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[4] origin:031-cmt-mmcm 29_701 +CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[5] origin:031-cmt-mmcm 28_701 +CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[6] origin:031-cmt-mmcm 29_700 +CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[7] origin:031-cmt-mmcm 28_700 +CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[8] origin:031-cmt-mmcm 29_699 +CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[9] origin:031-cmt-mmcm 28_699 +CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[10] origin:031-cmt-mmcm 29_698 +CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[11] origin:031-cmt-mmcm 28_698 +CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[12] origin:031-cmt-mmcm 29_697 +CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[13] origin:031-cmt-mmcm 28_697 +CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[14] origin:031-cmt-mmcm 29_696 +CMT_TOP_R_LOWER_B.MMCME2_ADV.POWER_REG_POWER_REG_POWER_REG[15] origin:031-cmt-mmcm 28_696 +CMT_TOP_R_LOWER_B.MMCME2_ADV.SS_EN origin:031-cmt-mmcm 28_388 28_696 28_698 28_700 28_702 28_850 28_915 28_95 29_389 29_697 29_701 29_703 +CMT_TOP_R_LOWER_B.MMCME2_ADV.STARTUP_WAIT origin:031-cmt-mmcm 29_94 +CMT_TOP_R_LOWER_B.MMCME2_ADV.TABLE[0] origin:031-cmt-mmcm 29_389 +CMT_TOP_R_LOWER_B.MMCME2_ADV.TABLE[1] origin:031-cmt-mmcm 28_388 +CMT_TOP_R_LOWER_B.MMCME2_ADV.TABLE[2] origin:031-cmt-mmcm 29_387 +CMT_TOP_R_LOWER_B.MMCME2_ADV.TABLE[3] origin:031-cmt-mmcm 28_386 +CMT_TOP_R_LOWER_B.MMCME2_ADV.TABLE[4] origin:031-cmt-mmcm 29_385 +CMT_TOP_R_LOWER_B.MMCME2_ADV.TABLE[5] origin:031-cmt-mmcm 28_384 +CMT_TOP_R_LOWER_B.MMCME2_ADV.TABLE[6] origin:031-cmt-mmcm 29_395 +CMT_TOP_R_LOWER_B.MMCME2_ADV.TABLE[7] origin:031-cmt-mmcm 28_394 +CMT_TOP_R_LOWER_B.MMCME2_ADV.TABLE[8] origin:031-cmt-mmcm 29_393 +CMT_TOP_R_LOWER_B.MMCME2_ADV.TABLE[9] origin:031-cmt-mmcm 28_392 +CMT_TOP_R_LOWER_B.MMCME2_ADV.ZINV_PSEN origin:031-cmt-mmcm 28_110 +CMT_TOP_R_LOWER_B.MMCME2_ADV.ZINV_PSINCDEC origin:031-cmt-mmcm 29_110 +CMT_TOP_R_LOWER_B.MMCME2_ADV.ZINV_PWRDWN origin:031-cmt-mmcm 28_111 +CMT_TOP_R_LOWER_B.MMCME2_ADV.ZINV_RST origin:031-cmt-mmcm 29_111 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_956 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_956 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_955 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_955 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_954 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_954 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_959 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_959 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_958 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_958 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_957 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_957 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_953 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_953 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_952 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_952 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_951 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_951 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_950 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_950 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_949 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_949 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_948 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_945 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_945 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_944 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_946 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_946 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_947 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_947 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_948 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT0_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_944 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_940 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_940 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_939 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_939 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_938 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_938 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_943 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_943 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_942 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_942 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_941 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_941 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_937 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_937 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_936 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_936 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_935 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_935 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_934 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_934 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_933 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_933 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_932 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_929 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_929 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_928 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_930 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_930 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_931 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_931 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_932 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT1_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_928 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_924 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_924 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_923 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_923 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_922 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_922 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_927 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_927 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_926 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_926 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_925 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_925 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_921 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_921 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_920 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_920 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_919 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_919 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_918 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_918 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_917 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_917 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_916 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_913 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_913 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_912 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_914 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_914 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_915 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_915 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_916 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT2_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_912 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_908 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_908 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_907 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_907 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_906 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_906 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_911 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_911 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_910 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_910 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_909 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_909 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_905 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_905 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_904 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_904 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_903 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_903 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_902 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_902 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_901 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_901 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_900 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_897 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_897 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_896 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_898 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_898 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_899 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_899 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_900 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT3_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_896 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_892 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_892 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_891 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_891 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_890 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_890 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_895 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_895 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_894 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_894 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_893 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_893 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_889 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_889 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_888 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_888 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_887 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_887 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_886 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_886 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_885 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_885 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_884 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_881 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_881 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_880 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_882 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_882 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_883 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_883 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_884 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT4_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_880 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_972 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_972 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_971 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_971 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_970 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_970 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_975 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_975 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_974 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_974 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_973 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_973 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_969 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_969 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_968 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_968 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[0] origin:031-cmt-mmcm 29_967 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[1] origin:031-cmt-mmcm 28_967 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[2] origin:031-cmt-mmcm 29_966 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[3] origin:031-cmt-mmcm 28_966 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[4] origin:031-cmt-mmcm 29_965 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[5] origin:031-cmt-mmcm 28_965 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_EDGE[0] origin:031-cmt-mmcm 28_964 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_FRAC_WF_F[0] origin:031-cmt-mmcm 29_962 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_MX[0] origin:031-cmt-mmcm 29_963 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_MX[1] origin:031-cmt-mmcm 28_963 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_NO_COUNT[0] origin:031-cmt-mmcm 29_964 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[0] origin:031-cmt-mmcm 28_962 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[1] origin:031-cmt-mmcm 29_961 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[2] origin:031-cmt-mmcm 28_961 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_RESERVED[0] origin:031-cmt-mmcm 29_960 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT5_CLKOUT2_FRACTIONAL_RESERVED[1] origin:031-cmt-mmcm 28_960 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_876 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_876 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_875 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_875 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_874 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_874 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_879 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_879 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_878 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_878 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_877 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_877 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_873 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_873 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_872 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_872 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[0] origin:031-cmt-mmcm 29_871 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[1] origin:031-cmt-mmcm 28_871 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[2] origin:031-cmt-mmcm 29_870 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[3] origin:031-cmt-mmcm 28_870 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[4] origin:031-cmt-mmcm 29_869 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[5] origin:031-cmt-mmcm 28_869 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_EDGE[0] origin:031-cmt-mmcm 28_868 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_FRAC_WF_F[0] origin:031-cmt-mmcm 29_866 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_MX[0] origin:031-cmt-mmcm 29_867 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_MX[1] origin:031-cmt-mmcm 28_867 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_NO_COUNT[0] origin:031-cmt-mmcm 29_868 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[0] origin:031-cmt-mmcm 28_866 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[1] origin:031-cmt-mmcm 29_865 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[2] origin:031-cmt-mmcm 28_865 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_RESERVED[0] origin:031-cmt-mmcm 29_864 +CMT_TOP_R_LOWER_B.MMCME2_ADV.CLKOUT6_CLKOUT2_FRACTIONAL_RESERVED[1] origin:031-cmt-mmcm 28_864 +CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[0] origin:031-cmt-mmcm 29_399 +CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[1] origin:031-cmt-mmcm 28_399 +CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[2] origin:031-cmt-mmcm 29_398 +CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[3] origin:031-cmt-mmcm 28_398 +CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[4] origin:031-cmt-mmcm 29_397 +CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[5] origin:031-cmt-mmcm 28_397 +CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[6] origin:031-cmt-mmcm 29_396 +CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[7] origin:031-cmt-mmcm 28_396 +CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[8] origin:031-cmt-mmcm 28_395 +CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[9] origin:031-cmt-mmcm 29_394 +CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[10] origin:031-cmt-mmcm 28_393 +CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG1_RESERVED[11] origin:031-cmt-mmcm 29_392 +CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[0] origin:031-cmt-mmcm 29_391 +CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[1] origin:031-cmt-mmcm 28_391 +CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[2] origin:031-cmt-mmcm 29_390 +CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[3] origin:031-cmt-mmcm 28_390 +CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[4] origin:031-cmt-mmcm 28_389 +CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[5] origin:031-cmt-mmcm 29_388 +CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[6] origin:031-cmt-mmcm 28_387 +CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[7] origin:031-cmt-mmcm 29_386 +CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[8] origin:031-cmt-mmcm 28_385 +CMT_TOP_R_LOWER_B.MMCME2_ADV.FILTREG2_RESERVED[9] origin:031-cmt-mmcm 29_384 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LOCKREG1_RESERVED[0] origin:031-cmt-mmcm 29_826 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LOCKREG1_RESERVED[1] origin:031-cmt-mmcm 28_826 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LOCKREG1_RESERVED[2] origin:031-cmt-mmcm 29_825 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LOCKREG1_RESERVED[3] origin:031-cmt-mmcm 28_825 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LOCKREG1_RESERVED[4] origin:031-cmt-mmcm 29_824 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LOCKREG1_RESERVED[5] origin:031-cmt-mmcm 28_824 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LOCKREG2_RESERVED[0] origin:031-cmt-mmcm 28_816 +CMT_TOP_R_LOWER_B.MMCME2_ADV.LOCKREG3_RESERVED[0] origin:031-cmt-mmcm 28_808 diff --git a/zynq7/segbits_cmt_top_r_upper_t.db b/zynq7/segbits_cmt_top_r_upper_t.db index 0e40593..eff93ea 100644 --- a/zynq7/segbits_cmt_top_r_upper_t.db +++ b/zynq7/segbits_cmt_top_r_upper_t.db @@ -21,346 +21,346 @@ CMT_TOP_R_UPPER_T.PLL_CLK_FREQ_BB0_NS_ACTIVE 29_00 29_09 29_17 CMT_TOP_R_UPPER_T.PLL_CLK_FREQ_BB1_NS_ACTIVE 28_01 29_10 29_18 CMT_TOP_R_UPPER_T.PLL_CLK_FREQ_BB2_NS_ACTIVE 29_01 29_11 29_19 CMT_TOP_R_UPPER_T.PLL_CLK_FREQ_BB3_NS_ACTIVE 28_02 29_12 29_20 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[0] 28_195 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[1] 29_195 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[2] 28_196 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[3] 29_196 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[4] 28_197 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[5] 29_197 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[0] 28_192 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[1] 29_192 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[2] 28_193 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[3] 29_193 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[4] 28_194 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[5] 29_194 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE[0] 28_198 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[0] 29_198 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[1] 28_199 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[2] 29_199 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[0] 28_200 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[1] 29_200 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[2] 28_201 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[3] 29_201 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[4] 28_202 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[5] 29_202 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_EDGE[0] 29_203 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[0] 28_206 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[1] 29_206 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[2] 28_207 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC_EN[0] 29_205 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC_WF_R[0] 28_205 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_MX[0] 28_204 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_MX[1] 29_204 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_NO_COUNT[0] 28_203 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_RESERVED[0] 29_207 -CMT_TOP_R_UPPER_T.PLLE2.COMPENSATION.Z_ZHOLD_OR_CLKIN_BUF 29_35 29_76 -CMT_TOP_R_UPPER_T.PLLE2.COMPENSATION.ZHOLD_NO_CLKIN_BUF 28_73 29_36 -CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_EDGE[0] 29_214 -CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[0] 28_211 -CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[1] 29_211 -CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[2] 28_212 -CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[3] 29_212 -CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[4] 28_213 -CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[5] 29_213 -CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[0] 28_208 -CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[1] 29_208 -CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[2] 28_209 -CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[3] 29_209 -CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[4] 28_210 -CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[5] 29_210 -CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_NO_COUNT[0] 28_214 -CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_RESERVED[0] 28_215 -CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_RESERVED[1] 29_215 -CMT_TOP_R_UPPER_T.PLLE2.IN_USE 28_37 28_48 28_74 28_78 28_216 28_219 28_222 28_266 28_280 28_283 28_284 28_592 28_622 28_623 28_624 28_627 28_628 28_768 28_785 28_786 28_787 28_788 28_790 28_791 28_792 28_793 28_795 28_796 28_797 28_798 28_799 28_803 28_806 28_807 28_811 28_812 28_815 28_816 28_817 28_818 28_819 28_821 28_822 28_823 28_824 28_826 28_827 28_828 28_829 28_832 28_835 28_838 28_841 28_845 28_847 29_48 29_77 29_78 29_79 29_268 29_281 29_282 29_283 29_563 29_567 29_589 29_621 29_622 29_625 29_626 29_627 29_785 29_786 29_788 29_790 29_791 29_793 29_797 29_798 29_800 29_809 29_811 29_812 29_813 29_814 29_815 29_816 29_817 29_819 29_823 29_824 29_825 29_826 29_827 29_829 29_830 29_831 29_832 29_835 29_836 29_838 29_839 29_840 29_841 29_842 29_845 -CMT_TOP_R_UPPER_T.PLLE2.INV_CLKINSEL 28_754 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[0] 28_232 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[1] 29_232 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[2] 28_233 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[3] 29_233 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[4] 28_234 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[5] 29_234 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[6] 28_235 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[7] 29_235 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[8] 28_236 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[9] 29_236 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[10] 28_240 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[11] 29_240 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[12] 28_241 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[13] 29_241 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[14] 28_242 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[15] 29_242 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[16] 28_243 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[17] 29_243 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[18] 28_244 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[19] 29_244 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[20] 28_224 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[21] 29_224 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[22] 28_225 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[23] 29_225 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[24] 28_226 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[25] 29_226 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[26] 28_227 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[27] 29_227 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[28] 28_228 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[29] 29_228 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[30] 28_237 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[31] 29_237 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[32] 28_238 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[33] 29_238 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[34] 28_239 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[35] 28_245 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[36] 29_245 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[37] 28_246 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[38] 29_246 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[39] 28_247 -CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[0] 28_352 -CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[1] 29_352 -CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[2] 28_353 -CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[3] 29_353 -CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[4] 28_354 -CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[5] 29_354 -CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[6] 28_355 -CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[7] 29_355 -CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[8] 28_356 -CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[9] 29_356 -CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[10] 28_357 -CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[11] 29_357 -CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[12] 28_358 -CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[13] 29_358 -CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[14] 28_359 -CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[15] 29_359 -CMT_TOP_R_UPPER_T.PLLE2.STARTUP_WAIT 28_769 -CMT_TOP_R_UPPER_T.PLLE2.TABLE[0] 28_666 -CMT_TOP_R_UPPER_T.PLLE2.TABLE[1] 29_667 -CMT_TOP_R_UPPER_T.PLLE2.TABLE[2] 28_668 -CMT_TOP_R_UPPER_T.PLLE2.TABLE[3] 29_669 -CMT_TOP_R_UPPER_T.PLLE2.TABLE[4] 28_670 -CMT_TOP_R_UPPER_T.PLLE2.TABLE[5] 29_671 -CMT_TOP_R_UPPER_T.PLLE2.TABLE[6] 28_660 -CMT_TOP_R_UPPER_T.PLLE2.TABLE[7] 29_661 -CMT_TOP_R_UPPER_T.PLLE2.TABLE[8] 28_662 -CMT_TOP_R_UPPER_T.PLLE2.TABLE[9] 29_663 -CMT_TOP_R_UPPER_T.PLLE2.ZINV_PWRDWN 29_752 -CMT_TOP_R_UPPER_T.PLLE2.ZINV_RST 28_752 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[0] 28_99 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[1] 29_99 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[2] 28_100 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[3] 29_100 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[4] 28_101 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[5] 29_101 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[0] 28_96 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[1] 29_96 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[2] 28_97 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[3] 29_97 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[4] 28_98 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[5] 29_98 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_OUTPUT_ENABLE[0] 28_102 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[0] 29_102 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[1] 28_103 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[2] 29_103 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[0] 28_104 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[1] 29_104 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[2] 28_105 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[3] 29_105 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[4] 28_106 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[5] 29_106 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_EDGE[0] 29_107 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[0] 28_110 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[1] 29_110 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[2] 28_111 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC_EN[0] 29_109 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC_WF_R[0] 28_109 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_MX[0] 28_108 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_MX[1] 29_108 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_NO_COUNT[0] 28_107 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_RESERVED[0] 29_111 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[0] 28_115 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[1] 29_115 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[2] 28_116 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[3] 29_116 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[4] 28_117 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[5] 29_117 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[0] 28_112 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[1] 29_112 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[2] 28_113 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[3] 29_113 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[4] 28_114 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[5] 29_114 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_OUTPUT_ENABLE[0] 28_118 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[0] 29_118 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[1] 28_119 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[2] 29_119 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[0] 28_120 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[1] 29_120 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[2] 28_121 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[3] 29_121 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[4] 28_122 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[5] 29_122 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_EDGE[0] 29_123 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[0] 28_126 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[1] 29_126 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[2] 28_127 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC_EN[0] 29_125 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC_WF_R[0] 28_125 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_MX[0] 28_124 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_MX[1] 29_124 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_NO_COUNT[0] 28_123 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_RESERVED[0] 29_127 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[0] 28_131 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[1] 29_131 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[2] 28_132 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[3] 29_132 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[4] 28_133 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[5] 29_133 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[0] 28_128 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[1] 29_128 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[2] 28_129 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[3] 29_129 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[4] 28_130 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[5] 29_130 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_OUTPUT_ENABLE[0] 28_134 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[0] 29_134 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[1] 28_135 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[2] 29_135 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[0] 28_136 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[1] 29_136 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[2] 28_137 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[3] 29_137 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[4] 28_138 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[5] 29_138 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_EDGE[0] 29_139 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[0] 28_142 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[1] 29_142 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[2] 28_143 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC_EN[0] 29_141 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC_WF_R[0] 28_141 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_MX[0] 28_140 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_MX[1] 29_140 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_NO_COUNT[0] 28_139 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_RESERVED[0] 29_143 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[0] 28_147 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[1] 29_147 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[2] 28_148 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[3] 29_148 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[4] 28_149 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[5] 29_149 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[0] 28_144 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[1] 29_144 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[2] 28_145 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[3] 29_145 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[4] 28_146 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[5] 29_146 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_OUTPUT_ENABLE[0] 28_150 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[0] 29_150 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[1] 28_151 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[2] 29_151 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[0] 28_152 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[1] 29_152 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[2] 28_153 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[3] 29_153 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[4] 28_154 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[5] 29_154 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_EDGE[0] 29_155 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[0] 28_158 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[1] 29_158 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[2] 28_159 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC_EN[0] 29_157 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC_WF_R[0] 28_157 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_MX[0] 28_156 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_MX[1] 29_156 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_NO_COUNT[0] 28_155 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_RESERVED[0] 29_159 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[0] 28_163 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[1] 29_163 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[2] 28_164 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[3] 29_164 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[4] 28_165 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[5] 29_165 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[0] 28_160 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[1] 29_160 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[2] 28_161 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[3] 29_161 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[4] 28_162 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[5] 29_162 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_OUTPUT_ENABLE[0] 28_166 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[0] 29_166 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[1] 28_167 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[2] 29_167 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[0] 28_168 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[1] 29_168 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[2] 28_169 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[3] 29_169 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[4] 28_170 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[5] 29_170 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_EDGE[0] 29_171 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[0] 28_174 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[1] 29_174 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[2] 28_175 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC_EN[0] 29_173 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC_WF_R[0] 28_173 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_MX[0] 28_172 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_MX[1] 29_172 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_NO_COUNT[0] 28_171 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_RESERVED[0] 29_175 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[0] 28_83 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[1] 29_83 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[2] 28_84 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[3] 29_84 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[4] 28_85 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[5] 29_85 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[0] 28_80 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[1] 29_80 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[2] 28_81 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[3] 29_81 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[4] 28_82 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[5] 29_82 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_OUTPUT_ENABLE[0] 28_86 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[0] 29_86 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[1] 28_87 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[2] 29_87 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[0] 28_88 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[1] 29_88 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[2] 28_89 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[3] 29_89 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[4] 28_90 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[5] 29_90 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_EDGE[0] 29_91 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[0] 28_94 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[1] 29_94 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[2] 28_95 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC_EN[0] 29_93 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC_WF_R[0] 28_93 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_MX[0] 28_92 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_MX[1] 29_92 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_NO_COUNT[0] 28_91 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_RESERVED[0] 29_95 -CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[0] 28_656 -CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[1] 29_656 -CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[2] 28_657 -CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[3] 29_657 -CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[4] 28_658 -CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[5] 29_658 -CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[6] 28_659 -CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[7] 29_659 -CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[8] 29_660 -CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[9] 28_661 -CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[10] 29_662 -CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[11] 28_663 -CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[0] 28_664 -CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[1] 29_664 -CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[2] 28_665 -CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[3] 29_665 -CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[4] 29_666 -CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[5] 28_667 -CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[6] 29_668 -CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[7] 28_669 -CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[8] 29_670 -CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[9] 28_671 -CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[0] 28_229 -CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[1] 29_229 -CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[2] 28_230 -CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[3] 29_230 -CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[4] 28_231 -CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[5] 29_231 -CMT_TOP_R_UPPER_T.PLLE2.LOCKREG2_RESERVED[0] 29_239 -CMT_TOP_R_UPPER_T.PLLE2.LOCKREG3_RESERVED[0] 29_247 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[0] 28_195 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[1] 29_195 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[2] 28_196 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[3] 29_196 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[4] 28_197 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[5] 29_197 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[0] 28_192 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[1] 29_192 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[2] 28_193 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[3] 29_193 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[4] 28_194 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[5] 29_194 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE[0] 28_198 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_PHASE_MUX[0] 29_198 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_PHASE_MUX[1] 28_199 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_PHASE_MUX[2] 29_199 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[0] 28_200 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[1] 29_200 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[2] 28_201 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[3] 29_201 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[4] 28_202 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[5] 29_202 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_EDGE[0] 29_203 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_FRAC[0] 28_206 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_FRAC[1] 29_206 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_FRAC[2] 28_207 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_FRAC_EN[0] 29_205 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_FRAC_WF_R[0] 28_205 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_MX[0] 28_204 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_MX[1] 29_204 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_NO_COUNT[0] 28_203 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_RESERVED[0] 29_207 +CMT_TOP_R_UPPER_T.PLLE2_ADV.COMPENSATION.Z_ZHOLD_OR_CLKIN_BUF 29_35 29_76 +CMT_TOP_R_UPPER_T.PLLE2_ADV.COMPENSATION.ZHOLD_NO_CLKIN_BUF 28_73 29_36 +CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_EDGE[0] 29_214 +CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_HIGH_TIME[0] 28_211 +CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_HIGH_TIME[1] 29_211 +CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_HIGH_TIME[2] 28_212 +CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_HIGH_TIME[3] 29_212 +CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_HIGH_TIME[4] 28_213 +CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_HIGH_TIME[5] 29_213 +CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_LOW_TIME[0] 28_208 +CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_LOW_TIME[1] 29_208 +CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_LOW_TIME[2] 28_209 +CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_LOW_TIME[3] 29_209 +CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_LOW_TIME[4] 28_210 +CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_LOW_TIME[5] 29_210 +CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_NO_COUNT[0] 28_214 +CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_RESERVED[0] 28_215 +CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_RESERVED[1] 29_215 +CMT_TOP_R_UPPER_T.PLLE2_ADV.IN_USE 28_37 28_48 28_74 28_78 28_216 28_219 28_222 28_266 28_280 28_283 28_284 28_592 28_622 28_623 28_624 28_627 28_628 28_768 28_785 28_786 28_787 28_788 28_790 28_791 28_792 28_793 28_795 28_796 28_797 28_798 28_799 28_803 28_806 28_807 28_811 28_812 28_815 28_816 28_817 28_818 28_819 28_821 28_822 28_823 28_824 28_826 28_827 28_828 28_829 28_832 28_835 28_838 28_841 28_845 28_847 29_48 29_77 29_78 29_79 29_268 29_281 29_282 29_283 29_563 29_567 29_589 29_621 29_622 29_625 29_626 29_627 29_785 29_786 29_788 29_790 29_791 29_793 29_797 29_798 29_800 29_809 29_811 29_812 29_813 29_814 29_815 29_816 29_817 29_819 29_823 29_824 29_825 29_826 29_827 29_829 29_830 29_831 29_832 29_835 29_836 29_838 29_839 29_840 29_841 29_842 29_845 +CMT_TOP_R_UPPER_T.PLLE2_ADV.INV_CLKINSEL 28_754 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[0] 28_232 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[1] 29_232 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[2] 28_233 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[3] 29_233 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[4] 28_234 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[5] 29_234 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[6] 28_235 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[7] 29_235 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[8] 28_236 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[9] 29_236 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[10] 28_240 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[11] 29_240 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[12] 28_241 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[13] 29_241 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[14] 28_242 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[15] 29_242 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[16] 28_243 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[17] 29_243 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[18] 28_244 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[19] 29_244 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[20] 28_224 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[21] 29_224 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[22] 28_225 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[23] 29_225 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[24] 28_226 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[25] 29_226 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[26] 28_227 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[27] 29_227 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[28] 28_228 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[29] 29_228 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[30] 28_237 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[31] 29_237 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[32] 28_238 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[33] 29_238 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[34] 28_239 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[35] 28_245 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[36] 29_245 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[37] 28_246 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[38] 29_246 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[39] 28_247 +CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[0] 28_352 +CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[1] 29_352 +CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[2] 28_353 +CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[3] 29_353 +CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[4] 28_354 +CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[5] 29_354 +CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[6] 28_355 +CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[7] 29_355 +CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[8] 28_356 +CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[9] 29_356 +CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[10] 28_357 +CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[11] 29_357 +CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[12] 28_358 +CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[13] 29_358 +CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[14] 28_359 +CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[15] 29_359 +CMT_TOP_R_UPPER_T.PLLE2_ADV.STARTUP_WAIT 28_769 +CMT_TOP_R_UPPER_T.PLLE2_ADV.TABLE[0] 28_666 +CMT_TOP_R_UPPER_T.PLLE2_ADV.TABLE[1] 29_667 +CMT_TOP_R_UPPER_T.PLLE2_ADV.TABLE[2] 28_668 +CMT_TOP_R_UPPER_T.PLLE2_ADV.TABLE[3] 29_669 +CMT_TOP_R_UPPER_T.PLLE2_ADV.TABLE[4] 28_670 +CMT_TOP_R_UPPER_T.PLLE2_ADV.TABLE[5] 29_671 +CMT_TOP_R_UPPER_T.PLLE2_ADV.TABLE[6] 28_660 +CMT_TOP_R_UPPER_T.PLLE2_ADV.TABLE[7] 29_661 +CMT_TOP_R_UPPER_T.PLLE2_ADV.TABLE[8] 28_662 +CMT_TOP_R_UPPER_T.PLLE2_ADV.TABLE[9] 29_663 +CMT_TOP_R_UPPER_T.PLLE2_ADV.ZINV_PWRDWN 29_752 +CMT_TOP_R_UPPER_T.PLLE2_ADV.ZINV_RST 28_752 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[0] 28_99 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[1] 29_99 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[2] 28_100 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[3] 29_100 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[4] 28_101 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[5] 29_101 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[0] 28_96 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[1] 29_96 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[2] 28_97 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[3] 29_97 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[4] 28_98 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[5] 29_98 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_OUTPUT_ENABLE[0] 28_102 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_PHASE_MUX[0] 29_102 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_PHASE_MUX[1] 28_103 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_PHASE_MUX[2] 29_103 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[0] 28_104 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[1] 29_104 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[2] 28_105 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[3] 29_105 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[4] 28_106 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[5] 29_106 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_EDGE[0] 29_107 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_FRAC[0] 28_110 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_FRAC[1] 29_110 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_FRAC[2] 28_111 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_FRAC_EN[0] 29_109 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_FRAC_WF_R[0] 28_109 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_MX[0] 28_108 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_MX[1] 29_108 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_NO_COUNT[0] 28_107 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_RESERVED[0] 29_111 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[0] 28_115 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[1] 29_115 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[2] 28_116 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[3] 29_116 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[4] 28_117 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[5] 29_117 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[0] 28_112 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[1] 29_112 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[2] 28_113 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[3] 29_113 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[4] 28_114 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[5] 29_114 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_OUTPUT_ENABLE[0] 28_118 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_PHASE_MUX[0] 29_118 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_PHASE_MUX[1] 28_119 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_PHASE_MUX[2] 29_119 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[0] 28_120 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[1] 29_120 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[2] 28_121 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[3] 29_121 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[4] 28_122 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[5] 29_122 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_EDGE[0] 29_123 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_FRAC[0] 28_126 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_FRAC[1] 29_126 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_FRAC[2] 28_127 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_FRAC_EN[0] 29_125 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_FRAC_WF_R[0] 28_125 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_MX[0] 28_124 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_MX[1] 29_124 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_NO_COUNT[0] 28_123 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_RESERVED[0] 29_127 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[0] 28_131 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[1] 29_131 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[2] 28_132 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[3] 29_132 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[4] 28_133 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[5] 29_133 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[0] 28_128 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[1] 29_128 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[2] 28_129 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[3] 29_129 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[4] 28_130 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[5] 29_130 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_OUTPUT_ENABLE[0] 28_134 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_PHASE_MUX[0] 29_134 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_PHASE_MUX[1] 28_135 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_PHASE_MUX[2] 29_135 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[0] 28_136 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[1] 29_136 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[2] 28_137 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[3] 29_137 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[4] 28_138 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[5] 29_138 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_EDGE[0] 29_139 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_FRAC[0] 28_142 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_FRAC[1] 29_142 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_FRAC[2] 28_143 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_FRAC_EN[0] 29_141 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_FRAC_WF_R[0] 28_141 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_MX[0] 28_140 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_MX[1] 29_140 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_NO_COUNT[0] 28_139 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_RESERVED[0] 29_143 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[0] 28_147 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[1] 29_147 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[2] 28_148 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[3] 29_148 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[4] 28_149 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[5] 29_149 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[0] 28_144 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[1] 29_144 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[2] 28_145 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[3] 29_145 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[4] 28_146 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[5] 29_146 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_OUTPUT_ENABLE[0] 28_150 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_PHASE_MUX[0] 29_150 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_PHASE_MUX[1] 28_151 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_PHASE_MUX[2] 29_151 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[0] 28_152 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[1] 29_152 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[2] 28_153 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[3] 29_153 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[4] 28_154 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[5] 29_154 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_EDGE[0] 29_155 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_FRAC[0] 28_158 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_FRAC[1] 29_158 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_FRAC[2] 28_159 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_FRAC_EN[0] 29_157 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_FRAC_WF_R[0] 28_157 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_MX[0] 28_156 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_MX[1] 29_156 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_NO_COUNT[0] 28_155 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_RESERVED[0] 29_159 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[0] 28_163 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[1] 29_163 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[2] 28_164 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[3] 29_164 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[4] 28_165 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[5] 29_165 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[0] 28_160 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[1] 29_160 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[2] 28_161 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[3] 29_161 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[4] 28_162 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[5] 29_162 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_OUTPUT_ENABLE[0] 28_166 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_PHASE_MUX[0] 29_166 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_PHASE_MUX[1] 28_167 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_PHASE_MUX[2] 29_167 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[0] 28_168 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[1] 29_168 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[2] 28_169 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[3] 29_169 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[4] 28_170 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[5] 29_170 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_EDGE[0] 29_171 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_FRAC[0] 28_174 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_FRAC[1] 29_174 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_FRAC[2] 28_175 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_FRAC_EN[0] 29_173 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_FRAC_WF_R[0] 28_173 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_MX[0] 28_172 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_MX[1] 29_172 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_NO_COUNT[0] 28_171 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_RESERVED[0] 29_175 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[0] 28_83 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[1] 29_83 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[2] 28_84 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[3] 29_84 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[4] 28_85 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[5] 29_85 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[0] 28_80 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[1] 29_80 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[2] 28_81 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[3] 29_81 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[4] 28_82 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[5] 29_82 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_OUTPUT_ENABLE[0] 28_86 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_PHASE_MUX[0] 29_86 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_PHASE_MUX[1] 28_87 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_PHASE_MUX[2] 29_87 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_DELAY_TIME[0] 28_88 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_DELAY_TIME[1] 29_88 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_DELAY_TIME[2] 28_89 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_DELAY_TIME[3] 29_89 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_DELAY_TIME[4] 28_90 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_DELAY_TIME[5] 29_90 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_EDGE[0] 29_91 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_FRAC[0] 28_94 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_FRAC[1] 29_94 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_FRAC[2] 28_95 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_FRAC_EN[0] 29_93 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_FRAC_WF_R[0] 28_93 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_MX[0] 28_92 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_MX[1] 29_92 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_NO_COUNT[0] 28_91 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_RESERVED[0] 29_95 +CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[0] 28_656 +CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[1] 29_656 +CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[2] 28_657 +CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[3] 29_657 +CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[4] 28_658 +CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[5] 29_658 +CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[6] 28_659 +CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[7] 29_659 +CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[8] 29_660 +CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[9] 28_661 +CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[10] 29_662 +CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[11] 28_663 +CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[0] 28_664 +CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[1] 29_664 +CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[2] 28_665 +CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[3] 29_665 +CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[4] 29_666 +CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[5] 28_667 +CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[6] 29_668 +CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[7] 28_669 +CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[8] 29_670 +CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[9] 28_671 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LOCKREG1_RESERVED[0] 28_229 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LOCKREG1_RESERVED[1] 29_229 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LOCKREG1_RESERVED[2] 28_230 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LOCKREG1_RESERVED[3] 29_230 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LOCKREG1_RESERVED[4] 28_231 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LOCKREG1_RESERVED[5] 29_231 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LOCKREG2_RESERVED[0] 29_239 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LOCKREG3_RESERVED[0] 29_247 diff --git a/zynq7/segbits_cmt_top_r_upper_t.origin_info.db b/zynq7/segbits_cmt_top_r_upper_t.origin_info.db index 6ee0558..7a858c2 100644 --- a/zynq7/segbits_cmt_top_r_upper_t.origin_info.db +++ b/zynq7/segbits_cmt_top_r_upper_t.origin_info.db @@ -21,346 +21,346 @@ CMT_TOP_R_UPPER_T.PLL_CLK_FREQ_BB0_NS_ACTIVE origin:034-cmt-pll-pips 29_00 29_09 CMT_TOP_R_UPPER_T.PLL_CLK_FREQ_BB1_NS_ACTIVE origin:034-cmt-pll-pips 28_01 29_10 29_18 CMT_TOP_R_UPPER_T.PLL_CLK_FREQ_BB2_NS_ACTIVE origin:034-cmt-pll-pips 29_01 29_11 29_19 CMT_TOP_R_UPPER_T.PLL_CLK_FREQ_BB3_NS_ACTIVE origin:034-cmt-pll-pips 28_02 29_12 29_20 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_195 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_195 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_196 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_196 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_197 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_197 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_192 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_192 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_193 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_193 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_194 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_194 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_198 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_198 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_199 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_199 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_200 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_200 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_201 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_201 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_202 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_202 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_203 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_206 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_206 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_207 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_205 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_205 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_MX[0] origin:032-cmt-pll 28_204 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_MX[1] origin:032-cmt-pll 29_204 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_203 -CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_207 -CMT_TOP_R_UPPER_T.PLLE2.COMPENSATION.Z_ZHOLD_OR_CLKIN_BUF origin:032-cmt-pll 29_35 29_76 -CMT_TOP_R_UPPER_T.PLLE2.COMPENSATION.ZHOLD_NO_CLKIN_BUF origin:032-cmt-pll 28_73 29_36 -CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_EDGE[0] origin:032-cmt-pll 29_214 -CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[0] origin:032-cmt-pll 28_211 -CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[1] origin:032-cmt-pll 29_211 -CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[2] origin:032-cmt-pll 28_212 -CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[3] origin:032-cmt-pll 29_212 -CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[4] origin:032-cmt-pll 28_213 -CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[5] origin:032-cmt-pll 29_213 -CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[0] origin:032-cmt-pll 28_208 -CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[1] origin:032-cmt-pll 29_208 -CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[2] origin:032-cmt-pll 28_209 -CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[3] origin:032-cmt-pll 29_209 -CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[4] origin:032-cmt-pll 28_210 -CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[5] origin:032-cmt-pll 29_210 -CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_NO_COUNT[0] origin:032-cmt-pll 28_214 -CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_RESERVED[0] origin:032-cmt-pll 28_215 -CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_RESERVED[1] origin:032-cmt-pll 29_215 -CMT_TOP_R_UPPER_T.PLLE2.IN_USE origin:032-cmt-pll 28_216 28_219 28_222 28_266 28_280 28_283 28_284 28_37 28_48 28_592 28_622 28_623 28_624 28_627 28_628 28_74 28_768 28_78 28_785 28_786 28_787 28_788 28_790 28_791 28_792 28_793 28_795 28_796 28_797 28_798 28_799 28_803 28_806 28_807 28_811 28_812 28_815 28_816 28_817 28_818 28_819 28_821 28_822 28_823 28_824 28_826 28_827 28_828 28_829 28_832 28_835 28_838 28_841 28_845 28_847 29_268 29_281 29_282 29_283 29_48 29_563 29_567 29_589 29_621 29_622 29_625 29_626 29_627 29_77 29_78 29_785 29_786 29_788 29_79 29_790 29_791 29_793 29_797 29_798 29_800 29_809 29_811 29_812 29_813 29_814 29_815 29_816 29_817 29_819 29_823 29_824 29_825 29_826 29_827 29_829 29_830 29_831 29_832 29_835 29_836 29_838 29_839 29_840 29_841 29_842 29_845 -CMT_TOP_R_UPPER_T.PLLE2.INV_CLKINSEL origin:032-cmt-pll 28_754 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[0] origin:032-cmt-pll 28_232 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[1] origin:032-cmt-pll 29_232 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[2] origin:032-cmt-pll 28_233 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[3] origin:032-cmt-pll 29_233 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[4] origin:032-cmt-pll 28_234 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[5] origin:032-cmt-pll 29_234 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[6] origin:032-cmt-pll 28_235 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[7] origin:032-cmt-pll 29_235 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[8] origin:032-cmt-pll 28_236 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[9] origin:032-cmt-pll 29_236 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[10] origin:032-cmt-pll 28_240 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[11] origin:032-cmt-pll 29_240 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[12] origin:032-cmt-pll 28_241 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[13] origin:032-cmt-pll 29_241 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[14] origin:032-cmt-pll 28_242 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[15] origin:032-cmt-pll 29_242 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[16] origin:032-cmt-pll 28_243 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[17] origin:032-cmt-pll 29_243 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[18] origin:032-cmt-pll 28_244 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[19] origin:032-cmt-pll 29_244 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[20] origin:032-cmt-pll 28_224 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[21] origin:032-cmt-pll 29_224 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[22] origin:032-cmt-pll 28_225 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[23] origin:032-cmt-pll 29_225 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[24] origin:032-cmt-pll 28_226 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[25] origin:032-cmt-pll 29_226 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[26] origin:032-cmt-pll 28_227 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[27] origin:032-cmt-pll 29_227 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[28] origin:032-cmt-pll 28_228 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[29] origin:032-cmt-pll 29_228 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[30] origin:032-cmt-pll 28_237 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[31] origin:032-cmt-pll 29_237 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[32] origin:032-cmt-pll 28_238 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[33] origin:032-cmt-pll 29_238 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[34] origin:032-cmt-pll 28_239 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[35] origin:032-cmt-pll 28_245 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[36] origin:032-cmt-pll 29_245 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[37] origin:032-cmt-pll 28_246 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[38] origin:032-cmt-pll 29_246 -CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[39] origin:032-cmt-pll 28_247 -CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[0] origin:032-cmt-pll 28_352 -CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[1] origin:032-cmt-pll 29_352 -CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[2] origin:032-cmt-pll 28_353 -CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[3] origin:032-cmt-pll 29_353 -CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[4] origin:032-cmt-pll 28_354 -CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[5] origin:032-cmt-pll 29_354 -CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[6] origin:032-cmt-pll 28_355 -CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[7] origin:032-cmt-pll 29_355 -CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[8] origin:032-cmt-pll 28_356 -CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[9] origin:032-cmt-pll 29_356 -CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[10] origin:032-cmt-pll 28_357 -CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[11] origin:032-cmt-pll 29_357 -CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[12] origin:032-cmt-pll 28_358 -CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[13] origin:032-cmt-pll 29_358 -CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[14] origin:032-cmt-pll 28_359 -CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[15] origin:032-cmt-pll 29_359 -CMT_TOP_R_UPPER_T.PLLE2.STARTUP_WAIT origin:032-cmt-pll 28_769 -CMT_TOP_R_UPPER_T.PLLE2.TABLE[0] origin:032-cmt-pll 28_666 -CMT_TOP_R_UPPER_T.PLLE2.TABLE[1] origin:032-cmt-pll 29_667 -CMT_TOP_R_UPPER_T.PLLE2.TABLE[2] origin:032-cmt-pll 28_668 -CMT_TOP_R_UPPER_T.PLLE2.TABLE[3] origin:032-cmt-pll 29_669 -CMT_TOP_R_UPPER_T.PLLE2.TABLE[4] origin:032-cmt-pll 28_670 -CMT_TOP_R_UPPER_T.PLLE2.TABLE[5] origin:032-cmt-pll 29_671 -CMT_TOP_R_UPPER_T.PLLE2.TABLE[6] origin:032-cmt-pll 28_660 -CMT_TOP_R_UPPER_T.PLLE2.TABLE[7] origin:032-cmt-pll 29_661 -CMT_TOP_R_UPPER_T.PLLE2.TABLE[8] origin:032-cmt-pll 28_662 -CMT_TOP_R_UPPER_T.PLLE2.TABLE[9] origin:032-cmt-pll 29_663 -CMT_TOP_R_UPPER_T.PLLE2.ZINV_PWRDWN origin:032-cmt-pll 29_752 -CMT_TOP_R_UPPER_T.PLLE2.ZINV_RST origin:032-cmt-pll 28_752 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_99 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_99 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_100 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_100 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_101 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_101 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_96 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_96 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_97 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_97 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_98 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_98 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_102 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_102 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_103 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_103 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_104 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_104 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_105 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_105 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_106 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_106 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_107 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_110 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_110 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_111 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_109 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_109 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_MX[0] origin:032-cmt-pll 28_108 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_MX[1] origin:032-cmt-pll 29_108 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_107 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_111 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_115 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_115 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_116 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_116 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_117 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_117 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_112 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_112 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_113 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_113 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_114 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_114 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_118 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_118 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_119 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_119 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_120 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_120 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_121 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_121 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_122 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_122 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_123 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_126 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_126 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_127 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_125 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_125 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_MX[0] origin:032-cmt-pll 28_124 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_MX[1] origin:032-cmt-pll 29_124 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_123 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_127 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_131 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_131 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_132 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_132 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_133 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_133 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_128 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_128 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_129 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_129 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_130 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_130 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_134 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_134 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_135 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_135 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_136 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_136 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_137 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_137 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_138 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_138 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_139 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_142 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_142 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_143 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_141 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_141 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_MX[0] origin:032-cmt-pll 28_140 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_MX[1] origin:032-cmt-pll 29_140 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_139 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_143 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_147 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_147 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_148 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_148 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_149 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_149 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_144 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_144 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_145 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_145 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_146 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_146 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_150 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_150 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_151 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_151 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_152 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_152 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_153 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_153 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_154 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_154 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_155 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_158 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_158 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_159 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_157 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_157 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_MX[0] origin:032-cmt-pll 28_156 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_MX[1] origin:032-cmt-pll 29_156 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_155 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_159 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_163 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_163 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_164 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_164 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_165 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_165 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_160 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_160 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_161 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_161 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_162 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_162 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_166 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_166 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_167 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_167 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_168 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_168 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_169 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_169 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_170 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_170 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_171 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_174 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_174 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_175 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_173 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_173 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_MX[0] origin:032-cmt-pll 28_172 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_MX[1] origin:032-cmt-pll 29_172 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_171 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_175 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_83 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_83 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_84 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_84 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_85 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_85 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_80 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_80 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_81 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_81 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_82 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_82 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_86 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_86 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_87 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_87 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_88 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_88 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_89 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_89 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_90 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_90 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_91 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_94 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_94 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_95 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_93 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_93 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_MX[0] origin:032-cmt-pll 28_92 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_MX[1] origin:032-cmt-pll 29_92 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_91 -CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_95 -CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[0] origin:032-cmt-pll 28_656 -CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[1] origin:032-cmt-pll 29_656 -CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[2] origin:032-cmt-pll 28_657 -CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[3] origin:032-cmt-pll 29_657 -CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[4] origin:032-cmt-pll 28_658 -CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[5] origin:032-cmt-pll 29_658 -CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[6] origin:032-cmt-pll 28_659 -CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[7] origin:032-cmt-pll 29_659 -CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[8] origin:032-cmt-pll 29_660 -CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[9] origin:032-cmt-pll 28_661 -CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[10] origin:032-cmt-pll 29_662 -CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[11] origin:032-cmt-pll 28_663 -CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[0] origin:032-cmt-pll 28_664 -CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[1] origin:032-cmt-pll 29_664 -CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[2] origin:032-cmt-pll 28_665 -CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[3] origin:032-cmt-pll 29_665 -CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[4] origin:032-cmt-pll 29_666 -CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[5] origin:032-cmt-pll 28_667 -CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[6] origin:032-cmt-pll 29_668 -CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[7] origin:032-cmt-pll 28_669 -CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[8] origin:032-cmt-pll 29_670 -CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[9] origin:032-cmt-pll 28_671 -CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[0] origin:032-cmt-pll 28_229 -CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[1] origin:032-cmt-pll 29_229 -CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[2] origin:032-cmt-pll 28_230 -CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[3] origin:032-cmt-pll 29_230 -CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[4] origin:032-cmt-pll 28_231 -CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[5] origin:032-cmt-pll 29_231 -CMT_TOP_R_UPPER_T.PLLE2.LOCKREG2_RESERVED[0] origin:032-cmt-pll 29_239 -CMT_TOP_R_UPPER_T.PLLE2.LOCKREG3_RESERVED[0] origin:032-cmt-pll 29_247 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_195 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_195 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_196 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_196 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_197 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_197 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_192 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_192 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_193 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_193 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_194 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_194 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_198 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_198 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_199 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_199 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_200 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_200 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_201 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_201 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_202 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_202 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_203 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_206 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_206 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_207 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_205 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_205 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_MX[0] origin:032-cmt-pll 28_204 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_MX[1] origin:032-cmt-pll 29_204 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_203 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKFBOUT_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_207 +CMT_TOP_R_UPPER_T.PLLE2_ADV.COMPENSATION.Z_ZHOLD_OR_CLKIN_BUF origin:032-cmt-pll 29_35 29_76 +CMT_TOP_R_UPPER_T.PLLE2_ADV.COMPENSATION.ZHOLD_NO_CLKIN_BUF origin:032-cmt-pll 28_73 29_36 +CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_EDGE[0] origin:032-cmt-pll 29_214 +CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_HIGH_TIME[0] origin:032-cmt-pll 28_211 +CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_HIGH_TIME[1] origin:032-cmt-pll 29_211 +CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_HIGH_TIME[2] origin:032-cmt-pll 28_212 +CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_HIGH_TIME[3] origin:032-cmt-pll 29_212 +CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_HIGH_TIME[4] origin:032-cmt-pll 28_213 +CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_HIGH_TIME[5] origin:032-cmt-pll 29_213 +CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_LOW_TIME[0] origin:032-cmt-pll 28_208 +CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_LOW_TIME[1] origin:032-cmt-pll 29_208 +CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_LOW_TIME[2] origin:032-cmt-pll 28_209 +CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_LOW_TIME[3] origin:032-cmt-pll 29_209 +CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_LOW_TIME[4] origin:032-cmt-pll 28_210 +CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_LOW_TIME[5] origin:032-cmt-pll 29_210 +CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_NO_COUNT[0] origin:032-cmt-pll 28_214 +CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_RESERVED[0] origin:032-cmt-pll 28_215 +CMT_TOP_R_UPPER_T.PLLE2_ADV.DIVCLK_DIVCLK_RESERVED[1] origin:032-cmt-pll 29_215 +CMT_TOP_R_UPPER_T.PLLE2_ADV.IN_USE origin:032-cmt-pll 28_216 28_219 28_222 28_266 28_280 28_283 28_284 28_37 28_48 28_592 28_622 28_623 28_624 28_627 28_628 28_74 28_768 28_78 28_785 28_786 28_787 28_788 28_790 28_791 28_792 28_793 28_795 28_796 28_797 28_798 28_799 28_803 28_806 28_807 28_811 28_812 28_815 28_816 28_817 28_818 28_819 28_821 28_822 28_823 28_824 28_826 28_827 28_828 28_829 28_832 28_835 28_838 28_841 28_845 28_847 29_268 29_281 29_282 29_283 29_48 29_563 29_567 29_589 29_621 29_622 29_625 29_626 29_627 29_77 29_78 29_785 29_786 29_788 29_79 29_790 29_791 29_793 29_797 29_798 29_800 29_809 29_811 29_812 29_813 29_814 29_815 29_816 29_817 29_819 29_823 29_824 29_825 29_826 29_827 29_829 29_830 29_831 29_832 29_835 29_836 29_838 29_839 29_840 29_841 29_842 29_845 +CMT_TOP_R_UPPER_T.PLLE2_ADV.INV_CLKINSEL origin:032-cmt-pll 28_754 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[0] origin:032-cmt-pll 28_232 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[1] origin:032-cmt-pll 29_232 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[2] origin:032-cmt-pll 28_233 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[3] origin:032-cmt-pll 29_233 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[4] origin:032-cmt-pll 28_234 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[5] origin:032-cmt-pll 29_234 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[6] origin:032-cmt-pll 28_235 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[7] origin:032-cmt-pll 29_235 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[8] origin:032-cmt-pll 28_236 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[9] origin:032-cmt-pll 29_236 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[10] origin:032-cmt-pll 28_240 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[11] origin:032-cmt-pll 29_240 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[12] origin:032-cmt-pll 28_241 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[13] origin:032-cmt-pll 29_241 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[14] origin:032-cmt-pll 28_242 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[15] origin:032-cmt-pll 29_242 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[16] origin:032-cmt-pll 28_243 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[17] origin:032-cmt-pll 29_243 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[18] origin:032-cmt-pll 28_244 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[19] origin:032-cmt-pll 29_244 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[20] origin:032-cmt-pll 28_224 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[21] origin:032-cmt-pll 29_224 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[22] origin:032-cmt-pll 28_225 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[23] origin:032-cmt-pll 29_225 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[24] origin:032-cmt-pll 28_226 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[25] origin:032-cmt-pll 29_226 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[26] origin:032-cmt-pll 28_227 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[27] origin:032-cmt-pll 29_227 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[28] origin:032-cmt-pll 28_228 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[29] origin:032-cmt-pll 29_228 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[30] origin:032-cmt-pll 28_237 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[31] origin:032-cmt-pll 29_237 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[32] origin:032-cmt-pll 28_238 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[33] origin:032-cmt-pll 29_238 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[34] origin:032-cmt-pll 28_239 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[35] origin:032-cmt-pll 28_245 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[36] origin:032-cmt-pll 29_245 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[37] origin:032-cmt-pll 28_246 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[38] origin:032-cmt-pll 29_246 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LKTABLE[39] origin:032-cmt-pll 28_247 +CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[0] origin:032-cmt-pll 28_352 +CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[1] origin:032-cmt-pll 29_352 +CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[2] origin:032-cmt-pll 28_353 +CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[3] origin:032-cmt-pll 29_353 +CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[4] origin:032-cmt-pll 28_354 +CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[5] origin:032-cmt-pll 29_354 +CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[6] origin:032-cmt-pll 28_355 +CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[7] origin:032-cmt-pll 29_355 +CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[8] origin:032-cmt-pll 28_356 +CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[9] origin:032-cmt-pll 29_356 +CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[10] origin:032-cmt-pll 28_357 +CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[11] origin:032-cmt-pll 29_357 +CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[12] origin:032-cmt-pll 28_358 +CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[13] origin:032-cmt-pll 29_358 +CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[14] origin:032-cmt-pll 28_359 +CMT_TOP_R_UPPER_T.PLLE2_ADV.POWER_REG_POWER_REG_POWER_REG[15] origin:032-cmt-pll 29_359 +CMT_TOP_R_UPPER_T.PLLE2_ADV.STARTUP_WAIT origin:032-cmt-pll 28_769 +CMT_TOP_R_UPPER_T.PLLE2_ADV.TABLE[0] origin:032-cmt-pll 28_666 +CMT_TOP_R_UPPER_T.PLLE2_ADV.TABLE[1] origin:032-cmt-pll 29_667 +CMT_TOP_R_UPPER_T.PLLE2_ADV.TABLE[2] origin:032-cmt-pll 28_668 +CMT_TOP_R_UPPER_T.PLLE2_ADV.TABLE[3] origin:032-cmt-pll 29_669 +CMT_TOP_R_UPPER_T.PLLE2_ADV.TABLE[4] origin:032-cmt-pll 28_670 +CMT_TOP_R_UPPER_T.PLLE2_ADV.TABLE[5] origin:032-cmt-pll 29_671 +CMT_TOP_R_UPPER_T.PLLE2_ADV.TABLE[6] origin:032-cmt-pll 28_660 +CMT_TOP_R_UPPER_T.PLLE2_ADV.TABLE[7] origin:032-cmt-pll 29_661 +CMT_TOP_R_UPPER_T.PLLE2_ADV.TABLE[8] origin:032-cmt-pll 28_662 +CMT_TOP_R_UPPER_T.PLLE2_ADV.TABLE[9] origin:032-cmt-pll 29_663 +CMT_TOP_R_UPPER_T.PLLE2_ADV.ZINV_PWRDWN origin:032-cmt-pll 29_752 +CMT_TOP_R_UPPER_T.PLLE2_ADV.ZINV_RST origin:032-cmt-pll 28_752 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_99 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_99 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_100 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_100 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_101 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_101 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_96 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_96 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_97 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_97 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_98 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_98 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_102 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_102 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_103 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_103 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_104 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_104 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_105 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_105 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_106 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_106 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_107 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_110 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_110 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_111 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_109 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_109 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_MX[0] origin:032-cmt-pll 28_108 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_MX[1] origin:032-cmt-pll 29_108 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_107 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT0_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_111 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_115 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_115 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_116 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_116 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_117 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_117 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_112 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_112 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_113 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_113 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_114 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_114 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_118 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_118 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_119 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_119 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_120 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_120 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_121 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_121 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_122 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_122 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_123 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_126 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_126 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_127 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_125 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_125 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_MX[0] origin:032-cmt-pll 28_124 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_MX[1] origin:032-cmt-pll 29_124 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_123 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT1_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_127 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_131 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_131 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_132 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_132 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_133 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_133 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_128 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_128 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_129 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_129 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_130 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_130 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_134 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_134 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_135 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_135 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_136 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_136 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_137 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_137 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_138 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_138 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_139 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_142 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_142 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_143 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_141 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_141 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_MX[0] origin:032-cmt-pll 28_140 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_MX[1] origin:032-cmt-pll 29_140 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_139 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT2_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_143 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_147 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_147 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_148 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_148 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_149 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_149 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_144 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_144 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_145 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_145 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_146 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_146 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_150 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_150 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_151 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_151 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_152 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_152 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_153 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_153 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_154 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_154 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_155 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_158 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_158 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_159 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_157 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_157 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_MX[0] origin:032-cmt-pll 28_156 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_MX[1] origin:032-cmt-pll 29_156 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_155 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT3_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_159 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_163 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_163 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_164 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_164 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_165 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_165 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_160 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_160 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_161 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_161 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_162 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_162 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_166 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_166 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_167 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_167 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_168 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_168 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_169 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_169 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_170 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_170 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_171 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_174 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_174 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_175 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_173 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_173 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_MX[0] origin:032-cmt-pll 28_172 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_MX[1] origin:032-cmt-pll 29_172 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_171 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT4_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_175 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_83 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_83 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_84 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_84 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_85 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_85 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_80 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_80 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_81 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_81 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_82 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_82 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_86 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_86 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_87 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_87 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_88 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_88 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_89 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_89 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_90 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_90 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_91 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_94 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_94 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_95 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_93 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_93 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_MX[0] origin:032-cmt-pll 28_92 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_MX[1] origin:032-cmt-pll 29_92 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_91 +CMT_TOP_R_UPPER_T.PLLE2_ADV.CLKOUT5_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_95 +CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[0] origin:032-cmt-pll 28_656 +CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[1] origin:032-cmt-pll 29_656 +CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[2] origin:032-cmt-pll 28_657 +CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[3] origin:032-cmt-pll 29_657 +CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[4] origin:032-cmt-pll 28_658 +CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[5] origin:032-cmt-pll 29_658 +CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[6] origin:032-cmt-pll 28_659 +CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[7] origin:032-cmt-pll 29_659 +CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[8] origin:032-cmt-pll 29_660 +CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[9] origin:032-cmt-pll 28_661 +CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[10] origin:032-cmt-pll 29_662 +CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG1_RESERVED[11] origin:032-cmt-pll 28_663 +CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[0] origin:032-cmt-pll 28_664 +CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[1] origin:032-cmt-pll 29_664 +CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[2] origin:032-cmt-pll 28_665 +CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[3] origin:032-cmt-pll 29_665 +CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[4] origin:032-cmt-pll 29_666 +CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[5] origin:032-cmt-pll 28_667 +CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[6] origin:032-cmt-pll 29_668 +CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[7] origin:032-cmt-pll 28_669 +CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[8] origin:032-cmt-pll 29_670 +CMT_TOP_R_UPPER_T.PLLE2_ADV.FILTREG2_RESERVED[9] origin:032-cmt-pll 28_671 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LOCKREG1_RESERVED[0] origin:032-cmt-pll 28_229 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LOCKREG1_RESERVED[1] origin:032-cmt-pll 29_229 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LOCKREG1_RESERVED[2] origin:032-cmt-pll 28_230 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LOCKREG1_RESERVED[3] origin:032-cmt-pll 29_230 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LOCKREG1_RESERVED[4] origin:032-cmt-pll 28_231 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LOCKREG1_RESERVED[5] origin:032-cmt-pll 29_231 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LOCKREG2_RESERVED[0] origin:032-cmt-pll 29_239 +CMT_TOP_R_UPPER_T.PLLE2_ADV.LOCKREG3_RESERVED[0] origin:032-cmt-pll 29_247 diff --git a/zynq7/segbits_int_l.origin_info.db b/zynq7/segbits_int_l.origin_info.db index 2324bd7..22f30e5 100644 --- a/zynq7/segbits_int_l.origin_info.db +++ b/zynq7/segbits_int_l.origin_info.db @@ -393,7 +393,7 @@ INT_L.FAN_ALT3.WW2END3 origin:050-pip-seed !22_56 !23_56 !24_56 19_57 25_56 INT_L.FAN_ALT4.BYP_BOUNCE_N3_3 origin:059-pip-byp-bounce !22_08 !23_08 !24_08 20_08 25_08 INT_L.FAN_ALT4.BYP_BOUNCE_N3_7 origin:059-pip-byp-bounce !22_08 !23_08 !25_08 20_08 24_08 INT_L.FAN_ALT4.FAN_BOUNCE2 origin:050-pip-seed !23_08 20_08 22_08 24_08 25_08 -INT_L.FAN_ALT4.FAN_BOUNCE7 origin:056-pip-rem !22_08 20_08 23_08 24_08 25_08 +INT_L.FAN_ALT4.FAN_BOUNCE7 origin:050-pip-seed !22_08 20_08 23_08 24_08 25_08 INT_L.FAN_ALT4.LOGIC_OUTS_L4 origin:050-pip-seed !23_08 21_08 22_08 24_08 25_08 INT_L.FAN_ALT4.LOGIC_OUTS_L8 origin:050-pip-seed !22_08 21_08 23_08 24_08 25_08 INT_L.FAN_ALT4.LOGIC_OUTS_L18 origin:050-pip-seed !22_08 !23_08 !25_08 21_08 24_08 @@ -1937,7 +1937,7 @@ INT_L.EE4BEG3.SE6END3 origin:050-pip-seed 03_57 06_56 INT_L.EE4BEG3.SS2END3 origin:050-pip-seed 03_56 05_59 INT_L.EE4BEG3.SS6END3 origin:050-pip-seed 05_59 06_56 INT_L.EE4BEG3.SW2END3 origin:050-pip-seed 02_57 05_59 -INT_L.EE4BEG3.SW6END3 origin:056-pip-rem 05_56 05_59 +INT_L.EE4BEG3.SW6END3 origin:050-pip-seed 05_56 05_59 INT_L.EL1BEG0.LOGIC_OUTS_L1 origin:050-pip-seed 07_20 14_21 INT_L.EL1BEG0.LOGIC_OUTS_L5 origin:050-pip-seed 11_21 14_21 INT_L.EL1BEG0.LOGIC_OUTS_L9 origin:050-pip-seed 10_21 13_21 @@ -2273,7 +2273,7 @@ INT_L.NE6BEG3.NW6END3 origin:050-pip-seed 04_53 06_52 INT_L.NE6BEG3.SE2END3 origin:050-pip-seed 02_53 05_55 INT_L.NE6BEG3.SE6END3 origin:050-pip-seed 05_55 06_52 INT_L.NE6BEG3.WW2END2 origin:050-pip-seed 03_52 04_53 -INT_L.NE6BEG3.WW4END3 origin:056-pip-rem 04_53 05_52 +INT_L.NE6BEG3.WW4END3 origin:050-pip-seed 04_53 05_52 INT_L.NL1BEG0.LOGIC_OUTS_L1 origin:050-pip-seed 07_16 14_17 INT_L.NL1BEG0.LOGIC_OUTS_L5 origin:050-pip-seed 11_17 14_17 INT_L.NL1BEG0.LOGIC_OUTS_L9 origin:050-pip-seed 10_17 13_17 @@ -3345,7 +3345,7 @@ INT_L.SW6BEG3.NW2END_S0_0 origin:050-pip-seed 02_61 05_63 INT_L.SW6BEG3.NW6END_S0_0 origin:050-pip-seed 05_63 06_60 INT_L.SW6BEG3.WW4END_S0_0 origin:050-pip-seed 05_60 05_63 INT_L.SW6BEG3.EE2END3 origin:050-pip-seed 03_60 04_61 -INT_L.SW6BEG3.EE4END3 origin:056-pip-rem 04_61 05_60 +INT_L.SW6BEG3.EE4END3 origin:050-pip-seed 04_61 05_60 INT_L.SW6BEG3.LH0 origin:056-pip-rem 04_62 05_60 INT_L.SW6BEG3.SE2END3 origin:050-pip-seed 02_61 04_61 INT_L.SW6BEG3.SE6END3 origin:050-pip-seed 04_61 06_60 @@ -3603,7 +3603,7 @@ INT_L.WW4BEG2.LOGIC_OUTS_L20 origin:050-pip-seed 04_34 06_32 INT_L.WW4BEG2.LVB_L0 origin:056-pip-rem 04_34 05_32 INT_L.WW4BEG2.LVB_L12 origin:056-pip-rem 05_32 07_33 INT_L.WW4BEG2.NE2END2 origin:050-pip-seed 02_33 05_35 -INT_L.WW4BEG2.NE6END2 origin:056-pip-rem 05_32 05_35 +INT_L.WW4BEG2.NE6END2 origin:050-pip-seed 05_32 05_35 INT_L.WW4BEG2.NN2END2 origin:050-pip-seed 03_32 05_35 INT_L.WW4BEG2.NN6END2 origin:050-pip-seed 05_35 06_32 INT_L.WW4BEG2.NW2END2 origin:050-pip-seed 02_33 03_33 @@ -3623,7 +3623,7 @@ INT_L.WW4BEG3.LOGIC_OUTS_L21 origin:050-pip-seed 06_48 07_49 INT_L.WW4BEG3.LV_L18 origin:056-pip-rem 05_48 07_49 INT_L.WW4BEG3.LH0 origin:056-pip-rem 04_50 05_48 INT_L.WW4BEG3.NE2END3 origin:050-pip-seed 02_49 05_51 -INT_L.WW4BEG3.NE6END3 origin:056-pip-rem 05_48 05_51 +INT_L.WW4BEG3.NE6END3 origin:050-pip-seed 05_48 05_51 INT_L.WW4BEG3.NN2END3 origin:050-pip-seed 03_48 05_51 INT_L.WW4BEG3.NN6END3 origin:050-pip-seed 05_51 06_48 INT_L.WW4BEG3.NW2END3 origin:050-pip-seed 02_49 03_49 diff --git a/zynq7/segbits_int_r.origin_info.db b/zynq7/segbits_int_r.origin_info.db index e91f19b..9ea6b56 100644 --- a/zynq7/segbits_int_r.origin_info.db +++ b/zynq7/segbits_int_r.origin_info.db @@ -329,7 +329,7 @@ INT_R.FAN_ALT3.WW2END3 origin:050-pip-seed !22_56 !23_56 !24_56 19_57 25_56 INT_R.FAN_ALT4.BYP_BOUNCE_N3_3 origin:059-pip-byp-bounce !22_08 !23_08 !24_08 20_08 25_08 INT_R.FAN_ALT4.BYP_BOUNCE_N3_7 origin:059-pip-byp-bounce !22_08 !23_08 !25_08 20_08 24_08 INT_R.FAN_ALT4.FAN_BOUNCE2 origin:050-pip-seed !23_08 20_08 22_08 24_08 25_08 -INT_R.FAN_ALT4.FAN_BOUNCE7 origin:056-pip-rem !22_08 20_08 23_08 24_08 25_08 +INT_R.FAN_ALT4.FAN_BOUNCE7 origin:050-pip-seed !22_08 20_08 23_08 24_08 25_08 INT_R.FAN_ALT4.LOGIC_OUTS4 origin:050-pip-seed !23_08 21_08 22_08 24_08 25_08 INT_R.FAN_ALT4.LOGIC_OUTS8 origin:050-pip-seed !22_08 21_08 23_08 24_08 25_08 INT_R.FAN_ALT4.LOGIC_OUTS18 origin:050-pip-seed !22_08 !23_08 !25_08 21_08 24_08 @@ -3623,7 +3623,7 @@ INT_R.WW4BEG3.LOGIC_OUTS21 origin:050-pip-seed 06_48 07_49 INT_R.WW4BEG3.LH0 origin:056-pip-rem 04_50 05_48 INT_R.WW4BEG3.LV18 origin:056-pip-rem 05_48 07_49 INT_R.WW4BEG3.NE2END3 origin:050-pip-seed 02_49 05_51 -INT_R.WW4BEG3.NE6END3 origin:056-pip-rem 05_48 05_51 +INT_R.WW4BEG3.NE6END3 origin:050-pip-seed 05_48 05_51 INT_R.WW4BEG3.NN2END3 origin:050-pip-seed 03_48 05_51 INT_R.WW4BEG3.NN6END3 origin:050-pip-seed 05_51 06_48 INT_R.WW4BEG3.NW2END3 origin:050-pip-seed 02_49 03_49 diff --git a/zynq7/segbits_liob33.db b/zynq7/segbits_liob33.db index 4d9f02a..e5c2ee6 100644 --- a/zynq7/segbits_liob33.db +++ b/zynq7/segbits_liob33.db @@ -48,6 +48,7 @@ LIOB33.IOB_Y1.IN_TERM.UNTUNED_SPLIT_40 38_04 38_06 39_05 39_07 LIOB33.IOB_Y1.IN_TERM.UNTUNED_SPLIT_50 38_04 !38_06 39_05 39_07 LIOB33.IOB_Y1.IN_TERM.UNTUNED_SPLIT_60 38_04 !38_06 !39_05 39_07 LIOB33.IOB_Y1.INTERMDISABLE.I 38_38 +LIOB33.IOB_Y1.LVDS_25_SSTL135_SSTL15.IN_DIFF 38_40 !38_42 39_41 LIOB33.IOB_Y1.LVTTL.DRIVE.I24 !38_00 !38_02 38_08 38_10 38_62 39_01 !39_09 !39_15 39_63 LIOB33.IOB_Y1.PULLTYPE.KEEPER !38_34 39_33 39_35 LIOB33.IOB_Y1.PULLTYPE.NONE !38_34 39_33 !39_35 @@ -57,8 +58,8 @@ LIOB33.IOB_Y1.ZIBUF_LOW_PWR 39_43 LIOB33.IOB_Y1.LVCMOS12.DRIVE.I4 !38_00 38_02 !38_08 !38_10 38_14 38_62 39_01 39_09 39_15 39_63 LIOB33.IOB_Y1.LVCMOS12.DRIVE.I12 38_00 !38_02 !38_08 !38_10 38_14 38_62 39_01 !39_09 39_15 39_63 LIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18.IN !38_40 38_42 39_41 +LIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVDS_25_LVTTL_SSTL135_SSTL15_TMDS_33.IN_ONLY !38_00 38_02 38_08 !38_10 38_14 !38_62 !39_01 39_09 !39_15 !39_63 LIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST !38_16 !38_18 !38_20 !38_22 !39_17 !39_21 -LIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.IN_ONLY !38_00 38_02 38_08 !38_10 38_14 !38_62 !39_01 39_09 !39_15 !39_63 LIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.SLEW.SLOW !38_16 38_18 !38_20 38_22 39_17 39_21 LIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_SSTL135_SSTL15.STEPDOWN 38_32 LIOB33.IOB_Y1.LVCMOS12_LVCMOS25.DRIVE.I8 !38_00 !38_02 38_08 !38_10 38_14 38_62 !39_01 !39_09 39_15 39_63 @@ -78,6 +79,5 @@ LIOB33.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I12_I8 !38_00 38_02 38_08 !38_10 38_62 39_01 LIOB33.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I12_I16 38_00 38_02 !38_08 !38_10 38_62 39_01 !39_09 !39_15 39_63 LIOB33.IOB_Y1.SSTL135.DRIVE.I_FIXED 38_00 !38_02 38_08 38_10 38_14 38_62 39_01 39_09 39_15 39_63 LIOB33.IOB_Y1.SSTL135_SSTL15.IN 38_40 !38_42 !39_41 -LIOB33.IOB_Y1.SSTL135_SSTL15.IN_DIFF 38_40 !38_42 39_41 LIOB33.IOB_Y1.SSTL135_SSTL15.SLEW.FAST 38_16 38_18 38_20 38_22 39_17 !39_21 LIOB33.OUT_DIFF 39_59 39_61 diff --git a/zynq7/segbits_liob33.origin_info.db b/zynq7/segbits_liob33.origin_info.db index 022593c..5c43c07 100644 --- a/zynq7/segbits_liob33.origin_info.db +++ b/zynq7/segbits_liob33.origin_info.db @@ -48,6 +48,7 @@ LIOB33.IOB_Y1.IN_TERM.UNTUNED_SPLIT_40 origin:030-iob 38_04 38_06 39_05 39_07 LIOB33.IOB_Y1.IN_TERM.UNTUNED_SPLIT_50 origin:030-iob !38_06 38_04 39_05 39_07 LIOB33.IOB_Y1.IN_TERM.UNTUNED_SPLIT_60 origin:030-iob !38_06 !39_05 38_04 39_07 LIOB33.IOB_Y1.INTERMDISABLE.I origin:030-iob 38_38 +LIOB33.IOB_Y1.LVDS_25_SSTL135_SSTL15.IN_DIFF origin:030-iob !38_42 38_40 39_41 LIOB33.IOB_Y1.LVTTL.DRIVE.I24 origin:030-iob !38_00 !38_02 !39_09 !39_15 38_08 38_10 38_62 39_01 39_63 LIOB33.IOB_Y1.PULLTYPE.KEEPER origin:030-iob !38_34 39_33 39_35 LIOB33.IOB_Y1.PULLTYPE.NONE origin:030-iob !38_34 !39_35 39_33 @@ -57,8 +58,8 @@ LIOB33.IOB_Y1.ZIBUF_LOW_PWR origin:030-iob 39_43 LIOB33.IOB_Y1.LVCMOS12.DRIVE.I4 origin:030-iob !38_00 !38_08 !38_10 38_02 38_14 38_62 39_01 39_09 39_15 39_63 LIOB33.IOB_Y1.LVCMOS12.DRIVE.I12 origin:030-iob !38_02 !38_08 !38_10 !39_09 38_00 38_14 38_62 39_01 39_15 39_63 LIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18.IN origin:030-iob !38_40 38_42 39_41 +LIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVDS_25_LVTTL_SSTL135_SSTL15_TMDS_33.IN_ONLY origin:030-iob !38_00 !38_10 !38_62 !39_01 !39_15 !39_63 38_02 38_08 38_14 39_09 LIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST origin:030-iob !38_16 !38_18 !38_20 !38_22 !39_17 !39_21 -LIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.IN_ONLY origin:030-iob !38_00 !38_10 !38_62 !39_01 !39_15 !39_63 38_02 38_08 38_14 39_09 LIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.SLEW.SLOW origin:030-iob !38_16 !38_20 38_18 38_22 39_17 39_21 LIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_SSTL135_SSTL15.STEPDOWN origin:030-iob 38_32 LIOB33.IOB_Y1.LVCMOS12_LVCMOS25.DRIVE.I8 origin:030-iob !38_00 !38_02 !38_10 !39_01 !39_09 38_08 38_14 38_62 39_15 39_63 @@ -78,6 +79,5 @@ LIOB33.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I12_I8 origin:030-iob !38_00 !38_10 !39_09 !3 LIOB33.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I12_I16 origin:030-iob !38_08 !38_10 !39_09 !39_15 38_00 38_02 38_62 39_01 39_63 LIOB33.IOB_Y1.SSTL135.DRIVE.I_FIXED origin:030-iob !38_02 38_00 38_08 38_10 38_14 38_62 39_01 39_09 39_15 39_63 LIOB33.IOB_Y1.SSTL135_SSTL15.IN origin:030-iob !38_42 !39_41 38_40 -LIOB33.IOB_Y1.SSTL135_SSTL15.IN_DIFF origin:030-iob !38_42 38_40 39_41 LIOB33.IOB_Y1.SSTL135_SSTL15.SLEW.FAST origin:030-iob !39_21 38_16 38_18 38_20 38_22 39_17 LIOB33.OUT_DIFF origin:030-iob 39_59 39_61 diff --git a/zynq7/segbits_riob33.db b/zynq7/segbits_riob33.db index a4b4403..bf489d5 100644 --- a/zynq7/segbits_riob33.db +++ b/zynq7/segbits_riob33.db @@ -48,6 +48,7 @@ RIOB33.IOB_Y1.IN_TERM.UNTUNED_SPLIT_40 38_04 38_06 39_05 39_07 RIOB33.IOB_Y1.IN_TERM.UNTUNED_SPLIT_50 38_04 !38_06 39_05 39_07 RIOB33.IOB_Y1.IN_TERM.UNTUNED_SPLIT_60 38_04 !38_06 !39_05 39_07 RIOB33.IOB_Y1.INTERMDISABLE.I 38_38 +RIOB33.IOB_Y1.LVDS_25_SSTL135_SSTL15.IN_DIFF 38_40 !38_42 39_41 RIOB33.IOB_Y1.LVTTL.DRIVE.I24 !38_00 !38_02 38_08 38_10 38_62 39_01 !39_09 !39_15 39_63 RIOB33.IOB_Y1.PULLTYPE.KEEPER !38_34 39_33 39_35 RIOB33.IOB_Y1.PULLTYPE.NONE !38_34 39_33 !39_35 @@ -57,8 +58,8 @@ RIOB33.IOB_Y1.ZIBUF_LOW_PWR 39_43 RIOB33.IOB_Y1.LVCMOS12.DRIVE.I4 !38_00 38_02 !38_08 !38_10 38_14 38_62 39_01 39_09 39_15 39_63 RIOB33.IOB_Y1.LVCMOS12.DRIVE.I12 38_00 !38_02 !38_08 !38_10 38_14 38_62 39_01 !39_09 39_15 39_63 RIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18.IN !38_40 38_42 39_41 +RIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVDS_25_LVTTL_SSTL135_SSTL15_TMDS_33.IN_ONLY !38_00 38_02 38_08 !38_10 38_14 !38_62 !39_01 39_09 !39_15 !39_63 RIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST !38_16 !38_18 !38_20 !38_22 !39_17 !39_21 -RIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.IN_ONLY !38_00 38_02 38_08 !38_10 38_14 !38_62 !39_01 39_09 !39_15 !39_63 RIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.SLEW.SLOW !38_16 38_18 !38_20 38_22 39_17 39_21 RIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_SSTL135_SSTL15.STEPDOWN 38_32 RIOB33.IOB_Y1.LVCMOS12_LVCMOS25.DRIVE.I8 !38_00 !38_02 38_08 !38_10 38_14 38_62 !39_01 !39_09 39_15 39_63 @@ -78,6 +79,5 @@ RIOB33.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I12_I8 !38_00 38_02 38_08 !38_10 38_62 39_01 RIOB33.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I12_I16 38_00 38_02 !38_08 !38_10 38_62 39_01 !39_09 !39_15 39_63 RIOB33.IOB_Y1.SSTL135.DRIVE.I_FIXED 38_00 !38_02 38_08 38_10 38_14 38_62 39_01 39_09 39_15 39_63 RIOB33.IOB_Y1.SSTL135_SSTL15.IN 38_40 !38_42 !39_41 -RIOB33.IOB_Y1.SSTL135_SSTL15.IN_DIFF 38_40 !38_42 39_41 RIOB33.IOB_Y1.SSTL135_SSTL15.SLEW.FAST 38_16 38_18 38_20 38_22 39_17 !39_21 RIOB33.OUT_DIFF 39_59 39_61 diff --git a/zynq7/segbits_riob33.origin_info.db b/zynq7/segbits_riob33.origin_info.db index 95c9159..cee7b38 100644 --- a/zynq7/segbits_riob33.origin_info.db +++ b/zynq7/segbits_riob33.origin_info.db @@ -48,6 +48,7 @@ RIOB33.IOB_Y1.IN_TERM.UNTUNED_SPLIT_40 origin:030-iob 38_04 38_06 39_05 39_07 RIOB33.IOB_Y1.IN_TERM.UNTUNED_SPLIT_50 origin:030-iob !38_06 38_04 39_05 39_07 RIOB33.IOB_Y1.IN_TERM.UNTUNED_SPLIT_60 origin:030-iob !38_06 !39_05 38_04 39_07 RIOB33.IOB_Y1.INTERMDISABLE.I origin:030-iob 38_38 +RIOB33.IOB_Y1.LVDS_25_SSTL135_SSTL15.IN_DIFF origin:030-iob !38_42 38_40 39_41 RIOB33.IOB_Y1.LVTTL.DRIVE.I24 origin:030-iob !38_00 !38_02 !39_09 !39_15 38_08 38_10 38_62 39_01 39_63 RIOB33.IOB_Y1.PULLTYPE.KEEPER origin:030-iob !38_34 39_33 39_35 RIOB33.IOB_Y1.PULLTYPE.NONE origin:030-iob !38_34 !39_35 39_33 @@ -57,8 +58,8 @@ RIOB33.IOB_Y1.ZIBUF_LOW_PWR origin:030-iob 39_43 RIOB33.IOB_Y1.LVCMOS12.DRIVE.I4 origin:030-iob !38_00 !38_08 !38_10 38_02 38_14 38_62 39_01 39_09 39_15 39_63 RIOB33.IOB_Y1.LVCMOS12.DRIVE.I12 origin:030-iob !38_02 !38_08 !38_10 !39_09 38_00 38_14 38_62 39_01 39_15 39_63 RIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18.IN origin:030-iob !38_40 38_42 39_41 +RIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVDS_25_LVTTL_SSTL135_SSTL15_TMDS_33.IN_ONLY origin:030-iob !38_00 !38_10 !38_62 !39_01 !39_15 !39_63 38_02 38_08 38_14 39_09 RIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST origin:030-iob !38_16 !38_18 !38_20 !38_22 !39_17 !39_21 -RIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.IN_ONLY origin:030-iob !38_00 !38_10 !38_62 !39_01 !39_15 !39_63 38_02 38_08 38_14 39_09 RIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.SLEW.SLOW origin:030-iob !38_16 !38_20 38_18 38_22 39_17 39_21 RIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_SSTL135_SSTL15.STEPDOWN origin:030-iob 38_32 RIOB33.IOB_Y1.LVCMOS12_LVCMOS25.DRIVE.I8 origin:030-iob !38_00 !38_02 !38_10 !39_01 !39_09 38_08 38_14 38_62 39_15 39_63 @@ -78,6 +79,5 @@ RIOB33.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I12_I8 origin:030-iob !38_00 !38_10 !39_09 !3 RIOB33.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I12_I16 origin:030-iob !38_08 !38_10 !39_09 !39_15 38_00 38_02 38_62 39_01 39_63 RIOB33.IOB_Y1.SSTL135.DRIVE.I_FIXED origin:030-iob !38_02 38_00 38_08 38_10 38_14 38_62 39_01 39_09 39_15 39_63 RIOB33.IOB_Y1.SSTL135_SSTL15.IN origin:030-iob !38_42 !39_41 38_40 -RIOB33.IOB_Y1.SSTL135_SSTL15.IN_DIFF origin:030-iob !38_42 38_40 39_41 RIOB33.IOB_Y1.SSTL135_SSTL15.SLEW.FAST origin:030-iob !39_21 38_16 38_18 38_20 38_22 39_17 RIOB33.OUT_DIFF origin:030-iob 39_59 39_61