Updating artix7 based on "Merge pull request #835 from antmicro/bel-timings-fixes".
See [Info File](Info.md) for details. Signed-off-by: Tim 'mithro' Ansell <me@mith.ro>
This commit is contained in:
Tim 'mithro' Ansell
parent
9f6bdab253
commit
1571b7e503
244
Info.md
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Info.md
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@ -37,20 +37,20 @@ These files are released under the very permissive [CC0 1.0 Universal](COPYING).
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# Details
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Last updated on Thu May 30 18:27:13 UTC 2019 (2019-05-30T18:27:13+00:00).
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Last updated on Thu May 30 18:31:27 UTC 2019 (2019-05-30T18:31:27+00:00).
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Created using [Project X-Ray](https://github.com/SymbiFlow/prjxray) version [6e895f3](https://github.com/SymbiFlow/prjxray/commit/6e895f39c003e929942cc6af8c1378d14238d34f).
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Created using [Project X-Ray](https://github.com/SymbiFlow/prjxray) version [8cb7366](https://github.com/SymbiFlow/prjxray/commit/8cb7366fa2c361fd5c8eec0aa0cb976808a39752).
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Latest commit was;
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```
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commit 6e895f39c003e929942cc6af8c1378d14238d34f
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Merge: e7ce84a e5d2a65
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Author: Tim Ansell <me@mith.ro>
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Date: Tue May 14 17:24:43 2019 -0700
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commit 8cb7366fa2c361fd5c8eec0aa0cb976808a39752
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Merge: 6e895f3 683b756
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Author: litghost <537074+litghost@users.noreply.github.com>
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Date: Mon May 20 10:38:28 2019 -0700
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Merge pull request #836 from antmicro/sdf-sort
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Merge pull request #835 from antmicro/bel-timings-fixes
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utils: makesdf: sort the output
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BEL timings fixes
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```
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@ -59,7 +59,7 @@ Date: Tue May 14 17:24:43 2019 -0700
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### Settings
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Created using following [settings/artix7.sh (sha256: 26e1ff93657132928a3b583c95347267d7afeb18a7b7036f0d7a6ea3367ae803)](https://github.com/SymbiFlow/prjxray/blob/6e895f39c003e929942cc6af8c1378d14238d34f/settings/artix7.sh)
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Created using following [settings/artix7.sh (sha256: 26e1ff93657132928a3b583c95347267d7afeb18a7b7036f0d7a6ea3367ae803)](https://github.com/SymbiFlow/prjxray/blob/8cb7366fa2c361fd5c8eec0aa0cb976808a39752/settings/artix7.sh)
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```shell
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export XRAY_DATABASE="artix7"
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export XRAY_PART="xc7a50tfgg484-1"
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@ -345,117 +345,117 @@ Results have checksums;
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* [`004efcd7f9e172780ca7b8c379ec329bcfc52f86beaa1d997f41dbef7ac4a242 ./artix7/tile_type_VFRAME.json`](./artix7/tile_type_VFRAME.json)
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* [`1604d48580815e26069c2b4909fcc50e8e8f974ad0beb349ced2329c302bb06b ./artix7/tileconn.json`](./artix7/tileconn.json)
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* [`08912d58cee8057f7557c307700162b1d3437766adeb95a79980bf3602a7a779 ./artix7/tilegrid.json`](./artix7/tilegrid.json)
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* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./artix7/timings/BRAM_INT_INTERFACE_L.sdf`](./artix7/timings/BRAM_INT_INTERFACE_L.sdf)
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* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./artix7/timings/BRAM_INT_INTERFACE_R.sdf`](./artix7/timings/BRAM_INT_INTERFACE_R.sdf)
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* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./artix7/timings/BRAM_L.sdf`](./artix7/timings/BRAM_L.sdf)
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* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./artix7/timings/BRAM_R.sdf`](./artix7/timings/BRAM_R.sdf)
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* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./artix7/timings/BRKH_BRAM.sdf`](./artix7/timings/BRKH_BRAM.sdf)
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* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./artix7/timings/BRKH_B_TERM_INT.sdf`](./artix7/timings/BRKH_B_TERM_INT.sdf)
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* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./artix7/timings/BRKH_CLB.sdf`](./artix7/timings/BRKH_CLB.sdf)
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* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./artix7/timings/BRKH_CLK.sdf`](./artix7/timings/BRKH_CLK.sdf)
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* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./artix7/timings/BRKH_CMT.sdf`](./artix7/timings/BRKH_CMT.sdf)
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* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./artix7/timings/BRKH_DSP_L.sdf`](./artix7/timings/BRKH_DSP_L.sdf)
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* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./artix7/timings/BRKH_DSP_R.sdf`](./artix7/timings/BRKH_DSP_R.sdf)
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* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./artix7/timings/BRKH_GTX.sdf`](./artix7/timings/BRKH_GTX.sdf)
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* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./artix7/timings/BRKH_INT.sdf`](./artix7/timings/BRKH_INT.sdf)
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* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./artix7/timings/BRKH_TERM_INT.sdf`](./artix7/timings/BRKH_TERM_INT.sdf)
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* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./artix7/timings/B_TERM_INT.sdf`](./artix7/timings/B_TERM_INT.sdf)
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* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./artix7/timings/CFG_CENTER_BOT.sdf`](./artix7/timings/CFG_CENTER_BOT.sdf)
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* [`cd6fac9b7dbf1a487d429380ac8085d18c9d29c1246ae02627822dffafe3ad81 ./artix7/timings/CFG_CENTER_MID.sdf`](./artix7/timings/CFG_CENTER_MID.sdf)
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* [`812a76710efb916c1f164be2deacabdadacf8059c66b34e6d70da22fd5fb83b4 ./artix7/timings/CFG_CENTER_TOP.sdf`](./artix7/timings/CFG_CENTER_TOP.sdf)
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* [`99a8265d9d9b9504c7a9da30353540edd417faa80a44f8bee82ff9ecb1460ee3 ./artix7/timings/CLBLL_L.sdf`](./artix7/timings/CLBLL_L.sdf)
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* [`99a8265d9d9b9504c7a9da30353540edd417faa80a44f8bee82ff9ecb1460ee3 ./artix7/timings/CLBLL_R.sdf`](./artix7/timings/CLBLL_R.sdf)
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* [`dbfcf17321beba13500b27a60b111f77ea33979f496d2eec9183062e31ba3192 ./artix7/timings/CLBLM_L.sdf`](./artix7/timings/CLBLM_L.sdf)
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* [`dbfcf17321beba13500b27a60b111f77ea33979f496d2eec9183062e31ba3192 ./artix7/timings/CLBLM_R.sdf`](./artix7/timings/CLBLM_R.sdf)
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* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./artix7/timings/CLK_BUFG_BOT_R.sdf`](./artix7/timings/CLK_BUFG_BOT_R.sdf)
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* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./artix7/timings/CLK_BUFG_REBUF.sdf`](./artix7/timings/CLK_BUFG_REBUF.sdf)
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* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./artix7/timings/CLK_BUFG_TOP_R.sdf`](./artix7/timings/CLK_BUFG_TOP_R.sdf)
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* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./artix7/timings/CLK_FEED.sdf`](./artix7/timings/CLK_FEED.sdf)
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* [`36ff9133a29111718ad6ec58246ac6ae789f402437bf71c55c45f843d5c4a4d0 ./artix7/timings/CLK_HROW_BOT_R.sdf`](./artix7/timings/CLK_HROW_BOT_R.sdf)
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* [`36ff9133a29111718ad6ec58246ac6ae789f402437bf71c55c45f843d5c4a4d0 ./artix7/timings/CLK_HROW_TOP_R.sdf`](./artix7/timings/CLK_HROW_TOP_R.sdf)
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* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./artix7/timings/CLK_MTBF2.sdf`](./artix7/timings/CLK_MTBF2.sdf)
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* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./artix7/timings/CLK_PMV.sdf`](./artix7/timings/CLK_PMV.sdf)
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* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./artix7/timings/CLK_PMV2.sdf`](./artix7/timings/CLK_PMV2.sdf)
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* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./artix7/timings/CLK_PMV2_SVT.sdf`](./artix7/timings/CLK_PMV2_SVT.sdf)
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* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./artix7/timings/CLK_PMVIOB.sdf`](./artix7/timings/CLK_PMVIOB.sdf)
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* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./artix7/timings/CLK_TERM.sdf`](./artix7/timings/CLK_TERM.sdf)
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* [`b66eb5de5e90669e7e0336da3da1fcf8da77ce87c138d54d7e9f88c3daaa7bb1 ./artix7/timings/CMT_FIFO_L.sdf`](./artix7/timings/CMT_FIFO_L.sdf)
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* [`b66eb5de5e90669e7e0336da3da1fcf8da77ce87c138d54d7e9f88c3daaa7bb1 ./artix7/timings/CMT_FIFO_R.sdf`](./artix7/timings/CMT_FIFO_R.sdf)
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* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./artix7/timings/CMT_PMV.sdf`](./artix7/timings/CMT_PMV.sdf)
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* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./artix7/timings/CMT_PMV_L.sdf`](./artix7/timings/CMT_PMV_L.sdf)
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* [`f7ce46685da0dcb128c08368d54744298097d42e153c2b290c4161cdf6e21a04 ./artix7/timings/CMT_TOP_L_LOWER_B.sdf`](./artix7/timings/CMT_TOP_L_LOWER_B.sdf)
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* [`3fe24923c7943ae381284c831b9bfc258b923af97b9764cae748a9a0c4f29c8a ./artix7/timings/CMT_TOP_L_LOWER_T.sdf`](./artix7/timings/CMT_TOP_L_LOWER_T.sdf)
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* [`02beb763074fb8ee7f4ec4fb37250102e9ebafc9cdeb5374da8c0bf783661400 ./artix7/timings/CMT_TOP_L_UPPER_B.sdf`](./artix7/timings/CMT_TOP_L_UPPER_B.sdf)
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* [`29ad486b2420a82118bb311a3e6f9fe53e5d6323d0be0a84bd4f6438f50d3d1e ./artix7/timings/CMT_TOP_L_UPPER_T.sdf`](./artix7/timings/CMT_TOP_L_UPPER_T.sdf)
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* [`f7ce46685da0dcb128c08368d54744298097d42e153c2b290c4161cdf6e21a04 ./artix7/timings/CMT_TOP_R_LOWER_B.sdf`](./artix7/timings/CMT_TOP_R_LOWER_B.sdf)
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* [`3fe24923c7943ae381284c831b9bfc258b923af97b9764cae748a9a0c4f29c8a ./artix7/timings/CMT_TOP_R_LOWER_T.sdf`](./artix7/timings/CMT_TOP_R_LOWER_T.sdf)
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* [`02beb763074fb8ee7f4ec4fb37250102e9ebafc9cdeb5374da8c0bf783661400 ./artix7/timings/CMT_TOP_R_UPPER_B.sdf`](./artix7/timings/CMT_TOP_R_UPPER_B.sdf)
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* [`29ad486b2420a82118bb311a3e6f9fe53e5d6323d0be0a84bd4f6438f50d3d1e ./artix7/timings/CMT_TOP_R_UPPER_T.sdf`](./artix7/timings/CMT_TOP_R_UPPER_T.sdf)
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* [`4f8382d090f11c8c139d227957e6127bcb3d4742bb1ebde7b883eec48a7e7974 ./artix7/timings/GTP_CHANNEL_0.sdf`](./artix7/timings/GTP_CHANNEL_0.sdf)
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* [`4f8382d090f11c8c139d227957e6127bcb3d4742bb1ebde7b883eec48a7e7974 ./artix7/timings/GTP_CHANNEL_1.sdf`](./artix7/timings/GTP_CHANNEL_1.sdf)
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* [`4f8382d090f11c8c139d227957e6127bcb3d4742bb1ebde7b883eec48a7e7974 ./artix7/timings/GTP_CHANNEL_2.sdf`](./artix7/timings/GTP_CHANNEL_2.sdf)
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* [`4f8382d090f11c8c139d227957e6127bcb3d4742bb1ebde7b883eec48a7e7974 ./artix7/timings/GTP_CHANNEL_3.sdf`](./artix7/timings/GTP_CHANNEL_3.sdf)
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* [`823dfa36be490839caec9dadc24474f8136406ab92178e4bd8b0a109fd102bdc ./artix7/timings/GTP_COMMON.sdf`](./artix7/timings/GTP_COMMON.sdf)
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* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./artix7/timings/GTP_INT_INTERFACE.sdf`](./artix7/timings/GTP_INT_INTERFACE.sdf)
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* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./artix7/timings/HCLK_BRAM.sdf`](./artix7/timings/HCLK_BRAM.sdf)
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* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./artix7/timings/HCLK_CLB.sdf`](./artix7/timings/HCLK_CLB.sdf)
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* [`99727d100f5d3bd7cb0e9a8458ed3ef8536d0097e24a899bc877dd04450b79f4 ./artix7/timings/HCLK_CMT.sdf`](./artix7/timings/HCLK_CMT.sdf)
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* [`99727d100f5d3bd7cb0e9a8458ed3ef8536d0097e24a899bc877dd04450b79f4 ./artix7/timings/HCLK_CMT_L.sdf`](./artix7/timings/HCLK_CMT_L.sdf)
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* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./artix7/timings/HCLK_DSP_L.sdf`](./artix7/timings/HCLK_DSP_L.sdf)
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* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./artix7/timings/HCLK_DSP_R.sdf`](./artix7/timings/HCLK_DSP_R.sdf)
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* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./artix7/timings/HCLK_FEEDTHRU_1.sdf`](./artix7/timings/HCLK_FEEDTHRU_1.sdf)
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* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./artix7/timings/HCLK_FEEDTHRU_2.sdf`](./artix7/timings/HCLK_FEEDTHRU_2.sdf)
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* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./artix7/timings/HCLK_FIFO_L.sdf`](./artix7/timings/HCLK_FIFO_L.sdf)
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* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./artix7/timings/HCLK_GTX.sdf`](./artix7/timings/HCLK_GTX.sdf)
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* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./artix7/timings/HCLK_INT_INTERFACE.sdf`](./artix7/timings/HCLK_INT_INTERFACE.sdf)
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* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./artix7/timings/HCLK_IOB.sdf`](./artix7/timings/HCLK_IOB.sdf)
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* [`c6cabe7722ffe90e8ccd1ed86fdda7ab1710eae1298e82cf0e5d1138b9b6a446 ./artix7/timings/HCLK_IOI3.sdf`](./artix7/timings/HCLK_IOI3.sdf)
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* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./artix7/timings/HCLK_L.sdf`](./artix7/timings/HCLK_L.sdf)
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* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./artix7/timings/HCLK_L_BOT_UTURN.sdf`](./artix7/timings/HCLK_L_BOT_UTURN.sdf)
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* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./artix7/timings/HCLK_R.sdf`](./artix7/timings/HCLK_R.sdf)
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* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./artix7/timings/HCLK_R_BOT_UTURN.sdf`](./artix7/timings/HCLK_R_BOT_UTURN.sdf)
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* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./artix7/timings/HCLK_TERM.sdf`](./artix7/timings/HCLK_TERM.sdf)
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* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./artix7/timings/HCLK_TERM_GTX.sdf`](./artix7/timings/HCLK_TERM_GTX.sdf)
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* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./artix7/timings/HCLK_VBRK.sdf`](./artix7/timings/HCLK_VBRK.sdf)
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* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./artix7/timings/HCLK_VFRAME.sdf`](./artix7/timings/HCLK_VFRAME.sdf)
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* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./artix7/timings/INT_FEEDTHRU_1.sdf`](./artix7/timings/INT_FEEDTHRU_1.sdf)
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* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./artix7/timings/INT_FEEDTHRU_2.sdf`](./artix7/timings/INT_FEEDTHRU_2.sdf)
|
||||
* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./artix7/timings/INT_INTERFACE_L.sdf`](./artix7/timings/INT_INTERFACE_L.sdf)
|
||||
* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./artix7/timings/INT_INTERFACE_R.sdf`](./artix7/timings/INT_INTERFACE_R.sdf)
|
||||
* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./artix7/timings/INT_L.sdf`](./artix7/timings/INT_L.sdf)
|
||||
* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./artix7/timings/INT_R.sdf`](./artix7/timings/INT_R.sdf)
|
||||
* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./artix7/timings/IO_INT_INTERFACE_L.sdf`](./artix7/timings/IO_INT_INTERFACE_L.sdf)
|
||||
* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./artix7/timings/IO_INT_INTERFACE_R.sdf`](./artix7/timings/IO_INT_INTERFACE_R.sdf)
|
||||
* [`e10996f1fc67db81b7cd58e11297e6a2687d2103281199434f8c588813d66016 ./artix7/timings/LIOB33.sdf`](./artix7/timings/LIOB33.sdf)
|
||||
* [`9befc627c1bb83308433ab488ade8d0e4e26dd59490d8d8f622a68406077b04f ./artix7/timings/LIOB33_SING.sdf`](./artix7/timings/LIOB33_SING.sdf)
|
||||
* [`40f6b84423acd88ac976c0006e0bf32a783133d674863e655df361e4c042137f ./artix7/timings/LIOI3.sdf`](./artix7/timings/LIOI3.sdf)
|
||||
* [`40f6b84423acd88ac976c0006e0bf32a783133d674863e655df361e4c042137f ./artix7/timings/LIOI3_SING.sdf`](./artix7/timings/LIOI3_SING.sdf)
|
||||
* [`40f6b84423acd88ac976c0006e0bf32a783133d674863e655df361e4c042137f ./artix7/timings/LIOI3_TBYTESRC.sdf`](./artix7/timings/LIOI3_TBYTESRC.sdf)
|
||||
* [`40f6b84423acd88ac976c0006e0bf32a783133d674863e655df361e4c042137f ./artix7/timings/LIOI3_TBYTETERM.sdf`](./artix7/timings/LIOI3_TBYTETERM.sdf)
|
||||
* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./artix7/timings/L_TERM_INT.sdf`](./artix7/timings/L_TERM_INT.sdf)
|
||||
* [`9d8f7ba72a6cf7ab618f8e570cf18dc3717de406f3d3f97303395f312a0013ae ./artix7/timings/MONITOR_BOT.sdf`](./artix7/timings/MONITOR_BOT.sdf)
|
||||
* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./artix7/timings/MONITOR_MID.sdf`](./artix7/timings/MONITOR_MID.sdf)
|
||||
* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./artix7/timings/MONITOR_TOP.sdf`](./artix7/timings/MONITOR_TOP.sdf)
|
||||
* [`d9b2b73637555d64f23e488085618c6d4293699dda806cb95a4f4219dae3d980 ./artix7/timings/PCIE_BOT.sdf`](./artix7/timings/PCIE_BOT.sdf)
|
||||
* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./artix7/timings/PCIE_INT_INTERFACE_L.sdf`](./artix7/timings/PCIE_INT_INTERFACE_L.sdf)
|
||||
* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./artix7/timings/PCIE_INT_INTERFACE_R.sdf`](./artix7/timings/PCIE_INT_INTERFACE_R.sdf)
|
||||
* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./artix7/timings/PCIE_NULL.sdf`](./artix7/timings/PCIE_NULL.sdf)
|
||||
* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./artix7/timings/PCIE_TOP.sdf`](./artix7/timings/PCIE_TOP.sdf)
|
||||
* [`e10996f1fc67db81b7cd58e11297e6a2687d2103281199434f8c588813d66016 ./artix7/timings/RIOB33.sdf`](./artix7/timings/RIOB33.sdf)
|
||||
* [`9befc627c1bb83308433ab488ade8d0e4e26dd59490d8d8f622a68406077b04f ./artix7/timings/RIOB33_SING.sdf`](./artix7/timings/RIOB33_SING.sdf)
|
||||
* [`40f6b84423acd88ac976c0006e0bf32a783133d674863e655df361e4c042137f ./artix7/timings/RIOI3.sdf`](./artix7/timings/RIOI3.sdf)
|
||||
* [`40f6b84423acd88ac976c0006e0bf32a783133d674863e655df361e4c042137f ./artix7/timings/RIOI3_SING.sdf`](./artix7/timings/RIOI3_SING.sdf)
|
||||
* [`40f6b84423acd88ac976c0006e0bf32a783133d674863e655df361e4c042137f ./artix7/timings/RIOI3_TBYTESRC.sdf`](./artix7/timings/RIOI3_TBYTESRC.sdf)
|
||||
* [`40f6b84423acd88ac976c0006e0bf32a783133d674863e655df361e4c042137f ./artix7/timings/RIOI3_TBYTETERM.sdf`](./artix7/timings/RIOI3_TBYTETERM.sdf)
|
||||
* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./artix7/timings/R_TERM_INT.sdf`](./artix7/timings/R_TERM_INT.sdf)
|
||||
* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./artix7/timings/R_TERM_INT_GTX.sdf`](./artix7/timings/R_TERM_INT_GTX.sdf)
|
||||
* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./artix7/timings/TERM_CMT.sdf`](./artix7/timings/TERM_CMT.sdf)
|
||||
* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./artix7/timings/T_TERM_INT.sdf`](./artix7/timings/T_TERM_INT.sdf)
|
||||
* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./artix7/timings/VBRK.sdf`](./artix7/timings/VBRK.sdf)
|
||||
* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./artix7/timings/VBRK_EXT.sdf`](./artix7/timings/VBRK_EXT.sdf)
|
||||
* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./artix7/timings/VFRAME.sdf`](./artix7/timings/VFRAME.sdf)
|
||||
* [`d265a4878ba731554e7ab84939adc6a163076ca4f1345db79a8172558d0ebab9 ./artix7/timings/slicel.sdf`](./artix7/timings/slicel.sdf)
|
||||
* [`86cdcd5e028d5c08865e841eda91e535a15744af99c092e073121668e955515f ./artix7/timings/slicem.sdf`](./artix7/timings/slicem.sdf)
|
||||
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./artix7/timings/BRAM_INT_INTERFACE_L.sdf`](./artix7/timings/BRAM_INT_INTERFACE_L.sdf)
|
||||
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./artix7/timings/BRAM_INT_INTERFACE_R.sdf`](./artix7/timings/BRAM_INT_INTERFACE_R.sdf)
|
||||
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./artix7/timings/BRAM_L.sdf`](./artix7/timings/BRAM_L.sdf)
|
||||
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./artix7/timings/BRAM_R.sdf`](./artix7/timings/BRAM_R.sdf)
|
||||
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./artix7/timings/BRKH_BRAM.sdf`](./artix7/timings/BRKH_BRAM.sdf)
|
||||
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./artix7/timings/BRKH_B_TERM_INT.sdf`](./artix7/timings/BRKH_B_TERM_INT.sdf)
|
||||
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./artix7/timings/BRKH_CLB.sdf`](./artix7/timings/BRKH_CLB.sdf)
|
||||
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./artix7/timings/BRKH_CLK.sdf`](./artix7/timings/BRKH_CLK.sdf)
|
||||
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./artix7/timings/BRKH_CMT.sdf`](./artix7/timings/BRKH_CMT.sdf)
|
||||
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./artix7/timings/BRKH_DSP_L.sdf`](./artix7/timings/BRKH_DSP_L.sdf)
|
||||
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./artix7/timings/BRKH_DSP_R.sdf`](./artix7/timings/BRKH_DSP_R.sdf)
|
||||
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./artix7/timings/BRKH_GTX.sdf`](./artix7/timings/BRKH_GTX.sdf)
|
||||
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./artix7/timings/BRKH_INT.sdf`](./artix7/timings/BRKH_INT.sdf)
|
||||
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./artix7/timings/BRKH_TERM_INT.sdf`](./artix7/timings/BRKH_TERM_INT.sdf)
|
||||
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./artix7/timings/B_TERM_INT.sdf`](./artix7/timings/B_TERM_INT.sdf)
|
||||
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./artix7/timings/CFG_CENTER_BOT.sdf`](./artix7/timings/CFG_CENTER_BOT.sdf)
|
||||
* [`8d6db739fe7463bf3806921de087423d59531ab44ff6fc1969c1421a39461bdb ./artix7/timings/CFG_CENTER_MID.sdf`](./artix7/timings/CFG_CENTER_MID.sdf)
|
||||
* [`6dc7edd0792e8305dd8309933c264512fc6a22f45cf0386422edc219d5a3b20a ./artix7/timings/CFG_CENTER_TOP.sdf`](./artix7/timings/CFG_CENTER_TOP.sdf)
|
||||
* [`c3811649b513500c04b1297aacc0b714889373899dad4d66dd7f8f5bb034272d ./artix7/timings/CLBLL_L.sdf`](./artix7/timings/CLBLL_L.sdf)
|
||||
* [`c3811649b513500c04b1297aacc0b714889373899dad4d66dd7f8f5bb034272d ./artix7/timings/CLBLL_R.sdf`](./artix7/timings/CLBLL_R.sdf)
|
||||
* [`aa30bd99d2e521fa5d5c441df3492e15df123d4145eda5269a76a749401ba33b ./artix7/timings/CLBLM_L.sdf`](./artix7/timings/CLBLM_L.sdf)
|
||||
* [`aa30bd99d2e521fa5d5c441df3492e15df123d4145eda5269a76a749401ba33b ./artix7/timings/CLBLM_R.sdf`](./artix7/timings/CLBLM_R.sdf)
|
||||
* [`4389bcb34bbc566f909c9d5d5d7bd4ac600dca5db76f33443319fed56630efa9 ./artix7/timings/CLK_BUFG_BOT_R.sdf`](./artix7/timings/CLK_BUFG_BOT_R.sdf)
|
||||
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./artix7/timings/CLK_BUFG_REBUF.sdf`](./artix7/timings/CLK_BUFG_REBUF.sdf)
|
||||
* [`4389bcb34bbc566f909c9d5d5d7bd4ac600dca5db76f33443319fed56630efa9 ./artix7/timings/CLK_BUFG_TOP_R.sdf`](./artix7/timings/CLK_BUFG_TOP_R.sdf)
|
||||
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./artix7/timings/CLK_FEED.sdf`](./artix7/timings/CLK_FEED.sdf)
|
||||
* [`107282bc35eb94dbd0973c82c576e638917629b83743274f9463c225f8079396 ./artix7/timings/CLK_HROW_BOT_R.sdf`](./artix7/timings/CLK_HROW_BOT_R.sdf)
|
||||
* [`107282bc35eb94dbd0973c82c576e638917629b83743274f9463c225f8079396 ./artix7/timings/CLK_HROW_TOP_R.sdf`](./artix7/timings/CLK_HROW_TOP_R.sdf)
|
||||
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./artix7/timings/CLK_MTBF2.sdf`](./artix7/timings/CLK_MTBF2.sdf)
|
||||
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./artix7/timings/CLK_PMV.sdf`](./artix7/timings/CLK_PMV.sdf)
|
||||
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./artix7/timings/CLK_PMV2.sdf`](./artix7/timings/CLK_PMV2.sdf)
|
||||
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./artix7/timings/CLK_PMV2_SVT.sdf`](./artix7/timings/CLK_PMV2_SVT.sdf)
|
||||
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./artix7/timings/CLK_PMVIOB.sdf`](./artix7/timings/CLK_PMVIOB.sdf)
|
||||
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./artix7/timings/CLK_TERM.sdf`](./artix7/timings/CLK_TERM.sdf)
|
||||
* [`366802adb3810a1cecf1674f01fe1a97f1338a7455d7a6e4796aa004311b9c8a ./artix7/timings/CMT_FIFO_L.sdf`](./artix7/timings/CMT_FIFO_L.sdf)
|
||||
* [`366802adb3810a1cecf1674f01fe1a97f1338a7455d7a6e4796aa004311b9c8a ./artix7/timings/CMT_FIFO_R.sdf`](./artix7/timings/CMT_FIFO_R.sdf)
|
||||
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./artix7/timings/CMT_PMV.sdf`](./artix7/timings/CMT_PMV.sdf)
|
||||
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./artix7/timings/CMT_PMV_L.sdf`](./artix7/timings/CMT_PMV_L.sdf)
|
||||
* [`c2e66425da5018d6e7aa2b0aec721bcecfdba26bfa26016598cd28e3112fffc4 ./artix7/timings/CMT_TOP_L_LOWER_B.sdf`](./artix7/timings/CMT_TOP_L_LOWER_B.sdf)
|
||||
* [`35863307207f2f40fdbf61f5a5065b0112305594d5375a758491ee52e2a848a8 ./artix7/timings/CMT_TOP_L_LOWER_T.sdf`](./artix7/timings/CMT_TOP_L_LOWER_T.sdf)
|
||||
* [`e8fdd4747aa8be4e39fe2ae27f51c8442c754485c8506fc5b021150f08289e95 ./artix7/timings/CMT_TOP_L_UPPER_B.sdf`](./artix7/timings/CMT_TOP_L_UPPER_B.sdf)
|
||||
* [`5a70eb78c2a91cef8d2322645ac12acef53241d264ce548017620963e396a8a9 ./artix7/timings/CMT_TOP_L_UPPER_T.sdf`](./artix7/timings/CMT_TOP_L_UPPER_T.sdf)
|
||||
* [`c2e66425da5018d6e7aa2b0aec721bcecfdba26bfa26016598cd28e3112fffc4 ./artix7/timings/CMT_TOP_R_LOWER_B.sdf`](./artix7/timings/CMT_TOP_R_LOWER_B.sdf)
|
||||
* [`35863307207f2f40fdbf61f5a5065b0112305594d5375a758491ee52e2a848a8 ./artix7/timings/CMT_TOP_R_LOWER_T.sdf`](./artix7/timings/CMT_TOP_R_LOWER_T.sdf)
|
||||
* [`e8fdd4747aa8be4e39fe2ae27f51c8442c754485c8506fc5b021150f08289e95 ./artix7/timings/CMT_TOP_R_UPPER_B.sdf`](./artix7/timings/CMT_TOP_R_UPPER_B.sdf)
|
||||
* [`5a70eb78c2a91cef8d2322645ac12acef53241d264ce548017620963e396a8a9 ./artix7/timings/CMT_TOP_R_UPPER_T.sdf`](./artix7/timings/CMT_TOP_R_UPPER_T.sdf)
|
||||
* [`6e723a9ad0acfa2a322e4fb2fed8b94c9f188d72bdf4e370e0e79860f1cbba92 ./artix7/timings/GTP_CHANNEL_0.sdf`](./artix7/timings/GTP_CHANNEL_0.sdf)
|
||||
* [`6e723a9ad0acfa2a322e4fb2fed8b94c9f188d72bdf4e370e0e79860f1cbba92 ./artix7/timings/GTP_CHANNEL_1.sdf`](./artix7/timings/GTP_CHANNEL_1.sdf)
|
||||
* [`6e723a9ad0acfa2a322e4fb2fed8b94c9f188d72bdf4e370e0e79860f1cbba92 ./artix7/timings/GTP_CHANNEL_2.sdf`](./artix7/timings/GTP_CHANNEL_2.sdf)
|
||||
* [`6e723a9ad0acfa2a322e4fb2fed8b94c9f188d72bdf4e370e0e79860f1cbba92 ./artix7/timings/GTP_CHANNEL_3.sdf`](./artix7/timings/GTP_CHANNEL_3.sdf)
|
||||
* [`aa79f422942e6767be523045374d542a4a51262eb7af8a5bd6c64312ff1b2927 ./artix7/timings/GTP_COMMON.sdf`](./artix7/timings/GTP_COMMON.sdf)
|
||||
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./artix7/timings/GTP_INT_INTERFACE.sdf`](./artix7/timings/GTP_INT_INTERFACE.sdf)
|
||||
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./artix7/timings/HCLK_BRAM.sdf`](./artix7/timings/HCLK_BRAM.sdf)
|
||||
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./artix7/timings/HCLK_CLB.sdf`](./artix7/timings/HCLK_CLB.sdf)
|
||||
* [`5c9e2c5d7143ad81acc0bfb001d97e14192f0d79bcd444d5a4127b4c8c5080ff ./artix7/timings/HCLK_CMT.sdf`](./artix7/timings/HCLK_CMT.sdf)
|
||||
* [`5c9e2c5d7143ad81acc0bfb001d97e14192f0d79bcd444d5a4127b4c8c5080ff ./artix7/timings/HCLK_CMT_L.sdf`](./artix7/timings/HCLK_CMT_L.sdf)
|
||||
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./artix7/timings/HCLK_DSP_L.sdf`](./artix7/timings/HCLK_DSP_L.sdf)
|
||||
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./artix7/timings/HCLK_DSP_R.sdf`](./artix7/timings/HCLK_DSP_R.sdf)
|
||||
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./artix7/timings/HCLK_FEEDTHRU_1.sdf`](./artix7/timings/HCLK_FEEDTHRU_1.sdf)
|
||||
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./artix7/timings/HCLK_FEEDTHRU_2.sdf`](./artix7/timings/HCLK_FEEDTHRU_2.sdf)
|
||||
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./artix7/timings/HCLK_FIFO_L.sdf`](./artix7/timings/HCLK_FIFO_L.sdf)
|
||||
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./artix7/timings/HCLK_GTX.sdf`](./artix7/timings/HCLK_GTX.sdf)
|
||||
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./artix7/timings/HCLK_INT_INTERFACE.sdf`](./artix7/timings/HCLK_INT_INTERFACE.sdf)
|
||||
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./artix7/timings/HCLK_IOB.sdf`](./artix7/timings/HCLK_IOB.sdf)
|
||||
* [`aa457af9f2c18f89df64c0cfedf6374e08fb7e0ef4c671f25c677f2de7430708 ./artix7/timings/HCLK_IOI3.sdf`](./artix7/timings/HCLK_IOI3.sdf)
|
||||
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./artix7/timings/HCLK_L.sdf`](./artix7/timings/HCLK_L.sdf)
|
||||
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./artix7/timings/HCLK_L_BOT_UTURN.sdf`](./artix7/timings/HCLK_L_BOT_UTURN.sdf)
|
||||
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./artix7/timings/HCLK_R.sdf`](./artix7/timings/HCLK_R.sdf)
|
||||
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./artix7/timings/HCLK_R_BOT_UTURN.sdf`](./artix7/timings/HCLK_R_BOT_UTURN.sdf)
|
||||
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./artix7/timings/HCLK_TERM.sdf`](./artix7/timings/HCLK_TERM.sdf)
|
||||
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./artix7/timings/HCLK_TERM_GTX.sdf`](./artix7/timings/HCLK_TERM_GTX.sdf)
|
||||
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./artix7/timings/HCLK_VBRK.sdf`](./artix7/timings/HCLK_VBRK.sdf)
|
||||
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./artix7/timings/HCLK_VFRAME.sdf`](./artix7/timings/HCLK_VFRAME.sdf)
|
||||
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./artix7/timings/INT_FEEDTHRU_1.sdf`](./artix7/timings/INT_FEEDTHRU_1.sdf)
|
||||
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./artix7/timings/INT_FEEDTHRU_2.sdf`](./artix7/timings/INT_FEEDTHRU_2.sdf)
|
||||
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./artix7/timings/INT_INTERFACE_L.sdf`](./artix7/timings/INT_INTERFACE_L.sdf)
|
||||
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./artix7/timings/INT_INTERFACE_R.sdf`](./artix7/timings/INT_INTERFACE_R.sdf)
|
||||
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./artix7/timings/INT_L.sdf`](./artix7/timings/INT_L.sdf)
|
||||
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./artix7/timings/INT_R.sdf`](./artix7/timings/INT_R.sdf)
|
||||
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./artix7/timings/IO_INT_INTERFACE_L.sdf`](./artix7/timings/IO_INT_INTERFACE_L.sdf)
|
||||
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./artix7/timings/IO_INT_INTERFACE_R.sdf`](./artix7/timings/IO_INT_INTERFACE_R.sdf)
|
||||
* [`9313a012de7cbb7120baf15fe30bf8d44b238cad6226ece1a9776746e2857863 ./artix7/timings/LIOB33.sdf`](./artix7/timings/LIOB33.sdf)
|
||||
* [`0fdaf6a593346b5cac8899eebf4f62d1732d6d6fb0a17c9f4b6a4e54e03c3523 ./artix7/timings/LIOB33_SING.sdf`](./artix7/timings/LIOB33_SING.sdf)
|
||||
* [`582431f616d6cba090545c71cea3ed3de7e1d07ee21820a2258bc9f397bb5083 ./artix7/timings/LIOI3.sdf`](./artix7/timings/LIOI3.sdf)
|
||||
* [`582431f616d6cba090545c71cea3ed3de7e1d07ee21820a2258bc9f397bb5083 ./artix7/timings/LIOI3_SING.sdf`](./artix7/timings/LIOI3_SING.sdf)
|
||||
* [`582431f616d6cba090545c71cea3ed3de7e1d07ee21820a2258bc9f397bb5083 ./artix7/timings/LIOI3_TBYTESRC.sdf`](./artix7/timings/LIOI3_TBYTESRC.sdf)
|
||||
* [`582431f616d6cba090545c71cea3ed3de7e1d07ee21820a2258bc9f397bb5083 ./artix7/timings/LIOI3_TBYTETERM.sdf`](./artix7/timings/LIOI3_TBYTETERM.sdf)
|
||||
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./artix7/timings/L_TERM_INT.sdf`](./artix7/timings/L_TERM_INT.sdf)
|
||||
* [`2af03d31603e237767ecaef977f8b6050c71d32a7632330ac8f42909dc22befc ./artix7/timings/MONITOR_BOT.sdf`](./artix7/timings/MONITOR_BOT.sdf)
|
||||
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./artix7/timings/MONITOR_MID.sdf`](./artix7/timings/MONITOR_MID.sdf)
|
||||
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./artix7/timings/MONITOR_TOP.sdf`](./artix7/timings/MONITOR_TOP.sdf)
|
||||
* [`6254f39239a1ba10b6243a77132493992378e52606eb28cf2e2a2d8948b7dbd2 ./artix7/timings/PCIE_BOT.sdf`](./artix7/timings/PCIE_BOT.sdf)
|
||||
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./artix7/timings/PCIE_INT_INTERFACE_L.sdf`](./artix7/timings/PCIE_INT_INTERFACE_L.sdf)
|
||||
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./artix7/timings/PCIE_INT_INTERFACE_R.sdf`](./artix7/timings/PCIE_INT_INTERFACE_R.sdf)
|
||||
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./artix7/timings/PCIE_NULL.sdf`](./artix7/timings/PCIE_NULL.sdf)
|
||||
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./artix7/timings/PCIE_TOP.sdf`](./artix7/timings/PCIE_TOP.sdf)
|
||||
* [`9313a012de7cbb7120baf15fe30bf8d44b238cad6226ece1a9776746e2857863 ./artix7/timings/RIOB33.sdf`](./artix7/timings/RIOB33.sdf)
|
||||
* [`0fdaf6a593346b5cac8899eebf4f62d1732d6d6fb0a17c9f4b6a4e54e03c3523 ./artix7/timings/RIOB33_SING.sdf`](./artix7/timings/RIOB33_SING.sdf)
|
||||
* [`582431f616d6cba090545c71cea3ed3de7e1d07ee21820a2258bc9f397bb5083 ./artix7/timings/RIOI3.sdf`](./artix7/timings/RIOI3.sdf)
|
||||
* [`582431f616d6cba090545c71cea3ed3de7e1d07ee21820a2258bc9f397bb5083 ./artix7/timings/RIOI3_SING.sdf`](./artix7/timings/RIOI3_SING.sdf)
|
||||
* [`582431f616d6cba090545c71cea3ed3de7e1d07ee21820a2258bc9f397bb5083 ./artix7/timings/RIOI3_TBYTESRC.sdf`](./artix7/timings/RIOI3_TBYTESRC.sdf)
|
||||
* [`582431f616d6cba090545c71cea3ed3de7e1d07ee21820a2258bc9f397bb5083 ./artix7/timings/RIOI3_TBYTETERM.sdf`](./artix7/timings/RIOI3_TBYTETERM.sdf)
|
||||
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./artix7/timings/R_TERM_INT.sdf`](./artix7/timings/R_TERM_INT.sdf)
|
||||
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./artix7/timings/R_TERM_INT_GTX.sdf`](./artix7/timings/R_TERM_INT_GTX.sdf)
|
||||
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./artix7/timings/TERM_CMT.sdf`](./artix7/timings/TERM_CMT.sdf)
|
||||
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./artix7/timings/T_TERM_INT.sdf`](./artix7/timings/T_TERM_INT.sdf)
|
||||
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./artix7/timings/VBRK.sdf`](./artix7/timings/VBRK.sdf)
|
||||
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./artix7/timings/VBRK_EXT.sdf`](./artix7/timings/VBRK_EXT.sdf)
|
||||
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./artix7/timings/VFRAME.sdf`](./artix7/timings/VFRAME.sdf)
|
||||
* [`35db35a7aa9d38d9b88716b554cad80b5b073f22f488a1077ec2804ff89dbe5c ./artix7/timings/slicel.sdf`](./artix7/timings/slicel.sdf)
|
||||
* [`d363b195b39e4f774a0a2ea0291ff0daa466c5642682dc7b96a389a2a2861387 ./artix7/timings/slicem.sdf`](./artix7/timings/slicem.sdf)
|
||||
* [`4c20ee41ea32668919b7d91a7fabe38960e0ee4d5b3b83f1d18102d48895bf1c ./artix7/xc7a35tcpg236-1.json`](./artix7/xc7a35tcpg236-1.json)
|
||||
* [`ef0724733da87455426a0f833642d96e9d206d047f4eb97072c3093f80c40d7d ./artix7/xc7a35tcpg236-1.yaml`](./artix7/xc7a35tcpg236-1.yaml)
|
||||
* [`ac928ee3c50e91facacb4173fdf70384f56e046bb14581bf75f760e406fe4f78 ./artix7/xc7a35tcpg236-1_package_pins.csv`](./artix7/xc7a35tcpg236-1_package_pins.csv)
|
||||
|
|
@ -471,7 +471,7 @@ Results have checksums;
|
|||
|
||||
### Settings
|
||||
|
||||
Created using following [settings/kintex7.sh (sha256: 794538b550d399255cbafeeb1b5ff183dc66ebc6cd8dc0f725e3f6a3977f757d)](https://github.com/SymbiFlow/prjxray/blob/6e895f39c003e929942cc6af8c1378d14238d34f/settings/kintex7.sh)
|
||||
Created using following [settings/kintex7.sh (sha256: 794538b550d399255cbafeeb1b5ff183dc66ebc6cd8dc0f725e3f6a3977f757d)](https://github.com/SymbiFlow/prjxray/blob/8cb7366fa2c361fd5c8eec0aa0cb976808a39752/settings/kintex7.sh)
|
||||
```shell
|
||||
export XRAY_DATABASE="kintex7"
|
||||
export XRAY_PART="xc7k70tfbg676-2"
|
||||
|
|
@ -752,7 +752,7 @@ Results have checksums;
|
|||
|
||||
### Settings
|
||||
|
||||
Created using following [settings/zynq7.sh (sha256: 61298e89dcc873eadba47f5c2f9f72a38fa022583b2c7ff89246b2e051585ad8)](https://github.com/SymbiFlow/prjxray/blob/6e895f39c003e929942cc6af8c1378d14238d34f/settings/zynq7.sh)
|
||||
Created using following [settings/zynq7.sh (sha256: 61298e89dcc873eadba47f5c2f9f72a38fa022583b2c7ff89246b2e051585ad8)](https://github.com/SymbiFlow/prjxray/blob/8cb7366fa2c361fd5c8eec0aa0cb976808a39752/settings/zynq7.sh)
|
||||
```shell
|
||||
export XRAY_DATABASE="zynq7"
|
||||
export XRAY_PART="xc7z010clg400-1"
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
)
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
)
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
)
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
)
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
)
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
)
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
)
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
)
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
)
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
)
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
)
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
)
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
)
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
)
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
)
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
)
|
||||
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
(CELL
|
||||
(CELLTYPE "CAPTURE")
|
||||
(INSTANCE CAPTURE)
|
||||
(TIMINGCHECK
|
||||
(HOLD CLK (posedge CLK) (0.000::0.000))
|
||||
(SETUP CLK (posedge CLK) (3.725::4.285))
|
||||
(HOLD CAP (posedge CLK) (0.000::0.000))
|
||||
(SETUP CAP (posedge CLK) (3.725::4.285))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
(CELL
|
||||
(CELLTYPE "DNA_PORT_DNA_PORTDNA_PORT")
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
(CELL
|
||||
(CELLTYPE "CARRY4")
|
||||
|
|
@ -245,7 +245,11 @@
|
|||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD CE (posedge CLK) (-0.011::-0.009))
|
||||
(HOLD DIN (posedge CLK) (0.181::0.225))
|
||||
(HOLD INIT (posedge CLK) (-0.074::-0.060))
|
||||
(SETUP CE (posedge CLK) (0.088::0.109))
|
||||
(SETUP DIN (posedge CLK) (-0.057::-0.046))
|
||||
(SETUP INIT (posedge CLK) (0.345::0.428))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
|
|
@ -274,7 +278,11 @@
|
|||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD CE (posedge CLK) (-0.011::-0.009))
|
||||
(HOLD DIN (posedge CLK) (0.194::0.241))
|
||||
(HOLD INIT (posedge CLK) (-0.074::-0.060))
|
||||
(SETUP CE (posedge CLK) (0.088::0.109))
|
||||
(SETUP DIN (posedge CLK) (-0.055::-0.045))
|
||||
(SETUP INIT (posedge CLK) (0.345::0.428))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
|
|
@ -303,6 +311,10 @@
|
|||
(IOPATH D Q (0.073::0.092)(0.213::0.264))
|
||||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD DIN (posedge CLK) (0.194::0.241))
|
||||
(SETUP DIN (posedge CLK) (-0.068::-0.056))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "REG_INIT_LAT_LOGIC_AND")
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
(CELL
|
||||
(CELLTYPE "CARRY4")
|
||||
|
|
@ -245,7 +245,11 @@
|
|||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD CE (posedge CLK) (-0.011::-0.009))
|
||||
(HOLD DIN (posedge CLK) (0.181::0.225))
|
||||
(HOLD INIT (posedge CLK) (-0.074::-0.060))
|
||||
(SETUP CE (posedge CLK) (0.088::0.109))
|
||||
(SETUP DIN (posedge CLK) (-0.057::-0.046))
|
||||
(SETUP INIT (posedge CLK) (0.345::0.428))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
|
|
@ -274,7 +278,11 @@
|
|||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD CE (posedge CLK) (-0.011::-0.009))
|
||||
(HOLD DIN (posedge CLK) (0.194::0.241))
|
||||
(HOLD INIT (posedge CLK) (-0.074::-0.060))
|
||||
(SETUP CE (posedge CLK) (0.088::0.109))
|
||||
(SETUP DIN (posedge CLK) (-0.055::-0.045))
|
||||
(SETUP INIT (posedge CLK) (0.345::0.428))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
|
|
@ -303,6 +311,10 @@
|
|||
(IOPATH D Q (0.073::0.092)(0.213::0.264))
|
||||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD DIN (posedge CLK) (0.194::0.241))
|
||||
(SETUP DIN (posedge CLK) (-0.068::-0.056))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "REG_INIT_LAT_LOGIC_AND")
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
(CELL
|
||||
(CELLTYPE "CARRY4")
|
||||
|
|
@ -245,7 +245,11 @@
|
|||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD CE (posedge CLK) (-0.011::-0.009))
|
||||
(HOLD DIN (posedge CLK) (0.181::0.225))
|
||||
(HOLD INIT (posedge CLK) (-0.074::-0.060))
|
||||
(SETUP CE (posedge CLK) (0.088::0.109))
|
||||
(SETUP DIN (posedge CLK) (-0.057::-0.046))
|
||||
(SETUP INIT (posedge CLK) (0.345::0.428))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
|
|
@ -274,7 +278,11 @@
|
|||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD CE (posedge CLK) (-0.011::-0.009))
|
||||
(HOLD DIN (posedge CLK) (0.194::0.241))
|
||||
(HOLD INIT (posedge CLK) (-0.074::-0.060))
|
||||
(SETUP CE (posedge CLK) (0.088::0.109))
|
||||
(SETUP DIN (posedge CLK) (-0.055::-0.045))
|
||||
(SETUP INIT (posedge CLK) (0.345::0.428))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
|
|
@ -303,6 +311,10 @@
|
|||
(IOPATH D Q (0.073::0.092)(0.213::0.264))
|
||||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD DIN (posedge CLK) (0.194::0.241))
|
||||
(SETUP DIN (posedge CLK) (-0.068::-0.056))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "REG_INIT_LAT_LOGIC_AND")
|
||||
|
|
@ -707,7 +719,11 @@
|
|||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD CE (posedge CLK) (-0.007::-0.005))
|
||||
(HOLD DIN (posedge CLK) (0.194::0.241))
|
||||
(HOLD INIT (posedge CLK) (-0.050::-0.041))
|
||||
(SETUP CE (posedge CLK) (0.088::0.109))
|
||||
(SETUP DIN (posedge CLK) (-0.074::-0.060))
|
||||
(SETUP INIT (posedge CLK) (0.445::0.552))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
|
|
@ -740,16 +756,16 @@
|
|||
(SETUP WA4 (posedge CLK) (0.248::0.208))
|
||||
(HOLD WA5 (posedge CLK) (0.332::0.314))
|
||||
(SETUP WA5 (posedge CLK) (0.236::0.245))
|
||||
(HOLD CLK (posedge CLK) (0.008::0.010))
|
||||
(SETUP CLK (posedge CLK) (0.527::0.654))
|
||||
(HOLD WE (posedge CLK) (0.008::0.010))
|
||||
(SETUP WE (posedge CLK) (0.527::0.654))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "LUT_OR_MEM5SHFREG")
|
||||
(INSTANCE SLICEM)
|
||||
(TIMINGCHECK
|
||||
(HOLD CLK (posedge CLK) (0.011::0.014))
|
||||
(SETUP CLK (posedge CLK) (0.514::0.638))
|
||||
(HOLD WE (posedge CLK) (0.011::0.014))
|
||||
(SETUP WE (posedge CLK) (0.514::0.638))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
|
|
@ -766,22 +782,22 @@
|
|||
(SETUP WA4 (posedge CLK) (0.248::0.208))
|
||||
(HOLD WA5 (posedge CLK) (0.332::0.314))
|
||||
(SETUP WA5 (posedge CLK) (0.236::0.245))
|
||||
(HOLD CLK (posedge CLK) (0.213::0.244))
|
||||
(SETUP CLK (posedge CLK) (0.302::0.362))
|
||||
(HOLD WA6 (posedge CLK) (0.213::0.244))
|
||||
(SETUP WA6 (posedge CLK) (0.302::0.362))
|
||||
(HOLD WA7 (posedge CLK) (0.184::0.228))
|
||||
(SETUP WA7 (posedge CLK) (0.496::0.616))
|
||||
(HOLD CLK (posedge CLK) (0.199::0.247))
|
||||
(SETUP CLK (posedge CLK) (0.511::0.633))
|
||||
(HOLD CLK (posedge CLK) (0.008::0.010))
|
||||
(SETUP CLK (posedge CLK) (0.527::0.654))
|
||||
(HOLD WA8 (posedge CLK) (0.199::0.247))
|
||||
(SETUP WA8 (posedge CLK) (0.511::0.633))
|
||||
(HOLD WE (posedge CLK) (0.008::0.010))
|
||||
(SETUP WE (posedge CLK) (0.527::0.654))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "LUT_OR_MEM6SHFREG")
|
||||
(INSTANCE SLICEM)
|
||||
(TIMINGCHECK
|
||||
(HOLD CLK (posedge CLK) (0.011::0.014))
|
||||
(SETUP CLK (posedge CLK) (0.514::0.638))
|
||||
(HOLD WE (posedge CLK) (0.011::0.014))
|
||||
(SETUP WE (posedge CLK) (0.514::0.638))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
|
|
@ -794,7 +810,11 @@
|
|||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD CE (posedge CLK) (-0.007::-0.005))
|
||||
(HOLD DIN (posedge CLK) (0.211::0.262))
|
||||
(HOLD INIT (posedge CLK) (-0.050::-0.041))
|
||||
(SETUP CE (posedge CLK) (0.088::0.109))
|
||||
(SETUP DIN (posedge CLK) (-0.074::-0.060))
|
||||
(SETUP INIT (posedge CLK) (0.445::0.552))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
|
|
@ -823,6 +843,10 @@
|
|||
(IOPATH D Q (0.075::0.094)(0.214::0.265))
|
||||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD DIN (posedge CLK) (0.211::0.262))
|
||||
(SETUP DIN (posedge CLK) (-0.078::-0.064))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "REG_INIT_LAT_LOGIC_AND")
|
||||
|
|
@ -858,8 +882,8 @@
|
|||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD CLK (posedge CLK) (0.155::0.192))
|
||||
(SETUP CLK (posedge CLK) (0.231::0.287))
|
||||
(HOLD DI1 (posedge CLK) (0.155::0.192))
|
||||
(SETUP DI1 (posedge CLK) (0.231::0.287))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
|
|
@ -871,8 +895,8 @@
|
|||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD CLK (posedge CLK) (0.075::0.093))
|
||||
(SETUP CLK (posedge CLK) (0.137::0.170))
|
||||
(HOLD DI1 (posedge CLK) (0.075::0.093))
|
||||
(SETUP DI1 (posedge CLK) (0.137::0.170))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
|
|
@ -890,8 +914,8 @@
|
|||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD CLK (posedge CLK) (0.155::0.192))
|
||||
(SETUP CLK (posedge CLK) (0.366::0.453))
|
||||
(HOLD DI1 (posedge CLK) (0.155::0.192))
|
||||
(SETUP DI1 (posedge CLK) (0.366::0.453))
|
||||
(HOLD DI2 (posedge CLK) (0.098::0.122))
|
||||
(SETUP DI2 (posedge CLK) (0.309::0.384))
|
||||
)
|
||||
|
|
@ -906,8 +930,8 @@
|
|||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD CLK (posedge CLK) (0.075::0.093))
|
||||
(SETUP CLK (posedge CLK) (0.137::0.170))
|
||||
(HOLD DI1 (posedge CLK) (0.075::0.093))
|
||||
(SETUP DI1 (posedge CLK) (0.137::0.170))
|
||||
(HOLD DI2 (posedge CLK) (0.076::0.094))
|
||||
(SETUP DI2 (posedge CLK) (0.140::0.173))
|
||||
)
|
||||
|
|
@ -926,8 +950,8 @@
|
|||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD CLK (posedge CLK) (0.154::0.191))
|
||||
(SETUP CLK (posedge CLK) (0.250::0.311))
|
||||
(HOLD DI1 (posedge CLK) (0.154::0.191))
|
||||
(SETUP DI1 (posedge CLK) (0.250::0.311))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
|
|
@ -939,8 +963,8 @@
|
|||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD CLK (posedge CLK) (0.070::0.087))
|
||||
(SETUP CLK (posedge CLK) (0.126::0.156))
|
||||
(HOLD DI1 (posedge CLK) (0.070::0.087))
|
||||
(SETUP DI1 (posedge CLK) (0.126::0.156))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
|
|
@ -958,8 +982,8 @@
|
|||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD CLK (posedge CLK) (0.154::0.191))
|
||||
(SETUP CLK (posedge CLK) (0.372::0.461))
|
||||
(HOLD DI1 (posedge CLK) (0.154::0.191))
|
||||
(SETUP DI1 (posedge CLK) (0.372::0.461))
|
||||
(HOLD DI2 (posedge CLK) (0.107::0.133))
|
||||
(SETUP DI2 (posedge CLK) (0.286::0.354))
|
||||
)
|
||||
|
|
@ -974,8 +998,8 @@
|
|||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD CLK (posedge CLK) (0.070::0.087))
|
||||
(SETUP CLK (posedge CLK) (0.126::0.156))
|
||||
(HOLD DI1 (posedge CLK) (0.070::0.087))
|
||||
(SETUP DI1 (posedge CLK) (0.126::0.156))
|
||||
(HOLD DI2 (posedge CLK) (0.089::0.110))
|
||||
(SETUP DI2 (posedge CLK) (0.143::0.178))
|
||||
)
|
||||
|
|
@ -994,8 +1018,8 @@
|
|||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD CLK (posedge CLK) (0.152::0.189))
|
||||
(SETUP CLK (posedge CLK) (0.243::0.301))
|
||||
(HOLD DI1 (posedge CLK) (0.152::0.189))
|
||||
(SETUP DI1 (posedge CLK) (0.243::0.301))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
|
|
@ -1007,8 +1031,8 @@
|
|||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD CLK (posedge CLK) (0.058::0.072))
|
||||
(SETUP CLK (posedge CLK) (0.117::0.145))
|
||||
(HOLD DI1 (posedge CLK) (0.058::0.072))
|
||||
(SETUP DI1 (posedge CLK) (0.117::0.145))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
|
|
@ -1026,8 +1050,8 @@
|
|||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD CLK (posedge CLK) (0.152::0.189))
|
||||
(SETUP CLK (posedge CLK) (0.368::0.457))
|
||||
(HOLD DI1 (posedge CLK) (0.152::0.189))
|
||||
(SETUP DI1 (posedge CLK) (0.368::0.457))
|
||||
(HOLD DI2 (posedge CLK) (0.091::0.113))
|
||||
(SETUP DI2 (posedge CLK) (0.302::0.375))
|
||||
)
|
||||
|
|
@ -1042,8 +1066,8 @@
|
|||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD CLK (posedge CLK) (0.058::0.072))
|
||||
(SETUP CLK (posedge CLK) (0.117::0.145))
|
||||
(HOLD DI1 (posedge CLK) (0.058::0.072))
|
||||
(SETUP DI1 (posedge CLK) (0.117::0.145))
|
||||
(HOLD DI2 (posedge CLK) (0.062::0.077))
|
||||
(SETUP DI2 (posedge CLK) (0.116::0.144))
|
||||
)
|
||||
|
|
@ -1062,8 +1086,8 @@
|
|||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD CLK (posedge CLK) (0.153::0.190))
|
||||
(SETUP CLK (posedge CLK) (0.111::0.137))
|
||||
(HOLD DI1 (posedge CLK) (0.153::0.190))
|
||||
(SETUP DI1 (posedge CLK) (0.111::0.137))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
|
|
@ -1075,8 +1099,8 @@
|
|||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD CLK (posedge CLK) (0.217::0.269))
|
||||
(SETUP CLK (posedge CLK) (-0.040::-0.033))
|
||||
(HOLD DI1 (posedge CLK) (0.217::0.269))
|
||||
(SETUP DI1 (posedge CLK) (-0.040::-0.033))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
|
|
@ -1094,8 +1118,8 @@
|
|||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD CLK (posedge CLK) (0.153::0.190))
|
||||
(SETUP CLK (posedge CLK) (0.250::0.310))
|
||||
(HOLD DI1 (posedge CLK) (0.153::0.190))
|
||||
(SETUP DI1 (posedge CLK) (0.250::0.310))
|
||||
(HOLD DI2 (posedge CLK) (0.106::0.132))
|
||||
(SETUP DI2 (posedge CLK) (0.269::0.334))
|
||||
)
|
||||
|
|
@ -1110,8 +1134,8 @@
|
|||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD CLK (posedge CLK) (0.217::0.269))
|
||||
(SETUP CLK (posedge CLK) (-0.040::-0.033))
|
||||
(HOLD DI1 (posedge CLK) (0.217::0.269))
|
||||
(SETUP DI1 (posedge CLK) (-0.040::-0.033))
|
||||
(HOLD DI2 (posedge CLK) (0.091::0.112))
|
||||
(SETUP DI2 (posedge CLK) (0.133::0.165))
|
||||
)
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
(CELL
|
||||
(CELLTYPE "CARRY4")
|
||||
|
|
@ -245,7 +245,11 @@
|
|||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD CE (posedge CLK) (-0.011::-0.009))
|
||||
(HOLD DIN (posedge CLK) (0.181::0.225))
|
||||
(HOLD INIT (posedge CLK) (-0.074::-0.060))
|
||||
(SETUP CE (posedge CLK) (0.088::0.109))
|
||||
(SETUP DIN (posedge CLK) (-0.057::-0.046))
|
||||
(SETUP INIT (posedge CLK) (0.345::0.428))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
|
|
@ -274,7 +278,11 @@
|
|||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD CE (posedge CLK) (-0.011::-0.009))
|
||||
(HOLD DIN (posedge CLK) (0.194::0.241))
|
||||
(HOLD INIT (posedge CLK) (-0.074::-0.060))
|
||||
(SETUP CE (posedge CLK) (0.088::0.109))
|
||||
(SETUP DIN (posedge CLK) (-0.055::-0.045))
|
||||
(SETUP INIT (posedge CLK) (0.345::0.428))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
|
|
@ -303,6 +311,10 @@
|
|||
(IOPATH D Q (0.073::0.092)(0.213::0.264))
|
||||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD DIN (posedge CLK) (0.194::0.241))
|
||||
(SETUP DIN (posedge CLK) (-0.068::-0.056))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "REG_INIT_LAT_LOGIC_AND")
|
||||
|
|
@ -707,7 +719,11 @@
|
|||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD CE (posedge CLK) (-0.007::-0.005))
|
||||
(HOLD DIN (posedge CLK) (0.194::0.241))
|
||||
(HOLD INIT (posedge CLK) (-0.050::-0.041))
|
||||
(SETUP CE (posedge CLK) (0.088::0.109))
|
||||
(SETUP DIN (posedge CLK) (-0.074::-0.060))
|
||||
(SETUP INIT (posedge CLK) (0.445::0.552))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
|
|
@ -740,16 +756,16 @@
|
|||
(SETUP WA4 (posedge CLK) (0.248::0.208))
|
||||
(HOLD WA5 (posedge CLK) (0.332::0.314))
|
||||
(SETUP WA5 (posedge CLK) (0.236::0.245))
|
||||
(HOLD CLK (posedge CLK) (0.008::0.010))
|
||||
(SETUP CLK (posedge CLK) (0.527::0.654))
|
||||
(HOLD WE (posedge CLK) (0.008::0.010))
|
||||
(SETUP WE (posedge CLK) (0.527::0.654))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "LUT_OR_MEM5SHFREG")
|
||||
(INSTANCE SLICEM)
|
||||
(TIMINGCHECK
|
||||
(HOLD CLK (posedge CLK) (0.011::0.014))
|
||||
(SETUP CLK (posedge CLK) (0.514::0.638))
|
||||
(HOLD WE (posedge CLK) (0.011::0.014))
|
||||
(SETUP WE (posedge CLK) (0.514::0.638))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
|
|
@ -766,22 +782,22 @@
|
|||
(SETUP WA4 (posedge CLK) (0.248::0.208))
|
||||
(HOLD WA5 (posedge CLK) (0.332::0.314))
|
||||
(SETUP WA5 (posedge CLK) (0.236::0.245))
|
||||
(HOLD CLK (posedge CLK) (0.213::0.244))
|
||||
(SETUP CLK (posedge CLK) (0.302::0.362))
|
||||
(HOLD WA6 (posedge CLK) (0.213::0.244))
|
||||
(SETUP WA6 (posedge CLK) (0.302::0.362))
|
||||
(HOLD WA7 (posedge CLK) (0.184::0.228))
|
||||
(SETUP WA7 (posedge CLK) (0.496::0.616))
|
||||
(HOLD CLK (posedge CLK) (0.199::0.247))
|
||||
(SETUP CLK (posedge CLK) (0.511::0.633))
|
||||
(HOLD CLK (posedge CLK) (0.008::0.010))
|
||||
(SETUP CLK (posedge CLK) (0.527::0.654))
|
||||
(HOLD WA8 (posedge CLK) (0.199::0.247))
|
||||
(SETUP WA8 (posedge CLK) (0.511::0.633))
|
||||
(HOLD WE (posedge CLK) (0.008::0.010))
|
||||
(SETUP WE (posedge CLK) (0.527::0.654))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "LUT_OR_MEM6SHFREG")
|
||||
(INSTANCE SLICEM)
|
||||
(TIMINGCHECK
|
||||
(HOLD CLK (posedge CLK) (0.011::0.014))
|
||||
(SETUP CLK (posedge CLK) (0.514::0.638))
|
||||
(HOLD WE (posedge CLK) (0.011::0.014))
|
||||
(SETUP WE (posedge CLK) (0.514::0.638))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
|
|
@ -794,7 +810,11 @@
|
|||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD CE (posedge CLK) (-0.007::-0.005))
|
||||
(HOLD DIN (posedge CLK) (0.211::0.262))
|
||||
(HOLD INIT (posedge CLK) (-0.050::-0.041))
|
||||
(SETUP CE (posedge CLK) (0.088::0.109))
|
||||
(SETUP DIN (posedge CLK) (-0.074::-0.060))
|
||||
(SETUP INIT (posedge CLK) (0.445::0.552))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
|
|
@ -823,6 +843,10 @@
|
|||
(IOPATH D Q (0.075::0.094)(0.214::0.265))
|
||||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD DIN (posedge CLK) (0.211::0.262))
|
||||
(SETUP DIN (posedge CLK) (-0.078::-0.064))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "REG_INIT_LAT_LOGIC_AND")
|
||||
|
|
@ -858,8 +882,8 @@
|
|||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD CLK (posedge CLK) (0.155::0.192))
|
||||
(SETUP CLK (posedge CLK) (0.231::0.287))
|
||||
(HOLD DI1 (posedge CLK) (0.155::0.192))
|
||||
(SETUP DI1 (posedge CLK) (0.231::0.287))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
|
|
@ -871,8 +895,8 @@
|
|||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD CLK (posedge CLK) (0.075::0.093))
|
||||
(SETUP CLK (posedge CLK) (0.137::0.170))
|
||||
(HOLD DI1 (posedge CLK) (0.075::0.093))
|
||||
(SETUP DI1 (posedge CLK) (0.137::0.170))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
|
|
@ -890,8 +914,8 @@
|
|||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD CLK (posedge CLK) (0.155::0.192))
|
||||
(SETUP CLK (posedge CLK) (0.366::0.453))
|
||||
(HOLD DI1 (posedge CLK) (0.155::0.192))
|
||||
(SETUP DI1 (posedge CLK) (0.366::0.453))
|
||||
(HOLD DI2 (posedge CLK) (0.098::0.122))
|
||||
(SETUP DI2 (posedge CLK) (0.309::0.384))
|
||||
)
|
||||
|
|
@ -906,8 +930,8 @@
|
|||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD CLK (posedge CLK) (0.075::0.093))
|
||||
(SETUP CLK (posedge CLK) (0.137::0.170))
|
||||
(HOLD DI1 (posedge CLK) (0.075::0.093))
|
||||
(SETUP DI1 (posedge CLK) (0.137::0.170))
|
||||
(HOLD DI2 (posedge CLK) (0.076::0.094))
|
||||
(SETUP DI2 (posedge CLK) (0.140::0.173))
|
||||
)
|
||||
|
|
@ -926,8 +950,8 @@
|
|||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD CLK (posedge CLK) (0.154::0.191))
|
||||
(SETUP CLK (posedge CLK) (0.250::0.311))
|
||||
(HOLD DI1 (posedge CLK) (0.154::0.191))
|
||||
(SETUP DI1 (posedge CLK) (0.250::0.311))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
|
|
@ -939,8 +963,8 @@
|
|||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD CLK (posedge CLK) (0.070::0.087))
|
||||
(SETUP CLK (posedge CLK) (0.126::0.156))
|
||||
(HOLD DI1 (posedge CLK) (0.070::0.087))
|
||||
(SETUP DI1 (posedge CLK) (0.126::0.156))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
|
|
@ -958,8 +982,8 @@
|
|||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD CLK (posedge CLK) (0.154::0.191))
|
||||
(SETUP CLK (posedge CLK) (0.372::0.461))
|
||||
(HOLD DI1 (posedge CLK) (0.154::0.191))
|
||||
(SETUP DI1 (posedge CLK) (0.372::0.461))
|
||||
(HOLD DI2 (posedge CLK) (0.107::0.133))
|
||||
(SETUP DI2 (posedge CLK) (0.286::0.354))
|
||||
)
|
||||
|
|
@ -974,8 +998,8 @@
|
|||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD CLK (posedge CLK) (0.070::0.087))
|
||||
(SETUP CLK (posedge CLK) (0.126::0.156))
|
||||
(HOLD DI1 (posedge CLK) (0.070::0.087))
|
||||
(SETUP DI1 (posedge CLK) (0.126::0.156))
|
||||
(HOLD DI2 (posedge CLK) (0.089::0.110))
|
||||
(SETUP DI2 (posedge CLK) (0.143::0.178))
|
||||
)
|
||||
|
|
@ -994,8 +1018,8 @@
|
|||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD CLK (posedge CLK) (0.152::0.189))
|
||||
(SETUP CLK (posedge CLK) (0.243::0.301))
|
||||
(HOLD DI1 (posedge CLK) (0.152::0.189))
|
||||
(SETUP DI1 (posedge CLK) (0.243::0.301))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
|
|
@ -1007,8 +1031,8 @@
|
|||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD CLK (posedge CLK) (0.058::0.072))
|
||||
(SETUP CLK (posedge CLK) (0.117::0.145))
|
||||
(HOLD DI1 (posedge CLK) (0.058::0.072))
|
||||
(SETUP DI1 (posedge CLK) (0.117::0.145))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
|
|
@ -1026,8 +1050,8 @@
|
|||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD CLK (posedge CLK) (0.152::0.189))
|
||||
(SETUP CLK (posedge CLK) (0.368::0.457))
|
||||
(HOLD DI1 (posedge CLK) (0.152::0.189))
|
||||
(SETUP DI1 (posedge CLK) (0.368::0.457))
|
||||
(HOLD DI2 (posedge CLK) (0.091::0.113))
|
||||
(SETUP DI2 (posedge CLK) (0.302::0.375))
|
||||
)
|
||||
|
|
@ -1042,8 +1066,8 @@
|
|||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD CLK (posedge CLK) (0.058::0.072))
|
||||
(SETUP CLK (posedge CLK) (0.117::0.145))
|
||||
(HOLD DI1 (posedge CLK) (0.058::0.072))
|
||||
(SETUP DI1 (posedge CLK) (0.117::0.145))
|
||||
(HOLD DI2 (posedge CLK) (0.062::0.077))
|
||||
(SETUP DI2 (posedge CLK) (0.116::0.144))
|
||||
)
|
||||
|
|
@ -1062,8 +1086,8 @@
|
|||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD CLK (posedge CLK) (0.153::0.190))
|
||||
(SETUP CLK (posedge CLK) (0.111::0.137))
|
||||
(HOLD DI1 (posedge CLK) (0.153::0.190))
|
||||
(SETUP DI1 (posedge CLK) (0.111::0.137))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
|
|
@ -1075,8 +1099,8 @@
|
|||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD CLK (posedge CLK) (0.217::0.269))
|
||||
(SETUP CLK (posedge CLK) (-0.040::-0.033))
|
||||
(HOLD DI1 (posedge CLK) (0.217::0.269))
|
||||
(SETUP DI1 (posedge CLK) (-0.040::-0.033))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
|
|
@ -1094,8 +1118,8 @@
|
|||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD CLK (posedge CLK) (0.153::0.190))
|
||||
(SETUP CLK (posedge CLK) (0.250::0.310))
|
||||
(HOLD DI1 (posedge CLK) (0.153::0.190))
|
||||
(SETUP DI1 (posedge CLK) (0.250::0.310))
|
||||
(HOLD DI2 (posedge CLK) (0.106::0.132))
|
||||
(SETUP DI2 (posedge CLK) (0.269::0.334))
|
||||
)
|
||||
|
|
@ -1110,8 +1134,8 @@
|
|||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD CLK (posedge CLK) (0.217::0.269))
|
||||
(SETUP CLK (posedge CLK) (-0.040::-0.033))
|
||||
(HOLD DI1 (posedge CLK) (0.217::0.269))
|
||||
(SETUP DI1 (posedge CLK) (-0.040::-0.033))
|
||||
(HOLD DI2 (posedge CLK) (0.091::0.112))
|
||||
(SETUP DI2 (posedge CLK) (0.133::0.165))
|
||||
)
|
||||
|
|
|
|||
|
|
@ -1,6 +1,15 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
(CELL
|
||||
(CELLTYPE "BUFGCTRL")
|
||||
(INSTANCE BUFGCTRL)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH I O (0.026::0.029)(0.091::0.096))
|
||||
)
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
)
|
||||
|
|
@ -1,6 +1,15 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
(CELL
|
||||
(CELLTYPE "BUFGCTRL")
|
||||
(INSTANCE BUFGCTRL)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH I O (0.026::0.029)(0.091::0.096))
|
||||
)
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
)
|
||||
|
|
@ -1,17 +1,8 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
(CELL
|
||||
(CELLTYPE "BUFHCE")
|
||||
(INSTANCE BUFHCE)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH I O (0.020::0.043)(0.081::0.127))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "BUFHCE_CE_TYPE_ASYNC")
|
||||
(INSTANCE BUFHCE)
|
||||
|
|
|
|||
|
|
@ -1,17 +1,8 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
(CELL
|
||||
(CELLTYPE "BUFHCE")
|
||||
(INSTANCE BUFHCE)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH I O (0.020::0.043)(0.081::0.127))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "BUFHCE_CE_TYPE_ASYNC")
|
||||
(INSTANCE BUFHCE)
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
)
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
)
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
)
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
)
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
)
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
)
|
||||
|
|
@ -1,230 +1,66 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
(CELL
|
||||
(CELLTYPE "IN_FIFO_IN_FIFOIN_FIFO")
|
||||
(INSTANCE IN_FIFO)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH RDCLK ALMOSTEMPTY (0.196::0.226)(0.462::0.531))
|
||||
(IOPATH RDCLK EMPTY (0.193::0.222)(0.536::0.617))
|
||||
(IOPATH WRCLK ALMOSTFULL (0.153::0.176)(0.462::0.531))
|
||||
(IOPATH WRCLK FULL (0.152::0.175)(0.665::0.765))
|
||||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD RDCLK (posedge RDCLK) (0.015::0.018))
|
||||
(SETUP RDCLK (posedge RDCLK) (0.509::0.586))
|
||||
(HOLD D0 (posedge WRCLK) (-0.080::-0.070))
|
||||
(SETUP D0 (posedge WRCLK) (0.473::0.544))
|
||||
(HOLD D1 (posedge WRCLK) (-0.069::-0.060))
|
||||
(SETUP D1 (posedge WRCLK) (0.496::0.571))
|
||||
(HOLD D2 (posedge WRCLK) (-0.073::-0.063))
|
||||
(SETUP D2 (posedge WRCLK) (0.456::0.524))
|
||||
(HOLD D3 (posedge WRCLK) (-0.050::-0.043))
|
||||
(SETUP D3 (posedge WRCLK) (0.453::0.521))
|
||||
(HOLD RDEN (posedge RDCLK) (0.015::0.018))
|
||||
(SETUP RDEN (posedge RDCLK) (0.509::0.586))
|
||||
(HOLD SCANENB (posedge RDCLK) (0.537::0.618))
|
||||
(SETUP SCANENB (posedge RDCLK) (0.976::1.123))
|
||||
(HOLD SCANENB (posedge WRCLK) (0.537::0.618))
|
||||
(SETUP SCANENB (posedge WRCLK) (0.976::1.123))
|
||||
(HOLD SCANIN (posedge RDCLK) (0.537::0.618))
|
||||
(SETUP SCANIN (posedge RDCLK) (0.976::1.123))
|
||||
(HOLD SCANIN (posedge WRCLK) (0.537::0.618))
|
||||
(SETUP SCANIN (posedge WRCLK) (0.976::1.123))
|
||||
(HOLD WREN (posedge WRCLK) (-0.019::-0.016))
|
||||
(SETUP WREN (posedge WRCLK) (0.461::0.530))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "IN_FIFO_IN_FIFOIN_FIFO_D0")
|
||||
(INSTANCE IN_FIFO)
|
||||
(TIMINGCHECK
|
||||
(HOLD WRCLK (posedge WRCLK) (-0.080::-0.070))
|
||||
(SETUP WRCLK (posedge WRCLK) (0.473::0.544))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "IN_FIFO_IN_FIFOIN_FIFO_D1")
|
||||
(INSTANCE IN_FIFO)
|
||||
(TIMINGCHECK
|
||||
(HOLD WRCLK (posedge WRCLK) (-0.069::-0.060))
|
||||
(SETUP WRCLK (posedge WRCLK) (0.496::0.571))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "IN_FIFO_IN_FIFOIN_FIFO_D2")
|
||||
(INSTANCE IN_FIFO)
|
||||
(TIMINGCHECK
|
||||
(HOLD WRCLK (posedge WRCLK) (-0.073::-0.063))
|
||||
(SETUP WRCLK (posedge WRCLK) (0.456::0.524))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "IN_FIFO_IN_FIFOIN_FIFO_D3")
|
||||
(INSTANCE IN_FIFO)
|
||||
(TIMINGCHECK
|
||||
(HOLD WRCLK (posedge WRCLK) (-0.050::-0.043))
|
||||
(SETUP WRCLK (posedge WRCLK) (0.453::0.521))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "IN_FIFO_IN_FIFOIN_FIFO_D4")
|
||||
(INSTANCE IN_FIFO)
|
||||
(TIMINGCHECK
|
||||
(HOLD WRCLK (posedge WRCLK) (-0.032::-0.028))
|
||||
(SETUP WRCLK (posedge WRCLK) (0.413::0.475))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "IN_FIFO_IN_FIFOIN_FIFO_D5")
|
||||
(INSTANCE IN_FIFO)
|
||||
(TIMINGCHECK
|
||||
(HOLD WRCLK (posedge WRCLK) (-0.026::-0.023))
|
||||
(SETUP WRCLK (posedge WRCLK) (0.404::0.465))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "IN_FIFO_IN_FIFOIN_FIFO_D6")
|
||||
(INSTANCE IN_FIFO)
|
||||
(TIMINGCHECK
|
||||
(HOLD WRCLK (posedge WRCLK) (-0.019::-0.016))
|
||||
(SETUP WRCLK (posedge WRCLK) (0.414::0.476))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "IN_FIFO_IN_FIFOIN_FIFO_D7")
|
||||
(INSTANCE IN_FIFO)
|
||||
(TIMINGCHECK
|
||||
(HOLD WRCLK (posedge WRCLK) (-0.032::-0.028))
|
||||
(SETUP WRCLK (posedge WRCLK) (0.414::0.476))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "IN_FIFO_IN_FIFOIN_FIFO_D8")
|
||||
(INSTANCE IN_FIFO)
|
||||
(TIMINGCHECK
|
||||
(HOLD WRCLK (posedge WRCLK) (-0.043::-0.037))
|
||||
(SETUP WRCLK (posedge WRCLK) (0.429::0.494))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "IN_FIFO_IN_FIFOIN_FIFO_D9")
|
||||
(INSTANCE IN_FIFO)
|
||||
(TIMINGCHECK
|
||||
(HOLD WRCLK (posedge WRCLK) (-0.040::-0.035))
|
||||
(SETUP WRCLK (posedge WRCLK) (0.454::0.522))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "IN_FIFO_IN_FIFOIN_FIFO_SCANIN")
|
||||
(INSTANCE IN_FIFO)
|
||||
(TIMINGCHECK
|
||||
(HOLD RDCLK (posedge RDCLK) (0.537::0.618))
|
||||
(SETUP RDCLK (posedge RDCLK) (0.976::1.123))
|
||||
(HOLD WRCLK (posedge WRCLK) (0.537::0.618))
|
||||
(SETUP WRCLK (posedge WRCLK) (0.976::1.123))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OUT_FIFO_OUT_FIFOOUT_FIFO")
|
||||
(INSTANCE OUT_FIFO)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH RDCLK ALMOSTEMPTY (0.131::0.151)(0.282::0.324))
|
||||
(IOPATH RDCLK EMPTY (0.137::0.157)(0.414::0.476))
|
||||
(IOPATH WRCLK ALMOSTFULL (0.138::0.159)(0.300::0.345))
|
||||
(IOPATH WRCLK FULL (0.137::0.157)(0.296::0.340))
|
||||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD D0 (posedge WRCLK) (-0.022::-0.019))
|
||||
(SETUP D0 (posedge WRCLK) (0.381::0.438))
|
||||
(HOLD D1 (posedge WRCLK) (-0.022::-0.019))
|
||||
(SETUP D1 (posedge WRCLK) (0.381::0.438))
|
||||
(HOLD D2 (posedge WRCLK) (-0.019::-0.016))
|
||||
(SETUP D2 (posedge WRCLK) (0.367::0.422))
|
||||
(HOLD D3 (posedge WRCLK) (-0.012::-0.011))
|
||||
(SETUP D3 (posedge WRCLK) (0.354::0.408))
|
||||
(HOLD D4 (posedge WRCLK) (-0.012::-0.011))
|
||||
(SETUP D4 (posedge WRCLK) (0.344::0.395))
|
||||
(HOLD D5 (posedge WRCLK) (-0.011::-0.010))
|
||||
(SETUP D5 (posedge WRCLK) (0.354::0.408))
|
||||
(HOLD D6 (posedge WRCLK) (-0.013::-0.012))
|
||||
(SETUP D6 (posedge WRCLK) (0.344::0.395))
|
||||
(HOLD D7 (posedge WRCLK) (-0.013::-0.012))
|
||||
(SETUP D7 (posedge WRCLK) (0.344::0.395))
|
||||
(HOLD RDEN (posedge RDCLK) (-0.013::-0.012))
|
||||
(SETUP RDEN (posedge RDCLK) (0.566::0.651))
|
||||
(HOLD SCANENB (posedge RDCLK) (0.537::0.618))
|
||||
(SETUP SCANENB (posedge RDCLK) (0.976::1.123))
|
||||
(HOLD SCANENB (posedge WRCLK) (0.537::0.618))
|
||||
(SETUP SCANENB (posedge WRCLK) (0.976::1.123))
|
||||
(HOLD SCANIN (posedge RDCLK) (0.537::0.618))
|
||||
(SETUP SCANIN (posedge RDCLK) (0.976::1.123))
|
||||
(HOLD SCANIN (posedge WRCLK) (0.537::0.618))
|
||||
(SETUP SCANIN (posedge WRCLK) (0.976::1.123))
|
||||
(HOLD WREN (posedge WRCLK) (-0.030::-0.026))
|
||||
(SETUP WREN (posedge WRCLK) (0.373::0.430))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OUT_FIFO_OUT_FIFOOUT_FIFO_D0")
|
||||
(INSTANCE OUT_FIFO)
|
||||
(TIMINGCHECK
|
||||
(HOLD WRCLK (posedge WRCLK) (-0.022::-0.019))
|
||||
(SETUP WRCLK (posedge WRCLK) (0.381::0.438))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OUT_FIFO_OUT_FIFOOUT_FIFO_D1")
|
||||
(INSTANCE OUT_FIFO)
|
||||
(TIMINGCHECK
|
||||
(HOLD WRCLK (posedge WRCLK) (-0.022::-0.019))
|
||||
(SETUP WRCLK (posedge WRCLK) (0.381::0.438))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OUT_FIFO_OUT_FIFOOUT_FIFO_D2")
|
||||
(INSTANCE OUT_FIFO)
|
||||
(TIMINGCHECK
|
||||
(HOLD WRCLK (posedge WRCLK) (-0.019::-0.016))
|
||||
(SETUP WRCLK (posedge WRCLK) (0.367::0.422))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OUT_FIFO_OUT_FIFOOUT_FIFO_D3")
|
||||
(INSTANCE OUT_FIFO)
|
||||
(TIMINGCHECK
|
||||
(HOLD WRCLK (posedge WRCLK) (-0.012::-0.011))
|
||||
(SETUP WRCLK (posedge WRCLK) (0.354::0.408))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OUT_FIFO_OUT_FIFOOUT_FIFO_D4")
|
||||
(INSTANCE OUT_FIFO)
|
||||
(TIMINGCHECK
|
||||
(HOLD WRCLK (posedge WRCLK) (-0.012::-0.011))
|
||||
(SETUP WRCLK (posedge WRCLK) (0.344::0.395))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OUT_FIFO_OUT_FIFOOUT_FIFO_D5")
|
||||
(INSTANCE OUT_FIFO)
|
||||
(TIMINGCHECK
|
||||
(HOLD WRCLK (posedge WRCLK) (-0.011::-0.010))
|
||||
(SETUP WRCLK (posedge WRCLK) (0.354::0.408))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OUT_FIFO_OUT_FIFOOUT_FIFO_D6")
|
||||
(INSTANCE OUT_FIFO)
|
||||
(TIMINGCHECK
|
||||
(HOLD WRCLK (posedge WRCLK) (-0.013::-0.012))
|
||||
(SETUP WRCLK (posedge WRCLK) (0.344::0.395))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OUT_FIFO_OUT_FIFOOUT_FIFO_D7")
|
||||
(INSTANCE OUT_FIFO)
|
||||
(TIMINGCHECK
|
||||
(HOLD WRCLK (posedge WRCLK) (-0.013::-0.012))
|
||||
(SETUP WRCLK (posedge WRCLK) (0.344::0.395))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OUT_FIFO_OUT_FIFOOUT_FIFO_D8")
|
||||
(INSTANCE OUT_FIFO)
|
||||
(TIMINGCHECK
|
||||
(HOLD WRCLK (posedge WRCLK) (-0.013::-0.012))
|
||||
(SETUP WRCLK (posedge WRCLK) (0.344::0.395))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OUT_FIFO_OUT_FIFOOUT_FIFO_D9")
|
||||
(INSTANCE OUT_FIFO)
|
||||
(TIMINGCHECK
|
||||
(HOLD WRCLK (posedge WRCLK) (-0.013::-0.012))
|
||||
(SETUP WRCLK (posedge WRCLK) (0.344::0.395))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OUT_FIFO_OUT_FIFOOUT_FIFO_SCANIN")
|
||||
(INSTANCE OUT_FIFO)
|
||||
(TIMINGCHECK
|
||||
(HOLD RDCLK (posedge RDCLK) (0.537::0.618))
|
||||
(SETUP RDCLK (posedge RDCLK) (0.976::1.123))
|
||||
(HOLD WRCLK (posedge WRCLK) (0.537::0.618))
|
||||
(SETUP WRCLK (posedge WRCLK) (0.976::1.123))
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -1,230 +1,66 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
(CELL
|
||||
(CELLTYPE "IN_FIFO_IN_FIFOIN_FIFO")
|
||||
(INSTANCE IN_FIFO)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH RDCLK ALMOSTEMPTY (0.196::0.226)(0.462::0.531))
|
||||
(IOPATH RDCLK EMPTY (0.193::0.222)(0.536::0.617))
|
||||
(IOPATH WRCLK ALMOSTFULL (0.153::0.176)(0.462::0.531))
|
||||
(IOPATH WRCLK FULL (0.152::0.175)(0.665::0.765))
|
||||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD RDCLK (posedge RDCLK) (0.015::0.018))
|
||||
(SETUP RDCLK (posedge RDCLK) (0.509::0.586))
|
||||
(HOLD D0 (posedge WRCLK) (-0.080::-0.070))
|
||||
(SETUP D0 (posedge WRCLK) (0.473::0.544))
|
||||
(HOLD D1 (posedge WRCLK) (-0.069::-0.060))
|
||||
(SETUP D1 (posedge WRCLK) (0.496::0.571))
|
||||
(HOLD D2 (posedge WRCLK) (-0.073::-0.063))
|
||||
(SETUP D2 (posedge WRCLK) (0.456::0.524))
|
||||
(HOLD D3 (posedge WRCLK) (-0.050::-0.043))
|
||||
(SETUP D3 (posedge WRCLK) (0.453::0.521))
|
||||
(HOLD RDEN (posedge RDCLK) (0.015::0.018))
|
||||
(SETUP RDEN (posedge RDCLK) (0.509::0.586))
|
||||
(HOLD SCANENB (posedge RDCLK) (0.537::0.618))
|
||||
(SETUP SCANENB (posedge RDCLK) (0.976::1.123))
|
||||
(HOLD SCANENB (posedge WRCLK) (0.537::0.618))
|
||||
(SETUP SCANENB (posedge WRCLK) (0.976::1.123))
|
||||
(HOLD SCANIN (posedge RDCLK) (0.537::0.618))
|
||||
(SETUP SCANIN (posedge RDCLK) (0.976::1.123))
|
||||
(HOLD SCANIN (posedge WRCLK) (0.537::0.618))
|
||||
(SETUP SCANIN (posedge WRCLK) (0.976::1.123))
|
||||
(HOLD WREN (posedge WRCLK) (-0.019::-0.016))
|
||||
(SETUP WREN (posedge WRCLK) (0.461::0.530))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "IN_FIFO_IN_FIFOIN_FIFO_D0")
|
||||
(INSTANCE IN_FIFO)
|
||||
(TIMINGCHECK
|
||||
(HOLD WRCLK (posedge WRCLK) (-0.080::-0.070))
|
||||
(SETUP WRCLK (posedge WRCLK) (0.473::0.544))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "IN_FIFO_IN_FIFOIN_FIFO_D1")
|
||||
(INSTANCE IN_FIFO)
|
||||
(TIMINGCHECK
|
||||
(HOLD WRCLK (posedge WRCLK) (-0.069::-0.060))
|
||||
(SETUP WRCLK (posedge WRCLK) (0.496::0.571))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "IN_FIFO_IN_FIFOIN_FIFO_D2")
|
||||
(INSTANCE IN_FIFO)
|
||||
(TIMINGCHECK
|
||||
(HOLD WRCLK (posedge WRCLK) (-0.073::-0.063))
|
||||
(SETUP WRCLK (posedge WRCLK) (0.456::0.524))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "IN_FIFO_IN_FIFOIN_FIFO_D3")
|
||||
(INSTANCE IN_FIFO)
|
||||
(TIMINGCHECK
|
||||
(HOLD WRCLK (posedge WRCLK) (-0.050::-0.043))
|
||||
(SETUP WRCLK (posedge WRCLK) (0.453::0.521))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "IN_FIFO_IN_FIFOIN_FIFO_D4")
|
||||
(INSTANCE IN_FIFO)
|
||||
(TIMINGCHECK
|
||||
(HOLD WRCLK (posedge WRCLK) (-0.032::-0.028))
|
||||
(SETUP WRCLK (posedge WRCLK) (0.413::0.475))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "IN_FIFO_IN_FIFOIN_FIFO_D5")
|
||||
(INSTANCE IN_FIFO)
|
||||
(TIMINGCHECK
|
||||
(HOLD WRCLK (posedge WRCLK) (-0.026::-0.023))
|
||||
(SETUP WRCLK (posedge WRCLK) (0.404::0.465))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "IN_FIFO_IN_FIFOIN_FIFO_D6")
|
||||
(INSTANCE IN_FIFO)
|
||||
(TIMINGCHECK
|
||||
(HOLD WRCLK (posedge WRCLK) (-0.019::-0.016))
|
||||
(SETUP WRCLK (posedge WRCLK) (0.414::0.476))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "IN_FIFO_IN_FIFOIN_FIFO_D7")
|
||||
(INSTANCE IN_FIFO)
|
||||
(TIMINGCHECK
|
||||
(HOLD WRCLK (posedge WRCLK) (-0.032::-0.028))
|
||||
(SETUP WRCLK (posedge WRCLK) (0.414::0.476))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "IN_FIFO_IN_FIFOIN_FIFO_D8")
|
||||
(INSTANCE IN_FIFO)
|
||||
(TIMINGCHECK
|
||||
(HOLD WRCLK (posedge WRCLK) (-0.043::-0.037))
|
||||
(SETUP WRCLK (posedge WRCLK) (0.429::0.494))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "IN_FIFO_IN_FIFOIN_FIFO_D9")
|
||||
(INSTANCE IN_FIFO)
|
||||
(TIMINGCHECK
|
||||
(HOLD WRCLK (posedge WRCLK) (-0.040::-0.035))
|
||||
(SETUP WRCLK (posedge WRCLK) (0.454::0.522))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "IN_FIFO_IN_FIFOIN_FIFO_SCANIN")
|
||||
(INSTANCE IN_FIFO)
|
||||
(TIMINGCHECK
|
||||
(HOLD RDCLK (posedge RDCLK) (0.537::0.618))
|
||||
(SETUP RDCLK (posedge RDCLK) (0.976::1.123))
|
||||
(HOLD WRCLK (posedge WRCLK) (0.537::0.618))
|
||||
(SETUP WRCLK (posedge WRCLK) (0.976::1.123))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OUT_FIFO_OUT_FIFOOUT_FIFO")
|
||||
(INSTANCE OUT_FIFO)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH RDCLK ALMOSTEMPTY (0.131::0.151)(0.282::0.324))
|
||||
(IOPATH RDCLK EMPTY (0.137::0.157)(0.414::0.476))
|
||||
(IOPATH WRCLK ALMOSTFULL (0.138::0.159)(0.300::0.345))
|
||||
(IOPATH WRCLK FULL (0.137::0.157)(0.296::0.340))
|
||||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD D0 (posedge WRCLK) (-0.022::-0.019))
|
||||
(SETUP D0 (posedge WRCLK) (0.381::0.438))
|
||||
(HOLD D1 (posedge WRCLK) (-0.022::-0.019))
|
||||
(SETUP D1 (posedge WRCLK) (0.381::0.438))
|
||||
(HOLD D2 (posedge WRCLK) (-0.019::-0.016))
|
||||
(SETUP D2 (posedge WRCLK) (0.367::0.422))
|
||||
(HOLD D3 (posedge WRCLK) (-0.012::-0.011))
|
||||
(SETUP D3 (posedge WRCLK) (0.354::0.408))
|
||||
(HOLD D4 (posedge WRCLK) (-0.012::-0.011))
|
||||
(SETUP D4 (posedge WRCLK) (0.344::0.395))
|
||||
(HOLD D5 (posedge WRCLK) (-0.011::-0.010))
|
||||
(SETUP D5 (posedge WRCLK) (0.354::0.408))
|
||||
(HOLD D6 (posedge WRCLK) (-0.013::-0.012))
|
||||
(SETUP D6 (posedge WRCLK) (0.344::0.395))
|
||||
(HOLD D7 (posedge WRCLK) (-0.013::-0.012))
|
||||
(SETUP D7 (posedge WRCLK) (0.344::0.395))
|
||||
(HOLD RDEN (posedge RDCLK) (-0.013::-0.012))
|
||||
(SETUP RDEN (posedge RDCLK) (0.566::0.651))
|
||||
(HOLD SCANENB (posedge RDCLK) (0.537::0.618))
|
||||
(SETUP SCANENB (posedge RDCLK) (0.976::1.123))
|
||||
(HOLD SCANENB (posedge WRCLK) (0.537::0.618))
|
||||
(SETUP SCANENB (posedge WRCLK) (0.976::1.123))
|
||||
(HOLD SCANIN (posedge RDCLK) (0.537::0.618))
|
||||
(SETUP SCANIN (posedge RDCLK) (0.976::1.123))
|
||||
(HOLD SCANIN (posedge WRCLK) (0.537::0.618))
|
||||
(SETUP SCANIN (posedge WRCLK) (0.976::1.123))
|
||||
(HOLD WREN (posedge WRCLK) (-0.030::-0.026))
|
||||
(SETUP WREN (posedge WRCLK) (0.373::0.430))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OUT_FIFO_OUT_FIFOOUT_FIFO_D0")
|
||||
(INSTANCE OUT_FIFO)
|
||||
(TIMINGCHECK
|
||||
(HOLD WRCLK (posedge WRCLK) (-0.022::-0.019))
|
||||
(SETUP WRCLK (posedge WRCLK) (0.381::0.438))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OUT_FIFO_OUT_FIFOOUT_FIFO_D1")
|
||||
(INSTANCE OUT_FIFO)
|
||||
(TIMINGCHECK
|
||||
(HOLD WRCLK (posedge WRCLK) (-0.022::-0.019))
|
||||
(SETUP WRCLK (posedge WRCLK) (0.381::0.438))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OUT_FIFO_OUT_FIFOOUT_FIFO_D2")
|
||||
(INSTANCE OUT_FIFO)
|
||||
(TIMINGCHECK
|
||||
(HOLD WRCLK (posedge WRCLK) (-0.019::-0.016))
|
||||
(SETUP WRCLK (posedge WRCLK) (0.367::0.422))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OUT_FIFO_OUT_FIFOOUT_FIFO_D3")
|
||||
(INSTANCE OUT_FIFO)
|
||||
(TIMINGCHECK
|
||||
(HOLD WRCLK (posedge WRCLK) (-0.012::-0.011))
|
||||
(SETUP WRCLK (posedge WRCLK) (0.354::0.408))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OUT_FIFO_OUT_FIFOOUT_FIFO_D4")
|
||||
(INSTANCE OUT_FIFO)
|
||||
(TIMINGCHECK
|
||||
(HOLD WRCLK (posedge WRCLK) (-0.012::-0.011))
|
||||
(SETUP WRCLK (posedge WRCLK) (0.344::0.395))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OUT_FIFO_OUT_FIFOOUT_FIFO_D5")
|
||||
(INSTANCE OUT_FIFO)
|
||||
(TIMINGCHECK
|
||||
(HOLD WRCLK (posedge WRCLK) (-0.011::-0.010))
|
||||
(SETUP WRCLK (posedge WRCLK) (0.354::0.408))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OUT_FIFO_OUT_FIFOOUT_FIFO_D6")
|
||||
(INSTANCE OUT_FIFO)
|
||||
(TIMINGCHECK
|
||||
(HOLD WRCLK (posedge WRCLK) (-0.013::-0.012))
|
||||
(SETUP WRCLK (posedge WRCLK) (0.344::0.395))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OUT_FIFO_OUT_FIFOOUT_FIFO_D7")
|
||||
(INSTANCE OUT_FIFO)
|
||||
(TIMINGCHECK
|
||||
(HOLD WRCLK (posedge WRCLK) (-0.013::-0.012))
|
||||
(SETUP WRCLK (posedge WRCLK) (0.344::0.395))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OUT_FIFO_OUT_FIFOOUT_FIFO_D8")
|
||||
(INSTANCE OUT_FIFO)
|
||||
(TIMINGCHECK
|
||||
(HOLD WRCLK (posedge WRCLK) (-0.013::-0.012))
|
||||
(SETUP WRCLK (posedge WRCLK) (0.344::0.395))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OUT_FIFO_OUT_FIFOOUT_FIFO_D9")
|
||||
(INSTANCE OUT_FIFO)
|
||||
(TIMINGCHECK
|
||||
(HOLD WRCLK (posedge WRCLK) (-0.013::-0.012))
|
||||
(SETUP WRCLK (posedge WRCLK) (0.344::0.395))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OUT_FIFO_OUT_FIFOOUT_FIFO_SCANIN")
|
||||
(INSTANCE OUT_FIFO)
|
||||
(TIMINGCHECK
|
||||
(HOLD RDCLK (posedge RDCLK) (0.537::0.618))
|
||||
(SETUP RDCLK (posedge RDCLK) (0.976::1.123))
|
||||
(HOLD WRCLK (posedge WRCLK) (0.537::0.618))
|
||||
(SETUP WRCLK (posedge WRCLK) (0.976::1.123))
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
)
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
)
|
||||
|
|
@ -1,25 +1,27 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
(CELL
|
||||
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV")
|
||||
(INSTANCE MMCME2_ADV)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH DCLK DRDY (0.286::0.304)(0.927::0.984))
|
||||
(IOPATH PSCLK PSDONE (0.318::0.338)(0.758::0.805))
|
||||
(IOPATH RST CLKFBSTOPPED (0.348::0.370)(0.549::0.583))
|
||||
(IOPATH RST CLKINSTOPPED (0.348::0.370)(0.549::0.583))
|
||||
(IOPATH RST LOCKED (3.000::3.000)(3.000::3.000))
|
||||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD DADDR (posedge DCLK) (0.141::0.150))
|
||||
(SETUP DADDR (posedge DCLK) (1.527::1.622))
|
||||
(HOLD DEN (posedge DCLK) (0.000::0.000))
|
||||
(SETUP DEN (posedge DCLK) (2.156::2.290))
|
||||
(HOLD DCLK (posedge DCLK) (0.141::0.150))
|
||||
(SETUP DCLK (posedge DCLK) (1.527::1.622))
|
||||
(HOLD DI (posedge DCLK) (0.141::0.150))
|
||||
(SETUP DI (posedge DCLK) (1.527::1.622))
|
||||
(HOLD DWE (posedge DCLK) (0.141::0.150))
|
||||
(SETUP DWE (posedge DCLK) (1.527::1.622))
|
||||
(HOLD PSEN (posedge PSCLK) (0.000::0.000))
|
||||
(SETUP PSEN (posedge PSCLK) (0.979::1.040))
|
||||
(HOLD PSINCDEC (posedge PSCLK) (0.000::0.000))
|
||||
|
|
@ -27,245 +29,229 @@
|
|||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_CLKOUT4_CASCADE_FALSE_COMPENSATION_BUF_IN")
|
||||
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_00")
|
||||
(INSTANCE MMCME2_ADV)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLKIN1 CLKOUT4 (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH CLKIN2 CLKOUT4 (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH TMUX_MUX_SEL TMUXOUT (0.527::0.560)(0.979::1.040))
|
||||
(IOPATH TMUX_MUX_SEL TMUXOUT (0.527::0.560)(0.979::1.040))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_CLKOUT4_CASCADE_FALSE_COMPENSATION_EXTERNAL")
|
||||
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_01")
|
||||
(INSTANCE MMCME2_ADV)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLKIN1 CLKOUT4 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT4 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH TMUX_MUX_SEL TMUXOUT (0.527::0.560)(0.979::1.040))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_CLKOUT4_CASCADE_FALSE_COMPENSATION_INTERNAL")
|
||||
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_BUF_IN")
|
||||
(INSTANCE MMCME2_ADV)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLKIN1 CLKOUT4 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN2 CLKOUT4 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH COMPENSATION CLKFBOUT (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH COMPENSATION CLKFBOUTB (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH COMPENSATION CLKOUT0 (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH COMPENSATION CLKOUT0B (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH COMPENSATION CLKOUT1 (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH COMPENSATION CLKOUT1B (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH COMPENSATION CLKOUT2 (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH COMPENSATION CLKOUT2B (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH COMPENSATION CLKOUT3 (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH COMPENSATION CLKOUT3B (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH COMPENSATION CLKOUT5 (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH COMPENSATION CLKOUT6 (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH COMPENSATION CLKFBOUT (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH COMPENSATION CLKFBOUTB (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH COMPENSATION CLKOUT0 (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH COMPENSATION CLKOUT0B (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH COMPENSATION CLKOUT1 (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH COMPENSATION CLKOUT1B (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH COMPENSATION CLKOUT2 (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH COMPENSATION CLKOUT2B (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH COMPENSATION CLKOUT3 (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH COMPENSATION CLKOUT3B (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH COMPENSATION CLKOUT5 (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH COMPENSATION CLKOUT6 (0.255::-0.260)(0.433::-0.240))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_CLKOUT4_CASCADE_FALSE_COMPENSATION_ZHOLD")
|
||||
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_EXTERNAL")
|
||||
(INSTANCE MMCME2_ADV)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLKIN1 CLKOUT4 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT4 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKFBOUT (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKFBOUTB (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT0 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT0B (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT1 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT1B (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT2 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT2B (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT3 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT3B (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT5 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT6 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKFBOUT (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKFBOUTB (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT0 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT0B (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT1 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT1B (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT2 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT2B (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT3 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT3B (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT5 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT6 (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_CLKOUT4_CASCADE_TRUE_COMPENSATION_BUF_IN")
|
||||
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_FALSE_COMPENSATION_BUF_IN")
|
||||
(INSTANCE MMCME2_ADV)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLKIN1 CLKOUT4 (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH CLKIN2 CLKOUT4 (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH CLKOUT4_CASCADE CLKOUT4 (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH CLKOUT4_CASCADE CLKOUT4 (0.255::-0.260)(0.433::-0.240))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_CLKOUT4_CASCADE_TRUE_COMPENSATION_EXTERNAL")
|
||||
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_FALSE_COMPENSATION_EXTERNAL")
|
||||
(INSTANCE MMCME2_ADV)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLKIN1 CLKOUT4 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT4 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKOUT4_CASCADE CLKOUT4 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKOUT4_CASCADE CLKOUT4 (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_CLKOUT4_CASCADE_TRUE_COMPENSATION_INTERNAL")
|
||||
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_FALSE_COMPENSATION_INTERNAL")
|
||||
(INSTANCE MMCME2_ADV)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLKIN1 CLKOUT4 (0.263::0.279)(0.492::0.522))
|
||||
(IOPATH CLKIN2 CLKOUT4 (0.263::0.279)(0.492::0.522))
|
||||
(IOPATH CLKOUT4_CASCADE CLKOUT4 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKOUT4_CASCADE CLKOUT4 (0.050::0.053)(0.083::0.088))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_CLKOUT4_CASCADE_TRUE_COMPENSATION_ZHOLD")
|
||||
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_FALSE_COMPENSATION_ZHOLD")
|
||||
(INSTANCE MMCME2_ADV)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLKIN1 CLKOUT4 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT4 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKOUT4_CASCADE CLKOUT4 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKOUT4_CASCADE CLKOUT4 (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_COMPENSATION_BUF_IN")
|
||||
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_INTERNAL")
|
||||
(INSTANCE MMCME2_ADV)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLKIN1 CLKFBOUT (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH CLKIN1 CLKFBOUTB (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH CLKIN1 CLKOUT0 (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH CLKIN1 CLKOUT0B (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH CLKIN1 CLKOUT1 (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH CLKIN1 CLKOUT1B (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH CLKIN1 CLKOUT2 (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH CLKIN1 CLKOUT2B (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH CLKIN1 CLKOUT3 (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH CLKIN1 CLKOUT3B (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH CLKIN1 CLKOUT5 (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH CLKIN1 CLKOUT6 (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH CLKIN2 CLKFBOUT (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH CLKIN2 CLKFBOUTB (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH CLKIN2 CLKOUT0 (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH CLKIN2 CLKOUT0B (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH CLKIN2 CLKOUT1 (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH CLKIN2 CLKOUT1B (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH CLKIN2 CLKOUT2 (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH CLKIN2 CLKOUT2B (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH CLKIN2 CLKOUT3 (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH CLKIN2 CLKOUT3B (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH CLKIN2 CLKOUT5 (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH CLKIN2 CLKOUT6 (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH COMPENSATION CLKFBOUT (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH COMPENSATION CLKFBOUTB (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH COMPENSATION CLKOUT0 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH COMPENSATION CLKOUT0B (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH COMPENSATION CLKOUT1 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH COMPENSATION CLKOUT1B (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH COMPENSATION CLKOUT2 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH COMPENSATION CLKOUT2B (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH COMPENSATION CLKOUT3 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH COMPENSATION CLKOUT3B (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH COMPENSATION CLKOUT5 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH COMPENSATION CLKOUT6 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH COMPENSATION CLKFBOUT (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH COMPENSATION CLKFBOUTB (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH COMPENSATION CLKOUT0 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH COMPENSATION CLKOUT0B (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH COMPENSATION CLKOUT1 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH COMPENSATION CLKOUT1B (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH COMPENSATION CLKOUT2 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH COMPENSATION CLKOUT2B (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH COMPENSATION CLKOUT3 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH COMPENSATION CLKOUT3B (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH COMPENSATION CLKOUT5 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH COMPENSATION CLKOUT6 (0.050::0.053)(0.083::0.088))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_COMPENSATION_EXTERNAL")
|
||||
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_TRUE_COMPENSATION_BUF_IN")
|
||||
(INSTANCE MMCME2_ADV)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLKIN1 CLKFBOUT (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKFBOUTB (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT0 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT0B (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT1 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT1B (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT2 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT2B (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT3 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT3B (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT5 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT6 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKFBOUT (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKFBOUTB (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT0 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT0B (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT1 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT1B (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT2 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT2B (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT3 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT3B (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT5 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT6 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKOUT4_CASCADE CLKOUT4 (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH CLKOUT4_CASCADE CLKOUT4 (0.255::-0.260)(0.433::-0.240))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_COMPENSATION_INTERNAL")
|
||||
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_TRUE_COMPENSATION_EXTERNAL")
|
||||
(INSTANCE MMCME2_ADV)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLKIN1 CLKFBOUT (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN1 CLKFBOUTB (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN1 CLKOUT0 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN1 CLKOUT0B (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN1 CLKOUT1 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN1 CLKOUT1B (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN1 CLKOUT2 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN1 CLKOUT2B (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN1 CLKOUT3 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN1 CLKOUT3B (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN1 CLKOUT5 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN1 CLKOUT6 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN2 CLKFBOUT (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN2 CLKFBOUTB (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN2 CLKOUT0 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN2 CLKOUT0B (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN2 CLKOUT1 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN2 CLKOUT1B (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN2 CLKOUT2 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN2 CLKOUT2B (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN2 CLKOUT3 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN2 CLKOUT3B (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN2 CLKOUT5 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN2 CLKOUT6 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKOUT4_CASCADE CLKOUT4 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKOUT4_CASCADE CLKOUT4 (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_COMPENSATION_ZHOLD")
|
||||
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_TRUE_COMPENSATION_INTERNAL")
|
||||
(INSTANCE MMCME2_ADV)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLKIN1 CLKFBOUT (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKFBOUTB (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT0 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT0B (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT1 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT1B (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT2 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT2B (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT3 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT3B (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT5 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT6 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKFBOUT (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKFBOUTB (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT0 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT0B (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT1 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT1B (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT2 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT2B (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT3 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT3B (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT5 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT6 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKOUT4_CASCADE CLKOUT4 (0.263::0.279)(0.492::0.522))
|
||||
(IOPATH CLKOUT4_CASCADE CLKOUT4 (0.263::0.279)(0.492::0.522))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_DADDR")
|
||||
(INSTANCE MMCME2_ADV)
|
||||
(TIMINGCHECK
|
||||
(HOLD DCLK (posedge DCLK) (0.141::0.150))
|
||||
(SETUP DCLK (posedge DCLK) (1.527::1.622))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_DI")
|
||||
(INSTANCE MMCME2_ADV)
|
||||
(TIMINGCHECK
|
||||
(HOLD DCLK (posedge DCLK) (0.141::0.150))
|
||||
(SETUP DCLK (posedge DCLK) (1.527::1.622))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_TMUX_MUX_SEL_00")
|
||||
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_TRUE_COMPENSATION_ZHOLD")
|
||||
(INSTANCE MMCME2_ADV)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLKIN1 TMUXOUT (0.527::0.560)(0.979::1.040))
|
||||
(IOPATH CLKIN2 TMUXOUT (0.527::0.560)(0.979::1.040))
|
||||
(IOPATH CLKOUT4_CASCADE CLKOUT4 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKOUT4_CASCADE CLKOUT4 (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_TMUX_MUX_SEL_01")
|
||||
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_ZHOLD")
|
||||
(INSTANCE MMCME2_ADV)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLKFBIN TMUXOUT (0.527::0.560)(0.979::1.040))
|
||||
(IOPATH COMPENSATION CLKFBOUT (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKFBOUTB (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT0 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT0B (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT1 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT1B (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT2 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT2B (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT3 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT3B (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT5 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT6 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKFBOUT (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKFBOUTB (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT0 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT0B (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT1 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT1B (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT2 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT2B (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT3 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT3B (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT5 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT6 (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_IN_PHY_PHASER_IN_PHYPHASER_IN_OUTPUT_CLK_SRC_DELAYED_MEM_REF")
|
||||
|
|
@ -65,30 +65,33 @@
|
|||
(IOPATH MEMREFCLK DQSFOUND (0.204::0.217)(0.379::0.402))
|
||||
(IOPATH RST DQSOUTOFRANGE (0.094::0.100)(0.186::0.198))
|
||||
(IOPATH RST PHASELOCKED (0.094::0.100)(0.186::0.198))
|
||||
(IOPATH SCANCLK SCANOUT (0.094::0.100)(0.186::0.198))
|
||||
(IOPATH SYSCLK FINEOVERFLOW (0.344::0.365)(0.667::0.708))
|
||||
(IOPATH SYSCLK STG1OVERFLOW (0.230::0.244)(0.431::0.458))
|
||||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD BURSTPENDING (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP BURSTPENDING (posedge SYSCLK) (0.040::0.042))
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.050::0.053))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.099::0.105))
|
||||
(HOLD COUNTERLOADEN (posedge SYSCLK) (0.050::0.053))
|
||||
(SETUP COUNTERLOADEN (posedge SYSCLK) (0.099::0.105))
|
||||
(HOLD COUNTERLOADVAL (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP COUNTERLOADVAL (posedge SYSCLK) (0.067::0.071))
|
||||
(HOLD COUNTERREADEN (posedge SYSCLK) (0.050::0.053))
|
||||
(SETUP COUNTERREADEN (posedge SYSCLK) (0.095::0.101))
|
||||
(HOLD DIVIDERST (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP DIVIDERST (posedge SYSCLK) (0.091::0.097))
|
||||
(HOLD EDGEADV (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP EDGEADV (posedge SYSCLK) (0.028::0.030))
|
||||
(HOLD ENCALIB (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP ENCALIB (posedge SYSCLK) (0.217::0.230))
|
||||
(HOLD ENSTG1 (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP ENSTG1 (posedge SYSCLK) (0.170::0.180))
|
||||
(HOLD ENSTG1ADJUSTB (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP ENSTG1ADJUSTB (posedge SYSCLK) (0.227::0.241))
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.050::0.053))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.072::0.076))
|
||||
(HOLD FINEENABLE (posedge SYSCLK) (0.050::0.053))
|
||||
(SETUP FINEENABLE (posedge SYSCLK) (0.072::0.076))
|
||||
(HOLD FINEINC (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP FINEINC (posedge SYSCLK) (0.057::0.061))
|
||||
(HOLD RANKSEL (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP RANKSEL (posedge SYSCLK) (0.228::0.242))
|
||||
(HOLD RSTDQSFIND (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP RSTDQSFIND (posedge SYSCLK) (0.156::0.166))
|
||||
(HOLD SCANENB (posedge SCANCLK) (0.000::0.000))
|
||||
|
|
@ -97,30 +100,16 @@
|
|||
(SETUP SCANIN (posedge SCANCLK) (0.030::0.032))
|
||||
(HOLD SCANMODEB (posedge SCANCLK) (0.000::0.000))
|
||||
(SETUP SCANMODEB (posedge SCANCLK) (0.526::0.559))
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.046::0.049))
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.227::0.241))
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.218::0.232))
|
||||
(HOLD SELCALORSTG1 (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP SELCALORSTG1 (posedge SYSCLK) (0.046::0.049))
|
||||
(HOLD STG1INCDEC (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP STG1INCDEC (posedge SYSCLK) (0.227::0.241))
|
||||
(HOLD STG1LOAD (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP STG1LOAD (posedge SYSCLK) (0.218::0.232))
|
||||
(HOLD STG1READ (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP STG1READ (posedge SYSCLK) (0.154::0.164))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_IN_PHY_PHASER_IN_PHYPHASER_IN_PHY_COUNTERLOADVAL")
|
||||
(INSTANCE PHASER_IN_PHY)
|
||||
(TIMINGCHECK
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.067::0.071))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_IN_PHY_PHASER_IN_PHYPHASER_IN_PHY_ENCALIB")
|
||||
(INSTANCE PHASER_IN_PHY)
|
||||
(TIMINGCHECK
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.217::0.230))
|
||||
(HOLD STG1REGL (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP STG1REGL (posedge SYSCLK) (0.218::0.231))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
|
|
@ -196,19 +185,14 @@
|
|||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_IN_PHY_PHASER_IN_PHYPHASER_IN_PHY_RANKSEL")
|
||||
(INSTANCE PHASER_IN_PHY)
|
||||
(TIMINGCHECK
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.228::0.242))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_IN_PHY_PHASER_IN_PHYPHASER_IN_PHY_STG1REGL")
|
||||
(INSTANCE PHASER_IN_PHY)
|
||||
(TIMINGCHECK
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.218::0.231))
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_ADV")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CTSBUS OCLK (0.351::0.373)(0.529::0.562))
|
||||
(IOPATH DQSBUS OCLK (0.346::0.367)(0.518::0.550))
|
||||
(IOPATH DTSBUS OCLK (0.137::0.145)(0.254::0.270))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
|
|
@ -340,36 +324,33 @@
|
|||
(CELL
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_PHY")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH SCANCLK SCANOUT (0.094::0.100)(0.186::0.198))
|
||||
(IOPATH SYSCLK COARSEOVERFLOW (0.143::0.152)(0.274::0.291))
|
||||
(IOPATH SYSCLK FINEOVERFLOW (0.182::0.193)(0.337::0.358))
|
||||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.126::0.134))
|
||||
(HOLD BURSTPENDING (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP BURSTPENDING (posedge SYSCLK) (0.126::0.134))
|
||||
(HOLD COARSEENABLE (posedge SYSCLK) (0.050::0.053))
|
||||
(SETUP COARSEENABLE (posedge SYSCLK) (0.114::0.121))
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.133::0.141))
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.050::0.053))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.099::0.105))
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.050::0.053))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.073::0.077))
|
||||
(HOLD COARSEINC (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP COARSEINC (posedge SYSCLK) (0.133::0.141))
|
||||
(HOLD COUNTERLOADEN (posedge SYSCLK) (0.050::0.053))
|
||||
(SETUP COUNTERLOADEN (posedge SYSCLK) (0.099::0.105))
|
||||
(HOLD COUNTERLOADVAL (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP COUNTERLOADVAL (posedge SYSCLK) (0.168::0.178))
|
||||
(HOLD COUNTERREADEN (posedge SYSCLK) (0.050::0.053))
|
||||
(SETUP COUNTERREADEN (posedge SYSCLK) (0.073::0.077))
|
||||
(HOLD EDGEADV (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP EDGEADV (posedge SYSCLK) (0.027::0.029))
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.050::0.053))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.169::0.179))
|
||||
(HOLD ENCALIB (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP ENCALIB (posedge SYSCLK) (0.176::0.187))
|
||||
(HOLD FINEENABLE (posedge SYSCLK) (0.050::0.053))
|
||||
(SETUP FINEENABLE (posedge SYSCLK) (0.169::0.179))
|
||||
(HOLD FINEINC (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP FINEINC (posedge SYSCLK) (0.050::0.053))
|
||||
(HOLD SCANENB (posedge SCANCLK) (0.000::0.000))
|
||||
(SETUP SCANENB (posedge SCANCLK) (0.488::0.518))
|
||||
(HOLD SCANIN (posedge SCANCLK) (0.000::0.000))
|
||||
(SETUP SCANIN (posedge SCANCLK) (0.194::0.206))
|
||||
(HOLD SCANCLK (posedge SCANCLK) (0.000::0.000))
|
||||
(SETUP SCANCLK (posedge SCANCLK) (0.966::1.026))
|
||||
(HOLD SCANMODEB (posedge SCANCLK) (0.000::0.000))
|
||||
(SETUP SCANMODEB (posedge SCANCLK) (0.966::1.026))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
|
|
@ -492,22 +473,6 @@
|
|||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_PHY_COUNTERLOADVAL")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
(TIMINGCHECK
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.168::0.178))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_PHY_ENCALIB")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
(TIMINGCHECK
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.176::0.187))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_PHY_OUTPUT_CLK_SRC_FREQ_REF")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_IN_PHY_PHASER_IN_PHYPHASER_IN_OUTPUT_CLK_SRC_DELAYED_MEM_REF")
|
||||
|
|
@ -65,30 +65,33 @@
|
|||
(IOPATH MEMREFCLK DQSFOUND (0.204::0.217)(0.379::0.402))
|
||||
(IOPATH RST DQSOUTOFRANGE (0.094::0.100)(0.186::0.198))
|
||||
(IOPATH RST PHASELOCKED (0.094::0.100)(0.186::0.198))
|
||||
(IOPATH SCANCLK SCANOUT (0.094::0.100)(0.186::0.198))
|
||||
(IOPATH SYSCLK FINEOVERFLOW (0.344::0.365)(0.667::0.708))
|
||||
(IOPATH SYSCLK STG1OVERFLOW (0.230::0.244)(0.431::0.458))
|
||||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD BURSTPENDING (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP BURSTPENDING (posedge SYSCLK) (0.040::0.042))
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.050::0.053))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.099::0.105))
|
||||
(HOLD COUNTERLOADEN (posedge SYSCLK) (0.050::0.053))
|
||||
(SETUP COUNTERLOADEN (posedge SYSCLK) (0.099::0.105))
|
||||
(HOLD COUNTERLOADVAL (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP COUNTERLOADVAL (posedge SYSCLK) (0.067::0.071))
|
||||
(HOLD COUNTERREADEN (posedge SYSCLK) (0.050::0.053))
|
||||
(SETUP COUNTERREADEN (posedge SYSCLK) (0.095::0.101))
|
||||
(HOLD DIVIDERST (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP DIVIDERST (posedge SYSCLK) (0.091::0.097))
|
||||
(HOLD EDGEADV (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP EDGEADV (posedge SYSCLK) (0.028::0.030))
|
||||
(HOLD ENCALIB (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP ENCALIB (posedge SYSCLK) (0.217::0.230))
|
||||
(HOLD ENSTG1 (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP ENSTG1 (posedge SYSCLK) (0.170::0.180))
|
||||
(HOLD ENSTG1ADJUSTB (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP ENSTG1ADJUSTB (posedge SYSCLK) (0.227::0.241))
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.050::0.053))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.072::0.076))
|
||||
(HOLD FINEENABLE (posedge SYSCLK) (0.050::0.053))
|
||||
(SETUP FINEENABLE (posedge SYSCLK) (0.072::0.076))
|
||||
(HOLD FINEINC (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP FINEINC (posedge SYSCLK) (0.057::0.061))
|
||||
(HOLD RANKSEL (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP RANKSEL (posedge SYSCLK) (0.228::0.242))
|
||||
(HOLD RSTDQSFIND (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP RSTDQSFIND (posedge SYSCLK) (0.156::0.166))
|
||||
(HOLD SCANENB (posedge SCANCLK) (0.000::0.000))
|
||||
|
|
@ -97,30 +100,16 @@
|
|||
(SETUP SCANIN (posedge SCANCLK) (0.030::0.032))
|
||||
(HOLD SCANMODEB (posedge SCANCLK) (0.000::0.000))
|
||||
(SETUP SCANMODEB (posedge SCANCLK) (0.526::0.559))
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.046::0.049))
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.227::0.241))
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.218::0.232))
|
||||
(HOLD SELCALORSTG1 (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP SELCALORSTG1 (posedge SYSCLK) (0.046::0.049))
|
||||
(HOLD STG1INCDEC (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP STG1INCDEC (posedge SYSCLK) (0.227::0.241))
|
||||
(HOLD STG1LOAD (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP STG1LOAD (posedge SYSCLK) (0.218::0.232))
|
||||
(HOLD STG1READ (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP STG1READ (posedge SYSCLK) (0.154::0.164))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_IN_PHY_PHASER_IN_PHYPHASER_IN_PHY_COUNTERLOADVAL")
|
||||
(INSTANCE PHASER_IN_PHY)
|
||||
(TIMINGCHECK
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.067::0.071))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_IN_PHY_PHASER_IN_PHYPHASER_IN_PHY_ENCALIB")
|
||||
(INSTANCE PHASER_IN_PHY)
|
||||
(TIMINGCHECK
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.217::0.230))
|
||||
(HOLD STG1REGL (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP STG1REGL (posedge SYSCLK) (0.218::0.231))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
|
|
@ -196,19 +185,14 @@
|
|||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_IN_PHY_PHASER_IN_PHYPHASER_IN_PHY_RANKSEL")
|
||||
(INSTANCE PHASER_IN_PHY)
|
||||
(TIMINGCHECK
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.228::0.242))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_IN_PHY_PHASER_IN_PHYPHASER_IN_PHY_STG1REGL")
|
||||
(INSTANCE PHASER_IN_PHY)
|
||||
(TIMINGCHECK
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.218::0.231))
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_ADV")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CTSBUS OCLK (0.351::0.373)(0.529::0.562))
|
||||
(IOPATH DQSBUS OCLK (0.346::0.367)(0.518::0.550))
|
||||
(IOPATH DTSBUS OCLK (0.137::0.145)(0.254::0.270))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
|
|
@ -340,36 +324,33 @@
|
|||
(CELL
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_PHY")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH SCANCLK SCANOUT (0.094::0.100)(0.186::0.198))
|
||||
(IOPATH SYSCLK COARSEOVERFLOW (0.143::0.152)(0.274::0.291))
|
||||
(IOPATH SYSCLK FINEOVERFLOW (0.182::0.193)(0.337::0.358))
|
||||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.126::0.134))
|
||||
(HOLD BURSTPENDING (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP BURSTPENDING (posedge SYSCLK) (0.126::0.134))
|
||||
(HOLD COARSEENABLE (posedge SYSCLK) (0.050::0.053))
|
||||
(SETUP COARSEENABLE (posedge SYSCLK) (0.114::0.121))
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.133::0.141))
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.050::0.053))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.099::0.105))
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.050::0.053))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.073::0.077))
|
||||
(HOLD COARSEINC (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP COARSEINC (posedge SYSCLK) (0.133::0.141))
|
||||
(HOLD COUNTERLOADEN (posedge SYSCLK) (0.050::0.053))
|
||||
(SETUP COUNTERLOADEN (posedge SYSCLK) (0.099::0.105))
|
||||
(HOLD COUNTERLOADVAL (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP COUNTERLOADVAL (posedge SYSCLK) (0.168::0.178))
|
||||
(HOLD COUNTERREADEN (posedge SYSCLK) (0.050::0.053))
|
||||
(SETUP COUNTERREADEN (posedge SYSCLK) (0.073::0.077))
|
||||
(HOLD EDGEADV (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP EDGEADV (posedge SYSCLK) (0.027::0.029))
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.050::0.053))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.169::0.179))
|
||||
(HOLD ENCALIB (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP ENCALIB (posedge SYSCLK) (0.176::0.187))
|
||||
(HOLD FINEENABLE (posedge SYSCLK) (0.050::0.053))
|
||||
(SETUP FINEENABLE (posedge SYSCLK) (0.169::0.179))
|
||||
(HOLD FINEINC (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP FINEINC (posedge SYSCLK) (0.050::0.053))
|
||||
(HOLD SCANENB (posedge SCANCLK) (0.000::0.000))
|
||||
(SETUP SCANENB (posedge SCANCLK) (0.488::0.518))
|
||||
(HOLD SCANIN (posedge SCANCLK) (0.000::0.000))
|
||||
(SETUP SCANIN (posedge SCANCLK) (0.194::0.206))
|
||||
(HOLD SCANCLK (posedge SCANCLK) (0.000::0.000))
|
||||
(SETUP SCANCLK (posedge SCANCLK) (0.966::1.026))
|
||||
(HOLD SCANMODEB (posedge SCANCLK) (0.000::0.000))
|
||||
(SETUP SCANMODEB (posedge SCANCLK) (0.966::1.026))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
|
|
@ -492,22 +473,6 @@
|
|||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_PHY_COUNTERLOADVAL")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
(TIMINGCHECK
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.168::0.178))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_PHY_ENCALIB")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
(TIMINGCHECK
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.176::0.187))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_PHY_OUTPUT_CLK_SRC_FREQ_REF")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
|
|
@ -531,45 +496,19 @@
|
|||
(CELL
|
||||
(CELLTYPE "PHY_CONTROL_PHY_CONTROLPHY_CONTROL")
|
||||
(INSTANCE PHY_CONTROL)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH MEMREFCLK PHYCTLEMPTY (0.313::0.360)(0.541::0.622))
|
||||
(IOPATH PHYCLK PHYCTLALMOSTFULL (0.158::0.182)(0.338::0.389))
|
||||
(IOPATH PHYCLK PHYCTLFULL (0.151::0.174)(0.321::0.369))
|
||||
(IOPATH PHYCLK PHYCTLREADY (0.174::0.200)(0.368::0.423))
|
||||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD MEMREFCLK (posedge MEMREFCLK) (0.203::0.233))
|
||||
(SETUP MEMREFCLK (posedge MEMREFCLK) (0.010::0.011))
|
||||
(HOLD PHYCLK (posedge PHYCLK) (0.049::0.056))
|
||||
(SETUP PHYCLK (posedge PHYCLK) (0.327::0.376))
|
||||
(HOLD MEMREFCLK (posedge MEMREFCLK) (0.151::0.174))
|
||||
(SETUP MEMREFCLK (posedge MEMREFCLK) (0.158::0.182))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHY_CONTROL_PHY_CONTROLPHY_CONTROL_PHYCTLWD")
|
||||
(INSTANCE PHY_CONTROL)
|
||||
(TIMINGCHECK
|
||||
(HOLD PHYCLK (posedge PHYCLK) (0.172::0.198))
|
||||
(SETUP PHYCLK (posedge PHYCLK) (0.215::0.248))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHY_CONTROL_PHY_CONTROLPHY_CONTROL_TESTINPUT")
|
||||
(INSTANCE PHY_CONTROL)
|
||||
(TIMINGCHECK
|
||||
(HOLD MEMREFCLK (posedge MEMREFCLK) (0.049::0.056))
|
||||
(SETUP MEMREFCLK (posedge MEMREFCLK) (0.244::0.281))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHY_CONTROL_PHY_CONTROLPHY_CONTROL_TESTSELECT")
|
||||
(INSTANCE PHY_CONTROL)
|
||||
(TIMINGCHECK
|
||||
(HOLD MEMREFCLK (posedge MEMREFCLK) (0.049::0.056))
|
||||
(SETUP MEMREFCLK (posedge MEMREFCLK) (0.244::0.281))
|
||||
(HOLD PHYCTLMSTREMPTY (posedge MEMREFCLK) (0.203::0.233))
|
||||
(SETUP PHYCTLMSTREMPTY (posedge MEMREFCLK) (0.010::0.011))
|
||||
(HOLD PHYCTLWD (posedge PHYCLK) (0.172::0.198))
|
||||
(SETUP PHYCTLWD (posedge PHYCLK) (0.215::0.248))
|
||||
(HOLD PHYCTLWRENABLE (posedge PHYCLK) (0.049::0.056))
|
||||
(SETUP PHYCTLWRENABLE (posedge PHYCLK) (0.327::0.376))
|
||||
(HOLD SYNCIN (posedge MEMREFCLK) (0.151::0.174))
|
||||
(SETUP SYNCIN (posedge MEMREFCLK) (0.158::0.182))
|
||||
(HOLD TESTINPUT (posedge MEMREFCLK) (0.049::0.056))
|
||||
(SETUP TESTINPUT (posedge MEMREFCLK) (0.244::0.281))
|
||||
(HOLD TESTSELECT (posedge MEMREFCLK) (0.049::0.056))
|
||||
(SETUP TESTSELECT (posedge MEMREFCLK) (0.244::0.281))
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -1,144 +1,131 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
(CELL
|
||||
(CELLTYPE "PLLE2_ADV_PLLE2_ADVPLLE2_ADV")
|
||||
(INSTANCE PLLE2_ADV)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH DCLK DRDY (0.286::0.304)(0.927::0.984))
|
||||
(IOPATH RST LOCKED (3.000::3.000)(3.000::3.000))
|
||||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD DADDR (posedge DCLK) (0.141::0.150))
|
||||
(SETUP DADDR (posedge DCLK) (1.527::1.622))
|
||||
(HOLD DEN (posedge DCLK) (0.000::0.000))
|
||||
(SETUP DEN (posedge DCLK) (2.156::2.290))
|
||||
(HOLD DCLK (posedge DCLK) (0.141::0.150))
|
||||
(SETUP DCLK (posedge DCLK) (1.527::1.622))
|
||||
(HOLD DI (posedge DCLK) (0.141::0.150))
|
||||
(SETUP DI (posedge DCLK) (1.527::1.622))
|
||||
(HOLD DWE (posedge DCLK) (0.141::0.150))
|
||||
(SETUP DWE (posedge DCLK) (1.527::1.622))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PLLE2_ADV_PLLE2_ADVPLLE2_ADV_COMPENSATION_BUF_IN")
|
||||
(CELLTYPE "PLLE2_ADV_PLLE2_ADVPLLE2_ADV_00")
|
||||
(INSTANCE PLLE2_ADV)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLKIN1 CLKFBOUT (0.144::-0.210)(0.360::-0.140))
|
||||
(IOPATH CLKIN1 CLKOUT0 (0.144::-0.210)(0.360::-0.140))
|
||||
(IOPATH CLKIN1 CLKOUT1 (0.144::-0.210)(0.360::-0.140))
|
||||
(IOPATH CLKIN1 CLKOUT2 (0.144::-0.210)(0.360::-0.140))
|
||||
(IOPATH CLKIN1 CLKOUT3 (0.144::-0.210)(0.360::-0.140))
|
||||
(IOPATH CLKIN1 CLKOUT4 (0.144::-0.210)(0.360::-0.140))
|
||||
(IOPATH CLKIN1 CLKOUT5 (0.144::-0.210)(0.360::-0.140))
|
||||
(IOPATH CLKIN2 CLKFBOUT (0.144::-0.210)(0.360::-0.140))
|
||||
(IOPATH CLKIN2 CLKOUT0 (0.144::-0.210)(0.360::-0.140))
|
||||
(IOPATH CLKIN2 CLKOUT1 (0.144::-0.210)(0.360::-0.140))
|
||||
(IOPATH CLKIN2 CLKOUT2 (0.144::-0.210)(0.360::-0.140))
|
||||
(IOPATH CLKIN2 CLKOUT3 (0.144::-0.210)(0.360::-0.140))
|
||||
(IOPATH CLKIN2 CLKOUT4 (0.144::-0.210)(0.360::-0.140))
|
||||
(IOPATH CLKIN2 CLKOUT5 (0.144::-0.210)(0.360::-0.140))
|
||||
(IOPATH TMUX_MUX_SEL TMUXOUT (0.527::0.560)(0.979::1.040))
|
||||
(IOPATH TMUX_MUX_SEL TMUXOUT (0.527::0.560)(0.979::1.040))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PLLE2_ADV_PLLE2_ADVPLLE2_ADV_COMPENSATION_EXTERNAL")
|
||||
(CELLTYPE "PLLE2_ADV_PLLE2_ADVPLLE2_ADV_01")
|
||||
(INSTANCE PLLE2_ADV)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLKIN1 CLKFBOUT (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT0 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT1 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT2 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT3 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT4 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT5 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKFBOUT (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT0 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT1 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT2 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT3 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT4 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT5 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH TMUX_MUX_SEL TMUXOUT (0.527::0.560)(0.979::1.040))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PLLE2_ADV_PLLE2_ADVPLLE2_ADV_COMPENSATION_INTERNAL")
|
||||
(CELLTYPE "PLLE2_ADV_PLLE2_ADVPLLE2_ADV_BUF_IN")
|
||||
(INSTANCE PLLE2_ADV)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLKIN1 CLKFBOUT (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN1 CLKOUT0 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN1 CLKOUT1 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN1 CLKOUT2 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN1 CLKOUT3 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN1 CLKOUT4 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN1 CLKOUT5 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN2 CLKFBOUT (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN2 CLKOUT0 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN2 CLKOUT1 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN2 CLKOUT2 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN2 CLKOUT3 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN2 CLKOUT4 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN2 CLKOUT5 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH COMPENSATION CLKFBOUT (0.144::-0.210)(0.360::-0.140))
|
||||
(IOPATH COMPENSATION CLKOUT0 (0.144::-0.210)(0.360::-0.140))
|
||||
(IOPATH COMPENSATION CLKOUT1 (0.144::-0.210)(0.360::-0.140))
|
||||
(IOPATH COMPENSATION CLKOUT2 (0.144::-0.210)(0.360::-0.140))
|
||||
(IOPATH COMPENSATION CLKOUT3 (0.144::-0.210)(0.360::-0.140))
|
||||
(IOPATH COMPENSATION CLKOUT4 (0.144::-0.210)(0.360::-0.140))
|
||||
(IOPATH COMPENSATION CLKOUT5 (0.144::-0.210)(0.360::-0.140))
|
||||
(IOPATH COMPENSATION CLKFBOUT (0.144::-0.210)(0.360::-0.140))
|
||||
(IOPATH COMPENSATION CLKOUT0 (0.144::-0.210)(0.360::-0.140))
|
||||
(IOPATH COMPENSATION CLKOUT1 (0.144::-0.210)(0.360::-0.140))
|
||||
(IOPATH COMPENSATION CLKOUT2 (0.144::-0.210)(0.360::-0.140))
|
||||
(IOPATH COMPENSATION CLKOUT3 (0.144::-0.210)(0.360::-0.140))
|
||||
(IOPATH COMPENSATION CLKOUT4 (0.144::-0.210)(0.360::-0.140))
|
||||
(IOPATH COMPENSATION CLKOUT5 (0.144::-0.210)(0.360::-0.140))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PLLE2_ADV_PLLE2_ADVPLLE2_ADV_COMPENSATION_ZHOLD")
|
||||
(CELLTYPE "PLLE2_ADV_PLLE2_ADVPLLE2_ADV_EXTERNAL")
|
||||
(INSTANCE PLLE2_ADV)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLKIN1 CLKFBOUT (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT0 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT1 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT2 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT3 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT4 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT5 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKFBOUT (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT0 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT1 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT2 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT3 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT4 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT5 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKFBOUT (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT0 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT1 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT2 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT3 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT4 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT5 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKFBOUT (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT0 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT1 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT2 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT3 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT4 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT5 (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PLLE2_ADV_PLLE2_ADVPLLE2_ADV_DADDR")
|
||||
(INSTANCE PLLE2_ADV)
|
||||
(TIMINGCHECK
|
||||
(HOLD DCLK (posedge DCLK) (0.141::0.150))
|
||||
(SETUP DCLK (posedge DCLK) (1.527::1.622))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PLLE2_ADV_PLLE2_ADVPLLE2_ADV_DI")
|
||||
(INSTANCE PLLE2_ADV)
|
||||
(TIMINGCHECK
|
||||
(HOLD DCLK (posedge DCLK) (0.141::0.150))
|
||||
(SETUP DCLK (posedge DCLK) (1.527::1.622))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PLLE2_ADV_PLLE2_ADVPLLE2_ADV_TMUX_MUX_SEL_00")
|
||||
(CELLTYPE "PLLE2_ADV_PLLE2_ADVPLLE2_ADV_INTERNAL")
|
||||
(INSTANCE PLLE2_ADV)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLKIN1 TMUXOUT (0.527::0.560)(0.979::1.040))
|
||||
(IOPATH CLKIN2 TMUXOUT (0.527::0.560)(0.979::1.040))
|
||||
(IOPATH COMPENSATION CLKFBOUT (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH COMPENSATION CLKOUT0 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH COMPENSATION CLKOUT1 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH COMPENSATION CLKOUT2 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH COMPENSATION CLKOUT3 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH COMPENSATION CLKOUT4 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH COMPENSATION CLKOUT5 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH COMPENSATION CLKFBOUT (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH COMPENSATION CLKOUT0 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH COMPENSATION CLKOUT1 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH COMPENSATION CLKOUT2 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH COMPENSATION CLKOUT3 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH COMPENSATION CLKOUT4 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH COMPENSATION CLKOUT5 (0.050::0.053)(0.083::0.088))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PLLE2_ADV_PLLE2_ADVPLLE2_ADV_TMUX_MUX_SEL_01")
|
||||
(CELLTYPE "PLLE2_ADV_PLLE2_ADVPLLE2_ADV_ZHOLD")
|
||||
(INSTANCE PLLE2_ADV)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLKFBIN TMUXOUT (0.527::0.560)(0.979::1.040))
|
||||
(IOPATH COMPENSATION CLKFBOUT (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT0 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT1 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT2 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT3 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT4 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT5 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKFBOUT (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT0 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT1 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT2 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT3 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT4 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT5 (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
|
|||
|
|
@ -1,25 +1,27 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
(CELL
|
||||
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV")
|
||||
(INSTANCE MMCME2_ADV)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH DCLK DRDY (0.286::0.304)(0.927::0.984))
|
||||
(IOPATH PSCLK PSDONE (0.318::0.338)(0.758::0.805))
|
||||
(IOPATH RST CLKFBSTOPPED (0.348::0.370)(0.549::0.583))
|
||||
(IOPATH RST CLKINSTOPPED (0.348::0.370)(0.549::0.583))
|
||||
(IOPATH RST LOCKED (3.000::3.000)(3.000::3.000))
|
||||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD DADDR (posedge DCLK) (0.141::0.150))
|
||||
(SETUP DADDR (posedge DCLK) (1.527::1.622))
|
||||
(HOLD DEN (posedge DCLK) (0.000::0.000))
|
||||
(SETUP DEN (posedge DCLK) (2.156::2.290))
|
||||
(HOLD DCLK (posedge DCLK) (0.141::0.150))
|
||||
(SETUP DCLK (posedge DCLK) (1.527::1.622))
|
||||
(HOLD DI (posedge DCLK) (0.141::0.150))
|
||||
(SETUP DI (posedge DCLK) (1.527::1.622))
|
||||
(HOLD DWE (posedge DCLK) (0.141::0.150))
|
||||
(SETUP DWE (posedge DCLK) (1.527::1.622))
|
||||
(HOLD PSEN (posedge PSCLK) (0.000::0.000))
|
||||
(SETUP PSEN (posedge PSCLK) (0.979::1.040))
|
||||
(HOLD PSINCDEC (posedge PSCLK) (0.000::0.000))
|
||||
|
|
@ -27,245 +29,229 @@
|
|||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_CLKOUT4_CASCADE_FALSE_COMPENSATION_BUF_IN")
|
||||
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_00")
|
||||
(INSTANCE MMCME2_ADV)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLKIN1 CLKOUT4 (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH CLKIN2 CLKOUT4 (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH TMUX_MUX_SEL TMUXOUT (0.527::0.560)(0.979::1.040))
|
||||
(IOPATH TMUX_MUX_SEL TMUXOUT (0.527::0.560)(0.979::1.040))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_CLKOUT4_CASCADE_FALSE_COMPENSATION_EXTERNAL")
|
||||
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_01")
|
||||
(INSTANCE MMCME2_ADV)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLKIN1 CLKOUT4 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT4 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH TMUX_MUX_SEL TMUXOUT (0.527::0.560)(0.979::1.040))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_CLKOUT4_CASCADE_FALSE_COMPENSATION_INTERNAL")
|
||||
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_BUF_IN")
|
||||
(INSTANCE MMCME2_ADV)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLKIN1 CLKOUT4 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN2 CLKOUT4 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH COMPENSATION CLKFBOUT (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH COMPENSATION CLKFBOUTB (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH COMPENSATION CLKOUT0 (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH COMPENSATION CLKOUT0B (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH COMPENSATION CLKOUT1 (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH COMPENSATION CLKOUT1B (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH COMPENSATION CLKOUT2 (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH COMPENSATION CLKOUT2B (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH COMPENSATION CLKOUT3 (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH COMPENSATION CLKOUT3B (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH COMPENSATION CLKOUT5 (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH COMPENSATION CLKOUT6 (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH COMPENSATION CLKFBOUT (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH COMPENSATION CLKFBOUTB (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH COMPENSATION CLKOUT0 (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH COMPENSATION CLKOUT0B (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH COMPENSATION CLKOUT1 (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH COMPENSATION CLKOUT1B (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH COMPENSATION CLKOUT2 (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH COMPENSATION CLKOUT2B (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH COMPENSATION CLKOUT3 (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH COMPENSATION CLKOUT3B (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH COMPENSATION CLKOUT5 (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH COMPENSATION CLKOUT6 (0.255::-0.260)(0.433::-0.240))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_CLKOUT4_CASCADE_FALSE_COMPENSATION_ZHOLD")
|
||||
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_EXTERNAL")
|
||||
(INSTANCE MMCME2_ADV)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLKIN1 CLKOUT4 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT4 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKFBOUT (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKFBOUTB (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT0 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT0B (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT1 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT1B (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT2 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT2B (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT3 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT3B (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT5 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT6 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKFBOUT (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKFBOUTB (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT0 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT0B (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT1 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT1B (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT2 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT2B (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT3 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT3B (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT5 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT6 (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_CLKOUT4_CASCADE_TRUE_COMPENSATION_BUF_IN")
|
||||
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_FALSE_COMPENSATION_BUF_IN")
|
||||
(INSTANCE MMCME2_ADV)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLKIN1 CLKOUT4 (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH CLKIN2 CLKOUT4 (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH CLKOUT4_CASCADE CLKOUT4 (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH CLKOUT4_CASCADE CLKOUT4 (0.255::-0.260)(0.433::-0.240))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_CLKOUT4_CASCADE_TRUE_COMPENSATION_EXTERNAL")
|
||||
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_FALSE_COMPENSATION_EXTERNAL")
|
||||
(INSTANCE MMCME2_ADV)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLKIN1 CLKOUT4 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT4 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKOUT4_CASCADE CLKOUT4 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKOUT4_CASCADE CLKOUT4 (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_CLKOUT4_CASCADE_TRUE_COMPENSATION_INTERNAL")
|
||||
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_FALSE_COMPENSATION_INTERNAL")
|
||||
(INSTANCE MMCME2_ADV)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLKIN1 CLKOUT4 (0.263::0.279)(0.492::0.522))
|
||||
(IOPATH CLKIN2 CLKOUT4 (0.263::0.279)(0.492::0.522))
|
||||
(IOPATH CLKOUT4_CASCADE CLKOUT4 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKOUT4_CASCADE CLKOUT4 (0.050::0.053)(0.083::0.088))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_CLKOUT4_CASCADE_TRUE_COMPENSATION_ZHOLD")
|
||||
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_FALSE_COMPENSATION_ZHOLD")
|
||||
(INSTANCE MMCME2_ADV)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLKIN1 CLKOUT4 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT4 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKOUT4_CASCADE CLKOUT4 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKOUT4_CASCADE CLKOUT4 (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_COMPENSATION_BUF_IN")
|
||||
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_INTERNAL")
|
||||
(INSTANCE MMCME2_ADV)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLKIN1 CLKFBOUT (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH CLKIN1 CLKFBOUTB (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH CLKIN1 CLKOUT0 (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH CLKIN1 CLKOUT0B (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH CLKIN1 CLKOUT1 (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH CLKIN1 CLKOUT1B (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH CLKIN1 CLKOUT2 (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH CLKIN1 CLKOUT2B (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH CLKIN1 CLKOUT3 (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH CLKIN1 CLKOUT3B (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH CLKIN1 CLKOUT5 (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH CLKIN1 CLKOUT6 (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH CLKIN2 CLKFBOUT (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH CLKIN2 CLKFBOUTB (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH CLKIN2 CLKOUT0 (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH CLKIN2 CLKOUT0B (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH CLKIN2 CLKOUT1 (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH CLKIN2 CLKOUT1B (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH CLKIN2 CLKOUT2 (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH CLKIN2 CLKOUT2B (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH CLKIN2 CLKOUT3 (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH CLKIN2 CLKOUT3B (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH CLKIN2 CLKOUT5 (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH CLKIN2 CLKOUT6 (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH COMPENSATION CLKFBOUT (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH COMPENSATION CLKFBOUTB (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH COMPENSATION CLKOUT0 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH COMPENSATION CLKOUT0B (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH COMPENSATION CLKOUT1 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH COMPENSATION CLKOUT1B (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH COMPENSATION CLKOUT2 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH COMPENSATION CLKOUT2B (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH COMPENSATION CLKOUT3 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH COMPENSATION CLKOUT3B (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH COMPENSATION CLKOUT5 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH COMPENSATION CLKOUT6 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH COMPENSATION CLKFBOUT (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH COMPENSATION CLKFBOUTB (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH COMPENSATION CLKOUT0 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH COMPENSATION CLKOUT0B (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH COMPENSATION CLKOUT1 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH COMPENSATION CLKOUT1B (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH COMPENSATION CLKOUT2 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH COMPENSATION CLKOUT2B (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH COMPENSATION CLKOUT3 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH COMPENSATION CLKOUT3B (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH COMPENSATION CLKOUT5 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH COMPENSATION CLKOUT6 (0.050::0.053)(0.083::0.088))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_COMPENSATION_EXTERNAL")
|
||||
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_TRUE_COMPENSATION_BUF_IN")
|
||||
(INSTANCE MMCME2_ADV)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLKIN1 CLKFBOUT (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKFBOUTB (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT0 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT0B (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT1 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT1B (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT2 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT2B (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT3 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT3B (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT5 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT6 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKFBOUT (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKFBOUTB (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT0 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT0B (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT1 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT1B (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT2 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT2B (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT3 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT3B (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT5 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT6 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKOUT4_CASCADE CLKOUT4 (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH CLKOUT4_CASCADE CLKOUT4 (0.255::-0.260)(0.433::-0.240))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_COMPENSATION_INTERNAL")
|
||||
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_TRUE_COMPENSATION_EXTERNAL")
|
||||
(INSTANCE MMCME2_ADV)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLKIN1 CLKFBOUT (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN1 CLKFBOUTB (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN1 CLKOUT0 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN1 CLKOUT0B (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN1 CLKOUT1 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN1 CLKOUT1B (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN1 CLKOUT2 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN1 CLKOUT2B (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN1 CLKOUT3 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN1 CLKOUT3B (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN1 CLKOUT5 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN1 CLKOUT6 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN2 CLKFBOUT (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN2 CLKFBOUTB (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN2 CLKOUT0 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN2 CLKOUT0B (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN2 CLKOUT1 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN2 CLKOUT1B (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN2 CLKOUT2 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN2 CLKOUT2B (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN2 CLKOUT3 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN2 CLKOUT3B (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN2 CLKOUT5 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN2 CLKOUT6 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKOUT4_CASCADE CLKOUT4 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKOUT4_CASCADE CLKOUT4 (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_COMPENSATION_ZHOLD")
|
||||
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_TRUE_COMPENSATION_INTERNAL")
|
||||
(INSTANCE MMCME2_ADV)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLKIN1 CLKFBOUT (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKFBOUTB (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT0 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT0B (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT1 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT1B (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT2 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT2B (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT3 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT3B (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT5 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT6 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKFBOUT (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKFBOUTB (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT0 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT0B (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT1 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT1B (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT2 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT2B (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT3 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT3B (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT5 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT6 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKOUT4_CASCADE CLKOUT4 (0.263::0.279)(0.492::0.522))
|
||||
(IOPATH CLKOUT4_CASCADE CLKOUT4 (0.263::0.279)(0.492::0.522))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_DADDR")
|
||||
(INSTANCE MMCME2_ADV)
|
||||
(TIMINGCHECK
|
||||
(HOLD DCLK (posedge DCLK) (0.141::0.150))
|
||||
(SETUP DCLK (posedge DCLK) (1.527::1.622))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_DI")
|
||||
(INSTANCE MMCME2_ADV)
|
||||
(TIMINGCHECK
|
||||
(HOLD DCLK (posedge DCLK) (0.141::0.150))
|
||||
(SETUP DCLK (posedge DCLK) (1.527::1.622))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_TMUX_MUX_SEL_00")
|
||||
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_TRUE_COMPENSATION_ZHOLD")
|
||||
(INSTANCE MMCME2_ADV)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLKIN1 TMUXOUT (0.527::0.560)(0.979::1.040))
|
||||
(IOPATH CLKIN2 TMUXOUT (0.527::0.560)(0.979::1.040))
|
||||
(IOPATH CLKOUT4_CASCADE CLKOUT4 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKOUT4_CASCADE CLKOUT4 (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_TMUX_MUX_SEL_01")
|
||||
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_ZHOLD")
|
||||
(INSTANCE MMCME2_ADV)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLKFBIN TMUXOUT (0.527::0.560)(0.979::1.040))
|
||||
(IOPATH COMPENSATION CLKFBOUT (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKFBOUTB (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT0 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT0B (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT1 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT1B (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT2 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT2B (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT3 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT3B (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT5 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT6 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKFBOUT (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKFBOUTB (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT0 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT0B (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT1 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT1B (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT2 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT2B (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT3 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT3B (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT5 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT6 (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_IN_PHY_PHASER_IN_PHYPHASER_IN_OUTPUT_CLK_SRC_DELAYED_MEM_REF")
|
||||
|
|
@ -65,30 +65,33 @@
|
|||
(IOPATH MEMREFCLK DQSFOUND (0.204::0.217)(0.379::0.402))
|
||||
(IOPATH RST DQSOUTOFRANGE (0.094::0.100)(0.186::0.198))
|
||||
(IOPATH RST PHASELOCKED (0.094::0.100)(0.186::0.198))
|
||||
(IOPATH SCANCLK SCANOUT (0.094::0.100)(0.186::0.198))
|
||||
(IOPATH SYSCLK FINEOVERFLOW (0.344::0.365)(0.667::0.708))
|
||||
(IOPATH SYSCLK STG1OVERFLOW (0.230::0.244)(0.431::0.458))
|
||||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD BURSTPENDING (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP BURSTPENDING (posedge SYSCLK) (0.040::0.042))
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.050::0.053))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.099::0.105))
|
||||
(HOLD COUNTERLOADEN (posedge SYSCLK) (0.050::0.053))
|
||||
(SETUP COUNTERLOADEN (posedge SYSCLK) (0.099::0.105))
|
||||
(HOLD COUNTERLOADVAL (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP COUNTERLOADVAL (posedge SYSCLK) (0.067::0.071))
|
||||
(HOLD COUNTERREADEN (posedge SYSCLK) (0.050::0.053))
|
||||
(SETUP COUNTERREADEN (posedge SYSCLK) (0.095::0.101))
|
||||
(HOLD DIVIDERST (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP DIVIDERST (posedge SYSCLK) (0.091::0.097))
|
||||
(HOLD EDGEADV (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP EDGEADV (posedge SYSCLK) (0.028::0.030))
|
||||
(HOLD ENCALIB (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP ENCALIB (posedge SYSCLK) (0.217::0.230))
|
||||
(HOLD ENSTG1 (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP ENSTG1 (posedge SYSCLK) (0.170::0.180))
|
||||
(HOLD ENSTG1ADJUSTB (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP ENSTG1ADJUSTB (posedge SYSCLK) (0.227::0.241))
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.050::0.053))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.072::0.076))
|
||||
(HOLD FINEENABLE (posedge SYSCLK) (0.050::0.053))
|
||||
(SETUP FINEENABLE (posedge SYSCLK) (0.072::0.076))
|
||||
(HOLD FINEINC (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP FINEINC (posedge SYSCLK) (0.057::0.061))
|
||||
(HOLD RANKSEL (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP RANKSEL (posedge SYSCLK) (0.228::0.242))
|
||||
(HOLD RSTDQSFIND (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP RSTDQSFIND (posedge SYSCLK) (0.156::0.166))
|
||||
(HOLD SCANENB (posedge SCANCLK) (0.000::0.000))
|
||||
|
|
@ -97,30 +100,16 @@
|
|||
(SETUP SCANIN (posedge SCANCLK) (0.030::0.032))
|
||||
(HOLD SCANMODEB (posedge SCANCLK) (0.000::0.000))
|
||||
(SETUP SCANMODEB (posedge SCANCLK) (0.526::0.559))
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.046::0.049))
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.227::0.241))
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.218::0.232))
|
||||
(HOLD SELCALORSTG1 (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP SELCALORSTG1 (posedge SYSCLK) (0.046::0.049))
|
||||
(HOLD STG1INCDEC (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP STG1INCDEC (posedge SYSCLK) (0.227::0.241))
|
||||
(HOLD STG1LOAD (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP STG1LOAD (posedge SYSCLK) (0.218::0.232))
|
||||
(HOLD STG1READ (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP STG1READ (posedge SYSCLK) (0.154::0.164))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_IN_PHY_PHASER_IN_PHYPHASER_IN_PHY_COUNTERLOADVAL")
|
||||
(INSTANCE PHASER_IN_PHY)
|
||||
(TIMINGCHECK
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.067::0.071))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_IN_PHY_PHASER_IN_PHYPHASER_IN_PHY_ENCALIB")
|
||||
(INSTANCE PHASER_IN_PHY)
|
||||
(TIMINGCHECK
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.217::0.230))
|
||||
(HOLD STG1REGL (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP STG1REGL (posedge SYSCLK) (0.218::0.231))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
|
|
@ -196,19 +185,14 @@
|
|||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_IN_PHY_PHASER_IN_PHYPHASER_IN_PHY_RANKSEL")
|
||||
(INSTANCE PHASER_IN_PHY)
|
||||
(TIMINGCHECK
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.228::0.242))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_IN_PHY_PHASER_IN_PHYPHASER_IN_PHY_STG1REGL")
|
||||
(INSTANCE PHASER_IN_PHY)
|
||||
(TIMINGCHECK
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.218::0.231))
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_ADV")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CTSBUS OCLK (0.351::0.373)(0.529::0.562))
|
||||
(IOPATH DQSBUS OCLK (0.346::0.367)(0.518::0.550))
|
||||
(IOPATH DTSBUS OCLK (0.137::0.145)(0.254::0.270))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
|
|
@ -340,36 +324,33 @@
|
|||
(CELL
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_PHY")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH SCANCLK SCANOUT (0.094::0.100)(0.186::0.198))
|
||||
(IOPATH SYSCLK COARSEOVERFLOW (0.143::0.152)(0.274::0.291))
|
||||
(IOPATH SYSCLK FINEOVERFLOW (0.182::0.193)(0.337::0.358))
|
||||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.126::0.134))
|
||||
(HOLD BURSTPENDING (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP BURSTPENDING (posedge SYSCLK) (0.126::0.134))
|
||||
(HOLD COARSEENABLE (posedge SYSCLK) (0.050::0.053))
|
||||
(SETUP COARSEENABLE (posedge SYSCLK) (0.114::0.121))
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.133::0.141))
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.050::0.053))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.099::0.105))
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.050::0.053))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.073::0.077))
|
||||
(HOLD COARSEINC (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP COARSEINC (posedge SYSCLK) (0.133::0.141))
|
||||
(HOLD COUNTERLOADEN (posedge SYSCLK) (0.050::0.053))
|
||||
(SETUP COUNTERLOADEN (posedge SYSCLK) (0.099::0.105))
|
||||
(HOLD COUNTERLOADVAL (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP COUNTERLOADVAL (posedge SYSCLK) (0.168::0.178))
|
||||
(HOLD COUNTERREADEN (posedge SYSCLK) (0.050::0.053))
|
||||
(SETUP COUNTERREADEN (posedge SYSCLK) (0.073::0.077))
|
||||
(HOLD EDGEADV (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP EDGEADV (posedge SYSCLK) (0.027::0.029))
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.050::0.053))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.169::0.179))
|
||||
(HOLD ENCALIB (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP ENCALIB (posedge SYSCLK) (0.176::0.187))
|
||||
(HOLD FINEENABLE (posedge SYSCLK) (0.050::0.053))
|
||||
(SETUP FINEENABLE (posedge SYSCLK) (0.169::0.179))
|
||||
(HOLD FINEINC (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP FINEINC (posedge SYSCLK) (0.050::0.053))
|
||||
(HOLD SCANENB (posedge SCANCLK) (0.000::0.000))
|
||||
(SETUP SCANENB (posedge SCANCLK) (0.488::0.518))
|
||||
(HOLD SCANIN (posedge SCANCLK) (0.000::0.000))
|
||||
(SETUP SCANIN (posedge SCANCLK) (0.194::0.206))
|
||||
(HOLD SCANCLK (posedge SCANCLK) (0.000::0.000))
|
||||
(SETUP SCANCLK (posedge SCANCLK) (0.966::1.026))
|
||||
(HOLD SCANMODEB (posedge SCANCLK) (0.000::0.000))
|
||||
(SETUP SCANMODEB (posedge SCANCLK) (0.966::1.026))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
|
|
@ -492,22 +473,6 @@
|
|||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_PHY_COUNTERLOADVAL")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
(TIMINGCHECK
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.168::0.178))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_PHY_ENCALIB")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
(TIMINGCHECK
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.176::0.187))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_PHY_OUTPUT_CLK_SRC_FREQ_REF")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_IN_PHY_PHASER_IN_PHYPHASER_IN_OUTPUT_CLK_SRC_DELAYED_MEM_REF")
|
||||
|
|
@ -65,30 +65,33 @@
|
|||
(IOPATH MEMREFCLK DQSFOUND (0.204::0.217)(0.379::0.402))
|
||||
(IOPATH RST DQSOUTOFRANGE (0.094::0.100)(0.186::0.198))
|
||||
(IOPATH RST PHASELOCKED (0.094::0.100)(0.186::0.198))
|
||||
(IOPATH SCANCLK SCANOUT (0.094::0.100)(0.186::0.198))
|
||||
(IOPATH SYSCLK FINEOVERFLOW (0.344::0.365)(0.667::0.708))
|
||||
(IOPATH SYSCLK STG1OVERFLOW (0.230::0.244)(0.431::0.458))
|
||||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD BURSTPENDING (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP BURSTPENDING (posedge SYSCLK) (0.040::0.042))
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.050::0.053))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.099::0.105))
|
||||
(HOLD COUNTERLOADEN (posedge SYSCLK) (0.050::0.053))
|
||||
(SETUP COUNTERLOADEN (posedge SYSCLK) (0.099::0.105))
|
||||
(HOLD COUNTERLOADVAL (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP COUNTERLOADVAL (posedge SYSCLK) (0.067::0.071))
|
||||
(HOLD COUNTERREADEN (posedge SYSCLK) (0.050::0.053))
|
||||
(SETUP COUNTERREADEN (posedge SYSCLK) (0.095::0.101))
|
||||
(HOLD DIVIDERST (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP DIVIDERST (posedge SYSCLK) (0.091::0.097))
|
||||
(HOLD EDGEADV (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP EDGEADV (posedge SYSCLK) (0.028::0.030))
|
||||
(HOLD ENCALIB (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP ENCALIB (posedge SYSCLK) (0.217::0.230))
|
||||
(HOLD ENSTG1 (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP ENSTG1 (posedge SYSCLK) (0.170::0.180))
|
||||
(HOLD ENSTG1ADJUSTB (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP ENSTG1ADJUSTB (posedge SYSCLK) (0.227::0.241))
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.050::0.053))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.072::0.076))
|
||||
(HOLD FINEENABLE (posedge SYSCLK) (0.050::0.053))
|
||||
(SETUP FINEENABLE (posedge SYSCLK) (0.072::0.076))
|
||||
(HOLD FINEINC (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP FINEINC (posedge SYSCLK) (0.057::0.061))
|
||||
(HOLD RANKSEL (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP RANKSEL (posedge SYSCLK) (0.228::0.242))
|
||||
(HOLD RSTDQSFIND (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP RSTDQSFIND (posedge SYSCLK) (0.156::0.166))
|
||||
(HOLD SCANENB (posedge SCANCLK) (0.000::0.000))
|
||||
|
|
@ -97,30 +100,16 @@
|
|||
(SETUP SCANIN (posedge SCANCLK) (0.030::0.032))
|
||||
(HOLD SCANMODEB (posedge SCANCLK) (0.000::0.000))
|
||||
(SETUP SCANMODEB (posedge SCANCLK) (0.526::0.559))
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.046::0.049))
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.227::0.241))
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.218::0.232))
|
||||
(HOLD SELCALORSTG1 (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP SELCALORSTG1 (posedge SYSCLK) (0.046::0.049))
|
||||
(HOLD STG1INCDEC (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP STG1INCDEC (posedge SYSCLK) (0.227::0.241))
|
||||
(HOLD STG1LOAD (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP STG1LOAD (posedge SYSCLK) (0.218::0.232))
|
||||
(HOLD STG1READ (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP STG1READ (posedge SYSCLK) (0.154::0.164))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_IN_PHY_PHASER_IN_PHYPHASER_IN_PHY_COUNTERLOADVAL")
|
||||
(INSTANCE PHASER_IN_PHY)
|
||||
(TIMINGCHECK
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.067::0.071))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_IN_PHY_PHASER_IN_PHYPHASER_IN_PHY_ENCALIB")
|
||||
(INSTANCE PHASER_IN_PHY)
|
||||
(TIMINGCHECK
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.217::0.230))
|
||||
(HOLD STG1REGL (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP STG1REGL (posedge SYSCLK) (0.218::0.231))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
|
|
@ -196,19 +185,14 @@
|
|||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_IN_PHY_PHASER_IN_PHYPHASER_IN_PHY_RANKSEL")
|
||||
(INSTANCE PHASER_IN_PHY)
|
||||
(TIMINGCHECK
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.228::0.242))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_IN_PHY_PHASER_IN_PHYPHASER_IN_PHY_STG1REGL")
|
||||
(INSTANCE PHASER_IN_PHY)
|
||||
(TIMINGCHECK
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.218::0.231))
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_ADV")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CTSBUS OCLK (0.351::0.373)(0.529::0.562))
|
||||
(IOPATH DQSBUS OCLK (0.346::0.367)(0.518::0.550))
|
||||
(IOPATH DTSBUS OCLK (0.137::0.145)(0.254::0.270))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
|
|
@ -340,36 +324,33 @@
|
|||
(CELL
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_PHY")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH SCANCLK SCANOUT (0.094::0.100)(0.186::0.198))
|
||||
(IOPATH SYSCLK COARSEOVERFLOW (0.143::0.152)(0.274::0.291))
|
||||
(IOPATH SYSCLK FINEOVERFLOW (0.182::0.193)(0.337::0.358))
|
||||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.126::0.134))
|
||||
(HOLD BURSTPENDING (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP BURSTPENDING (posedge SYSCLK) (0.126::0.134))
|
||||
(HOLD COARSEENABLE (posedge SYSCLK) (0.050::0.053))
|
||||
(SETUP COARSEENABLE (posedge SYSCLK) (0.114::0.121))
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.133::0.141))
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.050::0.053))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.099::0.105))
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.050::0.053))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.073::0.077))
|
||||
(HOLD COARSEINC (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP COARSEINC (posedge SYSCLK) (0.133::0.141))
|
||||
(HOLD COUNTERLOADEN (posedge SYSCLK) (0.050::0.053))
|
||||
(SETUP COUNTERLOADEN (posedge SYSCLK) (0.099::0.105))
|
||||
(HOLD COUNTERLOADVAL (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP COUNTERLOADVAL (posedge SYSCLK) (0.168::0.178))
|
||||
(HOLD COUNTERREADEN (posedge SYSCLK) (0.050::0.053))
|
||||
(SETUP COUNTERREADEN (posedge SYSCLK) (0.073::0.077))
|
||||
(HOLD EDGEADV (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP EDGEADV (posedge SYSCLK) (0.027::0.029))
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.050::0.053))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.169::0.179))
|
||||
(HOLD ENCALIB (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP ENCALIB (posedge SYSCLK) (0.176::0.187))
|
||||
(HOLD FINEENABLE (posedge SYSCLK) (0.050::0.053))
|
||||
(SETUP FINEENABLE (posedge SYSCLK) (0.169::0.179))
|
||||
(HOLD FINEINC (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP FINEINC (posedge SYSCLK) (0.050::0.053))
|
||||
(HOLD SCANENB (posedge SCANCLK) (0.000::0.000))
|
||||
(SETUP SCANENB (posedge SCANCLK) (0.488::0.518))
|
||||
(HOLD SCANIN (posedge SCANCLK) (0.000::0.000))
|
||||
(SETUP SCANIN (posedge SCANCLK) (0.194::0.206))
|
||||
(HOLD SCANCLK (posedge SCANCLK) (0.000::0.000))
|
||||
(SETUP SCANCLK (posedge SCANCLK) (0.966::1.026))
|
||||
(HOLD SCANMODEB (posedge SCANCLK) (0.000::0.000))
|
||||
(SETUP SCANMODEB (posedge SCANCLK) (0.966::1.026))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
|
|
@ -492,22 +473,6 @@
|
|||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_PHY_COUNTERLOADVAL")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
(TIMINGCHECK
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.168::0.178))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_PHY_ENCALIB")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
(TIMINGCHECK
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.176::0.187))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_PHY_OUTPUT_CLK_SRC_FREQ_REF")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
|
|
@ -531,45 +496,19 @@
|
|||
(CELL
|
||||
(CELLTYPE "PHY_CONTROL_PHY_CONTROLPHY_CONTROL")
|
||||
(INSTANCE PHY_CONTROL)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH MEMREFCLK PHYCTLEMPTY (0.313::0.360)(0.541::0.622))
|
||||
(IOPATH PHYCLK PHYCTLALMOSTFULL (0.158::0.182)(0.338::0.389))
|
||||
(IOPATH PHYCLK PHYCTLFULL (0.151::0.174)(0.321::0.369))
|
||||
(IOPATH PHYCLK PHYCTLREADY (0.174::0.200)(0.368::0.423))
|
||||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD MEMREFCLK (posedge MEMREFCLK) (0.203::0.233))
|
||||
(SETUP MEMREFCLK (posedge MEMREFCLK) (0.010::0.011))
|
||||
(HOLD PHYCLK (posedge PHYCLK) (0.049::0.056))
|
||||
(SETUP PHYCLK (posedge PHYCLK) (0.327::0.376))
|
||||
(HOLD MEMREFCLK (posedge MEMREFCLK) (0.151::0.174))
|
||||
(SETUP MEMREFCLK (posedge MEMREFCLK) (0.158::0.182))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHY_CONTROL_PHY_CONTROLPHY_CONTROL_PHYCTLWD")
|
||||
(INSTANCE PHY_CONTROL)
|
||||
(TIMINGCHECK
|
||||
(HOLD PHYCLK (posedge PHYCLK) (0.172::0.198))
|
||||
(SETUP PHYCLK (posedge PHYCLK) (0.215::0.248))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHY_CONTROL_PHY_CONTROLPHY_CONTROL_TESTINPUT")
|
||||
(INSTANCE PHY_CONTROL)
|
||||
(TIMINGCHECK
|
||||
(HOLD MEMREFCLK (posedge MEMREFCLK) (0.049::0.056))
|
||||
(SETUP MEMREFCLK (posedge MEMREFCLK) (0.244::0.281))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHY_CONTROL_PHY_CONTROLPHY_CONTROL_TESTSELECT")
|
||||
(INSTANCE PHY_CONTROL)
|
||||
(TIMINGCHECK
|
||||
(HOLD MEMREFCLK (posedge MEMREFCLK) (0.049::0.056))
|
||||
(SETUP MEMREFCLK (posedge MEMREFCLK) (0.244::0.281))
|
||||
(HOLD PHYCTLMSTREMPTY (posedge MEMREFCLK) (0.203::0.233))
|
||||
(SETUP PHYCTLMSTREMPTY (posedge MEMREFCLK) (0.010::0.011))
|
||||
(HOLD PHYCTLWD (posedge PHYCLK) (0.172::0.198))
|
||||
(SETUP PHYCTLWD (posedge PHYCLK) (0.215::0.248))
|
||||
(HOLD PHYCTLWRENABLE (posedge PHYCLK) (0.049::0.056))
|
||||
(SETUP PHYCTLWRENABLE (posedge PHYCLK) (0.327::0.376))
|
||||
(HOLD SYNCIN (posedge MEMREFCLK) (0.151::0.174))
|
||||
(SETUP SYNCIN (posedge MEMREFCLK) (0.158::0.182))
|
||||
(HOLD TESTINPUT (posedge MEMREFCLK) (0.049::0.056))
|
||||
(SETUP TESTINPUT (posedge MEMREFCLK) (0.244::0.281))
|
||||
(HOLD TESTSELECT (posedge MEMREFCLK) (0.049::0.056))
|
||||
(SETUP TESTSELECT (posedge MEMREFCLK) (0.244::0.281))
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -1,144 +1,131 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
(CELL
|
||||
(CELLTYPE "PLLE2_ADV_PLLE2_ADVPLLE2_ADV")
|
||||
(INSTANCE PLLE2_ADV)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH DCLK DRDY (0.286::0.304)(0.927::0.984))
|
||||
(IOPATH RST LOCKED (3.000::3.000)(3.000::3.000))
|
||||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD DADDR (posedge DCLK) (0.141::0.150))
|
||||
(SETUP DADDR (posedge DCLK) (1.527::1.622))
|
||||
(HOLD DEN (posedge DCLK) (0.000::0.000))
|
||||
(SETUP DEN (posedge DCLK) (2.156::2.290))
|
||||
(HOLD DCLK (posedge DCLK) (0.141::0.150))
|
||||
(SETUP DCLK (posedge DCLK) (1.527::1.622))
|
||||
(HOLD DI (posedge DCLK) (0.141::0.150))
|
||||
(SETUP DI (posedge DCLK) (1.527::1.622))
|
||||
(HOLD DWE (posedge DCLK) (0.141::0.150))
|
||||
(SETUP DWE (posedge DCLK) (1.527::1.622))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PLLE2_ADV_PLLE2_ADVPLLE2_ADV_COMPENSATION_BUF_IN")
|
||||
(CELLTYPE "PLLE2_ADV_PLLE2_ADVPLLE2_ADV_00")
|
||||
(INSTANCE PLLE2_ADV)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLKIN1 CLKFBOUT (0.144::-0.210)(0.360::-0.140))
|
||||
(IOPATH CLKIN1 CLKOUT0 (0.144::-0.210)(0.360::-0.140))
|
||||
(IOPATH CLKIN1 CLKOUT1 (0.144::-0.210)(0.360::-0.140))
|
||||
(IOPATH CLKIN1 CLKOUT2 (0.144::-0.210)(0.360::-0.140))
|
||||
(IOPATH CLKIN1 CLKOUT3 (0.144::-0.210)(0.360::-0.140))
|
||||
(IOPATH CLKIN1 CLKOUT4 (0.144::-0.210)(0.360::-0.140))
|
||||
(IOPATH CLKIN1 CLKOUT5 (0.144::-0.210)(0.360::-0.140))
|
||||
(IOPATH CLKIN2 CLKFBOUT (0.144::-0.210)(0.360::-0.140))
|
||||
(IOPATH CLKIN2 CLKOUT0 (0.144::-0.210)(0.360::-0.140))
|
||||
(IOPATH CLKIN2 CLKOUT1 (0.144::-0.210)(0.360::-0.140))
|
||||
(IOPATH CLKIN2 CLKOUT2 (0.144::-0.210)(0.360::-0.140))
|
||||
(IOPATH CLKIN2 CLKOUT3 (0.144::-0.210)(0.360::-0.140))
|
||||
(IOPATH CLKIN2 CLKOUT4 (0.144::-0.210)(0.360::-0.140))
|
||||
(IOPATH CLKIN2 CLKOUT5 (0.144::-0.210)(0.360::-0.140))
|
||||
(IOPATH TMUX_MUX_SEL TMUXOUT (0.527::0.560)(0.979::1.040))
|
||||
(IOPATH TMUX_MUX_SEL TMUXOUT (0.527::0.560)(0.979::1.040))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PLLE2_ADV_PLLE2_ADVPLLE2_ADV_COMPENSATION_EXTERNAL")
|
||||
(CELLTYPE "PLLE2_ADV_PLLE2_ADVPLLE2_ADV_01")
|
||||
(INSTANCE PLLE2_ADV)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLKIN1 CLKFBOUT (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT0 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT1 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT2 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT3 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT4 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT5 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKFBOUT (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT0 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT1 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT2 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT3 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT4 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT5 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH TMUX_MUX_SEL TMUXOUT (0.527::0.560)(0.979::1.040))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PLLE2_ADV_PLLE2_ADVPLLE2_ADV_COMPENSATION_INTERNAL")
|
||||
(CELLTYPE "PLLE2_ADV_PLLE2_ADVPLLE2_ADV_BUF_IN")
|
||||
(INSTANCE PLLE2_ADV)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLKIN1 CLKFBOUT (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN1 CLKOUT0 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN1 CLKOUT1 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN1 CLKOUT2 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN1 CLKOUT3 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN1 CLKOUT4 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN1 CLKOUT5 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN2 CLKFBOUT (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN2 CLKOUT0 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN2 CLKOUT1 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN2 CLKOUT2 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN2 CLKOUT3 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN2 CLKOUT4 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN2 CLKOUT5 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH COMPENSATION CLKFBOUT (0.144::-0.210)(0.360::-0.140))
|
||||
(IOPATH COMPENSATION CLKOUT0 (0.144::-0.210)(0.360::-0.140))
|
||||
(IOPATH COMPENSATION CLKOUT1 (0.144::-0.210)(0.360::-0.140))
|
||||
(IOPATH COMPENSATION CLKOUT2 (0.144::-0.210)(0.360::-0.140))
|
||||
(IOPATH COMPENSATION CLKOUT3 (0.144::-0.210)(0.360::-0.140))
|
||||
(IOPATH COMPENSATION CLKOUT4 (0.144::-0.210)(0.360::-0.140))
|
||||
(IOPATH COMPENSATION CLKOUT5 (0.144::-0.210)(0.360::-0.140))
|
||||
(IOPATH COMPENSATION CLKFBOUT (0.144::-0.210)(0.360::-0.140))
|
||||
(IOPATH COMPENSATION CLKOUT0 (0.144::-0.210)(0.360::-0.140))
|
||||
(IOPATH COMPENSATION CLKOUT1 (0.144::-0.210)(0.360::-0.140))
|
||||
(IOPATH COMPENSATION CLKOUT2 (0.144::-0.210)(0.360::-0.140))
|
||||
(IOPATH COMPENSATION CLKOUT3 (0.144::-0.210)(0.360::-0.140))
|
||||
(IOPATH COMPENSATION CLKOUT4 (0.144::-0.210)(0.360::-0.140))
|
||||
(IOPATH COMPENSATION CLKOUT5 (0.144::-0.210)(0.360::-0.140))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PLLE2_ADV_PLLE2_ADVPLLE2_ADV_COMPENSATION_ZHOLD")
|
||||
(CELLTYPE "PLLE2_ADV_PLLE2_ADVPLLE2_ADV_EXTERNAL")
|
||||
(INSTANCE PLLE2_ADV)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLKIN1 CLKFBOUT (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT0 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT1 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT2 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT3 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT4 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT5 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKFBOUT (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT0 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT1 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT2 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT3 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT4 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT5 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKFBOUT (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT0 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT1 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT2 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT3 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT4 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT5 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKFBOUT (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT0 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT1 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT2 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT3 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT4 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT5 (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PLLE2_ADV_PLLE2_ADVPLLE2_ADV_DADDR")
|
||||
(INSTANCE PLLE2_ADV)
|
||||
(TIMINGCHECK
|
||||
(HOLD DCLK (posedge DCLK) (0.141::0.150))
|
||||
(SETUP DCLK (posedge DCLK) (1.527::1.622))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PLLE2_ADV_PLLE2_ADVPLLE2_ADV_DI")
|
||||
(INSTANCE PLLE2_ADV)
|
||||
(TIMINGCHECK
|
||||
(HOLD DCLK (posedge DCLK) (0.141::0.150))
|
||||
(SETUP DCLK (posedge DCLK) (1.527::1.622))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PLLE2_ADV_PLLE2_ADVPLLE2_ADV_TMUX_MUX_SEL_00")
|
||||
(CELLTYPE "PLLE2_ADV_PLLE2_ADVPLLE2_ADV_INTERNAL")
|
||||
(INSTANCE PLLE2_ADV)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLKIN1 TMUXOUT (0.527::0.560)(0.979::1.040))
|
||||
(IOPATH CLKIN2 TMUXOUT (0.527::0.560)(0.979::1.040))
|
||||
(IOPATH COMPENSATION CLKFBOUT (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH COMPENSATION CLKOUT0 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH COMPENSATION CLKOUT1 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH COMPENSATION CLKOUT2 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH COMPENSATION CLKOUT3 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH COMPENSATION CLKOUT4 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH COMPENSATION CLKOUT5 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH COMPENSATION CLKFBOUT (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH COMPENSATION CLKOUT0 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH COMPENSATION CLKOUT1 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH COMPENSATION CLKOUT2 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH COMPENSATION CLKOUT3 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH COMPENSATION CLKOUT4 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH COMPENSATION CLKOUT5 (0.050::0.053)(0.083::0.088))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PLLE2_ADV_PLLE2_ADVPLLE2_ADV_TMUX_MUX_SEL_01")
|
||||
(CELLTYPE "PLLE2_ADV_PLLE2_ADVPLLE2_ADV_ZHOLD")
|
||||
(INSTANCE PLLE2_ADV)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLKFBIN TMUXOUT (0.527::0.560)(0.979::1.040))
|
||||
(IOPATH COMPENSATION CLKFBOUT (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT0 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT1 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT2 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT3 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT4 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT5 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKFBOUT (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT0 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT1 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT2 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT3 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT4 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT5 (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
|
|||
|
|
@ -1,14 +1,13 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH DRPCLK DRPRDY (0.530::0.563)(0.836::0.888))
|
||||
(IOPATH PMASCANCLK0 PMASCANOUT6 (0.452::0.720)(1.657::2.640))
|
||||
(IOPATH PMASCANCLK1 PMASCANOUT0 (0.452::0.720)(1.657::2.640))
|
||||
(IOPATH PMASCANCLK1 PMASCANOUT1 (0.452::0.720)(1.657::2.640))
|
||||
|
|
@ -16,104 +15,101 @@
|
|||
(IOPATH PMASCANCLK1 PMASCANOUT3 (0.452::0.720)(1.657::2.640))
|
||||
(IOPATH PMASCANCLK2 PMASCANOUT4 (0.452::0.720)(1.657::2.640))
|
||||
(IOPATH PMASCANCLK3 PMASCANOUT5 (0.452::0.720)(1.657::2.640))
|
||||
(IOPATH RXUSRCLK2 PHYSTATUS (0.472::0.501)(1.021::1.084))
|
||||
(IOPATH RXUSRCLK2 RXBYTEISALIGNED (0.490::0.520)(1.012::1.075))
|
||||
(IOPATH RXUSRCLK2 RXBYTEREALIGN (0.492::0.522)(1.001::1.063))
|
||||
(IOPATH RXUSRCLK2 RXCHANBONDSEQ (0.449::0.477)(1.030::1.094))
|
||||
(IOPATH RXUSRCLK2 RXCHANISALIGNED (0.498::0.529)(1.002::1.064))
|
||||
(IOPATH RXUSRCLK2 RXCHANREALIGN (0.452::0.480)(1.022::1.085))
|
||||
(IOPATH RXUSRCLK2 RXCOMINITDET (0.494::0.525)(0.978::1.039))
|
||||
(IOPATH RXUSRCLK2 RXCOMMADET (0.445::0.473)(0.921::0.978))
|
||||
(IOPATH RXUSRCLK2 RXCOMSASDET (0.511::0.543)(1.026::1.090))
|
||||
(IOPATH RXUSRCLK2 RXCOMWAKEDET (0.509::0.541)(1.054::1.119))
|
||||
(IOPATH RXUSRCLK2 RXHEADERVALID (0.437::0.464)(0.991::1.052))
|
||||
(IOPATH RXUSRCLK2 RXPRBSERR (0.470::0.499)(0.955::1.014))
|
||||
(IOPATH RXUSRCLK2 RXRATEDONE (0.471::0.500)(0.962::1.022))
|
||||
(IOPATH RXUSRCLK2 RXRESETDONE (0.525::0.558)(0.954::1.013))
|
||||
(IOPATH RXUSRCLK2 RXVALID (0.480::0.510)(1.016::1.079))
|
||||
(IOPATH TXUSRCLK2 TXCOMFINISH (0.899::1.055)(1.101::1.293))
|
||||
(IOPATH TXUSRCLK2 TXGEARBOXREADY (0.470::0.499)(1.026::1.090))
|
||||
(IOPATH TXUSRCLK2 TXRATEDONE (0.487::0.517)(1.005::1.067))
|
||||
(IOPATH TXUSRCLK2 TXRESETDONE (0.482::0.512)(0.973::1.033))
|
||||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD DRPCLK (posedge DRPCLK) (0.160::0.170))
|
||||
(SETUP DRPCLK (posedge DRPCLK) (0.380::0.403))
|
||||
(HOLD DRPCLK (posedge DRPCLK) (0.140::0.149))
|
||||
(SETUP DRPCLK (posedge DRPCLK) (0.380::0.403))
|
||||
(HOLD RXUSRCLK2 (posedge RXUSRCLK2) (0.105::0.111))
|
||||
(SETUP RXUSRCLK2 (posedge RXUSRCLK2) (0.680::0.722))
|
||||
(HOLD RXUSRCLK2 (posedge RXUSRCLK2) (0.107::0.114))
|
||||
(SETUP RXUSRCLK2 (posedge RXUSRCLK2) (0.680::0.722))
|
||||
(HOLD DRPADDR (posedge DRPCLK) (0.172::0.183))
|
||||
(SETUP DRPADDR (posedge DRPCLK) (0.380::0.403))
|
||||
(HOLD DRPDI (posedge DRPCLK) (0.154::0.164))
|
||||
(SETUP DRPDI (posedge DRPCLK) (0.380::0.403))
|
||||
(HOLD DRPEN (posedge DRPCLK) (0.160::0.170))
|
||||
(SETUP DRPEN (posedge DRPCLK) (0.380::0.403))
|
||||
(HOLD DRPWE (posedge DRPCLK) (0.140::0.149))
|
||||
(SETUP DRPWE (posedge DRPCLK) (0.380::0.403))
|
||||
(HOLD RX8B10BEN (posedge RXUSRCLK2) (0.105::0.111))
|
||||
(SETUP RX8B10BEN (posedge RXUSRCLK2) (0.680::0.722))
|
||||
(HOLD RXCHBONDEN (posedge RXUSRCLK2) (0.107::0.114))
|
||||
(SETUP RXCHBONDEN (posedge RXUSRCLK2) (0.680::0.722))
|
||||
(HOLD RXCHBONDLEVEL (posedge RXUSRCLK2) (0.113::0.120))
|
||||
(SETUP RXCHBONDLEVEL (posedge RXUSRCLK2) (0.680::0.722))
|
||||
(HOLD RXCHBONDMASTER (posedge RXUSRCLK2) (0.097::0.103))
|
||||
(SETUP RXCHBONDMASTER (posedge RXUSRCLK2) (0.680::0.722))
|
||||
(HOLD RXUSRCLK2 (posedge RXUSRCLK2) (0.098::0.104))
|
||||
(SETUP RXUSRCLK2 (posedge RXUSRCLK2) (0.680::0.722))
|
||||
(HOLD RXUSRCLK2 (posedge RXUSRCLK2) (0.100::0.106))
|
||||
(SETUP RXUSRCLK2 (posedge RXUSRCLK2) (0.680::0.722))
|
||||
(HOLD RXUSRCLK2 (posedge RXUSRCLK2) (0.095::0.101))
|
||||
(SETUP RXUSRCLK2 (posedge RXUSRCLK2) (0.680::0.722))
|
||||
(HOLD RXCHBONDSLAVE (posedge RXUSRCLK2) (0.098::0.104))
|
||||
(SETUP RXCHBONDSLAVE (posedge RXUSRCLK2) (0.680::0.722))
|
||||
(HOLD RXCOMMADETEN (posedge RXUSRCLK2) (0.100::0.106))
|
||||
(SETUP RXCOMMADETEN (posedge RXUSRCLK2) (0.680::0.722))
|
||||
(HOLD RXGEARBOXSLIP (posedge RXUSRCLK2) (0.095::0.101))
|
||||
(SETUP RXGEARBOXSLIP (posedge RXUSRCLK2) (0.680::0.722))
|
||||
(HOLD RXMCOMMAALIGNEN (posedge RXUSRCLK2) (0.129::0.137))
|
||||
(SETUP RXMCOMMAALIGNEN (posedge RXUSRCLK2) (0.680::0.722))
|
||||
(HOLD RXUSRCLK2 (posedge RXUSRCLK2) (0.132::0.140))
|
||||
(SETUP RXUSRCLK2 (posedge RXUSRCLK2) (0.680::0.722))
|
||||
(HOLD RXUSRCLK2 (posedge RXUSRCLK2) (0.116::0.123))
|
||||
(SETUP RXUSRCLK2 (posedge RXUSRCLK2) (0.680::0.722))
|
||||
(HOLD RXUSRCLK2 (posedge RXUSRCLK2) (0.132::0.140))
|
||||
(SETUP RXUSRCLK2 (posedge RXUSRCLK2) (0.680::0.722))
|
||||
(HOLD RXPCOMMAALIGNEN (posedge RXUSRCLK2) (0.132::0.140))
|
||||
(SETUP RXPCOMMAALIGNEN (posedge RXUSRCLK2) (0.680::0.722))
|
||||
(HOLD RXPOLARITY (posedge RXUSRCLK2) (0.116::0.123))
|
||||
(SETUP RXPOLARITY (posedge RXUSRCLK2) (0.680::0.722))
|
||||
(HOLD RXPRBSCNTRESET (posedge RXUSRCLK2) (0.132::0.140))
|
||||
(SETUP RXPRBSCNTRESET (posedge RXUSRCLK2) (0.680::0.722))
|
||||
(HOLD RXPRBSSEL (posedge RXUSRCLK2) (0.121::0.128))
|
||||
(SETUP RXPRBSSEL (posedge RXUSRCLK2) (0.680::0.722))
|
||||
(HOLD RXRATE (posedge RXUSRCLK2) (0.119::0.126))
|
||||
(SETUP RXRATE (posedge RXUSRCLK2) (0.680::0.722))
|
||||
(HOLD RXSLIDE (posedge RXUSRCLK2) (0.133::0.141))
|
||||
(SETUP RXSLIDE (posedge RXUSRCLK2) (0.680::0.722))
|
||||
(HOLD SCANCLK (posedge SCANCLK) (0.723::0.832))
|
||||
(SETUP SCANCLK (posedge SCANCLK) (1.220::1.404))
|
||||
(HOLD SCANENB (posedge SCANCLK) (0.723::0.832))
|
||||
(SETUP SCANENB (posedge SCANCLK) (1.220::1.404))
|
||||
(HOLD SCANIN (posedge SCANCLK) (0.723::0.832))
|
||||
(SETUP SCANIN (posedge SCANCLK) (1.220::1.404))
|
||||
(HOLD SCANMODEB (posedge SCANCLK) (0.723::0.832))
|
||||
(SETUP SCANMODEB (posedge SCANCLK) (1.220::1.404))
|
||||
(HOLD SETERRSTATUS (posedge RXUSRCLK2) (0.209::0.246))
|
||||
(SETUP SETERRSTATUS (posedge RXUSRCLK2) (0.680::0.722))
|
||||
(HOLD TX8B10BBYPASS (posedge TXUSRCLK2) (0.161::0.171))
|
||||
(SETUP TX8B10BBYPASS (posedge TXUSRCLK2) (0.680::0.722))
|
||||
(HOLD TX8B10BEN (posedge TXUSRCLK2) (0.153::0.163))
|
||||
(SETUP TX8B10BEN (posedge TXUSRCLK2) (0.680::0.722))
|
||||
(HOLD TXCHARDISPMODE (posedge TXUSRCLK2) (0.170::0.181))
|
||||
(SETUP TXCHARDISPMODE (posedge TXUSRCLK2) (0.680::0.722))
|
||||
(HOLD TXCHARDISPVAL (posedge TXUSRCLK2) (0.167::0.177))
|
||||
(SETUP TXCHARDISPVAL (posedge TXUSRCLK2) (0.680::0.722))
|
||||
(HOLD TXCHARISK (posedge TXUSRCLK2) (0.160::0.170))
|
||||
(SETUP TXCHARISK (posedge TXUSRCLK2) (0.680::0.722))
|
||||
(HOLD TXCOMINIT (posedge TXUSRCLK2) (0.172::0.183))
|
||||
(SETUP TXCOMINIT (posedge TXUSRCLK2) (0.680::0.722))
|
||||
(HOLD TXCOMSAS (posedge TXUSRCLK2) (0.136::0.144))
|
||||
(SETUP TXCOMSAS (posedge TXUSRCLK2) (0.680::0.722))
|
||||
(HOLD TXUSRCLK2 (posedge TXUSRCLK2) (0.160::0.170))
|
||||
(SETUP TXUSRCLK2 (posedge TXUSRCLK2) (0.680::0.722))
|
||||
(HOLD TXUSRCLK2 (posedge TXUSRCLK2) (0.169::0.179))
|
||||
(SETUP TXUSRCLK2 (posedge TXUSRCLK2) (0.680::0.722))
|
||||
(HOLD TXCOMWAKE (posedge TXUSRCLK2) (0.160::0.170))
|
||||
(SETUP TXCOMWAKE (posedge TXUSRCLK2) (0.680::0.722))
|
||||
(HOLD TXDATA (posedge TXUSRCLK2) (0.173::0.184))
|
||||
(SETUP TXDATA (posedge TXUSRCLK2) (0.680::0.722))
|
||||
(HOLD TXDETECTRX (posedge TXUSRCLK2) (0.169::0.179))
|
||||
(SETUP TXDETECTRX (posedge TXUSRCLK2) (0.680::0.722))
|
||||
(HOLD TXDLYHOLD (posedge TXPHDLYTSTCLK) (0.387::0.617))
|
||||
(SETUP TXDLYHOLD (posedge TXPHDLYTSTCLK) (0.581::0.925))
|
||||
(HOLD TXPHDLYTSTCLK (posedge TXPHDLYTSTCLK) (0.387::0.617))
|
||||
(SETUP TXPHDLYTSTCLK (posedge TXPHDLYTSTCLK) (0.581::0.925))
|
||||
(HOLD TXDLYUPDOWN (posedge TXPHDLYTSTCLK) (0.387::0.617))
|
||||
(SETUP TXDLYUPDOWN (posedge TXPHDLYTSTCLK) (0.581::0.925))
|
||||
(HOLD TXELECIDLE (posedge TXUSRCLK2) (0.072::0.076))
|
||||
(SETUP TXELECIDLE (posedge TXUSRCLK2) (0.680::0.722))
|
||||
(HOLD TXHEADER (posedge TXUSRCLK2) (0.167::0.177))
|
||||
(SETUP TXHEADER (posedge TXUSRCLK2) (0.680::0.722))
|
||||
(HOLD TXINHIBIT (posedge TXUSRCLK2) (0.153::0.162))
|
||||
(SETUP TXINHIBIT (posedge TXUSRCLK2) (0.680::0.722))
|
||||
(HOLD TXUSRCLK2 (posedge TXUSRCLK2) (0.143::0.152))
|
||||
(SETUP TXUSRCLK2 (posedge TXUSRCLK2) (0.680::0.722))
|
||||
(HOLD TXUSRCLK2 (posedge TXUSRCLK2) (0.160::0.170))
|
||||
(SETUP TXUSRCLK2 (posedge TXUSRCLK2) (0.680::0.722))
|
||||
(HOLD TXUSRCLK2 (posedge TXUSRCLK2) (0.148::0.157))
|
||||
(SETUP TXUSRCLK2 (posedge TXUSRCLK2) (0.680::0.722))
|
||||
(HOLD TXPD (posedge TXUSRCLK2) (0.209::0.246))
|
||||
(SETUP TXPD (posedge TXUSRCLK2) (0.680::0.722))
|
||||
(HOLD TXPOLARITY (posedge TXUSRCLK2) (0.143::0.152))
|
||||
(SETUP TXPOLARITY (posedge TXUSRCLK2) (0.680::0.722))
|
||||
(HOLD TXPRBSFORCEERR (posedge TXUSRCLK2) (0.160::0.170))
|
||||
(SETUP TXPRBSFORCEERR (posedge TXUSRCLK2) (0.680::0.722))
|
||||
(HOLD TXPRBSSEL (posedge TXUSRCLK2) (0.160::0.170))
|
||||
(SETUP TXPRBSSEL (posedge TXUSRCLK2) (0.680::0.722))
|
||||
(HOLD TXRATE (posedge TXUSRCLK2) (0.153::0.162))
|
||||
(SETUP TXRATE (posedge TXUSRCLK2) (0.680::0.722))
|
||||
(HOLD TXSEQUENCE (posedge TXUSRCLK2) (0.172::0.183))
|
||||
(SETUP TXSEQUENCE (posedge TXUSRCLK2) (0.680::0.722))
|
||||
(HOLD TXSTARTSEQ (posedge TXUSRCLK2) (0.148::0.157))
|
||||
(SETUP TXSTARTSEQ (posedge TXUSRCLK2) (0.680::0.722))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_DRPADDR")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD DRPCLK (posedge DRPCLK) (0.172::0.183))
|
||||
(SETUP DRPCLK (posedge DRPCLK) (0.380::0.403))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_DRPDI")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD DRPCLK (posedge DRPCLK) (0.154::0.164))
|
||||
(SETUP DRPCLK (posedge DRPCLK) (0.380::0.403))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXCHBONDI_GEN_RXUSRCLK_FALSE_RX_DATA_WIDTH_16")
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXCHBONDI_GEN_FALSE_RX_DATA_WIDTH_16")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD RXUSRCLK (posedge RXUSRCLK) (0.159::0.183))
|
||||
|
|
@ -121,7 +117,7 @@
|
|||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXCHBONDI_GEN_RXUSRCLK_FALSE_RX_DATA_WIDTH_20")
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXCHBONDI_GEN_FALSE_RX_DATA_WIDTH_20")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD RXUSRCLK (posedge RXUSRCLK) (0.159::0.183))
|
||||
|
|
@ -129,7 +125,7 @@
|
|||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXCHBONDI_GEN_RXUSRCLK_FALSE_RX_DATA_WIDTH_32")
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXCHBONDI_GEN_FALSE_RX_DATA_WIDTH_32")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD RXUSRCLK (posedge RXUSRCLK) (0.159::0.183))
|
||||
|
|
@ -137,7 +133,7 @@
|
|||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXCHBONDI_GEN_RXUSRCLK_FALSE_RX_DATA_WIDTH_40")
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXCHBONDI_GEN_FALSE_RX_DATA_WIDTH_40")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD RXUSRCLK (posedge RXUSRCLK) (0.159::0.183))
|
||||
|
|
@ -145,7 +141,23 @@
|
|||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXCHBONDI_GEN_RXUSRCLK_TRUE_RX_DATA_WIDTH_32")
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXCHBONDI_GEN_TRUE_16")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD RX_DATA_WIDTH (posedge RXUSRCLK2) (0.159::0.183))
|
||||
(SETUP RX_DATA_WIDTH (posedge RXUSRCLK2) (0.328::0.378))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXCHBONDI_GEN_TRUE_20")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD RX_DATA_WIDTH (posedge RXUSRCLK2) (0.159::0.183))
|
||||
(SETUP RX_DATA_WIDTH (posedge RXUSRCLK2) (0.328::0.378))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXCHBONDI_GEN_TRUE_RX_DATA_WIDTH_32")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD RXUSRCLK (posedge RXUSRCLK) (0.159::0.183))
|
||||
|
|
@ -153,117 +165,13 @@
|
|||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXCHBONDI_GEN_RXUSRCLK_TRUE_RX_DATA_WIDTH_40")
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXCHBONDI_GEN_TRUE_RX_DATA_WIDTH_40")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD RXUSRCLK (posedge RXUSRCLK) (0.159::0.183))
|
||||
(SETUP RXUSRCLK (posedge RXUSRCLK) (0.328::0.378))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXCHBONDI_GEN_TRUE_RX_DATA_WIDTH_16")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD RXUSRCLK2 (posedge RXUSRCLK2) (0.159::0.183))
|
||||
(SETUP RXUSRCLK2 (posedge RXUSRCLK2) (0.328::0.378))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXCHBONDI_GEN_TRUE_RX_DATA_WIDTH_20")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD RXUSRCLK2 (posedge RXUSRCLK2) (0.159::0.183))
|
||||
(SETUP RXUSRCLK2 (posedge RXUSRCLK2) (0.328::0.378))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXCHBONDLEVEL")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD RXUSRCLK2 (posedge RXUSRCLK2) (0.113::0.120))
|
||||
(SETUP RXUSRCLK2 (posedge RXUSRCLK2) (0.680::0.722))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXPRBSSEL")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD RXUSRCLK2 (posedge RXUSRCLK2) (0.121::0.128))
|
||||
(SETUP RXUSRCLK2 (posedge RXUSRCLK2) (0.680::0.722))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXRATE")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD RXUSRCLK2 (posedge RXUSRCLK2) (0.119::0.126))
|
||||
(SETUP RXUSRCLK2 (posedge RXUSRCLK2) (0.680::0.722))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_SCANIN")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD SCANCLK (posedge SCANCLK) (0.723::0.832))
|
||||
(SETUP SCANCLK (posedge SCANCLK) (1.220::1.404))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_TX8B10BBYPASS")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD TXUSRCLK2 (posedge TXUSRCLK2) (0.161::0.171))
|
||||
(SETUP TXUSRCLK2 (posedge TXUSRCLK2) (0.680::0.722))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_TXCHARDISPMODE")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD TXUSRCLK2 (posedge TXUSRCLK2) (0.170::0.181))
|
||||
(SETUP TXUSRCLK2 (posedge TXUSRCLK2) (0.680::0.722))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_TXCHARDISPVAL")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD TXUSRCLK2 (posedge TXUSRCLK2) (0.167::0.177))
|
||||
(SETUP TXUSRCLK2 (posedge TXUSRCLK2) (0.680::0.722))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_TXCHARISK")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD TXUSRCLK2 (posedge TXUSRCLK2) (0.160::0.170))
|
||||
(SETUP TXUSRCLK2 (posedge TXUSRCLK2) (0.680::0.722))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_TXDATA")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD TXUSRCLK2 (posedge TXUSRCLK2) (0.173::0.184))
|
||||
(SETUP TXUSRCLK2 (posedge TXUSRCLK2) (0.680::0.722))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_TXHEADER")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD TXUSRCLK2 (posedge TXUSRCLK2) (0.167::0.177))
|
||||
(SETUP TXUSRCLK2 (posedge TXUSRCLK2) (0.680::0.722))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_TXPD")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD TXUSRCLK2 (posedge TXUSRCLK2) (0.209::0.246))
|
||||
(SETUP TXUSRCLK2 (posedge TXUSRCLK2) (0.680::0.722))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_TXPI_PPMCLK_SEL_TXUSRCLK")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
|
|
@ -281,43 +189,13 @@
|
|||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_TXPIPPMSTEPSIZE_TXPI_PPMCLK_SEL_TXUSRCLK")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD TXUSRCLK (posedge TXUSRCLK) (0.158::0.168))
|
||||
(SETUP TXUSRCLK (posedge TXUSRCLK) (0.466::0.495))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_TXPIPPMSTEPSIZE_TXPI_PPMCLK_SEL_TXUSRCLK2")
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_TXPIPPMSTEPSIZE_TXPI_PPMCLK_SEL")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD TXUSRCLK2 (posedge TXUSRCLK2) (0.158::0.168))
|
||||
(SETUP TXUSRCLK2 (posedge TXUSRCLK2) (0.466::0.495))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_TXPRBSSEL")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD TXUSRCLK2 (posedge TXUSRCLK2) (0.160::0.170))
|
||||
(SETUP TXUSRCLK2 (posedge TXUSRCLK2) (0.680::0.722))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_TXRATE")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD TXUSRCLK2 (posedge TXUSRCLK2) (0.153::0.162))
|
||||
(SETUP TXUSRCLK2 (posedge TXUSRCLK2) (0.680::0.722))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_TXSEQUENCE")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD TXUSRCLK2 (posedge TXUSRCLK2) (0.172::0.183))
|
||||
(SETUP TXUSRCLK2 (posedge TXUSRCLK2) (0.680::0.722))
|
||||
(HOLD TXUSRCLK (posedge TXUSRCLK) (0.158::0.168))
|
||||
(SETUP TXUSRCLK (posedge TXUSRCLK) (0.466::0.495))
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -1,14 +1,13 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH DRPCLK DRPRDY (0.530::0.563)(0.836::0.888))
|
||||
(IOPATH PMASCANCLK0 PMASCANOUT6 (0.452::0.720)(1.657::2.640))
|
||||
(IOPATH PMASCANCLK1 PMASCANOUT0 (0.452::0.720)(1.657::2.640))
|
||||
(IOPATH PMASCANCLK1 PMASCANOUT1 (0.452::0.720)(1.657::2.640))
|
||||
|
|
@ -16,104 +15,101 @@
|
|||
(IOPATH PMASCANCLK1 PMASCANOUT3 (0.452::0.720)(1.657::2.640))
|
||||
(IOPATH PMASCANCLK2 PMASCANOUT4 (0.452::0.720)(1.657::2.640))
|
||||
(IOPATH PMASCANCLK3 PMASCANOUT5 (0.452::0.720)(1.657::2.640))
|
||||
(IOPATH RXUSRCLK2 PHYSTATUS (0.472::0.501)(1.021::1.084))
|
||||
(IOPATH RXUSRCLK2 RXBYTEISALIGNED (0.490::0.520)(1.012::1.075))
|
||||
(IOPATH RXUSRCLK2 RXBYTEREALIGN (0.492::0.522)(1.001::1.063))
|
||||
(IOPATH RXUSRCLK2 RXCHANBONDSEQ (0.449::0.477)(1.030::1.094))
|
||||
(IOPATH RXUSRCLK2 RXCHANISALIGNED (0.498::0.529)(1.002::1.064))
|
||||
(IOPATH RXUSRCLK2 RXCHANREALIGN (0.452::0.480)(1.022::1.085))
|
||||
(IOPATH RXUSRCLK2 RXCOMINITDET (0.494::0.525)(0.978::1.039))
|
||||
(IOPATH RXUSRCLK2 RXCOMMADET (0.445::0.473)(0.921::0.978))
|
||||
(IOPATH RXUSRCLK2 RXCOMSASDET (0.511::0.543)(1.026::1.090))
|
||||
(IOPATH RXUSRCLK2 RXCOMWAKEDET (0.509::0.541)(1.054::1.119))
|
||||
(IOPATH RXUSRCLK2 RXHEADERVALID (0.437::0.464)(0.991::1.052))
|
||||
(IOPATH RXUSRCLK2 RXPRBSERR (0.470::0.499)(0.955::1.014))
|
||||
(IOPATH RXUSRCLK2 RXRATEDONE (0.471::0.500)(0.962::1.022))
|
||||
(IOPATH RXUSRCLK2 RXRESETDONE (0.525::0.558)(0.954::1.013))
|
||||
(IOPATH RXUSRCLK2 RXVALID (0.480::0.510)(1.016::1.079))
|
||||
(IOPATH TXUSRCLK2 TXCOMFINISH (0.899::1.055)(1.101::1.293))
|
||||
(IOPATH TXUSRCLK2 TXGEARBOXREADY (0.470::0.499)(1.026::1.090))
|
||||
(IOPATH TXUSRCLK2 TXRATEDONE (0.487::0.517)(1.005::1.067))
|
||||
(IOPATH TXUSRCLK2 TXRESETDONE (0.482::0.512)(0.973::1.033))
|
||||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD DRPCLK (posedge DRPCLK) (0.160::0.170))
|
||||
(SETUP DRPCLK (posedge DRPCLK) (0.380::0.403))
|
||||
(HOLD DRPCLK (posedge DRPCLK) (0.140::0.149))
|
||||
(SETUP DRPCLK (posedge DRPCLK) (0.380::0.403))
|
||||
(HOLD RXUSRCLK2 (posedge RXUSRCLK2) (0.105::0.111))
|
||||
(SETUP RXUSRCLK2 (posedge RXUSRCLK2) (0.680::0.722))
|
||||
(HOLD RXUSRCLK2 (posedge RXUSRCLK2) (0.107::0.114))
|
||||
(SETUP RXUSRCLK2 (posedge RXUSRCLK2) (0.680::0.722))
|
||||
(HOLD DRPADDR (posedge DRPCLK) (0.172::0.183))
|
||||
(SETUP DRPADDR (posedge DRPCLK) (0.380::0.403))
|
||||
(HOLD DRPDI (posedge DRPCLK) (0.154::0.164))
|
||||
(SETUP DRPDI (posedge DRPCLK) (0.380::0.403))
|
||||
(HOLD DRPEN (posedge DRPCLK) (0.160::0.170))
|
||||
(SETUP DRPEN (posedge DRPCLK) (0.380::0.403))
|
||||
(HOLD DRPWE (posedge DRPCLK) (0.140::0.149))
|
||||
(SETUP DRPWE (posedge DRPCLK) (0.380::0.403))
|
||||
(HOLD RX8B10BEN (posedge RXUSRCLK2) (0.105::0.111))
|
||||
(SETUP RX8B10BEN (posedge RXUSRCLK2) (0.680::0.722))
|
||||
(HOLD RXCHBONDEN (posedge RXUSRCLK2) (0.107::0.114))
|
||||
(SETUP RXCHBONDEN (posedge RXUSRCLK2) (0.680::0.722))
|
||||
(HOLD RXCHBONDLEVEL (posedge RXUSRCLK2) (0.113::0.120))
|
||||
(SETUP RXCHBONDLEVEL (posedge RXUSRCLK2) (0.680::0.722))
|
||||
(HOLD RXCHBONDMASTER (posedge RXUSRCLK2) (0.097::0.103))
|
||||
(SETUP RXCHBONDMASTER (posedge RXUSRCLK2) (0.680::0.722))
|
||||
(HOLD RXUSRCLK2 (posedge RXUSRCLK2) (0.098::0.104))
|
||||
(SETUP RXUSRCLK2 (posedge RXUSRCLK2) (0.680::0.722))
|
||||
(HOLD RXUSRCLK2 (posedge RXUSRCLK2) (0.100::0.106))
|
||||
(SETUP RXUSRCLK2 (posedge RXUSRCLK2) (0.680::0.722))
|
||||
(HOLD RXUSRCLK2 (posedge RXUSRCLK2) (0.095::0.101))
|
||||
(SETUP RXUSRCLK2 (posedge RXUSRCLK2) (0.680::0.722))
|
||||
(HOLD RXCHBONDSLAVE (posedge RXUSRCLK2) (0.098::0.104))
|
||||
(SETUP RXCHBONDSLAVE (posedge RXUSRCLK2) (0.680::0.722))
|
||||
(HOLD RXCOMMADETEN (posedge RXUSRCLK2) (0.100::0.106))
|
||||
(SETUP RXCOMMADETEN (posedge RXUSRCLK2) (0.680::0.722))
|
||||
(HOLD RXGEARBOXSLIP (posedge RXUSRCLK2) (0.095::0.101))
|
||||
(SETUP RXGEARBOXSLIP (posedge RXUSRCLK2) (0.680::0.722))
|
||||
(HOLD RXMCOMMAALIGNEN (posedge RXUSRCLK2) (0.129::0.137))
|
||||
(SETUP RXMCOMMAALIGNEN (posedge RXUSRCLK2) (0.680::0.722))
|
||||
(HOLD RXUSRCLK2 (posedge RXUSRCLK2) (0.132::0.140))
|
||||
(SETUP RXUSRCLK2 (posedge RXUSRCLK2) (0.680::0.722))
|
||||
(HOLD RXUSRCLK2 (posedge RXUSRCLK2) (0.116::0.123))
|
||||
(SETUP RXUSRCLK2 (posedge RXUSRCLK2) (0.680::0.722))
|
||||
(HOLD RXUSRCLK2 (posedge RXUSRCLK2) (0.132::0.140))
|
||||
(SETUP RXUSRCLK2 (posedge RXUSRCLK2) (0.680::0.722))
|
||||
(HOLD RXPCOMMAALIGNEN (posedge RXUSRCLK2) (0.132::0.140))
|
||||
(SETUP RXPCOMMAALIGNEN (posedge RXUSRCLK2) (0.680::0.722))
|
||||
(HOLD RXPOLARITY (posedge RXUSRCLK2) (0.116::0.123))
|
||||
(SETUP RXPOLARITY (posedge RXUSRCLK2) (0.680::0.722))
|
||||
(HOLD RXPRBSCNTRESET (posedge RXUSRCLK2) (0.132::0.140))
|
||||
(SETUP RXPRBSCNTRESET (posedge RXUSRCLK2) (0.680::0.722))
|
||||
(HOLD RXPRBSSEL (posedge RXUSRCLK2) (0.121::0.128))
|
||||
(SETUP RXPRBSSEL (posedge RXUSRCLK2) (0.680::0.722))
|
||||
(HOLD RXRATE (posedge RXUSRCLK2) (0.119::0.126))
|
||||
(SETUP RXRATE (posedge RXUSRCLK2) (0.680::0.722))
|
||||
(HOLD RXSLIDE (posedge RXUSRCLK2) (0.133::0.141))
|
||||
(SETUP RXSLIDE (posedge RXUSRCLK2) (0.680::0.722))
|
||||
(HOLD SCANCLK (posedge SCANCLK) (0.723::0.832))
|
||||
(SETUP SCANCLK (posedge SCANCLK) (1.220::1.404))
|
||||
(HOLD SCANENB (posedge SCANCLK) (0.723::0.832))
|
||||
(SETUP SCANENB (posedge SCANCLK) (1.220::1.404))
|
||||
(HOLD SCANIN (posedge SCANCLK) (0.723::0.832))
|
||||
(SETUP SCANIN (posedge SCANCLK) (1.220::1.404))
|
||||
(HOLD SCANMODEB (posedge SCANCLK) (0.723::0.832))
|
||||
(SETUP SCANMODEB (posedge SCANCLK) (1.220::1.404))
|
||||
(HOLD SETERRSTATUS (posedge RXUSRCLK2) (0.209::0.246))
|
||||
(SETUP SETERRSTATUS (posedge RXUSRCLK2) (0.680::0.722))
|
||||
(HOLD TX8B10BBYPASS (posedge TXUSRCLK2) (0.161::0.171))
|
||||
(SETUP TX8B10BBYPASS (posedge TXUSRCLK2) (0.680::0.722))
|
||||
(HOLD TX8B10BEN (posedge TXUSRCLK2) (0.153::0.163))
|
||||
(SETUP TX8B10BEN (posedge TXUSRCLK2) (0.680::0.722))
|
||||
(HOLD TXCHARDISPMODE (posedge TXUSRCLK2) (0.170::0.181))
|
||||
(SETUP TXCHARDISPMODE (posedge TXUSRCLK2) (0.680::0.722))
|
||||
(HOLD TXCHARDISPVAL (posedge TXUSRCLK2) (0.167::0.177))
|
||||
(SETUP TXCHARDISPVAL (posedge TXUSRCLK2) (0.680::0.722))
|
||||
(HOLD TXCHARISK (posedge TXUSRCLK2) (0.160::0.170))
|
||||
(SETUP TXCHARISK (posedge TXUSRCLK2) (0.680::0.722))
|
||||
(HOLD TXCOMINIT (posedge TXUSRCLK2) (0.172::0.183))
|
||||
(SETUP TXCOMINIT (posedge TXUSRCLK2) (0.680::0.722))
|
||||
(HOLD TXCOMSAS (posedge TXUSRCLK2) (0.136::0.144))
|
||||
(SETUP TXCOMSAS (posedge TXUSRCLK2) (0.680::0.722))
|
||||
(HOLD TXUSRCLK2 (posedge TXUSRCLK2) (0.160::0.170))
|
||||
(SETUP TXUSRCLK2 (posedge TXUSRCLK2) (0.680::0.722))
|
||||
(HOLD TXUSRCLK2 (posedge TXUSRCLK2) (0.169::0.179))
|
||||
(SETUP TXUSRCLK2 (posedge TXUSRCLK2) (0.680::0.722))
|
||||
(HOLD TXCOMWAKE (posedge TXUSRCLK2) (0.160::0.170))
|
||||
(SETUP TXCOMWAKE (posedge TXUSRCLK2) (0.680::0.722))
|
||||
(HOLD TXDATA (posedge TXUSRCLK2) (0.173::0.184))
|
||||
(SETUP TXDATA (posedge TXUSRCLK2) (0.680::0.722))
|
||||
(HOLD TXDETECTRX (posedge TXUSRCLK2) (0.169::0.179))
|
||||
(SETUP TXDETECTRX (posedge TXUSRCLK2) (0.680::0.722))
|
||||
(HOLD TXDLYHOLD (posedge TXPHDLYTSTCLK) (0.387::0.617))
|
||||
(SETUP TXDLYHOLD (posedge TXPHDLYTSTCLK) (0.581::0.925))
|
||||
(HOLD TXPHDLYTSTCLK (posedge TXPHDLYTSTCLK) (0.387::0.617))
|
||||
(SETUP TXPHDLYTSTCLK (posedge TXPHDLYTSTCLK) (0.581::0.925))
|
||||
(HOLD TXDLYUPDOWN (posedge TXPHDLYTSTCLK) (0.387::0.617))
|
||||
(SETUP TXDLYUPDOWN (posedge TXPHDLYTSTCLK) (0.581::0.925))
|
||||
(HOLD TXELECIDLE (posedge TXUSRCLK2) (0.072::0.076))
|
||||
(SETUP TXELECIDLE (posedge TXUSRCLK2) (0.680::0.722))
|
||||
(HOLD TXHEADER (posedge TXUSRCLK2) (0.167::0.177))
|
||||
(SETUP TXHEADER (posedge TXUSRCLK2) (0.680::0.722))
|
||||
(HOLD TXINHIBIT (posedge TXUSRCLK2) (0.153::0.162))
|
||||
(SETUP TXINHIBIT (posedge TXUSRCLK2) (0.680::0.722))
|
||||
(HOLD TXUSRCLK2 (posedge TXUSRCLK2) (0.143::0.152))
|
||||
(SETUP TXUSRCLK2 (posedge TXUSRCLK2) (0.680::0.722))
|
||||
(HOLD TXUSRCLK2 (posedge TXUSRCLK2) (0.160::0.170))
|
||||
(SETUP TXUSRCLK2 (posedge TXUSRCLK2) (0.680::0.722))
|
||||
(HOLD TXUSRCLK2 (posedge TXUSRCLK2) (0.148::0.157))
|
||||
(SETUP TXUSRCLK2 (posedge TXUSRCLK2) (0.680::0.722))
|
||||
(HOLD TXPD (posedge TXUSRCLK2) (0.209::0.246))
|
||||
(SETUP TXPD (posedge TXUSRCLK2) (0.680::0.722))
|
||||
(HOLD TXPOLARITY (posedge TXUSRCLK2) (0.143::0.152))
|
||||
(SETUP TXPOLARITY (posedge TXUSRCLK2) (0.680::0.722))
|
||||
(HOLD TXPRBSFORCEERR (posedge TXUSRCLK2) (0.160::0.170))
|
||||
(SETUP TXPRBSFORCEERR (posedge TXUSRCLK2) (0.680::0.722))
|
||||
(HOLD TXPRBSSEL (posedge TXUSRCLK2) (0.160::0.170))
|
||||
(SETUP TXPRBSSEL (posedge TXUSRCLK2) (0.680::0.722))
|
||||
(HOLD TXRATE (posedge TXUSRCLK2) (0.153::0.162))
|
||||
(SETUP TXRATE (posedge TXUSRCLK2) (0.680::0.722))
|
||||
(HOLD TXSEQUENCE (posedge TXUSRCLK2) (0.172::0.183))
|
||||
(SETUP TXSEQUENCE (posedge TXUSRCLK2) (0.680::0.722))
|
||||
(HOLD TXSTARTSEQ (posedge TXUSRCLK2) (0.148::0.157))
|
||||
(SETUP TXSTARTSEQ (posedge TXUSRCLK2) (0.680::0.722))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_DRPADDR")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD DRPCLK (posedge DRPCLK) (0.172::0.183))
|
||||
(SETUP DRPCLK (posedge DRPCLK) (0.380::0.403))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_DRPDI")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD DRPCLK (posedge DRPCLK) (0.154::0.164))
|
||||
(SETUP DRPCLK (posedge DRPCLK) (0.380::0.403))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXCHBONDI_GEN_RXUSRCLK_FALSE_RX_DATA_WIDTH_16")
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXCHBONDI_GEN_FALSE_RX_DATA_WIDTH_16")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD RXUSRCLK (posedge RXUSRCLK) (0.159::0.183))
|
||||
|
|
@ -121,7 +117,7 @@
|
|||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXCHBONDI_GEN_RXUSRCLK_FALSE_RX_DATA_WIDTH_20")
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXCHBONDI_GEN_FALSE_RX_DATA_WIDTH_20")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD RXUSRCLK (posedge RXUSRCLK) (0.159::0.183))
|
||||
|
|
@ -129,7 +125,7 @@
|
|||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXCHBONDI_GEN_RXUSRCLK_FALSE_RX_DATA_WIDTH_32")
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXCHBONDI_GEN_FALSE_RX_DATA_WIDTH_32")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD RXUSRCLK (posedge RXUSRCLK) (0.159::0.183))
|
||||
|
|
@ -137,7 +133,7 @@
|
|||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXCHBONDI_GEN_RXUSRCLK_FALSE_RX_DATA_WIDTH_40")
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXCHBONDI_GEN_FALSE_RX_DATA_WIDTH_40")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD RXUSRCLK (posedge RXUSRCLK) (0.159::0.183))
|
||||
|
|
@ -145,7 +141,23 @@
|
|||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXCHBONDI_GEN_RXUSRCLK_TRUE_RX_DATA_WIDTH_32")
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXCHBONDI_GEN_TRUE_16")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD RX_DATA_WIDTH (posedge RXUSRCLK2) (0.159::0.183))
|
||||
(SETUP RX_DATA_WIDTH (posedge RXUSRCLK2) (0.328::0.378))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXCHBONDI_GEN_TRUE_20")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD RX_DATA_WIDTH (posedge RXUSRCLK2) (0.159::0.183))
|
||||
(SETUP RX_DATA_WIDTH (posedge RXUSRCLK2) (0.328::0.378))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXCHBONDI_GEN_TRUE_RX_DATA_WIDTH_32")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD RXUSRCLK (posedge RXUSRCLK) (0.159::0.183))
|
||||
|
|
@ -153,117 +165,13 @@
|
|||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXCHBONDI_GEN_RXUSRCLK_TRUE_RX_DATA_WIDTH_40")
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXCHBONDI_GEN_TRUE_RX_DATA_WIDTH_40")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD RXUSRCLK (posedge RXUSRCLK) (0.159::0.183))
|
||||
(SETUP RXUSRCLK (posedge RXUSRCLK) (0.328::0.378))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXCHBONDI_GEN_TRUE_RX_DATA_WIDTH_16")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD RXUSRCLK2 (posedge RXUSRCLK2) (0.159::0.183))
|
||||
(SETUP RXUSRCLK2 (posedge RXUSRCLK2) (0.328::0.378))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXCHBONDI_GEN_TRUE_RX_DATA_WIDTH_20")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD RXUSRCLK2 (posedge RXUSRCLK2) (0.159::0.183))
|
||||
(SETUP RXUSRCLK2 (posedge RXUSRCLK2) (0.328::0.378))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXCHBONDLEVEL")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD RXUSRCLK2 (posedge RXUSRCLK2) (0.113::0.120))
|
||||
(SETUP RXUSRCLK2 (posedge RXUSRCLK2) (0.680::0.722))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXPRBSSEL")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD RXUSRCLK2 (posedge RXUSRCLK2) (0.121::0.128))
|
||||
(SETUP RXUSRCLK2 (posedge RXUSRCLK2) (0.680::0.722))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXRATE")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD RXUSRCLK2 (posedge RXUSRCLK2) (0.119::0.126))
|
||||
(SETUP RXUSRCLK2 (posedge RXUSRCLK2) (0.680::0.722))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_SCANIN")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD SCANCLK (posedge SCANCLK) (0.723::0.832))
|
||||
(SETUP SCANCLK (posedge SCANCLK) (1.220::1.404))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_TX8B10BBYPASS")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD TXUSRCLK2 (posedge TXUSRCLK2) (0.161::0.171))
|
||||
(SETUP TXUSRCLK2 (posedge TXUSRCLK2) (0.680::0.722))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_TXCHARDISPMODE")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD TXUSRCLK2 (posedge TXUSRCLK2) (0.170::0.181))
|
||||
(SETUP TXUSRCLK2 (posedge TXUSRCLK2) (0.680::0.722))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_TXCHARDISPVAL")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD TXUSRCLK2 (posedge TXUSRCLK2) (0.167::0.177))
|
||||
(SETUP TXUSRCLK2 (posedge TXUSRCLK2) (0.680::0.722))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_TXCHARISK")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD TXUSRCLK2 (posedge TXUSRCLK2) (0.160::0.170))
|
||||
(SETUP TXUSRCLK2 (posedge TXUSRCLK2) (0.680::0.722))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_TXDATA")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD TXUSRCLK2 (posedge TXUSRCLK2) (0.173::0.184))
|
||||
(SETUP TXUSRCLK2 (posedge TXUSRCLK2) (0.680::0.722))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_TXHEADER")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD TXUSRCLK2 (posedge TXUSRCLK2) (0.167::0.177))
|
||||
(SETUP TXUSRCLK2 (posedge TXUSRCLK2) (0.680::0.722))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_TXPD")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD TXUSRCLK2 (posedge TXUSRCLK2) (0.209::0.246))
|
||||
(SETUP TXUSRCLK2 (posedge TXUSRCLK2) (0.680::0.722))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_TXPI_PPMCLK_SEL_TXUSRCLK")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
|
|
@ -281,43 +189,13 @@
|
|||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_TXPIPPMSTEPSIZE_TXPI_PPMCLK_SEL_TXUSRCLK")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD TXUSRCLK (posedge TXUSRCLK) (0.158::0.168))
|
||||
(SETUP TXUSRCLK (posedge TXUSRCLK) (0.466::0.495))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_TXPIPPMSTEPSIZE_TXPI_PPMCLK_SEL_TXUSRCLK2")
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_TXPIPPMSTEPSIZE_TXPI_PPMCLK_SEL")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD TXUSRCLK2 (posedge TXUSRCLK2) (0.158::0.168))
|
||||
(SETUP TXUSRCLK2 (posedge TXUSRCLK2) (0.466::0.495))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_TXPRBSSEL")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD TXUSRCLK2 (posedge TXUSRCLK2) (0.160::0.170))
|
||||
(SETUP TXUSRCLK2 (posedge TXUSRCLK2) (0.680::0.722))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_TXRATE")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD TXUSRCLK2 (posedge TXUSRCLK2) (0.153::0.162))
|
||||
(SETUP TXUSRCLK2 (posedge TXUSRCLK2) (0.680::0.722))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_TXSEQUENCE")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD TXUSRCLK2 (posedge TXUSRCLK2) (0.172::0.183))
|
||||
(SETUP TXUSRCLK2 (posedge TXUSRCLK2) (0.680::0.722))
|
||||
(HOLD TXUSRCLK (posedge TXUSRCLK) (0.158::0.168))
|
||||
(SETUP TXUSRCLK (posedge TXUSRCLK) (0.466::0.495))
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -1,14 +1,13 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH DRPCLK DRPRDY (0.530::0.563)(0.836::0.888))
|
||||
(IOPATH PMASCANCLK0 PMASCANOUT6 (0.452::0.720)(1.657::2.640))
|
||||
(IOPATH PMASCANCLK1 PMASCANOUT0 (0.452::0.720)(1.657::2.640))
|
||||
(IOPATH PMASCANCLK1 PMASCANOUT1 (0.452::0.720)(1.657::2.640))
|
||||
|
|
@ -16,104 +15,101 @@
|
|||
(IOPATH PMASCANCLK1 PMASCANOUT3 (0.452::0.720)(1.657::2.640))
|
||||
(IOPATH PMASCANCLK2 PMASCANOUT4 (0.452::0.720)(1.657::2.640))
|
||||
(IOPATH PMASCANCLK3 PMASCANOUT5 (0.452::0.720)(1.657::2.640))
|
||||
(IOPATH RXUSRCLK2 PHYSTATUS (0.472::0.501)(1.021::1.084))
|
||||
(IOPATH RXUSRCLK2 RXBYTEISALIGNED (0.490::0.520)(1.012::1.075))
|
||||
(IOPATH RXUSRCLK2 RXBYTEREALIGN (0.492::0.522)(1.001::1.063))
|
||||
(IOPATH RXUSRCLK2 RXCHANBONDSEQ (0.449::0.477)(1.030::1.094))
|
||||
(IOPATH RXUSRCLK2 RXCHANISALIGNED (0.498::0.529)(1.002::1.064))
|
||||
(IOPATH RXUSRCLK2 RXCHANREALIGN (0.452::0.480)(1.022::1.085))
|
||||
(IOPATH RXUSRCLK2 RXCOMINITDET (0.494::0.525)(0.978::1.039))
|
||||
(IOPATH RXUSRCLK2 RXCOMMADET (0.445::0.473)(0.921::0.978))
|
||||
(IOPATH RXUSRCLK2 RXCOMSASDET (0.511::0.543)(1.026::1.090))
|
||||
(IOPATH RXUSRCLK2 RXCOMWAKEDET (0.509::0.541)(1.054::1.119))
|
||||
(IOPATH RXUSRCLK2 RXHEADERVALID (0.437::0.464)(0.991::1.052))
|
||||
(IOPATH RXUSRCLK2 RXPRBSERR (0.470::0.499)(0.955::1.014))
|
||||
(IOPATH RXUSRCLK2 RXRATEDONE (0.471::0.500)(0.962::1.022))
|
||||
(IOPATH RXUSRCLK2 RXRESETDONE (0.525::0.558)(0.954::1.013))
|
||||
(IOPATH RXUSRCLK2 RXVALID (0.480::0.510)(1.016::1.079))
|
||||
(IOPATH TXUSRCLK2 TXCOMFINISH (0.899::1.055)(1.101::1.293))
|
||||
(IOPATH TXUSRCLK2 TXGEARBOXREADY (0.470::0.499)(1.026::1.090))
|
||||
(IOPATH TXUSRCLK2 TXRATEDONE (0.487::0.517)(1.005::1.067))
|
||||
(IOPATH TXUSRCLK2 TXRESETDONE (0.482::0.512)(0.973::1.033))
|
||||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD DRPCLK (posedge DRPCLK) (0.160::0.170))
|
||||
(SETUP DRPCLK (posedge DRPCLK) (0.380::0.403))
|
||||
(HOLD DRPCLK (posedge DRPCLK) (0.140::0.149))
|
||||
(SETUP DRPCLK (posedge DRPCLK) (0.380::0.403))
|
||||
(HOLD RXUSRCLK2 (posedge RXUSRCLK2) (0.105::0.111))
|
||||
(SETUP RXUSRCLK2 (posedge RXUSRCLK2) (0.680::0.722))
|
||||
(HOLD RXUSRCLK2 (posedge RXUSRCLK2) (0.107::0.114))
|
||||
(SETUP RXUSRCLK2 (posedge RXUSRCLK2) (0.680::0.722))
|
||||
(HOLD DRPADDR (posedge DRPCLK) (0.172::0.183))
|
||||
(SETUP DRPADDR (posedge DRPCLK) (0.380::0.403))
|
||||
(HOLD DRPDI (posedge DRPCLK) (0.154::0.164))
|
||||
(SETUP DRPDI (posedge DRPCLK) (0.380::0.403))
|
||||
(HOLD DRPEN (posedge DRPCLK) (0.160::0.170))
|
||||
(SETUP DRPEN (posedge DRPCLK) (0.380::0.403))
|
||||
(HOLD DRPWE (posedge DRPCLK) (0.140::0.149))
|
||||
(SETUP DRPWE (posedge DRPCLK) (0.380::0.403))
|
||||
(HOLD RX8B10BEN (posedge RXUSRCLK2) (0.105::0.111))
|
||||
(SETUP RX8B10BEN (posedge RXUSRCLK2) (0.680::0.722))
|
||||
(HOLD RXCHBONDEN (posedge RXUSRCLK2) (0.107::0.114))
|
||||
(SETUP RXCHBONDEN (posedge RXUSRCLK2) (0.680::0.722))
|
||||
(HOLD RXCHBONDLEVEL (posedge RXUSRCLK2) (0.113::0.120))
|
||||
(SETUP RXCHBONDLEVEL (posedge RXUSRCLK2) (0.680::0.722))
|
||||
(HOLD RXCHBONDMASTER (posedge RXUSRCLK2) (0.097::0.103))
|
||||
(SETUP RXCHBONDMASTER (posedge RXUSRCLK2) (0.680::0.722))
|
||||
(HOLD RXUSRCLK2 (posedge RXUSRCLK2) (0.098::0.104))
|
||||
(SETUP RXUSRCLK2 (posedge RXUSRCLK2) (0.680::0.722))
|
||||
(HOLD RXUSRCLK2 (posedge RXUSRCLK2) (0.100::0.106))
|
||||
(SETUP RXUSRCLK2 (posedge RXUSRCLK2) (0.680::0.722))
|
||||
(HOLD RXUSRCLK2 (posedge RXUSRCLK2) (0.095::0.101))
|
||||
(SETUP RXUSRCLK2 (posedge RXUSRCLK2) (0.680::0.722))
|
||||
(HOLD RXCHBONDSLAVE (posedge RXUSRCLK2) (0.098::0.104))
|
||||
(SETUP RXCHBONDSLAVE (posedge RXUSRCLK2) (0.680::0.722))
|
||||
(HOLD RXCOMMADETEN (posedge RXUSRCLK2) (0.100::0.106))
|
||||
(SETUP RXCOMMADETEN (posedge RXUSRCLK2) (0.680::0.722))
|
||||
(HOLD RXGEARBOXSLIP (posedge RXUSRCLK2) (0.095::0.101))
|
||||
(SETUP RXGEARBOXSLIP (posedge RXUSRCLK2) (0.680::0.722))
|
||||
(HOLD RXMCOMMAALIGNEN (posedge RXUSRCLK2) (0.129::0.137))
|
||||
(SETUP RXMCOMMAALIGNEN (posedge RXUSRCLK2) (0.680::0.722))
|
||||
(HOLD RXUSRCLK2 (posedge RXUSRCLK2) (0.132::0.140))
|
||||
(SETUP RXUSRCLK2 (posedge RXUSRCLK2) (0.680::0.722))
|
||||
(HOLD RXUSRCLK2 (posedge RXUSRCLK2) (0.116::0.123))
|
||||
(SETUP RXUSRCLK2 (posedge RXUSRCLK2) (0.680::0.722))
|
||||
(HOLD RXUSRCLK2 (posedge RXUSRCLK2) (0.132::0.140))
|
||||
(SETUP RXUSRCLK2 (posedge RXUSRCLK2) (0.680::0.722))
|
||||
(HOLD RXPCOMMAALIGNEN (posedge RXUSRCLK2) (0.132::0.140))
|
||||
(SETUP RXPCOMMAALIGNEN (posedge RXUSRCLK2) (0.680::0.722))
|
||||
(HOLD RXPOLARITY (posedge RXUSRCLK2) (0.116::0.123))
|
||||
(SETUP RXPOLARITY (posedge RXUSRCLK2) (0.680::0.722))
|
||||
(HOLD RXPRBSCNTRESET (posedge RXUSRCLK2) (0.132::0.140))
|
||||
(SETUP RXPRBSCNTRESET (posedge RXUSRCLK2) (0.680::0.722))
|
||||
(HOLD RXPRBSSEL (posedge RXUSRCLK2) (0.121::0.128))
|
||||
(SETUP RXPRBSSEL (posedge RXUSRCLK2) (0.680::0.722))
|
||||
(HOLD RXRATE (posedge RXUSRCLK2) (0.119::0.126))
|
||||
(SETUP RXRATE (posedge RXUSRCLK2) (0.680::0.722))
|
||||
(HOLD RXSLIDE (posedge RXUSRCLK2) (0.133::0.141))
|
||||
(SETUP RXSLIDE (posedge RXUSRCLK2) (0.680::0.722))
|
||||
(HOLD SCANCLK (posedge SCANCLK) (0.723::0.832))
|
||||
(SETUP SCANCLK (posedge SCANCLK) (1.220::1.404))
|
||||
(HOLD SCANENB (posedge SCANCLK) (0.723::0.832))
|
||||
(SETUP SCANENB (posedge SCANCLK) (1.220::1.404))
|
||||
(HOLD SCANIN (posedge SCANCLK) (0.723::0.832))
|
||||
(SETUP SCANIN (posedge SCANCLK) (1.220::1.404))
|
||||
(HOLD SCANMODEB (posedge SCANCLK) (0.723::0.832))
|
||||
(SETUP SCANMODEB (posedge SCANCLK) (1.220::1.404))
|
||||
(HOLD SETERRSTATUS (posedge RXUSRCLK2) (0.209::0.246))
|
||||
(SETUP SETERRSTATUS (posedge RXUSRCLK2) (0.680::0.722))
|
||||
(HOLD TX8B10BBYPASS (posedge TXUSRCLK2) (0.161::0.171))
|
||||
(SETUP TX8B10BBYPASS (posedge TXUSRCLK2) (0.680::0.722))
|
||||
(HOLD TX8B10BEN (posedge TXUSRCLK2) (0.153::0.163))
|
||||
(SETUP TX8B10BEN (posedge TXUSRCLK2) (0.680::0.722))
|
||||
(HOLD TXCHARDISPMODE (posedge TXUSRCLK2) (0.170::0.181))
|
||||
(SETUP TXCHARDISPMODE (posedge TXUSRCLK2) (0.680::0.722))
|
||||
(HOLD TXCHARDISPVAL (posedge TXUSRCLK2) (0.167::0.177))
|
||||
(SETUP TXCHARDISPVAL (posedge TXUSRCLK2) (0.680::0.722))
|
||||
(HOLD TXCHARISK (posedge TXUSRCLK2) (0.160::0.170))
|
||||
(SETUP TXCHARISK (posedge TXUSRCLK2) (0.680::0.722))
|
||||
(HOLD TXCOMINIT (posedge TXUSRCLK2) (0.172::0.183))
|
||||
(SETUP TXCOMINIT (posedge TXUSRCLK2) (0.680::0.722))
|
||||
(HOLD TXCOMSAS (posedge TXUSRCLK2) (0.136::0.144))
|
||||
(SETUP TXCOMSAS (posedge TXUSRCLK2) (0.680::0.722))
|
||||
(HOLD TXUSRCLK2 (posedge TXUSRCLK2) (0.160::0.170))
|
||||
(SETUP TXUSRCLK2 (posedge TXUSRCLK2) (0.680::0.722))
|
||||
(HOLD TXUSRCLK2 (posedge TXUSRCLK2) (0.169::0.179))
|
||||
(SETUP TXUSRCLK2 (posedge TXUSRCLK2) (0.680::0.722))
|
||||
(HOLD TXCOMWAKE (posedge TXUSRCLK2) (0.160::0.170))
|
||||
(SETUP TXCOMWAKE (posedge TXUSRCLK2) (0.680::0.722))
|
||||
(HOLD TXDATA (posedge TXUSRCLK2) (0.173::0.184))
|
||||
(SETUP TXDATA (posedge TXUSRCLK2) (0.680::0.722))
|
||||
(HOLD TXDETECTRX (posedge TXUSRCLK2) (0.169::0.179))
|
||||
(SETUP TXDETECTRX (posedge TXUSRCLK2) (0.680::0.722))
|
||||
(HOLD TXDLYHOLD (posedge TXPHDLYTSTCLK) (0.387::0.617))
|
||||
(SETUP TXDLYHOLD (posedge TXPHDLYTSTCLK) (0.581::0.925))
|
||||
(HOLD TXPHDLYTSTCLK (posedge TXPHDLYTSTCLK) (0.387::0.617))
|
||||
(SETUP TXPHDLYTSTCLK (posedge TXPHDLYTSTCLK) (0.581::0.925))
|
||||
(HOLD TXDLYUPDOWN (posedge TXPHDLYTSTCLK) (0.387::0.617))
|
||||
(SETUP TXDLYUPDOWN (posedge TXPHDLYTSTCLK) (0.581::0.925))
|
||||
(HOLD TXELECIDLE (posedge TXUSRCLK2) (0.072::0.076))
|
||||
(SETUP TXELECIDLE (posedge TXUSRCLK2) (0.680::0.722))
|
||||
(HOLD TXHEADER (posedge TXUSRCLK2) (0.167::0.177))
|
||||
(SETUP TXHEADER (posedge TXUSRCLK2) (0.680::0.722))
|
||||
(HOLD TXINHIBIT (posedge TXUSRCLK2) (0.153::0.162))
|
||||
(SETUP TXINHIBIT (posedge TXUSRCLK2) (0.680::0.722))
|
||||
(HOLD TXUSRCLK2 (posedge TXUSRCLK2) (0.143::0.152))
|
||||
(SETUP TXUSRCLK2 (posedge TXUSRCLK2) (0.680::0.722))
|
||||
(HOLD TXUSRCLK2 (posedge TXUSRCLK2) (0.160::0.170))
|
||||
(SETUP TXUSRCLK2 (posedge TXUSRCLK2) (0.680::0.722))
|
||||
(HOLD TXUSRCLK2 (posedge TXUSRCLK2) (0.148::0.157))
|
||||
(SETUP TXUSRCLK2 (posedge TXUSRCLK2) (0.680::0.722))
|
||||
(HOLD TXPD (posedge TXUSRCLK2) (0.209::0.246))
|
||||
(SETUP TXPD (posedge TXUSRCLK2) (0.680::0.722))
|
||||
(HOLD TXPOLARITY (posedge TXUSRCLK2) (0.143::0.152))
|
||||
(SETUP TXPOLARITY (posedge TXUSRCLK2) (0.680::0.722))
|
||||
(HOLD TXPRBSFORCEERR (posedge TXUSRCLK2) (0.160::0.170))
|
||||
(SETUP TXPRBSFORCEERR (posedge TXUSRCLK2) (0.680::0.722))
|
||||
(HOLD TXPRBSSEL (posedge TXUSRCLK2) (0.160::0.170))
|
||||
(SETUP TXPRBSSEL (posedge TXUSRCLK2) (0.680::0.722))
|
||||
(HOLD TXRATE (posedge TXUSRCLK2) (0.153::0.162))
|
||||
(SETUP TXRATE (posedge TXUSRCLK2) (0.680::0.722))
|
||||
(HOLD TXSEQUENCE (posedge TXUSRCLK2) (0.172::0.183))
|
||||
(SETUP TXSEQUENCE (posedge TXUSRCLK2) (0.680::0.722))
|
||||
(HOLD TXSTARTSEQ (posedge TXUSRCLK2) (0.148::0.157))
|
||||
(SETUP TXSTARTSEQ (posedge TXUSRCLK2) (0.680::0.722))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_DRPADDR")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD DRPCLK (posedge DRPCLK) (0.172::0.183))
|
||||
(SETUP DRPCLK (posedge DRPCLK) (0.380::0.403))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_DRPDI")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD DRPCLK (posedge DRPCLK) (0.154::0.164))
|
||||
(SETUP DRPCLK (posedge DRPCLK) (0.380::0.403))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXCHBONDI_GEN_RXUSRCLK_FALSE_RX_DATA_WIDTH_16")
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXCHBONDI_GEN_FALSE_RX_DATA_WIDTH_16")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD RXUSRCLK (posedge RXUSRCLK) (0.159::0.183))
|
||||
|
|
@ -121,7 +117,7 @@
|
|||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXCHBONDI_GEN_RXUSRCLK_FALSE_RX_DATA_WIDTH_20")
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXCHBONDI_GEN_FALSE_RX_DATA_WIDTH_20")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD RXUSRCLK (posedge RXUSRCLK) (0.159::0.183))
|
||||
|
|
@ -129,7 +125,7 @@
|
|||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXCHBONDI_GEN_RXUSRCLK_FALSE_RX_DATA_WIDTH_32")
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXCHBONDI_GEN_FALSE_RX_DATA_WIDTH_32")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD RXUSRCLK (posedge RXUSRCLK) (0.159::0.183))
|
||||
|
|
@ -137,7 +133,7 @@
|
|||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXCHBONDI_GEN_RXUSRCLK_FALSE_RX_DATA_WIDTH_40")
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXCHBONDI_GEN_FALSE_RX_DATA_WIDTH_40")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD RXUSRCLK (posedge RXUSRCLK) (0.159::0.183))
|
||||
|
|
@ -145,7 +141,23 @@
|
|||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXCHBONDI_GEN_RXUSRCLK_TRUE_RX_DATA_WIDTH_32")
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXCHBONDI_GEN_TRUE_16")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD RX_DATA_WIDTH (posedge RXUSRCLK2) (0.159::0.183))
|
||||
(SETUP RX_DATA_WIDTH (posedge RXUSRCLK2) (0.328::0.378))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXCHBONDI_GEN_TRUE_20")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD RX_DATA_WIDTH (posedge RXUSRCLK2) (0.159::0.183))
|
||||
(SETUP RX_DATA_WIDTH (posedge RXUSRCLK2) (0.328::0.378))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXCHBONDI_GEN_TRUE_RX_DATA_WIDTH_32")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD RXUSRCLK (posedge RXUSRCLK) (0.159::0.183))
|
||||
|
|
@ -153,117 +165,13 @@
|
|||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXCHBONDI_GEN_RXUSRCLK_TRUE_RX_DATA_WIDTH_40")
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXCHBONDI_GEN_TRUE_RX_DATA_WIDTH_40")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD RXUSRCLK (posedge RXUSRCLK) (0.159::0.183))
|
||||
(SETUP RXUSRCLK (posedge RXUSRCLK) (0.328::0.378))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXCHBONDI_GEN_TRUE_RX_DATA_WIDTH_16")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD RXUSRCLK2 (posedge RXUSRCLK2) (0.159::0.183))
|
||||
(SETUP RXUSRCLK2 (posedge RXUSRCLK2) (0.328::0.378))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXCHBONDI_GEN_TRUE_RX_DATA_WIDTH_20")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD RXUSRCLK2 (posedge RXUSRCLK2) (0.159::0.183))
|
||||
(SETUP RXUSRCLK2 (posedge RXUSRCLK2) (0.328::0.378))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXCHBONDLEVEL")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD RXUSRCLK2 (posedge RXUSRCLK2) (0.113::0.120))
|
||||
(SETUP RXUSRCLK2 (posedge RXUSRCLK2) (0.680::0.722))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXPRBSSEL")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD RXUSRCLK2 (posedge RXUSRCLK2) (0.121::0.128))
|
||||
(SETUP RXUSRCLK2 (posedge RXUSRCLK2) (0.680::0.722))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXRATE")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD RXUSRCLK2 (posedge RXUSRCLK2) (0.119::0.126))
|
||||
(SETUP RXUSRCLK2 (posedge RXUSRCLK2) (0.680::0.722))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_SCANIN")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD SCANCLK (posedge SCANCLK) (0.723::0.832))
|
||||
(SETUP SCANCLK (posedge SCANCLK) (1.220::1.404))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_TX8B10BBYPASS")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD TXUSRCLK2 (posedge TXUSRCLK2) (0.161::0.171))
|
||||
(SETUP TXUSRCLK2 (posedge TXUSRCLK2) (0.680::0.722))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_TXCHARDISPMODE")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD TXUSRCLK2 (posedge TXUSRCLK2) (0.170::0.181))
|
||||
(SETUP TXUSRCLK2 (posedge TXUSRCLK2) (0.680::0.722))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_TXCHARDISPVAL")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD TXUSRCLK2 (posedge TXUSRCLK2) (0.167::0.177))
|
||||
(SETUP TXUSRCLK2 (posedge TXUSRCLK2) (0.680::0.722))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_TXCHARISK")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD TXUSRCLK2 (posedge TXUSRCLK2) (0.160::0.170))
|
||||
(SETUP TXUSRCLK2 (posedge TXUSRCLK2) (0.680::0.722))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_TXDATA")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD TXUSRCLK2 (posedge TXUSRCLK2) (0.173::0.184))
|
||||
(SETUP TXUSRCLK2 (posedge TXUSRCLK2) (0.680::0.722))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_TXHEADER")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD TXUSRCLK2 (posedge TXUSRCLK2) (0.167::0.177))
|
||||
(SETUP TXUSRCLK2 (posedge TXUSRCLK2) (0.680::0.722))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_TXPD")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD TXUSRCLK2 (posedge TXUSRCLK2) (0.209::0.246))
|
||||
(SETUP TXUSRCLK2 (posedge TXUSRCLK2) (0.680::0.722))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_TXPI_PPMCLK_SEL_TXUSRCLK")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
|
|
@ -281,43 +189,13 @@
|
|||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_TXPIPPMSTEPSIZE_TXPI_PPMCLK_SEL_TXUSRCLK")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD TXUSRCLK (posedge TXUSRCLK) (0.158::0.168))
|
||||
(SETUP TXUSRCLK (posedge TXUSRCLK) (0.466::0.495))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_TXPIPPMSTEPSIZE_TXPI_PPMCLK_SEL_TXUSRCLK2")
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_TXPIPPMSTEPSIZE_TXPI_PPMCLK_SEL")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD TXUSRCLK2 (posedge TXUSRCLK2) (0.158::0.168))
|
||||
(SETUP TXUSRCLK2 (posedge TXUSRCLK2) (0.466::0.495))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_TXPRBSSEL")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD TXUSRCLK2 (posedge TXUSRCLK2) (0.160::0.170))
|
||||
(SETUP TXUSRCLK2 (posedge TXUSRCLK2) (0.680::0.722))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_TXRATE")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD TXUSRCLK2 (posedge TXUSRCLK2) (0.153::0.162))
|
||||
(SETUP TXUSRCLK2 (posedge TXUSRCLK2) (0.680::0.722))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_TXSEQUENCE")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD TXUSRCLK2 (posedge TXUSRCLK2) (0.172::0.183))
|
||||
(SETUP TXUSRCLK2 (posedge TXUSRCLK2) (0.680::0.722))
|
||||
(HOLD TXUSRCLK (posedge TXUSRCLK) (0.158::0.168))
|
||||
(SETUP TXUSRCLK (posedge TXUSRCLK) (0.466::0.495))
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -1,14 +1,13 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH DRPCLK DRPRDY (0.530::0.563)(0.836::0.888))
|
||||
(IOPATH PMASCANCLK0 PMASCANOUT6 (0.452::0.720)(1.657::2.640))
|
||||
(IOPATH PMASCANCLK1 PMASCANOUT0 (0.452::0.720)(1.657::2.640))
|
||||
(IOPATH PMASCANCLK1 PMASCANOUT1 (0.452::0.720)(1.657::2.640))
|
||||
|
|
@ -16,104 +15,101 @@
|
|||
(IOPATH PMASCANCLK1 PMASCANOUT3 (0.452::0.720)(1.657::2.640))
|
||||
(IOPATH PMASCANCLK2 PMASCANOUT4 (0.452::0.720)(1.657::2.640))
|
||||
(IOPATH PMASCANCLK3 PMASCANOUT5 (0.452::0.720)(1.657::2.640))
|
||||
(IOPATH RXUSRCLK2 PHYSTATUS (0.472::0.501)(1.021::1.084))
|
||||
(IOPATH RXUSRCLK2 RXBYTEISALIGNED (0.490::0.520)(1.012::1.075))
|
||||
(IOPATH RXUSRCLK2 RXBYTEREALIGN (0.492::0.522)(1.001::1.063))
|
||||
(IOPATH RXUSRCLK2 RXCHANBONDSEQ (0.449::0.477)(1.030::1.094))
|
||||
(IOPATH RXUSRCLK2 RXCHANISALIGNED (0.498::0.529)(1.002::1.064))
|
||||
(IOPATH RXUSRCLK2 RXCHANREALIGN (0.452::0.480)(1.022::1.085))
|
||||
(IOPATH RXUSRCLK2 RXCOMINITDET (0.494::0.525)(0.978::1.039))
|
||||
(IOPATH RXUSRCLK2 RXCOMMADET (0.445::0.473)(0.921::0.978))
|
||||
(IOPATH RXUSRCLK2 RXCOMSASDET (0.511::0.543)(1.026::1.090))
|
||||
(IOPATH RXUSRCLK2 RXCOMWAKEDET (0.509::0.541)(1.054::1.119))
|
||||
(IOPATH RXUSRCLK2 RXHEADERVALID (0.437::0.464)(0.991::1.052))
|
||||
(IOPATH RXUSRCLK2 RXPRBSERR (0.470::0.499)(0.955::1.014))
|
||||
(IOPATH RXUSRCLK2 RXRATEDONE (0.471::0.500)(0.962::1.022))
|
||||
(IOPATH RXUSRCLK2 RXRESETDONE (0.525::0.558)(0.954::1.013))
|
||||
(IOPATH RXUSRCLK2 RXVALID (0.480::0.510)(1.016::1.079))
|
||||
(IOPATH TXUSRCLK2 TXCOMFINISH (0.899::1.055)(1.101::1.293))
|
||||
(IOPATH TXUSRCLK2 TXGEARBOXREADY (0.470::0.499)(1.026::1.090))
|
||||
(IOPATH TXUSRCLK2 TXRATEDONE (0.487::0.517)(1.005::1.067))
|
||||
(IOPATH TXUSRCLK2 TXRESETDONE (0.482::0.512)(0.973::1.033))
|
||||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD DRPCLK (posedge DRPCLK) (0.160::0.170))
|
||||
(SETUP DRPCLK (posedge DRPCLK) (0.380::0.403))
|
||||
(HOLD DRPCLK (posedge DRPCLK) (0.140::0.149))
|
||||
(SETUP DRPCLK (posedge DRPCLK) (0.380::0.403))
|
||||
(HOLD RXUSRCLK2 (posedge RXUSRCLK2) (0.105::0.111))
|
||||
(SETUP RXUSRCLK2 (posedge RXUSRCLK2) (0.680::0.722))
|
||||
(HOLD RXUSRCLK2 (posedge RXUSRCLK2) (0.107::0.114))
|
||||
(SETUP RXUSRCLK2 (posedge RXUSRCLK2) (0.680::0.722))
|
||||
(HOLD DRPADDR (posedge DRPCLK) (0.172::0.183))
|
||||
(SETUP DRPADDR (posedge DRPCLK) (0.380::0.403))
|
||||
(HOLD DRPDI (posedge DRPCLK) (0.154::0.164))
|
||||
(SETUP DRPDI (posedge DRPCLK) (0.380::0.403))
|
||||
(HOLD DRPEN (posedge DRPCLK) (0.160::0.170))
|
||||
(SETUP DRPEN (posedge DRPCLK) (0.380::0.403))
|
||||
(HOLD DRPWE (posedge DRPCLK) (0.140::0.149))
|
||||
(SETUP DRPWE (posedge DRPCLK) (0.380::0.403))
|
||||
(HOLD RX8B10BEN (posedge RXUSRCLK2) (0.105::0.111))
|
||||
(SETUP RX8B10BEN (posedge RXUSRCLK2) (0.680::0.722))
|
||||
(HOLD RXCHBONDEN (posedge RXUSRCLK2) (0.107::0.114))
|
||||
(SETUP RXCHBONDEN (posedge RXUSRCLK2) (0.680::0.722))
|
||||
(HOLD RXCHBONDLEVEL (posedge RXUSRCLK2) (0.113::0.120))
|
||||
(SETUP RXCHBONDLEVEL (posedge RXUSRCLK2) (0.680::0.722))
|
||||
(HOLD RXCHBONDMASTER (posedge RXUSRCLK2) (0.097::0.103))
|
||||
(SETUP RXCHBONDMASTER (posedge RXUSRCLK2) (0.680::0.722))
|
||||
(HOLD RXUSRCLK2 (posedge RXUSRCLK2) (0.098::0.104))
|
||||
(SETUP RXUSRCLK2 (posedge RXUSRCLK2) (0.680::0.722))
|
||||
(HOLD RXUSRCLK2 (posedge RXUSRCLK2) (0.100::0.106))
|
||||
(SETUP RXUSRCLK2 (posedge RXUSRCLK2) (0.680::0.722))
|
||||
(HOLD RXUSRCLK2 (posedge RXUSRCLK2) (0.095::0.101))
|
||||
(SETUP RXUSRCLK2 (posedge RXUSRCLK2) (0.680::0.722))
|
||||
(HOLD RXCHBONDSLAVE (posedge RXUSRCLK2) (0.098::0.104))
|
||||
(SETUP RXCHBONDSLAVE (posedge RXUSRCLK2) (0.680::0.722))
|
||||
(HOLD RXCOMMADETEN (posedge RXUSRCLK2) (0.100::0.106))
|
||||
(SETUP RXCOMMADETEN (posedge RXUSRCLK2) (0.680::0.722))
|
||||
(HOLD RXGEARBOXSLIP (posedge RXUSRCLK2) (0.095::0.101))
|
||||
(SETUP RXGEARBOXSLIP (posedge RXUSRCLK2) (0.680::0.722))
|
||||
(HOLD RXMCOMMAALIGNEN (posedge RXUSRCLK2) (0.129::0.137))
|
||||
(SETUP RXMCOMMAALIGNEN (posedge RXUSRCLK2) (0.680::0.722))
|
||||
(HOLD RXUSRCLK2 (posedge RXUSRCLK2) (0.132::0.140))
|
||||
(SETUP RXUSRCLK2 (posedge RXUSRCLK2) (0.680::0.722))
|
||||
(HOLD RXUSRCLK2 (posedge RXUSRCLK2) (0.116::0.123))
|
||||
(SETUP RXUSRCLK2 (posedge RXUSRCLK2) (0.680::0.722))
|
||||
(HOLD RXUSRCLK2 (posedge RXUSRCLK2) (0.132::0.140))
|
||||
(SETUP RXUSRCLK2 (posedge RXUSRCLK2) (0.680::0.722))
|
||||
(HOLD RXPCOMMAALIGNEN (posedge RXUSRCLK2) (0.132::0.140))
|
||||
(SETUP RXPCOMMAALIGNEN (posedge RXUSRCLK2) (0.680::0.722))
|
||||
(HOLD RXPOLARITY (posedge RXUSRCLK2) (0.116::0.123))
|
||||
(SETUP RXPOLARITY (posedge RXUSRCLK2) (0.680::0.722))
|
||||
(HOLD RXPRBSCNTRESET (posedge RXUSRCLK2) (0.132::0.140))
|
||||
(SETUP RXPRBSCNTRESET (posedge RXUSRCLK2) (0.680::0.722))
|
||||
(HOLD RXPRBSSEL (posedge RXUSRCLK2) (0.121::0.128))
|
||||
(SETUP RXPRBSSEL (posedge RXUSRCLK2) (0.680::0.722))
|
||||
(HOLD RXRATE (posedge RXUSRCLK2) (0.119::0.126))
|
||||
(SETUP RXRATE (posedge RXUSRCLK2) (0.680::0.722))
|
||||
(HOLD RXSLIDE (posedge RXUSRCLK2) (0.133::0.141))
|
||||
(SETUP RXSLIDE (posedge RXUSRCLK2) (0.680::0.722))
|
||||
(HOLD SCANCLK (posedge SCANCLK) (0.723::0.832))
|
||||
(SETUP SCANCLK (posedge SCANCLK) (1.220::1.404))
|
||||
(HOLD SCANENB (posedge SCANCLK) (0.723::0.832))
|
||||
(SETUP SCANENB (posedge SCANCLK) (1.220::1.404))
|
||||
(HOLD SCANIN (posedge SCANCLK) (0.723::0.832))
|
||||
(SETUP SCANIN (posedge SCANCLK) (1.220::1.404))
|
||||
(HOLD SCANMODEB (posedge SCANCLK) (0.723::0.832))
|
||||
(SETUP SCANMODEB (posedge SCANCLK) (1.220::1.404))
|
||||
(HOLD SETERRSTATUS (posedge RXUSRCLK2) (0.209::0.246))
|
||||
(SETUP SETERRSTATUS (posedge RXUSRCLK2) (0.680::0.722))
|
||||
(HOLD TX8B10BBYPASS (posedge TXUSRCLK2) (0.161::0.171))
|
||||
(SETUP TX8B10BBYPASS (posedge TXUSRCLK2) (0.680::0.722))
|
||||
(HOLD TX8B10BEN (posedge TXUSRCLK2) (0.153::0.163))
|
||||
(SETUP TX8B10BEN (posedge TXUSRCLK2) (0.680::0.722))
|
||||
(HOLD TXCHARDISPMODE (posedge TXUSRCLK2) (0.170::0.181))
|
||||
(SETUP TXCHARDISPMODE (posedge TXUSRCLK2) (0.680::0.722))
|
||||
(HOLD TXCHARDISPVAL (posedge TXUSRCLK2) (0.167::0.177))
|
||||
(SETUP TXCHARDISPVAL (posedge TXUSRCLK2) (0.680::0.722))
|
||||
(HOLD TXCHARISK (posedge TXUSRCLK2) (0.160::0.170))
|
||||
(SETUP TXCHARISK (posedge TXUSRCLK2) (0.680::0.722))
|
||||
(HOLD TXCOMINIT (posedge TXUSRCLK2) (0.172::0.183))
|
||||
(SETUP TXCOMINIT (posedge TXUSRCLK2) (0.680::0.722))
|
||||
(HOLD TXCOMSAS (posedge TXUSRCLK2) (0.136::0.144))
|
||||
(SETUP TXCOMSAS (posedge TXUSRCLK2) (0.680::0.722))
|
||||
(HOLD TXUSRCLK2 (posedge TXUSRCLK2) (0.160::0.170))
|
||||
(SETUP TXUSRCLK2 (posedge TXUSRCLK2) (0.680::0.722))
|
||||
(HOLD TXUSRCLK2 (posedge TXUSRCLK2) (0.169::0.179))
|
||||
(SETUP TXUSRCLK2 (posedge TXUSRCLK2) (0.680::0.722))
|
||||
(HOLD TXCOMWAKE (posedge TXUSRCLK2) (0.160::0.170))
|
||||
(SETUP TXCOMWAKE (posedge TXUSRCLK2) (0.680::0.722))
|
||||
(HOLD TXDATA (posedge TXUSRCLK2) (0.173::0.184))
|
||||
(SETUP TXDATA (posedge TXUSRCLK2) (0.680::0.722))
|
||||
(HOLD TXDETECTRX (posedge TXUSRCLK2) (0.169::0.179))
|
||||
(SETUP TXDETECTRX (posedge TXUSRCLK2) (0.680::0.722))
|
||||
(HOLD TXDLYHOLD (posedge TXPHDLYTSTCLK) (0.387::0.617))
|
||||
(SETUP TXDLYHOLD (posedge TXPHDLYTSTCLK) (0.581::0.925))
|
||||
(HOLD TXPHDLYTSTCLK (posedge TXPHDLYTSTCLK) (0.387::0.617))
|
||||
(SETUP TXPHDLYTSTCLK (posedge TXPHDLYTSTCLK) (0.581::0.925))
|
||||
(HOLD TXDLYUPDOWN (posedge TXPHDLYTSTCLK) (0.387::0.617))
|
||||
(SETUP TXDLYUPDOWN (posedge TXPHDLYTSTCLK) (0.581::0.925))
|
||||
(HOLD TXELECIDLE (posedge TXUSRCLK2) (0.072::0.076))
|
||||
(SETUP TXELECIDLE (posedge TXUSRCLK2) (0.680::0.722))
|
||||
(HOLD TXHEADER (posedge TXUSRCLK2) (0.167::0.177))
|
||||
(SETUP TXHEADER (posedge TXUSRCLK2) (0.680::0.722))
|
||||
(HOLD TXINHIBIT (posedge TXUSRCLK2) (0.153::0.162))
|
||||
(SETUP TXINHIBIT (posedge TXUSRCLK2) (0.680::0.722))
|
||||
(HOLD TXUSRCLK2 (posedge TXUSRCLK2) (0.143::0.152))
|
||||
(SETUP TXUSRCLK2 (posedge TXUSRCLK2) (0.680::0.722))
|
||||
(HOLD TXUSRCLK2 (posedge TXUSRCLK2) (0.160::0.170))
|
||||
(SETUP TXUSRCLK2 (posedge TXUSRCLK2) (0.680::0.722))
|
||||
(HOLD TXUSRCLK2 (posedge TXUSRCLK2) (0.148::0.157))
|
||||
(SETUP TXUSRCLK2 (posedge TXUSRCLK2) (0.680::0.722))
|
||||
(HOLD TXPD (posedge TXUSRCLK2) (0.209::0.246))
|
||||
(SETUP TXPD (posedge TXUSRCLK2) (0.680::0.722))
|
||||
(HOLD TXPOLARITY (posedge TXUSRCLK2) (0.143::0.152))
|
||||
(SETUP TXPOLARITY (posedge TXUSRCLK2) (0.680::0.722))
|
||||
(HOLD TXPRBSFORCEERR (posedge TXUSRCLK2) (0.160::0.170))
|
||||
(SETUP TXPRBSFORCEERR (posedge TXUSRCLK2) (0.680::0.722))
|
||||
(HOLD TXPRBSSEL (posedge TXUSRCLK2) (0.160::0.170))
|
||||
(SETUP TXPRBSSEL (posedge TXUSRCLK2) (0.680::0.722))
|
||||
(HOLD TXRATE (posedge TXUSRCLK2) (0.153::0.162))
|
||||
(SETUP TXRATE (posedge TXUSRCLK2) (0.680::0.722))
|
||||
(HOLD TXSEQUENCE (posedge TXUSRCLK2) (0.172::0.183))
|
||||
(SETUP TXSEQUENCE (posedge TXUSRCLK2) (0.680::0.722))
|
||||
(HOLD TXSTARTSEQ (posedge TXUSRCLK2) (0.148::0.157))
|
||||
(SETUP TXSTARTSEQ (posedge TXUSRCLK2) (0.680::0.722))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_DRPADDR")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD DRPCLK (posedge DRPCLK) (0.172::0.183))
|
||||
(SETUP DRPCLK (posedge DRPCLK) (0.380::0.403))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_DRPDI")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD DRPCLK (posedge DRPCLK) (0.154::0.164))
|
||||
(SETUP DRPCLK (posedge DRPCLK) (0.380::0.403))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXCHBONDI_GEN_RXUSRCLK_FALSE_RX_DATA_WIDTH_16")
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXCHBONDI_GEN_FALSE_RX_DATA_WIDTH_16")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD RXUSRCLK (posedge RXUSRCLK) (0.159::0.183))
|
||||
|
|
@ -121,7 +117,7 @@
|
|||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXCHBONDI_GEN_RXUSRCLK_FALSE_RX_DATA_WIDTH_20")
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXCHBONDI_GEN_FALSE_RX_DATA_WIDTH_20")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD RXUSRCLK (posedge RXUSRCLK) (0.159::0.183))
|
||||
|
|
@ -129,7 +125,7 @@
|
|||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXCHBONDI_GEN_RXUSRCLK_FALSE_RX_DATA_WIDTH_32")
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXCHBONDI_GEN_FALSE_RX_DATA_WIDTH_32")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD RXUSRCLK (posedge RXUSRCLK) (0.159::0.183))
|
||||
|
|
@ -137,7 +133,7 @@
|
|||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXCHBONDI_GEN_RXUSRCLK_FALSE_RX_DATA_WIDTH_40")
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXCHBONDI_GEN_FALSE_RX_DATA_WIDTH_40")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD RXUSRCLK (posedge RXUSRCLK) (0.159::0.183))
|
||||
|
|
@ -145,7 +141,23 @@
|
|||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXCHBONDI_GEN_RXUSRCLK_TRUE_RX_DATA_WIDTH_32")
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXCHBONDI_GEN_TRUE_16")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD RX_DATA_WIDTH (posedge RXUSRCLK2) (0.159::0.183))
|
||||
(SETUP RX_DATA_WIDTH (posedge RXUSRCLK2) (0.328::0.378))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXCHBONDI_GEN_TRUE_20")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD RX_DATA_WIDTH (posedge RXUSRCLK2) (0.159::0.183))
|
||||
(SETUP RX_DATA_WIDTH (posedge RXUSRCLK2) (0.328::0.378))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXCHBONDI_GEN_TRUE_RX_DATA_WIDTH_32")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD RXUSRCLK (posedge RXUSRCLK) (0.159::0.183))
|
||||
|
|
@ -153,117 +165,13 @@
|
|||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXCHBONDI_GEN_RXUSRCLK_TRUE_RX_DATA_WIDTH_40")
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXCHBONDI_GEN_TRUE_RX_DATA_WIDTH_40")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD RXUSRCLK (posedge RXUSRCLK) (0.159::0.183))
|
||||
(SETUP RXUSRCLK (posedge RXUSRCLK) (0.328::0.378))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXCHBONDI_GEN_TRUE_RX_DATA_WIDTH_16")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD RXUSRCLK2 (posedge RXUSRCLK2) (0.159::0.183))
|
||||
(SETUP RXUSRCLK2 (posedge RXUSRCLK2) (0.328::0.378))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXCHBONDI_GEN_TRUE_RX_DATA_WIDTH_20")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD RXUSRCLK2 (posedge RXUSRCLK2) (0.159::0.183))
|
||||
(SETUP RXUSRCLK2 (posedge RXUSRCLK2) (0.328::0.378))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXCHBONDLEVEL")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD RXUSRCLK2 (posedge RXUSRCLK2) (0.113::0.120))
|
||||
(SETUP RXUSRCLK2 (posedge RXUSRCLK2) (0.680::0.722))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXPRBSSEL")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD RXUSRCLK2 (posedge RXUSRCLK2) (0.121::0.128))
|
||||
(SETUP RXUSRCLK2 (posedge RXUSRCLK2) (0.680::0.722))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXRATE")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD RXUSRCLK2 (posedge RXUSRCLK2) (0.119::0.126))
|
||||
(SETUP RXUSRCLK2 (posedge RXUSRCLK2) (0.680::0.722))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_SCANIN")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD SCANCLK (posedge SCANCLK) (0.723::0.832))
|
||||
(SETUP SCANCLK (posedge SCANCLK) (1.220::1.404))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_TX8B10BBYPASS")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD TXUSRCLK2 (posedge TXUSRCLK2) (0.161::0.171))
|
||||
(SETUP TXUSRCLK2 (posedge TXUSRCLK2) (0.680::0.722))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_TXCHARDISPMODE")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD TXUSRCLK2 (posedge TXUSRCLK2) (0.170::0.181))
|
||||
(SETUP TXUSRCLK2 (posedge TXUSRCLK2) (0.680::0.722))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_TXCHARDISPVAL")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD TXUSRCLK2 (posedge TXUSRCLK2) (0.167::0.177))
|
||||
(SETUP TXUSRCLK2 (posedge TXUSRCLK2) (0.680::0.722))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_TXCHARISK")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD TXUSRCLK2 (posedge TXUSRCLK2) (0.160::0.170))
|
||||
(SETUP TXUSRCLK2 (posedge TXUSRCLK2) (0.680::0.722))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_TXDATA")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD TXUSRCLK2 (posedge TXUSRCLK2) (0.173::0.184))
|
||||
(SETUP TXUSRCLK2 (posedge TXUSRCLK2) (0.680::0.722))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_TXHEADER")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD TXUSRCLK2 (posedge TXUSRCLK2) (0.167::0.177))
|
||||
(SETUP TXUSRCLK2 (posedge TXUSRCLK2) (0.680::0.722))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_TXPD")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD TXUSRCLK2 (posedge TXUSRCLK2) (0.209::0.246))
|
||||
(SETUP TXUSRCLK2 (posedge TXUSRCLK2) (0.680::0.722))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_TXPI_PPMCLK_SEL_TXUSRCLK")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
|
|
@ -281,43 +189,13 @@
|
|||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_TXPIPPMSTEPSIZE_TXPI_PPMCLK_SEL_TXUSRCLK")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD TXUSRCLK (posedge TXUSRCLK) (0.158::0.168))
|
||||
(SETUP TXUSRCLK (posedge TXUSRCLK) (0.466::0.495))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_TXPIPPMSTEPSIZE_TXPI_PPMCLK_SEL_TXUSRCLK2")
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_TXPIPPMSTEPSIZE_TXPI_PPMCLK_SEL")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD TXUSRCLK2 (posedge TXUSRCLK2) (0.158::0.168))
|
||||
(SETUP TXUSRCLK2 (posedge TXUSRCLK2) (0.466::0.495))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_TXPRBSSEL")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD TXUSRCLK2 (posedge TXUSRCLK2) (0.160::0.170))
|
||||
(SETUP TXUSRCLK2 (posedge TXUSRCLK2) (0.680::0.722))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_TXRATE")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD TXUSRCLK2 (posedge TXUSRCLK2) (0.153::0.162))
|
||||
(SETUP TXUSRCLK2 (posedge TXUSRCLK2) (0.680::0.722))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_TXSEQUENCE")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD TXUSRCLK2 (posedge TXUSRCLK2) (0.172::0.183))
|
||||
(SETUP TXUSRCLK2 (posedge TXUSRCLK2) (0.680::0.722))
|
||||
(HOLD TXUSRCLK (posedge TXUSRCLK) (0.158::0.168))
|
||||
(SETUP TXUSRCLK (posedge TXUSRCLK) (0.466::0.495))
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -1,14 +1,13 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_COMMON_GTPE2_COMMONGTPE2_COMMON")
|
||||
(INSTANCE GTPE2_COMMON)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH DRPCLK DRPRDY (0.530::0.563)(0.836::0.888))
|
||||
(IOPATH GTGREFCLK0 REFCLKOUTMONITOR0 (0.452::0.720)(1.657::2.640))
|
||||
(IOPATH GTGREFCLK0 REFCLKOUTMONITOR1 (0.452::0.720)(1.657::2.640))
|
||||
(IOPATH GTGREFCLK1 REFCLKOUTMONITOR0 (0.452::0.720)(1.657::2.640))
|
||||
|
|
@ -25,26 +24,14 @@
|
|||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD DRPCLK (posedge DRPCLK) (0.160::0.170))
|
||||
(SETUP DRPCLK (posedge DRPCLK) (0.380::0.403))
|
||||
(HOLD DRPCLK (posedge DRPCLK) (0.140::0.149))
|
||||
(SETUP DRPCLK (posedge DRPCLK) (0.380::0.403))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_COMMON_GTPE2_COMMONGTPE2_COMMON_DRPADDR")
|
||||
(INSTANCE GTPE2_COMMON)
|
||||
(TIMINGCHECK
|
||||
(HOLD DRPCLK (posedge DRPCLK) (0.172::0.183))
|
||||
(SETUP DRPCLK (posedge DRPCLK) (0.380::0.403))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_COMMON_GTPE2_COMMONGTPE2_COMMON_DRPDI")
|
||||
(INSTANCE GTPE2_COMMON)
|
||||
(TIMINGCHECK
|
||||
(HOLD DRPCLK (posedge DRPCLK) (0.154::0.164))
|
||||
(SETUP DRPCLK (posedge DRPCLK) (0.380::0.403))
|
||||
(HOLD DRPADDR (posedge DRPCLK) (0.172::0.183))
|
||||
(SETUP DRPADDR (posedge DRPCLK) (0.380::0.403))
|
||||
(HOLD DRPDI (posedge DRPCLK) (0.154::0.164))
|
||||
(SETUP DRPDI (posedge DRPCLK) (0.380::0.403))
|
||||
(HOLD DRPEN (posedge DRPCLK) (0.160::0.170))
|
||||
(SETUP DRPEN (posedge DRPCLK) (0.380::0.403))
|
||||
(HOLD DRPWE (posedge DRPCLK) (0.140::0.149))
|
||||
(SETUP DRPWE (posedge DRPCLK) (0.380::0.403))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
)
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
)
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
)
|
||||
|
|
@ -1,17 +1,8 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
(CELL
|
||||
(CELLTYPE "BUFMRCE")
|
||||
(INSTANCE BUFMRCE)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH I O (0.033::0.035)(0.097::0.103))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "BUFMRCE_CE_TYPE_SYNC_INIT_OUT_0")
|
||||
(INSTANCE BUFMRCE)
|
||||
|
|
|
|||
|
|
@ -1,17 +1,8 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
(CELL
|
||||
(CELLTYPE "BUFMRCE")
|
||||
(INSTANCE BUFMRCE)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH I O (0.033::0.035)(0.097::0.103))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "BUFMRCE_CE_TYPE_SYNC_INIT_OUT_0")
|
||||
(INSTANCE BUFMRCE)
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
)
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
)
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
)
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
)
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
)
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
)
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
)
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
)
|
||||
|
|
@ -1,7 +1,7 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
(CELL
|
||||
(CELLTYPE "BUFIO_DELAY_BYPASS_FALSE")
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
)
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
)
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
)
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
)
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
)
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
)
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
)
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
)
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
)
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
)
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
)
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
)
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
)
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
)
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
)
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
)
|
||||
|
|
@ -1,7 +1,7 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
(CELL
|
||||
(CELLTYPE "IOB33M_INBUF_ENIOB33_IOBM_INBUF_EN")
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
(CELL
|
||||
(CELLTYPE "IOB33_INBUF_ENIOB33_IOB_INBUF_EN")
|
||||
|
|
|
|||
|
|
@ -1,24 +1,8 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
(CELL
|
||||
(CELLTYPE "IDELAYE2_CNTVALUEIN_IDELAY_TYPE_VAR_LOAD")
|
||||
(INSTANCE IDELAYE2)
|
||||
(TIMINGCHECK
|
||||
(HOLD C (posedge C) (0.128::0.138))
|
||||
(SETUP C (posedge C) (0.094::0.102))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "IDELAYE2_CNTVALUEIN_IDELAY_TYPE_VAR_LOAD_PIPE")
|
||||
(INSTANCE IDELAYE2)
|
||||
(TIMINGCHECK
|
||||
(HOLD C (posedge C) (0.258::0.280))
|
||||
(SETUP C (posedge C) (-0.081::-0.075))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "IDELAYE2_DELAY_SRC_DATAIN")
|
||||
(INSTANCE IDELAYE2)
|
||||
|
|
@ -73,6 +57,22 @@
|
|||
(SETUP LD (posedge C) (0.089::0.097))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "IDELAYE2CNTVALUEIN_VAR_LOAD")
|
||||
(INSTANCE IDELAYE2)
|
||||
(TIMINGCHECK
|
||||
(HOLD IDELAY_TYPE (posedge C) (0.128::0.138))
|
||||
(SETUP IDELAY_TYPE (posedge C) (0.094::0.102))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "IDELAYE2CNTVALUEIN_VAR_LOAD_PIPE")
|
||||
(INSTANCE IDELAYE2)
|
||||
(TIMINGCHECK
|
||||
(HOLD IDELAY_TYPE (posedge C) (0.258::0.280))
|
||||
(SETUP IDELAY_TYPE (posedge C) (-0.081::-0.075))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "ILOGICE3_IFF")
|
||||
(INSTANCE ILOGICE3)
|
||||
|
|
@ -87,12 +87,12 @@
|
|||
(CELLTYPE "ILOGICE3_IFF_DDR")
|
||||
(INSTANCE ILOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD CKB (posedge CKB) (-0.076::-0.066))
|
||||
(SETUP CKB (posedge CKB) (0.430::0.726))
|
||||
(HOLD CE (posedge CKB) (-0.076::-0.066))
|
||||
(SETUP CE (posedge CKB) (0.430::0.726))
|
||||
(HOLD D (posedge CK) (0.022::0.026))
|
||||
(SETUP D (posedge CK) (0.091::0.105))
|
||||
(HOLD CKB (posedge CKB) (0.022::0.026))
|
||||
(SETUP CKB (posedge CKB) (0.091::0.105))
|
||||
(HOLD D (posedge CKB) (0.022::0.026))
|
||||
(SETUP D (posedge CKB) (0.091::0.105))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
|
|
@ -155,6 +155,13 @@
|
|||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "ILOGICE3_IFF_RECOV")
|
||||
(INSTANCE ILOGICE3)
|
||||
(TIMINGCHECK
|
||||
(SETUP SR (posedge CK) (0.518::0.596))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "ILOGICE3_IFF_SAMEEDGE")
|
||||
(INSTANCE ILOGICE3)
|
||||
|
|
@ -167,13 +174,6 @@
|
|||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "ILOGICE3_IFF_SETUP")
|
||||
(INSTANCE ILOGICE3)
|
||||
(TIMINGCHECK
|
||||
(RECOVERY SR (posedge CK) (0.518::0.596))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "SELMUX2_1")
|
||||
(INSTANCE ILOGICE3)
|
||||
|
|
@ -189,6 +189,8 @@
|
|||
(CELLTYPE "OLOGICE3_OUTFF")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD OCE (posedge CK) (-0.059::-0.051))
|
||||
(SETUP OCE (posedge CK) (0.380::0.504))
|
||||
(HOLD SR (posedge CK) (-0.142::-0.124))
|
||||
(RECOVERY SR (posedge CK) (0.261::0.300))
|
||||
(REMOVAL SR (posedge CK) (0.000::0.000))
|
||||
|
|
@ -211,6 +213,16 @@
|
|||
(TIMINGCHECK
|
||||
(HOLD D2 (posedge CK) (-0.164::-0.143))
|
||||
(SETUP D2 (posedge CK) (0.689::0.834))
|
||||
(HOLD OCE (posedge CK) (-0.124::-0.108))
|
||||
(SETUP OCE (posedge CK) (0.380::0.482))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_OUTFF_DDR_SAMEEDGE")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD OCE (posedge CK) (-0.124::-0.108))
|
||||
(SETUP OCE (posedge CK) (0.380::0.482))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
|
|
@ -242,30 +254,6 @@
|
|||
(SETUP D1 (posedge CK) (0.351::0.404))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_OUTFF_OCE")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD CK (posedge CK) (-0.059::-0.051))
|
||||
(SETUP CK (posedge CK) (0.380::0.504))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_OUTFF_OCE_DDR_NEG")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD CK (posedge CK) (-0.124::-0.108))
|
||||
(SETUP CK (posedge CK) (0.380::0.482))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_OUTFF_OCE_DDR_SAMEEDGE")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD CK (posedge CK) (-0.124::-0.108))
|
||||
(SETUP CK (posedge CK) (0.380::0.482))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_OUTFF_OPPEDGE")
|
||||
(INSTANCE OLOGICE3)
|
||||
|
|
@ -294,6 +282,8 @@
|
|||
(RECOVERY SR (posedge CK) (0.249::0.286))
|
||||
(REMOVAL SR (posedge CK) (0.000::0.000))
|
||||
(SETUP SR (posedge CK) (0.471::0.591))
|
||||
(HOLD TCE (posedge CK) (-0.068::-0.060))
|
||||
(SETUP TCE (posedge CK) (0.389::0.505))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
|
|
@ -312,6 +302,16 @@
|
|||
(TIMINGCHECK
|
||||
(HOLD D2 (posedge CK) (-0.302::-0.264))
|
||||
(SETUP D2 (posedge CK) (0.622::0.788))
|
||||
(HOLD TCE (posedge CK) (-0.068::-0.060))
|
||||
(SETUP TCE (posedge CK) (0.389::0.505))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_TFF_DDR_SAMEEDGE")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD TCE (posedge CK) (-0.068::-0.060))
|
||||
(SETUP TCE (posedge CK) (0.389::0.505))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
|
|
@ -363,28 +363,4 @@
|
|||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_TFF_TCE")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD CK (posedge CK) (-0.068::-0.060))
|
||||
(SETUP CK (posedge CK) (0.389::0.505))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_TFF_TCE_DDR_NEG")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD CK (posedge CK) (-0.068::-0.060))
|
||||
(SETUP CK (posedge CK) (0.389::0.505))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_TFF_TCE_DDR_SAMEEDGE")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD CK (posedge CK) (-0.068::-0.060))
|
||||
(SETUP CK (posedge CK) (0.389::0.505))
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -1,24 +1,8 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
(CELL
|
||||
(CELLTYPE "IDELAYE2_CNTVALUEIN_IDELAY_TYPE_VAR_LOAD")
|
||||
(INSTANCE IDELAYE2)
|
||||
(TIMINGCHECK
|
||||
(HOLD C (posedge C) (0.128::0.138))
|
||||
(SETUP C (posedge C) (0.094::0.102))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "IDELAYE2_CNTVALUEIN_IDELAY_TYPE_VAR_LOAD_PIPE")
|
||||
(INSTANCE IDELAYE2)
|
||||
(TIMINGCHECK
|
||||
(HOLD C (posedge C) (0.258::0.280))
|
||||
(SETUP C (posedge C) (-0.081::-0.075))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "IDELAYE2_DELAY_SRC_DATAIN")
|
||||
(INSTANCE IDELAYE2)
|
||||
|
|
@ -73,6 +57,22 @@
|
|||
(SETUP LD (posedge C) (0.089::0.097))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "IDELAYE2CNTVALUEIN_VAR_LOAD")
|
||||
(INSTANCE IDELAYE2)
|
||||
(TIMINGCHECK
|
||||
(HOLD IDELAY_TYPE (posedge C) (0.128::0.138))
|
||||
(SETUP IDELAY_TYPE (posedge C) (0.094::0.102))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "IDELAYE2CNTVALUEIN_VAR_LOAD_PIPE")
|
||||
(INSTANCE IDELAYE2)
|
||||
(TIMINGCHECK
|
||||
(HOLD IDELAY_TYPE (posedge C) (0.258::0.280))
|
||||
(SETUP IDELAY_TYPE (posedge C) (-0.081::-0.075))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "ILOGICE3_IFF")
|
||||
(INSTANCE ILOGICE3)
|
||||
|
|
@ -87,12 +87,12 @@
|
|||
(CELLTYPE "ILOGICE3_IFF_DDR")
|
||||
(INSTANCE ILOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD CKB (posedge CKB) (-0.076::-0.066))
|
||||
(SETUP CKB (posedge CKB) (0.430::0.726))
|
||||
(HOLD CE (posedge CKB) (-0.076::-0.066))
|
||||
(SETUP CE (posedge CKB) (0.430::0.726))
|
||||
(HOLD D (posedge CK) (0.022::0.026))
|
||||
(SETUP D (posedge CK) (0.091::0.105))
|
||||
(HOLD CKB (posedge CKB) (0.022::0.026))
|
||||
(SETUP CKB (posedge CKB) (0.091::0.105))
|
||||
(HOLD D (posedge CKB) (0.022::0.026))
|
||||
(SETUP D (posedge CKB) (0.091::0.105))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
|
|
@ -155,6 +155,13 @@
|
|||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "ILOGICE3_IFF_RECOV")
|
||||
(INSTANCE ILOGICE3)
|
||||
(TIMINGCHECK
|
||||
(SETUP SR (posedge CK) (0.518::0.596))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "ILOGICE3_IFF_SAMEEDGE")
|
||||
(INSTANCE ILOGICE3)
|
||||
|
|
@ -167,13 +174,6 @@
|
|||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "ILOGICE3_IFF_SETUP")
|
||||
(INSTANCE ILOGICE3)
|
||||
(TIMINGCHECK
|
||||
(RECOVERY SR (posedge CK) (0.518::0.596))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "SELMUX2_1")
|
||||
(INSTANCE ILOGICE3)
|
||||
|
|
@ -189,6 +189,8 @@
|
|||
(CELLTYPE "OLOGICE3_OUTFF")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD OCE (posedge CK) (-0.059::-0.051))
|
||||
(SETUP OCE (posedge CK) (0.380::0.504))
|
||||
(HOLD SR (posedge CK) (-0.142::-0.124))
|
||||
(RECOVERY SR (posedge CK) (0.261::0.300))
|
||||
(REMOVAL SR (posedge CK) (0.000::0.000))
|
||||
|
|
@ -211,6 +213,16 @@
|
|||
(TIMINGCHECK
|
||||
(HOLD D2 (posedge CK) (-0.164::-0.143))
|
||||
(SETUP D2 (posedge CK) (0.689::0.834))
|
||||
(HOLD OCE (posedge CK) (-0.124::-0.108))
|
||||
(SETUP OCE (posedge CK) (0.380::0.482))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_OUTFF_DDR_SAMEEDGE")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD OCE (posedge CK) (-0.124::-0.108))
|
||||
(SETUP OCE (posedge CK) (0.380::0.482))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
|
|
@ -242,30 +254,6 @@
|
|||
(SETUP D1 (posedge CK) (0.351::0.404))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_OUTFF_OCE")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD CK (posedge CK) (-0.059::-0.051))
|
||||
(SETUP CK (posedge CK) (0.380::0.504))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_OUTFF_OCE_DDR_NEG")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD CK (posedge CK) (-0.124::-0.108))
|
||||
(SETUP CK (posedge CK) (0.380::0.482))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_OUTFF_OCE_DDR_SAMEEDGE")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD CK (posedge CK) (-0.124::-0.108))
|
||||
(SETUP CK (posedge CK) (0.380::0.482))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_OUTFF_OPPEDGE")
|
||||
(INSTANCE OLOGICE3)
|
||||
|
|
@ -294,6 +282,8 @@
|
|||
(RECOVERY SR (posedge CK) (0.249::0.286))
|
||||
(REMOVAL SR (posedge CK) (0.000::0.000))
|
||||
(SETUP SR (posedge CK) (0.471::0.591))
|
||||
(HOLD TCE (posedge CK) (-0.068::-0.060))
|
||||
(SETUP TCE (posedge CK) (0.389::0.505))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
|
|
@ -312,6 +302,16 @@
|
|||
(TIMINGCHECK
|
||||
(HOLD D2 (posedge CK) (-0.302::-0.264))
|
||||
(SETUP D2 (posedge CK) (0.622::0.788))
|
||||
(HOLD TCE (posedge CK) (-0.068::-0.060))
|
||||
(SETUP TCE (posedge CK) (0.389::0.505))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_TFF_DDR_SAMEEDGE")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD TCE (posedge CK) (-0.068::-0.060))
|
||||
(SETUP TCE (posedge CK) (0.389::0.505))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
|
|
@ -363,28 +363,4 @@
|
|||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_TFF_TCE")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD CK (posedge CK) (-0.068::-0.060))
|
||||
(SETUP CK (posedge CK) (0.389::0.505))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_TFF_TCE_DDR_NEG")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD CK (posedge CK) (-0.068::-0.060))
|
||||
(SETUP CK (posedge CK) (0.389::0.505))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_TFF_TCE_DDR_SAMEEDGE")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD CK (posedge CK) (-0.068::-0.060))
|
||||
(SETUP CK (posedge CK) (0.389::0.505))
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -1,24 +1,8 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
(CELL
|
||||
(CELLTYPE "IDELAYE2_CNTVALUEIN_IDELAY_TYPE_VAR_LOAD")
|
||||
(INSTANCE IDELAYE2)
|
||||
(TIMINGCHECK
|
||||
(HOLD C (posedge C) (0.128::0.138))
|
||||
(SETUP C (posedge C) (0.094::0.102))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "IDELAYE2_CNTVALUEIN_IDELAY_TYPE_VAR_LOAD_PIPE")
|
||||
(INSTANCE IDELAYE2)
|
||||
(TIMINGCHECK
|
||||
(HOLD C (posedge C) (0.258::0.280))
|
||||
(SETUP C (posedge C) (-0.081::-0.075))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "IDELAYE2_DELAY_SRC_DATAIN")
|
||||
(INSTANCE IDELAYE2)
|
||||
|
|
@ -73,6 +57,22 @@
|
|||
(SETUP LD (posedge C) (0.089::0.097))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "IDELAYE2CNTVALUEIN_VAR_LOAD")
|
||||
(INSTANCE IDELAYE2)
|
||||
(TIMINGCHECK
|
||||
(HOLD IDELAY_TYPE (posedge C) (0.128::0.138))
|
||||
(SETUP IDELAY_TYPE (posedge C) (0.094::0.102))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "IDELAYE2CNTVALUEIN_VAR_LOAD_PIPE")
|
||||
(INSTANCE IDELAYE2)
|
||||
(TIMINGCHECK
|
||||
(HOLD IDELAY_TYPE (posedge C) (0.258::0.280))
|
||||
(SETUP IDELAY_TYPE (posedge C) (-0.081::-0.075))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "ILOGICE3_IFF")
|
||||
(INSTANCE ILOGICE3)
|
||||
|
|
@ -87,12 +87,12 @@
|
|||
(CELLTYPE "ILOGICE3_IFF_DDR")
|
||||
(INSTANCE ILOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD CKB (posedge CKB) (-0.076::-0.066))
|
||||
(SETUP CKB (posedge CKB) (0.430::0.726))
|
||||
(HOLD CE (posedge CKB) (-0.076::-0.066))
|
||||
(SETUP CE (posedge CKB) (0.430::0.726))
|
||||
(HOLD D (posedge CK) (0.022::0.026))
|
||||
(SETUP D (posedge CK) (0.091::0.105))
|
||||
(HOLD CKB (posedge CKB) (0.022::0.026))
|
||||
(SETUP CKB (posedge CKB) (0.091::0.105))
|
||||
(HOLD D (posedge CKB) (0.022::0.026))
|
||||
(SETUP D (posedge CKB) (0.091::0.105))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
|
|
@ -155,6 +155,13 @@
|
|||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "ILOGICE3_IFF_RECOV")
|
||||
(INSTANCE ILOGICE3)
|
||||
(TIMINGCHECK
|
||||
(SETUP SR (posedge CK) (0.518::0.596))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "ILOGICE3_IFF_SAMEEDGE")
|
||||
(INSTANCE ILOGICE3)
|
||||
|
|
@ -167,13 +174,6 @@
|
|||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "ILOGICE3_IFF_SETUP")
|
||||
(INSTANCE ILOGICE3)
|
||||
(TIMINGCHECK
|
||||
(RECOVERY SR (posedge CK) (0.518::0.596))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "SELMUX2_1")
|
||||
(INSTANCE ILOGICE3)
|
||||
|
|
@ -189,6 +189,8 @@
|
|||
(CELLTYPE "OLOGICE3_OUTFF")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD OCE (posedge CK) (-0.059::-0.051))
|
||||
(SETUP OCE (posedge CK) (0.380::0.504))
|
||||
(HOLD SR (posedge CK) (-0.142::-0.124))
|
||||
(RECOVERY SR (posedge CK) (0.261::0.300))
|
||||
(REMOVAL SR (posedge CK) (0.000::0.000))
|
||||
|
|
@ -211,6 +213,16 @@
|
|||
(TIMINGCHECK
|
||||
(HOLD D2 (posedge CK) (-0.164::-0.143))
|
||||
(SETUP D2 (posedge CK) (0.689::0.834))
|
||||
(HOLD OCE (posedge CK) (-0.124::-0.108))
|
||||
(SETUP OCE (posedge CK) (0.380::0.482))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_OUTFF_DDR_SAMEEDGE")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD OCE (posedge CK) (-0.124::-0.108))
|
||||
(SETUP OCE (posedge CK) (0.380::0.482))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
|
|
@ -242,30 +254,6 @@
|
|||
(SETUP D1 (posedge CK) (0.351::0.404))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_OUTFF_OCE")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD CK (posedge CK) (-0.059::-0.051))
|
||||
(SETUP CK (posedge CK) (0.380::0.504))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_OUTFF_OCE_DDR_NEG")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD CK (posedge CK) (-0.124::-0.108))
|
||||
(SETUP CK (posedge CK) (0.380::0.482))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_OUTFF_OCE_DDR_SAMEEDGE")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD CK (posedge CK) (-0.124::-0.108))
|
||||
(SETUP CK (posedge CK) (0.380::0.482))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_OUTFF_OPPEDGE")
|
||||
(INSTANCE OLOGICE3)
|
||||
|
|
@ -294,6 +282,8 @@
|
|||
(RECOVERY SR (posedge CK) (0.249::0.286))
|
||||
(REMOVAL SR (posedge CK) (0.000::0.000))
|
||||
(SETUP SR (posedge CK) (0.471::0.591))
|
||||
(HOLD TCE (posedge CK) (-0.068::-0.060))
|
||||
(SETUP TCE (posedge CK) (0.389::0.505))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
|
|
@ -312,6 +302,16 @@
|
|||
(TIMINGCHECK
|
||||
(HOLD D2 (posedge CK) (-0.302::-0.264))
|
||||
(SETUP D2 (posedge CK) (0.622::0.788))
|
||||
(HOLD TCE (posedge CK) (-0.068::-0.060))
|
||||
(SETUP TCE (posedge CK) (0.389::0.505))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_TFF_DDR_SAMEEDGE")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD TCE (posedge CK) (-0.068::-0.060))
|
||||
(SETUP TCE (posedge CK) (0.389::0.505))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
|
|
@ -363,28 +363,4 @@
|
|||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_TFF_TCE")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD CK (posedge CK) (-0.068::-0.060))
|
||||
(SETUP CK (posedge CK) (0.389::0.505))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_TFF_TCE_DDR_NEG")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD CK (posedge CK) (-0.068::-0.060))
|
||||
(SETUP CK (posedge CK) (0.389::0.505))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_TFF_TCE_DDR_SAMEEDGE")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD CK (posedge CK) (-0.068::-0.060))
|
||||
(SETUP CK (posedge CK) (0.389::0.505))
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -1,24 +1,8 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
(CELL
|
||||
(CELLTYPE "IDELAYE2_CNTVALUEIN_IDELAY_TYPE_VAR_LOAD")
|
||||
(INSTANCE IDELAYE2)
|
||||
(TIMINGCHECK
|
||||
(HOLD C (posedge C) (0.128::0.138))
|
||||
(SETUP C (posedge C) (0.094::0.102))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "IDELAYE2_CNTVALUEIN_IDELAY_TYPE_VAR_LOAD_PIPE")
|
||||
(INSTANCE IDELAYE2)
|
||||
(TIMINGCHECK
|
||||
(HOLD C (posedge C) (0.258::0.280))
|
||||
(SETUP C (posedge C) (-0.081::-0.075))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "IDELAYE2_DELAY_SRC_DATAIN")
|
||||
(INSTANCE IDELAYE2)
|
||||
|
|
@ -73,6 +57,22 @@
|
|||
(SETUP LD (posedge C) (0.089::0.097))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "IDELAYE2CNTVALUEIN_VAR_LOAD")
|
||||
(INSTANCE IDELAYE2)
|
||||
(TIMINGCHECK
|
||||
(HOLD IDELAY_TYPE (posedge C) (0.128::0.138))
|
||||
(SETUP IDELAY_TYPE (posedge C) (0.094::0.102))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "IDELAYE2CNTVALUEIN_VAR_LOAD_PIPE")
|
||||
(INSTANCE IDELAYE2)
|
||||
(TIMINGCHECK
|
||||
(HOLD IDELAY_TYPE (posedge C) (0.258::0.280))
|
||||
(SETUP IDELAY_TYPE (posedge C) (-0.081::-0.075))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "ILOGICE3_IFF")
|
||||
(INSTANCE ILOGICE3)
|
||||
|
|
@ -87,12 +87,12 @@
|
|||
(CELLTYPE "ILOGICE3_IFF_DDR")
|
||||
(INSTANCE ILOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD CKB (posedge CKB) (-0.076::-0.066))
|
||||
(SETUP CKB (posedge CKB) (0.430::0.726))
|
||||
(HOLD CE (posedge CKB) (-0.076::-0.066))
|
||||
(SETUP CE (posedge CKB) (0.430::0.726))
|
||||
(HOLD D (posedge CK) (0.022::0.026))
|
||||
(SETUP D (posedge CK) (0.091::0.105))
|
||||
(HOLD CKB (posedge CKB) (0.022::0.026))
|
||||
(SETUP CKB (posedge CKB) (0.091::0.105))
|
||||
(HOLD D (posedge CKB) (0.022::0.026))
|
||||
(SETUP D (posedge CKB) (0.091::0.105))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
|
|
@ -155,6 +155,13 @@
|
|||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "ILOGICE3_IFF_RECOV")
|
||||
(INSTANCE ILOGICE3)
|
||||
(TIMINGCHECK
|
||||
(SETUP SR (posedge CK) (0.518::0.596))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "ILOGICE3_IFF_SAMEEDGE")
|
||||
(INSTANCE ILOGICE3)
|
||||
|
|
@ -167,13 +174,6 @@
|
|||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "ILOGICE3_IFF_SETUP")
|
||||
(INSTANCE ILOGICE3)
|
||||
(TIMINGCHECK
|
||||
(RECOVERY SR (posedge CK) (0.518::0.596))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "SELMUX2_1")
|
||||
(INSTANCE ILOGICE3)
|
||||
|
|
@ -189,6 +189,8 @@
|
|||
(CELLTYPE "OLOGICE3_OUTFF")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD OCE (posedge CK) (-0.059::-0.051))
|
||||
(SETUP OCE (posedge CK) (0.380::0.504))
|
||||
(HOLD SR (posedge CK) (-0.142::-0.124))
|
||||
(RECOVERY SR (posedge CK) (0.261::0.300))
|
||||
(REMOVAL SR (posedge CK) (0.000::0.000))
|
||||
|
|
@ -211,6 +213,16 @@
|
|||
(TIMINGCHECK
|
||||
(HOLD D2 (posedge CK) (-0.164::-0.143))
|
||||
(SETUP D2 (posedge CK) (0.689::0.834))
|
||||
(HOLD OCE (posedge CK) (-0.124::-0.108))
|
||||
(SETUP OCE (posedge CK) (0.380::0.482))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_OUTFF_DDR_SAMEEDGE")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD OCE (posedge CK) (-0.124::-0.108))
|
||||
(SETUP OCE (posedge CK) (0.380::0.482))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
|
|
@ -242,30 +254,6 @@
|
|||
(SETUP D1 (posedge CK) (0.351::0.404))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_OUTFF_OCE")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD CK (posedge CK) (-0.059::-0.051))
|
||||
(SETUP CK (posedge CK) (0.380::0.504))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_OUTFF_OCE_DDR_NEG")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD CK (posedge CK) (-0.124::-0.108))
|
||||
(SETUP CK (posedge CK) (0.380::0.482))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_OUTFF_OCE_DDR_SAMEEDGE")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD CK (posedge CK) (-0.124::-0.108))
|
||||
(SETUP CK (posedge CK) (0.380::0.482))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_OUTFF_OPPEDGE")
|
||||
(INSTANCE OLOGICE3)
|
||||
|
|
@ -294,6 +282,8 @@
|
|||
(RECOVERY SR (posedge CK) (0.249::0.286))
|
||||
(REMOVAL SR (posedge CK) (0.000::0.000))
|
||||
(SETUP SR (posedge CK) (0.471::0.591))
|
||||
(HOLD TCE (posedge CK) (-0.068::-0.060))
|
||||
(SETUP TCE (posedge CK) (0.389::0.505))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
|
|
@ -312,6 +302,16 @@
|
|||
(TIMINGCHECK
|
||||
(HOLD D2 (posedge CK) (-0.302::-0.264))
|
||||
(SETUP D2 (posedge CK) (0.622::0.788))
|
||||
(HOLD TCE (posedge CK) (-0.068::-0.060))
|
||||
(SETUP TCE (posedge CK) (0.389::0.505))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_TFF_DDR_SAMEEDGE")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD TCE (posedge CK) (-0.068::-0.060))
|
||||
(SETUP TCE (posedge CK) (0.389::0.505))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
|
|
@ -363,28 +363,4 @@
|
|||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_TFF_TCE")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD CK (posedge CK) (-0.068::-0.060))
|
||||
(SETUP CK (posedge CK) (0.389::0.505))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_TFF_TCE_DDR_NEG")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD CK (posedge CK) (-0.068::-0.060))
|
||||
(SETUP CK (posedge CK) (0.389::0.505))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_TFF_TCE_DDR_SAMEEDGE")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD CK (posedge CK) (-0.068::-0.060))
|
||||
(SETUP CK (posedge CK) (0.389::0.505))
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
)
|
||||
|
|
@ -1,44 +1,20 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
(CELL
|
||||
(CELLTYPE "XADC")
|
||||
(INSTANCE XADC)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH DCLK BUSY (0.301::0.319)(1.218::1.294))
|
||||
(IOPATH DCLK DRDY (0.256::0.272)(1.132::1.204))
|
||||
(IOPATH DCLK EOC (0.379::0.403)(1.437::1.527))
|
||||
(IOPATH DCLK EOS (0.288::0.306)(1.231::1.309))
|
||||
(IOPATH DCLK JTAGBUSY (0.334::0.354)(1.331::1.415))
|
||||
(IOPATH DCLK JTAGLOCKED (0.276::0.294)(1.190::1.264))
|
||||
(IOPATH DCLK JTAGMODIFIED (0.273::0.289)(1.177::1.251))
|
||||
(IOPATH DCLK OT (0.301::0.319)(1.269::1.349))
|
||||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD DCLK (posedge DCLK) (-0.025::-0.013))
|
||||
(SETUP DCLK (posedge DCLK) (0.800::0.848))
|
||||
(HOLD DCLK (posedge DCLK) (-0.022::-0.005))
|
||||
(SETUP DCLK (posedge DCLK) (0.531::0.565))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "XADC_DADDR")
|
||||
(INSTANCE XADC)
|
||||
(TIMINGCHECK
|
||||
(HOLD DCLK (posedge DCLK) (-0.002::0.017))
|
||||
(SETUP DCLK (posedge DCLK) (0.659::0.699))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "XADC_DI")
|
||||
(INSTANCE XADC)
|
||||
(TIMINGCHECK
|
||||
(HOLD DCLK (posedge DCLK) (-0.009::0.010))
|
||||
(SETUP DCLK (posedge DCLK) (0.610::0.648))
|
||||
(HOLD DADDR (posedge DCLK) (-0.002::0.017))
|
||||
(SETUP DADDR (posedge DCLK) (0.659::0.699))
|
||||
(HOLD DEN (posedge DCLK) (-0.025::-0.013))
|
||||
(SETUP DEN (posedge DCLK) (0.800::0.848))
|
||||
(HOLD DI (posedge DCLK) (-0.009::0.010))
|
||||
(SETUP DI (posedge DCLK) (0.610::0.648))
|
||||
(HOLD DWE (posedge DCLK) (-0.022::-0.005))
|
||||
(SETUP DWE (posedge DCLK) (0.531::0.565))
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
)
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
)
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,6 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
)
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
)
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
)
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
)
|
||||
|
|
@ -1,7 +1,7 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
(CELL
|
||||
(CELLTYPE "IOB33M_INBUF_ENIOB33_IOBM_INBUF_EN")
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
(CELL
|
||||
(CELLTYPE "IOB33_INBUF_ENIOB33_IOB_INBUF_EN")
|
||||
|
|
|
|||
|
|
@ -1,24 +1,8 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
(CELL
|
||||
(CELLTYPE "IDELAYE2_CNTVALUEIN_IDELAY_TYPE_VAR_LOAD")
|
||||
(INSTANCE IDELAYE2)
|
||||
(TIMINGCHECK
|
||||
(HOLD C (posedge C) (0.128::0.138))
|
||||
(SETUP C (posedge C) (0.094::0.102))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "IDELAYE2_CNTVALUEIN_IDELAY_TYPE_VAR_LOAD_PIPE")
|
||||
(INSTANCE IDELAYE2)
|
||||
(TIMINGCHECK
|
||||
(HOLD C (posedge C) (0.258::0.280))
|
||||
(SETUP C (posedge C) (-0.081::-0.075))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "IDELAYE2_DELAY_SRC_DATAIN")
|
||||
(INSTANCE IDELAYE2)
|
||||
|
|
@ -73,6 +57,22 @@
|
|||
(SETUP LD (posedge C) (0.089::0.097))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "IDELAYE2CNTVALUEIN_VAR_LOAD")
|
||||
(INSTANCE IDELAYE2)
|
||||
(TIMINGCHECK
|
||||
(HOLD IDELAY_TYPE (posedge C) (0.128::0.138))
|
||||
(SETUP IDELAY_TYPE (posedge C) (0.094::0.102))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "IDELAYE2CNTVALUEIN_VAR_LOAD_PIPE")
|
||||
(INSTANCE IDELAYE2)
|
||||
(TIMINGCHECK
|
||||
(HOLD IDELAY_TYPE (posedge C) (0.258::0.280))
|
||||
(SETUP IDELAY_TYPE (posedge C) (-0.081::-0.075))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "ILOGICE3_IFF")
|
||||
(INSTANCE ILOGICE3)
|
||||
|
|
@ -87,12 +87,12 @@
|
|||
(CELLTYPE "ILOGICE3_IFF_DDR")
|
||||
(INSTANCE ILOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD CKB (posedge CKB) (-0.076::-0.066))
|
||||
(SETUP CKB (posedge CKB) (0.430::0.726))
|
||||
(HOLD CE (posedge CKB) (-0.076::-0.066))
|
||||
(SETUP CE (posedge CKB) (0.430::0.726))
|
||||
(HOLD D (posedge CK) (0.022::0.026))
|
||||
(SETUP D (posedge CK) (0.091::0.105))
|
||||
(HOLD CKB (posedge CKB) (0.022::0.026))
|
||||
(SETUP CKB (posedge CKB) (0.091::0.105))
|
||||
(HOLD D (posedge CKB) (0.022::0.026))
|
||||
(SETUP D (posedge CKB) (0.091::0.105))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
|
|
@ -155,6 +155,13 @@
|
|||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "ILOGICE3_IFF_RECOV")
|
||||
(INSTANCE ILOGICE3)
|
||||
(TIMINGCHECK
|
||||
(SETUP SR (posedge CK) (0.518::0.596))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "ILOGICE3_IFF_SAMEEDGE")
|
||||
(INSTANCE ILOGICE3)
|
||||
|
|
@ -167,13 +174,6 @@
|
|||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "ILOGICE3_IFF_SETUP")
|
||||
(INSTANCE ILOGICE3)
|
||||
(TIMINGCHECK
|
||||
(RECOVERY SR (posedge CK) (0.518::0.596))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "SELMUX2_1")
|
||||
(INSTANCE ILOGICE3)
|
||||
|
|
@ -189,6 +189,8 @@
|
|||
(CELLTYPE "OLOGICE3_OUTFF")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD OCE (posedge CK) (-0.059::-0.051))
|
||||
(SETUP OCE (posedge CK) (0.380::0.504))
|
||||
(HOLD SR (posedge CK) (-0.142::-0.124))
|
||||
(RECOVERY SR (posedge CK) (0.261::0.300))
|
||||
(REMOVAL SR (posedge CK) (0.000::0.000))
|
||||
|
|
@ -211,6 +213,16 @@
|
|||
(TIMINGCHECK
|
||||
(HOLD D2 (posedge CK) (-0.164::-0.143))
|
||||
(SETUP D2 (posedge CK) (0.689::0.834))
|
||||
(HOLD OCE (posedge CK) (-0.124::-0.108))
|
||||
(SETUP OCE (posedge CK) (0.380::0.482))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_OUTFF_DDR_SAMEEDGE")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD OCE (posedge CK) (-0.124::-0.108))
|
||||
(SETUP OCE (posedge CK) (0.380::0.482))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
|
|
@ -242,30 +254,6 @@
|
|||
(SETUP D1 (posedge CK) (0.351::0.404))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_OUTFF_OCE")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD CK (posedge CK) (-0.059::-0.051))
|
||||
(SETUP CK (posedge CK) (0.380::0.504))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_OUTFF_OCE_DDR_NEG")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD CK (posedge CK) (-0.124::-0.108))
|
||||
(SETUP CK (posedge CK) (0.380::0.482))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_OUTFF_OCE_DDR_SAMEEDGE")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD CK (posedge CK) (-0.124::-0.108))
|
||||
(SETUP CK (posedge CK) (0.380::0.482))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_OUTFF_OPPEDGE")
|
||||
(INSTANCE OLOGICE3)
|
||||
|
|
@ -294,6 +282,8 @@
|
|||
(RECOVERY SR (posedge CK) (0.249::0.286))
|
||||
(REMOVAL SR (posedge CK) (0.000::0.000))
|
||||
(SETUP SR (posedge CK) (0.471::0.591))
|
||||
(HOLD TCE (posedge CK) (-0.068::-0.060))
|
||||
(SETUP TCE (posedge CK) (0.389::0.505))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
|
|
@ -312,6 +302,16 @@
|
|||
(TIMINGCHECK
|
||||
(HOLD D2 (posedge CK) (-0.302::-0.264))
|
||||
(SETUP D2 (posedge CK) (0.622::0.788))
|
||||
(HOLD TCE (posedge CK) (-0.068::-0.060))
|
||||
(SETUP TCE (posedge CK) (0.389::0.505))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_TFF_DDR_SAMEEDGE")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD TCE (posedge CK) (-0.068::-0.060))
|
||||
(SETUP TCE (posedge CK) (0.389::0.505))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
|
|
@ -363,28 +363,4 @@
|
|||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_TFF_TCE")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD CK (posedge CK) (-0.068::-0.060))
|
||||
(SETUP CK (posedge CK) (0.389::0.505))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_TFF_TCE_DDR_NEG")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD CK (posedge CK) (-0.068::-0.060))
|
||||
(SETUP CK (posedge CK) (0.389::0.505))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_TFF_TCE_DDR_SAMEEDGE")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD CK (posedge CK) (-0.068::-0.060))
|
||||
(SETUP CK (posedge CK) (0.389::0.505))
|
||||
)
|
||||
)
|
||||
)
|
||||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue