Canonicalizing the JSON files.
See [Info File](Info.md) for details. Signed-off-by: Tim 'mithro' Ansell <me@mith.ro>
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Info.md
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Info.md
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@ -37,7 +37,7 @@ These files are released under the very permissive [CC0 1.0 Universal](COPYING).
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# Details
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Last updated on Mon Nov 12 02:59:35 UTC 2018 (2018-11-12T02:59:35+00:00).
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Last updated on Fri Dec 7 01:01:06 UTC 2018 (2018-12-07T01:01:06+00:00).
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Created using [Project X-Ray](https://github.com/SymbiFlow/prjxray) version [v0.0-984-gb43bf35](https://github.com/SymbiFlow/prjxray/commit/b43bf3539f51ed8a755ae245682cd660ca23d813).
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@ -92,15 +92,15 @@ Results have checksums;
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* [`6864d8edcef442cb129f83b9c5cd27be85d1b4bded8007bbeadcfc70717f8c48 ./artix7/gridinfo/grid-xc7a50tfgg484-1-db.txt`](./artix7/gridinfo/grid-xc7a50tfgg484-1-db.txt)
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* [`8416e8eef29e5defebbd3e45f60baa15cbcc22d66647a8da62ec7c42eff8b521 ./artix7/harness/arty-a7/pmod/design.bit`](./artix7/harness/arty-a7/pmod/design.bit)
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* [`c98eefb677a5cd469b75223d6ceb0e95f5d331de00291193caed008f33ee746c ./artix7/harness/arty-a7/pmod/design.dcp`](./artix7/harness/arty-a7/pmod/design.dcp)
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* [`64173d4eabd1ed0d33f8513d5247a384635c8352ea3b0c86bdb30b1229e8b713 ./artix7/harness/arty-a7/pmod/design.json`](./artix7/harness/arty-a7/pmod/design.json)
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* [`13382ee7fffcd88636892517929e7c60a6e82bb63324a4e48414bb16eb81174b ./artix7/harness/arty-a7/pmod/design.json`](./artix7/harness/arty-a7/pmod/design.json)
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* [`0c0db34e2b1a0f38b05799ad7e042874d43443d79426e9f32f0b63c71a8c9d3d ./artix7/harness/arty-a7/pmod/design.txt`](./artix7/harness/arty-a7/pmod/design.txt)
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* [`0df8a22d29a4425ee1da4363b8cdb56c82c1ab71913fbe36b4470b3ebc082c60 ./artix7/harness/arty-a7/swbut/design.bit`](./artix7/harness/arty-a7/swbut/design.bit)
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* [`578bbe948ecc1af59c3e9cda0aacd53841d31534a6ec156af9d2779aee8770f4 ./artix7/harness/arty-a7/swbut/design.dcp`](./artix7/harness/arty-a7/swbut/design.dcp)
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* [`44fbfe293c32ae7729c10ae7df08a7f85703feb2129949be30af6c5b1202c14d ./artix7/harness/arty-a7/swbut/design.json`](./artix7/harness/arty-a7/swbut/design.json)
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* [`124264a1ac88ce1e72eef3d337dc1b67287413036e1e0bf4e1eb52df3cef17ee ./artix7/harness/arty-a7/swbut/design.json`](./artix7/harness/arty-a7/swbut/design.json)
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* [`d8c1255df5bc352fbff05b9688b86becfc7d28ee82663256332e0a7b8ac4b338 ./artix7/harness/arty-a7/swbut/design.txt`](./artix7/harness/arty-a7/swbut/design.txt)
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* [`c805c150d4a58e392a1c41046261fec0b2c76fe1cce5812253902fc95715ba54 ./artix7/harness/basys3/swbut/design.bit`](./artix7/harness/basys3/swbut/design.bit)
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* [`29981e44415eaeff674c940dcd5b5be4fc5b04efa1c10f6a43eb054101e0c966 ./artix7/harness/basys3/swbut/design.dcp`](./artix7/harness/basys3/swbut/design.dcp)
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* [`e2d3754c0e87be5e1c511b9564843644d7bc787229267d7f43a432f93a99ffd5 ./artix7/harness/basys3/swbut/design.json`](./artix7/harness/basys3/swbut/design.json)
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* [`65cbe9fc850652b79386575b9d9f7bb157757b27d49a40fc5297cff3f22084df ./artix7/harness/basys3/swbut/design.json`](./artix7/harness/basys3/swbut/design.json)
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* [`cd4000b96378f736d31686b381ebd4349898b3b8bd09606223c7ca48cb1a5aba ./artix7/harness/basys3/swbut/design.txt`](./artix7/harness/basys3/swbut/design.txt)
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* [`4c0a815ab8943181331f7aa9ac77655a0a640d9a409a602e4f24f8feb5f905e9 ./artix7/harness/README.md`](./artix7/harness/README.md)
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* [`1c863520307fac805e9dec67ed91eabf663e7cf873b3da16e581cefa771ed9c4 ./artix7/mask_bram_l.db`](./artix7/mask_bram_l.db)
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@ -134,164 +134,164 @@ Results have checksums;
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* [`90d9243f3210a3ac7feb0d5c4434d62bd74ebf5edc75b95a9eae22540d462d3f ./artix7/segbits_int_l.db`](./artix7/segbits_int_l.db)
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* [`13bc58bf4a42029adf4f9b06ffd7c9436e2294bf4fdc16cdaa70505c28a2a7b7 ./artix7/segbits_int_r.db`](./artix7/segbits_int_r.db)
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* [`d77b40f729b66962f0197a5e31b43860326401b6116ac36e727411319adac0f2 ./artix7/settings.sh`](./artix7/settings.sh)
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* [`1964c2803e6b0f4d372b5a14e1ef9e4091808c2c7c00bd28133b0009fbed245d ./artix7/site_type_BSCAN.json`](./artix7/site_type_BSCAN.json)
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* [`4fa1d86ce4dbfc4613a7ebb55a3e13991cd3e75b2e2114a337c2f02a0e87e678 ./artix7/site_type_BUFGCTRL.json`](./artix7/site_type_BUFGCTRL.json)
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* [`8ba38d2e8bc24d17cc8e48864851b8aebac7ca474dad7f6a8dd1f1132d7baed3 ./artix7/site_type_BUFHCE.json`](./artix7/site_type_BUFHCE.json)
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* [`5740037dbc51ac28ac205289ea1a86b6b41cf9a537f80c0ad5034970183cfbf4 ./artix7/site_type_BUFIO.json`](./artix7/site_type_BUFIO.json)
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* [`cba48853673d59e4f8c4359ad897f806c91268454958d83d8568d0e4ec4cc4dd ./artix7/site_type_BUFMRCE.json`](./artix7/site_type_BUFMRCE.json)
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* [`131fe7fddda638714900780dc66a032b7f9f417a4b387273cb3da3f6294ca76d ./artix7/site_type_BUFR.json`](./artix7/site_type_BUFR.json)
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* [`4d7dfb734e9cd51094ebb026bea0104ac72fc1747fd196e68bedda363155ad1b ./artix7/site_type_CAPTURE.json`](./artix7/site_type_CAPTURE.json)
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* [`d6d095ed918127a2970d71c73cf668124fc000fcf37ad5eec803dbd9efbe9a17 ./artix7/site_type_DCIRESET.json`](./artix7/site_type_DCIRESET.json)
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* [`012311ea9db7d8d1a88c6a8ad13bec27d8d77295f854aa74846f14b28cefcc75 ./artix7/site_type_DNA_PORT.json`](./artix7/site_type_DNA_PORT.json)
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* [`5552d8b433594c63d8ff68025dc32b4ce01926526d693641857449e3c0695dd0 ./artix7/site_type_DSP48E1.json`](./artix7/site_type_DSP48E1.json)
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* [`d2075b59398f90a9222e687c7d78a7e298b857932927574af45cd3c0ac27d3c0 ./artix7/site_type_EFUSE_USR.json`](./artix7/site_type_EFUSE_USR.json)
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* [`677f42ebcf8a1c4ad29e66b332b8cf6385224b0b055763034e064bc817edc3e2 ./artix7/site_type_FIFO18E1.json`](./artix7/site_type_FIFO18E1.json)
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* [`2f5700b15d191e1792237013dbe68cdbf9cc70d7fbe5126fb614dbe136b6ff66 ./artix7/site_type_FRAME_ECC.json`](./artix7/site_type_FRAME_ECC.json)
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* [`870e61cb994da5a84914ddecb729bbc4f37e432c27c48b763326eb673ea207ea ./artix7/site_type_GTPE2_CHANNEL.json`](./artix7/site_type_GTPE2_CHANNEL.json)
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* [`2d2ba2a7d336fef2f08b04f5aea599676fe002ad6f68736f66be1e7c5d4ab7a2 ./artix7/site_type_GTPE2_COMMON.json`](./artix7/site_type_GTPE2_COMMON.json)
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* [`ccfb41b477859def7583e7a32b8e2e65dd6356a7c3771761b8561625a7cb5591 ./artix7/site_type_IBUFDS_GTE2.json`](./artix7/site_type_IBUFDS_GTE2.json)
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* [`8cec0f1eb9788e3875fa13a951f12391234eb7d489c07bd138c64fa6cd006814 ./artix7/site_type_ICAP.json`](./artix7/site_type_ICAP.json)
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* [`b9075f486aa2a14c65b7f2714f1f5d0c94c1721ebd4ff29abcf21b979daab978 ./artix7/site_type_IDELAYCTRL.json`](./artix7/site_type_IDELAYCTRL.json)
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* [`045824ab1f5f70f41a2889303322e37d98f68be4b0a778b34f687e7473eb9193 ./artix7/site_type_IDELAYE2.json`](./artix7/site_type_IDELAYE2.json)
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* [`3a19f338249dba79b78d286d8270c87c58687bb72414a778b5a7e687cbb07555 ./artix7/site_type_ILOGICE3.json`](./artix7/site_type_ILOGICE3.json)
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* [`c38bda752c26d6bc96b7d0c932d32a985d95a612994b257d06497b3b8544c1b4 ./artix7/site_type_IN_FIFO.json`](./artix7/site_type_IN_FIFO.json)
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* [`6494bc80cf0758385e3ffafc1586e15faf8e8586f4bfcaac856ec4925c2a3fa5 ./artix7/site_type_IOB33.json`](./artix7/site_type_IOB33.json)
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* [`fa3a3c52d649446e2b10cebbaf965f008dfdbe3b2ff6ea5652fb2e3ab5ec2119 ./artix7/site_type_IOB33M.json`](./artix7/site_type_IOB33M.json)
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* [`5a779859f0ac32fd0b1e67e592031e2a6817499c10d950fbceb67ec60981958e ./artix7/site_type_IOB33S.json`](./artix7/site_type_IOB33S.json)
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* [`57f36c456bb9936328761cba5d98ac11aef35480951e4bbd01ebff87f281da35 ./artix7/site_type_IPAD.json`](./artix7/site_type_IPAD.json)
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* [`6ca708c74131a6cc465ad7140101e1b53673dda44b9e9b05427e5ee043d812e0 ./artix7/site_type_MMCME2_ADV.json`](./artix7/site_type_MMCME2_ADV.json)
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* [`e2635cc5529a1718ebebaeadc83d75767d6837d9a21def7ff1865369834a3bae ./artix7/site_type_OLOGICE3.json`](./artix7/site_type_OLOGICE3.json)
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* [`9f63a604386b226e8b4a28dd5e30bbe7c31da95775c2a8099ffe4c42dd7cc4cd ./artix7/site_type_OPAD.json`](./artix7/site_type_OPAD.json)
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* [`483078ba9991cd9f8f69350fe3568f26898eab3a4685ef330558dc59b77ad32e ./artix7/site_type_OUT_FIFO.json`](./artix7/site_type_OUT_FIFO.json)
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* [`868ff8634196b4ff0821b60a92f22b9d706962b6a956dc0da95610cae414b16a ./artix7/site_type_PCIE_2_1.json`](./artix7/site_type_PCIE_2_1.json)
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* [`07a29aede8c9f0d1e7c3c50cae199a7fd395091b563cd2369550455dd66828fc ./artix7/site_type_PHASER_IN_PHY.json`](./artix7/site_type_PHASER_IN_PHY.json)
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* [`2c7d3e7499eb21294df24c71109b9e58163248de7b232b6fab1f528cbec0ddcf ./artix7/site_type_PHASER_OUT_PHY.json`](./artix7/site_type_PHASER_OUT_PHY.json)
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* [`ee33d28bc9369ef379c2729fb1c7a24a47970a2d076c7c041c8ecb5738924fd7 ./artix7/site_type_PHASER_REF.json`](./artix7/site_type_PHASER_REF.json)
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* [`d6b9ed9f4910dd7461c38dfeb87ca706eaf1253bd15ded1df8f820919ddb4ea1 ./artix7/site_type_PHY_CONTROL.json`](./artix7/site_type_PHY_CONTROL.json)
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* [`29472966a4f054633c77544609f47018a6753e7c5212006c83c0d7db80145489 ./artix7/site_type_PLLE2_ADV.json`](./artix7/site_type_PLLE2_ADV.json)
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* [`dde67b650f00ad996f86aae5828f5fdab981c28e28f8c2353fdfcceafbcab591 ./artix7/site_type_PMV2.json`](./artix7/site_type_PMV2.json)
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* [`c552b72eaaaca5aa774fbf7b9929290a7395eab514477ba38b5a180965e7831b ./artix7/site_type_RAMB18E1.json`](./artix7/site_type_RAMB18E1.json)
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* [`66051f9ee1ab46b59987a37a42cf3442da3cef15fa5533f006117caff47486d6 ./artix7/site_type_RAMBFIFO36E1.json`](./artix7/site_type_RAMBFIFO36E1.json)
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* [`2b5d948347739c21fdb4fad7dbb1b5a4637182e6852e548edf8ff6ba63322a9a ./artix7/site_type_SLICEL.json`](./artix7/site_type_SLICEL.json)
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* [`2c85b664ba4c6d5f0b39df0ac4507feefa2137e56c24adb03b8f455955dcc2db ./artix7/site_type_SLICEM.json`](./artix7/site_type_SLICEM.json)
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* [`8a3bf7142d6a657e5d434ff066ff35a9267c47416474867565fd1abc0845c5b2 ./artix7/site_type_STARTUP.json`](./artix7/site_type_STARTUP.json)
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* [`8e5baf846e629316cefb781c26c09b6a39ca509d03dd381967c3e92f429dbda3 ./artix7/site_type_TIEOFF.json`](./artix7/site_type_TIEOFF.json)
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* [`a8bbff4d452d9a984b6b86eadabb083ec48ada24359e00c9eb99b8e8b6cb8a20 ./artix7/site_type_USR_ACCESS.json`](./artix7/site_type_USR_ACCESS.json)
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* [`ad77b4609302b54b2f371cc0f50262a507a19521c6dd86391acf3c7e5f20d887 ./artix7/site_type_XADC.json`](./artix7/site_type_XADC.json)
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* [`cece037771908d5d6b065651f94ed799dd028504365044431ae5ea88ffd44234 ./artix7/tileconn.json`](./artix7/tileconn.json)
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* [`ce74444d4f416951cb1aaff3a6197624ae94ab961ef5960c718752d70f775500 ./artix7/tilegrid.json`](./artix7/tilegrid.json)
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* [`56db412abc3d12c12bee1cfe4c5aaac0ea9e3668be3a9e058e86673272a6cd69 ./artix7/tile_type_BRAM_INT_INTERFACE_L.json`](./artix7/tile_type_BRAM_INT_INTERFACE_L.json)
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* [`5fde8c4861cb1dd36ec4a39aa3b4dc10df5401e17bed982a09c6a7577b0ff01d ./artix7/tile_type_BRAM_INT_INTERFACE_R.json`](./artix7/tile_type_BRAM_INT_INTERFACE_R.json)
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* [`3374015c97e4a10e64a853d0fecdd44588859115f76423ede1588232591cb343 ./artix7/tile_type_BRAM_L.json`](./artix7/tile_type_BRAM_L.json)
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* [`0e48e69982688b07098a1fac5167024f02e6ed3afae55377b5ede8f6a16f146d ./artix7/tile_type_BRAM_R.json`](./artix7/tile_type_BRAM_R.json)
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* [`d90e2b9eebb7221e94297a13a987100bdbd070bad88a70f9d758a6d1a5036133 ./artix7/tile_type_BRKH_BRAM.json`](./artix7/tile_type_BRKH_BRAM.json)
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* [`1ca1d22fbf2ab0ce39ea4da8e2c8d6833418f5f4d7ec02e62dbdcad671c2479c ./artix7/tile_type_BRKH_B_TERM_INT.json`](./artix7/tile_type_BRKH_B_TERM_INT.json)
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* [`b23ca51a084ef98835710b9c1c0deae6b78deacbc8c6a8f1c02b0d61db93d02d ./artix7/tile_type_BRKH_CLB.json`](./artix7/tile_type_BRKH_CLB.json)
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* [`61823ee1e9156a284970ef49d1b4ebbeb4afd57aad594b4f5f37db5ee0659370 ./artix7/tile_type_BRKH_CLK.json`](./artix7/tile_type_BRKH_CLK.json)
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* [`9f636390fc90eccc4f98ad1ef1ff526b85d40bb052024b7d5f90ca09cb7e17f9 ./artix7/tile_type_BRKH_CMT.json`](./artix7/tile_type_BRKH_CMT.json)
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* [`0629a079029b418b01308d21bfc6309ffcf8476bf57328a8c5b3cc9623bb8406 ./artix7/tile_type_BRKH_DSP_L.json`](./artix7/tile_type_BRKH_DSP_L.json)
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* [`e7d63108a6369354166d3bbdf134b0ef5ca9e7f443e9a0fe514fa7ff602a0388 ./artix7/tile_type_BRKH_DSP_R.json`](./artix7/tile_type_BRKH_DSP_R.json)
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* [`e6013cdb3a761a93bcb7520182721200220052aa68d794c706200192aa4bb7ec ./artix7/tile_type_BRKH_GTX.json`](./artix7/tile_type_BRKH_GTX.json)
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* [`3d51f166ab08934045829433645f61766439fe712bfeb9cf272b164a994b75dc ./artix7/tile_type_BRKH_INT.json`](./artix7/tile_type_BRKH_INT.json)
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* [`f5a7617297ccd63e39841118f8ebc260410daa7cfe998a74969d3d44595fcaa4 ./artix7/tile_type_BRKH_TERM_INT.json`](./artix7/tile_type_BRKH_TERM_INT.json)
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* [`c991fd82f6e918d5f687fe1099dffa7b951fc3b7761eb782fcd3bcb4a8a4ff66 ./artix7/tile_type_B_TERM_INT.json`](./artix7/tile_type_B_TERM_INT.json)
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* [`6f7fc06f6c36cffbad9b57a2c315c2fc0f557d65d8bf47999e7f29ac7da7330b ./artix7/tile_type_CFG_CENTER_BOT.json`](./artix7/tile_type_CFG_CENTER_BOT.json)
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* [`d3a4e5424572b0ad0814a902f7f66323a7dfc32f3055d57e854bbf70fa330b8e ./artix7/tile_type_CFG_CENTER_MID.json`](./artix7/tile_type_CFG_CENTER_MID.json)
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* [`d3455134d42c1421ff6ef4c964b05388d2eb54b41b6d45373827d61aede50d44 ./artix7/tile_type_CFG_CENTER_TOP.json`](./artix7/tile_type_CFG_CENTER_TOP.json)
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* [`a203272826ea9f1eeb3e6056e9d2e3e0cb99fe713c2ad8be18d3f7f4c1b11ade ./artix7/tile_type_CLBLL_L.json`](./artix7/tile_type_CLBLL_L.json)
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* [`44eeaa2e4604c23dd197edb3ca87ef397b2b1ccfea09d3b81bda3aeb84bd0e29 ./artix7/tile_type_CLBLL_R.json`](./artix7/tile_type_CLBLL_R.json)
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* [`e0281b9beb15fb0f7f8f1adacf6f522b1ad3185fd4231eff3d6c9cbb09520af8 ./artix7/tile_type_CLBLM_L.json`](./artix7/tile_type_CLBLM_L.json)
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* [`4ff52e67caee84d274b09104c35839d72d3da64382844e241e47e522420efe32 ./artix7/tile_type_CLBLM_R.json`](./artix7/tile_type_CLBLM_R.json)
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* [`f96926eab4db048265f7705066f4dc10123216696493a20d04dc37421287fc24 ./artix7/tile_type_CLK_BUFG_BOT_R.json`](./artix7/tile_type_CLK_BUFG_BOT_R.json)
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* [`3619d7654fd3b2c3683e665b07ebfe3bf186c73243e4786a4f813c65e96a2953 ./artix7/tile_type_CLK_BUFG_REBUF.json`](./artix7/tile_type_CLK_BUFG_REBUF.json)
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* [`e55843644057f2bac2de32800d13a6678adfc7ace6f3f87bc7d9308a890ab4cf ./artix7/tile_type_CLK_BUFG_TOP_R.json`](./artix7/tile_type_CLK_BUFG_TOP_R.json)
|
||||
* [`330e832ab39944e545dc4368d740d7008eb206ae174a314d428b2a69759c734a ./artix7/tile_type_CLK_FEED.json`](./artix7/tile_type_CLK_FEED.json)
|
||||
* [`a4e3af127e5b84f02331bf0902f9c8b476e07eb66d0f654737cc2c7a31eb7124 ./artix7/tile_type_CLK_HROW_BOT_R.json`](./artix7/tile_type_CLK_HROW_BOT_R.json)
|
||||
* [`df19db73d751056f630aad7200696d075ca374da013ec2e65c21cc5b22aaf3a8 ./artix7/tile_type_CLK_HROW_TOP_R.json`](./artix7/tile_type_CLK_HROW_TOP_R.json)
|
||||
* [`e301aed166fe1b17371b11f8c09be6b4ca67a29215ab4765a2b2b73a090f3faa ./artix7/tile_type_CLK_MTBF2.json`](./artix7/tile_type_CLK_MTBF2.json)
|
||||
* [`0267636db7d2bc3bc61aaf4d72ca49057ad61d3a66d847bd8485bc1e19856dc3 ./artix7/tile_type_CLK_PMV2.json`](./artix7/tile_type_CLK_PMV2.json)
|
||||
* [`dde992fee973fc9234219c412cc885cd56b00a4ec9da11495fd0b336bd354081 ./artix7/tile_type_CLK_PMV2_SVT.json`](./artix7/tile_type_CLK_PMV2_SVT.json)
|
||||
* [`930097848128274de976b51a22e25b82b6d9cd6201e234ffd125cc5c00978a23 ./artix7/tile_type_CLK_PMVIOB.json`](./artix7/tile_type_CLK_PMVIOB.json)
|
||||
* [`0747fc22ad9c6a769108d363b083c866bbe41089845c4b2f0de78fb9fc6970ff ./artix7/tile_type_CLK_PMV.json`](./artix7/tile_type_CLK_PMV.json)
|
||||
* [`cb231767fed449d9a3fca540404c46b81afdcd1ebfdf078966ba164e51c249bd ./artix7/tile_type_CLK_TERM.json`](./artix7/tile_type_CLK_TERM.json)
|
||||
* [`366f32ea0b98ac3fac3b4562669757c044ddc9c6128af3c01106959b0a4c19b0 ./artix7/tile_type_CMT_FIFO_L.json`](./artix7/tile_type_CMT_FIFO_L.json)
|
||||
* [`76e2d0f5ab4525eb473ec74fe375ed677b9f24a74c9d9b1e45cf9219a2b75820 ./artix7/tile_type_CMT_FIFO_R.json`](./artix7/tile_type_CMT_FIFO_R.json)
|
||||
* [`925d42b6185298b570a4746ac1f2ef996c0524b7500075275ef42650580dcb77 ./artix7/tile_type_CMT_PMV.json`](./artix7/tile_type_CMT_PMV.json)
|
||||
* [`7bcf64a7ea3a66da50aae5e789a31389358ab44c8ddf2e128ca66c2520d75438 ./artix7/tile_type_CMT_PMV_L.json`](./artix7/tile_type_CMT_PMV_L.json)
|
||||
* [`17c0cc33e5650d528c4fcb70efcc5354976e3b911b2f2e647c9b835b06ad2d34 ./artix7/tile_type_CMT_TOP_L_LOWER_B.json`](./artix7/tile_type_CMT_TOP_L_LOWER_B.json)
|
||||
* [`5f8bbb7ab0e5059b5dfca1a8b9ec54577c2d74d3c4b62a287424587e3b2f54e7 ./artix7/tile_type_CMT_TOP_L_LOWER_T.json`](./artix7/tile_type_CMT_TOP_L_LOWER_T.json)
|
||||
* [`5c0cc2c6aa116b31c21617da63cdd08fa7cad9fb5d32c199d7fe87b37430674d ./artix7/tile_type_CMT_TOP_L_UPPER_B.json`](./artix7/tile_type_CMT_TOP_L_UPPER_B.json)
|
||||
* [`66ef32256a5ed5eabf808e45f41300c829e5906a37b6820c41efc61dcef6f823 ./artix7/tile_type_CMT_TOP_L_UPPER_T.json`](./artix7/tile_type_CMT_TOP_L_UPPER_T.json)
|
||||
* [`006c0f3ae43a0601f78e12599ecf1f057df5e48b253432b1d56f1457d204ceae ./artix7/tile_type_CMT_TOP_R_LOWER_B.json`](./artix7/tile_type_CMT_TOP_R_LOWER_B.json)
|
||||
* [`94cbbc28123830f1c3402e03974f1a941a18c06259aa0c666ce9341777c78f4e ./artix7/tile_type_CMT_TOP_R_LOWER_T.json`](./artix7/tile_type_CMT_TOP_R_LOWER_T.json)
|
||||
* [`fcba6389824828c4ba0e51b1794a0350ed01043c57536d332d00ee2167e0ea95 ./artix7/tile_type_CMT_TOP_R_UPPER_B.json`](./artix7/tile_type_CMT_TOP_R_UPPER_B.json)
|
||||
* [`7d59357d3b6e1ffef42781449f4a273c906d13ccdc37c6260ab6df86a2c01b6e ./artix7/tile_type_CMT_TOP_R_UPPER_T.json`](./artix7/tile_type_CMT_TOP_R_UPPER_T.json)
|
||||
* [`48e9fb2ac16461732deca6c7f8fa4e7700ca6c1387b778edcd1a2e7a70ddea7a ./artix7/tile_type_DSP_L.json`](./artix7/tile_type_DSP_L.json)
|
||||
* [`093148b3a94a6c10913d3ffd62e68fc1e1a86d157c55f6142298ddebcefaf1fc ./artix7/tile_type_DSP_R.json`](./artix7/tile_type_DSP_R.json)
|
||||
* [`56c016d56fd36bbc8bb2f849b9002c798c705c5f34c999d3480b483571a7bf7a ./artix7/tile_type_GTP_CHANNEL_0.json`](./artix7/tile_type_GTP_CHANNEL_0.json)
|
||||
* [`6ec66aeb66441ad3f6428ae244751f145e9993528a018d601d4527c5ee3e3f96 ./artix7/tile_type_GTP_CHANNEL_1.json`](./artix7/tile_type_GTP_CHANNEL_1.json)
|
||||
* [`ed3c6a6af10c0d48982a047f3f7ac74fe3fbc174ace3af880a589fba45dd42ed ./artix7/tile_type_GTP_CHANNEL_2.json`](./artix7/tile_type_GTP_CHANNEL_2.json)
|
||||
* [`7a7ed978605314dcacaabaeaf9d31bc91a537e17484a294b0ae59a2ac7c1e734 ./artix7/tile_type_GTP_CHANNEL_3.json`](./artix7/tile_type_GTP_CHANNEL_3.json)
|
||||
* [`8eb3b5942619031579a02a02e285a0455be63c5730b366cbc8988cc2b9cb3a47 ./artix7/tile_type_GTP_COMMON.json`](./artix7/tile_type_GTP_COMMON.json)
|
||||
* [`706d3462d4fe1c9c4421df976136e934d54d71f2c4ee53f87b699c4c0924d4db ./artix7/tile_type_GTP_INT_INTERFACE.json`](./artix7/tile_type_GTP_INT_INTERFACE.json)
|
||||
* [`6e04d570c84732729e7020c86d69154abad88e9fea01c204d29c0ad34af56d9e ./artix7/tile_type_HCLK_BRAM.json`](./artix7/tile_type_HCLK_BRAM.json)
|
||||
* [`db4869b63b9c903c55aaa7dbce47052c1c39042c7184c3f88b85cef5677a4e68 ./artix7/tile_type_HCLK_CLB.json`](./artix7/tile_type_HCLK_CLB.json)
|
||||
* [`5605e47e54ced33c70c9a4a5d6ad7ea6bd2a4621bcc29a2bc98f84cbb5318729 ./artix7/tile_type_HCLK_CMT.json`](./artix7/tile_type_HCLK_CMT.json)
|
||||
* [`ea5aef6b3a0f6237bdce2d22c01961f1868f2a4ec17bc57967c59ebd8c98e781 ./artix7/tile_type_HCLK_CMT_L.json`](./artix7/tile_type_HCLK_CMT_L.json)
|
||||
* [`cad72613fa22fd079d8359b70e361dfee47a39fecddd21bd4ca6261440e6c7f2 ./artix7/tile_type_HCLK_DSP_L.json`](./artix7/tile_type_HCLK_DSP_L.json)
|
||||
* [`c94881752dbd2d1cee70510d5a9776e45eb1b9bc98299bae7556dd94d84ac9ee ./artix7/tile_type_HCLK_DSP_R.json`](./artix7/tile_type_HCLK_DSP_R.json)
|
||||
* [`e97bf2f0562ec9f3c9bd28d31bad32a131fbb13440096c9a1106a42d7c30a8a2 ./artix7/tile_type_HCLK_FEEDTHRU_1.json`](./artix7/tile_type_HCLK_FEEDTHRU_1.json)
|
||||
* [`1224c1e07a74106abfe790911cad14631d2d7b9e071551ae87ce22e94586a254 ./artix7/tile_type_HCLK_FEEDTHRU_2.json`](./artix7/tile_type_HCLK_FEEDTHRU_2.json)
|
||||
* [`9153c00fb532285a3f5908aac04444f66f556be6510b14ead6a4e00090235723 ./artix7/tile_type_HCLK_FIFO_L.json`](./artix7/tile_type_HCLK_FIFO_L.json)
|
||||
* [`0b238152eba5a5bce46a5cf14fe175d87d7394fcb1772d8cb1690b0ebadc66e4 ./artix7/tile_type_HCLK_GTX.json`](./artix7/tile_type_HCLK_GTX.json)
|
||||
* [`addd808e24003e2f2b51003726d6395d07eed6e77bfcc3c1a3cfa02df67f608d ./artix7/tile_type_HCLK_INT_INTERFACE.json`](./artix7/tile_type_HCLK_INT_INTERFACE.json)
|
||||
* [`e62be537ade1cf2be5768604f1567f7be8296c7eeb6dbce01def983d471958df ./artix7/tile_type_HCLK_IOB.json`](./artix7/tile_type_HCLK_IOB.json)
|
||||
* [`6d725f338f9ead2b40d8e4377fec02d57daee72677f6ce7c8761128ce4f37742 ./artix7/tile_type_HCLK_IOI3.json`](./artix7/tile_type_HCLK_IOI3.json)
|
||||
* [`6efc0af3e02fcbd170b76ea081d748a6eba14c4fb4e766a42f4dee47b94d03c5 ./artix7/tile_type_HCLK_L_BOT_UTURN.json`](./artix7/tile_type_HCLK_L_BOT_UTURN.json)
|
||||
* [`aa4205dbd7787658bb57f66dd471c3b4bdcb0420123db01d9da7fe8c2b4782b0 ./artix7/tile_type_HCLK_L.json`](./artix7/tile_type_HCLK_L.json)
|
||||
* [`94fba32801db0f18d065791ff922b0a4dc11ee6c37a6485b1dbfeafc881ae026 ./artix7/tile_type_HCLK_R_BOT_UTURN.json`](./artix7/tile_type_HCLK_R_BOT_UTURN.json)
|
||||
* [`427b35722adcb30006e8ece93b5c4e463feefd74a130b0ca03db59bce8cc45fe ./artix7/tile_type_HCLK_R.json`](./artix7/tile_type_HCLK_R.json)
|
||||
* [`9ec44fc735677e9a8f5fa71f0bfe6e05bab6975f4d32d1fc6999b5fb34fe263e ./artix7/tile_type_HCLK_TERM_GTX.json`](./artix7/tile_type_HCLK_TERM_GTX.json)
|
||||
* [`d4af410c0b97ec9222abfddba4a91b1f23942431eb13cf37dcd8ed4a0c00f50a ./artix7/tile_type_HCLK_TERM.json`](./artix7/tile_type_HCLK_TERM.json)
|
||||
* [`a47ab1f6d74cc4b94e338db09d6a3267b6d650b473d5e021f4e73aa7375d89dc ./artix7/tile_type_HCLK_VBRK.json`](./artix7/tile_type_HCLK_VBRK.json)
|
||||
* [`7c110a1f341e637d750a585efadeabd92789fb15f9ec32d3efc187b884d357da ./artix7/tile_type_HCLK_VFRAME.json`](./artix7/tile_type_HCLK_VFRAME.json)
|
||||
* [`aa13f4ec5d440ccf5560a552c9cb1b69021dd6b4a096a72f09c769b79033ad7d ./artix7/tile_type_INT_FEEDTHRU_1.json`](./artix7/tile_type_INT_FEEDTHRU_1.json)
|
||||
* [`a00f2d8da58bafb44fa201f24861ba12205fe494d1d75301c8d21118f0ceaa92 ./artix7/tile_type_INT_FEEDTHRU_2.json`](./artix7/tile_type_INT_FEEDTHRU_2.json)
|
||||
* [`870df57fc52c7fd9b124a91870f9f27ba06368b1da9aab8ce7de6e67778f8c80 ./artix7/tile_type_INT_INTERFACE_L.json`](./artix7/tile_type_INT_INTERFACE_L.json)
|
||||
* [`2624e9b62c62d561bf82898fa9cac9dc627f54d51d09e93f034f21484ac5ea69 ./artix7/tile_type_INT_INTERFACE_R.json`](./artix7/tile_type_INT_INTERFACE_R.json)
|
||||
* [`64a43c04cf6d619fb84df28ca6fd4b943422f588bc11e5035a8f8214bd9fd109 ./artix7/tile_type_INT_L.json`](./artix7/tile_type_INT_L.json)
|
||||
* [`16e33e1cec76e45e2b143b706bc84e69954f7440245d23859659e7cdc62e628c ./artix7/tile_type_INT_R.json`](./artix7/tile_type_INT_R.json)
|
||||
* [`d9b299aea8d485728aae7c9eb157308b12f923baa0c73709801dcecbd30fe5df ./artix7/tile_type_IO_INT_INTERFACE_L.json`](./artix7/tile_type_IO_INT_INTERFACE_L.json)
|
||||
* [`08363c3524ca1c9efd46b575beac2450990a560a876128c1b1e029a86f8f6aed ./artix7/tile_type_IO_INT_INTERFACE_R.json`](./artix7/tile_type_IO_INT_INTERFACE_R.json)
|
||||
* [`9afc4fdd483ee7f6ed781220dd5e65d46fff7d0c408010b7e7ac24b39c6fa112 ./artix7/tile_type_LIOB33.json`](./artix7/tile_type_LIOB33.json)
|
||||
* [`47f49959e2cd589f023dc2a6c98f5f48ef9fa21fec9717280614ff8b9c72c347 ./artix7/tile_type_LIOB33_SING.json`](./artix7/tile_type_LIOB33_SING.json)
|
||||
* [`cc31c69ecb8245b52b0e62311e028dc2dccd658817a0e14ccce10f499e88c0e3 ./artix7/tile_type_LIOI3.json`](./artix7/tile_type_LIOI3.json)
|
||||
* [`7eca0d27597eba0cf91baff2bf2084d48a4efc0f39268eddcf066662de9ad6b9 ./artix7/tile_type_LIOI3_SING.json`](./artix7/tile_type_LIOI3_SING.json)
|
||||
* [`c48539f3910201f7069804cdbacb83d0721f6b95a68cfee2ec8d6035893409c4 ./artix7/tile_type_LIOI3_TBYTESRC.json`](./artix7/tile_type_LIOI3_TBYTESRC.json)
|
||||
* [`ecfab821b2dae9221e64343a6de46e812623ffbd99b117ff01a847e1caba81a9 ./artix7/tile_type_LIOI3_TBYTETERM.json`](./artix7/tile_type_LIOI3_TBYTETERM.json)
|
||||
* [`8451737d70e6dce0211b85e2343a1daa5fac47017a95f7b19f85ae3efa21cca3 ./artix7/tile_type_L_TERM_INT.json`](./artix7/tile_type_L_TERM_INT.json)
|
||||
* [`9e361342e80dac0278cc6acc0a6b52b1236aa74a04be3a2671556a867b7c92d3 ./artix7/tile_type_MONITOR_BOT.json`](./artix7/tile_type_MONITOR_BOT.json)
|
||||
* [`2b3850d81e0f4fbb6a9bf049de77b99b644c65fbef79fe51b04e4e7ec762d379 ./artix7/tile_type_MONITOR_MID.json`](./artix7/tile_type_MONITOR_MID.json)
|
||||
* [`e85d9d434b86fbf79062ea765d2565e2f9645c1f321653ff25fd3b1e0c6d303d ./artix7/tile_type_MONITOR_TOP.json`](./artix7/tile_type_MONITOR_TOP.json)
|
||||
* [`2ce6ba0efbc6fa49637a90e7c003140d6a5b5fac401c243a3e75505909a5bc7f ./artix7/tile_type_NULL.json`](./artix7/tile_type_NULL.json)
|
||||
* [`86335dda91660eafb7cb39f40706ab11f4113bb96fab2835ad6e3c210b25a5db ./artix7/tile_type_PCIE_BOT.json`](./artix7/tile_type_PCIE_BOT.json)
|
||||
* [`27848877c1f6de2425823155a1387d56a26802ff4400a68945eda10c6aa7f394 ./artix7/tile_type_PCIE_INT_INTERFACE_L.json`](./artix7/tile_type_PCIE_INT_INTERFACE_L.json)
|
||||
* [`d8353f3b93905313827c71114ce17c1ece756843487ff11a86cfd8488723b409 ./artix7/tile_type_PCIE_INT_INTERFACE_R.json`](./artix7/tile_type_PCIE_INT_INTERFACE_R.json)
|
||||
* [`d61def0be37737195c1490b8a0141d490b82be3813664c59ca876035492662fc ./artix7/tile_type_PCIE_NULL.json`](./artix7/tile_type_PCIE_NULL.json)
|
||||
* [`c0c1ea1ee074c261ae528f40af0889bf87d0f2d1b1dc8fa9d91b9f434dbe0ba0 ./artix7/tile_type_PCIE_TOP.json`](./artix7/tile_type_PCIE_TOP.json)
|
||||
* [`8e995e366365b71079600c13337e024426712aa8b9678c13e9da3d12d23b767f ./artix7/tile_type_RIOB33.json`](./artix7/tile_type_RIOB33.json)
|
||||
* [`8ac59745346f219d3f6e4ee9b93083953e895e1ad571bef583a3ad809971c19f ./artix7/tile_type_RIOB33_SING.json`](./artix7/tile_type_RIOB33_SING.json)
|
||||
* [`423861b9d981b7190a5b572cfc3c5625b225f0ccdab2902d2ecce8288ce1bf8c ./artix7/tile_type_RIOI3.json`](./artix7/tile_type_RIOI3.json)
|
||||
* [`bab573b5cb97e3023c66354e35d21ce8cbbe5f354f6a78ef666e0cbb1b4904a9 ./artix7/tile_type_RIOI3_SING.json`](./artix7/tile_type_RIOI3_SING.json)
|
||||
* [`b748c1e71731f0c80bb73b8dd1600a6c70a3ca549c77bde0043cba922e945578 ./artix7/tile_type_RIOI3_TBYTESRC.json`](./artix7/tile_type_RIOI3_TBYTESRC.json)
|
||||
* [`86cf1f5de171b322f0ef68187b091f4a70f903893dcaaaa0a1f3fc13305ad0ee ./artix7/tile_type_RIOI3_TBYTETERM.json`](./artix7/tile_type_RIOI3_TBYTETERM.json)
|
||||
* [`0a786cf51d4102ca179cbde5121024f9a565cac9e0cf7cdf6a2f934dae431ed2 ./artix7/tile_type_R_TERM_INT_GTX.json`](./artix7/tile_type_R_TERM_INT_GTX.json)
|
||||
* [`1e2b6e49f515d4ba18d6384e5824ce447e49416788380caf767335d7d5207b0f ./artix7/tile_type_R_TERM_INT.json`](./artix7/tile_type_R_TERM_INT.json)
|
||||
* [`0b54b5d401ce831f2e39513c933bcd07cad9af7b29e26fb5b5fd8c2fbffa1490 ./artix7/tile_type_TERM_CMT.json`](./artix7/tile_type_TERM_CMT.json)
|
||||
* [`10a3d1ddfae1aef0790f09c8a075d3ee655b64bfd72db454dd0f7a5fdf5c9595 ./artix7/tile_type_T_TERM_INT.json`](./artix7/tile_type_T_TERM_INT.json)
|
||||
* [`27033dfca5462da31e805a4d29e54d69ceb5de3487a364e40630073fcefbb408 ./artix7/tile_type_VBRK_EXT.json`](./artix7/tile_type_VBRK_EXT.json)
|
||||
* [`5e7547acab0a27e3e47521b350da09e6a82d8c1a1e4259996d63a60f768f2f63 ./artix7/tile_type_VBRK.json`](./artix7/tile_type_VBRK.json)
|
||||
* [`d41f88c544effafefbf13060f1710a622d282fd24214b36bbe0164a3a17b3399 ./artix7/tile_type_VFRAME.json`](./artix7/tile_type_VFRAME.json)
|
||||
* [`6a998dd55a7aa4ab33db25db7b5167d57f3d708713baf1fca394dc2940f12007 ./artix7/site_type_BSCAN.json`](./artix7/site_type_BSCAN.json)
|
||||
* [`7f59ea08fa5dbf9ce84ea26f03f13cd02683fce9cdd98621e501e422bf09d165 ./artix7/site_type_BUFGCTRL.json`](./artix7/site_type_BUFGCTRL.json)
|
||||
* [`2d6c78790d74503f0810356de3a765b380b319f09a41593bc8cbe8979defd1f7 ./artix7/site_type_BUFHCE.json`](./artix7/site_type_BUFHCE.json)
|
||||
* [`7d2ad5e0c2a12242cabe03aa9a89bdc1ad4413720c45243809371e06be84a88b ./artix7/site_type_BUFIO.json`](./artix7/site_type_BUFIO.json)
|
||||
* [`99ac6ee5e9381bc68e9e7c0ba1e75779a80360b3854b87cc124819a17cd23a75 ./artix7/site_type_BUFMRCE.json`](./artix7/site_type_BUFMRCE.json)
|
||||
* [`ea18314ade2d867b7ee931c71ccca7780dcda5da63e4c986a5db37508c8df60a ./artix7/site_type_BUFR.json`](./artix7/site_type_BUFR.json)
|
||||
* [`15b8fa9480b7f789bf65aca97263c2b97d120eb3ab79d4330d17e39c36bd0131 ./artix7/site_type_CAPTURE.json`](./artix7/site_type_CAPTURE.json)
|
||||
* [`af89e5523c49b0ede53efd5c2304d1e1a5efb553b52ec873526923f2fd019705 ./artix7/site_type_DCIRESET.json`](./artix7/site_type_DCIRESET.json)
|
||||
* [`79effefe83be725ab9cf4c1167e6e2582144317654c179b5076ae19f7462403b ./artix7/site_type_DNA_PORT.json`](./artix7/site_type_DNA_PORT.json)
|
||||
* [`2326eb345b6c10062379bbb3c7afe5ebc4b9ecbc104f8947158dbae09c09e7c8 ./artix7/site_type_DSP48E1.json`](./artix7/site_type_DSP48E1.json)
|
||||
* [`75db786def8e1871ca3fd7c65d6481a53464f000343b32155ee3a05dd86eb0b3 ./artix7/site_type_EFUSE_USR.json`](./artix7/site_type_EFUSE_USR.json)
|
||||
* [`a9e6d74302ee507649432e33e31d21d8feaf6b51e2ae0f26a579c16f57f59512 ./artix7/site_type_FIFO18E1.json`](./artix7/site_type_FIFO18E1.json)
|
||||
* [`0d1ff1869cb0c2ceb18b7d6e4d53abc15db8712ed4f6845c6ed093e0d28d2fe8 ./artix7/site_type_FRAME_ECC.json`](./artix7/site_type_FRAME_ECC.json)
|
||||
* [`77cf2f8bdde15b54743f8ce3e919890f15954003786b0be8b5ae034e72fa7e27 ./artix7/site_type_GTPE2_CHANNEL.json`](./artix7/site_type_GTPE2_CHANNEL.json)
|
||||
* [`bab2074cd8be6c79f978b03a2f7a631a6ed01fc5a8cd35b1a92348fb7854ecb0 ./artix7/site_type_GTPE2_COMMON.json`](./artix7/site_type_GTPE2_COMMON.json)
|
||||
* [`e4b974ca43493be5444c2c2a4a0c243712e882499f8ca87efc38bdca267cc988 ./artix7/site_type_IBUFDS_GTE2.json`](./artix7/site_type_IBUFDS_GTE2.json)
|
||||
* [`a2514cd2da5e5cabdc3babd476b014b6b44a2cc8fca19f2f2785cb207abbb751 ./artix7/site_type_ICAP.json`](./artix7/site_type_ICAP.json)
|
||||
* [`d23176a42d861807d5bd2559e58f31e3ffe516d3c0597ace669c88f0f8bdd145 ./artix7/site_type_IDELAYCTRL.json`](./artix7/site_type_IDELAYCTRL.json)
|
||||
* [`2bf5daae4d45e9b6d65fbfa7c73426c896bc071d9b577b57371f8570836acb86 ./artix7/site_type_IDELAYE2.json`](./artix7/site_type_IDELAYE2.json)
|
||||
* [`05ffeb28332d5d17fc32b2410da41b0b97426a01bb4a3cd84849ab386b50c543 ./artix7/site_type_ILOGICE3.json`](./artix7/site_type_ILOGICE3.json)
|
||||
* [`ef48fb9be2319b50b808ead0726bc6a037377fe10fbf3d22ca9acd29def80e2b ./artix7/site_type_IN_FIFO.json`](./artix7/site_type_IN_FIFO.json)
|
||||
* [`c98ef8397786c5c71b2c5a43824ce47f0e46c93424eef58ad47bf0f7c7d42675 ./artix7/site_type_IOB33.json`](./artix7/site_type_IOB33.json)
|
||||
* [`76e2eb01e49adb5b5d7586d57b5dc07b2104aac9295f173d2b2b3724a86a9eb0 ./artix7/site_type_IOB33M.json`](./artix7/site_type_IOB33M.json)
|
||||
* [`ccdec6f60ba548d85b3b24345c0fbc4b5e703c0de936f12c09c5c0fb822fcf3e ./artix7/site_type_IOB33S.json`](./artix7/site_type_IOB33S.json)
|
||||
* [`7d0bc5533db085e0ef68a2dbd16906b4936bb35efa4790953c2c4ee607f1ed28 ./artix7/site_type_IPAD.json`](./artix7/site_type_IPAD.json)
|
||||
* [`bf073833d9a7b9e125d4829e464cdd67a61bf9195d0dd7854f1fa6397014aacc ./artix7/site_type_MMCME2_ADV.json`](./artix7/site_type_MMCME2_ADV.json)
|
||||
* [`186eac82246b8b10da9abab93b15f638bdb8ef446ce0e4b4ceb797e2091132dd ./artix7/site_type_OLOGICE3.json`](./artix7/site_type_OLOGICE3.json)
|
||||
* [`b4670a20c46552416276ba8e5442b4c3d24c6215650a212f00f874dc78371bca ./artix7/site_type_OPAD.json`](./artix7/site_type_OPAD.json)
|
||||
* [`776619b1507bfe996cfa7b900058cff911bd96a29dac1b33e5b29aa662053aad ./artix7/site_type_OUT_FIFO.json`](./artix7/site_type_OUT_FIFO.json)
|
||||
* [`06edd04ea43682f65f2d8cbc6282d5e10385c23e75bd61ddd99c4e6ce2b9fcf6 ./artix7/site_type_PCIE_2_1.json`](./artix7/site_type_PCIE_2_1.json)
|
||||
* [`311eda695286ee7edd51cc78c3c6bdbe9901bcb515308a17572302af321fdbc4 ./artix7/site_type_PHASER_IN_PHY.json`](./artix7/site_type_PHASER_IN_PHY.json)
|
||||
* [`2474fdfcd0bd228964e62f4875e9684e15984ee57e40b17f6759a5897148cba5 ./artix7/site_type_PHASER_OUT_PHY.json`](./artix7/site_type_PHASER_OUT_PHY.json)
|
||||
* [`f8aefb394bd6cef6244a56a4376bf0a44ce368741dfbce8cf7f5df45a71c47a3 ./artix7/site_type_PHASER_REF.json`](./artix7/site_type_PHASER_REF.json)
|
||||
* [`01733676f386e217548135ed297b2fa73e0d0d17003b84513708ed8508f447ce ./artix7/site_type_PHY_CONTROL.json`](./artix7/site_type_PHY_CONTROL.json)
|
||||
* [`e314d184ac0bbe656ca4d34c33af80149b4d7dbe6798094de089462f78b52405 ./artix7/site_type_PLLE2_ADV.json`](./artix7/site_type_PLLE2_ADV.json)
|
||||
* [`58897a08e0442222f117be75393c6b46360933abc71ff1de142ba7adcaabfa3f ./artix7/site_type_PMV2.json`](./artix7/site_type_PMV2.json)
|
||||
* [`110126d521d4744019d75f9c0bdcef76851b2c8f003fed0d5dbb7f7806aadae7 ./artix7/site_type_RAMB18E1.json`](./artix7/site_type_RAMB18E1.json)
|
||||
* [`1ab295693d283025d16966f5ed48515046fea1078529d48e0eab5eef732bcb40 ./artix7/site_type_RAMBFIFO36E1.json`](./artix7/site_type_RAMBFIFO36E1.json)
|
||||
* [`586145c0b465d7ac945746193cf4f38ec5bb26bbc52997bce47d5fbdd9d0c241 ./artix7/site_type_SLICEL.json`](./artix7/site_type_SLICEL.json)
|
||||
* [`201ecff6bb7d78c8597d467e55486fc00b2ad95a6a7dee0cd98346ab9e8c888a ./artix7/site_type_SLICEM.json`](./artix7/site_type_SLICEM.json)
|
||||
* [`872bc95eb5f912fc95ca2ca18960b14b9cc20f00bf30b7227d0c6c9b0f3bbeb0 ./artix7/site_type_STARTUP.json`](./artix7/site_type_STARTUP.json)
|
||||
* [`db8c88384575a7e0562692550bdba7a4089ea5fabe451bf58403d3a85af419a0 ./artix7/site_type_TIEOFF.json`](./artix7/site_type_TIEOFF.json)
|
||||
* [`4d6130cb2604efae8ca5d628b95be2549083c16c639d335bdc906924e37ec28c ./artix7/site_type_USR_ACCESS.json`](./artix7/site_type_USR_ACCESS.json)
|
||||
* [`dbf0ff3b27d1fac02572351765f1b17b3e950ed4e8fe95ac6bcd71012e4f7b2d ./artix7/site_type_XADC.json`](./artix7/site_type_XADC.json)
|
||||
* [`2af71373b90795d9db335d93f255391c9f11abc72a1dfd96b9d964bf254290d3 ./artix7/tileconn.json`](./artix7/tileconn.json)
|
||||
* [`455829274901658159f9f06f8021b34a19e8fe891991a4c3ea137a8d5646e998 ./artix7/tilegrid.json`](./artix7/tilegrid.json)
|
||||
* [`a93b4be2b2832d1a9240b892f6d8db469f3d9cf6229cc6856a197e854f4abc8a ./artix7/tile_type_BRAM_INT_INTERFACE_L.json`](./artix7/tile_type_BRAM_INT_INTERFACE_L.json)
|
||||
* [`fff3e640e286158767fc484ec932d0ce7eba48c1168798c11c7779426a846004 ./artix7/tile_type_BRAM_INT_INTERFACE_R.json`](./artix7/tile_type_BRAM_INT_INTERFACE_R.json)
|
||||
* [`ea83df939d85f211eebf41d40d8ee9c5b7f1d6c493c5f4b842cbf3b6d9b9b186 ./artix7/tile_type_BRAM_L.json`](./artix7/tile_type_BRAM_L.json)
|
||||
* [`6ab1d2945ad2a51c7b533a555f3e07734043f158e15082a459e4aea08f4f17ae ./artix7/tile_type_BRAM_R.json`](./artix7/tile_type_BRAM_R.json)
|
||||
* [`db6c15155f364bd395363fb230bf43119a0081e41d659b0afb01dc5144da723a ./artix7/tile_type_BRKH_BRAM.json`](./artix7/tile_type_BRKH_BRAM.json)
|
||||
* [`9d3a3030a2e3b2cf1ac5325613d6f97121d92520573f5623f4bca7cc1f93f488 ./artix7/tile_type_BRKH_B_TERM_INT.json`](./artix7/tile_type_BRKH_B_TERM_INT.json)
|
||||
* [`118df8447c839ff5b9e2325e328c0251d67f9bf5db209b7f2782f9235f240311 ./artix7/tile_type_BRKH_CLB.json`](./artix7/tile_type_BRKH_CLB.json)
|
||||
* [`0d3e86aab90d3bb52dd77b187695d3cb3777e46336d1fc1725b6329b8902b626 ./artix7/tile_type_BRKH_CLK.json`](./artix7/tile_type_BRKH_CLK.json)
|
||||
* [`7679aeafb655e2bd58deddc3ab9746ee00e801e4f6b3cd93e17d66f211beb288 ./artix7/tile_type_BRKH_CMT.json`](./artix7/tile_type_BRKH_CMT.json)
|
||||
* [`5c19ea98b80ca36a2a91388352ebd37bba5b85e2580a5cb10ef1b9a31b26a009 ./artix7/tile_type_BRKH_DSP_L.json`](./artix7/tile_type_BRKH_DSP_L.json)
|
||||
* [`15db89f4dc5243d4e315e8130937270919397031ec30ec764fde6400f9b5d651 ./artix7/tile_type_BRKH_DSP_R.json`](./artix7/tile_type_BRKH_DSP_R.json)
|
||||
* [`856754623cc87f0058d073999e25faab904f7edef7beb0a818e60ab853fa5b97 ./artix7/tile_type_BRKH_GTX.json`](./artix7/tile_type_BRKH_GTX.json)
|
||||
* [`f2e45380bacb76cfb51982ce6e561a9af21d8df0e51bbf0d1ab946e0372739e1 ./artix7/tile_type_BRKH_INT.json`](./artix7/tile_type_BRKH_INT.json)
|
||||
* [`f03132d07804f511371569891bf51d6c14490ee9460f57728e179ee2a7be4cdc ./artix7/tile_type_BRKH_TERM_INT.json`](./artix7/tile_type_BRKH_TERM_INT.json)
|
||||
* [`3c0cc073cc1c80424074ca96a1a87099e040512d279c313109b96146adf94c8e ./artix7/tile_type_B_TERM_INT.json`](./artix7/tile_type_B_TERM_INT.json)
|
||||
* [`b4cf053f06f3965af2f05b74e43eff6bdf24daf8ee2cb61ddeeee70e71ed660d ./artix7/tile_type_CFG_CENTER_BOT.json`](./artix7/tile_type_CFG_CENTER_BOT.json)
|
||||
* [`82468ad16be6809588902afecfb06ec15ec7408b6cd1e3b99fe14430a62e11a2 ./artix7/tile_type_CFG_CENTER_MID.json`](./artix7/tile_type_CFG_CENTER_MID.json)
|
||||
* [`413970a4868c43567623a14b4093be69899de10ebba2f62fd06137660b35b6dc ./artix7/tile_type_CFG_CENTER_TOP.json`](./artix7/tile_type_CFG_CENTER_TOP.json)
|
||||
* [`51e08a3158bfddccb5c43b0dc7ff6f55fe303df871795fdd921b8963e619e95c ./artix7/tile_type_CLBLL_L.json`](./artix7/tile_type_CLBLL_L.json)
|
||||
* [`9b2e66795a517636d5af80c81ec7ac1c8189a553648a9b2d767c5ec3e9819508 ./artix7/tile_type_CLBLL_R.json`](./artix7/tile_type_CLBLL_R.json)
|
||||
* [`0b0e0bb74eb6b8864a94663ec9adb7f14f29ebdffafb3088bbf794b51935a322 ./artix7/tile_type_CLBLM_L.json`](./artix7/tile_type_CLBLM_L.json)
|
||||
* [`ec924ac530dbd8592880606da2244a55d19c05a14357ab8032aecc7ef2eb0fa9 ./artix7/tile_type_CLBLM_R.json`](./artix7/tile_type_CLBLM_R.json)
|
||||
* [`656de9ce6a18a058c083d07bae3433fde5899680ac68165e9e8430023c2f123c ./artix7/tile_type_CLK_BUFG_BOT_R.json`](./artix7/tile_type_CLK_BUFG_BOT_R.json)
|
||||
* [`6aa792786a1fbb38c20f1aceba3936775473d8dff5529f7aa41e8da38eee4c0c ./artix7/tile_type_CLK_BUFG_REBUF.json`](./artix7/tile_type_CLK_BUFG_REBUF.json)
|
||||
* [`c478ac96f632d69db13f870eab1d86a84b3e47af5a2b4b6b93c3c71b3d75e87e ./artix7/tile_type_CLK_BUFG_TOP_R.json`](./artix7/tile_type_CLK_BUFG_TOP_R.json)
|
||||
* [`d6df6130236178fdfecd77e7ab871dd7f5f5d91270aff446bbc6082b5d611f50 ./artix7/tile_type_CLK_FEED.json`](./artix7/tile_type_CLK_FEED.json)
|
||||
* [`1a9f04a7268c7db635363e4c6d5885b3979cf9d7d3c67a202b3ac3af5c124122 ./artix7/tile_type_CLK_HROW_BOT_R.json`](./artix7/tile_type_CLK_HROW_BOT_R.json)
|
||||
* [`b0b961602f0f9fdb17e2ca7566ef85543f0734b7e4e9822d4e5ce3763def1bdc ./artix7/tile_type_CLK_HROW_TOP_R.json`](./artix7/tile_type_CLK_HROW_TOP_R.json)
|
||||
* [`54365a8bfc347ca228266b6a682e0ccb1a5c98283c90efc3b738b962134d62ba ./artix7/tile_type_CLK_MTBF2.json`](./artix7/tile_type_CLK_MTBF2.json)
|
||||
* [`60f5de137907091563bc64aadc4caab115d6527c31525c6ede9148b4f9b5f3d9 ./artix7/tile_type_CLK_PMV2.json`](./artix7/tile_type_CLK_PMV2.json)
|
||||
* [`392df005504cbc65b160a7eacf01d885617b0c2869269ba5de7b490c069993fe ./artix7/tile_type_CLK_PMV2_SVT.json`](./artix7/tile_type_CLK_PMV2_SVT.json)
|
||||
* [`aeb291f8b0d6e930b1a9dfeddf444f78cf7b8a3e1b4bfd68695a610b4a56df15 ./artix7/tile_type_CLK_PMVIOB.json`](./artix7/tile_type_CLK_PMVIOB.json)
|
||||
* [`2cf3b04cc58a0d9c9655d8a002ad789f15cc0da42ce797d616501af10ceaf3e5 ./artix7/tile_type_CLK_PMV.json`](./artix7/tile_type_CLK_PMV.json)
|
||||
* [`3049d7d2fd6c902737f1a17661eea9fd8e195e7623e602737e5573bc226b659e ./artix7/tile_type_CLK_TERM.json`](./artix7/tile_type_CLK_TERM.json)
|
||||
* [`f34c8817cd592fbd84bf5320aa2afe886e400219227e23106ab20bb14bf6b0e9 ./artix7/tile_type_CMT_FIFO_L.json`](./artix7/tile_type_CMT_FIFO_L.json)
|
||||
* [`3f5c5c44013567f9162fecd20bc76a888f5426f363445c83a90e7765e7ac5328 ./artix7/tile_type_CMT_FIFO_R.json`](./artix7/tile_type_CMT_FIFO_R.json)
|
||||
* [`ee092eb4fe6b8acdd0e145c57e0555390668dfe0b4fb4ecf72f1104a1f464380 ./artix7/tile_type_CMT_PMV.json`](./artix7/tile_type_CMT_PMV.json)
|
||||
* [`f14e9d7dc485f0f7feba84cbc2824d2f6f49f78db009feaef3425a4bf818454a ./artix7/tile_type_CMT_PMV_L.json`](./artix7/tile_type_CMT_PMV_L.json)
|
||||
* [`e7931a0f222780de2736402376667bfa06deaf5631af6e3ae7ecdc04ef4cf0e9 ./artix7/tile_type_CMT_TOP_L_LOWER_B.json`](./artix7/tile_type_CMT_TOP_L_LOWER_B.json)
|
||||
* [`a6e0cf15801f96b7dbb09beb5c50d0468a971b615707990c9dc6f9b2606b9fcf ./artix7/tile_type_CMT_TOP_L_LOWER_T.json`](./artix7/tile_type_CMT_TOP_L_LOWER_T.json)
|
||||
* [`be837955af15b1b057d389f90db066e7364a4aabc63174797157028d950a0736 ./artix7/tile_type_CMT_TOP_L_UPPER_B.json`](./artix7/tile_type_CMT_TOP_L_UPPER_B.json)
|
||||
* [`601852861f50e91ec1398eeb464500f8364fea828630ce02e5feb3c2754eab1e ./artix7/tile_type_CMT_TOP_L_UPPER_T.json`](./artix7/tile_type_CMT_TOP_L_UPPER_T.json)
|
||||
* [`41f0cdfdfe2a777484296d12f667fe87051c918264be5548cf1e8f8c0a82d6fa ./artix7/tile_type_CMT_TOP_R_LOWER_B.json`](./artix7/tile_type_CMT_TOP_R_LOWER_B.json)
|
||||
* [`769bdd34e337f36851ea020d58e56fd4e3b574b82e64b165c9f9e97c3e7a1619 ./artix7/tile_type_CMT_TOP_R_LOWER_T.json`](./artix7/tile_type_CMT_TOP_R_LOWER_T.json)
|
||||
* [`c276d9faead06cb6b67ab993a1b06f3a3547b0cefbf79008f007123f884a05f9 ./artix7/tile_type_CMT_TOP_R_UPPER_B.json`](./artix7/tile_type_CMT_TOP_R_UPPER_B.json)
|
||||
* [`e91fbf80b93b718cf155474a3aa109323562c24e436fcd0d1ecfd49dae334c85 ./artix7/tile_type_CMT_TOP_R_UPPER_T.json`](./artix7/tile_type_CMT_TOP_R_UPPER_T.json)
|
||||
* [`d974d8b2ed0f24712a667d24cb18c39d02e967820c2dc0dda0c2cb9e720f3e61 ./artix7/tile_type_DSP_L.json`](./artix7/tile_type_DSP_L.json)
|
||||
* [`36af7277166ad1c44d805c719b48f84e9fba4934402df04bbd0c1aefb5148715 ./artix7/tile_type_DSP_R.json`](./artix7/tile_type_DSP_R.json)
|
||||
* [`bf49bc8adf109a0df4145cafa3dbb7ea56cfff0fa76d87194a3a4278a3139934 ./artix7/tile_type_GTP_CHANNEL_0.json`](./artix7/tile_type_GTP_CHANNEL_0.json)
|
||||
* [`71420e22ec3b1c98516d39351fffb9c0e35fa25e0e3d36f1aab5eb626cbaca03 ./artix7/tile_type_GTP_CHANNEL_1.json`](./artix7/tile_type_GTP_CHANNEL_1.json)
|
||||
* [`35a49d1b89098b4b40ddbbe7c0d15e0d0e84e4fa3d7c83fc386e52f8fec5ac6c ./artix7/tile_type_GTP_CHANNEL_2.json`](./artix7/tile_type_GTP_CHANNEL_2.json)
|
||||
* [`635bac1584ffde0c4c74fe62ea5b80875df647f7f9da1d0ee57968c533dc9e50 ./artix7/tile_type_GTP_CHANNEL_3.json`](./artix7/tile_type_GTP_CHANNEL_3.json)
|
||||
* [`f581abfe65da2db8d833e144c3526fabc993016c9abea0112967e7837c3c8bdd ./artix7/tile_type_GTP_COMMON.json`](./artix7/tile_type_GTP_COMMON.json)
|
||||
* [`7f7c6b69d7e2923ebeed16e83f6a25b35d5a1f18a61442ce6d9823db842b5570 ./artix7/tile_type_GTP_INT_INTERFACE.json`](./artix7/tile_type_GTP_INT_INTERFACE.json)
|
||||
* [`354ef04f0bdda1de5dcdcd33f5755a1d23ed12736f9130cf7be4b1177331ac42 ./artix7/tile_type_HCLK_BRAM.json`](./artix7/tile_type_HCLK_BRAM.json)
|
||||
* [`df7c1fe5e634ef598e274709c416a89cbb7a466467ba8bb7aa2a06c92271f2ef ./artix7/tile_type_HCLK_CLB.json`](./artix7/tile_type_HCLK_CLB.json)
|
||||
* [`28bf8be9e5b51f2125c8af8a9e4645494bc09265f212a19762dca8731934dd29 ./artix7/tile_type_HCLK_CMT.json`](./artix7/tile_type_HCLK_CMT.json)
|
||||
* [`1a3eaf022b48825d6054418bf8c6eb9813fdfde0ed316d9ce2195559bb2c9b75 ./artix7/tile_type_HCLK_CMT_L.json`](./artix7/tile_type_HCLK_CMT_L.json)
|
||||
* [`ba1573347a1e8aaf273177dd9a47ae0cbb460031944c4e9207aaeec06e6d6f3d ./artix7/tile_type_HCLK_DSP_L.json`](./artix7/tile_type_HCLK_DSP_L.json)
|
||||
* [`1558e3a24f99161db174a0000aa7bf463ea2f658fdc0d5de95857c63e4781e76 ./artix7/tile_type_HCLK_DSP_R.json`](./artix7/tile_type_HCLK_DSP_R.json)
|
||||
* [`981440f3c25fe99c89e59397d1f53ae2ea0ede7bf3b31ccd455a3f37cc1aa7df ./artix7/tile_type_HCLK_FEEDTHRU_1.json`](./artix7/tile_type_HCLK_FEEDTHRU_1.json)
|
||||
* [`3114e5e086d22c789be17eab304f8cdc111c6a16815206ecabe587b47821d189 ./artix7/tile_type_HCLK_FEEDTHRU_2.json`](./artix7/tile_type_HCLK_FEEDTHRU_2.json)
|
||||
* [`b41e34860cc61a3ddfe4237aca23aa6f076c91c8419e432bad2b8808a0e2f066 ./artix7/tile_type_HCLK_FIFO_L.json`](./artix7/tile_type_HCLK_FIFO_L.json)
|
||||
* [`7ab3f91abd87e8fc978a8c565578f62a62ca9f9f3a0f91ca5fc1f12eee48e24d ./artix7/tile_type_HCLK_GTX.json`](./artix7/tile_type_HCLK_GTX.json)
|
||||
* [`e9b15f998078da307163484c613e6428527269203566108aced10b9d10b5330c ./artix7/tile_type_HCLK_INT_INTERFACE.json`](./artix7/tile_type_HCLK_INT_INTERFACE.json)
|
||||
* [`89ccb8895863d40efc4a2d2af8df687a12ddd32b77b81ace67263b1118a3597d ./artix7/tile_type_HCLK_IOB.json`](./artix7/tile_type_HCLK_IOB.json)
|
||||
* [`13dc53e8a8b564d9ba858abba842e052bd2d9c92f3585ca06aa185fddd389f21 ./artix7/tile_type_HCLK_IOI3.json`](./artix7/tile_type_HCLK_IOI3.json)
|
||||
* [`06bf665ee2c3cedd70c74dc2a62681b5f1bb3b3068672389fafd11c6eef95b2e ./artix7/tile_type_HCLK_L_BOT_UTURN.json`](./artix7/tile_type_HCLK_L_BOT_UTURN.json)
|
||||
* [`416fcad956b2082d8a17e57190f1470171f134397a4cdb23beccc35edcd58c50 ./artix7/tile_type_HCLK_L.json`](./artix7/tile_type_HCLK_L.json)
|
||||
* [`fa5fe9cf004090046dc5a6829410efb4379a9670f0fdd01e7bb8a8c1bb01bff0 ./artix7/tile_type_HCLK_R_BOT_UTURN.json`](./artix7/tile_type_HCLK_R_BOT_UTURN.json)
|
||||
* [`750bdec4a5452c3d177995e0ed1405aca81a1a2b1998fb244fcfe0c266bdf0ee ./artix7/tile_type_HCLK_R.json`](./artix7/tile_type_HCLK_R.json)
|
||||
* [`b371b59e75bb9b18ba85b6ad43eaae3defe411a77c383c2c65780d8763c90f98 ./artix7/tile_type_HCLK_TERM_GTX.json`](./artix7/tile_type_HCLK_TERM_GTX.json)
|
||||
* [`3713a04488775af071b9488eb191415e084b3c17e9a03ab38e514b61d822172e ./artix7/tile_type_HCLK_TERM.json`](./artix7/tile_type_HCLK_TERM.json)
|
||||
* [`29f2633c9d8109d756ca8bafb3537d8bbfebb7f4999a25d41ed7176b9f2e8258 ./artix7/tile_type_HCLK_VBRK.json`](./artix7/tile_type_HCLK_VBRK.json)
|
||||
* [`5c818e93dedf3f75062bca58782ac334a9c25bece6406766fb72c329ba7f67b7 ./artix7/tile_type_HCLK_VFRAME.json`](./artix7/tile_type_HCLK_VFRAME.json)
|
||||
* [`fa8e254275184672267a3b7fcaf21aed716c77467ab487bb4bcc6e32f0c102f3 ./artix7/tile_type_INT_FEEDTHRU_1.json`](./artix7/tile_type_INT_FEEDTHRU_1.json)
|
||||
* [`fc80af4e87d86b5b5554e1b44546440bfab85bc4ae1557ceed06d8209d098f38 ./artix7/tile_type_INT_FEEDTHRU_2.json`](./artix7/tile_type_INT_FEEDTHRU_2.json)
|
||||
* [`2f388adb0b97739b0292e3aefb249346e48916d4c02816d2dd477ca66baaca38 ./artix7/tile_type_INT_INTERFACE_L.json`](./artix7/tile_type_INT_INTERFACE_L.json)
|
||||
* [`9b5d722203552f898fb7ec3cee58904f61bebaae1501d5adbc6fbbd670634d67 ./artix7/tile_type_INT_INTERFACE_R.json`](./artix7/tile_type_INT_INTERFACE_R.json)
|
||||
* [`acb01192a3328a1071cfb9ee54c16107d164a6249068a25dfa731fd933f10be6 ./artix7/tile_type_INT_L.json`](./artix7/tile_type_INT_L.json)
|
||||
* [`b1ada7c7e90afe1b4942897912f028b258e7157bbd9041f399b268fe256b270c ./artix7/tile_type_INT_R.json`](./artix7/tile_type_INT_R.json)
|
||||
* [`1eb3c6e2ffed9dd7bf8c88db42e5ddb3834966d59935973be256dbe3081c26d8 ./artix7/tile_type_IO_INT_INTERFACE_L.json`](./artix7/tile_type_IO_INT_INTERFACE_L.json)
|
||||
* [`c77d0a3cac3f62df502bf81e5b3ec9dd902872b9d642a711734f434259a3ca74 ./artix7/tile_type_IO_INT_INTERFACE_R.json`](./artix7/tile_type_IO_INT_INTERFACE_R.json)
|
||||
* [`16a518f917b854c87eafdebe24261b758a868940de8a4629de650befa9f86da0 ./artix7/tile_type_LIOB33.json`](./artix7/tile_type_LIOB33.json)
|
||||
* [`c095de913db4bddfcabbd5697a841500d344f83881f4d1beac75428cb25aad64 ./artix7/tile_type_LIOB33_SING.json`](./artix7/tile_type_LIOB33_SING.json)
|
||||
* [`72855c141f9eaf7238ff243e223439eee18df1b1bfba4f8a686835f1542c880a ./artix7/tile_type_LIOI3.json`](./artix7/tile_type_LIOI3.json)
|
||||
* [`1e6fad575e8b68ce44fea9b0509cc5d83ca0670cf97cebf4a29f983bee5ae49e ./artix7/tile_type_LIOI3_SING.json`](./artix7/tile_type_LIOI3_SING.json)
|
||||
* [`f35fc20f3f65bf3f867cf477bcdd288e7270fda5d0204742d2f137fe08476f1d ./artix7/tile_type_LIOI3_TBYTESRC.json`](./artix7/tile_type_LIOI3_TBYTESRC.json)
|
||||
* [`05cf5e8fda8975612f1eaf0a08c8f9c18b9719d471cdd382241d8788698e6297 ./artix7/tile_type_LIOI3_TBYTETERM.json`](./artix7/tile_type_LIOI3_TBYTETERM.json)
|
||||
* [`e1c8778875bb256d12ed385b622bce95d86f5bd46c7aa5748f74f0854e39f2fd ./artix7/tile_type_L_TERM_INT.json`](./artix7/tile_type_L_TERM_INT.json)
|
||||
* [`37fadb30f0cef301907968b8129ae02704ba4c9d11caa42db31fed8734a4f2da ./artix7/tile_type_MONITOR_BOT.json`](./artix7/tile_type_MONITOR_BOT.json)
|
||||
* [`f2e9686909e9dfa00edde4d8020bf7da5cc33be88c5f12cb0b9495146da427b3 ./artix7/tile_type_MONITOR_MID.json`](./artix7/tile_type_MONITOR_MID.json)
|
||||
* [`7ac845de92f8b347fbfab9b6e0602939db7bb754ab7457f8f69ea9c5edf25675 ./artix7/tile_type_MONITOR_TOP.json`](./artix7/tile_type_MONITOR_TOP.json)
|
||||
* [`2397779fbc09ce1abbb28d2d3b0dbd2c2d8ab733971455898b720ed41405943c ./artix7/tile_type_NULL.json`](./artix7/tile_type_NULL.json)
|
||||
* [`cdde011fe6911e6bada3d8cb076a638fbcbe8daf3a3a1f312f6435a0393e742c ./artix7/tile_type_PCIE_BOT.json`](./artix7/tile_type_PCIE_BOT.json)
|
||||
* [`f40a6d7b7146547db93e4de9bcde2079a2a2b2e4059741ae77365d684d777514 ./artix7/tile_type_PCIE_INT_INTERFACE_L.json`](./artix7/tile_type_PCIE_INT_INTERFACE_L.json)
|
||||
* [`ace3f9b3eeea6b9ed9505bc4c9934731ee7c3ed5e18279ec1845564210ab9b44 ./artix7/tile_type_PCIE_INT_INTERFACE_R.json`](./artix7/tile_type_PCIE_INT_INTERFACE_R.json)
|
||||
* [`12f4f10939cf94413223482516debe3c272717af213589426b58ca4bc9043df7 ./artix7/tile_type_PCIE_NULL.json`](./artix7/tile_type_PCIE_NULL.json)
|
||||
* [`e3ef7cfe139e7d320b2e47fac82f33fc8dbbf9727a76ca093f35f4c85703ac58 ./artix7/tile_type_PCIE_TOP.json`](./artix7/tile_type_PCIE_TOP.json)
|
||||
* [`ba17ebf1d15798abb6cf1dfd778ec238d3e6a511123712844212505af309ab41 ./artix7/tile_type_RIOB33.json`](./artix7/tile_type_RIOB33.json)
|
||||
* [`b36cfe448aaaafd07e3be3766340a98d5be6c3f0a8130a617d863faf50935d9b ./artix7/tile_type_RIOB33_SING.json`](./artix7/tile_type_RIOB33_SING.json)
|
||||
* [`2cf0dad0a74b62c4405e570b5d3603dec445a2a2ff2e25f6a4e7e2cdc0bb28a3 ./artix7/tile_type_RIOI3.json`](./artix7/tile_type_RIOI3.json)
|
||||
* [`18668c5f60af9b0bc73bdf2558151015bd46c58cd8f50902be92ec2d5ba32741 ./artix7/tile_type_RIOI3_SING.json`](./artix7/tile_type_RIOI3_SING.json)
|
||||
* [`598dcc4e3ecc740d7a9f8436f1687b727acc4dc670516c5b9fde4f9b741062e3 ./artix7/tile_type_RIOI3_TBYTESRC.json`](./artix7/tile_type_RIOI3_TBYTESRC.json)
|
||||
* [`c16190419588267fbca00b1b2e0d3f5f193a9eea8b783f1230056a23b551f529 ./artix7/tile_type_RIOI3_TBYTETERM.json`](./artix7/tile_type_RIOI3_TBYTETERM.json)
|
||||
* [`3f8ed6685fa00260c4c65b8401a4cf13aea24d833a634cc567aaeeeb1c29b23a ./artix7/tile_type_R_TERM_INT_GTX.json`](./artix7/tile_type_R_TERM_INT_GTX.json)
|
||||
* [`50eb0be5594840accc6fbf8cd9f060d57b9a5e975e035157545dd86451563a36 ./artix7/tile_type_R_TERM_INT.json`](./artix7/tile_type_R_TERM_INT.json)
|
||||
* [`6a66169978dc3250a90b949218a5f3d82ee68b2aac7868ad6f3aabe0ec7a8c05 ./artix7/tile_type_TERM_CMT.json`](./artix7/tile_type_TERM_CMT.json)
|
||||
* [`861c90352175d3daab60219cd90a25ed429ea635b22eb06581c70625b8e606a7 ./artix7/tile_type_T_TERM_INT.json`](./artix7/tile_type_T_TERM_INT.json)
|
||||
* [`2ce397e17c318c2fd95ebc20bb9c683e12d08ecaab5914f434e9e6ba80b108d8 ./artix7/tile_type_VBRK_EXT.json`](./artix7/tile_type_VBRK_EXT.json)
|
||||
* [`05351758a94de46419680b6d8306ea0366afe7ba14bf0539726db96cdc76cf8d ./artix7/tile_type_VBRK.json`](./artix7/tile_type_VBRK.json)
|
||||
* [`4b910b14d8ff3234d37be5adfc19808701ff336c943e35492414e8417a7d856c ./artix7/tile_type_VFRAME.json`](./artix7/tile_type_VFRAME.json)
|
||||
* [`ef0724733da87455426a0f833642d96e9d206d047f4eb97072c3093f80c40d7d ./artix7/xc7a35tcpg236-1.yaml`](./artix7/xc7a35tcpg236-1.yaml)
|
||||
* [`ef0724733da87455426a0f833642d96e9d206d047f4eb97072c3093f80c40d7d ./artix7/xc7a35tcsg324-1.yaml`](./artix7/xc7a35tcsg324-1.yaml)
|
||||
* [`41c360b1e2f7e08b9051f1160a34954ce4c05a445a07f226f1f4059caf1fa1d3 ./artix7/xc7a50tfgg484-1.yaml`](./artix7/xc7a50tfgg484-1.yaml)
|
||||
|
|
@ -383,171 +383,171 @@ Results have checksums;
|
|||
* [`51b25643ef3b8a7a90181ad61199cd70ac8c5baa18ee1aacd2e81ff50ccdbfcf ./kintex7/segbits_int_l.db`](./kintex7/segbits_int_l.db)
|
||||
* [`05d1165f911881b3600b01f86cad9a6618c8b0dadb7014def3145f9254fd0c45 ./kintex7/segbits_int_r.db`](./kintex7/segbits_int_r.db)
|
||||
* [`555d484e8c10c35897ac446eb7a1bbebf0606c56dcd19caa9c8d916bb77cad64 ./kintex7/settings.sh`](./kintex7/settings.sh)
|
||||
* [`3d3390a265afd578bb096a995b3cd820b910712e6392d8abf6c4d90ba77cf3bd ./kintex7/site_type_BSCAN.json`](./kintex7/site_type_BSCAN.json)
|
||||
* [`b4fd720cdfda56436ae275c9b96eac3b02d1eb46cc7ed67bcdbe02a22288f96a ./kintex7/site_type_BUFGCTRL.json`](./kintex7/site_type_BUFGCTRL.json)
|
||||
* [`de586b421d77a904b9814921ad04b9dd37bf55dccbcb457d2cd5b7bd2059e408 ./kintex7/site_type_BUFHCE.json`](./kintex7/site_type_BUFHCE.json)
|
||||
* [`b8fba943d1daba4bf68b60662ecd54d15d2e420844b3c365fccbbf540397e04f ./kintex7/site_type_BUFIO.json`](./kintex7/site_type_BUFIO.json)
|
||||
* [`12f445c57c357a516bee5821b4432afa3428cc2435485fe4760d9f9d71df01da ./kintex7/site_type_BUFMRCE.json`](./kintex7/site_type_BUFMRCE.json)
|
||||
* [`7f74df4f448f0688ff77300ca3a78f43d850876f50974dd99fa3e4b2b9eb93c4 ./kintex7/site_type_BUFR.json`](./kintex7/site_type_BUFR.json)
|
||||
* [`918f7d1fa92e0781305ce37ec4a4803efbb19472b165b7a56fa78f254f5df8dc ./kintex7/site_type_CAPTURE.json`](./kintex7/site_type_CAPTURE.json)
|
||||
* [`74c501f8de850d82eb3f3c9b1e50dfb0c29ead2449b03d85378bef0483219e0f ./kintex7/site_type_DCIRESET.json`](./kintex7/site_type_DCIRESET.json)
|
||||
* [`e7e73464183458595a02afa7da58537dffd3dcd098c0e96dcce7ec197ac8afa7 ./kintex7/site_type_DNA_PORT.json`](./kintex7/site_type_DNA_PORT.json)
|
||||
* [`0f696a78a57fab8995671dba639ac73d61013f4ec7aa65239662362be50a06ae ./kintex7/site_type_DSP48E1.json`](./kintex7/site_type_DSP48E1.json)
|
||||
* [`ad1f2dc2bc5629fdc3a4308b045d103d76f38612d04c9dc8bde50339575d8d40 ./kintex7/site_type_EFUSE_USR.json`](./kintex7/site_type_EFUSE_USR.json)
|
||||
* [`ae4b06dee05c810b85a6385d605d4bbf65ac169161b6fc3fe0199eb7737169a2 ./kintex7/site_type_FIFO18E1.json`](./kintex7/site_type_FIFO18E1.json)
|
||||
* [`653cd09ce90f58d1e2be7ecc5522f058b30a7ec2b95ed549cf5f053d982a4ef7 ./kintex7/site_type_FRAME_ECC.json`](./kintex7/site_type_FRAME_ECC.json)
|
||||
* [`16b0e88823f0490f8faa0f20cd175e06de645daf15397754c747570626f7737d ./kintex7/site_type_GTXE2_CHANNEL.json`](./kintex7/site_type_GTXE2_CHANNEL.json)
|
||||
* [`e95bb4dcf5840cb482468f1a7d7160e1905a93c7f56a4d07891a671d250986b1 ./kintex7/site_type_GTXE2_COMMON.json`](./kintex7/site_type_GTXE2_COMMON.json)
|
||||
* [`334f26f9d610cf1527cd3debabb454ce0db96130bf263a3efbe7ffddbcc5872c ./kintex7/site_type_IBUFDS_GTE2.json`](./kintex7/site_type_IBUFDS_GTE2.json)
|
||||
* [`de547e93791ca92f8679a8a7d606505ceaa04436f82bdac851035d1836c60f59 ./kintex7/site_type_ICAP.json`](./kintex7/site_type_ICAP.json)
|
||||
* [`a50c2bc260b5359aa96658a7191fa85212b12363b68cfcb6a75230392b35eefb ./kintex7/site_type_IDELAYCTRL.json`](./kintex7/site_type_IDELAYCTRL.json)
|
||||
* [`ac42f477f213fc05f118b8f24c51ed01cbcf1c4dfd7ef3fe71ea3415cc4eb98d ./kintex7/site_type_IDELAYE2_FINEDELAY.json`](./kintex7/site_type_IDELAYE2_FINEDELAY.json)
|
||||
* [`4eafb55d1b61747fd9ef8196454bb0a5df9d0784aeaef7a8e6da67dc1e51668e ./kintex7/site_type_IDELAYE2.json`](./kintex7/site_type_IDELAYE2.json)
|
||||
* [`b572d4069bb6289d79baa673237a86a5e7d28b0efc6122e9505e31476144ca5d ./kintex7/site_type_ILOGICE2.json`](./kintex7/site_type_ILOGICE2.json)
|
||||
* [`97cce70ba181e41b8a0ca9076b470ce49dfefae95f588837d73686f82d4305c8 ./kintex7/site_type_ILOGICE3.json`](./kintex7/site_type_ILOGICE3.json)
|
||||
* [`dbd9354873d1673301b9779a04c23db947c325280fdefc05fec5fec974d25e69 ./kintex7/site_type_IN_FIFO.json`](./kintex7/site_type_IN_FIFO.json)
|
||||
* [`9cd9d19d9805453ff7319c84f7e092e7af999c054cf11eb4f4839015b599dbee ./kintex7/site_type_IOB18.json`](./kintex7/site_type_IOB18.json)
|
||||
* [`126b44af8a35bf0fc2a981bd240169a4ce12371f4db48d71bfafd2fb714a54f5 ./kintex7/site_type_IOB18M.json`](./kintex7/site_type_IOB18M.json)
|
||||
* [`6f850e2eb9ff74e61dc8ee43296ffbba1e195951bba7ab9b195c72bc0c765f20 ./kintex7/site_type_IOB18S.json`](./kintex7/site_type_IOB18S.json)
|
||||
* [`8d88647b1059737d103ec85b97fc2ea4c1acf871c20feacc7df9e3074ed0e54b ./kintex7/site_type_IOB33.json`](./kintex7/site_type_IOB33.json)
|
||||
* [`d4ad99dabcca0c2040f348634e8758f9335f4e4b3f97ff7c53d67a929a5252be ./kintex7/site_type_IOB33M.json`](./kintex7/site_type_IOB33M.json)
|
||||
* [`f875e1ba42bb51dd6ae044223e196c763bd19bfcec40384343a4b6bee5b7cd4f ./kintex7/site_type_IOB33S.json`](./kintex7/site_type_IOB33S.json)
|
||||
* [`6922af5e94c020bf330e088a74c09ad7be09b4264756154dea5769d5631e22bf ./kintex7/site_type_IPAD.json`](./kintex7/site_type_IPAD.json)
|
||||
* [`c6536a1020e7164cd3e596c01526c5e3365a73cdfd9c1a6f2cf3616544eced1d ./kintex7/site_type_MMCME2_ADV.json`](./kintex7/site_type_MMCME2_ADV.json)
|
||||
* [`437ef6ec381eb246a9df43bf6e2e7232a4246bbf87deab3980910b627221e17d ./kintex7/site_type_ODELAYE2.json`](./kintex7/site_type_ODELAYE2.json)
|
||||
* [`b51e1d6cf2e8874843e19afbddda3c8ba4dac5801890c389cb21b474c4c3b19d ./kintex7/site_type_OLOGICE2.json`](./kintex7/site_type_OLOGICE2.json)
|
||||
* [`1567aa8832b40e8706ce45da566f681a101ea3ca581a308f0fc0cea40f8e9c20 ./kintex7/site_type_OLOGICE3.json`](./kintex7/site_type_OLOGICE3.json)
|
||||
* [`26a864898c5fccc0713e6c50cc1d979b85c7f80ef283ad7f4bebc390b272a0a0 ./kintex7/site_type_OPAD.json`](./kintex7/site_type_OPAD.json)
|
||||
* [`83dd093773549002cf7a1c7b0f4a1aa9309006f4954d5d44986aa9a4c0dd070a ./kintex7/site_type_OUT_FIFO.json`](./kintex7/site_type_OUT_FIFO.json)
|
||||
* [`a1e6a8c61bd25f4022d8fcd7516d3d81cdde6985b32fd82104f007460cff04f9 ./kintex7/site_type_PCIE_2_1.json`](./kintex7/site_type_PCIE_2_1.json)
|
||||
* [`aff4c1cecba401965587250c873f7c2a144b6472416ac4623b34dbce6b393aa0 ./kintex7/site_type_PHASER_IN_PHY.json`](./kintex7/site_type_PHASER_IN_PHY.json)
|
||||
* [`1b18d9c78eb215d6e93c994128c1522fd4227c339f000fa3207e02f2a9a78137 ./kintex7/site_type_PHASER_OUT_PHY.json`](./kintex7/site_type_PHASER_OUT_PHY.json)
|
||||
* [`3c74a6c5775b46fedb0f870bd9cfacdba57fe7699d4784e9e485425030675dbf ./kintex7/site_type_PHASER_REF.json`](./kintex7/site_type_PHASER_REF.json)
|
||||
* [`397270675c85b40f5b749c6939fe6209005b6201a26434c743f294ef25d5ca98 ./kintex7/site_type_PHY_CONTROL.json`](./kintex7/site_type_PHY_CONTROL.json)
|
||||
* [`be572d2892f943ab8a69d03924da674b0f64bf61ad69ff7968242743609e21f3 ./kintex7/site_type_PLLE2_ADV.json`](./kintex7/site_type_PLLE2_ADV.json)
|
||||
* [`cabec9a6d1e017ff751a80c2ec10d0b0b76ef014d1ba73f6ea6793e3ec2ff2dc ./kintex7/site_type_PMV2.json`](./kintex7/site_type_PMV2.json)
|
||||
* [`1a869b379e657531322f061b568950595a8fb6030c32f5fea82bfdc19df50120 ./kintex7/site_type_RAMB18E1.json`](./kintex7/site_type_RAMB18E1.json)
|
||||
* [`a9c86c49d3287782468a28f710fa1334fe2c5a69bb8b20cc804caf112e703148 ./kintex7/site_type_RAMBFIFO36E1.json`](./kintex7/site_type_RAMBFIFO36E1.json)
|
||||
* [`51804af3230d43c989f909b2a305c67e1c7cc8bafefda5d912864e1fb74a4d14 ./kintex7/site_type_SLICEL.json`](./kintex7/site_type_SLICEL.json)
|
||||
* [`1ad52d9cf41a20610535e24cd352b7c9cd85e33dd3d0f57580ab56063eb184a5 ./kintex7/site_type_SLICEM.json`](./kintex7/site_type_SLICEM.json)
|
||||
* [`ba727d2d69816bcace78fd39fd3431ff2a4d89ef94c5401380b475bd49f11ca5 ./kintex7/site_type_STARTUP.json`](./kintex7/site_type_STARTUP.json)
|
||||
* [`7329766c3d005888d7c26e2971eede01b5868561ebf3a2fd79418ede9b8eea7e ./kintex7/site_type_TIEOFF.json`](./kintex7/site_type_TIEOFF.json)
|
||||
* [`8630a9324f0e03108cde9c677bd86d0bde54576467691b225e0428948b44d526 ./kintex7/site_type_USR_ACCESS.json`](./kintex7/site_type_USR_ACCESS.json)
|
||||
* [`dfcdd7535d3da5d3e3fd5ab6487490eacbb697d28058d9a59d6d053b56a348f4 ./kintex7/site_type_XADC.json`](./kintex7/site_type_XADC.json)
|
||||
* [`fcc005f080da4cebe34427d6ffdab475fa1e994e06ae865cada7556a33a5caa5 ./kintex7/tileconn.json`](./kintex7/tileconn.json)
|
||||
* [`6a998dd55a7aa4ab33db25db7b5167d57f3d708713baf1fca394dc2940f12007 ./kintex7/site_type_BSCAN.json`](./kintex7/site_type_BSCAN.json)
|
||||
* [`7f59ea08fa5dbf9ce84ea26f03f13cd02683fce9cdd98621e501e422bf09d165 ./kintex7/site_type_BUFGCTRL.json`](./kintex7/site_type_BUFGCTRL.json)
|
||||
* [`2d6c78790d74503f0810356de3a765b380b319f09a41593bc8cbe8979defd1f7 ./kintex7/site_type_BUFHCE.json`](./kintex7/site_type_BUFHCE.json)
|
||||
* [`7d2ad5e0c2a12242cabe03aa9a89bdc1ad4413720c45243809371e06be84a88b ./kintex7/site_type_BUFIO.json`](./kintex7/site_type_BUFIO.json)
|
||||
* [`99ac6ee5e9381bc68e9e7c0ba1e75779a80360b3854b87cc124819a17cd23a75 ./kintex7/site_type_BUFMRCE.json`](./kintex7/site_type_BUFMRCE.json)
|
||||
* [`ea18314ade2d867b7ee931c71ccca7780dcda5da63e4c986a5db37508c8df60a ./kintex7/site_type_BUFR.json`](./kintex7/site_type_BUFR.json)
|
||||
* [`15b8fa9480b7f789bf65aca97263c2b97d120eb3ab79d4330d17e39c36bd0131 ./kintex7/site_type_CAPTURE.json`](./kintex7/site_type_CAPTURE.json)
|
||||
* [`af89e5523c49b0ede53efd5c2304d1e1a5efb553b52ec873526923f2fd019705 ./kintex7/site_type_DCIRESET.json`](./kintex7/site_type_DCIRESET.json)
|
||||
* [`79effefe83be725ab9cf4c1167e6e2582144317654c179b5076ae19f7462403b ./kintex7/site_type_DNA_PORT.json`](./kintex7/site_type_DNA_PORT.json)
|
||||
* [`2326eb345b6c10062379bbb3c7afe5ebc4b9ecbc104f8947158dbae09c09e7c8 ./kintex7/site_type_DSP48E1.json`](./kintex7/site_type_DSP48E1.json)
|
||||
* [`75db786def8e1871ca3fd7c65d6481a53464f000343b32155ee3a05dd86eb0b3 ./kintex7/site_type_EFUSE_USR.json`](./kintex7/site_type_EFUSE_USR.json)
|
||||
* [`a9e6d74302ee507649432e33e31d21d8feaf6b51e2ae0f26a579c16f57f59512 ./kintex7/site_type_FIFO18E1.json`](./kintex7/site_type_FIFO18E1.json)
|
||||
* [`0d1ff1869cb0c2ceb18b7d6e4d53abc15db8712ed4f6845c6ed093e0d28d2fe8 ./kintex7/site_type_FRAME_ECC.json`](./kintex7/site_type_FRAME_ECC.json)
|
||||
* [`05ed1223045527c7e10b5a0d922d083578688f8a0810e875c278ba8d47d66c20 ./kintex7/site_type_GTXE2_CHANNEL.json`](./kintex7/site_type_GTXE2_CHANNEL.json)
|
||||
* [`5737b0e28f7a90325af014732099cbb9f08ede99b3b1000fd5570f71c122bf40 ./kintex7/site_type_GTXE2_COMMON.json`](./kintex7/site_type_GTXE2_COMMON.json)
|
||||
* [`e4b974ca43493be5444c2c2a4a0c243712e882499f8ca87efc38bdca267cc988 ./kintex7/site_type_IBUFDS_GTE2.json`](./kintex7/site_type_IBUFDS_GTE2.json)
|
||||
* [`a2514cd2da5e5cabdc3babd476b014b6b44a2cc8fca19f2f2785cb207abbb751 ./kintex7/site_type_ICAP.json`](./kintex7/site_type_ICAP.json)
|
||||
* [`d23176a42d861807d5bd2559e58f31e3ffe516d3c0597ace669c88f0f8bdd145 ./kintex7/site_type_IDELAYCTRL.json`](./kintex7/site_type_IDELAYCTRL.json)
|
||||
* [`c1a434d73a7f5f724d409b15605b5f50d7f4ac5439a81318615abb2ba54df9bb ./kintex7/site_type_IDELAYE2_FINEDELAY.json`](./kintex7/site_type_IDELAYE2_FINEDELAY.json)
|
||||
* [`2bf5daae4d45e9b6d65fbfa7c73426c896bc071d9b577b57371f8570836acb86 ./kintex7/site_type_IDELAYE2.json`](./kintex7/site_type_IDELAYE2.json)
|
||||
* [`6f75612da1fead215c14b426955b95c43da5a5ecc2186ae44e6ef8b002a39601 ./kintex7/site_type_ILOGICE2.json`](./kintex7/site_type_ILOGICE2.json)
|
||||
* [`05ffeb28332d5d17fc32b2410da41b0b97426a01bb4a3cd84849ab386b50c543 ./kintex7/site_type_ILOGICE3.json`](./kintex7/site_type_ILOGICE3.json)
|
||||
* [`ef48fb9be2319b50b808ead0726bc6a037377fe10fbf3d22ca9acd29def80e2b ./kintex7/site_type_IN_FIFO.json`](./kintex7/site_type_IN_FIFO.json)
|
||||
* [`cb9bf6a49c387a625cbe8afe2d163d934d8252144a4ebcb36ac141d6ee9de378 ./kintex7/site_type_IOB18.json`](./kintex7/site_type_IOB18.json)
|
||||
* [`a724418b2e0edafa67d9d0c0b191e70996208605f776928e48e421ec3a9735b7 ./kintex7/site_type_IOB18M.json`](./kintex7/site_type_IOB18M.json)
|
||||
* [`ed03ec4038f98d25d4ad1239ecc0fb7ab3c1e65ff5f0202dd2ce346f4c951169 ./kintex7/site_type_IOB18S.json`](./kintex7/site_type_IOB18S.json)
|
||||
* [`c98ef8397786c5c71b2c5a43824ce47f0e46c93424eef58ad47bf0f7c7d42675 ./kintex7/site_type_IOB33.json`](./kintex7/site_type_IOB33.json)
|
||||
* [`76e2eb01e49adb5b5d7586d57b5dc07b2104aac9295f173d2b2b3724a86a9eb0 ./kintex7/site_type_IOB33M.json`](./kintex7/site_type_IOB33M.json)
|
||||
* [`ccdec6f60ba548d85b3b24345c0fbc4b5e703c0de936f12c09c5c0fb822fcf3e ./kintex7/site_type_IOB33S.json`](./kintex7/site_type_IOB33S.json)
|
||||
* [`7d0bc5533db085e0ef68a2dbd16906b4936bb35efa4790953c2c4ee607f1ed28 ./kintex7/site_type_IPAD.json`](./kintex7/site_type_IPAD.json)
|
||||
* [`bf073833d9a7b9e125d4829e464cdd67a61bf9195d0dd7854f1fa6397014aacc ./kintex7/site_type_MMCME2_ADV.json`](./kintex7/site_type_MMCME2_ADV.json)
|
||||
* [`0f76338fa2b9ee17a822e82126c9b94afd83145fbae7f28ca40545bb63ae893a ./kintex7/site_type_ODELAYE2.json`](./kintex7/site_type_ODELAYE2.json)
|
||||
* [`0b567e91c282fb210517867640479d683307861470b2e10f39c3300cdf3a6887 ./kintex7/site_type_OLOGICE2.json`](./kintex7/site_type_OLOGICE2.json)
|
||||
* [`186eac82246b8b10da9abab93b15f638bdb8ef446ce0e4b4ceb797e2091132dd ./kintex7/site_type_OLOGICE3.json`](./kintex7/site_type_OLOGICE3.json)
|
||||
* [`b4670a20c46552416276ba8e5442b4c3d24c6215650a212f00f874dc78371bca ./kintex7/site_type_OPAD.json`](./kintex7/site_type_OPAD.json)
|
||||
* [`776619b1507bfe996cfa7b900058cff911bd96a29dac1b33e5b29aa662053aad ./kintex7/site_type_OUT_FIFO.json`](./kintex7/site_type_OUT_FIFO.json)
|
||||
* [`06edd04ea43682f65f2d8cbc6282d5e10385c23e75bd61ddd99c4e6ce2b9fcf6 ./kintex7/site_type_PCIE_2_1.json`](./kintex7/site_type_PCIE_2_1.json)
|
||||
* [`311eda695286ee7edd51cc78c3c6bdbe9901bcb515308a17572302af321fdbc4 ./kintex7/site_type_PHASER_IN_PHY.json`](./kintex7/site_type_PHASER_IN_PHY.json)
|
||||
* [`2474fdfcd0bd228964e62f4875e9684e15984ee57e40b17f6759a5897148cba5 ./kintex7/site_type_PHASER_OUT_PHY.json`](./kintex7/site_type_PHASER_OUT_PHY.json)
|
||||
* [`f8aefb394bd6cef6244a56a4376bf0a44ce368741dfbce8cf7f5df45a71c47a3 ./kintex7/site_type_PHASER_REF.json`](./kintex7/site_type_PHASER_REF.json)
|
||||
* [`01733676f386e217548135ed297b2fa73e0d0d17003b84513708ed8508f447ce ./kintex7/site_type_PHY_CONTROL.json`](./kintex7/site_type_PHY_CONTROL.json)
|
||||
* [`e314d184ac0bbe656ca4d34c33af80149b4d7dbe6798094de089462f78b52405 ./kintex7/site_type_PLLE2_ADV.json`](./kintex7/site_type_PLLE2_ADV.json)
|
||||
* [`58897a08e0442222f117be75393c6b46360933abc71ff1de142ba7adcaabfa3f ./kintex7/site_type_PMV2.json`](./kintex7/site_type_PMV2.json)
|
||||
* [`110126d521d4744019d75f9c0bdcef76851b2c8f003fed0d5dbb7f7806aadae7 ./kintex7/site_type_RAMB18E1.json`](./kintex7/site_type_RAMB18E1.json)
|
||||
* [`1ab295693d283025d16966f5ed48515046fea1078529d48e0eab5eef732bcb40 ./kintex7/site_type_RAMBFIFO36E1.json`](./kintex7/site_type_RAMBFIFO36E1.json)
|
||||
* [`586145c0b465d7ac945746193cf4f38ec5bb26bbc52997bce47d5fbdd9d0c241 ./kintex7/site_type_SLICEL.json`](./kintex7/site_type_SLICEL.json)
|
||||
* [`201ecff6bb7d78c8597d467e55486fc00b2ad95a6a7dee0cd98346ab9e8c888a ./kintex7/site_type_SLICEM.json`](./kintex7/site_type_SLICEM.json)
|
||||
* [`872bc95eb5f912fc95ca2ca18960b14b9cc20f00bf30b7227d0c6c9b0f3bbeb0 ./kintex7/site_type_STARTUP.json`](./kintex7/site_type_STARTUP.json)
|
||||
* [`db8c88384575a7e0562692550bdba7a4089ea5fabe451bf58403d3a85af419a0 ./kintex7/site_type_TIEOFF.json`](./kintex7/site_type_TIEOFF.json)
|
||||
* [`4d6130cb2604efae8ca5d628b95be2549083c16c639d335bdc906924e37ec28c ./kintex7/site_type_USR_ACCESS.json`](./kintex7/site_type_USR_ACCESS.json)
|
||||
* [`dbf0ff3b27d1fac02572351765f1b17b3e950ed4e8fe95ac6bcd71012e4f7b2d ./kintex7/site_type_XADC.json`](./kintex7/site_type_XADC.json)
|
||||
* [`7f9142831f091d653501a1179b597502fa831e744b5392bab6a8bdd8f7827f50 ./kintex7/tileconn.json`](./kintex7/tileconn.json)
|
||||
* [`2ccb101556ecee8ad729fbdd2dcbca296beb0cddc1755f649de3255cbaa51b2f ./kintex7/tilegrid.json`](./kintex7/tilegrid.json)
|
||||
* [`e41553a434c96945d188d8f4c9479b2c8cdcc266aecedcaec808ce3313a90838 ./kintex7/tile_type_BRAM_INT_INTERFACE_L.json`](./kintex7/tile_type_BRAM_INT_INTERFACE_L.json)
|
||||
* [`bcdc2360681535c7bd1059bc7589563ee13658a0054e6e7bdc9e2c666f32c161 ./kintex7/tile_type_BRAM_INT_INTERFACE_R.json`](./kintex7/tile_type_BRAM_INT_INTERFACE_R.json)
|
||||
* [`c02f17fd75d3f9c51cdee987c564623ec7a260a4189b5762fb8ce52ac37403a8 ./kintex7/tile_type_BRAM_L.json`](./kintex7/tile_type_BRAM_L.json)
|
||||
* [`4860e2e56b17e157efdd9a05e8dd8929bb4b302ba610754d6749eb57cd9707d7 ./kintex7/tile_type_BRAM_R.json`](./kintex7/tile_type_BRAM_R.json)
|
||||
* [`a2c7168fac50a80ba1ffd64533b079b2f6c7cf3ebfa506f7dd28c42ad102e605 ./kintex7/tile_type_BRKH_BRAM.json`](./kintex7/tile_type_BRKH_BRAM.json)
|
||||
* [`3147439b966fd3ca65030a80e8cd78de68bfb8493db6adcaddda0dd195edc1d8 ./kintex7/tile_type_BRKH_B_TERM_INT.json`](./kintex7/tile_type_BRKH_B_TERM_INT.json)
|
||||
* [`21f2bf31f07964e8f4d8878ff6ad90f7c956f91c1ffdfa3775f46935e907676e ./kintex7/tile_type_BRKH_CLB.json`](./kintex7/tile_type_BRKH_CLB.json)
|
||||
* [`d1c4672ad9c1bcff94d597847751abb6fbac92584c22598abc08ac7c7af8021b ./kintex7/tile_type_BRKH_CLK.json`](./kintex7/tile_type_BRKH_CLK.json)
|
||||
* [`5578b9e473da648aea8413aee1003f0472dd2826327eb65ec42848ed96735ecc ./kintex7/tile_type_BRKH_CMT.json`](./kintex7/tile_type_BRKH_CMT.json)
|
||||
* [`ea3e20731602dc5096ca43000f46ec5ecfa01aa91d166b2c6503b37530b06ac5 ./kintex7/tile_type_BRKH_DSP_L.json`](./kintex7/tile_type_BRKH_DSP_L.json)
|
||||
* [`8e4dd08bb2ca3fce962e6b34a2133f122a96e5e1ae16c2d969c2078c049687b5 ./kintex7/tile_type_BRKH_DSP_R.json`](./kintex7/tile_type_BRKH_DSP_R.json)
|
||||
* [`4914b83cd7fb2ff11eeaa679fbafcfcc59b5e089e02890b9d99cf703c719a820 ./kintex7/tile_type_BRKH_GTX.json`](./kintex7/tile_type_BRKH_GTX.json)
|
||||
* [`5fe2c1814b8fac0bc28f32205ea620dff25be4dd9754122a0185d1395b354c5f ./kintex7/tile_type_BRKH_INT.json`](./kintex7/tile_type_BRKH_INT.json)
|
||||
* [`3d438a6e8f9a7abaf7ec414d67f786fb9b1fa58cdc91649bef84688c00df85c1 ./kintex7/tile_type_BRKH_TERM_INT.json`](./kintex7/tile_type_BRKH_TERM_INT.json)
|
||||
* [`9ea642a0684cc8102c865e7d6c486a888c88e102dc873f13e7f6d46d47e00047 ./kintex7/tile_type_B_TERM_INT.json`](./kintex7/tile_type_B_TERM_INT.json)
|
||||
* [`0000c209ed73d7f807258ae042ff63c39c259b1239675d19454b3b000ea71ac2 ./kintex7/tile_type_CFG_CENTER_BOT.json`](./kintex7/tile_type_CFG_CENTER_BOT.json)
|
||||
* [`32b33effc6925a1af80e119159f536dd768bdea60336fcad5a8d6d081a2372dc ./kintex7/tile_type_CFG_CENTER_MID.json`](./kintex7/tile_type_CFG_CENTER_MID.json)
|
||||
* [`020ae47321f03311f5897f2c79c569368315a816a42549289d009570a2d76c4a ./kintex7/tile_type_CFG_CENTER_TOP.json`](./kintex7/tile_type_CFG_CENTER_TOP.json)
|
||||
* [`a49fcafa32e32533ded2d3425d1b0b072e841f932747e6169118837bcf2b59d1 ./kintex7/tile_type_CLBLL_L.json`](./kintex7/tile_type_CLBLL_L.json)
|
||||
* [`fadf83bf66fb1597816743f59567e632c494495545e00b0d02aa6207691a85b2 ./kintex7/tile_type_CLBLL_R.json`](./kintex7/tile_type_CLBLL_R.json)
|
||||
* [`063337506d9f67a776b79b480f744830321ff3d5acfdb667d431e1c80a0bb8f9 ./kintex7/tile_type_CLBLM_L.json`](./kintex7/tile_type_CLBLM_L.json)
|
||||
* [`5bc4d0154647a684fc9d29f68ce9df390ed2fcd7ce3fd45592013ec26934fa5f ./kintex7/tile_type_CLBLM_R.json`](./kintex7/tile_type_CLBLM_R.json)
|
||||
* [`bfc9e3df22c7a99e9af69c7110b1c404fe607c84c3dc77b8004273b630e35fb8 ./kintex7/tile_type_CLK_BUFG_BOT_R.json`](./kintex7/tile_type_CLK_BUFG_BOT_R.json)
|
||||
* [`666b6bc037b409912132e3cff9ae3fe752f9f9dc32d8a46fbc63603e8a610bde ./kintex7/tile_type_CLK_BUFG_REBUF.json`](./kintex7/tile_type_CLK_BUFG_REBUF.json)
|
||||
* [`868b04aab06f4d7285980fb76f87ccb1479966667a525858fed1f2c9216e9c9e ./kintex7/tile_type_CLK_BUFG_TOP_R.json`](./kintex7/tile_type_CLK_BUFG_TOP_R.json)
|
||||
* [`9c2af1c0da6184efb136bd14308401459a411c95bdb2ffc1a51c42fed96b6146 ./kintex7/tile_type_CLK_FEED.json`](./kintex7/tile_type_CLK_FEED.json)
|
||||
* [`fa1be3fdfd71f9b1cc10bfd7ddc926801e55fc72632baad0a255e96bada68d0d ./kintex7/tile_type_CLK_HROW_BOT_R.json`](./kintex7/tile_type_CLK_HROW_BOT_R.json)
|
||||
* [`d2ee4dfc7b939cfa99feab874bd23d247e7305c0d303fc068eb6871e987c2c7b ./kintex7/tile_type_CLK_HROW_TOP_R.json`](./kintex7/tile_type_CLK_HROW_TOP_R.json)
|
||||
* [`f7c3840af1472567372deba23095e1c611599c9b8b2b324d724f475ede4a1fd2 ./kintex7/tile_type_CLK_MTBF2.json`](./kintex7/tile_type_CLK_MTBF2.json)
|
||||
* [`27fcefe864e7f7e94ecc0e93562598d4f9893c2781b0898c00d1e248eb57bafb ./kintex7/tile_type_CLK_PMV2.json`](./kintex7/tile_type_CLK_PMV2.json)
|
||||
* [`4c322a13547b7541c6bfacfabd022732f18c2d631155f420b2581d33ef6c4fe8 ./kintex7/tile_type_CLK_PMV2_SVT.json`](./kintex7/tile_type_CLK_PMV2_SVT.json)
|
||||
* [`c6a4ea7ebb2c777757db340988b102cdf40ac41b047122a1f4a78acad6615363 ./kintex7/tile_type_CLK_PMVIOB.json`](./kintex7/tile_type_CLK_PMVIOB.json)
|
||||
* [`0d720ca3564a20b00f765b8434411ed005278d5dac53a2ba9824382dec34f91a ./kintex7/tile_type_CLK_PMV.json`](./kintex7/tile_type_CLK_PMV.json)
|
||||
* [`acbd313bd0e8fa6bc14d913035d9f48c44bdc694b44b80af81003230b6b43bc3 ./kintex7/tile_type_CLK_TERM.json`](./kintex7/tile_type_CLK_TERM.json)
|
||||
* [`7ebaf8de3ac6d90a54f7bba8ad9296f711e495d31faff3d69d7fa5a738536345 ./kintex7/tile_type_CMT_FIFO_L.json`](./kintex7/tile_type_CMT_FIFO_L.json)
|
||||
* [`f5a063540d3cfa2448ad9dbdd159eb1556639bd25c1a1a13e5c4b20bdb3705fb ./kintex7/tile_type_CMT_FIFO_R.json`](./kintex7/tile_type_CMT_FIFO_R.json)
|
||||
* [`eb15ba5757944c16d529084037357a3caf65f261f4b96e2224502d5bbd3ff385 ./kintex7/tile_type_CMT_PMV.json`](./kintex7/tile_type_CMT_PMV.json)
|
||||
* [`40e69910d395ab4490c52cd7164d340979fa75b8bf6038ec6ad632434327d1c4 ./kintex7/tile_type_CMT_PMV_L.json`](./kintex7/tile_type_CMT_PMV_L.json)
|
||||
* [`bf3185ece81d8b23884efb2ec6a679da17503d40dbca626d77a3120fe25b7dc0 ./kintex7/tile_type_CMT_TOP_L_LOWER_B.json`](./kintex7/tile_type_CMT_TOP_L_LOWER_B.json)
|
||||
* [`7c214c04796b00a899239386dbf96a3374526d4f598260a66a17528df2c25490 ./kintex7/tile_type_CMT_TOP_L_LOWER_T.json`](./kintex7/tile_type_CMT_TOP_L_LOWER_T.json)
|
||||
* [`1fecfa3bd69bf4052fd03b8e6befeefffd4497fd8a26304e2203d5015dfdd96e ./kintex7/tile_type_CMT_TOP_L_UPPER_B.json`](./kintex7/tile_type_CMT_TOP_L_UPPER_B.json)
|
||||
* [`71ec5188a2672ca580fde960587162e824910bf5ca442ed0667b04ed8f8ec658 ./kintex7/tile_type_CMT_TOP_L_UPPER_T.json`](./kintex7/tile_type_CMT_TOP_L_UPPER_T.json)
|
||||
* [`290c5b101ab12b3aee3f21ea2e0b49d9c4eb2ba12fe163b67d0325b3f113cede ./kintex7/tile_type_CMT_TOP_R_LOWER_B.json`](./kintex7/tile_type_CMT_TOP_R_LOWER_B.json)
|
||||
* [`df0721000e697f028e7b19885f707083aca76fe9770325c4c3ac21f335ad1213 ./kintex7/tile_type_CMT_TOP_R_LOWER_T.json`](./kintex7/tile_type_CMT_TOP_R_LOWER_T.json)
|
||||
* [`7b04421048a84bb525184a825dafb7434ce34ad5b5aaa25d03682471f07d409a ./kintex7/tile_type_CMT_TOP_R_UPPER_B.json`](./kintex7/tile_type_CMT_TOP_R_UPPER_B.json)
|
||||
* [`81cc5f8cc02f8d03dbcb2099d5a6d6abf6d535923cd5d110bf1a14c5881ac2f7 ./kintex7/tile_type_CMT_TOP_R_UPPER_T.json`](./kintex7/tile_type_CMT_TOP_R_UPPER_T.json)
|
||||
* [`d9b3ed62399b13be64de5189e7073cb4a9bb9d6138c518bd0bdfa117be5f8d25 ./kintex7/tile_type_DSP_L.json`](./kintex7/tile_type_DSP_L.json)
|
||||
* [`c94c9737ea45ca39c9c5f93b0e15f73d5f0ba0a9657e1aa092360c6afbdb502c ./kintex7/tile_type_DSP_R.json`](./kintex7/tile_type_DSP_R.json)
|
||||
* [`143ef93a6d36530005f72fb35c5c6d329a77ee89fda3f9b49a5384a748e33130 ./kintex7/tile_type_GTX_CHANNEL_0.json`](./kintex7/tile_type_GTX_CHANNEL_0.json)
|
||||
* [`635967c5bd4e17f217b04163bc6f093b96258df49bd70f52772a2d6ecfe9f09b ./kintex7/tile_type_GTX_CHANNEL_1.json`](./kintex7/tile_type_GTX_CHANNEL_1.json)
|
||||
* [`dc56bd7a0b202176c881376a25d606a652c6fc2628e14d0e33f04c687a87902e ./kintex7/tile_type_GTX_CHANNEL_2.json`](./kintex7/tile_type_GTX_CHANNEL_2.json)
|
||||
* [`1b3214d207350e3ea4735d1c4d7281c961203de23e6b69c135db4374d36a422f ./kintex7/tile_type_GTX_CHANNEL_3.json`](./kintex7/tile_type_GTX_CHANNEL_3.json)
|
||||
* [`816700f8baad2f8bc5a65149662d274169ff3508512bb60b241f1b744c895ef8 ./kintex7/tile_type_GTX_COMMON.json`](./kintex7/tile_type_GTX_COMMON.json)
|
||||
* [`20a27c3adf87bee51238e3f5855c48e305d370faf3cf221086f2a39a0c6fb601 ./kintex7/tile_type_GTX_INT_INTERFACE.json`](./kintex7/tile_type_GTX_INT_INTERFACE.json)
|
||||
* [`e2f1b81b49be2e71ba2a80ffb217bcbeffffeabefe97b5d09811c4ff4c617e36 ./kintex7/tile_type_HCLK_BRAM.json`](./kintex7/tile_type_HCLK_BRAM.json)
|
||||
* [`64b5e77fffa455fee7ffdf8d4fc0ec0c5770c59cf2c7d3cfdf3352baa70417a1 ./kintex7/tile_type_HCLK_CLB.json`](./kintex7/tile_type_HCLK_CLB.json)
|
||||
* [`c92ea55ecb7c2fb73c1ed2f4b9cd884724001bfdd92de5fc4bf10a2e5abc39e5 ./kintex7/tile_type_HCLK_CMT.json`](./kintex7/tile_type_HCLK_CMT.json)
|
||||
* [`8df99aa03d4e77f5a9acdc5770a1b294f022eb69b838328fc8d367614a8c2daa ./kintex7/tile_type_HCLK_CMT_L.json`](./kintex7/tile_type_HCLK_CMT_L.json)
|
||||
* [`f41d0d6065a4c247c9742a7f564f062a18582e8c928ec9d9140648b99503d92e ./kintex7/tile_type_HCLK_DSP_L.json`](./kintex7/tile_type_HCLK_DSP_L.json)
|
||||
* [`c923a360ae2c99bb443282431b03ba8b8fba68d05b82a0ff797b716f34bfc251 ./kintex7/tile_type_HCLK_DSP_R.json`](./kintex7/tile_type_HCLK_DSP_R.json)
|
||||
* [`dde046196e4a4d4da476226fd9667483f82d39cef00bf9dc38cef5f17ab1c914 ./kintex7/tile_type_HCLK_FEEDTHRU_1.json`](./kintex7/tile_type_HCLK_FEEDTHRU_1.json)
|
||||
* [`9bbb0a7d24a5d02ad01c0e39039130ccc909e879abc349a92f597cbe469dd49d ./kintex7/tile_type_HCLK_FEEDTHRU_2.json`](./kintex7/tile_type_HCLK_FEEDTHRU_2.json)
|
||||
* [`84c757904074b41d7c14fbbba37ce47a9f72f998e9e623eb206d15d5b78d1d41 ./kintex7/tile_type_HCLK_FIFO_L.json`](./kintex7/tile_type_HCLK_FIFO_L.json)
|
||||
* [`8425afb4d0a2d98e1dfd1d26393aa80a74e51f56d1e9aef8935a7970f04bf14d ./kintex7/tile_type_HCLK_GTX.json`](./kintex7/tile_type_HCLK_GTX.json)
|
||||
* [`81407bfaf8f2526850bd6d4e715895af022f0408c91484608b8381fc12393df2 ./kintex7/tile_type_HCLK_INT_INTERFACE.json`](./kintex7/tile_type_HCLK_INT_INTERFACE.json)
|
||||
* [`4c1f24d434ce7b48dae3d9b4d06bd64af7e1e5837d0dc0bc792d42e76bf113cb ./kintex7/tile_type_HCLK_IOB.json`](./kintex7/tile_type_HCLK_IOB.json)
|
||||
* [`76260e86d5ecdd6b1f114ffe05ac2a959afcaca4be25635c2d4ecf3f76ff6986 ./kintex7/tile_type_HCLK_IOI3.json`](./kintex7/tile_type_HCLK_IOI3.json)
|
||||
* [`d39f1659520b0538d275a30d56a24eb176174e10f43fd8817363cc26ddca1f0c ./kintex7/tile_type_HCLK_IOI.json`](./kintex7/tile_type_HCLK_IOI.json)
|
||||
* [`34f7588770dde88264dfa413b3a56d724001efcf8a70b696a44ac87810150ec6 ./kintex7/tile_type_HCLK_L_BOT_UTURN.json`](./kintex7/tile_type_HCLK_L_BOT_UTURN.json)
|
||||
* [`574450912455e0c9088b68833d6e535b8868f34deee4c25387301b1de9296a00 ./kintex7/tile_type_HCLK_L.json`](./kintex7/tile_type_HCLK_L.json)
|
||||
* [`037972ef07a8be72225783db245097c0037b4fd4a42c3551b60114b65968973a ./kintex7/tile_type_HCLK_R_BOT_UTURN.json`](./kintex7/tile_type_HCLK_R_BOT_UTURN.json)
|
||||
* [`064f051fd195837ec3dd8560bb555be5ce1b66bd8eec94e8b709e365a1fcc2d5 ./kintex7/tile_type_HCLK_R.json`](./kintex7/tile_type_HCLK_R.json)
|
||||
* [`52aff0ffab55a41d78b9a276dee0b9decc97022c020c74c5a96ad3d92bed5863 ./kintex7/tile_type_HCLK_TERM_GTX.json`](./kintex7/tile_type_HCLK_TERM_GTX.json)
|
||||
* [`eb62ef0efc2a718ccf84321087ad832ab0467b3203d680adc701179fadc91bf6 ./kintex7/tile_type_HCLK_TERM.json`](./kintex7/tile_type_HCLK_TERM.json)
|
||||
* [`220b12b284dddb2c238552b0218797d0ba3457ed18175ab70cef8415f0c0201a ./kintex7/tile_type_HCLK_VBRK.json`](./kintex7/tile_type_HCLK_VBRK.json)
|
||||
* [`46330a09e75de3b349d69a0083b9304822f7fbf8ae1a5fb763da4784973dd240 ./kintex7/tile_type_HCLK_VFRAME.json`](./kintex7/tile_type_HCLK_VFRAME.json)
|
||||
* [`7f09e309e6653af7118d7fc931fe31b246b7cc8531923861496eedf3dc77b5be ./kintex7/tile_type_INT_FEEDTHRU_1.json`](./kintex7/tile_type_INT_FEEDTHRU_1.json)
|
||||
* [`28b7ecc94f160d54bc79368c562fe4df0e843509e5434771ed8f6b55f18b6bf4 ./kintex7/tile_type_INT_FEEDTHRU_2.json`](./kintex7/tile_type_INT_FEEDTHRU_2.json)
|
||||
* [`6aa23f8918efc454795ab7822e52e3999edb1c198eddd8e6aa0c2f653d40d1e4 ./kintex7/tile_type_INT_INTERFACE_L.json`](./kintex7/tile_type_INT_INTERFACE_L.json)
|
||||
* [`0b317673faf61ae014f66ceb9db46191c8e4f3c8b0a14cc017982ef283e4395e ./kintex7/tile_type_INT_INTERFACE_R.json`](./kintex7/tile_type_INT_INTERFACE_R.json)
|
||||
* [`26700b39a04bd369ee5563ca9e84ac01f87895c05da73e0ce6046336cc8852ce ./kintex7/tile_type_INT_L.json`](./kintex7/tile_type_INT_L.json)
|
||||
* [`2e37a5d868bd73ddc1a7d1ecf90df3e8710e6bbbb9f972c14129116326a6b4e4 ./kintex7/tile_type_INT_R.json`](./kintex7/tile_type_INT_R.json)
|
||||
* [`aa66ce19f9ad6b965241375bfb47bd89e2a1348a58c968368e86281931b44590 ./kintex7/tile_type_IO_INT_INTERFACE_L.json`](./kintex7/tile_type_IO_INT_INTERFACE_L.json)
|
||||
* [`0b1638c1d020419c7cd893f6f0777fe7e9b31f59cd3df806a04a1d8a75236ca4 ./kintex7/tile_type_IO_INT_INTERFACE_R.json`](./kintex7/tile_type_IO_INT_INTERFACE_R.json)
|
||||
* [`834aeafff58ab00c55362bcb5b8f57a0c4eba75bed850857396f451005de25b7 ./kintex7/tile_type_LIOB33.json`](./kintex7/tile_type_LIOB33.json)
|
||||
* [`1cd4802b53f8b51ebda08cb505216bd2359ebe8a25b9b25f0a47009e7bd50a0e ./kintex7/tile_type_LIOB33_SING.json`](./kintex7/tile_type_LIOB33_SING.json)
|
||||
* [`197d350086961d53460b275c6d38f58dff6b9ddc4022498c1ba7462e975167b6 ./kintex7/tile_type_LIOI3.json`](./kintex7/tile_type_LIOI3.json)
|
||||
* [`fcee806a19995fefb66d1abf203cabe4551ca5a1555b74438ddb9ebde743a3b7 ./kintex7/tile_type_LIOI3_SING.json`](./kintex7/tile_type_LIOI3_SING.json)
|
||||
* [`72d291224c4e6a7c875a3985731909c51c7e912670215ce3102129b879d4237d ./kintex7/tile_type_LIOI3_TBYTESRC.json`](./kintex7/tile_type_LIOI3_TBYTESRC.json)
|
||||
* [`afb7e0c93c96a5f1390d9ea8a7a1427f13a523949ccc3cfb4e73c8a95ecdecf8 ./kintex7/tile_type_LIOI3_TBYTETERM.json`](./kintex7/tile_type_LIOI3_TBYTETERM.json)
|
||||
* [`916025d46555f5911087f1f062d9af1fb5f8fc69df39cc5d230d448098ff32e6 ./kintex7/tile_type_L_TERM_INT.json`](./kintex7/tile_type_L_TERM_INT.json)
|
||||
* [`76c1cd952c48be9fc23f284bccaef7fc45589ec023aee73266984877c034d8f7 ./kintex7/tile_type_MONITOR_BOT_FUJI2.json`](./kintex7/tile_type_MONITOR_BOT_FUJI2.json)
|
||||
* [`6ba81b6b8cc26d484121a92431e780fb60a4fcf3fc5fb87c057281a671b01536 ./kintex7/tile_type_MONITOR_MID_FUJI2.json`](./kintex7/tile_type_MONITOR_MID_FUJI2.json)
|
||||
* [`86b81044a371a36deeb7c2ba96f2ae7c109a2a81dede577d887e32b129c5f18a ./kintex7/tile_type_MONITOR_TOP_FUJI2.json`](./kintex7/tile_type_MONITOR_TOP_FUJI2.json)
|
||||
* [`5d1de70987a005e1b8b2fa0589cd53a201e1f2c9836921e6040a000b9484a228 ./kintex7/tile_type_NULL.json`](./kintex7/tile_type_NULL.json)
|
||||
* [`1ecb8c465ca2a8586c69e79c3d8ec072b9c2c875df10bd1de4decb8bc92f9d55 ./kintex7/tile_type_PCIE_BOT.json`](./kintex7/tile_type_PCIE_BOT.json)
|
||||
* [`aa7b93e6c781119b8d5f87a10fc48ebaa73a4eead078e93132b7ddaa33dc88c3 ./kintex7/tile_type_PCIE_INT_INTERFACE_L.json`](./kintex7/tile_type_PCIE_INT_INTERFACE_L.json)
|
||||
* [`0ec7eb6ac887ffd60a1cce398c2b221bcbfb0fc7b4cdff1127beecc48197e3a7 ./kintex7/tile_type_PCIE_INT_INTERFACE_R.json`](./kintex7/tile_type_PCIE_INT_INTERFACE_R.json)
|
||||
* [`f8abe2a7f48b0b15d56403fe33643420508dfb0b864fb2dd1318705bae67eeb0 ./kintex7/tile_type_PCIE_NULL.json`](./kintex7/tile_type_PCIE_NULL.json)
|
||||
* [`0f42ceb80f80cdead3214dd5082582573d861183720c3f68aa9efe6510c81252 ./kintex7/tile_type_PCIE_TOP.json`](./kintex7/tile_type_PCIE_TOP.json)
|
||||
* [`e7ba0a1160e8ca8a9a99ca17b5c624dc75858ae448adb1ff1e1dadd90d9cd602 ./kintex7/tile_type_RIOB18.json`](./kintex7/tile_type_RIOB18.json)
|
||||
* [`e3e6fcf61bcdee2fd8b46d6e9669b4c73feb8f19e6796762f9ccbad14e5448fe ./kintex7/tile_type_RIOB18_SING.json`](./kintex7/tile_type_RIOB18_SING.json)
|
||||
* [`41e9510b0f26afe800182bbd33f9bd595c62da90e5240513ba45acae935e15b2 ./kintex7/tile_type_RIOI.json`](./kintex7/tile_type_RIOI.json)
|
||||
* [`f49c630e38cdae7604634429d94f3f366fdaa7633d8839db2ce981c88aa42f53 ./kintex7/tile_type_RIOI_SING.json`](./kintex7/tile_type_RIOI_SING.json)
|
||||
* [`f9f803ced00d2affd7f15055757ff71010f336622c023ba96d55afdb1e93df2e ./kintex7/tile_type_RIOI_TBYTESRC.json`](./kintex7/tile_type_RIOI_TBYTESRC.json)
|
||||
* [`b451e9504276aa50b8ab30db52de2b0c90e539d93565e0fa2fd1286c9fe9701c ./kintex7/tile_type_RIOI_TBYTETERM.json`](./kintex7/tile_type_RIOI_TBYTETERM.json)
|
||||
* [`8b67fcc25ba2c2a2fc6e40e02b9c937a2f24a15cf341b76f185505e3de8b1f30 ./kintex7/tile_type_R_TERM_INT_GTX.json`](./kintex7/tile_type_R_TERM_INT_GTX.json)
|
||||
* [`e4fb30a3dbc933eb7329ae159d273d3c1812db2cc687a96ff9593723978b3aa8 ./kintex7/tile_type_R_TERM_INT.json`](./kintex7/tile_type_R_TERM_INT.json)
|
||||
* [`f9376a728ef3da4da5cabdc092004a3147ad5ef4f23fb35b123c808ca8cf70c4 ./kintex7/tile_type_TERM_CMT.json`](./kintex7/tile_type_TERM_CMT.json)
|
||||
* [`05c16b5d98372ae3c77cdd752aaf56fa2eb9f935a976c93cbc1228e5e2c79f22 ./kintex7/tile_type_T_TERM_INT.json`](./kintex7/tile_type_T_TERM_INT.json)
|
||||
* [`3c16819ae98be7cb228351b295b569dd44f9783f76dd986c230c9627b2051479 ./kintex7/tile_type_VBRK_EXT.json`](./kintex7/tile_type_VBRK_EXT.json)
|
||||
* [`b1df8c22d9d53b06c1e99cef0671c426c5b6b07af2a829b5a6ba4d135b4190d7 ./kintex7/tile_type_VBRK.json`](./kintex7/tile_type_VBRK.json)
|
||||
* [`29958122ee0af5d22e10da2fca1ebd680c7aeda1f600ebeeab71d350de8c4a55 ./kintex7/tile_type_VFRAME.json`](./kintex7/tile_type_VFRAME.json)
|
||||
* [`a93b4be2b2832d1a9240b892f6d8db469f3d9cf6229cc6856a197e854f4abc8a ./kintex7/tile_type_BRAM_INT_INTERFACE_L.json`](./kintex7/tile_type_BRAM_INT_INTERFACE_L.json)
|
||||
* [`fff3e640e286158767fc484ec932d0ce7eba48c1168798c11c7779426a846004 ./kintex7/tile_type_BRAM_INT_INTERFACE_R.json`](./kintex7/tile_type_BRAM_INT_INTERFACE_R.json)
|
||||
* [`fe1ba3b913bc91940d08dc034ef0c5ad7d530d15b5458c7240abedb4400c52ad ./kintex7/tile_type_BRAM_L.json`](./kintex7/tile_type_BRAM_L.json)
|
||||
* [`0b3e0084e0ee328d9fc74180b3f10468d575ada3850117de77d6789bde11c3fa ./kintex7/tile_type_BRAM_R.json`](./kintex7/tile_type_BRAM_R.json)
|
||||
* [`db6c15155f364bd395363fb230bf43119a0081e41d659b0afb01dc5144da723a ./kintex7/tile_type_BRKH_BRAM.json`](./kintex7/tile_type_BRKH_BRAM.json)
|
||||
* [`9d3a3030a2e3b2cf1ac5325613d6f97121d92520573f5623f4bca7cc1f93f488 ./kintex7/tile_type_BRKH_B_TERM_INT.json`](./kintex7/tile_type_BRKH_B_TERM_INT.json)
|
||||
* [`118df8447c839ff5b9e2325e328c0251d67f9bf5db209b7f2782f9235f240311 ./kintex7/tile_type_BRKH_CLB.json`](./kintex7/tile_type_BRKH_CLB.json)
|
||||
* [`0d3e86aab90d3bb52dd77b187695d3cb3777e46336d1fc1725b6329b8902b626 ./kintex7/tile_type_BRKH_CLK.json`](./kintex7/tile_type_BRKH_CLK.json)
|
||||
* [`7679aeafb655e2bd58deddc3ab9746ee00e801e4f6b3cd93e17d66f211beb288 ./kintex7/tile_type_BRKH_CMT.json`](./kintex7/tile_type_BRKH_CMT.json)
|
||||
* [`5c19ea98b80ca36a2a91388352ebd37bba5b85e2580a5cb10ef1b9a31b26a009 ./kintex7/tile_type_BRKH_DSP_L.json`](./kintex7/tile_type_BRKH_DSP_L.json)
|
||||
* [`15db89f4dc5243d4e315e8130937270919397031ec30ec764fde6400f9b5d651 ./kintex7/tile_type_BRKH_DSP_R.json`](./kintex7/tile_type_BRKH_DSP_R.json)
|
||||
* [`856754623cc87f0058d073999e25faab904f7edef7beb0a818e60ab853fa5b97 ./kintex7/tile_type_BRKH_GTX.json`](./kintex7/tile_type_BRKH_GTX.json)
|
||||
* [`f2e45380bacb76cfb51982ce6e561a9af21d8df0e51bbf0d1ab946e0372739e1 ./kintex7/tile_type_BRKH_INT.json`](./kintex7/tile_type_BRKH_INT.json)
|
||||
* [`f03132d07804f511371569891bf51d6c14490ee9460f57728e179ee2a7be4cdc ./kintex7/tile_type_BRKH_TERM_INT.json`](./kintex7/tile_type_BRKH_TERM_INT.json)
|
||||
* [`3c0cc073cc1c80424074ca96a1a87099e040512d279c313109b96146adf94c8e ./kintex7/tile_type_B_TERM_INT.json`](./kintex7/tile_type_B_TERM_INT.json)
|
||||
* [`b4cf053f06f3965af2f05b74e43eff6bdf24daf8ee2cb61ddeeee70e71ed660d ./kintex7/tile_type_CFG_CENTER_BOT.json`](./kintex7/tile_type_CFG_CENTER_BOT.json)
|
||||
* [`82468ad16be6809588902afecfb06ec15ec7408b6cd1e3b99fe14430a62e11a2 ./kintex7/tile_type_CFG_CENTER_MID.json`](./kintex7/tile_type_CFG_CENTER_MID.json)
|
||||
* [`413970a4868c43567623a14b4093be69899de10ebba2f62fd06137660b35b6dc ./kintex7/tile_type_CFG_CENTER_TOP.json`](./kintex7/tile_type_CFG_CENTER_TOP.json)
|
||||
* [`51e08a3158bfddccb5c43b0dc7ff6f55fe303df871795fdd921b8963e619e95c ./kintex7/tile_type_CLBLL_L.json`](./kintex7/tile_type_CLBLL_L.json)
|
||||
* [`9b2e66795a517636d5af80c81ec7ac1c8189a553648a9b2d767c5ec3e9819508 ./kintex7/tile_type_CLBLL_R.json`](./kintex7/tile_type_CLBLL_R.json)
|
||||
* [`0b0e0bb74eb6b8864a94663ec9adb7f14f29ebdffafb3088bbf794b51935a322 ./kintex7/tile_type_CLBLM_L.json`](./kintex7/tile_type_CLBLM_L.json)
|
||||
* [`ec924ac530dbd8592880606da2244a55d19c05a14357ab8032aecc7ef2eb0fa9 ./kintex7/tile_type_CLBLM_R.json`](./kintex7/tile_type_CLBLM_R.json)
|
||||
* [`656de9ce6a18a058c083d07bae3433fde5899680ac68165e9e8430023c2f123c ./kintex7/tile_type_CLK_BUFG_BOT_R.json`](./kintex7/tile_type_CLK_BUFG_BOT_R.json)
|
||||
* [`6aa792786a1fbb38c20f1aceba3936775473d8dff5529f7aa41e8da38eee4c0c ./kintex7/tile_type_CLK_BUFG_REBUF.json`](./kintex7/tile_type_CLK_BUFG_REBUF.json)
|
||||
* [`c478ac96f632d69db13f870eab1d86a84b3e47af5a2b4b6b93c3c71b3d75e87e ./kintex7/tile_type_CLK_BUFG_TOP_R.json`](./kintex7/tile_type_CLK_BUFG_TOP_R.json)
|
||||
* [`d6df6130236178fdfecd77e7ab871dd7f5f5d91270aff446bbc6082b5d611f50 ./kintex7/tile_type_CLK_FEED.json`](./kintex7/tile_type_CLK_FEED.json)
|
||||
* [`1a9f04a7268c7db635363e4c6d5885b3979cf9d7d3c67a202b3ac3af5c124122 ./kintex7/tile_type_CLK_HROW_BOT_R.json`](./kintex7/tile_type_CLK_HROW_BOT_R.json)
|
||||
* [`b0b961602f0f9fdb17e2ca7566ef85543f0734b7e4e9822d4e5ce3763def1bdc ./kintex7/tile_type_CLK_HROW_TOP_R.json`](./kintex7/tile_type_CLK_HROW_TOP_R.json)
|
||||
* [`54365a8bfc347ca228266b6a682e0ccb1a5c98283c90efc3b738b962134d62ba ./kintex7/tile_type_CLK_MTBF2.json`](./kintex7/tile_type_CLK_MTBF2.json)
|
||||
* [`60f5de137907091563bc64aadc4caab115d6527c31525c6ede9148b4f9b5f3d9 ./kintex7/tile_type_CLK_PMV2.json`](./kintex7/tile_type_CLK_PMV2.json)
|
||||
* [`392df005504cbc65b160a7eacf01d885617b0c2869269ba5de7b490c069993fe ./kintex7/tile_type_CLK_PMV2_SVT.json`](./kintex7/tile_type_CLK_PMV2_SVT.json)
|
||||
* [`aeb291f8b0d6e930b1a9dfeddf444f78cf7b8a3e1b4bfd68695a610b4a56df15 ./kintex7/tile_type_CLK_PMVIOB.json`](./kintex7/tile_type_CLK_PMVIOB.json)
|
||||
* [`2cf3b04cc58a0d9c9655d8a002ad789f15cc0da42ce797d616501af10ceaf3e5 ./kintex7/tile_type_CLK_PMV.json`](./kintex7/tile_type_CLK_PMV.json)
|
||||
* [`3049d7d2fd6c902737f1a17661eea9fd8e195e7623e602737e5573bc226b659e ./kintex7/tile_type_CLK_TERM.json`](./kintex7/tile_type_CLK_TERM.json)
|
||||
* [`f34c8817cd592fbd84bf5320aa2afe886e400219227e23106ab20bb14bf6b0e9 ./kintex7/tile_type_CMT_FIFO_L.json`](./kintex7/tile_type_CMT_FIFO_L.json)
|
||||
* [`3f5c5c44013567f9162fecd20bc76a888f5426f363445c83a90e7765e7ac5328 ./kintex7/tile_type_CMT_FIFO_R.json`](./kintex7/tile_type_CMT_FIFO_R.json)
|
||||
* [`ee092eb4fe6b8acdd0e145c57e0555390668dfe0b4fb4ecf72f1104a1f464380 ./kintex7/tile_type_CMT_PMV.json`](./kintex7/tile_type_CMT_PMV.json)
|
||||
* [`f14e9d7dc485f0f7feba84cbc2824d2f6f49f78db009feaef3425a4bf818454a ./kintex7/tile_type_CMT_PMV_L.json`](./kintex7/tile_type_CMT_PMV_L.json)
|
||||
* [`e7931a0f222780de2736402376667bfa06deaf5631af6e3ae7ecdc04ef4cf0e9 ./kintex7/tile_type_CMT_TOP_L_LOWER_B.json`](./kintex7/tile_type_CMT_TOP_L_LOWER_B.json)
|
||||
* [`a6e0cf15801f96b7dbb09beb5c50d0468a971b615707990c9dc6f9b2606b9fcf ./kintex7/tile_type_CMT_TOP_L_LOWER_T.json`](./kintex7/tile_type_CMT_TOP_L_LOWER_T.json)
|
||||
* [`be837955af15b1b057d389f90db066e7364a4aabc63174797157028d950a0736 ./kintex7/tile_type_CMT_TOP_L_UPPER_B.json`](./kintex7/tile_type_CMT_TOP_L_UPPER_B.json)
|
||||
* [`601852861f50e91ec1398eeb464500f8364fea828630ce02e5feb3c2754eab1e ./kintex7/tile_type_CMT_TOP_L_UPPER_T.json`](./kintex7/tile_type_CMT_TOP_L_UPPER_T.json)
|
||||
* [`41f0cdfdfe2a777484296d12f667fe87051c918264be5548cf1e8f8c0a82d6fa ./kintex7/tile_type_CMT_TOP_R_LOWER_B.json`](./kintex7/tile_type_CMT_TOP_R_LOWER_B.json)
|
||||
* [`769bdd34e337f36851ea020d58e56fd4e3b574b82e64b165c9f9e97c3e7a1619 ./kintex7/tile_type_CMT_TOP_R_LOWER_T.json`](./kintex7/tile_type_CMT_TOP_R_LOWER_T.json)
|
||||
* [`fabeef8ceadc3b73a5130c62a4ec27196d86bea851d9e4b65fab4a5c869ddfbb ./kintex7/tile_type_CMT_TOP_R_UPPER_B.json`](./kintex7/tile_type_CMT_TOP_R_UPPER_B.json)
|
||||
* [`e91fbf80b93b718cf155474a3aa109323562c24e436fcd0d1ecfd49dae334c85 ./kintex7/tile_type_CMT_TOP_R_UPPER_T.json`](./kintex7/tile_type_CMT_TOP_R_UPPER_T.json)
|
||||
* [`03a09a31d4f5cbacfcbc57cc3d7d02cb2cc1ff385fed3dce09e13656dbe78156 ./kintex7/tile_type_DSP_L.json`](./kintex7/tile_type_DSP_L.json)
|
||||
* [`6a81b824a37477aa4aa885f05e03c730da5bce3175a693cea55e1c9ca3ad18d4 ./kintex7/tile_type_DSP_R.json`](./kintex7/tile_type_DSP_R.json)
|
||||
* [`d04fd948a2dc32da998526ede6ccac34e621bf8e36bcc31169c33044b2d9b0d9 ./kintex7/tile_type_GTX_CHANNEL_0.json`](./kintex7/tile_type_GTX_CHANNEL_0.json)
|
||||
* [`b91cd38187c42ff361ea0800a164f450b5ea391b6eccbfef40a49f279d63671c ./kintex7/tile_type_GTX_CHANNEL_1.json`](./kintex7/tile_type_GTX_CHANNEL_1.json)
|
||||
* [`12e3a21b5755c12735f8de94a8d7b1007bdefff3d88e673a02987aa7cde40e5c ./kintex7/tile_type_GTX_CHANNEL_2.json`](./kintex7/tile_type_GTX_CHANNEL_2.json)
|
||||
* [`e64e65fce02864e351975dffc0847c58dc6699cac2c7a883c6373eaf4cf30933 ./kintex7/tile_type_GTX_CHANNEL_3.json`](./kintex7/tile_type_GTX_CHANNEL_3.json)
|
||||
* [`8a473573c5ec94768f3755b8f88a59de13e9af8fffcc6107d7515f38f6640aa0 ./kintex7/tile_type_GTX_COMMON.json`](./kintex7/tile_type_GTX_COMMON.json)
|
||||
* [`cc2506b94140f6190f373e1e6f0c46793545b6a43a74f8b5a2a1a7ada4c9ec0e ./kintex7/tile_type_GTX_INT_INTERFACE.json`](./kintex7/tile_type_GTX_INT_INTERFACE.json)
|
||||
* [`354ef04f0bdda1de5dcdcd33f5755a1d23ed12736f9130cf7be4b1177331ac42 ./kintex7/tile_type_HCLK_BRAM.json`](./kintex7/tile_type_HCLK_BRAM.json)
|
||||
* [`df7c1fe5e634ef598e274709c416a89cbb7a466467ba8bb7aa2a06c92271f2ef ./kintex7/tile_type_HCLK_CLB.json`](./kintex7/tile_type_HCLK_CLB.json)
|
||||
* [`28bf8be9e5b51f2125c8af8a9e4645494bc09265f212a19762dca8731934dd29 ./kintex7/tile_type_HCLK_CMT.json`](./kintex7/tile_type_HCLK_CMT.json)
|
||||
* [`1a3eaf022b48825d6054418bf8c6eb9813fdfde0ed316d9ce2195559bb2c9b75 ./kintex7/tile_type_HCLK_CMT_L.json`](./kintex7/tile_type_HCLK_CMT_L.json)
|
||||
* [`ba1573347a1e8aaf273177dd9a47ae0cbb460031944c4e9207aaeec06e6d6f3d ./kintex7/tile_type_HCLK_DSP_L.json`](./kintex7/tile_type_HCLK_DSP_L.json)
|
||||
* [`1558e3a24f99161db174a0000aa7bf463ea2f658fdc0d5de95857c63e4781e76 ./kintex7/tile_type_HCLK_DSP_R.json`](./kintex7/tile_type_HCLK_DSP_R.json)
|
||||
* [`981440f3c25fe99c89e59397d1f53ae2ea0ede7bf3b31ccd455a3f37cc1aa7df ./kintex7/tile_type_HCLK_FEEDTHRU_1.json`](./kintex7/tile_type_HCLK_FEEDTHRU_1.json)
|
||||
* [`3114e5e086d22c789be17eab304f8cdc111c6a16815206ecabe587b47821d189 ./kintex7/tile_type_HCLK_FEEDTHRU_2.json`](./kintex7/tile_type_HCLK_FEEDTHRU_2.json)
|
||||
* [`b41e34860cc61a3ddfe4237aca23aa6f076c91c8419e432bad2b8808a0e2f066 ./kintex7/tile_type_HCLK_FIFO_L.json`](./kintex7/tile_type_HCLK_FIFO_L.json)
|
||||
* [`7ab3f91abd87e8fc978a8c565578f62a62ca9f9f3a0f91ca5fc1f12eee48e24d ./kintex7/tile_type_HCLK_GTX.json`](./kintex7/tile_type_HCLK_GTX.json)
|
||||
* [`e9b15f998078da307163484c613e6428527269203566108aced10b9d10b5330c ./kintex7/tile_type_HCLK_INT_INTERFACE.json`](./kintex7/tile_type_HCLK_INT_INTERFACE.json)
|
||||
* [`89ccb8895863d40efc4a2d2af8df687a12ddd32b77b81ace67263b1118a3597d ./kintex7/tile_type_HCLK_IOB.json`](./kintex7/tile_type_HCLK_IOB.json)
|
||||
* [`6ea4fc281d2c2a2becc5ae9ac19a59b19d491bab36a16397e58327fae820350b ./kintex7/tile_type_HCLK_IOI3.json`](./kintex7/tile_type_HCLK_IOI3.json)
|
||||
* [`04ea9ae2d99f532b1146ff7e3246c4b77d43b03ea82d52d9fb58931da2355601 ./kintex7/tile_type_HCLK_IOI.json`](./kintex7/tile_type_HCLK_IOI.json)
|
||||
* [`06bf665ee2c3cedd70c74dc2a62681b5f1bb3b3068672389fafd11c6eef95b2e ./kintex7/tile_type_HCLK_L_BOT_UTURN.json`](./kintex7/tile_type_HCLK_L_BOT_UTURN.json)
|
||||
* [`416fcad956b2082d8a17e57190f1470171f134397a4cdb23beccc35edcd58c50 ./kintex7/tile_type_HCLK_L.json`](./kintex7/tile_type_HCLK_L.json)
|
||||
* [`fa5fe9cf004090046dc5a6829410efb4379a9670f0fdd01e7bb8a8c1bb01bff0 ./kintex7/tile_type_HCLK_R_BOT_UTURN.json`](./kintex7/tile_type_HCLK_R_BOT_UTURN.json)
|
||||
* [`750bdec4a5452c3d177995e0ed1405aca81a1a2b1998fb244fcfe0c266bdf0ee ./kintex7/tile_type_HCLK_R.json`](./kintex7/tile_type_HCLK_R.json)
|
||||
* [`b371b59e75bb9b18ba85b6ad43eaae3defe411a77c383c2c65780d8763c90f98 ./kintex7/tile_type_HCLK_TERM_GTX.json`](./kintex7/tile_type_HCLK_TERM_GTX.json)
|
||||
* [`3713a04488775af071b9488eb191415e084b3c17e9a03ab38e514b61d822172e ./kintex7/tile_type_HCLK_TERM.json`](./kintex7/tile_type_HCLK_TERM.json)
|
||||
* [`29f2633c9d8109d756ca8bafb3537d8bbfebb7f4999a25d41ed7176b9f2e8258 ./kintex7/tile_type_HCLK_VBRK.json`](./kintex7/tile_type_HCLK_VBRK.json)
|
||||
* [`5c818e93dedf3f75062bca58782ac334a9c25bece6406766fb72c329ba7f67b7 ./kintex7/tile_type_HCLK_VFRAME.json`](./kintex7/tile_type_HCLK_VFRAME.json)
|
||||
* [`fa8e254275184672267a3b7fcaf21aed716c77467ab487bb4bcc6e32f0c102f3 ./kintex7/tile_type_INT_FEEDTHRU_1.json`](./kintex7/tile_type_INT_FEEDTHRU_1.json)
|
||||
* [`fc80af4e87d86b5b5554e1b44546440bfab85bc4ae1557ceed06d8209d098f38 ./kintex7/tile_type_INT_FEEDTHRU_2.json`](./kintex7/tile_type_INT_FEEDTHRU_2.json)
|
||||
* [`2f388adb0b97739b0292e3aefb249346e48916d4c02816d2dd477ca66baaca38 ./kintex7/tile_type_INT_INTERFACE_L.json`](./kintex7/tile_type_INT_INTERFACE_L.json)
|
||||
* [`9b5d722203552f898fb7ec3cee58904f61bebaae1501d5adbc6fbbd670634d67 ./kintex7/tile_type_INT_INTERFACE_R.json`](./kintex7/tile_type_INT_INTERFACE_R.json)
|
||||
* [`acb01192a3328a1071cfb9ee54c16107d164a6249068a25dfa731fd933f10be6 ./kintex7/tile_type_INT_L.json`](./kintex7/tile_type_INT_L.json)
|
||||
* [`b1ada7c7e90afe1b4942897912f028b258e7157bbd9041f399b268fe256b270c ./kintex7/tile_type_INT_R.json`](./kintex7/tile_type_INT_R.json)
|
||||
* [`1eb3c6e2ffed9dd7bf8c88db42e5ddb3834966d59935973be256dbe3081c26d8 ./kintex7/tile_type_IO_INT_INTERFACE_L.json`](./kintex7/tile_type_IO_INT_INTERFACE_L.json)
|
||||
* [`c77d0a3cac3f62df502bf81e5b3ec9dd902872b9d642a711734f434259a3ca74 ./kintex7/tile_type_IO_INT_INTERFACE_R.json`](./kintex7/tile_type_IO_INT_INTERFACE_R.json)
|
||||
* [`16a518f917b854c87eafdebe24261b758a868940de8a4629de650befa9f86da0 ./kintex7/tile_type_LIOB33.json`](./kintex7/tile_type_LIOB33.json)
|
||||
* [`c095de913db4bddfcabbd5697a841500d344f83881f4d1beac75428cb25aad64 ./kintex7/tile_type_LIOB33_SING.json`](./kintex7/tile_type_LIOB33_SING.json)
|
||||
* [`72855c141f9eaf7238ff243e223439eee18df1b1bfba4f8a686835f1542c880a ./kintex7/tile_type_LIOI3.json`](./kintex7/tile_type_LIOI3.json)
|
||||
* [`1e6fad575e8b68ce44fea9b0509cc5d83ca0670cf97cebf4a29f983bee5ae49e ./kintex7/tile_type_LIOI3_SING.json`](./kintex7/tile_type_LIOI3_SING.json)
|
||||
* [`f35fc20f3f65bf3f867cf477bcdd288e7270fda5d0204742d2f137fe08476f1d ./kintex7/tile_type_LIOI3_TBYTESRC.json`](./kintex7/tile_type_LIOI3_TBYTESRC.json)
|
||||
* [`05cf5e8fda8975612f1eaf0a08c8f9c18b9719d471cdd382241d8788698e6297 ./kintex7/tile_type_LIOI3_TBYTETERM.json`](./kintex7/tile_type_LIOI3_TBYTETERM.json)
|
||||
* [`e1c8778875bb256d12ed385b622bce95d86f5bd46c7aa5748f74f0854e39f2fd ./kintex7/tile_type_L_TERM_INT.json`](./kintex7/tile_type_L_TERM_INT.json)
|
||||
* [`3ee96506f2b4554c95c04365ac76da9d9df49a0882c0bc51763968a95bd426ed ./kintex7/tile_type_MONITOR_BOT_FUJI2.json`](./kintex7/tile_type_MONITOR_BOT_FUJI2.json)
|
||||
* [`7043cb553eec51674f1d2e34dcfdb7e2458f0412cf1103ad2d4369c3b9d21b20 ./kintex7/tile_type_MONITOR_MID_FUJI2.json`](./kintex7/tile_type_MONITOR_MID_FUJI2.json)
|
||||
* [`a067e6134b9585d01b365b4ea89c523a10d491b18fee28db79846deca1541e73 ./kintex7/tile_type_MONITOR_TOP_FUJI2.json`](./kintex7/tile_type_MONITOR_TOP_FUJI2.json)
|
||||
* [`2397779fbc09ce1abbb28d2d3b0dbd2c2d8ab733971455898b720ed41405943c ./kintex7/tile_type_NULL.json`](./kintex7/tile_type_NULL.json)
|
||||
* [`cdde011fe6911e6bada3d8cb076a638fbcbe8daf3a3a1f312f6435a0393e742c ./kintex7/tile_type_PCIE_BOT.json`](./kintex7/tile_type_PCIE_BOT.json)
|
||||
* [`f40a6d7b7146547db93e4de9bcde2079a2a2b2e4059741ae77365d684d777514 ./kintex7/tile_type_PCIE_INT_INTERFACE_L.json`](./kintex7/tile_type_PCIE_INT_INTERFACE_L.json)
|
||||
* [`ace3f9b3eeea6b9ed9505bc4c9934731ee7c3ed5e18279ec1845564210ab9b44 ./kintex7/tile_type_PCIE_INT_INTERFACE_R.json`](./kintex7/tile_type_PCIE_INT_INTERFACE_R.json)
|
||||
* [`12f4f10939cf94413223482516debe3c272717af213589426b58ca4bc9043df7 ./kintex7/tile_type_PCIE_NULL.json`](./kintex7/tile_type_PCIE_NULL.json)
|
||||
* [`e3ef7cfe139e7d320b2e47fac82f33fc8dbbf9727a76ca093f35f4c85703ac58 ./kintex7/tile_type_PCIE_TOP.json`](./kintex7/tile_type_PCIE_TOP.json)
|
||||
* [`fcf3b72e6b038ed65ef58fd4c1f0e7b3ec6d9c530a7b4d2e3d646db757c9adf2 ./kintex7/tile_type_RIOB18.json`](./kintex7/tile_type_RIOB18.json)
|
||||
* [`af89547e9585767a881eea25331c1d2a18a9f37bbc1f9d69fe03c45a9a270bd7 ./kintex7/tile_type_RIOB18_SING.json`](./kintex7/tile_type_RIOB18_SING.json)
|
||||
* [`d0850c3b1fb8c75b9e6bd2a0b61043d251956bc8553f614c4bb0bf02ee6aa23b ./kintex7/tile_type_RIOI.json`](./kintex7/tile_type_RIOI.json)
|
||||
* [`2612c6eef42b6767ec3d06379ab74edd25203ab8a2920004b3c34892465b0217 ./kintex7/tile_type_RIOI_SING.json`](./kintex7/tile_type_RIOI_SING.json)
|
||||
* [`7707013ce13e9ea1f6c2c24ad93877cab11fc92bd51e663fda6673777df3cdad ./kintex7/tile_type_RIOI_TBYTESRC.json`](./kintex7/tile_type_RIOI_TBYTESRC.json)
|
||||
* [`1fec66d8e84dd2da267a0a2c64a482e2ecf263e023ffcaaffe1c72ebb8930a73 ./kintex7/tile_type_RIOI_TBYTETERM.json`](./kintex7/tile_type_RIOI_TBYTETERM.json)
|
||||
* [`3f8ed6685fa00260c4c65b8401a4cf13aea24d833a634cc567aaeeeb1c29b23a ./kintex7/tile_type_R_TERM_INT_GTX.json`](./kintex7/tile_type_R_TERM_INT_GTX.json)
|
||||
* [`50eb0be5594840accc6fbf8cd9f060d57b9a5e975e035157545dd86451563a36 ./kintex7/tile_type_R_TERM_INT.json`](./kintex7/tile_type_R_TERM_INT.json)
|
||||
* [`6a66169978dc3250a90b949218a5f3d82ee68b2aac7868ad6f3aabe0ec7a8c05 ./kintex7/tile_type_TERM_CMT.json`](./kintex7/tile_type_TERM_CMT.json)
|
||||
* [`861c90352175d3daab60219cd90a25ed429ea635b22eb06581c70625b8e606a7 ./kintex7/tile_type_T_TERM_INT.json`](./kintex7/tile_type_T_TERM_INT.json)
|
||||
* [`2ce397e17c318c2fd95ebc20bb9c683e12d08ecaab5914f434e9e6ba80b108d8 ./kintex7/tile_type_VBRK_EXT.json`](./kintex7/tile_type_VBRK_EXT.json)
|
||||
* [`05351758a94de46419680b6d8306ea0366afe7ba14bf0539726db96cdc76cf8d ./kintex7/tile_type_VBRK.json`](./kintex7/tile_type_VBRK.json)
|
||||
* [`4b910b14d8ff3234d37be5adfc19808701ff336c943e35492414e8417a7d856c ./kintex7/tile_type_VFRAME.json`](./kintex7/tile_type_VFRAME.json)
|
||||
* [`44c1530cc9a184551c98face08bd4ab0a7ec3883623175a52da5c59fba9bfa38 ./kintex7/xc7k70tfbg676-2.yaml`](./kintex7/xc7k70tfbg676-2.yaml)
|
||||
|
||||
|
|
|
|||
|
|
@ -109,4 +109,4 @@
|
|||
"wire": "VBRK_X29Y152/VBRK_SW4A0"
|
||||
}
|
||||
]
|
||||
}
|
||||
}
|
||||
|
|
@ -109,4 +109,4 @@
|
|||
"wire": ""
|
||||
}
|
||||
]
|
||||
}
|
||||
}
|
||||
|
|
@ -109,4 +109,4 @@
|
|||
"wire": "VBRK_X29Y152/VBRK_SW4A0"
|
||||
}
|
||||
]
|
||||
}
|
||||
}
|
||||
|
|
@ -3,10 +3,7 @@
|
|||
"CAPTURE": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TDO": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"UPDATE": {
|
||||
"DRCK": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"RESET": {
|
||||
|
|
@ -15,25 +12,28 @@
|
|||
"RUNTEST": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SEL": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SHIFT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TMS": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TDI": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TCK": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SEL": {
|
||||
"TDI": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DRCK": {
|
||||
"TDO": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TMS": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"UPDATE": {
|
||||
"direction": "OUT"
|
||||
}
|
||||
},
|
||||
"site_pips": {},
|
||||
"type": "BSCAN"
|
||||
}
|
||||
}
|
||||
|
|
@ -1,82 +1,82 @@
|
|||
{
|
||||
"site_pins": {
|
||||
"IGNORE1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"I1": {
|
||||
"CE0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CE1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"S1": {
|
||||
"I0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CE0": {
|
||||
"I1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"S0": {
|
||||
"IGNORE0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"IGNORE1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"I0": {
|
||||
"S0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"IGNORE0": {
|
||||
"S1": {
|
||||
"direction": "IN"
|
||||
}
|
||||
},
|
||||
"site_pips": {
|
||||
"IGNORE0INV:IGNORE0": {
|
||||
"from_pin": "IGNORE0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"IGNORE1INV:IGNORE1_B": {
|
||||
"from_pin": "IGNORE1_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"S0INV:S0_B": {
|
||||
"from_pin": "S0_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"IGNORE1INV:IGNORE1": {
|
||||
"from_pin": "IGNORE1",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"S1INV:S1_B": {
|
||||
"from_pin": "S1_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"CE1INV:CE1": {
|
||||
"from_pin": "CE1",
|
||||
"CE0INV:CE0": {
|
||||
"from_pin": "CE0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"CE0INV:CE0_B": {
|
||||
"from_pin": "CE0_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"CE1INV:CE1": {
|
||||
"from_pin": "CE1",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"CE1INV:CE1_B": {
|
||||
"from_pin": "CE1_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"S1INV:S1": {
|
||||
"from_pin": "S1",
|
||||
"IGNORE0INV:IGNORE0": {
|
||||
"from_pin": "IGNORE0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"IGNORE0INV:IGNORE0_B": {
|
||||
"from_pin": "IGNORE0_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"IGNORE1INV:IGNORE1": {
|
||||
"from_pin": "IGNORE1",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"IGNORE1INV:IGNORE1_B": {
|
||||
"from_pin": "IGNORE1_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"S0INV:S0": {
|
||||
"from_pin": "S0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"CE0INV:CE0": {
|
||||
"from_pin": "CE0",
|
||||
"S0INV:S0_B": {
|
||||
"from_pin": "S0_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"IGNORE0INV:IGNORE0_B": {
|
||||
"from_pin": "IGNORE0_B",
|
||||
"S1INV:S1": {
|
||||
"from_pin": "S1",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"S1INV:S1_B": {
|
||||
"from_pin": "S1_B",
|
||||
"to_pin": "OUT"
|
||||
}
|
||||
},
|
||||
"type": "BUFGCTRL"
|
||||
}
|
||||
}
|
||||
|
|
@ -1,24 +1,24 @@
|
|||
{
|
||||
"site_pins": {
|
||||
"O": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CE": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"I": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O": {
|
||||
"direction": "OUT"
|
||||
}
|
||||
},
|
||||
"site_pips": {
|
||||
"CEINV:CE_B": {
|
||||
"from_pin": "CE_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"CEINV:CE": {
|
||||
"from_pin": "CE",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"CEINV:CE_B": {
|
||||
"from_pin": "CE_B",
|
||||
"to_pin": "OUT"
|
||||
}
|
||||
},
|
||||
"type": "BUFHCE"
|
||||
}
|
||||
}
|
||||
|
|
@ -1,12 +1,12 @@
|
|||
{
|
||||
"site_pins": {
|
||||
"O": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"I": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O": {
|
||||
"direction": "OUT"
|
||||
}
|
||||
},
|
||||
"site_pips": {},
|
||||
"type": "BUFIO"
|
||||
}
|
||||
}
|
||||
|
|
@ -1,24 +1,24 @@
|
|||
{
|
||||
"site_pins": {
|
||||
"O": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CE": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"I": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O": {
|
||||
"direction": "OUT"
|
||||
}
|
||||
},
|
||||
"site_pips": {
|
||||
"CEINV:CE_B": {
|
||||
"from_pin": "CE_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"CEINV:CE": {
|
||||
"from_pin": "CE",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"CEINV:CE_B": {
|
||||
"from_pin": "CE_B",
|
||||
"to_pin": "OUT"
|
||||
}
|
||||
},
|
||||
"type": "BUFMRCE"
|
||||
}
|
||||
}
|
||||
|
|
@ -1,18 +1,18 @@
|
|||
{
|
||||
"site_pins": {
|
||||
"CLR": {
|
||||
"CE": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CE": {
|
||||
"CLR": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"I": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O": {
|
||||
"direction": "OUT"
|
||||
}
|
||||
},
|
||||
"site_pips": {},
|
||||
"type": "BUFR"
|
||||
}
|
||||
}
|
||||
|
|
@ -1,12 +1,12 @@
|
|||
{
|
||||
"site_pins": {
|
||||
"CLK": {
|
||||
"CAP": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CAP": {
|
||||
"CLK": {
|
||||
"direction": "IN"
|
||||
}
|
||||
},
|
||||
"site_pips": {},
|
||||
"type": "CAPTURE"
|
||||
}
|
||||
}
|
||||
|
|
@ -9,4 +9,4 @@
|
|||
},
|
||||
"site_pips": {},
|
||||
"type": "DCIRESET"
|
||||
}
|
||||
}
|
||||
|
|
@ -18,4 +18,4 @@
|
|||
},
|
||||
"site_pips": {},
|
||||
"type": "DNA_PORT"
|
||||
}
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,102 +1,102 @@
|
|||
{
|
||||
"site_pins": {
|
||||
"EFUSEUSR7": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR12": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR19": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR20": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR13": {
|
||||
"EFUSEUSR0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR29": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR14": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR9": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR15": {
|
||||
"EFUSEUSR10": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR11": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR23": {
|
||||
"EFUSEUSR12": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR26": {
|
||||
"EFUSEUSR13": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR30": {
|
||||
"EFUSEUSR14": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR24": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR28": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR10": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR21": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR5": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR22": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR6": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR27": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR17": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR8": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR18": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR31": {
|
||||
"EFUSEUSR15": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR16": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR17": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR18": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR19": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR20": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR21": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR22": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR23": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR24": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR25": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR26": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR27": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR28": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR29": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR30": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR31": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR5": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR6": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR7": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR8": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EFUSEUSR9": {
|
||||
"direction": "OUT"
|
||||
}
|
||||
},
|
||||
"site_pips": {},
|
||||
"type": "EFUSE_USR"
|
||||
}
|
||||
}
|
||||
|
|
@ -1,493 +1,493 @@
|
|||
{
|
||||
"site_pins": {
|
||||
"WEBWE6": {
|
||||
"ADDRARDADDR0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DO1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"ADDRARDADDR1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DIPBDIP0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DIADI9": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"WRERR": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DIADI1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DIPADIP0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ADDRBWRADDR1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DO13": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"ADDRBWRADDR8": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"WRCOUNT3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"RDCOUNT9": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"WRCOUNT7": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"REGCLKB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DO7": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO29": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO9": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO14": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DIADI14": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ADDRARDADDR11": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DIADI7": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"WEBWE7": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DO5": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO22": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"WEA1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ADDRARDADDR6": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"WREN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DIADI4": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ADDRBWRADDR5": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"RDCOUNT8": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"ALMOSTEMPTY": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"RDERR": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DIBDI9": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"WRCOUNT0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"WRCOUNT8": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DIBDI15": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DO6": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"WEBWE2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ADDRARDADDR10": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DO23": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DIADI0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"EMPTY": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DIBDI1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DIADI12": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DOP1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"ADDRARDADDR8": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ADDRBWRADDR0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"RSTREG": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"RDCOUNT7": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"ADDRBWRADDR10": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DO16": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO20": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"ALMOSTFULL": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"WEBWE4": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ADDRARDADDR4": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"WRCOUNT11": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DIADI3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"REGCE": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DO19": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"ADDRARDADDR0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DIADI2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ADDRBTIEHIGH1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"RDCOUNT3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"RDEN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DIBDI0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"WEBWE1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"RDCOUNT2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"ADDRARDADDR7": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"RDCOUNT11": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO31": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO21": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"RDRCLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DIADI13": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"WRCOUNT2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DIADI5": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DOP0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"ADDRBWRADDR4": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DIADI15": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"WEBWE0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ADDRBWRADDR2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"WRCOUNT6": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO17": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"RDCOUNT6": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"RDCOUNT5": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DIBDI5": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DO0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DIBDI13": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ADDRARDADDR5": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ADDRARDADDR3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DO30": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FULL": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"WEA0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ADDRARDADDR2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DIADI11": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DO11": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO25": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DOP3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"WRCLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DIBDI14": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ADDRBWRADDR3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DOP2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"ADDRARDADDR9": {
|
||||
"ADDRARDADDR11": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ADDRARDADDR12": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DO15": {
|
||||
"direction": "OUT"
|
||||
"ADDRARDADDR13": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"RSTREGB": {
|
||||
"ADDRARDADDR2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ADDRARDADDR3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ADDRARDADDR4": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ADDRARDADDR5": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ADDRARDADDR6": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ADDRARDADDR7": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ADDRARDADDR8": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ADDRARDADDR9": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ADDRATIEHIGH0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ADDRATIEHIGH1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DO24": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DIPADIP1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DIADI6": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ADDRBTIEHIGH0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DO12": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DIBDI12": {
|
||||
"ADDRBTIEHIGH1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"WRCOUNT10": {
|
||||
"direction": "OUT"
|
||||
"ADDRBWRADDR0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DIBDI3": {
|
||||
"ADDRBWRADDR1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ADDRBWRADDR10": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ADDRBWRADDR11": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ADDRBWRADDR12": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ADDRBWRADDR13": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"RDCLK": {
|
||||
"ADDRBWRADDR2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DIBDI4": {
|
||||
"ADDRBWRADDR3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"RDCOUNT1": {
|
||||
"direction": "OUT"
|
||||
"ADDRBWRADDR4": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"RDCOUNT4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"WEBWE3": {
|
||||
"ADDRBWRADDR5": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ADDRBWRADDR6": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DIBDI7": {
|
||||
"ADDRBWRADDR7": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DIBDI10": {
|
||||
"ADDRBWRADDR8": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DIBDI6": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DIPBDIP1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DO26": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"RSTRAMB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"RST": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"WRCOUNT5": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO28": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"REGCEB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DIBDI2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DO10": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"ADDRATIEHIGH0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DIBDI11": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"WRCOUNT1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO8": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"ADDRBWRADDR12": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"WRCOUNT9": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"ADDRBWRADDR11": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DO2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"ADDRBWRADDR9": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"WEA3": {
|
||||
"ALMOSTEMPTY": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"ALMOSTFULL": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DIADI0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ADDRARDADDR13": {
|
||||
"DIADI1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ADDRBWRADDR7": {
|
||||
"DIADI10": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"WEBWE5": {
|
||||
"DIADI11": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DIADI12": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DIADI13": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DIADI14": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DIADI15": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DIADI2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DIADI3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DIADI4": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DIADI5": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DIADI6": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DIADI7": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DIADI8": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DO3": {
|
||||
"direction": "OUT"
|
||||
"DIADI9": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DO18": {
|
||||
"direction": "OUT"
|
||||
"DIBDI0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"WRCOUNT4": {
|
||||
"direction": "OUT"
|
||||
"DIBDI1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"WEA2": {
|
||||
"DIBDI10": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DIBDI11": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DIBDI12": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DIBDI13": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DIBDI14": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DIBDI15": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DIBDI2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DIBDI3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DIBDI4": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DIBDI5": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DIBDI6": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DIBDI7": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DIBDI8": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"RDCOUNT0": {
|
||||
"DIBDI9": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DIPADIP0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DIPADIP1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DIPBDIP0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DIPBDIP1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DO0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO10": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO11": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO12": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO13": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO14": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO15": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO16": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO17": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO18": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO19": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO20": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO21": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO22": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO23": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO24": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO25": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO26": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO27": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DIADI10": {
|
||||
"DO28": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO29": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO30": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO31": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO5": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO6": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO7": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO8": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO9": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DOP0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DOP1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DOP2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DOP3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EMPTY": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FULL": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"RDCLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"RDCOUNT0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"RDCOUNT1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"RDCOUNT10": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"RDCOUNT11": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"RDCOUNT2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"RDCOUNT3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"RDCOUNT4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"RDCOUNT5": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"RDCOUNT6": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"RDCOUNT7": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"RDCOUNT8": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"RDCOUNT9": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"RDEN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"RDERR": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"RDRCLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"REGCE": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"REGCEB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"REGCLKB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"RST": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"RSTRAMB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"RSTREG": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"RSTREGB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"WEA0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"WEA1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"WEA2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"WEA3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"WEBWE0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"WEBWE1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"WEBWE2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"WEBWE3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"WEBWE4": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"WEBWE5": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"WEBWE6": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"WEBWE7": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"WRCLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"WRCOUNT0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"WRCOUNT1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"WRCOUNT10": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"WRCOUNT11": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"WRCOUNT2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"WRCOUNT3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"WRCOUNT4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"WRCOUNT5": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"WRCOUNT6": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"WRCOUNT7": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"WRCOUNT8": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"WRCOUNT9": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"WREN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"WRERR": {
|
||||
"direction": "OUT"
|
||||
}
|
||||
},
|
||||
"site_pips": {
|
||||
"WRENINV:WREN_B": {
|
||||
"from_pin": "WREN_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"RSTINV:RST": {
|
||||
"from_pin": "RST",
|
||||
"RDCLKINV:RDCLK": {
|
||||
"from_pin": "RDCLK",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"RDCLKINV:RDCLK_B": {
|
||||
"from_pin": "RDCLK_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"RDENINV:RDEN": {
|
||||
"from_pin": "RDEN",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"RDENINV:RDEN_B": {
|
||||
"from_pin": "RDEN_B",
|
||||
"to_pin": "OUT"
|
||||
|
|
@ -496,42 +496,42 @@
|
|||
"from_pin": "RDRCLK",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"WRENINV:WREN": {
|
||||
"from_pin": "WREN",
|
||||
"RDRCLKINV:RDRCLK_B": {
|
||||
"from_pin": "RDRCLK_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"RDENINV:RDEN": {
|
||||
"from_pin": "RDEN",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"WRCLKINV:WRCLK_B": {
|
||||
"from_pin": "WRCLK_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"WRCLKINV:WRCLK": {
|
||||
"from_pin": "WRCLK",
|
||||
"RSTINV:RST": {
|
||||
"from_pin": "RST",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"RSTINV:RST_B": {
|
||||
"from_pin": "RST_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"RDCLKINV:RDCLK": {
|
||||
"from_pin": "RDCLK",
|
||||
"RSTREGINV:RSTREG": {
|
||||
"from_pin": "RSTREG",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"RSTREGINV:RSTREG_B": {
|
||||
"from_pin": "RSTREG_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"RDRCLKINV:RDRCLK_B": {
|
||||
"from_pin": "RDRCLK_B",
|
||||
"WRCLKINV:WRCLK": {
|
||||
"from_pin": "WRCLK",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"RSTREGINV:RSTREG": {
|
||||
"from_pin": "RSTREG",
|
||||
"WRCLKINV:WRCLK_B": {
|
||||
"from_pin": "WRCLK_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"WRENINV:WREN": {
|
||||
"from_pin": "WREN",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"WRENINV:WREN_B": {
|
||||
"from_pin": "WREN_B",
|
||||
"to_pin": "OUT"
|
||||
}
|
||||
},
|
||||
"type": "FIFO18E1"
|
||||
}
|
||||
}
|
||||
|
|
@ -1,108 +1,33 @@
|
|||
{
|
||||
"site_pins": {
|
||||
"SYNDROME1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNBIT2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR24": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNDROME2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR21": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR23": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNDROME10": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNBIT1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNDROME7": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR13": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNWORD5": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR8": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNBIT4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNWORD0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNDROMEVALID": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR14": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR7": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNWORD1": {
|
||||
"CRCERROR": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"ECCERROR": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR12": {
|
||||
"ECCERRORSINGLE": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR18": {
|
||||
"FAR0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNWORD4": {
|
||||
"FAR1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR10": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNWORD2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNWORD6": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR9": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR11": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR5": {
|
||||
"FAR12": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"ECCERRORSINGLE": {
|
||||
"FAR13": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNDROME11": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNDROME12": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR3": {
|
||||
"FAR14": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR15": {
|
||||
|
|
@ -111,61 +36,136 @@
|
|||
"FAR16": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNDROME9": {
|
||||
"FAR17": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNDROME3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNBIT0": {
|
||||
"FAR18": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR19": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNDROME8": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR6": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNDROME4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR17": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR22": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNWORD3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNDROME5": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR25": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNBIT3": {
|
||||
"FAR2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR20": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR21": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR22": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR23": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR24": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR25": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR5": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR6": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR7": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR8": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FAR9": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNBIT0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNBIT1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNBIT2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNBIT3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNBIT4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNDROME0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNDROME1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNDROME10": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNDROME11": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNDROME12": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNDROME2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNDROME3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNDROME4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNDROME5": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNDROME6": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CRCERROR": {
|
||||
"SYNDROME7": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNDROME8": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNDROME9": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNDROMEVALID": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNWORD0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNWORD1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNWORD2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNWORD3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNWORD4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNWORD5": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNWORD6": {
|
||||
"direction": "OUT"
|
||||
}
|
||||
},
|
||||
"site_pips": {},
|
||||
"type": "FRAME_ECC"
|
||||
}
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,518 +1,486 @@
|
|||
{
|
||||
"site_pins": {
|
||||
"PLL1REFCLKSEL1": {
|
||||
"BGBYPASSB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DMONITOROUT7": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DRPDO8": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PLL0REFCLKLOST": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PMARSVDOUT2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DRPDO7": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PLL0FBCLKLOST": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PLL1OUTCLK": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DRPDO6": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PMASCANOUT0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"BGRCALOVRD3": {
|
||||
"BGMONITORENB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"GTWESTREFCLK1": {
|
||||
"BGPDB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DRPADDR4": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PLLRSVD13": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DRPDI15": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"GTEASTREFCLK0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PLL1REFCLKLOST": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DRPDO10": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"BGRCALOVRD0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PLLRSVD112": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PLLRSVD15": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PLLRSVD12": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PLLRSVD18": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DRPEN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DRPDO3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DRPDI13": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PLL0RESET": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DRPDI11": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PLLRSVD14": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"GTWESTREFCLK0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DRPDI0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"REFCLKOUTMONITOR1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"RCALENB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PLL1FBCLKLOST": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PMARSVDOUT15": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PLL1LOCKDETCLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DRPDO15": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PMARSVD7": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PMASCANCLK0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PMARSVD0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"BGRCALOVRD1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PMARSVDOUT9": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PMARSVD6": {
|
||||
"BGRCALOVRD2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DRPDI14": {
|
||||
"BGRCALOVRD3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DMONITOROUT2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DRPRDY": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DRPADDR1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PMARSVDOUT3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PLL0OUTREFCLK": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PMASCANIN3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DRPDO13": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PLL1LOCK": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PMASCANENB": {
|
||||
"BGRCALOVRD4": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"BGRCALOVRDENB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PLL1RESET": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"GTREFCLK0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DRPDI5": {
|
||||
"direction": "IN"
|
||||
"DMONITOROUT0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DMONITOROUT1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DRPDO11": {
|
||||
"DMONITOROUT2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PLL0REFCLKSEL1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PMASCANCLK1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PMASCANOUT2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PLLRSVD19": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"BGRCALOVRD2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PMASCANIN2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PLL0REFCLKSEL2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PLLRSVD16": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DRPDO2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DMONITOROUT0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DRPDI4": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"QDPMASCANMODEB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DRPDO5": {
|
||||
"DMONITOROUT3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DMONITOROUT4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PLLRSVD10": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"GTREFCLK1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DRPDO0": {
|
||||
"DMONITOROUT5": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DRPCLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PLLCLKSPARE": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DRPDI3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PLL1PD": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PLLRSVD20": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PMASCANOUT3": {
|
||||
"DMONITOROUT6": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PMARSVDOUT7": {
|
||||
"DMONITOROUT7": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PLLRSVD115": {
|
||||
"DRPADDR0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PLLRSVD24": {
|
||||
"DRPADDR1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DRPADDR2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"GTGREFCLK0": {
|
||||
"DRPADDR3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DRPDI7": {
|
||||
"DRPADDR4": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PMARSVDOUT5": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PMARSVDOUT10": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"GTEASTREFCLK1": {
|
||||
"DRPADDR5": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PMARSVD5": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DRPDO14": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"QDPMASCANRSTEN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PMARSVD2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DRPDI6": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PMARSVDOUT6": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DRPDO4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PMASCANOUT1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DRPADDR6": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DMONITOROUT6": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DRPDO9": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PLL0LOCKEN": {
|
||||
"DRPADDR7": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PMASCANIN0": {
|
||||
"DRPCLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PMARSVDOUT13": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"REFCLKOUTMONITOR0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PMARSVD1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DMONITOROUT3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PLLRSVD110": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DRPADDR0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PLLRSVD17": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PLLRSVD114": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DRPDI8": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DRPDO1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"GTGREFCLK1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PLLRSVD11": {
|
||||
"DRPDI0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DRPDI1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PMASCANIN1": {
|
||||
"DRPDI10": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PLL0PD": {
|
||||
"DRPDI11": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PMARSVDOUT11": {
|
||||
"DRPDI12": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DRPDI13": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DRPDI14": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DRPDI15": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DRPDI2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DRPDI3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DRPDI4": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DRPDI5": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DRPDI6": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DRPDI7": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DRPDI8": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DRPDI9": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DRPDO0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"BGRCALOVRD4": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PLL1OUTREFCLK": {
|
||||
"DRPDO1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PMARSVDOUT1": {
|
||||
"DRPDO10": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PLL0OUTCLK": {
|
||||
"DRPDO11": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PLLRSVD21": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PMARSVDOUT4": {
|
||||
"DRPDO12": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PMASCANIN4": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PMARSVDOUT14": {
|
||||
"DRPDO13": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PLL1REFCLKSEL2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PLL0REFCLKSEL0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PLL1LOCKEN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PMASCANOUT4": {
|
||||
"DRPDO14": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PMARSVDOUT8": {
|
||||
"DRPDO15": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"BGMONITORENB": {
|
||||
"DRPDO2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DRPDO3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DRPDO4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DRPDO5": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DRPDO6": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DRPDO7": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DRPDO8": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DRPDO9": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DRPEN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DRPRDY": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DRPWE": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"GTEASTREFCLK0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"GTEASTREFCLK1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"GTGREFCLK0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"GTGREFCLK1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"GTREFCLK0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"GTREFCLK1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"GTWESTREFCLK0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"GTWESTREFCLK1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PLL0FBCLKLOST": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PLL0LOCK": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PLL0LOCKDETCLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"BGBYPASSB": {
|
||||
"PLL0LOCKEN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DRPDI2": {
|
||||
"PLL0OUTCLK": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PLL0OUTREFCLK": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PLL0PD": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DRPADDR5": {
|
||||
"PLL0REFCLKLOST": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PLL0REFCLKSEL0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DRPDI9": {
|
||||
"PLL0REFCLKSEL1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PLLRSVD23": {
|
||||
"PLL0REFCLKSEL2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PLL0RESET": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PLL1FBCLKLOST": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PLL1LOCK": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PLL1LOCKDETCLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PLL1LOCKEN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PLL1OUTCLK": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PLL1OUTREFCLK": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PLL1PD": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PLL1REFCLKLOST": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PLL1REFCLKSEL0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PMARSVDOUT12": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DRPDO12": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"BGPDB": {
|
||||
"PLL1REFCLKSEL1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PLLRSVD113": {
|
||||
"PLL1REFCLKSEL2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DRPDI12": {
|
||||
"PLL1RESET": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PMARSVDOUT0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DRPADDR3": {
|
||||
"PLLCLKSPARE": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PMARSVD4": {
|
||||
"PLLRSVD10": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DMONITOROUT5": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DRPWE": {
|
||||
"PLLRSVD11": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PLLRSVD22": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PMARSVD3": {
|
||||
"PLLRSVD110": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PLLRSVD111": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DRPADDR7": {
|
||||
"PLLRSVD112": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DRPDI10": {
|
||||
"PLLRSVD113": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PLLRSVD114": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PLLRSVD115": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PLLRSVD12": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PLLRSVD13": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PLLRSVD14": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PLLRSVD15": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PLLRSVD16": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PLLRSVD17": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PLLRSVD18": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PLLRSVD19": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PLLRSVD20": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PLLRSVD21": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PLLRSVD22": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PLLRSVD23": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PLLRSVD24": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PMARSVD0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PMARSVD1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PMARSVD2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PMARSVD3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PMARSVD4": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PMARSVD5": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PMARSVD6": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PMARSVD7": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PMARSVDOUT0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PMARSVDOUT1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PMARSVDOUT10": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PMARSVDOUT11": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PMARSVDOUT12": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PMARSVDOUT13": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PMARSVDOUT14": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PMARSVDOUT15": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PMARSVDOUT2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PMARSVDOUT3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PMARSVDOUT4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PMARSVDOUT5": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PMARSVDOUT6": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PMARSVDOUT7": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PMARSVDOUT8": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PMARSVDOUT9": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PMASCANCLK0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PMASCANCLK1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PMASCANENB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PMASCANIN0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PMASCANIN1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PMASCANIN2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PMASCANIN3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PMASCANIN4": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PMASCANOUT0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PMASCANOUT1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PMASCANOUT2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PMASCANOUT3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PMASCANOUT4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"QDPMASCANMODEB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"QDPMASCANRSTEN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"RCALENB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"REFCLKOUTMONITOR0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"REFCLKOUTMONITOR1": {
|
||||
"direction": "OUT"
|
||||
}
|
||||
},
|
||||
"site_pips": {
|
||||
"PLL1LOCKDETCLKINV:PLL1LOCKDETCLK": {
|
||||
"from_pin": "PLL1LOCKDETCLK",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"PMASCANCLK0INV:PMASCANCLK0_B": {
|
||||
"from_pin": "PMASCANCLK0_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"PLL0LOCKDETCLKINV:PLL0LOCKDETCLK_B": {
|
||||
"from_pin": "PLL0LOCKDETCLK_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"PLL1LOCKDETCLKINV:PLL1LOCKDETCLK_B": {
|
||||
"from_pin": "PLL1LOCKDETCLK_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"PMASCANCLK1INV:PMASCANCLK1": {
|
||||
"from_pin": "PMASCANCLK1",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"PLL0LOCKDETCLKINV:PLL0LOCKDETCLK": {
|
||||
"from_pin": "PLL0LOCKDETCLK",
|
||||
"DRPCLKINV:DRPCLK": {
|
||||
"from_pin": "DRPCLK",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"DRPCLKINV:DRPCLK_B": {
|
||||
"from_pin": "DRPCLK_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"PMASCANCLK1INV:PMASCANCLK1_B": {
|
||||
"from_pin": "PMASCANCLK1_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"PLLCLKSPAREINV:PLLCLKSPARE_B": {
|
||||
"from_pin": "PLLCLKSPARE_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"PLLCLKSPAREINV:PLLCLKSPARE": {
|
||||
"from_pin": "PLLCLKSPARE",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"GTGREFCLK0INV:GTGREFCLK0": {
|
||||
"from_pin": "GTGREFCLK0",
|
||||
"to_pin": "OUT"
|
||||
|
|
@ -521,22 +489,54 @@
|
|||
"from_pin": "GTGREFCLK0_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"GTGREFCLK1INV:GTGREFCLK1": {
|
||||
"from_pin": "GTGREFCLK1",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"GTGREFCLK1INV:GTGREFCLK1_B": {
|
||||
"from_pin": "GTGREFCLK1_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"DRPCLKINV:DRPCLK": {
|
||||
"from_pin": "DRPCLK",
|
||||
"PLL0LOCKDETCLKINV:PLL0LOCKDETCLK": {
|
||||
"from_pin": "PLL0LOCKDETCLK",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"GTGREFCLK1INV:GTGREFCLK1": {
|
||||
"from_pin": "GTGREFCLK1",
|
||||
"PLL0LOCKDETCLKINV:PLL0LOCKDETCLK_B": {
|
||||
"from_pin": "PLL0LOCKDETCLK_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"PLL1LOCKDETCLKINV:PLL1LOCKDETCLK": {
|
||||
"from_pin": "PLL1LOCKDETCLK",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"PLL1LOCKDETCLKINV:PLL1LOCKDETCLK_B": {
|
||||
"from_pin": "PLL1LOCKDETCLK_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"PLLCLKSPAREINV:PLLCLKSPARE": {
|
||||
"from_pin": "PLLCLKSPARE",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"PLLCLKSPAREINV:PLLCLKSPARE_B": {
|
||||
"from_pin": "PLLCLKSPARE_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"PMASCANCLK0INV:PMASCANCLK0": {
|
||||
"from_pin": "PMASCANCLK0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"PMASCANCLK0INV:PMASCANCLK0_B": {
|
||||
"from_pin": "PMASCANCLK0_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"PMASCANCLK1INV:PMASCANCLK1": {
|
||||
"from_pin": "PMASCANCLK1",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"PMASCANCLK1INV:PMASCANCLK1_B": {
|
||||
"from_pin": "PMASCANCLK1_B",
|
||||
"to_pin": "OUT"
|
||||
}
|
||||
},
|
||||
"type": "GTPE2_COMMON"
|
||||
}
|
||||
}
|
||||
|
|
@ -1,12 +1,9 @@
|
|||
{
|
||||
"site_pins": {
|
||||
"CLKTESTSIG": {
|
||||
"CEB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ODIV2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CEB": {
|
||||
"CLKTESTSIG": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"I": {
|
||||
|
|
@ -17,6 +14,9 @@
|
|||
},
|
||||
"O": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"ODIV2": {
|
||||
"direction": "OUT"
|
||||
}
|
||||
},
|
||||
"site_pips": {
|
||||
|
|
@ -30,4 +30,4 @@
|
|||
}
|
||||
},
|
||||
"type": "IBUFDS_GTE2"
|
||||
}
|
||||
}
|
||||
|
|
@ -1,90 +1,60 @@
|
|||
{
|
||||
"site_pins": {
|
||||
"O19": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"O5": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"I9": {
|
||||
"CLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"I23": {
|
||||
"CSIB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O24": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"I30": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"I15": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O13": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"I2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"O27": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"I31": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"I26": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O30": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"RDWRB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"I3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"I11": {
|
||||
"I0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"I1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O9": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CLK": {
|
||||
"I10": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"I20": {
|
||||
"I11": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O15": {
|
||||
"direction": "OUT"
|
||||
"I12": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"I21": {
|
||||
"I13": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"I14": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"I15": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"I16": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O12": {
|
||||
"direction": "OUT"
|
||||
"I17": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O17": {
|
||||
"direction": "OUT"
|
||||
"I18": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O0": {
|
||||
"direction": "OUT"
|
||||
"I19": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"I8": {
|
||||
"I2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"I20": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"I21": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"I22": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"I23": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"I24": {
|
||||
|
|
@ -93,97 +63,25 @@
|
|||
"I25": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CSIB": {
|
||||
"I26": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O20": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"O29": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"O31": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"O7": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"O8": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"O28": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"I27": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O16": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"I17": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"I18": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"I12": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O25": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"I10": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"I7": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"I13": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O22": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"O23": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"I29": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"I28": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O10": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"O11": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"O21": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"O6": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"I22": {
|
||||
"I29": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"I14": {
|
||||
"I3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"I6": {
|
||||
"I30": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O26": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"I19": {
|
||||
"I31": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"I4": {
|
||||
|
|
@ -192,16 +90,118 @@
|
|||
"I5": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O18": {
|
||||
"I6": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"I7": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"I8": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"I9": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"I0": {
|
||||
"direction": "IN"
|
||||
"O1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"O10": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"O11": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"O12": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"O13": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"O14": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"O15": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"O16": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"O17": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"O18": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"O19": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"O2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"O20": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"O21": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"O22": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"O23": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"O24": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"O25": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"O26": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"O27": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"O28": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"O29": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"O3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"O30": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"O31": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"O4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"O5": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"O6": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"O7": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"O8": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"O9": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"RDWRB": {
|
||||
"direction": "IN"
|
||||
}
|
||||
},
|
||||
"site_pips": {},
|
||||
"type": "ICAP"
|
||||
}
|
||||
}
|
||||
|
|
@ -1,27 +1,27 @@
|
|||
{
|
||||
"site_pins": {
|
||||
"DNPULSEOUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"OUTN1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"OUTN65": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"RDY": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"REFCLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"RST": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"UPPULSEOUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DNPULSEOUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"OUTN65": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"REFCLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"RDY": {
|
||||
"direction": "OUT"
|
||||
}
|
||||
},
|
||||
"site_pips": {},
|
||||
"type": "IDELAYCTRL"
|
||||
}
|
||||
}
|
||||
|
|
@ -1,100 +1,100 @@
|
|||
{
|
||||
"site_pins": {
|
||||
"IFDLY1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DATAIN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"INC": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"C": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CNTVALUEOUT2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"IFDLY2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CNTVALUEOUT1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"LDPIPEEN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"IFDLY0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CNTVALUEIN1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"LD": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"IDATAIN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CNTVALUEOUT4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CNTVALUEOUT0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CE": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CNTVALUEIN2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CNTVALUEIN0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CINVCTRL": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CNTVALUEIN0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CNTVALUEIN1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CNTVALUEIN2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CNTVALUEIN3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CNTVALUEIN4": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CNTVALUEOUT0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CNTVALUEOUT1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CNTVALUEOUT2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CNTVALUEOUT3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CNTVALUEIN4": {
|
||||
"CNTVALUEOUT4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATAIN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DATAOUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"REGRST": {
|
||||
"IDATAIN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CNTVALUEIN3": {
|
||||
"IFDLY0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"IFDLY1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"IFDLY2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"INC": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"LD": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"LDPIPEEN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"REGRST": {
|
||||
"direction": "IN"
|
||||
}
|
||||
},
|
||||
"site_pips": {
|
||||
"IDATAININV:IDATAIN_B": {
|
||||
"from_pin": "IDATAIN_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"DATAININV:DATAIN": {
|
||||
"from_pin": "DATAIN",
|
||||
"CINV:C": {
|
||||
"from_pin": "C",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"CINV:C_B": {
|
||||
"from_pin": "C_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"IDATAININV:IDATAIN": {
|
||||
"from_pin": "IDATAIN",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"CINV:C": {
|
||||
"from_pin": "C",
|
||||
"DATAININV:DATAIN": {
|
||||
"from_pin": "DATAIN",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"DATAININV:DATAIN_B": {
|
||||
"from_pin": "DATAIN_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"IDATAININV:IDATAIN": {
|
||||
"from_pin": "IDATAIN",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"IDATAININV:IDATAIN_B": {
|
||||
"from_pin": "IDATAIN_B",
|
||||
"to_pin": "OUT"
|
||||
}
|
||||
},
|
||||
"type": "IDELAYE2"
|
||||
}
|
||||
}
|
||||
|
|
@ -1,90 +1,39 @@
|
|||
{
|
||||
"site_pins": {
|
||||
"TFB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"OFB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"BITSLIP": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CLKDIV": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"REV": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SHIFTOUT1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q5": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SHIFTIN1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SHIFTOUT2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DYNCLKSEL": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CLKDIVP": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CE1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CLKB": {
|
||||
"CE2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q8": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q6": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DYNCLKDIVSEL": {
|
||||
"CLKB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"OCLKB": {
|
||||
"CLKDIV": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SHIFTIN2": {
|
||||
"CLKDIVP": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SR": {
|
||||
"D": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CE2": {
|
||||
"DDLY": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q7": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DYNCLKDIVPSEL": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DDLY": {
|
||||
"DYNCLKDIVSEL": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DYNCLKSEL": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O": {
|
||||
|
|
@ -92,51 +41,90 @@
|
|||
},
|
||||
"OCLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"OCLKB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"OFB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q5": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q6": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q7": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q8": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"REV": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SHIFTIN1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SHIFTIN2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SHIFTOUT1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SHIFTOUT2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SR": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TFB": {
|
||||
"direction": "IN"
|
||||
}
|
||||
},
|
||||
"site_pips": {
|
||||
"IFFDELMUXE3:1": {
|
||||
"from_pin": "1",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"CE1USED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"CLKBINV:CLKB_B": {
|
||||
"from_pin": "CLKB_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"DINV:D_B": {
|
||||
"from_pin": "D_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"CLKINV:CLK": {
|
||||
"from_pin": "CLK",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"ZHOLD_FABRIC_INV:D_B": {
|
||||
"from_pin": "D_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"CLKBINV:CLKB": {
|
||||
"from_pin": "CLKB",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"SRUSED:0": {
|
||||
"from_pin": "0",
|
||||
"CLKBINV:CLKB_B": {
|
||||
"from_pin": "CLKB_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"ZHOLD_IFF_INV:D": {
|
||||
"from_pin": "D",
|
||||
"CLKINV:CLK": {
|
||||
"from_pin": "CLK",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"IFFDELMUXE3:0": {
|
||||
"from_pin": "0",
|
||||
"CLKINV:CLK_B": {
|
||||
"from_pin": "CLK_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"IDELMUXE3:2": {
|
||||
"from_pin": "2",
|
||||
"D2OBYP_SEL:GND": {
|
||||
"from_pin": "GND",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"D2OBYP_SEL:T": {
|
||||
"from_pin": "T",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"D2OFFBYP_SEL:GND": {
|
||||
"from_pin": "GND",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"D2OFFBYP_SEL:T": {
|
||||
|
|
@ -147,40 +135,28 @@
|
|||
"from_pin": "D",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"ZHOLD_FABRIC_INV:D": {
|
||||
"from_pin": "D",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"IMUX:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"REVUSED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"IMUX:1": {
|
||||
"from_pin": "1",
|
||||
"DINV:D_B": {
|
||||
"from_pin": "D_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"IDELMUXE3:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"D2OFFBYP_SEL:GND": {
|
||||
"from_pin": "GND",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"D2OBYP_SEL:GND": {
|
||||
"from_pin": "GND",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"IFFMUX:1": {
|
||||
"IDELMUXE3:1": {
|
||||
"from_pin": "1",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"CLKINV:CLK_B": {
|
||||
"from_pin": "CLK_B",
|
||||
"IDELMUXE3:2": {
|
||||
"from_pin": "2",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"IFFDELMUXE3:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"IFFDELMUXE3:1": {
|
||||
"from_pin": "1",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"IFFDELMUXE3:2": {
|
||||
|
|
@ -191,18 +167,42 @@
|
|||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"ZHOLD_IFF_INV:D_B": {
|
||||
"from_pin": "D_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"IDELMUXE3:1": {
|
||||
"IFFMUX:1": {
|
||||
"from_pin": "1",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"D2OBYP_SEL:T": {
|
||||
"from_pin": "T",
|
||||
"IMUX:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"IMUX:1": {
|
||||
"from_pin": "1",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"REVUSED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"SRUSED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"ZHOLD_FABRIC_INV:D": {
|
||||
"from_pin": "D",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"ZHOLD_FABRIC_INV:D_B": {
|
||||
"from_pin": "D_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"ZHOLD_IFF_INV:D": {
|
||||
"from_pin": "D",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"ZHOLD_IFF_INV:D_B": {
|
||||
"from_pin": "D_B",
|
||||
"to_pin": "OUT"
|
||||
}
|
||||
},
|
||||
"type": "ILOGICE3"
|
||||
}
|
||||
}
|
||||
|
|
@ -1,453 +1,453 @@
|
|||
{
|
||||
"site_pins": {
|
||||
"Q61": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q73": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D91": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q00": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D41": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D02": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q84": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D70": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q60": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D51": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D22": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D92": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTWRITEDISB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SCANIN0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D00": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q11": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q16": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D53": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q40": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D65": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D11": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D30": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q12": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D50": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q32": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"ALMOSTEMPTY": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q07": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q35": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q55": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D67": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q93": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q85": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D56": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q30": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q67": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q71": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SCANOUT0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q52": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q86": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D40": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D62": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q51": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q25": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q92": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q97": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"ALMOSTFULL": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D42": {
|
||||
"D00": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q96": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q31": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q54": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q82": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SCANIN1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q63": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SCANIN3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D57": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D82": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D31": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"RDEN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q66": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q91": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q21": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"RESET": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q47": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D01": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D52": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q04": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q20": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q01": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D13": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D23": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q17": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q87": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q06": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D72": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D20": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTMODEB": {
|
||||
"D02": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D03": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q26": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D71": {
|
||||
"D10": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q22": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q37": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EMPTY": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q03": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q27": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q95": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D61": {
|
||||
"D11": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D80": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D55": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q81": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D32": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D54": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q64": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D12": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q13": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q94": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FULL": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D64": {
|
||||
"D13": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D60": {
|
||||
"D20": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SCANOUT1": {
|
||||
"direction": "OUT"
|
||||
"D21": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q36": {
|
||||
"direction": "OUT"
|
||||
"D22": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D83": {
|
||||
"D23": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D30": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D31": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D32": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D33": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q53": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q34": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"WRCLK": {
|
||||
"D40": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D10": {
|
||||
"D41": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q44": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTREADDISB": {
|
||||
"D42": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"WREN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q75": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q33": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SCANOUT2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D21": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q42": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q65": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SCANENB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q23": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D81": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q80": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q43": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q77": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q76": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q50": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q24": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SCANOUT3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q56": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q83": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D43": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q57": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q90": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q62": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D93": {
|
||||
"D50": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q74": {
|
||||
"direction": "OUT"
|
||||
"D51": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D52": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D53": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D54": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D55": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D56": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D57": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D60": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D61": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D62": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D63": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q70": {
|
||||
"direction": "OUT"
|
||||
"D64": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q02": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q14": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D73": {
|
||||
"D65": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D66": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q72": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SCANIN2": {
|
||||
"D67": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q10": {
|
||||
"direction": "OUT"
|
||||
"D70": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q46": {
|
||||
"direction": "OUT"
|
||||
"D71": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D72": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D73": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D80": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D81": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D82": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D83": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D90": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"RDCLK": {
|
||||
"D91": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D92": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D93": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"EMPTY": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FULL": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q00": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q01": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q02": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q03": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q04": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q05": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q41": {
|
||||
"Q06": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q07": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q10": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q11": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q12": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q13": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q14": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q15": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q16": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q17": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q20": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q21": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q22": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q23": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q24": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q25": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q26": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q27": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q30": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q31": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q32": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q33": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q34": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q35": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q36": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q37": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q40": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q41": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q42": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q43": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q44": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q45": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q46": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q47": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q50": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q51": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q52": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q53": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q54": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q55": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q56": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q57": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q60": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q61": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q62": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q63": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q64": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q65": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q66": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q67": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q70": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q71": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q72": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q73": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q74": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q75": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q76": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q77": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q80": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q81": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q82": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q83": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q84": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q85": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q86": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q87": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q90": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q91": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q92": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q93": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q94": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q95": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q96": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q97": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"RDCLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"RDEN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"RESET": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SCANENB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SCANIN0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SCANIN1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SCANIN2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SCANIN3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SCANOUT0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SCANOUT1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SCANOUT2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SCANOUT3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTMODEB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTREADDISB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTWRITEDISB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"WRCLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"WREN": {
|
||||
"direction": "IN"
|
||||
}
|
||||
},
|
||||
"site_pips": {},
|
||||
"type": "IN_FIFO"
|
||||
}
|
||||
}
|
||||
|
|
@ -1,9 +1,9 @@
|
|||
{
|
||||
"site_pins": {
|
||||
"PD_INT_EN": {
|
||||
"DIFFI_IN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DIFFI_IN": {
|
||||
"DIFFO_IN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DIFFO_OUT": {
|
||||
|
|
@ -12,57 +12,61 @@
|
|||
"DIFF_TERM_INT_EN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PADOUT": {
|
||||
"I": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"T": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"IBUFDISABLE": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"T_OUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"INTERMDISABLE": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PU_INT_EN": {
|
||||
"KEEPER_INT_EN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O_IN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O_OUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"KEEPER_INT_EN": {
|
||||
"PADOUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PD_INT_EN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PU_INT_EN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"T": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"T_IN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"I": {
|
||||
"T_OUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"O": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DIFFO_IN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O_IN": {
|
||||
"direction": "IN"
|
||||
}
|
||||
},
|
||||
"site_pips": {
|
||||
"DIFFI_INUSED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"IBUFDISABLE_SEL:GND": {
|
||||
"from_pin": "GND",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"IBUFDISABLE_SEL:I": {
|
||||
"from_pin": "I",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"OUSED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"TUSED:0": {
|
||||
"from_pin": "0",
|
||||
"INTERMDISABLE_SEL:GND": {
|
||||
"from_pin": "GND",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"INTERMDISABLE_SEL:I": {
|
||||
|
|
@ -73,22 +77,18 @@
|
|||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"OUSED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"PADOUTUSED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"INTERMDISABLE_SEL:GND": {
|
||||
"from_pin": "GND",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"DIFFI_INUSED:0": {
|
||||
"TUSED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"IBUFDISABLE_SEL:GND": {
|
||||
"from_pin": "GND",
|
||||
"to_pin": "OUT"
|
||||
}
|
||||
},
|
||||
"type": "IOB33"
|
||||
}
|
||||
}
|
||||
|
|
@ -1,64 +1,76 @@
|
|||
{
|
||||
"site_pins": {
|
||||
"T_OUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DIFFI_IN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DIFFO_OUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PD_INT_EN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DIFF_TERM_INT_EN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PADOUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"IBUFDISABLE": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"KEEPER_INT_EN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"INTERMDISABLE": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PU_INT_EN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O_OUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"O_IN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"T_IN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"I": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"O": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DIFFO_IN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DIFFO_OUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DIFF_TERM_INT_EN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"I": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"IBUFDISABLE": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"INTERMDISABLE": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"KEEPER_INT_EN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O_IN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O_OUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PADOUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PD_INT_EN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PU_INT_EN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"T": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"T_IN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"T_OUT": {
|
||||
"direction": "OUT"
|
||||
}
|
||||
},
|
||||
"site_pips": {
|
||||
"INTERMDISABLE_SEL:GND": {
|
||||
"DIFFI_INUSED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"DIFFO_OUTUSED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"IBUFDISABLE_SEL:GND": {
|
||||
"from_pin": "GND",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"T_OUTUSED:0": {
|
||||
"from_pin": "0",
|
||||
"IBUFDISABLE_SEL:I": {
|
||||
"from_pin": "I",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"INTERMDISABLE_SEL:GND": {
|
||||
"from_pin": "GND",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"INTERMDISABLE_SEL:I": {
|
||||
|
|
@ -69,38 +81,26 @@
|
|||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"DIFFI_INUSED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"IBUFDISABLE_SEL:GND": {
|
||||
"from_pin": "GND",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"OUSED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"IBUFDISABLE_SEL:I": {
|
||||
"from_pin": "I",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"PADOUTUSED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"O_OUTUSED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"DIFFO_OUTUSED:0": {
|
||||
"PADOUTUSED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"TUSED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"T_OUTUSED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
}
|
||||
},
|
||||
"type": "IOB33M"
|
||||
}
|
||||
}
|
||||
|
|
@ -1,58 +1,78 @@
|
|||
{
|
||||
"site_pins": {
|
||||
"T_OUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DIFFI_IN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DIFFO_OUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PD_INT_EN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DIFF_TERM_INT_EN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PADOUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"IBUFDISABLE": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"KEEPER_INT_EN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"INTERMDISABLE": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PU_INT_EN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O_OUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"O_IN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"T_IN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"I": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"O": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DIFFO_IN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DIFFO_OUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DIFF_TERM_INT_EN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"I": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"IBUFDISABLE": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"INTERMDISABLE": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"KEEPER_INT_EN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O_IN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O_OUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PADOUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PD_INT_EN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PU_INT_EN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"T": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"T_IN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"T_OUT": {
|
||||
"direction": "OUT"
|
||||
}
|
||||
},
|
||||
"site_pips": {
|
||||
"DIFFI_INUSED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"DIFFO_INUSED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"IBUFDISABLE_SEL:GND": {
|
||||
"from_pin": "GND",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"IBUFDISABLE_SEL:I": {
|
||||
"from_pin": "I",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"INTERMDISABLE_SEL:GND": {
|
||||
"from_pin": "GND",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"INTERMDISABLE_SEL:I": {
|
||||
"from_pin": "I",
|
||||
"to_pin": "OUT"
|
||||
|
|
@ -61,35 +81,15 @@
|
|||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"OUTMUX:0": {
|
||||
"OINMUX:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"DIFFI_INUSED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"IBUFDISABLE_SEL:GND": {
|
||||
"from_pin": "GND",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"OINMUX:1": {
|
||||
"from_pin": "1",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"TINMUX:1": {
|
||||
"from_pin": "1",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"IBUFDISABLE_SEL:I": {
|
||||
"from_pin": "I",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"DIFFO_INUSED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"PADOUTUSED:0": {
|
||||
"OUTMUX:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
|
|
@ -97,18 +97,18 @@
|
|||
"from_pin": "1",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"OINMUX:0": {
|
||||
"PADOUTUSED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"INTERMDISABLE_SEL:GND": {
|
||||
"from_pin": "GND",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"TINMUX:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"TINMUX:1": {
|
||||
"from_pin": "1",
|
||||
"to_pin": "OUT"
|
||||
}
|
||||
},
|
||||
"type": "IOB33S"
|
||||
}
|
||||
}
|
||||
|
|
@ -6,4 +6,4 @@
|
|||
},
|
||||
"site_pips": {},
|
||||
"type": "IPAD"
|
||||
}
|
||||
}
|
||||
|
|
@ -1,244 +1,100 @@
|
|||
{
|
||||
"site_pins": {
|
||||
"TESTOUT13": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT10": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CLKOUT1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CLKOUT6": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT56": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT61": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT23": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO11": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN1": {
|
||||
"CLKFBIN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT17": {
|
||||
"CLKFBOUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO9": {
|
||||
"CLKFBOUTB": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN24": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN18": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT54": {
|
||||
"CLKFBSTOPPED": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN20": {
|
||||
"CLKIN1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT11": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN6": {
|
||||
"CLKIN2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT62": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN30": {
|
||||
"CLKINSEL": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DWE": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT27": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PSDONE": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN19": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DI4": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN13": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DI0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DO13": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT36": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DI3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN4": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT28": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DADDR5": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT9": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TMUXOUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT15": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DI6": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN14": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DI11": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT33": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN27": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT49": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT16": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT7": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DADDR4": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT50": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT5": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO12": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DI5": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT31": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN17": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DI2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT32": {
|
||||
"CLKINSTOPPED": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CLKOUT0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN9": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DI9": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PWRDWN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT59": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CLKOUT4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CLKINSTOPPED": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CLKOUT3B": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT24": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CLKFBOUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CLKOUT0B": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DRDY": {
|
||||
"CLKOUT1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT63": {
|
||||
"CLKOUT1B": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DADDR0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DCLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CLKFBSTOPPED": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT21": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DI15": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT57": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT47": {
|
||||
"CLKOUT2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CLKOUT2B": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT12": {
|
||||
"CLKOUT3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO0": {
|
||||
"CLKOUT3B": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DI7": {
|
||||
"CLKOUT4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CLKOUT5": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CLKOUT6": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DADDR0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT14": {
|
||||
"direction": "OUT"
|
||||
"DADDR1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DADDR2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DADDR3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DADDR4": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DADDR5": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DADDR6": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DCLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DEN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DI0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DI1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DI10": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DI11": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DI12": {
|
||||
"direction": "IN"
|
||||
|
|
@ -246,284 +102,420 @@
|
|||
"DI13": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN25": {
|
||||
"DI14": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CLKOUT3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO14": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO7": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN0": {
|
||||
"DI15": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT40": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CLKIN1": {
|
||||
"DI2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PSCLK": {
|
||||
"DI3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DADDR1": {
|
||||
"DI4": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT45": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN26": {
|
||||
"DI5": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT60": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"LOCKED": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT55": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT41": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DI10": {
|
||||
"DI6": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN15": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DADDR3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN8": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DEN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT53": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT37": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CLKOUT5": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN22": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DADDR6": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN29": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT51": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT29": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CLKFBOUTB": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT39": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO15": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT38": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT35": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN16": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN11": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DADDR2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT58": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PSEN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN5": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT18": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT52": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN7": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT42": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO5": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CLKOUT1B": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN21": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DO6": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CLKFBIN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN31": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"RST": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT6": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT8": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN28": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT25": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT22": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DI1": {
|
||||
"DI7": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DI8": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CLKOUT2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CLKIN2": {
|
||||
"DI9": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PSINCDEC": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DO8": {
|
||||
"DO0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT48": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT20": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN23": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT34": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CLKINSEL": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DI14": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT46": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN12": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DO3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT44": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT43": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN10": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT30": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT19": {
|
||||
"DO1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO10": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO11": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO12": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO13": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO14": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO15": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO5": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO6": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO7": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO8": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO9": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DRDY": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DWE": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"LOCKED": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PSCLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PSDONE": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PSEN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PSINCDEC": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PWRDWN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"RST": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN10": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN11": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN12": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN13": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN14": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN15": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN16": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN17": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN18": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN19": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN20": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN21": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN22": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN23": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN24": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN25": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN26": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN27": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN28": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN29": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN30": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN31": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN4": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN5": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN6": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN7": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN8": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN9": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT10": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT11": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT12": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT13": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT14": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT15": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT16": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT17": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT18": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT19": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT20": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT21": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT22": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT23": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT24": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT25": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT26": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT27": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT28": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT29": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT30": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT31": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT32": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT33": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT34": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT35": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT36": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT37": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT38": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT39": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT40": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT41": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT42": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT43": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT44": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT45": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT46": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT47": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT48": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT49": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT5": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT50": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT51": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT52": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT53": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT54": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT55": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT56": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT57": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT58": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT59": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT6": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT60": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT61": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT62": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT63": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT7": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT8": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT9": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TMUXOUT": {
|
||||
"direction": "OUT"
|
||||
}
|
||||
},
|
||||
"site_pips": {
|
||||
"CLKINSELINV:CLKINSEL_B": {
|
||||
"from_pin": "CLKINSEL_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"RSTINV:RST_B": {
|
||||
"from_pin": "RST_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"PSENINV:PSEN_B": {
|
||||
"from_pin": "PSEN_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"RSTINV:RST": {
|
||||
"from_pin": "RST",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"CLKINSELINV:CLKINSEL": {
|
||||
"from_pin": "CLKINSEL",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"CLKINSELINV:CLKINSEL_B": {
|
||||
"from_pin": "CLKINSEL_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"PSENINV:PSEN": {
|
||||
"from_pin": "PSEN",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"PSENINV:PSEN_B": {
|
||||
"from_pin": "PSEN_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"PSINCDECINV:PSINCDEC": {
|
||||
"from_pin": "PSINCDEC",
|
||||
"to_pin": "OUT"
|
||||
|
|
@ -539,7 +531,15 @@
|
|||
"PWRDWNINV:PWRDWN_B": {
|
||||
"from_pin": "PWRDWN_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"RSTINV:RST": {
|
||||
"from_pin": "RST",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"RSTINV:RST_B": {
|
||||
"from_pin": "RST_B",
|
||||
"to_pin": "OUT"
|
||||
}
|
||||
},
|
||||
"type": "MMCME2_ADV"
|
||||
}
|
||||
}
|
||||
|
|
@ -1,72 +1,24 @@
|
|||
{
|
||||
"site_pins": {
|
||||
"TFB": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TBYTEOUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"OFB": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"OQ": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CLKDIV": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TCE": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D6": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D4": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D8": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TBYTEIN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TQ": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SHIFTOUT1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"T2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CLKDIVFB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CLKDIVF": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"IOCLKGLITCH": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SHIFTIN1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SHIFTOUT2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D7": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CLKDIVB": {
|
||||
"CLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CLKB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D5": {
|
||||
"CLKDIV": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CLK": {
|
||||
"CLKDIVB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CLKDIVF": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CLKDIVFB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D2": {
|
||||
|
|
@ -75,57 +27,89 @@
|
|||
"D3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"T1": {
|
||||
"D4": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D5": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D6": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D7": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D8": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"IOCLKGLITCH": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"OCE": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"OFB": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"OQ": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"REV": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SHIFTIN1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SHIFTIN2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"OCE": {
|
||||
"direction": "IN"
|
||||
"SHIFTOUT1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"REV": {
|
||||
"direction": "IN"
|
||||
"SHIFTOUT2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SR": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"T1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"T2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"T3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"T4": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D1": {
|
||||
"TBYTEIN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TBYTEOUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TCE": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TFB": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TQ": {
|
||||
"direction": "OUT"
|
||||
}
|
||||
},
|
||||
"site_pips": {
|
||||
"T1USED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"OREVUSED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"CLKINV:CLK": {
|
||||
"from_pin": "CLK",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"TMUX:T1": {
|
||||
"from_pin": "T1",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"CLKINV:CLK_B": {
|
||||
"from_pin": "CLK_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"D2INV:D2": {
|
||||
"from_pin": "D2",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"OMUX:D1": {
|
||||
"D1INV:D1": {
|
||||
"from_pin": "D1",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
|
|
@ -133,11 +117,19 @@
|
|||
"from_pin": "D1_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"OMUX:OUTFF": {
|
||||
"from_pin": "OUTFF",
|
||||
"D2INV:D2": {
|
||||
"from_pin": "D2",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"TQUSED:0": {
|
||||
"D2INV:D2_B": {
|
||||
"from_pin": "D2_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"O1USED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"OCEUSED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
|
|
@ -145,51 +137,23 @@
|
|||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"TFBUSED:0": {
|
||||
"from_pin": "0",
|
||||
"OMUX:D1": {
|
||||
"from_pin": "D1",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"TCEUSED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"TMUX:TFF": {
|
||||
"from_pin": "TFF",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"O1USED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"T2INV:T2_B": {
|
||||
"from_pin": "T2_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"T1INV:T1_B": {
|
||||
"from_pin": "T1_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"T2INV:T2": {
|
||||
"from_pin": "T2",
|
||||
"OMUX:OUTFF": {
|
||||
"from_pin": "OUTFF",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"OQUSED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"TSRUSED:0": {
|
||||
"OREVUSED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"D1INV:D1": {
|
||||
"from_pin": "D1",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"OCEUSED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"TREVUSED:0": {
|
||||
"OSRUSED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
|
|
@ -197,14 +161,50 @@
|
|||
"from_pin": "T1",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"D2INV:D2_B": {
|
||||
"from_pin": "D2_B",
|
||||
"T1INV:T1_B": {
|
||||
"from_pin": "T1_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"OSRUSED:0": {
|
||||
"T1USED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"T2INV:T2": {
|
||||
"from_pin": "T2",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"T2INV:T2_B": {
|
||||
"from_pin": "T2_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"TCEUSED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"TFBUSED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"TMUX:T1": {
|
||||
"from_pin": "T1",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"TMUX:TFF": {
|
||||
"from_pin": "TFF",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"TQUSED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"TREVUSED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"TSRUSED:0": {
|
||||
"from_pin": "0",
|
||||
"to_pin": "OUT"
|
||||
}
|
||||
},
|
||||
"type": "OLOGICE3"
|
||||
}
|
||||
}
|
||||
|
|
@ -6,4 +6,4 @@
|
|||
},
|
||||
"site_pips": {},
|
||||
"type": "OPAD"
|
||||
}
|
||||
}
|
||||
|
|
@ -1,453 +1,453 @@
|
|||
{
|
||||
"site_pins": {
|
||||
"D02": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q73": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D91": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q00": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D41": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D05": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D81": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D70": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q60": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D34": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D44": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ALMOSTEMPTY": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D51": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D55": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D92": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTWRITEDISB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SCANIN0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D00": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D46": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D24": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q40": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D97": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D11": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D30": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q12": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D50": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D40": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D95": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"WREN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D77": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q55": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D67": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q93": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q52": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D56": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D36": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q67": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q21": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SCANOUT0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D62": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D16": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q51": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D31": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D86": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q92": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"ALMOSTFULL": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D42": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D90": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q31": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D26": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SCANIN1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SCANIN3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D15": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q70": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D57": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D87": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D61": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"RDEN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q66": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q91": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q71": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"RESET": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D72": {
|
||||
"D00": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D01": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D52": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q20": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D47": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q01": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D13": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D23": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q61": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D82": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D20": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTMODEB": {
|
||||
"D02": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D03": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q30": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q22": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D14": {
|
||||
"D04": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"EMPTY": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q03": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q63": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D35": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D80": {
|
||||
"D05": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D06": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q81": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D32": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D54": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q64": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q13": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D85": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"FULL": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D64": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D60": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SCANOUT1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q32": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D83": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D96": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D33": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D76": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q11": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"WRCLK": {
|
||||
"D07": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D10": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D71": {
|
||||
"D11": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D04": {
|
||||
"D12": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D45": {
|
||||
"D13": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTREADDISB": {
|
||||
"D14": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D74": {
|
||||
"D15": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D63": {
|
||||
"D16": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q33": {
|
||||
"direction": "OUT"
|
||||
"D17": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SCANOUT2": {
|
||||
"direction": "OUT"
|
||||
"D20": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D21": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q65": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D66": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q42": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D07": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SCANENB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q23": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"RDCLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q80": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q43": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q54": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q50": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SCANOUT3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q56": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q83": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D43": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q57": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q90": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q62": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D93": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D37": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D22": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q72": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D17": {
|
||||
"D23": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D65": {
|
||||
"D24": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D84": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q02": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D12": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D75": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D73": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D53": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q53": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SCANIN2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q10": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"D25": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D26": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D27": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"Q41": {
|
||||
"direction": "OUT"
|
||||
"D30": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D31": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D32": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D33": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D34": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D35": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D36": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D37": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D40": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D41": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D42": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D43": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D44": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D45": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D46": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D47": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D50": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D51": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D52": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D53": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D54": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D55": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D56": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D57": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D60": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D61": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D62": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D63": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D64": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D65": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D66": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D67": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D70": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D71": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D72": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D73": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D74": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D75": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D76": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D77": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D80": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D81": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D82": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D83": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D84": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D85": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D86": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D87": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D90": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D91": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D92": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D93": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D94": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D95": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D96": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"D97": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"EMPTY": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FULL": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q00": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q01": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q02": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q03": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q10": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q11": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q12": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q13": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q20": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q21": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q22": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q23": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q30": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q31": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q32": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q33": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q40": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q41": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q42": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q43": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q50": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q51": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q52": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q53": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q54": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q55": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q56": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q57": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q60": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q61": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q62": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q63": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q64": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q65": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q66": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q67": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q70": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q71": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q72": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q73": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q80": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q81": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q82": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q83": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q90": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q91": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q92": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"Q93": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"RDCLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"RDEN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"RESET": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SCANENB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SCANIN0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SCANIN1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SCANIN2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SCANIN3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SCANOUT0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SCANOUT1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SCANOUT2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SCANOUT3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTMODEB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTREADDISB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTWRITEDISB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"WRCLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"WREN": {
|
||||
"direction": "IN"
|
||||
}
|
||||
},
|
||||
"site_pips": {},
|
||||
"type": "OUT_FIFO"
|
||||
}
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,150 +1,27 @@
|
|||
{
|
||||
"site_pins": {
|
||||
"FINEINC": {
|
||||
"BURSTPENDING": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"STG1REGL7": {
|
||||
"BURSTPENDINGPHY": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN3": {
|
||||
"COUNTERLOADEN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COUNTERLOADVAL0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SCANIN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COUNTERREADVAL1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"RANKSELPHY0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ENSTG1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"STG1READ": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"STG1REGR2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN6": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SCANOUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"STG1REGL0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"STG1INCDEC": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ICLKDIV": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"ENSTG1ADJUSTB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COUNTERREADVAL3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"WRENABLE": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"RANKSELPHY1": {
|
||||
"COUNTERLOADVAL1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COUNTERLOADVAL2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PHASELOCKED": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"COUNTERREADVAL0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN9": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ENCALIBPHY0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"RANKSEL1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COUNTERREADVAL2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"COUNTERLOADVAL3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DQSFOUND": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SCANCLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"RSTDQSFIND": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"STG1REGR7": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN11": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN7": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"FREQREFCLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SCANMODEB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"RST": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"STG1REGL6": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DIVIDERST": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COUNTERREADVAL5": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"ENCALIB1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SYSCLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN4": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"STG1REGL8": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"BURSTPENDING": {
|
||||
"COUNTERLOADVAL4": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COUNTERLOADVAL5": {
|
||||
|
|
@ -153,139 +30,262 @@
|
|||
"COUNTERREADEN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COUNTERLOADVAL1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"STG1REGR0": {
|
||||
"COUNTERREADVAL0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"STG1REGL5": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ISERDESRST": {
|
||||
"COUNTERREADVAL1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SELCALORSTG1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT2": {
|
||||
"COUNTERREADVAL2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"STG1REGR3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"COUNTERLOADEN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"STG1OVERFLOW": {
|
||||
"COUNTERREADVAL3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"COUNTERREADVAL4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"BURSTPENDINGPHY": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"STG1REGR4": {
|
||||
"COUNTERREADVAL5": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PHASEREFCLK": {
|
||||
"DIVIDERST": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"RCLK": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"STG1REGR6": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"STG1REGR1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN5": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ICLK": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SCANENB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"STG1REGL1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"FINEOVERFLOW": {
|
||||
"DQSFOUND": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DQSOUTOFRANGE": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"ENCALIB0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"STG1REGL2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"STG1REGR8": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EDGEADV": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"STG1REGL4": {
|
||||
"ENCALIB0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ENCALIB1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ENCALIBPHY0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ENCALIBPHY1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"STG1REGR5": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"RANKSEL0": {
|
||||
"ENSTG1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COUNTERLOADVAL4": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SYNCIN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN10": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN8": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN12": {
|
||||
"ENSTG1ADJUSTB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"FINEENABLE": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"STG1REGL3": {
|
||||
"FINEINC": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"FINEOVERFLOW": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FREQREFCLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ICLK": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"ICLKDIV": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"ISERDESRST": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"MEMREFCLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHASELOCKED": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PHASEREFCLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"RANKSEL0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"RANKSEL1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"RANKSELPHY0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"RANKSELPHY1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"RCLK": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"RST": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"RSTDQSFIND": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SCANCLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SCANENB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SCANIN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SCANMODEB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SCANOUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SELCALORSTG1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"STG1INCDEC": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"STG1LOAD": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"STG1OVERFLOW": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"STG1READ": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"STG1REGL0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"STG1REGL1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"STG1REGL2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"STG1REGL3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"STG1REGL4": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"STG1REGL5": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"STG1REGL6": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"STG1REGL7": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"STG1REGL8": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"STG1REGR0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"STG1REGR1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"STG1REGR2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"STG1REGR3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"STG1REGR4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"STG1REGR5": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"STG1REGR6": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"STG1REGR7": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"STG1REGR8": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNCIN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SYSCLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN10": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN11": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN12": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN13": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"MEMREFCLK": {
|
||||
"TESTIN2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN4": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN5": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN6": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN7": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN8": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN9": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"WRENABLE": {
|
||||
"direction": "OUT"
|
||||
}
|
||||
},
|
||||
"site_pips": {
|
||||
"RSTINV:RST_B": {
|
||||
"from_pin": "RST_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"RSTINV:RST": {
|
||||
"from_pin": "RST",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"RSTINV:RST_B": {
|
||||
"from_pin": "RST_B",
|
||||
"to_pin": "OUT"
|
||||
}
|
||||
},
|
||||
"type": "PHASER_IN_PHY"
|
||||
}
|
||||
}
|
||||
|
|
@ -1,201 +1,150 @@
|
|||
{
|
||||
"site_pins": {
|
||||
"FINEINC": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN5": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COUNTERREADVAL5": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"ENCALIB1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COARSEOVERFLOW": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"COUNTERLOADVAL0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"OCLKDIV": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN4": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COUNTERREADVAL3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"BURSTPENDING": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COUNTERLOADVAL5": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COUNTERREADEN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DIVIDERST": {
|
||||
"BURSTPENDINGPHY": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COARSEENABLE": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COUNTERLOADVAL1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN15": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COARSEINC": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SELFINEOCLKDELAY": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FINEOVERFLOW": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN11": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DTSBUS0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SCANOUT": {
|
||||
"COARSEOVERFLOW": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"COUNTERLOADEN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"FINEENABLE": {
|
||||
"COUNTERLOADVAL0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN13": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COUNTERREADVAL4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"BURSTPENDINGPHY": {
|
||||
"COUNTERLOADVAL1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COUNTERLOADVAL2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHASEREFCLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"OCLK": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYSCLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN14": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"RDENABLE": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SCANIN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CTSBUS1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"COUNTERLOADVAL7": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DTSBUS1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"COUNTERREADVAL1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"COUNTERREADVAL8": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"COUNTERREADVAL7": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"RST": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN6": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ENCALIB0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COUNTERREADVAL0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"MEMREFCLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN9": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ENCALIBPHY0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"EDGEADV": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COUNTERREADVAL2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"COUNTERREADVAL6": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"ENCALIBPHY1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CTSBUS0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"COUNTERLOADVAL3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COUNTERLOADVAL4": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COUNTERLOADVAL5": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COUNTERLOADVAL6": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COUNTERLOADVAL7": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COUNTERLOADVAL8": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COUNTERREADEN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COUNTERREADVAL0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"COUNTERREADVAL1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"COUNTERREADVAL2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"COUNTERREADVAL3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"COUNTERREADVAL4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"COUNTERREADVAL5": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"COUNTERREADVAL6": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"COUNTERREADVAL7": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"COUNTERREADVAL8": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CTSBUS0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CTSBUS1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DIVIDERST": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DQSBUS0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DQSBUS1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DTSBUS0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DTSBUS1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"EDGEADV": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ENCALIB0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ENCALIB1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ENCALIBPHY0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"ENCALIBPHY1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"FINEENABLE": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"FINEINC": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"FINEOVERFLOW": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"FREQREFCLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"MEMREFCLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"OCLK": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"OCLKDELAYED": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"OCLKDIV": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"OSERDESRST": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNCIN": {
|
||||
"PHASEREFCLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COUNTERLOADVAL8": {
|
||||
"RDENABLE": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"RST": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SCANCLK": {
|
||||
|
|
@ -204,43 +153,94 @@
|
|||
"SCANENB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN8": {
|
||||
"SCANIN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DQSBUS0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN12": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DQSBUS1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SCANMODEB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN7": {
|
||||
"SCANOUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SELFINEOCLKDELAY": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SYNCIN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SYSCLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN10": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"FREQREFCLK": {
|
||||
"TESTIN11": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"COUNTERLOADVAL6": {
|
||||
"TESTIN12": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN13": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN14": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN15": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN4": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN5": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN6": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN7": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN8": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN9": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT3": {
|
||||
"direction": "OUT"
|
||||
}
|
||||
},
|
||||
"site_pips": {
|
||||
"RSTINV:RST_B": {
|
||||
"from_pin": "RST_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"RSTINV:RST": {
|
||||
"from_pin": "RST",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"RSTINV:RST_B": {
|
||||
"from_pin": "RST_B",
|
||||
"to_pin": "OUT"
|
||||
}
|
||||
},
|
||||
"type": "PHASER_OUT_PHY"
|
||||
}
|
||||
}
|
||||
|
|
@ -1,31 +1,22 @@
|
|||
{
|
||||
"site_pins": {
|
||||
"TESTIN5": {
|
||||
"CLKIN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT7": {
|
||||
"CLKOUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN0": {
|
||||
"LOCKED": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PWRDWN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"RST": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CLKOUT": {
|
||||
"direction": "OUT"
|
||||
"TESTIN0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN1": {
|
||||
"direction": "IN"
|
||||
|
|
@ -33,57 +24,66 @@
|
|||
"TESTIN2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PWRDWN": {
|
||||
"TESTIN3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TMUXOUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN6": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"LOCKED": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN4": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN5": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN6": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN7": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT5": {
|
||||
"TESTOUT0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CLKIN": {
|
||||
"direction": "IN"
|
||||
"TESTOUT1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT6": {
|
||||
"TESTOUT2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT5": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT6": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT7": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TMUXOUT": {
|
||||
"direction": "OUT"
|
||||
}
|
||||
},
|
||||
"site_pips": {
|
||||
"RSTINV:RST_B": {
|
||||
"from_pin": "RST_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"PWRDWNINV:PWRDWN": {
|
||||
"from_pin": "PWRDWN",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"PWRDWNINV:PWRDWN_B": {
|
||||
"from_pin": "PWRDWN_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"RSTINV:RST": {
|
||||
"from_pin": "RST",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"PWRDWNINV:PWRDWN_B": {
|
||||
"from_pin": "PWRDWN_B",
|
||||
"RSTINV:RST_B": {
|
||||
"from_pin": "RST_B",
|
||||
"to_pin": "OUT"
|
||||
}
|
||||
},
|
||||
"type": "PHASER_REF"
|
||||
}
|
||||
}
|
||||
|
|
@ -1,318 +1,318 @@
|
|||
{
|
||||
"site_pins": {
|
||||
"PHYCTLALMOSTFULL": {
|
||||
"AUXOUTPUT0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"AUXOUTPUT1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"AUXOUTPUT2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"AUXOUTPUT3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PHYCTLWD10": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTINPUT15": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"OUTBURSTPENDING0": {
|
||||
"INBURSTPENDING0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTINPUT0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWD0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWD16": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUTPUT5": {
|
||||
"INBURSTPENDING1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUTPUT14": {
|
||||
"INBURSTPENDING2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"INRANKC1": {
|
||||
"INBURSTPENDING3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"AUXOUTPUT0": {
|
||||
"INRANKA0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"INRANKA1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTINPUT10": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWD24": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWD8": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWD17": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTINPUT1": {
|
||||
"direction": "IN"
|
||||
"INRANKB0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"INRANKB1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PHYCTLWD7": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWD1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLFULL": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PHYCTLWD11": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWRENABLE": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWD26": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWD23": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"INBURSTPENDING0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"INRANKC0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PHYCTLWD19": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"INRANKB0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PHYCTLWD9": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTSELECT2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTINPUT4": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUTPUT10": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PHYCTLWD2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUTPUT12": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"INRANKD1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PHYCTLWD28": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUTPUT6": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PHYCTLEMPTY": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUTPUT8": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUTPUT7": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"OUTBURSTPENDING1": {
|
||||
"INRANKC1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"INRANKD0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUTPUT0": {
|
||||
"INRANKD1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PHYCTLWD5": {
|
||||
"MEMREFCLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTINPUT13": {
|
||||
"direction": "IN"
|
||||
"OUTBURSTPENDING0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"OUTBURSTPENDING1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"OUTBURSTPENDING2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"OUTBURSTPENDING3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTINPUT12": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"RESET": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWD31": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTINPUT3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWD29": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUTPUT4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUTPUT11": {
|
||||
"PCENABLECALIB0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PCENABLECALIB1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PHYCLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLALMOSTFULL": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PHYCTLEMPTY": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PHYCTLFULL": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PHYCTLMSTREMPTY": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLREADY": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PHYCTLWD0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWD1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWD10": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWD11": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWD12": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWD13": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWD14": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWD15": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWD16": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWD17": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWD18": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWD19": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWD2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWD20": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWD21": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWD22": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWD23": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWD24": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWD25": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWD26": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWD27": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWD28": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWD29": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWD3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWD30": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWD31": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWD4": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWD5": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWD6": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWD7": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWD8": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWD9": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWRENABLE": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PLLLOCK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"READCALIBENABLE": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"REFDLLLOCK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"RESET": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SCANENABLEN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SYNCIN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTINPUT0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTINPUT1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTINPUT10": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTINPUT11": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTINPUT12": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTINPUT13": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTINPUT14": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTINPUT15": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTINPUT2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTINPUT3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTINPUT4": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTINPUT5": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTINPUT6": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTINPUT7": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTINPUT8": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTINPUT9": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUTPUT0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUTPUT1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUTPUT10": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUTPUT11": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUTPUT12": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUTPUT13": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUTPUT14": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUTPUT15": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUTPUT2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUTPUT3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUTPUT4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUTPUT5": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUTPUT6": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUTPUT7": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUTPUT8": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUTPUT9": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"INBURSTPENDING3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PHYCTLWD3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PLLLOCK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"REFDLLLOCK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTINPUT7": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWD27": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWD6": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWD18": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTINPUT5": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"OUTBURSTPENDING2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PHYCTLWD21": {
|
||||
"TESTSELECT0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTSELECT1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"AUXOUTPUT2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PHYCTLWD15": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTINPUT6": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWD22": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTSELECT0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWD4": {
|
||||
"TESTSELECT2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"WRITECALIBENABLE": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"INBURSTPENDING1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTINPUT14": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWD12": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTINPUT8": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLMSTREMPTY": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWD20": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWD25": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUTPUT13": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"INRANKA0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"READCALIBENABLE": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PCENABLECALIB0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"AUXOUTPUT1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"SYNCIN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"SCANENABLEN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWD30": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTINPUT2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUTPUT1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"INBURSTPENDING2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUTPUT3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PHYCTLWD14": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTINPUT9": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLWD13": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PHYCTLREADY": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"MEMREFCLK": {
|
||||
"direction": "IN"
|
||||
}
|
||||
},
|
||||
"site_pips": {},
|
||||
"type": "PHY_CONTROL"
|
||||
}
|
||||
}
|
||||
|
|
@ -1,485 +1,477 @@
|
|||
{
|
||||
"site_pins": {
|
||||
"TESTOUT13": {
|
||||
"CLKFBIN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CLKFBOUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO1": {
|
||||
"direction": "OUT"
|
||||
"CLKIN1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT10": {
|
||||
"CLKIN2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CLKINSEL": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CLKOUT0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CLKOUT1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT41": {
|
||||
"CLKOUT2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DI5": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DO13": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT56": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT23": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO11": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT17": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO9": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN24": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN18": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT54": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN20": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT11": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN6": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT62": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DWE": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT22": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN19": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DI4": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN13": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DI0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DRDY": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT28": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DI3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DI13": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DADDR5": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT9": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT15": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DI6": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN14": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DI11": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT33": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN27": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT49": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT16": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT7": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DADDR4": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT50": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT5": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO12": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT57": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT31": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN17": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DI2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT32": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CLKOUT0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN9": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DI9": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PWRDWN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT59": {
|
||||
"CLKOUT3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CLKOUT4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TMUXOUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT24": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CLKFBOUT": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN4": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT63": {
|
||||
"CLKOUT5": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DADDR0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DCLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT21": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DI15": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CLKOUT5": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN11": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN7": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT12": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN30": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT36": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DI7": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT6": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN25": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CLKOUT3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO14": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT14": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CLKIN1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT38": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DADDR1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT45": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN26": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT60": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"LOCKED": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT55": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DI10": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN15": {
|
||||
"DADDR2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DADDR3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN8": {
|
||||
"DADDR4": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DEN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT53": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT27": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT37": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN31": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN22": {
|
||||
"DADDR5": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DADDR6": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN29": {
|
||||
"DCLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT51": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT29": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT39": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO15": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DI12": {
|
||||
"DEN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT35": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN16": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT47": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DADDR2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT58": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN5": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT18": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT52": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT40": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO5": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN21": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DO6": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CLKFBIN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"RST": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT8": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO7": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN28": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT25": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT61": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CLKINSEL": {
|
||||
"DI0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DI1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DI8": {
|
||||
"DI10": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CLKOUT2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CLKIN2": {
|
||||
"DI11": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DO8": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT48": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT20": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN23": {
|
||||
"DI12": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT34": {
|
||||
"direction": "OUT"
|
||||
"DI13": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DI14": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT46": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT42": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN12": {
|
||||
"DI15": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DO3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT44": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT43": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTIN10": {
|
||||
"DI2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT30": {
|
||||
"DI3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DI4": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DI5": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DI6": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DI7": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DI8": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DI9": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"DO0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT19": {
|
||||
"DO1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO10": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO11": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO12": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO13": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO14": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO15": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO5": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO6": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO7": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO8": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DO9": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DRDY": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DWE": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"LOCKED": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"PWRDWN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"RST": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN10": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN11": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN12": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN13": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN14": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN15": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN16": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN17": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN18": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN19": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN20": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN21": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN22": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN23": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN24": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN25": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN26": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN27": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN28": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN29": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN3": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN30": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN31": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN4": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN5": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN6": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN7": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN8": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTIN9": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"TESTOUT0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT10": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT11": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT12": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT13": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT14": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT15": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT16": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT17": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT18": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT19": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT20": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT21": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT22": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT23": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT24": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT25": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT26": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT27": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT28": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT29": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT30": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT31": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT32": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT33": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT34": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT35": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT36": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT37": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT38": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT39": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT40": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT41": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT42": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT43": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT44": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT45": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT46": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT47": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT48": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT49": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT5": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT50": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT51": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT52": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT53": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT54": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT55": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT56": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT57": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT58": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT59": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT6": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT60": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT61": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT62": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT63": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT7": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT8": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TESTOUT9": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"TMUXOUT": {
|
||||
"direction": "OUT"
|
||||
}
|
||||
},
|
||||
"site_pips": {
|
||||
"CLKINSELINV:CLKINSEL_B": {
|
||||
"from_pin": "CLKINSEL_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"RSTINV:RST_B": {
|
||||
"from_pin": "RST_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"RSTINV:RST": {
|
||||
"from_pin": "RST",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"CLKINSELINV:CLKINSEL": {
|
||||
"from_pin": "CLKINSEL",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"CLKINSELINV:CLKINSEL_B": {
|
||||
"from_pin": "CLKINSEL_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"PWRDWNINV:PWRDWN": {
|
||||
"from_pin": "PWRDWN",
|
||||
"to_pin": "OUT"
|
||||
|
|
@ -487,7 +479,15 @@
|
|||
"PWRDWNINV:PWRDWN_B": {
|
||||
"from_pin": "PWRDWN_B",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"RSTINV:RST": {
|
||||
"from_pin": "RST",
|
||||
"to_pin": "OUT"
|
||||
},
|
||||
"RSTINV:RST_B": {
|
||||
"from_pin": "RST_B",
|
||||
"to_pin": "OUT"
|
||||
}
|
||||
},
|
||||
"type": "PLLE2_ADV"
|
||||
}
|
||||
}
|
||||
|
|
@ -1,27 +1,27 @@
|
|||
{
|
||||
"site_pins": {
|
||||
"ODIV2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"ODIV4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"A0": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"EN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"A1": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"A2": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"EN": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"O": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"ODIV2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"ODIV4": {
|
||||
"direction": "OUT"
|
||||
}
|
||||
},
|
||||
"site_pips": {},
|
||||
"type": "PMV2"
|
||||
}
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -1,45 +1,45 @@
|
|||
{
|
||||
"site_pins": {
|
||||
"USRDONEO": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"CFGCLK": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"GTS": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PREQ": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CFGMCLK": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CLK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"PACK": {
|
||||
"direction": "IN"
|
||||
"EOS": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"GSR": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"GTS": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"KEYCLEARB": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"USRCCLKO": {
|
||||
"PACK": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"USRDONETS": {
|
||||
"PREQ": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"USRCCLKO": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"USRCCLKTS": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"EOS": {
|
||||
"direction": "OUT"
|
||||
"USRDONEO": {
|
||||
"direction": "IN"
|
||||
},
|
||||
"USRDONETS": {
|
||||
"direction": "IN"
|
||||
}
|
||||
},
|
||||
"site_pips": {},
|
||||
"type": "STARTUP"
|
||||
}
|
||||
}
|
||||
|
|
@ -9,4 +9,4 @@
|
|||
},
|
||||
"site_pips": {},
|
||||
"type": "TIEOFF"
|
||||
}
|
||||
}
|
||||
|
|
@ -1,108 +1,108 @@
|
|||
{
|
||||
"site_pins": {
|
||||
"DATA14": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA19": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA22": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATAVALID": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA8": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA13": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA12": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA7": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA5": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA10": {
|
||||
"CFGCLK": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA0": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA21": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA28": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA1": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA17": {
|
||||
"DATA10": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA23": {
|
||||
"DATA11": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"CFGCLK": {
|
||||
"DATA12": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA13": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA14": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA15": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA16": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA17": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA18": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA30": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA9": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA26": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA29": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA24": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA27": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA6": {
|
||||
"DATA19": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA2": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA20": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA21": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA22": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA23": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA24": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA25": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA26": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA27": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA28": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA29": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA3": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA30": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA31": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA4": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA15": {
|
||||
"DATA5": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA20": {
|
||||
"DATA6": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA11": {
|
||||
"DATA7": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA8": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATA9": {
|
||||
"direction": "OUT"
|
||||
},
|
||||
"DATAVALID": {
|
||||
"direction": "OUT"
|
||||
}
|
||||
},
|
||||
"site_pips": {},
|
||||
"type": "USR_ACCESS"
|
||||
}
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,476 +1,476 @@
|
|||
{
|
||||
"wires": [
|
||||
"INT_INTERFACE_EE4A0",
|
||||
"INT_INTERFACE_BRAM_IMUX30",
|
||||
"INT_INTERFACE_BYP1",
|
||||
"INT_INTERFACE_BRAM_IMUX18",
|
||||
"INT_INTERFACE_SE4C2",
|
||||
"INT_INTERFACE_NW2A1",
|
||||
"INT_INTERFACE_SW4A3",
|
||||
"INT_INTERFACE_WL1END3",
|
||||
"INT_INTERFACE_WW4END1",
|
||||
"INT_INTERFACE_FAN1",
|
||||
"INT_INTERFACE_NE4BEG2",
|
||||
"INT_INTERFACE_NE4BEG3",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B9",
|
||||
"INT_INTERFACE_WW4B3",
|
||||
"INT_INTERFACE_LH6",
|
||||
"INT_INTERFACE_WW4C3",
|
||||
"INT_INTERFACE_BRAM_IMUX19",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX0",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L20",
|
||||
"INT_INTERFACE_BRAM_IMUX39",
|
||||
"INT_INTERFACE_WW2END2",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B1",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L18",
|
||||
"INT_INTERFACE_NW4END0",
|
||||
"INT_INTERFACE_EE4C1",
|
||||
"INT_INTERFACE_LH3",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX39",
|
||||
"INT_INTERFACE_BRAM_IMUX3",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B15",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX22",
|
||||
"INT_INTERFACE_WW4A3",
|
||||
"INT_INTERFACE_WW4END2",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX24",
|
||||
"INT_INTERFACE_BRAM_IMUX43",
|
||||
"INT_INTERFACE_BRAM_IMUX21",
|
||||
"INT_INTERFACE_MONITOR_N",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B2",
|
||||
"INT_INTERFACE_NE2A3",
|
||||
"INT_INTERFACE_NW4A2",
|
||||
"INT_INTERFACE_BRAM_IMUX28",
|
||||
"INT_INTERFACE_EL1BEG3",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX32",
|
||||
"L_INT_INTER_DQS_IOTOPHASER",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L22",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX6",
|
||||
"INT_INTERFACE_SE2A2",
|
||||
"INT_INTERFACE_LH7",
|
||||
"INT_INTERFACE_EL1BEG0",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX25",
|
||||
"INT_INTERFACE_BRAM_IMUX14",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B6",
|
||||
"INT_INTERFACE_SW4A2",
|
||||
"INT_INTERFACE_SE4BEG0",
|
||||
"INT_INTERFACE_CLK1",
|
||||
"INT_INTERFACE_EE4BEG2",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B0",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L3",
|
||||
"INT_INTERFACE_PHASER_TO_IO_OCLKDIV",
|
||||
"INT_INTERFACE_NW4END1",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX35",
|
||||
"INT_INTERFACE_EL1BEG2",
|
||||
"INT_INTERFACE_BRAM_IMUX11",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX4",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX20",
|
||||
"INT_INTERFACE_NE4C3",
|
||||
"INT_INTERFACE_BRAM_IMUX40",
|
||||
"INT_INTERFACE_WW2A2",
|
||||
"INT_INTERFACE_BRAM_IMUX26",
|
||||
"INT_INTERFACE_LH8",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B3",
|
||||
"INT_INTERFACE_NW4A1",
|
||||
"INT_INTERFACE_BRAM_IMUX44",
|
||||
"INT_INTERFACE_FAN0",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L10",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B4",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX18",
|
||||
"INT_INTERFACE_MONITOR_P",
|
||||
"INT_INTERFACE_EE2BEG3",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX47",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L11",
|
||||
"INT_INTERFACE_BRAM_IMUX24",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L19",
|
||||
"INT_INTERFACE_SE4BEG2",
|
||||
"INT_INTERFACE_BRAM_IMUX27",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX12",
|
||||
"INT_INTERFACE_BRAM_IMUX4",
|
||||
"INT_INTERFACE_EE4C0",
|
||||
"INT_INTERFACE_WL1END2",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L5",
|
||||
"INT_INTERFACE_BRAM_IMUX8",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B17",
|
||||
"INT_INTERFACE_NW4END2",
|
||||
"INT_INTERFACE_BRAM_IMUX16",
|
||||
"INT_INTERFACE_BLOCK_OUTS_L_B0",
|
||||
"INT_INTERFACE_NW2A2",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX43",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L23",
|
||||
"INT_INTERFACE_WW4END3",
|
||||
"INT_INTERFACE_BYP2",
|
||||
"INT_INTERFACE_SE2A3",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L8",
|
||||
"INT_INTERFACE_EE4BEG1",
|
||||
"INT_INTERFACE_BRAM_IMUX35",
|
||||
"INT_INTERFACE_BRAM_IMUX41",
|
||||
"INT_INTERFACE_WW2END3",
|
||||
"INT_INTERFACE_SW4END2",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX3",
|
||||
"INT_INTERFACE_WW4END0",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B23",
|
||||
"INT_INTERFACE_CLK0",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX15",
|
||||
"INT_INTERFACE_NE2A1",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX37",
|
||||
"INT_INTERFACE_PHASER_TO_IO_ICLKDIV",
|
||||
"INT_INTERFACE_NE4BEG1",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX31",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B16",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX7",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX44",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX21",
|
||||
"INT_INTERFACE_BYP5",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L15",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B11",
|
||||
"INT_INTERFACE_WW4B1",
|
||||
"INT_INTERFACE_NE4BEG0",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX14",
|
||||
"INT_INTERFACE_NE4C2",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX26",
|
||||
"INT_INTERFACE_WR1END2",
|
||||
"INT_INTERFACE_BRAM_IMUX0",
|
||||
"INT_INTERFACE_EE2BEG0",
|
||||
"INT_INTERFACE_BRAM_IMUX31",
|
||||
"INT_INTERFACE_BRAM_IMUX34",
|
||||
"INT_INTERFACE_PHASER_TO_IO_ICLK",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L6",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B14",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX45",
|
||||
"INT_INTERFACE_ER1BEG0",
|
||||
"INT_INTERFACE_NW2A3",
|
||||
"INT_INTERFACE_BRAM_IMUX23",
|
||||
"INT_INTERFACE_WR1END3",
|
||||
"INT_INTERFACE_LH12",
|
||||
"INT_INTERFACE_ER1BEG2",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B7",
|
||||
"INT_INTERFACE_NE4C0",
|
||||
"INT_INTERFACE_SE4BEG3",
|
||||
"INT_INTERFACE_PHASER_TO_IO_OCLK",
|
||||
"INT_INTERFACE_WW2END0",
|
||||
"INT_INTERFACE_WW4C0",
|
||||
"INT_INTERFACE_WL1END1",
|
||||
"INT_INTERFACE_NW2A0",
|
||||
"INT_INTERFACE_EE2A2",
|
||||
"INT_INTERFACE_BRAM_IMUX22",
|
||||
"INT_INTERFACE_EE4B2",
|
||||
"INT_INTERFACE_FAN6",
|
||||
"INT_INTERFACE_WW2END1",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B20",
|
||||
"INT_INTERFACE_LH2",
|
||||
"INT_INTERFACE_NW4A0",
|
||||
"INT_INTERFACE_SW2A2",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L14",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX33",
|
||||
"INT_INTERFACE_EE4B1",
|
||||
"INT_INTERFACE_WW4B2",
|
||||
"INT_INTERFACE_EE4C2",
|
||||
"INT_INTERFACE_SW4END1",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B12",
|
||||
"INT_INTERFACE_PHASER_TO_IO_OCLK1X_90",
|
||||
"INT_INTERFACE_SW2A0",
|
||||
"INT_INTERFACE_BRAM_IMUX45",
|
||||
"INT_INTERFACE_SW2A3",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX10",
|
||||
"INT_INTERFACE_BRAM_IMUX32",
|
||||
"INT_INTERFACE_EE4A3",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L2",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L0",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX9",
|
||||
"INT_INTERFACE_BRAM_IMUX12",
|
||||
"INT_INTERFACE_BRAM_IMUX17",
|
||||
"INT_INTERFACE_BRAM_IMUX2",
|
||||
"INT_INTERFACE_ER1BEG3",
|
||||
"INT_INTERFACE_WW4A2",
|
||||
"INT_INTERFACE_NE4C1",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX29",
|
||||
"INT_INTERFACE_BLOCK_OUTS_L_B2",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B19",
|
||||
"INT_INTERFACE_NW4END3",
|
||||
"INT_INTERFACE_EE2A1",
|
||||
"INT_INTERFACE_WW2A3",
|
||||
"INT_INTERFACE_WL1END0",
|
||||
"INT_INTERFACE_BYP4",
|
||||
"INT_INTERFACE_WW2A1",
|
||||
"INT_INTERFACE_EE4B0",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX23",
|
||||
"INT_INTERFACE_FAN3",
|
||||
"INT_INTERFACE_EE4B3",
|
||||
"INT_INTERFACE_SW4A0",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX17",
|
||||
"INT_INTERFACE_SE2A1",
|
||||
"INT_INTERFACE_WW4C1",
|
||||
"INT_INTERFACE_FAN5",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX40",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX34",
|
||||
"INT_INTERFACE_EE2A3",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L21",
|
||||
"INT_INTERFACE_EE4BEG3",
|
||||
"INT_INTERFACE_EE2BEG2",
|
||||
"INT_INTERFACE_BRAM_IMUX6",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX2",
|
||||
"INT_INTERFACE_BLOCK_OUTS_L_B3",
|
||||
"INT_INTERFACE_WR1END0",
|
||||
"INT_INTERFACE_BRAM_IMUX10",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L13",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX36",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B10",
|
||||
"INT_INTERFACE_WW4B0",
|
||||
"INT_INTERFACE_SW2A1",
|
||||
"INT_INTERFACE_WW2A0",
|
||||
"INT_INTERFACE_EE4A2",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B13",
|
||||
"INT_INTERFACE_EE4BEG0",
|
||||
"INT_INTERFACE_BRAM_IMUX42",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L1",
|
||||
"INT_INTERFACE_BRAM_IMUX5",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX42",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L9",
|
||||
"INT_INTERFACE_FAN2",
|
||||
"INT_INTERFACE_NW4A3",
|
||||
"INT_INTERFACE_BRAM_IMUX38",
|
||||
"INT_INTERFACE_SE2A0",
|
||||
"INT_INTERFACE_BRAM_IMUX29",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B21",
|
||||
"INT_INTERFACE_BRAM_IMUX9",
|
||||
"INT_INTERFACE_EE4C3",
|
||||
"INT_INTERFACE_BYP3",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L16",
|
||||
"INT_INTERFACE_BRAM_IMUX46",
|
||||
"INT_INTERFACE_BRAM_IMUX37",
|
||||
"INT_INTERFACE_BRAM_IMUX20",
|
||||
"INT_INTERFACE_LH1",
|
||||
"INT_INTERFACE_BYP7",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX5",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX13",
|
||||
"INT_INTERFACE_BRAM_IMUX15",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B22",
|
||||
"INT_INTERFACE_SE4BEG1",
|
||||
"INT_INTERFACE_BRAM_IMUX47",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX38",
|
||||
"INT_INTERFACE_SE4C3",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L7",
|
||||
"INT_INTERFACE_BRAM_IMUX1",
|
||||
"INT_INTERFACE_NE2A2",
|
||||
"INT_INTERFACE_FAN7",
|
||||
"INT_INTERFACE_EE2BEG1",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX16",
|
||||
"INT_INTERFACE_WW4A0",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B8",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L17",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX19",
|
||||
"INT_INTERFACE_LH4",
|
||||
"INT_INTERFACE_SE4C1",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX1",
|
||||
"INT_INTERFACE_BRAM_IMUX25",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX30",
|
||||
"INT_INTERFACE_WW4A1",
|
||||
"INT_INTERFACE_BRAM_IMUX7",
|
||||
"INT_INTERFACE_FAN4",
|
||||
"INT_INTERFACE_CTRL0",
|
||||
"INT_INTERFACE_WW4C2",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B18",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX8",
|
||||
"INT_INTERFACE_LH9",
|
||||
"INT_INTERFACE_ER1BEG1",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L12",
|
||||
"INT_INTERFACE_WR1END1",
|
||||
"INT_INTERFACE_SW4END3",
|
||||
"INT_INTERFACE_BYP0",
|
||||
"INT_INTERFACE_EE2A0",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX46",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX11",
|
||||
"INT_INTERFACE_SE4C0",
|
||||
"INT_INTERFACE_LH5",
|
||||
"INT_INTERFACE_BRAM_IMUX33",
|
||||
"INT_INTERFACE_LH10",
|
||||
"INT_INTERFACE_BRAM_IMUX36",
|
||||
"INT_INTERFACE_NE2A0",
|
||||
"INT_INTERFACE_BLOCK_OUTS_L_B1",
|
||||
"INT_INTERFACE_EL1BEG1",
|
||||
"INT_INTERFACE_LH11",
|
||||
"INT_INTERFACE_SW4A1",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B5",
|
||||
"INT_INTERFACE_BYP6",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L4",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX28",
|
||||
"INT_INTERFACE_CTRL1",
|
||||
"INT_INTERFACE_BRAM_IMUX13",
|
||||
"INT_INTERFACE_EE4A1",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX41",
|
||||
"INT_INTERFACE_SW4END0",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX27"
|
||||
],
|
||||
"pips": {
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B4->>INT_INTERFACE_LOGIC_OUTS_L4": {
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B4",
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B0->>INT_INTERFACE_LOGIC_OUTS_L0": {
|
||||
"can_invert": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L0",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L4",
|
||||
"can_invert": "0"
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B1->>INT_INTERFACE_LOGIC_OUTS_L1": {
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B1",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"can_invert": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L1",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B17->>INT_INTERFACE_LOGIC_OUTS_L17": {
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B17",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L17",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B22->>INT_INTERFACE_LOGIC_OUTS_L22": {
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B22",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L22",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B14->>INT_INTERFACE_LOGIC_OUTS_L14": {
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B14",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L14",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B18->>INT_INTERFACE_LOGIC_OUTS_L18": {
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B18",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L18",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B21->>INT_INTERFACE_LOGIC_OUTS_L21": {
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B21",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L21",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B7->>INT_INTERFACE_LOGIC_OUTS_L7": {
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B7",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L7",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B2->>INT_INTERFACE_LOGIC_OUTS_L2": {
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B2",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L2",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B19->>INT_INTERFACE_LOGIC_OUTS_L19": {
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B19",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L19",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B11->>INT_INTERFACE_LOGIC_OUTS_L11": {
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B11",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L11",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B23->>INT_INTERFACE_LOGIC_OUTS_L23": {
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B23",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L23",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B3->>INT_INTERFACE_LOGIC_OUTS_L3": {
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B3",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L3",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B6->>INT_INTERFACE_LOGIC_OUTS_L6": {
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B6",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L6",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B0->>INT_INTERFACE_LOGIC_OUTS_L0": {
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B0",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L0",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B13->>INT_INTERFACE_LOGIC_OUTS_L13": {
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B13",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L13",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B12->>INT_INTERFACE_LOGIC_OUTS_L12": {
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B12",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L12",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B15->>INT_INTERFACE_LOGIC_OUTS_L15": {
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B15",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L15",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B20->>INT_INTERFACE_LOGIC_OUTS_L20": {
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B20",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L20",
|
||||
"can_invert": "0"
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B1"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B10->>INT_INTERFACE_LOGIC_OUTS_L10": {
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B10",
|
||||
"can_invert": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L10",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L10",
|
||||
"can_invert": "0"
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B10"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B11->>INT_INTERFACE_LOGIC_OUTS_L11": {
|
||||
"can_invert": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L11",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B11"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B12->>INT_INTERFACE_LOGIC_OUTS_L12": {
|
||||
"can_invert": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L12",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B12"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B13->>INT_INTERFACE_LOGIC_OUTS_L13": {
|
||||
"can_invert": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L13",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B13"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B14->>INT_INTERFACE_LOGIC_OUTS_L14": {
|
||||
"can_invert": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L14",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B14"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B15->>INT_INTERFACE_LOGIC_OUTS_L15": {
|
||||
"can_invert": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L15",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B15"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B16->>INT_INTERFACE_LOGIC_OUTS_L16": {
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B16",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"can_invert": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L16",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B9->>INT_INTERFACE_LOGIC_OUTS_L9": {
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B9",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L9",
|
||||
"can_invert": "0"
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B16"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B8->>INT_INTERFACE_LOGIC_OUTS_L8": {
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B8",
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B17->>INT_INTERFACE_LOGIC_OUTS_L17": {
|
||||
"can_invert": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L17",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L8",
|
||||
"can_invert": "0"
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B17"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B18->>INT_INTERFACE_LOGIC_OUTS_L18": {
|
||||
"can_invert": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L18",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B18"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B19->>INT_INTERFACE_LOGIC_OUTS_L19": {
|
||||
"can_invert": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L19",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B19"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B2->>INT_INTERFACE_LOGIC_OUTS_L2": {
|
||||
"can_invert": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L2",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B2"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B20->>INT_INTERFACE_LOGIC_OUTS_L20": {
|
||||
"can_invert": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L20",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B20"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B21->>INT_INTERFACE_LOGIC_OUTS_L21": {
|
||||
"can_invert": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L21",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B21"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B22->>INT_INTERFACE_LOGIC_OUTS_L22": {
|
||||
"can_invert": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L22",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B22"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B23->>INT_INTERFACE_LOGIC_OUTS_L23": {
|
||||
"can_invert": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L23",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B23"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B3->>INT_INTERFACE_LOGIC_OUTS_L3": {
|
||||
"can_invert": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L3",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B3"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B4->>INT_INTERFACE_LOGIC_OUTS_L4": {
|
||||
"can_invert": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L4",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B4"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B5->>INT_INTERFACE_LOGIC_OUTS_L5": {
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B5",
|
||||
"can_invert": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L5",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L5",
|
||||
"can_invert": "0"
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B5"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B6->>INT_INTERFACE_LOGIC_OUTS_L6": {
|
||||
"can_invert": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L6",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B6"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B7->>INT_INTERFACE_LOGIC_OUTS_L7": {
|
||||
"can_invert": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L7",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B7"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B8->>INT_INTERFACE_LOGIC_OUTS_L8": {
|
||||
"can_invert": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L8",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B8"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B9->>INT_INTERFACE_LOGIC_OUTS_L9": {
|
||||
"can_invert": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L9",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B9"
|
||||
}
|
||||
},
|
||||
"sites": [],
|
||||
"tile_type": "BRAM_INT_INTERFACE_L",
|
||||
"sites": []
|
||||
}
|
||||
"wires": [
|
||||
"INT_INTERFACE_BLOCK_OUTS_L_B0",
|
||||
"INT_INTERFACE_BLOCK_OUTS_L_B1",
|
||||
"INT_INTERFACE_BLOCK_OUTS_L_B2",
|
||||
"INT_INTERFACE_BLOCK_OUTS_L_B3",
|
||||
"INT_INTERFACE_BRAM_IMUX0",
|
||||
"INT_INTERFACE_BRAM_IMUX1",
|
||||
"INT_INTERFACE_BRAM_IMUX10",
|
||||
"INT_INTERFACE_BRAM_IMUX11",
|
||||
"INT_INTERFACE_BRAM_IMUX12",
|
||||
"INT_INTERFACE_BRAM_IMUX13",
|
||||
"INT_INTERFACE_BRAM_IMUX14",
|
||||
"INT_INTERFACE_BRAM_IMUX15",
|
||||
"INT_INTERFACE_BRAM_IMUX16",
|
||||
"INT_INTERFACE_BRAM_IMUX17",
|
||||
"INT_INTERFACE_BRAM_IMUX18",
|
||||
"INT_INTERFACE_BRAM_IMUX19",
|
||||
"INT_INTERFACE_BRAM_IMUX2",
|
||||
"INT_INTERFACE_BRAM_IMUX20",
|
||||
"INT_INTERFACE_BRAM_IMUX21",
|
||||
"INT_INTERFACE_BRAM_IMUX22",
|
||||
"INT_INTERFACE_BRAM_IMUX23",
|
||||
"INT_INTERFACE_BRAM_IMUX24",
|
||||
"INT_INTERFACE_BRAM_IMUX25",
|
||||
"INT_INTERFACE_BRAM_IMUX26",
|
||||
"INT_INTERFACE_BRAM_IMUX27",
|
||||
"INT_INTERFACE_BRAM_IMUX28",
|
||||
"INT_INTERFACE_BRAM_IMUX29",
|
||||
"INT_INTERFACE_BRAM_IMUX3",
|
||||
"INT_INTERFACE_BRAM_IMUX30",
|
||||
"INT_INTERFACE_BRAM_IMUX31",
|
||||
"INT_INTERFACE_BRAM_IMUX32",
|
||||
"INT_INTERFACE_BRAM_IMUX33",
|
||||
"INT_INTERFACE_BRAM_IMUX34",
|
||||
"INT_INTERFACE_BRAM_IMUX35",
|
||||
"INT_INTERFACE_BRAM_IMUX36",
|
||||
"INT_INTERFACE_BRAM_IMUX37",
|
||||
"INT_INTERFACE_BRAM_IMUX38",
|
||||
"INT_INTERFACE_BRAM_IMUX39",
|
||||
"INT_INTERFACE_BRAM_IMUX4",
|
||||
"INT_INTERFACE_BRAM_IMUX40",
|
||||
"INT_INTERFACE_BRAM_IMUX41",
|
||||
"INT_INTERFACE_BRAM_IMUX42",
|
||||
"INT_INTERFACE_BRAM_IMUX43",
|
||||
"INT_INTERFACE_BRAM_IMUX44",
|
||||
"INT_INTERFACE_BRAM_IMUX45",
|
||||
"INT_INTERFACE_BRAM_IMUX46",
|
||||
"INT_INTERFACE_BRAM_IMUX47",
|
||||
"INT_INTERFACE_BRAM_IMUX5",
|
||||
"INT_INTERFACE_BRAM_IMUX6",
|
||||
"INT_INTERFACE_BRAM_IMUX7",
|
||||
"INT_INTERFACE_BRAM_IMUX8",
|
||||
"INT_INTERFACE_BRAM_IMUX9",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX0",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX1",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX10",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX11",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX12",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX13",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX14",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX15",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX16",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX17",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX18",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX19",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX2",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX20",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX21",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX22",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX23",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX24",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX25",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX26",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX27",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX28",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX29",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX3",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX30",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX31",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX32",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX33",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX34",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX35",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX36",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX37",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX38",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX39",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX4",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX40",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX41",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX42",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX43",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX44",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX45",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX46",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX47",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX5",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX6",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX7",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX8",
|
||||
"INT_INTERFACE_BRAM_UTURN_IMUX9",
|
||||
"INT_INTERFACE_BYP0",
|
||||
"INT_INTERFACE_BYP1",
|
||||
"INT_INTERFACE_BYP2",
|
||||
"INT_INTERFACE_BYP3",
|
||||
"INT_INTERFACE_BYP4",
|
||||
"INT_INTERFACE_BYP5",
|
||||
"INT_INTERFACE_BYP6",
|
||||
"INT_INTERFACE_BYP7",
|
||||
"INT_INTERFACE_CLK0",
|
||||
"INT_INTERFACE_CLK1",
|
||||
"INT_INTERFACE_CTRL0",
|
||||
"INT_INTERFACE_CTRL1",
|
||||
"INT_INTERFACE_EE2A0",
|
||||
"INT_INTERFACE_EE2A1",
|
||||
"INT_INTERFACE_EE2A2",
|
||||
"INT_INTERFACE_EE2A3",
|
||||
"INT_INTERFACE_EE2BEG0",
|
||||
"INT_INTERFACE_EE2BEG1",
|
||||
"INT_INTERFACE_EE2BEG2",
|
||||
"INT_INTERFACE_EE2BEG3",
|
||||
"INT_INTERFACE_EE4A0",
|
||||
"INT_INTERFACE_EE4A1",
|
||||
"INT_INTERFACE_EE4A2",
|
||||
"INT_INTERFACE_EE4A3",
|
||||
"INT_INTERFACE_EE4B0",
|
||||
"INT_INTERFACE_EE4B1",
|
||||
"INT_INTERFACE_EE4B2",
|
||||
"INT_INTERFACE_EE4B3",
|
||||
"INT_INTERFACE_EE4BEG0",
|
||||
"INT_INTERFACE_EE4BEG1",
|
||||
"INT_INTERFACE_EE4BEG2",
|
||||
"INT_INTERFACE_EE4BEG3",
|
||||
"INT_INTERFACE_EE4C0",
|
||||
"INT_INTERFACE_EE4C1",
|
||||
"INT_INTERFACE_EE4C2",
|
||||
"INT_INTERFACE_EE4C3",
|
||||
"INT_INTERFACE_EL1BEG0",
|
||||
"INT_INTERFACE_EL1BEG1",
|
||||
"INT_INTERFACE_EL1BEG2",
|
||||
"INT_INTERFACE_EL1BEG3",
|
||||
"INT_INTERFACE_ER1BEG0",
|
||||
"INT_INTERFACE_ER1BEG1",
|
||||
"INT_INTERFACE_ER1BEG2",
|
||||
"INT_INTERFACE_ER1BEG3",
|
||||
"INT_INTERFACE_FAN0",
|
||||
"INT_INTERFACE_FAN1",
|
||||
"INT_INTERFACE_FAN2",
|
||||
"INT_INTERFACE_FAN3",
|
||||
"INT_INTERFACE_FAN4",
|
||||
"INT_INTERFACE_FAN5",
|
||||
"INT_INTERFACE_FAN6",
|
||||
"INT_INTERFACE_FAN7",
|
||||
"INT_INTERFACE_LH1",
|
||||
"INT_INTERFACE_LH10",
|
||||
"INT_INTERFACE_LH11",
|
||||
"INT_INTERFACE_LH12",
|
||||
"INT_INTERFACE_LH2",
|
||||
"INT_INTERFACE_LH3",
|
||||
"INT_INTERFACE_LH4",
|
||||
"INT_INTERFACE_LH5",
|
||||
"INT_INTERFACE_LH6",
|
||||
"INT_INTERFACE_LH7",
|
||||
"INT_INTERFACE_LH8",
|
||||
"INT_INTERFACE_LH9",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L0",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L1",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L10",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L11",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L12",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L13",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L14",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L15",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L16",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L17",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L18",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L19",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L2",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L20",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L21",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L22",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L23",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L3",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L4",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L5",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L6",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L7",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L8",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L9",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B0",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B1",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B10",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B11",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B12",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B13",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B14",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B15",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B16",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B17",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B18",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B19",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B2",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B20",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B21",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B22",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B23",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B3",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B4",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B5",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B6",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B7",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B8",
|
||||
"INT_INTERFACE_LOGIC_OUTS_L_B9",
|
||||
"INT_INTERFACE_MONITOR_N",
|
||||
"INT_INTERFACE_MONITOR_P",
|
||||
"INT_INTERFACE_NE2A0",
|
||||
"INT_INTERFACE_NE2A1",
|
||||
"INT_INTERFACE_NE2A2",
|
||||
"INT_INTERFACE_NE2A3",
|
||||
"INT_INTERFACE_NE4BEG0",
|
||||
"INT_INTERFACE_NE4BEG1",
|
||||
"INT_INTERFACE_NE4BEG2",
|
||||
"INT_INTERFACE_NE4BEG3",
|
||||
"INT_INTERFACE_NE4C0",
|
||||
"INT_INTERFACE_NE4C1",
|
||||
"INT_INTERFACE_NE4C2",
|
||||
"INT_INTERFACE_NE4C3",
|
||||
"INT_INTERFACE_NW2A0",
|
||||
"INT_INTERFACE_NW2A1",
|
||||
"INT_INTERFACE_NW2A2",
|
||||
"INT_INTERFACE_NW2A3",
|
||||
"INT_INTERFACE_NW4A0",
|
||||
"INT_INTERFACE_NW4A1",
|
||||
"INT_INTERFACE_NW4A2",
|
||||
"INT_INTERFACE_NW4A3",
|
||||
"INT_INTERFACE_NW4END0",
|
||||
"INT_INTERFACE_NW4END1",
|
||||
"INT_INTERFACE_NW4END2",
|
||||
"INT_INTERFACE_NW4END3",
|
||||
"INT_INTERFACE_PHASER_TO_IO_ICLK",
|
||||
"INT_INTERFACE_PHASER_TO_IO_ICLKDIV",
|
||||
"INT_INTERFACE_PHASER_TO_IO_OCLK",
|
||||
"INT_INTERFACE_PHASER_TO_IO_OCLK1X_90",
|
||||
"INT_INTERFACE_PHASER_TO_IO_OCLKDIV",
|
||||
"INT_INTERFACE_SE2A0",
|
||||
"INT_INTERFACE_SE2A1",
|
||||
"INT_INTERFACE_SE2A2",
|
||||
"INT_INTERFACE_SE2A3",
|
||||
"INT_INTERFACE_SE4BEG0",
|
||||
"INT_INTERFACE_SE4BEG1",
|
||||
"INT_INTERFACE_SE4BEG2",
|
||||
"INT_INTERFACE_SE4BEG3",
|
||||
"INT_INTERFACE_SE4C0",
|
||||
"INT_INTERFACE_SE4C1",
|
||||
"INT_INTERFACE_SE4C2",
|
||||
"INT_INTERFACE_SE4C3",
|
||||
"INT_INTERFACE_SW2A0",
|
||||
"INT_INTERFACE_SW2A1",
|
||||
"INT_INTERFACE_SW2A2",
|
||||
"INT_INTERFACE_SW2A3",
|
||||
"INT_INTERFACE_SW4A0",
|
||||
"INT_INTERFACE_SW4A1",
|
||||
"INT_INTERFACE_SW4A2",
|
||||
"INT_INTERFACE_SW4A3",
|
||||
"INT_INTERFACE_SW4END0",
|
||||
"INT_INTERFACE_SW4END1",
|
||||
"INT_INTERFACE_SW4END2",
|
||||
"INT_INTERFACE_SW4END3",
|
||||
"INT_INTERFACE_WL1END0",
|
||||
"INT_INTERFACE_WL1END1",
|
||||
"INT_INTERFACE_WL1END2",
|
||||
"INT_INTERFACE_WL1END3",
|
||||
"INT_INTERFACE_WR1END0",
|
||||
"INT_INTERFACE_WR1END1",
|
||||
"INT_INTERFACE_WR1END2",
|
||||
"INT_INTERFACE_WR1END3",
|
||||
"INT_INTERFACE_WW2A0",
|
||||
"INT_INTERFACE_WW2A1",
|
||||
"INT_INTERFACE_WW2A2",
|
||||
"INT_INTERFACE_WW2A3",
|
||||
"INT_INTERFACE_WW2END0",
|
||||
"INT_INTERFACE_WW2END1",
|
||||
"INT_INTERFACE_WW2END2",
|
||||
"INT_INTERFACE_WW2END3",
|
||||
"INT_INTERFACE_WW4A0",
|
||||
"INT_INTERFACE_WW4A1",
|
||||
"INT_INTERFACE_WW4A2",
|
||||
"INT_INTERFACE_WW4A3",
|
||||
"INT_INTERFACE_WW4B0",
|
||||
"INT_INTERFACE_WW4B1",
|
||||
"INT_INTERFACE_WW4B2",
|
||||
"INT_INTERFACE_WW4B3",
|
||||
"INT_INTERFACE_WW4C0",
|
||||
"INT_INTERFACE_WW4C1",
|
||||
"INT_INTERFACE_WW4C2",
|
||||
"INT_INTERFACE_WW4C3",
|
||||
"INT_INTERFACE_WW4END0",
|
||||
"INT_INTERFACE_WW4END1",
|
||||
"INT_INTERFACE_WW4END2",
|
||||
"INT_INTERFACE_WW4END3",
|
||||
"L_INT_INTER_DQS_IOTOPHASER"
|
||||
]
|
||||
}
|
||||
|
|
@ -1,476 +1,476 @@
|
|||
{
|
||||
"wires": [
|
||||
"INT_INTERFACE_EE4A0",
|
||||
"INT_INTERFACE_BRAM_IMUX30",
|
||||
"INT_INTERFACE_BYP1",
|
||||
"INT_INTERFACE_BRAM_IMUX18",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX5",
|
||||
"INT_INTERFACE_LOGIC_OUTS6",
|
||||
"INT_INTERFACE_SE4C2",
|
||||
"INT_INTERFACE_NW2A1",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX0",
|
||||
"INT_INTERFACE_SW4A3",
|
||||
"INT_INTERFACE_WL1END3",
|
||||
"INT_INTERFACE_WW4END1",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX14",
|
||||
"INT_INTERFACE_FAN1",
|
||||
"INT_INTERFACE_NE4BEG2",
|
||||
"INT_INTERFACE_NE4BEG3",
|
||||
"INT_INTERFACE_WW4B3",
|
||||
"INT_INTERFACE_LH6",
|
||||
"INT_INTERFACE_LOGIC_OUTS10",
|
||||
"INT_INTERFACE_LOGIC_OUTS3",
|
||||
"INT_INTERFACE_WW4C3",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B12",
|
||||
"INT_INTERFACE_BRAM_IMUX19",
|
||||
"INT_INTERFACE_BRAM_IMUX39",
|
||||
"INT_INTERFACE_WW2END2",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX30",
|
||||
"INT_INTERFACE_NW4END0",
|
||||
"INT_INTERFACE_EE4C1",
|
||||
"INT_INTERFACE_LH3",
|
||||
"INT_INTERFACE_BRAM_IMUX3",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX42",
|
||||
"INT_INTERFACE_WW4A3",
|
||||
"INT_INTERFACE_WW4END2",
|
||||
"INT_INTERFACE_BRAM_IMUX43",
|
||||
"INT_INTERFACE_BRAM_IMUX21",
|
||||
"INT_INTERFACE_LOGIC_OUTS15",
|
||||
"INT_INTERFACE_MONITOR_N",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX34",
|
||||
"INT_INTERFACE_NE2A3",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX10",
|
||||
"INT_INTERFACE_NW4A2",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B23",
|
||||
"INT_INTERFACE_LOGIC_OUTS7",
|
||||
"INT_INTERFACE_BRAM_IMUX28",
|
||||
"INT_INTERFACE_EL1BEG3",
|
||||
"L_INT_INTER_DQS_IOTOPHASER",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX17",
|
||||
"INT_INTERFACE_SE2A2",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX19",
|
||||
"INT_INTERFACE_LH7",
|
||||
"INT_INTERFACE_EL1BEG0",
|
||||
"INT_INTERFACE_BRAM_IMUX14",
|
||||
"INT_INTERFACE_LOGIC_OUTS21",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX22",
|
||||
"INT_INTERFACE_SW4A2",
|
||||
"INT_INTERFACE_SE4BEG0",
|
||||
"INT_INTERFACE_CLK1",
|
||||
"INT_INTERFACE_EE4BEG2",
|
||||
"INT_INTERFACE_BLOCK_OUTS_B3",
|
||||
"INT_INTERFACE_LOGIC_OUTS19",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX13",
|
||||
"INT_INTERFACE_PHASER_TO_IO_OCLKDIV",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX45",
|
||||
"INT_INTERFACE_LOGIC_OUTS12",
|
||||
"INT_INTERFACE_NW4END1",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX33",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B11",
|
||||
"INT_INTERFACE_BRAM_IMUX11",
|
||||
"INT_INTERFACE_BLOCK_OUTS_B2",
|
||||
"INT_INTERFACE_EL1BEG2",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX37",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B8",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX43",
|
||||
"INT_INTERFACE_BRAM_IMUX40",
|
||||
"INT_INTERFACE_NE4C3",
|
||||
"INT_INTERFACE_WW2A2",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B0",
|
||||
"INT_INTERFACE_BRAM_IMUX26",
|
||||
"INT_INTERFACE_LH8",
|
||||
"INT_INTERFACE_NW4A1",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX3",
|
||||
"INT_INTERFACE_BRAM_IMUX44",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX2",
|
||||
"INT_INTERFACE_FAN0",
|
||||
"INT_INTERFACE_LOGIC_OUTS0",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX29",
|
||||
"INT_INTERFACE_EE2BEG3",
|
||||
"INT_INTERFACE_MONITOR_P",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX12",
|
||||
"INT_INTERFACE_BRAM_IMUX24",
|
||||
"INT_INTERFACE_SE4BEG2",
|
||||
"INT_INTERFACE_BRAM_IMUX27",
|
||||
"INT_INTERFACE_BRAM_IMUX4",
|
||||
"INT_INTERFACE_EE4C0",
|
||||
"INT_INTERFACE_WL1END2",
|
||||
"INT_INTERFACE_BRAM_IMUX8",
|
||||
"INT_INTERFACE_NW4END2",
|
||||
"INT_INTERFACE_BLOCK_OUTS_B1",
|
||||
"INT_INTERFACE_BRAM_IMUX16",
|
||||
"INT_INTERFACE_NW2A2",
|
||||
"INT_INTERFACE_WW4END3",
|
||||
"INT_INTERFACE_BYP2",
|
||||
"INT_INTERFACE_SE2A3",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX8",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B20",
|
||||
"INT_INTERFACE_EE4BEG1",
|
||||
"INT_INTERFACE_BRAM_IMUX35",
|
||||
"INT_INTERFACE_BRAM_IMUX41",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX15",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX36",
|
||||
"INT_INTERFACE_SW4END2",
|
||||
"INT_INTERFACE_WW2END3",
|
||||
"INT_INTERFACE_WW4END0",
|
||||
"INT_INTERFACE_CLK0",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B9",
|
||||
"INT_INTERFACE_NE2A1",
|
||||
"INT_INTERFACE_PHASER_TO_IO_ICLKDIV",
|
||||
"INT_INTERFACE_LOGIC_OUTS4",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX39",
|
||||
"INT_INTERFACE_NE4BEG1",
|
||||
"INT_INTERFACE_LOGIC_OUTS18",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B13",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX4",
|
||||
"INT_INTERFACE_BYP5",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B1",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX21",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B6",
|
||||
"INT_INTERFACE_WW4B1",
|
||||
"INT_INTERFACE_NE4BEG0",
|
||||
"INT_INTERFACE_LOGIC_OUTS8",
|
||||
"INT_INTERFACE_NE4C2",
|
||||
"INT_INTERFACE_WR1END2",
|
||||
"INT_INTERFACE_BRAM_IMUX0",
|
||||
"INT_INTERFACE_EE2BEG0",
|
||||
"INT_INTERFACE_BRAM_IMUX31",
|
||||
"INT_INTERFACE_BRAM_IMUX34",
|
||||
"INT_INTERFACE_PHASER_TO_IO_ICLK",
|
||||
"INT_INTERFACE_LOGIC_OUTS1",
|
||||
"INT_INTERFACE_ER1BEG0",
|
||||
"INT_INTERFACE_LOGIC_OUTS13",
|
||||
"INT_INTERFACE_NW2A3",
|
||||
"INT_INTERFACE_BRAM_IMUX23",
|
||||
"INT_INTERFACE_WR1END3",
|
||||
"INT_INTERFACE_LH12",
|
||||
"INT_INTERFACE_LOGIC_OUTS5",
|
||||
"INT_INTERFACE_NE4C0",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX7",
|
||||
"INT_INTERFACE_SE4BEG3",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B4",
|
||||
"INT_INTERFACE_PHASER_TO_IO_OCLK",
|
||||
"INT_INTERFACE_WW2END0",
|
||||
"INT_INTERFACE_WW4C0",
|
||||
"INT_INTERFACE_WL1END1",
|
||||
"INT_INTERFACE_NW2A0",
|
||||
"INT_INTERFACE_EE2A2",
|
||||
"INT_INTERFACE_BRAM_IMUX22",
|
||||
"INT_INTERFACE_EE4B2",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX32",
|
||||
"INT_INTERFACE_FAN6",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B3",
|
||||
"INT_INTERFACE_WW2END1",
|
||||
"INT_INTERFACE_LH2",
|
||||
"INT_INTERFACE_NW4A0",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX24",
|
||||
"INT_INTERFACE_SW2A2",
|
||||
"INT_INTERFACE_EE4B1",
|
||||
"INT_INTERFACE_WW4B2",
|
||||
"INT_INTERFACE_EE4C2",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B14",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX41",
|
||||
"INT_INTERFACE_SW4END1",
|
||||
"INT_INTERFACE_PHASER_TO_IO_OCLK1X_90",
|
||||
"INT_INTERFACE_SW2A0",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX18",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX40",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B19",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX38",
|
||||
"INT_INTERFACE_BRAM_IMUX45",
|
||||
"INT_INTERFACE_SW2A3",
|
||||
"INT_INTERFACE_LOGIC_OUTS11",
|
||||
"INT_INTERFACE_BRAM_IMUX32",
|
||||
"INT_INTERFACE_EE4A3",
|
||||
"INT_INTERFACE_BRAM_IMUX12",
|
||||
"INT_INTERFACE_BRAM_IMUX17",
|
||||
"INT_INTERFACE_BRAM_IMUX2",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B2",
|
||||
"INT_INTERFACE_ER1BEG3",
|
||||
"INT_INTERFACE_WW4A2",
|
||||
"INT_INTERFACE_NE4C1",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B22",
|
||||
"INT_INTERFACE_NW4END3",
|
||||
"INT_INTERFACE_EE2A1",
|
||||
"INT_INTERFACE_WW2A3",
|
||||
"INT_INTERFACE_WL1END0",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B17",
|
||||
"INT_INTERFACE_WW2A1",
|
||||
"INT_INTERFACE_BYP4",
|
||||
"INT_INTERFACE_FAN3",
|
||||
"INT_INTERFACE_EE4B0",
|
||||
"INT_INTERFACE_EE4B3",
|
||||
"INT_INTERFACE_SW4A0",
|
||||
"INT_INTERFACE_SE2A1",
|
||||
"INT_INTERFACE_WW4C1",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX9",
|
||||
"INT_INTERFACE_FAN5",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX25",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B5",
|
||||
"INT_INTERFACE_EE2A3",
|
||||
"INT_INTERFACE_EE4BEG3",
|
||||
"INT_INTERFACE_EE2BEG2",
|
||||
"INT_INTERFACE_BRAM_IMUX6",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX6",
|
||||
"INT_INTERFACE_WR1END0",
|
||||
"INT_INTERFACE_BRAM_IMUX10",
|
||||
"INT_INTERFACE_LOGIC_OUTS23",
|
||||
"INT_INTERFACE_WW4B0",
|
||||
"INT_INTERFACE_SW2A1",
|
||||
"INT_INTERFACE_WW2A0",
|
||||
"INT_INTERFACE_EE4A2",
|
||||
"INT_INTERFACE_LOGIC_OUTS20",
|
||||
"INT_INTERFACE_EE4BEG0",
|
||||
"INT_INTERFACE_BRAM_IMUX42",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B18",
|
||||
"INT_INTERFACE_BRAM_IMUX5",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B10",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B21",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX28",
|
||||
"INT_INTERFACE_FAN2",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX20",
|
||||
"INT_INTERFACE_NW4A3",
|
||||
"INT_INTERFACE_BRAM_IMUX38",
|
||||
"INT_INTERFACE_LOGIC_OUTS14",
|
||||
"INT_INTERFACE_SE2A0",
|
||||
"INT_INTERFACE_BRAM_IMUX29",
|
||||
"INT_INTERFACE_BRAM_IMUX9",
|
||||
"INT_INTERFACE_EE4C3",
|
||||
"INT_INTERFACE_BYP3",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX11",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B7",
|
||||
"INT_INTERFACE_BRAM_IMUX46",
|
||||
"INT_INTERFACE_BRAM_IMUX37",
|
||||
"INT_INTERFACE_BRAM_IMUX20",
|
||||
"INT_INTERFACE_LH1",
|
||||
"INT_INTERFACE_BYP7",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B15",
|
||||
"INT_INTERFACE_BRAM_IMUX15",
|
||||
"INT_INTERFACE_SE4BEG1",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX44",
|
||||
"INT_INTERFACE_BRAM_IMUX47",
|
||||
"INT_INTERFACE_SE4C3",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX23",
|
||||
"INT_INTERFACE_BRAM_IMUX1",
|
||||
"INT_INTERFACE_NE2A2",
|
||||
"INT_INTERFACE_FAN7",
|
||||
"INT_INTERFACE_EE2BEG1",
|
||||
"INT_INTERFACE_WW4A0",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX35",
|
||||
"INT_INTERFACE_LH4",
|
||||
"INT_INTERFACE_LOGIC_OUTS17",
|
||||
"INT_INTERFACE_SE4C1",
|
||||
"INT_INTERFACE_BRAM_IMUX25",
|
||||
"INT_INTERFACE_BRAM_IMUX7",
|
||||
"INT_INTERFACE_LOGIC_OUTS16",
|
||||
"INT_INTERFACE_WW4A1",
|
||||
"INT_INTERFACE_FAN4",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX31",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX27",
|
||||
"INT_INTERFACE_CTRL0",
|
||||
"INT_INTERFACE_WW4C2",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX47",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX26",
|
||||
"INT_INTERFACE_LH9",
|
||||
"INT_INTERFACE_ER1BEG1",
|
||||
"INT_INTERFACE_WR1END1",
|
||||
"INT_INTERFACE_LOGIC_OUTS22",
|
||||
"INT_INTERFACE_SW4END3",
|
||||
"INT_INTERFACE_BYP0",
|
||||
"INT_INTERFACE_SE4C0",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX16",
|
||||
"INT_INTERFACE_LH5",
|
||||
"INT_INTERFACE_LH10",
|
||||
"INT_INTERFACE_EE2A0",
|
||||
"INT_INTERFACE_BRAM_IMUX33",
|
||||
"INT_INTERFACE_LH11",
|
||||
"INT_INTERFACE_BRAM_IMUX36",
|
||||
"INT_INTERFACE_NE2A0",
|
||||
"INT_INTERFACE_EL1BEG1",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX46",
|
||||
"INT_INTERFACE_SW4A1",
|
||||
"INT_INTERFACE_BLOCK_OUTS_B0",
|
||||
"INT_INTERFACE_LOGIC_OUTS9",
|
||||
"INT_INTERFACE_BYP6",
|
||||
"INT_INTERFACE_CTRL1",
|
||||
"INT_INTERFACE_BRAM_IMUX13",
|
||||
"INT_INTERFACE_EE4A1",
|
||||
"INT_INTERFACE_LOGIC_OUTS2",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B16",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX1",
|
||||
"INT_INTERFACE_SW4END0",
|
||||
"INT_INTERFACE_ER1BEG2"
|
||||
],
|
||||
"pips": {
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B10->>INT_INTERFACE_LOGIC_OUTS10": {
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B10",
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B0->>INT_INTERFACE_LOGIC_OUTS0": {
|
||||
"can_invert": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS0",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS10",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B16->>INT_INTERFACE_LOGIC_OUTS16": {
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B16",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS16",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B4->>INT_INTERFACE_LOGIC_OUTS4": {
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B4",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS4",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B7->>INT_INTERFACE_LOGIC_OUTS7": {
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B7",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS7",
|
||||
"can_invert": "0"
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B1->>INT_INTERFACE_LOGIC_OUTS1": {
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B1",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"can_invert": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS1",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B12->>INT_INTERFACE_LOGIC_OUTS12": {
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B12",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS12",
|
||||
"can_invert": "0"
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B1"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B5->>INT_INTERFACE_LOGIC_OUTS5": {
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B5",
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B10->>INT_INTERFACE_LOGIC_OUTS10": {
|
||||
"can_invert": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS10",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS5",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B15->>INT_INTERFACE_LOGIC_OUTS15": {
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B15",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS15",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B18->>INT_INTERFACE_LOGIC_OUTS18": {
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B18",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS18",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B2->>INT_INTERFACE_LOGIC_OUTS2": {
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B2",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS2",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B19->>INT_INTERFACE_LOGIC_OUTS19": {
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B19",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS19",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B6->>INT_INTERFACE_LOGIC_OUTS6": {
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B6",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS6",
|
||||
"can_invert": "0"
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B10"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B11->>INT_INTERFACE_LOGIC_OUTS11": {
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B11",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"can_invert": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS11",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B8->>INT_INTERFACE_LOGIC_OUTS8": {
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B8",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS8",
|
||||
"can_invert": "0"
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B11"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B3->>INT_INTERFACE_LOGIC_OUTS3": {
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B3",
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B12->>INT_INTERFACE_LOGIC_OUTS12": {
|
||||
"can_invert": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS12",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS3",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B21->>INT_INTERFACE_LOGIC_OUTS21": {
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B21",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS21",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B20->>INT_INTERFACE_LOGIC_OUTS20": {
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B20",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS20",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B14->>INT_INTERFACE_LOGIC_OUTS14": {
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B14",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS14",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B17->>INT_INTERFACE_LOGIC_OUTS17": {
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B17",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS17",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B9->>INT_INTERFACE_LOGIC_OUTS9": {
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B9",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS9",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B23->>INT_INTERFACE_LOGIC_OUTS23": {
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B23",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS23",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B22->>INT_INTERFACE_LOGIC_OUTS22": {
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B22",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS22",
|
||||
"can_invert": "0"
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B12"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B13->>INT_INTERFACE_LOGIC_OUTS13": {
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B13",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"can_invert": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS13",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B0->>INT_INTERFACE_LOGIC_OUTS0": {
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B0",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS0",
|
||||
"can_invert": "0"
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B13"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B14->>INT_INTERFACE_LOGIC_OUTS14": {
|
||||
"can_invert": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS14",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B14"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B15->>INT_INTERFACE_LOGIC_OUTS15": {
|
||||
"can_invert": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS15",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B15"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B16->>INT_INTERFACE_LOGIC_OUTS16": {
|
||||
"can_invert": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS16",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B16"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B17->>INT_INTERFACE_LOGIC_OUTS17": {
|
||||
"can_invert": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS17",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B17"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B18->>INT_INTERFACE_LOGIC_OUTS18": {
|
||||
"can_invert": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS18",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B18"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B19->>INT_INTERFACE_LOGIC_OUTS19": {
|
||||
"can_invert": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS19",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B19"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B2->>INT_INTERFACE_LOGIC_OUTS2": {
|
||||
"can_invert": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS2",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B2"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B20->>INT_INTERFACE_LOGIC_OUTS20": {
|
||||
"can_invert": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS20",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B20"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B21->>INT_INTERFACE_LOGIC_OUTS21": {
|
||||
"can_invert": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS21",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B21"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B22->>INT_INTERFACE_LOGIC_OUTS22": {
|
||||
"can_invert": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS22",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B22"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B23->>INT_INTERFACE_LOGIC_OUTS23": {
|
||||
"can_invert": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS23",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B23"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B3->>INT_INTERFACE_LOGIC_OUTS3": {
|
||||
"can_invert": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS3",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B3"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B4->>INT_INTERFACE_LOGIC_OUTS4": {
|
||||
"can_invert": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS4",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B4"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B5->>INT_INTERFACE_LOGIC_OUTS5": {
|
||||
"can_invert": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS5",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B5"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B6->>INT_INTERFACE_LOGIC_OUTS6": {
|
||||
"can_invert": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS6",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B6"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B7->>INT_INTERFACE_LOGIC_OUTS7": {
|
||||
"can_invert": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS7",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B7"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B8->>INT_INTERFACE_LOGIC_OUTS8": {
|
||||
"can_invert": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS8",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B8"
|
||||
},
|
||||
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B9->>INT_INTERFACE_LOGIC_OUTS9": {
|
||||
"can_invert": "0",
|
||||
"dst_wire": "INT_INTERFACE_LOGIC_OUTS9",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B9"
|
||||
}
|
||||
},
|
||||
"sites": [],
|
||||
"tile_type": "BRAM_INT_INTERFACE_R",
|
||||
"sites": []
|
||||
}
|
||||
"wires": [
|
||||
"INT_INTERFACE_BLOCK_OUTS_B0",
|
||||
"INT_INTERFACE_BLOCK_OUTS_B1",
|
||||
"INT_INTERFACE_BLOCK_OUTS_B2",
|
||||
"INT_INTERFACE_BLOCK_OUTS_B3",
|
||||
"INT_INTERFACE_BRAM_IMUX0",
|
||||
"INT_INTERFACE_BRAM_IMUX1",
|
||||
"INT_INTERFACE_BRAM_IMUX10",
|
||||
"INT_INTERFACE_BRAM_IMUX11",
|
||||
"INT_INTERFACE_BRAM_IMUX12",
|
||||
"INT_INTERFACE_BRAM_IMUX13",
|
||||
"INT_INTERFACE_BRAM_IMUX14",
|
||||
"INT_INTERFACE_BRAM_IMUX15",
|
||||
"INT_INTERFACE_BRAM_IMUX16",
|
||||
"INT_INTERFACE_BRAM_IMUX17",
|
||||
"INT_INTERFACE_BRAM_IMUX18",
|
||||
"INT_INTERFACE_BRAM_IMUX19",
|
||||
"INT_INTERFACE_BRAM_IMUX2",
|
||||
"INT_INTERFACE_BRAM_IMUX20",
|
||||
"INT_INTERFACE_BRAM_IMUX21",
|
||||
"INT_INTERFACE_BRAM_IMUX22",
|
||||
"INT_INTERFACE_BRAM_IMUX23",
|
||||
"INT_INTERFACE_BRAM_IMUX24",
|
||||
"INT_INTERFACE_BRAM_IMUX25",
|
||||
"INT_INTERFACE_BRAM_IMUX26",
|
||||
"INT_INTERFACE_BRAM_IMUX27",
|
||||
"INT_INTERFACE_BRAM_IMUX28",
|
||||
"INT_INTERFACE_BRAM_IMUX29",
|
||||
"INT_INTERFACE_BRAM_IMUX3",
|
||||
"INT_INTERFACE_BRAM_IMUX30",
|
||||
"INT_INTERFACE_BRAM_IMUX31",
|
||||
"INT_INTERFACE_BRAM_IMUX32",
|
||||
"INT_INTERFACE_BRAM_IMUX33",
|
||||
"INT_INTERFACE_BRAM_IMUX34",
|
||||
"INT_INTERFACE_BRAM_IMUX35",
|
||||
"INT_INTERFACE_BRAM_IMUX36",
|
||||
"INT_INTERFACE_BRAM_IMUX37",
|
||||
"INT_INTERFACE_BRAM_IMUX38",
|
||||
"INT_INTERFACE_BRAM_IMUX39",
|
||||
"INT_INTERFACE_BRAM_IMUX4",
|
||||
"INT_INTERFACE_BRAM_IMUX40",
|
||||
"INT_INTERFACE_BRAM_IMUX41",
|
||||
"INT_INTERFACE_BRAM_IMUX42",
|
||||
"INT_INTERFACE_BRAM_IMUX43",
|
||||
"INT_INTERFACE_BRAM_IMUX44",
|
||||
"INT_INTERFACE_BRAM_IMUX45",
|
||||
"INT_INTERFACE_BRAM_IMUX46",
|
||||
"INT_INTERFACE_BRAM_IMUX47",
|
||||
"INT_INTERFACE_BRAM_IMUX5",
|
||||
"INT_INTERFACE_BRAM_IMUX6",
|
||||
"INT_INTERFACE_BRAM_IMUX7",
|
||||
"INT_INTERFACE_BRAM_IMUX8",
|
||||
"INT_INTERFACE_BRAM_IMUX9",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX0",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX1",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX10",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX11",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX12",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX13",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX14",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX15",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX16",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX17",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX18",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX19",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX2",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX20",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX21",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX22",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX23",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX24",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX25",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX26",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX27",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX28",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX29",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX3",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX30",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX31",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX32",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX33",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX34",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX35",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX36",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX37",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX38",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX39",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX4",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX40",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX41",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX42",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX43",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX44",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX45",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX46",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX47",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX5",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX6",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX7",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX8",
|
||||
"INT_INTERFACE_BRAM_UTURN_R_IMUX9",
|
||||
"INT_INTERFACE_BYP0",
|
||||
"INT_INTERFACE_BYP1",
|
||||
"INT_INTERFACE_BYP2",
|
||||
"INT_INTERFACE_BYP3",
|
||||
"INT_INTERFACE_BYP4",
|
||||
"INT_INTERFACE_BYP5",
|
||||
"INT_INTERFACE_BYP6",
|
||||
"INT_INTERFACE_BYP7",
|
||||
"INT_INTERFACE_CLK0",
|
||||
"INT_INTERFACE_CLK1",
|
||||
"INT_INTERFACE_CTRL0",
|
||||
"INT_INTERFACE_CTRL1",
|
||||
"INT_INTERFACE_EE2A0",
|
||||
"INT_INTERFACE_EE2A1",
|
||||
"INT_INTERFACE_EE2A2",
|
||||
"INT_INTERFACE_EE2A3",
|
||||
"INT_INTERFACE_EE2BEG0",
|
||||
"INT_INTERFACE_EE2BEG1",
|
||||
"INT_INTERFACE_EE2BEG2",
|
||||
"INT_INTERFACE_EE2BEG3",
|
||||
"INT_INTERFACE_EE4A0",
|
||||
"INT_INTERFACE_EE4A1",
|
||||
"INT_INTERFACE_EE4A2",
|
||||
"INT_INTERFACE_EE4A3",
|
||||
"INT_INTERFACE_EE4B0",
|
||||
"INT_INTERFACE_EE4B1",
|
||||
"INT_INTERFACE_EE4B2",
|
||||
"INT_INTERFACE_EE4B3",
|
||||
"INT_INTERFACE_EE4BEG0",
|
||||
"INT_INTERFACE_EE4BEG1",
|
||||
"INT_INTERFACE_EE4BEG2",
|
||||
"INT_INTERFACE_EE4BEG3",
|
||||
"INT_INTERFACE_EE4C0",
|
||||
"INT_INTERFACE_EE4C1",
|
||||
"INT_INTERFACE_EE4C2",
|
||||
"INT_INTERFACE_EE4C3",
|
||||
"INT_INTERFACE_EL1BEG0",
|
||||
"INT_INTERFACE_EL1BEG1",
|
||||
"INT_INTERFACE_EL1BEG2",
|
||||
"INT_INTERFACE_EL1BEG3",
|
||||
"INT_INTERFACE_ER1BEG0",
|
||||
"INT_INTERFACE_ER1BEG1",
|
||||
"INT_INTERFACE_ER1BEG2",
|
||||
"INT_INTERFACE_ER1BEG3",
|
||||
"INT_INTERFACE_FAN0",
|
||||
"INT_INTERFACE_FAN1",
|
||||
"INT_INTERFACE_FAN2",
|
||||
"INT_INTERFACE_FAN3",
|
||||
"INT_INTERFACE_FAN4",
|
||||
"INT_INTERFACE_FAN5",
|
||||
"INT_INTERFACE_FAN6",
|
||||
"INT_INTERFACE_FAN7",
|
||||
"INT_INTERFACE_LH1",
|
||||
"INT_INTERFACE_LH10",
|
||||
"INT_INTERFACE_LH11",
|
||||
"INT_INTERFACE_LH12",
|
||||
"INT_INTERFACE_LH2",
|
||||
"INT_INTERFACE_LH3",
|
||||
"INT_INTERFACE_LH4",
|
||||
"INT_INTERFACE_LH5",
|
||||
"INT_INTERFACE_LH6",
|
||||
"INT_INTERFACE_LH7",
|
||||
"INT_INTERFACE_LH8",
|
||||
"INT_INTERFACE_LH9",
|
||||
"INT_INTERFACE_LOGIC_OUTS0",
|
||||
"INT_INTERFACE_LOGIC_OUTS1",
|
||||
"INT_INTERFACE_LOGIC_OUTS10",
|
||||
"INT_INTERFACE_LOGIC_OUTS11",
|
||||
"INT_INTERFACE_LOGIC_OUTS12",
|
||||
"INT_INTERFACE_LOGIC_OUTS13",
|
||||
"INT_INTERFACE_LOGIC_OUTS14",
|
||||
"INT_INTERFACE_LOGIC_OUTS15",
|
||||
"INT_INTERFACE_LOGIC_OUTS16",
|
||||
"INT_INTERFACE_LOGIC_OUTS17",
|
||||
"INT_INTERFACE_LOGIC_OUTS18",
|
||||
"INT_INTERFACE_LOGIC_OUTS19",
|
||||
"INT_INTERFACE_LOGIC_OUTS2",
|
||||
"INT_INTERFACE_LOGIC_OUTS20",
|
||||
"INT_INTERFACE_LOGIC_OUTS21",
|
||||
"INT_INTERFACE_LOGIC_OUTS22",
|
||||
"INT_INTERFACE_LOGIC_OUTS23",
|
||||
"INT_INTERFACE_LOGIC_OUTS3",
|
||||
"INT_INTERFACE_LOGIC_OUTS4",
|
||||
"INT_INTERFACE_LOGIC_OUTS5",
|
||||
"INT_INTERFACE_LOGIC_OUTS6",
|
||||
"INT_INTERFACE_LOGIC_OUTS7",
|
||||
"INT_INTERFACE_LOGIC_OUTS8",
|
||||
"INT_INTERFACE_LOGIC_OUTS9",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B0",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B1",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B10",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B11",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B12",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B13",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B14",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B15",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B16",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B17",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B18",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B19",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B2",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B20",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B21",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B22",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B23",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B3",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B4",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B5",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B6",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B7",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B8",
|
||||
"INT_INTERFACE_LOGIC_OUTS_B9",
|
||||
"INT_INTERFACE_MONITOR_N",
|
||||
"INT_INTERFACE_MONITOR_P",
|
||||
"INT_INTERFACE_NE2A0",
|
||||
"INT_INTERFACE_NE2A1",
|
||||
"INT_INTERFACE_NE2A2",
|
||||
"INT_INTERFACE_NE2A3",
|
||||
"INT_INTERFACE_NE4BEG0",
|
||||
"INT_INTERFACE_NE4BEG1",
|
||||
"INT_INTERFACE_NE4BEG2",
|
||||
"INT_INTERFACE_NE4BEG3",
|
||||
"INT_INTERFACE_NE4C0",
|
||||
"INT_INTERFACE_NE4C1",
|
||||
"INT_INTERFACE_NE4C2",
|
||||
"INT_INTERFACE_NE4C3",
|
||||
"INT_INTERFACE_NW2A0",
|
||||
"INT_INTERFACE_NW2A1",
|
||||
"INT_INTERFACE_NW2A2",
|
||||
"INT_INTERFACE_NW2A3",
|
||||
"INT_INTERFACE_NW4A0",
|
||||
"INT_INTERFACE_NW4A1",
|
||||
"INT_INTERFACE_NW4A2",
|
||||
"INT_INTERFACE_NW4A3",
|
||||
"INT_INTERFACE_NW4END0",
|
||||
"INT_INTERFACE_NW4END1",
|
||||
"INT_INTERFACE_NW4END2",
|
||||
"INT_INTERFACE_NW4END3",
|
||||
"INT_INTERFACE_PHASER_TO_IO_ICLK",
|
||||
"INT_INTERFACE_PHASER_TO_IO_ICLKDIV",
|
||||
"INT_INTERFACE_PHASER_TO_IO_OCLK",
|
||||
"INT_INTERFACE_PHASER_TO_IO_OCLK1X_90",
|
||||
"INT_INTERFACE_PHASER_TO_IO_OCLKDIV",
|
||||
"INT_INTERFACE_SE2A0",
|
||||
"INT_INTERFACE_SE2A1",
|
||||
"INT_INTERFACE_SE2A2",
|
||||
"INT_INTERFACE_SE2A3",
|
||||
"INT_INTERFACE_SE4BEG0",
|
||||
"INT_INTERFACE_SE4BEG1",
|
||||
"INT_INTERFACE_SE4BEG2",
|
||||
"INT_INTERFACE_SE4BEG3",
|
||||
"INT_INTERFACE_SE4C0",
|
||||
"INT_INTERFACE_SE4C1",
|
||||
"INT_INTERFACE_SE4C2",
|
||||
"INT_INTERFACE_SE4C3",
|
||||
"INT_INTERFACE_SW2A0",
|
||||
"INT_INTERFACE_SW2A1",
|
||||
"INT_INTERFACE_SW2A2",
|
||||
"INT_INTERFACE_SW2A3",
|
||||
"INT_INTERFACE_SW4A0",
|
||||
"INT_INTERFACE_SW4A1",
|
||||
"INT_INTERFACE_SW4A2",
|
||||
"INT_INTERFACE_SW4A3",
|
||||
"INT_INTERFACE_SW4END0",
|
||||
"INT_INTERFACE_SW4END1",
|
||||
"INT_INTERFACE_SW4END2",
|
||||
"INT_INTERFACE_SW4END3",
|
||||
"INT_INTERFACE_WL1END0",
|
||||
"INT_INTERFACE_WL1END1",
|
||||
"INT_INTERFACE_WL1END2",
|
||||
"INT_INTERFACE_WL1END3",
|
||||
"INT_INTERFACE_WR1END0",
|
||||
"INT_INTERFACE_WR1END1",
|
||||
"INT_INTERFACE_WR1END2",
|
||||
"INT_INTERFACE_WR1END3",
|
||||
"INT_INTERFACE_WW2A0",
|
||||
"INT_INTERFACE_WW2A1",
|
||||
"INT_INTERFACE_WW2A2",
|
||||
"INT_INTERFACE_WW2A3",
|
||||
"INT_INTERFACE_WW2END0",
|
||||
"INT_INTERFACE_WW2END1",
|
||||
"INT_INTERFACE_WW2END2",
|
||||
"INT_INTERFACE_WW2END3",
|
||||
"INT_INTERFACE_WW4A0",
|
||||
"INT_INTERFACE_WW4A1",
|
||||
"INT_INTERFACE_WW4A2",
|
||||
"INT_INTERFACE_WW4A3",
|
||||
"INT_INTERFACE_WW4B0",
|
||||
"INT_INTERFACE_WW4B1",
|
||||
"INT_INTERFACE_WW4B2",
|
||||
"INT_INTERFACE_WW4B3",
|
||||
"INT_INTERFACE_WW4C0",
|
||||
"INT_INTERFACE_WW4C1",
|
||||
"INT_INTERFACE_WW4C2",
|
||||
"INT_INTERFACE_WW4C3",
|
||||
"INT_INTERFACE_WW4END0",
|
||||
"INT_INTERFACE_WW4END1",
|
||||
"INT_INTERFACE_WW4END2",
|
||||
"INT_INTERFACE_WW4END3",
|
||||
"L_INT_INTER_DQS_IOTOPHASER"
|
||||
]
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -1,71 +1,71 @@
|
|||
{
|
||||
"wires": [
|
||||
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU14",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU3",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU5",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU1",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU8",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU3",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU7",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU9",
|
||||
"BRKH_BRAM_CASCADEB_R",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU6",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU3",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU11",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU2",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU13",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU6",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU8",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU0",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU13",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU2",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU5",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU9",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU1",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU1",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU14",
|
||||
"BRKH_BRAM_CASCADEB_L",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU7",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU11",
|
||||
"BRKH_BRAM_CASCADEA_L",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU11",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU14",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU1",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU9",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU12",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU12",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU9",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU0",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU8",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU2",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU10",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU3",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU6",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU10",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU12",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU4",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU4",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU6",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU14",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU4",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU10",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU2",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU13",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU11",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU0",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU10",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU13",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU0",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU7",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU5",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU5",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU8",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU12",
|
||||
"BRKH_BRAM_CASCADEA_R",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU4",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU7"
|
||||
],
|
||||
"pips": {},
|
||||
"sites": [],
|
||||
"tile_type": "BRKH_BRAM",
|
||||
"sites": []
|
||||
}
|
||||
"wires": [
|
||||
"BRKH_BRAM_CASCADEA_L",
|
||||
"BRKH_BRAM_CASCADEA_R",
|
||||
"BRKH_BRAM_CASCADEB_L",
|
||||
"BRKH_BRAM_CASCADEB_R",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU0",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU1",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU10",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU11",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU12",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU13",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU14",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU2",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU3",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU4",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU5",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU6",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU7",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU8",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU9",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU0",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU1",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU10",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU11",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU12",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU13",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU14",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU2",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU3",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU4",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU5",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU6",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU7",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU8",
|
||||
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU9",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU0",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU1",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU10",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU11",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU12",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU13",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU14",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU2",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU3",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU4",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU5",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU6",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU7",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU8",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU9",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU0",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU1",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU10",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU11",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU12",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU13",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU14",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU2",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU3",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU4",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU5",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU6",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU7",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU8",
|
||||
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU9"
|
||||
]
|
||||
}
|
||||
|
|
@ -1,125 +1,125 @@
|
|||
{
|
||||
"wires": [
|
||||
"B_TERM_UTURN_INT_SS2A1",
|
||||
"B_TERM_UTURN_INT_SW6C0",
|
||||
"B_TERM_UTURN_INT_LV3",
|
||||
"B_TERM_UTURN_INT_LVB_L1",
|
||||
"B_TERM_UTURN_INT_SE6A1",
|
||||
"B_TERM_UTURN_INT_SS6D0",
|
||||
"B_TERM_UTURN_INT_SS6B3",
|
||||
"B_TERM_UTURN_INT_LVB3",
|
||||
"B_TERM_UTURN_INT_SS6BEG1",
|
||||
"B_TERM_UTURN_INT_SS6E2",
|
||||
"B_TERM_UTURN_INT_LV_L5",
|
||||
"B_TERM_UTURN_INT_SE6D3",
|
||||
"B_TERM_UTURN_INT_LV_L2",
|
||||
"B_TERM_UTURN_INT_SE6C0",
|
||||
"B_TERM_UTURN_INT_LV5",
|
||||
"B_TERM_UTURN_INT_LV9",
|
||||
"B_TERM_UTURN_INT_SE6B3",
|
||||
"B_TERM_UTURN_INT_LV2",
|
||||
"B_TERM_UTURN_INT_LVB1",
|
||||
"B_TERM_UTURN_INT_ER1BEG0",
|
||||
"B_TERM_UTURN_INT_SS2BEG1",
|
||||
"B_TERM_UTURN_INT_SW2BEG2",
|
||||
"B_TERM_UTURN_INT_SS6BEG2",
|
||||
"B_TERM_UTURN_INT_FAN_BOUNCE0",
|
||||
"B_TERM_UTURN_INT_SW6END_N0_3",
|
||||
"B_TERM_UTURN_INT_LV7",
|
||||
"B_TERM_UTURN_INT_SS6B2",
|
||||
"B_TERM_UTURN_INT_SS6E3",
|
||||
"B_TERM_UTURN_INT_SW6C1",
|
||||
"B_TERM_UTURN_INT_LVB4",
|
||||
"B_TERM_UTURN_INT_SE6C2",
|
||||
"B_TERM_UTURN_INT_SS2BEG3",
|
||||
"B_TERM_UTURN_INT_LVB_L2",
|
||||
"B_TERM_UTURN_INT_SS6A2",
|
||||
"B_TERM_UTURN_INT_SW6D2",
|
||||
"B_TERM_UTURN_INT_SL1BEG1",
|
||||
"B_TERM_UTURN_INT_LV_L3",
|
||||
"B_TERM_UTURN_INT_SS2BEG2",
|
||||
"B_TERM_UTURN_INT_LVB2",
|
||||
"B_TERM_UTURN_INT_SR1BEG1",
|
||||
"B_TERM_UTURN_INT_ER1END_N3_3",
|
||||
"B_TERM_UTURN_INT_SS6A3",
|
||||
"B_TERM_UTURN_INT_SW6A1",
|
||||
"B_TERM_UTURN_INT_SL1BEG0",
|
||||
"B_TERM_UTURN_INT_SS6B1",
|
||||
"B_TERM_UTURN_INT_SE2BEG2",
|
||||
"B_TERM_UTURN_INT_LV_L9",
|
||||
"B_TERM_UTURN_INT_SS6BEG3",
|
||||
"B_TERM_UTURN_INT_SL1BEG3",
|
||||
"B_TERM_UTURN_INT_LV_L6",
|
||||
"B_TERM_UTURN_INT_LVB5",
|
||||
"B_TERM_UTURN_INT_LVB_L4",
|
||||
"B_TERM_UTURN_INT_SR1BEG2",
|
||||
"B_TERM_UTURN_INT_SS2A3",
|
||||
"B_TERM_UTURN_INT_SS6D1",
|
||||
"B_TERM_UTURN_INT_LVB0",
|
||||
"B_TERM_UTURN_INT_LV_L4",
|
||||
"B_TERM_UTURN_INT_SS6C3",
|
||||
"B_TERM_UTURN_INT_FAN_BOUNCE4",
|
||||
"B_TERM_UTURN_INT_SW6C3",
|
||||
"B_TERM_UTURN_INT_LV6",
|
||||
"B_TERM_UTURN_INT_SS6BEG0",
|
||||
"B_TERM_UTURN_INT_LV_L7",
|
||||
"B_TERM_UTURN_INT_SW6B0",
|
||||
"B_TERM_UTURN_INT_SS6D3",
|
||||
"B_TERM_UTURN_INT_FAN_BOUNCE2",
|
||||
"B_TERM_UTURN_INT_SS6D2",
|
||||
"B_TERM_UTURN_INT_SW6D3",
|
||||
"B_TERM_UTURN_INT_SL1BEG2",
|
||||
"B_TERM_UTURN_INT_SW6D1",
|
||||
"B_TERM_UTURN_INT_SS6C1",
|
||||
"B_TERM_UTURN_INT_LVB_L5",
|
||||
"B_TERM_UTURN_INT_SS2A2",
|
||||
"B_TERM_UTURN_INT_SS6E0",
|
||||
"B_TERM_UTURN_INT_SW2BEG1",
|
||||
"B_TERM_UTURN_INT_SW6A0",
|
||||
"B_TERM_UTURN_INT_SE2BEG0",
|
||||
"B_TERM_UTURN_INT_LV4",
|
||||
"B_TERM_UTURN_INT_SS6A0",
|
||||
"B_TERM_UTURN_INT_SW6A2",
|
||||
"B_TERM_UTURN_INT_SE6D2",
|
||||
"B_TERM_UTURN_INT_SE6C3",
|
||||
"B_TERM_UTURN_INT_FAN_BOUNCE6",
|
||||
"B_TERM_UTURN_INT_LV_L18",
|
||||
"B_TERM_UTURN_INT_LVB_L3",
|
||||
"B_TERM_UTURN_INT_LV18",
|
||||
"B_TERM_UTURN_INT_SR1BEG3",
|
||||
"B_TERM_UTURN_INT_SS6C0",
|
||||
"B_TERM_UTURN_INT_SE6D1",
|
||||
"B_TERM_UTURN_INT_SE6B1",
|
||||
"B_TERM_UTURN_INT_SE6A2",
|
||||
"B_TERM_UTURN_INT_SS2BEG0",
|
||||
"B_TERM_UTURN_INT_SW6B1",
|
||||
"B_TERM_UTURN_INT_SE6B2",
|
||||
"B_TERM_UTURN_INT_SE2BEG3",
|
||||
"B_TERM_UTURN_INT_WR1END0",
|
||||
"B_TERM_UTURN_INT_SW6B2",
|
||||
"B_TERM_UTURN_INT_SE6B0",
|
||||
"B_TERM_UTURN_INT_SS6C2",
|
||||
"B_TERM_UTURN_INT_SW2BEG3",
|
||||
"B_TERM_UTURN_INT_SE2BEG1",
|
||||
"B_TERM_UTURN_INT_SE6A3",
|
||||
"B_TERM_UTURN_INT_SE6D0",
|
||||
"B_TERM_UTURN_INT_SS6A1",
|
||||
"B_TERM_UTURN_INT_LV8",
|
||||
"B_TERM_UTURN_INT_LVB_L0",
|
||||
"B_TERM_UTURN_INT_WR1BEG0",
|
||||
"B_TERM_UTURN_INT_SW2BEG0",
|
||||
"B_TERM_UTURN_INT_SW6A3",
|
||||
"B_TERM_UTURN_INT_SE6C1",
|
||||
"B_TERM_UTURN_INT_LV_L8",
|
||||
"B_TERM_UTURN_INT_SS6B0",
|
||||
"B_TERM_UTURN_INT_SW6B3",
|
||||
"B_TERM_UTURN_INT_SW6C2",
|
||||
"B_TERM_UTURN_INT_SW6D0",
|
||||
"B_TERM_UTURN_INT_SS2A0",
|
||||
"B_TERM_UTURN_INT_SS6E1",
|
||||
"B_TERM_UTURN_INT_SE6A0"
|
||||
],
|
||||
"pips": {},
|
||||
"sites": [],
|
||||
"tile_type": "BRKH_B_TERM_INT",
|
||||
"sites": []
|
||||
}
|
||||
"wires": [
|
||||
"B_TERM_UTURN_INT_ER1BEG0",
|
||||
"B_TERM_UTURN_INT_ER1END_N3_3",
|
||||
"B_TERM_UTURN_INT_FAN_BOUNCE0",
|
||||
"B_TERM_UTURN_INT_FAN_BOUNCE2",
|
||||
"B_TERM_UTURN_INT_FAN_BOUNCE4",
|
||||
"B_TERM_UTURN_INT_FAN_BOUNCE6",
|
||||
"B_TERM_UTURN_INT_LV18",
|
||||
"B_TERM_UTURN_INT_LV2",
|
||||
"B_TERM_UTURN_INT_LV3",
|
||||
"B_TERM_UTURN_INT_LV4",
|
||||
"B_TERM_UTURN_INT_LV5",
|
||||
"B_TERM_UTURN_INT_LV6",
|
||||
"B_TERM_UTURN_INT_LV7",
|
||||
"B_TERM_UTURN_INT_LV8",
|
||||
"B_TERM_UTURN_INT_LV9",
|
||||
"B_TERM_UTURN_INT_LVB0",
|
||||
"B_TERM_UTURN_INT_LVB1",
|
||||
"B_TERM_UTURN_INT_LVB2",
|
||||
"B_TERM_UTURN_INT_LVB3",
|
||||
"B_TERM_UTURN_INT_LVB4",
|
||||
"B_TERM_UTURN_INT_LVB5",
|
||||
"B_TERM_UTURN_INT_LVB_L0",
|
||||
"B_TERM_UTURN_INT_LVB_L1",
|
||||
"B_TERM_UTURN_INT_LVB_L2",
|
||||
"B_TERM_UTURN_INT_LVB_L3",
|
||||
"B_TERM_UTURN_INT_LVB_L4",
|
||||
"B_TERM_UTURN_INT_LVB_L5",
|
||||
"B_TERM_UTURN_INT_LV_L18",
|
||||
"B_TERM_UTURN_INT_LV_L2",
|
||||
"B_TERM_UTURN_INT_LV_L3",
|
||||
"B_TERM_UTURN_INT_LV_L4",
|
||||
"B_TERM_UTURN_INT_LV_L5",
|
||||
"B_TERM_UTURN_INT_LV_L6",
|
||||
"B_TERM_UTURN_INT_LV_L7",
|
||||
"B_TERM_UTURN_INT_LV_L8",
|
||||
"B_TERM_UTURN_INT_LV_L9",
|
||||
"B_TERM_UTURN_INT_SE2BEG0",
|
||||
"B_TERM_UTURN_INT_SE2BEG1",
|
||||
"B_TERM_UTURN_INT_SE2BEG2",
|
||||
"B_TERM_UTURN_INT_SE2BEG3",
|
||||
"B_TERM_UTURN_INT_SE6A0",
|
||||
"B_TERM_UTURN_INT_SE6A1",
|
||||
"B_TERM_UTURN_INT_SE6A2",
|
||||
"B_TERM_UTURN_INT_SE6A3",
|
||||
"B_TERM_UTURN_INT_SE6B0",
|
||||
"B_TERM_UTURN_INT_SE6B1",
|
||||
"B_TERM_UTURN_INT_SE6B2",
|
||||
"B_TERM_UTURN_INT_SE6B3",
|
||||
"B_TERM_UTURN_INT_SE6C0",
|
||||
"B_TERM_UTURN_INT_SE6C1",
|
||||
"B_TERM_UTURN_INT_SE6C2",
|
||||
"B_TERM_UTURN_INT_SE6C3",
|
||||
"B_TERM_UTURN_INT_SE6D0",
|
||||
"B_TERM_UTURN_INT_SE6D1",
|
||||
"B_TERM_UTURN_INT_SE6D2",
|
||||
"B_TERM_UTURN_INT_SE6D3",
|
||||
"B_TERM_UTURN_INT_SL1BEG0",
|
||||
"B_TERM_UTURN_INT_SL1BEG1",
|
||||
"B_TERM_UTURN_INT_SL1BEG2",
|
||||
"B_TERM_UTURN_INT_SL1BEG3",
|
||||
"B_TERM_UTURN_INT_SR1BEG1",
|
||||
"B_TERM_UTURN_INT_SR1BEG2",
|
||||
"B_TERM_UTURN_INT_SR1BEG3",
|
||||
"B_TERM_UTURN_INT_SS2A0",
|
||||
"B_TERM_UTURN_INT_SS2A1",
|
||||
"B_TERM_UTURN_INT_SS2A2",
|
||||
"B_TERM_UTURN_INT_SS2A3",
|
||||
"B_TERM_UTURN_INT_SS2BEG0",
|
||||
"B_TERM_UTURN_INT_SS2BEG1",
|
||||
"B_TERM_UTURN_INT_SS2BEG2",
|
||||
"B_TERM_UTURN_INT_SS2BEG3",
|
||||
"B_TERM_UTURN_INT_SS6A0",
|
||||
"B_TERM_UTURN_INT_SS6A1",
|
||||
"B_TERM_UTURN_INT_SS6A2",
|
||||
"B_TERM_UTURN_INT_SS6A3",
|
||||
"B_TERM_UTURN_INT_SS6B0",
|
||||
"B_TERM_UTURN_INT_SS6B1",
|
||||
"B_TERM_UTURN_INT_SS6B2",
|
||||
"B_TERM_UTURN_INT_SS6B3",
|
||||
"B_TERM_UTURN_INT_SS6BEG0",
|
||||
"B_TERM_UTURN_INT_SS6BEG1",
|
||||
"B_TERM_UTURN_INT_SS6BEG2",
|
||||
"B_TERM_UTURN_INT_SS6BEG3",
|
||||
"B_TERM_UTURN_INT_SS6C0",
|
||||
"B_TERM_UTURN_INT_SS6C1",
|
||||
"B_TERM_UTURN_INT_SS6C2",
|
||||
"B_TERM_UTURN_INT_SS6C3",
|
||||
"B_TERM_UTURN_INT_SS6D0",
|
||||
"B_TERM_UTURN_INT_SS6D1",
|
||||
"B_TERM_UTURN_INT_SS6D2",
|
||||
"B_TERM_UTURN_INT_SS6D3",
|
||||
"B_TERM_UTURN_INT_SS6E0",
|
||||
"B_TERM_UTURN_INT_SS6E1",
|
||||
"B_TERM_UTURN_INT_SS6E2",
|
||||
"B_TERM_UTURN_INT_SS6E3",
|
||||
"B_TERM_UTURN_INT_SW2BEG0",
|
||||
"B_TERM_UTURN_INT_SW2BEG1",
|
||||
"B_TERM_UTURN_INT_SW2BEG2",
|
||||
"B_TERM_UTURN_INT_SW2BEG3",
|
||||
"B_TERM_UTURN_INT_SW6A0",
|
||||
"B_TERM_UTURN_INT_SW6A1",
|
||||
"B_TERM_UTURN_INT_SW6A2",
|
||||
"B_TERM_UTURN_INT_SW6A3",
|
||||
"B_TERM_UTURN_INT_SW6B0",
|
||||
"B_TERM_UTURN_INT_SW6B1",
|
||||
"B_TERM_UTURN_INT_SW6B2",
|
||||
"B_TERM_UTURN_INT_SW6B3",
|
||||
"B_TERM_UTURN_INT_SW6C0",
|
||||
"B_TERM_UTURN_INT_SW6C1",
|
||||
"B_TERM_UTURN_INT_SW6C2",
|
||||
"B_TERM_UTURN_INT_SW6C3",
|
||||
"B_TERM_UTURN_INT_SW6D0",
|
||||
"B_TERM_UTURN_INT_SW6D1",
|
||||
"B_TERM_UTURN_INT_SW6D2",
|
||||
"B_TERM_UTURN_INT_SW6D3",
|
||||
"B_TERM_UTURN_INT_SW6END_N0_3",
|
||||
"B_TERM_UTURN_INT_WR1BEG0",
|
||||
"B_TERM_UTURN_INT_WR1END0"
|
||||
]
|
||||
}
|
||||
|
|
@ -1,11 +1,11 @@
|
|||
{
|
||||
"pips": {},
|
||||
"sites": [],
|
||||
"tile_type": "BRKH_CLB",
|
||||
"wires": [
|
||||
"BRKH_CLB_COUT0_L",
|
||||
"BRKH_CLB_COUT0_R",
|
||||
"BRKH_CLB_COUT1_L",
|
||||
"BRKH_CLB_COUT0_L",
|
||||
"BRKH_CLB_COUT1_R"
|
||||
],
|
||||
"pips": {},
|
||||
"tile_type": "BRKH_CLB",
|
||||
"sites": []
|
||||
}
|
||||
]
|
||||
}
|
||||
|
|
@ -1,135 +1,135 @@
|
|||
{
|
||||
"wires": [
|
||||
"BRKH_CLK_CK_BUFG_CASC5",
|
||||
"BRKH_CLK_CK_GCLK7",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC10",
|
||||
"BRKH_CLK_CK_BUFG_CASC9",
|
||||
"BRKH_CLK_R_CK_GCLK5",
|
||||
"BRKH_CLK_CK_GCLK21",
|
||||
"BRKH_CLK_R_CK_GCLK2",
|
||||
"BRKH_CLK_CK_BUFG_CASC13",
|
||||
"BRKH_CLK_CK_GCLK15",
|
||||
"BRKH_CLK_CK_GCLK27",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC29",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC15",
|
||||
"BRKH_CLK_R_CK_GCLK14",
|
||||
"BRKH_CLK_R_CK_GCLK10",
|
||||
"BRKH_CLK_CK_BUFG_CASC14",
|
||||
"BRKH_CLK_CK_BUFG_CASC24",
|
||||
"BRKH_CLK_CK_GCLK12",
|
||||
"BRKH_CLK_CK_BUFG_CASC20",
|
||||
"BRKH_CLK_R_CK_GCLK26",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC26",
|
||||
"BRKH_CLK_R_CK_GCLK18",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC19",
|
||||
"BRKH_CLK_CK_GCLK11",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC6",
|
||||
"BRKH_CLK_CK_GCLK20",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC2",
|
||||
"BRKH_CLK_R_CK_GCLK22",
|
||||
"BRKH_CLK_CK_BUFG_CASC3",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC14",
|
||||
"BRKH_CLK_CK_BUFG_CASC15",
|
||||
"BRKH_CLK_CK_GCLK30",
|
||||
"BRKH_CLK_CK_BUFG_CASC31",
|
||||
"BRKH_CLK_CK_BUFG_CASC29",
|
||||
"BRKH_CLK_CK_BUFG_CASC23",
|
||||
"BRKH_CLK_CK_BUFG_CASC12",
|
||||
"BRKH_CLK_CK_GCLK18",
|
||||
"BRKH_CLK_R_CK_GCLK25",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC23",
|
||||
"BRKH_CLK_R_CK_GCLK3",
|
||||
"BRKH_CLK_CK_BUFG_CASC1",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC3",
|
||||
"BRKH_CLK_CK_GCLK23",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC1",
|
||||
"BRKH_CLK_CK_BUFG_CASC11",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC20",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC8",
|
||||
"BRKH_CLK_R_CK_GCLK20",
|
||||
"BRKH_CLK_CK_BUFG_CASC2",
|
||||
"BRKH_CLK_R_CK_GCLK15",
|
||||
"BRKH_CLK_R_CK_GCLK17",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC12",
|
||||
"BRKH_CLK_CK_GCLK25",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC11",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC21",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC30",
|
||||
"BRKH_CLK_R_CK_GCLK13",
|
||||
"BRKH_CLK_CK_GCLK13",
|
||||
"BRKH_CLK_CK_BUFG_CASC17",
|
||||
"BRKH_CLK_R_CK_GCLK8",
|
||||
"BRKH_CLK_CK_BUFG_CASC7",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC4",
|
||||
"BRKH_CLK_R_CK_GCLK27",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC25",
|
||||
"BRKH_CLK_R_CK_GCLK6",
|
||||
"BRKH_CLK_CK_BUFG_CASC8",
|
||||
"BRKH_CLK_CK_GCLK19",
|
||||
"BRKH_CLK_R_CK_GCLK7",
|
||||
"BRKH_CLK_R_CK_GCLK19",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC16",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC5",
|
||||
"BRKH_CLK_CK_BUFG_CASC19",
|
||||
"BRKH_CLK_CK_GCLK4",
|
||||
"BRKH_CLK_CK_GCLK26",
|
||||
"BRKH_CLK_CK_BUFG_CASC25",
|
||||
"BRKH_CLK_CK_BUFG_CASC22",
|
||||
"BRKH_CLK_R_CK_GCLK12",
|
||||
"BRKH_CLK_CK_GCLK29",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC27",
|
||||
"BRKH_CLK_CK_GCLK2",
|
||||
"BRKH_CLK_CK_BUFG_CASC21",
|
||||
"BRKH_CLK_R_CK_GCLK11",
|
||||
"BRKH_CLK_R_CK_GCLK21",
|
||||
"BRKH_CLK_R_CK_GCLK1",
|
||||
"BRKH_CLK_CK_GCLK1",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC18",
|
||||
"BRKH_CLK_CK_GCLK14",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC24",
|
||||
"BRKH_CLK_CK_BUFG_CASC16",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC28",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC7",
|
||||
"BRKH_CLK_R_CK_GCLK29",
|
||||
"BRKH_CLK_CK_BUFG_CASC30",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC22",
|
||||
"BRKH_CLK_CK_GCLK6",
|
||||
"BRKH_CLK_R_CK_GCLK23",
|
||||
"BRKH_CLK_CK_BUFG_CASC18",
|
||||
"BRKH_CLK_R_CK_GCLK0",
|
||||
"BRKH_CLK_CK_BUFG_CASC6",
|
||||
"BRKH_CLK_CK_GCLK28",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC31",
|
||||
"BRKH_CLK_CK_GCLK0",
|
||||
"BRKH_CLK_R_CK_GCLK16",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC17",
|
||||
"BRKH_CLK_R_CK_GCLK31",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC0",
|
||||
"BRKH_CLK_CK_BUFG_CASC26",
|
||||
"BRKH_CLK_R_CK_GCLK30",
|
||||
"BRKH_CLK_CK_GCLK17",
|
||||
"BRKH_CLK_CK_GCLK22",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC9",
|
||||
"BRKH_CLK_CK_BUFG_CASC10",
|
||||
"BRKH_CLK_CK_GCLK24",
|
||||
"BRKH_CLK_CK_GCLK8",
|
||||
"BRKH_CLK_R_CK_GCLK9",
|
||||
"BRKH_CLK_CK_GCLK5",
|
||||
"BRKH_CLK_CK_GCLK31",
|
||||
"BRKH_CLK_CK_GCLK10",
|
||||
"BRKH_CLK_CK_GCLK3",
|
||||
"BRKH_CLK_CK_BUFG_CASC0",
|
||||
"BRKH_CLK_R_CK_GCLK4",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC13",
|
||||
"BRKH_CLK_CK_BUFG_CASC4",
|
||||
"BRKH_CLK_R_CK_GCLK28",
|
||||
"BRKH_CLK_CK_BUFG_CASC27",
|
||||
"BRKH_CLK_R_CK_GCLK24",
|
||||
"BRKH_CLK_CK_GCLK16",
|
||||
"BRKH_CLK_CK_BUFG_CASC28",
|
||||
"BRKH_CLK_CK_GCLK9"
|
||||
],
|
||||
"pips": {},
|
||||
"sites": [],
|
||||
"tile_type": "BRKH_CLK",
|
||||
"sites": []
|
||||
}
|
||||
"wires": [
|
||||
"BRKH_CLK_CK_BUFG_CASC0",
|
||||
"BRKH_CLK_CK_BUFG_CASC1",
|
||||
"BRKH_CLK_CK_BUFG_CASC10",
|
||||
"BRKH_CLK_CK_BUFG_CASC11",
|
||||
"BRKH_CLK_CK_BUFG_CASC12",
|
||||
"BRKH_CLK_CK_BUFG_CASC13",
|
||||
"BRKH_CLK_CK_BUFG_CASC14",
|
||||
"BRKH_CLK_CK_BUFG_CASC15",
|
||||
"BRKH_CLK_CK_BUFG_CASC16",
|
||||
"BRKH_CLK_CK_BUFG_CASC17",
|
||||
"BRKH_CLK_CK_BUFG_CASC18",
|
||||
"BRKH_CLK_CK_BUFG_CASC19",
|
||||
"BRKH_CLK_CK_BUFG_CASC2",
|
||||
"BRKH_CLK_CK_BUFG_CASC20",
|
||||
"BRKH_CLK_CK_BUFG_CASC21",
|
||||
"BRKH_CLK_CK_BUFG_CASC22",
|
||||
"BRKH_CLK_CK_BUFG_CASC23",
|
||||
"BRKH_CLK_CK_BUFG_CASC24",
|
||||
"BRKH_CLK_CK_BUFG_CASC25",
|
||||
"BRKH_CLK_CK_BUFG_CASC26",
|
||||
"BRKH_CLK_CK_BUFG_CASC27",
|
||||
"BRKH_CLK_CK_BUFG_CASC28",
|
||||
"BRKH_CLK_CK_BUFG_CASC29",
|
||||
"BRKH_CLK_CK_BUFG_CASC3",
|
||||
"BRKH_CLK_CK_BUFG_CASC30",
|
||||
"BRKH_CLK_CK_BUFG_CASC31",
|
||||
"BRKH_CLK_CK_BUFG_CASC4",
|
||||
"BRKH_CLK_CK_BUFG_CASC5",
|
||||
"BRKH_CLK_CK_BUFG_CASC6",
|
||||
"BRKH_CLK_CK_BUFG_CASC7",
|
||||
"BRKH_CLK_CK_BUFG_CASC8",
|
||||
"BRKH_CLK_CK_BUFG_CASC9",
|
||||
"BRKH_CLK_CK_GCLK0",
|
||||
"BRKH_CLK_CK_GCLK1",
|
||||
"BRKH_CLK_CK_GCLK10",
|
||||
"BRKH_CLK_CK_GCLK11",
|
||||
"BRKH_CLK_CK_GCLK12",
|
||||
"BRKH_CLK_CK_GCLK13",
|
||||
"BRKH_CLK_CK_GCLK14",
|
||||
"BRKH_CLK_CK_GCLK15",
|
||||
"BRKH_CLK_CK_GCLK16",
|
||||
"BRKH_CLK_CK_GCLK17",
|
||||
"BRKH_CLK_CK_GCLK18",
|
||||
"BRKH_CLK_CK_GCLK19",
|
||||
"BRKH_CLK_CK_GCLK2",
|
||||
"BRKH_CLK_CK_GCLK20",
|
||||
"BRKH_CLK_CK_GCLK21",
|
||||
"BRKH_CLK_CK_GCLK22",
|
||||
"BRKH_CLK_CK_GCLK23",
|
||||
"BRKH_CLK_CK_GCLK24",
|
||||
"BRKH_CLK_CK_GCLK25",
|
||||
"BRKH_CLK_CK_GCLK26",
|
||||
"BRKH_CLK_CK_GCLK27",
|
||||
"BRKH_CLK_CK_GCLK28",
|
||||
"BRKH_CLK_CK_GCLK29",
|
||||
"BRKH_CLK_CK_GCLK3",
|
||||
"BRKH_CLK_CK_GCLK30",
|
||||
"BRKH_CLK_CK_GCLK31",
|
||||
"BRKH_CLK_CK_GCLK4",
|
||||
"BRKH_CLK_CK_GCLK5",
|
||||
"BRKH_CLK_CK_GCLK6",
|
||||
"BRKH_CLK_CK_GCLK7",
|
||||
"BRKH_CLK_CK_GCLK8",
|
||||
"BRKH_CLK_CK_GCLK9",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC0",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC1",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC10",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC11",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC12",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC13",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC14",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC15",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC16",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC17",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC18",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC19",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC2",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC20",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC21",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC22",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC23",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC24",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC25",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC26",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC27",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC28",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC29",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC3",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC30",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC31",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC4",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC5",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC6",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC7",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC8",
|
||||
"BRKH_CLK_R_CK_BUFG_CASC9",
|
||||
"BRKH_CLK_R_CK_GCLK0",
|
||||
"BRKH_CLK_R_CK_GCLK1",
|
||||
"BRKH_CLK_R_CK_GCLK10",
|
||||
"BRKH_CLK_R_CK_GCLK11",
|
||||
"BRKH_CLK_R_CK_GCLK12",
|
||||
"BRKH_CLK_R_CK_GCLK13",
|
||||
"BRKH_CLK_R_CK_GCLK14",
|
||||
"BRKH_CLK_R_CK_GCLK15",
|
||||
"BRKH_CLK_R_CK_GCLK16",
|
||||
"BRKH_CLK_R_CK_GCLK17",
|
||||
"BRKH_CLK_R_CK_GCLK18",
|
||||
"BRKH_CLK_R_CK_GCLK19",
|
||||
"BRKH_CLK_R_CK_GCLK2",
|
||||
"BRKH_CLK_R_CK_GCLK20",
|
||||
"BRKH_CLK_R_CK_GCLK21",
|
||||
"BRKH_CLK_R_CK_GCLK22",
|
||||
"BRKH_CLK_R_CK_GCLK23",
|
||||
"BRKH_CLK_R_CK_GCLK24",
|
||||
"BRKH_CLK_R_CK_GCLK25",
|
||||
"BRKH_CLK_R_CK_GCLK26",
|
||||
"BRKH_CLK_R_CK_GCLK27",
|
||||
"BRKH_CLK_R_CK_GCLK28",
|
||||
"BRKH_CLK_R_CK_GCLK29",
|
||||
"BRKH_CLK_R_CK_GCLK3",
|
||||
"BRKH_CLK_R_CK_GCLK30",
|
||||
"BRKH_CLK_R_CK_GCLK31",
|
||||
"BRKH_CLK_R_CK_GCLK4",
|
||||
"BRKH_CLK_R_CK_GCLK5",
|
||||
"BRKH_CLK_R_CK_GCLK6",
|
||||
"BRKH_CLK_R_CK_GCLK7",
|
||||
"BRKH_CLK_R_CK_GCLK8",
|
||||
"BRKH_CLK_R_CK_GCLK9"
|
||||
]
|
||||
}
|
||||
|
|
@ -1,16 +1,16 @@
|
|||
{
|
||||
"wires": [
|
||||
"BRKH_CMT_PHASEREF1",
|
||||
"BRKH_CMT_FREQ_REF_NS2",
|
||||
"BRKH_CMT_PHASEREF0",
|
||||
"BRKH_CMT_FREQ_REF_NS1",
|
||||
"BRKH_CMT_PHASEREF_BELOW1",
|
||||
"BRKH_CMT_FREQ_REF_NS0",
|
||||
"BRKH_CMT_PHYCTRL_SYNC_BB",
|
||||
"BRKH_CMT_PHASEREF_BELOW0",
|
||||
"BRKH_CMT_FREQ_REF_NS3"
|
||||
],
|
||||
"pips": {},
|
||||
"sites": [],
|
||||
"tile_type": "BRKH_CMT",
|
||||
"sites": []
|
||||
}
|
||||
"wires": [
|
||||
"BRKH_CMT_FREQ_REF_NS0",
|
||||
"BRKH_CMT_FREQ_REF_NS1",
|
||||
"BRKH_CMT_FREQ_REF_NS2",
|
||||
"BRKH_CMT_FREQ_REF_NS3",
|
||||
"BRKH_CMT_PHASEREF0",
|
||||
"BRKH_CMT_PHASEREF1",
|
||||
"BRKH_CMT_PHASEREF_BELOW0",
|
||||
"BRKH_CMT_PHASEREF_BELOW1",
|
||||
"BRKH_CMT_PHYCTRL_SYNC_BB"
|
||||
]
|
||||
}
|
||||
|
|
@ -1,105 +1,105 @@
|
|||
{
|
||||
"pips": {},
|
||||
"sites": [],
|
||||
"tile_type": "BRKH_DSP_L",
|
||||
"wires": [
|
||||
"BRKH_DSP_PCIN36",
|
||||
"BRKH_DSP_BCIN10",
|
||||
"BRKH_DSP_PCIN1",
|
||||
"BRKH_DSP_ACIN2",
|
||||
"BRKH_DSP_BCIN1",
|
||||
"BRKH_DSP_ACIN6",
|
||||
"BRKH_DSP_MULTSIGNIN",
|
||||
"BRKH_DSP_ACIN8",
|
||||
"BRKH_DSP_PCIN13",
|
||||
"BRKH_DSP_BCIN6",
|
||||
"BRKH_DSP_ACIN28",
|
||||
"BRKH_DSP_PCIN4",
|
||||
"BRKH_DSP_PCIN43",
|
||||
"BRKH_DSP_ACIN9",
|
||||
"BRKH_DSP_BCIN15",
|
||||
"BRKH_DSP_ACIN5",
|
||||
"BRKH_DSP_BCIN2",
|
||||
"BRKH_DSP_PCIN16",
|
||||
"BRKH_DSP_PCIN44",
|
||||
"BRKH_DSP_PCIN25",
|
||||
"BRKH_DSP_ACIN12",
|
||||
"BRKH_DSP_BCIN14",
|
||||
"BRKH_DSP_ACIN4",
|
||||
"BRKH_DSP_PCIN2",
|
||||
"BRKH_DSP_PCIN28",
|
||||
"BRKH_DSP_PCIN14",
|
||||
"BRKH_DSP_PCIN8",
|
||||
"BRKH_DSP_ACIN21",
|
||||
"BRKH_DSP_PCIN6",
|
||||
"BRKH_DSP_ACIN18",
|
||||
"BRKH_DSP_BCIN13",
|
||||
"BRKH_DSP_ACIN0",
|
||||
"BRKH_DSP_PCIN15",
|
||||
"BRKH_DSP_PCIN3",
|
||||
"BRKH_DSP_PCIN18",
|
||||
"BRKH_DSP_PCIN32",
|
||||
"BRKH_DSP_CARRYCASCIN",
|
||||
"BRKH_DSP_ACIN7",
|
||||
"BRKH_DSP_PCIN9",
|
||||
"BRKH_DSP_PCIN27",
|
||||
"BRKH_DSP_PCIN17",
|
||||
"BRKH_DSP_PCIN45",
|
||||
"BRKH_DSP_PCIN26",
|
||||
"BRKH_DSP_BCIN8",
|
||||
"BRKH_DSP_PCIN46",
|
||||
"BRKH_DSP_PCIN34",
|
||||
"BRKH_DSP_ACIN17",
|
||||
"BRKH_DSP_PCIN40",
|
||||
"BRKH_DSP_PCIN20",
|
||||
"BRKH_DSP_PCIN12",
|
||||
"BRKH_DSP_PCIN7",
|
||||
"BRKH_DSP_ACIN24",
|
||||
"BRKH_DSP_PCIN21",
|
||||
"BRKH_DSP_BCIN5",
|
||||
"BRKH_DSP_PCIN31",
|
||||
"BRKH_DSP_BCIN4",
|
||||
"BRKH_DSP_ACIN20",
|
||||
"BRKH_DSP_ACIN27",
|
||||
"BRKH_DSP_PCIN41",
|
||||
"BRKH_DSP_PCIN11",
|
||||
"BRKH_DSP_PCIN39",
|
||||
"BRKH_DSP_ACIN1",
|
||||
"BRKH_DSP_ACIN10",
|
||||
"BRKH_DSP_ACIN11",
|
||||
"BRKH_DSP_PCIN33",
|
||||
"BRKH_DSP_PCIN30",
|
||||
"BRKH_DSP_PCIN37",
|
||||
"BRKH_DSP_ACIN12",
|
||||
"BRKH_DSP_ACIN13",
|
||||
"BRKH_DSP_ACIN14",
|
||||
"BRKH_DSP_ACIN15",
|
||||
"BRKH_DSP_ACIN16",
|
||||
"BRKH_DSP_ACIN10",
|
||||
"BRKH_DSP_PCIN38",
|
||||
"BRKH_DSP_ACIN26",
|
||||
"BRKH_DSP_BCIN9",
|
||||
"BRKH_DSP_ACIN14",
|
||||
"BRKH_DSP_ACIN3",
|
||||
"BRKH_DSP_PCIN29",
|
||||
"BRKH_DSP_PCIN10",
|
||||
"BRKH_DSP_BCIN12",
|
||||
"BRKH_DSP_PCIN24",
|
||||
"BRKH_DSP_BCIN7",
|
||||
"BRKH_DSP_PCIN22",
|
||||
"BRKH_DSP_PCIN19",
|
||||
"BRKH_DSP_PCIN47",
|
||||
"BRKH_DSP_ACIN22",
|
||||
"BRKH_DSP_ACIN25",
|
||||
"BRKH_DSP_ACIN23",
|
||||
"BRKH_DSP_BCIN0",
|
||||
"BRKH_DSP_ACIN13",
|
||||
"BRKH_DSP_PCIN0",
|
||||
"BRKH_DSP_ACIN29",
|
||||
"BRKH_DSP_ACIN17",
|
||||
"BRKH_DSP_ACIN18",
|
||||
"BRKH_DSP_ACIN19",
|
||||
"BRKH_DSP_ACIN1",
|
||||
"BRKH_DSP_PCIN5",
|
||||
"BRKH_DSP_PCIN35",
|
||||
"BRKH_DSP_ACIN2",
|
||||
"BRKH_DSP_ACIN20",
|
||||
"BRKH_DSP_ACIN21",
|
||||
"BRKH_DSP_ACIN22",
|
||||
"BRKH_DSP_ACIN23",
|
||||
"BRKH_DSP_ACIN24",
|
||||
"BRKH_DSP_ACIN25",
|
||||
"BRKH_DSP_ACIN26",
|
||||
"BRKH_DSP_ACIN27",
|
||||
"BRKH_DSP_ACIN28",
|
||||
"BRKH_DSP_ACIN29",
|
||||
"BRKH_DSP_ACIN3",
|
||||
"BRKH_DSP_ACIN4",
|
||||
"BRKH_DSP_ACIN5",
|
||||
"BRKH_DSP_ACIN6",
|
||||
"BRKH_DSP_ACIN7",
|
||||
"BRKH_DSP_ACIN8",
|
||||
"BRKH_DSP_ACIN9",
|
||||
"BRKH_DSP_BCIN0",
|
||||
"BRKH_DSP_BCIN1",
|
||||
"BRKH_DSP_BCIN10",
|
||||
"BRKH_DSP_BCIN11",
|
||||
"BRKH_DSP_PCIN42",
|
||||
"BRKH_DSP_BCIN3",
|
||||
"BRKH_DSP_BCIN17",
|
||||
"BRKH_DSP_BCIN12",
|
||||
"BRKH_DSP_BCIN13",
|
||||
"BRKH_DSP_BCIN14",
|
||||
"BRKH_DSP_BCIN15",
|
||||
"BRKH_DSP_BCIN16",
|
||||
"BRKH_DSP_PCIN23"
|
||||
],
|
||||
"pips": {},
|
||||
"tile_type": "BRKH_DSP_L",
|
||||
"sites": []
|
||||
}
|
||||
"BRKH_DSP_BCIN17",
|
||||
"BRKH_DSP_BCIN2",
|
||||
"BRKH_DSP_BCIN3",
|
||||
"BRKH_DSP_BCIN4",
|
||||
"BRKH_DSP_BCIN5",
|
||||
"BRKH_DSP_BCIN6",
|
||||
"BRKH_DSP_BCIN7",
|
||||
"BRKH_DSP_BCIN8",
|
||||
"BRKH_DSP_BCIN9",
|
||||
"BRKH_DSP_CARRYCASCIN",
|
||||
"BRKH_DSP_MULTSIGNIN",
|
||||
"BRKH_DSP_PCIN0",
|
||||
"BRKH_DSP_PCIN1",
|
||||
"BRKH_DSP_PCIN10",
|
||||
"BRKH_DSP_PCIN11",
|
||||
"BRKH_DSP_PCIN12",
|
||||
"BRKH_DSP_PCIN13",
|
||||
"BRKH_DSP_PCIN14",
|
||||
"BRKH_DSP_PCIN15",
|
||||
"BRKH_DSP_PCIN16",
|
||||
"BRKH_DSP_PCIN17",
|
||||
"BRKH_DSP_PCIN18",
|
||||
"BRKH_DSP_PCIN19",
|
||||
"BRKH_DSP_PCIN2",
|
||||
"BRKH_DSP_PCIN20",
|
||||
"BRKH_DSP_PCIN21",
|
||||
"BRKH_DSP_PCIN22",
|
||||
"BRKH_DSP_PCIN23",
|
||||
"BRKH_DSP_PCIN24",
|
||||
"BRKH_DSP_PCIN25",
|
||||
"BRKH_DSP_PCIN26",
|
||||
"BRKH_DSP_PCIN27",
|
||||
"BRKH_DSP_PCIN28",
|
||||
"BRKH_DSP_PCIN29",
|
||||
"BRKH_DSP_PCIN3",
|
||||
"BRKH_DSP_PCIN30",
|
||||
"BRKH_DSP_PCIN31",
|
||||
"BRKH_DSP_PCIN32",
|
||||
"BRKH_DSP_PCIN33",
|
||||
"BRKH_DSP_PCIN34",
|
||||
"BRKH_DSP_PCIN35",
|
||||
"BRKH_DSP_PCIN36",
|
||||
"BRKH_DSP_PCIN37",
|
||||
"BRKH_DSP_PCIN38",
|
||||
"BRKH_DSP_PCIN39",
|
||||
"BRKH_DSP_PCIN4",
|
||||
"BRKH_DSP_PCIN40",
|
||||
"BRKH_DSP_PCIN41",
|
||||
"BRKH_DSP_PCIN42",
|
||||
"BRKH_DSP_PCIN43",
|
||||
"BRKH_DSP_PCIN44",
|
||||
"BRKH_DSP_PCIN45",
|
||||
"BRKH_DSP_PCIN46",
|
||||
"BRKH_DSP_PCIN47",
|
||||
"BRKH_DSP_PCIN5",
|
||||
"BRKH_DSP_PCIN6",
|
||||
"BRKH_DSP_PCIN7",
|
||||
"BRKH_DSP_PCIN8",
|
||||
"BRKH_DSP_PCIN9"
|
||||
]
|
||||
}
|
||||
|
|
@ -1,105 +1,105 @@
|
|||
{
|
||||
"pips": {},
|
||||
"sites": [],
|
||||
"tile_type": "BRKH_DSP_R",
|
||||
"wires": [
|
||||
"BRKH_DSP_PCIN36",
|
||||
"BRKH_DSP_BCIN10",
|
||||
"BRKH_DSP_PCIN1",
|
||||
"BRKH_DSP_ACIN2",
|
||||
"BRKH_DSP_BCIN1",
|
||||
"BRKH_DSP_ACIN6",
|
||||
"BRKH_DSP_MULTSIGNIN",
|
||||
"BRKH_DSP_ACIN8",
|
||||
"BRKH_DSP_PCIN13",
|
||||
"BRKH_DSP_BCIN6",
|
||||
"BRKH_DSP_ACIN28",
|
||||
"BRKH_DSP_PCIN4",
|
||||
"BRKH_DSP_PCIN43",
|
||||
"BRKH_DSP_ACIN9",
|
||||
"BRKH_DSP_BCIN15",
|
||||
"BRKH_DSP_ACIN5",
|
||||
"BRKH_DSP_BCIN2",
|
||||
"BRKH_DSP_PCIN16",
|
||||
"BRKH_DSP_PCIN44",
|
||||
"BRKH_DSP_PCIN25",
|
||||
"BRKH_DSP_ACIN12",
|
||||
"BRKH_DSP_BCIN14",
|
||||
"BRKH_DSP_ACIN4",
|
||||
"BRKH_DSP_PCIN2",
|
||||
"BRKH_DSP_PCIN28",
|
||||
"BRKH_DSP_PCIN14",
|
||||
"BRKH_DSP_PCIN8",
|
||||
"BRKH_DSP_ACIN21",
|
||||
"BRKH_DSP_PCIN6",
|
||||
"BRKH_DSP_ACIN18",
|
||||
"BRKH_DSP_BCIN13",
|
||||
"BRKH_DSP_ACIN0",
|
||||
"BRKH_DSP_PCIN15",
|
||||
"BRKH_DSP_PCIN3",
|
||||
"BRKH_DSP_PCIN18",
|
||||
"BRKH_DSP_PCIN32",
|
||||
"BRKH_DSP_CARRYCASCIN",
|
||||
"BRKH_DSP_ACIN7",
|
||||
"BRKH_DSP_PCIN9",
|
||||
"BRKH_DSP_PCIN27",
|
||||
"BRKH_DSP_PCIN17",
|
||||
"BRKH_DSP_PCIN45",
|
||||
"BRKH_DSP_PCIN26",
|
||||
"BRKH_DSP_BCIN8",
|
||||
"BRKH_DSP_PCIN46",
|
||||
"BRKH_DSP_PCIN34",
|
||||
"BRKH_DSP_ACIN17",
|
||||
"BRKH_DSP_PCIN40",
|
||||
"BRKH_DSP_PCIN20",
|
||||
"BRKH_DSP_PCIN12",
|
||||
"BRKH_DSP_PCIN7",
|
||||
"BRKH_DSP_ACIN24",
|
||||
"BRKH_DSP_PCIN21",
|
||||
"BRKH_DSP_BCIN5",
|
||||
"BRKH_DSP_PCIN31",
|
||||
"BRKH_DSP_BCIN4",
|
||||
"BRKH_DSP_ACIN20",
|
||||
"BRKH_DSP_ACIN27",
|
||||
"BRKH_DSP_PCIN41",
|
||||
"BRKH_DSP_PCIN11",
|
||||
"BRKH_DSP_PCIN39",
|
||||
"BRKH_DSP_ACIN1",
|
||||
"BRKH_DSP_ACIN10",
|
||||
"BRKH_DSP_ACIN11",
|
||||
"BRKH_DSP_PCIN33",
|
||||
"BRKH_DSP_PCIN30",
|
||||
"BRKH_DSP_PCIN37",
|
||||
"BRKH_DSP_ACIN12",
|
||||
"BRKH_DSP_ACIN13",
|
||||
"BRKH_DSP_ACIN14",
|
||||
"BRKH_DSP_ACIN15",
|
||||
"BRKH_DSP_ACIN16",
|
||||
"BRKH_DSP_ACIN10",
|
||||
"BRKH_DSP_PCIN38",
|
||||
"BRKH_DSP_ACIN26",
|
||||
"BRKH_DSP_BCIN9",
|
||||
"BRKH_DSP_ACIN14",
|
||||
"BRKH_DSP_ACIN3",
|
||||
"BRKH_DSP_PCIN29",
|
||||
"BRKH_DSP_PCIN10",
|
||||
"BRKH_DSP_BCIN12",
|
||||
"BRKH_DSP_PCIN24",
|
||||
"BRKH_DSP_BCIN7",
|
||||
"BRKH_DSP_PCIN22",
|
||||
"BRKH_DSP_PCIN19",
|
||||
"BRKH_DSP_PCIN47",
|
||||
"BRKH_DSP_ACIN22",
|
||||
"BRKH_DSP_ACIN25",
|
||||
"BRKH_DSP_ACIN23",
|
||||
"BRKH_DSP_BCIN0",
|
||||
"BRKH_DSP_ACIN13",
|
||||
"BRKH_DSP_PCIN0",
|
||||
"BRKH_DSP_ACIN29",
|
||||
"BRKH_DSP_ACIN17",
|
||||
"BRKH_DSP_ACIN18",
|
||||
"BRKH_DSP_ACIN19",
|
||||
"BRKH_DSP_ACIN1",
|
||||
"BRKH_DSP_PCIN5",
|
||||
"BRKH_DSP_PCIN35",
|
||||
"BRKH_DSP_ACIN2",
|
||||
"BRKH_DSP_ACIN20",
|
||||
"BRKH_DSP_ACIN21",
|
||||
"BRKH_DSP_ACIN22",
|
||||
"BRKH_DSP_ACIN23",
|
||||
"BRKH_DSP_ACIN24",
|
||||
"BRKH_DSP_ACIN25",
|
||||
"BRKH_DSP_ACIN26",
|
||||
"BRKH_DSP_ACIN27",
|
||||
"BRKH_DSP_ACIN28",
|
||||
"BRKH_DSP_ACIN29",
|
||||
"BRKH_DSP_ACIN3",
|
||||
"BRKH_DSP_ACIN4",
|
||||
"BRKH_DSP_ACIN5",
|
||||
"BRKH_DSP_ACIN6",
|
||||
"BRKH_DSP_ACIN7",
|
||||
"BRKH_DSP_ACIN8",
|
||||
"BRKH_DSP_ACIN9",
|
||||
"BRKH_DSP_BCIN0",
|
||||
"BRKH_DSP_BCIN1",
|
||||
"BRKH_DSP_BCIN10",
|
||||
"BRKH_DSP_BCIN11",
|
||||
"BRKH_DSP_PCIN42",
|
||||
"BRKH_DSP_BCIN3",
|
||||
"BRKH_DSP_BCIN17",
|
||||
"BRKH_DSP_BCIN12",
|
||||
"BRKH_DSP_BCIN13",
|
||||
"BRKH_DSP_BCIN14",
|
||||
"BRKH_DSP_BCIN15",
|
||||
"BRKH_DSP_BCIN16",
|
||||
"BRKH_DSP_PCIN23"
|
||||
],
|
||||
"pips": {},
|
||||
"tile_type": "BRKH_DSP_R",
|
||||
"sites": []
|
||||
}
|
||||
"BRKH_DSP_BCIN17",
|
||||
"BRKH_DSP_BCIN2",
|
||||
"BRKH_DSP_BCIN3",
|
||||
"BRKH_DSP_BCIN4",
|
||||
"BRKH_DSP_BCIN5",
|
||||
"BRKH_DSP_BCIN6",
|
||||
"BRKH_DSP_BCIN7",
|
||||
"BRKH_DSP_BCIN8",
|
||||
"BRKH_DSP_BCIN9",
|
||||
"BRKH_DSP_CARRYCASCIN",
|
||||
"BRKH_DSP_MULTSIGNIN",
|
||||
"BRKH_DSP_PCIN0",
|
||||
"BRKH_DSP_PCIN1",
|
||||
"BRKH_DSP_PCIN10",
|
||||
"BRKH_DSP_PCIN11",
|
||||
"BRKH_DSP_PCIN12",
|
||||
"BRKH_DSP_PCIN13",
|
||||
"BRKH_DSP_PCIN14",
|
||||
"BRKH_DSP_PCIN15",
|
||||
"BRKH_DSP_PCIN16",
|
||||
"BRKH_DSP_PCIN17",
|
||||
"BRKH_DSP_PCIN18",
|
||||
"BRKH_DSP_PCIN19",
|
||||
"BRKH_DSP_PCIN2",
|
||||
"BRKH_DSP_PCIN20",
|
||||
"BRKH_DSP_PCIN21",
|
||||
"BRKH_DSP_PCIN22",
|
||||
"BRKH_DSP_PCIN23",
|
||||
"BRKH_DSP_PCIN24",
|
||||
"BRKH_DSP_PCIN25",
|
||||
"BRKH_DSP_PCIN26",
|
||||
"BRKH_DSP_PCIN27",
|
||||
"BRKH_DSP_PCIN28",
|
||||
"BRKH_DSP_PCIN29",
|
||||
"BRKH_DSP_PCIN3",
|
||||
"BRKH_DSP_PCIN30",
|
||||
"BRKH_DSP_PCIN31",
|
||||
"BRKH_DSP_PCIN32",
|
||||
"BRKH_DSP_PCIN33",
|
||||
"BRKH_DSP_PCIN34",
|
||||
"BRKH_DSP_PCIN35",
|
||||
"BRKH_DSP_PCIN36",
|
||||
"BRKH_DSP_PCIN37",
|
||||
"BRKH_DSP_PCIN38",
|
||||
"BRKH_DSP_PCIN39",
|
||||
"BRKH_DSP_PCIN4",
|
||||
"BRKH_DSP_PCIN40",
|
||||
"BRKH_DSP_PCIN41",
|
||||
"BRKH_DSP_PCIN42",
|
||||
"BRKH_DSP_PCIN43",
|
||||
"BRKH_DSP_PCIN44",
|
||||
"BRKH_DSP_PCIN45",
|
||||
"BRKH_DSP_PCIN46",
|
||||
"BRKH_DSP_PCIN47",
|
||||
"BRKH_DSP_PCIN5",
|
||||
"BRKH_DSP_PCIN6",
|
||||
"BRKH_DSP_PCIN7",
|
||||
"BRKH_DSP_PCIN8",
|
||||
"BRKH_DSP_PCIN9"
|
||||
]
|
||||
}
|
||||
|
|
@ -1,104 +1,104 @@
|
|||
{
|
||||
"wires": [
|
||||
"BRKH_GTX_NORTHREFCLK0_UPPER",
|
||||
"BRKH_GTX_REFCLK0_UPPER",
|
||||
"BRKH_GTX_SOUTHREFCLK0_UPPER",
|
||||
"BRKH_GTX_SOUTHREFCLK1_UPPER",
|
||||
"BRKH_GTX_SOUTHREFCLK0_LOWER",
|
||||
"BRKH_GTX_NORTHREFCLK1_UPPER",
|
||||
"BRKH_GTX_REFCLK1_LOWER",
|
||||
"BRKH_GTX_REFCLK1_UPPER",
|
||||
"BRKH_GTX_REFCLK0_LOWER",
|
||||
"BRKH_GTX_SOUTHREFCLK1_LOWER",
|
||||
"BRKH_GTX_NORTHREFCLK1_LOWER",
|
||||
"BRKH_GTX_NORTHREFCLK0_LOWER"
|
||||
],
|
||||
"pips": {
|
||||
"BRKH_GTX.BRKH_GTX_REFCLK0_LOWER->BRKH_GTX_NORTHREFCLK0_UPPER": {
|
||||
"src_wire": "BRKH_GTX_REFCLK0_LOWER",
|
||||
"BRKH_GTX.BRKH_GTX_NORTHREFCLK0_LOWER->BRKH_GTX_NORTHREFCLK0_UPPER": {
|
||||
"can_invert": "0",
|
||||
"dst_wire": "BRKH_GTX_NORTHREFCLK0_UPPER",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"can_invert": "0",
|
||||
"dst_wire": "BRKH_GTX_NORTHREFCLK0_UPPER"
|
||||
},
|
||||
"BRKH_GTX.BRKH_GTX_SOUTHREFCLK1_UPPER->BRKH_GTX_SOUTHREFCLK1_LOWER": {
|
||||
"src_wire": "BRKH_GTX_SOUTHREFCLK1_UPPER",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"can_invert": "0",
|
||||
"dst_wire": "BRKH_GTX_SOUTHREFCLK1_LOWER"
|
||||
"src_wire": "BRKH_GTX_NORTHREFCLK0_LOWER"
|
||||
},
|
||||
"BRKH_GTX.BRKH_GTX_NORTHREFCLK1_LOWER->BRKH_GTX_NORTHREFCLK1_UPPER": {
|
||||
"src_wire": "BRKH_GTX_NORTHREFCLK1_LOWER",
|
||||
"can_invert": "0",
|
||||
"dst_wire": "BRKH_GTX_NORTHREFCLK1_UPPER",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"can_invert": "0",
|
||||
"dst_wire": "BRKH_GTX_NORTHREFCLK1_UPPER"
|
||||
"src_wire": "BRKH_GTX_NORTHREFCLK1_LOWER"
|
||||
},
|
||||
"BRKH_GTX.BRKH_GTX_REFCLK1_UPPER->BRKH_GTX_SOUTHREFCLK1_LOWER": {
|
||||
"src_wire": "BRKH_GTX_REFCLK1_UPPER",
|
||||
"BRKH_GTX.BRKH_GTX_REFCLK0_LOWER->BRKH_GTX_NORTHREFCLK0_UPPER": {
|
||||
"can_invert": "0",
|
||||
"dst_wire": "BRKH_GTX_NORTHREFCLK0_UPPER",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"can_invert": "0",
|
||||
"dst_wire": "BRKH_GTX_SOUTHREFCLK1_LOWER"
|
||||
},
|
||||
"BRKH_GTX.BRKH_GTX_SOUTHREFCLK0_UPPER->BRKH_GTX_SOUTHREFCLK0_LOWER": {
|
||||
"src_wire": "BRKH_GTX_SOUTHREFCLK0_UPPER",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"can_invert": "0",
|
||||
"dst_wire": "BRKH_GTX_SOUTHREFCLK0_LOWER"
|
||||
},
|
||||
"BRKH_GTX.BRKH_GTX_REFCLK1_LOWER->BRKH_GTX_NORTHREFCLK0_UPPER": {
|
||||
"src_wire": "BRKH_GTX_REFCLK1_LOWER",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"can_invert": "0",
|
||||
"dst_wire": "BRKH_GTX_NORTHREFCLK0_UPPER"
|
||||
},
|
||||
"BRKH_GTX.BRKH_GTX_REFCLK1_LOWER->BRKH_GTX_NORTHREFCLK1_UPPER": {
|
||||
"src_wire": "BRKH_GTX_REFCLK1_LOWER",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"can_invert": "0",
|
||||
"dst_wire": "BRKH_GTX_NORTHREFCLK1_UPPER"
|
||||
},
|
||||
"BRKH_GTX.BRKH_GTX_REFCLK0_UPPER->BRKH_GTX_SOUTHREFCLK0_LOWER": {
|
||||
"src_wire": "BRKH_GTX_REFCLK0_UPPER",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"can_invert": "0",
|
||||
"dst_wire": "BRKH_GTX_SOUTHREFCLK0_LOWER"
|
||||
},
|
||||
"BRKH_GTX.BRKH_GTX_REFCLK1_UPPER->BRKH_GTX_SOUTHREFCLK0_LOWER": {
|
||||
"src_wire": "BRKH_GTX_REFCLK1_UPPER",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"can_invert": "0",
|
||||
"dst_wire": "BRKH_GTX_SOUTHREFCLK0_LOWER"
|
||||
},
|
||||
"BRKH_GTX.BRKH_GTX_NORTHREFCLK0_LOWER->BRKH_GTX_NORTHREFCLK0_UPPER": {
|
||||
"src_wire": "BRKH_GTX_NORTHREFCLK0_LOWER",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"can_invert": "0",
|
||||
"dst_wire": "BRKH_GTX_NORTHREFCLK0_UPPER"
|
||||
},
|
||||
"BRKH_GTX.BRKH_GTX_REFCLK0_UPPER->BRKH_GTX_SOUTHREFCLK1_LOWER": {
|
||||
"src_wire": "BRKH_GTX_REFCLK0_UPPER",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"can_invert": "0",
|
||||
"dst_wire": "BRKH_GTX_SOUTHREFCLK1_LOWER"
|
||||
"src_wire": "BRKH_GTX_REFCLK0_LOWER"
|
||||
},
|
||||
"BRKH_GTX.BRKH_GTX_REFCLK0_LOWER->BRKH_GTX_NORTHREFCLK1_UPPER": {
|
||||
"src_wire": "BRKH_GTX_REFCLK0_LOWER",
|
||||
"can_invert": "0",
|
||||
"dst_wire": "BRKH_GTX_NORTHREFCLK1_UPPER",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"src_wire": "BRKH_GTX_REFCLK0_LOWER"
|
||||
},
|
||||
"BRKH_GTX.BRKH_GTX_REFCLK0_UPPER->BRKH_GTX_SOUTHREFCLK0_LOWER": {
|
||||
"can_invert": "0",
|
||||
"dst_wire": "BRKH_GTX_NORTHREFCLK1_UPPER"
|
||||
"dst_wire": "BRKH_GTX_SOUTHREFCLK0_LOWER",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"src_wire": "BRKH_GTX_REFCLK0_UPPER"
|
||||
},
|
||||
"BRKH_GTX.BRKH_GTX_REFCLK0_UPPER->BRKH_GTX_SOUTHREFCLK1_LOWER": {
|
||||
"can_invert": "0",
|
||||
"dst_wire": "BRKH_GTX_SOUTHREFCLK1_LOWER",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"src_wire": "BRKH_GTX_REFCLK0_UPPER"
|
||||
},
|
||||
"BRKH_GTX.BRKH_GTX_REFCLK1_LOWER->BRKH_GTX_NORTHREFCLK0_UPPER": {
|
||||
"can_invert": "0",
|
||||
"dst_wire": "BRKH_GTX_NORTHREFCLK0_UPPER",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"src_wire": "BRKH_GTX_REFCLK1_LOWER"
|
||||
},
|
||||
"BRKH_GTX.BRKH_GTX_REFCLK1_LOWER->BRKH_GTX_NORTHREFCLK1_UPPER": {
|
||||
"can_invert": "0",
|
||||
"dst_wire": "BRKH_GTX_NORTHREFCLK1_UPPER",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"src_wire": "BRKH_GTX_REFCLK1_LOWER"
|
||||
},
|
||||
"BRKH_GTX.BRKH_GTX_REFCLK1_UPPER->BRKH_GTX_SOUTHREFCLK0_LOWER": {
|
||||
"can_invert": "0",
|
||||
"dst_wire": "BRKH_GTX_SOUTHREFCLK0_LOWER",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"src_wire": "BRKH_GTX_REFCLK1_UPPER"
|
||||
},
|
||||
"BRKH_GTX.BRKH_GTX_REFCLK1_UPPER->BRKH_GTX_SOUTHREFCLK1_LOWER": {
|
||||
"can_invert": "0",
|
||||
"dst_wire": "BRKH_GTX_SOUTHREFCLK1_LOWER",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"src_wire": "BRKH_GTX_REFCLK1_UPPER"
|
||||
},
|
||||
"BRKH_GTX.BRKH_GTX_SOUTHREFCLK0_UPPER->BRKH_GTX_SOUTHREFCLK0_LOWER": {
|
||||
"can_invert": "0",
|
||||
"dst_wire": "BRKH_GTX_SOUTHREFCLK0_LOWER",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"src_wire": "BRKH_GTX_SOUTHREFCLK0_UPPER"
|
||||
},
|
||||
"BRKH_GTX.BRKH_GTX_SOUTHREFCLK1_UPPER->BRKH_GTX_SOUTHREFCLK1_LOWER": {
|
||||
"can_invert": "0",
|
||||
"dst_wire": "BRKH_GTX_SOUTHREFCLK1_LOWER",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"src_wire": "BRKH_GTX_SOUTHREFCLK1_UPPER"
|
||||
}
|
||||
},
|
||||
"sites": [],
|
||||
"tile_type": "BRKH_GTX",
|
||||
"sites": []
|
||||
}
|
||||
"wires": [
|
||||
"BRKH_GTX_NORTHREFCLK0_LOWER",
|
||||
"BRKH_GTX_NORTHREFCLK0_UPPER",
|
||||
"BRKH_GTX_NORTHREFCLK1_LOWER",
|
||||
"BRKH_GTX_NORTHREFCLK1_UPPER",
|
||||
"BRKH_GTX_REFCLK0_LOWER",
|
||||
"BRKH_GTX_REFCLK0_UPPER",
|
||||
"BRKH_GTX_REFCLK1_LOWER",
|
||||
"BRKH_GTX_REFCLK1_UPPER",
|
||||
"BRKH_GTX_SOUTHREFCLK0_LOWER",
|
||||
"BRKH_GTX_SOUTHREFCLK0_UPPER",
|
||||
"BRKH_GTX_SOUTHREFCLK1_LOWER",
|
||||
"BRKH_GTX_SOUTHREFCLK1_UPPER"
|
||||
]
|
||||
}
|
||||
|
|
@ -1,367 +1,367 @@
|
|||
{
|
||||
"wires": [
|
||||
"BRKH_INT_SS6B3",
|
||||
"BRKH_INT_NE6A3",
|
||||
"BRKH_INT_SS6C0",
|
||||
"BRKH_INT_NN6C1",
|
||||
"BRKH_INT_NE2BEG1",
|
||||
"BRKH_INT_LV6",
|
||||
"BRKH_INT_SS2A1",
|
||||
"BRKH_INT_SS6END2",
|
||||
"BRKH_INT_SS6END_N0_3",
|
||||
"BRKH_INT_NN2BEG3",
|
||||
"BRKH_INT_NE6A2",
|
||||
"BRKH_INT_SS6A2",
|
||||
"BRKH_INT_NW6A3",
|
||||
"BRKH_INT_FAN_BOUNCE_S3_0",
|
||||
"BRKH_INT_SW6D3",
|
||||
"BRKH_INT_SW2A0",
|
||||
"BRKH_INT_BYP_BOUNCE2",
|
||||
"BRKH_INT_NN6D0",
|
||||
"BRKH_INT_SR1END2",
|
||||
"BRKH_INT_NN6D2",
|
||||
"BRKH_INT_L_LV11",
|
||||
"BRKH_INT_LVB_L12",
|
||||
"BRKH_INT_SS6B2",
|
||||
"BRKH_INT_SS6D1",
|
||||
"BRKH_INT_NE2END_S3_0",
|
||||
"BRKH_INT_BYP_BOUNCE7",
|
||||
"BRKH_INT_NN2BEG2",
|
||||
"BRKH_INT_NE6A0",
|
||||
"BRKH_INT_NW6D0",
|
||||
"BRKH_INT_LVB_L10",
|
||||
"BRKH_INT_SW6E1",
|
||||
"BRKH_INT_FAN_BOUNCE_S3_6",
|
||||
"BRKH_INT_NE6C3",
|
||||
"BRKH_INT_NN2A3",
|
||||
"BRKH_INT_LV4",
|
||||
"BRKH_INT_SW6D1",
|
||||
"BRKH_INT_NW6A1",
|
||||
"BRKH_INT_SS6D2",
|
||||
"BRKH_INT_NW2BEG2",
|
||||
"BRKH_INT_LV10",
|
||||
"BRKH_INT_NL1BEG2_SLOW",
|
||||
"BRKH_INT_SL1END2_SLOW",
|
||||
"BRKH_INT_WR1END_S1_0",
|
||||
"BRKH_INT_SW6B1",
|
||||
"BRKH_INT_SR1END3",
|
||||
"BRKH_INT_L_LV5",
|
||||
"BRKH_INT_LV8",
|
||||
"BRKH_INT_NW6C2",
|
||||
"BRKH_INT_SS2END3",
|
||||
"BRKH_INT_L_LV3",
|
||||
"BRKH_INT_SS6A0",
|
||||
"BRKH_INT_L_LV13",
|
||||
"BRKH_INT_LVB11",
|
||||
"BRKH_INT_NW6B0",
|
||||
"BRKH_INT_SW6B0",
|
||||
"BRKH_INT_LVB9",
|
||||
"BRKH_INT_NE6B3",
|
||||
"BRKH_INT_SW6E3",
|
||||
"BRKH_INT_LV9",
|
||||
"BRKH_INT_SW6B3",
|
||||
"BRKH_INT_NN6B2",
|
||||
"BRKH_INT_L_LV7",
|
||||
"BRKH_INT_NR1BEG1_SLOW",
|
||||
"BRKH_INT_SE6D1",
|
||||
"BRKH_INT_SE6E1",
|
||||
"BRKH_INT_SS6C2",
|
||||
"BRKH_INT_SS6B0",
|
||||
"BRKH_INT_NW6D1",
|
||||
"BRKH_INT_LVB_L7",
|
||||
"BRKH_INT_SE6E0",
|
||||
"BRKH_INT_SE6C3",
|
||||
"BRKH_INT_NN2A1",
|
||||
"BRKH_INT_LV15",
|
||||
"BRKH_INT_NN2END_S2_0",
|
||||
"BRKH_INT_NN6B0",
|
||||
"BRKH_INT_SS6C3",
|
||||
"BRKH_INT_SR1END3_SLOW",
|
||||
"BRKH_INT_FAN_BOUNCE_S3_4",
|
||||
"BRKH_INT_NN6E0",
|
||||
"BRKH_INT_SE6E2",
|
||||
"BRKH_INT_SS2A3",
|
||||
"BRKH_INT_SE6B0",
|
||||
"BRKH_INT_LV7",
|
||||
"BRKH_INT_NN6E2",
|
||||
"BRKH_INT_LVB_L6",
|
||||
"BRKH_INT_SS2A2",
|
||||
"BRKH_INT_LVB_L2",
|
||||
"BRKH_INT_WL1BEG3",
|
||||
"BRKH_INT_SE6C2",
|
||||
"BRKH_INT_NL1BEG0",
|
||||
"BRKH_INT_NN2A2",
|
||||
"BRKH_INT_SS6E1",
|
||||
"BRKH_INT_SE2A3",
|
||||
"BRKH_INT_LVB_L9",
|
||||
"BRKH_INT_NE6D1",
|
||||
"BRKH_INT_SS6E3",
|
||||
"BRKH_INT_SW2A1",
|
||||
"BRKH_INT_NR1BEG3_SLOW",
|
||||
"BRKH_INT_NN6A2",
|
||||
"BRKH_INT_NE2BEG3",
|
||||
"BRKH_INT_LVB10",
|
||||
"BRKH_INT_BYP_BOUNCE6",
|
||||
"BRKH_INT_L_LV12",
|
||||
"BRKH_INT_EL1BEG3",
|
||||
"BRKH_INT_SW6C1",
|
||||
"BRKH_INT_NW6B2",
|
||||
"BRKH_INT_L_LV0",
|
||||
"BRKH_INT_SL1END3",
|
||||
"BRKH_INT_NR1BEG1",
|
||||
"BRKH_INT_NN6A3",
|
||||
"BRKH_INT_SL1END3_SLOW",
|
||||
"BRKH_INT_SW2A3",
|
||||
"BRKH_INT_BYP_BOUNCE3",
|
||||
"BRKH_INT_SS6D3",
|
||||
"BRKH_INT_NW6B1",
|
||||
"BRKH_INT_LVB8",
|
||||
"BRKH_INT_SS6D0",
|
||||
"BRKH_INT_NN6A0",
|
||||
"BRKH_INT_SE6C0",
|
||||
"BRKH_INT_SE2A0",
|
||||
"BRKH_INT_SS2END0",
|
||||
"BRKH_INT_NN6D1",
|
||||
"BRKH_INT_L_LV15",
|
||||
"BRKH_INT_NL1BEG1",
|
||||
"BRKH_INT_L_LV10",
|
||||
"BRKH_INT_SE6C1",
|
||||
"BRKH_INT_SW2A2",
|
||||
"BRKH_INT_LVB3",
|
||||
"BRKH_INT_NW6C0",
|
||||
"BRKH_INT_NN6C0",
|
||||
"BRKH_INT_SS2END1",
|
||||
"BRKH_INT_SS6END1",
|
||||
"BRKH_INT_NE6B1",
|
||||
"BRKH_INT_SR1END1",
|
||||
"BRKH_INT_NN6A1",
|
||||
"BRKH_INT_NN2BEG1",
|
||||
"BRKH_INT_L_LV8",
|
||||
"BRKH_INT_NE6D0",
|
||||
"BRKH_INT_WW2END3",
|
||||
"BRKH_INT_LV2",
|
||||
"BRKH_INT_SW6E2",
|
||||
"BRKH_INT_NE6D2",
|
||||
"BRKH_INT_L_LV17",
|
||||
"BRKH_INT_LV14",
|
||||
"BRKH_INT_NN6C2",
|
||||
"BRKH_INT_LV5",
|
||||
"BRKH_INT_LVB2",
|
||||
"BRKH_INT_NN6D3",
|
||||
"BRKH_INT_NN6BEG0",
|
||||
"BRKH_INT_SW6D0",
|
||||
"BRKH_INT_NW6D3",
|
||||
"BRKH_INT_NR1BEG3",
|
||||
"BRKH_INT_SE2A2",
|
||||
"BRKH_INT_EL1END_S3_0",
|
||||
"BRKH_INT_SE6D2",
|
||||
"BRKH_INT_NN6C3",
|
||||
"BRKH_INT_NE6D3",
|
||||
"BRKH_INT_SE6D3",
|
||||
"BRKH_INT_SW6D2",
|
||||
"BRKH_INT_NL1BEG2",
|
||||
"BRKH_INT_NE6C1",
|
||||
"BRKH_INT_NW2BEG1",
|
||||
"BRKH_INT_SS6E2",
|
||||
"BRKH_INT_NW6C1",
|
||||
"BRKH_INT_SS6C1",
|
||||
"BRKH_INT_LV3",
|
||||
"BRKH_INT_NE2BEG2",
|
||||
"BRKH_INT_SS2END_N0_3",
|
||||
"BRKH_INT_SS6B1",
|
||||
"BRKH_INT_SE6B3",
|
||||
"BRKH_INT_FAN_BOUNCE_S3_2",
|
||||
"BRKH_INT_L_LV4",
|
||||
"BRKH_INT_NL1END_S3_0",
|
||||
"BRKH_INT_SW6C0",
|
||||
"BRKH_INT_SS2END2",
|
||||
"BRKH_INT_ER1END3",
|
||||
"BRKH_INT_SL1END0",
|
||||
"BRKH_INT_LVB1",
|
||||
"BRKH_INT_LVB_L3",
|
||||
"BRKH_INT_NN6B3",
|
||||
"BRKH_INT_LVB_L4",
|
||||
"BRKH_INT_SE6B1",
|
||||
"BRKH_INT_NW6B3",
|
||||
"BRKH_INT_NN2BEG0",
|
||||
"BRKH_INT_SR1END1_SLOW",
|
||||
"BRKH_INT_L_LV9",
|
||||
"BRKH_INT_LV11",
|
||||
"BRKH_INT_SW6C2",
|
||||
"BRKH_INT_WL1END3",
|
||||
"BRKH_INT_LVB_L1",
|
||||
"BRKH_INT_SS6A1",
|
||||
"BRKH_INT_L_LV14",
|
||||
"BRKH_INT_LVB_L11",
|
||||
"BRKH_INT_NN6BEG2",
|
||||
"BRKH_INT_SW6B2",
|
||||
"BRKH_INT_L_LV16",
|
||||
"BRKH_INT_LV12",
|
||||
"BRKH_INT_LV16",
|
||||
"BRKH_INT_ER1BEG_S0",
|
||||
"BRKH_INT_NN6E3",
|
||||
"BRKH_INT_SS6END3",
|
||||
"BRKH_INT_NR1BEG0",
|
||||
"BRKH_INT_L_LV6",
|
||||
"BRKH_INT_NW6D2",
|
||||
"BRKH_INT_NW6A0",
|
||||
"BRKH_INT_LVB_L5",
|
||||
"BRKH_INT_SW2END3",
|
||||
"BRKH_INT_NN6E1",
|
||||
"BRKH_INT_NE2BEG0",
|
||||
"BRKH_INT_SL1END2",
|
||||
"BRKH_INT_NL1BEG0_SLOW",
|
||||
"BRKH_INT_SL1END1_SLOW",
|
||||
"BRKH_INT_NR1BEG2_SLOW",
|
||||
"BRKH_INT_NR1BEG2",
|
||||
"BRKH_INT_SW6END3",
|
||||
"BRKH_INT_NE6C2",
|
||||
"BRKH_INT_SS6A3",
|
||||
"BRKH_INT_NW6END_S0_0",
|
||||
"BRKH_INT_NW2END_S0_0",
|
||||
"BRKH_INT_SE6E3",
|
||||
"BRKH_INT_NR1BEG0_SLOW",
|
||||
"BRKH_INT_NE6B0",
|
||||
"BRKH_INT_NE6A1",
|
||||
"BRKH_INT_NL1BEG1_SLOW",
|
||||
"BRKH_INT_NN6END_S1_0",
|
||||
"BRKH_INT_SR1END_N3_3",
|
||||
"BRKH_INT_SE6B2",
|
||||
"BRKH_INT_SE2A1",
|
||||
"BRKH_INT_L_LV2",
|
||||
"BRKH_INT_SL1END0_SLOW",
|
||||
"BRKH_INT_NN6B1",
|
||||
"BRKH_INT_WR1BEG_S0",
|
||||
"BRKH_INT_SS6E0",
|
||||
"BRKH_INT_SR1END2_SLOW",
|
||||
"BRKH_INT_LVB_L8",
|
||||
"BRKH_INT_LV17",
|
||||
"BRKH_INT_NW2BEG0",
|
||||
"BRKH_INT_NW6C3",
|
||||
"BRKH_INT_SE6D0",
|
||||
"BRKH_INT_SS2A0",
|
||||
"BRKH_INT_LV0",
|
||||
"BRKH_INT_LVB4",
|
||||
"BRKH_INT_NE6B2",
|
||||
"BRKH_INT_SW6E0",
|
||||
"BRKH_INT_SW6C3",
|
||||
"BRKH_INT_LV13",
|
||||
"BRKH_INT_SL1END1",
|
||||
"BRKH_INT_NW2BEG3",
|
||||
"BRKH_INT_NW6A2",
|
||||
"BRKH_INT_NN6BEG1",
|
||||
"BRKH_INT_NN6BEG3",
|
||||
"BRKH_INT_WW4END_S0_0",
|
||||
"BRKH_INT_LVB6",
|
||||
"BRKH_INT_L_LV1",
|
||||
"BRKH_INT_SS6END0",
|
||||
"BRKH_INT_NE6C0",
|
||||
"BRKH_INT_NN2A0",
|
||||
"BRKH_INT_LVB12",
|
||||
"BRKH_INT_LVB5",
|
||||
"BRKH_INT_LV1",
|
||||
"BRKH_INT_LVB7"
|
||||
],
|
||||
"pips": {
|
||||
"BRKH_INT.BRKH_INT_NL1BEG2->>BRKH_INT_NL1BEG2_SLOW": {
|
||||
"src_wire": "BRKH_INT_NL1BEG2",
|
||||
"BRKH_INT.BRKH_INT_NL1BEG0->>BRKH_INT_NL1BEG0_SLOW": {
|
||||
"can_invert": "0",
|
||||
"dst_wire": "BRKH_INT_NL1BEG0_SLOW",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "BRKH_INT_NL1BEG2_SLOW",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRKH_INT.BRKH_INT_NR1BEG0->>BRKH_INT_NR1BEG0_SLOW": {
|
||||
"src_wire": "BRKH_INT_NR1BEG0",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "BRKH_INT_NR1BEG0_SLOW",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRKH_INT.BRKH_INT_SL1END0_SLOW->>BRKH_INT_SL1END0": {
|
||||
"src_wire": "BRKH_INT_SL1END0_SLOW",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "BRKH_INT_SL1END0",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRKH_INT.BRKH_INT_NR1BEG1->>BRKH_INT_NR1BEG1_SLOW": {
|
||||
"src_wire": "BRKH_INT_NR1BEG1",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "BRKH_INT_NR1BEG1_SLOW",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRKH_INT.BRKH_INT_NR1BEG2->>BRKH_INT_NR1BEG2_SLOW": {
|
||||
"src_wire": "BRKH_INT_NR1BEG2",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "BRKH_INT_NR1BEG2_SLOW",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRKH_INT.BRKH_INT_SR1END3_SLOW->>BRKH_INT_SR1END3": {
|
||||
"src_wire": "BRKH_INT_SR1END3_SLOW",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "BRKH_INT_SR1END3",
|
||||
"can_invert": "0"
|
||||
"src_wire": "BRKH_INT_NL1BEG0"
|
||||
},
|
||||
"BRKH_INT.BRKH_INT_NL1BEG1->>BRKH_INT_NL1BEG1_SLOW": {
|
||||
"src_wire": "BRKH_INT_NL1BEG1",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"can_invert": "0",
|
||||
"dst_wire": "BRKH_INT_NL1BEG1_SLOW",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRKH_INT.BRKH_INT_SL1END2_SLOW->>BRKH_INT_SL1END2": {
|
||||
"src_wire": "BRKH_INT_SL1END2_SLOW",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "BRKH_INT_SL1END2",
|
||||
"can_invert": "0"
|
||||
"src_wire": "BRKH_INT_NL1BEG1"
|
||||
},
|
||||
"BRKH_INT.BRKH_INT_NL1BEG0->>BRKH_INT_NL1BEG0_SLOW": {
|
||||
"src_wire": "BRKH_INT_NL1BEG0",
|
||||
"BRKH_INT.BRKH_INT_NL1BEG2->>BRKH_INT_NL1BEG2_SLOW": {
|
||||
"can_invert": "0",
|
||||
"dst_wire": "BRKH_INT_NL1BEG2_SLOW",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "BRKH_INT_NL1BEG0_SLOW",
|
||||
"can_invert": "0"
|
||||
"src_wire": "BRKH_INT_NL1BEG2"
|
||||
},
|
||||
"BRKH_INT.BRKH_INT_SR1END2_SLOW->>BRKH_INT_SR1END2": {
|
||||
"src_wire": "BRKH_INT_SR1END2_SLOW",
|
||||
"BRKH_INT.BRKH_INT_NR1BEG0->>BRKH_INT_NR1BEG0_SLOW": {
|
||||
"can_invert": "0",
|
||||
"dst_wire": "BRKH_INT_NR1BEG0_SLOW",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "BRKH_INT_SR1END2",
|
||||
"can_invert": "0"
|
||||
"src_wire": "BRKH_INT_NR1BEG0"
|
||||
},
|
||||
"BRKH_INT.BRKH_INT_NR1BEG1->>BRKH_INT_NR1BEG1_SLOW": {
|
||||
"can_invert": "0",
|
||||
"dst_wire": "BRKH_INT_NR1BEG1_SLOW",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"src_wire": "BRKH_INT_NR1BEG1"
|
||||
},
|
||||
"BRKH_INT.BRKH_INT_NR1BEG2->>BRKH_INT_NR1BEG2_SLOW": {
|
||||
"can_invert": "0",
|
||||
"dst_wire": "BRKH_INT_NR1BEG2_SLOW",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"src_wire": "BRKH_INT_NR1BEG2"
|
||||
},
|
||||
"BRKH_INT.BRKH_INT_NR1BEG3->>BRKH_INT_NR1BEG3_SLOW": {
|
||||
"src_wire": "BRKH_INT_NR1BEG3",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"can_invert": "0",
|
||||
"dst_wire": "BRKH_INT_NR1BEG3_SLOW",
|
||||
"can_invert": "0"
|
||||
},
|
||||
"BRKH_INT.BRKH_INT_SL1END3_SLOW->>BRKH_INT_SL1END3": {
|
||||
"src_wire": "BRKH_INT_SL1END3_SLOW",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "BRKH_INT_SL1END3",
|
||||
"can_invert": "0"
|
||||
"src_wire": "BRKH_INT_NR1BEG3"
|
||||
},
|
||||
"BRKH_INT.BRKH_INT_SR1END1_SLOW->>BRKH_INT_SR1END1": {
|
||||
"src_wire": "BRKH_INT_SR1END1_SLOW",
|
||||
"BRKH_INT.BRKH_INT_SL1END0_SLOW->>BRKH_INT_SL1END0": {
|
||||
"can_invert": "0",
|
||||
"dst_wire": "BRKH_INT_SL1END0",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "BRKH_INT_SR1END1",
|
||||
"can_invert": "0"
|
||||
"src_wire": "BRKH_INT_SL1END0_SLOW"
|
||||
},
|
||||
"BRKH_INT.BRKH_INT_SL1END1_SLOW->>BRKH_INT_SL1END1": {
|
||||
"src_wire": "BRKH_INT_SL1END1_SLOW",
|
||||
"can_invert": "0",
|
||||
"dst_wire": "BRKH_INT_SL1END1",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"dst_wire": "BRKH_INT_SL1END1",
|
||||
"can_invert": "0"
|
||||
"src_wire": "BRKH_INT_SL1END1_SLOW"
|
||||
},
|
||||
"BRKH_INT.BRKH_INT_SL1END2_SLOW->>BRKH_INT_SL1END2": {
|
||||
"can_invert": "0",
|
||||
"dst_wire": "BRKH_INT_SL1END2",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"src_wire": "BRKH_INT_SL1END2_SLOW"
|
||||
},
|
||||
"BRKH_INT.BRKH_INT_SL1END3_SLOW->>BRKH_INT_SL1END3": {
|
||||
"can_invert": "0",
|
||||
"dst_wire": "BRKH_INT_SL1END3",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"src_wire": "BRKH_INT_SL1END3_SLOW"
|
||||
},
|
||||
"BRKH_INT.BRKH_INT_SR1END1_SLOW->>BRKH_INT_SR1END1": {
|
||||
"can_invert": "0",
|
||||
"dst_wire": "BRKH_INT_SR1END1",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"src_wire": "BRKH_INT_SR1END1_SLOW"
|
||||
},
|
||||
"BRKH_INT.BRKH_INT_SR1END2_SLOW->>BRKH_INT_SR1END2": {
|
||||
"can_invert": "0",
|
||||
"dst_wire": "BRKH_INT_SR1END2",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"src_wire": "BRKH_INT_SR1END2_SLOW"
|
||||
},
|
||||
"BRKH_INT.BRKH_INT_SR1END3_SLOW->>BRKH_INT_SR1END3": {
|
||||
"can_invert": "0",
|
||||
"dst_wire": "BRKH_INT_SR1END3",
|
||||
"is_directional": "1",
|
||||
"is_pseudo": "0",
|
||||
"src_wire": "BRKH_INT_SR1END3_SLOW"
|
||||
}
|
||||
},
|
||||
"sites": [],
|
||||
"tile_type": "BRKH_INT",
|
||||
"sites": []
|
||||
}
|
||||
"wires": [
|
||||
"BRKH_INT_BYP_BOUNCE2",
|
||||
"BRKH_INT_BYP_BOUNCE3",
|
||||
"BRKH_INT_BYP_BOUNCE6",
|
||||
"BRKH_INT_BYP_BOUNCE7",
|
||||
"BRKH_INT_EL1BEG3",
|
||||
"BRKH_INT_EL1END_S3_0",
|
||||
"BRKH_INT_ER1BEG_S0",
|
||||
"BRKH_INT_ER1END3",
|
||||
"BRKH_INT_FAN_BOUNCE_S3_0",
|
||||
"BRKH_INT_FAN_BOUNCE_S3_2",
|
||||
"BRKH_INT_FAN_BOUNCE_S3_4",
|
||||
"BRKH_INT_FAN_BOUNCE_S3_6",
|
||||
"BRKH_INT_LV0",
|
||||
"BRKH_INT_LV1",
|
||||
"BRKH_INT_LV10",
|
||||
"BRKH_INT_LV11",
|
||||
"BRKH_INT_LV12",
|
||||
"BRKH_INT_LV13",
|
||||
"BRKH_INT_LV14",
|
||||
"BRKH_INT_LV15",
|
||||
"BRKH_INT_LV16",
|
||||
"BRKH_INT_LV17",
|
||||
"BRKH_INT_LV2",
|
||||
"BRKH_INT_LV3",
|
||||
"BRKH_INT_LV4",
|
||||
"BRKH_INT_LV5",
|
||||
"BRKH_INT_LV6",
|
||||
"BRKH_INT_LV7",
|
||||
"BRKH_INT_LV8",
|
||||
"BRKH_INT_LV9",
|
||||
"BRKH_INT_LVB1",
|
||||
"BRKH_INT_LVB10",
|
||||
"BRKH_INT_LVB11",
|
||||
"BRKH_INT_LVB12",
|
||||
"BRKH_INT_LVB2",
|
||||
"BRKH_INT_LVB3",
|
||||
"BRKH_INT_LVB4",
|
||||
"BRKH_INT_LVB5",
|
||||
"BRKH_INT_LVB6",
|
||||
"BRKH_INT_LVB7",
|
||||
"BRKH_INT_LVB8",
|
||||
"BRKH_INT_LVB9",
|
||||
"BRKH_INT_LVB_L1",
|
||||
"BRKH_INT_LVB_L10",
|
||||
"BRKH_INT_LVB_L11",
|
||||
"BRKH_INT_LVB_L12",
|
||||
"BRKH_INT_LVB_L2",
|
||||
"BRKH_INT_LVB_L3",
|
||||
"BRKH_INT_LVB_L4",
|
||||
"BRKH_INT_LVB_L5",
|
||||
"BRKH_INT_LVB_L6",
|
||||
"BRKH_INT_LVB_L7",
|
||||
"BRKH_INT_LVB_L8",
|
||||
"BRKH_INT_LVB_L9",
|
||||
"BRKH_INT_L_LV0",
|
||||
"BRKH_INT_L_LV1",
|
||||
"BRKH_INT_L_LV10",
|
||||
"BRKH_INT_L_LV11",
|
||||
"BRKH_INT_L_LV12",
|
||||
"BRKH_INT_L_LV13",
|
||||
"BRKH_INT_L_LV14",
|
||||
"BRKH_INT_L_LV15",
|
||||
"BRKH_INT_L_LV16",
|
||||
"BRKH_INT_L_LV17",
|
||||
"BRKH_INT_L_LV2",
|
||||
"BRKH_INT_L_LV3",
|
||||
"BRKH_INT_L_LV4",
|
||||
"BRKH_INT_L_LV5",
|
||||
"BRKH_INT_L_LV6",
|
||||
"BRKH_INT_L_LV7",
|
||||
"BRKH_INT_L_LV8",
|
||||
"BRKH_INT_L_LV9",
|
||||
"BRKH_INT_NE2BEG0",
|
||||
"BRKH_INT_NE2BEG1",
|
||||
"BRKH_INT_NE2BEG2",
|
||||
"BRKH_INT_NE2BEG3",
|
||||
"BRKH_INT_NE2END_S3_0",
|
||||
"BRKH_INT_NE6A0",
|
||||
"BRKH_INT_NE6A1",
|
||||
"BRKH_INT_NE6A2",
|
||||
"BRKH_INT_NE6A3",
|
||||
"BRKH_INT_NE6B0",
|
||||
"BRKH_INT_NE6B1",
|
||||
"BRKH_INT_NE6B2",
|
||||
"BRKH_INT_NE6B3",
|
||||
"BRKH_INT_NE6C0",
|
||||
"BRKH_INT_NE6C1",
|
||||
"BRKH_INT_NE6C2",
|
||||
"BRKH_INT_NE6C3",
|
||||
"BRKH_INT_NE6D0",
|
||||
"BRKH_INT_NE6D1",
|
||||
"BRKH_INT_NE6D2",
|
||||
"BRKH_INT_NE6D3",
|
||||
"BRKH_INT_NL1BEG0",
|
||||
"BRKH_INT_NL1BEG0_SLOW",
|
||||
"BRKH_INT_NL1BEG1",
|
||||
"BRKH_INT_NL1BEG1_SLOW",
|
||||
"BRKH_INT_NL1BEG2",
|
||||
"BRKH_INT_NL1BEG2_SLOW",
|
||||
"BRKH_INT_NL1END_S3_0",
|
||||
"BRKH_INT_NN2A0",
|
||||
"BRKH_INT_NN2A1",
|
||||
"BRKH_INT_NN2A2",
|
||||
"BRKH_INT_NN2A3",
|
||||
"BRKH_INT_NN2BEG0",
|
||||
"BRKH_INT_NN2BEG1",
|
||||
"BRKH_INT_NN2BEG2",
|
||||
"BRKH_INT_NN2BEG3",
|
||||
"BRKH_INT_NN2END_S2_0",
|
||||
"BRKH_INT_NN6A0",
|
||||
"BRKH_INT_NN6A1",
|
||||
"BRKH_INT_NN6A2",
|
||||
"BRKH_INT_NN6A3",
|
||||
"BRKH_INT_NN6B0",
|
||||
"BRKH_INT_NN6B1",
|
||||
"BRKH_INT_NN6B2",
|
||||
"BRKH_INT_NN6B3",
|
||||
"BRKH_INT_NN6BEG0",
|
||||
"BRKH_INT_NN6BEG1",
|
||||
"BRKH_INT_NN6BEG2",
|
||||
"BRKH_INT_NN6BEG3",
|
||||
"BRKH_INT_NN6C0",
|
||||
"BRKH_INT_NN6C1",
|
||||
"BRKH_INT_NN6C2",
|
||||
"BRKH_INT_NN6C3",
|
||||
"BRKH_INT_NN6D0",
|
||||
"BRKH_INT_NN6D1",
|
||||
"BRKH_INT_NN6D2",
|
||||
"BRKH_INT_NN6D3",
|
||||
"BRKH_INT_NN6E0",
|
||||
"BRKH_INT_NN6E1",
|
||||
"BRKH_INT_NN6E2",
|
||||
"BRKH_INT_NN6E3",
|
||||
"BRKH_INT_NN6END_S1_0",
|
||||
"BRKH_INT_NR1BEG0",
|
||||
"BRKH_INT_NR1BEG0_SLOW",
|
||||
"BRKH_INT_NR1BEG1",
|
||||
"BRKH_INT_NR1BEG1_SLOW",
|
||||
"BRKH_INT_NR1BEG2",
|
||||
"BRKH_INT_NR1BEG2_SLOW",
|
||||
"BRKH_INT_NR1BEG3",
|
||||
"BRKH_INT_NR1BEG3_SLOW",
|
||||
"BRKH_INT_NW2BEG0",
|
||||
"BRKH_INT_NW2BEG1",
|
||||
"BRKH_INT_NW2BEG2",
|
||||
"BRKH_INT_NW2BEG3",
|
||||
"BRKH_INT_NW2END_S0_0",
|
||||
"BRKH_INT_NW6A0",
|
||||
"BRKH_INT_NW6A1",
|
||||
"BRKH_INT_NW6A2",
|
||||
"BRKH_INT_NW6A3",
|
||||
"BRKH_INT_NW6B0",
|
||||
"BRKH_INT_NW6B1",
|
||||
"BRKH_INT_NW6B2",
|
||||
"BRKH_INT_NW6B3",
|
||||
"BRKH_INT_NW6C0",
|
||||
"BRKH_INT_NW6C1",
|
||||
"BRKH_INT_NW6C2",
|
||||
"BRKH_INT_NW6C3",
|
||||
"BRKH_INT_NW6D0",
|
||||
"BRKH_INT_NW6D1",
|
||||
"BRKH_INT_NW6D2",
|
||||
"BRKH_INT_NW6D3",
|
||||
"BRKH_INT_NW6END_S0_0",
|
||||
"BRKH_INT_SE2A0",
|
||||
"BRKH_INT_SE2A1",
|
||||
"BRKH_INT_SE2A2",
|
||||
"BRKH_INT_SE2A3",
|
||||
"BRKH_INT_SE6B0",
|
||||
"BRKH_INT_SE6B1",
|
||||
"BRKH_INT_SE6B2",
|
||||
"BRKH_INT_SE6B3",
|
||||
"BRKH_INT_SE6C0",
|
||||
"BRKH_INT_SE6C1",
|
||||
"BRKH_INT_SE6C2",
|
||||
"BRKH_INT_SE6C3",
|
||||
"BRKH_INT_SE6D0",
|
||||
"BRKH_INT_SE6D1",
|
||||
"BRKH_INT_SE6D2",
|
||||
"BRKH_INT_SE6D3",
|
||||
"BRKH_INT_SE6E0",
|
||||
"BRKH_INT_SE6E1",
|
||||
"BRKH_INT_SE6E2",
|
||||
"BRKH_INT_SE6E3",
|
||||
"BRKH_INT_SL1END0",
|
||||
"BRKH_INT_SL1END0_SLOW",
|
||||
"BRKH_INT_SL1END1",
|
||||
"BRKH_INT_SL1END1_SLOW",
|
||||
"BRKH_INT_SL1END2",
|
||||
"BRKH_INT_SL1END2_SLOW",
|
||||
"BRKH_INT_SL1END3",
|
||||
"BRKH_INT_SL1END3_SLOW",
|
||||
"BRKH_INT_SR1END1",
|
||||
"BRKH_INT_SR1END1_SLOW",
|
||||
"BRKH_INT_SR1END2",
|
||||
"BRKH_INT_SR1END2_SLOW",
|
||||
"BRKH_INT_SR1END3",
|
||||
"BRKH_INT_SR1END3_SLOW",
|
||||
"BRKH_INT_SR1END_N3_3",
|
||||
"BRKH_INT_SS2A0",
|
||||
"BRKH_INT_SS2A1",
|
||||
"BRKH_INT_SS2A2",
|
||||
"BRKH_INT_SS2A3",
|
||||
"BRKH_INT_SS2END0",
|
||||
"BRKH_INT_SS2END1",
|
||||
"BRKH_INT_SS2END2",
|
||||
"BRKH_INT_SS2END3",
|
||||
"BRKH_INT_SS2END_N0_3",
|
||||
"BRKH_INT_SS6A0",
|
||||
"BRKH_INT_SS6A1",
|
||||
"BRKH_INT_SS6A2",
|
||||
"BRKH_INT_SS6A3",
|
||||
"BRKH_INT_SS6B0",
|
||||
"BRKH_INT_SS6B1",
|
||||
"BRKH_INT_SS6B2",
|
||||
"BRKH_INT_SS6B3",
|
||||
"BRKH_INT_SS6C0",
|
||||
"BRKH_INT_SS6C1",
|
||||
"BRKH_INT_SS6C2",
|
||||
"BRKH_INT_SS6C3",
|
||||
"BRKH_INT_SS6D0",
|
||||
"BRKH_INT_SS6D1",
|
||||
"BRKH_INT_SS6D2",
|
||||
"BRKH_INT_SS6D3",
|
||||
"BRKH_INT_SS6E0",
|
||||
"BRKH_INT_SS6E1",
|
||||
"BRKH_INT_SS6E2",
|
||||
"BRKH_INT_SS6E3",
|
||||
"BRKH_INT_SS6END0",
|
||||
"BRKH_INT_SS6END1",
|
||||
"BRKH_INT_SS6END2",
|
||||
"BRKH_INT_SS6END3",
|
||||
"BRKH_INT_SS6END_N0_3",
|
||||
"BRKH_INT_SW2A0",
|
||||
"BRKH_INT_SW2A1",
|
||||
"BRKH_INT_SW2A2",
|
||||
"BRKH_INT_SW2A3",
|
||||
"BRKH_INT_SW2END3",
|
||||
"BRKH_INT_SW6B0",
|
||||
"BRKH_INT_SW6B1",
|
||||
"BRKH_INT_SW6B2",
|
||||
"BRKH_INT_SW6B3",
|
||||
"BRKH_INT_SW6C0",
|
||||
"BRKH_INT_SW6C1",
|
||||
"BRKH_INT_SW6C2",
|
||||
"BRKH_INT_SW6C3",
|
||||
"BRKH_INT_SW6D0",
|
||||
"BRKH_INT_SW6D1",
|
||||
"BRKH_INT_SW6D2",
|
||||
"BRKH_INT_SW6D3",
|
||||
"BRKH_INT_SW6E0",
|
||||
"BRKH_INT_SW6E1",
|
||||
"BRKH_INT_SW6E2",
|
||||
"BRKH_INT_SW6E3",
|
||||
"BRKH_INT_SW6END3",
|
||||
"BRKH_INT_WL1BEG3",
|
||||
"BRKH_INT_WL1END3",
|
||||
"BRKH_INT_WR1BEG_S0",
|
||||
"BRKH_INT_WR1END_S1_0",
|
||||
"BRKH_INT_WW2END3",
|
||||
"BRKH_INT_WW4END_S0_0"
|
||||
]
|
||||
}
|
||||
|
|
@ -1,124 +1,124 @@
|
|||
{
|
||||
"pips": {},
|
||||
"sites": [],
|
||||
"tile_type": "BRKH_TERM_INT",
|
||||
"wires": [
|
||||
"T_TERM_UTURN_INT_SE6D1",
|
||||
"T_TERM_UTURN_INT_LV_L9",
|
||||
"T_TERM_UTURN_INT_SS6C2",
|
||||
"T_TERM_UTURN_INT_WR1BEG_S0",
|
||||
"T_TERM_UTURN_INT_SE6B0",
|
||||
"T_TERM_UTURN_INT_LVB_L3",
|
||||
"T_TERM_UTURN_INT_LVB_L5",
|
||||
"T_TERM_UTURN_INT_FAN_BOUNCE_S3_2",
|
||||
"T_TERM_UTURN_INT_SW2A1",
|
||||
"T_TERM_UTURN_INT_SL1END2_SLOW",
|
||||
"T_TERM_UTURN_INT_LVB_L1",
|
||||
"T_TERM_INT_UTURN_LV_R16",
|
||||
"T_TERM_INT_UTURN_LV_R17",
|
||||
"T_TERM_INT_UTURN_LV_R2",
|
||||
"T_TERM_INT_UTURN_LV_R3",
|
||||
"T_TERM_INT_UTURN_LV_R4",
|
||||
"T_TERM_INT_UTURN_LV_R5",
|
||||
"T_TERM_INT_UTURN_LV_R6",
|
||||
"T_TERM_INT_UTURN_LV_R7",
|
||||
"T_TERM_INT_UTURN_LV_R9",
|
||||
"T_TERM_UTURN_INT_ER1BEG_S0",
|
||||
"T_TERM_UTURN_INT_ER1END3",
|
||||
"T_TERM_UTURN_INT_FAN_BOUNCE_S3_0",
|
||||
"T_TERM_UTURN_INT_SE6D3",
|
||||
"T_TERM_UTURN_INT_SL1END1_SLOW",
|
||||
"T_TERM_UTURN_INT_SW6B1",
|
||||
"T_TERM_UTURN_INT_LV_L6",
|
||||
"T_TERM_UTURN_INT_SS6E1",
|
||||
"T_TERM_UTURN_INT_FAN_BOUNCE_S3_2",
|
||||
"T_TERM_UTURN_INT_FAN_BOUNCE_S3_4",
|
||||
"T_TERM_UTURN_INT_FAN_BOUNCE_S3_6",
|
||||
"T_TERM_UTURN_INT_LVB0",
|
||||
"T_TERM_UTURN_INT_LVB1",
|
||||
"T_TERM_UTURN_INT_LVB2",
|
||||
"T_TERM_UTURN_INT_LVB3",
|
||||
"T_TERM_UTURN_INT_LVB4",
|
||||
"T_TERM_UTURN_INT_LVB5",
|
||||
"T_TERM_UTURN_INT_LVB_L0",
|
||||
"T_TERM_UTURN_INT_LVB_L1",
|
||||
"T_TERM_UTURN_INT_LVB_L2",
|
||||
"T_TERM_UTURN_INT_LVB_L3",
|
||||
"T_TERM_UTURN_INT_LVB_L4",
|
||||
"T_TERM_UTURN_INT_LVB_L5",
|
||||
"T_TERM_UTURN_INT_LV_L16",
|
||||
"T_TERM_UTURN_INT_LV_L17",
|
||||
"T_TERM_UTURN_INT_LV_L2",
|
||||
"T_TERM_UTURN_INT_LV_L3",
|
||||
"T_TERM_UTURN_INT_LV_L4",
|
||||
"T_TERM_UTURN_INT_LV_L5",
|
||||
"T_TERM_UTURN_INT_LV_L6",
|
||||
"T_TERM_UTURN_INT_LV_L7",
|
||||
"T_TERM_UTURN_INT_LV_L9",
|
||||
"T_TERM_UTURN_INT_SE2A0",
|
||||
"T_TERM_UTURN_INT_SE2A1",
|
||||
"T_TERM_UTURN_INT_SE2A2",
|
||||
"T_TERM_UTURN_INT_SE2A3",
|
||||
"T_TERM_UTURN_INT_SE6B0",
|
||||
"T_TERM_UTURN_INT_SE6B1",
|
||||
"T_TERM_UTURN_INT_SE6B2",
|
||||
"T_TERM_UTURN_INT_SE6B3",
|
||||
"T_TERM_UTURN_INT_SE6C0",
|
||||
"T_TERM_UTURN_INT_SE6C1",
|
||||
"T_TERM_UTURN_INT_SE6C2",
|
||||
"T_TERM_UTURN_INT_SE6C3",
|
||||
"T_TERM_UTURN_INT_SE6D0",
|
||||
"T_TERM_UTURN_INT_SE6D1",
|
||||
"T_TERM_UTURN_INT_SE6D2",
|
||||
"T_TERM_UTURN_INT_SE6D3",
|
||||
"T_TERM_UTURN_INT_SE6E0",
|
||||
"T_TERM_UTURN_INT_SE6E1",
|
||||
"T_TERM_UTURN_INT_SE6E2",
|
||||
"T_TERM_UTURN_INT_SE6E3",
|
||||
"T_TERM_UTURN_INT_SL1END0_SLOW",
|
||||
"T_TERM_UTURN_INT_SL1END1_SLOW",
|
||||
"T_TERM_UTURN_INT_SL1END2_SLOW",
|
||||
"T_TERM_UTURN_INT_SL1END3_SLOW",
|
||||
"T_TERM_UTURN_INT_SR1END1_SLOW",
|
||||
"T_TERM_UTURN_INT_SR1END2_SLOW",
|
||||
"T_TERM_UTURN_INT_SR1END3_SLOW",
|
||||
"T_TERM_UTURN_INT_SS2A0",
|
||||
"T_TERM_UTURN_INT_SS2A1",
|
||||
"T_TERM_UTURN_INT_SS2A2",
|
||||
"T_TERM_UTURN_INT_SS2A3",
|
||||
"T_TERM_UTURN_INT_SS2END0",
|
||||
"T_TERM_UTURN_INT_SS2END1",
|
||||
"T_TERM_UTURN_INT_SS2END2",
|
||||
"T_TERM_UTURN_INT_SS2END3",
|
||||
"T_TERM_UTURN_INT_SS6A0",
|
||||
"T_TERM_UTURN_INT_SS6A1",
|
||||
"T_TERM_UTURN_INT_SS6A2",
|
||||
"T_TERM_UTURN_INT_SS6A3",
|
||||
"T_TERM_UTURN_INT_SS6B0",
|
||||
"T_TERM_UTURN_INT_SS6B1",
|
||||
"T_TERM_UTURN_INT_SS6B2",
|
||||
"T_TERM_UTURN_INT_SS6B3",
|
||||
"T_TERM_UTURN_INT_SS6C0",
|
||||
"T_TERM_UTURN_INT_SS6C1",
|
||||
"T_TERM_UTURN_INT_SS6C2",
|
||||
"T_TERM_UTURN_INT_SS6C3",
|
||||
"T_TERM_UTURN_INT_SS6D0",
|
||||
"T_TERM_UTURN_INT_SS6D1",
|
||||
"T_TERM_UTURN_INT_SS6D2",
|
||||
"T_TERM_UTURN_INT_SS6D3",
|
||||
"T_TERM_UTURN_INT_SS6E0",
|
||||
"T_TERM_UTURN_INT_SS6E1",
|
||||
"T_TERM_UTURN_INT_SS6E2",
|
||||
"T_TERM_UTURN_INT_SS6E3",
|
||||
"T_TERM_UTURN_INT_SS6END0",
|
||||
"T_TERM_UTURN_INT_SS6END1",
|
||||
"T_TERM_UTURN_INT_SS6END2",
|
||||
"T_TERM_UTURN_INT_SS6END3",
|
||||
"T_TERM_UTURN_INT_SW2A0",
|
||||
"T_TERM_UTURN_INT_SW2A1",
|
||||
"T_TERM_UTURN_INT_SW2A2",
|
||||
"T_TERM_UTURN_INT_SW2A3",
|
||||
"T_TERM_UTURN_INT_SW6B0",
|
||||
"T_TERM_UTURN_INT_SW6B1",
|
||||
"T_TERM_UTURN_INT_SW6B2",
|
||||
"T_TERM_UTURN_INT_SW6B3",
|
||||
"T_TERM_UTURN_INT_SW6C0",
|
||||
"T_TERM_UTURN_INT_SW6C1",
|
||||
"T_TERM_UTURN_INT_SW6C2",
|
||||
"T_TERM_UTURN_INT_SW6C3",
|
||||
"T_TERM_UTURN_INT_SW6D0",
|
||||
"T_TERM_UTURN_INT_SW6D1",
|
||||
"T_TERM_UTURN_INT_SW6D2",
|
||||
"T_TERM_UTURN_INT_SW6D3",
|
||||
"T_TERM_UTURN_INT_SW6E0",
|
||||
"T_TERM_UTURN_INT_SW6E1",
|
||||
"T_TERM_UTURN_INT_SW6E2",
|
||||
"T_TERM_UTURN_INT_LVB0",
|
||||
"T_TERM_UTURN_INT_LVB4",
|
||||
"T_TERM_INT_UTURN_LV_R3",
|
||||
"T_TERM_UTURN_INT_SS6END2",
|
||||
"T_TERM_UTURN_INT_SS2A2",
|
||||
"T_TERM_UTURN_INT_SW6D1",
|
||||
"T_TERM_UTURN_INT_SR1END3_SLOW",
|
||||
"T_TERM_UTURN_INT_LV_L16",
|
||||
"T_TERM_UTURN_INT_SS6E3",
|
||||
"T_TERM_UTURN_INT_SS2A3",
|
||||
"T_TERM_INT_UTURN_LV_R4",
|
||||
"T_TERM_UTURN_INT_SS2END1",
|
||||
"T_TERM_UTURN_INT_LVB2",
|
||||
"T_TERM_UTURN_INT_LV_L2",
|
||||
"T_TERM_INT_UTURN_LV_R6",
|
||||
"T_TERM_INT_UTURN_LV_R2",
|
||||
"T_TERM_UTURN_INT_SS6B2",
|
||||
"T_TERM_UTURN_INT_SS2END3",
|
||||
"T_TERM_UTURN_INT_SS2END2",
|
||||
"T_TERM_UTURN_INT_SS6E2",
|
||||
"T_TERM_UTURN_INT_SE6C0",
|
||||
"T_TERM_UTURN_INT_SW2A3",
|
||||
"T_TERM_UTURN_INT_SR1END2_SLOW",
|
||||
"T_TERM_UTURN_INT_SS6A2",
|
||||
"T_TERM_UTURN_INT_SW6D3",
|
||||
"T_TERM_UTURN_INT_SS6E0",
|
||||
"T_TERM_UTURN_INT_FAN_BOUNCE_S3_6",
|
||||
"T_TERM_UTURN_INT_SS6C0",
|
||||
"T_TERM_UTURN_INT_SW6C1",
|
||||
"T_TERM_UTURN_INT_ER1END3",
|
||||
"T_TERM_UTURN_INT_SS6C1",
|
||||
"T_TERM_UTURN_INT_SE6D0",
|
||||
"T_TERM_UTURN_INT_SS6A3",
|
||||
"T_TERM_UTURN_INT_SE6E3",
|
||||
"T_TERM_UTURN_INT_SE2A0",
|
||||
"T_TERM_UTURN_INT_LVB_L4",
|
||||
"T_TERM_UTURN_INT_SS6B1",
|
||||
"T_TERM_UTURN_INT_SW6D0",
|
||||
"T_TERM_UTURN_INT_LVB5",
|
||||
"T_TERM_UTURN_INT_SS6A1",
|
||||
"T_TERM_UTURN_INT_SS6D2",
|
||||
"T_TERM_UTURN_INT_SS6A0",
|
||||
"T_TERM_UTURN_INT_SE6E2",
|
||||
"T_TERM_UTURN_INT_SE6D2",
|
||||
"T_TERM_UTURN_INT_SW6D2",
|
||||
"T_TERM_UTURN_INT_FAN_BOUNCE_S3_4",
|
||||
"T_TERM_UTURN_INT_ER1BEG_S0",
|
||||
"T_TERM_UTURN_INT_SE6C3",
|
||||
"T_TERM_UTURN_INT_SS6END0",
|
||||
"T_TERM_UTURN_INT_SS6B3",
|
||||
"T_TERM_UTURN_INT_SE6C2",
|
||||
"T_TERM_UTURN_INT_SE2A2",
|
||||
"T_TERM_INT_UTURN_LV_R7",
|
||||
"T_TERM_UTURN_INT_SS6B0",
|
||||
"T_TERM_INT_UTURN_LV_R16",
|
||||
"T_TERM_UTURN_INT_SW6B0",
|
||||
"T_TERM_UTURN_INT_SW6C2",
|
||||
"T_TERM_UTURN_INT_LV_L4",
|
||||
"T_TERM_UTURN_INT_SW2A2",
|
||||
"T_TERM_UTURN_INT_SE6C1",
|
||||
"T_TERM_UTURN_INT_LV_L7",
|
||||
"T_TERM_INT_UTURN_LV_R17",
|
||||
"T_TERM_UTURN_INT_LVB3",
|
||||
"T_TERM_UTURN_INT_SS6C3",
|
||||
"T_TERM_UTURN_INT_SL1END0_SLOW",
|
||||
"T_TERM_UTURN_INT_SS6D3",
|
||||
"T_TERM_INT_UTURN_LV_R9",
|
||||
"T_TERM_UTURN_INT_SW6C0",
|
||||
"T_TERM_UTURN_INT_SE2A1",
|
||||
"T_TERM_UTURN_INT_SS6END3",
|
||||
"T_TERM_UTURN_INT_LV_L3",
|
||||
"T_TERM_UTURN_INT_SS6D1",
|
||||
"T_TERM_UTURN_INT_LVB1",
|
||||
"T_TERM_UTURN_INT_SW6E0",
|
||||
"T_TERM_UTURN_INT_SE6E1",
|
||||
"T_TERM_UTURN_INT_SS6D0",
|
||||
"T_TERM_UTURN_INT_SE6E0",
|
||||
"T_TERM_UTURN_INT_SS2A1",
|
||||
"T_TERM_UTURN_INT_SE6B2",
|
||||
"T_TERM_UTURN_INT_SR1END1_SLOW",
|
||||
"T_TERM_UTURN_INT_LV_L17",
|
||||
"T_TERM_UTURN_INT_SW6B3",
|
||||
"T_TERM_UTURN_INT_SS2A0",
|
||||
"T_TERM_UTURN_INT_LVB_L2",
|
||||
"T_TERM_UTURN_INT_SW6B2",
|
||||
"T_TERM_INT_UTURN_LV_R5",
|
||||
"T_TERM_UTURN_INT_SE6B1",
|
||||
"T_TERM_UTURN_INT_SS6END1",
|
||||
"T_TERM_UTURN_INT_WR1END_S1_0",
|
||||
"T_TERM_UTURN_INT_SE6B3",
|
||||
"T_TERM_UTURN_INT_LV_L5",
|
||||
"T_TERM_UTURN_INT_SL1END3_SLOW",
|
||||
"T_TERM_UTURN_INT_SE2A3",
|
||||
"T_TERM_UTURN_INT_SW6C3",
|
||||
"T_TERM_UTURN_INT_SW6E3",
|
||||
"T_TERM_UTURN_INT_SW2A0"
|
||||
],
|
||||
"pips": {},
|
||||
"tile_type": "BRKH_TERM_INT",
|
||||
"sites": []
|
||||
}
|
||||
"T_TERM_UTURN_INT_WR1BEG_S0",
|
||||
"T_TERM_UTURN_INT_WR1END_S1_0"
|
||||
]
|
||||
}
|
||||
|
|
@ -1,125 +1,125 @@
|
|||
{
|
||||
"wires": [
|
||||
"B_TERM_UTURN_INT_SS2A1",
|
||||
"B_TERM_UTURN_INT_SW6C0",
|
||||
"B_TERM_UTURN_INT_LV3",
|
||||
"B_TERM_UTURN_INT_LVB_L1",
|
||||
"B_TERM_UTURN_INT_SE6A1",
|
||||
"B_TERM_UTURN_INT_SS6D0",
|
||||
"B_TERM_UTURN_INT_SS6B3",
|
||||
"B_TERM_UTURN_INT_LVB3",
|
||||
"B_TERM_UTURN_INT_SS6BEG1",
|
||||
"B_TERM_UTURN_INT_SS6E2",
|
||||
"B_TERM_UTURN_INT_LV_L5",
|
||||
"B_TERM_UTURN_INT_SE6D3",
|
||||
"B_TERM_UTURN_INT_LV_L2",
|
||||
"B_TERM_UTURN_INT_SE6C0",
|
||||
"B_TERM_UTURN_INT_LV5",
|
||||
"B_TERM_UTURN_INT_LV9",
|
||||
"B_TERM_UTURN_INT_SE6B3",
|
||||
"B_TERM_UTURN_INT_LV2",
|
||||
"B_TERM_UTURN_INT_LVB1",
|
||||
"B_TERM_UTURN_INT_ER1BEG0",
|
||||
"B_TERM_UTURN_INT_SS2BEG1",
|
||||
"B_TERM_UTURN_INT_SW2BEG2",
|
||||
"B_TERM_UTURN_INT_SS6BEG2",
|
||||
"B_TERM_UTURN_INT_FAN_BOUNCE0",
|
||||
"B_TERM_UTURN_INT_SW6END_N0_3",
|
||||
"B_TERM_UTURN_INT_LV7",
|
||||
"B_TERM_UTURN_INT_SS6B2",
|
||||
"B_TERM_UTURN_INT_SS6E3",
|
||||
"B_TERM_UTURN_INT_SW6C1",
|
||||
"B_TERM_UTURN_INT_LVB4",
|
||||
"B_TERM_UTURN_INT_SE6C2",
|
||||
"B_TERM_UTURN_INT_SS2BEG3",
|
||||
"B_TERM_UTURN_INT_LVB_L2",
|
||||
"B_TERM_UTURN_INT_SS6A2",
|
||||
"B_TERM_UTURN_INT_SW6D2",
|
||||
"B_TERM_UTURN_INT_SL1BEG1",
|
||||
"B_TERM_UTURN_INT_LV_L3",
|
||||
"B_TERM_UTURN_INT_SS2BEG2",
|
||||
"B_TERM_UTURN_INT_LVB2",
|
||||
"B_TERM_UTURN_INT_SR1BEG1",
|
||||
"B_TERM_UTURN_INT_ER1END_N3_3",
|
||||
"B_TERM_UTURN_INT_SS6A3",
|
||||
"B_TERM_UTURN_INT_SW6A1",
|
||||
"B_TERM_UTURN_INT_SL1BEG0",
|
||||
"B_TERM_UTURN_INT_SS6B1",
|
||||
"B_TERM_UTURN_INT_SE2BEG2",
|
||||
"B_TERM_UTURN_INT_LV_L9",
|
||||
"B_TERM_UTURN_INT_SS6BEG3",
|
||||
"B_TERM_UTURN_INT_SL1BEG3",
|
||||
"B_TERM_UTURN_INT_LV_L6",
|
||||
"B_TERM_UTURN_INT_LVB5",
|
||||
"B_TERM_UTURN_INT_LVB_L4",
|
||||
"B_TERM_UTURN_INT_SR1BEG2",
|
||||
"B_TERM_UTURN_INT_SS2A3",
|
||||
"B_TERM_UTURN_INT_SS6D1",
|
||||
"B_TERM_UTURN_INT_LVB0",
|
||||
"B_TERM_UTURN_INT_LV_L4",
|
||||
"B_TERM_UTURN_INT_SS6C3",
|
||||
"B_TERM_UTURN_INT_FAN_BOUNCE4",
|
||||
"B_TERM_UTURN_INT_SW6C3",
|
||||
"B_TERM_UTURN_INT_LV6",
|
||||
"B_TERM_UTURN_INT_SS6BEG0",
|
||||
"B_TERM_UTURN_INT_LV_L7",
|
||||
"B_TERM_UTURN_INT_SW6B0",
|
||||
"B_TERM_UTURN_INT_SS6D3",
|
||||
"B_TERM_UTURN_INT_FAN_BOUNCE2",
|
||||
"B_TERM_UTURN_INT_SS6D2",
|
||||
"B_TERM_UTURN_INT_SW6D3",
|
||||
"B_TERM_UTURN_INT_SL1BEG2",
|
||||
"B_TERM_UTURN_INT_SW6D1",
|
||||
"B_TERM_UTURN_INT_SS6C1",
|
||||
"B_TERM_UTURN_INT_LVB_L5",
|
||||
"B_TERM_UTURN_INT_SS2A2",
|
||||
"B_TERM_UTURN_INT_SS6E0",
|
||||
"B_TERM_UTURN_INT_SW2BEG1",
|
||||
"B_TERM_UTURN_INT_SW6A0",
|
||||
"B_TERM_UTURN_INT_SE2BEG0",
|
||||
"B_TERM_UTURN_INT_LV4",
|
||||
"B_TERM_UTURN_INT_SS6A0",
|
||||
"B_TERM_UTURN_INT_SW6A2",
|
||||
"B_TERM_UTURN_INT_SE6D2",
|
||||
"B_TERM_UTURN_INT_SE6C3",
|
||||
"B_TERM_UTURN_INT_FAN_BOUNCE6",
|
||||
"B_TERM_UTURN_INT_LV_L18",
|
||||
"B_TERM_UTURN_INT_LVB_L3",
|
||||
"B_TERM_UTURN_INT_LV18",
|
||||
"B_TERM_UTURN_INT_SR1BEG3",
|
||||
"B_TERM_UTURN_INT_SS6C0",
|
||||
"B_TERM_UTURN_INT_SE6D1",
|
||||
"B_TERM_UTURN_INT_SE6B1",
|
||||
"B_TERM_UTURN_INT_SE6A2",
|
||||
"B_TERM_UTURN_INT_SS2BEG0",
|
||||
"B_TERM_UTURN_INT_SW6B1",
|
||||
"B_TERM_UTURN_INT_SE6B2",
|
||||
"B_TERM_UTURN_INT_SE2BEG3",
|
||||
"B_TERM_UTURN_INT_WR1END0",
|
||||
"B_TERM_UTURN_INT_SW6B2",
|
||||
"B_TERM_UTURN_INT_SE6B0",
|
||||
"B_TERM_UTURN_INT_SS6C2",
|
||||
"B_TERM_UTURN_INT_SW2BEG3",
|
||||
"B_TERM_UTURN_INT_SE2BEG1",
|
||||
"B_TERM_UTURN_INT_SE6A3",
|
||||
"B_TERM_UTURN_INT_SE6D0",
|
||||
"B_TERM_UTURN_INT_SS6A1",
|
||||
"B_TERM_UTURN_INT_LV8",
|
||||
"B_TERM_UTURN_INT_LVB_L0",
|
||||
"B_TERM_UTURN_INT_WR1BEG0",
|
||||
"B_TERM_UTURN_INT_SW2BEG0",
|
||||
"B_TERM_UTURN_INT_SW6A3",
|
||||
"B_TERM_UTURN_INT_SE6C1",
|
||||
"B_TERM_UTURN_INT_LV_L8",
|
||||
"B_TERM_UTURN_INT_SS6B0",
|
||||
"B_TERM_UTURN_INT_SW6B3",
|
||||
"B_TERM_UTURN_INT_SW6C2",
|
||||
"B_TERM_UTURN_INT_SW6D0",
|
||||
"B_TERM_UTURN_INT_SS2A0",
|
||||
"B_TERM_UTURN_INT_SS6E1",
|
||||
"B_TERM_UTURN_INT_SE6A0"
|
||||
],
|
||||
"pips": {},
|
||||
"sites": [],
|
||||
"tile_type": "B_TERM_INT",
|
||||
"sites": []
|
||||
}
|
||||
"wires": [
|
||||
"B_TERM_UTURN_INT_ER1BEG0",
|
||||
"B_TERM_UTURN_INT_ER1END_N3_3",
|
||||
"B_TERM_UTURN_INT_FAN_BOUNCE0",
|
||||
"B_TERM_UTURN_INT_FAN_BOUNCE2",
|
||||
"B_TERM_UTURN_INT_FAN_BOUNCE4",
|
||||
"B_TERM_UTURN_INT_FAN_BOUNCE6",
|
||||
"B_TERM_UTURN_INT_LV18",
|
||||
"B_TERM_UTURN_INT_LV2",
|
||||
"B_TERM_UTURN_INT_LV3",
|
||||
"B_TERM_UTURN_INT_LV4",
|
||||
"B_TERM_UTURN_INT_LV5",
|
||||
"B_TERM_UTURN_INT_LV6",
|
||||
"B_TERM_UTURN_INT_LV7",
|
||||
"B_TERM_UTURN_INT_LV8",
|
||||
"B_TERM_UTURN_INT_LV9",
|
||||
"B_TERM_UTURN_INT_LVB0",
|
||||
"B_TERM_UTURN_INT_LVB1",
|
||||
"B_TERM_UTURN_INT_LVB2",
|
||||
"B_TERM_UTURN_INT_LVB3",
|
||||
"B_TERM_UTURN_INT_LVB4",
|
||||
"B_TERM_UTURN_INT_LVB5",
|
||||
"B_TERM_UTURN_INT_LVB_L0",
|
||||
"B_TERM_UTURN_INT_LVB_L1",
|
||||
"B_TERM_UTURN_INT_LVB_L2",
|
||||
"B_TERM_UTURN_INT_LVB_L3",
|
||||
"B_TERM_UTURN_INT_LVB_L4",
|
||||
"B_TERM_UTURN_INT_LVB_L5",
|
||||
"B_TERM_UTURN_INT_LV_L18",
|
||||
"B_TERM_UTURN_INT_LV_L2",
|
||||
"B_TERM_UTURN_INT_LV_L3",
|
||||
"B_TERM_UTURN_INT_LV_L4",
|
||||
"B_TERM_UTURN_INT_LV_L5",
|
||||
"B_TERM_UTURN_INT_LV_L6",
|
||||
"B_TERM_UTURN_INT_LV_L7",
|
||||
"B_TERM_UTURN_INT_LV_L8",
|
||||
"B_TERM_UTURN_INT_LV_L9",
|
||||
"B_TERM_UTURN_INT_SE2BEG0",
|
||||
"B_TERM_UTURN_INT_SE2BEG1",
|
||||
"B_TERM_UTURN_INT_SE2BEG2",
|
||||
"B_TERM_UTURN_INT_SE2BEG3",
|
||||
"B_TERM_UTURN_INT_SE6A0",
|
||||
"B_TERM_UTURN_INT_SE6A1",
|
||||
"B_TERM_UTURN_INT_SE6A2",
|
||||
"B_TERM_UTURN_INT_SE6A3",
|
||||
"B_TERM_UTURN_INT_SE6B0",
|
||||
"B_TERM_UTURN_INT_SE6B1",
|
||||
"B_TERM_UTURN_INT_SE6B2",
|
||||
"B_TERM_UTURN_INT_SE6B3",
|
||||
"B_TERM_UTURN_INT_SE6C0",
|
||||
"B_TERM_UTURN_INT_SE6C1",
|
||||
"B_TERM_UTURN_INT_SE6C2",
|
||||
"B_TERM_UTURN_INT_SE6C3",
|
||||
"B_TERM_UTURN_INT_SE6D0",
|
||||
"B_TERM_UTURN_INT_SE6D1",
|
||||
"B_TERM_UTURN_INT_SE6D2",
|
||||
"B_TERM_UTURN_INT_SE6D3",
|
||||
"B_TERM_UTURN_INT_SL1BEG0",
|
||||
"B_TERM_UTURN_INT_SL1BEG1",
|
||||
"B_TERM_UTURN_INT_SL1BEG2",
|
||||
"B_TERM_UTURN_INT_SL1BEG3",
|
||||
"B_TERM_UTURN_INT_SR1BEG1",
|
||||
"B_TERM_UTURN_INT_SR1BEG2",
|
||||
"B_TERM_UTURN_INT_SR1BEG3",
|
||||
"B_TERM_UTURN_INT_SS2A0",
|
||||
"B_TERM_UTURN_INT_SS2A1",
|
||||
"B_TERM_UTURN_INT_SS2A2",
|
||||
"B_TERM_UTURN_INT_SS2A3",
|
||||
"B_TERM_UTURN_INT_SS2BEG0",
|
||||
"B_TERM_UTURN_INT_SS2BEG1",
|
||||
"B_TERM_UTURN_INT_SS2BEG2",
|
||||
"B_TERM_UTURN_INT_SS2BEG3",
|
||||
"B_TERM_UTURN_INT_SS6A0",
|
||||
"B_TERM_UTURN_INT_SS6A1",
|
||||
"B_TERM_UTURN_INT_SS6A2",
|
||||
"B_TERM_UTURN_INT_SS6A3",
|
||||
"B_TERM_UTURN_INT_SS6B0",
|
||||
"B_TERM_UTURN_INT_SS6B1",
|
||||
"B_TERM_UTURN_INT_SS6B2",
|
||||
"B_TERM_UTURN_INT_SS6B3",
|
||||
"B_TERM_UTURN_INT_SS6BEG0",
|
||||
"B_TERM_UTURN_INT_SS6BEG1",
|
||||
"B_TERM_UTURN_INT_SS6BEG2",
|
||||
"B_TERM_UTURN_INT_SS6BEG3",
|
||||
"B_TERM_UTURN_INT_SS6C0",
|
||||
"B_TERM_UTURN_INT_SS6C1",
|
||||
"B_TERM_UTURN_INT_SS6C2",
|
||||
"B_TERM_UTURN_INT_SS6C3",
|
||||
"B_TERM_UTURN_INT_SS6D0",
|
||||
"B_TERM_UTURN_INT_SS6D1",
|
||||
"B_TERM_UTURN_INT_SS6D2",
|
||||
"B_TERM_UTURN_INT_SS6D3",
|
||||
"B_TERM_UTURN_INT_SS6E0",
|
||||
"B_TERM_UTURN_INT_SS6E1",
|
||||
"B_TERM_UTURN_INT_SS6E2",
|
||||
"B_TERM_UTURN_INT_SS6E3",
|
||||
"B_TERM_UTURN_INT_SW2BEG0",
|
||||
"B_TERM_UTURN_INT_SW2BEG1",
|
||||
"B_TERM_UTURN_INT_SW2BEG2",
|
||||
"B_TERM_UTURN_INT_SW2BEG3",
|
||||
"B_TERM_UTURN_INT_SW6A0",
|
||||
"B_TERM_UTURN_INT_SW6A1",
|
||||
"B_TERM_UTURN_INT_SW6A2",
|
||||
"B_TERM_UTURN_INT_SW6A3",
|
||||
"B_TERM_UTURN_INT_SW6B0",
|
||||
"B_TERM_UTURN_INT_SW6B1",
|
||||
"B_TERM_UTURN_INT_SW6B2",
|
||||
"B_TERM_UTURN_INT_SW6B3",
|
||||
"B_TERM_UTURN_INT_SW6C0",
|
||||
"B_TERM_UTURN_INT_SW6C1",
|
||||
"B_TERM_UTURN_INT_SW6C2",
|
||||
"B_TERM_UTURN_INT_SW6C3",
|
||||
"B_TERM_UTURN_INT_SW6D0",
|
||||
"B_TERM_UTURN_INT_SW6D1",
|
||||
"B_TERM_UTURN_INT_SW6D2",
|
||||
"B_TERM_UTURN_INT_SW6D3",
|
||||
"B_TERM_UTURN_INT_SW6END_N0_3",
|
||||
"B_TERM_UTURN_INT_WR1BEG0",
|
||||
"B_TERM_UTURN_INT_WR1END0"
|
||||
]
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -1,261 +1,261 @@
|
|||
{
|
||||
"pips": {},
|
||||
"sites": [],
|
||||
"tile_type": "CLK_FEED",
|
||||
"wires": [
|
||||
"CLK_FEED_NE2A0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC28",
|
||||
"CLK_FEED_CK_GCLK19",
|
||||
"CLK_FEED_ER1BEG3",
|
||||
"CLK_FEED_CK_BUFG_CASC29",
|
||||
"CLK_FEED_R_CK_GCLK18",
|
||||
"CLK_FEED_R_CK_GCLK6",
|
||||
"CLK_FEED_R_CK_GCLK31",
|
||||
"CLK_FEED_CK_BUFG_CASC0",
|
||||
"CLK_FEED_CK_BUFG_CASC1",
|
||||
"CLK_FEED_LH7",
|
||||
"CLK_FEED_CK_BUFG_CASC3",
|
||||
"CLK_FEED_WW4B2",
|
||||
"CLK_FEED_LH12",
|
||||
"CLK_FEED_R_CK_BUFG_CASC14",
|
||||
"CLK_FEED_EE4A3",
|
||||
"CLK_FEED_CK_BUFG_CASC13",
|
||||
"CLK_FEED_ER1BEG0",
|
||||
"CLK_FEED_SW4END3",
|
||||
"CLK_FEED_WL1END0",
|
||||
"CLK_FEED_SW2A0",
|
||||
"CLK_FEED_R_CK_GCLK13",
|
||||
"CLK_FEED_CK_BUFG_CASC26",
|
||||
"CLK_FEED_SE4BEG1",
|
||||
"CLK_FEED_CK_BUFG_CASC7",
|
||||
"CLK_FEED_CK_BUFG_CASC5",
|
||||
"CLK_FEED_CK_GCLK18",
|
||||
"CLK_FEED_WW4A3",
|
||||
"CLK_FEED_R_CK_BUFG_CASC10",
|
||||
"CLK_FEED_WW4C2",
|
||||
"CLK_FEED_NW4END3",
|
||||
"CLK_FEED_CK_GCLK27",
|
||||
"CLK_FEED_R_CK_GCLK3",
|
||||
"CLK_FEED_CK_BUFG_CASC21",
|
||||
"CLK_FEED_WW2END0",
|
||||
"CLK_FEED_WW2A1",
|
||||
"CLK_FEED_R_CK_BUFG_CASC22",
|
||||
"CLK_FEED_R_CK_BUFG_CASC0",
|
||||
"CLK_FEED_CK_GCLK12",
|
||||
"CLK_FEED_WW2A2",
|
||||
"CLK_FEED_CK_BUFG_CASC10",
|
||||
"CLK_FEED_EE4A2",
|
||||
"CLK_FEED_EE4B0",
|
||||
"CLK_FEED_CK_BUFG_CASC11",
|
||||
"CLK_FEED_CK_BUFG_CASC12",
|
||||
"CLK_FEED_R_CK_BUFG_CASC25",
|
||||
"CLK_FEED_EE4A1",
|
||||
"CLK_FEED_R_CK_BUFG_CASC17",
|
||||
"CLK_FEED_R_CK_BUFG_CASC30",
|
||||
"CLK_FEED_CK_GCLK15",
|
||||
"CLK_FEED_R_CK_BUFG_CASC26",
|
||||
"CLK_FEED_WW2END1",
|
||||
"CLK_FEED_ER1BEG1",
|
||||
"CLK_FEED_EL1BEG0",
|
||||
"CLK_FEED_NE4C3",
|
||||
"CLK_FEED_WW4C0",
|
||||
"CLK_FEED_CK_GCLK24",
|
||||
"CLK_FEED_NE2A2",
|
||||
"CLK_FEED_SE4BEG3",
|
||||
"CLK_FEED_CK_BUFG_CASC4",
|
||||
"CLK_FEED_CK_GCLK23",
|
||||
"CLK_FEED_CK_BUFG_CASC13",
|
||||
"CLK_FEED_CK_BUFG_CASC14",
|
||||
"CLK_FEED_CK_BUFG_CASC15",
|
||||
"CLK_FEED_CK_BUFG_CASC16",
|
||||
"CLK_FEED_CK_BUFG_CASC17",
|
||||
"CLK_FEED_CK_BUFG_CASC18",
|
||||
"CLK_FEED_CK_BUFG_CASC19",
|
||||
"CLK_FEED_CK_BUFG_CASC2",
|
||||
"CLK_FEED_CK_BUFG_CASC20",
|
||||
"CLK_FEED_R_CK_GCLK12",
|
||||
"CLK_FEED_R_CK_BUFG_CASC27",
|
||||
"CLK_FEED_SE4C3",
|
||||
"CLK_FEED_NW4A2",
|
||||
"CLK_FEED_CK_GCLK22",
|
||||
"CLK_FEED_R_CK_GCLK9",
|
||||
"CLK_FEED_CK_GCLK17",
|
||||
"CLK_FEED_CK_BUFG_CASC6",
|
||||
"CLK_FEED_MONITOR_P",
|
||||
"CLK_FEED_NW2A2",
|
||||
"CLK_FEED_EE4BEG1",
|
||||
"CLK_FEED_R_CK_GCLK14",
|
||||
"CLK_FEED_EE4C0",
|
||||
"CLK_FEED_EE4BEG3",
|
||||
"CLK_FEED_NE2A1",
|
||||
"CLK_FEED_WL1END3",
|
||||
"CLK_FEED_CK_GCLK28",
|
||||
"CLK_FEED_WW4B1",
|
||||
"CLK_FEED_WW4END1",
|
||||
"CLK_FEED_SW4END0",
|
||||
"CLK_FEED_R_CK_GCLK17",
|
||||
"CLK_FEED_R_CK_BUFG_CASC11",
|
||||
"CLK_FEED_WW4C1",
|
||||
"CLK_FEED_EL1BEG3",
|
||||
"CLK_FEED_SE2A3",
|
||||
"CLK_FEED_R_CK_GCLK22",
|
||||
"CLK_FEED_NE4C0",
|
||||
"CLK_FEED_WW2A3",
|
||||
"CLK_FEED_NW4END1",
|
||||
"CLK_FEED_SE2A2",
|
||||
"CLK_FEED_EE4B2",
|
||||
"CLK_FEED_R_CK_GCLK29",
|
||||
"CLK_FEED_WW2END3",
|
||||
"CLK_FEED_LH4",
|
||||
"CLK_FEED_WL1END2",
|
||||
"CLK_FEED_CK_GCLK2",
|
||||
"CLK_FEED_R_CK_GCLK25",
|
||||
"CLK_FEED_R_CK_BUFG_CASC13",
|
||||
"CLK_FEED_CK_BUFG_CASC21",
|
||||
"CLK_FEED_CK_BUFG_CASC22",
|
||||
"CLK_FEED_CK_BUFG_CASC23",
|
||||
"CLK_FEED_CK_BUFG_CASC24",
|
||||
"CLK_FEED_CK_BUFG_CASC25",
|
||||
"CLK_FEED_CK_BUFG_CASC26",
|
||||
"CLK_FEED_CK_BUFG_CASC27",
|
||||
"CLK_FEED_NW2A1",
|
||||
"CLK_FEED_SW4A3",
|
||||
"CLK_FEED_CK_BUFG_CASC28",
|
||||
"CLK_FEED_CK_BUFG_CASC29",
|
||||
"CLK_FEED_CK_BUFG_CASC3",
|
||||
"CLK_FEED_CK_BUFG_CASC30",
|
||||
"CLK_FEED_CK_BUFG_CASC31",
|
||||
"CLK_FEED_CK_BUFG_CASC4",
|
||||
"CLK_FEED_CK_BUFG_CASC5",
|
||||
"CLK_FEED_CK_BUFG_CASC6",
|
||||
"CLK_FEED_CK_BUFG_CASC7",
|
||||
"CLK_FEED_CK_BUFG_CASC8",
|
||||
"CLK_FEED_CK_BUFG_CASC9",
|
||||
"CLK_FEED_CK_GCLK0",
|
||||
"CLK_FEED_CK_GCLK1",
|
||||
"CLK_FEED_LH1",
|
||||
"CLK_FEED_CK_GCLK10",
|
||||
"CLK_FEED_CK_GCLK11",
|
||||
"CLK_FEED_CK_GCLK12",
|
||||
"CLK_FEED_CK_GCLK13",
|
||||
"CLK_FEED_CK_GCLK14",
|
||||
"CLK_FEED_R_CK_GCLK2",
|
||||
"CLK_FEED_R_CK_BUFG_CASC2",
|
||||
"CLK_FEED_WR1END0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC20",
|
||||
"CLK_FEED_NE4C1",
|
||||
"CLK_FEED_CK_GCLK15",
|
||||
"CLK_FEED_CK_GCLK16",
|
||||
"CLK_FEED_R_CK_GCLK5",
|
||||
"CLK_FEED_SE4C0",
|
||||
"CLK_FEED_CK_GCLK17",
|
||||
"CLK_FEED_CK_GCLK18",
|
||||
"CLK_FEED_CK_GCLK19",
|
||||
"CLK_FEED_CK_GCLK2",
|
||||
"CLK_FEED_CK_GCLK20",
|
||||
"CLK_FEED_CK_GCLK21",
|
||||
"CLK_FEED_CK_GCLK22",
|
||||
"CLK_FEED_CK_GCLK23",
|
||||
"CLK_FEED_CK_GCLK24",
|
||||
"CLK_FEED_CK_GCLK25",
|
||||
"CLK_FEED_CK_GCLK26",
|
||||
"CLK_FEED_CK_GCLK27",
|
||||
"CLK_FEED_CK_GCLK28",
|
||||
"CLK_FEED_CK_GCLK29",
|
||||
"CLK_FEED_CK_GCLK3",
|
||||
"CLK_FEED_CK_GCLK30",
|
||||
"CLK_FEED_CK_GCLK31",
|
||||
"CLK_FEED_CK_GCLK4",
|
||||
"CLK_FEED_CK_GCLK5",
|
||||
"CLK_FEED_CK_GCLK6",
|
||||
"CLK_FEED_CK_GCLK7",
|
||||
"CLK_FEED_CK_GCLK8",
|
||||
"CLK_FEED_CK_GCLK9",
|
||||
"CLK_FEED_EE2A0",
|
||||
"CLK_FEED_EE2A1",
|
||||
"CLK_FEED_EE2A2",
|
||||
"CLK_FEED_EE2A3",
|
||||
"CLK_FEED_EE2BEG0",
|
||||
"CLK_FEED_EE2BEG1",
|
||||
"CLK_FEED_EE2BEG2",
|
||||
"CLK_FEED_EE2BEG3",
|
||||
"CLK_FEED_EE4A0",
|
||||
"CLK_FEED_EE4A1",
|
||||
"CLK_FEED_EE4A2",
|
||||
"CLK_FEED_EE4A3",
|
||||
"CLK_FEED_EE4B0",
|
||||
"CLK_FEED_EE4B1",
|
||||
"CLK_FEED_EE4B2",
|
||||
"CLK_FEED_EE4B3",
|
||||
"CLK_FEED_EE4BEG0",
|
||||
"CLK_FEED_EE4BEG1",
|
||||
"CLK_FEED_EE4BEG2",
|
||||
"CLK_FEED_EE4BEG3",
|
||||
"CLK_FEED_EE4C0",
|
||||
"CLK_FEED_EE4C1",
|
||||
"CLK_FEED_EE4C2",
|
||||
"CLK_FEED_EE4C3",
|
||||
"CLK_FEED_EL1BEG0",
|
||||
"CLK_FEED_EL1BEG1",
|
||||
"CLK_FEED_EL1BEG2",
|
||||
"CLK_FEED_EE4B1",
|
||||
"CLK_FEED_CK_BUFG_CASC22",
|
||||
"CLK_FEED_WR1END1",
|
||||
"CLK_FEED_NW4END0",
|
||||
"CLK_FEED_EE2BEG1",
|
||||
"CLK_FEED_R_CK_GCLK23",
|
||||
"CLK_FEED_R_CK_GCLK1",
|
||||
"CLK_FEED_LH2",
|
||||
"CLK_FEED_SW2A2",
|
||||
"CLK_FEED_EL1BEG3",
|
||||
"CLK_FEED_ER1BEG0",
|
||||
"CLK_FEED_ER1BEG1",
|
||||
"CLK_FEED_ER1BEG2",
|
||||
"CLK_FEED_WL1END1",
|
||||
"CLK_FEED_NW4A1",
|
||||
"CLK_FEED_SW4A2",
|
||||
"CLK_FEED_CK_GCLK10",
|
||||
"CLK_FEED_CK_BUFG_CASC14",
|
||||
"CLK_FEED_CK_BUFG_CASC28",
|
||||
"CLK_FEED_CK_BUFG_CASC18",
|
||||
"CLK_FEED_R_CK_GCLK24",
|
||||
"CLK_FEED_EE2A1",
|
||||
"CLK_FEED_R_CK_BUFG_CASC15",
|
||||
"CLK_FEED_SW2A1",
|
||||
"CLK_FEED_CK_BUFG_CASC8",
|
||||
"CLK_FEED_CK_BUFG_CASC2",
|
||||
"CLK_FEED_R_CK_BUFG_CASC8",
|
||||
"CLK_FEED_R_CK_GCLK0",
|
||||
"CLK_FEED_WW4B3",
|
||||
"CLK_FEED_CK_GCLK3",
|
||||
"CLK_FEED_LH3",
|
||||
"CLK_FEED_SE2A0",
|
||||
"CLK_FEED_NE4C2",
|
||||
"CLK_FEED_WW4C3",
|
||||
"CLK_FEED_NW4A0",
|
||||
"CLK_FEED_EE4B3",
|
||||
"CLK_FEED_R_CK_GCLK20",
|
||||
"CLK_FEED_CK_BUFG_CASC25",
|
||||
"CLK_FEED_EE2A3",
|
||||
"CLK_FEED_R_CK_GCLK28",
|
||||
"CLK_FEED_LH11",
|
||||
"CLK_FEED_WW4B0",
|
||||
"CLK_FEED_CK_GCLK4",
|
||||
"CLK_FEED_CK_GCLK13",
|
||||
"CLK_FEED_WW2END2",
|
||||
"CLK_FEED_SW4END2",
|
||||
"CLK_FEED_NW2A0",
|
||||
"CLK_FEED_R_CK_GCLK30",
|
||||
"CLK_FEED_R_CK_BUFG_CASC1",
|
||||
"CLK_FEED_CK_GCLK25",
|
||||
"CLK_FEED_CK_BUFG_CASC19",
|
||||
"CLK_FEED_WW4A2",
|
||||
"CLK_FEED_R_CK_BUFG_CASC6",
|
||||
"CLK_FEED_R_CK_BUFG_CASC29",
|
||||
"CLK_FEED_SW4END1",
|
||||
"CLK_FEED_ER1BEG3",
|
||||
"CLK_FEED_LH1",
|
||||
"CLK_FEED_LH10",
|
||||
"CLK_FEED_CK_BUFG_CASC0",
|
||||
"CLK_FEED_NE4BEG3",
|
||||
"CLK_FEED_R_CK_GCLK26",
|
||||
"CLK_FEED_CK_GCLK7",
|
||||
"CLK_FEED_R_CK_BUFG_CASC16",
|
||||
"CLK_FEED_CK_BUFG_CASC23",
|
||||
"CLK_FEED_EE2BEG0",
|
||||
"CLK_FEED_CK_GCLK26",
|
||||
"CLK_FEED_CK_BUFG_CASC15",
|
||||
"CLK_FEED_SW4A1",
|
||||
"CLK_FEED_WW4A0",
|
||||
"CLK_FEED_CK_BUFG_CASC17",
|
||||
"CLK_FEED_LH11",
|
||||
"CLK_FEED_LH12",
|
||||
"CLK_FEED_LH2",
|
||||
"CLK_FEED_LH3",
|
||||
"CLK_FEED_LH4",
|
||||
"CLK_FEED_LH5",
|
||||
"CLK_FEED_LH6",
|
||||
"CLK_FEED_LH7",
|
||||
"CLK_FEED_LH8",
|
||||
"CLK_FEED_LH9",
|
||||
"CLK_FEED_MONITOR_N",
|
||||
"CLK_FEED_MONITOR_P",
|
||||
"CLK_FEED_NE2A0",
|
||||
"CLK_FEED_NE2A1",
|
||||
"CLK_FEED_NE2A2",
|
||||
"CLK_FEED_NE2A3",
|
||||
"CLK_FEED_CK_GCLK21",
|
||||
"CLK_FEED_NE4BEG0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC23",
|
||||
"CLK_FEED_NE4BEG1",
|
||||
"CLK_FEED_WW4END0",
|
||||
"CLK_FEED_NE4BEG2",
|
||||
"CLK_FEED_NE4BEG3",
|
||||
"CLK_FEED_NE4C0",
|
||||
"CLK_FEED_NE4C1",
|
||||
"CLK_FEED_NE4C2",
|
||||
"CLK_FEED_NE4C3",
|
||||
"CLK_FEED_NW2A0",
|
||||
"CLK_FEED_NW2A1",
|
||||
"CLK_FEED_NW2A2",
|
||||
"CLK_FEED_NW2A3",
|
||||
"CLK_FEED_NW4A0",
|
||||
"CLK_FEED_NW4A1",
|
||||
"CLK_FEED_NW4A2",
|
||||
"CLK_FEED_NW4A3",
|
||||
"CLK_FEED_NW4END0",
|
||||
"CLK_FEED_NW4END1",
|
||||
"CLK_FEED_NW4END2",
|
||||
"CLK_FEED_NW4END3",
|
||||
"CLK_FEED_R_CK_BUFG_CASC0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC1",
|
||||
"CLK_FEED_R_CK_BUFG_CASC10",
|
||||
"CLK_FEED_R_CK_BUFG_CASC11",
|
||||
"CLK_FEED_R_CK_BUFG_CASC12",
|
||||
"CLK_FEED_SE4BEG2",
|
||||
"CLK_FEED_EE2BEG3",
|
||||
"CLK_FEED_R_CK_BUFG_CASC13",
|
||||
"CLK_FEED_R_CK_BUFG_CASC14",
|
||||
"CLK_FEED_R_CK_BUFG_CASC15",
|
||||
"CLK_FEED_R_CK_BUFG_CASC16",
|
||||
"CLK_FEED_R_CK_BUFG_CASC17",
|
||||
"CLK_FEED_R_CK_BUFG_CASC18",
|
||||
"CLK_FEED_R_CK_BUFG_CASC19",
|
||||
"CLK_FEED_R_CK_BUFG_CASC2",
|
||||
"CLK_FEED_R_CK_BUFG_CASC20",
|
||||
"CLK_FEED_R_CK_BUFG_CASC21",
|
||||
"CLK_FEED_R_CK_BUFG_CASC22",
|
||||
"CLK_FEED_R_CK_BUFG_CASC23",
|
||||
"CLK_FEED_R_CK_BUFG_CASC24",
|
||||
"CLK_FEED_R_CK_BUFG_CASC25",
|
||||
"CLK_FEED_R_CK_BUFG_CASC26",
|
||||
"CLK_FEED_R_CK_BUFG_CASC27",
|
||||
"CLK_FEED_R_CK_BUFG_CASC28",
|
||||
"CLK_FEED_R_CK_BUFG_CASC29",
|
||||
"CLK_FEED_R_CK_BUFG_CASC3",
|
||||
"CLK_FEED_R_CK_BUFG_CASC30",
|
||||
"CLK_FEED_R_CK_BUFG_CASC31",
|
||||
"CLK_FEED_R_CK_BUFG_CASC4",
|
||||
"CLK_FEED_R_CK_BUFG_CASC5",
|
||||
"CLK_FEED_R_CK_BUFG_CASC6",
|
||||
"CLK_FEED_R_CK_BUFG_CASC7",
|
||||
"CLK_FEED_R_CK_BUFG_CASC8",
|
||||
"CLK_FEED_R_CK_BUFG_CASC9",
|
||||
"CLK_FEED_R_CK_GCLK0",
|
||||
"CLK_FEED_R_CK_GCLK1",
|
||||
"CLK_FEED_R_CK_GCLK10",
|
||||
"CLK_FEED_R_CK_GCLK11",
|
||||
"CLK_FEED_R_CK_GCLK12",
|
||||
"CLK_FEED_R_CK_GCLK13",
|
||||
"CLK_FEED_R_CK_GCLK14",
|
||||
"CLK_FEED_R_CK_GCLK15",
|
||||
"CLK_FEED_R_CK_GCLK16",
|
||||
"CLK_FEED_R_CK_GCLK17",
|
||||
"CLK_FEED_R_CK_GCLK18",
|
||||
"CLK_FEED_R_CK_GCLK19",
|
||||
"CLK_FEED_R_CK_GCLK2",
|
||||
"CLK_FEED_R_CK_GCLK20",
|
||||
"CLK_FEED_R_CK_GCLK21",
|
||||
"CLK_FEED_R_CK_GCLK22",
|
||||
"CLK_FEED_R_CK_GCLK23",
|
||||
"CLK_FEED_R_CK_GCLK24",
|
||||
"CLK_FEED_R_CK_GCLK25",
|
||||
"CLK_FEED_R_CK_GCLK26",
|
||||
"CLK_FEED_R_CK_GCLK27",
|
||||
"CLK_FEED_R_CK_GCLK28",
|
||||
"CLK_FEED_R_CK_GCLK29",
|
||||
"CLK_FEED_R_CK_GCLK3",
|
||||
"CLK_FEED_R_CK_GCLK30",
|
||||
"CLK_FEED_R_CK_GCLK31",
|
||||
"CLK_FEED_R_CK_GCLK4",
|
||||
"CLK_FEED_R_CK_GCLK5",
|
||||
"CLK_FEED_R_CK_GCLK6",
|
||||
"CLK_FEED_R_CK_GCLK7",
|
||||
"CLK_FEED_R_CK_GCLK8",
|
||||
"CLK_FEED_CK_BUFG_CASC30",
|
||||
"CLK_FEED_WW4A1",
|
||||
"CLK_FEED_EE4BEG0",
|
||||
"CLK_FEED_WR1END2",
|
||||
"CLK_FEED_CK_BUFG_CASC24",
|
||||
"CLK_FEED_R_CK_GCLK16",
|
||||
"CLK_FEED_R_CK_GCLK10",
|
||||
"CLK_FEED_CK_BUFG_CASC16",
|
||||
"CLK_FEED_R_CK_BUFG_CASC5",
|
||||
"CLK_FEED_CK_GCLK5",
|
||||
"CLK_FEED_R_CK_BUFG_CASC18",
|
||||
"CLK_FEED_NE4BEG2",
|
||||
"CLK_FEED_R_CK_GCLK11",
|
||||
"CLK_FEED_R_CK_GCLK4",
|
||||
"CLK_FEED_R_CK_BUFG_CASC7",
|
||||
"CLK_FEED_SE4C1",
|
||||
"CLK_FEED_CK_GCLK20",
|
||||
"CLK_FEED_NW4END2",
|
||||
"CLK_FEED_EE4BEG2",
|
||||
"CLK_FEED_CK_GCLK30",
|
||||
"CLK_FEED_R_CK_GCLK9",
|
||||
"CLK_FEED_SE2A0",
|
||||
"CLK_FEED_SE2A1",
|
||||
"CLK_FEED_CK_GCLK29",
|
||||
"CLK_FEED_R_CK_GCLK27",
|
||||
"CLK_FEED_LH6",
|
||||
"CLK_FEED_CK_GCLK9",
|
||||
"CLK_FEED_SW4A0",
|
||||
"CLK_FEED_EE4C1",
|
||||
"CLK_FEED_CK_BUFG_CASC11",
|
||||
"CLK_FEED_CK_GCLK8",
|
||||
"CLK_FEED_R_CK_BUFG_CASC9",
|
||||
"CLK_FEED_R_CK_BUFG_CASC3",
|
||||
"CLK_FEED_WW4END2",
|
||||
"CLK_FEED_CK_GCLK6",
|
||||
"CLK_FEED_EE2A2",
|
||||
"CLK_FEED_EE4C3",
|
||||
"CLK_FEED_NW2A3",
|
||||
"CLK_FEED_R_CK_BUFG_CASC24",
|
||||
"CLK_FEED_EE2A0",
|
||||
"CLK_FEED_R_CK_GCLK19",
|
||||
"CLK_FEED_EE2BEG2",
|
||||
"CLK_FEED_R_CK_BUFG_CASC19",
|
||||
"CLK_FEED_WW4END3",
|
||||
"CLK_FEED_CK_GCLK31",
|
||||
"CLK_FEED_SW2A3",
|
||||
"CLK_FEED_SE4C2",
|
||||
"CLK_FEED_EE4C2",
|
||||
"CLK_FEED_SE2A2",
|
||||
"CLK_FEED_SE2A3",
|
||||
"CLK_FEED_SE4BEG0",
|
||||
"CLK_FEED_LH9",
|
||||
"CLK_FEED_R_CK_GCLK15",
|
||||
"CLK_FEED_LH5",
|
||||
"CLK_FEED_NW4A3",
|
||||
"CLK_FEED_R_CK_BUFG_CASC4",
|
||||
"CLK_FEED_R_CK_BUFG_CASC21",
|
||||
"CLK_FEED_CK_GCLK0",
|
||||
"CLK_FEED_MONITOR_N",
|
||||
"CLK_FEED_CK_GCLK11",
|
||||
"CLK_FEED_R_CK_BUFG_CASC31",
|
||||
"CLK_FEED_R_CK_GCLK21",
|
||||
"CLK_FEED_WW2A0",
|
||||
"CLK_FEED_CK_BUFG_CASC9",
|
||||
"CLK_FEED_EE4A0",
|
||||
"CLK_FEED_SE4BEG1",
|
||||
"CLK_FEED_SE4BEG2",
|
||||
"CLK_FEED_SE4BEG3",
|
||||
"CLK_FEED_SE4C0",
|
||||
"CLK_FEED_SE4C1",
|
||||
"CLK_FEED_SE4C2",
|
||||
"CLK_FEED_SE4C3",
|
||||
"CLK_FEED_SW2A0",
|
||||
"CLK_FEED_SW2A1",
|
||||
"CLK_FEED_SW2A2",
|
||||
"CLK_FEED_SW2A3",
|
||||
"CLK_FEED_SW4A0",
|
||||
"CLK_FEED_SW4A1",
|
||||
"CLK_FEED_SW4A2",
|
||||
"CLK_FEED_SW4A3",
|
||||
"CLK_FEED_SW4END0",
|
||||
"CLK_FEED_SW4END1",
|
||||
"CLK_FEED_SW4END2",
|
||||
"CLK_FEED_SW4END3",
|
||||
"CLK_FEED_WL1END0",
|
||||
"CLK_FEED_WL1END1",
|
||||
"CLK_FEED_WL1END2",
|
||||
"CLK_FEED_WL1END3",
|
||||
"CLK_FEED_WR1END0",
|
||||
"CLK_FEED_WR1END1",
|
||||
"CLK_FEED_WR1END2",
|
||||
"CLK_FEED_WR1END3",
|
||||
"CLK_FEED_LH8"
|
||||
],
|
||||
"pips": {},
|
||||
"tile_type": "CLK_FEED",
|
||||
"sites": []
|
||||
}
|
||||
"CLK_FEED_WW2A0",
|
||||
"CLK_FEED_WW2A1",
|
||||
"CLK_FEED_WW2A2",
|
||||
"CLK_FEED_WW2A3",
|
||||
"CLK_FEED_WW2END0",
|
||||
"CLK_FEED_WW2END1",
|
||||
"CLK_FEED_WW2END2",
|
||||
"CLK_FEED_WW2END3",
|
||||
"CLK_FEED_WW4A0",
|
||||
"CLK_FEED_WW4A1",
|
||||
"CLK_FEED_WW4A2",
|
||||
"CLK_FEED_WW4A3",
|
||||
"CLK_FEED_WW4B0",
|
||||
"CLK_FEED_WW4B1",
|
||||
"CLK_FEED_WW4B2",
|
||||
"CLK_FEED_WW4B3",
|
||||
"CLK_FEED_WW4C0",
|
||||
"CLK_FEED_WW4C1",
|
||||
"CLK_FEED_WW4C2",
|
||||
"CLK_FEED_WW4C3",
|
||||
"CLK_FEED_WW4END0",
|
||||
"CLK_FEED_WW4END1",
|
||||
"CLK_FEED_WW4END2",
|
||||
"CLK_FEED_WW4END3"
|
||||
]
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -1,365 +1,365 @@
|
|||
{
|
||||
"pips": {},
|
||||
"sites": [],
|
||||
"tile_type": "CLK_MTBF2",
|
||||
"wires": [
|
||||
"CLK_FEED_NE2A0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC28",
|
||||
"CLK_FEED_CK_GCLK19",
|
||||
"CLK_FEED_ER1BEG3",
|
||||
"CLK_FEED_CK_BUFG_CASC29",
|
||||
"CLK_FEED_R_CK_GCLK18",
|
||||
"CLK_FEED_R_CK_GCLK31",
|
||||
"CLK_PMV_CLK1_0",
|
||||
"CLK_FEED_CK_BUFG_CASC0",
|
||||
"CLK_FEED_CK_BUFG_CASC1",
|
||||
"CLK_FEED_R_CK_GCLK6",
|
||||
"CLK_FEED_LH7",
|
||||
"CLK_FEED_CK_BUFG_CASC3",
|
||||
"CLK_FEED_WW4B2",
|
||||
"CLK_FEED_LH12",
|
||||
"CLK_FEED_R_CK_BUFG_CASC14",
|
||||
"CLK_FEED_EE4A3",
|
||||
"CLK_FEED_CK_BUFG_CASC10",
|
||||
"CLK_FEED_CK_BUFG_CASC11",
|
||||
"CLK_FEED_CK_BUFG_CASC12",
|
||||
"CLK_FEED_CK_BUFG_CASC13",
|
||||
"CLK_PMV_IMUX28_0",
|
||||
"CLK_PMV_IMUX24_0",
|
||||
"CLK_FEED_CK_BUFG_CASC14",
|
||||
"CLK_FEED_CK_BUFG_CASC15",
|
||||
"CLK_FEED_CK_BUFG_CASC16",
|
||||
"CLK_FEED_CK_BUFG_CASC17",
|
||||
"CLK_FEED_CK_BUFG_CASC18",
|
||||
"CLK_FEED_CK_BUFG_CASC19",
|
||||
"CLK_FEED_CK_BUFG_CASC2",
|
||||
"CLK_FEED_CK_BUFG_CASC20",
|
||||
"CLK_FEED_CK_BUFG_CASC21",
|
||||
"CLK_FEED_CK_BUFG_CASC22",
|
||||
"CLK_FEED_CK_BUFG_CASC23",
|
||||
"CLK_FEED_CK_BUFG_CASC24",
|
||||
"CLK_FEED_CK_BUFG_CASC25",
|
||||
"CLK_FEED_CK_BUFG_CASC26",
|
||||
"CLK_FEED_CK_BUFG_CASC27",
|
||||
"CLK_FEED_CK_BUFG_CASC28",
|
||||
"CLK_FEED_CK_BUFG_CASC29",
|
||||
"CLK_FEED_CK_BUFG_CASC3",
|
||||
"CLK_FEED_CK_BUFG_CASC30",
|
||||
"CLK_FEED_CK_BUFG_CASC31",
|
||||
"CLK_FEED_CK_BUFG_CASC4",
|
||||
"CLK_FEED_CK_BUFG_CASC5",
|
||||
"CLK_FEED_CK_BUFG_CASC6",
|
||||
"CLK_FEED_CK_BUFG_CASC7",
|
||||
"CLK_FEED_CK_BUFG_CASC8",
|
||||
"CLK_FEED_CK_BUFG_CASC9",
|
||||
"CLK_FEED_CK_GCLK0",
|
||||
"CLK_FEED_CK_GCLK1",
|
||||
"CLK_FEED_CK_GCLK10",
|
||||
"CLK_FEED_CK_GCLK11",
|
||||
"CLK_FEED_CK_GCLK12",
|
||||
"CLK_FEED_CK_GCLK13",
|
||||
"CLK_FEED_CK_GCLK14",
|
||||
"CLK_FEED_CK_GCLK15",
|
||||
"CLK_FEED_CK_GCLK16",
|
||||
"CLK_FEED_CK_GCLK17",
|
||||
"CLK_FEED_CK_GCLK18",
|
||||
"CLK_FEED_CK_GCLK19",
|
||||
"CLK_FEED_CK_GCLK2",
|
||||
"CLK_FEED_CK_GCLK20",
|
||||
"CLK_FEED_CK_GCLK21",
|
||||
"CLK_FEED_CK_GCLK22",
|
||||
"CLK_FEED_CK_GCLK23",
|
||||
"CLK_FEED_CK_GCLK24",
|
||||
"CLK_FEED_CK_GCLK25",
|
||||
"CLK_FEED_CK_GCLK26",
|
||||
"CLK_FEED_CK_GCLK27",
|
||||
"CLK_FEED_CK_GCLK28",
|
||||
"CLK_FEED_CK_GCLK29",
|
||||
"CLK_FEED_CK_GCLK3",
|
||||
"CLK_FEED_CK_GCLK30",
|
||||
"CLK_FEED_CK_GCLK31",
|
||||
"CLK_FEED_CK_GCLK4",
|
||||
"CLK_FEED_CK_GCLK5",
|
||||
"CLK_FEED_CK_GCLK6",
|
||||
"CLK_FEED_CK_GCLK7",
|
||||
"CLK_FEED_CK_GCLK8",
|
||||
"CLK_FEED_CK_GCLK9",
|
||||
"CLK_FEED_EE2A0",
|
||||
"CLK_FEED_EE2A1",
|
||||
"CLK_FEED_EE2A2",
|
||||
"CLK_FEED_EE2A3",
|
||||
"CLK_FEED_EE2BEG0",
|
||||
"CLK_FEED_EE2BEG1",
|
||||
"CLK_FEED_EE2BEG2",
|
||||
"CLK_FEED_EE2BEG3",
|
||||
"CLK_FEED_EE4A0",
|
||||
"CLK_FEED_EE4A1",
|
||||
"CLK_FEED_EE4A2",
|
||||
"CLK_FEED_EE4A3",
|
||||
"CLK_FEED_EE4B0",
|
||||
"CLK_FEED_EE4B1",
|
||||
"CLK_FEED_EE4B2",
|
||||
"CLK_FEED_EE4B3",
|
||||
"CLK_FEED_EE4BEG0",
|
||||
"CLK_FEED_EE4BEG1",
|
||||
"CLK_FEED_EE4BEG2",
|
||||
"CLK_FEED_EE4BEG3",
|
||||
"CLK_FEED_EE4C0",
|
||||
"CLK_FEED_EE4C1",
|
||||
"CLK_FEED_EE4C2",
|
||||
"CLK_FEED_EE4C3",
|
||||
"CLK_FEED_EL1BEG0",
|
||||
"CLK_FEED_EL1BEG1",
|
||||
"CLK_FEED_EL1BEG2",
|
||||
"CLK_FEED_EL1BEG3",
|
||||
"CLK_FEED_ER1BEG0",
|
||||
"CLK_PMV_IMUX44_0",
|
||||
"CLK_FEED_ER1BEG1",
|
||||
"CLK_FEED_ER1BEG2",
|
||||
"CLK_FEED_ER1BEG3",
|
||||
"CLK_FEED_LH1",
|
||||
"CLK_FEED_LH10",
|
||||
"CLK_FEED_LH11",
|
||||
"CLK_FEED_LH12",
|
||||
"CLK_FEED_LH2",
|
||||
"CLK_FEED_LH3",
|
||||
"CLK_FEED_LH4",
|
||||
"CLK_FEED_LH5",
|
||||
"CLK_FEED_LH6",
|
||||
"CLK_FEED_LH7",
|
||||
"CLK_FEED_LH8",
|
||||
"CLK_FEED_LH9",
|
||||
"CLK_FEED_MONITOR_N",
|
||||
"CLK_FEED_MONITOR_P",
|
||||
"CLK_FEED_NE2A0",
|
||||
"CLK_FEED_NE2A1",
|
||||
"CLK_FEED_NE2A2",
|
||||
"CLK_FEED_NE2A3",
|
||||
"CLK_FEED_NE4BEG0",
|
||||
"CLK_FEED_NE4BEG1",
|
||||
"CLK_FEED_NE4BEG2",
|
||||
"CLK_FEED_NE4BEG3",
|
||||
"CLK_FEED_NE4C0",
|
||||
"CLK_FEED_NE4C1",
|
||||
"CLK_FEED_NE4C2",
|
||||
"CLK_FEED_NE4C3",
|
||||
"CLK_FEED_NW2A0",
|
||||
"CLK_FEED_NW2A1",
|
||||
"CLK_FEED_NW2A2",
|
||||
"CLK_FEED_NW2A3",
|
||||
"CLK_FEED_NW4A0",
|
||||
"CLK_FEED_NW4A1",
|
||||
"CLK_FEED_NW4A2",
|
||||
"CLK_FEED_NW4A3",
|
||||
"CLK_FEED_NW4END0",
|
||||
"CLK_FEED_NW4END1",
|
||||
"CLK_FEED_NW4END2",
|
||||
"CLK_FEED_NW4END3",
|
||||
"CLK_FEED_R_CK_BUFG_CASC0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC1",
|
||||
"CLK_FEED_R_CK_BUFG_CASC10",
|
||||
"CLK_FEED_R_CK_BUFG_CASC11",
|
||||
"CLK_FEED_R_CK_BUFG_CASC12",
|
||||
"CLK_FEED_R_CK_BUFG_CASC13",
|
||||
"CLK_FEED_R_CK_BUFG_CASC14",
|
||||
"CLK_FEED_R_CK_BUFG_CASC15",
|
||||
"CLK_FEED_R_CK_BUFG_CASC16",
|
||||
"CLK_FEED_R_CK_BUFG_CASC17",
|
||||
"CLK_FEED_R_CK_BUFG_CASC18",
|
||||
"CLK_FEED_R_CK_BUFG_CASC19",
|
||||
"CLK_FEED_R_CK_BUFG_CASC2",
|
||||
"CLK_FEED_R_CK_BUFG_CASC20",
|
||||
"CLK_FEED_R_CK_BUFG_CASC21",
|
||||
"CLK_FEED_R_CK_BUFG_CASC22",
|
||||
"CLK_FEED_R_CK_BUFG_CASC23",
|
||||
"CLK_FEED_R_CK_BUFG_CASC24",
|
||||
"CLK_FEED_R_CK_BUFG_CASC25",
|
||||
"CLK_FEED_R_CK_BUFG_CASC26",
|
||||
"CLK_FEED_R_CK_BUFG_CASC27",
|
||||
"CLK_FEED_R_CK_BUFG_CASC28",
|
||||
"CLK_FEED_R_CK_BUFG_CASC29",
|
||||
"CLK_FEED_R_CK_BUFG_CASC3",
|
||||
"CLK_FEED_R_CK_BUFG_CASC30",
|
||||
"CLK_FEED_R_CK_BUFG_CASC31",
|
||||
"CLK_FEED_R_CK_BUFG_CASC4",
|
||||
"CLK_FEED_R_CK_BUFG_CASC5",
|
||||
"CLK_FEED_R_CK_BUFG_CASC6",
|
||||
"CLK_FEED_R_CK_BUFG_CASC7",
|
||||
"CLK_FEED_R_CK_BUFG_CASC8",
|
||||
"CLK_FEED_R_CK_BUFG_CASC9",
|
||||
"CLK_FEED_R_CK_GCLK0",
|
||||
"CLK_FEED_R_CK_GCLK1",
|
||||
"CLK_FEED_R_CK_GCLK10",
|
||||
"CLK_FEED_R_CK_GCLK11",
|
||||
"CLK_FEED_R_CK_GCLK12",
|
||||
"CLK_FEED_R_CK_GCLK13",
|
||||
"CLK_FEED_R_CK_GCLK14",
|
||||
"CLK_FEED_R_CK_GCLK15",
|
||||
"CLK_FEED_R_CK_GCLK16",
|
||||
"CLK_FEED_R_CK_GCLK17",
|
||||
"CLK_FEED_R_CK_GCLK18",
|
||||
"CLK_FEED_R_CK_GCLK19",
|
||||
"CLK_FEED_R_CK_GCLK2",
|
||||
"CLK_FEED_R_CK_GCLK20",
|
||||
"CLK_FEED_R_CK_GCLK21",
|
||||
"CLK_FEED_R_CK_GCLK22",
|
||||
"CLK_FEED_R_CK_GCLK23",
|
||||
"CLK_FEED_R_CK_GCLK24",
|
||||
"CLK_FEED_R_CK_GCLK25",
|
||||
"CLK_FEED_R_CK_GCLK26",
|
||||
"CLK_FEED_R_CK_GCLK27",
|
||||
"CLK_FEED_R_CK_GCLK28",
|
||||
"CLK_FEED_R_CK_GCLK29",
|
||||
"CLK_FEED_R_CK_GCLK3",
|
||||
"CLK_FEED_R_CK_GCLK30",
|
||||
"CLK_FEED_R_CK_GCLK31",
|
||||
"CLK_FEED_R_CK_GCLK4",
|
||||
"CLK_FEED_R_CK_GCLK5",
|
||||
"CLK_FEED_R_CK_GCLK6",
|
||||
"CLK_FEED_R_CK_GCLK7",
|
||||
"CLK_FEED_R_CK_GCLK8",
|
||||
"CLK_FEED_R_CK_GCLK9",
|
||||
"CLK_FEED_SE2A0",
|
||||
"CLK_FEED_SE2A1",
|
||||
"CLK_FEED_SE2A2",
|
||||
"CLK_FEED_SE2A3",
|
||||
"CLK_FEED_SE4BEG0",
|
||||
"CLK_FEED_SE4BEG1",
|
||||
"CLK_FEED_SE4BEG2",
|
||||
"CLK_FEED_SE4BEG3",
|
||||
"CLK_FEED_SE4C0",
|
||||
"CLK_FEED_SE4C1",
|
||||
"CLK_FEED_SE4C2",
|
||||
"CLK_FEED_SE4C3",
|
||||
"CLK_FEED_SW2A0",
|
||||
"CLK_FEED_SW2A1",
|
||||
"CLK_FEED_SW2A2",
|
||||
"CLK_FEED_SW2A3",
|
||||
"CLK_FEED_SW4A0",
|
||||
"CLK_FEED_SW4A1",
|
||||
"CLK_FEED_SW4A2",
|
||||
"CLK_FEED_SW4A3",
|
||||
"CLK_FEED_SW4END0",
|
||||
"CLK_FEED_SW4END1",
|
||||
"CLK_FEED_SW4END2",
|
||||
"CLK_FEED_SW4END3",
|
||||
"CLK_FEED_WL1END0",
|
||||
"CLK_FEED_SW2A0",
|
||||
"CLK_PMV_IMUX15_0",
|
||||
"CLK_PMV_IMUX43_0",
|
||||
"CLK_PMV_FAN0_0",
|
||||
"CLK_FEED_R_CK_GCLK13",
|
||||
"CLK_PMV_FAN1_0",
|
||||
"CLK_FEED_CK_BUFG_CASC26",
|
||||
"CLK_FEED_SE4BEG1",
|
||||
"CLK_FEED_CK_BUFG_CASC7",
|
||||
"CLK_PMV_IMUX11_0",
|
||||
"CLK_PMV_LOGIC_OUTS12_0",
|
||||
"CLK_FEED_CK_BUFG_CASC5",
|
||||
"CLK_FEED_CK_GCLK18",
|
||||
"CLK_PMV_BYP0_0",
|
||||
"CLK_FEED_WW4A3",
|
||||
"CLK_FEED_R_CK_BUFG_CASC10",
|
||||
"CLK_FEED_WW4C2",
|
||||
"CLK_FEED_NW4END3",
|
||||
"CLK_FEED_CK_GCLK27",
|
||||
"CLK_PMV_IMUX33_0",
|
||||
"CLK_FEED_R_CK_GCLK3",
|
||||
"CLK_FEED_CK_BUFG_CASC21",
|
||||
"CLK_FEED_WW2END0",
|
||||
"CLK_FEED_WW2A1",
|
||||
"CLK_PMV_LOGIC_OUTS18_0",
|
||||
"CLK_PMV_IMUX26_0",
|
||||
"CLK_MTBF2_Q3B",
|
||||
"CLK_FEED_R_CK_BUFG_CASC22",
|
||||
"CLK_PMV_LOGIC_OUTS3_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC0",
|
||||
"CLK_FEED_EE4A2",
|
||||
"CLK_FEED_CK_GCLK12",
|
||||
"CLK_FEED_EE4B0",
|
||||
"CLK_FEED_WW2A2",
|
||||
"CLK_FEED_CK_BUFG_CASC10",
|
||||
"CLK_FEED_CK_BUFG_CASC12",
|
||||
"CLK_FEED_R_CK_BUFG_CASC25",
|
||||
"CLK_FEED_EE4A1",
|
||||
"CLK_PMV_LOGIC_OUTS23_0",
|
||||
"CLK_PMV_IMUX29_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC17",
|
||||
"CLK_PMV_LOGIC_OUTS5_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC30",
|
||||
"CLK_PMV_IMUX31_0",
|
||||
"CLK_FEED_CK_GCLK15",
|
||||
"CLK_FEED_R_CK_BUFG_CASC26",
|
||||
"CLK_FEED_WW2END1",
|
||||
"CLK_FEED_ER1BEG1",
|
||||
"CLK_FEED_EL1BEG0",
|
||||
"CLK_PMV_LOGIC_OUTS1_0",
|
||||
"CLK_PMV_LOGIC_OUTS21_0",
|
||||
"CLK_FEED_NE4C3",
|
||||
"CLK_FEED_WW4C0",
|
||||
"CLK_PMV_IMUX20_0",
|
||||
"CLK_PMV_BYP4_0",
|
||||
"CLK_FEED_CK_GCLK24",
|
||||
"CLK_FEED_NE2A2",
|
||||
"CLK_FEED_SE4BEG3",
|
||||
"CLK_PMV_LOGIC_OUTS16_0",
|
||||
"CLK_PMV_IMUX16_0",
|
||||
"CLK_FEED_CK_BUFG_CASC4",
|
||||
"CLK_PMV_IMUX9_0",
|
||||
"CLK_FEED_CK_GCLK23",
|
||||
"CLK_FEED_CK_BUFG_CASC20",
|
||||
"CLK_FEED_R_CK_GCLK12",
|
||||
"CLK_FEED_R_CK_BUFG_CASC27",
|
||||
"CLK_FEED_SE4C3",
|
||||
"CLK_FEED_CK_GCLK22",
|
||||
"CLK_FEED_NW4A2",
|
||||
"CLK_FEED_R_CK_GCLK9",
|
||||
"CLK_FEED_CK_GCLK17",
|
||||
"CLK_PMV_BYP7_0",
|
||||
"CLK_FEED_CK_BUFG_CASC6",
|
||||
"CLK_FEED_MONITOR_P",
|
||||
"CLK_FEED_NW2A2",
|
||||
"CLK_FEED_EE4BEG1",
|
||||
"CLK_FEED_R_CK_GCLK14",
|
||||
"CLK_FEED_EE4C0",
|
||||
"CLK_PMV_IMUX2_0",
|
||||
"CLK_FEED_EE4BEG3",
|
||||
"CLK_FEED_NE2A1",
|
||||
"CLK_FEED_WL1END3",
|
||||
"CLK_FEED_CK_GCLK28",
|
||||
"CLK_MTBF2_Q1B",
|
||||
"CLK_PMV_IMUX35_0",
|
||||
"CLK_PMV_LOGIC_OUTS7_0",
|
||||
"CLK_FEED_WW4B1",
|
||||
"CLK_FEED_SW4END0",
|
||||
"CLK_FEED_WW4END1",
|
||||
"CLK_FEED_R_CK_GCLK17",
|
||||
"CLK_FEED_R_CK_BUFG_CASC11",
|
||||
"CLK_MTBF2_Q0B",
|
||||
"CLK_FEED_WW4C1",
|
||||
"CLK_FEED_EL1BEG3",
|
||||
"CLK_MTBF2_DIN",
|
||||
"CLK_PMV_IMUX17_0",
|
||||
"CLK_FEED_SE2A3",
|
||||
"CLK_FEED_R_CK_GCLK22",
|
||||
"CLK_FEED_NE4C0",
|
||||
"CLK_FEED_WW2A3",
|
||||
"CLK_FEED_NW4END1",
|
||||
"CLK_MTBF2_Q4B",
|
||||
"CLK_PMV_IMUX8_0",
|
||||
"CLK_MTBF2_Q2B",
|
||||
"CLK_FEED_SE2A2",
|
||||
"CLK_FEED_EE4B2",
|
||||
"CLK_MTBF2_Q5B",
|
||||
"CLK_FEED_R_CK_GCLK29",
|
||||
"CLK_FEED_WW2END3",
|
||||
"CLK_FEED_LH4",
|
||||
"CLK_FEED_WL1END2",
|
||||
"CLK_FEED_CK_GCLK2",
|
||||
"CLK_FEED_R_CK_GCLK25",
|
||||
"CLK_PMV_FAN3_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC13",
|
||||
"CLK_FEED_CK_BUFG_CASC27",
|
||||
"CLK_FEED_NW2A1",
|
||||
"CLK_FEED_SW4A3",
|
||||
"CLK_FEED_CK_BUFG_CASC31",
|
||||
"CLK_PMV_BYP3_0",
|
||||
"CLK_FEED_CK_GCLK1",
|
||||
"CLK_FEED_LH1",
|
||||
"CLK_FEED_CK_GCLK14",
|
||||
"CLK_FEED_R_CK_GCLK2",
|
||||
"CLK_FEED_R_CK_BUFG_CASC2",
|
||||
"CLK_PMV_CLK0_0",
|
||||
"CLK_FEED_WR1END0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC20",
|
||||
"CLK_FEED_NE4C1",
|
||||
"CLK_FEED_CK_GCLK16",
|
||||
"CLK_PMV_FAN2_0",
|
||||
"CLK_FEED_R_CK_GCLK5",
|
||||
"CLK_FEED_SE4C0",
|
||||
"CLK_FEED_EL1BEG2",
|
||||
"CLK_FEED_EL1BEG1",
|
||||
"CLK_FEED_EE4B1",
|
||||
"CLK_FEED_CK_BUFG_CASC22",
|
||||
"CLK_PMV_IMUX40_0",
|
||||
"CLK_FEED_WR1END1",
|
||||
"CLK_FEED_NW4END0",
|
||||
"CLK_PMV_IMUX42_0",
|
||||
"CLK_FEED_EE2BEG1",
|
||||
"CLK_FEED_R_CK_GCLK23",
|
||||
"CLK_FEED_R_CK_GCLK1",
|
||||
"CLK_FEED_LH2",
|
||||
"CLK_FEED_SW2A2",
|
||||
"CLK_FEED_ER1BEG2",
|
||||
"CLK_FEED_WL1END1",
|
||||
"CLK_PMV_IMUX47_0",
|
||||
"CLK_FEED_NW4A1",
|
||||
"CLK_PMV_BYP1_0",
|
||||
"CLK_PMV_IMUX5_0",
|
||||
"CLK_FEED_SW4A2",
|
||||
"CLK_FEED_CK_GCLK10",
|
||||
"CLK_FEED_CK_BUFG_CASC14",
|
||||
"CLK_FEED_CK_BUFG_CASC28",
|
||||
"CLK_PMV_FAN7_0",
|
||||
"CLK_FEED_CK_BUFG_CASC18",
|
||||
"CLK_FEED_R_CK_GCLK24",
|
||||
"CLK_FEED_EE2A1",
|
||||
"CLK_FEED_R_CK_BUFG_CASC15",
|
||||
"CLK_PMV_LOGIC_OUTS10_0",
|
||||
"CLK_FEED_SW2A1",
|
||||
"CLK_FEED_CK_BUFG_CASC8",
|
||||
"CLK_PMV_IMUX45_0",
|
||||
"CLK_FEED_CK_BUFG_CASC2",
|
||||
"CLK_FEED_R_CK_BUFG_CASC8",
|
||||
"CLK_PMV_BYP2_0",
|
||||
"CLK_PMV_IMUX14_0",
|
||||
"CLK_FEED_R_CK_GCLK0",
|
||||
"CLK_FEED_WW4B3",
|
||||
"CLK_PMV_IMUX7_0",
|
||||
"CLK_MTBF2_RESET",
|
||||
"CLK_FEED_CK_GCLK3",
|
||||
"CLK_FEED_LH3",
|
||||
"CLK_PMV_IMUX6_0",
|
||||
"CLK_FEED_SE2A0",
|
||||
"CLK_FEED_NE4C2",
|
||||
"CLK_FEED_WW4C3",
|
||||
"CLK_PMV_IMUX38_0",
|
||||
"CLK_PMV_FAN6_0",
|
||||
"CLK_FEED_EE4B3",
|
||||
"CLK_FEED_NW4A0",
|
||||
"CLK_FEED_CK_BUFG_CASC25",
|
||||
"CLK_FEED_R_CK_GCLK20",
|
||||
"CLK_FEED_EE2A3",
|
||||
"CLK_FEED_R_CK_GCLK28",
|
||||
"CLK_FEED_LH11",
|
||||
"CLK_FEED_WW4B0",
|
||||
"CLK_PMV_IMUX30_0",
|
||||
"CLK_PMV_FAN4_0",
|
||||
"CLK_FEED_CK_GCLK4",
|
||||
"CLK_FEED_CK_GCLK13",
|
||||
"CLK_FEED_WW2END2",
|
||||
"CLK_FEED_SW4END2",
|
||||
"CLK_PMV_LOGIC_OUTS4_0",
|
||||
"CLK_PMV_LOGIC_OUTS6_0",
|
||||
"CLK_FEED_NW2A0",
|
||||
"CLK_FEED_R_CK_GCLK30",
|
||||
"CLK_FEED_R_CK_BUFG_CASC1",
|
||||
"CLK_FEED_CK_GCLK25",
|
||||
"CLK_PMV_IMUX1_0",
|
||||
"CLK_FEED_CK_BUFG_CASC19",
|
||||
"CLK_PMV_IMUX34_0",
|
||||
"CLK_FEED_WW4A2",
|
||||
"CLK_MTBF2_EN",
|
||||
"CLK_FEED_R_CK_BUFG_CASC6",
|
||||
"CLK_PMV_LOGIC_OUTS17_0",
|
||||
"CLK_PMV_LOGIC_OUTS9_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC29",
|
||||
"CLK_FEED_SW4END1",
|
||||
"CLK_FEED_LH10",
|
||||
"CLK_FEED_CK_BUFG_CASC0",
|
||||
"CLK_PMV_IMUX21_0",
|
||||
"CLK_FEED_NE4BEG3",
|
||||
"CLK_FEED_R_CK_GCLK26",
|
||||
"CLK_PMV_IMUX41_0",
|
||||
"CLK_PMV_IMUX46_0",
|
||||
"CLK_PMV_IMUX25_0",
|
||||
"CLK_PMV_IMUX39_0",
|
||||
"CLK_FEED_CK_GCLK7",
|
||||
"CLK_FEED_CK_BUFG_CASC23",
|
||||
"CLK_FEED_R_CK_BUFG_CASC16",
|
||||
"CLK_FEED_EE2BEG0",
|
||||
"CLK_FEED_CK_GCLK26",
|
||||
"CLK_FEED_CK_BUFG_CASC15",
|
||||
"CLK_FEED_SW4A1",
|
||||
"CLK_FEED_WW4A0",
|
||||
"CLK_PMV_IMUX22_0",
|
||||
"CLK_PMV_LOGIC_OUTS11_0",
|
||||
"CLK_PMV_BYP5_0",
|
||||
"CLK_PMV_LOGIC_OUTS15_0",
|
||||
"CLK_FEED_NE2A3",
|
||||
"CLK_FEED_CK_BUFG_CASC17",
|
||||
"CLK_FEED_CK_GCLK21",
|
||||
"CLK_MTBF2_CLK",
|
||||
"CLK_PMV_LOGIC_OUTS0_0",
|
||||
"CLK_FEED_NE4BEG0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC23",
|
||||
"CLK_FEED_NE4BEG1",
|
||||
"CLK_PMV_LOGIC_OUTS19_0",
|
||||
"CLK_FEED_WW4END0",
|
||||
"CLK_MTBF2_Q7B",
|
||||
"CLK_FEED_R_CK_BUFG_CASC12",
|
||||
"CLK_FEED_SE4BEG2",
|
||||
"CLK_FEED_EE2BEG3",
|
||||
"CLK_FEED_R_CK_GCLK7",
|
||||
"CLK_PMV_IMUX4_0",
|
||||
"CLK_FEED_CK_BUFG_CASC30",
|
||||
"CLK_FEED_R_CK_GCLK8",
|
||||
"CLK_FEED_WW4A1",
|
||||
"CLK_FEED_EE4BEG0",
|
||||
"CLK_FEED_WL1END2",
|
||||
"CLK_FEED_WL1END3",
|
||||
"CLK_FEED_WR1END0",
|
||||
"CLK_FEED_WR1END1",
|
||||
"CLK_FEED_WR1END2",
|
||||
"CLK_FEED_CK_BUFG_CASC24",
|
||||
"CLK_FEED_R_CK_GCLK16",
|
||||
"CLK_FEED_R_CK_GCLK10",
|
||||
"CLK_FEED_CK_BUFG_CASC16",
|
||||
"CLK_MTBF2_Q6B",
|
||||
"CLK_FEED_R_CK_BUFG_CASC5",
|
||||
"CLK_FEED_CK_GCLK5",
|
||||
"CLK_FEED_R_CK_BUFG_CASC18",
|
||||
"CLK_FEED_NE4BEG2",
|
||||
"CLK_PMV_LOGIC_OUTS20_0",
|
||||
"CLK_FEED_R_CK_GCLK4",
|
||||
"CLK_FEED_R_CK_GCLK11",
|
||||
"CLK_PMV_IMUX12_0",
|
||||
"CLK_PMV_IMUX37_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC7",
|
||||
"CLK_PMV_IMUX18_0",
|
||||
"CLK_FEED_SE4C1",
|
||||
"CLK_FEED_CK_GCLK20",
|
||||
"CLK_PMV_LOGIC_OUTS8_0",
|
||||
"CLK_FEED_NW4END2",
|
||||
"CLK_FEED_EE4BEG2",
|
||||
"CLK_FEED_CK_GCLK30",
|
||||
"CLK_FEED_SE2A1",
|
||||
"CLK_FEED_LH6",
|
||||
"CLK_FEED_CK_GCLK29",
|
||||
"CLK_FEED_R_CK_GCLK27",
|
||||
"CLK_FEED_EE4C1",
|
||||
"CLK_FEED_SW4A0",
|
||||
"CLK_FEED_CK_GCLK9",
|
||||
"CLK_FEED_CK_BUFG_CASC11",
|
||||
"CLK_FEED_CK_GCLK8",
|
||||
"CLK_FEED_R_CK_BUFG_CASC9",
|
||||
"CLK_FEED_R_CK_BUFG_CASC3",
|
||||
"CLK_FEED_WW4END2",
|
||||
"CLK_FEED_CK_GCLK6",
|
||||
"CLK_FEED_EE2A2",
|
||||
"CLK_PMV_LOGIC_OUTS14_0",
|
||||
"CLK_PMV_LOGIC_OUTS2_0",
|
||||
"CLK_FEED_EE4C3",
|
||||
"CLK_FEED_NW2A3",
|
||||
"CLK_PMV_CTRL0_0",
|
||||
"CLK_PMV_LOGIC_OUTS22_0",
|
||||
"CLK_PMV_IMUX0_0",
|
||||
"CLK_FEED_EE2A0",
|
||||
"CLK_PMV_FAN5_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC24",
|
||||
"CLK_PMV_BYP6_0",
|
||||
"CLK_FEED_R_CK_GCLK19",
|
||||
"CLK_FEED_EE2BEG2",
|
||||
"CLK_FEED_R_CK_BUFG_CASC19",
|
||||
"CLK_FEED_WW4END3",
|
||||
"CLK_FEED_CK_GCLK31",
|
||||
"CLK_FEED_SW2A3",
|
||||
"CLK_PMV_IMUX23_0",
|
||||
"CLK_PMV_IMUX19_0",
|
||||
"CLK_PMV_IMUX36_0",
|
||||
"CLK_FEED_SE4C2",
|
||||
"CLK_FEED_EE4C2",
|
||||
"CLK_PMV_IMUX13_0",
|
||||
"CLK_FEED_SE4BEG0",
|
||||
"CLK_PMV_IMUX27_0",
|
||||
"CLK_FEED_LH9",
|
||||
"CLK_FEED_R_CK_GCLK15",
|
||||
"CLK_PMV_IMUX3_0",
|
||||
"CLK_PMV_CTRL1_0",
|
||||
"CLK_FEED_LH5",
|
||||
"CLK_PMV_LOGIC_OUTS13_0",
|
||||
"CLK_FEED_NW4A3",
|
||||
"CLK_PMV_IMUX10_0",
|
||||
"CLK_PMV_IMUX32_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC4",
|
||||
"CLK_FEED_R_CK_BUFG_CASC21",
|
||||
"CLK_FEED_CK_GCLK0",
|
||||
"CLK_FEED_MONITOR_N",
|
||||
"CLK_FEED_CK_GCLK11",
|
||||
"CLK_FEED_R_CK_BUFG_CASC31",
|
||||
"CLK_FEED_WW2A0",
|
||||
"CLK_FEED_EE4A0",
|
||||
"CLK_FEED_CK_BUFG_CASC9",
|
||||
"CLK_FEED_R_CK_GCLK21",
|
||||
"CLK_FEED_WR1END3",
|
||||
"CLK_FEED_LH8"
|
||||
],
|
||||
"pips": {},
|
||||
"tile_type": "CLK_MTBF2",
|
||||
"sites": []
|
||||
}
|
||||
"CLK_FEED_WW2A0",
|
||||
"CLK_FEED_WW2A1",
|
||||
"CLK_FEED_WW2A2",
|
||||
"CLK_FEED_WW2A3",
|
||||
"CLK_FEED_WW2END0",
|
||||
"CLK_FEED_WW2END1",
|
||||
"CLK_FEED_WW2END2",
|
||||
"CLK_FEED_WW2END3",
|
||||
"CLK_FEED_WW4A0",
|
||||
"CLK_FEED_WW4A1",
|
||||
"CLK_FEED_WW4A2",
|
||||
"CLK_FEED_WW4A3",
|
||||
"CLK_FEED_WW4B0",
|
||||
"CLK_FEED_WW4B1",
|
||||
"CLK_FEED_WW4B2",
|
||||
"CLK_FEED_WW4B3",
|
||||
"CLK_FEED_WW4C0",
|
||||
"CLK_FEED_WW4C1",
|
||||
"CLK_FEED_WW4C2",
|
||||
"CLK_FEED_WW4C3",
|
||||
"CLK_FEED_WW4END0",
|
||||
"CLK_FEED_WW4END1",
|
||||
"CLK_FEED_WW4END2",
|
||||
"CLK_FEED_WW4END3",
|
||||
"CLK_MTBF2_CLK",
|
||||
"CLK_MTBF2_DIN",
|
||||
"CLK_MTBF2_EN",
|
||||
"CLK_MTBF2_Q0B",
|
||||
"CLK_MTBF2_Q1B",
|
||||
"CLK_MTBF2_Q2B",
|
||||
"CLK_MTBF2_Q3B",
|
||||
"CLK_MTBF2_Q4B",
|
||||
"CLK_MTBF2_Q5B",
|
||||
"CLK_MTBF2_Q6B",
|
||||
"CLK_MTBF2_Q7B",
|
||||
"CLK_MTBF2_RESET",
|
||||
"CLK_PMV_BYP0_0",
|
||||
"CLK_PMV_BYP1_0",
|
||||
"CLK_PMV_BYP2_0",
|
||||
"CLK_PMV_BYP3_0",
|
||||
"CLK_PMV_BYP4_0",
|
||||
"CLK_PMV_BYP5_0",
|
||||
"CLK_PMV_BYP6_0",
|
||||
"CLK_PMV_BYP7_0",
|
||||
"CLK_PMV_CLK0_0",
|
||||
"CLK_PMV_CLK1_0",
|
||||
"CLK_PMV_CTRL0_0",
|
||||
"CLK_PMV_CTRL1_0",
|
||||
"CLK_PMV_FAN0_0",
|
||||
"CLK_PMV_FAN1_0",
|
||||
"CLK_PMV_FAN2_0",
|
||||
"CLK_PMV_FAN3_0",
|
||||
"CLK_PMV_FAN4_0",
|
||||
"CLK_PMV_FAN5_0",
|
||||
"CLK_PMV_FAN6_0",
|
||||
"CLK_PMV_FAN7_0",
|
||||
"CLK_PMV_IMUX0_0",
|
||||
"CLK_PMV_IMUX10_0",
|
||||
"CLK_PMV_IMUX11_0",
|
||||
"CLK_PMV_IMUX12_0",
|
||||
"CLK_PMV_IMUX13_0",
|
||||
"CLK_PMV_IMUX14_0",
|
||||
"CLK_PMV_IMUX15_0",
|
||||
"CLK_PMV_IMUX16_0",
|
||||
"CLK_PMV_IMUX17_0",
|
||||
"CLK_PMV_IMUX18_0",
|
||||
"CLK_PMV_IMUX19_0",
|
||||
"CLK_PMV_IMUX1_0",
|
||||
"CLK_PMV_IMUX20_0",
|
||||
"CLK_PMV_IMUX21_0",
|
||||
"CLK_PMV_IMUX22_0",
|
||||
"CLK_PMV_IMUX23_0",
|
||||
"CLK_PMV_IMUX24_0",
|
||||
"CLK_PMV_IMUX25_0",
|
||||
"CLK_PMV_IMUX26_0",
|
||||
"CLK_PMV_IMUX27_0",
|
||||
"CLK_PMV_IMUX28_0",
|
||||
"CLK_PMV_IMUX29_0",
|
||||
"CLK_PMV_IMUX2_0",
|
||||
"CLK_PMV_IMUX30_0",
|
||||
"CLK_PMV_IMUX31_0",
|
||||
"CLK_PMV_IMUX32_0",
|
||||
"CLK_PMV_IMUX33_0",
|
||||
"CLK_PMV_IMUX34_0",
|
||||
"CLK_PMV_IMUX35_0",
|
||||
"CLK_PMV_IMUX36_0",
|
||||
"CLK_PMV_IMUX37_0",
|
||||
"CLK_PMV_IMUX38_0",
|
||||
"CLK_PMV_IMUX39_0",
|
||||
"CLK_PMV_IMUX3_0",
|
||||
"CLK_PMV_IMUX40_0",
|
||||
"CLK_PMV_IMUX41_0",
|
||||
"CLK_PMV_IMUX42_0",
|
||||
"CLK_PMV_IMUX43_0",
|
||||
"CLK_PMV_IMUX44_0",
|
||||
"CLK_PMV_IMUX45_0",
|
||||
"CLK_PMV_IMUX46_0",
|
||||
"CLK_PMV_IMUX47_0",
|
||||
"CLK_PMV_IMUX4_0",
|
||||
"CLK_PMV_IMUX5_0",
|
||||
"CLK_PMV_IMUX6_0",
|
||||
"CLK_PMV_IMUX7_0",
|
||||
"CLK_PMV_IMUX8_0",
|
||||
"CLK_PMV_IMUX9_0",
|
||||
"CLK_PMV_LOGIC_OUTS0_0",
|
||||
"CLK_PMV_LOGIC_OUTS10_0",
|
||||
"CLK_PMV_LOGIC_OUTS11_0",
|
||||
"CLK_PMV_LOGIC_OUTS12_0",
|
||||
"CLK_PMV_LOGIC_OUTS13_0",
|
||||
"CLK_PMV_LOGIC_OUTS14_0",
|
||||
"CLK_PMV_LOGIC_OUTS15_0",
|
||||
"CLK_PMV_LOGIC_OUTS16_0",
|
||||
"CLK_PMV_LOGIC_OUTS17_0",
|
||||
"CLK_PMV_LOGIC_OUTS18_0",
|
||||
"CLK_PMV_LOGIC_OUTS19_0",
|
||||
"CLK_PMV_LOGIC_OUTS1_0",
|
||||
"CLK_PMV_LOGIC_OUTS20_0",
|
||||
"CLK_PMV_LOGIC_OUTS21_0",
|
||||
"CLK_PMV_LOGIC_OUTS22_0",
|
||||
"CLK_PMV_LOGIC_OUTS23_0",
|
||||
"CLK_PMV_LOGIC_OUTS2_0",
|
||||
"CLK_PMV_LOGIC_OUTS3_0",
|
||||
"CLK_PMV_LOGIC_OUTS4_0",
|
||||
"CLK_PMV_LOGIC_OUTS5_0",
|
||||
"CLK_PMV_LOGIC_OUTS6_0",
|
||||
"CLK_PMV_LOGIC_OUTS7_0",
|
||||
"CLK_PMV_LOGIC_OUTS8_0",
|
||||
"CLK_PMV_LOGIC_OUTS9_0"
|
||||
]
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,377 +1,377 @@
|
|||
{
|
||||
"wires": [
|
||||
"CLK_FEED_NE2A0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC28",
|
||||
"CLK_FEED_CK_GCLK19",
|
||||
"CLK_FEED_ER1BEG3",
|
||||
"CLK_FEED_CK_BUFG_CASC29",
|
||||
"CLK_FEED_R_CK_GCLK18",
|
||||
"CLK_FEED_R_CK_GCLK31",
|
||||
"CLK_PMV_CLK1_0",
|
||||
"CLK_FEED_CK_BUFG_CASC1",
|
||||
"CLK_FEED_R_CK_GCLK6",
|
||||
"CLK_FEED_LH7",
|
||||
"CLK_FEED_CK_BUFG_CASC3",
|
||||
"CLK_FEED_WW4B2",
|
||||
"CLK_FEED_LH12",
|
||||
"CLK_FEED_R_CK_BUFG_CASC14",
|
||||
"CLK_FEED_EE4A3",
|
||||
"CLK_FEED_CK_BUFG_CASC13",
|
||||
"CLK_PMV_IMUX28_0",
|
||||
"CLK_PMV_IMUX24_0",
|
||||
"CLK_FEED_ER1BEG0",
|
||||
"CLK_PMV_IMUX44_0",
|
||||
"CLK_FEED_SW4END3",
|
||||
"CLK_FEED_WL1END0",
|
||||
"CLK_FEED_SW2A0",
|
||||
"CLK_PMV_IMUX15_0",
|
||||
"CLK_PMV_IMUX43_0",
|
||||
"CLK_PMV_FAN0_0",
|
||||
"CLK_FEED_R_CK_GCLK13",
|
||||
"CLK_PMV_FAN1_0",
|
||||
"CLK_FEED_CK_BUFG_CASC26",
|
||||
"CLK_FEED_SE4BEG1",
|
||||
"CLK_FEED_CK_BUFG_CASC7",
|
||||
"CLK_PMV_IMUX11_0",
|
||||
"CLK_PMV_LOGIC_OUTS12_0",
|
||||
"CLK_FEED_CK_BUFG_CASC5",
|
||||
"CLK_FEED_CK_GCLK18",
|
||||
"CLK_PMV_BYP0_0",
|
||||
"CLK_FEED_WW4A3",
|
||||
"CLK_FEED_R_CK_BUFG_CASC10",
|
||||
"CLK_FEED_WW4C2",
|
||||
"CLK_FEED_NW4END3",
|
||||
"CLK_FEED_CK_GCLK27",
|
||||
"CLK_PMV_IMUX33_0",
|
||||
"CLK_FEED_R_CK_GCLK3",
|
||||
"CLK_FEED_CK_BUFG_CASC21",
|
||||
"CLK_FEED_WW2END0",
|
||||
"CLK_FEED_WW2A1",
|
||||
"CLK_PMV_LOGIC_OUTS18_0",
|
||||
"CLK_PMV_IMUX26_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC22",
|
||||
"CLK_PMV2_EN",
|
||||
"CLK_PMV_LOGIC_OUTS3_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC0",
|
||||
"CLK_FEED_CK_GCLK12",
|
||||
"CLK_FEED_EE4A2",
|
||||
"CLK_FEED_EE4B0",
|
||||
"CLK_FEED_WW2A2",
|
||||
"CLK_FEED_CK_BUFG_CASC10",
|
||||
"CLK_FEED_CK_BUFG_CASC12",
|
||||
"CLK_FEED_R_CK_BUFG_CASC25",
|
||||
"CLK_FEED_EE4A1",
|
||||
"CLK_PMV_LOGIC_OUTS23_0",
|
||||
"CLK_PMV_IMUX29_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC17",
|
||||
"CLK_PMV_LOGIC_OUTS5_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC30",
|
||||
"CLK_PMV_IMUX31_0",
|
||||
"CLK_FEED_CK_GCLK15",
|
||||
"CLK_FEED_R_CK_BUFG_CASC26",
|
||||
"CLK_FEED_WW2END1",
|
||||
"CLK_PMV2_ODIV2",
|
||||
"CLK_FEED_ER1BEG1",
|
||||
"CLK_FEED_EL1BEG0",
|
||||
"CLK_PMV_LOGIC_OUTS1_0",
|
||||
"CLK_PMV_LOGIC_OUTS21_0",
|
||||
"CLK_FEED_NE4C3",
|
||||
"CLK_FEED_WW4C0",
|
||||
"CLK_PMV_IMUX20_0",
|
||||
"CLK_PMV_BYP4_0",
|
||||
"CLK_FEED_CK_GCLK24",
|
||||
"CLK_FEED_NE2A2",
|
||||
"CLK_FEED_SE4BEG3",
|
||||
"CLK_PMV_LOGIC_OUTS16_0",
|
||||
"CLK_PMV_IMUX16_0",
|
||||
"CLK_FEED_CK_BUFG_CASC4",
|
||||
"CLK_PMV_IMUX9_0",
|
||||
"CLK_FEED_CK_GCLK23",
|
||||
"CLK_FEED_CK_BUFG_CASC20",
|
||||
"CLK_FEED_R_CK_GCLK12",
|
||||
"CLK_FEED_R_CK_BUFG_CASC27",
|
||||
"CLK_FEED_SE4C3",
|
||||
"CLK_FEED_CK_GCLK22",
|
||||
"CLK_FEED_NW4A2",
|
||||
"CLK_FEED_R_CK_GCLK9",
|
||||
"CLK_FEED_CK_GCLK17",
|
||||
"CLK_PMV_BYP7_0",
|
||||
"CLK_FEED_CK_BUFG_CASC6",
|
||||
"CLK_FEED_MONITOR_P",
|
||||
"CLK_FEED_NW2A2",
|
||||
"CLK_FEED_EE4BEG1",
|
||||
"CLK_FEED_R_CK_GCLK14",
|
||||
"CLK_FEED_EE4C0",
|
||||
"CLK_PMV_IMUX2_0",
|
||||
"CLK_FEED_EE4BEG3",
|
||||
"CLK_FEED_NE2A1",
|
||||
"CLK_FEED_WL1END3",
|
||||
"CLK_FEED_CK_GCLK28",
|
||||
"CLK_PMV_IMUX35_0",
|
||||
"CLK_PMV_LOGIC_OUTS7_0",
|
||||
"CLK_FEED_WW4B1",
|
||||
"CLK_FEED_SW4END0",
|
||||
"CLK_FEED_WW4END1",
|
||||
"CLK_FEED_R_CK_GCLK17",
|
||||
"CLK_FEED_R_CK_BUFG_CASC11",
|
||||
"CLK_FEED_WW4C1",
|
||||
"CLK_FEED_EL1BEG3",
|
||||
"CLK_PMV_IMUX17_0",
|
||||
"CLK_FEED_SE2A3",
|
||||
"CLK_FEED_R_CK_GCLK22",
|
||||
"CLK_FEED_NE4C0",
|
||||
"CLK_FEED_WW2A3",
|
||||
"CLK_FEED_NW4END1",
|
||||
"CLK_PMV_IMUX8_0",
|
||||
"CLK_FEED_SE2A2",
|
||||
"CLK_FEED_EE4B2",
|
||||
"CLK_FEED_R_CK_GCLK29",
|
||||
"CLK_FEED_WW2END3",
|
||||
"CLK_FEED_LH4",
|
||||
"CLK_FEED_WL1END2",
|
||||
"CLK_FEED_CK_GCLK2",
|
||||
"CLK_FEED_R_CK_GCLK25",
|
||||
"CLK_PMV_FAN3_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC13",
|
||||
"CLK_FEED_CK_BUFG_CASC27",
|
||||
"CLK_FEED_NW2A1",
|
||||
"CLK_FEED_SW4A3",
|
||||
"CLK_FEED_CK_BUFG_CASC31",
|
||||
"CLK_PMV_BYP3_0",
|
||||
"CLK_FEED_CK_GCLK1",
|
||||
"CLK_FEED_LH1",
|
||||
"CLK_FEED_CK_GCLK14",
|
||||
"CLK_FEED_R_CK_GCLK2",
|
||||
"CLK_FEED_R_CK_BUFG_CASC2",
|
||||
"CLK_PMV_CLK0_0",
|
||||
"CLK_FEED_WR1END0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC20",
|
||||
"CLK_FEED_NE4C1",
|
||||
"CLK_FEED_CK_GCLK16",
|
||||
"CLK_PMV_FAN2_0",
|
||||
"CLK_FEED_R_CK_GCLK5",
|
||||
"CLK_FEED_SE4C0",
|
||||
"CLK_FEED_EL1BEG2",
|
||||
"CLK_FEED_EL1BEG1",
|
||||
"CLK_FEED_EE4B1",
|
||||
"CLK_PMV2_A0",
|
||||
"CLK_FEED_CK_BUFG_CASC22",
|
||||
"CLK_PMV_IMUX40_0",
|
||||
"CLK_FEED_WR1END1",
|
||||
"CLK_FEED_NW4END0",
|
||||
"CLK_PMV_IMUX42_0",
|
||||
"CLK_FEED_EE2BEG1",
|
||||
"CLK_FEED_R_CK_GCLK23",
|
||||
"CLK_PMV2_A2",
|
||||
"CLK_FEED_R_CK_GCLK1",
|
||||
"CLK_FEED_LH2",
|
||||
"CLK_FEED_SW2A2",
|
||||
"CLK_FEED_ER1BEG2",
|
||||
"CLK_FEED_WL1END1",
|
||||
"CLK_PMV_IMUX47_0",
|
||||
"CLK_FEED_NW4A1",
|
||||
"CLK_PMV_BYP1_0",
|
||||
"CLK_PMV_IMUX5_0",
|
||||
"CLK_FEED_SW4A2",
|
||||
"CLK_FEED_CK_GCLK10",
|
||||
"CLK_FEED_CK_BUFG_CASC14",
|
||||
"CLK_FEED_CK_BUFG_CASC28",
|
||||
"CLK_PMV_FAN7_0",
|
||||
"CLK_FEED_CK_BUFG_CASC18",
|
||||
"CLK_FEED_R_CK_GCLK24",
|
||||
"CLK_FEED_EE2A1",
|
||||
"CLK_FEED_R_CK_BUFG_CASC15",
|
||||
"CLK_PMV_LOGIC_OUTS10_0",
|
||||
"CLK_FEED_SW2A1",
|
||||
"CLK_FEED_CK_BUFG_CASC8",
|
||||
"CLK_PMV_IMUX45_0",
|
||||
"CLK_FEED_CK_BUFG_CASC2",
|
||||
"CLK_FEED_R_CK_BUFG_CASC8",
|
||||
"CLK_PMV_BYP2_0",
|
||||
"CLK_PMV_IMUX14_0",
|
||||
"CLK_FEED_R_CK_GCLK0",
|
||||
"CLK_FEED_WW4B3",
|
||||
"CLK_PMV_IMUX7_0",
|
||||
"CLK_FEED_CK_GCLK3",
|
||||
"CLK_FEED_LH3",
|
||||
"CLK_PMV_IMUX6_0",
|
||||
"CLK_FEED_SE2A0",
|
||||
"CLK_FEED_NE4C2",
|
||||
"CLK_FEED_WW4C3",
|
||||
"CLK_PMV_IMUX38_0",
|
||||
"CLK_PMV_FAN6_0",
|
||||
"CLK_FEED_EE4B3",
|
||||
"CLK_PMV2_ODIV4",
|
||||
"CLK_FEED_NW4A0",
|
||||
"CLK_FEED_CK_BUFG_CASC25",
|
||||
"CLK_FEED_R_CK_GCLK20",
|
||||
"CLK_FEED_EE2A3",
|
||||
"CLK_FEED_R_CK_GCLK28",
|
||||
"CLK_FEED_LH11",
|
||||
"CLK_FEED_WW4B0",
|
||||
"CLK_PMV_IMUX30_0",
|
||||
"CLK_PMV_FAN4_0",
|
||||
"CLK_FEED_CK_GCLK4",
|
||||
"CLK_FEED_CK_GCLK13",
|
||||
"CLK_FEED_WW2END2",
|
||||
"CLK_FEED_SW4END2",
|
||||
"CLK_PMV_LOGIC_OUTS4_0",
|
||||
"CLK_PMV_LOGIC_OUTS6_0",
|
||||
"CLK_FEED_NW2A0",
|
||||
"CLK_FEED_R_CK_GCLK30",
|
||||
"CLK_FEED_R_CK_BUFG_CASC1",
|
||||
"CLK_FEED_CK_GCLK25",
|
||||
"CLK_PMV_IMUX1_0",
|
||||
"CLK_FEED_CK_BUFG_CASC19",
|
||||
"CLK_PMV_IMUX34_0",
|
||||
"CLK_FEED_WW4A2",
|
||||
"CLK_FEED_R_CK_BUFG_CASC6",
|
||||
"CLK_PMV_LOGIC_OUTS17_0",
|
||||
"CLK_PMV_LOGIC_OUTS9_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC29",
|
||||
"CLK_FEED_SW4END1",
|
||||
"CLK_FEED_LH10",
|
||||
"CLK_FEED_CK_BUFG_CASC0",
|
||||
"CLK_PMV_IMUX21_0",
|
||||
"CLK_FEED_NE4BEG3",
|
||||
"CLK_FEED_R_CK_GCLK26",
|
||||
"CLK_PMV_IMUX41_0",
|
||||
"CLK_PMV_IMUX46_0",
|
||||
"CLK_PMV_IMUX25_0",
|
||||
"CLK_PMV_IMUX39_0",
|
||||
"CLK_FEED_CK_GCLK7",
|
||||
"CLK_FEED_CK_BUFG_CASC23",
|
||||
"CLK_FEED_R_CK_BUFG_CASC16",
|
||||
"CLK_FEED_EE2BEG0",
|
||||
"CLK_FEED_CK_GCLK26",
|
||||
"CLK_FEED_CK_BUFG_CASC15",
|
||||
"CLK_FEED_SW4A1",
|
||||
"CLK_FEED_WW4A0",
|
||||
"CLK_PMV_IMUX22_0",
|
||||
"CLK_PMV_LOGIC_OUTS11_0",
|
||||
"CLK_PMV_BYP5_0",
|
||||
"CLK_PMV_LOGIC_OUTS15_0",
|
||||
"CLK_FEED_NE2A3",
|
||||
"CLK_FEED_CK_BUFG_CASC17",
|
||||
"CLK_FEED_CK_GCLK21",
|
||||
"CLK_PMV_LOGIC_OUTS0_0",
|
||||
"CLK_FEED_NE4BEG0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC23",
|
||||
"CLK_FEED_NE4BEG1",
|
||||
"CLK_PMV_LOGIC_OUTS19_0",
|
||||
"CLK_FEED_WW4END0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC12",
|
||||
"CLK_FEED_SE4BEG2",
|
||||
"CLK_FEED_EE2BEG3",
|
||||
"CLK_FEED_R_CK_GCLK7",
|
||||
"CLK_PMV_IMUX4_0",
|
||||
"CLK_FEED_CK_BUFG_CASC30",
|
||||
"CLK_PMV2_A1",
|
||||
"CLK_FEED_R_CK_GCLK8",
|
||||
"CLK_FEED_WW4A1",
|
||||
"CLK_FEED_EE4BEG0",
|
||||
"CLK_FEED_WR1END2",
|
||||
"CLK_FEED_CK_BUFG_CASC24",
|
||||
"CLK_FEED_R_CK_GCLK16",
|
||||
"CLK_FEED_R_CK_GCLK10",
|
||||
"CLK_FEED_CK_BUFG_CASC16",
|
||||
"CLK_FEED_R_CK_BUFG_CASC5",
|
||||
"CLK_FEED_CK_GCLK5",
|
||||
"CLK_FEED_R_CK_BUFG_CASC18",
|
||||
"CLK_FEED_NE4BEG2",
|
||||
"CLK_FEED_R_CK_GCLK11",
|
||||
"CLK_PMV_LOGIC_OUTS20_0",
|
||||
"CLK_FEED_R_CK_GCLK4",
|
||||
"CLK_PMV_IMUX12_0",
|
||||
"CLK_PMV_IMUX37_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC7",
|
||||
"CLK_PMV_IMUX18_0",
|
||||
"CLK_FEED_SE4C1",
|
||||
"CLK_FEED_CK_GCLK20",
|
||||
"CLK_PMV_LOGIC_OUTS8_0",
|
||||
"CLK_FEED_NW4END2",
|
||||
"CLK_FEED_EE4BEG2",
|
||||
"CLK_FEED_CK_GCLK30",
|
||||
"CLK_FEED_SE2A1",
|
||||
"CLK_FEED_LH6",
|
||||
"CLK_FEED_CK_GCLK29",
|
||||
"CLK_FEED_R_CK_GCLK27",
|
||||
"CLK_FEED_EE4C1",
|
||||
"CLK_FEED_SW4A0",
|
||||
"CLK_FEED_CK_GCLK9",
|
||||
"CLK_FEED_CK_BUFG_CASC11",
|
||||
"CLK_FEED_CK_GCLK8",
|
||||
"CLK_FEED_R_CK_BUFG_CASC9",
|
||||
"CLK_FEED_R_CK_BUFG_CASC3",
|
||||
"CLK_FEED_WW4END2",
|
||||
"CLK_FEED_CK_GCLK6",
|
||||
"CLK_FEED_EE2A2",
|
||||
"CLK_PMV_LOGIC_OUTS2_0",
|
||||
"CLK_PMV_LOGIC_OUTS14_0",
|
||||
"CLK_FEED_EE4C3",
|
||||
"CLK_FEED_NW2A3",
|
||||
"CLK_PMV_CTRL0_0",
|
||||
"CLK_PMV_LOGIC_OUTS22_0",
|
||||
"CLK_PMV_IMUX0_0",
|
||||
"CLK_FEED_EE2A0",
|
||||
"CLK_PMV_FAN5_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC24",
|
||||
"CLK_PMV_BYP6_0",
|
||||
"CLK_FEED_R_CK_GCLK19",
|
||||
"CLK_FEED_EE2BEG2",
|
||||
"CLK_FEED_R_CK_BUFG_CASC19",
|
||||
"CLK_FEED_WW4END3",
|
||||
"CLK_FEED_CK_GCLK31",
|
||||
"CLK_FEED_SW2A3",
|
||||
"CLK_PMV_IMUX23_0",
|
||||
"CLK_PMV_IMUX19_0",
|
||||
"CLK_PMV_IMUX36_0",
|
||||
"CLK_FEED_SE4C2",
|
||||
"CLK_FEED_EE4C2",
|
||||
"CLK_PMV_IMUX13_0",
|
||||
"CLK_FEED_SE4BEG0",
|
||||
"CLK_PMV_IMUX27_0",
|
||||
"CLK_FEED_LH9",
|
||||
"CLK_PMV2_O",
|
||||
"CLK_FEED_R_CK_GCLK15",
|
||||
"CLK_PMV_IMUX3_0",
|
||||
"CLK_PMV_CTRL1_0",
|
||||
"CLK_FEED_LH5",
|
||||
"CLK_PMV_LOGIC_OUTS13_0",
|
||||
"CLK_FEED_NW4A3",
|
||||
"CLK_PMV_IMUX10_0",
|
||||
"CLK_PMV_IMUX32_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC4",
|
||||
"CLK_FEED_R_CK_BUFG_CASC21",
|
||||
"CLK_FEED_CK_GCLK0",
|
||||
"CLK_FEED_MONITOR_N",
|
||||
"CLK_FEED_CK_GCLK11",
|
||||
"CLK_FEED_R_CK_BUFG_CASC31",
|
||||
"CLK_FEED_WW2A0",
|
||||
"CLK_FEED_EE4A0",
|
||||
"CLK_FEED_CK_BUFG_CASC9",
|
||||
"CLK_FEED_R_CK_GCLK21",
|
||||
"CLK_FEED_WR1END3",
|
||||
"CLK_FEED_LH8"
|
||||
],
|
||||
"pips": {},
|
||||
"tile_type": "CLK_PMV2",
|
||||
"sites": [
|
||||
{
|
||||
"type": "PMV2",
|
||||
"name": "X0Y0",
|
||||
"prefix": "PMV",
|
||||
"site_pins": {
|
||||
"EN": "CLK_PMV2_EN",
|
||||
"A0": "CLK_PMV2_A0",
|
||||
"ODIV2": "CLK_PMV2_ODIV2",
|
||||
"A2": "CLK_PMV2_A2",
|
||||
"ODIV4": "CLK_PMV2_ODIV4",
|
||||
"A1": "CLK_PMV2_A1",
|
||||
"O": "CLK_PMV2_O"
|
||||
"A2": "CLK_PMV2_A2",
|
||||
"EN": "CLK_PMV2_EN",
|
||||
"O": "CLK_PMV2_O",
|
||||
"ODIV2": "CLK_PMV2_ODIV2",
|
||||
"ODIV4": "CLK_PMV2_ODIV4"
|
||||
},
|
||||
"y_coord": 0,
|
||||
"type": "PMV2",
|
||||
"x_coord": 0,
|
||||
"prefix": "PMV"
|
||||
"y_coord": 0
|
||||
}
|
||||
],
|
||||
"tile_type": "CLK_PMV2",
|
||||
"wires": [
|
||||
"CLK_FEED_CK_BUFG_CASC0",
|
||||
"CLK_FEED_CK_BUFG_CASC1",
|
||||
"CLK_FEED_CK_BUFG_CASC10",
|
||||
"CLK_FEED_CK_BUFG_CASC11",
|
||||
"CLK_FEED_CK_BUFG_CASC12",
|
||||
"CLK_FEED_CK_BUFG_CASC13",
|
||||
"CLK_FEED_CK_BUFG_CASC14",
|
||||
"CLK_FEED_CK_BUFG_CASC15",
|
||||
"CLK_FEED_CK_BUFG_CASC16",
|
||||
"CLK_FEED_CK_BUFG_CASC17",
|
||||
"CLK_FEED_CK_BUFG_CASC18",
|
||||
"CLK_FEED_CK_BUFG_CASC19",
|
||||
"CLK_FEED_CK_BUFG_CASC2",
|
||||
"CLK_FEED_CK_BUFG_CASC20",
|
||||
"CLK_FEED_CK_BUFG_CASC21",
|
||||
"CLK_FEED_CK_BUFG_CASC22",
|
||||
"CLK_FEED_CK_BUFG_CASC23",
|
||||
"CLK_FEED_CK_BUFG_CASC24",
|
||||
"CLK_FEED_CK_BUFG_CASC25",
|
||||
"CLK_FEED_CK_BUFG_CASC26",
|
||||
"CLK_FEED_CK_BUFG_CASC27",
|
||||
"CLK_FEED_CK_BUFG_CASC28",
|
||||
"CLK_FEED_CK_BUFG_CASC29",
|
||||
"CLK_FEED_CK_BUFG_CASC3",
|
||||
"CLK_FEED_CK_BUFG_CASC30",
|
||||
"CLK_FEED_CK_BUFG_CASC31",
|
||||
"CLK_FEED_CK_BUFG_CASC4",
|
||||
"CLK_FEED_CK_BUFG_CASC5",
|
||||
"CLK_FEED_CK_BUFG_CASC6",
|
||||
"CLK_FEED_CK_BUFG_CASC7",
|
||||
"CLK_FEED_CK_BUFG_CASC8",
|
||||
"CLK_FEED_CK_BUFG_CASC9",
|
||||
"CLK_FEED_CK_GCLK0",
|
||||
"CLK_FEED_CK_GCLK1",
|
||||
"CLK_FEED_CK_GCLK10",
|
||||
"CLK_FEED_CK_GCLK11",
|
||||
"CLK_FEED_CK_GCLK12",
|
||||
"CLK_FEED_CK_GCLK13",
|
||||
"CLK_FEED_CK_GCLK14",
|
||||
"CLK_FEED_CK_GCLK15",
|
||||
"CLK_FEED_CK_GCLK16",
|
||||
"CLK_FEED_CK_GCLK17",
|
||||
"CLK_FEED_CK_GCLK18",
|
||||
"CLK_FEED_CK_GCLK19",
|
||||
"CLK_FEED_CK_GCLK2",
|
||||
"CLK_FEED_CK_GCLK20",
|
||||
"CLK_FEED_CK_GCLK21",
|
||||
"CLK_FEED_CK_GCLK22",
|
||||
"CLK_FEED_CK_GCLK23",
|
||||
"CLK_FEED_CK_GCLK24",
|
||||
"CLK_FEED_CK_GCLK25",
|
||||
"CLK_FEED_CK_GCLK26",
|
||||
"CLK_FEED_CK_GCLK27",
|
||||
"CLK_FEED_CK_GCLK28",
|
||||
"CLK_FEED_CK_GCLK29",
|
||||
"CLK_FEED_CK_GCLK3",
|
||||
"CLK_FEED_CK_GCLK30",
|
||||
"CLK_FEED_CK_GCLK31",
|
||||
"CLK_FEED_CK_GCLK4",
|
||||
"CLK_FEED_CK_GCLK5",
|
||||
"CLK_FEED_CK_GCLK6",
|
||||
"CLK_FEED_CK_GCLK7",
|
||||
"CLK_FEED_CK_GCLK8",
|
||||
"CLK_FEED_CK_GCLK9",
|
||||
"CLK_FEED_EE2A0",
|
||||
"CLK_FEED_EE2A1",
|
||||
"CLK_FEED_EE2A2",
|
||||
"CLK_FEED_EE2A3",
|
||||
"CLK_FEED_EE2BEG0",
|
||||
"CLK_FEED_EE2BEG1",
|
||||
"CLK_FEED_EE2BEG2",
|
||||
"CLK_FEED_EE2BEG3",
|
||||
"CLK_FEED_EE4A0",
|
||||
"CLK_FEED_EE4A1",
|
||||
"CLK_FEED_EE4A2",
|
||||
"CLK_FEED_EE4A3",
|
||||
"CLK_FEED_EE4B0",
|
||||
"CLK_FEED_EE4B1",
|
||||
"CLK_FEED_EE4B2",
|
||||
"CLK_FEED_EE4B3",
|
||||
"CLK_FEED_EE4BEG0",
|
||||
"CLK_FEED_EE4BEG1",
|
||||
"CLK_FEED_EE4BEG2",
|
||||
"CLK_FEED_EE4BEG3",
|
||||
"CLK_FEED_EE4C0",
|
||||
"CLK_FEED_EE4C1",
|
||||
"CLK_FEED_EE4C2",
|
||||
"CLK_FEED_EE4C3",
|
||||
"CLK_FEED_EL1BEG0",
|
||||
"CLK_FEED_EL1BEG1",
|
||||
"CLK_FEED_EL1BEG2",
|
||||
"CLK_FEED_EL1BEG3",
|
||||
"CLK_FEED_ER1BEG0",
|
||||
"CLK_FEED_ER1BEG1",
|
||||
"CLK_FEED_ER1BEG2",
|
||||
"CLK_FEED_ER1BEG3",
|
||||
"CLK_FEED_LH1",
|
||||
"CLK_FEED_LH10",
|
||||
"CLK_FEED_LH11",
|
||||
"CLK_FEED_LH12",
|
||||
"CLK_FEED_LH2",
|
||||
"CLK_FEED_LH3",
|
||||
"CLK_FEED_LH4",
|
||||
"CLK_FEED_LH5",
|
||||
"CLK_FEED_LH6",
|
||||
"CLK_FEED_LH7",
|
||||
"CLK_FEED_LH8",
|
||||
"CLK_FEED_LH9",
|
||||
"CLK_FEED_MONITOR_N",
|
||||
"CLK_FEED_MONITOR_P",
|
||||
"CLK_FEED_NE2A0",
|
||||
"CLK_FEED_NE2A1",
|
||||
"CLK_FEED_NE2A2",
|
||||
"CLK_FEED_NE2A3",
|
||||
"CLK_FEED_NE4BEG0",
|
||||
"CLK_FEED_NE4BEG1",
|
||||
"CLK_FEED_NE4BEG2",
|
||||
"CLK_FEED_NE4BEG3",
|
||||
"CLK_FEED_NE4C0",
|
||||
"CLK_FEED_NE4C1",
|
||||
"CLK_FEED_NE4C2",
|
||||
"CLK_FEED_NE4C3",
|
||||
"CLK_FEED_NW2A0",
|
||||
"CLK_FEED_NW2A1",
|
||||
"CLK_FEED_NW2A2",
|
||||
"CLK_FEED_NW2A3",
|
||||
"CLK_FEED_NW4A0",
|
||||
"CLK_FEED_NW4A1",
|
||||
"CLK_FEED_NW4A2",
|
||||
"CLK_FEED_NW4A3",
|
||||
"CLK_FEED_NW4END0",
|
||||
"CLK_FEED_NW4END1",
|
||||
"CLK_FEED_NW4END2",
|
||||
"CLK_FEED_NW4END3",
|
||||
"CLK_FEED_R_CK_BUFG_CASC0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC1",
|
||||
"CLK_FEED_R_CK_BUFG_CASC10",
|
||||
"CLK_FEED_R_CK_BUFG_CASC11",
|
||||
"CLK_FEED_R_CK_BUFG_CASC12",
|
||||
"CLK_FEED_R_CK_BUFG_CASC13",
|
||||
"CLK_FEED_R_CK_BUFG_CASC14",
|
||||
"CLK_FEED_R_CK_BUFG_CASC15",
|
||||
"CLK_FEED_R_CK_BUFG_CASC16",
|
||||
"CLK_FEED_R_CK_BUFG_CASC17",
|
||||
"CLK_FEED_R_CK_BUFG_CASC18",
|
||||
"CLK_FEED_R_CK_BUFG_CASC19",
|
||||
"CLK_FEED_R_CK_BUFG_CASC2",
|
||||
"CLK_FEED_R_CK_BUFG_CASC20",
|
||||
"CLK_FEED_R_CK_BUFG_CASC21",
|
||||
"CLK_FEED_R_CK_BUFG_CASC22",
|
||||
"CLK_FEED_R_CK_BUFG_CASC23",
|
||||
"CLK_FEED_R_CK_BUFG_CASC24",
|
||||
"CLK_FEED_R_CK_BUFG_CASC25",
|
||||
"CLK_FEED_R_CK_BUFG_CASC26",
|
||||
"CLK_FEED_R_CK_BUFG_CASC27",
|
||||
"CLK_FEED_R_CK_BUFG_CASC28",
|
||||
"CLK_FEED_R_CK_BUFG_CASC29",
|
||||
"CLK_FEED_R_CK_BUFG_CASC3",
|
||||
"CLK_FEED_R_CK_BUFG_CASC30",
|
||||
"CLK_FEED_R_CK_BUFG_CASC31",
|
||||
"CLK_FEED_R_CK_BUFG_CASC4",
|
||||
"CLK_FEED_R_CK_BUFG_CASC5",
|
||||
"CLK_FEED_R_CK_BUFG_CASC6",
|
||||
"CLK_FEED_R_CK_BUFG_CASC7",
|
||||
"CLK_FEED_R_CK_BUFG_CASC8",
|
||||
"CLK_FEED_R_CK_BUFG_CASC9",
|
||||
"CLK_FEED_R_CK_GCLK0",
|
||||
"CLK_FEED_R_CK_GCLK1",
|
||||
"CLK_FEED_R_CK_GCLK10",
|
||||
"CLK_FEED_R_CK_GCLK11",
|
||||
"CLK_FEED_R_CK_GCLK12",
|
||||
"CLK_FEED_R_CK_GCLK13",
|
||||
"CLK_FEED_R_CK_GCLK14",
|
||||
"CLK_FEED_R_CK_GCLK15",
|
||||
"CLK_FEED_R_CK_GCLK16",
|
||||
"CLK_FEED_R_CK_GCLK17",
|
||||
"CLK_FEED_R_CK_GCLK18",
|
||||
"CLK_FEED_R_CK_GCLK19",
|
||||
"CLK_FEED_R_CK_GCLK2",
|
||||
"CLK_FEED_R_CK_GCLK20",
|
||||
"CLK_FEED_R_CK_GCLK21",
|
||||
"CLK_FEED_R_CK_GCLK22",
|
||||
"CLK_FEED_R_CK_GCLK23",
|
||||
"CLK_FEED_R_CK_GCLK24",
|
||||
"CLK_FEED_R_CK_GCLK25",
|
||||
"CLK_FEED_R_CK_GCLK26",
|
||||
"CLK_FEED_R_CK_GCLK27",
|
||||
"CLK_FEED_R_CK_GCLK28",
|
||||
"CLK_FEED_R_CK_GCLK29",
|
||||
"CLK_FEED_R_CK_GCLK3",
|
||||
"CLK_FEED_R_CK_GCLK30",
|
||||
"CLK_FEED_R_CK_GCLK31",
|
||||
"CLK_FEED_R_CK_GCLK4",
|
||||
"CLK_FEED_R_CK_GCLK5",
|
||||
"CLK_FEED_R_CK_GCLK6",
|
||||
"CLK_FEED_R_CK_GCLK7",
|
||||
"CLK_FEED_R_CK_GCLK8",
|
||||
"CLK_FEED_R_CK_GCLK9",
|
||||
"CLK_FEED_SE2A0",
|
||||
"CLK_FEED_SE2A1",
|
||||
"CLK_FEED_SE2A2",
|
||||
"CLK_FEED_SE2A3",
|
||||
"CLK_FEED_SE4BEG0",
|
||||
"CLK_FEED_SE4BEG1",
|
||||
"CLK_FEED_SE4BEG2",
|
||||
"CLK_FEED_SE4BEG3",
|
||||
"CLK_FEED_SE4C0",
|
||||
"CLK_FEED_SE4C1",
|
||||
"CLK_FEED_SE4C2",
|
||||
"CLK_FEED_SE4C3",
|
||||
"CLK_FEED_SW2A0",
|
||||
"CLK_FEED_SW2A1",
|
||||
"CLK_FEED_SW2A2",
|
||||
"CLK_FEED_SW2A3",
|
||||
"CLK_FEED_SW4A0",
|
||||
"CLK_FEED_SW4A1",
|
||||
"CLK_FEED_SW4A2",
|
||||
"CLK_FEED_SW4A3",
|
||||
"CLK_FEED_SW4END0",
|
||||
"CLK_FEED_SW4END1",
|
||||
"CLK_FEED_SW4END2",
|
||||
"CLK_FEED_SW4END3",
|
||||
"CLK_FEED_WL1END0",
|
||||
"CLK_FEED_WL1END1",
|
||||
"CLK_FEED_WL1END2",
|
||||
"CLK_FEED_WL1END3",
|
||||
"CLK_FEED_WR1END0",
|
||||
"CLK_FEED_WR1END1",
|
||||
"CLK_FEED_WR1END2",
|
||||
"CLK_FEED_WR1END3",
|
||||
"CLK_FEED_WW2A0",
|
||||
"CLK_FEED_WW2A1",
|
||||
"CLK_FEED_WW2A2",
|
||||
"CLK_FEED_WW2A3",
|
||||
"CLK_FEED_WW2END0",
|
||||
"CLK_FEED_WW2END1",
|
||||
"CLK_FEED_WW2END2",
|
||||
"CLK_FEED_WW2END3",
|
||||
"CLK_FEED_WW4A0",
|
||||
"CLK_FEED_WW4A1",
|
||||
"CLK_FEED_WW4A2",
|
||||
"CLK_FEED_WW4A3",
|
||||
"CLK_FEED_WW4B0",
|
||||
"CLK_FEED_WW4B1",
|
||||
"CLK_FEED_WW4B2",
|
||||
"CLK_FEED_WW4B3",
|
||||
"CLK_FEED_WW4C0",
|
||||
"CLK_FEED_WW4C1",
|
||||
"CLK_FEED_WW4C2",
|
||||
"CLK_FEED_WW4C3",
|
||||
"CLK_FEED_WW4END0",
|
||||
"CLK_FEED_WW4END1",
|
||||
"CLK_FEED_WW4END2",
|
||||
"CLK_FEED_WW4END3",
|
||||
"CLK_PMV2_A0",
|
||||
"CLK_PMV2_A1",
|
||||
"CLK_PMV2_A2",
|
||||
"CLK_PMV2_EN",
|
||||
"CLK_PMV2_O",
|
||||
"CLK_PMV2_ODIV2",
|
||||
"CLK_PMV2_ODIV4",
|
||||
"CLK_PMV_BYP0_0",
|
||||
"CLK_PMV_BYP1_0",
|
||||
"CLK_PMV_BYP2_0",
|
||||
"CLK_PMV_BYP3_0",
|
||||
"CLK_PMV_BYP4_0",
|
||||
"CLK_PMV_BYP5_0",
|
||||
"CLK_PMV_BYP6_0",
|
||||
"CLK_PMV_BYP7_0",
|
||||
"CLK_PMV_CLK0_0",
|
||||
"CLK_PMV_CLK1_0",
|
||||
"CLK_PMV_CTRL0_0",
|
||||
"CLK_PMV_CTRL1_0",
|
||||
"CLK_PMV_FAN0_0",
|
||||
"CLK_PMV_FAN1_0",
|
||||
"CLK_PMV_FAN2_0",
|
||||
"CLK_PMV_FAN3_0",
|
||||
"CLK_PMV_FAN4_0",
|
||||
"CLK_PMV_FAN5_0",
|
||||
"CLK_PMV_FAN6_0",
|
||||
"CLK_PMV_FAN7_0",
|
||||
"CLK_PMV_IMUX0_0",
|
||||
"CLK_PMV_IMUX10_0",
|
||||
"CLK_PMV_IMUX11_0",
|
||||
"CLK_PMV_IMUX12_0",
|
||||
"CLK_PMV_IMUX13_0",
|
||||
"CLK_PMV_IMUX14_0",
|
||||
"CLK_PMV_IMUX15_0",
|
||||
"CLK_PMV_IMUX16_0",
|
||||
"CLK_PMV_IMUX17_0",
|
||||
"CLK_PMV_IMUX18_0",
|
||||
"CLK_PMV_IMUX19_0",
|
||||
"CLK_PMV_IMUX1_0",
|
||||
"CLK_PMV_IMUX20_0",
|
||||
"CLK_PMV_IMUX21_0",
|
||||
"CLK_PMV_IMUX22_0",
|
||||
"CLK_PMV_IMUX23_0",
|
||||
"CLK_PMV_IMUX24_0",
|
||||
"CLK_PMV_IMUX25_0",
|
||||
"CLK_PMV_IMUX26_0",
|
||||
"CLK_PMV_IMUX27_0",
|
||||
"CLK_PMV_IMUX28_0",
|
||||
"CLK_PMV_IMUX29_0",
|
||||
"CLK_PMV_IMUX2_0",
|
||||
"CLK_PMV_IMUX30_0",
|
||||
"CLK_PMV_IMUX31_0",
|
||||
"CLK_PMV_IMUX32_0",
|
||||
"CLK_PMV_IMUX33_0",
|
||||
"CLK_PMV_IMUX34_0",
|
||||
"CLK_PMV_IMUX35_0",
|
||||
"CLK_PMV_IMUX36_0",
|
||||
"CLK_PMV_IMUX37_0",
|
||||
"CLK_PMV_IMUX38_0",
|
||||
"CLK_PMV_IMUX39_0",
|
||||
"CLK_PMV_IMUX3_0",
|
||||
"CLK_PMV_IMUX40_0",
|
||||
"CLK_PMV_IMUX41_0",
|
||||
"CLK_PMV_IMUX42_0",
|
||||
"CLK_PMV_IMUX43_0",
|
||||
"CLK_PMV_IMUX44_0",
|
||||
"CLK_PMV_IMUX45_0",
|
||||
"CLK_PMV_IMUX46_0",
|
||||
"CLK_PMV_IMUX47_0",
|
||||
"CLK_PMV_IMUX4_0",
|
||||
"CLK_PMV_IMUX5_0",
|
||||
"CLK_PMV_IMUX6_0",
|
||||
"CLK_PMV_IMUX7_0",
|
||||
"CLK_PMV_IMUX8_0",
|
||||
"CLK_PMV_IMUX9_0",
|
||||
"CLK_PMV_LOGIC_OUTS0_0",
|
||||
"CLK_PMV_LOGIC_OUTS10_0",
|
||||
"CLK_PMV_LOGIC_OUTS11_0",
|
||||
"CLK_PMV_LOGIC_OUTS12_0",
|
||||
"CLK_PMV_LOGIC_OUTS13_0",
|
||||
"CLK_PMV_LOGIC_OUTS14_0",
|
||||
"CLK_PMV_LOGIC_OUTS15_0",
|
||||
"CLK_PMV_LOGIC_OUTS16_0",
|
||||
"CLK_PMV_LOGIC_OUTS17_0",
|
||||
"CLK_PMV_LOGIC_OUTS18_0",
|
||||
"CLK_PMV_LOGIC_OUTS19_0",
|
||||
"CLK_PMV_LOGIC_OUTS1_0",
|
||||
"CLK_PMV_LOGIC_OUTS20_0",
|
||||
"CLK_PMV_LOGIC_OUTS21_0",
|
||||
"CLK_PMV_LOGIC_OUTS22_0",
|
||||
"CLK_PMV_LOGIC_OUTS23_0",
|
||||
"CLK_PMV_LOGIC_OUTS2_0",
|
||||
"CLK_PMV_LOGIC_OUTS3_0",
|
||||
"CLK_PMV_LOGIC_OUTS4_0",
|
||||
"CLK_PMV_LOGIC_OUTS5_0",
|
||||
"CLK_PMV_LOGIC_OUTS6_0",
|
||||
"CLK_PMV_LOGIC_OUTS7_0",
|
||||
"CLK_PMV_LOGIC_OUTS8_0",
|
||||
"CLK_PMV_LOGIC_OUTS9_0"
|
||||
]
|
||||
}
|
||||
}
|
||||
|
|
@ -1,360 +1,360 @@
|
|||
{
|
||||
"pips": {},
|
||||
"sites": [],
|
||||
"tile_type": "CLK_PMV2_SVT",
|
||||
"wires": [
|
||||
"CLK_FEED_NE2A0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC28",
|
||||
"CLK_FEED_CK_GCLK19",
|
||||
"CLK_FEED_ER1BEG3",
|
||||
"CLK_FEED_CK_BUFG_CASC29",
|
||||
"CLK_FEED_R_CK_GCLK18",
|
||||
"CLK_FEED_R_CK_GCLK31",
|
||||
"CLK_PMV_CLK1_0",
|
||||
"CLK_FEED_CK_BUFG_CASC0",
|
||||
"CLK_FEED_CK_BUFG_CASC1",
|
||||
"CLK_FEED_R_CK_GCLK6",
|
||||
"CLK_FEED_LH7",
|
||||
"CLK_FEED_CK_BUFG_CASC3",
|
||||
"CLK_FEED_WW4B2",
|
||||
"CLK_FEED_LH12",
|
||||
"CLK_FEED_R_CK_BUFG_CASC14",
|
||||
"CLK_FEED_EE4A3",
|
||||
"CLK_FEED_CK_BUFG_CASC10",
|
||||
"CLK_FEED_CK_BUFG_CASC11",
|
||||
"CLK_FEED_CK_BUFG_CASC12",
|
||||
"CLK_FEED_CK_BUFG_CASC13",
|
||||
"CLK_PMV_IMUX28_0",
|
||||
"CLK_PMV_IMUX24_0",
|
||||
"CLK_FEED_CK_BUFG_CASC14",
|
||||
"CLK_FEED_CK_BUFG_CASC15",
|
||||
"CLK_FEED_CK_BUFG_CASC16",
|
||||
"CLK_FEED_CK_BUFG_CASC17",
|
||||
"CLK_FEED_CK_BUFG_CASC18",
|
||||
"CLK_FEED_CK_BUFG_CASC19",
|
||||
"CLK_FEED_CK_BUFG_CASC2",
|
||||
"CLK_FEED_CK_BUFG_CASC20",
|
||||
"CLK_FEED_CK_BUFG_CASC21",
|
||||
"CLK_FEED_CK_BUFG_CASC22",
|
||||
"CLK_FEED_CK_BUFG_CASC23",
|
||||
"CLK_FEED_CK_BUFG_CASC24",
|
||||
"CLK_FEED_CK_BUFG_CASC25",
|
||||
"CLK_FEED_CK_BUFG_CASC26",
|
||||
"CLK_FEED_CK_BUFG_CASC27",
|
||||
"CLK_FEED_CK_BUFG_CASC28",
|
||||
"CLK_FEED_CK_BUFG_CASC29",
|
||||
"CLK_FEED_CK_BUFG_CASC3",
|
||||
"CLK_FEED_CK_BUFG_CASC30",
|
||||
"CLK_FEED_CK_BUFG_CASC31",
|
||||
"CLK_FEED_CK_BUFG_CASC4",
|
||||
"CLK_FEED_CK_BUFG_CASC5",
|
||||
"CLK_FEED_CK_BUFG_CASC6",
|
||||
"CLK_FEED_CK_BUFG_CASC7",
|
||||
"CLK_FEED_CK_BUFG_CASC8",
|
||||
"CLK_FEED_CK_BUFG_CASC9",
|
||||
"CLK_FEED_CK_GCLK0",
|
||||
"CLK_FEED_CK_GCLK1",
|
||||
"CLK_FEED_CK_GCLK10",
|
||||
"CLK_FEED_CK_GCLK11",
|
||||
"CLK_FEED_CK_GCLK12",
|
||||
"CLK_FEED_CK_GCLK13",
|
||||
"CLK_FEED_CK_GCLK14",
|
||||
"CLK_FEED_CK_GCLK15",
|
||||
"CLK_FEED_CK_GCLK16",
|
||||
"CLK_FEED_CK_GCLK17",
|
||||
"CLK_FEED_CK_GCLK18",
|
||||
"CLK_FEED_CK_GCLK19",
|
||||
"CLK_FEED_CK_GCLK2",
|
||||
"CLK_FEED_CK_GCLK20",
|
||||
"CLK_FEED_CK_GCLK21",
|
||||
"CLK_FEED_CK_GCLK22",
|
||||
"CLK_FEED_CK_GCLK23",
|
||||
"CLK_FEED_CK_GCLK24",
|
||||
"CLK_FEED_CK_GCLK25",
|
||||
"CLK_FEED_CK_GCLK26",
|
||||
"CLK_FEED_CK_GCLK27",
|
||||
"CLK_FEED_CK_GCLK28",
|
||||
"CLK_FEED_CK_GCLK29",
|
||||
"CLK_FEED_CK_GCLK3",
|
||||
"CLK_FEED_CK_GCLK30",
|
||||
"CLK_FEED_CK_GCLK31",
|
||||
"CLK_FEED_CK_GCLK4",
|
||||
"CLK_FEED_CK_GCLK5",
|
||||
"CLK_FEED_CK_GCLK6",
|
||||
"CLK_FEED_CK_GCLK7",
|
||||
"CLK_FEED_CK_GCLK8",
|
||||
"CLK_FEED_CK_GCLK9",
|
||||
"CLK_FEED_EE2A0",
|
||||
"CLK_FEED_EE2A1",
|
||||
"CLK_FEED_EE2A2",
|
||||
"CLK_FEED_EE2A3",
|
||||
"CLK_FEED_EE2BEG0",
|
||||
"CLK_FEED_EE2BEG1",
|
||||
"CLK_FEED_EE2BEG2",
|
||||
"CLK_FEED_EE2BEG3",
|
||||
"CLK_FEED_EE4A0",
|
||||
"CLK_FEED_EE4A1",
|
||||
"CLK_FEED_EE4A2",
|
||||
"CLK_FEED_EE4A3",
|
||||
"CLK_FEED_EE4B0",
|
||||
"CLK_FEED_EE4B1",
|
||||
"CLK_FEED_EE4B2",
|
||||
"CLK_FEED_EE4B3",
|
||||
"CLK_FEED_EE4BEG0",
|
||||
"CLK_FEED_EE4BEG1",
|
||||
"CLK_FEED_EE4BEG2",
|
||||
"CLK_FEED_EE4BEG3",
|
||||
"CLK_FEED_EE4C0",
|
||||
"CLK_FEED_EE4C1",
|
||||
"CLK_FEED_EE4C2",
|
||||
"CLK_FEED_EE4C3",
|
||||
"CLK_FEED_EL1BEG0",
|
||||
"CLK_FEED_EL1BEG1",
|
||||
"CLK_FEED_EL1BEG2",
|
||||
"CLK_FEED_EL1BEG3",
|
||||
"CLK_FEED_ER1BEG0",
|
||||
"CLK_PMV_IMUX44_0",
|
||||
"CLK_FEED_ER1BEG1",
|
||||
"CLK_FEED_ER1BEG2",
|
||||
"CLK_FEED_ER1BEG3",
|
||||
"CLK_FEED_LH1",
|
||||
"CLK_FEED_LH10",
|
||||
"CLK_FEED_LH11",
|
||||
"CLK_FEED_LH12",
|
||||
"CLK_FEED_LH2",
|
||||
"CLK_FEED_LH3",
|
||||
"CLK_FEED_LH4",
|
||||
"CLK_FEED_LH5",
|
||||
"CLK_FEED_LH6",
|
||||
"CLK_FEED_LH7",
|
||||
"CLK_FEED_LH8",
|
||||
"CLK_FEED_LH9",
|
||||
"CLK_FEED_MONITOR_N",
|
||||
"CLK_FEED_MONITOR_P",
|
||||
"CLK_FEED_NE2A0",
|
||||
"CLK_FEED_NE2A1",
|
||||
"CLK_FEED_NE2A2",
|
||||
"CLK_FEED_NE2A3",
|
||||
"CLK_FEED_NE4BEG0",
|
||||
"CLK_FEED_NE4BEG1",
|
||||
"CLK_FEED_NE4BEG2",
|
||||
"CLK_FEED_NE4BEG3",
|
||||
"CLK_FEED_NE4C0",
|
||||
"CLK_FEED_NE4C1",
|
||||
"CLK_FEED_NE4C2",
|
||||
"CLK_FEED_NE4C3",
|
||||
"CLK_FEED_NW2A0",
|
||||
"CLK_FEED_NW2A1",
|
||||
"CLK_FEED_NW2A2",
|
||||
"CLK_FEED_NW2A3",
|
||||
"CLK_FEED_NW4A0",
|
||||
"CLK_FEED_NW4A1",
|
||||
"CLK_FEED_NW4A2",
|
||||
"CLK_FEED_NW4A3",
|
||||
"CLK_FEED_NW4END0",
|
||||
"CLK_FEED_NW4END1",
|
||||
"CLK_FEED_NW4END2",
|
||||
"CLK_FEED_NW4END3",
|
||||
"CLK_FEED_R_CK_BUFG_CASC0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC1",
|
||||
"CLK_FEED_R_CK_BUFG_CASC10",
|
||||
"CLK_FEED_R_CK_BUFG_CASC11",
|
||||
"CLK_FEED_R_CK_BUFG_CASC12",
|
||||
"CLK_FEED_R_CK_BUFG_CASC13",
|
||||
"CLK_FEED_R_CK_BUFG_CASC14",
|
||||
"CLK_FEED_R_CK_BUFG_CASC15",
|
||||
"CLK_FEED_R_CK_BUFG_CASC16",
|
||||
"CLK_FEED_R_CK_BUFG_CASC17",
|
||||
"CLK_FEED_R_CK_BUFG_CASC18",
|
||||
"CLK_FEED_R_CK_BUFG_CASC19",
|
||||
"CLK_FEED_R_CK_BUFG_CASC2",
|
||||
"CLK_FEED_R_CK_BUFG_CASC20",
|
||||
"CLK_FEED_R_CK_BUFG_CASC21",
|
||||
"CLK_FEED_R_CK_BUFG_CASC22",
|
||||
"CLK_FEED_R_CK_BUFG_CASC23",
|
||||
"CLK_FEED_R_CK_BUFG_CASC24",
|
||||
"CLK_FEED_R_CK_BUFG_CASC25",
|
||||
"CLK_FEED_R_CK_BUFG_CASC26",
|
||||
"CLK_FEED_R_CK_BUFG_CASC27",
|
||||
"CLK_FEED_R_CK_BUFG_CASC28",
|
||||
"CLK_FEED_R_CK_BUFG_CASC29",
|
||||
"CLK_FEED_R_CK_BUFG_CASC3",
|
||||
"CLK_FEED_R_CK_BUFG_CASC30",
|
||||
"CLK_FEED_R_CK_BUFG_CASC31",
|
||||
"CLK_FEED_R_CK_BUFG_CASC4",
|
||||
"CLK_FEED_R_CK_BUFG_CASC5",
|
||||
"CLK_FEED_R_CK_BUFG_CASC6",
|
||||
"CLK_FEED_R_CK_BUFG_CASC7",
|
||||
"CLK_FEED_R_CK_BUFG_CASC8",
|
||||
"CLK_FEED_R_CK_BUFG_CASC9",
|
||||
"CLK_FEED_R_CK_GCLK0",
|
||||
"CLK_FEED_R_CK_GCLK1",
|
||||
"CLK_FEED_R_CK_GCLK10",
|
||||
"CLK_FEED_R_CK_GCLK11",
|
||||
"CLK_FEED_R_CK_GCLK12",
|
||||
"CLK_FEED_R_CK_GCLK13",
|
||||
"CLK_FEED_R_CK_GCLK14",
|
||||
"CLK_FEED_R_CK_GCLK15",
|
||||
"CLK_FEED_R_CK_GCLK16",
|
||||
"CLK_FEED_R_CK_GCLK17",
|
||||
"CLK_FEED_R_CK_GCLK18",
|
||||
"CLK_FEED_R_CK_GCLK19",
|
||||
"CLK_FEED_R_CK_GCLK2",
|
||||
"CLK_FEED_R_CK_GCLK20",
|
||||
"CLK_FEED_R_CK_GCLK21",
|
||||
"CLK_FEED_R_CK_GCLK22",
|
||||
"CLK_FEED_R_CK_GCLK23",
|
||||
"CLK_FEED_R_CK_GCLK24",
|
||||
"CLK_FEED_R_CK_GCLK25",
|
||||
"CLK_FEED_R_CK_GCLK26",
|
||||
"CLK_FEED_R_CK_GCLK27",
|
||||
"CLK_FEED_R_CK_GCLK28",
|
||||
"CLK_FEED_R_CK_GCLK29",
|
||||
"CLK_FEED_R_CK_GCLK3",
|
||||
"CLK_FEED_R_CK_GCLK30",
|
||||
"CLK_FEED_R_CK_GCLK31",
|
||||
"CLK_FEED_R_CK_GCLK4",
|
||||
"CLK_FEED_R_CK_GCLK5",
|
||||
"CLK_FEED_R_CK_GCLK6",
|
||||
"CLK_FEED_R_CK_GCLK7",
|
||||
"CLK_FEED_R_CK_GCLK8",
|
||||
"CLK_FEED_R_CK_GCLK9",
|
||||
"CLK_FEED_SE2A0",
|
||||
"CLK_FEED_SE2A1",
|
||||
"CLK_FEED_SE2A2",
|
||||
"CLK_FEED_SE2A3",
|
||||
"CLK_FEED_SE4BEG0",
|
||||
"CLK_FEED_SE4BEG1",
|
||||
"CLK_FEED_SE4BEG2",
|
||||
"CLK_FEED_SE4BEG3",
|
||||
"CLK_FEED_SE4C0",
|
||||
"CLK_FEED_SE4C1",
|
||||
"CLK_FEED_SE4C2",
|
||||
"CLK_FEED_SE4C3",
|
||||
"CLK_FEED_SW2A0",
|
||||
"CLK_FEED_SW2A1",
|
||||
"CLK_FEED_SW2A2",
|
||||
"CLK_FEED_SW2A3",
|
||||
"CLK_FEED_SW4A0",
|
||||
"CLK_FEED_SW4A1",
|
||||
"CLK_FEED_SW4A2",
|
||||
"CLK_FEED_SW4A3",
|
||||
"CLK_FEED_SW4END0",
|
||||
"CLK_FEED_SW4END1",
|
||||
"CLK_FEED_SW4END2",
|
||||
"CLK_FEED_SW4END3",
|
||||
"CLK_FEED_WL1END0",
|
||||
"CLK_FEED_SW2A0",
|
||||
"CLK_PMV_IMUX15_0",
|
||||
"CLK_PMV_IMUX43_0",
|
||||
"CLK_PMV_FAN0_0",
|
||||
"CLK_FEED_R_CK_GCLK13",
|
||||
"CLK_PMV_FAN1_0",
|
||||
"CLK_FEED_CK_BUFG_CASC26",
|
||||
"CLK_FEED_SE4BEG1",
|
||||
"CLK_FEED_CK_BUFG_CASC7",
|
||||
"CLK_PMV_IMUX11_0",
|
||||
"CLK_PMV_LOGIC_OUTS12_0",
|
||||
"CLK_FEED_CK_BUFG_CASC5",
|
||||
"CLK_FEED_CK_GCLK18",
|
||||
"CLK_PMV_BYP0_0",
|
||||
"CLK_FEED_WW4A3",
|
||||
"CLK_FEED_R_CK_BUFG_CASC10",
|
||||
"CLK_FEED_WW4C2",
|
||||
"CLK_FEED_NW4END3",
|
||||
"CLK_FEED_CK_GCLK27",
|
||||
"CLK_PMV_IMUX33_0",
|
||||
"CLK_FEED_R_CK_GCLK3",
|
||||
"CLK_FEED_CK_BUFG_CASC21",
|
||||
"CLK_FEED_WW2END0",
|
||||
"CLK_FEED_WW2A1",
|
||||
"CLK_PMV_LOGIC_OUTS18_0",
|
||||
"CLK_PMV_IMUX26_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC22",
|
||||
"CLK_PMV2_EN",
|
||||
"CLK_PMV_LOGIC_OUTS3_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC0",
|
||||
"CLK_FEED_CK_GCLK12",
|
||||
"CLK_FEED_EE4A2",
|
||||
"CLK_FEED_EE4B0",
|
||||
"CLK_FEED_WW2A2",
|
||||
"CLK_FEED_CK_BUFG_CASC10",
|
||||
"CLK_FEED_CK_BUFG_CASC12",
|
||||
"CLK_FEED_R_CK_BUFG_CASC25",
|
||||
"CLK_FEED_EE4A1",
|
||||
"CLK_PMV_LOGIC_OUTS23_0",
|
||||
"CLK_PMV_IMUX29_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC17",
|
||||
"CLK_PMV_LOGIC_OUTS5_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC30",
|
||||
"CLK_PMV_IMUX31_0",
|
||||
"CLK_FEED_CK_GCLK15",
|
||||
"CLK_FEED_R_CK_BUFG_CASC26",
|
||||
"CLK_FEED_WW2END1",
|
||||
"CLK_PMV2_ODIV2",
|
||||
"CLK_FEED_ER1BEG1",
|
||||
"CLK_FEED_EL1BEG0",
|
||||
"CLK_PMV_LOGIC_OUTS1_0",
|
||||
"CLK_PMV_LOGIC_OUTS21_0",
|
||||
"CLK_FEED_NE4C3",
|
||||
"CLK_FEED_WW4C0",
|
||||
"CLK_PMV_IMUX20_0",
|
||||
"CLK_PMV_BYP4_0",
|
||||
"CLK_FEED_CK_GCLK24",
|
||||
"CLK_FEED_NE2A2",
|
||||
"CLK_FEED_SE4BEG3",
|
||||
"CLK_PMV_LOGIC_OUTS16_0",
|
||||
"CLK_PMV_IMUX16_0",
|
||||
"CLK_FEED_CK_BUFG_CASC4",
|
||||
"CLK_PMV_IMUX9_0",
|
||||
"CLK_FEED_CK_GCLK23",
|
||||
"CLK_FEED_CK_BUFG_CASC20",
|
||||
"CLK_FEED_R_CK_GCLK12",
|
||||
"CLK_FEED_R_CK_BUFG_CASC27",
|
||||
"CLK_FEED_SE4C3",
|
||||
"CLK_FEED_CK_GCLK22",
|
||||
"CLK_FEED_NW4A2",
|
||||
"CLK_FEED_R_CK_GCLK9",
|
||||
"CLK_FEED_CK_GCLK17",
|
||||
"CLK_PMV_BYP7_0",
|
||||
"CLK_FEED_CK_BUFG_CASC6",
|
||||
"CLK_FEED_MONITOR_P",
|
||||
"CLK_FEED_NW2A2",
|
||||
"CLK_FEED_EE4BEG1",
|
||||
"CLK_FEED_R_CK_GCLK14",
|
||||
"CLK_FEED_EE4C0",
|
||||
"CLK_PMV_IMUX2_0",
|
||||
"CLK_FEED_EE4BEG3",
|
||||
"CLK_FEED_NE2A1",
|
||||
"CLK_FEED_WL1END3",
|
||||
"CLK_FEED_CK_GCLK28",
|
||||
"CLK_PMV_IMUX35_0",
|
||||
"CLK_PMV_LOGIC_OUTS7_0",
|
||||
"CLK_FEED_WW4B1",
|
||||
"CLK_FEED_SW4END0",
|
||||
"CLK_FEED_WW4END1",
|
||||
"CLK_FEED_R_CK_GCLK17",
|
||||
"CLK_FEED_R_CK_BUFG_CASC11",
|
||||
"CLK_FEED_WW4C1",
|
||||
"CLK_FEED_EL1BEG3",
|
||||
"CLK_PMV_IMUX17_0",
|
||||
"CLK_FEED_SE2A3",
|
||||
"CLK_FEED_R_CK_GCLK22",
|
||||
"CLK_FEED_NE4C0",
|
||||
"CLK_FEED_WW2A3",
|
||||
"CLK_FEED_NW4END1",
|
||||
"CLK_PMV_IMUX8_0",
|
||||
"CLK_FEED_SE2A2",
|
||||
"CLK_FEED_EE4B2",
|
||||
"CLK_FEED_R_CK_GCLK29",
|
||||
"CLK_FEED_WW2END3",
|
||||
"CLK_FEED_LH4",
|
||||
"CLK_FEED_WL1END2",
|
||||
"CLK_FEED_CK_GCLK2",
|
||||
"CLK_FEED_R_CK_GCLK25",
|
||||
"CLK_PMV_FAN3_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC13",
|
||||
"CLK_FEED_CK_BUFG_CASC27",
|
||||
"CLK_FEED_NW2A1",
|
||||
"CLK_FEED_SW4A3",
|
||||
"CLK_FEED_CK_BUFG_CASC31",
|
||||
"CLK_PMV_BYP3_0",
|
||||
"CLK_FEED_CK_GCLK1",
|
||||
"CLK_FEED_LH1",
|
||||
"CLK_FEED_CK_GCLK14",
|
||||
"CLK_FEED_R_CK_GCLK2",
|
||||
"CLK_FEED_R_CK_BUFG_CASC2",
|
||||
"CLK_PMV_CLK0_0",
|
||||
"CLK_FEED_WR1END0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC20",
|
||||
"CLK_FEED_NE4C1",
|
||||
"CLK_FEED_CK_GCLK16",
|
||||
"CLK_PMV_FAN2_0",
|
||||
"CLK_FEED_R_CK_GCLK5",
|
||||
"CLK_FEED_SE4C0",
|
||||
"CLK_FEED_EL1BEG2",
|
||||
"CLK_FEED_EL1BEG1",
|
||||
"CLK_FEED_EE4B1",
|
||||
"CLK_PMV2_A0",
|
||||
"CLK_FEED_CK_BUFG_CASC22",
|
||||
"CLK_PMV_IMUX40_0",
|
||||
"CLK_FEED_WR1END1",
|
||||
"CLK_FEED_NW4END0",
|
||||
"CLK_PMV_IMUX42_0",
|
||||
"CLK_FEED_EE2BEG1",
|
||||
"CLK_FEED_R_CK_GCLK23",
|
||||
"CLK_PMV2_A2",
|
||||
"CLK_FEED_R_CK_GCLK1",
|
||||
"CLK_FEED_LH2",
|
||||
"CLK_FEED_SW2A2",
|
||||
"CLK_FEED_ER1BEG2",
|
||||
"CLK_FEED_WL1END1",
|
||||
"CLK_PMV_IMUX47_0",
|
||||
"CLK_FEED_NW4A1",
|
||||
"CLK_PMV_BYP1_0",
|
||||
"CLK_PMV_IMUX5_0",
|
||||
"CLK_FEED_SW4A2",
|
||||
"CLK_FEED_CK_GCLK10",
|
||||
"CLK_FEED_CK_BUFG_CASC14",
|
||||
"CLK_FEED_CK_BUFG_CASC28",
|
||||
"CLK_PMV_FAN7_0",
|
||||
"CLK_FEED_CK_BUFG_CASC18",
|
||||
"CLK_FEED_R_CK_GCLK24",
|
||||
"CLK_FEED_EE2A1",
|
||||
"CLK_FEED_R_CK_BUFG_CASC15",
|
||||
"CLK_PMV_LOGIC_OUTS10_0",
|
||||
"CLK_FEED_SW2A1",
|
||||
"CLK_FEED_CK_BUFG_CASC8",
|
||||
"CLK_PMV_IMUX45_0",
|
||||
"CLK_FEED_CK_BUFG_CASC2",
|
||||
"CLK_FEED_R_CK_BUFG_CASC8",
|
||||
"CLK_PMV_BYP2_0",
|
||||
"CLK_PMV_IMUX14_0",
|
||||
"CLK_FEED_R_CK_GCLK0",
|
||||
"CLK_FEED_WW4B3",
|
||||
"CLK_PMV_IMUX7_0",
|
||||
"CLK_FEED_CK_GCLK3",
|
||||
"CLK_FEED_LH3",
|
||||
"CLK_PMV_IMUX6_0",
|
||||
"CLK_FEED_SE2A0",
|
||||
"CLK_FEED_NE4C2",
|
||||
"CLK_FEED_WW4C3",
|
||||
"CLK_PMV_IMUX38_0",
|
||||
"CLK_PMV_FAN6_0",
|
||||
"CLK_FEED_EE4B3",
|
||||
"CLK_PMV2_ODIV4",
|
||||
"CLK_FEED_NW4A0",
|
||||
"CLK_FEED_CK_BUFG_CASC25",
|
||||
"CLK_FEED_R_CK_GCLK20",
|
||||
"CLK_FEED_EE2A3",
|
||||
"CLK_FEED_R_CK_GCLK28",
|
||||
"CLK_FEED_LH11",
|
||||
"CLK_FEED_WW4B0",
|
||||
"CLK_PMV_IMUX30_0",
|
||||
"CLK_PMV_FAN4_0",
|
||||
"CLK_FEED_CK_GCLK4",
|
||||
"CLK_FEED_CK_GCLK13",
|
||||
"CLK_FEED_WW2END2",
|
||||
"CLK_FEED_SW4END2",
|
||||
"CLK_PMV_LOGIC_OUTS4_0",
|
||||
"CLK_PMV_LOGIC_OUTS6_0",
|
||||
"CLK_FEED_NW2A0",
|
||||
"CLK_FEED_R_CK_GCLK30",
|
||||
"CLK_FEED_R_CK_BUFG_CASC1",
|
||||
"CLK_FEED_CK_GCLK25",
|
||||
"CLK_PMV_IMUX1_0",
|
||||
"CLK_FEED_CK_BUFG_CASC19",
|
||||
"CLK_PMV_IMUX34_0",
|
||||
"CLK_FEED_WW4A2",
|
||||
"CLK_FEED_R_CK_BUFG_CASC6",
|
||||
"CLK_PMV_LOGIC_OUTS17_0",
|
||||
"CLK_PMV_LOGIC_OUTS9_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC29",
|
||||
"CLK_FEED_SW4END1",
|
||||
"CLK_FEED_LH10",
|
||||
"CLK_FEED_CK_BUFG_CASC0",
|
||||
"CLK_PMV_IMUX21_0",
|
||||
"CLK_FEED_NE4BEG3",
|
||||
"CLK_FEED_R_CK_GCLK26",
|
||||
"CLK_PMV_IMUX41_0",
|
||||
"CLK_PMV_IMUX46_0",
|
||||
"CLK_PMV_IMUX25_0",
|
||||
"CLK_PMV_IMUX39_0",
|
||||
"CLK_FEED_CK_GCLK7",
|
||||
"CLK_FEED_CK_BUFG_CASC23",
|
||||
"CLK_FEED_R_CK_BUFG_CASC16",
|
||||
"CLK_FEED_EE2BEG0",
|
||||
"CLK_FEED_CK_GCLK26",
|
||||
"CLK_FEED_CK_BUFG_CASC15",
|
||||
"CLK_FEED_SW4A1",
|
||||
"CLK_FEED_WW4A0",
|
||||
"CLK_PMV_IMUX22_0",
|
||||
"CLK_PMV_LOGIC_OUTS11_0",
|
||||
"CLK_PMV_BYP5_0",
|
||||
"CLK_PMV_LOGIC_OUTS15_0",
|
||||
"CLK_FEED_NE2A3",
|
||||
"CLK_FEED_CK_BUFG_CASC17",
|
||||
"CLK_FEED_CK_GCLK21",
|
||||
"CLK_PMV_LOGIC_OUTS0_0",
|
||||
"CLK_FEED_NE4BEG0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC23",
|
||||
"CLK_FEED_NE4BEG1",
|
||||
"CLK_PMV_LOGIC_OUTS19_0",
|
||||
"CLK_FEED_WW4END0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC12",
|
||||
"CLK_FEED_SE4BEG2",
|
||||
"CLK_FEED_EE2BEG3",
|
||||
"CLK_FEED_R_CK_GCLK7",
|
||||
"CLK_PMV_IMUX4_0",
|
||||
"CLK_FEED_CK_BUFG_CASC30",
|
||||
"CLK_PMV2_A1",
|
||||
"CLK_FEED_R_CK_GCLK8",
|
||||
"CLK_FEED_WW4A1",
|
||||
"CLK_FEED_EE4BEG0",
|
||||
"CLK_FEED_WL1END2",
|
||||
"CLK_FEED_WL1END3",
|
||||
"CLK_FEED_WR1END0",
|
||||
"CLK_FEED_WR1END1",
|
||||
"CLK_FEED_WR1END2",
|
||||
"CLK_FEED_CK_BUFG_CASC24",
|
||||
"CLK_FEED_R_CK_GCLK16",
|
||||
"CLK_FEED_R_CK_GCLK10",
|
||||
"CLK_FEED_CK_BUFG_CASC16",
|
||||
"CLK_FEED_R_CK_BUFG_CASC5",
|
||||
"CLK_FEED_CK_GCLK5",
|
||||
"CLK_FEED_R_CK_BUFG_CASC18",
|
||||
"CLK_FEED_NE4BEG2",
|
||||
"CLK_FEED_R_CK_GCLK11",
|
||||
"CLK_PMV_LOGIC_OUTS20_0",
|
||||
"CLK_FEED_R_CK_GCLK4",
|
||||
"CLK_PMV_IMUX12_0",
|
||||
"CLK_PMV_IMUX37_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC7",
|
||||
"CLK_PMV_IMUX18_0",
|
||||
"CLK_FEED_SE4C1",
|
||||
"CLK_FEED_CK_GCLK20",
|
||||
"CLK_PMV_LOGIC_OUTS8_0",
|
||||
"CLK_FEED_NW4END2",
|
||||
"CLK_FEED_EE4BEG2",
|
||||
"CLK_FEED_CK_GCLK30",
|
||||
"CLK_FEED_SE2A1",
|
||||
"CLK_FEED_LH6",
|
||||
"CLK_FEED_CK_GCLK29",
|
||||
"CLK_FEED_R_CK_GCLK27",
|
||||
"CLK_FEED_EE4C1",
|
||||
"CLK_FEED_SW4A0",
|
||||
"CLK_FEED_CK_GCLK9",
|
||||
"CLK_FEED_CK_BUFG_CASC11",
|
||||
"CLK_FEED_CK_GCLK8",
|
||||
"CLK_FEED_R_CK_BUFG_CASC9",
|
||||
"CLK_FEED_R_CK_BUFG_CASC3",
|
||||
"CLK_FEED_WW4END2",
|
||||
"CLK_FEED_CK_GCLK6",
|
||||
"CLK_FEED_EE2A2",
|
||||
"CLK_PMV_LOGIC_OUTS2_0",
|
||||
"CLK_PMV_LOGIC_OUTS14_0",
|
||||
"CLK_FEED_EE4C3",
|
||||
"CLK_FEED_NW2A3",
|
||||
"CLK_PMV_CTRL0_0",
|
||||
"CLK_PMV_LOGIC_OUTS22_0",
|
||||
"CLK_PMV_IMUX0_0",
|
||||
"CLK_FEED_EE2A0",
|
||||
"CLK_PMV_FAN5_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC24",
|
||||
"CLK_PMV_BYP6_0",
|
||||
"CLK_FEED_R_CK_GCLK19",
|
||||
"CLK_FEED_EE2BEG2",
|
||||
"CLK_FEED_R_CK_BUFG_CASC19",
|
||||
"CLK_FEED_WW4END3",
|
||||
"CLK_FEED_CK_GCLK31",
|
||||
"CLK_FEED_SW2A3",
|
||||
"CLK_PMV_IMUX23_0",
|
||||
"CLK_PMV_IMUX19_0",
|
||||
"CLK_PMV_IMUX36_0",
|
||||
"CLK_FEED_SE4C2",
|
||||
"CLK_FEED_EE4C2",
|
||||
"CLK_PMV_IMUX13_0",
|
||||
"CLK_FEED_SE4BEG0",
|
||||
"CLK_PMV_IMUX27_0",
|
||||
"CLK_FEED_LH9",
|
||||
"CLK_PMV2_O",
|
||||
"CLK_FEED_R_CK_GCLK15",
|
||||
"CLK_PMV_IMUX3_0",
|
||||
"CLK_PMV_CTRL1_0",
|
||||
"CLK_FEED_LH5",
|
||||
"CLK_PMV_LOGIC_OUTS13_0",
|
||||
"CLK_FEED_NW4A3",
|
||||
"CLK_PMV_IMUX10_0",
|
||||
"CLK_PMV_IMUX32_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC4",
|
||||
"CLK_FEED_R_CK_BUFG_CASC21",
|
||||
"CLK_FEED_CK_GCLK0",
|
||||
"CLK_FEED_MONITOR_N",
|
||||
"CLK_FEED_CK_GCLK11",
|
||||
"CLK_FEED_R_CK_BUFG_CASC31",
|
||||
"CLK_FEED_WW2A0",
|
||||
"CLK_FEED_EE4A0",
|
||||
"CLK_FEED_CK_BUFG_CASC9",
|
||||
"CLK_FEED_R_CK_GCLK21",
|
||||
"CLK_FEED_WR1END3",
|
||||
"CLK_FEED_LH8"
|
||||
],
|
||||
"pips": {},
|
||||
"tile_type": "CLK_PMV2_SVT",
|
||||
"sites": []
|
||||
}
|
||||
"CLK_FEED_WW2A0",
|
||||
"CLK_FEED_WW2A1",
|
||||
"CLK_FEED_WW2A2",
|
||||
"CLK_FEED_WW2A3",
|
||||
"CLK_FEED_WW2END0",
|
||||
"CLK_FEED_WW2END1",
|
||||
"CLK_FEED_WW2END2",
|
||||
"CLK_FEED_WW2END3",
|
||||
"CLK_FEED_WW4A0",
|
||||
"CLK_FEED_WW4A1",
|
||||
"CLK_FEED_WW4A2",
|
||||
"CLK_FEED_WW4A3",
|
||||
"CLK_FEED_WW4B0",
|
||||
"CLK_FEED_WW4B1",
|
||||
"CLK_FEED_WW4B2",
|
||||
"CLK_FEED_WW4B3",
|
||||
"CLK_FEED_WW4C0",
|
||||
"CLK_FEED_WW4C1",
|
||||
"CLK_FEED_WW4C2",
|
||||
"CLK_FEED_WW4C3",
|
||||
"CLK_FEED_WW4END0",
|
||||
"CLK_FEED_WW4END1",
|
||||
"CLK_FEED_WW4END2",
|
||||
"CLK_FEED_WW4END3",
|
||||
"CLK_PMV2_A0",
|
||||
"CLK_PMV2_A1",
|
||||
"CLK_PMV2_A2",
|
||||
"CLK_PMV2_EN",
|
||||
"CLK_PMV2_O",
|
||||
"CLK_PMV2_ODIV2",
|
||||
"CLK_PMV2_ODIV4",
|
||||
"CLK_PMV_BYP0_0",
|
||||
"CLK_PMV_BYP1_0",
|
||||
"CLK_PMV_BYP2_0",
|
||||
"CLK_PMV_BYP3_0",
|
||||
"CLK_PMV_BYP4_0",
|
||||
"CLK_PMV_BYP5_0",
|
||||
"CLK_PMV_BYP6_0",
|
||||
"CLK_PMV_BYP7_0",
|
||||
"CLK_PMV_CLK0_0",
|
||||
"CLK_PMV_CLK1_0",
|
||||
"CLK_PMV_CTRL0_0",
|
||||
"CLK_PMV_CTRL1_0",
|
||||
"CLK_PMV_FAN0_0",
|
||||
"CLK_PMV_FAN1_0",
|
||||
"CLK_PMV_FAN2_0",
|
||||
"CLK_PMV_FAN3_0",
|
||||
"CLK_PMV_FAN4_0",
|
||||
"CLK_PMV_FAN5_0",
|
||||
"CLK_PMV_FAN6_0",
|
||||
"CLK_PMV_FAN7_0",
|
||||
"CLK_PMV_IMUX0_0",
|
||||
"CLK_PMV_IMUX10_0",
|
||||
"CLK_PMV_IMUX11_0",
|
||||
"CLK_PMV_IMUX12_0",
|
||||
"CLK_PMV_IMUX13_0",
|
||||
"CLK_PMV_IMUX14_0",
|
||||
"CLK_PMV_IMUX15_0",
|
||||
"CLK_PMV_IMUX16_0",
|
||||
"CLK_PMV_IMUX17_0",
|
||||
"CLK_PMV_IMUX18_0",
|
||||
"CLK_PMV_IMUX19_0",
|
||||
"CLK_PMV_IMUX1_0",
|
||||
"CLK_PMV_IMUX20_0",
|
||||
"CLK_PMV_IMUX21_0",
|
||||
"CLK_PMV_IMUX22_0",
|
||||
"CLK_PMV_IMUX23_0",
|
||||
"CLK_PMV_IMUX24_0",
|
||||
"CLK_PMV_IMUX25_0",
|
||||
"CLK_PMV_IMUX26_0",
|
||||
"CLK_PMV_IMUX27_0",
|
||||
"CLK_PMV_IMUX28_0",
|
||||
"CLK_PMV_IMUX29_0",
|
||||
"CLK_PMV_IMUX2_0",
|
||||
"CLK_PMV_IMUX30_0",
|
||||
"CLK_PMV_IMUX31_0",
|
||||
"CLK_PMV_IMUX32_0",
|
||||
"CLK_PMV_IMUX33_0",
|
||||
"CLK_PMV_IMUX34_0",
|
||||
"CLK_PMV_IMUX35_0",
|
||||
"CLK_PMV_IMUX36_0",
|
||||
"CLK_PMV_IMUX37_0",
|
||||
"CLK_PMV_IMUX38_0",
|
||||
"CLK_PMV_IMUX39_0",
|
||||
"CLK_PMV_IMUX3_0",
|
||||
"CLK_PMV_IMUX40_0",
|
||||
"CLK_PMV_IMUX41_0",
|
||||
"CLK_PMV_IMUX42_0",
|
||||
"CLK_PMV_IMUX43_0",
|
||||
"CLK_PMV_IMUX44_0",
|
||||
"CLK_PMV_IMUX45_0",
|
||||
"CLK_PMV_IMUX46_0",
|
||||
"CLK_PMV_IMUX47_0",
|
||||
"CLK_PMV_IMUX4_0",
|
||||
"CLK_PMV_IMUX5_0",
|
||||
"CLK_PMV_IMUX6_0",
|
||||
"CLK_PMV_IMUX7_0",
|
||||
"CLK_PMV_IMUX8_0",
|
||||
"CLK_PMV_IMUX9_0",
|
||||
"CLK_PMV_LOGIC_OUTS0_0",
|
||||
"CLK_PMV_LOGIC_OUTS10_0",
|
||||
"CLK_PMV_LOGIC_OUTS11_0",
|
||||
"CLK_PMV_LOGIC_OUTS12_0",
|
||||
"CLK_PMV_LOGIC_OUTS13_0",
|
||||
"CLK_PMV_LOGIC_OUTS14_0",
|
||||
"CLK_PMV_LOGIC_OUTS15_0",
|
||||
"CLK_PMV_LOGIC_OUTS16_0",
|
||||
"CLK_PMV_LOGIC_OUTS17_0",
|
||||
"CLK_PMV_LOGIC_OUTS18_0",
|
||||
"CLK_PMV_LOGIC_OUTS19_0",
|
||||
"CLK_PMV_LOGIC_OUTS1_0",
|
||||
"CLK_PMV_LOGIC_OUTS20_0",
|
||||
"CLK_PMV_LOGIC_OUTS21_0",
|
||||
"CLK_PMV_LOGIC_OUTS22_0",
|
||||
"CLK_PMV_LOGIC_OUTS23_0",
|
||||
"CLK_PMV_LOGIC_OUTS2_0",
|
||||
"CLK_PMV_LOGIC_OUTS3_0",
|
||||
"CLK_PMV_LOGIC_OUTS4_0",
|
||||
"CLK_PMV_LOGIC_OUTS5_0",
|
||||
"CLK_PMV_LOGIC_OUTS6_0",
|
||||
"CLK_PMV_LOGIC_OUTS7_0",
|
||||
"CLK_PMV_LOGIC_OUTS8_0",
|
||||
"CLK_PMV_LOGIC_OUTS9_0"
|
||||
]
|
||||
}
|
||||
|
|
@ -1,359 +1,359 @@
|
|||
{
|
||||
"pips": {},
|
||||
"sites": [],
|
||||
"tile_type": "CLK_PMVIOB",
|
||||
"wires": [
|
||||
"CLK_FEED_NE2A0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC28",
|
||||
"CLK_FEED_CK_GCLK19",
|
||||
"CLK_FEED_ER1BEG3",
|
||||
"CLK_FEED_CK_BUFG_CASC29",
|
||||
"CLK_FEED_R_CK_GCLK18",
|
||||
"CLK_FEED_R_CK_GCLK31",
|
||||
"CLK_PMV_CLK1_0",
|
||||
"CLK_FEED_CK_BUFG_CASC0",
|
||||
"CLK_FEED_CK_BUFG_CASC1",
|
||||
"CLK_FEED_R_CK_GCLK6",
|
||||
"CLK_FEED_LH7",
|
||||
"CLK_FEED_CK_BUFG_CASC3",
|
||||
"CLK_FEED_WW4B2",
|
||||
"CLK_PMVIOB_ODIV4",
|
||||
"CLK_FEED_LH12",
|
||||
"CLK_FEED_R_CK_BUFG_CASC14",
|
||||
"CLK_FEED_EE4A3",
|
||||
"CLK_FEED_CK_BUFG_CASC10",
|
||||
"CLK_FEED_CK_BUFG_CASC11",
|
||||
"CLK_FEED_CK_BUFG_CASC12",
|
||||
"CLK_FEED_CK_BUFG_CASC13",
|
||||
"CLK_PMV_IMUX28_0",
|
||||
"CLK_PMV_IMUX24_0",
|
||||
"CLK_FEED_CK_BUFG_CASC14",
|
||||
"CLK_FEED_CK_BUFG_CASC15",
|
||||
"CLK_FEED_CK_BUFG_CASC16",
|
||||
"CLK_FEED_CK_BUFG_CASC17",
|
||||
"CLK_FEED_CK_BUFG_CASC18",
|
||||
"CLK_FEED_CK_BUFG_CASC19",
|
||||
"CLK_FEED_CK_BUFG_CASC2",
|
||||
"CLK_FEED_CK_BUFG_CASC20",
|
||||
"CLK_FEED_CK_BUFG_CASC21",
|
||||
"CLK_FEED_CK_BUFG_CASC22",
|
||||
"CLK_FEED_CK_BUFG_CASC23",
|
||||
"CLK_FEED_CK_BUFG_CASC24",
|
||||
"CLK_FEED_CK_BUFG_CASC25",
|
||||
"CLK_FEED_CK_BUFG_CASC26",
|
||||
"CLK_FEED_CK_BUFG_CASC27",
|
||||
"CLK_FEED_CK_BUFG_CASC28",
|
||||
"CLK_FEED_CK_BUFG_CASC29",
|
||||
"CLK_FEED_CK_BUFG_CASC3",
|
||||
"CLK_FEED_CK_BUFG_CASC30",
|
||||
"CLK_FEED_CK_BUFG_CASC31",
|
||||
"CLK_FEED_CK_BUFG_CASC4",
|
||||
"CLK_FEED_CK_BUFG_CASC5",
|
||||
"CLK_FEED_CK_BUFG_CASC6",
|
||||
"CLK_FEED_CK_BUFG_CASC7",
|
||||
"CLK_FEED_CK_BUFG_CASC8",
|
||||
"CLK_FEED_CK_BUFG_CASC9",
|
||||
"CLK_FEED_CK_GCLK0",
|
||||
"CLK_FEED_CK_GCLK1",
|
||||
"CLK_FEED_CK_GCLK10",
|
||||
"CLK_FEED_CK_GCLK11",
|
||||
"CLK_FEED_CK_GCLK12",
|
||||
"CLK_FEED_CK_GCLK13",
|
||||
"CLK_FEED_CK_GCLK14",
|
||||
"CLK_FEED_CK_GCLK15",
|
||||
"CLK_FEED_CK_GCLK16",
|
||||
"CLK_FEED_CK_GCLK17",
|
||||
"CLK_FEED_CK_GCLK18",
|
||||
"CLK_FEED_CK_GCLK19",
|
||||
"CLK_FEED_CK_GCLK2",
|
||||
"CLK_FEED_CK_GCLK20",
|
||||
"CLK_FEED_CK_GCLK21",
|
||||
"CLK_FEED_CK_GCLK22",
|
||||
"CLK_FEED_CK_GCLK23",
|
||||
"CLK_FEED_CK_GCLK24",
|
||||
"CLK_FEED_CK_GCLK25",
|
||||
"CLK_FEED_CK_GCLK26",
|
||||
"CLK_FEED_CK_GCLK27",
|
||||
"CLK_FEED_CK_GCLK28",
|
||||
"CLK_FEED_CK_GCLK29",
|
||||
"CLK_FEED_CK_GCLK3",
|
||||
"CLK_FEED_CK_GCLK30",
|
||||
"CLK_FEED_CK_GCLK31",
|
||||
"CLK_FEED_CK_GCLK4",
|
||||
"CLK_FEED_CK_GCLK5",
|
||||
"CLK_FEED_CK_GCLK6",
|
||||
"CLK_FEED_CK_GCLK7",
|
||||
"CLK_FEED_CK_GCLK8",
|
||||
"CLK_FEED_CK_GCLK9",
|
||||
"CLK_FEED_EE2A0",
|
||||
"CLK_FEED_EE2A1",
|
||||
"CLK_FEED_EE2A2",
|
||||
"CLK_FEED_EE2A3",
|
||||
"CLK_FEED_EE2BEG0",
|
||||
"CLK_FEED_EE2BEG1",
|
||||
"CLK_FEED_EE2BEG2",
|
||||
"CLK_FEED_EE2BEG3",
|
||||
"CLK_FEED_EE4A0",
|
||||
"CLK_FEED_EE4A1",
|
||||
"CLK_FEED_EE4A2",
|
||||
"CLK_FEED_EE4A3",
|
||||
"CLK_FEED_EE4B0",
|
||||
"CLK_FEED_EE4B1",
|
||||
"CLK_FEED_EE4B2",
|
||||
"CLK_FEED_EE4B3",
|
||||
"CLK_FEED_EE4BEG0",
|
||||
"CLK_FEED_EE4BEG1",
|
||||
"CLK_FEED_EE4BEG2",
|
||||
"CLK_FEED_EE4BEG3",
|
||||
"CLK_FEED_EE4C0",
|
||||
"CLK_FEED_EE4C1",
|
||||
"CLK_FEED_EE4C2",
|
||||
"CLK_FEED_EE4C3",
|
||||
"CLK_FEED_EL1BEG0",
|
||||
"CLK_FEED_EL1BEG1",
|
||||
"CLK_FEED_EL1BEG2",
|
||||
"CLK_FEED_EL1BEG3",
|
||||
"CLK_FEED_ER1BEG0",
|
||||
"CLK_PMVIOB_ODIV2",
|
||||
"CLK_PMV_IMUX44_0",
|
||||
"CLK_FEED_ER1BEG1",
|
||||
"CLK_FEED_ER1BEG2",
|
||||
"CLK_FEED_ER1BEG3",
|
||||
"CLK_FEED_LH1",
|
||||
"CLK_FEED_LH10",
|
||||
"CLK_FEED_LH11",
|
||||
"CLK_FEED_LH12",
|
||||
"CLK_FEED_LH2",
|
||||
"CLK_FEED_LH3",
|
||||
"CLK_FEED_LH4",
|
||||
"CLK_FEED_LH5",
|
||||
"CLK_FEED_LH6",
|
||||
"CLK_FEED_LH7",
|
||||
"CLK_FEED_LH8",
|
||||
"CLK_FEED_LH9",
|
||||
"CLK_FEED_MONITOR_N",
|
||||
"CLK_FEED_MONITOR_P",
|
||||
"CLK_FEED_NE2A0",
|
||||
"CLK_FEED_NE2A1",
|
||||
"CLK_FEED_NE2A2",
|
||||
"CLK_FEED_NE2A3",
|
||||
"CLK_FEED_NE4BEG0",
|
||||
"CLK_FEED_NE4BEG1",
|
||||
"CLK_FEED_NE4BEG2",
|
||||
"CLK_FEED_NE4BEG3",
|
||||
"CLK_FEED_NE4C0",
|
||||
"CLK_FEED_NE4C1",
|
||||
"CLK_FEED_NE4C2",
|
||||
"CLK_FEED_NE4C3",
|
||||
"CLK_FEED_NW2A0",
|
||||
"CLK_FEED_NW2A1",
|
||||
"CLK_FEED_NW2A2",
|
||||
"CLK_FEED_NW2A3",
|
||||
"CLK_FEED_NW4A0",
|
||||
"CLK_FEED_NW4A1",
|
||||
"CLK_FEED_NW4A2",
|
||||
"CLK_FEED_NW4A3",
|
||||
"CLK_FEED_NW4END0",
|
||||
"CLK_FEED_NW4END1",
|
||||
"CLK_FEED_NW4END2",
|
||||
"CLK_FEED_NW4END3",
|
||||
"CLK_FEED_R_CK_BUFG_CASC0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC1",
|
||||
"CLK_FEED_R_CK_BUFG_CASC10",
|
||||
"CLK_FEED_R_CK_BUFG_CASC11",
|
||||
"CLK_FEED_R_CK_BUFG_CASC12",
|
||||
"CLK_FEED_R_CK_BUFG_CASC13",
|
||||
"CLK_FEED_R_CK_BUFG_CASC14",
|
||||
"CLK_FEED_R_CK_BUFG_CASC15",
|
||||
"CLK_FEED_R_CK_BUFG_CASC16",
|
||||
"CLK_FEED_R_CK_BUFG_CASC17",
|
||||
"CLK_FEED_R_CK_BUFG_CASC18",
|
||||
"CLK_FEED_R_CK_BUFG_CASC19",
|
||||
"CLK_FEED_R_CK_BUFG_CASC2",
|
||||
"CLK_FEED_R_CK_BUFG_CASC20",
|
||||
"CLK_FEED_R_CK_BUFG_CASC21",
|
||||
"CLK_FEED_R_CK_BUFG_CASC22",
|
||||
"CLK_FEED_R_CK_BUFG_CASC23",
|
||||
"CLK_FEED_R_CK_BUFG_CASC24",
|
||||
"CLK_FEED_R_CK_BUFG_CASC25",
|
||||
"CLK_FEED_R_CK_BUFG_CASC26",
|
||||
"CLK_FEED_R_CK_BUFG_CASC27",
|
||||
"CLK_FEED_R_CK_BUFG_CASC28",
|
||||
"CLK_FEED_R_CK_BUFG_CASC29",
|
||||
"CLK_FEED_R_CK_BUFG_CASC3",
|
||||
"CLK_FEED_R_CK_BUFG_CASC30",
|
||||
"CLK_FEED_R_CK_BUFG_CASC31",
|
||||
"CLK_FEED_R_CK_BUFG_CASC4",
|
||||
"CLK_FEED_R_CK_BUFG_CASC5",
|
||||
"CLK_FEED_R_CK_BUFG_CASC6",
|
||||
"CLK_FEED_R_CK_BUFG_CASC7",
|
||||
"CLK_FEED_R_CK_BUFG_CASC8",
|
||||
"CLK_FEED_R_CK_BUFG_CASC9",
|
||||
"CLK_FEED_R_CK_GCLK0",
|
||||
"CLK_FEED_R_CK_GCLK1",
|
||||
"CLK_FEED_R_CK_GCLK10",
|
||||
"CLK_FEED_R_CK_GCLK11",
|
||||
"CLK_FEED_R_CK_GCLK12",
|
||||
"CLK_FEED_R_CK_GCLK13",
|
||||
"CLK_FEED_R_CK_GCLK14",
|
||||
"CLK_FEED_R_CK_GCLK15",
|
||||
"CLK_FEED_R_CK_GCLK16",
|
||||
"CLK_FEED_R_CK_GCLK17",
|
||||
"CLK_FEED_R_CK_GCLK18",
|
||||
"CLK_FEED_R_CK_GCLK19",
|
||||
"CLK_FEED_R_CK_GCLK2",
|
||||
"CLK_FEED_R_CK_GCLK20",
|
||||
"CLK_FEED_R_CK_GCLK21",
|
||||
"CLK_FEED_R_CK_GCLK22",
|
||||
"CLK_FEED_R_CK_GCLK23",
|
||||
"CLK_FEED_R_CK_GCLK24",
|
||||
"CLK_FEED_R_CK_GCLK25",
|
||||
"CLK_FEED_R_CK_GCLK26",
|
||||
"CLK_FEED_R_CK_GCLK27",
|
||||
"CLK_FEED_R_CK_GCLK28",
|
||||
"CLK_FEED_R_CK_GCLK29",
|
||||
"CLK_FEED_R_CK_GCLK3",
|
||||
"CLK_FEED_R_CK_GCLK30",
|
||||
"CLK_FEED_R_CK_GCLK31",
|
||||
"CLK_FEED_R_CK_GCLK4",
|
||||
"CLK_FEED_R_CK_GCLK5",
|
||||
"CLK_FEED_R_CK_GCLK6",
|
||||
"CLK_FEED_R_CK_GCLK7",
|
||||
"CLK_FEED_R_CK_GCLK8",
|
||||
"CLK_FEED_R_CK_GCLK9",
|
||||
"CLK_FEED_SE2A0",
|
||||
"CLK_FEED_SE2A1",
|
||||
"CLK_FEED_SE2A2",
|
||||
"CLK_FEED_SE2A3",
|
||||
"CLK_FEED_SE4BEG0",
|
||||
"CLK_FEED_SE4BEG1",
|
||||
"CLK_FEED_SE4BEG2",
|
||||
"CLK_FEED_SE4BEG3",
|
||||
"CLK_FEED_SE4C0",
|
||||
"CLK_FEED_SE4C1",
|
||||
"CLK_FEED_SE4C2",
|
||||
"CLK_FEED_SE4C3",
|
||||
"CLK_FEED_SW2A0",
|
||||
"CLK_FEED_SW2A1",
|
||||
"CLK_FEED_SW2A2",
|
||||
"CLK_FEED_SW2A3",
|
||||
"CLK_FEED_SW4A0",
|
||||
"CLK_FEED_SW4A1",
|
||||
"CLK_FEED_SW4A2",
|
||||
"CLK_FEED_SW4A3",
|
||||
"CLK_FEED_SW4END0",
|
||||
"CLK_FEED_SW4END1",
|
||||
"CLK_FEED_SW4END2",
|
||||
"CLK_FEED_SW4END3",
|
||||
"CLK_FEED_WL1END0",
|
||||
"CLK_FEED_SW2A0",
|
||||
"CLK_PMV_IMUX15_0",
|
||||
"CLK_PMV_IMUX43_0",
|
||||
"CLK_PMV_FAN0_0",
|
||||
"CLK_FEED_R_CK_GCLK13",
|
||||
"CLK_PMV_FAN1_0",
|
||||
"CLK_FEED_CK_BUFG_CASC26",
|
||||
"CLK_FEED_SE4BEG1",
|
||||
"CLK_FEED_CK_BUFG_CASC7",
|
||||
"CLK_PMV_IMUX11_0",
|
||||
"CLK_PMV_LOGIC_OUTS12_0",
|
||||
"CLK_FEED_CK_BUFG_CASC5",
|
||||
"CLK_FEED_CK_GCLK18",
|
||||
"CLK_PMV_BYP0_0",
|
||||
"CLK_FEED_WW4A3",
|
||||
"CLK_FEED_R_CK_BUFG_CASC10",
|
||||
"CLK_FEED_WW4C2",
|
||||
"CLK_FEED_NW4END3",
|
||||
"CLK_FEED_CK_GCLK27",
|
||||
"CLK_PMV_IMUX33_0",
|
||||
"CLK_FEED_R_CK_GCLK3",
|
||||
"CLK_FEED_CK_BUFG_CASC21",
|
||||
"CLK_FEED_WW2END0",
|
||||
"CLK_FEED_WW2A1",
|
||||
"CLK_PMV_LOGIC_OUTS18_0",
|
||||
"CLK_PMV_IMUX26_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC22",
|
||||
"CLK_PMV_LOGIC_OUTS3_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC0",
|
||||
"CLK_FEED_CK_GCLK12",
|
||||
"CLK_FEED_EE4A2",
|
||||
"CLK_FEED_EE4B0",
|
||||
"CLK_FEED_WW2A2",
|
||||
"CLK_FEED_CK_BUFG_CASC10",
|
||||
"CLK_FEED_CK_BUFG_CASC12",
|
||||
"CLK_FEED_R_CK_BUFG_CASC25",
|
||||
"CLK_FEED_EE4A1",
|
||||
"CLK_PMV_LOGIC_OUTS23_0",
|
||||
"CLK_PMV_IMUX29_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC17",
|
||||
"CLK_PMV_LOGIC_OUTS5_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC30",
|
||||
"CLK_PMV_IMUX31_0",
|
||||
"CLK_FEED_CK_GCLK15",
|
||||
"CLK_PMVIOB_EN",
|
||||
"CLK_FEED_R_CK_BUFG_CASC26",
|
||||
"CLK_FEED_WW2END1",
|
||||
"CLK_FEED_ER1BEG1",
|
||||
"CLK_FEED_EL1BEG0",
|
||||
"CLK_PMV_LOGIC_OUTS1_0",
|
||||
"CLK_PMV_LOGIC_OUTS21_0",
|
||||
"CLK_FEED_NE4C3",
|
||||
"CLK_FEED_WW4C0",
|
||||
"CLK_PMV_IMUX20_0",
|
||||
"CLK_PMV_BYP4_0",
|
||||
"CLK_FEED_CK_GCLK24",
|
||||
"CLK_FEED_NE2A2",
|
||||
"CLK_FEED_SE4BEG3",
|
||||
"CLK_PMV_LOGIC_OUTS16_0",
|
||||
"CLK_PMV_IMUX16_0",
|
||||
"CLK_FEED_CK_BUFG_CASC4",
|
||||
"CLK_PMV_IMUX9_0",
|
||||
"CLK_FEED_CK_GCLK23",
|
||||
"CLK_FEED_CK_BUFG_CASC20",
|
||||
"CLK_FEED_R_CK_GCLK12",
|
||||
"CLK_FEED_R_CK_BUFG_CASC27",
|
||||
"CLK_FEED_SE4C3",
|
||||
"CLK_FEED_CK_GCLK22",
|
||||
"CLK_FEED_NW4A2",
|
||||
"CLK_FEED_R_CK_GCLK9",
|
||||
"CLK_FEED_CK_GCLK17",
|
||||
"CLK_PMV_BYP7_0",
|
||||
"CLK_FEED_CK_BUFG_CASC6",
|
||||
"CLK_FEED_MONITOR_P",
|
||||
"CLK_FEED_NW2A2",
|
||||
"CLK_FEED_EE4BEG1",
|
||||
"CLK_FEED_R_CK_GCLK14",
|
||||
"CLK_FEED_EE4C0",
|
||||
"CLK_PMV_IMUX2_0",
|
||||
"CLK_FEED_EE4BEG3",
|
||||
"CLK_FEED_NE2A1",
|
||||
"CLK_FEED_WL1END3",
|
||||
"CLK_FEED_CK_GCLK28",
|
||||
"CLK_PMV_IMUX35_0",
|
||||
"CLK_PMV_LOGIC_OUTS7_0",
|
||||
"CLK_FEED_WW4B1",
|
||||
"CLK_FEED_SW4END0",
|
||||
"CLK_FEED_WW4END1",
|
||||
"CLK_FEED_R_CK_GCLK17",
|
||||
"CLK_FEED_R_CK_BUFG_CASC11",
|
||||
"CLK_FEED_WW4C1",
|
||||
"CLK_FEED_EL1BEG3",
|
||||
"CLK_PMV_IMUX17_0",
|
||||
"CLK_FEED_SE2A3",
|
||||
"CLK_FEED_R_CK_GCLK22",
|
||||
"CLK_FEED_NE4C0",
|
||||
"CLK_FEED_WW2A3",
|
||||
"CLK_FEED_NW4END1",
|
||||
"CLK_PMV_IMUX8_0",
|
||||
"CLK_FEED_SE2A2",
|
||||
"CLK_FEED_EE4B2",
|
||||
"CLK_FEED_R_CK_GCLK29",
|
||||
"CLK_FEED_WW2END3",
|
||||
"CLK_FEED_LH4",
|
||||
"CLK_FEED_WL1END2",
|
||||
"CLK_FEED_CK_GCLK2",
|
||||
"CLK_FEED_R_CK_GCLK25",
|
||||
"CLK_PMV_FAN3_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC13",
|
||||
"CLK_FEED_CK_BUFG_CASC27",
|
||||
"CLK_FEED_NW2A1",
|
||||
"CLK_FEED_SW4A3",
|
||||
"CLK_FEED_CK_BUFG_CASC31",
|
||||
"CLK_PMV_BYP3_0",
|
||||
"CLK_FEED_CK_GCLK1",
|
||||
"CLK_FEED_LH1",
|
||||
"CLK_FEED_CK_GCLK14",
|
||||
"CLK_FEED_R_CK_GCLK2",
|
||||
"CLK_FEED_R_CK_BUFG_CASC2",
|
||||
"CLK_PMV_CLK0_0",
|
||||
"CLK_FEED_WR1END0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC20",
|
||||
"CLK_FEED_NE4C1",
|
||||
"CLK_FEED_CK_GCLK16",
|
||||
"CLK_PMV_FAN2_0",
|
||||
"CLK_FEED_R_CK_GCLK5",
|
||||
"CLK_FEED_SE4C0",
|
||||
"CLK_FEED_EL1BEG2",
|
||||
"CLK_FEED_EL1BEG1",
|
||||
"CLK_FEED_EE4B1",
|
||||
"CLK_FEED_CK_BUFG_CASC22",
|
||||
"CLK_PMV_IMUX40_0",
|
||||
"CLK_FEED_WR1END1",
|
||||
"CLK_FEED_NW4END0",
|
||||
"CLK_PMV_IMUX42_0",
|
||||
"CLK_FEED_EE2BEG1",
|
||||
"CLK_FEED_R_CK_GCLK23",
|
||||
"CLK_PMVIOB_A0",
|
||||
"CLK_FEED_R_CK_GCLK1",
|
||||
"CLK_FEED_LH2",
|
||||
"CLK_FEED_SW2A2",
|
||||
"CLK_FEED_ER1BEG2",
|
||||
"CLK_FEED_WL1END1",
|
||||
"CLK_PMV_IMUX47_0",
|
||||
"CLK_FEED_NW4A1",
|
||||
"CLK_PMV_BYP1_0",
|
||||
"CLK_PMV_IMUX5_0",
|
||||
"CLK_FEED_SW4A2",
|
||||
"CLK_FEED_CK_GCLK10",
|
||||
"CLK_FEED_CK_BUFG_CASC14",
|
||||
"CLK_FEED_CK_BUFG_CASC28",
|
||||
"CLK_PMV_FAN7_0",
|
||||
"CLK_FEED_CK_BUFG_CASC18",
|
||||
"CLK_FEED_R_CK_GCLK24",
|
||||
"CLK_FEED_EE2A1",
|
||||
"CLK_FEED_R_CK_BUFG_CASC15",
|
||||
"CLK_PMV_LOGIC_OUTS10_0",
|
||||
"CLK_FEED_SW2A1",
|
||||
"CLK_FEED_CK_BUFG_CASC8",
|
||||
"CLK_PMV_IMUX45_0",
|
||||
"CLK_FEED_CK_BUFG_CASC2",
|
||||
"CLK_FEED_R_CK_BUFG_CASC8",
|
||||
"CLK_PMV_BYP2_0",
|
||||
"CLK_PMV_IMUX14_0",
|
||||
"CLK_FEED_R_CK_GCLK0",
|
||||
"CLK_FEED_WW4B3",
|
||||
"CLK_PMV_IMUX7_0",
|
||||
"CLK_FEED_CK_GCLK3",
|
||||
"CLK_FEED_LH3",
|
||||
"CLK_PMV_IMUX6_0",
|
||||
"CLK_FEED_SE2A0",
|
||||
"CLK_FEED_NE4C2",
|
||||
"CLK_FEED_WW4C3",
|
||||
"CLK_PMV_IMUX38_0",
|
||||
"CLK_PMV_FAN6_0",
|
||||
"CLK_FEED_EE4B3",
|
||||
"CLK_FEED_NW4A0",
|
||||
"CLK_FEED_CK_BUFG_CASC25",
|
||||
"CLK_FEED_R_CK_GCLK20",
|
||||
"CLK_FEED_EE2A3",
|
||||
"CLK_FEED_R_CK_GCLK28",
|
||||
"CLK_FEED_LH11",
|
||||
"CLK_FEED_WW4B0",
|
||||
"CLK_PMV_IMUX30_0",
|
||||
"CLK_PMV_FAN4_0",
|
||||
"CLK_FEED_CK_GCLK4",
|
||||
"CLK_FEED_CK_GCLK13",
|
||||
"CLK_FEED_WW2END2",
|
||||
"CLK_FEED_SW4END2",
|
||||
"CLK_PMV_LOGIC_OUTS4_0",
|
||||
"CLK_PMV_LOGIC_OUTS6_0",
|
||||
"CLK_FEED_NW2A0",
|
||||
"CLK_FEED_R_CK_GCLK30",
|
||||
"CLK_FEED_R_CK_BUFG_CASC1",
|
||||
"CLK_FEED_CK_GCLK25",
|
||||
"CLK_PMV_IMUX1_0",
|
||||
"CLK_FEED_CK_BUFG_CASC19",
|
||||
"CLK_PMV_IMUX34_0",
|
||||
"CLK_FEED_WW4A2",
|
||||
"CLK_FEED_R_CK_BUFG_CASC6",
|
||||
"CLK_PMV_LOGIC_OUTS17_0",
|
||||
"CLK_PMV_LOGIC_OUTS9_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC29",
|
||||
"CLK_FEED_SW4END1",
|
||||
"CLK_FEED_LH10",
|
||||
"CLK_FEED_CK_BUFG_CASC0",
|
||||
"CLK_PMV_IMUX21_0",
|
||||
"CLK_FEED_NE4BEG3",
|
||||
"CLK_FEED_R_CK_GCLK26",
|
||||
"CLK_PMV_IMUX41_0",
|
||||
"CLK_PMV_IMUX46_0",
|
||||
"CLK_PMV_IMUX25_0",
|
||||
"CLK_PMV_IMUX39_0",
|
||||
"CLK_FEED_CK_GCLK7",
|
||||
"CLK_FEED_CK_BUFG_CASC23",
|
||||
"CLK_FEED_R_CK_BUFG_CASC16",
|
||||
"CLK_FEED_EE2BEG0",
|
||||
"CLK_FEED_CK_GCLK26",
|
||||
"CLK_FEED_CK_BUFG_CASC15",
|
||||
"CLK_FEED_SW4A1",
|
||||
"CLK_PMVIOB_O",
|
||||
"CLK_FEED_WW4A0",
|
||||
"CLK_PMV_IMUX22_0",
|
||||
"CLK_PMV_LOGIC_OUTS11_0",
|
||||
"CLK_PMV_BYP5_0",
|
||||
"CLK_PMV_LOGIC_OUTS15_0",
|
||||
"CLK_FEED_NE2A3",
|
||||
"CLK_FEED_CK_BUFG_CASC17",
|
||||
"CLK_FEED_CK_GCLK21",
|
||||
"CLK_PMV_LOGIC_OUTS0_0",
|
||||
"CLK_FEED_NE4BEG0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC23",
|
||||
"CLK_FEED_NE4BEG1",
|
||||
"CLK_PMV_LOGIC_OUTS19_0",
|
||||
"CLK_FEED_WW4END0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC12",
|
||||
"CLK_FEED_SE4BEG2",
|
||||
"CLK_FEED_EE2BEG3",
|
||||
"CLK_FEED_R_CK_GCLK7",
|
||||
"CLK_PMV_IMUX4_0",
|
||||
"CLK_FEED_CK_BUFG_CASC30",
|
||||
"CLK_FEED_R_CK_GCLK8",
|
||||
"CLK_FEED_WW4A1",
|
||||
"CLK_FEED_EE4BEG0",
|
||||
"CLK_FEED_WL1END2",
|
||||
"CLK_FEED_WL1END3",
|
||||
"CLK_FEED_WR1END0",
|
||||
"CLK_FEED_WR1END1",
|
||||
"CLK_FEED_WR1END2",
|
||||
"CLK_FEED_CK_BUFG_CASC24",
|
||||
"CLK_FEED_R_CK_GCLK16",
|
||||
"CLK_FEED_R_CK_GCLK10",
|
||||
"CLK_FEED_CK_BUFG_CASC16",
|
||||
"CLK_FEED_R_CK_BUFG_CASC5",
|
||||
"CLK_FEED_CK_GCLK5",
|
||||
"CLK_FEED_R_CK_BUFG_CASC18",
|
||||
"CLK_PMVIOB_A1",
|
||||
"CLK_FEED_NE4BEG2",
|
||||
"CLK_FEED_R_CK_GCLK11",
|
||||
"CLK_FEED_R_CK_GCLK4",
|
||||
"CLK_PMV_LOGIC_OUTS20_0",
|
||||
"CLK_PMV_IMUX12_0",
|
||||
"CLK_PMV_IMUX37_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC7",
|
||||
"CLK_PMV_IMUX18_0",
|
||||
"CLK_FEED_SE4C1",
|
||||
"CLK_FEED_CK_GCLK20",
|
||||
"CLK_PMV_LOGIC_OUTS8_0",
|
||||
"CLK_FEED_NW4END2",
|
||||
"CLK_FEED_EE4BEG2",
|
||||
"CLK_FEED_CK_GCLK30",
|
||||
"CLK_FEED_SE2A1",
|
||||
"CLK_FEED_LH6",
|
||||
"CLK_FEED_CK_GCLK29",
|
||||
"CLK_FEED_R_CK_GCLK27",
|
||||
"CLK_FEED_EE4C1",
|
||||
"CLK_FEED_SW4A0",
|
||||
"CLK_FEED_CK_GCLK9",
|
||||
"CLK_FEED_CK_BUFG_CASC11",
|
||||
"CLK_FEED_CK_GCLK8",
|
||||
"CLK_FEED_R_CK_BUFG_CASC9",
|
||||
"CLK_FEED_R_CK_BUFG_CASC3",
|
||||
"CLK_FEED_WW4END2",
|
||||
"CLK_FEED_CK_GCLK6",
|
||||
"CLK_FEED_EE2A2",
|
||||
"CLK_PMV_LOGIC_OUTS2_0",
|
||||
"CLK_PMV_LOGIC_OUTS14_0",
|
||||
"CLK_FEED_EE4C3",
|
||||
"CLK_FEED_NW2A3",
|
||||
"CLK_PMV_CTRL0_0",
|
||||
"CLK_PMV_LOGIC_OUTS22_0",
|
||||
"CLK_PMV_IMUX0_0",
|
||||
"CLK_FEED_EE2A0",
|
||||
"CLK_PMV_FAN5_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC24",
|
||||
"CLK_PMV_BYP6_0",
|
||||
"CLK_FEED_R_CK_GCLK19",
|
||||
"CLK_FEED_EE2BEG2",
|
||||
"CLK_FEED_R_CK_BUFG_CASC19",
|
||||
"CLK_FEED_WW4END3",
|
||||
"CLK_FEED_CK_GCLK31",
|
||||
"CLK_FEED_SW2A3",
|
||||
"CLK_PMV_IMUX23_0",
|
||||
"CLK_PMV_IMUX19_0",
|
||||
"CLK_PMV_IMUX36_0",
|
||||
"CLK_FEED_SE4C2",
|
||||
"CLK_FEED_EE4C2",
|
||||
"CLK_PMV_IMUX13_0",
|
||||
"CLK_FEED_SE4BEG0",
|
||||
"CLK_PMV_IMUX27_0",
|
||||
"CLK_FEED_LH9",
|
||||
"CLK_FEED_R_CK_GCLK15",
|
||||
"CLK_PMV_IMUX3_0",
|
||||
"CLK_PMV_CTRL1_0",
|
||||
"CLK_FEED_LH5",
|
||||
"CLK_PMV_LOGIC_OUTS13_0",
|
||||
"CLK_FEED_NW4A3",
|
||||
"CLK_PMV_IMUX10_0",
|
||||
"CLK_PMV_IMUX32_0",
|
||||
"CLK_FEED_R_CK_BUFG_CASC4",
|
||||
"CLK_FEED_R_CK_BUFG_CASC21",
|
||||
"CLK_FEED_CK_GCLK0",
|
||||
"CLK_FEED_MONITOR_N",
|
||||
"CLK_FEED_CK_GCLK11",
|
||||
"CLK_FEED_R_CK_BUFG_CASC31",
|
||||
"CLK_FEED_WW2A0",
|
||||
"CLK_FEED_EE4A0",
|
||||
"CLK_FEED_CK_BUFG_CASC9",
|
||||
"CLK_FEED_R_CK_GCLK21",
|
||||
"CLK_FEED_WR1END3",
|
||||
"CLK_FEED_LH8"
|
||||
],
|
||||
"pips": {},
|
||||
"tile_type": "CLK_PMVIOB",
|
||||
"sites": []
|
||||
}
|
||||
"CLK_FEED_WW2A0",
|
||||
"CLK_FEED_WW2A1",
|
||||
"CLK_FEED_WW2A2",
|
||||
"CLK_FEED_WW2A3",
|
||||
"CLK_FEED_WW2END0",
|
||||
"CLK_FEED_WW2END1",
|
||||
"CLK_FEED_WW2END2",
|
||||
"CLK_FEED_WW2END3",
|
||||
"CLK_FEED_WW4A0",
|
||||
"CLK_FEED_WW4A1",
|
||||
"CLK_FEED_WW4A2",
|
||||
"CLK_FEED_WW4A3",
|
||||
"CLK_FEED_WW4B0",
|
||||
"CLK_FEED_WW4B1",
|
||||
"CLK_FEED_WW4B2",
|
||||
"CLK_FEED_WW4B3",
|
||||
"CLK_FEED_WW4C0",
|
||||
"CLK_FEED_WW4C1",
|
||||
"CLK_FEED_WW4C2",
|
||||
"CLK_FEED_WW4C3",
|
||||
"CLK_FEED_WW4END0",
|
||||
"CLK_FEED_WW4END1",
|
||||
"CLK_FEED_WW4END2",
|
||||
"CLK_FEED_WW4END3",
|
||||
"CLK_PMVIOB_A0",
|
||||
"CLK_PMVIOB_A1",
|
||||
"CLK_PMVIOB_EN",
|
||||
"CLK_PMVIOB_O",
|
||||
"CLK_PMVIOB_ODIV2",
|
||||
"CLK_PMVIOB_ODIV4",
|
||||
"CLK_PMV_BYP0_0",
|
||||
"CLK_PMV_BYP1_0",
|
||||
"CLK_PMV_BYP2_0",
|
||||
"CLK_PMV_BYP3_0",
|
||||
"CLK_PMV_BYP4_0",
|
||||
"CLK_PMV_BYP5_0",
|
||||
"CLK_PMV_BYP6_0",
|
||||
"CLK_PMV_BYP7_0",
|
||||
"CLK_PMV_CLK0_0",
|
||||
"CLK_PMV_CLK1_0",
|
||||
"CLK_PMV_CTRL0_0",
|
||||
"CLK_PMV_CTRL1_0",
|
||||
"CLK_PMV_FAN0_0",
|
||||
"CLK_PMV_FAN1_0",
|
||||
"CLK_PMV_FAN2_0",
|
||||
"CLK_PMV_FAN3_0",
|
||||
"CLK_PMV_FAN4_0",
|
||||
"CLK_PMV_FAN5_0",
|
||||
"CLK_PMV_FAN6_0",
|
||||
"CLK_PMV_FAN7_0",
|
||||
"CLK_PMV_IMUX0_0",
|
||||
"CLK_PMV_IMUX10_0",
|
||||
"CLK_PMV_IMUX11_0",
|
||||
"CLK_PMV_IMUX12_0",
|
||||
"CLK_PMV_IMUX13_0",
|
||||
"CLK_PMV_IMUX14_0",
|
||||
"CLK_PMV_IMUX15_0",
|
||||
"CLK_PMV_IMUX16_0",
|
||||
"CLK_PMV_IMUX17_0",
|
||||
"CLK_PMV_IMUX18_0",
|
||||
"CLK_PMV_IMUX19_0",
|
||||
"CLK_PMV_IMUX1_0",
|
||||
"CLK_PMV_IMUX20_0",
|
||||
"CLK_PMV_IMUX21_0",
|
||||
"CLK_PMV_IMUX22_0",
|
||||
"CLK_PMV_IMUX23_0",
|
||||
"CLK_PMV_IMUX24_0",
|
||||
"CLK_PMV_IMUX25_0",
|
||||
"CLK_PMV_IMUX26_0",
|
||||
"CLK_PMV_IMUX27_0",
|
||||
"CLK_PMV_IMUX28_0",
|
||||
"CLK_PMV_IMUX29_0",
|
||||
"CLK_PMV_IMUX2_0",
|
||||
"CLK_PMV_IMUX30_0",
|
||||
"CLK_PMV_IMUX31_0",
|
||||
"CLK_PMV_IMUX32_0",
|
||||
"CLK_PMV_IMUX33_0",
|
||||
"CLK_PMV_IMUX34_0",
|
||||
"CLK_PMV_IMUX35_0",
|
||||
"CLK_PMV_IMUX36_0",
|
||||
"CLK_PMV_IMUX37_0",
|
||||
"CLK_PMV_IMUX38_0",
|
||||
"CLK_PMV_IMUX39_0",
|
||||
"CLK_PMV_IMUX3_0",
|
||||
"CLK_PMV_IMUX40_0",
|
||||
"CLK_PMV_IMUX41_0",
|
||||
"CLK_PMV_IMUX42_0",
|
||||
"CLK_PMV_IMUX43_0",
|
||||
"CLK_PMV_IMUX44_0",
|
||||
"CLK_PMV_IMUX45_0",
|
||||
"CLK_PMV_IMUX46_0",
|
||||
"CLK_PMV_IMUX47_0",
|
||||
"CLK_PMV_IMUX4_0",
|
||||
"CLK_PMV_IMUX5_0",
|
||||
"CLK_PMV_IMUX6_0",
|
||||
"CLK_PMV_IMUX7_0",
|
||||
"CLK_PMV_IMUX8_0",
|
||||
"CLK_PMV_IMUX9_0",
|
||||
"CLK_PMV_LOGIC_OUTS0_0",
|
||||
"CLK_PMV_LOGIC_OUTS10_0",
|
||||
"CLK_PMV_LOGIC_OUTS11_0",
|
||||
"CLK_PMV_LOGIC_OUTS12_0",
|
||||
"CLK_PMV_LOGIC_OUTS13_0",
|
||||
"CLK_PMV_LOGIC_OUTS14_0",
|
||||
"CLK_PMV_LOGIC_OUTS15_0",
|
||||
"CLK_PMV_LOGIC_OUTS16_0",
|
||||
"CLK_PMV_LOGIC_OUTS17_0",
|
||||
"CLK_PMV_LOGIC_OUTS18_0",
|
||||
"CLK_PMV_LOGIC_OUTS19_0",
|
||||
"CLK_PMV_LOGIC_OUTS1_0",
|
||||
"CLK_PMV_LOGIC_OUTS20_0",
|
||||
"CLK_PMV_LOGIC_OUTS21_0",
|
||||
"CLK_PMV_LOGIC_OUTS22_0",
|
||||
"CLK_PMV_LOGIC_OUTS23_0",
|
||||
"CLK_PMV_LOGIC_OUTS2_0",
|
||||
"CLK_PMV_LOGIC_OUTS3_0",
|
||||
"CLK_PMV_LOGIC_OUTS4_0",
|
||||
"CLK_PMV_LOGIC_OUTS5_0",
|
||||
"CLK_PMV_LOGIC_OUTS6_0",
|
||||
"CLK_PMV_LOGIC_OUTS7_0",
|
||||
"CLK_PMV_LOGIC_OUTS8_0",
|
||||
"CLK_PMV_LOGIC_OUTS9_0"
|
||||
]
|
||||
}
|
||||
|
|
@ -1,71 +1,71 @@
|
|||
{
|
||||
"wires": [
|
||||
"CLK_TERM_R_GCLK22",
|
||||
"CLK_TERM_GCLK29",
|
||||
"CLK_TERM_GCLK1",
|
||||
"CLK_TERM_R_GCLK21",
|
||||
"CLK_TERM_R_GCLK18",
|
||||
"CLK_TERM_GCLK16",
|
||||
"CLK_TERM_GCLK27",
|
||||
"CLK_TERM_R_GCLK13",
|
||||
"CLK_TERM_GCLK24",
|
||||
"CLK_TERM_GCLK11",
|
||||
"CLK_TERM_GCLK13",
|
||||
"CLK_TERM_R_GCLK19",
|
||||
"CLK_TERM_R_GCLK3",
|
||||
"CLK_TERM_GCLK5",
|
||||
"CLK_TERM_R_GCLK11",
|
||||
"CLK_TERM_GCLK20",
|
||||
"CLK_TERM_GCLK28",
|
||||
"CLK_TERM_R_GCLK28",
|
||||
"CLK_TERM_GCLK15",
|
||||
"CLK_TERM_GCLK23",
|
||||
"CLK_TERM_GCLK2",
|
||||
"CLK_TERM_R_GCLK14",
|
||||
"CLK_TERM_GCLK3",
|
||||
"CLK_TERM_R_GCLK24",
|
||||
"CLK_TERM_GCLK19",
|
||||
"CLK_TERM_R_GCLK8",
|
||||
"CLK_TERM_R_GCLK0",
|
||||
"CLK_TERM_GCLK10",
|
||||
"CLK_TERM_GCLK22",
|
||||
"CLK_TERM_R_GCLK9",
|
||||
"CLK_TERM_GCLK21",
|
||||
"CLK_TERM_GCLK7",
|
||||
"CLK_TERM_GCLK17",
|
||||
"CLK_TERM_GCLK12",
|
||||
"CLK_TERM_R_GCLK15",
|
||||
"CLK_TERM_R_GCLK6",
|
||||
"CLK_TERM_R_GCLK29",
|
||||
"CLK_TERM_R_GCLK7",
|
||||
"CLK_TERM_R_GCLK1",
|
||||
"CLK_TERM_R_GCLK23",
|
||||
"CLK_TERM_R_GCLK16",
|
||||
"CLK_TERM_R_GCLK4",
|
||||
"CLK_TERM_GCLK26",
|
||||
"CLK_TERM_R_GCLK30",
|
||||
"CLK_TERM_GCLK14",
|
||||
"CLK_TERM_GCLK30",
|
||||
"CLK_TERM_R_GCLK2",
|
||||
"CLK_TERM_R_GCLK25",
|
||||
"CLK_TERM_R_GCLK5",
|
||||
"CLK_TERM_R_GCLK20",
|
||||
"CLK_TERM_GCLK9",
|
||||
"CLK_TERM_GCLK6",
|
||||
"CLK_TERM_GCLK31",
|
||||
"CLK_TERM_R_GCLK10",
|
||||
"CLK_TERM_R_GCLK26",
|
||||
"CLK_TERM_R_GCLK17",
|
||||
"CLK_TERM_GCLK18",
|
||||
"CLK_TERM_R_GCLK12",
|
||||
"CLK_TERM_R_GCLK31",
|
||||
"CLK_TERM_GCLK4",
|
||||
"CLK_TERM_GCLK0",
|
||||
"CLK_TERM_GCLK25",
|
||||
"CLK_TERM_GCLK8",
|
||||
"CLK_TERM_R_GCLK27"
|
||||
],
|
||||
"pips": {},
|
||||
"sites": [],
|
||||
"tile_type": "CLK_TERM",
|
||||
"sites": []
|
||||
}
|
||||
"wires": [
|
||||
"CLK_TERM_GCLK0",
|
||||
"CLK_TERM_GCLK1",
|
||||
"CLK_TERM_GCLK10",
|
||||
"CLK_TERM_GCLK11",
|
||||
"CLK_TERM_GCLK12",
|
||||
"CLK_TERM_GCLK13",
|
||||
"CLK_TERM_GCLK14",
|
||||
"CLK_TERM_GCLK15",
|
||||
"CLK_TERM_GCLK16",
|
||||
"CLK_TERM_GCLK17",
|
||||
"CLK_TERM_GCLK18",
|
||||
"CLK_TERM_GCLK19",
|
||||
"CLK_TERM_GCLK2",
|
||||
"CLK_TERM_GCLK20",
|
||||
"CLK_TERM_GCLK21",
|
||||
"CLK_TERM_GCLK22",
|
||||
"CLK_TERM_GCLK23",
|
||||
"CLK_TERM_GCLK24",
|
||||
"CLK_TERM_GCLK25",
|
||||
"CLK_TERM_GCLK26",
|
||||
"CLK_TERM_GCLK27",
|
||||
"CLK_TERM_GCLK28",
|
||||
"CLK_TERM_GCLK29",
|
||||
"CLK_TERM_GCLK3",
|
||||
"CLK_TERM_GCLK30",
|
||||
"CLK_TERM_GCLK31",
|
||||
"CLK_TERM_GCLK4",
|
||||
"CLK_TERM_GCLK5",
|
||||
"CLK_TERM_GCLK6",
|
||||
"CLK_TERM_GCLK7",
|
||||
"CLK_TERM_GCLK8",
|
||||
"CLK_TERM_GCLK9",
|
||||
"CLK_TERM_R_GCLK0",
|
||||
"CLK_TERM_R_GCLK1",
|
||||
"CLK_TERM_R_GCLK10",
|
||||
"CLK_TERM_R_GCLK11",
|
||||
"CLK_TERM_R_GCLK12",
|
||||
"CLK_TERM_R_GCLK13",
|
||||
"CLK_TERM_R_GCLK14",
|
||||
"CLK_TERM_R_GCLK15",
|
||||
"CLK_TERM_R_GCLK16",
|
||||
"CLK_TERM_R_GCLK17",
|
||||
"CLK_TERM_R_GCLK18",
|
||||
"CLK_TERM_R_GCLK19",
|
||||
"CLK_TERM_R_GCLK2",
|
||||
"CLK_TERM_R_GCLK20",
|
||||
"CLK_TERM_R_GCLK21",
|
||||
"CLK_TERM_R_GCLK22",
|
||||
"CLK_TERM_R_GCLK23",
|
||||
"CLK_TERM_R_GCLK24",
|
||||
"CLK_TERM_R_GCLK25",
|
||||
"CLK_TERM_R_GCLK26",
|
||||
"CLK_TERM_R_GCLK27",
|
||||
"CLK_TERM_R_GCLK28",
|
||||
"CLK_TERM_R_GCLK29",
|
||||
"CLK_TERM_R_GCLK3",
|
||||
"CLK_TERM_R_GCLK30",
|
||||
"CLK_TERM_R_GCLK31",
|
||||
"CLK_TERM_R_GCLK4",
|
||||
"CLK_TERM_R_GCLK5",
|
||||
"CLK_TERM_R_GCLK6",
|
||||
"CLK_TERM_R_GCLK7",
|
||||
"CLK_TERM_R_GCLK8",
|
||||
"CLK_TERM_R_GCLK9"
|
||||
]
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -1,230 +1,230 @@
|
|||
{
|
||||
"wires": [
|
||||
"CMT_PMV_LOGIC_OUTS0",
|
||||
"CMT_PMV_EE4C1",
|
||||
"CMT_PMV_IMUX19",
|
||||
"CMT_PMV_IMUX29",
|
||||
"CMT_PMV_LH2",
|
||||
"CMT_PMV_IMUX11",
|
||||
"L_TERM_INT_PHASER_TO_IO_OCLK1X_90",
|
||||
"CMT_PMV_WW4A2",
|
||||
"CMT_PMV_WW2A1",
|
||||
"CMT_PMV_WW2END2",
|
||||
"L_TERM_INT_PHASER_TO_IO_OCLKDIV",
|
||||
"CMT_PMV_BYP1",
|
||||
"CMT_PMV_WL1END3",
|
||||
"CMT_PMV_EE4A0",
|
||||
"CMT_PMV_NW4END0",
|
||||
"CMT_PMV_LOGIC_OUTS8",
|
||||
"CMT_PMV_LOGIC_OUTS1",
|
||||
"CMT_PMV_WL1END2",
|
||||
"CMT_PMV_SW2A3",
|
||||
"L_TERM_INT_PHASER_TO_IO_OCLK",
|
||||
"CMT_PMV_EE4C2",
|
||||
"CMT_PMV_IMUX39",
|
||||
"CMT_PMV_IMUX43",
|
||||
"CMT_PMV_LOGIC_OUTS14",
|
||||
"CMT_PMV_LOGIC_OUTS13",
|
||||
"CMT_PMV_IMUX0",
|
||||
"CMT_PMV_SW4END3",
|
||||
"CMT_PMV_ER1BEG3",
|
||||
"CMT_PMV_NW2A3",
|
||||
"CMT_PMV_WW4A3",
|
||||
"CMT_PMV_SW4A2",
|
||||
"CMT_PMV_LH10",
|
||||
"CMT_PMV_BYP4",
|
||||
"CMT_PMV_EE2BEG2",
|
||||
"CMT_PMV_EL1BEG3",
|
||||
"CMT_PMV_IMUX8",
|
||||
"CMT_PMV_SE4BEG3",
|
||||
"CMT_PMV_IMUX35",
|
||||
"CMT_PMV_IMUX10",
|
||||
"CMT_PMV_SW4END1",
|
||||
"CMT_PMV_WL1END1",
|
||||
"CMT_PMV_WW2END3",
|
||||
"CMT_PMV_WW4END1",
|
||||
"CMT_PMV_EE4B0",
|
||||
"CMT_PMV_SW4A1",
|
||||
"CMT_PMV_CTRL1",
|
||||
"CMT_PMV_CLK0",
|
||||
"CMT_PMV_IMUX31",
|
||||
"CMT_PMV_EE4A3",
|
||||
"CMT_PMV_SW2A1",
|
||||
"CMT_PMV_WW2END1",
|
||||
"CMT_PMV_NW4END1",
|
||||
"CMT_PMV_LH3",
|
||||
"CMT_PMV_LH7",
|
||||
"CMT_PMV_LOGIC_OUTS2",
|
||||
"CMT_PMV_LH9",
|
||||
"CMT_PMV_SE2A3",
|
||||
"CMT_PMV_IMUX34",
|
||||
"CMT_PMV_NE4C1",
|
||||
"CMT_PMV_FAN0",
|
||||
"CMT_PMV_LH11",
|
||||
"CMT_PMV_WW2A3",
|
||||
"CMT_PMV_IMUX1",
|
||||
"CMT_PMV_IMUX13",
|
||||
"CMT_PMV_EL1BEG2",
|
||||
"CMT_PMV_LOGIC_OUTS17",
|
||||
"CMT_PMV_BYP6",
|
||||
"CMT_PMV_SW4A0",
|
||||
"CMT_PMV_WW4C0",
|
||||
"CMT_PMV_IMUX21",
|
||||
"CMT_PMV_IMUX12",
|
||||
"CMT_PMV_NE4BEG3",
|
||||
"CMT_PMV_LH4",
|
||||
"CMT_PMV_BYP3",
|
||||
"CMT_PMV_IMUX4",
|
||||
"CMT_PMV_IMUX47",
|
||||
"CMT_PMV_NE2A0",
|
||||
"CMT_PMV_WW4A1",
|
||||
"CMT_PMV_LH1",
|
||||
"CMT_PMV_NW4A0",
|
||||
"CMT_PMV_IMUX41",
|
||||
"CMT_PMV_LOGIC_OUTS11",
|
||||
"CMT_PMV_IMUX26",
|
||||
"CMT_PMV_NE4C0",
|
||||
"CMT_PMV_LOGIC_OUTS18",
|
||||
"CMT_PMV_IMUX15",
|
||||
"CMT_PMV_IMUX44",
|
||||
"CMT_PMV_NW4A2",
|
||||
"CMT_PMV_WW4END3",
|
||||
"CMT_PMV_IMUX42",
|
||||
"CMT_PMV_LOGIC_OUTS15",
|
||||
"CMT_PMV_SE4C3",
|
||||
"CMT_PMV_EE4BEG0",
|
||||
"CMT_PMV_SW2A0",
|
||||
"CMT_PMV_IMUX23",
|
||||
"CMT_PMV_BYP0",
|
||||
"CMT_PMV_LOGIC_OUTS21",
|
||||
"CMT_PMV_NE2A3",
|
||||
"CMT_PMV_WW2END0",
|
||||
"CMT_PMV_FAN7",
|
||||
"CMT_PMV_EE2BEG0",
|
||||
"CMT_PMV_NE4BEG0",
|
||||
"CMT_PMV_IMUX27",
|
||||
"CMT_PMV_NW2A2",
|
||||
"CMT_PMV_LOGIC_OUTS12",
|
||||
"CMT_PMV_WW4B1",
|
||||
"CMT_PMV_NE4BEG2",
|
||||
"CMT_PMV_MONITOR_N",
|
||||
"CMT_PMV_WW4B3",
|
||||
"CMT_PMV_LOGIC_OUTS4",
|
||||
"CMT_PMV_WR1END1",
|
||||
"CMT_PMV_LH5",
|
||||
"CMT_PMV_WR1END0",
|
||||
"CMT_PMV_LH12",
|
||||
"CMT_PMV_IMUX46",
|
||||
"CMT_PMV_EE4B3",
|
||||
"CMT_PMV_EE4A2",
|
||||
"CMT_PMV_NE4C2",
|
||||
"CMT_PMV_WW4C1",
|
||||
"CMT_PMV_WW4C3",
|
||||
"CMT_PMV_IMUX9",
|
||||
"CMT_PMV_LOGIC_OUTS7",
|
||||
"CMT_PMV_WW4B2",
|
||||
"CMT_PMV_EE4C0",
|
||||
"CMT_PMV_SE4C2",
|
||||
"CMT_PMV_LH6",
|
||||
"CMT_PMV_SE4BEG1",
|
||||
"CMT_PMV_WW4B0",
|
||||
"CMT_PMV_IMUX24",
|
||||
"CMT_PMV_SW4END0",
|
||||
"CMT_PMV_IMUX14",
|
||||
"CMT_PMV_FAN2",
|
||||
"CMT_PMV_LOGIC_OUTS9",
|
||||
"CMT_PMV_IMUX3",
|
||||
"CMT_PMV_WW4C2",
|
||||
"L_TERM_INT_PHASER_TO_IO_ICLKDIV",
|
||||
"CMT_PMV_WR1END2",
|
||||
"CMT_PMV_IMUX45",
|
||||
"CMT_PMV_EE4A1",
|
||||
"CMT_PMV_IMUX28",
|
||||
"CMT_PMV_NW4END3",
|
||||
"CMT_PMV_EE2A0",
|
||||
"CMT_PMV_EL1BEG0",
|
||||
"CMT_PMV_WW4A0",
|
||||
"CMT_PMV_EE2A3",
|
||||
"CMT_PMV_FAN3",
|
||||
"CMT_PMV_ER1BEG2",
|
||||
"CMT_PMV_IMUX17",
|
||||
"CMT_PMV_LH8",
|
||||
"CMT_PMV_EE2BEG1",
|
||||
"CMT_PMV_EE4C3",
|
||||
"CMT_PMV_NE4C3",
|
||||
"CMT_PMV_FAN5",
|
||||
"CMT_PMV_LOGIC_OUTS3",
|
||||
"CMT_PMV_FAN4",
|
||||
"CMT_PMV_BYP7",
|
||||
"CMT_PMV_SE4BEG2",
|
||||
"CMT_PMV_WR1END3",
|
||||
"CMT_PMV_SW4A3",
|
||||
"CMT_PMV_IMUX16",
|
||||
"CMT_PMV_CLK1",
|
||||
"CMT_PMV_LOGIC_OUTS6",
|
||||
"CMT_PMV_EE2BEG3",
|
||||
"CMT_PMV_NE2A1",
|
||||
"CMT_PMV_SW4END2",
|
||||
"CMT_PMV_SE4BEG0",
|
||||
"CMT_PMV_SW2A2",
|
||||
"CMT_PMV_EE4BEG3",
|
||||
"CMT_PMV_WL1END0",
|
||||
"CMT_PMV_LOGIC_OUTS23",
|
||||
"CMT_PMV_NW2A0",
|
||||
"CMT_PMV_WW2A2",
|
||||
"CMT_PMV_LOGIC_OUTS20",
|
||||
"CMT_PMV_NE4BEG1",
|
||||
"CMT_PMV_LOGIC_OUTS19",
|
||||
"CMT_PMV_IMUX18",
|
||||
"CMT_PMV_EE4BEG2",
|
||||
"CMT_PMV_NW4A3",
|
||||
"CMT_PMV_LOGIC_OUTS16",
|
||||
"CMT_PMV_IMUX33",
|
||||
"CMT_PMV_LOGIC_OUTS10",
|
||||
"CMT_PMV_IMUX30",
|
||||
"CMT_PMV_SE2A2",
|
||||
"CMT_PMV_IMUX37",
|
||||
"CMT_PMV_NW4A1",
|
||||
"CMT_PMV_WW4END0",
|
||||
"L_TERM_INT_PHASER_TO_IO_ICLK",
|
||||
"CMT_PMV_EE2A1",
|
||||
"CMT_PMV_IMUX5",
|
||||
"CMT_PMV_IMUX38",
|
||||
"CMT_PMV_IMUX7",
|
||||
"CMT_PMV_NE2A2",
|
||||
"CMT_PMV_SE2A0",
|
||||
"CMT_PMV_ER1BEG1",
|
||||
"CMT_PMV_EE2A2",
|
||||
"CMT_PMV_IMUX40",
|
||||
"CMT_PMV_NW2A1",
|
||||
"CMT_PMV_IMUX20",
|
||||
"CMT_PMV_WW2A0",
|
||||
"CMT_PMV_SE4C1",
|
||||
"CMT_PMV_MONITOR_P",
|
||||
"CMT_PMV_LOGIC_OUTS5",
|
||||
"CMT_PMV_EE4B1",
|
||||
"CMT_PMV_IMUX22",
|
||||
"CMT_PMV_ER1BEG0",
|
||||
"CMT_PMV_SE2A1",
|
||||
"CMT_PMV_LOGIC_OUTS22",
|
||||
"CMT_PMV_IMUX25",
|
||||
"CMT_PMV_FAN6",
|
||||
"CMT_PMV_CTRL0",
|
||||
"CMT_PMV_BYP5",
|
||||
"CMT_PMV_EE4BEG1",
|
||||
"CMT_PMV_WW4END2",
|
||||
"CMT_PMV_IMUX36",
|
||||
"CMT_PMV_EL1BEG1",
|
||||
"CMT_PMV_NW4END2",
|
||||
"CMT_PMV_IMUX6",
|
||||
"CMT_PMV_IMUX2",
|
||||
"CMT_PMV_EE4B2",
|
||||
"CMT_PMV_IMUX32",
|
||||
"CMT_PMV_BYP2",
|
||||
"CMT_PMV_FAN1",
|
||||
"CMT_PMV_SE4C0"
|
||||
],
|
||||
"pips": {},
|
||||
"sites": [],
|
||||
"tile_type": "CMT_PMV",
|
||||
"sites": []
|
||||
}
|
||||
"wires": [
|
||||
"CMT_PMV_BYP0",
|
||||
"CMT_PMV_BYP1",
|
||||
"CMT_PMV_BYP2",
|
||||
"CMT_PMV_BYP3",
|
||||
"CMT_PMV_BYP4",
|
||||
"CMT_PMV_BYP5",
|
||||
"CMT_PMV_BYP6",
|
||||
"CMT_PMV_BYP7",
|
||||
"CMT_PMV_CLK0",
|
||||
"CMT_PMV_CLK1",
|
||||
"CMT_PMV_CTRL0",
|
||||
"CMT_PMV_CTRL1",
|
||||
"CMT_PMV_EE2A0",
|
||||
"CMT_PMV_EE2A1",
|
||||
"CMT_PMV_EE2A2",
|
||||
"CMT_PMV_EE2A3",
|
||||
"CMT_PMV_EE2BEG0",
|
||||
"CMT_PMV_EE2BEG1",
|
||||
"CMT_PMV_EE2BEG2",
|
||||
"CMT_PMV_EE2BEG3",
|
||||
"CMT_PMV_EE4A0",
|
||||
"CMT_PMV_EE4A1",
|
||||
"CMT_PMV_EE4A2",
|
||||
"CMT_PMV_EE4A3",
|
||||
"CMT_PMV_EE4B0",
|
||||
"CMT_PMV_EE4B1",
|
||||
"CMT_PMV_EE4B2",
|
||||
"CMT_PMV_EE4B3",
|
||||
"CMT_PMV_EE4BEG0",
|
||||
"CMT_PMV_EE4BEG1",
|
||||
"CMT_PMV_EE4BEG2",
|
||||
"CMT_PMV_EE4BEG3",
|
||||
"CMT_PMV_EE4C0",
|
||||
"CMT_PMV_EE4C1",
|
||||
"CMT_PMV_EE4C2",
|
||||
"CMT_PMV_EE4C3",
|
||||
"CMT_PMV_EL1BEG0",
|
||||
"CMT_PMV_EL1BEG1",
|
||||
"CMT_PMV_EL1BEG2",
|
||||
"CMT_PMV_EL1BEG3",
|
||||
"CMT_PMV_ER1BEG0",
|
||||
"CMT_PMV_ER1BEG1",
|
||||
"CMT_PMV_ER1BEG2",
|
||||
"CMT_PMV_ER1BEG3",
|
||||
"CMT_PMV_FAN0",
|
||||
"CMT_PMV_FAN1",
|
||||
"CMT_PMV_FAN2",
|
||||
"CMT_PMV_FAN3",
|
||||
"CMT_PMV_FAN4",
|
||||
"CMT_PMV_FAN5",
|
||||
"CMT_PMV_FAN6",
|
||||
"CMT_PMV_FAN7",
|
||||
"CMT_PMV_IMUX0",
|
||||
"CMT_PMV_IMUX1",
|
||||
"CMT_PMV_IMUX10",
|
||||
"CMT_PMV_IMUX11",
|
||||
"CMT_PMV_IMUX12",
|
||||
"CMT_PMV_IMUX13",
|
||||
"CMT_PMV_IMUX14",
|
||||
"CMT_PMV_IMUX15",
|
||||
"CMT_PMV_IMUX16",
|
||||
"CMT_PMV_IMUX17",
|
||||
"CMT_PMV_IMUX18",
|
||||
"CMT_PMV_IMUX19",
|
||||
"CMT_PMV_IMUX2",
|
||||
"CMT_PMV_IMUX20",
|
||||
"CMT_PMV_IMUX21",
|
||||
"CMT_PMV_IMUX22",
|
||||
"CMT_PMV_IMUX23",
|
||||
"CMT_PMV_IMUX24",
|
||||
"CMT_PMV_IMUX25",
|
||||
"CMT_PMV_IMUX26",
|
||||
"CMT_PMV_IMUX27",
|
||||
"CMT_PMV_IMUX28",
|
||||
"CMT_PMV_IMUX29",
|
||||
"CMT_PMV_IMUX3",
|
||||
"CMT_PMV_IMUX30",
|
||||
"CMT_PMV_IMUX31",
|
||||
"CMT_PMV_IMUX32",
|
||||
"CMT_PMV_IMUX33",
|
||||
"CMT_PMV_IMUX34",
|
||||
"CMT_PMV_IMUX35",
|
||||
"CMT_PMV_IMUX36",
|
||||
"CMT_PMV_IMUX37",
|
||||
"CMT_PMV_IMUX38",
|
||||
"CMT_PMV_IMUX39",
|
||||
"CMT_PMV_IMUX4",
|
||||
"CMT_PMV_IMUX40",
|
||||
"CMT_PMV_IMUX41",
|
||||
"CMT_PMV_IMUX42",
|
||||
"CMT_PMV_IMUX43",
|
||||
"CMT_PMV_IMUX44",
|
||||
"CMT_PMV_IMUX45",
|
||||
"CMT_PMV_IMUX46",
|
||||
"CMT_PMV_IMUX47",
|
||||
"CMT_PMV_IMUX5",
|
||||
"CMT_PMV_IMUX6",
|
||||
"CMT_PMV_IMUX7",
|
||||
"CMT_PMV_IMUX8",
|
||||
"CMT_PMV_IMUX9",
|
||||
"CMT_PMV_LH1",
|
||||
"CMT_PMV_LH10",
|
||||
"CMT_PMV_LH11",
|
||||
"CMT_PMV_LH12",
|
||||
"CMT_PMV_LH2",
|
||||
"CMT_PMV_LH3",
|
||||
"CMT_PMV_LH4",
|
||||
"CMT_PMV_LH5",
|
||||
"CMT_PMV_LH6",
|
||||
"CMT_PMV_LH7",
|
||||
"CMT_PMV_LH8",
|
||||
"CMT_PMV_LH9",
|
||||
"CMT_PMV_LOGIC_OUTS0",
|
||||
"CMT_PMV_LOGIC_OUTS1",
|
||||
"CMT_PMV_LOGIC_OUTS10",
|
||||
"CMT_PMV_LOGIC_OUTS11",
|
||||
"CMT_PMV_LOGIC_OUTS12",
|
||||
"CMT_PMV_LOGIC_OUTS13",
|
||||
"CMT_PMV_LOGIC_OUTS14",
|
||||
"CMT_PMV_LOGIC_OUTS15",
|
||||
"CMT_PMV_LOGIC_OUTS16",
|
||||
"CMT_PMV_LOGIC_OUTS17",
|
||||
"CMT_PMV_LOGIC_OUTS18",
|
||||
"CMT_PMV_LOGIC_OUTS19",
|
||||
"CMT_PMV_LOGIC_OUTS2",
|
||||
"CMT_PMV_LOGIC_OUTS20",
|
||||
"CMT_PMV_LOGIC_OUTS21",
|
||||
"CMT_PMV_LOGIC_OUTS22",
|
||||
"CMT_PMV_LOGIC_OUTS23",
|
||||
"CMT_PMV_LOGIC_OUTS3",
|
||||
"CMT_PMV_LOGIC_OUTS4",
|
||||
"CMT_PMV_LOGIC_OUTS5",
|
||||
"CMT_PMV_LOGIC_OUTS6",
|
||||
"CMT_PMV_LOGIC_OUTS7",
|
||||
"CMT_PMV_LOGIC_OUTS8",
|
||||
"CMT_PMV_LOGIC_OUTS9",
|
||||
"CMT_PMV_MONITOR_N",
|
||||
"CMT_PMV_MONITOR_P",
|
||||
"CMT_PMV_NE2A0",
|
||||
"CMT_PMV_NE2A1",
|
||||
"CMT_PMV_NE2A2",
|
||||
"CMT_PMV_NE2A3",
|
||||
"CMT_PMV_NE4BEG0",
|
||||
"CMT_PMV_NE4BEG1",
|
||||
"CMT_PMV_NE4BEG2",
|
||||
"CMT_PMV_NE4BEG3",
|
||||
"CMT_PMV_NE4C0",
|
||||
"CMT_PMV_NE4C1",
|
||||
"CMT_PMV_NE4C2",
|
||||
"CMT_PMV_NE4C3",
|
||||
"CMT_PMV_NW2A0",
|
||||
"CMT_PMV_NW2A1",
|
||||
"CMT_PMV_NW2A2",
|
||||
"CMT_PMV_NW2A3",
|
||||
"CMT_PMV_NW4A0",
|
||||
"CMT_PMV_NW4A1",
|
||||
"CMT_PMV_NW4A2",
|
||||
"CMT_PMV_NW4A3",
|
||||
"CMT_PMV_NW4END0",
|
||||
"CMT_PMV_NW4END1",
|
||||
"CMT_PMV_NW4END2",
|
||||
"CMT_PMV_NW4END3",
|
||||
"CMT_PMV_SE2A0",
|
||||
"CMT_PMV_SE2A1",
|
||||
"CMT_PMV_SE2A2",
|
||||
"CMT_PMV_SE2A3",
|
||||
"CMT_PMV_SE4BEG0",
|
||||
"CMT_PMV_SE4BEG1",
|
||||
"CMT_PMV_SE4BEG2",
|
||||
"CMT_PMV_SE4BEG3",
|
||||
"CMT_PMV_SE4C0",
|
||||
"CMT_PMV_SE4C1",
|
||||
"CMT_PMV_SE4C2",
|
||||
"CMT_PMV_SE4C3",
|
||||
"CMT_PMV_SW2A0",
|
||||
"CMT_PMV_SW2A1",
|
||||
"CMT_PMV_SW2A2",
|
||||
"CMT_PMV_SW2A3",
|
||||
"CMT_PMV_SW4A0",
|
||||
"CMT_PMV_SW4A1",
|
||||
"CMT_PMV_SW4A2",
|
||||
"CMT_PMV_SW4A3",
|
||||
"CMT_PMV_SW4END0",
|
||||
"CMT_PMV_SW4END1",
|
||||
"CMT_PMV_SW4END2",
|
||||
"CMT_PMV_SW4END3",
|
||||
"CMT_PMV_WL1END0",
|
||||
"CMT_PMV_WL1END1",
|
||||
"CMT_PMV_WL1END2",
|
||||
"CMT_PMV_WL1END3",
|
||||
"CMT_PMV_WR1END0",
|
||||
"CMT_PMV_WR1END1",
|
||||
"CMT_PMV_WR1END2",
|
||||
"CMT_PMV_WR1END3",
|
||||
"CMT_PMV_WW2A0",
|
||||
"CMT_PMV_WW2A1",
|
||||
"CMT_PMV_WW2A2",
|
||||
"CMT_PMV_WW2A3",
|
||||
"CMT_PMV_WW2END0",
|
||||
"CMT_PMV_WW2END1",
|
||||
"CMT_PMV_WW2END2",
|
||||
"CMT_PMV_WW2END3",
|
||||
"CMT_PMV_WW4A0",
|
||||
"CMT_PMV_WW4A1",
|
||||
"CMT_PMV_WW4A2",
|
||||
"CMT_PMV_WW4A3",
|
||||
"CMT_PMV_WW4B0",
|
||||
"CMT_PMV_WW4B1",
|
||||
"CMT_PMV_WW4B2",
|
||||
"CMT_PMV_WW4B3",
|
||||
"CMT_PMV_WW4C0",
|
||||
"CMT_PMV_WW4C1",
|
||||
"CMT_PMV_WW4C2",
|
||||
"CMT_PMV_WW4C3",
|
||||
"CMT_PMV_WW4END0",
|
||||
"CMT_PMV_WW4END1",
|
||||
"CMT_PMV_WW4END2",
|
||||
"CMT_PMV_WW4END3",
|
||||
"L_TERM_INT_PHASER_TO_IO_ICLK",
|
||||
"L_TERM_INT_PHASER_TO_IO_ICLKDIV",
|
||||
"L_TERM_INT_PHASER_TO_IO_OCLK",
|
||||
"L_TERM_INT_PHASER_TO_IO_OCLK1X_90",
|
||||
"L_TERM_INT_PHASER_TO_IO_OCLKDIV"
|
||||
]
|
||||
}
|
||||
|
|
@ -1,230 +1,230 @@
|
|||
{
|
||||
"wires": [
|
||||
"CMT_PMV_LOGIC_OUTS0",
|
||||
"CMT_PMV_EE4C1",
|
||||
"CMT_PMV_IMUX19",
|
||||
"CMT_PMV_IMUX29",
|
||||
"CMT_PMV_LH2",
|
||||
"CMT_PMV_IMUX11",
|
||||
"L_TERM_INT_PHASER_TO_IO_OCLK1X_90",
|
||||
"CMT_PMV_WW4A2",
|
||||
"CMT_PMV_WW2A1",
|
||||
"CMT_PMV_WW2END2",
|
||||
"L_TERM_INT_PHASER_TO_IO_OCLKDIV",
|
||||
"CMT_PMV_BYP1",
|
||||
"CMT_PMV_WL1END3",
|
||||
"CMT_PMV_EE4A0",
|
||||
"CMT_PMV_NW4END0",
|
||||
"CMT_PMV_LOGIC_OUTS8",
|
||||
"CMT_PMV_LOGIC_OUTS1",
|
||||
"CMT_PMV_WL1END2",
|
||||
"CMT_PMV_SW2A3",
|
||||
"L_TERM_INT_PHASER_TO_IO_OCLK",
|
||||
"CMT_PMV_EE4C2",
|
||||
"CMT_PMV_IMUX39",
|
||||
"CMT_PMV_IMUX43",
|
||||
"CMT_PMV_LOGIC_OUTS14",
|
||||
"CMT_PMV_LOGIC_OUTS13",
|
||||
"CMT_PMV_IMUX0",
|
||||
"CMT_PMV_SW4END3",
|
||||
"CMT_PMV_ER1BEG3",
|
||||
"CMT_PMV_NW2A3",
|
||||
"CMT_PMV_WW4A3",
|
||||
"CMT_PMV_SW4A2",
|
||||
"CMT_PMV_LH10",
|
||||
"CMT_PMV_BYP4",
|
||||
"CMT_PMV_EE2BEG2",
|
||||
"CMT_PMV_EL1BEG3",
|
||||
"CMT_PMV_IMUX8",
|
||||
"CMT_PMV_SE4BEG3",
|
||||
"CMT_PMV_IMUX35",
|
||||
"CMT_PMV_IMUX10",
|
||||
"CMT_PMV_SW4END1",
|
||||
"CMT_PMV_WL1END1",
|
||||
"CMT_PMV_WW2END3",
|
||||
"CMT_PMV_WW4END1",
|
||||
"CMT_PMV_EE4B0",
|
||||
"CMT_PMV_SW4A1",
|
||||
"CMT_PMV_CTRL1",
|
||||
"CMT_PMV_CLK0",
|
||||
"CMT_PMV_IMUX31",
|
||||
"CMT_PMV_EE4A3",
|
||||
"CMT_PMV_SW2A1",
|
||||
"CMT_PMV_WW2END1",
|
||||
"CMT_PMV_NW4END1",
|
||||
"CMT_PMV_LH3",
|
||||
"CMT_PMV_LH7",
|
||||
"CMT_PMV_LOGIC_OUTS2",
|
||||
"CMT_PMV_LH9",
|
||||
"CMT_PMV_SE2A3",
|
||||
"CMT_PMV_IMUX34",
|
||||
"CMT_PMV_NE4C1",
|
||||
"CMT_PMV_FAN0",
|
||||
"CMT_PMV_LH11",
|
||||
"CMT_PMV_WW2A3",
|
||||
"CMT_PMV_IMUX1",
|
||||
"CMT_PMV_IMUX13",
|
||||
"CMT_PMV_EL1BEG2",
|
||||
"CMT_PMV_LOGIC_OUTS17",
|
||||
"CMT_PMV_BYP6",
|
||||
"CMT_PMV_SW4A0",
|
||||
"CMT_PMV_WW4C0",
|
||||
"CMT_PMV_IMUX21",
|
||||
"CMT_PMV_IMUX12",
|
||||
"CMT_PMV_NE4BEG3",
|
||||
"CMT_PMV_LH4",
|
||||
"CMT_PMV_BYP3",
|
||||
"CMT_PMV_IMUX4",
|
||||
"CMT_PMV_IMUX47",
|
||||
"CMT_PMV_NE2A0",
|
||||
"CMT_PMV_WW4A1",
|
||||
"CMT_PMV_LH1",
|
||||
"CMT_PMV_NW4A0",
|
||||
"CMT_PMV_IMUX41",
|
||||
"CMT_PMV_LOGIC_OUTS11",
|
||||
"CMT_PMV_IMUX26",
|
||||
"CMT_PMV_NE4C0",
|
||||
"CMT_PMV_LOGIC_OUTS18",
|
||||
"CMT_PMV_IMUX15",
|
||||
"CMT_PMV_IMUX44",
|
||||
"CMT_PMV_NW4A2",
|
||||
"CMT_PMV_WW4END3",
|
||||
"CMT_PMV_IMUX42",
|
||||
"CMT_PMV_LOGIC_OUTS15",
|
||||
"CMT_PMV_SE4C3",
|
||||
"CMT_PMV_EE4BEG0",
|
||||
"CMT_PMV_SW2A0",
|
||||
"CMT_PMV_IMUX23",
|
||||
"CMT_PMV_BYP0",
|
||||
"CMT_PMV_LOGIC_OUTS21",
|
||||
"CMT_PMV_NE2A3",
|
||||
"CMT_PMV_WW2END0",
|
||||
"CMT_PMV_FAN7",
|
||||
"CMT_PMV_EE2BEG0",
|
||||
"CMT_PMV_NE4BEG0",
|
||||
"CMT_PMV_IMUX27",
|
||||
"CMT_PMV_NW2A2",
|
||||
"CMT_PMV_LOGIC_OUTS12",
|
||||
"CMT_PMV_WW4B1",
|
||||
"CMT_PMV_NE4BEG2",
|
||||
"CMT_PMV_MONITOR_N",
|
||||
"CMT_PMV_WW4B3",
|
||||
"CMT_PMV_LOGIC_OUTS4",
|
||||
"CMT_PMV_WR1END1",
|
||||
"CMT_PMV_LH5",
|
||||
"CMT_PMV_WR1END0",
|
||||
"CMT_PMV_LH12",
|
||||
"CMT_PMV_IMUX46",
|
||||
"CMT_PMV_EE4B3",
|
||||
"CMT_PMV_EE4A2",
|
||||
"CMT_PMV_NE4C2",
|
||||
"CMT_PMV_WW4C1",
|
||||
"CMT_PMV_WW4C3",
|
||||
"CMT_PMV_IMUX9",
|
||||
"CMT_PMV_LOGIC_OUTS7",
|
||||
"CMT_PMV_WW4B2",
|
||||
"CMT_PMV_EE4C0",
|
||||
"CMT_PMV_SE4C2",
|
||||
"CMT_PMV_LH6",
|
||||
"CMT_PMV_SE4BEG1",
|
||||
"CMT_PMV_WW4B0",
|
||||
"CMT_PMV_IMUX24",
|
||||
"CMT_PMV_SW4END0",
|
||||
"CMT_PMV_IMUX14",
|
||||
"CMT_PMV_FAN2",
|
||||
"CMT_PMV_LOGIC_OUTS9",
|
||||
"CMT_PMV_IMUX3",
|
||||
"CMT_PMV_WW4C2",
|
||||
"L_TERM_INT_PHASER_TO_IO_ICLKDIV",
|
||||
"CMT_PMV_WR1END2",
|
||||
"CMT_PMV_IMUX45",
|
||||
"CMT_PMV_EE4A1",
|
||||
"CMT_PMV_IMUX28",
|
||||
"CMT_PMV_NW4END3",
|
||||
"CMT_PMV_EE2A0",
|
||||
"CMT_PMV_EL1BEG0",
|
||||
"CMT_PMV_WW4A0",
|
||||
"CMT_PMV_EE2A3",
|
||||
"CMT_PMV_FAN3",
|
||||
"CMT_PMV_ER1BEG2",
|
||||
"CMT_PMV_IMUX17",
|
||||
"CMT_PMV_LH8",
|
||||
"CMT_PMV_EE2BEG1",
|
||||
"CMT_PMV_EE4C3",
|
||||
"CMT_PMV_NE4C3",
|
||||
"CMT_PMV_FAN5",
|
||||
"CMT_PMV_LOGIC_OUTS3",
|
||||
"CMT_PMV_FAN4",
|
||||
"CMT_PMV_BYP7",
|
||||
"CMT_PMV_SE4BEG2",
|
||||
"CMT_PMV_WR1END3",
|
||||
"CMT_PMV_SW4A3",
|
||||
"CMT_PMV_IMUX16",
|
||||
"CMT_PMV_CLK1",
|
||||
"CMT_PMV_LOGIC_OUTS6",
|
||||
"CMT_PMV_EE2BEG3",
|
||||
"CMT_PMV_NE2A1",
|
||||
"CMT_PMV_SW4END2",
|
||||
"CMT_PMV_SE4BEG0",
|
||||
"CMT_PMV_SW2A2",
|
||||
"CMT_PMV_EE4BEG3",
|
||||
"CMT_PMV_WL1END0",
|
||||
"CMT_PMV_LOGIC_OUTS23",
|
||||
"CMT_PMV_NW2A0",
|
||||
"CMT_PMV_WW2A2",
|
||||
"CMT_PMV_LOGIC_OUTS20",
|
||||
"CMT_PMV_NE4BEG1",
|
||||
"CMT_PMV_LOGIC_OUTS19",
|
||||
"CMT_PMV_IMUX18",
|
||||
"CMT_PMV_EE4BEG2",
|
||||
"CMT_PMV_NW4A3",
|
||||
"CMT_PMV_LOGIC_OUTS16",
|
||||
"CMT_PMV_IMUX33",
|
||||
"CMT_PMV_LOGIC_OUTS10",
|
||||
"CMT_PMV_IMUX30",
|
||||
"CMT_PMV_SE2A2",
|
||||
"CMT_PMV_IMUX37",
|
||||
"CMT_PMV_NW4A1",
|
||||
"CMT_PMV_WW4END0",
|
||||
"L_TERM_INT_PHASER_TO_IO_ICLK",
|
||||
"CMT_PMV_EE2A1",
|
||||
"CMT_PMV_IMUX5",
|
||||
"CMT_PMV_IMUX38",
|
||||
"CMT_PMV_IMUX7",
|
||||
"CMT_PMV_NE2A2",
|
||||
"CMT_PMV_SE2A0",
|
||||
"CMT_PMV_ER1BEG1",
|
||||
"CMT_PMV_EE2A2",
|
||||
"CMT_PMV_IMUX40",
|
||||
"CMT_PMV_NW2A1",
|
||||
"CMT_PMV_IMUX20",
|
||||
"CMT_PMV_WW2A0",
|
||||
"CMT_PMV_SE4C1",
|
||||
"CMT_PMV_MONITOR_P",
|
||||
"CMT_PMV_LOGIC_OUTS5",
|
||||
"CMT_PMV_EE4B1",
|
||||
"CMT_PMV_IMUX22",
|
||||
"CMT_PMV_ER1BEG0",
|
||||
"CMT_PMV_SE2A1",
|
||||
"CMT_PMV_LOGIC_OUTS22",
|
||||
"CMT_PMV_IMUX25",
|
||||
"CMT_PMV_FAN6",
|
||||
"CMT_PMV_CTRL0",
|
||||
"CMT_PMV_BYP5",
|
||||
"CMT_PMV_EE4BEG1",
|
||||
"CMT_PMV_WW4END2",
|
||||
"CMT_PMV_IMUX36",
|
||||
"CMT_PMV_EL1BEG1",
|
||||
"CMT_PMV_NW4END2",
|
||||
"CMT_PMV_IMUX6",
|
||||
"CMT_PMV_IMUX2",
|
||||
"CMT_PMV_EE4B2",
|
||||
"CMT_PMV_IMUX32",
|
||||
"CMT_PMV_BYP2",
|
||||
"CMT_PMV_FAN1",
|
||||
"CMT_PMV_SE4C0"
|
||||
],
|
||||
"pips": {},
|
||||
"sites": [],
|
||||
"tile_type": "CMT_PMV_L",
|
||||
"sites": []
|
||||
}
|
||||
"wires": [
|
||||
"CMT_PMV_BYP0",
|
||||
"CMT_PMV_BYP1",
|
||||
"CMT_PMV_BYP2",
|
||||
"CMT_PMV_BYP3",
|
||||
"CMT_PMV_BYP4",
|
||||
"CMT_PMV_BYP5",
|
||||
"CMT_PMV_BYP6",
|
||||
"CMT_PMV_BYP7",
|
||||
"CMT_PMV_CLK0",
|
||||
"CMT_PMV_CLK1",
|
||||
"CMT_PMV_CTRL0",
|
||||
"CMT_PMV_CTRL1",
|
||||
"CMT_PMV_EE2A0",
|
||||
"CMT_PMV_EE2A1",
|
||||
"CMT_PMV_EE2A2",
|
||||
"CMT_PMV_EE2A3",
|
||||
"CMT_PMV_EE2BEG0",
|
||||
"CMT_PMV_EE2BEG1",
|
||||
"CMT_PMV_EE2BEG2",
|
||||
"CMT_PMV_EE2BEG3",
|
||||
"CMT_PMV_EE4A0",
|
||||
"CMT_PMV_EE4A1",
|
||||
"CMT_PMV_EE4A2",
|
||||
"CMT_PMV_EE4A3",
|
||||
"CMT_PMV_EE4B0",
|
||||
"CMT_PMV_EE4B1",
|
||||
"CMT_PMV_EE4B2",
|
||||
"CMT_PMV_EE4B3",
|
||||
"CMT_PMV_EE4BEG0",
|
||||
"CMT_PMV_EE4BEG1",
|
||||
"CMT_PMV_EE4BEG2",
|
||||
"CMT_PMV_EE4BEG3",
|
||||
"CMT_PMV_EE4C0",
|
||||
"CMT_PMV_EE4C1",
|
||||
"CMT_PMV_EE4C2",
|
||||
"CMT_PMV_EE4C3",
|
||||
"CMT_PMV_EL1BEG0",
|
||||
"CMT_PMV_EL1BEG1",
|
||||
"CMT_PMV_EL1BEG2",
|
||||
"CMT_PMV_EL1BEG3",
|
||||
"CMT_PMV_ER1BEG0",
|
||||
"CMT_PMV_ER1BEG1",
|
||||
"CMT_PMV_ER1BEG2",
|
||||
"CMT_PMV_ER1BEG3",
|
||||
"CMT_PMV_FAN0",
|
||||
"CMT_PMV_FAN1",
|
||||
"CMT_PMV_FAN2",
|
||||
"CMT_PMV_FAN3",
|
||||
"CMT_PMV_FAN4",
|
||||
"CMT_PMV_FAN5",
|
||||
"CMT_PMV_FAN6",
|
||||
"CMT_PMV_FAN7",
|
||||
"CMT_PMV_IMUX0",
|
||||
"CMT_PMV_IMUX1",
|
||||
"CMT_PMV_IMUX10",
|
||||
"CMT_PMV_IMUX11",
|
||||
"CMT_PMV_IMUX12",
|
||||
"CMT_PMV_IMUX13",
|
||||
"CMT_PMV_IMUX14",
|
||||
"CMT_PMV_IMUX15",
|
||||
"CMT_PMV_IMUX16",
|
||||
"CMT_PMV_IMUX17",
|
||||
"CMT_PMV_IMUX18",
|
||||
"CMT_PMV_IMUX19",
|
||||
"CMT_PMV_IMUX2",
|
||||
"CMT_PMV_IMUX20",
|
||||
"CMT_PMV_IMUX21",
|
||||
"CMT_PMV_IMUX22",
|
||||
"CMT_PMV_IMUX23",
|
||||
"CMT_PMV_IMUX24",
|
||||
"CMT_PMV_IMUX25",
|
||||
"CMT_PMV_IMUX26",
|
||||
"CMT_PMV_IMUX27",
|
||||
"CMT_PMV_IMUX28",
|
||||
"CMT_PMV_IMUX29",
|
||||
"CMT_PMV_IMUX3",
|
||||
"CMT_PMV_IMUX30",
|
||||
"CMT_PMV_IMUX31",
|
||||
"CMT_PMV_IMUX32",
|
||||
"CMT_PMV_IMUX33",
|
||||
"CMT_PMV_IMUX34",
|
||||
"CMT_PMV_IMUX35",
|
||||
"CMT_PMV_IMUX36",
|
||||
"CMT_PMV_IMUX37",
|
||||
"CMT_PMV_IMUX38",
|
||||
"CMT_PMV_IMUX39",
|
||||
"CMT_PMV_IMUX4",
|
||||
"CMT_PMV_IMUX40",
|
||||
"CMT_PMV_IMUX41",
|
||||
"CMT_PMV_IMUX42",
|
||||
"CMT_PMV_IMUX43",
|
||||
"CMT_PMV_IMUX44",
|
||||
"CMT_PMV_IMUX45",
|
||||
"CMT_PMV_IMUX46",
|
||||
"CMT_PMV_IMUX47",
|
||||
"CMT_PMV_IMUX5",
|
||||
"CMT_PMV_IMUX6",
|
||||
"CMT_PMV_IMUX7",
|
||||
"CMT_PMV_IMUX8",
|
||||
"CMT_PMV_IMUX9",
|
||||
"CMT_PMV_LH1",
|
||||
"CMT_PMV_LH10",
|
||||
"CMT_PMV_LH11",
|
||||
"CMT_PMV_LH12",
|
||||
"CMT_PMV_LH2",
|
||||
"CMT_PMV_LH3",
|
||||
"CMT_PMV_LH4",
|
||||
"CMT_PMV_LH5",
|
||||
"CMT_PMV_LH6",
|
||||
"CMT_PMV_LH7",
|
||||
"CMT_PMV_LH8",
|
||||
"CMT_PMV_LH9",
|
||||
"CMT_PMV_LOGIC_OUTS0",
|
||||
"CMT_PMV_LOGIC_OUTS1",
|
||||
"CMT_PMV_LOGIC_OUTS10",
|
||||
"CMT_PMV_LOGIC_OUTS11",
|
||||
"CMT_PMV_LOGIC_OUTS12",
|
||||
"CMT_PMV_LOGIC_OUTS13",
|
||||
"CMT_PMV_LOGIC_OUTS14",
|
||||
"CMT_PMV_LOGIC_OUTS15",
|
||||
"CMT_PMV_LOGIC_OUTS16",
|
||||
"CMT_PMV_LOGIC_OUTS17",
|
||||
"CMT_PMV_LOGIC_OUTS18",
|
||||
"CMT_PMV_LOGIC_OUTS19",
|
||||
"CMT_PMV_LOGIC_OUTS2",
|
||||
"CMT_PMV_LOGIC_OUTS20",
|
||||
"CMT_PMV_LOGIC_OUTS21",
|
||||
"CMT_PMV_LOGIC_OUTS22",
|
||||
"CMT_PMV_LOGIC_OUTS23",
|
||||
"CMT_PMV_LOGIC_OUTS3",
|
||||
"CMT_PMV_LOGIC_OUTS4",
|
||||
"CMT_PMV_LOGIC_OUTS5",
|
||||
"CMT_PMV_LOGIC_OUTS6",
|
||||
"CMT_PMV_LOGIC_OUTS7",
|
||||
"CMT_PMV_LOGIC_OUTS8",
|
||||
"CMT_PMV_LOGIC_OUTS9",
|
||||
"CMT_PMV_MONITOR_N",
|
||||
"CMT_PMV_MONITOR_P",
|
||||
"CMT_PMV_NE2A0",
|
||||
"CMT_PMV_NE2A1",
|
||||
"CMT_PMV_NE2A2",
|
||||
"CMT_PMV_NE2A3",
|
||||
"CMT_PMV_NE4BEG0",
|
||||
"CMT_PMV_NE4BEG1",
|
||||
"CMT_PMV_NE4BEG2",
|
||||
"CMT_PMV_NE4BEG3",
|
||||
"CMT_PMV_NE4C0",
|
||||
"CMT_PMV_NE4C1",
|
||||
"CMT_PMV_NE4C2",
|
||||
"CMT_PMV_NE4C3",
|
||||
"CMT_PMV_NW2A0",
|
||||
"CMT_PMV_NW2A1",
|
||||
"CMT_PMV_NW2A2",
|
||||
"CMT_PMV_NW2A3",
|
||||
"CMT_PMV_NW4A0",
|
||||
"CMT_PMV_NW4A1",
|
||||
"CMT_PMV_NW4A2",
|
||||
"CMT_PMV_NW4A3",
|
||||
"CMT_PMV_NW4END0",
|
||||
"CMT_PMV_NW4END1",
|
||||
"CMT_PMV_NW4END2",
|
||||
"CMT_PMV_NW4END3",
|
||||
"CMT_PMV_SE2A0",
|
||||
"CMT_PMV_SE2A1",
|
||||
"CMT_PMV_SE2A2",
|
||||
"CMT_PMV_SE2A3",
|
||||
"CMT_PMV_SE4BEG0",
|
||||
"CMT_PMV_SE4BEG1",
|
||||
"CMT_PMV_SE4BEG2",
|
||||
"CMT_PMV_SE4BEG3",
|
||||
"CMT_PMV_SE4C0",
|
||||
"CMT_PMV_SE4C1",
|
||||
"CMT_PMV_SE4C2",
|
||||
"CMT_PMV_SE4C3",
|
||||
"CMT_PMV_SW2A0",
|
||||
"CMT_PMV_SW2A1",
|
||||
"CMT_PMV_SW2A2",
|
||||
"CMT_PMV_SW2A3",
|
||||
"CMT_PMV_SW4A0",
|
||||
"CMT_PMV_SW4A1",
|
||||
"CMT_PMV_SW4A2",
|
||||
"CMT_PMV_SW4A3",
|
||||
"CMT_PMV_SW4END0",
|
||||
"CMT_PMV_SW4END1",
|
||||
"CMT_PMV_SW4END2",
|
||||
"CMT_PMV_SW4END3",
|
||||
"CMT_PMV_WL1END0",
|
||||
"CMT_PMV_WL1END1",
|
||||
"CMT_PMV_WL1END2",
|
||||
"CMT_PMV_WL1END3",
|
||||
"CMT_PMV_WR1END0",
|
||||
"CMT_PMV_WR1END1",
|
||||
"CMT_PMV_WR1END2",
|
||||
"CMT_PMV_WR1END3",
|
||||
"CMT_PMV_WW2A0",
|
||||
"CMT_PMV_WW2A1",
|
||||
"CMT_PMV_WW2A2",
|
||||
"CMT_PMV_WW2A3",
|
||||
"CMT_PMV_WW2END0",
|
||||
"CMT_PMV_WW2END1",
|
||||
"CMT_PMV_WW2END2",
|
||||
"CMT_PMV_WW2END3",
|
||||
"CMT_PMV_WW4A0",
|
||||
"CMT_PMV_WW4A1",
|
||||
"CMT_PMV_WW4A2",
|
||||
"CMT_PMV_WW4A3",
|
||||
"CMT_PMV_WW4B0",
|
||||
"CMT_PMV_WW4B1",
|
||||
"CMT_PMV_WW4B2",
|
||||
"CMT_PMV_WW4B3",
|
||||
"CMT_PMV_WW4C0",
|
||||
"CMT_PMV_WW4C1",
|
||||
"CMT_PMV_WW4C2",
|
||||
"CMT_PMV_WW4C3",
|
||||
"CMT_PMV_WW4END0",
|
||||
"CMT_PMV_WW4END1",
|
||||
"CMT_PMV_WW4END2",
|
||||
"CMT_PMV_WW4END3",
|
||||
"L_TERM_INT_PHASER_TO_IO_ICLK",
|
||||
"L_TERM_INT_PHASER_TO_IO_ICLKDIV",
|
||||
"L_TERM_INT_PHASER_TO_IO_OCLK",
|
||||
"L_TERM_INT_PHASER_TO_IO_OCLK1X_90",
|
||||
"L_TERM_INT_PHASER_TO_IO_OCLKDIV"
|
||||
]
|
||||
}
|
||||
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Load Diff
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Load Diff
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Load Diff
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Load Diff
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Load Diff
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Load Diff
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Load Diff
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Load Diff
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Load Diff
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Load Diff
File diff suppressed because it is too large
Load Diff
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Load Diff
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Load Diff
File diff suppressed because it is too large
Load Diff
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue