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prjxray-db
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Updating info based on "Merge pull request #715 from litghost/fix_pip_list". 

See [Info File](Info.md) for details.

Signed-off-by: Tim 'mithro' Ansell <me@mith.ro>
This commit is contained in:
Tim 'mithro' Ansell 2019-03-13 21:42:34 +00:00
parent 69fa7e6538
commit 0025af8b0a
14 changed files with 78238 additions and 75512 deletions
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24
Info.md
View File

@ -37,7 +37,7 @@ These files are released under the very permissive [CC0 1.0 Universal](COPYING).
# Details # Details
Last updated on Wed Mar 13 01:29:20 UTC 2019 (2019-03-13T01:29:20+00:00). Last updated on Wed Mar 13 21:42:34 UTC 2019 (2019-03-13T21:42:34+00:00).
Created using [Project X-Ray](https://github.com/SymbiFlow/prjxray) version [45a8af8](https://github.com/SymbiFlow/prjxray/commit/45a8af8d71c285e7115112c564e5d46b6c81dd97). Created using [Project X-Ray](https://github.com/SymbiFlow/prjxray) version [45a8af8](https://github.com/SymbiFlow/prjxray/commit/45a8af8d71c285e7115112c564e5d46b6c81dd97).
@ -632,22 +632,24 @@ Results have checksums;
* [`389d7501980b8d12b5fe58af98158372ac3eaa1f557434f6ad96b7610c1ad378 ./zynq7/element_counts.csv`](./zynq7/element_counts.csv) * [`389d7501980b8d12b5fe58af98158372ac3eaa1f557434f6ad96b7610c1ad378 ./zynq7/element_counts.csv`](./zynq7/element_counts.csv)
* [`fca753747fb1d583483e22980c4dae3a2de6451a326d46eab3581ea6f50f5b2d ./zynq7/mask_bram_l.block_ram.db`](./zynq7/mask_bram_l.block_ram.db) * [`fca753747fb1d583483e22980c4dae3a2de6451a326d46eab3581ea6f50f5b2d ./zynq7/mask_bram_l.block_ram.db`](./zynq7/mask_bram_l.block_ram.db)
* [`da9713f8d180c1a25603745eeb8b303dc03b7922d9ccf5a330fd43d74262b0f7 ./zynq7/mask_bram_l.db`](./zynq7/mask_bram_l.db) * [`3adab1bc4365599535597dd6366028004dd056a17a3349d328965b23a6a4064a ./zynq7/mask_bram_l.db`](./zynq7/mask_bram_l.db)
* [`fca753747fb1d583483e22980c4dae3a2de6451a326d46eab3581ea6f50f5b2d ./zynq7/mask_bram_r.block_ram.db`](./zynq7/mask_bram_r.block_ram.db) * [`fca753747fb1d583483e22980c4dae3a2de6451a326d46eab3581ea6f50f5b2d ./zynq7/mask_bram_r.block_ram.db`](./zynq7/mask_bram_r.block_ram.db)
* [`da9713f8d180c1a25603745eeb8b303dc03b7922d9ccf5a330fd43d74262b0f7 ./zynq7/mask_bram_r.db`](./zynq7/mask_bram_r.db) * [`3adab1bc4365599535597dd6366028004dd056a17a3349d328965b23a6a4064a ./zynq7/mask_bram_r.db`](./zynq7/mask_bram_r.db)
* [`4f37a37c925f92956b6fc010034529a4cc37698ecb7dd263a0fe737ad600cde7 ./zynq7/mask_clbll_l.db`](./zynq7/mask_clbll_l.db) * [`4f37a37c925f92956b6fc010034529a4cc37698ecb7dd263a0fe737ad600cde7 ./zynq7/mask_clbll_l.db`](./zynq7/mask_clbll_l.db)
* [`4f37a37c925f92956b6fc010034529a4cc37698ecb7dd263a0fe737ad600cde7 ./zynq7/mask_clbll_r.db`](./zynq7/mask_clbll_r.db) * [`4f37a37c925f92956b6fc010034529a4cc37698ecb7dd263a0fe737ad600cde7 ./zynq7/mask_clbll_r.db`](./zynq7/mask_clbll_r.db)
* [`5c274320294201935a3edccb43eca8e347ca1f0acded71ec388c794877d4b55b ./zynq7/mask_clblm_l.db`](./zynq7/mask_clblm_l.db) * [`5c274320294201935a3edccb43eca8e347ca1f0acded71ec388c794877d4b55b ./zynq7/mask_clblm_l.db`](./zynq7/mask_clblm_l.db)
* [`5c274320294201935a3edccb43eca8e347ca1f0acded71ec388c794877d4b55b ./zynq7/mask_clblm_r.db`](./zynq7/mask_clblm_r.db) * [`5c274320294201935a3edccb43eca8e347ca1f0acded71ec388c794877d4b55b ./zynq7/mask_clblm_r.db`](./zynq7/mask_clblm_r.db)
* [`2879d43bc47befb7ac196f32f897755e16118424dad701335daa87960bcd268f ./zynq7/mask_clk_bufg_bot_r.db`](./zynq7/mask_clk_bufg_bot_r.db) * [`f2932beb245918b0613c2abfad2b6d15c1cf31956d5a9ad9d76faec5e4dc54f7 ./zynq7/mask_clk_bufg_bot_r.db`](./zynq7/mask_clk_bufg_bot_r.db)
* [`fab582dba708b87f84b7d493cfc738317201a90cdf73a438a753f7512eee7dea ./zynq7/mask_clk_bufg_rebuf.db`](./zynq7/mask_clk_bufg_rebuf.db) * [`fab582dba708b87f84b7d493cfc738317201a90cdf73a438a753f7512eee7dea ./zynq7/mask_clk_bufg_rebuf.db`](./zynq7/mask_clk_bufg_rebuf.db)
* [`2879d43bc47befb7ac196f32f897755e16118424dad701335daa87960bcd268f ./zynq7/mask_clk_bufg_top_r.db`](./zynq7/mask_clk_bufg_top_r.db) * [`f2932beb245918b0613c2abfad2b6d15c1cf31956d5a9ad9d76faec5e4dc54f7 ./zynq7/mask_clk_bufg_top_r.db`](./zynq7/mask_clk_bufg_top_r.db)
* [`54c076cbee2f848e15bc434a531fbe8fd2b73d3d3394c80b66e2b8ffa1a2b5c1 ./zynq7/mask_clk_hrow_bot_r.db`](./zynq7/mask_clk_hrow_bot_r.db) * [`54c076cbee2f848e15bc434a531fbe8fd2b73d3d3394c80b66e2b8ffa1a2b5c1 ./zynq7/mask_clk_hrow_bot_r.db`](./zynq7/mask_clk_hrow_bot_r.db)
* [`54c076cbee2f848e15bc434a531fbe8fd2b73d3d3394c80b66e2b8ffa1a2b5c1 ./zynq7/mask_clk_hrow_top_r.db`](./zynq7/mask_clk_hrow_top_r.db) * [`54c076cbee2f848e15bc434a531fbe8fd2b73d3d3394c80b66e2b8ffa1a2b5c1 ./zynq7/mask_clk_hrow_top_r.db`](./zynq7/mask_clk_hrow_top_r.db)
* [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./zynq7/mask_dsp_l.db`](./zynq7/mask_dsp_l.db) * [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./zynq7/mask_dsp_l.db`](./zynq7/mask_dsp_l.db)
* [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./zynq7/mask_dsp_r.db`](./zynq7/mask_dsp_r.db) * [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./zynq7/mask_dsp_r.db`](./zynq7/mask_dsp_r.db)
* [`76d1e0bd4b7ad492cf3fe8698b2b5f46f7dcc5fe446984e5dccae373c63edafd ./zynq7/mask_hclk_l.db`](./zynq7/mask_hclk_l.db) * [`76d1e0bd4b7ad492cf3fe8698b2b5f46f7dcc5fe446984e5dccae373c63edafd ./zynq7/mask_hclk_l.db`](./zynq7/mask_hclk_l.db)
* [`76d1e0bd4b7ad492cf3fe8698b2b5f46f7dcc5fe446984e5dccae373c63edafd ./zynq7/mask_hclk_r.db`](./zynq7/mask_hclk_r.db) * [`76d1e0bd4b7ad492cf3fe8698b2b5f46f7dcc5fe446984e5dccae373c63edafd ./zynq7/mask_hclk_r.db`](./zynq7/mask_hclk_r.db)
* [`88c90bebca39f40487ea4836e7870fa2e0ffa7b8d5f4bc21a29cb580c1266e22 ./zynq7/mask_liob33.db`](./zynq7/mask_liob33.db)
* [`88c90bebca39f40487ea4836e7870fa2e0ffa7b8d5f4bc21a29cb580c1266e22 ./zynq7/mask_riob33.db`](./zynq7/mask_riob33.db)
* [`d94e4d13df16da498224f0e94deaa310fbf471b6f9ec0ec8b2308fe62fa2eeaf ./zynq7/ppips_bram_int_interface_l.db`](./zynq7/ppips_bram_int_interface_l.db) * [`d94e4d13df16da498224f0e94deaa310fbf471b6f9ec0ec8b2308fe62fa2eeaf ./zynq7/ppips_bram_int_interface_l.db`](./zynq7/ppips_bram_int_interface_l.db)
* [`b48d766ac6f9dd0e21280d3a04dd448ea39016143309c0c7867fc00d730a59ae ./zynq7/ppips_bram_int_interface_r.db`](./zynq7/ppips_bram_int_interface_r.db) * [`b48d766ac6f9dd0e21280d3a04dd448ea39016143309c0c7867fc00d730a59ae ./zynq7/ppips_bram_int_interface_r.db`](./zynq7/ppips_bram_int_interface_r.db)
* [`2c68f8b128aeb79197013c3a1774522143a3507a8fa595a98c22dba2553fd5ce ./zynq7/ppips_bram_l.db`](./zynq7/ppips_bram_l.db) * [`2c68f8b128aeb79197013c3a1774522143a3507a8fa595a98c22dba2553fd5ce ./zynq7/ppips_bram_l.db`](./zynq7/ppips_bram_l.db)
@ -662,10 +664,10 @@ Results have checksums;
* [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./zynq7/ppips_hclk_r.db`](./zynq7/ppips_hclk_r.db) * [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./zynq7/ppips_hclk_r.db`](./zynq7/ppips_hclk_r.db)
* [`d300ad4128a192e416a958471013b7554f141fd1f816715828b1e5a87838f18d ./zynq7/ppips_int_l.db`](./zynq7/ppips_int_l.db) * [`d300ad4128a192e416a958471013b7554f141fd1f816715828b1e5a87838f18d ./zynq7/ppips_int_l.db`](./zynq7/ppips_int_l.db)
* [`46564e746b8d9e37bf46a68f2915bd1395efb68508d48d336a4dfb9342105285 ./zynq7/ppips_int_r.db`](./zynq7/ppips_int_r.db) * [`46564e746b8d9e37bf46a68f2915bd1395efb68508d48d336a4dfb9342105285 ./zynq7/ppips_int_r.db`](./zynq7/ppips_int_r.db)
* [`63cab7c6cb50b9a86cd6de4ec02cfba93b99ac622684a1196b3d70adb1472fc1 ./zynq7/segbits_bram_l.block_ram.db`](./zynq7/segbits_bram_l.block_ram.db) * [`8a2136e564ac92c06b226ef8715a122050fcabbb063f69eeaf46cfee5c89670f ./zynq7/segbits_bram_l.block_ram.db`](./zynq7/segbits_bram_l.block_ram.db)
* [`f61ce3972e8a3db9dd090a626c018c247788b5ba0946968b641d108de325a0a1 ./zynq7/segbits_bram_l.db`](./zynq7/segbits_bram_l.db) * [`53d975bf59b763b9f764106db362ee7f6a753e9e72a5e2be334041658a5ea4ba ./zynq7/segbits_bram_l.db`](./zynq7/segbits_bram_l.db)
* [`6daa967b706d7fc5cdf597ed9f142df8f3003ded2fee3d622d484b21ceda2827 ./zynq7/segbits_bram_r.block_ram.db`](./zynq7/segbits_bram_r.block_ram.db) * [`a635577b55878c69df492c16b67a1dfbd1d4b786a695abe3e95a62d9540ecea5 ./zynq7/segbits_bram_r.block_ram.db`](./zynq7/segbits_bram_r.block_ram.db)
* [`d675f037111e500b21acb0b455d77f3b972de1f68643d69a842ea8ffb44db65a ./zynq7/segbits_bram_r.db`](./zynq7/segbits_bram_r.db) * [`b826680f3768091cb345ca6e62e3210ffb53a88ebdfdf4ca70f466f80cdacb1f ./zynq7/segbits_bram_r.db`](./zynq7/segbits_bram_r.db)
* [`ef6706ef033396c75469738223e66d1b5f38b832e27b5bb80f07efd571e28fb7 ./zynq7/segbits_clbll_l.db`](./zynq7/segbits_clbll_l.db) * [`ef6706ef033396c75469738223e66d1b5f38b832e27b5bb80f07efd571e28fb7 ./zynq7/segbits_clbll_l.db`](./zynq7/segbits_clbll_l.db)
* [`53c0ea2b05a2c4ddf2b6cce38073534d0c21b893fc5783dc777d97de2f2d6a9e ./zynq7/segbits_clbll_r.db`](./zynq7/segbits_clbll_r.db) * [`53c0ea2b05a2c4ddf2b6cce38073534d0c21b893fc5783dc777d97de2f2d6a9e ./zynq7/segbits_clbll_r.db`](./zynq7/segbits_clbll_r.db)
* [`e6459c01d0c1c7724fa02716103fd02a3e2a75d6b7326f4c937f158a264ffe85 ./zynq7/segbits_clblm_l.db`](./zynq7/segbits_clblm_l.db) * [`e6459c01d0c1c7724fa02716103fd02a3e2a75d6b7326f4c937f158a264ffe85 ./zynq7/segbits_clblm_l.db`](./zynq7/segbits_clblm_l.db)
@ -681,6 +683,8 @@ Results have checksums;
* [`51288ec0be63172fcb2a12a92853150c62a21e894c2d42a2586046c462bf57a9 ./zynq7/segbits_hclk_r.db`](./zynq7/segbits_hclk_r.db) * [`51288ec0be63172fcb2a12a92853150c62a21e894c2d42a2586046c462bf57a9 ./zynq7/segbits_hclk_r.db`](./zynq7/segbits_hclk_r.db)
* [`0ea44e8dfaf97ed200f30b2afe117e94e1a68bdb26af2e09e69e855414779520 ./zynq7/segbits_int_l.db`](./zynq7/segbits_int_l.db) * [`0ea44e8dfaf97ed200f30b2afe117e94e1a68bdb26af2e09e69e855414779520 ./zynq7/segbits_int_l.db`](./zynq7/segbits_int_l.db)
* [`1541c7832dd161c5b3b5745d08fe0ee6f92bfbd372b76c12f54afc032c888556 ./zynq7/segbits_int_r.db`](./zynq7/segbits_int_r.db) * [`1541c7832dd161c5b3b5745d08fe0ee6f92bfbd372b76c12f54afc032c888556 ./zynq7/segbits_int_r.db`](./zynq7/segbits_int_r.db)
* [`bed06fc405947c72a47a7fbac7adbc220efd2dc8d73f321ed70b8d2490ab745b ./zynq7/segbits_liob33.db`](./zynq7/segbits_liob33.db)
* [`8ec421f8f4ce1bab7e81bcbf0cbdc37fb3f6ed4715bc2fdf75db336805efc53e ./zynq7/segbits_riob33.db`](./zynq7/segbits_riob33.db)
* [`ee26e7dbf78c2a37118c49ce7edb5fa44afd51850a24824ba8b68e34366f0787 ./zynq7/settings.sh`](./zynq7/settings.sh) * [`ee26e7dbf78c2a37118c49ce7edb5fa44afd51850a24824ba8b68e34366f0787 ./zynq7/settings.sh`](./zynq7/settings.sh)
* [`ac6ba9ad814503f0fdc1dabb4292aaccd1a2195f5b348276cfee12aed3d96a70 ./zynq7/site_type_BSCAN.json`](./zynq7/site_type_BSCAN.json) * [`ac6ba9ad814503f0fdc1dabb4292aaccd1a2195f5b348276cfee12aed3d96a70 ./zynq7/site_type_BSCAN.json`](./zynq7/site_type_BSCAN.json)
* [`64724ba2f8af98df5e1d92e5c2da2e6d5a41eec6580f796405e271dadb4e63be ./zynq7/site_type_BUFGCTRL.json`](./zynq7/site_type_BUFGCTRL.json) * [`64724ba2f8af98df5e1d92e5c2da2e6d5a41eec6580f796405e271dadb4e63be ./zynq7/site_type_BUFGCTRL.json`](./zynq7/site_type_BUFGCTRL.json)
@ -814,6 +818,6 @@ Results have checksums;
* [`dee783006fa5b5964d20457323cad59171a60397d730e9fe0840389587695727 ./zynq7/tile_type_VBRK.json`](./zynq7/tile_type_VBRK.json) * [`dee783006fa5b5964d20457323cad59171a60397d730e9fe0840389587695727 ./zynq7/tile_type_VBRK.json`](./zynq7/tile_type_VBRK.json)
* [`004efcd7f9e172780ca7b8c379ec329bcfc52f86beaa1d997f41dbef7ac4a242 ./zynq7/tile_type_VFRAME.json`](./zynq7/tile_type_VFRAME.json) * [`004efcd7f9e172780ca7b8c379ec329bcfc52f86beaa1d997f41dbef7ac4a242 ./zynq7/tile_type_VFRAME.json`](./zynq7/tile_type_VFRAME.json)
* [`e6d0ebf9b27f60f4afdab85a357bff4d7cf2cd77c3a6c0f2d887022cda874066 ./zynq7/tileconn.json`](./zynq7/tileconn.json) * [`e6d0ebf9b27f60f4afdab85a357bff4d7cf2cd77c3a6c0f2d887022cda874066 ./zynq7/tileconn.json`](./zynq7/tileconn.json)
* [`6c92e63046927e065add31b58033e6e72aaf85432ee602fda05be0c2a7f1577b ./zynq7/tilegrid.json`](./zynq7/tilegrid.json) * [`2f47bc43658a75f97bc3b2eab79d2a5d3adc9cb008609d2ed94ddb76e1386e11 ./zynq7/tilegrid.json`](./zynq7/tilegrid.json)
* [`f3704845c7559e0289c9a1c6f42a7874be6d5d7aef3e0f285647b8ca62a154b3 ./zynq7/xc7z010clg400-1.json`](./zynq7/xc7z010clg400-1.json) * [`f3704845c7559e0289c9a1c6f42a7874be6d5d7aef3e0f285647b8ca62a154b3 ./zynq7/xc7z010clg400-1.json`](./zynq7/xc7z010clg400-1.json)
* [`43a136f26603c51bd97e9489d223bbc80f278fcc234225ed9fde404402f22683 ./zynq7/xc7z010clg400-1.yaml`](./zynq7/xc7z010clg400-1.yaml) * [`43a136f26603c51bd97e9489d223bbc80f278fcc234225ed9fde404402f22683 ./zynq7/xc7z010clg400-1.yaml`](./zynq7/xc7z010clg400-1.yaml)

534
zynq7/mask_bram_l.db
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zynq7/mask_bram_r.db
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zynq7/mask_clk_bufg_bot_r.db
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zynq7/mask_clk_bufg_top_r.db
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zynq7/mask_liob33.db Normal file
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zynq7/mask_riob33.db Normal file
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zynq7/segbits_bram_l.block_ram.db
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zynq7/segbits_bram_l.db
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@ -178,6 +178,8 @@ BRAM_L.BRAM_ADDRBWRADDRU13.BRAM_IMUX_ADDRBWRADDRU13 !26_141 !26_142 !26_143
BRAM_L.BRAM_ADDRBWRADDRU14.BRAM_CASCINBOT_ADDRBWRADDRU14 26_269 !26_270 26_271 BRAM_L.BRAM_ADDRBWRADDRU14.BRAM_CASCINBOT_ADDRBWRADDRU14 26_269 !26_270 26_271
BRAM_L.BRAM_ADDRBWRADDRU14.BRAM_CASCINTOP_ADDRBWRADDRU14 !26_269 26_270 26_271 BRAM_L.BRAM_ADDRBWRADDRU14.BRAM_CASCINTOP_ADDRBWRADDRU14 !26_269 26_270 26_271
BRAM_L.BRAM_ADDRBWRADDRU14.BRAM_IMUX_ADDRBWRADDRU14 !26_269 !26_270 !26_271 BRAM_L.BRAM_ADDRBWRADDRU14.BRAM_IMUX_ADDRBWRADDRU14 !26_269 !26_270 !26_271
BRAM_L.CASCOUT_ARD_ACTIVE 26_170
BRAM_L.CASCOUT_BWR_ACTIVE 26_172
BRAM_L.EN_SYN 27_171 BRAM_L.EN_SYN 27_171
BRAM_L.FIRST_WORD_FALL_THROUGH 27_170 BRAM_L.FIRST_WORD_FALL_THROUGH 27_170
BRAM_L.ZALMOST_EMPTY_OFFSET[0] 27_288 BRAM_L.ZALMOST_EMPTY_OFFSET[0] 27_288
@ -210,42 +212,6 @@ BRAM_L.RAMB18_Y0.DOA_REG 27_69
BRAM_L.RAMB18_Y0.DOB_REG 27_72 BRAM_L.RAMB18_Y0.DOB_REG 27_72
BRAM_L.RAMB18_Y0.FIFO_MODE 27_150 BRAM_L.RAMB18_Y0.FIFO_MODE 27_150
BRAM_L.RAMB18_Y0.IN_USE 27_99 27_100 BRAM_L.RAMB18_Y0.IN_USE 27_99 27_100
BRAM_L.RAMB18_Y0.INIT_A[0] 27_73
BRAM_L.RAMB18_Y0.INIT_A[1] 27_65
BRAM_L.RAMB18_Y0.INIT_A[2] 27_137
BRAM_L.RAMB18_Y0.INIT_A[3] 27_121
BRAM_L.RAMB18_Y0.INIT_A[4] 27_105
BRAM_L.RAMB18_Y0.INIT_A[5] 27_89
BRAM_L.RAMB18_Y0.INIT_A[6] 27_57
BRAM_L.RAMB18_Y0.INIT_A[7] 27_41
BRAM_L.RAMB18_Y0.INIT_A[8] 27_25
BRAM_L.RAMB18_Y0.INIT_A[9] 27_09
BRAM_L.RAMB18_Y0.INIT_A[10] 27_129
BRAM_L.RAMB18_Y0.INIT_A[11] 27_113
BRAM_L.RAMB18_Y0.INIT_A[12] 27_97
BRAM_L.RAMB18_Y0.INIT_A[13] 27_81
BRAM_L.RAMB18_Y0.INIT_A[14] 27_49
BRAM_L.RAMB18_Y0.INIT_A[15] 27_33
BRAM_L.RAMB18_Y0.INIT_A[16] 27_17
BRAM_L.RAMB18_Y0.INIT_A[17] 27_01
BRAM_L.RAMB18_Y0.INIT_B[0] 27_79
BRAM_L.RAMB18_Y0.INIT_B[1] 27_71
BRAM_L.RAMB18_Y0.INIT_B[2] 27_143
BRAM_L.RAMB18_Y0.INIT_B[3] 27_127
BRAM_L.RAMB18_Y0.INIT_B[4] 27_111
BRAM_L.RAMB18_Y0.INIT_B[5] 27_95
BRAM_L.RAMB18_Y0.INIT_B[6] 27_63
BRAM_L.RAMB18_Y0.INIT_B[7] 27_47
BRAM_L.RAMB18_Y0.INIT_B[8] 27_31
BRAM_L.RAMB18_Y0.INIT_B[9] 27_15
BRAM_L.RAMB18_Y0.INIT_B[10] 27_135
BRAM_L.RAMB18_Y0.INIT_B[11] 27_119
BRAM_L.RAMB18_Y0.INIT_B[12] 27_103
BRAM_L.RAMB18_Y0.INIT_B[13] 27_87
BRAM_L.RAMB18_Y0.INIT_B[14] 27_55
BRAM_L.RAMB18_Y0.INIT_B[15] 27_39
BRAM_L.RAMB18_Y0.INIT_B[16] 27_23
BRAM_L.RAMB18_Y0.INIT_B[17] 27_07
BRAM_L.RAMB18_Y0.RDADDR_COLLISION_HWCONFIG_DELAYED_WRITE !27_96 BRAM_L.RAMB18_Y0.RDADDR_COLLISION_HWCONFIG_DELAYED_WRITE !27_96
BRAM_L.RAMB18_Y0.RDADDR_COLLISION_HWCONFIG_PERFORMANCE 27_96 BRAM_L.RAMB18_Y0.RDADDR_COLLISION_HWCONFIG_PERFORMANCE 27_96
BRAM_L.RAMB18_Y0.READ_WIDTH_A_1 !27_35 !27_36 !27_37 BRAM_L.RAMB18_Y0.READ_WIDTH_A_1 !27_35 !27_36 !27_37
@ -262,42 +228,8 @@ BRAM_L.RAMB18_Y0.RSTREG_PRIORITY_A_REGCE 27_124
BRAM_L.RAMB18_Y0.RSTREG_PRIORITY_A_RSTREG !27_124 BRAM_L.RAMB18_Y0.RSTREG_PRIORITY_A_RSTREG !27_124
BRAM_L.RAMB18_Y0.RSTREG_PRIORITY_B_REGCE 27_125 BRAM_L.RAMB18_Y0.RSTREG_PRIORITY_B_REGCE 27_125
BRAM_L.RAMB18_Y0.RSTREG_PRIORITY_B_RSTREG !27_125 BRAM_L.RAMB18_Y0.RSTREG_PRIORITY_B_RSTREG !27_125
BRAM_L.RAMB18_Y0.SRVAL_A[0] 27_74 BRAM_L.RAMB18_Y0.SDP_READ_WIDTH_36 27_48
BRAM_L.RAMB18_Y0.SRVAL_A[1] 27_66 BRAM_L.RAMB18_Y0.SDP_WRITE_WIDTH_36 27_40
BRAM_L.RAMB18_Y0.SRVAL_A[2] 27_138
BRAM_L.RAMB18_Y0.SRVAL_A[3] 27_122
BRAM_L.RAMB18_Y0.SRVAL_A[4] 27_106
BRAM_L.RAMB18_Y0.SRVAL_A[5] 27_90
BRAM_L.RAMB18_Y0.SRVAL_A[6] 27_58
BRAM_L.RAMB18_Y0.SRVAL_A[7] 27_42
BRAM_L.RAMB18_Y0.SRVAL_A[8] 27_26
BRAM_L.RAMB18_Y0.SRVAL_A[9] 27_10
BRAM_L.RAMB18_Y0.SRVAL_A[10] 27_130
BRAM_L.RAMB18_Y0.SRVAL_A[11] 27_114
BRAM_L.RAMB18_Y0.SRVAL_A[12] 27_98
BRAM_L.RAMB18_Y0.SRVAL_A[13] 27_82
BRAM_L.RAMB18_Y0.SRVAL_A[14] 27_50
BRAM_L.RAMB18_Y0.SRVAL_A[15] 27_34
BRAM_L.RAMB18_Y0.SRVAL_A[16] 27_18
BRAM_L.RAMB18_Y0.SRVAL_A[17] 27_02
BRAM_L.RAMB18_Y0.SRVAL_B[0] 27_78
BRAM_L.RAMB18_Y0.SRVAL_B[1] 27_70
BRAM_L.RAMB18_Y0.SRVAL_B[2] 27_142
BRAM_L.RAMB18_Y0.SRVAL_B[3] 27_126
BRAM_L.RAMB18_Y0.SRVAL_B[4] 27_110
BRAM_L.RAMB18_Y0.SRVAL_B[5] 27_94
BRAM_L.RAMB18_Y0.SRVAL_B[6] 27_62
BRAM_L.RAMB18_Y0.SRVAL_B[7] 27_46
BRAM_L.RAMB18_Y0.SRVAL_B[8] 27_30
BRAM_L.RAMB18_Y0.SRVAL_B[9] 27_14
BRAM_L.RAMB18_Y0.SRVAL_B[10] 27_134
BRAM_L.RAMB18_Y0.SRVAL_B[11] 27_118
BRAM_L.RAMB18_Y0.SRVAL_B[12] 27_102
BRAM_L.RAMB18_Y0.SRVAL_B[13] 27_86
BRAM_L.RAMB18_Y0.SRVAL_B[14] 27_54
BRAM_L.RAMB18_Y0.SRVAL_B[15] 27_38
BRAM_L.RAMB18_Y0.SRVAL_B[16] 27_22
BRAM_L.RAMB18_Y0.SRVAL_B[17] 27_06
BRAM_L.RAMB18_Y0.WRITE_MODE_A_NO_CHANGE 27_64 BRAM_L.RAMB18_Y0.WRITE_MODE_A_NO_CHANGE 27_64
BRAM_L.RAMB18_Y0.WRITE_MODE_A_READ_FIRST 27_56 BRAM_L.RAMB18_Y0.WRITE_MODE_A_READ_FIRST 27_56
BRAM_L.RAMB18_Y0.WRITE_MODE_B_NO_CHANGE 27_68 BRAM_L.RAMB18_Y0.WRITE_MODE_B_NO_CHANGE 27_68
@ -312,6 +244,42 @@ BRAM_L.RAMB18_Y0.WRITE_WIDTH_B_2 27_59 !27_60 !27_61
BRAM_L.RAMB18_Y0.WRITE_WIDTH_B_4 !27_59 27_60 !27_61 BRAM_L.RAMB18_Y0.WRITE_WIDTH_B_4 !27_59 27_60 !27_61
BRAM_L.RAMB18_Y0.WRITE_WIDTH_B_9 27_59 27_60 !27_61 BRAM_L.RAMB18_Y0.WRITE_WIDTH_B_9 27_59 27_60 !27_61
BRAM_L.RAMB18_Y0.WRITE_WIDTH_B_18 !27_59 !27_60 27_61 BRAM_L.RAMB18_Y0.WRITE_WIDTH_B_18 !27_59 !27_60 27_61
BRAM_L.RAMB18_Y0.ZINIT_A[0] 27_73
BRAM_L.RAMB18_Y0.ZINIT_A[1] 27_65
BRAM_L.RAMB18_Y0.ZINIT_A[2] 27_137
BRAM_L.RAMB18_Y0.ZINIT_A[3] 27_121
BRAM_L.RAMB18_Y0.ZINIT_A[4] 27_105
BRAM_L.RAMB18_Y0.ZINIT_A[5] 27_89
BRAM_L.RAMB18_Y0.ZINIT_A[6] 27_57
BRAM_L.RAMB18_Y0.ZINIT_A[7] 27_41
BRAM_L.RAMB18_Y0.ZINIT_A[8] 27_25
BRAM_L.RAMB18_Y0.ZINIT_A[9] 27_09
BRAM_L.RAMB18_Y0.ZINIT_A[10] 27_129
BRAM_L.RAMB18_Y0.ZINIT_A[11] 27_113
BRAM_L.RAMB18_Y0.ZINIT_A[12] 27_97
BRAM_L.RAMB18_Y0.ZINIT_A[13] 27_81
BRAM_L.RAMB18_Y0.ZINIT_A[14] 27_49
BRAM_L.RAMB18_Y0.ZINIT_A[15] 27_33
BRAM_L.RAMB18_Y0.ZINIT_A[16] 27_17
BRAM_L.RAMB18_Y0.ZINIT_A[17] 27_01
BRAM_L.RAMB18_Y0.ZINIT_B[0] 27_79
BRAM_L.RAMB18_Y0.ZINIT_B[1] 27_71
BRAM_L.RAMB18_Y0.ZINIT_B[2] 27_143
BRAM_L.RAMB18_Y0.ZINIT_B[3] 27_127
BRAM_L.RAMB18_Y0.ZINIT_B[4] 27_111
BRAM_L.RAMB18_Y0.ZINIT_B[5] 27_95
BRAM_L.RAMB18_Y0.ZINIT_B[6] 27_63
BRAM_L.RAMB18_Y0.ZINIT_B[7] 27_47
BRAM_L.RAMB18_Y0.ZINIT_B[8] 27_31
BRAM_L.RAMB18_Y0.ZINIT_B[9] 27_15
BRAM_L.RAMB18_Y0.ZINIT_B[10] 27_135
BRAM_L.RAMB18_Y0.ZINIT_B[11] 27_119
BRAM_L.RAMB18_Y0.ZINIT_B[12] 27_103
BRAM_L.RAMB18_Y0.ZINIT_B[13] 27_87
BRAM_L.RAMB18_Y0.ZINIT_B[14] 27_55
BRAM_L.RAMB18_Y0.ZINIT_B[15] 27_39
BRAM_L.RAMB18_Y0.ZINIT_B[16] 27_23
BRAM_L.RAMB18_Y0.ZINIT_B[17] 27_07
BRAM_L.RAMB18_Y0.ZINV_CLKARDCLK 27_107 BRAM_L.RAMB18_Y0.ZINV_CLKARDCLK 27_107
BRAM_L.RAMB18_Y0.ZINV_CLKBWRCLK 27_109 BRAM_L.RAMB18_Y0.ZINV_CLKBWRCLK 27_109
BRAM_L.RAMB18_Y0.ZINV_ENARDEN 27_112 BRAM_L.RAMB18_Y0.ZINV_ENARDEN 27_112
@ -322,46 +290,46 @@ BRAM_L.RAMB18_Y0.ZINV_RSTRAMARSTRAM 27_116
BRAM_L.RAMB18_Y0.ZINV_RSTRAMB 27_117 BRAM_L.RAMB18_Y0.ZINV_RSTRAMB 27_117
BRAM_L.RAMB18_Y0.ZINV_RSTREGARSTREG 27_120 BRAM_L.RAMB18_Y0.ZINV_RSTREGARSTREG 27_120
BRAM_L.RAMB18_Y0.ZINV_RSTREGB 27_123 BRAM_L.RAMB18_Y0.ZINV_RSTREGB 27_123
BRAM_L.RAMB18_Y0.ZSRVAL_A[0] 27_74
BRAM_L.RAMB18_Y0.ZSRVAL_A[1] 27_66
BRAM_L.RAMB18_Y0.ZSRVAL_A[2] 27_138
BRAM_L.RAMB18_Y0.ZSRVAL_A[3] 27_122
BRAM_L.RAMB18_Y0.ZSRVAL_A[4] 27_106
BRAM_L.RAMB18_Y0.ZSRVAL_A[5] 27_90
BRAM_L.RAMB18_Y0.ZSRVAL_A[6] 27_58
BRAM_L.RAMB18_Y0.ZSRVAL_A[7] 27_42
BRAM_L.RAMB18_Y0.ZSRVAL_A[8] 27_26
BRAM_L.RAMB18_Y0.ZSRVAL_A[9] 27_10
BRAM_L.RAMB18_Y0.ZSRVAL_A[10] 27_130
BRAM_L.RAMB18_Y0.ZSRVAL_A[11] 27_114
BRAM_L.RAMB18_Y0.ZSRVAL_A[12] 27_98
BRAM_L.RAMB18_Y0.ZSRVAL_A[13] 27_82
BRAM_L.RAMB18_Y0.ZSRVAL_A[14] 27_50
BRAM_L.RAMB18_Y0.ZSRVAL_A[15] 27_34
BRAM_L.RAMB18_Y0.ZSRVAL_A[16] 27_18
BRAM_L.RAMB18_Y0.ZSRVAL_A[17] 27_02
BRAM_L.RAMB18_Y0.ZSRVAL_B[0] 27_78
BRAM_L.RAMB18_Y0.ZSRVAL_B[1] 27_70
BRAM_L.RAMB18_Y0.ZSRVAL_B[2] 27_142
BRAM_L.RAMB18_Y0.ZSRVAL_B[3] 27_126
BRAM_L.RAMB18_Y0.ZSRVAL_B[4] 27_110
BRAM_L.RAMB18_Y0.ZSRVAL_B[5] 27_94
BRAM_L.RAMB18_Y0.ZSRVAL_B[6] 27_62
BRAM_L.RAMB18_Y0.ZSRVAL_B[7] 27_46
BRAM_L.RAMB18_Y0.ZSRVAL_B[8] 27_30
BRAM_L.RAMB18_Y0.ZSRVAL_B[9] 27_14
BRAM_L.RAMB18_Y0.ZSRVAL_B[10] 27_134
BRAM_L.RAMB18_Y0.ZSRVAL_B[11] 27_118
BRAM_L.RAMB18_Y0.ZSRVAL_B[12] 27_102
BRAM_L.RAMB18_Y0.ZSRVAL_B[13] 27_86
BRAM_L.RAMB18_Y0.ZSRVAL_B[14] 27_54
BRAM_L.RAMB18_Y0.ZSRVAL_B[15] 27_38
BRAM_L.RAMB18_Y0.ZSRVAL_B[16] 27_22
BRAM_L.RAMB18_Y0.ZSRVAL_B[17] 27_06
BRAM_L.RAMB18_Y1.DOA_REG 27_251 BRAM_L.RAMB18_Y1.DOA_REG 27_251
BRAM_L.RAMB18_Y1.DOB_REG 27_248 BRAM_L.RAMB18_Y1.DOB_REG 27_248
BRAM_L.RAMB18_Y1.FIFO_MODE 27_169 BRAM_L.RAMB18_Y1.FIFO_MODE 27_169
BRAM_L.RAMB18_Y1.IN_USE 27_220 27_221 BRAM_L.RAMB18_Y1.IN_USE 27_220 27_221
BRAM_L.RAMB18_Y1.INIT_A[0] 27_249
BRAM_L.RAMB18_Y1.INIT_A[1] 27_241
BRAM_L.RAMB18_Y1.INIT_A[2] 27_313
BRAM_L.RAMB18_Y1.INIT_A[3] 27_297
BRAM_L.RAMB18_Y1.INIT_A[4] 27_281
BRAM_L.RAMB18_Y1.INIT_A[5] 27_265
BRAM_L.RAMB18_Y1.INIT_A[6] 27_233
BRAM_L.RAMB18_Y1.INIT_A[7] 27_217
BRAM_L.RAMB18_Y1.INIT_A[8] 27_201
BRAM_L.RAMB18_Y1.INIT_A[9] 27_185
BRAM_L.RAMB18_Y1.INIT_A[10] 27_305
BRAM_L.RAMB18_Y1.INIT_A[11] 27_289
BRAM_L.RAMB18_Y1.INIT_A[12] 27_273
BRAM_L.RAMB18_Y1.INIT_A[13] 27_257
BRAM_L.RAMB18_Y1.INIT_A[14] 27_225
BRAM_L.RAMB18_Y1.INIT_A[15] 27_209
BRAM_L.RAMB18_Y1.INIT_A[16] 27_193
BRAM_L.RAMB18_Y1.INIT_A[17] 27_177
BRAM_L.RAMB18_Y1.INIT_B[0] 27_255
BRAM_L.RAMB18_Y1.INIT_B[1] 27_247
BRAM_L.RAMB18_Y1.INIT_B[2] 27_319
BRAM_L.RAMB18_Y1.INIT_B[3] 27_303
BRAM_L.RAMB18_Y1.INIT_B[4] 27_287
BRAM_L.RAMB18_Y1.INIT_B[5] 27_271
BRAM_L.RAMB18_Y1.INIT_B[6] 27_239
BRAM_L.RAMB18_Y1.INIT_B[7] 27_223
BRAM_L.RAMB18_Y1.INIT_B[8] 27_207
BRAM_L.RAMB18_Y1.INIT_B[9] 27_191
BRAM_L.RAMB18_Y1.INIT_B[10] 27_311
BRAM_L.RAMB18_Y1.INIT_B[11] 27_295
BRAM_L.RAMB18_Y1.INIT_B[12] 27_279
BRAM_L.RAMB18_Y1.INIT_B[13] 27_263
BRAM_L.RAMB18_Y1.INIT_B[14] 27_231
BRAM_L.RAMB18_Y1.INIT_B[15] 27_215
BRAM_L.RAMB18_Y1.INIT_B[16] 27_199
BRAM_L.RAMB18_Y1.INIT_B[17] 27_183
BRAM_L.RAMB18_Y1.RDADDR_COLLISION_HWCONFIG_DELAYED_WRITE !27_224 BRAM_L.RAMB18_Y1.RDADDR_COLLISION_HWCONFIG_DELAYED_WRITE !27_224
BRAM_L.RAMB18_Y1.RDADDR_COLLISION_HWCONFIG_PERFORMANCE 27_224 BRAM_L.RAMB18_Y1.RDADDR_COLLISION_HWCONFIG_PERFORMANCE 27_224
BRAM_L.RAMB18_Y1.READ_WIDTH_A_1 !27_283 !27_284 !27_285 BRAM_L.RAMB18_Y1.READ_WIDTH_A_1 !27_283 !27_284 !27_285
@ -378,42 +346,8 @@ BRAM_L.RAMB18_Y1.RSTREG_PRIORITY_A_REGCE 27_196
BRAM_L.RAMB18_Y1.RSTREG_PRIORITY_A_RSTREG !27_196 BRAM_L.RAMB18_Y1.RSTREG_PRIORITY_A_RSTREG !27_196
BRAM_L.RAMB18_Y1.RSTREG_PRIORITY_B_REGCE 27_195 BRAM_L.RAMB18_Y1.RSTREG_PRIORITY_B_REGCE 27_195
BRAM_L.RAMB18_Y1.RSTREG_PRIORITY_B_RSTREG !27_195 BRAM_L.RAMB18_Y1.RSTREG_PRIORITY_B_RSTREG !27_195
BRAM_L.RAMB18_Y1.SRVAL_A[0] 27_250 BRAM_L.RAMB18_Y1.SDP_READ_WIDTH_36 27_272
BRAM_L.RAMB18_Y1.SRVAL_A[1] 27_242 BRAM_L.RAMB18_Y1.SDP_WRITE_WIDTH_36 27_280
BRAM_L.RAMB18_Y1.SRVAL_A[2] 27_314
BRAM_L.RAMB18_Y1.SRVAL_A[3] 27_298
BRAM_L.RAMB18_Y1.SRVAL_A[4] 27_282
BRAM_L.RAMB18_Y1.SRVAL_A[5] 27_266
BRAM_L.RAMB18_Y1.SRVAL_A[6] 27_234
BRAM_L.RAMB18_Y1.SRVAL_A[7] 27_218
BRAM_L.RAMB18_Y1.SRVAL_A[8] 27_202
BRAM_L.RAMB18_Y1.SRVAL_A[9] 27_186
BRAM_L.RAMB18_Y1.SRVAL_A[10] 27_306
BRAM_L.RAMB18_Y1.SRVAL_A[11] 27_290
BRAM_L.RAMB18_Y1.SRVAL_A[12] 27_274
BRAM_L.RAMB18_Y1.SRVAL_A[13] 27_258
BRAM_L.RAMB18_Y1.SRVAL_A[14] 27_226
BRAM_L.RAMB18_Y1.SRVAL_A[15] 27_210
BRAM_L.RAMB18_Y1.SRVAL_A[16] 27_194
BRAM_L.RAMB18_Y1.SRVAL_A[17] 27_178
BRAM_L.RAMB18_Y1.SRVAL_B[0] 27_254
BRAM_L.RAMB18_Y1.SRVAL_B[1] 27_246
BRAM_L.RAMB18_Y1.SRVAL_B[2] 27_318
BRAM_L.RAMB18_Y1.SRVAL_B[3] 27_302
BRAM_L.RAMB18_Y1.SRVAL_B[4] 27_286
BRAM_L.RAMB18_Y1.SRVAL_B[5] 27_270
BRAM_L.RAMB18_Y1.SRVAL_B[6] 27_238
BRAM_L.RAMB18_Y1.SRVAL_B[7] 27_222
BRAM_L.RAMB18_Y1.SRVAL_B[8] 27_206
BRAM_L.RAMB18_Y1.SRVAL_B[9] 27_190
BRAM_L.RAMB18_Y1.SRVAL_B[10] 27_310
BRAM_L.RAMB18_Y1.SRVAL_B[11] 27_294
BRAM_L.RAMB18_Y1.SRVAL_B[12] 27_278
BRAM_L.RAMB18_Y1.SRVAL_B[13] 27_262
BRAM_L.RAMB18_Y1.SRVAL_B[14] 27_230
BRAM_L.RAMB18_Y1.SRVAL_B[15] 27_214
BRAM_L.RAMB18_Y1.SRVAL_B[16] 27_198
BRAM_L.RAMB18_Y1.SRVAL_B[17] 27_182
BRAM_L.RAMB18_Y1.WRITE_MODE_A_NO_CHANGE 27_256 BRAM_L.RAMB18_Y1.WRITE_MODE_A_NO_CHANGE 27_256
BRAM_L.RAMB18_Y1.WRITE_MODE_A_READ_FIRST 27_264 BRAM_L.RAMB18_Y1.WRITE_MODE_A_READ_FIRST 27_264
BRAM_L.RAMB18_Y1.WRITE_MODE_B_NO_CHANGE 27_252 BRAM_L.RAMB18_Y1.WRITE_MODE_B_NO_CHANGE 27_252
@ -428,6 +362,42 @@ BRAM_L.RAMB18_Y1.WRITE_WIDTH_B_2 !27_259 !27_260 27_261
BRAM_L.RAMB18_Y1.WRITE_WIDTH_B_4 !27_259 27_260 !27_261 BRAM_L.RAMB18_Y1.WRITE_WIDTH_B_4 !27_259 27_260 !27_261
BRAM_L.RAMB18_Y1.WRITE_WIDTH_B_9 !27_259 27_260 27_261 BRAM_L.RAMB18_Y1.WRITE_WIDTH_B_9 !27_259 27_260 27_261
BRAM_L.RAMB18_Y1.WRITE_WIDTH_B_18 27_259 !27_260 !27_261 BRAM_L.RAMB18_Y1.WRITE_WIDTH_B_18 27_259 !27_260 !27_261
BRAM_L.RAMB18_Y1.ZINIT_A[0] 27_249
BRAM_L.RAMB18_Y1.ZINIT_A[1] 27_241
BRAM_L.RAMB18_Y1.ZINIT_A[2] 27_313
BRAM_L.RAMB18_Y1.ZINIT_A[3] 27_297
BRAM_L.RAMB18_Y1.ZINIT_A[4] 27_281
BRAM_L.RAMB18_Y1.ZINIT_A[5] 27_265
BRAM_L.RAMB18_Y1.ZINIT_A[6] 27_233
BRAM_L.RAMB18_Y1.ZINIT_A[7] 27_217
BRAM_L.RAMB18_Y1.ZINIT_A[8] 27_201
BRAM_L.RAMB18_Y1.ZINIT_A[9] 27_185
BRAM_L.RAMB18_Y1.ZINIT_A[10] 27_305
BRAM_L.RAMB18_Y1.ZINIT_A[11] 27_289
BRAM_L.RAMB18_Y1.ZINIT_A[12] 27_273
BRAM_L.RAMB18_Y1.ZINIT_A[13] 27_257
BRAM_L.RAMB18_Y1.ZINIT_A[14] 27_225
BRAM_L.RAMB18_Y1.ZINIT_A[15] 27_209
BRAM_L.RAMB18_Y1.ZINIT_A[16] 27_193
BRAM_L.RAMB18_Y1.ZINIT_A[17] 27_177
BRAM_L.RAMB18_Y1.ZINIT_B[0] 27_255
BRAM_L.RAMB18_Y1.ZINIT_B[1] 27_247
BRAM_L.RAMB18_Y1.ZINIT_B[2] 27_319
BRAM_L.RAMB18_Y1.ZINIT_B[3] 27_303
BRAM_L.RAMB18_Y1.ZINIT_B[4] 27_287
BRAM_L.RAMB18_Y1.ZINIT_B[5] 27_271
BRAM_L.RAMB18_Y1.ZINIT_B[6] 27_239
BRAM_L.RAMB18_Y1.ZINIT_B[7] 27_223
BRAM_L.RAMB18_Y1.ZINIT_B[8] 27_207
BRAM_L.RAMB18_Y1.ZINIT_B[9] 27_191
BRAM_L.RAMB18_Y1.ZINIT_B[10] 27_311
BRAM_L.RAMB18_Y1.ZINIT_B[11] 27_295
BRAM_L.RAMB18_Y1.ZINIT_B[12] 27_279
BRAM_L.RAMB18_Y1.ZINIT_B[13] 27_263
BRAM_L.RAMB18_Y1.ZINIT_B[14] 27_231
BRAM_L.RAMB18_Y1.ZINIT_B[15] 27_215
BRAM_L.RAMB18_Y1.ZINIT_B[16] 27_199
BRAM_L.RAMB18_Y1.ZINIT_B[17] 27_183
BRAM_L.RAMB18_Y1.ZINV_CLKARDCLK 27_213 BRAM_L.RAMB18_Y1.ZINV_CLKARDCLK 27_213
BRAM_L.RAMB18_Y1.ZINV_CLKBWRCLK 27_211 BRAM_L.RAMB18_Y1.ZINV_CLKBWRCLK 27_211
BRAM_L.RAMB18_Y1.ZINV_ENARDEN 27_208 BRAM_L.RAMB18_Y1.ZINV_ENARDEN 27_208
@ -438,6 +408,42 @@ BRAM_L.RAMB18_Y1.ZINV_RSTRAMARSTRAM 27_204
BRAM_L.RAMB18_Y1.ZINV_RSTRAMB 27_203 BRAM_L.RAMB18_Y1.ZINV_RSTRAMB 27_203
BRAM_L.RAMB18_Y1.ZINV_RSTREGARSTREG 27_200 BRAM_L.RAMB18_Y1.ZINV_RSTREGARSTREG 27_200
BRAM_L.RAMB18_Y1.ZINV_RSTREGB 27_197 BRAM_L.RAMB18_Y1.ZINV_RSTREGB 27_197
BRAM_L.RAMB18_Y1.ZSRVAL_A[0] 27_250
BRAM_L.RAMB18_Y1.ZSRVAL_A[1] 27_242
BRAM_L.RAMB18_Y1.ZSRVAL_A[2] 27_314
BRAM_L.RAMB18_Y1.ZSRVAL_A[3] 27_298
BRAM_L.RAMB18_Y1.ZSRVAL_A[4] 27_282
BRAM_L.RAMB18_Y1.ZSRVAL_A[5] 27_266
BRAM_L.RAMB18_Y1.ZSRVAL_A[6] 27_234
BRAM_L.RAMB18_Y1.ZSRVAL_A[7] 27_218
BRAM_L.RAMB18_Y1.ZSRVAL_A[8] 27_202
BRAM_L.RAMB18_Y1.ZSRVAL_A[9] 27_186
BRAM_L.RAMB18_Y1.ZSRVAL_A[10] 27_306
BRAM_L.RAMB18_Y1.ZSRVAL_A[11] 27_290
BRAM_L.RAMB18_Y1.ZSRVAL_A[12] 27_274
BRAM_L.RAMB18_Y1.ZSRVAL_A[13] 27_258
BRAM_L.RAMB18_Y1.ZSRVAL_A[14] 27_226
BRAM_L.RAMB18_Y1.ZSRVAL_A[15] 27_210
BRAM_L.RAMB18_Y1.ZSRVAL_A[16] 27_194
BRAM_L.RAMB18_Y1.ZSRVAL_A[17] 27_178
BRAM_L.RAMB18_Y1.ZSRVAL_B[0] 27_254
BRAM_L.RAMB18_Y1.ZSRVAL_B[1] 27_246
BRAM_L.RAMB18_Y1.ZSRVAL_B[2] 27_318
BRAM_L.RAMB18_Y1.ZSRVAL_B[3] 27_302
BRAM_L.RAMB18_Y1.ZSRVAL_B[4] 27_286
BRAM_L.RAMB18_Y1.ZSRVAL_B[5] 27_270
BRAM_L.RAMB18_Y1.ZSRVAL_B[6] 27_238
BRAM_L.RAMB18_Y1.ZSRVAL_B[7] 27_222
BRAM_L.RAMB18_Y1.ZSRVAL_B[8] 27_206
BRAM_L.RAMB18_Y1.ZSRVAL_B[9] 27_190
BRAM_L.RAMB18_Y1.ZSRVAL_B[10] 27_310
BRAM_L.RAMB18_Y1.ZSRVAL_B[11] 27_294
BRAM_L.RAMB18_Y1.ZSRVAL_B[12] 27_278
BRAM_L.RAMB18_Y1.ZSRVAL_B[13] 27_262
BRAM_L.RAMB18_Y1.ZSRVAL_B[14] 27_230
BRAM_L.RAMB18_Y1.ZSRVAL_B[15] 27_214
BRAM_L.RAMB18_Y1.ZSRVAL_B[16] 27_198
BRAM_L.RAMB18_Y1.ZSRVAL_B[17] 27_182
BRAM_L.RAMB36.EN_ECC_READ 27_175 BRAM_L.RAMB36.EN_ECC_READ 27_175
BRAM_L.RAMB36.EN_ECC_WRITE 27_162 BRAM_L.RAMB36.EN_ECC_WRITE 27_162
BRAM_L.RAMB36.RAM_EXTENSION_A_LOWER 27_188 BRAM_L.RAMB36.RAM_EXTENSION_A_LOWER 27_188

73728
zynq7/segbits_bram_r.block_ram.db
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File diff suppressed because it is too large Load Diff

294
zynq7/segbits_bram_r.db
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@ -178,6 +178,8 @@ BRAM_R.BRAM_ADDRBWRADDRU13.BRAM_R_IMUX_ADDRBWRADDRU13 !26_141 !26_142 !26_143
BRAM_R.BRAM_ADDRBWRADDRU14.BRAM_CASCINBOT_ADDRBWRADDRU14 26_269 !26_270 26_271 BRAM_R.BRAM_ADDRBWRADDRU14.BRAM_CASCINBOT_ADDRBWRADDRU14 26_269 !26_270 26_271
BRAM_R.BRAM_ADDRBWRADDRU14.BRAM_CASCINTOP_ADDRBWRADDRU14 !26_269 26_270 26_271 BRAM_R.BRAM_ADDRBWRADDRU14.BRAM_CASCINTOP_ADDRBWRADDRU14 !26_269 26_270 26_271
BRAM_R.BRAM_ADDRBWRADDRU14.BRAM_R_IMUX_ADDRBWRADDRU14 !26_269 !26_270 !26_271 BRAM_R.BRAM_ADDRBWRADDRU14.BRAM_R_IMUX_ADDRBWRADDRU14 !26_269 !26_270 !26_271
BRAM_R.CASCOUT_ARD_ACTIVE 26_170
BRAM_R.CASCOUT_BWR_ACTIVE 26_172
BRAM_R.EN_SYN 27_171 BRAM_R.EN_SYN 27_171
BRAM_R.FIRST_WORD_FALL_THROUGH 27_170 BRAM_R.FIRST_WORD_FALL_THROUGH 27_170
BRAM_R.ZALMOST_EMPTY_OFFSET[0] 27_288 BRAM_R.ZALMOST_EMPTY_OFFSET[0] 27_288
@ -210,42 +212,6 @@ BRAM_R.RAMB18_Y0.DOA_REG 27_69
BRAM_R.RAMB18_Y0.DOB_REG 27_72 BRAM_R.RAMB18_Y0.DOB_REG 27_72
BRAM_R.RAMB18_Y0.FIFO_MODE 27_150 BRAM_R.RAMB18_Y0.FIFO_MODE 27_150
BRAM_R.RAMB18_Y0.IN_USE 27_99 27_100 BRAM_R.RAMB18_Y0.IN_USE 27_99 27_100
BRAM_R.RAMB18_Y0.INIT_A[0] 27_73
BRAM_R.RAMB18_Y0.INIT_A[1] 27_65
BRAM_R.RAMB18_Y0.INIT_A[2] 27_137
BRAM_R.RAMB18_Y0.INIT_A[3] 27_121
BRAM_R.RAMB18_Y0.INIT_A[4] 27_105
BRAM_R.RAMB18_Y0.INIT_A[5] 27_89
BRAM_R.RAMB18_Y0.INIT_A[6] 27_57
BRAM_R.RAMB18_Y0.INIT_A[7] 27_41
BRAM_R.RAMB18_Y0.INIT_A[8] 27_25
BRAM_R.RAMB18_Y0.INIT_A[9] 27_09
BRAM_R.RAMB18_Y0.INIT_A[10] 27_129
BRAM_R.RAMB18_Y0.INIT_A[11] 27_113
BRAM_R.RAMB18_Y0.INIT_A[12] 27_97
BRAM_R.RAMB18_Y0.INIT_A[13] 27_81
BRAM_R.RAMB18_Y0.INIT_A[14] 27_49
BRAM_R.RAMB18_Y0.INIT_A[15] 27_33
BRAM_R.RAMB18_Y0.INIT_A[16] 27_17
BRAM_R.RAMB18_Y0.INIT_A[17] 27_01
BRAM_R.RAMB18_Y0.INIT_B[0] 27_79
BRAM_R.RAMB18_Y0.INIT_B[1] 27_71
BRAM_R.RAMB18_Y0.INIT_B[2] 27_143
BRAM_R.RAMB18_Y0.INIT_B[3] 27_127
BRAM_R.RAMB18_Y0.INIT_B[4] 27_111
BRAM_R.RAMB18_Y0.INIT_B[5] 27_95
BRAM_R.RAMB18_Y0.INIT_B[6] 27_63
BRAM_R.RAMB18_Y0.INIT_B[7] 27_47
BRAM_R.RAMB18_Y0.INIT_B[8] 27_31
BRAM_R.RAMB18_Y0.INIT_B[9] 27_15
BRAM_R.RAMB18_Y0.INIT_B[10] 27_135
BRAM_R.RAMB18_Y0.INIT_B[11] 27_119
BRAM_R.RAMB18_Y0.INIT_B[12] 27_103
BRAM_R.RAMB18_Y0.INIT_B[13] 27_87
BRAM_R.RAMB18_Y0.INIT_B[14] 27_55
BRAM_R.RAMB18_Y0.INIT_B[15] 27_39
BRAM_R.RAMB18_Y0.INIT_B[16] 27_23
BRAM_R.RAMB18_Y0.INIT_B[17] 27_07
BRAM_R.RAMB18_Y0.RDADDR_COLLISION_HWCONFIG_DELAYED_WRITE !27_96 BRAM_R.RAMB18_Y0.RDADDR_COLLISION_HWCONFIG_DELAYED_WRITE !27_96
BRAM_R.RAMB18_Y0.RDADDR_COLLISION_HWCONFIG_PERFORMANCE 27_96 BRAM_R.RAMB18_Y0.RDADDR_COLLISION_HWCONFIG_PERFORMANCE 27_96
BRAM_R.RAMB18_Y0.READ_WIDTH_A_1 !27_35 !27_36 !27_37 BRAM_R.RAMB18_Y0.READ_WIDTH_A_1 !27_35 !27_36 !27_37
@ -262,42 +228,8 @@ BRAM_R.RAMB18_Y0.RSTREG_PRIORITY_A_REGCE 27_124
BRAM_R.RAMB18_Y0.RSTREG_PRIORITY_A_RSTREG !27_124 BRAM_R.RAMB18_Y0.RSTREG_PRIORITY_A_RSTREG !27_124
BRAM_R.RAMB18_Y0.RSTREG_PRIORITY_B_REGCE 27_125 BRAM_R.RAMB18_Y0.RSTREG_PRIORITY_B_REGCE 27_125
BRAM_R.RAMB18_Y0.RSTREG_PRIORITY_B_RSTREG !27_125 BRAM_R.RAMB18_Y0.RSTREG_PRIORITY_B_RSTREG !27_125
BRAM_R.RAMB18_Y0.SRVAL_A[0] 27_74 BRAM_R.RAMB18_Y0.SDP_READ_WIDTH_36 27_48
BRAM_R.RAMB18_Y0.SRVAL_A[1] 27_66 BRAM_R.RAMB18_Y0.SDP_WRITE_WIDTH_36 27_40
BRAM_R.RAMB18_Y0.SRVAL_A[2] 27_138
BRAM_R.RAMB18_Y0.SRVAL_A[3] 27_122
BRAM_R.RAMB18_Y0.SRVAL_A[4] 27_106
BRAM_R.RAMB18_Y0.SRVAL_A[5] 27_90
BRAM_R.RAMB18_Y0.SRVAL_A[6] 27_58
BRAM_R.RAMB18_Y0.SRVAL_A[7] 27_42
BRAM_R.RAMB18_Y0.SRVAL_A[8] 27_26
BRAM_R.RAMB18_Y0.SRVAL_A[9] 27_10
BRAM_R.RAMB18_Y0.SRVAL_A[10] 27_130
BRAM_R.RAMB18_Y0.SRVAL_A[11] 27_114
BRAM_R.RAMB18_Y0.SRVAL_A[12] 27_98
BRAM_R.RAMB18_Y0.SRVAL_A[13] 27_82
BRAM_R.RAMB18_Y0.SRVAL_A[14] 27_50
BRAM_R.RAMB18_Y0.SRVAL_A[15] 27_34
BRAM_R.RAMB18_Y0.SRVAL_A[16] 27_18
BRAM_R.RAMB18_Y0.SRVAL_A[17] 27_02
BRAM_R.RAMB18_Y0.SRVAL_B[0] 27_78
BRAM_R.RAMB18_Y0.SRVAL_B[1] 27_70
BRAM_R.RAMB18_Y0.SRVAL_B[2] 27_142
BRAM_R.RAMB18_Y0.SRVAL_B[3] 27_126
BRAM_R.RAMB18_Y0.SRVAL_B[4] 27_110
BRAM_R.RAMB18_Y0.SRVAL_B[5] 27_94
BRAM_R.RAMB18_Y0.SRVAL_B[6] 27_62
BRAM_R.RAMB18_Y0.SRVAL_B[7] 27_46
BRAM_R.RAMB18_Y0.SRVAL_B[8] 27_30
BRAM_R.RAMB18_Y0.SRVAL_B[9] 27_14
BRAM_R.RAMB18_Y0.SRVAL_B[10] 27_134
BRAM_R.RAMB18_Y0.SRVAL_B[11] 27_118
BRAM_R.RAMB18_Y0.SRVAL_B[12] 27_102
BRAM_R.RAMB18_Y0.SRVAL_B[13] 27_86
BRAM_R.RAMB18_Y0.SRVAL_B[14] 27_54
BRAM_R.RAMB18_Y0.SRVAL_B[15] 27_38
BRAM_R.RAMB18_Y0.SRVAL_B[16] 27_22
BRAM_R.RAMB18_Y0.SRVAL_B[17] 27_06
BRAM_R.RAMB18_Y0.WRITE_MODE_A_NO_CHANGE 27_64 BRAM_R.RAMB18_Y0.WRITE_MODE_A_NO_CHANGE 27_64
BRAM_R.RAMB18_Y0.WRITE_MODE_A_READ_FIRST 27_56 BRAM_R.RAMB18_Y0.WRITE_MODE_A_READ_FIRST 27_56
BRAM_R.RAMB18_Y0.WRITE_MODE_B_NO_CHANGE 27_68 BRAM_R.RAMB18_Y0.WRITE_MODE_B_NO_CHANGE 27_68
@ -312,6 +244,42 @@ BRAM_R.RAMB18_Y0.WRITE_WIDTH_B_2 27_59 !27_60 !27_61
BRAM_R.RAMB18_Y0.WRITE_WIDTH_B_4 !27_59 27_60 !27_61 BRAM_R.RAMB18_Y0.WRITE_WIDTH_B_4 !27_59 27_60 !27_61
BRAM_R.RAMB18_Y0.WRITE_WIDTH_B_9 27_59 27_60 !27_61 BRAM_R.RAMB18_Y0.WRITE_WIDTH_B_9 27_59 27_60 !27_61
BRAM_R.RAMB18_Y0.WRITE_WIDTH_B_18 !27_59 !27_60 27_61 BRAM_R.RAMB18_Y0.WRITE_WIDTH_B_18 !27_59 !27_60 27_61
BRAM_R.RAMB18_Y0.ZINIT_A[0] 27_73
BRAM_R.RAMB18_Y0.ZINIT_A[1] 27_65
BRAM_R.RAMB18_Y0.ZINIT_A[2] 27_137
BRAM_R.RAMB18_Y0.ZINIT_A[3] 27_121
BRAM_R.RAMB18_Y0.ZINIT_A[4] 27_105
BRAM_R.RAMB18_Y0.ZINIT_A[5] 27_89
BRAM_R.RAMB18_Y0.ZINIT_A[6] 27_57
BRAM_R.RAMB18_Y0.ZINIT_A[7] 27_41
BRAM_R.RAMB18_Y0.ZINIT_A[8] 27_25
BRAM_R.RAMB18_Y0.ZINIT_A[9] 27_09
BRAM_R.RAMB18_Y0.ZINIT_A[10] 27_129
BRAM_R.RAMB18_Y0.ZINIT_A[11] 27_113
BRAM_R.RAMB18_Y0.ZINIT_A[12] 27_97
BRAM_R.RAMB18_Y0.ZINIT_A[13] 27_81
BRAM_R.RAMB18_Y0.ZINIT_A[14] 27_49
BRAM_R.RAMB18_Y0.ZINIT_A[15] 27_33
BRAM_R.RAMB18_Y0.ZINIT_A[16] 27_17
BRAM_R.RAMB18_Y0.ZINIT_A[17] 27_01
BRAM_R.RAMB18_Y0.ZINIT_B[0] 27_79
BRAM_R.RAMB18_Y0.ZINIT_B[1] 27_71
BRAM_R.RAMB18_Y0.ZINIT_B[2] 27_143
BRAM_R.RAMB18_Y0.ZINIT_B[3] 27_127
BRAM_R.RAMB18_Y0.ZINIT_B[4] 27_111
BRAM_R.RAMB18_Y0.ZINIT_B[5] 27_95
BRAM_R.RAMB18_Y0.ZINIT_B[6] 27_63
BRAM_R.RAMB18_Y0.ZINIT_B[7] 27_47
BRAM_R.RAMB18_Y0.ZINIT_B[8] 27_31
BRAM_R.RAMB18_Y0.ZINIT_B[9] 27_15
BRAM_R.RAMB18_Y0.ZINIT_B[10] 27_135
BRAM_R.RAMB18_Y0.ZINIT_B[11] 27_119
BRAM_R.RAMB18_Y0.ZINIT_B[12] 27_103
BRAM_R.RAMB18_Y0.ZINIT_B[13] 27_87
BRAM_R.RAMB18_Y0.ZINIT_B[14] 27_55
BRAM_R.RAMB18_Y0.ZINIT_B[15] 27_39
BRAM_R.RAMB18_Y0.ZINIT_B[16] 27_23
BRAM_R.RAMB18_Y0.ZINIT_B[17] 27_07
BRAM_R.RAMB18_Y0.ZINV_CLKARDCLK 27_107 BRAM_R.RAMB18_Y0.ZINV_CLKARDCLK 27_107
BRAM_R.RAMB18_Y0.ZINV_CLKBWRCLK 27_109 BRAM_R.RAMB18_Y0.ZINV_CLKBWRCLK 27_109
BRAM_R.RAMB18_Y0.ZINV_ENARDEN 27_112 BRAM_R.RAMB18_Y0.ZINV_ENARDEN 27_112
@ -322,46 +290,46 @@ BRAM_R.RAMB18_Y0.ZINV_RSTRAMARSTRAM 27_116
BRAM_R.RAMB18_Y0.ZINV_RSTRAMB 27_117 BRAM_R.RAMB18_Y0.ZINV_RSTRAMB 27_117
BRAM_R.RAMB18_Y0.ZINV_RSTREGARSTREG 27_120 BRAM_R.RAMB18_Y0.ZINV_RSTREGARSTREG 27_120
BRAM_R.RAMB18_Y0.ZINV_RSTREGB 27_123 BRAM_R.RAMB18_Y0.ZINV_RSTREGB 27_123
BRAM_R.RAMB18_Y0.ZSRVAL_A[0] 27_74
BRAM_R.RAMB18_Y0.ZSRVAL_A[1] 27_66
BRAM_R.RAMB18_Y0.ZSRVAL_A[2] 27_138
BRAM_R.RAMB18_Y0.ZSRVAL_A[3] 27_122
BRAM_R.RAMB18_Y0.ZSRVAL_A[4] 27_106
BRAM_R.RAMB18_Y0.ZSRVAL_A[5] 27_90
BRAM_R.RAMB18_Y0.ZSRVAL_A[6] 27_58
BRAM_R.RAMB18_Y0.ZSRVAL_A[7] 27_42
BRAM_R.RAMB18_Y0.ZSRVAL_A[8] 27_26
BRAM_R.RAMB18_Y0.ZSRVAL_A[9] 27_10
BRAM_R.RAMB18_Y0.ZSRVAL_A[10] 27_130
BRAM_R.RAMB18_Y0.ZSRVAL_A[11] 27_114
BRAM_R.RAMB18_Y0.ZSRVAL_A[12] 27_98
BRAM_R.RAMB18_Y0.ZSRVAL_A[13] 27_82
BRAM_R.RAMB18_Y0.ZSRVAL_A[14] 27_50
BRAM_R.RAMB18_Y0.ZSRVAL_A[15] 27_34
BRAM_R.RAMB18_Y0.ZSRVAL_A[16] 27_18
BRAM_R.RAMB18_Y0.ZSRVAL_A[17] 27_02
BRAM_R.RAMB18_Y0.ZSRVAL_B[0] 27_78
BRAM_R.RAMB18_Y0.ZSRVAL_B[1] 27_70
BRAM_R.RAMB18_Y0.ZSRVAL_B[2] 27_142
BRAM_R.RAMB18_Y0.ZSRVAL_B[3] 27_126
BRAM_R.RAMB18_Y0.ZSRVAL_B[4] 27_110
BRAM_R.RAMB18_Y0.ZSRVAL_B[5] 27_94
BRAM_R.RAMB18_Y0.ZSRVAL_B[6] 27_62
BRAM_R.RAMB18_Y0.ZSRVAL_B[7] 27_46
BRAM_R.RAMB18_Y0.ZSRVAL_B[8] 27_30
BRAM_R.RAMB18_Y0.ZSRVAL_B[9] 27_14
BRAM_R.RAMB18_Y0.ZSRVAL_B[10] 27_134
BRAM_R.RAMB18_Y0.ZSRVAL_B[11] 27_118
BRAM_R.RAMB18_Y0.ZSRVAL_B[12] 27_102
BRAM_R.RAMB18_Y0.ZSRVAL_B[13] 27_86
BRAM_R.RAMB18_Y0.ZSRVAL_B[14] 27_54
BRAM_R.RAMB18_Y0.ZSRVAL_B[15] 27_38
BRAM_R.RAMB18_Y0.ZSRVAL_B[16] 27_22
BRAM_R.RAMB18_Y0.ZSRVAL_B[17] 27_06
BRAM_R.RAMB18_Y1.DOA_REG 27_251 BRAM_R.RAMB18_Y1.DOA_REG 27_251
BRAM_R.RAMB18_Y1.DOB_REG 27_248 BRAM_R.RAMB18_Y1.DOB_REG 27_248
BRAM_R.RAMB18_Y1.FIFO_MODE 27_169 BRAM_R.RAMB18_Y1.FIFO_MODE 27_169
BRAM_R.RAMB18_Y1.IN_USE 27_220 27_221 BRAM_R.RAMB18_Y1.IN_USE 27_220 27_221
BRAM_R.RAMB18_Y1.INIT_A[0] 27_249
BRAM_R.RAMB18_Y1.INIT_A[1] 27_241
BRAM_R.RAMB18_Y1.INIT_A[2] 27_313
BRAM_R.RAMB18_Y1.INIT_A[3] 27_297
BRAM_R.RAMB18_Y1.INIT_A[4] 27_281
BRAM_R.RAMB18_Y1.INIT_A[5] 27_265
BRAM_R.RAMB18_Y1.INIT_A[6] 27_233
BRAM_R.RAMB18_Y1.INIT_A[7] 27_217
BRAM_R.RAMB18_Y1.INIT_A[8] 27_201
BRAM_R.RAMB18_Y1.INIT_A[9] 27_185
BRAM_R.RAMB18_Y1.INIT_A[10] 27_305
BRAM_R.RAMB18_Y1.INIT_A[11] 27_289
BRAM_R.RAMB18_Y1.INIT_A[12] 27_273
BRAM_R.RAMB18_Y1.INIT_A[13] 27_257
BRAM_R.RAMB18_Y1.INIT_A[14] 27_225
BRAM_R.RAMB18_Y1.INIT_A[15] 27_209
BRAM_R.RAMB18_Y1.INIT_A[16] 27_193
BRAM_R.RAMB18_Y1.INIT_A[17] 27_177
BRAM_R.RAMB18_Y1.INIT_B[0] 27_255
BRAM_R.RAMB18_Y1.INIT_B[1] 27_247
BRAM_R.RAMB18_Y1.INIT_B[2] 27_319
BRAM_R.RAMB18_Y1.INIT_B[3] 27_303
BRAM_R.RAMB18_Y1.INIT_B[4] 27_287
BRAM_R.RAMB18_Y1.INIT_B[5] 27_271
BRAM_R.RAMB18_Y1.INIT_B[6] 27_239
BRAM_R.RAMB18_Y1.INIT_B[7] 27_223
BRAM_R.RAMB18_Y1.INIT_B[8] 27_207
BRAM_R.RAMB18_Y1.INIT_B[9] 27_191
BRAM_R.RAMB18_Y1.INIT_B[10] 27_311
BRAM_R.RAMB18_Y1.INIT_B[11] 27_295
BRAM_R.RAMB18_Y1.INIT_B[12] 27_279
BRAM_R.RAMB18_Y1.INIT_B[13] 27_263
BRAM_R.RAMB18_Y1.INIT_B[14] 27_231
BRAM_R.RAMB18_Y1.INIT_B[15] 27_215
BRAM_R.RAMB18_Y1.INIT_B[16] 27_199
BRAM_R.RAMB18_Y1.INIT_B[17] 27_183
BRAM_R.RAMB18_Y1.RDADDR_COLLISION_HWCONFIG_DELAYED_WRITE !27_224 BRAM_R.RAMB18_Y1.RDADDR_COLLISION_HWCONFIG_DELAYED_WRITE !27_224
BRAM_R.RAMB18_Y1.RDADDR_COLLISION_HWCONFIG_PERFORMANCE 27_224 BRAM_R.RAMB18_Y1.RDADDR_COLLISION_HWCONFIG_PERFORMANCE 27_224
BRAM_R.RAMB18_Y1.READ_WIDTH_A_1 !27_283 !27_284 !27_285 BRAM_R.RAMB18_Y1.READ_WIDTH_A_1 !27_283 !27_284 !27_285
@ -378,42 +346,8 @@ BRAM_R.RAMB18_Y1.RSTREG_PRIORITY_A_REGCE 27_196
BRAM_R.RAMB18_Y1.RSTREG_PRIORITY_A_RSTREG !27_196 BRAM_R.RAMB18_Y1.RSTREG_PRIORITY_A_RSTREG !27_196
BRAM_R.RAMB18_Y1.RSTREG_PRIORITY_B_REGCE 27_195 BRAM_R.RAMB18_Y1.RSTREG_PRIORITY_B_REGCE 27_195
BRAM_R.RAMB18_Y1.RSTREG_PRIORITY_B_RSTREG !27_195 BRAM_R.RAMB18_Y1.RSTREG_PRIORITY_B_RSTREG !27_195
BRAM_R.RAMB18_Y1.SRVAL_A[0] 27_250 BRAM_R.RAMB18_Y1.SDP_READ_WIDTH_36 27_272
BRAM_R.RAMB18_Y1.SRVAL_A[1] 27_242 BRAM_R.RAMB18_Y1.SDP_WRITE_WIDTH_36 27_280
BRAM_R.RAMB18_Y1.SRVAL_A[2] 27_314
BRAM_R.RAMB18_Y1.SRVAL_A[3] 27_298
BRAM_R.RAMB18_Y1.SRVAL_A[4] 27_282
BRAM_R.RAMB18_Y1.SRVAL_A[5] 27_266
BRAM_R.RAMB18_Y1.SRVAL_A[6] 27_234
BRAM_R.RAMB18_Y1.SRVAL_A[7] 27_218
BRAM_R.RAMB18_Y1.SRVAL_A[8] 27_202
BRAM_R.RAMB18_Y1.SRVAL_A[9] 27_186
BRAM_R.RAMB18_Y1.SRVAL_A[10] 27_306
BRAM_R.RAMB18_Y1.SRVAL_A[11] 27_290
BRAM_R.RAMB18_Y1.SRVAL_A[12] 27_274
BRAM_R.RAMB18_Y1.SRVAL_A[13] 27_258
BRAM_R.RAMB18_Y1.SRVAL_A[14] 27_226
BRAM_R.RAMB18_Y1.SRVAL_A[15] 27_210
BRAM_R.RAMB18_Y1.SRVAL_A[16] 27_194
BRAM_R.RAMB18_Y1.SRVAL_A[17] 27_178
BRAM_R.RAMB18_Y1.SRVAL_B[0] 27_254
BRAM_R.RAMB18_Y1.SRVAL_B[1] 27_246
BRAM_R.RAMB18_Y1.SRVAL_B[2] 27_318
BRAM_R.RAMB18_Y1.SRVAL_B[3] 27_302
BRAM_R.RAMB18_Y1.SRVAL_B[4] 27_286
BRAM_R.RAMB18_Y1.SRVAL_B[5] 27_270
BRAM_R.RAMB18_Y1.SRVAL_B[6] 27_238
BRAM_R.RAMB18_Y1.SRVAL_B[7] 27_222
BRAM_R.RAMB18_Y1.SRVAL_B[8] 27_206
BRAM_R.RAMB18_Y1.SRVAL_B[9] 27_190
BRAM_R.RAMB18_Y1.SRVAL_B[10] 27_310
BRAM_R.RAMB18_Y1.SRVAL_B[11] 27_294
BRAM_R.RAMB18_Y1.SRVAL_B[12] 27_278
BRAM_R.RAMB18_Y1.SRVAL_B[13] 27_262
BRAM_R.RAMB18_Y1.SRVAL_B[14] 27_230
BRAM_R.RAMB18_Y1.SRVAL_B[15] 27_214
BRAM_R.RAMB18_Y1.SRVAL_B[16] 27_198
BRAM_R.RAMB18_Y1.SRVAL_B[17] 27_182
BRAM_R.RAMB18_Y1.WRITE_MODE_A_NO_CHANGE 27_256 BRAM_R.RAMB18_Y1.WRITE_MODE_A_NO_CHANGE 27_256
BRAM_R.RAMB18_Y1.WRITE_MODE_A_READ_FIRST 27_264 BRAM_R.RAMB18_Y1.WRITE_MODE_A_READ_FIRST 27_264
BRAM_R.RAMB18_Y1.WRITE_MODE_B_NO_CHANGE 27_252 BRAM_R.RAMB18_Y1.WRITE_MODE_B_NO_CHANGE 27_252
@ -428,6 +362,42 @@ BRAM_R.RAMB18_Y1.WRITE_WIDTH_B_2 !27_259 !27_260 27_261
BRAM_R.RAMB18_Y1.WRITE_WIDTH_B_4 !27_259 27_260 !27_261 BRAM_R.RAMB18_Y1.WRITE_WIDTH_B_4 !27_259 27_260 !27_261
BRAM_R.RAMB18_Y1.WRITE_WIDTH_B_9 !27_259 27_260 27_261 BRAM_R.RAMB18_Y1.WRITE_WIDTH_B_9 !27_259 27_260 27_261
BRAM_R.RAMB18_Y1.WRITE_WIDTH_B_18 27_259 !27_260 !27_261 BRAM_R.RAMB18_Y1.WRITE_WIDTH_B_18 27_259 !27_260 !27_261
BRAM_R.RAMB18_Y1.ZINIT_A[0] 27_249
BRAM_R.RAMB18_Y1.ZINIT_A[1] 27_241
BRAM_R.RAMB18_Y1.ZINIT_A[2] 27_313
BRAM_R.RAMB18_Y1.ZINIT_A[3] 27_297
BRAM_R.RAMB18_Y1.ZINIT_A[4] 27_281
BRAM_R.RAMB18_Y1.ZINIT_A[5] 27_265
BRAM_R.RAMB18_Y1.ZINIT_A[6] 27_233
BRAM_R.RAMB18_Y1.ZINIT_A[7] 27_217
BRAM_R.RAMB18_Y1.ZINIT_A[8] 27_201
BRAM_R.RAMB18_Y1.ZINIT_A[9] 27_185
BRAM_R.RAMB18_Y1.ZINIT_A[10] 27_305
BRAM_R.RAMB18_Y1.ZINIT_A[11] 27_289
BRAM_R.RAMB18_Y1.ZINIT_A[12] 27_273
BRAM_R.RAMB18_Y1.ZINIT_A[13] 27_257
BRAM_R.RAMB18_Y1.ZINIT_A[14] 27_225
BRAM_R.RAMB18_Y1.ZINIT_A[15] 27_209
BRAM_R.RAMB18_Y1.ZINIT_A[16] 27_193
BRAM_R.RAMB18_Y1.ZINIT_A[17] 27_177
BRAM_R.RAMB18_Y1.ZINIT_B[0] 27_255
BRAM_R.RAMB18_Y1.ZINIT_B[1] 27_247
BRAM_R.RAMB18_Y1.ZINIT_B[2] 27_319
BRAM_R.RAMB18_Y1.ZINIT_B[3] 27_303
BRAM_R.RAMB18_Y1.ZINIT_B[4] 27_287
BRAM_R.RAMB18_Y1.ZINIT_B[5] 27_271
BRAM_R.RAMB18_Y1.ZINIT_B[6] 27_239
BRAM_R.RAMB18_Y1.ZINIT_B[7] 27_223
BRAM_R.RAMB18_Y1.ZINIT_B[8] 27_207
BRAM_R.RAMB18_Y1.ZINIT_B[9] 27_191
BRAM_R.RAMB18_Y1.ZINIT_B[10] 27_311
BRAM_R.RAMB18_Y1.ZINIT_B[11] 27_295
BRAM_R.RAMB18_Y1.ZINIT_B[12] 27_279
BRAM_R.RAMB18_Y1.ZINIT_B[13] 27_263
BRAM_R.RAMB18_Y1.ZINIT_B[14] 27_231
BRAM_R.RAMB18_Y1.ZINIT_B[15] 27_215
BRAM_R.RAMB18_Y1.ZINIT_B[16] 27_199
BRAM_R.RAMB18_Y1.ZINIT_B[17] 27_183
BRAM_R.RAMB18_Y1.ZINV_CLKARDCLK 27_213 BRAM_R.RAMB18_Y1.ZINV_CLKARDCLK 27_213
BRAM_R.RAMB18_Y1.ZINV_CLKBWRCLK 27_211 BRAM_R.RAMB18_Y1.ZINV_CLKBWRCLK 27_211
BRAM_R.RAMB18_Y1.ZINV_ENARDEN 27_208 BRAM_R.RAMB18_Y1.ZINV_ENARDEN 27_208
@ -438,6 +408,42 @@ BRAM_R.RAMB18_Y1.ZINV_RSTRAMARSTRAM 27_204
BRAM_R.RAMB18_Y1.ZINV_RSTRAMB 27_203 BRAM_R.RAMB18_Y1.ZINV_RSTRAMB 27_203
BRAM_R.RAMB18_Y1.ZINV_RSTREGARSTREG 27_200 BRAM_R.RAMB18_Y1.ZINV_RSTREGARSTREG 27_200
BRAM_R.RAMB18_Y1.ZINV_RSTREGB 27_197 BRAM_R.RAMB18_Y1.ZINV_RSTREGB 27_197
BRAM_R.RAMB18_Y1.ZSRVAL_A[0] 27_250
BRAM_R.RAMB18_Y1.ZSRVAL_A[1] 27_242
BRAM_R.RAMB18_Y1.ZSRVAL_A[2] 27_314
BRAM_R.RAMB18_Y1.ZSRVAL_A[3] 27_298
BRAM_R.RAMB18_Y1.ZSRVAL_A[4] 27_282
BRAM_R.RAMB18_Y1.ZSRVAL_A[5] 27_266
BRAM_R.RAMB18_Y1.ZSRVAL_A[6] 27_234
BRAM_R.RAMB18_Y1.ZSRVAL_A[7] 27_218
BRAM_R.RAMB18_Y1.ZSRVAL_A[8] 27_202
BRAM_R.RAMB18_Y1.ZSRVAL_A[9] 27_186
BRAM_R.RAMB18_Y1.ZSRVAL_A[10] 27_306
BRAM_R.RAMB18_Y1.ZSRVAL_A[11] 27_290
BRAM_R.RAMB18_Y1.ZSRVAL_A[12] 27_274
BRAM_R.RAMB18_Y1.ZSRVAL_A[13] 27_258
BRAM_R.RAMB18_Y1.ZSRVAL_A[14] 27_226
BRAM_R.RAMB18_Y1.ZSRVAL_A[15] 27_210
BRAM_R.RAMB18_Y1.ZSRVAL_A[16] 27_194
BRAM_R.RAMB18_Y1.ZSRVAL_A[17] 27_178
BRAM_R.RAMB18_Y1.ZSRVAL_B[0] 27_254
BRAM_R.RAMB18_Y1.ZSRVAL_B[1] 27_246
BRAM_R.RAMB18_Y1.ZSRVAL_B[2] 27_318
BRAM_R.RAMB18_Y1.ZSRVAL_B[3] 27_302
BRAM_R.RAMB18_Y1.ZSRVAL_B[4] 27_286
BRAM_R.RAMB18_Y1.ZSRVAL_B[5] 27_270
BRAM_R.RAMB18_Y1.ZSRVAL_B[6] 27_238
BRAM_R.RAMB18_Y1.ZSRVAL_B[7] 27_222
BRAM_R.RAMB18_Y1.ZSRVAL_B[8] 27_206
BRAM_R.RAMB18_Y1.ZSRVAL_B[9] 27_190
BRAM_R.RAMB18_Y1.ZSRVAL_B[10] 27_310
BRAM_R.RAMB18_Y1.ZSRVAL_B[11] 27_294
BRAM_R.RAMB18_Y1.ZSRVAL_B[12] 27_278
BRAM_R.RAMB18_Y1.ZSRVAL_B[13] 27_262
BRAM_R.RAMB18_Y1.ZSRVAL_B[14] 27_230
BRAM_R.RAMB18_Y1.ZSRVAL_B[15] 27_214
BRAM_R.RAMB18_Y1.ZSRVAL_B[16] 27_198
BRAM_R.RAMB18_Y1.ZSRVAL_B[17] 27_182
BRAM_R.RAMB36.EN_ECC_READ 27_175 BRAM_R.RAMB36.EN_ECC_READ 27_175
BRAM_R.RAMB36.EN_ECC_WRITE 27_162 BRAM_R.RAMB36.EN_ECC_WRITE 27_162
BRAM_R.RAMB36.RAM_EXTENSION_A_LOWER 27_188 BRAM_R.RAMB36.RAM_EXTENSION_A_LOWER 27_188

125
zynq7/segbits_liob33.db Normal file
View File

@ -0,0 +1,125 @@
LIOB33.IOB_Y0.IBUFDISABLE.I 38_82
LIOB33.IOB_Y0.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE 27_98
LIOB33.IOB_Y0.IFF.DDR_CLK_EDGE.SAME_EDGE 26_99
LIOB33.IOB_Y0.IFF.SRTYPE.SYNC 29_67
LIOB33.IOB_Y0.IFF.ZINIT_Q1 28_72
LIOB33.IOB_Y0.IFF.ZINIT_Q2 28_76
LIOB33.IOB_Y0.IFF.ZINIT_Q3 28_86
LIOB33.IOB_Y0.IFF.ZINIT_Q4 28_94
LIOB33.IOB_Y0.IFF.ZINV_C 28_126 29_123 29_125
LIOB33.IOB_Y0.IFF.ZINV_OCLK 28_64
LIOB33.IOB_Y0.IFF.ZSRVAL_Q1 29_71
LIOB33.IOB_Y0.IFF.ZSRVAL_Q2 29_75
LIOB33.IOB_Y0.IFF.ZSRVAL_Q3 29_85
LIOB33.IOB_Y0.IFF.ZSRVAL_Q4 29_93
LIOB33.IOB_Y0.INOUT 30_67
LIOB33.IOB_Y0.INTERMDISABLE.I 39_89
LIOB33.IOB_Y0.ISERDES.DATA_RATE.SDR 27_108
LIOB33.IOB_Y0.ISERDES.INTERFACE_TYPE.MEMORY_DDR3 26_117
LIOB33.IOB_Y0.ISERDES.INTERFACE_TYPE.OVERSAMPLE 26_115
LIOB33.IOB_Y0.LVTTL.DRIVE.I24 31_86 32_66 33_111 38_64 !38_112 !38_118 38_126 39_65 !39_95 39_117 39_119 !39_125 !39_127
LIOB33.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE !31_92
LIOB33.IOB_Y0.ODDR.DDR_CLK_EDGE.SAME_EDGE 31_92
LIOB33.IOB_Y0.OFF.ZINIT_Q 33_97
LIOB33.IOB_Y0.OSERDESE.DATA_RATE_TQ.BUF 32_66
LIOB33.IOB_Y0.OSERDESE.DATA_RATE_TQ.DDR 32_70
LIOB33.IOB_Y0.OSERDESE.DATA_RATE_TQ.SDR 33_69
LIOB33.IOB_Y0.OSERDESE.DATA_WIDTH.2 30_127
LIOB33.IOB_Y0.OSERDESE.DATA_WIDTH.3 31_126
LIOB33.IOB_Y0.OSERDESE.DATA_WIDTH.4 31_124
LIOB33.IOB_Y0.OSERDESE.DATA_WIDTH.5 30_121
LIOB33.IOB_Y0.OSERDESE.DATA_WIDTH.6 31_120
LIOB33.IOB_Y0.OSERDESE.DATA_WIDTH.7 30_123
LIOB33.IOB_Y0.OSERDESE.DATA_WIDTH.8 31_116
LIOB33.IOB_Y0.PULLTYPE.KEEPER 38_92 38_94 !39_93
LIOB33.IOB_Y0.PULLTYPE.NONE !38_92 38_94 !39_93
LIOB33.IOB_Y0.PULLTYPE.PULLDOWN !38_92 !38_94 !39_93
LIOB33.IOB_Y0.PULLTYPE.PULLUP !38_92 38_94 39_93
LIOB33.IOB_Y0.SLEW.FAST !38_106 !38_110 !39_105 !39_109
LIOB33.IOB_Y0.SLEW.SLOW 38_106 38_110 39_105 39_109
LIOB33.IOB_Y0.TFF.ZINIT_Q 30_75
LIOB33.IOB_Y0.ZINV_D 29_109
LIOB33.IOB_Y0.IDELMUXE3.0 29_101
LIOB33.IOB_Y0.IFFDELMUXE3.0 28_116
LIOB33.IOB_Y0.LVCMOS12.DRIVE.I4 31_86 32_66 33_111 38_64 38_112 38_118 38_126 39_65 39_95 !39_117 !39_119 39_125 !39_127
LIOB33.IOB_Y0.LVCMOS12.DRIVE.I8 31_86 32_66 33_111 38_64 38_112 !38_118 !38_126 39_65 39_95 !39_117 39_119 !39_125 !39_127
LIOB33.IOB_Y0.LVCMOS12.DRIVE.I12 31_86 32_66 33_111 38_64 38_112 !38_118 38_126 39_65 39_95 !39_117 !39_119 !39_125 39_127
LIOB33.IOB_Y0.LVCMOS15.DRIVE.I8 31_86 32_66 33_111 38_64 38_112 !38_118 38_126 39_65 39_95 !39_117 39_119 39_125 39_127
LIOB33.IOB_Y0.LVCMOS15.DRIVE.I12 31_86 32_66 33_111 38_64 38_112 !38_118 !38_126 39_65 39_95 !39_117 !39_119 !39_125 39_127
LIOB33.IOB_Y0.LVCMOS15.DRIVE.I16 31_86 32_66 33_111 38_64 38_112 38_118 38_126 39_65 39_95 39_117 !39_119 !39_125 39_127
LIOB33.IOB_Y0.LVCMOS15_LVCMOS18.DRIVE.I4 31_86 32_66 33_111 38_64 38_112 38_118 !38_126 39_65 39_95 !39_117 !39_119 39_125 39_127
LIOB33.IOB_Y0.LVCMOS18.DRIVE.I12_I8 31_86 32_66 33_111 38_64 38_112 !38_118 38_126 39_65 39_95 !39_117 39_119 39_125 !39_127
LIOB33.IOB_Y0.LVCMOS18.DRIVE.I16 31_86 32_66 33_111 38_64 38_112 !38_118 38_126 39_65 39_95 !39_117 !39_119 39_125 39_127
LIOB33.IOB_Y0.LVCMOS18.DRIVE.I24 31_86 32_66 33_111 38_64 38_112 !38_118 38_126 39_65 39_95 39_117 39_119 !39_125 !39_127
LIOB33.IOB_Y0.LVCMOS25.DRIVE.I4 31_86 32_66 33_111 38_64 38_112 38_118 !38_126 39_65 !39_95 !39_117 !39_119 39_125 39_127
LIOB33.IOB_Y0.LVCMOS25.DRIVE.I8 31_86 32_66 33_111 38_64 38_112 !38_118 !38_126 39_65 !39_95 !39_117 39_119 !39_125 !39_127
LIOB33.IOB_Y0.LVCMOS25.DRIVE.I12 31_86 32_66 33_111 38_64 38_112 !38_118 !38_126 39_65 !39_95 !39_117 !39_119 !39_125 !39_127
LIOB33.IOB_Y0.LVCMOS25.DRIVE.I16 31_86 32_66 33_111 38_64 38_112 38_118 38_126 39_65 !39_95 39_117 !39_119 !39_125 !39_127
LIOB33.IOB_Y0.LVCMOS33.DRIVE.I16 31_86 32_66 33_111 38_64 !38_112 38_118 !38_126 39_65 !39_95 39_117 !39_119 !39_125 39_127
LIOB33.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I4 31_86 32_66 33_111 38_64 !38_112 38_118 !38_126 39_65 !39_95 !39_117 !39_119 39_125 39_127
LIOB33.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I12_I8 31_86 32_66 33_111 38_64 !38_112 !38_118 38_126 39_65 !39_95 !39_117 39_119 39_125 !39_127
LIOB33.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I12_I16 31_86 32_66 33_111 38_64 !38_112 !38_118 38_126 39_65 !39_95 !39_117 !39_119 39_125 39_127
LIOB33.IOB_Y1.IBUFDISABLE.I 39_45
LIOB33.IOB_Y1.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE 26_29
LIOB33.IOB_Y1.IFF.DDR_CLK_EDGE.SAME_EDGE 27_28
LIOB33.IOB_Y1.IFF.SRTYPE.SYNC 28_60
LIOB33.IOB_Y1.IFF.ZINIT_Q1 29_55
LIOB33.IOB_Y1.IFF.ZINIT_Q2 29_51
LIOB33.IOB_Y1.IFF.ZINIT_Q3 29_41
LIOB33.IOB_Y1.IFF.ZINIT_Q4 29_33
LIOB33.IOB_Y1.IFF.ZINV_C 28_02 28_04 29_01
LIOB33.IOB_Y1.IFF.ZINV_OCLK 29_63
LIOB33.IOB_Y1.IFF.ZSRVAL_Q1 28_56
LIOB33.IOB_Y1.IFF.ZSRVAL_Q2 28_52
LIOB33.IOB_Y1.IFF.ZSRVAL_Q3 28_42
LIOB33.IOB_Y1.IFF.ZSRVAL_Q4 28_34
LIOB33.IOB_Y1.IN_ONLY 38_02 38_08 39_09
LIOB33.IOB_Y1.INOUT 31_60
LIOB33.IOB_Y1.INTERMDISABLE.I 38_38
LIOB33.IOB_Y1.ISERDES.DATA_RATE.SDR 26_19
LIOB33.IOB_Y1.ISERDES.INTERFACE_TYPE.MEMORY_DDR3 27_10
LIOB33.IOB_Y1.ISERDES.INTERFACE_TYPE.OVERSAMPLE 27_12
LIOB33.IOB_Y1.LVTTL.DRIVE.I24 30_41 32_16 33_61 !38_00 !38_02 38_08 38_10 !38_14 !38_32 38_62 39_01 !39_09 !39_15 39_63
LIOB33.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE !30_35
LIOB33.IOB_Y1.ODDR.DDR_CLK_EDGE.SAME_EDGE 30_35
LIOB33.IOB_Y1.OFF.ZINIT_Q 32_30
LIOB33.IOB_Y1.OSERDESE.DATA_RATE_TQ.BUF 33_61
LIOB33.IOB_Y1.OSERDESE.DATA_RATE_TQ.DDR 33_57
LIOB33.IOB_Y1.OSERDESE.DATA_RATE_TQ.SDR 32_58
LIOB33.IOB_Y1.OSERDESE.DATA_WIDTH.2 31_00
LIOB33.IOB_Y1.OSERDESE.DATA_WIDTH.3 30_01
LIOB33.IOB_Y1.OSERDESE.DATA_WIDTH.4 30_03
LIOB33.IOB_Y1.OSERDESE.DATA_WIDTH.5 31_06
LIOB33.IOB_Y1.OSERDESE.DATA_WIDTH.6 30_07
LIOB33.IOB_Y1.OSERDESE.DATA_WIDTH.7 31_04
LIOB33.IOB_Y1.OSERDESE.DATA_WIDTH.8 30_11
LIOB33.IOB_Y1.PULLTYPE.KEEPER !38_34 39_33 39_35
LIOB33.IOB_Y1.PULLTYPE.NONE !38_34 39_33 !39_35
LIOB33.IOB_Y1.PULLTYPE.PULLDOWN !38_34 !39_33 !39_35
LIOB33.IOB_Y1.PULLTYPE.PULLUP 38_34 39_33 !39_35
LIOB33.IOB_Y1.SLEW.FAST !38_18 !38_22 !39_17 !39_21
LIOB33.IOB_Y1.SLEW.SLOW 38_18 38_22 39_17 39_21
LIOB33.IOB_Y1.TFF.ZINIT_Q 31_52
LIOB33.IOB_Y1.ZINV_D 28_18
LIOB33.IOB_Y1.IDELMUXE3.0 28_26
LIOB33.IOB_Y1.IFFDELMUXE3.0 29_11
LIOB33.IOB_Y1.LVCMOS12.DRIVE.I4 30_41 32_16 33_61 !38_00 38_02 !38_08 !38_10 38_14 38_32 38_62 39_01 39_09 39_15 39_63
LIOB33.IOB_Y1.LVCMOS12.DRIVE.I8 30_41 32_16 33_61 !38_00 !38_02 38_08 !38_10 38_14 38_32 38_62 !39_01 !39_09 39_15 39_63
LIOB33.IOB_Y1.LVCMOS12.DRIVE.I12 30_41 32_16 33_61 38_00 !38_02 !38_08 !38_10 38_14 38_32 38_62 39_01 !39_09 39_15 39_63
LIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18.IN 38_14 !38_40 38_42 39_41
LIOB33.IOB_Y1.LVCMOS15.DRIVE.I8 30_41 32_16 33_61 38_00 38_02 38_08 !38_10 38_14 38_32 38_62 39_01 !39_09 39_15 39_63
LIOB33.IOB_Y1.LVCMOS15.DRIVE.I12 30_41 32_16 33_61 38_00 !38_02 !38_08 !38_10 38_14 38_32 38_62 !39_01 !39_09 39_15 39_63
LIOB33.IOB_Y1.LVCMOS15.DRIVE.I16 30_41 32_16 33_61 38_00 !38_02 !38_08 38_10 38_14 38_32 38_62 39_01 39_09 39_15 39_63
LIOB33.IOB_Y1.LVCMOS15_LVCMOS18.DRIVE.I4 30_41 32_16 33_61 38_00 38_02 !38_08 !38_10 38_14 38_32 38_62 !39_01 39_09 39_15 39_63
LIOB33.IOB_Y1.LVCMOS18.DRIVE.I12_I8 30_41 32_16 33_61 !38_00 38_02 38_08 !38_10 38_14 38_32 38_62 39_01 !39_09 39_15 39_63
LIOB33.IOB_Y1.LVCMOS18.DRIVE.I16 30_41 32_16 33_61 38_00 38_02 !38_08 !38_10 38_14 38_32 38_62 39_01 !39_09 39_15 39_63
LIOB33.IOB_Y1.LVCMOS18.DRIVE.I24 30_41 32_16 33_61 !38_00 !38_02 38_08 38_10 38_14 38_32 38_62 39_01 !39_09 39_15 39_63
LIOB33.IOB_Y1.LVCMOS25.DRIVE.I4 30_41 32_16 33_61 38_00 38_02 !38_08 !38_10 38_14 !38_32 38_62 !39_01 39_09 39_15 39_63
LIOB33.IOB_Y1.LVCMOS25.DRIVE.I8 30_41 32_16 33_61 !38_00 !38_02 38_08 !38_10 38_14 !38_32 38_62 !39_01 !39_09 39_15 39_63
LIOB33.IOB_Y1.LVCMOS25.DRIVE.I12 30_41 32_16 33_61 !38_00 !38_02 !38_08 !38_10 38_14 !38_32 38_62 !39_01 !39_09 39_15 39_63
LIOB33.IOB_Y1.LVCMOS25.DRIVE.I16 30_41 32_16 33_61 !38_00 !38_02 !38_08 38_10 38_14 !38_32 38_62 39_01 39_09 39_15 39_63
LIOB33.IOB_Y1.LVCMOS25_LVCMOS33_LVTTL.IN 38_14 38_40 38_42 39_41
LIOB33.IOB_Y1.LVCMOS33.DRIVE.I16 30_41 32_16 33_61 38_00 !38_02 !38_08 38_10 !38_14 !38_32 38_62 !39_01 39_09 !39_15 39_63
LIOB33.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I4 30_41 32_16 33_61 38_00 38_02 !38_08 !38_10 !38_14 !38_32 38_62 !39_01 39_09 !39_15 39_63
LIOB33.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I12_I8 30_41 32_16 33_61 !38_00 38_02 38_08 !38_10 !38_14 !38_32 38_62 39_01 !39_09 !39_15 39_63
LIOB33.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I12_I16 30_41 32_16 33_61 38_00 38_02 !38_08 !38_10 !38_14 !38_32 38_62 39_01 !39_09 !39_15 39_63

125
zynq7/segbits_riob33.db Normal file
View File

@ -0,0 +1,125 @@
RIOB33.IOB_Y0.IBUFDISABLE.I 38_82
RIOB33.IOB_Y0.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE 27_98
RIOB33.IOB_Y0.IFF.DDR_CLK_EDGE.SAME_EDGE 26_99
RIOB33.IOB_Y0.IFF.SRTYPE.SYNC 29_67
RIOB33.IOB_Y0.IFF.ZINIT_Q1 28_72
RIOB33.IOB_Y0.IFF.ZINIT_Q2 28_76
RIOB33.IOB_Y0.IFF.ZINIT_Q3 28_86
RIOB33.IOB_Y0.IFF.ZINIT_Q4 28_94
RIOB33.IOB_Y0.IFF.ZINV_C 28_126 29_123 29_125
RIOB33.IOB_Y0.IFF.ZINV_OCLK 28_64
RIOB33.IOB_Y0.IFF.ZSRVAL_Q1 29_71
RIOB33.IOB_Y0.IFF.ZSRVAL_Q2 29_75
RIOB33.IOB_Y0.IFF.ZSRVAL_Q3 29_85
RIOB33.IOB_Y0.IFF.ZSRVAL_Q4 29_93
RIOB33.IOB_Y0.INOUT 30_67
RIOB33.IOB_Y0.INTERMDISABLE.I 39_89
RIOB33.IOB_Y0.ISERDES.DATA_RATE.SDR 27_108
RIOB33.IOB_Y0.ISERDES.INTERFACE_TYPE.MEMORY_DDR3 26_117
RIOB33.IOB_Y0.ISERDES.INTERFACE_TYPE.OVERSAMPLE 26_115
RIOB33.IOB_Y0.LVTTL.DRIVE.I24 31_86 32_66 33_111 38_64 !38_112 !38_118 38_126 39_65 !39_95 39_117 39_119 !39_125 !39_127
RIOB33.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE !31_92
RIOB33.IOB_Y0.ODDR.DDR_CLK_EDGE.SAME_EDGE 31_92
RIOB33.IOB_Y0.OFF.ZINIT_Q 33_97
RIOB33.IOB_Y0.OSERDESE.DATA_RATE_TQ.BUF 32_66
RIOB33.IOB_Y0.OSERDESE.DATA_RATE_TQ.DDR 32_70
RIOB33.IOB_Y0.OSERDESE.DATA_RATE_TQ.SDR 33_69
RIOB33.IOB_Y0.OSERDESE.DATA_WIDTH.2 30_127
RIOB33.IOB_Y0.OSERDESE.DATA_WIDTH.3 31_126
RIOB33.IOB_Y0.OSERDESE.DATA_WIDTH.4 31_124
RIOB33.IOB_Y0.OSERDESE.DATA_WIDTH.5 30_121
RIOB33.IOB_Y0.OSERDESE.DATA_WIDTH.6 31_120
RIOB33.IOB_Y0.OSERDESE.DATA_WIDTH.7 30_123
RIOB33.IOB_Y0.OSERDESE.DATA_WIDTH.8 31_116
RIOB33.IOB_Y0.PULLTYPE.KEEPER 38_92 38_94 !39_93
RIOB33.IOB_Y0.PULLTYPE.NONE !38_92 38_94 !39_93
RIOB33.IOB_Y0.PULLTYPE.PULLDOWN !38_92 !38_94 !39_93
RIOB33.IOB_Y0.PULLTYPE.PULLUP !38_92 38_94 39_93
RIOB33.IOB_Y0.SLEW.FAST !38_106 !38_110 !39_105 !39_109
RIOB33.IOB_Y0.SLEW.SLOW 38_106 38_110 39_105 39_109
RIOB33.IOB_Y0.TFF.ZINIT_Q 30_75
RIOB33.IOB_Y0.ZINV_D 29_109
RIOB33.IOB_Y0.IDELMUXE3.0 29_101
RIOB33.IOB_Y0.IFFDELMUXE3.0 28_116
RIOB33.IOB_Y0.LVCMOS12.DRIVE.I4 31_86 32_66 33_111 38_64 38_112 38_118 38_126 39_65 39_95 !39_117 !39_119 39_125 !39_127
RIOB33.IOB_Y0.LVCMOS12.DRIVE.I8 31_86 32_66 33_111 38_64 38_112 !38_118 !38_126 39_65 39_95 !39_117 39_119 !39_125 !39_127
RIOB33.IOB_Y0.LVCMOS12.DRIVE.I12 31_86 32_66 33_111 38_64 38_112 !38_118 38_126 39_65 39_95 !39_117 !39_119 !39_125 39_127
RIOB33.IOB_Y0.LVCMOS15.DRIVE.I8 31_86 32_66 33_111 38_64 38_112 !38_118 38_126 39_65 39_95 !39_117 39_119 39_125 39_127
RIOB33.IOB_Y0.LVCMOS15.DRIVE.I12 31_86 32_66 33_111 38_64 38_112 !38_118 !38_126 39_65 39_95 !39_117 !39_119 !39_125 39_127
RIOB33.IOB_Y0.LVCMOS15.DRIVE.I16 31_86 32_66 33_111 38_64 38_112 38_118 38_126 39_65 39_95 39_117 !39_119 !39_125 39_127
RIOB33.IOB_Y0.LVCMOS15_LVCMOS18.DRIVE.I4 31_86 32_66 33_111 38_64 38_112 38_118 !38_126 39_65 39_95 !39_117 !39_119 39_125 39_127
RIOB33.IOB_Y0.LVCMOS18.DRIVE.I12_I8 31_86 32_66 33_111 38_64 38_112 !38_118 38_126 39_65 39_95 !39_117 39_119 39_125 !39_127
RIOB33.IOB_Y0.LVCMOS18.DRIVE.I16 31_86 32_66 33_111 38_64 38_112 !38_118 38_126 39_65 39_95 !39_117 !39_119 39_125 39_127
RIOB33.IOB_Y0.LVCMOS18.DRIVE.I24 31_86 32_66 33_111 38_64 38_112 !38_118 38_126 39_65 39_95 39_117 39_119 !39_125 !39_127
RIOB33.IOB_Y0.LVCMOS25.DRIVE.I4 31_86 32_66 33_111 38_64 38_112 38_118 !38_126 39_65 !39_95 !39_117 !39_119 39_125 39_127
RIOB33.IOB_Y0.LVCMOS25.DRIVE.I8 31_86 32_66 33_111 38_64 38_112 !38_118 !38_126 39_65 !39_95 !39_117 39_119 !39_125 !39_127
RIOB33.IOB_Y0.LVCMOS25.DRIVE.I12 31_86 32_66 33_111 38_64 38_112 !38_118 !38_126 39_65 !39_95 !39_117 !39_119 !39_125 !39_127
RIOB33.IOB_Y0.LVCMOS25.DRIVE.I16 31_86 32_66 33_111 38_64 38_112 38_118 38_126 39_65 !39_95 39_117 !39_119 !39_125 !39_127
RIOB33.IOB_Y0.LVCMOS33.DRIVE.I16 31_86 32_66 33_111 38_64 !38_112 38_118 !38_126 39_65 !39_95 39_117 !39_119 !39_125 39_127
RIOB33.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I4 31_86 32_66 33_111 38_64 !38_112 38_118 !38_126 39_65 !39_95 !39_117 !39_119 39_125 39_127
RIOB33.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I12_I8 31_86 32_66 33_111 38_64 !38_112 !38_118 38_126 39_65 !39_95 !39_117 39_119 39_125 !39_127
RIOB33.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I12_I16 31_86 32_66 33_111 38_64 !38_112 !38_118 38_126 39_65 !39_95 !39_117 !39_119 39_125 39_127
RIOB33.IOB_Y1.IBUFDISABLE.I 39_45
RIOB33.IOB_Y1.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE 26_29
RIOB33.IOB_Y1.IFF.DDR_CLK_EDGE.SAME_EDGE 27_28
RIOB33.IOB_Y1.IFF.SRTYPE.SYNC 28_60
RIOB33.IOB_Y1.IFF.ZINIT_Q1 29_55
RIOB33.IOB_Y1.IFF.ZINIT_Q2 29_51
RIOB33.IOB_Y1.IFF.ZINIT_Q3 29_41
RIOB33.IOB_Y1.IFF.ZINIT_Q4 29_33
RIOB33.IOB_Y1.IFF.ZINV_C 28_02 28_04 29_01
RIOB33.IOB_Y1.IFF.ZINV_OCLK 29_63
RIOB33.IOB_Y1.IFF.ZSRVAL_Q1 28_56
RIOB33.IOB_Y1.IFF.ZSRVAL_Q2 28_52
RIOB33.IOB_Y1.IFF.ZSRVAL_Q3 28_42
RIOB33.IOB_Y1.IFF.ZSRVAL_Q4 28_34
RIOB33.IOB_Y1.IN_ONLY 38_02 38_08 39_09
RIOB33.IOB_Y1.INOUT 31_60
RIOB33.IOB_Y1.INTERMDISABLE.I 38_38
RIOB33.IOB_Y1.ISERDES.DATA_RATE.SDR 26_19
RIOB33.IOB_Y1.ISERDES.INTERFACE_TYPE.MEMORY_DDR3 27_10
RIOB33.IOB_Y1.ISERDES.INTERFACE_TYPE.OVERSAMPLE 27_12
RIOB33.IOB_Y1.LVTTL.DRIVE.I24 30_41 32_16 33_61 !38_00 !38_02 38_08 38_10 !38_14 !38_32 38_62 39_01 !39_09 !39_15 39_63
RIOB33.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE !30_35
RIOB33.IOB_Y1.ODDR.DDR_CLK_EDGE.SAME_EDGE 30_35
RIOB33.IOB_Y1.OFF.ZINIT_Q 32_30
RIOB33.IOB_Y1.OSERDESE.DATA_RATE_TQ.BUF 33_61
RIOB33.IOB_Y1.OSERDESE.DATA_RATE_TQ.DDR 33_57
RIOB33.IOB_Y1.OSERDESE.DATA_RATE_TQ.SDR 32_58
RIOB33.IOB_Y1.OSERDESE.DATA_WIDTH.2 31_00
RIOB33.IOB_Y1.OSERDESE.DATA_WIDTH.3 30_01
RIOB33.IOB_Y1.OSERDESE.DATA_WIDTH.4 30_03
RIOB33.IOB_Y1.OSERDESE.DATA_WIDTH.5 31_06
RIOB33.IOB_Y1.OSERDESE.DATA_WIDTH.6 30_07
RIOB33.IOB_Y1.OSERDESE.DATA_WIDTH.7 31_04
RIOB33.IOB_Y1.OSERDESE.DATA_WIDTH.8 30_11
RIOB33.IOB_Y1.PULLTYPE.KEEPER !38_34 39_33 39_35
RIOB33.IOB_Y1.PULLTYPE.NONE !38_34 39_33 !39_35
RIOB33.IOB_Y1.PULLTYPE.PULLDOWN !38_34 !39_33 !39_35
RIOB33.IOB_Y1.PULLTYPE.PULLUP 38_34 39_33 !39_35
RIOB33.IOB_Y1.SLEW.FAST !38_18 !38_22 !39_17 !39_21
RIOB33.IOB_Y1.SLEW.SLOW 38_18 38_22 39_17 39_21
RIOB33.IOB_Y1.TFF.ZINIT_Q 31_52
RIOB33.IOB_Y1.ZINV_D 28_18
RIOB33.IOB_Y1.IDELMUXE3.0 28_26
RIOB33.IOB_Y1.IFFDELMUXE3.0 29_11
RIOB33.IOB_Y1.LVCMOS12.DRIVE.I4 30_41 32_16 33_61 !38_00 38_02 !38_08 !38_10 38_14 38_32 38_62 39_01 39_09 39_15 39_63
RIOB33.IOB_Y1.LVCMOS12.DRIVE.I8 30_41 32_16 33_61 !38_00 !38_02 38_08 !38_10 38_14 38_32 38_62 !39_01 !39_09 39_15 39_63
RIOB33.IOB_Y1.LVCMOS12.DRIVE.I12 30_41 32_16 33_61 38_00 !38_02 !38_08 !38_10 38_14 38_32 38_62 39_01 !39_09 39_15 39_63
RIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18.IN 38_14 !38_40 38_42 39_41
RIOB33.IOB_Y1.LVCMOS15.DRIVE.I8 30_41 32_16 33_61 38_00 38_02 38_08 !38_10 38_14 38_32 38_62 39_01 !39_09 39_15 39_63
RIOB33.IOB_Y1.LVCMOS15.DRIVE.I12 30_41 32_16 33_61 38_00 !38_02 !38_08 !38_10 38_14 38_32 38_62 !39_01 !39_09 39_15 39_63
RIOB33.IOB_Y1.LVCMOS15.DRIVE.I16 30_41 32_16 33_61 38_00 !38_02 !38_08 38_10 38_14 38_32 38_62 39_01 39_09 39_15 39_63
RIOB33.IOB_Y1.LVCMOS15_LVCMOS18.DRIVE.I4 30_41 32_16 33_61 38_00 38_02 !38_08 !38_10 38_14 38_32 38_62 !39_01 39_09 39_15 39_63
RIOB33.IOB_Y1.LVCMOS18.DRIVE.I12_I8 30_41 32_16 33_61 !38_00 38_02 38_08 !38_10 38_14 38_32 38_62 39_01 !39_09 39_15 39_63
RIOB33.IOB_Y1.LVCMOS18.DRIVE.I16 30_41 32_16 33_61 38_00 38_02 !38_08 !38_10 38_14 38_32 38_62 39_01 !39_09 39_15 39_63
RIOB33.IOB_Y1.LVCMOS18.DRIVE.I24 30_41 32_16 33_61 !38_00 !38_02 38_08 38_10 38_14 38_32 38_62 39_01 !39_09 39_15 39_63
RIOB33.IOB_Y1.LVCMOS25.DRIVE.I4 30_41 32_16 33_61 38_00 38_02 !38_08 !38_10 38_14 !38_32 38_62 !39_01 39_09 39_15 39_63
RIOB33.IOB_Y1.LVCMOS25.DRIVE.I8 30_41 32_16 33_61 !38_00 !38_02 38_08 !38_10 38_14 !38_32 38_62 !39_01 !39_09 39_15 39_63
RIOB33.IOB_Y1.LVCMOS25.DRIVE.I12 30_41 32_16 33_61 !38_00 !38_02 !38_08 !38_10 38_14 !38_32 38_62 !39_01 !39_09 39_15 39_63
RIOB33.IOB_Y1.LVCMOS25.DRIVE.I16 30_41 32_16 33_61 !38_00 !38_02 !38_08 38_10 38_14 !38_32 38_62 39_01 39_09 39_15 39_63
RIOB33.IOB_Y1.LVCMOS25_LVCMOS33_LVTTL.IN 38_14 38_40 38_42 39_41
RIOB33.IOB_Y1.LVCMOS33.DRIVE.I16 30_41 32_16 33_61 38_00 !38_02 !38_08 38_10 !38_14 !38_32 38_62 !39_01 39_09 !39_15 39_63
RIOB33.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I4 30_41 32_16 33_61 38_00 38_02 !38_08 !38_10 !38_14 !38_32 38_62 !39_01 39_09 !39_15 39_63
RIOB33.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I12_I8 30_41 32_16 33_61 !38_00 38_02 38_08 !38_10 !38_14 !38_32 38_62 39_01 !39_09 !39_15 39_63
RIOB33.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I12_I16 30_41 32_16 33_61 38_00 38_02 !38_08 !38_10 !38_14 !38_32 38_62 39_01 !39_09 !39_15 39_63

64
zynq7/tilegrid.json
View File

@ -138504,7 +138504,21 @@
"type": "PSS4" "type": "PSS4"
}, },
"RIOB33_SING_X31Y0": { "RIOB33_SING_X31Y0": {
"bits": {}, "bits": {
"CLB_IO_CLK": {
"alias": {
"sites": {
"IOB33_Y0": "IOB33_Y0"
},
"start_offset": 2,
"type": "RIOB33"
},
"baseaddr": "0x00401B80",
"frames": 42,
"offset": 0,
"words": 2
}
},
"grid_x": 127, "grid_x": 127,
"grid_y": 103, "grid_y": 103,
"sites": { "sites": {
@ -138513,7 +138527,21 @@
"type": "RIOB33_SING" "type": "RIOB33_SING"
}, },
"RIOB33_SING_X31Y49": { "RIOB33_SING_X31Y49": {
"bits": {}, "bits": {
"CLB_IO_CLK": {
"alias": {
"sites": {
"IOB33_Y0": "IOB33_Y1"
},
"start_offset": 0,
"type": "RIOB33"
},
"baseaddr": "0x00401B80",
"frames": 42,
"offset": 99,
"words": 2
}
},
"grid_x": 127, "grid_x": 127,
"grid_y": 53, "grid_y": 53,
"sites": { "sites": {
@ -138522,7 +138550,21 @@
"type": "RIOB33_SING" "type": "RIOB33_SING"
}, },
"RIOB33_SING_X31Y50": { "RIOB33_SING_X31Y50": {
"bits": {}, "bits": {
"CLB_IO_CLK": {
"alias": {
"sites": {
"IOB33_Y0": "IOB33_Y0"
},
"start_offset": 2,
"type": "RIOB33"
},
"baseaddr": "0x00001B80",
"frames": 42,
"offset": 0,
"words": 2
}
},
"grid_x": 127, "grid_x": 127,
"grid_y": 51, "grid_y": 51,
"sites": { "sites": {
@ -138531,7 +138573,21 @@
"type": "RIOB33_SING" "type": "RIOB33_SING"
}, },
"RIOB33_SING_X31Y99": { "RIOB33_SING_X31Y99": {
"bits": {}, "bits": {
"CLB_IO_CLK": {
"alias": {
"sites": {
"IOB33_Y0": "IOB33_Y1"
},
"start_offset": 0,
"type": "RIOB33"
},
"baseaddr": "0x00001B80",
"frames": 42,
"offset": 99,
"words": 2
}
},
"grid_x": 127, "grid_x": 127,
"grid_y": 1, "grid_y": 1,
"sites": { "sites": {