Miodrag Milanović bc3df10ff3 Add alternate clock routes and CP pass through [sc-184] (#17) ... * Add alternate clock routes * Add pins for alternate signals * Add more pips and placeholder for metadata * Add data/mask for pips * Add pips for testing * fix CPE_CPLINES OUTx inputs * resources * Added rest of CP lines pips * Change to block and resource * Fix chip database error * Timing data for CP lines * Fix bitstream * Bump database version		2026-02-25 08:11:36 +01:00
..
__init__.py	Start modeling chip die	2024-12-09 10:57:04 +01:00
chip.py	Add alternate clock routes and CP pass through [sc-184] (#17)	2026-02-25 08:11:36 +01:00
die.py	Add alternate clock routes and CP pass through [sc-184] (#17)	2026-02-25 08:11:36 +01:00
timing.py	Add timing information from dly files	2025-05-27 15:21:14 +02:00