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Project Peppercorn - GateMate FPGA Bitstream Documentation
210 Commits 2 Branches 14 Tags 11 MiB
Python 70.2%
C++ 28.6%
CMake 1.1%
Shell 0.1%
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Miodrag Milanović bc3df10ff3
Add alternate clock routes and CP pass through [sc-184] (#17) 
* Add alternate clock routes

* Add pins for alternate signals

* Add more pips and placeholder for metadata

* Add data/mask for pips

* Add pips for testing

* fix CPE_CPLINES OUTx inputs

* resources

* Added rest of CP lines pips

* Change to block and resource

* Fix chip database error

* Timing data for CP lines

* Fix bitstream

* Bump database version
 		2026-02-25 08:11:36 +01:00
delay Add delay blobs, fixes #9 2025-09-30 12:49:35 +02:00
docs add write_cmd_spll for designs without PLLs 2025-10-22 09:14:51 +02:00
gatemate Add alternate clock routes and CP pass through [sc-184] (#17) 2026-02-25 08:11:36 +01:00
libgm cleanup 2025-12-30 10:12:10 +01:00
schematics/cpe fix C/P line errata caused by misunderstanding inversion 2026-01-09 13:45:33 +00:00
tools Extract SERDES config 2025-04-30 09:57:28 +02:00
.gitignore Add delay blobs, fixes #9 2025-09-30 12:49:35 +02:00
.readthedocs.yaml Update readthedocs config 2024-12-04 17:19:41 +01:00
COPYING License and README 2024-12-04 11:45:48 +01:00
README.md License and README 2024-12-04 11:45:48 +01:00
decompress.py Add timing information from dly files 2025-05-27 15:21:14 +02:00
delay.sh Download only with delay files 2025-06-05 07:00:12 +02:00
environment.sh Start modeling chip die 2024-12-09 10:57:04 +01:00

README.md

Project Peppercorn

GateMate FPGAs Bitstream Documentation and Tools

Credits

Code is heavily based on prjtrellis. Special thanks goes to @gatecat

License

All software (code, associated documentation, support files, etc) in the Project Peppercorn repository are licensed under the very permissive ISC Licence. A copy can be found in the COPYING file.

All new contributions must also be released under this license.