luke/prjpeppercorn

mirror of https://github.com/YosysHQ/prjpeppercorn.git synced 2026-08-29 01:03:08 +02:00

T

Miodrag Milanović 5d5f927d93 Merge pull request #8 from YosysHQ/bram

Split BRAM into halfs

2025-09-02 08:04:53 +02:00

Fix CMD_CFGMODE formatting

2025-07-08 16:57:52 +02:00

bump database version

2025-08-29 14:57:41 +02:00

Fix reading with gmunpack and clangformat

2025-07-09 12:52:00 +02:00

update CPE schematics to cover C/P lines

2025-07-19 11:35:43 +01:00

Extract SERDES config

2025-04-30 09:57:28 +02:00

.gitignore

Add timing information from dly files

2025-05-27 15:21:14 +02:00

.readthedocs.yaml

Update readthedocs config

2024-12-04 17:19:41 +01:00

COPYING

License and README

2024-12-04 11:45:48 +01:00

decompress.py

Add timing information from dly files

2025-05-27 15:21:14 +02:00

delay.sh

Download only with delay files

2025-06-05 07:00:12 +02:00

environment.sh

Start modeling chip die

2024-12-09 10:57:04 +01:00

README.md

License and README

2024-12-04 11:45:48 +01:00

README.md

Project Peppercorn

GateMate FPGAs Bitstream Documentation and Tools

Credits

Code is heavily based on prjtrellis. Special thanks goes to @gatecat

License

All software (code, associated documentation, support files, etc) in the Project Peppercorn repository are licensed under the very permissive ISC Licence. A copy can be found in the COPYING file.

All new contributions must also be released under this license.