mirror of https://github.com/YosysHQ/prjpeppercorn.git synced 2026-08-22 22:06:38 +02:00

T

Patrick Urban b1eb52f45c TileBitDatabase: Fix SERDES RX parameter ordering (#20 )

* TileBitDatabase: fix RX reset parameter ordering

* docs: update CMD_CHG_STATUS bit 7

2026-06-16 14:07:15 +02:00

delay

Add delay blobs, fixes #9

2025-09-30 12:49:35 +02:00

docs

TileBitDatabase: Fix SERDES RX parameter ordering (#20 )

2026-06-16 14:07:15 +02:00

gatemate

Bump chip database

2026-03-18 13:13:58 +01:00

libgm

TileBitDatabase: Fix SERDES RX parameter ordering (#20 )

2026-06-16 14:07:15 +02:00

schematics/cpe

fix C/P line errata caused by misunderstanding inversion

2026-01-09 13:45:33 +00:00

tools

Extract SERDES config

2025-04-30 09:57:28 +02:00

.gitignore

Add delay blobs, fixes #9

2025-09-30 12:49:35 +02:00

.readthedocs.yaml

Update readthedocs config

2024-12-04 17:19:41 +01:00

COPYING

License and README

2024-12-04 11:45:48 +01:00

decompress.py

Add timing information from dly files

2025-05-27 15:21:14 +02:00

delay.sh

Download only with delay files

2025-06-05 07:00:12 +02:00

environment.sh

Start modeling chip die

2024-12-09 10:57:04 +01:00

README.md

License and README

2024-12-04 11:45:48 +01:00

README.md

Project Peppercorn

GateMate FPGAs Bitstream Documentation and Tools

Credits

Code is heavily based on prjtrellis. Special thanks goes to @gatecat

License

All software (code, associated documentation, support files, etc) in the Project Peppercorn repository are licensed under the very permissive ISC Licence. A copy can be found in the COPYING file.

All new contributions must also be released under this license.