Merge branch 'YosysHQ:main' into cfgmode
This commit is contained in:
Patrick Urban
GitHub
commit
9148a1b81d
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@ -23,7 +23,7 @@ from dataclasses import dataclass
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from typing import List, Dict
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from timing import decompress_timing
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DATABASE_VERSION = 1.2
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DATABASE_VERSION = 1.3
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@dataclass(eq=True, order=True)
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class Pad:
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308
gatemate/die.py
308
gatemate/die.py
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@ -244,43 +244,118 @@ class TileInfo:
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prim_index : int
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PRIMITIVES_PINS = {
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"CPE_HALF_U": [
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Pin("RAM_I" ,PinType.INPUT, "CPE_WIRE_L", True),
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Pin("IN1" ,PinType.INPUT, "CPE_WIRE_L", True),
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Pin("IN2" ,PinType.INPUT, "CPE_WIRE_L", True),
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Pin("IN3" ,PinType.INPUT, "CPE_WIRE_L", True),
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Pin("IN4" ,PinType.INPUT, "CPE_WIRE_L", True),
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Pin("CLK" ,PinType.INPUT, "CPE_WIRE_L", True),
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Pin("EN" ,PinType.INPUT, "CPE_WIRE_L", True),
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Pin("SR" ,PinType.INPUT, "CPE_WIRE_L", True),
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Pin("OUT" ,PinType.OUTPUT, "CPE_WIRE_B", True),
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Pin("RAM_O" ,PinType.OUTPUT, "CPE_WIRE_B", True),
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"CPE_LT_U": [
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Pin("IN1" ,PinType.INPUT, "CPE_WIRE", True),
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Pin("IN2" ,PinType.INPUT, "CPE_WIRE", True),
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Pin("IN3" ,PinType.INPUT, "CPE_WIRE", True),
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Pin("IN4" ,PinType.INPUT, "CPE_WIRE", True),
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Pin("OUT" ,PinType.OUTPUT, "CPE_WIRE", True),
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Pin("CPOUT" ,PinType.OUTPUT, "CPE_WIRE", True),
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Pin("PINY1" ,PinType.INPUT, "CPE_WIRE", True),
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Pin("CINX" ,PinType.INPUT, "CPE_WIRE", True),
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],
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"CPE_FF_U": [
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Pin("DIN" ,PinType.INPUT, "CPE_WIRE", True),
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Pin("CLK" ,PinType.INPUT, "CPE_WIRE", True),
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Pin("EN" ,PinType.INPUT, "CPE_WIRE", True),
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Pin("SR" ,PinType.INPUT, "CPE_WIRE", True),
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Pin("DOUT" ,PinType.OUTPUT, "CPE_WIRE", True),
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],
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"CPE_RAMIO_U": [
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Pin("RAM_I" ,PinType.INPUT, "CPE_WIRE", True),
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Pin("I" ,PinType.INPUT, "CPE_WIRE", True),
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Pin("OUT" ,PinType.OUTPUT, "CPE_WIRE", True),
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Pin("RAM_O" ,PinType.OUTPUT, "CPE_WIRE", True),
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],
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"CPE_LT_L": [
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Pin("IN1" ,PinType.INPUT, "CPE_WIRE", True),
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Pin("IN2" ,PinType.INPUT, "CPE_WIRE", True),
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Pin("IN3" ,PinType.INPUT, "CPE_WIRE", True),
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Pin("IN4" ,PinType.INPUT, "CPE_WIRE", True),
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Pin("COMBIN" ,PinType.INPUT, "CPE_WIRE", True),
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Pin("OUT" ,PinType.OUTPUT, "CPE_WIRE", True),
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Pin("CPOUT" ,PinType.OUTPUT, "CPE_WIRE", True),
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Pin("CINX" ,PinType.INPUT, "CPE_WIRE", True),
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Pin("PINX" ,PinType.INPUT, "CPE_WIRE", True),
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Pin("CINY1" ,PinType.INPUT, "CPE_WIRE", True),
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Pin("PINY1" ,PinType.INPUT, "CPE_WIRE", True),
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Pin("CINY2" ,PinType.INPUT, "CPE_WIRE", True),
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Pin("PINY2" ,PinType.INPUT, "CPE_WIRE", True),
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Pin("COUTX" ,PinType.OUTPUT, "CPE_WIRE", True),
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Pin("POUTX" ,PinType.OUTPUT, "CPE_WIRE", True),
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Pin("COUTY1" ,PinType.OUTPUT, "CPE_WIRE", True),
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Pin("POUTY1" ,PinType.OUTPUT, "CPE_WIRE", True),
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Pin("COUTY2" ,PinType.OUTPUT, "CPE_WIRE", True),
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Pin("POUTY2" ,PinType.OUTPUT, "CPE_WIRE", True),
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],
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"CPE_FF_L": [
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Pin("DIN" ,PinType.INPUT, "CPE_WIRE", True),
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Pin("CLK" ,PinType.INPUT, "CPE_WIRE", True),
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Pin("EN" ,PinType.INPUT, "CPE_WIRE", True),
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Pin("SR" ,PinType.INPUT, "CPE_WIRE", True),
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Pin("DOUT" ,PinType.OUTPUT, "CPE_WIRE", True),
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],
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"CPE_RAMIO_L": [
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Pin("RAM_I" ,PinType.INPUT, "CPE_WIRE", True),
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Pin("I" ,PinType.INPUT, "CPE_WIRE", True),
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Pin("OUT" ,PinType.OUTPUT, "CPE_WIRE", True),
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Pin("RAM_O" ,PinType.OUTPUT, "CPE_WIRE", True),
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],
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"CPE_LT_FULL": [
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Pin("IN1" ,PinType.INPUT, "CPE_WIRE", True),
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Pin("IN2" ,PinType.INPUT, "CPE_WIRE", True),
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Pin("IN3" ,PinType.INPUT, "CPE_WIRE", True),
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Pin("IN4" ,PinType.INPUT, "CPE_WIRE", True),
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Pin("IN5" ,PinType.INPUT, "CPE_WIRE", True),
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Pin("IN6" ,PinType.INPUT, "CPE_WIRE", True),
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Pin("IN7" ,PinType.INPUT, "CPE_WIRE", True),
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Pin("IN8" ,PinType.INPUT, "CPE_WIRE", True),
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Pin("OUT1" ,PinType.OUTPUT, "CPE_WIRE", True),
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Pin("OUT2" ,PinType.OUTPUT, "CPE_WIRE", True),
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Pin("CPOUT1" ,PinType.OUTPUT, "CPE_WIRE", True),
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Pin("CPOUT2" ,PinType.OUTPUT, "CPE_WIRE", True),
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Pin("MUXOUT" ,PinType.OUTPUT, "CPE_WIRE", True),
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"CPE_HALF_L": [
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Pin("RAM_I" ,PinType.INPUT, "CPE_WIRE_L", True),
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Pin("IN1" ,PinType.INPUT, "CPE_WIRE_L", True),
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Pin("IN2" ,PinType.INPUT, "CPE_WIRE_L", True),
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Pin("IN3" ,PinType.INPUT, "CPE_WIRE_L", True),
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Pin("IN4" ,PinType.INPUT, "CPE_WIRE_L", True),
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Pin("CLK" ,PinType.INPUT, "CPE_WIRE_L", True),
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Pin("EN" ,PinType.INPUT, "CPE_WIRE_L", True),
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Pin("SR" ,PinType.INPUT, "CPE_WIRE_L", True),
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Pin("OUT" ,PinType.OUTPUT, "CPE_WIRE_B", True),
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Pin("RAM_O" ,PinType.OUTPUT, "CPE_WIRE_B", True),
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Pin("CINX" ,PinType.INPUT, "CPE_WIRE", True),
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Pin("PINX" ,PinType.INPUT, "CPE_WIRE", True),
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Pin("CINY1" ,PinType.INPUT, "CPE_WIRE", True),
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Pin("PINY1" ,PinType.INPUT, "CPE_WIRE", True),
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Pin("CINY2" ,PinType.INPUT, "CPE_WIRE", True),
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Pin("PINY2" ,PinType.INPUT, "CPE_WIRE", True),
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Pin("COUTX" ,PinType.OUTPUT, "CPE_WIRE", True),
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Pin("POUTX" ,PinType.OUTPUT, "CPE_WIRE", True),
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Pin("COUTY1" ,PinType.OUTPUT, "CPE_WIRE", True),
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Pin("POUTY1" ,PinType.OUTPUT, "CPE_WIRE", True),
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Pin("COUTY2" ,PinType.OUTPUT, "CPE_WIRE", True),
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Pin("POUTY2" ,PinType.OUTPUT, "CPE_WIRE", True),
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# For MX8
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Pin("CLK" ,PinType.INPUT, "CPE_WIRE", True),
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Pin("EN" ,PinType.INPUT, "CPE_WIRE", True),
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Pin("SR" ,PinType.INPUT, "CPE_WIRE", True),
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],
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"CPE_COMP": [
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Pin("COMB1" ,PinType.INPUT, "CPE_WIRE", True),
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Pin("COMB2" ,PinType.INPUT, "CPE_WIRE", True),
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Pin("COMPOUT",PinType.OUTPUT, "CPE_WIRE", True),
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],
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"CPE_CPLINES": [
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Pin("OUT1" ,PinType.OUTPUT, "CPE_WIRE", True),
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Pin("OUT2" ,PinType.OUTPUT, "CPE_WIRE", True),
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Pin("COMPOUT",PinType.OUTPUT, "CPE_WIRE", True),
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Pin("CINX" ,PinType.INPUT, "CPE_WIRE_L", True),
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Pin("PINX" ,PinType.INPUT, "CPE_WIRE_L", True),
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Pin("CINY1" ,PinType.INPUT, "CPE_WIRE_B", True),
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Pin("PINY1" ,PinType.INPUT, "CPE_WIRE_B", True),
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Pin("CINY2" ,PinType.INPUT, "CPE_WIRE_B", True),
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Pin("PINY2" ,PinType.INPUT, "CPE_WIRE_B", True),
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Pin("COUTX" ,PinType.OUTPUT, "CPE_WIRE_B", True),
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Pin("POUTX" ,PinType.OUTPUT, "CPE_WIRE_B", True),
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Pin("COUTY1" ,PinType.OUTPUT, "CPE_WIRE_T", True),
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Pin("POUTY1" ,PinType.OUTPUT, "CPE_WIRE_T", True),
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Pin("COUTY2" ,PinType.OUTPUT, "CPE_WIRE_T", True),
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Pin("POUTY2" ,PinType.OUTPUT, "CPE_WIRE_T", True),
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Pin("CINX" ,PinType.INPUT, "CPE_WIRE", True),
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Pin("PINX" ,PinType.INPUT, "CPE_WIRE", True),
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Pin("CINY1" ,PinType.INPUT, "CPE_WIRE", True),
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Pin("PINY1" ,PinType.INPUT, "CPE_WIRE", True),
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Pin("CINY2" ,PinType.INPUT, "CPE_WIRE", True),
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Pin("PINY2" ,PinType.INPUT, "CPE_WIRE", True),
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Pin("COUTX" ,PinType.OUTPUT, "CPE_WIRE", True),
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Pin("POUTX" ,PinType.OUTPUT, "CPE_WIRE", True),
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Pin("COUTY1" ,PinType.OUTPUT, "CPE_WIRE", True),
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Pin("POUTY1" ,PinType.OUTPUT, "CPE_WIRE", True),
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Pin("COUTY2" ,PinType.OUTPUT, "CPE_WIRE", True),
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Pin("POUTY2" ,PinType.OUTPUT, "CPE_WIRE", True),
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],
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"GPIO" : [
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@ -1337,12 +1412,19 @@ def get_groups_for_type(type):
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def get_primitives_for_type(type):
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primitives = []
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if "CPE" in type:
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primitives.append(Primitive("CPE_HALF_U","CPE_HALF_U",0))
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primitives.append(Primitive("CPE_HALF_L","CPE_HALF_L",1))
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primitives.append(Primitive("CPE_LT_U","CPE_LT_U",0))
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primitives.append(Primitive("CPE_LT_L","CPE_LT_L",1))
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primitives.append(Primitive("CPE_FF_U","CPE_FF_U",2))
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primitives.append(Primitive("CPE_FF_L","CPE_FF_L",3))
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primitives.append(Primitive("CPE_RAMIO_U","CPE_RAMIO_U",4))
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primitives.append(Primitive("CPE_RAMIO_L","CPE_RAMIO_L",5))
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primitives.append(Primitive("CPE_COMP","CPE_COMP",6))
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primitives.append(Primitive("CPE_CPLINES","CPE_CPLINES",7))
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primitives.append(Primitive("CPE_LT_FULL","CPE_LT_FULL",8))
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if "RAM" in type:
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primitives.append(Primitive("RAM","RAM",4))
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primitives.append(Primitive("RAM","RAM",10))
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if "SERDES" in type:
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primitives.append(Primitive("SERDES","SERDES",4))
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primitives.append(Primitive("SERDES","SERDES",10))
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if "GPIO" in type:
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primitives.append(Primitive("GPIO","GPIO",0))
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if "PLL" in type:
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@ -1353,8 +1435,8 @@ def get_primitives_for_type(type):
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primitives.append(Primitive("PLL2","PLL",4))
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primitives.append(Primitive("PLL3","PLL",5))
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if "CFG_CTRL" in type:
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primitives.append(Primitive("CFG_CTRL","CFG_CTRL",2))
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primitives.append(Primitive("USR_RSTN","USR_RSTN",3))
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primitives.append(Primitive("CFG_CTRL","CFG_CTRL",10))
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primitives.append(Primitive("USR_RSTN","USR_RSTN",11))
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return primitives
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def get_primitive_pins(bel):
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@ -2324,10 +2406,12 @@ def get_pins_constraint(type_name, prim_name, prim_type):
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return val
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def get_pin_connection_name(prim, pin):
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if prim.type == "CPE_HALF_U":
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if prim.type == "CPE_LT_U":
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match pin.name:
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case "OUT":
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return "CPE.OUT2"
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return "CPE.COMBOUT2_int"
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case "CPOUT":
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return "CPE.CPOUT2_int"
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case "IN1":
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return "CPE.IN1_int"
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case "IN2":
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@ -2336,16 +2420,34 @@ def get_pin_connection_name(prim, pin):
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return "CPE.IN3_int"
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case "IN4":
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return "CPE.IN4_int"
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case _:
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return f"CPE.{pin.name}"
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elif prim.type == "CPE_FF_U":
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match pin.name:
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case "DIN":
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return "CPE.DIN2_int"
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case "DOUT":
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return "CPE.DOUT2_int"
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case _:
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return f"CPE.{pin.name}"
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elif prim.type == "CPE_RAMIO_U":
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match pin.name:
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case "OUT":
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return "CPE.OUT2"
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case "RAM_O":
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return "CPE.RAM_O2"
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case "RAM_I":
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return "CPE.RAM_I2"
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case "I":
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return "CPE.OUT2_int"
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case _:
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return f"CPE.{pin.name}"
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elif prim.type == "CPE_HALF_L":
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elif prim.type == "CPE_LT_L":
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match pin.name:
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case "OUT":
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return "CPE.OUT1"
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return "CPE.COMBOUT1_int"
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case "CPOUT":
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return "CPE.CPOUT1_int"
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case "IN1":
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return "CPE.IN5_int"
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case "IN2":
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@ -2354,10 +2456,78 @@ def get_pin_connection_name(prim, pin):
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return "CPE.IN7_int"
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case "IN4":
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return "CPE.IN8_int"
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case "COMBIN":
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return "CPE.COMBIN_int"
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case _:
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return f"CPE.{pin.name}"
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elif prim.type == "CPE_LT_FULL":
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match pin.name:
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case "OUT1":
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return "CPE.COMBOUT1_int"
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case "OUT2":
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return "CPE.COMBOUT2_int"
|
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case "CPOUT1":
|
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return "CPE.CPOUT1_int"
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case "CPOUT2":
|
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return "CPE.CPOUT2_int"
|
||||
case "MUXOUT":
|
||||
return "CPE.MUXOUT_int"
|
||||
case "IN1":
|
||||
return "CPE.IN1_int"
|
||||
case "IN2":
|
||||
return "CPE.IN2_int"
|
||||
case "IN3":
|
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return "CPE.IN3_int"
|
||||
case "IN4":
|
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return "CPE.IN4_int"
|
||||
case "IN5":
|
||||
return "CPE.IN5_int"
|
||||
case "IN6":
|
||||
return "CPE.IN6_int"
|
||||
case "IN7":
|
||||
return "CPE.IN7_int"
|
||||
case "IN8":
|
||||
return "CPE.IN8_int"
|
||||
case _:
|
||||
return f"CPE.{pin.name}"
|
||||
elif prim.type == "CPE_FF_L":
|
||||
match pin.name:
|
||||
case "DIN":
|
||||
return "CPE.DIN1_int"
|
||||
case "DOUT":
|
||||
return "CPE.DOUT1_int"
|
||||
case _:
|
||||
return f"CPE.{pin.name}"
|
||||
elif prim.type == "CPE_RAMIO_L":
|
||||
match pin.name:
|
||||
case "OUT":
|
||||
return "CPE.OUT1"
|
||||
case "RAM_O":
|
||||
return "CPE.RAM_O1"
|
||||
case "RAM_I":
|
||||
return "CPE.RAM_I1"
|
||||
case "I":
|
||||
return "CPE.OUT1_int"
|
||||
case _:
|
||||
return f"CPE.{pin.name}"
|
||||
elif prim.type == "CPE_COMP":
|
||||
match pin.name:
|
||||
case "COMB1":
|
||||
return "CPE.COMBIN1_int"
|
||||
case "COMB2":
|
||||
return "CPE.COMBIN2_int"
|
||||
case "COMPOUT":
|
||||
return "CPE.COMPOUT_int"
|
||||
case _:
|
||||
return f"CPE.{pin.name}"
|
||||
elif prim.type == "CPE_CPLINES":
|
||||
match pin.name:
|
||||
case "OUT1":
|
||||
return "CPE.OUT1_IN_int"
|
||||
case "OUT2":
|
||||
return "CPE.OUT2_IN_int"
|
||||
case "COMPOUT":
|
||||
return "CPE.COMPOUT_IN_int"
|
||||
case _:
|
||||
return f"CPE.{pin.name}"
|
||||
return f"{prim.name}.{pin.name}"
|
||||
|
|
@ -2391,6 +2561,24 @@ def get_endpoints_for_type(type):
|
|||
create_wire("CPE.IN6_int", type="CPE_WIRE_INT")
|
||||
create_wire("CPE.IN7_int", type="CPE_WIRE_INT")
|
||||
create_wire("CPE.IN8_int", type="CPE_WIRE_INT")
|
||||
create_wire("CPE.OUT1_int", type="CPE_WIRE_INT")
|
||||
create_wire("CPE.OUT2_int", type="CPE_WIRE_INT")
|
||||
create_wire("CPE.COMBOUT1_int", type="CPE_WIRE_INT")
|
||||
create_wire("CPE.COMBOUT2_int", type="CPE_WIRE_INT")
|
||||
create_wire("CPE.COMBIN1_int", type="CPE_WIRE_INT")
|
||||
create_wire("CPE.COMBIN2_int", type="CPE_WIRE_INT")
|
||||
create_wire("CPE.MUXOUT_int", type="CPE_WIRE_INT")
|
||||
create_wire("CPE.COMPOUT_int", type="CPE_WIRE_INT")
|
||||
create_wire("CPE.OUT1_IN_int", type="CPE_WIRE_INT")
|
||||
create_wire("CPE.OUT2_IN_int", type="CPE_WIRE_INT")
|
||||
create_wire("CPE.COMPOUT_IN_int", type="CPE_WIRE_INT")
|
||||
create_wire("CPE.CPOUT1_int", type="CPE_WIRE_INT")
|
||||
create_wire("CPE.CPOUT2_int", type="CPE_WIRE_INT")
|
||||
create_wire("CPE.COMBIN_int", type="CPE_WIRE_INT")
|
||||
create_wire("CPE.DIN1_int", type="CPE_WIRE_INT")
|
||||
create_wire("CPE.DIN2_int", type="CPE_WIRE_INT")
|
||||
create_wire("CPE.DOUT1_int", type="CPE_WIRE_INT")
|
||||
create_wire("CPE.DOUT2_int", type="CPE_WIRE_INT")
|
||||
create_wire("CPE.CLK" , type="CPE_WIRE_L")
|
||||
create_wire("CPE.EN" , type="CPE_WIRE_L")
|
||||
create_wire("CPE.SR" , type="CPE_WIRE_L")
|
||||
|
|
@ -2563,10 +2751,6 @@ def get_mux_connections_for_type(type):
|
|||
# CPE
|
||||
for i in range(1,9):
|
||||
create_mux(f"CPE.IN{i}", f"CPE.IN{i}_int", 0, 0, False, None, False)
|
||||
create_mux("CPE.PINY1", "CPE.IN2_int", 1, 1, False, "CPE.C_I1")
|
||||
create_mux("CPE.CINX", "CPE.IN4_int", 1, 1, False, "CPE.C_I2")
|
||||
create_mux("CPE.PINY1", "CPE.IN6_int", 1, 1, False, "CPE.C_I3")
|
||||
create_mux("CPE.PINX", "CPE.IN8_int", 1, 1, False, "CPE.C_I4")
|
||||
for p in range(1,13):
|
||||
plane = f"{p:02d}"
|
||||
for i in range(8):
|
||||
|
|
@ -2574,6 +2758,34 @@ def get_mux_connections_for_type(type):
|
|||
if "OM" in type and p>=9:
|
||||
for i in range(4):
|
||||
create_mux(f"OM.P{plane}.D{i}", f"OM.P{plane}.Y", 2, i, True, f"OM.P{plane}")
|
||||
create_mux("CPE.DOUT1_int", "CPE.OUT1_int", 2, 0, False, "CPE.C_O1", delay="del_dummy")
|
||||
create_mux("CPE.MUXOUT_int", "CPE.OUT1_int", 2, 1, False, "CPE.C_O1", delay="del_dummy")
|
||||
create_mux("CPE.CPOUT1_int", "CPE.OUT1_int", 2, 2, False, "CPE.C_O1", delay="del_dummy")
|
||||
create_mux("CPE.COMBOUT1_int", "CPE.OUT1_int", 2, 3, False, "CPE.C_O1", delay="del_dummy")
|
||||
create_mux("CPE.COMBOUT1_int", "CPE.DIN1_int", 1, 0, False, visible=False, delay="del_dummy")
|
||||
|
||||
create_mux("CPE.DOUT2_int", "CPE.OUT2_int", 2, 0, False, "CPE.C_O2", delay="del_dummy")
|
||||
create_mux("CPE.MUXOUT_int", "CPE.OUT2_int", 2, 1, False, "CPE.C_O2", delay="del_dummy")
|
||||
create_mux("CPE.CPOUT2_int", "CPE.OUT2_int", 2, 2, False, "CPE.C_O2", delay="del_dummy")
|
||||
create_mux("CPE.COMBOUT2_int", "CPE.OUT2_int", 2, 3, False, "CPE.C_O2", delay="del_dummy")
|
||||
|
||||
create_mux("CPE.MUXOUT_int", "CPE.DIN2_int", 1, 1, False, "CPE.C_BR", delay="del_dummy")
|
||||
create_mux("CPE.COMBOUT1_int", "CPE.DIN2_int", 1, 0, False, "CPE.C_2D_IN", delay="del_dummy")
|
||||
create_mux("CPE.COMBOUT2_int", "CPE.DIN2_int", 1, 1, False, "CPE.C_2D_IN", delay="del_dummy")
|
||||
|
||||
# Virtual connections
|
||||
create_mux("CPE.COMBOUT1_int", "CPE.COMBIN1_int", 1, 0, False, visible=False, delay="del_dummy")
|
||||
create_mux("CPE.COMBOUT2_int", "CPE.COMBIN2_int", 1, 0, False, visible=False, delay="del_dummy")
|
||||
|
||||
create_mux("CPE.OUT1_int", "CPE.OUT1_IN_int", 1, 0, False, visible=False, delay="del_dummy")
|
||||
create_mux("CPE.OUT2_int", "CPE.OUT2_IN_int", 1, 0, False, visible=False, delay="del_dummy")
|
||||
create_mux("CPE.COMPOUT_int", "CPE.COMPOUT_IN_int", 1, 0, False, visible=False, delay="del_dummy")
|
||||
|
||||
create_mux("CPE.OUT1_int", "CPE.OUT1", 1, 0, False, visible=False, delay="del_dummy")
|
||||
create_mux("CPE.OUT2_int", "CPE.OUT2", 1, 0, False, visible=False, delay="del_dummy")
|
||||
|
||||
# Connecting upper and lower L2T4
|
||||
create_mux("CPE.COMBOUT2_int", "CPE.COMBIN_int", 1, 0, False, visible=False, delay="del_dummy")
|
||||
|
||||
if "SB_BIG" in type:
|
||||
# SB_BIG
|
||||
|
|
|
|||
|
|
@ -781,33 +781,33 @@ ConfigBitDatabase::ConfigBitDatabase() : BaseBitDatabase(Die::DIE_CONFIG_SIZE *
|
|||
|
||||
pos += 32;
|
||||
// GLBOUT matrix
|
||||
add_word_settings("GLBOUT.GLB0", pos + 0, 3);
|
||||
add_word_settings("GLBOUT.USR_GLB0", pos + 3, 1);
|
||||
add_word_settings("GLBOUT.GLB0_CFG", pos + 0, 3);
|
||||
add_word_settings("GLBOUT.USR_GLB0_EN", pos + 3, 1);
|
||||
add_word_settings("GLBOUT.GLB0_EN", pos + 4, 1);
|
||||
// bits 5-7 not used
|
||||
add_word_settings("GLBOUT.FB0", pos + 8, 2);
|
||||
add_word_settings("GLBOUT.USR_FB0", pos + 10, 1);
|
||||
add_word_settings("GLBOUT.FB0_CFG", pos + 8, 2);
|
||||
add_word_settings("GLBOUT.USR_FB0_EN", pos + 10, 1);
|
||||
// bits 11-15 not used
|
||||
add_word_settings("GLBOUT.GLB1", pos + 16, 3);
|
||||
add_word_settings("GLBOUT.USR_GLB1", pos + 19, 1);
|
||||
add_word_settings("GLBOUT.GLB1_CFG", pos + 16, 3);
|
||||
add_word_settings("GLBOUT.USR_GLB1_EN", pos + 19, 1);
|
||||
add_word_settings("GLBOUT.GLB1_EN", pos + 20, 1);
|
||||
// bits 21-23 not used
|
||||
add_word_settings("GLBOUT.FB1", pos + 24, 2);
|
||||
add_word_settings("GLBOUT.USR_FB1", pos + 26, 1);
|
||||
add_word_settings("GLBOUT.FB1_CFG", pos + 24, 2);
|
||||
add_word_settings("GLBOUT.USR_FB1_EN", pos + 26, 1);
|
||||
// bits 27-31 not used
|
||||
add_word_settings("GLBOUT.GLB2", pos + 32, 3);
|
||||
add_word_settings("GLBOUT.USR_GLB2", pos + 35, 1);
|
||||
add_word_settings("GLBOUT.GLB2_CFG", pos + 32, 3);
|
||||
add_word_settings("GLBOUT.USR_GLB2_EN", pos + 35, 1);
|
||||
add_word_settings("GLBOUT.GLB2_EN", pos + 36, 1);
|
||||
// bits 37-39 not used
|
||||
add_word_settings("GLBOUT.FB2", pos + 40, 2);
|
||||
add_word_settings("GLBOUT.USR_FB2", pos + 42, 1);
|
||||
add_word_settings("GLBOUT.FB2_CFG", pos + 40, 2);
|
||||
add_word_settings("GLBOUT.USR_FB2_EN", pos + 42, 1);
|
||||
// bits 43-47 not used
|
||||
add_word_settings("GLBOUT.GLB3", pos + 48, 3);
|
||||
add_word_settings("GLBOUT.USR_GLB3", pos + 51, 1);
|
||||
add_word_settings("GLBOUT.GLB3_CFG", pos + 48, 3);
|
||||
add_word_settings("GLBOUT.USR_GLB3_EN", pos + 51, 1);
|
||||
add_word_settings("GLBOUT.GLB3_EN", pos + 52, 1);
|
||||
// bits 53-55 not used
|
||||
add_word_settings("GLBOUT.FB3", pos + 56, 2);
|
||||
add_word_settings("GLBOUT.USR_FB3", pos + 58, 1);
|
||||
add_word_settings("GLBOUT.FB3_CFG", pos + 56, 2);
|
||||
add_word_settings("GLBOUT.USR_FB3_EN", pos + 58, 1);
|
||||
// bits 59-63 not used
|
||||
|
||||
pos = Die::STATUS_CFG_START * 8;
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
Binary file not shown.
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,2 @@
|
|||
(kicad_pcb (version 20241229) (generator "pcbnew") (generator_version "9.0")
|
||||
)
|
||||
|
|
@ -0,0 +1,642 @@
|
|||
{
|
||||
"board": {
|
||||
"3dviewports": [],
|
||||
"design_settings": {
|
||||
"defaults": {
|
||||
"apply_defaults_to_fp_fields": false,
|
||||
"apply_defaults_to_fp_shapes": false,
|
||||
"apply_defaults_to_fp_text": false,
|
||||
"board_outline_line_width": 0.05,
|
||||
"copper_line_width": 0.2,
|
||||
"copper_text_italic": false,
|
||||
"copper_text_size_h": 1.5,
|
||||
"copper_text_size_v": 1.5,
|
||||
"copper_text_thickness": 0.3,
|
||||
"copper_text_upright": false,
|
||||
"courtyard_line_width": 0.05,
|
||||
"dimension_precision": 4,
|
||||
"dimension_units": 3,
|
||||
"dimensions": {
|
||||
"arrow_length": 1270000,
|
||||
"extension_offset": 500000,
|
||||
"keep_text_aligned": true,
|
||||
"suppress_zeroes": true,
|
||||
"text_position": 0,
|
||||
"units_format": 0
|
||||
},
|
||||
"fab_line_width": 0.1,
|
||||
"fab_text_italic": false,
|
||||
"fab_text_size_h": 1.0,
|
||||
"fab_text_size_v": 1.0,
|
||||
"fab_text_thickness": 0.15,
|
||||
"fab_text_upright": false,
|
||||
"other_line_width": 0.1,
|
||||
"other_text_italic": false,
|
||||
"other_text_size_h": 1.0,
|
||||
"other_text_size_v": 1.0,
|
||||
"other_text_thickness": 0.15,
|
||||
"other_text_upright": false,
|
||||
"pads": {
|
||||
"drill": 0.8,
|
||||
"height": 1.27,
|
||||
"width": 2.54
|
||||
},
|
||||
"silk_line_width": 0.1,
|
||||
"silk_text_italic": false,
|
||||
"silk_text_size_h": 1.0,
|
||||
"silk_text_size_v": 1.0,
|
||||
"silk_text_thickness": 0.1,
|
||||
"silk_text_upright": false,
|
||||
"zones": {
|
||||
"min_clearance": 0.5
|
||||
}
|
||||
},
|
||||
"diff_pair_dimensions": [],
|
||||
"drc_exclusions": [],
|
||||
"meta": {
|
||||
"version": 2
|
||||
},
|
||||
"rule_severities": {
|
||||
"annular_width": "error",
|
||||
"clearance": "error",
|
||||
"connection_width": "warning",
|
||||
"copper_edge_clearance": "error",
|
||||
"copper_sliver": "warning",
|
||||
"courtyards_overlap": "error",
|
||||
"creepage": "error",
|
||||
"diff_pair_gap_out_of_range": "error",
|
||||
"diff_pair_uncoupled_length_too_long": "error",
|
||||
"drill_out_of_range": "error",
|
||||
"duplicate_footprints": "warning",
|
||||
"extra_footprint": "warning",
|
||||
"footprint": "error",
|
||||
"footprint_filters_mismatch": "ignore",
|
||||
"footprint_symbol_mismatch": "warning",
|
||||
"footprint_type_mismatch": "ignore",
|
||||
"hole_clearance": "error",
|
||||
"hole_to_hole": "warning",
|
||||
"holes_co_located": "warning",
|
||||
"invalid_outline": "error",
|
||||
"isolated_copper": "warning",
|
||||
"item_on_disabled_layer": "error",
|
||||
"items_not_allowed": "error",
|
||||
"length_out_of_range": "error",
|
||||
"lib_footprint_issues": "warning",
|
||||
"lib_footprint_mismatch": "warning",
|
||||
"malformed_courtyard": "error",
|
||||
"microvia_drill_out_of_range": "error",
|
||||
"mirrored_text_on_front_layer": "warning",
|
||||
"missing_courtyard": "ignore",
|
||||
"missing_footprint": "warning",
|
||||
"net_conflict": "warning",
|
||||
"nonmirrored_text_on_back_layer": "warning",
|
||||
"npth_inside_courtyard": "ignore",
|
||||
"padstack": "warning",
|
||||
"pth_inside_courtyard": "ignore",
|
||||
"shorting_items": "error",
|
||||
"silk_edge_clearance": "warning",
|
||||
"silk_over_copper": "warning",
|
||||
"silk_overlap": "warning",
|
||||
"skew_out_of_range": "error",
|
||||
"solder_mask_bridge": "error",
|
||||
"starved_thermal": "error",
|
||||
"text_height": "warning",
|
||||
"text_on_edge_cuts": "error",
|
||||
"text_thickness": "warning",
|
||||
"through_hole_pad_without_hole": "error",
|
||||
"too_many_vias": "error",
|
||||
"track_angle": "error",
|
||||
"track_dangling": "warning",
|
||||
"track_segment_length": "error",
|
||||
"track_width": "error",
|
||||
"tracks_crossing": "error",
|
||||
"unconnected_items": "error",
|
||||
"unresolved_variable": "error",
|
||||
"via_dangling": "warning",
|
||||
"zones_intersect": "error"
|
||||
},
|
||||
"rules": {
|
||||
"max_error": 0.005,
|
||||
"min_clearance": 0.0,
|
||||
"min_connection": 0.0,
|
||||
"min_copper_edge_clearance": 0.5,
|
||||
"min_groove_width": 0.0,
|
||||
"min_hole_clearance": 0.25,
|
||||
"min_hole_to_hole": 0.25,
|
||||
"min_microvia_diameter": 0.2,
|
||||
"min_microvia_drill": 0.1,
|
||||
"min_resolved_spokes": 2,
|
||||
"min_silk_clearance": 0.0,
|
||||
"min_text_height": 0.8,
|
||||
"min_text_thickness": 0.08,
|
||||
"min_through_hole_diameter": 0.3,
|
||||
"min_track_width": 0.0,
|
||||
"min_via_annular_width": 0.1,
|
||||
"min_via_diameter": 0.5,
|
||||
"solder_mask_to_copper_clearance": 0.0,
|
||||
"use_height_for_length_calcs": true
|
||||
},
|
||||
"teardrop_options": [
|
||||
{
|
||||
"td_onpthpad": true,
|
||||
"td_onroundshapesonly": false,
|
||||
"td_onsmdpad": true,
|
||||
"td_ontrackend": false,
|
||||
"td_onvia": true
|
||||
}
|
||||
],
|
||||
"teardrop_parameters": [
|
||||
{
|
||||
"td_allow_use_two_tracks": true,
|
||||
"td_curve_segcount": 0,
|
||||
"td_height_ratio": 1.0,
|
||||
"td_length_ratio": 0.5,
|
||||
"td_maxheight": 2.0,
|
||||
"td_maxlen": 1.0,
|
||||
"td_on_pad_in_zone": false,
|
||||
"td_target_name": "td_round_shape",
|
||||
"td_width_to_size_filter_ratio": 0.9
|
||||
},
|
||||
{
|
||||
"td_allow_use_two_tracks": true,
|
||||
"td_curve_segcount": 0,
|
||||
"td_height_ratio": 1.0,
|
||||
"td_length_ratio": 0.5,
|
||||
"td_maxheight": 2.0,
|
||||
"td_maxlen": 1.0,
|
||||
"td_on_pad_in_zone": false,
|
||||
"td_target_name": "td_rect_shape",
|
||||
"td_width_to_size_filter_ratio": 0.9
|
||||
},
|
||||
{
|
||||
"td_allow_use_two_tracks": true,
|
||||
"td_curve_segcount": 0,
|
||||
"td_height_ratio": 1.0,
|
||||
"td_length_ratio": 0.5,
|
||||
"td_maxheight": 2.0,
|
||||
"td_maxlen": 1.0,
|
||||
"td_on_pad_in_zone": false,
|
||||
"td_target_name": "td_track_end",
|
||||
"td_width_to_size_filter_ratio": 0.9
|
||||
}
|
||||
],
|
||||
"track_widths": [],
|
||||
"tuning_pattern_settings": {
|
||||
"diff_pair_defaults": {
|
||||
"corner_radius_percentage": 80,
|
||||
"corner_style": 1,
|
||||
"max_amplitude": 1.0,
|
||||
"min_amplitude": 0.2,
|
||||
"single_sided": false,
|
||||
"spacing": 1.0
|
||||
},
|
||||
"diff_pair_skew_defaults": {
|
||||
"corner_radius_percentage": 80,
|
||||
"corner_style": 1,
|
||||
"max_amplitude": 1.0,
|
||||
"min_amplitude": 0.2,
|
||||
"single_sided": false,
|
||||
"spacing": 0.6
|
||||
},
|
||||
"single_track_defaults": {
|
||||
"corner_radius_percentage": 80,
|
||||
"corner_style": 1,
|
||||
"max_amplitude": 1.0,
|
||||
"min_amplitude": 0.2,
|
||||
"single_sided": false,
|
||||
"spacing": 0.6
|
||||
}
|
||||
},
|
||||
"via_dimensions": [],
|
||||
"zones_allow_external_fillets": false
|
||||
},
|
||||
"ipc2581": {
|
||||
"dist": "",
|
||||
"distpn": "",
|
||||
"internal_id": "",
|
||||
"mfg": "",
|
||||
"mpn": ""
|
||||
},
|
||||
"layer_pairs": [],
|
||||
"layer_presets": [],
|
||||
"viewports": []
|
||||
},
|
||||
"boards": [],
|
||||
"cvpcb": {
|
||||
"equivalence_files": []
|
||||
},
|
||||
"erc": {
|
||||
"erc_exclusions": [],
|
||||
"meta": {
|
||||
"version": 0
|
||||
},
|
||||
"pin_map": [
|
||||
[
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
2
|
||||
],
|
||||
[
|
||||
0,
|
||||
2,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2
|
||||
],
|
||||
[
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
1,
|
||||
2
|
||||
],
|
||||
[
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
1,
|
||||
2,
|
||||
1,
|
||||
1,
|
||||
2
|
||||
],
|
||||
[
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
2
|
||||
],
|
||||
[
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
2
|
||||
],
|
||||
[
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
0,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
2
|
||||
],
|
||||
[
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
2
|
||||
],
|
||||
[
|
||||
0,
|
||||
2,
|
||||
1,
|
||||
2,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2
|
||||
],
|
||||
[
|
||||
0,
|
||||
2,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
2,
|
||||
0,
|
||||
0,
|
||||
2
|
||||
],
|
||||
[
|
||||
0,
|
||||
2,
|
||||
1,
|
||||
1,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
2,
|
||||
0,
|
||||
0,
|
||||
2
|
||||
],
|
||||
[
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2
|
||||
]
|
||||
],
|
||||
"rule_severities": {
|
||||
"bus_definition_conflict": "error",
|
||||
"bus_entry_needed": "error",
|
||||
"bus_to_bus_conflict": "error",
|
||||
"bus_to_net_conflict": "error",
|
||||
"different_unit_footprint": "error",
|
||||
"different_unit_net": "error",
|
||||
"duplicate_reference": "error",
|
||||
"duplicate_sheet_names": "error",
|
||||
"endpoint_off_grid": "warning",
|
||||
"extra_units": "error",
|
||||
"footprint_filter": "ignore",
|
||||
"footprint_link_issues": "warning",
|
||||
"four_way_junction": "ignore",
|
||||
"global_label_dangling": "warning",
|
||||
"hier_label_mismatch": "error",
|
||||
"label_dangling": "error",
|
||||
"label_multiple_wires": "warning",
|
||||
"lib_symbol_issues": "warning",
|
||||
"lib_symbol_mismatch": "warning",
|
||||
"missing_bidi_pin": "warning",
|
||||
"missing_input_pin": "warning",
|
||||
"missing_power_pin": "error",
|
||||
"missing_unit": "warning",
|
||||
"multiple_net_names": "warning",
|
||||
"net_not_bus_member": "warning",
|
||||
"no_connect_connected": "warning",
|
||||
"no_connect_dangling": "warning",
|
||||
"pin_not_connected": "error",
|
||||
"pin_not_driven": "error",
|
||||
"pin_to_pin": "warning",
|
||||
"power_pin_not_driven": "error",
|
||||
"same_local_global_label": "warning",
|
||||
"similar_label_and_power": "warning",
|
||||
"similar_labels": "warning",
|
||||
"similar_power": "warning",
|
||||
"simulation_model_issue": "ignore",
|
||||
"single_global_label": "ignore",
|
||||
"unannotated": "error",
|
||||
"unconnected_wire_endpoint": "warning",
|
||||
"unit_value_mismatch": "error",
|
||||
"unresolved_variable": "error",
|
||||
"wire_dangling": "error"
|
||||
}
|
||||
},
|
||||
"libraries": {
|
||||
"pinned_footprint_libs": [],
|
||||
"pinned_symbol_libs": []
|
||||
},
|
||||
"meta": {
|
||||
"filename": "prjpeppercorn.kicad_pro",
|
||||
"version": 3
|
||||
},
|
||||
"net_settings": {
|
||||
"classes": [
|
||||
{
|
||||
"bus_width": 12,
|
||||
"clearance": 0.2,
|
||||
"diff_pair_gap": 0.25,
|
||||
"diff_pair_via_gap": 0.25,
|
||||
"diff_pair_width": 0.2,
|
||||
"line_style": 0,
|
||||
"microvia_diameter": 0.3,
|
||||
"microvia_drill": 0.1,
|
||||
"name": "Default",
|
||||
"pcb_color": "rgba(0, 0, 0, 0.000)",
|
||||
"priority": 2147483647,
|
||||
"schematic_color": "rgba(0, 0, 0, 0.000)",
|
||||
"track_width": 0.2,
|
||||
"via_diameter": 0.6,
|
||||
"via_drill": 0.3,
|
||||
"wire_width": 6
|
||||
}
|
||||
],
|
||||
"meta": {
|
||||
"version": 4
|
||||
},
|
||||
"net_colors": null,
|
||||
"netclass_assignments": null,
|
||||
"netclass_patterns": []
|
||||
},
|
||||
"pcbnew": {
|
||||
"last_paths": {
|
||||
"gencad": "",
|
||||
"idf": "",
|
||||
"netlist": "",
|
||||
"plot": "",
|
||||
"pos_files": "",
|
||||
"specctra_dsn": "",
|
||||
"step": "",
|
||||
"svg": "",
|
||||
"vrml": ""
|
||||
},
|
||||
"page_layout_descr_file": ""
|
||||
},
|
||||
"schematic": {
|
||||
"annotate_start_num": 0,
|
||||
"bom_export_filename": "${PROJECTNAME}.csv",
|
||||
"bom_fmt_presets": [],
|
||||
"bom_fmt_settings": {
|
||||
"field_delimiter": ",",
|
||||
"keep_line_breaks": false,
|
||||
"keep_tabs": false,
|
||||
"name": "CSV",
|
||||
"ref_delimiter": ",",
|
||||
"ref_range_delimiter": "",
|
||||
"string_delimiter": "\""
|
||||
},
|
||||
"bom_presets": [],
|
||||
"bom_settings": {
|
||||
"exclude_dnp": false,
|
||||
"fields_ordered": [
|
||||
{
|
||||
"group_by": false,
|
||||
"label": "Reference",
|
||||
"name": "Reference",
|
||||
"show": true
|
||||
},
|
||||
{
|
||||
"group_by": false,
|
||||
"label": "Qty",
|
||||
"name": "${QUANTITY}",
|
||||
"show": true
|
||||
},
|
||||
{
|
||||
"group_by": true,
|
||||
"label": "Value",
|
||||
"name": "Value",
|
||||
"show": true
|
||||
},
|
||||
{
|
||||
"group_by": true,
|
||||
"label": "DNP",
|
||||
"name": "${DNP}",
|
||||
"show": true
|
||||
},
|
||||
{
|
||||
"group_by": true,
|
||||
"label": "Exclude from BOM",
|
||||
"name": "${EXCLUDE_FROM_BOM}",
|
||||
"show": true
|
||||
},
|
||||
{
|
||||
"group_by": true,
|
||||
"label": "Exclude from Board",
|
||||
"name": "${EXCLUDE_FROM_BOARD}",
|
||||
"show": true
|
||||
},
|
||||
{
|
||||
"group_by": true,
|
||||
"label": "Footprint",
|
||||
"name": "Footprint",
|
||||
"show": true
|
||||
},
|
||||
{
|
||||
"group_by": false,
|
||||
"label": "Datasheet",
|
||||
"name": "Datasheet",
|
||||
"show": true
|
||||
}
|
||||
],
|
||||
"filter_string": "",
|
||||
"group_symbols": true,
|
||||
"include_excluded_from_bom": true,
|
||||
"name": "Default Editing",
|
||||
"sort_asc": true,
|
||||
"sort_field": "Reference"
|
||||
},
|
||||
"connection_grid_size": 50.0,
|
||||
"drawing": {
|
||||
"dashed_lines_dash_length_ratio": 12.0,
|
||||
"dashed_lines_gap_length_ratio": 3.0,
|
||||
"default_line_thickness": 6.0,
|
||||
"default_text_size": 50.0,
|
||||
"field_names": [],
|
||||
"intersheets_ref_own_page": false,
|
||||
"intersheets_ref_prefix": "",
|
||||
"intersheets_ref_short": false,
|
||||
"intersheets_ref_show": false,
|
||||
"intersheets_ref_suffix": "",
|
||||
"junction_size_choice": 3,
|
||||
"label_size_ratio": 0.375,
|
||||
"operating_point_overlay_i_precision": 3,
|
||||
"operating_point_overlay_i_range": "~A",
|
||||
"operating_point_overlay_v_precision": 3,
|
||||
"operating_point_overlay_v_range": "~V",
|
||||
"overbar_offset_ratio": 1.23,
|
||||
"pin_symbol_size": 25.0,
|
||||
"text_offset_ratio": 0.15
|
||||
},
|
||||
"legacy_lib_dir": "",
|
||||
"legacy_lib_list": [],
|
||||
"meta": {
|
||||
"version": 1
|
||||
},
|
||||
"net_format_name": "",
|
||||
"page_layout_descr_file": "",
|
||||
"plot_directory": "",
|
||||
"space_save_all_events": true,
|
||||
"spice_current_sheet_as_root": false,
|
||||
"spice_external_command": "spice \"%I\"",
|
||||
"spice_model_current_sheet_as_root": true,
|
||||
"spice_save_all_currents": false,
|
||||
"spice_save_all_dissipations": false,
|
||||
"spice_save_all_voltages": false,
|
||||
"subpart_first_id": 65,
|
||||
"subpart_id_separator": 0
|
||||
},
|
||||
"sheets": [
|
||||
[
|
||||
"5a7723f7-3f6f-437e-b958-e402b06d3f54",
|
||||
"Root"
|
||||
],
|
||||
[
|
||||
"cb769740-e0a9-4f3d-b622-ba158089ec4b",
|
||||
"Cologne Processing Element"
|
||||
],
|
||||
[
|
||||
"72ce5b8e-65cd-4ef4-93c6-ada8bc7993bf",
|
||||
"C_FUNCTION=0"
|
||||
],
|
||||
[
|
||||
"c7e1e454-4a3a-497b-82a6-da398b72cabb",
|
||||
"C_FUNCTION=1"
|
||||
],
|
||||
[
|
||||
"2cdae2f1-b557-4e09-a2ce-72fe69c1cde7",
|
||||
"C_FUNCTION=4"
|
||||
],
|
||||
[
|
||||
"2f1e56f5-88a6-4944-a409-72559104271f",
|
||||
"C_FUNCTION=5"
|
||||
],
|
||||
[
|
||||
"7870fc3a-1ee9-4a55-a2a2-8f09313f282c",
|
||||
"C_FUNCTION=6"
|
||||
]
|
||||
],
|
||||
"text_variables": {}
|
||||
}
|
||||
|
|
@ -0,0 +1,59 @@
|
|||
(kicad_sch
|
||||
(version 20250114)
|
||||
(generator "eeschema")
|
||||
(generator_version "9.0")
|
||||
(uuid "5a7723f7-3f6f-437e-b958-e402b06d3f54")
|
||||
(paper "A3")
|
||||
(title_block
|
||||
(company "YosysHQ")
|
||||
)
|
||||
(lib_symbols)
|
||||
(sheet
|
||||
(at 31.75 26.035)
|
||||
(size 19.05 18.415)
|
||||
(exclude_from_sim no)
|
||||
(in_bom yes)
|
||||
(on_board yes)
|
||||
(dnp no)
|
||||
(fields_autoplaced yes)
|
||||
(stroke
|
||||
(width 0.1524)
|
||||
(type solid)
|
||||
)
|
||||
(fill
|
||||
(color 0 0 0 0.0000)
|
||||
)
|
||||
(uuid "cb769740-e0a9-4f3d-b622-ba158089ec4b")
|
||||
(property "Sheetname" "Cologne Processing Element"
|
||||
(at 31.75 25.3234 0)
|
||||
(effects
|
||||
(font
|
||||
(size 1.27 1.27)
|
||||
)
|
||||
(justify left bottom)
|
||||
)
|
||||
)
|
||||
(property "Sheetfile" "cpe.kicad_sch"
|
||||
(at 31.75 45.0346 0)
|
||||
(effects
|
||||
(font
|
||||
(size 1.27 1.27)
|
||||
)
|
||||
(justify left top)
|
||||
)
|
||||
)
|
||||
(instances
|
||||
(project "prjpeppercorn"
|
||||
(path "/5a7723f7-3f6f-437e-b958-e402b06d3f54"
|
||||
(page "2")
|
||||
)
|
||||
)
|
||||
)
|
||||
)
|
||||
(sheet_instances
|
||||
(path "/"
|
||||
(page "1")
|
||||
)
|
||||
)
|
||||
(embedded_fonts no)
|
||||
)
|
||||
|
|
@ -0,0 +1,4 @@
|
|||
(sym_lib_table
|
||||
(version 7)
|
||||
(lib (name "peppercorn")(type "KiCad")(uri "${KIPRJMOD}/peppercorn.kicad_sym")(options "")(descr ""))
|
||||
)
|
||||
Loading…
Reference in New Issue