luke
/
prjpeppercorn
mirror of https://github.com/YosysHQ/prjpeppercorn.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Merge pull request #6 from YosysHQ/new_timing 

gatemate: add IOSEL as separate primitive
This commit is contained in:
Miodrag Milanović 2025-08-14 12:20:15 +02:00 committed by GitHub
parent d7e7bf6e93 6ad315609d
commit 22ec1e2d7b
No known key found for this signature in database
GPG Key ID: B5690EEEBB952194
2 changed files with 47 additions and 33 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

28
gatemate/chip.py
View File

@ -23,7 +23,7 @@ from dataclasses import dataclass
from typing import List, Dict from typing import List, Dict
from timing import decompress_timing from timing import decompress_timing
DATABASE_VERSION = 1.3 DATABASE_VERSION = 1.4
@dataclass(eq=True, order=True) @dataclass(eq=True, order=True)
class Pad: class Pad:
@ -172,7 +172,7 @@ class Chip:
if bank.bank == "W2" and p == "A" and num in [5,6,7,8]: if bank.bank == "W2" and p == "A" and num in [5,6,7,8]:
flags = 8-num+1 # will be 1-4 for different clock sources flags = 8-num+1 # will be 1-4 for different clock sources
if pad_name not in not_exist: if pad_name not in not_exist:
pads.append(Pad(loc.x + d.offset_x,loc.y + d.offset_y,pad_name,"GPIO","",self.get_bank_number(bank.bank),flags,ddr)) pads.append(Pad(loc.x + d.offset_x,loc.y + d.offset_y,pad_name,"IOSEL","",self.get_bank_number(bank.bank),flags,ddr))
return pads return pads
CCGM1_DEVICES = { CCGM1_DEVICES = {
@ -352,8 +352,8 @@ def get_timings(name):
name = f"edge_xy{i1-2}_s{i2+1}_{inputs[i3]}_{outputs[i4]}" name = f"edge_xy{i1-2}_s{i2+1}_{inputs[i3]}_{outputs[i4]}"
val[name] = convert_delay(d) val[name] = convert_delay(d)
inputs = [ 'CLOCK0','CLOCK1','CLOCK2','CLOCK3','OUT1_I','OUT2_I','OUT3_I','OUT4_I','GPIO_IN','RESET','DDR_I'] inputs = [ 'CLOCK0','CLOCK1','CLOCK2','CLOCK3','OUT1','OUT2','OUT3','OUT4','GPIO_IN','RESET','DDR']
outputs = [ 'IN1_O','IN2_O','GPIO_OUT','GPIO_EN' ] outputs = [ 'IN1','IN2','GPIO_OUT','GPIO_EN' ]
for i1 in range(11): # [1..11] for i1 in range(11): # [1..11]
for i2 in range(4): # [1..4] for i2 in range(4): # [1..4]
@ -364,8 +364,8 @@ def get_timings(name):
val[name] = convert_delay(d) val[name] = convert_delay(d)
inputs = [ 'CLK0_I','CLK1_I','CLK2_I','CLK3_I','SERDES_CLK','SPI_CLK','JTAG_CLK'] inputs = [ 'CLK0','CLK1','CLK2','CLK3','SER_CLK','SPI_CLK','JTAG_CLK']
outputs = [ 'CLK_OUT0','CLK_OUT1','CLK_OUT2','CLK_OUT3' ] outputs = [ 'CLK_REF0','CLK_REF1','CLK_REF2','CLK_REF3' ]
for i1 in range(7): # [1..7] for i1 in range(7): # [1..7]
for i2 in range(4): # [1..4] for i2 in range(4): # [1..4]
d = timing_data.CLKIN_del_arr[i1][i2] d = timing_data.CLKIN_del_arr[i1][i2]
@ -374,13 +374,13 @@ def get_timings(name):
name = f"clkin_{inputs[i1]}_{outputs[i2]}" name = f"clkin_{inputs[i1]}_{outputs[i2]}"
val[name] = convert_delay(d) val[name] = convert_delay(d)
inputs = [ 'CLK0_0','CLK90_0','CLK180_0','CLK270_0','CLKREF_0', inputs = [ 'CLK0_0','CLK90_0','CLK180_0','CLK270_0','CLK_REF_OUT0',
'CLK0_1','CLK90_1','CLK180_1','CLK270_1','CLKREF_1', 'CLK0_1','CLK90_1','CLK180_1','CLK270_1','CLK_REF_OUT1',
'CLK0_2','CLK90_2','CLK180_2','CLK270_2','CLKREF_2', 'CLK0_2','CLK90_2','CLK180_2','CLK270_2','CLK_REF_OUT2',
'CLK0_3','CLK90_3','CLK180_3','CLK270_3','CLKREF_3', 'CLK0_3','CLK90_3','CLK180_3','CLK270_3','CLK_REF_OUT3',
'U_CLK0','U_CLK1','U_CLK2','U_CLK3', 'USR_GLB0','USR_GLB1','USR_GLB2','USR_GLB3',
'U_FB0', 'U_FB1', 'U_FB2', 'U_FB3' ] 'USR_FB0', 'USR_FB1', 'USR_FB2', 'USR_FB3' ]
outputs = [ 'CLOCK0','CLOCK1','CLOCK2','CLOCK3', outputs = [ 'GLB0','GLB1','GLB2','GLB3',
'CLK_FB0','CLK_FB1','CLK_FB2','CLK_FB3'] 'CLK_FB0','CLK_FB1','CLK_FB2','CLK_FB3']
for i1 in range(28): # [1..28] for i1 in range(28): # [1..28]
for i2 in range(8): # [1..8] for i2 in range(8): # [1..8]
@ -390,7 +390,7 @@ def get_timings(name):
name = f"glbout_{inputs[i1]}_{outputs[i2]}" name = f"glbout_{inputs[i1]}_{outputs[i2]}"
val[name] = convert_delay(d) val[name] = convert_delay(d)
# All feedback delays calculated are same, we just take one # All feedback delays calculated are same, we just take one
val["glbout_FEEDBACK_delay"] = val["glbout_CLK0_0_CLK_FB0"] - val["glbout_CLK0_0_CLOCK0"] val["glbout_FEEDBACK_delay"] = val["glbout_CLK0_0_CLK_FB0"] - val["glbout_CLK0_0_GLB0"]
inputs = ['clk_ref_i','clock_core0_i','adpll_enable_i','adpll_status_read_i','locked_steady_reset_i','autn_en_i','reset_n_i'] inputs = ['clk_ref_i','clock_core0_i','adpll_enable_i','adpll_status_read_i','locked_steady_reset_i','autn_en_i','reset_n_i']
outputs = ['clk_core0_o','clk_core90_o','clk_core180_o','clk_core270_o', 'pll_locked_o', 'pll_locked_steady_o'] outputs = ['clk_core0_o','clk_core90_o','clk_core180_o','clk_core270_o', 'pll_locked_o', 'pll_locked_steady_o']

52
gatemate/die.py
View File

@ -340,9 +340,9 @@ PRIMITIVES_PINS = {
Pin("COMPOUT",PinType.OUTPUT, "CPE_WIRE", True), Pin("COMPOUT",PinType.OUTPUT, "CPE_WIRE", True),
], ],
"CPE_CPLINES": [ "CPE_CPLINES": [
Pin("OUT1" ,PinType.OUTPUT, "CPE_WIRE", True), Pin("OUT1" ,PinType.INPUT, "CPE_WIRE", True),
Pin("OUT2" ,PinType.OUTPUT, "CPE_WIRE", True), Pin("OUT2" ,PinType.INPUT, "CPE_WIRE", True),
Pin("COMPOUT",PinType.OUTPUT, "CPE_WIRE", True), Pin("COMPOUT",PinType.INPUT, "CPE_WIRE", True),
Pin("CINX" ,PinType.INPUT, "CPE_WIRE", True), Pin("CINX" ,PinType.INPUT, "CPE_WIRE", True),
Pin("PINX" ,PinType.INPUT, "CPE_WIRE", True), Pin("PINX" ,PinType.INPUT, "CPE_WIRE", True),
@ -357,8 +357,11 @@ PRIMITIVES_PINS = {
Pin("COUTY2" ,PinType.OUTPUT, "CPE_WIRE", True), Pin("COUTY2" ,PinType.OUTPUT, "CPE_WIRE", True),
Pin("POUTY2" ,PinType.OUTPUT, "CPE_WIRE", True), Pin("POUTY2" ,PinType.OUTPUT, "CPE_WIRE", True),
], ],
"IOSEL" : [
Pin("GPIO_OUT", PinType.OUTPUT,"GPIO_WIRE"),
Pin("GPIO_EN" , PinType.OUTPUT,"GPIO_WIRE"),
Pin("GPIO_IN" , PinType.INPUT, "GPIO_WIRE"),
"GPIO" : [
Pin("IN1" , PinType.OUTPUT,"GPIO_WIRE"), Pin("IN1" , PinType.OUTPUT,"GPIO_WIRE"),
Pin("IN2" , PinType.OUTPUT,"GPIO_WIRE"), Pin("IN2" , PinType.OUTPUT,"GPIO_WIRE"),
Pin("OUT1" , PinType.INPUT, "GPIO_WIRE"), Pin("OUT1" , PinType.INPUT, "GPIO_WIRE"),
@ -372,6 +375,12 @@ PRIMITIVES_PINS = {
Pin("CLOCK2", PinType.INPUT, "GPIO_WIRE"), Pin("CLOCK2", PinType.INPUT, "GPIO_WIRE"),
Pin("CLOCK3", PinType.INPUT, "GPIO_WIRE"), Pin("CLOCK3", PinType.INPUT, "GPIO_WIRE"),
Pin("CLOCK4", PinType.INPUT, "GPIO_WIRE"), Pin("CLOCK4", PinType.INPUT, "GPIO_WIRE"),
],
"GPIO" : [
Pin("Y", PinType.INPUT, "GPIO_WIRE"),
Pin("T", PinType.INPUT, "GPIO_WIRE"),
Pin("A", PinType.OUTPUT,"GPIO_WIRE"),
# PAD wires # PAD wires
Pin("I", PinType.INPUT, "GPIO_WIRE"), Pin("I", PinType.INPUT, "GPIO_WIRE"),
Pin("O", PinType.OUTPUT,"GPIO_WIRE"), Pin("O", PinType.OUTPUT,"GPIO_WIRE"),
@ -1427,6 +1436,7 @@ def get_primitives_for_type(type):
primitives.append(Primitive("SERDES","SERDES",10)) primitives.append(Primitive("SERDES","SERDES",10))
if "GPIO" in type: if "GPIO" in type:
primitives.append(Primitive("GPIO","GPIO",0)) primitives.append(Primitive("GPIO","GPIO",0))
primitives.append(Primitive("IOSEL","IOSEL",1))
if "PLL" in type: if "PLL" in type:
primitives.append(Primitive("CLKIN","CLKIN",0)) primitives.append(Primitive("CLKIN","CLKIN",0))
primitives.append(Primitive("GLBOUT","GLBOUT",1)) primitives.append(Primitive("GLBOUT","GLBOUT",1))
@ -2358,7 +2368,7 @@ def get_pins_constraint(type_name, prim_name, prim_type):
val.append(PinConstr("TX_POWER_DOWN_N_I", 25, 4, RAM_OUTPUT, 1)) val.append(PinConstr("TX_POWER_DOWN_N_I", 25, 4, RAM_OUTPUT, 1))
val.append(PinConstr("RX_POWER_DOWN_N_I", 25, 2, RAM_OUTPUT, 1)) val.append(PinConstr("RX_POWER_DOWN_N_I", 25, 2, RAM_OUTPUT, 1))
val.append(PinConstr("TX_ELEC_IDLE_I", 25, 0, RAM_OUTPUT, 1)) val.append(PinConstr("TX_ELEC_IDLE_I", 25, 0, RAM_OUTPUT, 1))
elif prim_type=="GPIO": elif prim_type=="IOSEL":
if "LES" in type_name: if "LES" in type_name:
val.append(PinConstr("OUT4", 3, 1, RAM_OUTPUT, 2)) val.append(PinConstr("OUT4", 3, 1, RAM_OUTPUT, 2))
val.append(PinConstr("OUT3", 3, 1, RAM_OUTPUT, 1)) val.append(PinConstr("OUT3", 3, 1, RAM_OUTPUT, 1))
@ -2845,8 +2855,12 @@ def get_mux_connections_for_type(type):
create_mux(f"SB_SML.P{plane}.Y4_int", f"SB_SML.P{plane}.Y4", 1, 1, True, f"SB_SML.P{plane}.Y4_INT", False, delay="del_dummy") create_mux(f"SB_SML.P{plane}.Y4_int", f"SB_SML.P{plane}.Y4", 1, 1, True, f"SB_SML.P{plane}.Y4_INT", False, delay="del_dummy")
create_mux(f"SB_SML.P{plane}.YDIAG_int", f"SB_SML.P{plane}.YDIAG", 1, 1, True, f"SB_SML.P{plane}.YDIAG_INT", False, delay="del_dummy") create_mux(f"SB_SML.P{plane}.YDIAG_int", f"SB_SML.P{plane}.YDIAG", 1, 1, True, f"SB_SML.P{plane}.YDIAG_INT", False, delay="del_dummy")
#if "GPIO" in type: if "GPIO" in type:
# # GPIO # GPIO
create_mux("IOSEL.GPIO_OUT", "GPIO.A", 1, 0, False, visible=False, delay="del_dummy")
create_mux("IOSEL.GPIO_EN", "GPIO.T", 1, 0, False, visible=False, delay="del_dummy")
create_mux("GPIO.Y", "IOSEL.GPIO_IN", 1, 0, False, visible=False, delay="del_dummy")
if "IOES" in type: if "IOES" in type:
# IOES # IOES
for p in range(1,13): for p in range(1,13):
@ -3300,15 +3314,15 @@ class Die:
plane = f"{p:02d}" plane = f"{p:02d}"
self.create_conn(sb_x,sb_y,f"{get_sb_type(sb_x,sb_y)}.P{plane}.{output}", x,y, f"IOES.ALTIN_{plane}") self.create_conn(sb_x,sb_y,f"{get_sb_type(sb_x,sb_y)}.P{plane}.{output}", x,y, f"IOES.ALTIN_{plane}")
self.create_conn(x,y, f"IOES.SB_IN_{plane}", sb_x,sb_y,f"{get_sb_type(sb_x,sb_y)}.P{plane}.D0") self.create_conn(x,y, f"IOES.SB_IN_{plane}", sb_x,sb_y,f"{get_sb_type(sb_x,sb_y)}.P{plane}.D0")
self.create_conn(gpio_x,gpio_y,"GPIO.IN1", x,y, "IOES.IO_IN1") self.create_conn(gpio_x,gpio_y,"IOSEL.IN1", x,y, "IOES.IO_IN1")
self.create_conn(gpio_x,gpio_y,"GPIO.IN2", x,y, "IOES.IO_IN2") self.create_conn(gpio_x,gpio_y,"IOSEL.IN2", x,y, "IOES.IO_IN2")
if not alt: if not alt:
self.create_ram_io_conn("GPIO", "GPIO", x, y) self.create_ram_io_conn("IOSEL", "IOSEL", x, y)
self.create_conn(PLL_X_POS, PLL_Y_POS, "GLBOUT.GLB0", gpio_x, gpio_y, "GPIO.CLOCK1", "del_GLBOUT_IO_SEL") self.create_conn(PLL_X_POS, PLL_Y_POS, "GLBOUT.GLB0", gpio_x, gpio_y, "IOSEL.CLOCK1", "del_GLBOUT_IO_SEL")
self.create_conn(PLL_X_POS, PLL_Y_POS, "GLBOUT.GLB1", gpio_x, gpio_y, "GPIO.CLOCK2", "del_GLBOUT_IO_SEL") self.create_conn(PLL_X_POS, PLL_Y_POS, "GLBOUT.GLB1", gpio_x, gpio_y, "IOSEL.CLOCK2", "del_GLBOUT_IO_SEL")
self.create_conn(PLL_X_POS, PLL_Y_POS, "GLBOUT.GLB2", gpio_x, gpio_y, "GPIO.CLOCK3", "del_GLBOUT_IO_SEL") self.create_conn(PLL_X_POS, PLL_Y_POS, "GLBOUT.GLB2", gpio_x, gpio_y, "IOSEL.CLOCK3", "del_GLBOUT_IO_SEL")
self.create_conn(PLL_X_POS, PLL_Y_POS, "GLBOUT.GLB3", gpio_x, gpio_y, "GPIO.CLOCK4", "del_GLBOUT_IO_SEL") self.create_conn(PLL_X_POS, PLL_Y_POS, "GLBOUT.GLB3", gpio_x, gpio_y, "IOSEL.CLOCK4", "del_GLBOUT_IO_SEL")
def create_pll(self): def create_pll(self):
# GPIO_W2_A[8] CLK0 # GPIO_W2_A[8] CLK0
@ -3319,13 +3333,13 @@ class Die:
# GPIO_S3_B[8] SPI_CLK # GPIO_S3_B[8] SPI_CLK
# GPIO_S3_A[5] JTAG_CLK # GPIO_S3_A[5] JTAG_CLK
loc = self.gpio_to_loc["GPIO_W2_A[8]"] loc = self.gpio_to_loc["GPIO_W2_A[8]"]
self.create_conn(loc.x, loc.y, "GPIO.IN1", PLL_X_POS, PLL_Y_POS, "CLKIN.CLK0") self.create_conn(loc.x, loc.y, "IOSEL.IN1", PLL_X_POS, PLL_Y_POS, "CLKIN.CLK0")
loc = self.gpio_to_loc["GPIO_W2_A[7]"] loc = self.gpio_to_loc["GPIO_W2_A[7]"]
self.create_conn(loc.x, loc.y, "GPIO.IN1", PLL_X_POS, PLL_Y_POS, "CLKIN.CLK1") self.create_conn(loc.x, loc.y, "IOSEL.IN1", PLL_X_POS, PLL_Y_POS, "CLKIN.CLK1")
loc = self.gpio_to_loc["GPIO_W2_A[6]"] loc = self.gpio_to_loc["GPIO_W2_A[6]"]
self.create_conn(loc.x, loc.y, "GPIO.IN1", PLL_X_POS, PLL_Y_POS, "CLKIN.CLK2") self.create_conn(loc.x, loc.y, "IOSEL.IN1", PLL_X_POS, PLL_Y_POS, "CLKIN.CLK2")
loc = self.gpio_to_loc["GPIO_W2_A[5]"] loc = self.gpio_to_loc["GPIO_W2_A[5]"]
self.create_conn(loc.x, loc.y, "GPIO.IN1", PLL_X_POS, PLL_Y_POS, "CLKIN.CLK3") self.create_conn(loc.x, loc.y, "IOSEL.IN1", PLL_X_POS, PLL_Y_POS, "CLKIN.CLK3")
self.create_ram_io_conn("GLBOUT", "GLBOUT", PLL_X_POS, PLL_Y_POS) self.create_ram_io_conn("GLBOUT", "GLBOUT", PLL_X_POS, PLL_Y_POS)
@ -3463,7 +3477,7 @@ class Die:
for port in ['A','B']: for port in ['A','B']:
for num in range(0,9): for num in range(0,9):
loc = self.io_pad_names[bank][port][num] loc = self.io_pad_names[bank][port][num]
self.create_conn(x, y , f"CPE.RAM_O{out}", loc.x, loc.y, "GPIO.DDR") self.create_conn(x, y , f"CPE.RAM_O{out}", loc.x, loc.y, "IOSEL.DDR")
self.ddr_i[bank] = Location(x+self.offset_x,y+self.offset_y,2-out) self.ddr_i[bank] = Location(x+self.offset_x,y+self.offset_y,2-out)
def misc_connections(self): def misc_connections(self):