From 7d94d89855979d351767c8707f3ca3f04b276a01 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Wed, 13 Aug 2025 12:51:33 +0200 Subject: [PATCH 1/4] Fix direction --- gatemate/die.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/gatemate/die.py b/gatemate/die.py index 952836e..58e3d42 100644 --- a/gatemate/die.py +++ b/gatemate/die.py @@ -340,9 +340,9 @@ PRIMITIVES_PINS = { Pin("COMPOUT",PinType.OUTPUT, "CPE_WIRE", True), ], "CPE_CPLINES": [ - Pin("OUT1" ,PinType.OUTPUT, "CPE_WIRE", True), - Pin("OUT2" ,PinType.OUTPUT, "CPE_WIRE", True), - Pin("COMPOUT",PinType.OUTPUT, "CPE_WIRE", True), + Pin("OUT1" ,PinType.INPUT, "CPE_WIRE", True), + Pin("OUT2" ,PinType.INPUT, "CPE_WIRE", True), + Pin("COMPOUT",PinType.INPUT, "CPE_WIRE", True), Pin("CINX" ,PinType.INPUT, "CPE_WIRE", True), Pin("PINX" ,PinType.INPUT, "CPE_WIRE", True), From 0fb182de180fbb4a6e8ec58f3da3787a9246ffd6 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Wed, 13 Aug 2025 12:52:04 +0200 Subject: [PATCH 2/4] rename to match port names --- gatemate/chip.py | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/gatemate/chip.py b/gatemate/chip.py index 84973a8..de31e53 100644 --- a/gatemate/chip.py +++ b/gatemate/chip.py @@ -352,8 +352,8 @@ def get_timings(name): name = f"edge_xy{i1-2}_s{i2+1}_{inputs[i3]}_{outputs[i4]}" val[name] = convert_delay(d) - inputs = [ 'CLOCK0','CLOCK1','CLOCK2','CLOCK3','OUT1_I','OUT2_I','OUT3_I','OUT4_I','GPIO_IN','RESET','DDR_I'] - outputs = [ 'IN1_O','IN2_O','GPIO_OUT','GPIO_EN' ] + inputs = [ 'CLOCK0','CLOCK1','CLOCK2','CLOCK3','OUT1','OUT2','OUT3','OUT4','GPIO_IN','RESET','DDR'] + outputs = [ 'IN1','IN2','GPIO_OUT','GPIO_EN' ] for i1 in range(11): # [1..11] for i2 in range(4): # [1..4] @@ -364,8 +364,8 @@ def get_timings(name): val[name] = convert_delay(d) - inputs = [ 'CLK0_I','CLK1_I','CLK2_I','CLK3_I','SERDES_CLK','SPI_CLK','JTAG_CLK'] - outputs = [ 'CLK_OUT0','CLK_OUT1','CLK_OUT2','CLK_OUT3' ] + inputs = [ 'CLK0','CLK1','CLK2','CLK3','SER_CLK','SPI_CLK','JTAG_CLK'] + outputs = [ 'CLK_REF0','CLK_REF1','CLK_REF2','CLK_REF3' ] for i1 in range(7): # [1..7] for i2 in range(4): # [1..4] d = timing_data.CLKIN_del_arr[i1][i2] @@ -374,13 +374,13 @@ def get_timings(name): name = f"clkin_{inputs[i1]}_{outputs[i2]}" val[name] = convert_delay(d) - inputs = [ 'CLK0_0','CLK90_0','CLK180_0','CLK270_0','CLKREF_0', - 'CLK0_1','CLK90_1','CLK180_1','CLK270_1','CLKREF_1', - 'CLK0_2','CLK90_2','CLK180_2','CLK270_2','CLKREF_2', - 'CLK0_3','CLK90_3','CLK180_3','CLK270_3','CLKREF_3', - 'U_CLK0','U_CLK1','U_CLK2','U_CLK3', - 'U_FB0', 'U_FB1', 'U_FB2', 'U_FB3' ] - outputs = [ 'CLOCK0','CLOCK1','CLOCK2','CLOCK3', + inputs = [ 'CLK0_0','CLK90_0','CLK180_0','CLK270_0','CLK_REF_OUT0', + 'CLK0_1','CLK90_1','CLK180_1','CLK270_1','CLK_REF_OUT1', + 'CLK0_2','CLK90_2','CLK180_2','CLK270_2','CLK_REF_OUT2', + 'CLK0_3','CLK90_3','CLK180_3','CLK270_3','CLK_REF_OUT3', + 'USR_GLB0','USR_GLB1','USR_GLB2','USR_GLB3', + 'USR_FB0', 'USR_FB1', 'USR_FB2', 'USR_FB3' ] + outputs = [ 'GLB0','GLB1','GLB2','GLB3', 'CLK_FB0','CLK_FB1','CLK_FB2','CLK_FB3'] for i1 in range(28): # [1..28] for i2 in range(8): # [1..8] @@ -390,7 +390,7 @@ def get_timings(name): name = f"glbout_{inputs[i1]}_{outputs[i2]}" val[name] = convert_delay(d) # All feedback delays calculated are same, we just take one - val["glbout_FEEDBACK_delay"] = val["glbout_CLK0_0_CLK_FB0"] - val["glbout_CLK0_0_CLOCK0"] + val["glbout_FEEDBACK_delay"] = val["glbout_CLK0_0_CLK_FB0"] - val["glbout_CLK0_0_GLB0"] inputs = ['clk_ref_i','clock_core0_i','adpll_enable_i','adpll_status_read_i','locked_steady_reset_i','autn_en_i','reset_n_i'] outputs = ['clk_core0_o','clk_core90_o','clk_core180_o','clk_core270_o', 'pll_locked_o', 'pll_locked_steady_o'] From 10b52f37f1088d0cd5b5a6a17c4f5c0e8cb75845 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Wed, 13 Aug 2025 15:49:44 +0200 Subject: [PATCH 3/4] Added IOSEL --- gatemate/chip.py | 2 +- gatemate/die.py | 46 ++++++++++++++++++++++++++++++---------------- 2 files changed, 31 insertions(+), 17 deletions(-) diff --git a/gatemate/chip.py b/gatemate/chip.py index de31e53..312f5bf 100644 --- a/gatemate/chip.py +++ b/gatemate/chip.py @@ -172,7 +172,7 @@ class Chip: if bank.bank == "W2" and p == "A" and num in [5,6,7,8]: flags = 8-num+1 # will be 1-4 for different clock sources if pad_name not in not_exist: - pads.append(Pad(loc.x + d.offset_x,loc.y + d.offset_y,pad_name,"GPIO","",self.get_bank_number(bank.bank),flags,ddr)) + pads.append(Pad(loc.x + d.offset_x,loc.y + d.offset_y,pad_name,"IOSEL","",self.get_bank_number(bank.bank),flags,ddr)) return pads CCGM1_DEVICES = { diff --git a/gatemate/die.py b/gatemate/die.py index 58e3d42..7ab0629 100644 --- a/gatemate/die.py +++ b/gatemate/die.py @@ -357,8 +357,11 @@ PRIMITIVES_PINS = { Pin("COUTY2" ,PinType.OUTPUT, "CPE_WIRE", True), Pin("POUTY2" ,PinType.OUTPUT, "CPE_WIRE", True), ], + "IOSEL" : [ + Pin("GPIO_OUT", PinType.OUTPUT,"GPIO_WIRE"), + Pin("GPIO_EN" , PinType.OUTPUT,"GPIO_WIRE"), + Pin("GPIO_IN" , PinType.INPUT, "GPIO_WIRE"), - "GPIO" : [ Pin("IN1" , PinType.OUTPUT,"GPIO_WIRE"), Pin("IN2" , PinType.OUTPUT,"GPIO_WIRE"), Pin("OUT1" , PinType.INPUT, "GPIO_WIRE"), @@ -372,6 +375,12 @@ PRIMITIVES_PINS = { Pin("CLOCK2", PinType.INPUT, "GPIO_WIRE"), Pin("CLOCK3", PinType.INPUT, "GPIO_WIRE"), Pin("CLOCK4", PinType.INPUT, "GPIO_WIRE"), + ], + "GPIO" : [ + Pin("Y", PinType.INPUT, "GPIO_WIRE"), + Pin("T", PinType.INPUT, "GPIO_WIRE"), + Pin("A", PinType.OUTPUT,"GPIO_WIRE"), + # PAD wires Pin("I", PinType.INPUT, "GPIO_WIRE"), Pin("O", PinType.OUTPUT,"GPIO_WIRE"), @@ -1427,6 +1436,7 @@ def get_primitives_for_type(type): primitives.append(Primitive("SERDES","SERDES",10)) if "GPIO" in type: primitives.append(Primitive("GPIO","GPIO",0)) + primitives.append(Primitive("IOSEL","IOSEL",1)) if "PLL" in type: primitives.append(Primitive("CLKIN","CLKIN",0)) primitives.append(Primitive("GLBOUT","GLBOUT",1)) @@ -2358,7 +2368,7 @@ def get_pins_constraint(type_name, prim_name, prim_type): val.append(PinConstr("TX_POWER_DOWN_N_I", 25, 4, RAM_OUTPUT, 1)) val.append(PinConstr("RX_POWER_DOWN_N_I", 25, 2, RAM_OUTPUT, 1)) val.append(PinConstr("TX_ELEC_IDLE_I", 25, 0, RAM_OUTPUT, 1)) - elif prim_type=="GPIO": + elif prim_type=="IOSEL": if "LES" in type_name: val.append(PinConstr("OUT4", 3, 1, RAM_OUTPUT, 2)) val.append(PinConstr("OUT3", 3, 1, RAM_OUTPUT, 1)) @@ -2845,8 +2855,12 @@ def get_mux_connections_for_type(type): create_mux(f"SB_SML.P{plane}.Y4_int", f"SB_SML.P{plane}.Y4", 1, 1, True, f"SB_SML.P{plane}.Y4_INT", False, delay="del_dummy") create_mux(f"SB_SML.P{plane}.YDIAG_int", f"SB_SML.P{plane}.YDIAG", 1, 1, True, f"SB_SML.P{plane}.YDIAG_INT", False, delay="del_dummy") - #if "GPIO" in type: - # # GPIO + if "GPIO" in type: + # GPIO + create_mux("IOSEL.GPIO_OUT", "GPIO.A", 1, 0, False, visible=False, delay="del_dummy") + create_mux("IOSEL.GPIO_EN", "GPIO.T", 1, 0, False, visible=False, delay="del_dummy") + create_mux("GPIO.Y", "IOSEL.GPIO_IN", 1, 0, False, visible=False, delay="del_dummy") + if "IOES" in type: # IOES for p in range(1,13): @@ -3300,15 +3314,15 @@ class Die: plane = f"{p:02d}" self.create_conn(sb_x,sb_y,f"{get_sb_type(sb_x,sb_y)}.P{plane}.{output}", x,y, f"IOES.ALTIN_{plane}") self.create_conn(x,y, f"IOES.SB_IN_{plane}", sb_x,sb_y,f"{get_sb_type(sb_x,sb_y)}.P{plane}.D0") - self.create_conn(gpio_x,gpio_y,"GPIO.IN1", x,y, "IOES.IO_IN1") - self.create_conn(gpio_x,gpio_y,"GPIO.IN2", x,y, "IOES.IO_IN2") + self.create_conn(gpio_x,gpio_y,"IOSEL.IN1", x,y, "IOES.IO_IN1") + self.create_conn(gpio_x,gpio_y,"IOSEL.IN2", x,y, "IOES.IO_IN2") if not alt: - self.create_ram_io_conn("GPIO", "GPIO", x, y) - self.create_conn(PLL_X_POS, PLL_Y_POS, "GLBOUT.GLB0", gpio_x, gpio_y, "GPIO.CLOCK1", "del_GLBOUT_IO_SEL") - self.create_conn(PLL_X_POS, PLL_Y_POS, "GLBOUT.GLB1", gpio_x, gpio_y, "GPIO.CLOCK2", "del_GLBOUT_IO_SEL") - self.create_conn(PLL_X_POS, PLL_Y_POS, "GLBOUT.GLB2", gpio_x, gpio_y, "GPIO.CLOCK3", "del_GLBOUT_IO_SEL") - self.create_conn(PLL_X_POS, PLL_Y_POS, "GLBOUT.GLB3", gpio_x, gpio_y, "GPIO.CLOCK4", "del_GLBOUT_IO_SEL") + self.create_ram_io_conn("IOSEL", "IOSEL", x, y) + self.create_conn(PLL_X_POS, PLL_Y_POS, "GLBOUT.GLB0", gpio_x, gpio_y, "IOSEL.CLOCK1", "del_GLBOUT_IO_SEL") + self.create_conn(PLL_X_POS, PLL_Y_POS, "GLBOUT.GLB1", gpio_x, gpio_y, "IOSEL.CLOCK2", "del_GLBOUT_IO_SEL") + self.create_conn(PLL_X_POS, PLL_Y_POS, "GLBOUT.GLB2", gpio_x, gpio_y, "IOSEL.CLOCK3", "del_GLBOUT_IO_SEL") + self.create_conn(PLL_X_POS, PLL_Y_POS, "GLBOUT.GLB3", gpio_x, gpio_y, "IOSEL.CLOCK4", "del_GLBOUT_IO_SEL") def create_pll(self): # GPIO_W2_A[8] CLK0 @@ -3319,13 +3333,13 @@ class Die: # GPIO_S3_B[8] SPI_CLK # GPIO_S3_A[5] JTAG_CLK loc = self.gpio_to_loc["GPIO_W2_A[8]"] - self.create_conn(loc.x, loc.y, "GPIO.IN1", PLL_X_POS, PLL_Y_POS, "CLKIN.CLK0") + self.create_conn(loc.x, loc.y, "IOSEL.IN1", PLL_X_POS, PLL_Y_POS, "CLKIN.CLK0") loc = self.gpio_to_loc["GPIO_W2_A[7]"] - self.create_conn(loc.x, loc.y, "GPIO.IN1", PLL_X_POS, PLL_Y_POS, "CLKIN.CLK1") + self.create_conn(loc.x, loc.y, "IOSEL.IN1", PLL_X_POS, PLL_Y_POS, "CLKIN.CLK1") loc = self.gpio_to_loc["GPIO_W2_A[6]"] - self.create_conn(loc.x, loc.y, "GPIO.IN1", PLL_X_POS, PLL_Y_POS, "CLKIN.CLK2") + self.create_conn(loc.x, loc.y, "IOSEL.IN1", PLL_X_POS, PLL_Y_POS, "CLKIN.CLK2") loc = self.gpio_to_loc["GPIO_W2_A[5]"] - self.create_conn(loc.x, loc.y, "GPIO.IN1", PLL_X_POS, PLL_Y_POS, "CLKIN.CLK3") + self.create_conn(loc.x, loc.y, "IOSEL.IN1", PLL_X_POS, PLL_Y_POS, "CLKIN.CLK3") self.create_ram_io_conn("GLBOUT", "GLBOUT", PLL_X_POS, PLL_Y_POS) @@ -3463,7 +3477,7 @@ class Die: for port in ['A','B']: for num in range(0,9): loc = self.io_pad_names[bank][port][num] - self.create_conn(x, y , f"CPE.RAM_O{out}", loc.x, loc.y, "GPIO.DDR") + self.create_conn(x, y , f"CPE.RAM_O{out}", loc.x, loc.y, "IOSEL.DDR") self.ddr_i[bank] = Location(x+self.offset_x,y+self.offset_y,2-out) def misc_connections(self): From 6ad315609d7669402888d2c690f0debf07a2aabf Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Thu, 14 Aug 2025 11:53:29 +0200 Subject: [PATCH 4/4] Bump database version --- gatemate/chip.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gatemate/chip.py b/gatemate/chip.py index 312f5bf..ace046b 100644 --- a/gatemate/chip.py +++ b/gatemate/chip.py @@ -23,7 +23,7 @@ from dataclasses import dataclass from typing import List, Dict from timing import decompress_timing -DATABASE_VERSION = 1.3 +DATABASE_VERSION = 1.4 @dataclass(eq=True, order=True) class Pad: