Gwenhael Goavec-Merou bf8106ef5f cable: added xilinxPlatformCableUsb_alt variant with PID==0x000D (found in SP601)

2026-06-04 16:21:54 +02:00

..

compatibility

doc/compatibility/fpga: Expand "EF" initialism

2026-02-24 08:36:27 -06:00

figs

altera: MAX10: added --flash-sector support with arbitrary binary file

2025-06-18 18:57:26 +02:00

guide

2-5 minor typos (#673)

2026-05-30 11:40:19 +02:00

vendors

board.hpp: Add brs-100-gw1nr9

2026-05-13 16:21:38 +10:00

boards.yml

feat: add agilex 3 A3CY100 model to fpga list (#669)

2026-05-24 08:42:14 +02:00

cable.yml

cable: added xilinxPlatformCableUsb_alt variant with PID==0x000D (found in SP601)

2026-06-04 16:21:54 +02:00

conf.py

doc/cable: move to yml

2022-02-20 15:47:35 +01:00

data.py

doc/data: adding an (unused for now) SPIFlash entry

2023-09-21 07:03:41 +02:00

FPGAs.yml

doc/FPGAs: added Agilex 3/5 entries

2026-04-08 17:03:49 +02:00

index.rst

colognechip integration: update documentation

2021-12-12 18:26:14 +01:00

Makefile

doc: add Sphinx site

2021-11-28 10:20:43 +01:00

requirements.txt

doc: declare board compatibility through a YAML file

2022-01-12 03:00:55 +01:00

todo.rst

doc: convert TODO from md to rst

2021-11-28 10:24:07 +01:00