Stéphane Chevigny 2ed5eb5eec Rename 5cefa5f23 to 5ce523, add documentation for board and fpga

2022-03-13 09:14:52 -04:00

..

compatibility

doc/cable: move to yml

2022-02-20 15:47:35 +01:00

guide

ftdi MPSSE / jtag: add option to use neg edge for TDO's sampling

2022-03-11 07:45:48 +01:00

vendors

colognechip integration: update vendor documentation

2021-12-10 12:41:33 +01:00

boards.yml

Rename 5cefa5f23 to 5ce523, add documentation for board and fpga

2022-03-13 09:14:52 -04:00

cable.yml

doc/cable: fix build failure

2022-03-10 20:09:42 +01:00

conf.py

doc/cable: move to yml

2022-02-20 15:47:35 +01:00

data.py

doc/cable: move to yml

2022-02-20 15:47:35 +01:00

FPGAs.yml

Rename 5cefa5f23 to 5ce523, add documentation for board and fpga

2022-03-13 09:14:52 -04:00

index.rst

colognechip integration: update documentation

2021-12-12 18:26:14 +01:00

Makefile

doc: add Sphinx site

2021-11-28 10:20:43 +01:00

requirements.txt

doc: declare board compatibility through a YAML file

2022-01-12 03:00:55 +01:00

todo.rst

doc: convert TODO from md to rst

2021-11-28 10:24:07 +01:00