162 lines
8.7 KiB
Markdown
162 lines
8.7 KiB
Markdown
# openFPGALoader
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<p align="right">
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<a title="Documentation" href="https://trabucayre.github.io/openFPGALoader"><img src="https://img.shields.io/website.svg?label=trabucayre.github.io%2FopenFPGALoader&longCache=true&style=flat-square&url=http%3A%2F%2Ftrabucayre.github.io%2FopenFPGALoader%2Findex.html&logo=GitHub"></a><!--
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-->
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<a title="'Test' workflow Status" href="https://github.com/trabucayre/openFPGALoader/actions/workflows/Test.yml"><img alt="'Test' workflow Status" src="https://img.shields.io/github/actions/workflow/status/trabucayre/openFPGALoader/Test.yml?branch=master&longCache=true&style=flat-square&label=Test&logo=github%20actions&logoColor=fff"></a><!--
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-->
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<a title="Releases" href="https://github.com/trabucayre/openFPGALoader/releases"><img src="https://img.shields.io/github/commits-since/trabucayre/openFPGALoader/latest.svg?longCache=true&style=flat-square&logo=git&logoColor=fff"></a>
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</p>
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<p align="center">
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<strong><a href="https://trabucayre.github.io/openFPGALoader/guide/first-steps.html">First steps</a> • <a href="https://trabucayre.github.io/openFPGALoader/guide/install.html">Install</a> • <a href="https://trabucayre.github.io/openFPGALoader/guide/troubleshooting.html">Troubleshooting</a></strong> • <a href="https://trabucayre.github.io/openFPGALoader/guide/advanced.html">Advanced usage</a>
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</p>
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Universal utility for programming FPGAs. Compatible with many boards, cables and FPGA from major manufacturers (Xilinx, Altera/Intel, Lattice, Gowin, Efinix, Anlogic, Cologne Chip). openFPGALoader works on Linux, Windows and macOS.
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Not sure if your hardware is supported? Check the hardware compatibility lists:
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* [FPGA compatibility list](https://trabucayre.github.io/openFPGALoader/compatibility/fpga.html)
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* [Board compatibility list](https://trabucayre.github.io/openFPGALoader/compatibility/board.html)
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* [Cable compatibility list](https://trabucayre.github.io/openFPGALoader/compatibility/cable.html)
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Also checkout the vendor-specific documentation:
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[Anlogic](https://trabucayre.github.io/openFPGALoader/vendors/anlogic.html),
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[Cologne Chip](https://trabucayre.github.io/openFPGALoader/vendors/colognechip.html),
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[Efinix](https://trabucayre.github.io/openFPGALoader/vendors/efinix.html),
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[Gowin](https://trabucayre.github.io/openFPGALoader/vendors/gowin.html),
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[Intel/Altera](https://trabucayre.github.io/openFPGALoader/vendors/intel.html),
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[Lattice](https://trabucayre.github.io/openFPGALoader/vendors/lattice.html),
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[Xilinx](https://trabucayre.github.io/openFPGALoader/vendors/xilinx.html).
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OpenFPGALoader has a dedicated channel: [#openFPGALoader at libera.chat](https://web.libera.chat/#openFPGALoader).
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## Quick Usage
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`arty` in the example below is one of the many FPGA board configurations listed [here](https://trabucayre.github.io/openFPGALoader/compatibility/board.html).
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```bash
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openFPGALoader -b arty arty_bitstream.bit # Loading in SRAM
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openFPGALoader -b arty -f arty_bitstream.bit # Writing in flash
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```
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You can also specify a JTAG cable model (complete list [here](https://trabucayre.github.io/openFPGALoader/compatibility/cable.html)) instead of the board model:
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```bash
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openFPGALoader -c cmsisdap fpga_bitstream.bit
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```
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## Usage
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```
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Usage: ./openFPGALoader [OPTION...] BIT_FILE
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openFPGALoader -- a program to flash FPGA
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--altsetting arg DFU interface altsetting (only for DFU mode)
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--bitstream arg bitstream
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--secondary-bitstream arg
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secondary bitstream (some Xilinx UltraScale
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boards)
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-b, --board arg board name, may be used instead of cable
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-B, --bridge arg disable spiOverJtag model detection by
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providing bitstream(intel/xilinx)
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-c, --cable arg jtag interface
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--status-pin arg JTAG mode / FTDI: GPIO pin number to use as a
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status indicator (active low)
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--invert-read-edge JTAG mode / FTDI: read on negative edge
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instead of positive
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--vid arg probe Vendor ID
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--pid arg probe Product ID
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--cable-index arg probe index (FTDI and cmsisDAP)
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--busdev-num arg select a probe by it bus and device number
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(bus_num:device_addr)
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--ftdi-serial arg FTDI chip serial number
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--ftdi-channel arg FTDI chip channel number (channels 0-3 map to
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A-D)
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-d, --device arg device to use (/dev/ttyUSBx)
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--detect detect FPGA, add -f to show connected flash
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--dfu DFU mode
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--dump-flash Dump flash mode
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--bulk-erase Bulk erase flash
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--enable-quad Enable quad mode for SPI Flash
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--disable-quad Disable quad mode for SPI Flash
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--target-flash arg for boards with multiple flash chips (some
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Xilinx UltraScale boards), select the target
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flash: primary (default), secondary or both
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--external-flash select ext flash for device with internal and
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external storage
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--file-size arg provides size in Byte to dump, must be used
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with dump-flash
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--file-type arg provides file type instead of let's deduced
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by using extension
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--flash-sector arg flash sector (Lattice and Altera MAX10 parts
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only)
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--fpga-part arg fpga model flavor + package
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--freq arg jtag frequency (Hz)
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-f, --write-flash write bitstream in flash (default: false)
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--index-chain arg device index in JTAG-chain
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--misc-device arg add JTAG non-FPGA devices <idcode,irlen,name>
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--ip arg IP address (XVC and remote bitbang client)
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--list-boards list all supported boards
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--list-cables list all supported cables
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--list-fpga list all supported FPGA
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-m, --write-sram write bitstream in SRAM (default: true)
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-o, --offset arg Start address (in bytes) for read/write into
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non volatile memory (default: 0)
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--pins arg pin config TDI:TDO:TCK:TMS or
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MOSI:MISO:SCK:CS[:HOLDN:WPN]
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--probe-firmware arg firmware for JTAG probe (usbBlasterII)
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--protect-flash arg protect SPI flash area
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--quiet Produce quiet output (no progress bar)
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-r, --reset reset FPGA after operations
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--scan-usb scan USB to display connected probes
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--skip-load-bridge skip writing bridge to SRAM when in
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write-flash mode
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--skip-reset skip resetting the device when in write-flash
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mode
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--spi SPI mode (only for FTDI in serial mode)
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--unprotect-flash Unprotect flash blocks
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-v, --verbose Produce verbose output
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--verbose-level arg verbose level -1: quiet, 0: normal,
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1:verbose, 2:debug
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-h, --help Give this help list
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--verify Verify write operation (SPI Flash only)
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--xvc Xilinx Virtual Cable Functions
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--port arg Xilinx Virtual Cable and remote bitbang Port
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(default 3721)
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--mcufw arg Microcontroller firmware
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--conmcu Connect JTAG to MCU
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-D, --read-dna Read DNA (Xilinx FPGA only)
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-X, --read-xadc Read XADC (Xilinx FPGA only)
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--read-register arg Read Status Register(Xilinx FPGA only)
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--user-flash arg User flash file (Gowin LittleBee FPGA only)
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-V, --Version Print program version
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Mandatory or optional arguments to long options are also mandatory or optional
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for any corresponding short options.
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Report bugs to <gwenhael.goavec-merou@trabucayre.com>.
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```
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By default **spiOverJtag** are search into `${CMAKE_INSTALL_FULL_DATAROOTDIR}`
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(*/usr/local/share/* by default). It's possible to change this behaviour by
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using an environment variable:
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```bash
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export OPENFPGALOADER_SOJ_DIR=/somewhere
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openFPGALoader xxxx
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```
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or
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```
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OPENFPGALOADER_SOJ_DIR=/somewhere openFPGALoader xxxx
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```
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`OPENFPGALOADER_SOJ_DIR` must point to directory containing **spiOverJtag**
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bitstreams.
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## Sponsors/Partners
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