* fix(spiOverJtag): package-specific FGG676 bitstream build for QMTech XC7A100T
- Makefile: add xc7a100tfgg676 target
- build.py: parse device+package form (e.g. xc7a100tfgg676), stop aliasing
a package-specific bitstream to other packages via symlink
- constr_xc7a_fgg676.xdc: set BITSTREAM.STARTUP.STARTUPCLK JtagClk (camelCase;
all-caps JTAGCLK is silently rejected and falls back to Cclk, leaving EOS=0
over JTAG), correct SPI pins to LVCMOS33 per QMTech schematic
- README.md: document package-specific bitstream build
- remove stale spiOverJtag_xc7a100tfgg676.bit.gz (rebuilt by above)
* spiOverJtag: reword FGG676 SPI-flash pin comment as package-level
These pins are fixed by the XC7A*T-FGG676 package, not by the QMTech board.
Reword the comment to reflect that any XC7A35T/50T/75T/100T/200T in the FGG676
package routes the SPI-flash signals to the same balls. Keep the QMTech
schematic only as the cross-check reference. No pin values changed.
Addresses trabucayre review on constr_xc7a_fgg676.xdc.
---------
Co-authored-by: gHashTag <admin@t27.ai>
ll_write() can request more than 1.5K of data, but recv() call will
return right away as soon as one packet is received. This causes large
transfers to break as not enough data is received.
Fixed by adding rx_exact flag and enabled it for ll_write()
Tested with Zynq7010 on a slow WiFi. Before the patch all uploads were
silently failing with no error in the log.
Signed-off-by: Vadzim Dambrouski <pftbest@gmail.com>
The IS25WP256 (0x9d7019, 1.8V variant of the IS25LP256) was missing
from the database, and neither 256Mb part had its Quad Enable bit
described (status register bit 6 per the IS25LP(WP)256D datasheet),
making --enable-quad fail on these parts. Required to boot Xilinx
bitstreams generated with SPI_BUSWIDTH 4.
* OpenBSD-Patch: Added the #include <sys/socket.h> in xvc_server.cpp to allow for compilation. Added a section to the README.md.
* Moved the Note regarding OpenBSD from the README.md into the doc/guide/troubleshooting.rst.
* reverted the README.md back to its original form.
* Removed a copy&paste error in the main.cpp file. Updated the documentation on OpenBSD.
* slight change to reflect the nomenclature of modules/devices in OpenBSD.
* "Windows" is spelled with only one "o".
Do not apply the Zynq non-volatile memory restriction when only reading FPGA DNA. Allow Zynq devices to use the existing 7-series DNA read path.
Tested on xc7z010 over XVC with --read-dna.
libusb_open_device_with_vid_pid() returns the first VID:PID match, so
with two ESP32-S3 cables connected, every invocation programmed the
same board. Replace it with a libusb_get_device_list() iteration that
also honours cable.bus_addr/device_addr (already exposed as
--busdev-num) and --usb-serial-num flag that matches the device
iSerialNumber by substring (useful with MAC-derived serials).
The -d /dev/ttyACM* path could not help: that's the CDC-ACM interface
(iface 0), while JTAG is on the vendor iface 2 reached via libusb;
ttyACM numbering and libusb enumeration order are independent.
Constraint: must keep existing single-board invocations working without flag changes
Confidence: high
Scope-risk: narrow
Directive: arguments struct uses positional aggregate init at main.cpp:120; new fields must add a matching slot
Not-tested: simultaneous two-board programming on real hardware (single-board path verified to build)
Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
Nicholas Dietz
Gwenhael Goavec-Merou
Matt Thompson
Mario Reisinger
Vasilev Dmitrii
Vadzim Dambrouski
Martin C
gHashTag
Florent Kermarrec
dettus
MYJ695
Hannes Rüger
r4d10n
parker-research
Craig Haywood
aisuneko icecat
Cayetano Santos
Denis Bodor