7ceaab0126
spiOverJtag: add bitstream for ECP4CE15F23
2021-11-28 16:51:42 +01:00
c6b02b4358
spiOverJtag: add 5CEBA4F23C8, fix sdc file and compress rbf file
2021-11-28 10:00:21 +01:00
0d57b58c26
spiOverJtag: use build.py for all devices, add xc6slx45
2021-07-11 08:57:46 +02:00
a4ccdae7df
add basys3 support
2021-04-20 21:28:14 +02:00
7039465353
rework xilinx fpga spiOverJtag to respect model/package
2021-04-19 21:17:08 +02:00
922d3b0b56
xilinx: add xca50t support
2020-12-08 07:32:30 +01:00
edad461d88
add support for artix-7 200t and nexys video board
2020-10-15 16:07:55 +02:00
20d72de3c4
spiOverJtag: add xc7a100 bitstream
2020-09-22 15:02:42 +02:00
ced3363ee5
Support Arty S7-50
...
Added Xilinx xc7s50 device to part.hpp; added support for generating
spiOverJtag bitstream file for that device and added bitstream to repo.
Converted xdc file from DOC line endings to native line endings.
2020-08-08 11:42:38 +02:00
5acae16a82
add design and bitstream to access SPI through JTAG
2019-10-05 19:03:28 +02:00
Gwenhael Goavec-Merou
Giuseppe Gebbia
Staf Verhaegen