Gwenhael Goavec-Merou
590553e432
src/fsparser: rewrite to use header instead of comments, add support for compressed bitstream
2021-02-12 07:34:14 +01:00
Gwenhael Goavec-Merou
210bdac09a
configBitstreamParser: external access to header keys/values
2021-02-10 08:02:20 +01:00
Gwenhael Goavec-Merou
e91c251eb0
svf_jtag: suppress CR when file is in DOS format
2021-02-08 06:31:56 +01:00
Gwenhael Goavec-Merou
d4692d5049
rawParser: typo
2021-02-06 11:42:50 +01:00
Gwenhael Goavec-Merou
1545b99748
rawParser: use raw_data buffer
2021-02-06 11:36:34 +01:00
Gwenhael Goavec-Merou
f6c036f1c0
anlogicBitParser: use _raw_data and work with this one instead of file descriptor
2021-02-06 11:29:32 +01:00
Gwenhael Goavec-Merou
5c49b1465a
all cable: always display real used frequency
2021-02-05 06:28:19 +01:00
Gwenhael Goavec-Merou
582261c758
xilinx: allow bin file to memory
2021-02-04 07:29:35 +01:00
Gwenhael Goavec-Merou
ad21a3bb36
recast verbose to int8_t to have more level of verbosity (-1 quiet, 0 normal, 1 verbose), add --quiet option, display progress bar when verbosity level >= 0
2021-01-30 07:57:49 +01:00
Gwenhael Goavec-Merou
1992360667
main: catch exception if FPGA can't be claimed.
2021-01-29 06:19:42 +01:00
Gwenhael Goavec-Merou
956d506bf7
fsparser: display warning message for missing or unknown idcode
2021-01-28 07:23:38 +01:00
Gwenhael Goavec-Merou
71c4b32202
display: add warning message
2021-01-28 07:22:24 +01:00
Gwenhael Goavec-Merou
dbc78f8c57
add seeedstudio runber (gowin GW1N-4)
2021-01-28 06:19:43 +01:00
Gwenhael Goavec-Merou
502546fcfc
fsparser: add missing GW1N-4(ES) idcode
2021-01-28 06:07:51 +01:00
Gwenhael Goavec-Merou
60800ee1a6
board: add entry for tec0117
2021-01-25 18:52:54 +01:00
Gwenhael Goavec-Merou
883268be25
efinixHexParser: use _raw_data instead of custom buffer
2021-01-24 18:21:47 +01:00
Gwenhael Goavec-Merou
46beaea14d
configBitstreamParser: introduce a buffer for unprocessed file content
2021-01-24 18:16:09 +01:00
Gwenhael Goavec-Merou
cd625d4c99
add efinix Xyloni support (spi mode only)
2021-01-21 07:11:10 +01:00
Gwenhael Goavec-Merou
0e5e609b34
ftdipp_mpsse: don't configures high bytes for devices with only one bank per channel
2021-01-21 06:57:35 +01:00
phdussud
717870e18b
Made last_time a private member of the ProgressBar class per code review comment.
2020-12-28 09:33:35 -08:00
phdussud
11baca9337
limit the progressBar update rate to 5 per second. This speeds up loading of small bin files.
2020-12-26 09:50:48 -08:00
Gwenhael Goavec-Merou
6fefebd02c
prepare release v0.2.1
2020-12-17 13:58:30 +01:00
Gwenhael Goavec-Merou
1b065277f9
add acorn CLE 215+ support
2020-12-17 09:28:45 +01:00
Gwenhael Goavec-Merou
6e44797677
add fairwaves xtrx pro board
2020-12-15 09:47:10 +01:00
Gwenhael Goavec-Merou
54b31651f3
xilinx: since xilinx generates bin file, drop limitation about flash start offset
2020-12-15 09:46:47 +01:00
phdussud
a11ec92a25
Fix gcc 10.2 error messages.
2020-12-12 15:48:45 -08:00
Gwenhael Goavec-Merou
922d3b0b56
xilinx: add xca50t support
2020-12-08 07:32:30 +01:00
Gwenhael Goavec-Merou
ed7e9340ba
lattice: add a memset to avoid valgrind warn
2020-11-27 08:29:09 +01:00
Gwenhael Goavec-Merou
88522b0e91
ftdiJtagBitbang: quick fix to avoid overflow in writeTDI
2020-11-26 09:26:08 +01:00
Gwenhael Goavec-Merou
bec5e4f35c
add xc7s25 support
2020-11-18 08:15:15 +01:00
Gwenhael Goavec-Merou
14c5b8e681
add support for ice40 FPGA and iCEBreaker, icestick, iCE40-HX8K, iCE40-HX1K-EVN boards
2020-10-31 15:02:54 +01:00
Gwenhael Goavec-Merou
818dbd301c
ftdipp_mpsse: reduce useless write
2020-10-31 11:10:14 +01:00
Gwenhael Goavec-Merou
7e15b5cabb
board: Fireant support
2020-10-31 10:44:44 +01:00
Gwenhael Goavec-Merou
6aa2176be1
board: typo
2020-10-31 10:44:14 +01:00
Gwenhael Goavec-Merou
537f02fa89
board: fix control pins size
2020-10-31 10:43:45 +01:00
Gwenhael Goavec-Merou
14b7122b4d
ftdispi: fix control size
2020-10-31 10:42:40 +01:00
Gwenhael Goavec-Merou
aa23aff388
main: review SPI mode for efinix active mode
2020-10-31 10:41:44 +01:00
Gwenhael Goavec-Merou
70fb5c8439
add efinix support
2020-10-31 10:39:06 +01:00
Gwenhael Goavec-Merou
3c9870bba3
introduce CBUS/DBUS pins value, add macro and pin mapping for board in SPI mode, reset and done signals
2020-10-31 08:40:18 +01:00
Gwenhael Goavec-Merou
fe8cd9998d
board: simplify board definition using preprocessor macro
2020-10-31 08:04:43 +01:00
Gwenhael Goavec-Merou
1bc20fee85
ftdispi: cleanup + fix + add support for wpn and holdn pins
2020-10-31 07:45:30 +01:00
Gwenhael Goavec-Merou
deefcd2d38
ftdipp_mpsse: update direction method
2020-10-31 07:38:06 +01:00
Gwenhael Goavec-Merou
b2abafa76d
ftdispi: start to use spi_pins_conf
2020-10-30 08:26:15 +01:00
Gwenhael Goavec-Merou
e347d2afd6
board: add spi_pins_conf structure
2020-10-30 08:23:49 +01:00
Gwenhael Goavec-Merou
b0f73aa8d9
ftdipp_mpsse: add method to configure individually pins direction
2020-10-30 08:18:38 +01:00
Gwenhael Goavec-Merou
2398ee1445
part: add LCMXO2-640HC
2020-10-29 08:24:30 +01:00
Gwenhael Goavec-Merou
88c6b2ff6d
Improve FTDI communication in bitbang mode
...
sub layer cut package in allowed size, so it's not mandatory to do this
at openFPGALoader level. The only situation when the size is important
is in read mode. So increase buffer size to reduce system calls.
2020-10-29 08:15:32 +01:00
Gwenhael Goavec-Merou
e0a5d376ba
ftdipp_mpsse: change VID/PID visibility
2020-10-29 07:40:56 +01:00
Gwenhael Goavec-Merou
f75a7f8395
ftdiJtagBitbang: some cleanup and reuse parent class buffer
2020-10-29 07:39:47 +01:00
Gwenhael Goavec-Merou
78ea8ac808
ftdipp_mpsse: change _buffer visibility
2020-10-29 07:39:07 +01:00