From 2754e99215bdc073a7c671f33bd0ac4b1cee395b Mon Sep 17 00:00:00 2001 From: Giovanni Bruni Date: Wed, 11 Oct 2023 10:04:29 +0200 Subject: [PATCH 1/6] cable: add FTDI FT4232HP mapping --- src/cable.hpp | 2 ++ src/libusb_ll.cpp | 2 ++ 2 files changed, 4 insertions(+) diff --git a/src/cable.hpp b/src/cable.hpp index 3814a08..a8019b0 100644 --- a/src/cable.hpp +++ b/src/cable.hpp @@ -108,6 +108,8 @@ static std::map cable_list = { {"ft232", FTDI_SER(0x0403, 0x6014, FTDI_INTF_A, 0x08, 0x0B, 0x08, 0x0B)}, {"ft232RL", FTDI_BB( 0x0403, 0x6001, FTDI_INTF_A, 0x08, 0x0B, 0x08, 0x0B)}, {"ft4232", FTDI_SER(0x0403, 0x6011, FTDI_INTF_A, 0x08, 0x0B, 0x08, 0x0B)}, + {"ft4232hp", FTDI_SER(0x0403, 0x6043, FTDI_INTF_A, 0x08, 0x0B, 0x00, 0x00)}, + {"ft4232hp_b", FTDI_SER(0x0403, 0x6043, FTDI_INTF_B, 0x08, 0x0B, 0x00, 0x00)}, {"ecpix5-debug", FTDI_SER(0x0403, 0x6010, FTDI_INTF_A, 0xF8, 0xFB, 0xFF, 0xFF)}, {"jlink", CABLE_DEF(MODE_JLINK, 0x1366, 0x0105 )}, {"jlink_base", CABLE_DEF(MODE_JLINK, 0x1366, 0x0101 )}, diff --git a/src/libusb_ll.cpp b/src/libusb_ll.cpp index f56efff..ce56639 100644 --- a/src/libusb_ll.cpp +++ b/src/libusb_ll.cpp @@ -74,6 +74,8 @@ bool libusb_ll::scan() snprintf(probe_type, 256, "ft232H"); else if (desc.idProduct == 0x6015) snprintf(probe_type, 256, "ft231X"); + else if (desc.idProduct == 0x6043) + snprintf(probe_type, 256, "FT4232HP"); else snprintf(probe_type, 256, "unknown FTDI"); found = true; From dce0c050a7bf7f78c5d75a0267b533787fc2aa0d Mon Sep 17 00:00:00 2001 From: Giovanni Bruni Date: Mon, 16 Oct 2023 08:01:03 +0200 Subject: [PATCH 2/6] board: add gr740-mini --- doc/boards.yml | 7 +++++++ src/board.hpp | 1 + 2 files changed, 8 insertions(+) diff --git a/doc/boards.yml b/doc/boards.yml index 3cc76fa..33c15b1 100644 --- a/doc/boards.yml +++ b/doc/boards.yml @@ -324,6 +324,13 @@ Flash: OK Constraints: Fomu-PVT +- ID: gr740-mini + Description: GR740-MINI + URL: https://gaisler.com/index.php/products/boards/gr740-mini + FPGA: CertusPro-NX LFCPNX-100 + Memory: OK + Flash: NA + - ID: honeycomb Description: honeycomb URL: https://github.com/Disasm/honeycomb-pcb diff --git a/src/board.hpp b/src/board.hpp index 33de882..5278b57 100644 --- a/src/board.hpp +++ b/src/board.hpp @@ -155,6 +155,7 @@ static std::map board_list = { SPI_BOARD("gatemate_evb_spi", "colognechip", "gatemate_evb_spi", DBUS4, DBUS5, CBUS0, DBUS3, DBUS0, DBUS1, DBUS2, 0, 0, CABLE_DEFAULT), JTAG_BOARD("genesys2", "xc7k325tffg900", "digilent_b", 0, 0, CABLE_DEFAULT), + JTAG_BOARD("gr740-mini", "", "ft4232hp_b", 0, 0, CABLE_DEFAULT), JTAG_BOARD("hseda-xc6slx16", "xc6slx16ftg256", "", 0, 0, CABLE_DEFAULT), /* most ice40 boards uses the same pinout */ SPI_BOARD("ice40_generic", "lattice", "ft2232", From 5f6074a7fc57e9c2c379da5bc5f928b6e6895ed7 Mon Sep 17 00:00:00 2001 From: Giovanni Bruni Date: Wed, 18 Oct 2023 16:01:23 +0200 Subject: [PATCH 3/6] lattice: fix bscan width and other minor things for NEXUS family --- src/lattice.cpp | 31 +++++++++++++++++++++++-------- 1 file changed, 23 insertions(+), 8 deletions(-) diff --git a/src/lattice.cpp b/src/lattice.cpp index 8b23a1a..0a21255 100644 --- a/src/lattice.cpp +++ b/src/lattice.cpp @@ -103,7 +103,7 @@ using namespace std; # define REG_STATUS_AUTH_DONE (1 << 18) /* Authentication done */ # define REG_STATUS_PRI_BOOT_FAIL (1 << 21) /* Primary boot failure (1= Fail) even though secondary boot successful */ # define REG_STATUS_CNF_CHK_MASK (0x0f << 23) /* Configuration Status Check */ -#define REG_STATUS_PRV_CNF_CHK_MASK (0x0fUL << 33) /* NEXUS_FAMILY: Configuration Status Check of previous bitstrem */ +#define REG_STATUS_PRV_CNF_CHK_MASK (0x0fUL << 34) /* NEXUS_FAMILY: Configuration Status Check of previous bitstrem */ # define REG_STATUS_MACHXO3D_CNF_CHK_MASK (0x0f << 22) /* Configuration Status Check */ # define REG_STATUS_EXEC_ERR (1 << 26) /*** NOT specified for MachXO3D ***/ # define REG_STATUS_DEV_VERIFIED (1 << 27) /* I=0 Device verified correct, I=1 Device failed to verify */ @@ -301,11 +301,20 @@ bool Lattice::program_mem() displayReadReg(readStatusReg()); } - /* The command code 0x1C is not listed in the manual? */ - /* preload 0x1C */ - uint8_t tx_buf[26]; - memset(tx_buf, 0xff, 26); - wr_rd(0x1C, tx_buf, 26, NULL, 0); + /* The command code 0x1C is not listed in the manual? + * PRELOAD/SAMPLE 0x1C + * For NEXUS family fpgas, the Bscan register is 362 bits long or + * 45.25 bytes => 46 bytes + */ + uint8_t tx_buf[46]; + memset(tx_buf, 0xff, 46); + int tx_len; + if(_fpga_family == NEXUS_FAMILY){ + tx_len = 46; + } else { + tx_len = 26; + } + wr_rd(0x1C, tx_buf, tx_len, NULL, 0); /* LSC_REFRESH 0x79 -- "Equivalent to toggle PROGRAMN pin" * We REFRESH only if the fpga is in a status of error due to @@ -375,9 +384,15 @@ bool Lattice::program_mem() printSuccess("DONE"); } - /* ISC ERASE */ + /* ISC ERASE + * For Nexus family (from svf file): 1 byte to tx 0x00 + */ printInfo("SRAM erase: ", false); - if (flashErase(FLASH_ERASE_SRAM) == false) { + uint32_t mask_erase[1] = {FLASH_ERASE_SRAM}; + if (_fpga_family == NEXUS_FAMILY){ + mask_erase[0] = 0x00; + } + if (flashErase(mask_erase[0]) == false) { printError("FAIL"); displayReadReg(readStatusReg()); return false; From 940da5fb2b88e0a891e0f1beb3339da6d3bfa075 Mon Sep 17 00:00:00 2001 From: Giovanni Bruni Date: Wed, 18 Oct 2023 16:02:45 +0200 Subject: [PATCH 4/6] spi flash: add mapping for Macronix MX25L51245G (CertusPro Versa board and gr740-mini) --- src/spiFlashdb.hpp | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/src/spiFlashdb.hpp b/src/spiFlashdb.hpp index f82490d..0b67727 100644 --- a/src/spiFlashdb.hpp +++ b/src/spiFlashdb.hpp @@ -283,6 +283,20 @@ static std::map flash_list = { .bp_len = 5, .bp_offset = {(1 << 2), (1 << 3), (1 << 4), (1 << 5)}} }, + {0xc2201a, { + /* https://www.macronix.com/Lists/Datasheet/Attachments/8745/MX25L51245G,%203V,%20512Mb,%20v1.7.pdf */ + .manufacturer = "Macronix", + .model = "MX25L51245G", + .nr_sector = 1024, + .sector_erase = true, + .subsector_erase = true, + .has_extended = false, + .tb_otp = true, + .tb_offset = (1 << 3), + .tb_register = CONFR, + .bp_len = 5, + .bp_offset = {(1 << 2), (1 << 3), (1 << 4), (1 << 5)}} + }, {0xef4014, { /* https://cdn-shop.adafruit.com/datasheets/W25Q80BV.pdf */ .manufacturer = "Winbond", From bab386911adaa649764b6e4acc14d9a4e0ec4cba Mon Sep 17 00:00:00 2001 From: Giovanni Bruni Date: Fri, 20 Oct 2023 07:52:49 +0200 Subject: [PATCH 5/6] spi flash: add mapping for Micron MT25/N25Q128_1_8V (Lattice Certus Versa and CertusPro eval boards) and distinguish between N25Q128 1.8V and 3V memories --- src/spiFlashdb.hpp | 21 +++++++++++++++++++-- 1 file changed, 19 insertions(+), 2 deletions(-) diff --git a/src/spiFlashdb.hpp b/src/spiFlashdb.hpp index 0b67727..6404302 100644 --- a/src/spiFlashdb.hpp +++ b/src/spiFlashdb.hpp @@ -139,9 +139,26 @@ static std::map flash_list = { .bp_len = 4, .bp_offset = {(1 << 2), (1 << 3), (1 << 4), (1 << 6)}} }, - {0x0020ba18, { + {0x0020bb18, { + /* https://www.micron.com/-/media/client/global/documents/products/data-sheet/nor-flash/serial-nor/n25q/n25q_128mb_1_8v_65nm.pdf */ + /* MT25QU128ABA has the same JEDEC-standard signature: https://media-www.micron.com/-/media/client/global/documents/products/data-sheet/nor-flash/serial-nor/mt25q/die-rev-a/mt25q_qlhs_u_128_aba_0.pdf */ + /* Differences: https://media-www.micron.com/-/media/client/global/documents/products/technical-note/nor-flash/tn2501_migrating_n25q_to_mt25ql.pdf */ .manufacturer = "micron", - .model = "N25Q128", + .model = "MT25/N25Q128_1_8V", + .nr_sector = 256, + .sector_erase = true, + .subsector_erase = true, + .has_extended = true, + .tb_otp = false, + .tb_offset = (1 << 5), + .tb_register = STATR, + .bp_len = 4, + .bp_offset = {(1 << 2), (1 << 3), (1 << 4), (1 << 6)}} + }, + {0x0020ba18, { + /* https://media-www.micron.com/-/media/client/global/documents/products/data-sheet/nor-flash/serial-nor/n25q/n25q_128mb_3v_65nm.pdf */ + .manufacturer = "micron", + .model = "N25Q128_3V", .nr_sector = 256, .sector_erase = true, .subsector_erase = true, From 590611a8d5383a30747555d447444b98f3cc76a6 Mon Sep 17 00:00:00 2001 From: Giovanni Bruni Date: Fri, 20 Oct 2023 08:44:20 +0200 Subject: [PATCH 6/6] lattice: fix the warning "left shift count >= width of type" shown in win32/64 builds --- src/lattice.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/lattice.cpp b/src/lattice.cpp index 0a21255..34f1ba9 100644 --- a/src/lattice.cpp +++ b/src/lattice.cpp @@ -103,7 +103,7 @@ using namespace std; # define REG_STATUS_AUTH_DONE (1 << 18) /* Authentication done */ # define REG_STATUS_PRI_BOOT_FAIL (1 << 21) /* Primary boot failure (1= Fail) even though secondary boot successful */ # define REG_STATUS_CNF_CHK_MASK (0x0f << 23) /* Configuration Status Check */ -#define REG_STATUS_PRV_CNF_CHK_MASK (0x0fUL << 34) /* NEXUS_FAMILY: Configuration Status Check of previous bitstrem */ +#define REG_STATUS_PRV_CNF_CHK_MASK (UINT64_C(0x0f) << 34) /* NEXUS_FAMILY: Configuration Status Check of previous bitstrem */ # define REG_STATUS_MACHXO3D_CNF_CHK_MASK (0x0f << 22) /* Configuration Status Check */ # define REG_STATUS_EXEC_ERR (1 << 26) /*** NOT specified for MachXO3D ***/ # define REG_STATUS_DEV_VERIFIED (1 << 27) /* I=0 Device verified correct, I=1 Device failed to verify */