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openFPGALoader
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Merge pull request #532 from fjullien/xc7s_fgga676 

Add support for Xilinx xc7s75fgga676
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Gwenhael Goavec-Merou 2025-03-25 21:25:30 +01:00 committed by GitHub
parent f5ed5c4400 1698d6751e
commit f7b7e77a47
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4 changed files with 12 additions and 0 deletions
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1
spiOverJtag/build.py
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@ -117,6 +117,7 @@ if tool in ["ise", "vivado"]:
"xc7s25csga225" : "xc7s_csga225",
"xc7s25csga324" : "xc7s_csga324",
"xc7s50csga324" : "xc7s_csga324",
"xc7s75fgga676" : "xc7s_fgga676",
"xcku040-ffva1156" : "xcku040_ffva1156",
"xcku060-ffva1156" : "xcku060_ffva1156",
"xcvu9p-flga2104" : "xcvu9p_flga2104",

10
spiOverJtag/constr_xc7s_fgga676.xdc Normal file
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@ -0,0 +1,10 @@
set_property CFGBVS VCCO [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH {4} [current_design]
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property -dict {PACKAGE_PIN R20 IOSTANDARD LVCMOS33} [get_ports {csn}];
set_property -dict {PACKAGE_PIN N23 IOSTANDARD LVCMOS33} [get_ports {sdi_dq0}];
set_property -dict {PACKAGE_PIN N24 IOSTANDARD LVCMOS33} [get_ports {sdo_dq1}];
set_property -dict {PACKAGE_PIN P23 IOSTANDARD LVCMOS33} [get_ports {wpn_dq2}];
set_property -dict {PACKAGE_PIN R23 IOSTANDARD LVCMOS33} [get_ports {hldn_dq3}];

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spiOverJtag/spiOverJtag_xc7s75fgga676.bit.gz Normal file
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1
src/part.hpp
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@ -70,6 +70,7 @@ static std::map <uint32_t, fpga_model> fpga_list = {
{0x03620093, {"xilinx", "spartan7", "xc7s15ftgb196-1", 6}},
{0x037c4093, {"xilinx", "spartan7", "xc7s25", 6}},
{0x0362f093, {"xilinx", "spartan7", "xc7s50", 6}},
{0x037c8093, {"xilinx", "spartan7", "xc7s75", 6}},
/* Xilinx Virtex6 */
{0x8424a093, {"xilinx", "virtex6", "xc6vlx130t", 10}},