diff --git a/spiOverJtag/build.py b/spiOverJtag/build.py
index f8dc708..a3668b5 100755
--- a/spiOverJtag/build.py
+++ b/spiOverJtag/build.py
@@ -117,6 +117,7 @@ if tool in ["ise", "vivado"]:
         "xc7s25csga225"    : "xc7s_csga225",
         "xc7s25csga324"    : "xc7s_csga324",
         "xc7s50csga324"    : "xc7s_csga324",
+        "xc7s75fgga676"    : "xc7s_fgga676",
         "xcku040-ffva1156" : "xcku040_ffva1156",
         "xcku060-ffva1156" : "xcku060_ffva1156",
         "xcvu9p-flga2104"  : "xcvu9p_flga2104",
diff --git a/spiOverJtag/constr_xc7s_fgga676.xdc b/spiOverJtag/constr_xc7s_fgga676.xdc
new file mode 100644
index 0000000..77a796c
--- /dev/null
+++ b/spiOverJtag/constr_xc7s_fgga676.xdc
@@ -0,0 +1,10 @@
+set_property CFGBVS VCCO [current_design]
+set_property CONFIG_VOLTAGE 3.3 [current_design]
+set_property BITSTREAM.CONFIG.SPI_BUSWIDTH {4} [current_design]
+set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
+
+set_property -dict {PACKAGE_PIN R20 IOSTANDARD LVCMOS33} [get_ports {csn}];
+set_property -dict {PACKAGE_PIN N23 IOSTANDARD LVCMOS33} [get_ports {sdi_dq0}];
+set_property -dict {PACKAGE_PIN N24 IOSTANDARD LVCMOS33} [get_ports {sdo_dq1}];
+set_property -dict {PACKAGE_PIN P23 IOSTANDARD LVCMOS33} [get_ports {wpn_dq2}];
+set_property -dict {PACKAGE_PIN R23 IOSTANDARD LVCMOS33} [get_ports {hldn_dq3}];
diff --git a/spiOverJtag/spiOverJtag_xc7s75fgga676.bit.gz b/spiOverJtag/spiOverJtag_xc7s75fgga676.bit.gz
new file mode 100644
index 0000000..d7a7f60
Binary files /dev/null and b/spiOverJtag/spiOverJtag_xc7s75fgga676.bit.gz differ
diff --git a/src/part.hpp b/src/part.hpp
index 08df174..589ea8a 100644
--- a/src/part.hpp
+++ b/src/part.hpp
@@ -70,6 +70,7 @@ static std::map <uint32_t, fpga_model> fpga_list = {
 	{0x03620093, {"xilinx", "spartan7", "xc7s15ftgb196-1", 6}},
 	{0x037c4093, {"xilinx", "spartan7", "xc7s25",          6}},
 	{0x0362f093, {"xilinx", "spartan7", "xc7s50",          6}},
+	{0x037c8093, {"xilinx", "spartan7", "xc7s75",          6}},
 
 	/* Xilinx Virtex6 */
 	{0x8424a093, {"xilinx", "virtex6", "xc6vlx130t", 10}},