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xilinx: add xcau7p-sbvc484 support over JTAG

This commit is contained in:
Nicholas Dietz 2026-06-15 17:02:35 -05:00 committed by Gwenhael Goavec-Merou
parent d90fa0ca85
commit ed82b6de3b
5 changed files with 18 additions and 3 deletions
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2
spiOverJtag/Makefile
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@ -15,7 +15,7 @@ XILINX_PARTS := xc3s500evq100 \
xcku040-ffva1156 xcku060-ffva1156 \ xcku040-ffva1156 xcku060-ffva1156 \
xcku5p-ffvb676 \ xcku5p-ffvb676 \
xcvu9p-flga2104 xcvu37p-fsvh2892 \ xcvu9p-flga2104 xcvu37p-fsvh2892 \
xcau10p-ffvb676 \ xcau7p-sbvc484 xcau10p-ffvb676 \
xcau15p-ffvb676 xcau15p-ffvb676
XILINX_BIT_FILES := $(addsuffix .bit.gz,$(addprefix spiOverJtag_, $(XILINX_PARTS))) XILINX_BIT_FILES := $(addsuffix .bit.gz,$(addprefix spiOverJtag_, $(XILINX_PARTS)))

3
spiOverJtag/build.py
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@ -166,6 +166,7 @@ if tool in ["ise", "vivado"]:
"xcku3p-ffva676" : "xcku3p_ffva676", "xcku3p-ffva676" : "xcku3p_ffva676",
"xcku3p-ffvb676" : "xcku3p_ffvb676", "xcku3p-ffvb676" : "xcku3p_ffvb676",
"xcku5p-ffvb676" : "xcku5p_ffvb676", "xcku5p-ffvb676" : "xcku5p_ffvb676",
"xcau7p-sbvc484" : "xcau7p_sbvc484",
"xcau10p-ffvb676" : "xcau10p_ffvb676", "xcau10p-ffvb676" : "xcau10p_ffvb676",
"xcau15p-ffvb676" : "xcau15p_ffvb676", "xcau15p-ffvb676" : "xcau15p_ffvb676",
}.get(part, pkg_name) }.get(part, pkg_name)
@ -233,7 +234,7 @@ if tool in ["ise", "vivado"]:
"description" : "secondary flash", "description" : "secondary flash",
"default" : 1, "default" : 1,
} }
elif part == "xcau10p-ffvb676": elif part in ["xcau10p-ffvb676", "xcau7p-sbvc484"]:
tool_options = {"part": part + "-1-e"} tool_options = {"part": part + "-1-e"}
elif part == "xcau15p-ffvb676": elif part == "xcau15p-ffvb676":
tool_options = {"part": part + "-2-e"} tool_options = {"part": part + "-2-e"}

7
spiOverJtag/constr_xcau7p_sbvc484.xdc Normal file
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@ -0,0 +1,7 @@
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property CONFIG_VOLTAGE 1.8 [current_design]
# Table 1-2 from UG570
set_property CFGBVS GND [current_design]
# Primary QSPI flash
# Connection done through the STARTUPE3 block

8
spiOverJtag/xilinx_spiOverJtag.v
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@ -32,6 +32,13 @@ module spiOverJtag
wire capture, drck, sel, update, shift; wire capture, drck, sel, update, shift;
wire tdi, tdo; wire tdi, tdo;
`ifdef xilinxultrascale
/* For ultrascale these signals are internal wires (not module ports);
declare them here so they are visible to spiOverJtag_core_prim below. */
wire csn;
wire sdi_dq0, sdo_dq1, wpn_dq2, hldn_dq3;
`endif
`ifndef spartan3e `ifndef spartan3e
`ifndef virtex6 `ifndef virtex6
/* Version Interface. */ /* Version Interface. */
@ -75,7 +82,6 @@ module spiOverJtag
`else // !spartan6 && !spartan3e `else // !spartan6 && !spartan3e
`ifdef xilinxultrascale `ifdef xilinxultrascale
assign sck = drck;
wire [3:0] di; wire [3:0] di;
assign sdo_dq1 = di[1]; assign sdo_dq1 = di[1];

1
src/part.hpp
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@ -131,6 +131,7 @@ static std::map <uint32_t, fpga_model> fpga_list = {
{0x03842093, {"xilinx", "virtexus", "xcvu095", 6}}, {0x03842093, {"xilinx", "virtexus", "xcvu095", 6}},
/* Xilinx Ultrascale+ / Artix */ /* Xilinx Ultrascale+ / Artix */
{0x04AF6093, {"xilinx", "artixusp", "xcau7p", 6}},
{0x04AC4033, {"xilinx", "artixusp", "xcau10p", 6}}, {0x04AC4033, {"xilinx", "artixusp", "xcau10p", 6}},
{0x04AC4093, {"xilinx", "artixusp", "xcau10p", 6}}, {0x04AC4093, {"xilinx", "artixusp", "xcau10p", 6}},
{0x04AC2093, {"xilinx", "artixusp", "xcau15p", 6}}, {0x04AC2093, {"xilinx", "artixusp", "xcau15p", 6}},