From ed82b6de3b8e08c1dff14ebbf1065a586e64078b Mon Sep 17 00:00:00 2001
From: Nicholas Dietz <github@poleguy.com>
Date: Mon, 15 Jun 2026 17:02:35 -0500
Subject: [PATCH] xilinx: add xcau7p-sbvc484 support over JTAG

---
 spiOverJtag/Makefile                  | 2 +-
 spiOverJtag/build.py                  | 3 ++-
 spiOverJtag/constr_xcau7p_sbvc484.xdc | 7 +++++++
 spiOverJtag/xilinx_spiOverJtag.v      | 8 +++++++-
 src/part.hpp                          | 1 +
 5 files changed, 18 insertions(+), 3 deletions(-)
 create mode 100644 spiOverJtag/constr_xcau7p_sbvc484.xdc

diff --git a/spiOverJtag/Makefile b/spiOverJtag/Makefile
index 7ac1da4..1734100 100644
--- a/spiOverJtag/Makefile
+++ b/spiOverJtag/Makefile
@@ -15,7 +15,7 @@ XILINX_PARTS := xc3s500evq100 \
 	xcku040-ffva1156 xcku060-ffva1156 \
 	xcku5p-ffvb676 \
 	xcvu9p-flga2104 xcvu37p-fsvh2892 \
-	xcau10p-ffvb676 \
+	xcau7p-sbvc484 xcau10p-ffvb676 \
 	xcau15p-ffvb676
 XILINX_BIT_FILES := $(addsuffix .bit.gz,$(addprefix spiOverJtag_, $(XILINX_PARTS)))
 
diff --git a/spiOverJtag/build.py b/spiOverJtag/build.py
index a1d1163..42f9ccd 100755
--- a/spiOverJtag/build.py
+++ b/spiOverJtag/build.py
@@ -166,6 +166,7 @@ if tool in ["ise", "vivado"]:
         "xcku3p-ffva676"   : "xcku3p_ffva676",
         "xcku3p-ffvb676"   : "xcku3p_ffvb676",
         "xcku5p-ffvb676"   : "xcku5p_ffvb676",
+        "xcau7p-sbvc484"   : "xcau7p_sbvc484",
         "xcau10p-ffvb676"  : "xcau10p_ffvb676",
         "xcau15p-ffvb676"  : "xcau15p_ffvb676",
     }.get(part, pkg_name)
@@ -233,7 +234,7 @@ if tool in ["ise", "vivado"]:
                     "description" : "secondary flash",
                     "default"     : 1,
                 }
-            elif part == "xcau10p-ffvb676":
+            elif part in ["xcau10p-ffvb676", "xcau7p-sbvc484"]:
                 tool_options = {"part": part + "-1-e"}
             elif part == "xcau15p-ffvb676":
                 tool_options = {"part": part + "-2-e"}
diff --git a/spiOverJtag/constr_xcau7p_sbvc484.xdc b/spiOverJtag/constr_xcau7p_sbvc484.xdc
new file mode 100644
index 0000000..bc4bb4a
--- /dev/null
+++ b/spiOverJtag/constr_xcau7p_sbvc484.xdc
@@ -0,0 +1,7 @@
+set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
+set_property CONFIG_VOLTAGE 1.8 [current_design]
+# Table 1-2 from UG570
+set_property CFGBVS GND [current_design]
+
+# Primary QSPI flash
+# Connection done through the STARTUPE3 block
diff --git a/spiOverJtag/xilinx_spiOverJtag.v b/spiOverJtag/xilinx_spiOverJtag.v
index a3e0dd8..6d212ab 100644
--- a/spiOverJtag/xilinx_spiOverJtag.v
+++ b/spiOverJtag/xilinx_spiOverJtag.v
@@ -32,6 +32,13 @@ module spiOverJtag
 	wire capture, drck, sel, update, shift;
 	wire tdi, tdo;
 
+`ifdef xilinxultrascale
+	/* For ultrascale these signals are internal wires (not module ports);
+	   declare them here so they are visible to spiOverJtag_core_prim below. */
+	wire csn;
+	wire sdi_dq0, sdo_dq1, wpn_dq2, hldn_dq3;
+`endif
+
 `ifndef spartan3e
 `ifndef virtex6
 	/* Version Interface. */
@@ -75,7 +82,6 @@ module spiOverJtag
 `else // !spartan6 && !spartan3e
 
 `ifdef xilinxultrascale
-	assign sck = drck;
 	wire [3:0] di;
 	assign sdo_dq1 = di[1];
 
diff --git a/src/part.hpp b/src/part.hpp
index 71f4564..1a96129 100644
--- a/src/part.hpp
+++ b/src/part.hpp
@@ -131,6 +131,7 @@ static std::map <uint32_t, fpga_model> fpga_list = {
 	{0x03842093, {"xilinx", "virtexus", "xcvu095", 6}},
 
 	/* Xilinx Ultrascale+ / Artix */
+	{0x04AF6093, {"xilinx", "artixusp",  "xcau7p",  6}},
 	{0x04AC4033, {"xilinx", "artixusp",  "xcau10p", 6}},
 	{0x04AC4093, {"xilinx", "artixusp",  "xcau10p", 6}},
 	{0x04AC2093, {"xilinx", "artixusp",  "xcau15p", 6}},