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Digilent arty s7 25

This commit is contained in:
Gwenhael Goavec-Merou 2021-12-19 17:35:23 +01:00
parent 4e70bdf0c5
commit e026aa28c7
2 changed files with 5 additions and 3 deletions
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3
doc/compatibility/board.rst
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@ -17,7 +17,8 @@ Boards
acornCle215 `Acorn CLE 215+ <http://squirrelsresearch.com/acorn-cle-215/>`__ Artix xc7a200tsbg484 OK OK acornCle215 `Acorn CLE 215+ <http://squirrelsresearch.com/acorn-cle-215/>`__ Artix xc7a200tsbg484 OK OK
alchitry_au `Alchitry Au <https://alchitry.com/products/alchitry-au-fpga-development-board>`__ Artix xc7a35tftg256 OK OK alchitry_au `Alchitry Au <https://alchitry.com/products/alchitry-au-fpga-development-board>`__ Artix xc7a35tftg256 OK OK
arty `Digilent Arty A7 <https://reference.digilentinc.com/reference/programmable-logic/arty-a7/start>`__ Artix xc7a35ticsg324 OK OK arty `Digilent Arty A7 <https://reference.digilentinc.com/reference/programmable-logic/arty-a7/start>`__ Artix xc7a35ticsg324 OK OK
arty `Digilent Arty S7 <https://reference.digilentinc.com/reference/programmable-logic/arty-s7/start>`__ Spartan7 xc7s50csga324 OK OK arty_s7_25 `Digilent Arty S7 <https://reference.digilentinc.com/reference/programmable-logic/arty-s7/start>`__ Spartan7 xc7s25csga324 OK OK
arty_s7_50 `Digilent Arty S7 <https://reference.digilentinc.com/reference/programmable-logic/arty-s7/start>`__ Spartan7 xc7s50csga324 OK OK
arty `Digilent Analog Discovery 2 <https://reference.digilentinc.com/test-and-measurement/analog-discovery-2/start>`__ Spartan6 xc6slx25 OK NT arty `Digilent Analog Discovery 2 <https://reference.digilentinc.com/test-and-measurement/analog-discovery-2/start>`__ Spartan6 xc6slx25 OK NT
arty `Digilent Digital Discovery <https://reference.digilentinc.com/test-and-measurement/digital-discovery/start>`__ Spartan6 xc6slx25 OK NT arty `Digilent Digital Discovery <https://reference.digilentinc.com/test-and-measurement/digital-discovery/start>`__ Spartan6 xc6slx25 OK NT
basys3 `Digilent Basys3 <https://reference.digilentinc.com/reference/programmable-logic/basys-3/start>`__ Artix xc7a35tcpg236 OK OK basys3 `Digilent Basys3 <https://reference.digilentinc.com/reference/programmable-logic/basys-3/start>`__ Artix xc7a35tcpg236 OK OK

1
src/board.hpp
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@ -105,6 +105,7 @@ static std::map <std::string, target_board_t> board_list = {
JTAG_BOARD("acornCle215", "xc7a200tsbg484", "", 0, 0, CABLE_DEFAULT), JTAG_BOARD("acornCle215", "xc7a200tsbg484", "", 0, 0, CABLE_DEFAULT),
JTAG_BOARD("alchitry_au", "xc7a35tftg256", "ft2232", 0, 0, CABLE_DEFAULT), JTAG_BOARD("alchitry_au", "xc7a35tftg256", "ft2232", 0, 0, CABLE_DEFAULT),
JTAG_BOARD("arty", "xc7a35tcsg324", "digilent", 0, 0, CABLE_MHZ(10)), JTAG_BOARD("arty", "xc7a35tcsg324", "digilent", 0, 0, CABLE_MHZ(10)),
JTAG_BOARD("arty_s7_25", "xc7s25csga324", "digilent", 0, 0, CABLE_DEFAULT),
JTAG_BOARD("basys3", "xc7a35tcpg236", "digilent", 0, 0, CABLE_DEFAULT), JTAG_BOARD("basys3", "xc7a35tcpg236", "digilent", 0, 0, CABLE_DEFAULT),
JTAG_BOARD("nexysVideo", "xc7a200tsbg484", "digilent_b", 0, 0, CABLE_DEFAULT), JTAG_BOARD("nexysVideo", "xc7a200tsbg484", "digilent_b", 0, 0, CABLE_DEFAULT),
JTAG_BOARD("kc705", "", "digilent", 0, 0, CABLE_DEFAULT), JTAG_BOARD("kc705", "", "digilent", 0, 0, CABLE_DEFAULT),