From e026aa28c74af16dea62cee4450d7a50e505d6e3 Mon Sep 17 00:00:00 2001 From: Gwenhael Goavec-Merou Date: Sun, 19 Dec 2021 17:35:23 +0100 Subject: [PATCH] Digilent arty s7 25 --- doc/compatibility/board.rst | 7 ++++--- src/board.hpp | 1 + 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/doc/compatibility/board.rst b/doc/compatibility/board.rst index 21a995a..58947b2 100644 --- a/doc/compatibility/board.rst +++ b/doc/compatibility/board.rst @@ -17,12 +17,13 @@ Boards acornCle215 `Acorn CLE 215+ `__ Artix xc7a200tsbg484 OK OK alchitry_au `Alchitry Au `__ Artix xc7a35tftg256 OK OK arty `Digilent Arty A7 `__ Artix xc7a35ticsg324 OK OK - arty `Digilent Arty S7 `__ Spartan7 xc7s50csga324 OK OK + arty_s7_25 `Digilent Arty S7 `__ Spartan7 xc7s25csga324 OK OK + arty_s7_50 `Digilent Arty S7 `__ Spartan7 xc7s50csga324 OK OK arty `Digilent Analog Discovery 2 `__ Spartan6 xc6slx25 OK NT arty `Digilent Digital Discovery `__ Spartan6 xc6slx25 OK NT basys3 `Digilent Basys3 `__ Artix xc7a35tcpg236 OK OK - gatemate_evb_jtag `Cologne Chip GateMate FPGA Evaluation Board (JTAG mode) `__ Cologne Chip GateMate Series OK OK - gatemate_evb_spi `Cologne Chip GateMate FPGA Evaluation Board (SPI mode) `__ Cologne Chip GateMate Series OK OK + gatemate_evb_jtag `Cologne Chip GateMate FPGA Evaluation Board (JTAG mode) `__ Cologne Chip GateMate Series OK OK + gatemate_evb_spi `Cologne Chip GateMate FPGA Evaluation Board (SPI mode) `__ Cologne Chip GateMate Series OK OK gatemate_pgm_spi `Cologne Chip GateMate FPGA Programmer (SPI mode) `__ Cologne Chip GateMate Series OK OK colorlight `Colorlight 5A-75B (version 7) `__ ECP5 LFE5U-25F-6BG256C OK OK colorlight_i5 `Colorlight I5 `__ ECP5 LFE5U-25F-6BG381C OK OK diff --git a/src/board.hpp b/src/board.hpp index 090d48e..dc7bd20 100644 --- a/src/board.hpp +++ b/src/board.hpp @@ -105,6 +105,7 @@ static std::map board_list = { JTAG_BOARD("acornCle215", "xc7a200tsbg484", "", 0, 0, CABLE_DEFAULT), JTAG_BOARD("alchitry_au", "xc7a35tftg256", "ft2232", 0, 0, CABLE_DEFAULT), JTAG_BOARD("arty", "xc7a35tcsg324", "digilent", 0, 0, CABLE_MHZ(10)), + JTAG_BOARD("arty_s7_25", "xc7s25csga324", "digilent", 0, 0, CABLE_DEFAULT), JTAG_BOARD("basys3", "xc7a35tcpg236", "digilent", 0, 0, CABLE_DEFAULT), JTAG_BOARD("nexysVideo", "xc7a200tsbg484", "digilent_b", 0, 0, CABLE_DEFAULT), JTAG_BOARD("kc705", "", "digilent", 0, 0, CABLE_DEFAULT),