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openFPGALoader
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Adds wpn and hldn signals.

This commit is contained in:
Billy Stevens 2021-07-04 21:35:07 -04:00
parent 05c07df4cc
commit db73fedf40
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1 changed files with 8 additions and 4 deletions
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12
spiOverJtag/xc6/xilinx_spiOverJtag_xc6.vhd
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@ -6,10 +6,12 @@ use UNISIM.vcomponents.all;
entity xilinx_spiOverJtag is entity xilinx_spiOverJtag is
port ( port (
csn : out std_logic; csn : out std_logic;
sdi : out std_logic; sdi : out std_logic;
sdo : in std_logic; sdo : in std_logic;
sck : out std_logic sck : out std_logic;
wpn : out std_logic;
hldn : out std_logic
); );
end entity xilinx_spiOverJtag; end entity xilinx_spiOverJtag;
@ -21,6 +23,8 @@ architecture bhv of xilinx_spiOverJtag is
signal tmp_up_s, tmp_shift_s, tmp_cap_s : std_logic; signal tmp_up_s, tmp_shift_s, tmp_cap_s : std_logic;
begin begin
wpn <= '1';
hldn <= '1';
-- jtag -> spi flash -- jtag -> spi flash
csn <= fsm_csn; csn <= fsm_csn;
sdi <= tdi; sdi <= tdi;