From db73fedf4090c985164051b9b6541d7acc632374 Mon Sep 17 00:00:00 2001
From: Billy Stevens <contact@wasv.me>
Date: Sun, 4 Jul 2021 21:35:07 -0400
Subject: [PATCH] Adds wpn and hldn signals.

---
 spiOverJtag/xc6/xilinx_spiOverJtag_xc6.vhd | 12 ++++++++----
 1 file changed, 8 insertions(+), 4 deletions(-)

diff --git a/spiOverJtag/xc6/xilinx_spiOverJtag_xc6.vhd b/spiOverJtag/xc6/xilinx_spiOverJtag_xc6.vhd
index b691620..dfa1620 100644
--- a/spiOverJtag/xc6/xilinx_spiOverJtag_xc6.vhd
+++ b/spiOverJtag/xc6/xilinx_spiOverJtag_xc6.vhd
@@ -6,10 +6,12 @@ use UNISIM.vcomponents.all;
 
 entity xilinx_spiOverJtag is
 	port (
-		csn       : out std_logic;
-		sdi	  : out std_logic;
-		sdo       : in std_logic;
-		sck       : out std_logic
+	 csn       : out std_logic;
+	 sdi       : out std_logic;
+	 sdo       : in std_logic;
+	 sck       : out std_logic;
+	 wpn	   : out std_logic;
+	 hldn      : out std_logic
 	);
 end entity xilinx_spiOverJtag;
 
@@ -21,6 +23,8 @@ architecture bhv of xilinx_spiOverJtag is
 
 	signal tmp_up_s, tmp_shift_s, tmp_cap_s : std_logic;
 begin
+	wpn <= '1';
+	hldn <= '1';
 	-- jtag -> spi flash
 	csn <= fsm_csn;
 	sdi <= tdi;