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Add support for Xilinx xczu17eg. It's tested on xczu17eg board with Digilent HS3 at 30Mbps.

This commit is contained in:
Zhongyi Chen 2023-09-22 19:33:01 -07:00
parent c82a8e6207
commit c0ad3225cc
2 changed files with 3 additions and 0 deletions
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1
doc/FPGAs.yml
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@ -295,6 +295,7 @@ Xilinx:
- xczu2cg - xczu2cg
- xczu9eg - xczu9eg
- xczu11eg - xczu11eg
- xczu17eg
URL: https://www.xilinx.com/products/silicon-devices/soc/zynq-ultrascale-mpsoc.html URL: https://www.xilinx.com/products/silicon-devices/soc/zynq-ultrascale-mpsoc.html
Memory: OK Memory: OK
Flash: NA Flash: NA

2
src/part.hpp
View File

@ -108,11 +108,13 @@ static std::map <uint32_t, fpga_model> fpga_list = {
{0x08e22126, {"xilinx", "zynqmp_cfgn", "xczu2cg", 4}}, {0x08e22126, {"xilinx", "zynqmp_cfgn", "xczu2cg", 4}},
{0x08e70126, {"xilinx", "zynqmp_cfgn", "xczu9eg", 4}}, {0x08e70126, {"xilinx", "zynqmp_cfgn", "xczu9eg", 4}},
{0x08e80126, {"xilinx", "zynqmp_cfgn","xczu11eg", 4}}, {0x08e80126, {"xilinx", "zynqmp_cfgn","xczu11eg", 4}},
{0x28eb2126, {"xilinx", "zynqmp_cfgn","xczu17eg", 4}},
{0x08e60126, {"xilinx", "zynqmp_cfgn", "xczu7ev", 4}}, {0x08e60126, {"xilinx", "zynqmp_cfgn", "xczu7ev", 4}},
{0x04711093, {"xilinx", "zynqmp", "xczu2cg", 6}}, {0x04711093, {"xilinx", "zynqmp", "xczu2cg", 6}},
{0x04738093, {"xilinx", "zynqmp", "xczu9eg", 6}}, {0x04738093, {"xilinx", "zynqmp", "xczu9eg", 6}},
{0x04740093, {"xilinx", "zynqmp", "xczu11eg", 6}}, {0x04740093, {"xilinx", "zynqmp", "xczu11eg", 6}},
{0x14759093, {"xilinx", "zynqmp", "xczu17eg", 6}},
{0x04730093, {"xilinx", "zynqmp", "xczu7ev", 6}}, {0x04730093, {"xilinx", "zynqmp", "xczu7ev", 6}},
/**************************************************************************/ /**************************************************************************/