From c0ad3225cc77b836be5da162e4ca638dd4dfe1f4 Mon Sep 17 00:00:00 2001
From: Zhongyi Chen <zhongyi.chen@gmail.com>
Date: Fri, 22 Sep 2023 19:33:01 -0700
Subject: [PATCH] Add support for Xilinx xczu17eg. It's tested on xczu17eg
 board with Digilent HS3 at 30Mbps.

---
 doc/FPGAs.yml | 1 +
 src/part.hpp  | 2 ++
 2 files changed, 3 insertions(+)

diff --git a/doc/FPGAs.yml b/doc/FPGAs.yml
index 07ad7ef..7908c1d 100644
--- a/doc/FPGAs.yml
+++ b/doc/FPGAs.yml
@@ -295,6 +295,7 @@ Xilinx:
       - xczu2cg
       - xczu9eg
       - xczu11eg
+      - xczu17eg
     URL: https://www.xilinx.com/products/silicon-devices/soc/zynq-ultrascale-mpsoc.html
     Memory: OK
     Flash: NA
diff --git a/src/part.hpp b/src/part.hpp
index 87b40b0..0c45448 100644
--- a/src/part.hpp
+++ b/src/part.hpp
@@ -108,11 +108,13 @@ static std::map <uint32_t, fpga_model> fpga_list = {
 	{0x08e22126, {"xilinx", "zynqmp_cfgn", "xczu2cg", 4}},
 	{0x08e70126, {"xilinx", "zynqmp_cfgn", "xczu9eg", 4}},
 	{0x08e80126, {"xilinx", "zynqmp_cfgn","xczu11eg", 4}},
+	{0x28eb2126, {"xilinx", "zynqmp_cfgn","xczu17eg", 4}},
 	{0x08e60126, {"xilinx", "zynqmp_cfgn", "xczu7ev", 4}},
 
 	{0x04711093, {"xilinx", "zynqmp",  "xczu2cg", 6}},
 	{0x04738093, {"xilinx", "zynqmp",  "xczu9eg", 6}},
 	{0x04740093, {"xilinx", "zynqmp", "xczu11eg", 6}},
+	{0x14759093, {"xilinx", "zynqmp", "xczu17eg", 6}},
 	{0x04730093, {"xilinx", "zynqmp",  "xczu7ev", 6}},
 
 	/**************************************************************************/