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openFPGALoader
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board: added ULX4M (DFU)

This commit is contained in:
Gwenhael Goavec-Merou 2025-07-19 09:45:04 +02:00
parent 5e91e20e29
commit b99672b69e
2 changed files with 8 additions and 0 deletions
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7
doc/boards.yml
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@ -895,6 +895,13 @@
Memory: NA Memory: NA
Flash: OK Flash: OK
- ID: ulx4m_dfu
Description: Radiona ULX4M LD/LS DFU mode
URL: https://github.com/intergalaktik/ulx4m-ls
FPGA: ECP5 LFE5U
Memory: NA
Flash: OK
- ID: vec_v6 - ID: vec_v6
Description: Xilinx VCU118 Description: Xilinx VCU118
URL: https://vmm-srs.docs.cern.ch/ URL: https://vmm-srs.docs.cern.ch/

1
src/board.hpp
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@ -255,6 +255,7 @@ static std::map <std::string, target_board_t> board_list = {
FT232RL_DCD, FT232RL_DSR, FT232RL_RI, FT232RL_CTS, CABLE_DEFAULT), FT232RL_DCD, FT232RL_DSR, FT232RL_RI, FT232RL_CTS, CABLE_DEFAULT),
DFU_BOARD("ulx3s_dfu", "", "dfu", 0x1d50, 0x614b, 0), DFU_BOARD("ulx3s_dfu", "", "dfu", 0x1d50, 0x614b, 0),
JTAG_BOARD("ulx3s_esp", "", "esp32s3", 0, 0, CABLE_DEFAULT), JTAG_BOARD("ulx3s_esp", "", "esp32s3", 0, 0, CABLE_DEFAULT),
DFU_BOARD("ulx4m_dfu", "", "dfu", 0x1d50, 0x614b, 0),
JTAG_BOARD("usrpx300", "xc7k325tffg900", "digilent", 0, 0, CABLE_MHZ(15)), JTAG_BOARD("usrpx300", "xc7k325tffg900", "digilent", 0, 0, CABLE_MHZ(15)),
JTAG_BOARD("usrpx310", "xc7k410tffg900", "digilent", 0, 0, CABLE_MHZ(15)), JTAG_BOARD("usrpx310", "xc7k410tffg900", "digilent", 0, 0, CABLE_MHZ(15)),
JTAG_BOARD("vec_v6", "xc6vlx130tff784", "ft2232", 0, 0, CABLE_DEFAULT), JTAG_BOARD("vec_v6", "xc6vlx130tff784", "ft2232", 0, 0, CABLE_DEFAULT),