From b99672b69e96145dbaf5c0d6af36cd0963a4cb59 Mon Sep 17 00:00:00 2001 From: Gwenhael Goavec-Merou Date: Sat, 19 Jul 2025 09:45:04 +0200 Subject: [PATCH] board: added ULX4M (DFU) --- doc/boards.yml | 7 +++++++ src/board.hpp | 1 + 2 files changed, 8 insertions(+) diff --git a/doc/boards.yml b/doc/boards.yml index 186a5e1..0e85a78 100644 --- a/doc/boards.yml +++ b/doc/boards.yml @@ -895,6 +895,13 @@ Memory: NA Flash: OK +- ID: ulx4m_dfu + Description: Radiona ULX4M LD/LS DFU mode + URL: https://github.com/intergalaktik/ulx4m-ls + FPGA: ECP5 LFE5U + Memory: NA + Flash: OK + - ID: vec_v6 Description: Xilinx VCU118 URL: https://vmm-srs.docs.cern.ch/ diff --git a/src/board.hpp b/src/board.hpp index 902d8b0..af3fee3 100644 --- a/src/board.hpp +++ b/src/board.hpp @@ -255,6 +255,7 @@ static std::map board_list = { FT232RL_DCD, FT232RL_DSR, FT232RL_RI, FT232RL_CTS, CABLE_DEFAULT), DFU_BOARD("ulx3s_dfu", "", "dfu", 0x1d50, 0x614b, 0), JTAG_BOARD("ulx3s_esp", "", "esp32s3", 0, 0, CABLE_DEFAULT), + DFU_BOARD("ulx4m_dfu", "", "dfu", 0x1d50, 0x614b, 0), JTAG_BOARD("usrpx300", "xc7k325tffg900", "digilent", 0, 0, CABLE_MHZ(15)), JTAG_BOARD("usrpx310", "xc7k410tffg900", "digilent", 0, 0, CABLE_MHZ(15)), JTAG_BOARD("vec_v6", "xc6vlx130tff784", "ft2232", 0, 0, CABLE_DEFAULT),