Merge pull request #97 from wasv/xc6

Adds support for the Xilinx Spartan 6

CMakeLists.txt

@@ -198,14 +198,9 @@ math(EXPR FTDI_VAL "${LIBFTDI_VERSION_MAJOR} * 100 + ${LIBFTDI_VERSION_MINOR}")
 add_definitions(-DFTDI_VERSION=${FTDI_VAL})
 
 install(TARGETS openFPGALoader DESTINATION bin)
+file(GLOB BITS_FILES spiOverJtag/spiOverJtag_*.bit)
 install(FILES 
 	test_sfl.svf
-	spiOverJtag/spiOverJtag_xc7a100tfgg484.bit
-	spiOverJtag/spiOverJtag_xc7a200tsbg484.bit
-	spiOverJtag/spiOverJtag_xc7a35tcsg324.bit
-	spiOverJtag/spiOverJtag_xc7a35tftg256.bit
-	spiOverJtag/spiOverJtag_xc7a50tcpg236.bit
-	spiOverJtag/spiOverJtag_xc7a75tfgg484.bit
-	spiOverJtag/spiOverJtag_xc7s50csga324.bit
+	${BITS_FILES}
 	DESTINATION ${CMAKE_INSTALL_DATAROOTDIR}/openFPGALoader
 )

spiOverJtag/xc6/.gitignore

@@ -0,0 +1,5 @@
+*
+!*.gitignore
+!*.ucf
+!*.vhd
+!*.tcl

spiOverJtag/xc6/constr_xc6s_fgg484.ucf

@@ -0,0 +1,6 @@
+CONFIG VCCAUX = "2.5";
+
+NET "sdo" LOC = AA20 | IOSTANDARD = LVCMOS33;
+NET "sdi" LOC = AB20 | IOSTANDARD = LVCMOS33;
+NET "csn" LOC = T5   | IOSTANDARD = LVCMOS33;
+NET "sck" LOC = Y21  | IOSTANDARD = LVCMOS33;

spiOverJtag/xc6/xilinx_spiOverJtag_xc6.tcl

@@ -0,0 +1,44 @@
+# 
+# Project automation script for spiOverJtag_xc6
+# 
+# Created for ISE version 14.7
+# 
+
+set myProject "xilinx_spiOverJtag_xc6"
+set myScript "xilinx_spiOverJtag_xc6.tcl"
+
+puts "\n$myScript: Rebuilding ($myProject)...\n"
+
+if { [file exists "${myProject}.xise" ] } {
+   project open $myProject
+} else {
+   project new $myProject
+
+   project set family "Spartan6"
+   project set device "xc6slx100"
+   project set package "fgg484"
+   project set speed "-2"
+   project set top_level_module_type "HDL"
+   project set synthesis_tool "XST (VHDL/Verilog)"
+   project set simulator "ISim (VHDL/Verilog)"
+   project set "Preferred Language" "VHDL"
+   project set "Enable Message Filtering" "false"
+   
+   project set "VHDL Source Analysis Standard" "VHDL-200X"
+   project set "Enable Internal Done Pipe" "true" -process "Generate Programming File"
+   
+   xfile add "constr_xc6s_fgg484.ucf"
+   xfile add "xilinx_spiOverJtag_xc6.vhd"
+   
+   project set top "bhv" "xilinx_spiOverJtag"
+}
+
+if { ! [ process run "Implement Design" ] } {
+   return false;
+}
+if { ! [ process run "Generate Programming File" ] } {
+   return false;
+}
+
+puts "Run completed successfully."
+project close

spiOverJtag/xc6/xilinx_spiOverJtag_xc6.vhd

@@ -0,0 +1,68 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+Library UNISIM;
+use UNISIM.vcomponents.all;
+
+entity xilinx_spiOverJtag is
+	port (
+	 csn       : out std_logic;
+	 sdi       : out std_logic;
+	 sdo       : in std_logic;
+	 sck       : out std_logic;
+	 wpn	   : out std_logic;
+	 hldn      : out std_logic
+	);
+end entity xilinx_spiOverJtag;
+
+architecture bhv of xilinx_spiOverJtag is
+	signal capture, drck, sel, shift, update : std_logic;
+	signal runtest : std_logic;
+	signal tdi, tdo   : std_logic;
+	signal fsm_csn : std_logic;
+
+	signal tmp_up_s, tmp_shift_s, tmp_cap_s : std_logic;
+begin
+	wpn <= '1';
+	hldn <= '1';
+	-- jtag -> spi flash
+	csn <= fsm_csn;
+	sdi <= tdi;
+	tdo <= tdi when (sel) = '0' else sdo;
+	sck <= drck;
+
+	tmp_cap_s <= capture and sel;
+	tmp_up_s <= update and sel;
+
+	process(drck, runtest) begin
+		if runtest = '1' then
+			fsm_csn <= '1';
+		elsif rising_edge(drck) then
+			if tmp_cap_s = '1' then
+				fsm_csn <= '0';
+			elsif tmp_up_s = '1' then
+				fsm_csn <= '1';
+			else
+				fsm_csn <= fsm_csn;
+			end if;
+		end if;
+	end process;
+
+	BSCAN_SPARTAN6_inst : BSCAN_SPARTAN6
+   generic map (
+      JTAG_CHAIN => 1  -- Value for USER command. Possible values: (1,2,3 or 4).
+   )
+   port map (
+      CAPTURE => capture, -- 1-bit output: CAPTURE output from TAP controller.
+      DRCK => drck,       -- 1-bit output: Data register output for USER functions.
+      RUNTEST => runtest, -- 1-bit output: Output signal that gets asserted when TAP controller is in Run Test
+                          -- Idle state.
+
+      SEL => sel,         -- 1-bit output: USER active output.
+      SHIFT => shift,     -- 1-bit output: SHIFT output from TAP controller.
+      TDI => tdi,         -- 1-bit output: TDI output from TAP controller.
+      UPDATE => update,   -- 1-bit output: UPDATE output from TAP controller
+      TDO => tdo          -- 1-bit input: Data input for USER function.
+   );
+
+end architecture bhv;

src/part.hpp

@@ -30,6 +30,7 @@ static std::map <int, fpga_model> fpga_list = {
 	{0x24001093, {"xilinx", "spartan6", "xc6slx9",  6}},
 	{0x24002093, {"xilinx", "spartan6", "xc6slx16", 6}},
 	{0x24004093, {"xilinx", "spartan6", "xc6slx25", 6}},
+	{0x24011093, {"xilinx", "spartan6", "xc6slx100", 6}},
 	{0x44008093, {"xilinx", "spartan6", "xc6slx45", 6}},
 	{0x03620093, {"xilinx", "spartan7", "xc7s15ftgb196-1", 6}},
 	{0x037c4093, {"xilinx", "spartan7", "xc7s25", 6}},