From f937cb9ab586d1159916228589a319a0afd9afb6 Mon Sep 17 00:00:00 2001 From: Billy Stevens Date: Sat, 3 Jul 2021 05:01:56 -0400 Subject: [PATCH 1/4] Adds support for the xc6slx100fgg484. Tested on a Pano Logic G2. --- CMakeLists.txt | 9 +- spiOverJtag/spiOverJtag_xc6slx100fgg484.bit | Bin 0 -> 3318013 bytes spiOverJtag/xc6/constr_xc6s_fgg484.ucf | 6 + spiOverJtag/xc6/xilinx_spiOverJtag_xc6.tcl | 318 ++++++++++++++++++++ spiOverJtag/xc6/xilinx_spiOverJtag_xc6.vhd | 64 ++++ src/part.hpp | 1 + 6 files changed, 391 insertions(+), 7 deletions(-) create mode 100644 spiOverJtag/spiOverJtag_xc6slx100fgg484.bit create mode 100644 spiOverJtag/xc6/constr_xc6s_fgg484.ucf create mode 100644 spiOverJtag/xc6/xilinx_spiOverJtag_xc6.tcl create mode 100644 spiOverJtag/xc6/xilinx_spiOverJtag_xc6.vhd diff --git a/CMakeLists.txt b/CMakeLists.txt index 2e2109a..2c3bafa 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -198,14 +198,9 @@ math(EXPR FTDI_VAL "${LIBFTDI_VERSION_MAJOR} * 100 + ${LIBFTDI_VERSION_MINOR}") add_definitions(-DFTDI_VERSION=${FTDI_VAL}) install(TARGETS openFPGALoader DESTINATION bin) +file(GLOB BITS_FILES spiOverJtag/spiOverJtag_*.bit) install(FILES test_sfl.svf - spiOverJtag/spiOverJtag_xc7a100tfgg484.bit - spiOverJtag/spiOverJtag_xc7a200tsbg484.bit - spiOverJtag/spiOverJtag_xc7a35tcsg324.bit - spiOverJtag/spiOverJtag_xc7a35tftg256.bit - spiOverJtag/spiOverJtag_xc7a50tcpg236.bit - spiOverJtag/spiOverJtag_xc7a75tfgg484.bit - spiOverJtag/spiOverJtag_xc7s50csga324.bit + ${BITS_FILES} DESTINATION ${CMAKE_INSTALL_DATAROOTDIR}/openFPGALoader ) diff --git a/spiOverJtag/spiOverJtag_xc6slx100fgg484.bit b/spiOverJtag/spiOverJtag_xc6slx100fgg484.bit new file mode 100644 index 0000000000000000000000000000000000000000..3858ff4b2dfd84c2cb98b28f610966b148aa7947 GIT binary patch literal 3318013 zcmeI*J&zq%835pO*G_Ux60%eXQE-eXpdoj?2BMINv4oJI2~BD+`BJ1PLJ2}H*Ahhv z3M6Rg;+BFI(K)H;_zmUO^KYev|=Vza{ z^qch6AAb1Wouk$2?RVa}`O?kwMtb(f>c-KFs~^3%I!Bh%@ zDbKXO{q^;?SNGC0IUU_we)s6stIMO?*ZzC->D9&IpH~mkzgM56yE#Qaj_s`s$0ybCAf@Ab-~7+Sc7>Z@

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b/spiOverJtag/xc6/xilinx_spiOverJtag_xc6.tcl @@ -0,0 +1,318 @@ +# +# Project automation script for spiOverJtag_xc6 +# +# Created for ISE version 14.7 +# +# This file contains several Tcl procedures (procs) that you can use to automate +# your project by running from xtclsh or the Project Navigator Tcl console. +# If you load this file (using the Tcl command: source xilinx_spiOverJtag_xc6.tcl), then you can +# run any of the procs included here. +# +# This script is generated assuming your project has HDL sources. +# Several of the defined procs won't apply to an EDIF or NGC based project. +# If that is the case, simply remove them from this script. +# +# You may also edit any of these procs to customize them. See comments in each +# proc for more instructions. +# +# This file contains the following procedures: +# +# Top Level procs (meant to be called directly by the user): +# run_process: you can use this top-level procedure to run any processes +# that you choose to by adding and removing comments, or by +# adding new entries. +# rebuild_project: you can alternatively use this top-level procedure +# to recreate your entire project, and the run selected processes. +# +# Lower Level (helper) procs (called under in various cases by the top level procs): +# show_help: print some basic information describing how this script works +# add_source_files: adds the listed source files to your project. +# set_project_props: sets the project properties that were in effect when this +# script was generated. +# create_libraries: creates and adds file to VHDL libraries that were defined when +# this script was generated. +# set_process_props: set the process properties as they were set for your project +# when this script was generated. +# + +set myProject "xilinx_spiOverJtag_xc6" +set myScript "xilinx_spiOverJtag_xc6.tcl" + +# +# Main (top-level) routines +# +# run_process +# This procedure is used to run processes on an existing project. You may comment or +# uncomment lines to control which processes are run. This routine is set up to run +# the Implement Design and Generate Programming File processes by default. This proc +# also sets process properties as specified in the "set_process_props" proc. Only +# those properties which have values different from their current settings in the project +# file will be modified in the project. +# +proc run_process {} { + + global myScript + global myProject + + ## put out a 'heartbeat' - so we know something's happening. + puts "\n$myScript: running ($myProject)...\n" + + if { ! [ open_project ] } { + return false + } + + set_process_props + # + # Remove the comment characters (#'s) to enable the following commands + # process run "Synthesize" + # process run "Translate" + # process run "Map" + # process run "Place & Route" + # + set task "Implement Design" + if { ! [run_task $task] } { + puts "$myScript: $task run failed, check run output for details." + project close + return + } + + set task "Generate Programming File" + if { ! [run_task $task] } { + puts "$myScript: $task run failed, check run output for details." + project close + return + } + + puts "Run completed (successfully)." + project close + +} + +# +# rebuild_project +# +# This procedure renames the project file (if it exists) and recreates the project. +# It then sets project properties and adds project sources as specified by the +# set_project_props and add_source_files support procs. It recreates VHDL Libraries +# as they existed at the time this script was generated. +# +# It then calls run_process to set process properties and run selected processes. +# +proc rebuild_project {} { + + global myScript + global myProject + + project close + ## put out a 'heartbeat' - so we know something's happening. + puts "\n$myScript: Rebuilding ($myProject)...\n" + + set proj_exts [ list ise xise gise ] + foreach ext $proj_exts { + set proj_name "${myProject}.$ext" + if { [ file exists $proj_name ] } { + file delete $proj_name + } + } + + project new $myProject + set_project_props + add_source_files + create_libraries + puts "$myScript: project rebuild completed." + + run_process + +} + +# +# Support Routines +# + +# +proc run_task { task } { + + # helper proc for run_process + + puts "Running '$task'" + set result [ process run "$task" ] + # + # check process status (and result) + set status [ process get $task status ] + if { ( ( $status != "up_to_date" ) && \ + ( $status != "warnings" ) ) || \ + ! $result } { + return false + } + return true +} + +# +# show_help: print information to help users understand the options available when +# running this script. +# +proc show_help {} { + + global myScript + + puts "" + puts "usage: xtclsh $myScript " + puts " or you can run xtclsh and then enter 'source $myScript'." + puts "" + puts "options:" + puts " run_process - set properties and run processes." + puts " rebuild_project - rebuild the project from scratch and run processes." + puts " set_project_props - set project properties (device, speed, etc.)" + puts " add_source_files - add source files" + puts " create_libraries - create vhdl libraries" + puts " set_process_props - set process property values" + puts " show_help - print this message" + puts "" +} + +proc open_project {} { + + global myScript + global myProject + + if { ! [ file exists ${myProject}.xise ] } { + ## project file isn't there, rebuild it. + puts "Project $myProject not found. Use project_rebuild to recreate it." + return false + } + + project open $myProject + + return true + +} +# +# set_project_props +# +# This procedure sets the project properties as they were set in the project +# at the time this script was generated. +# +proc set_project_props {} { + + global myScript + + if { ! [ open_project ] } { + return false + } + + puts "$myScript: Setting project properties..." + + project set family "Spartan6" + project set device "xc6slx100" + project set package "fgg484" + project set speed "-2" + project set top_level_module_type "HDL" + project set synthesis_tool "XST (VHDL/Verilog)" + project set simulator "ISim (VHDL/Verilog)" + project set "Preferred Language" "VHDL" + project set "Enable Message Filtering" "false" + +} + + +# +# add_source_files +# +# This procedure add the source files that were known to the project at the +# time this script was generated. +# +proc add_source_files {} { + + global myScript + + if { ! [ open_project ] } { + return false + } + + puts "$myScript: Adding sources to project..." + + xfile add "constr_xc6s_fgg484.ucf" + xfile add "xilinx_spiOverJtag_xc6.vhd" + + # Set the Top Module as well... + project set top "bhv" "xilinx_spiOverJtag" + + puts "$myScript: project sources reloaded." + +} ; # end add_source_files + +# +# create_libraries +# +# This procedure defines VHDL libraries and associates files with those libraries. +# It is expected to be used when recreating the project. Any libraries defined +# when this script was generated are recreated by this procedure. +# +proc create_libraries {} { + + global myScript + + if { ! [ open_project ] } { + return false + } + + puts "$myScript: Creating libraries..." + + + # must close the project or library definitions aren't saved. + project save + +} ; # end create_libraries + +# +# set_process_props +# +# This procedure sets properties as requested during script generation (either +# all of the properties, or only those modified from their defaults). +# +proc set_process_props {} { + + global myScript + + if { ! [ open_project ] } { + return false + } + + puts "$myScript: setting process properties..." + + project set "VHDL Source Analysis Standard" "VHDL-200X" + project set "Enable Internal Done Pipe" "true" -process "Generate Programming File" + + puts "$myScript: project property values set." + +} ; # end set_process_props + +proc main {} { + + if { [llength $::argv] == 0 } { + show_help + return true + } + + foreach option $::argv { + switch $option { + "show_help" { show_help } + "run_process" { run_process } + "rebuild_project" { rebuild_project } + "set_project_props" { set_project_props } + "add_source_files" { add_source_files } + "create_libraries" { create_libraries } + "set_process_props" { set_process_props } + default { puts "unrecognized option: $option"; show_help } + } + } +} + +if { $tcl_interactive } { + show_help +} else { + if {[catch {main} result]} { + puts "$myScript failed: $result." + } +} + diff --git a/spiOverJtag/xc6/xilinx_spiOverJtag_xc6.vhd b/spiOverJtag/xc6/xilinx_spiOverJtag_xc6.vhd new file mode 100644 index 0000000..b691620 --- /dev/null +++ b/spiOverJtag/xc6/xilinx_spiOverJtag_xc6.vhd @@ -0,0 +1,64 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; +Library UNISIM; +use UNISIM.vcomponents.all; + +entity xilinx_spiOverJtag is + port ( + csn : out std_logic; + sdi : out std_logic; + sdo : in std_logic; + sck : out std_logic + ); +end entity xilinx_spiOverJtag; + +architecture bhv of xilinx_spiOverJtag is + signal capture, drck, sel, shift, update : std_logic; + signal runtest : std_logic; + signal tdi, tdo : std_logic; + signal fsm_csn : std_logic; + + signal tmp_up_s, tmp_shift_s, tmp_cap_s : std_logic; +begin + -- jtag -> spi flash + csn <= fsm_csn; + sdi <= tdi; + tdo <= tdi when (sel) = '0' else sdo; + sck <= drck; + + tmp_cap_s <= capture and sel; + tmp_up_s <= update and sel; + + process(drck, runtest) begin + if runtest = '1' then + fsm_csn <= '1'; + elsif rising_edge(drck) then + if tmp_cap_s = '1' then + fsm_csn <= '0'; + elsif tmp_up_s = '1' then + fsm_csn <= '1'; + else + fsm_csn <= fsm_csn; + end if; + end if; + end process; + + BSCAN_SPARTAN6_inst : BSCAN_SPARTAN6 + generic map ( + JTAG_CHAIN => 1 -- Value for USER command. Possible values: (1,2,3 or 4). + ) + port map ( + CAPTURE => capture, -- 1-bit output: CAPTURE output from TAP controller. + DRCK => drck, -- 1-bit output: Data register output for USER functions. + RUNTEST => runtest, -- 1-bit output: Output signal that gets asserted when TAP controller is in Run Test + -- Idle state. + + SEL => sel, -- 1-bit output: USER active output. + SHIFT => shift, -- 1-bit output: SHIFT output from TAP controller. + TDI => tdi, -- 1-bit output: TDI output from TAP controller. + UPDATE => update, -- 1-bit output: UPDATE output from TAP controller + TDO => tdo -- 1-bit input: Data input for USER function. + ); + +end architecture bhv; diff --git a/src/part.hpp b/src/part.hpp index 07ea17d..23e7861 100644 --- a/src/part.hpp +++ b/src/part.hpp @@ -30,6 +30,7 @@ static std::map fpga_list = { {0x24001093, {"xilinx", "spartan6", "xc6slx9", 6}}, {0x24002093, {"xilinx", "spartan6", "xc6slx16", 6}}, {0x24004093, {"xilinx", "spartan6", "xc6slx25", 6}}, + {0x24011093, {"xilinx", "spartan6", "xc6slx100", 6}}, {0x44008093, {"xilinx", "spartan6", "xc6slx45", 6}}, {0x03620093, {"xilinx", "spartan7", "xc7s15ftgb196-1", 6}}, {0x037c4093, {"xilinx", "spartan7", "xc7s25", 6}}, From 1d6505182cbc58d378929516f4d35e3c1c78f30b Mon Sep 17 00:00:00 2001 From: Billy Stevens Date: Sun, 4 Jul 2021 21:33:48 -0400 Subject: [PATCH 2/4] Adds .gitignore for ISE build files. --- spiOverJtag/xc6/.gitignore | 5 +++++ 1 file changed, 5 insertions(+) create mode 100644 spiOverJtag/xc6/.gitignore diff --git a/spiOverJtag/xc6/.gitignore b/spiOverJtag/xc6/.gitignore new file mode 100644 index 0000000..64ff60f --- /dev/null +++ b/spiOverJtag/xc6/.gitignore @@ -0,0 +1,5 @@ +* +!*.gitignore +!*.ucf +!*.vhd +!*.tcl From 05c07df4cca5e1f8c6af8e7f302622a23040f98d Mon Sep 17 00:00:00 2001 From: Billy Stevens Date: Sun, 4 Jul 2021 21:34:23 -0400 Subject: [PATCH 3/4] Condenses TCL script. --- spiOverJtag/xc6/xilinx_spiOverJtag_xc6.tcl | 308 ++------------------- 1 file changed, 17 insertions(+), 291 deletions(-) diff --git a/spiOverJtag/xc6/xilinx_spiOverJtag_xc6.tcl b/spiOverJtag/xc6/xilinx_spiOverJtag_xc6.tcl index e7267db..73344b1 100644 --- a/spiOverJtag/xc6/xilinx_spiOverJtag_xc6.tcl +++ b/spiOverJtag/xc6/xilinx_spiOverJtag_xc6.tcl @@ -3,204 +3,16 @@ # # Created for ISE version 14.7 # -# This file contains several Tcl procedures (procs) that you can use to automate -# your project by running from xtclsh or the Project Navigator Tcl console. -# If you load this file (using the Tcl command: source xilinx_spiOverJtag_xc6.tcl), then you can -# run any of the procs included here. -# -# This script is generated assuming your project has HDL sources. -# Several of the defined procs won't apply to an EDIF or NGC based project. -# If that is the case, simply remove them from this script. -# -# You may also edit any of these procs to customize them. See comments in each -# proc for more instructions. -# -# This file contains the following procedures: -# -# Top Level procs (meant to be called directly by the user): -# run_process: you can use this top-level procedure to run any processes -# that you choose to by adding and removing comments, or by -# adding new entries. -# rebuild_project: you can alternatively use this top-level procedure -# to recreate your entire project, and the run selected processes. -# -# Lower Level (helper) procs (called under in various cases by the top level procs): -# show_help: print some basic information describing how this script works -# add_source_files: adds the listed source files to your project. -# set_project_props: sets the project properties that were in effect when this -# script was generated. -# create_libraries: creates and adds file to VHDL libraries that were defined when -# this script was generated. -# set_process_props: set the process properties as they were set for your project -# when this script was generated. -# set myProject "xilinx_spiOverJtag_xc6" set myScript "xilinx_spiOverJtag_xc6.tcl" -# -# Main (top-level) routines -# -# run_process -# This procedure is used to run processes on an existing project. You may comment or -# uncomment lines to control which processes are run. This routine is set up to run -# the Implement Design and Generate Programming File processes by default. This proc -# also sets process properties as specified in the "set_process_props" proc. Only -# those properties which have values different from their current settings in the project -# file will be modified in the project. -# -proc run_process {} { - - global myScript - global myProject - - ## put out a 'heartbeat' - so we know something's happening. - puts "\n$myScript: running ($myProject)...\n" - - if { ! [ open_project ] } { - return false - } - - set_process_props - # - # Remove the comment characters (#'s) to enable the following commands - # process run "Synthesize" - # process run "Translate" - # process run "Map" - # process run "Place & Route" - # - set task "Implement Design" - if { ! [run_task $task] } { - puts "$myScript: $task run failed, check run output for details." - project close - return - } - - set task "Generate Programming File" - if { ! [run_task $task] } { - puts "$myScript: $task run failed, check run output for details." - project close - return - } - - puts "Run completed (successfully)." - project close - -} - -# -# rebuild_project -# -# This procedure renames the project file (if it exists) and recreates the project. -# It then sets project properties and adds project sources as specified by the -# set_project_props and add_source_files support procs. It recreates VHDL Libraries -# as they existed at the time this script was generated. -# -# It then calls run_process to set process properties and run selected processes. -# -proc rebuild_project {} { - - global myScript - global myProject - - project close - ## put out a 'heartbeat' - so we know something's happening. - puts "\n$myScript: Rebuilding ($myProject)...\n" - - set proj_exts [ list ise xise gise ] - foreach ext $proj_exts { - set proj_name "${myProject}.$ext" - if { [ file exists $proj_name ] } { - file delete $proj_name - } - } - - project new $myProject - set_project_props - add_source_files - create_libraries - puts "$myScript: project rebuild completed." - - run_process - -} - -# -# Support Routines -# - -# -proc run_task { task } { - - # helper proc for run_process - - puts "Running '$task'" - set result [ process run "$task" ] - # - # check process status (and result) - set status [ process get $task status ] - if { ( ( $status != "up_to_date" ) && \ - ( $status != "warnings" ) ) || \ - ! $result } { - return false - } - return true -} - -# -# show_help: print information to help users understand the options available when -# running this script. -# -proc show_help {} { - - global myScript - - puts "" - puts "usage: xtclsh $myScript " - puts " or you can run xtclsh and then enter 'source $myScript'." - puts "" - puts "options:" - puts " run_process - set properties and run processes." - puts " rebuild_project - rebuild the project from scratch and run processes." - puts " set_project_props - set project properties (device, speed, etc.)" - puts " add_source_files - add source files" - puts " create_libraries - create vhdl libraries" - puts " set_process_props - set process property values" - puts " show_help - print this message" - puts "" -} - -proc open_project {} { - - global myScript - global myProject - - if { ! [ file exists ${myProject}.xise ] } { - ## project file isn't there, rebuild it. - puts "Project $myProject not found. Use project_rebuild to recreate it." - return false - } +puts "\n$myScript: Rebuilding ($myProject)...\n" +if { [file exists "${myProject}.xise" ] } { project open $myProject - - return true - -} -# -# set_project_props -# -# This procedure sets the project properties as they were set in the project -# at the time this script was generated. -# -proc set_project_props {} { - - global myScript - - if { ! [ open_project ] } { - return false - } - - puts "$myScript: Setting project properties..." +} else { + project new $myProject project set family "Spartan6" project set device "xc6slx100" @@ -211,108 +23,22 @@ proc set_project_props {} { project set simulator "ISim (VHDL/Verilog)" project set "Preferred Language" "VHDL" project set "Enable Message Filtering" "false" - -} - - -# -# add_source_files -# -# This procedure add the source files that were known to the project at the -# time this script was generated. -# -proc add_source_files {} { - - global myScript - - if { ! [ open_project ] } { - return false - } - - puts "$myScript: Adding sources to project..." - - xfile add "constr_xc6s_fgg484.ucf" - xfile add "xilinx_spiOverJtag_xc6.vhd" - - # Set the Top Module as well... - project set top "bhv" "xilinx_spiOverJtag" - - puts "$myScript: project sources reloaded." - -} ; # end add_source_files - -# -# create_libraries -# -# This procedure defines VHDL libraries and associates files with those libraries. -# It is expected to be used when recreating the project. Any libraries defined -# when this script was generated are recreated by this procedure. -# -proc create_libraries {} { - - global myScript - - if { ! [ open_project ] } { - return false - } - - puts "$myScript: Creating libraries..." - - - # must close the project or library definitions aren't saved. - project save - -} ; # end create_libraries - -# -# set_process_props -# -# This procedure sets properties as requested during script generation (either -# all of the properties, or only those modified from their defaults). -# -proc set_process_props {} { - - global myScript - - if { ! [ open_project ] } { - return false - } - - puts "$myScript: setting process properties..." - + project set "VHDL Source Analysis Standard" "VHDL-200X" project set "Enable Internal Done Pipe" "true" -process "Generate Programming File" - - puts "$myScript: project property values set." - -} ; # end set_process_props - -proc main {} { - - if { [llength $::argv] == 0 } { - show_help - return true - } - - foreach option $::argv { - switch $option { - "show_help" { show_help } - "run_process" { run_process } - "rebuild_project" { rebuild_project } - "set_project_props" { set_project_props } - "add_source_files" { add_source_files } - "create_libraries" { create_libraries } - "set_process_props" { set_process_props } - default { puts "unrecognized option: $option"; show_help } - } - } + + xfile add "constr_xc6s_fgg484.ucf" + xfile add "xilinx_spiOverJtag_xc6.vhd" + + project set top "bhv" "xilinx_spiOverJtag" } -if { $tcl_interactive } { - show_help -} else { - if {[catch {main} result]} { - puts "$myScript failed: $result." - } +if { ! [ process run "Implement Design" ] } { + return false; +} +if { ! [ process run "Generate Programming File" ] } { + return false; } +puts "Run completed successfully." +project close From db73fedf4090c985164051b9b6541d7acc632374 Mon Sep 17 00:00:00 2001 From: Billy Stevens Date: Sun, 4 Jul 2021 21:35:07 -0400 Subject: [PATCH 4/4] Adds wpn and hldn signals. --- spiOverJtag/xc6/xilinx_spiOverJtag_xc6.vhd | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/spiOverJtag/xc6/xilinx_spiOverJtag_xc6.vhd b/spiOverJtag/xc6/xilinx_spiOverJtag_xc6.vhd index b691620..dfa1620 100644 --- a/spiOverJtag/xc6/xilinx_spiOverJtag_xc6.vhd +++ b/spiOverJtag/xc6/xilinx_spiOverJtag_xc6.vhd @@ -6,10 +6,12 @@ use UNISIM.vcomponents.all; entity xilinx_spiOverJtag is port ( - csn : out std_logic; - sdi : out std_logic; - sdo : in std_logic; - sck : out std_logic + csn : out std_logic; + sdi : out std_logic; + sdo : in std_logic; + sck : out std_logic; + wpn : out std_logic; + hldn : out std_logic ); end entity xilinx_spiOverJtag; @@ -21,6 +23,8 @@ architecture bhv of xilinx_spiOverJtag is signal tmp_up_s, tmp_shift_s, tmp_cap_s : std_logic; begin + wpn <= '1'; + hldn <= '1'; -- jtag -> spi flash csn <= fsm_csn; sdi <= tdi;