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https://github.com/trabucayre/openFPGALoader.git
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doc: declare FPGA compatibility list through YAML file
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+82
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from typing import List, Union
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from pathlib import Path
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from dataclasses import dataclass
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from yaml import load as yaml_load, Loader as yaml_loader, dump as yaml_dump
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from tabulate import tabulate
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ROOT = Path(__file__).resolve().parent
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@dataclass
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class Board:
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ID: str
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Description: str = None
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URL: str = None
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FPGA: str = None
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Memory: str = None
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Flash: str = None
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Constraints: str = None
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def ReadBoardDataFromYAML():
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with (ROOT / 'boards.yml').open('r', encoding='utf-8') as fptr:
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data = [Board(**item) for item in yaml_load(fptr, yaml_loader)]
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return data
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def BoardDataToTable(data, tablefmt: str = "rst"):
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def processConstraints(constraints):
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if constraints is None:
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return None
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if isinstance(constraints, str):
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constraints = [constraints]
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return " ".join([f":ref:`{item} ➚ <constraints:boards:{item.lower()}>`" for item in constraints])
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return tabulate(
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[
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[
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item.ID,
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f"`{item.Description} <{item.URL}>`__",
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item.FPGA,
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item.Memory,
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item.Flash,
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processConstraints(item.Constraints)
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] for item in data
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],
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headers=["Board name", "Description", "FPGA", "Memory", "Flash", "Constraints"],
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tablefmt=tablefmt
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)
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@dataclass
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class FPGA:
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Model: Union[str, List[str]]
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Description: str
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URL: str = None
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Memory: str = None
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Flash: str = None
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def ReadFPGADataFromYAML():
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with (ROOT / 'FPGAs.yml').open('r', encoding='utf-8') as fptr:
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data = yaml_load(fptr, yaml_loader)
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for vendor, content in data.items():
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data[vendor] = [FPGA(**item) for item in content]
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return data
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def FPGADataToTable(data, tablefmt: str = "rst"):
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return tabulate(
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[
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[
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vendor,
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f"`{item.Description} <{item.URL}>`__",
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item.Model if isinstance(item.Model, str) else ', '.join(item.Model),
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item.Memory,
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item.Flash
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] for vendor, content in data.items() for item in content
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],
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headers=["Vendor", "Description", "Model", "Memory", "Flash"],
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tablefmt=tablefmt
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)
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