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rework xilinx fpga spiOverJtag to respect model/package

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This commit is contained in:
Gwenhael Goavec-Merou
2021-04-19 21:17:08 +02:00
parent 65a1e995ec
commit 7039465353
21 changed files with 123 additions and 63 deletions
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src/board.hpp
+37 -36
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@@ -68,57 +68,58 @@ enum {
typedef struct {
std::string manufacturer;
std::string cable_name; /*! provide name of one entry in cable_list */
std::string fpga_part; /*! provide full fpga model name with package */
uint16_t reset_pin; /*! reset pin value */
uint16_t done_pin; /*! done pin value */
uint16_t mode; /*! communication type (JTAG or SPI) */
jtag_pins_conf_t jtag_pins_config; /*! for bitbang, provide struct with pins value */
spi_pins_conf_t spi_pins_config; /*! for SPI, provide struct with pins value */
} target_cable_t;
} target_board_t;
#define JTAG_BOARD(_name, _cable, _rst, _done) \
{_name, {"", _cable, _rst, _done, COMM_JTAG, {}, {}}}
#define JTAG_BITBANG_BOARD(_name, _cable, _rst, _done, _tms, _tck, _tdi, _tdo) \
{_name, {"", _cable, _rst, _done, COMM_JTAG, { _tms, _tck, _tdi, _tdo }, {}}}
#define JTAG_BOARD(_name, _fpga_part, _cable, _rst, _done) \
{_name, {"", _cable, _fpga_part, _rst, _done, COMM_JTAG, {}, {}}}
#define JTAG_BITBANG_BOARD(_name, _fpga_part, _cable, _rst, _done, _tms, _tck, _tdi, _tdo) \
{_name, {"", _cable, _fpga_part, _rst, _done, COMM_JTAG, { _tms, _tck, _tdi, _tdo }, {}}}
#define SPI_BOARD(_name, _manufacturer, _cable, _rst, _done, _cs, _sck, _si, _so, _holdn, _wpn) \
{_name, {_manufacturer, _cable, _rst, _done, COMM_SPI, {}, \
{_name, {_manufacturer, _cable, "", _rst, _done, COMM_SPI, {}, \
{_cs, _sck, _so, _si, _holdn, _wpn}}}
static std::map <std::string, target_cable_t> board_list = {
JTAG_BOARD("acornCle215", "", 0, 0),
JTAG_BOARD("alchitry_au", "ft2232", 0, 0),
JTAG_BOARD("arty", "digilent", 0, 0),
JTAG_BOARD("nexysVideo", "digilent_b", 0, 0),
JTAG_BOARD("kc705", "digilent", 0, 0),
JTAG_BOARD("colorlight", "", 0, 0),
JTAG_BOARD("crosslinknx_evn", "ft2232", 0, 0),
JTAG_BOARD("cyc1000", "ft2232", 0, 0),
JTAG_BOARD("de0", "usb-blaster",0, 0),
JTAG_BOARD("de0nano", "usb-blaster",0, 0),
JTAG_BOARD("ecp5_evn", "ft2232", 0, 0),
SPI_BOARD("fireant", "efinix", "ft232",
static std::map <std::string, target_board_t> board_list = {
JTAG_BOARD("acornCle215", "xc7a200tsbg484", "", 0, 0),
JTAG_BOARD("alchitry_au", "xc7a35tftg256", "ft2232", 0, 0),
JTAG_BOARD("arty", "xc7a35tcsg324", "digilent", 0, 0),
JTAG_BOARD("nexysVideo", "xc7a200tsbg484", "digilent_b", 0, 0),
JTAG_BOARD("kc705", "", "digilent", 0, 0),
JTAG_BOARD("colorlight", "", "", 0, 0),
JTAG_BOARD("crosslinknx_evn", "", "ft2232", 0, 0),
JTAG_BOARD("cyc1000", "", "ft2232", 0, 0),
JTAG_BOARD("de0", "", "usb-blaster",0, 0),
JTAG_BOARD("de0nano", "", "usb-blaster",0, 0),
JTAG_BOARD("ecp5_evn", "", "ft2232", 0, 0),
SPI_BOARD("fireant", "efinix", "ft232",
DBUS4, DBUS5, DBUS3, DBUS0, DBUS1, DBUS2, DBUS6, 0),
/* most ice40 boards uses the same pinout */
SPI_BOARD("ice40_generic", "lattice", "ft2232",
SPI_BOARD("ice40_generic", "lattice", "ft2232",
DBUS7, DBUS6,
DBUS4, DBUS0, DBUS1, DBUS2,
0, 0),
JTAG_BOARD("machXO2EVN", "ft2232", 0, 0),
JTAG_BOARD("machXO3SK", "ft2232", 0, 0),
JTAG_BOARD("machXO3EVN", "ft2232", 0, 0),
JTAG_BOARD("licheeTang", "anlogicCable", 0, 0),
JTAG_BOARD("machXO2EVN", "", "ft2232", 0, 0),
JTAG_BOARD("machXO3SK", "", "ft2232", 0, 0),
JTAG_BOARD("machXO3EVN", "", "ft2232", 0, 0),
JTAG_BOARD("licheeTang", "", "anlogicCable", 0, 0),
/* left for backward compatibility, use tec0117 instead */
JTAG_BOARD("littleBee", "ft2232", 0, 0),
JTAG_BOARD("spartanEdgeAccelBoard", "",0, 0),
JTAG_BOARD("pipistrello", "ft2232", 0, 0),
JTAG_BOARD("qmtechCycloneV", "", 0, 0),
JTAG_BOARD("runber", "ft232", 0, 0),
JTAG_BOARD("tangnano", "ft2232", 0, 0),
JTAG_BOARD("tec0117", "ft2232", 0, 0),
JTAG_BITBANG_BOARD("ulx2s", "ft232RL", 0, 0, FT232RL_RI, FT232RL_DSR, FT232RL_CTS, FT232RL_DCD),
JTAG_BITBANG_BOARD("ulx3s", "ft231X", 0, 0, FT232RL_DCD, FT232RL_DSR, FT232RL_RI, FT232RL_CTS),
JTAG_BOARD("ecpix5", "ecpix5-debug", 0, 0),
JTAG_BOARD("xtrx", "" , 0, 0),
SPI_BOARD("xyloni_spi", "efinix", "efinix_spi",
JTAG_BOARD("littleBee", "", "ft2232", 0, 0),
JTAG_BOARD("spartanEdgeAccelBoard", "", "",0, 0),
JTAG_BOARD("pipistrello", "", "ft2232", 0, 0),
JTAG_BOARD("qmtechCycloneV", "", "", 0, 0),
JTAG_BOARD("runber", "", "ft232", 0, 0),
JTAG_BOARD("tangnano", "", "ft2232", 0, 0),
JTAG_BOARD("tec0117", "", "ft2232", 0, 0),
JTAG_BITBANG_BOARD("ulx2s", "", "ft232RL", 0, 0, FT232RL_RI, FT232RL_DSR, FT232RL_CTS, FT232RL_DCD),
JTAG_BITBANG_BOARD("ulx3s", "", "ft231X", 0, 0, FT232RL_DCD, FT232RL_DSR, FT232RL_RI, FT232RL_CTS),
JTAG_BOARD("ecpix5", "", "ecpix5-debug", 0, 0),
JTAG_BOARD("xtrx", "xc7a50tcpg236", "" , 0, 0),
SPI_BOARD("xyloni_spi", "efinix", "efinix_spi",
DBUS4 | DBUS7, DBUS5, DBUS3, DBUS0, DBUS1, DBUS2, DBUS6, 0),
};
src/main.cpp
+13 -4
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@@ -62,6 +62,7 @@ struct arguments {
bool is_list_command;
bool spi;
string file_type;
string fpga_part;
};
int parse_opt(int argc, char **argv, struct arguments *args, jtag_pins_conf_t *pins_config);
@@ -71,12 +72,13 @@ void displaySupported(const struct arguments &args);
int main(int argc, char **argv)
{
cable_t cable;
target_cable_t *board = NULL;
target_board_t *board = NULL;
jtag_pins_conf_t pins_config = {0, 0, 0, 0};
/* command line args. */
struct arguments args = {0, false, false, 0, "", "", "-", "", -1, 6000000, "-",
false, false, false, false, Device::WR_SRAM, false, false, ""};
false, false, false, false, Device::WR_SRAM, false, false, "",
""};
/* parse arguments */
try {
if (parse_opt(argc, argv, &args, &pins_config))
@@ -122,6 +124,12 @@ int main(int argc, char **argv)
cout << "Board default cable overridden with " << args.cable << endl;
}
}
/* Xilinx only: to write flash exact fpga model must be provided */
if (!board->fpga_part.empty() && !args.fpga_part.empty())
printInfo("Board default fpga part overridden with " + args.fpga_part);
else if (!board->fpga_part.empty() && args.fpga_part.empty())
args.fpga_part = board->fpga_part;
}
if (args.cable[0] == '-') { /* if no board and no cable */
@@ -269,7 +277,7 @@ int main(int argc, char **argv)
try {
if (fab == "xilinx") {
fpga = new Xilinx(jtag, args.bit_file, args.file_type,
args.prg_type, args.verbose);
args.prg_type, args.fpga_part, args.verbose);
} else if (fab == "altera") {
fpga = new Altera(jtag, args.bit_file, args.file_type,
args.verbose);
@@ -370,6 +378,7 @@ int parse_opt(int argc, char **argv, struct arguments *args, jtag_pins_conf_t *p
cxxopts::value<bool>(args->detect))
("file-type", "provides file type instead of let's deduced by using extension",
cxxopts::value<string>(args->file_type))
("fpga-part", "fpga model flavor + package", cxxopts::value<string>(args->fpga_part))
("freq", "jtag frequency (Hz)", cxxopts::value<string>(freqo))
("f,write-flash",
"write bitstream in flash (default: false, only for Gowin and ECP5 devices)")
@@ -543,7 +552,7 @@ void displaySupported(const struct arguments &args)
printSuccess(t.str());
for (auto b = board_list.begin(); b != board_list.end(); b++) {
stringstream ss;
target_cable_t c = (*b).second;
target_board_t c = (*b).second;
ss << setw(15) << left << (*b).first << " " << c.cable_name;
printInfo(ss.str());
}
src/xilinx.cpp
+12 -3
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@@ -1,5 +1,6 @@
#include <iostream>
#include <stdexcept>
#include <string>
#include "jtag.hpp"
#include "bitparser.hpp"
@@ -15,8 +16,9 @@
Xilinx::Xilinx(Jtag *jtag, const std::string &filename,
const std::string &file_type,
Device::prog_type_t prg_type, int8_t verbose):
Device(jtag, filename, file_type, verbose)
Device::prog_type_t prg_type,
std::string device_package, int8_t verbose):
Device(jtag, filename, file_type, verbose),_device_package(device_package)
{
if (!_file_extension.empty()) {
if (_file_extension == "mcs") {
@@ -123,9 +125,16 @@ void Xilinx::program(unsigned int offset)
void Xilinx::program_spi(ConfigBitstreamParser * bit, unsigned int offset)
{
if (_device_package.empty()) {
printError("Can't program SPI flash: missing device-package information");
return;
}
// DATA_DIR is defined at compile time.
std::string bitname = DATA_DIR "/openFPGALoader/spiOverJtag_";
bitname += fpga_list[idCode()].model + ".bit";
bitname += _device_package + ".bit";
std::cout << "use: " << bitname << std::endl;
/* first: load spi over jtag */
try {
src/xilinx.hpp
+5 -1
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@@ -12,7 +12,8 @@ class Xilinx: public Device, SPIInterface {
public:
Xilinx(Jtag *jtag, const std::string &filename,
const std::string &file_type,
Device::prog_type_t prg_type, int8_t verbose);
Device::prog_type_t prg_type,
std::string device_package, int8_t verbose);
~Xilinx();
void program(unsigned int offset = 0) override;
@@ -27,6 +28,9 @@ class Xilinx: public Device, SPIInterface {
int spi_put(uint8_t *tx, uint8_t *rx, uint32_t len) override;
int spi_wait(uint8_t cmd, uint8_t mask, uint8_t cond,
uint32_t timeout, bool verbose = false) override;
private:
std::string _device_package;
};
#endif