366 lines
9.5 KiB
C++
366 lines
9.5 KiB
C++
#include <iostream>
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#include <stdexcept>
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#include <string>
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#include "jtag.hpp"
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#include "bitparser.hpp"
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#include "configBitstreamParser.hpp"
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#include "mcsParser.hpp"
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#include "spiFlash.hpp"
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#include "rawParser.hpp"
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#include "display.hpp"
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#include "xilinx.hpp"
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#include "part.hpp"
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#include "progressBar.hpp"
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Xilinx::Xilinx(Jtag *jtag, const std::string &filename,
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const std::string &file_type,
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Device::prog_type_t prg_type,
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std::string device_package, int8_t verbose):
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Device(jtag, filename, file_type, verbose),_device_package(device_package)
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{
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if (!_file_extension.empty()) {
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if (_file_extension == "mcs") {
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_mode = Device::SPI_MODE;
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} else if (_file_extension == "bit" || _file_extension == "bin") {
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if (prg_type == Device::WR_SRAM)
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_mode = Device::MEM_MODE;
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else
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_mode = Device::SPI_MODE;
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} else {
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_mode = Device::SPI_MODE;
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}
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}
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}
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Xilinx::~Xilinx() {}
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#define USER1 0x02
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#define CFG_IN 0x05
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#define USERCODE 0x08
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#define IDCODE 0x09
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#define ISC_ENABLE 0x10
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#define JPROGRAM 0x0B
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#define JSTART 0x0C
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#define JSHUTDOWN 0x0D
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#define ISC_DISABLE 0x16
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#define BYPASS 0x3f
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void Xilinx::reset()
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{
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_jtag->shiftIR(JSHUTDOWN, 6);
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_jtag->shiftIR(JPROGRAM, 6);
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_jtag->set_state(Jtag::RUN_TEST_IDLE);
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_jtag->toggleClk(10000*12);
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_jtag->set_state(Jtag::RUN_TEST_IDLE);
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_jtag->toggleClk(2000);
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_jtag->shiftIR(BYPASS, 6);
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_jtag->set_state(Jtag::RUN_TEST_IDLE);
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_jtag->toggleClk(2000);
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}
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int Xilinx::idCode()
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{
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unsigned char tx_data[4]= {0x00, 0x00, 0x00, 0x00};
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unsigned char rx_data[4];
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_jtag->go_test_logic_reset();
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_jtag->shiftIR(IDCODE, 6);
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_jtag->shiftDR(tx_data, rx_data, 32);
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return ((rx_data[0] & 0x000000ff) |
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((rx_data[1] << 8) & 0x0000ff00) |
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((rx_data[2] << 16) & 0x00ff0000) |
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((rx_data[3] << 24) & 0xff000000));
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}
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void Xilinx::program(unsigned int offset)
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{
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ConfigBitstreamParser *bit;
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bool reverse = false;
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/* nothing to do */
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if (_mode == Device::NONE_MODE)
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return;
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if (_mode == Device::MEM_MODE)
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reverse = true;
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printInfo("Open file ", false);
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try {
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if (_file_extension == "bit")
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bit = new BitParser(_filename, reverse, _verbose);
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else if (_file_extension == "mcs")
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bit = new McsParser(_filename, reverse, _verbose);
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else
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bit = new RawParser(_filename, reverse);
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} catch (std::exception &e) {
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printError("FAIL");
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return;
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}
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printSuccess("DONE");
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printInfo("Parse file ", false);
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if (bit->parse() == EXIT_FAILURE) {
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printError("FAIL");
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delete bit;
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return;
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} else {
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printSuccess("DONE");
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}
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if (_verbose)
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bit->displayHeader();
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if (_mode == Device::SPI_MODE) {
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program_spi(bit, offset);
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reset();
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} else {
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program_mem(bit);
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}
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delete bit;
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}
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void Xilinx::program_spi(ConfigBitstreamParser * bit, unsigned int offset)
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{
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if (_device_package.empty()) {
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printError("Can't program SPI flash: missing device-package information");
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return;
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}
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// DATA_DIR is defined at compile time.
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std::string bitname = DATA_DIR "/openFPGALoader/spiOverJtag_";
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bitname += _device_package + ".bit";
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std::cout << "use: " << bitname << std::endl;
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/* first: load spi over jtag */
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try {
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BitParser bridge(bitname, true, _verbose);
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bridge.parse();
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program_mem(&bridge);
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} catch (std::exception &e) {
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printError(e.what());
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throw std::runtime_error(e.what());
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}
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SPIFlash spiFlash(this, (_verbose ? 1 : (_quiet ? -1 : 0)));
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spiFlash.reset();
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spiFlash.read_id();
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spiFlash.read_status_reg();
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spiFlash.erase_and_prog(offset, bit->getData(), bit->getLength()/8);
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}
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void Xilinx::program_mem(ConfigBitstreamParser *bitfile)
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{
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if (_file_extension.empty()) return;
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std::cout << "load program" << std::endl;
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unsigned char tx_buf, rx_buf;
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/* comment TDI TMS TCK
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* 1: On power-up, place a logic 1 on the TMS,
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* and clock the TCK five times. This ensures X 1 5
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* starting in the TLR (Test-Logic-Reset) state.
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*/
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_jtag->go_test_logic_reset();
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/*
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* 2: Move into the RTI state. X 0 1
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* 3: Move into the SELECT-IR state. X 1 2
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* 4: Enter the SHIFT-IR state. X 0 2
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* 5: Start loading the JPROGRAM instruction, 01011(4) 0 5
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* LSB first:
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* 6: Load the MSB of the JPROGRAM instruction
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* when exiting SHIFT-IR, as defined in the 0 1 1
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* IEEE standard.
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* 7: Place a logic 1 on the TMS and clock the
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* TCK five times. This ensures starting in X 1 5
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* the TLR (Test-Logic-Reset) state.
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*/
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_jtag->shiftIR(JPROGRAM, 6);
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/* test */
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tx_buf = BYPASS;
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do {
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_jtag->shiftIR(&tx_buf, &rx_buf, 6);
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} while (!(rx_buf &0x01));
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/*
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* 8: Move into the RTI state. X 0 10,000(1)
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*/
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_jtag->set_state(Jtag::RUN_TEST_IDLE);
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_jtag->toggleClk(10000*12);
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/*
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* 9: Start loading the CFG_IN instruction,
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* LSB first: 00101 0 5
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* 10: Load the MSB of CFG_IN instruction when
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* exiting SHIFT-IR, as defined in the 0 1 1
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* IEEE standard.
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*/
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_jtag->shiftIR(CFG_IN, 6);
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/*
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* 11: Enter the SELECT-DR state. X 1 2
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*/
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_jtag->set_state(Jtag::SELECT_DR_SCAN);
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/*
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* 12: Enter the SHIFT-DR state. X 0 2
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*/
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_jtag->set_state(Jtag::SHIFT_DR);
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/*
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* 13: Shift in the FPGA bitstream. Bitn (MSB)
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* is the first bit in the bitstream(2). bit1...bitn 0 (bits in bitstream)-1
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* 14: Shift in the last bit of the bitstream.
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* Bit0 (LSB) shifts on the transition to bit0 1 1
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* EXIT1-DR.
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*/
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/* GGM: TODO */
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int byte_length = bitfile->getLength() / 8;
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uint8_t *data = bitfile->getData();
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int tx_len, tx_end;
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int burst_len = byte_length / 100;
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ProgressBar progress("Flash SRAM", byte_length, 50, _quiet);
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for (int i=0; i < byte_length; i+=burst_len) {
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if (i + burst_len > byte_length) {
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tx_len = (byte_length - i) * 8;
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tx_end = 1;
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} else {
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tx_len = burst_len * 8;
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tx_end = 0;
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}
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_jtag->read_write(data+i, NULL, tx_len, tx_end);
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_jtag->flush();
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progress.display(i);
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}
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progress.done();
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/*
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* 15: Enter UPDATE-DR state. X 1 1
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*/
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_jtag->set_state(Jtag::UPDATE_DR);
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/*
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* 16: Move into RTI state. X 0 1
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*/
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_jtag->set_state(Jtag::RUN_TEST_IDLE);
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/*
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* 17: Enter the SELECT-IR state. X 1 2
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* 18: Move to the SHIFT-IR state. X 0 2
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* 19: Start loading the JSTART instruction
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* (optional). The JSTART instruction 01100 0 5
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* initializes the startup sequence.
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* 20: Load the last bit of the JSTART instruction. 0 1 1
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* 21: Move to the UPDATE-IR state. X 1 1
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*/
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_jtag->shiftIR(JSTART, 6, Jtag::UPDATE_IR);
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/*
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* 22: Move to the RTI state and clock the
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* startup sequence by applying a minimum X 0 2000
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* of 2000 clock cycles to the TCK.
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*/
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_jtag->set_state(Jtag::RUN_TEST_IDLE);
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_jtag->toggleClk(2000);
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/*
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* 23: Move to the TLR state. The device is
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* now functional. X 1 3
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*/
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_jtag->go_test_logic_reset();
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}
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/*
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* jtag : jtag interface
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* cmd : opcode for SPI flash
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* tx : buffer to send
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* rx : buffer to fill
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* len : number of byte to send/receive (cmd not comprise)
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* so to send only a cmd set len to 0 (or omit this param)
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*/
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int Xilinx::spi_put(uint8_t cmd,
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uint8_t *tx, uint8_t *rx, uint32_t len)
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{
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int xfer_len = len + 1 + ((rx == NULL) ? 0 : 1);
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uint8_t jtx[xfer_len];
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jtx[0] = McsParser::reverseByte(cmd);
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/* uint8_t jtx[xfer_len] = {McsParser::reverseByte(cmd)}; */
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uint8_t jrx[xfer_len];
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if (tx != NULL) {
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for (uint32_t i=0; i < len; i++)
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jtx[i+1] = McsParser::reverseByte(tx[i]);
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}
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/* addr BSCAN user1 */
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_jtag->shiftIR(USER1, 6);
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/* send first already stored cmd,
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* in the same time store each byte
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* to next
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*/
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_jtag->shiftDR(jtx, (rx == NULL)? NULL: jrx, 8*xfer_len);
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if (rx != NULL) {
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for (uint32_t i=0; i < len; i++)
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rx[i] = McsParser::reverseByte(jrx[i+1] >> 1) | (jrx[i+2] & 0x01);
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}
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return 0;
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}
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int Xilinx::spi_put(uint8_t *tx, uint8_t *rx, uint32_t len)
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{
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int xfer_len = len + ((rx == NULL) ? 0 : 1);
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uint8_t jtx[xfer_len];
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uint8_t jrx[xfer_len];
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if (tx != NULL) {
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for (uint32_t i=0; i < len; i++)
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jtx[i] = McsParser::reverseByte(tx[i]);
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}
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/* addr BSCAN user1 */
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_jtag->shiftIR(USER1, 6);
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/* send first already stored cmd,
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* in the same time store each byte
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* to next
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*/
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_jtag->shiftDR(jtx, (rx == NULL)? NULL: jrx, 8*xfer_len);
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if (rx != NULL) {
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for (uint32_t i=0; i < len; i++)
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rx[i] = McsParser::reverseByte(jrx[i] >> 1) | (jrx[i+1] & 0x01);
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}
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return 0;
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}
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int Xilinx::spi_wait(uint8_t cmd, uint8_t mask, uint8_t cond,
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uint32_t timeout, bool verbose)
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{
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uint8_t rx[2];
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uint8_t dummy[2];
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uint8_t tmp;
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uint8_t tx = McsParser::reverseByte(cmd);
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uint32_t count = 0;
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_jtag->shiftIR(USER1, 6, Jtag::UPDATE_IR);
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_jtag->set_state(Jtag::SHIFT_DR);
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_jtag->read_write(&tx, NULL, 8, 0);
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do {
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_jtag->read_write(dummy, rx, 8*2, 0);
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tmp = (McsParser::reverseByte(rx[0]>>1)) | (0x01 & rx[1]);
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count++;
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if (count == timeout){
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printf("timeout: %x %x %x\n", tmp, rx[0], rx[1]);
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break;
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}
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if (tmp & ~0x3) {
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printf("Error: rx %x %x %x\n", tmp, McsParser::reverseByte(rx[0]), rx[1]);
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count = timeout;
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break;
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}
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if (verbose) {
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printf("%x %x %x %u\n", tmp, mask, cond, count);
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}
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} while ((tmp & mask) != cond);
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_jtag->go_test_logic_reset();
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if (count == timeout) {
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printf("%x\n", tmp);
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std::cout << "wait: Error" << std::endl;
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return -ETIME;
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} else {
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return 0;
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}
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}
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