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part: Zynq XC7Z045

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Gwenhael Goavec-Merou 2022-03-10 18:53:12 +01:00
parent 74eb812c6d
commit 6ba1968952
1 changed files with 1 additions and 0 deletions
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src/part.hpp
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@ -54,6 +54,7 @@ static std::map <int, fpga_model> fpga_list = {
{0x03722093, {"xilinx", "zynq", "xc7z010", 6}}, {0x03722093, {"xilinx", "zynq", "xc7z010", 6}},
{0x03727093, {"xilinx", "zynq", "xc7z020", 6}}, {0x03727093, {"xilinx", "zynq", "xc7z020", 6}},
{0x23731093, {"xilinx", "zynq", "xc7z045", 6}},
/* When powering a zynq ultrascale+ MPSoC, PL Tap and ARM dap /* When powering a zynq ultrascale+ MPSoC, PL Tap and ARM dap
* are disabled and only PS tap with a specific IDCODE is seen. * are disabled and only PS tap with a specific IDCODE is seen.