From 6ba1968952e52fe7658c0f4afcc98488002621aa Mon Sep 17 00:00:00 2001
From: Gwenhael Goavec-Merou <gwenhael.goavec-merou@trabucayre.com>
Date: Thu, 10 Mar 2022 18:53:12 +0100
Subject: [PATCH] part: Zynq XC7Z045

---
 src/part.hpp | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/part.hpp b/src/part.hpp
index 445ce40..6032fa5 100644
--- a/src/part.hpp
+++ b/src/part.hpp
@@ -54,6 +54,7 @@ static std::map <int, fpga_model> fpga_list = {
 
 	{0x03722093, {"xilinx", "zynq",     "xc7z010", 6}},
 	{0x03727093, {"xilinx", "zynq",     "xc7z020", 6}},
+	{0x23731093, {"xilinx", "zynq",     "xc7z045", 6}},
 
 	/* When powering a zynq ultrascale+ MPSoC, PL Tap and ARM dap
 	 * are disabled and only PS tap with a specific IDCODE is seen.