From 50c8d54791dbbe436c23d9954fd4ebbe9d6653c0 Mon Sep 17 00:00:00 2001
From: Gwenhael Goavec-Merou <gwenhael.goavec-merou@trabucayre.com>
Date: Sun, 16 Feb 2020 15:03:55 +0100
Subject: [PATCH] xilinx: fix a random segfault and add progress status for
 load in sram

---
 src/xilinx.cpp | 22 +++++++++++++++++++++-
 1 file changed, 21 insertions(+), 1 deletion(-)

diff --git a/src/xilinx.cpp b/src/xilinx.cpp
index eac2477..cec8f1f 100644
--- a/src/xilinx.cpp
+++ b/src/xilinx.cpp
@@ -8,6 +8,7 @@
 
 #include "xilinx.hpp"
 #include "part.hpp"
+#include "progressBar.hpp"
 
 Xilinx::Xilinx(FtdiJtag *jtag, std::string filename, bool verbose):
 	Device(jtag, filename, verbose)
@@ -153,7 +154,26 @@ void Xilinx::program_mem(BitParser &bitfile)
 	 *     EXIT1-DR.
 	 */
 	/* GGM: TODO */
-	_jtag->shiftDR(bitfile.getData(), NULL, 8*bitfile.getLength());
+	int byte_length = bitfile.getLength();
+	uint8_t *data = bitfile.getData();
+	int tx_len, tx_end;
+	int burst_len = byte_length / 100;
+
+	ProgressBar progress("Flash SRAM", byte_length, 50);
+
+	for (int i=0; i < byte_length; i+=burst_len) {
+		if (i + burst_len > byte_length) {
+			tx_len = (byte_length - i) * 8;
+			tx_end = 1;
+		} else {
+			tx_len = burst_len * 8;
+			tx_end = 0;
+		}
+		_jtag->read_write(data+i, NULL, tx_len, tx_end);
+		_jtag->flush();
+		progress.display(i);
+	}
+	progress.done();
 	/*
 	 * 15: Enter UPDATE-DR state.                         X     1   1
 	 */