From d188314ae329efe6dce186a0d14cbec57c6bd84d Mon Sep 17 00:00:00 2001 From: TG Date: Wed, 9 Feb 2022 17:21:19 +0100 Subject: [PATCH 1/4] part: add altera 5CSEMA5 (cyclone V Soc) --- src/part.hpp | 1 + 1 file changed, 1 insertion(+) diff --git a/src/part.hpp b/src/part.hpp index df8d8a6..422aee6 100644 --- a/src/part.hpp +++ b/src/part.hpp @@ -71,6 +71,7 @@ static std::map fpga_list = { {0x02b050dd, {"altera", "cyclone V", "5CEBA4", 10}}, {0x02d020dd, {"altera", "cyclone V Soc", "5CSEBA6", 10}}, {0x02d010dd, {"altera", "cyclone V Soc", "5CSEMA4", 10}}, + {0x02d120dd, {"altera", "cyclone V Soc", "5CSEMA5", 10}}, {0x00000001, {"efinix", "Trion", "T4/T8", 4}}, {0x00210a79, {"efinix", "Trion", "T8QFP144/T13/T20", 4}}, From 5aa34c6364659fbe0f5f97d9597f733a03f3a9b1 Mon Sep 17 00:00:00 2001 From: TG Date: Wed, 9 Feb 2022 17:22:38 +0100 Subject: [PATCH 2/4] board: add Terasic DE1-SoC board --- src/board.hpp | 1 + 1 file changed, 1 insertion(+) diff --git a/src/board.hpp b/src/board.hpp index 766c934..61630ef 100644 --- a/src/board.hpp +++ b/src/board.hpp @@ -126,6 +126,7 @@ static std::map board_list = { JTAG_BOARD("de0nano", "ep4ce2217", "usb-blaster",0, 0, CABLE_DEFAULT), JTAG_BOARD("de0nanoSoc", "", "usb-blasterII",0, 0, CABLE_DEFAULT), JTAG_BOARD("de10nano", "", "usb-blasterII",0, 0, CABLE_DEFAULT), + JTAG_BOARD("de1Soc", "5CSEMA5", "usb-blasterII",0, 0, CABLE_DEFAULT), JTAG_BOARD("ecp5_evn", "", "ft2232", 0, 0, CABLE_DEFAULT), SPI_BOARD("fireant", "efinix", "ft232", DBUS4, DBUS5, 0, DBUS3, DBUS0, DBUS1, DBUS2, DBUS6, 0, CABLE_DEFAULT), From 89e1fb89d2a33c1a2eba2fbb6ab988713a86c959 Mon Sep 17 00:00:00 2001 From: TG Date: Wed, 9 Feb 2022 18:11:39 +0100 Subject: [PATCH 3/4] doc: add Cyclone V SE SoC FPGA to the supported parts --- doc/FPGAs.yml | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/doc/FPGAs.yml b/doc/FPGAs.yml index e964cd2..97d6968 100644 --- a/doc/FPGAs.yml +++ b/doc/FPGAs.yml @@ -81,6 +81,15 @@ Intel: Memory: OK Flash: OK + - Description: Cyclone V SE SoC + Model: + - 5CSEBA6 + - 5CSEMA4 + - 5CSEMA5 + URL: https://www.intel.com/content/www/us/en/products/programmable/fpga/cyclone-v.html + Memory: OK + Flash: NT + - Description: Cyclone 10 LP Model: 10CL025 URL: https://www.intel.com/content/www/us/en/products/programmable/fpga/cyclone-10.html From 94ca103360cf90de2d219be8b2e9399b8a48094c Mon Sep 17 00:00:00 2001 From: TG Date: Wed, 9 Feb 2022 18:16:40 +0100 Subject: [PATCH 4/4] doc: add reference to the Terasic DE1-SoC board --- doc/boards.yml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/doc/boards.yml b/doc/boards.yml index 94a036a..4fa129d 100644 --- a/doc/boards.yml +++ b/doc/boards.yml @@ -170,6 +170,12 @@ FPGA: Cyclone V SoC 5CSEBA6U23I7 Memory: OK +- ID: de1Soc + Description: Terasic DE1-SoC + URL: https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=167&No=836 + FPGA: Cyclone V SoC 5CSEMA5F31C6 + Memory: OK + - ID: ecp5_evn Description: Lattice ECP5 5G Evaluation Board URL: https://www.latticesemi.com/en/Products/DevelopmentBoardsAndKits/ECP5EvaluationBoard