From d4e8eef676e1041c705d079bb3e4b15b16ac8950 Mon Sep 17 00:00:00 2001 From: jonathan kimmitt Date: Mon, 21 Feb 2022 08:11:57 +0000 Subject: [PATCH 1/3] Add board and cable defaults for genesys2 --- doc/boards.yml | 7 +++++++ spiOverJtag/spiOverJtag_xc7k325tffg900.bit.gz | Bin 0 -> 12544 bytes src/board.hpp | 1 + 3 files changed, 8 insertions(+) create mode 100644 spiOverJtag/spiOverJtag_xc7k325tffg900.bit.gz diff --git a/doc/boards.yml b/doc/boards.yml index 62db7db..43340e9 100644 --- a/doc/boards.yml +++ b/doc/boards.yml @@ -361,6 +361,13 @@ Memory: OK Flash: OK +- ID: genesys2 + Description: Digilent Kintex7 Evaluation Board + URL: https://digilent.com/reference/programmable-logic/genesys-2/start + FPGA: Kintex xc7k325tffg900 + Memory: OK + Flash: OK + - ID: runber Description: SeeedStudio Gowin RUNBER URL: https://www.seeedstudio.com/Gowin-RUNBER-Development-Board-p-4779.html diff --git a/spiOverJtag/spiOverJtag_xc7k325tffg900.bit.gz b/spiOverJtag/spiOverJtag_xc7k325tffg900.bit.gz new file mode 100644 index 0000000000000000000000000000000000000000..4df3112576e7e5ee5dfbf990fd83b8677f6602b9 GIT binary patch literal 12544 zcmeI$eKeG59|!O|u_^NM*poR8tF7HUD5D()gAq$nrjXYruj5@ZLJX6cXg6g=D>WLz zpqlkE7=yfojapNUEu$$iVlWslOC^KMX3uIn=Q;b|?m18AT-QI>b?)zV{m$?H-1q&@ zt(7J(-%3{Yht@|ELJyw`Jb56-FW4s@Zyb*N#waEzC>Ujo()SOIfhM_)2aZ|6pqJ#Q zXDd^w!yA=CQ_zXkrF1*z)Pi)>X9p3cdfP*uW%KTQ`xE7iA!^GVN_vJreg@v|)fHAY zq(B-lSgy!ZcO76E1FfME)3LvkaLV%Gb+RxK6q;V+0E9l94H8K-keqZC7cKHe1*yPPR zm2=)Fz0R8*Q?dR{vB`Q68lto#30CwWO%+K<`28v&+rkW=NVe4BB%H#mZ~`oZ{ho+V z%>wib1U>-)1Ad;6r@E^m2Ti%~MyuqaZ&W#N-D=-Wze-WDvIpVCN(H*j{30VZoBS=b zHGL5N_!@`Kt{FUPTXUn@h#47Sa)^TENeyFV6~b>SQ5K0};)Fbh(Y;tGhe4)uZZAT$O9yGz zs!1Li3KMZxdAQDI5M(_jdcWHm84K~!g|cg#p=U04so|S&s(s0nggtN;SN%ise&L4l zxO=XiZ9!3m+-fi4Nx_@(fAiDREo-RpvBkhyERvL2;M64#x$zP;TCkB`AD5%ypZ)O6 zL(ds@5!+L5c-OzEH?Sv3~bxmqm*%%AId;|i2i4Byh89!Ha&r|qmu4-y}(JC z@Yl^i5T#@@UXU-u?Aw;<{qWw4`|=+huZ(JFx%!KXi>91#{)_LJ-4SV}<10tEcNfeV z!1$Ye0$G}O4%vmySjlCd(!Hg&cJLN&+i=`3Gje5rJ)1uxO8MJSmUw>j5*_mR;jRAK zf%mg-p2o5|{ffEG*U)hT;l_`We|FhA+A9&($C{2TjO;5_GlOxbmWg$jybj!63KQGE zaGWTG^{tdVu9w&@?Cc#ZJzK1#b&lC>;^K^&N8Wgadu>N8T6$|_#=6H#`YMwiMI@06 zCGIZ_s5398y%RaB}*>nm=Hq^>-#E2+#hquBUnAqVL;^b@0oF#9>>Zhe*@!dZqCRn7a<> z{``tQS|BE)y-qsPF*90|M{M64wu=^TA#M&2)3U+_s4*j@NQ;4vD1Yrv_8XVunwwV@b>*94xK$YOKgC-p)hDhziZ{1Zu+ktoqC_1DOHaK63wbz9 zZ_^vk=hn6hCa})^w7M_!9l2OV9CL+PMT2IGJt0O}O^=O;kB}NEU;YfH&f3<1fK8Z&| zNpx*r`o(c~*~YXo-0TR-X>$5&^j8+~%_b?5}Fesat% zA38srwXx39K}AkD*C~5i2I?DUYmEkVYO9ev)iZnBlE%v_LTsJ=&2@IFRc{*dZIAk! zkM^H^89_B500e*l5C8%|00;m9An%e2tyxWAg zK$OUflJwHL%ruMMdC%2e4Y|%VZ#2S3ti5 D&yx`P literal 0 HcmV?d00001 diff --git a/src/board.hpp b/src/board.hpp index da7b0e7..2dca419 100644 --- a/src/board.hpp +++ b/src/board.hpp @@ -162,6 +162,7 @@ static std::map board_list = { JTAG_BOARD("qmtechCycloneIV", "ep4ce1523", "", 0, 0, CABLE_DEFAULT), JTAG_BOARD("qmtechCycloneV", "5ce223", "", 0, 0, CABLE_DEFAULT), JTAG_BOARD("qmtechKintex7", "xc7k325tffg676", "", 0, 0, CABLE_DEFAULT), + JTAG_BOARD("genesys2", "xc7k325tffg900", "digilent_b", 0, 0, CABLE_MHZ(6)), JTAG_BOARD("runber", "", "ft232", 0, 0, CABLE_DEFAULT), JTAG_BOARD("tangnano", "", "ch552_jtag", 0, 0, CABLE_DEFAULT), JTAG_BOARD("tangnano1k", "", "ft2232", 0, 0, CABLE_DEFAULT), From 3cfdfb1856ca941cdc3d9faa56bd51006f7ec210 Mon Sep 17 00:00:00 2001 From: Torsten Reuschel <89043237+unbtorsten@users.noreply.github.com> Date: Mon, 21 Feb 2022 23:05:37 -0400 Subject: [PATCH 2/3] Update board.hpp Use default cable. This is equivalent to 6MHz setting, albeit more versatile. --- src/board.hpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/board.hpp b/src/board.hpp index 2dca419..622adb6 100644 --- a/src/board.hpp +++ b/src/board.hpp @@ -162,7 +162,7 @@ static std::map board_list = { JTAG_BOARD("qmtechCycloneIV", "ep4ce1523", "", 0, 0, CABLE_DEFAULT), JTAG_BOARD("qmtechCycloneV", "5ce223", "", 0, 0, CABLE_DEFAULT), JTAG_BOARD("qmtechKintex7", "xc7k325tffg676", "", 0, 0, CABLE_DEFAULT), - JTAG_BOARD("genesys2", "xc7k325tffg900", "digilent_b", 0, 0, CABLE_MHZ(6)), + JTAG_BOARD("genesys2", "xc7k325tffg900", "digilent_b", 0, 0, CABLE_DEFAULT), JTAG_BOARD("runber", "", "ft232", 0, 0, CABLE_DEFAULT), JTAG_BOARD("tangnano", "", "ch552_jtag", 0, 0, CABLE_DEFAULT), JTAG_BOARD("tangnano1k", "", "ft2232", 0, 0, CABLE_DEFAULT), From 255d90b7505e8e76e404ff00e6bb3b8d1a0cb6e7 Mon Sep 17 00:00:00 2001 From: unbtorsten Date: Tue, 22 Feb 2022 13:01:02 -0400 Subject: [PATCH 3/3] add spiOverJtag build process for Kintex7 ffg900-2 packages, amend and extend build process for ff676-1 package --- spiOverJtag/Makefile | 3 ++- spiOverJtag/build.py | 5 +++++ spiOverJtag/constr_xc7k_ffg900.xdc | 10 ++++++++++ spiOverJtag/xilinx_spiOverJtag.tcl | 2 ++ 4 files changed, 19 insertions(+), 1 deletion(-) create mode 100644 spiOverJtag/constr_xc7k_ffg900.xdc diff --git a/spiOverJtag/Makefile b/spiOverJtag/Makefile index 3692db1..7cd5006 100644 --- a/spiOverJtag/Makefile +++ b/spiOverJtag/Makefile @@ -1,7 +1,8 @@ XILINX_PARTS := xc6slx16ftg256 xc6slx16csg324 xc6slx45csg324 xc6slx100fgg484 \ xc7a35tcpg236 xc7a35tcsg324 xc7a35tftg256 \ xc7a50tcpg236 xc7a75tfgg484 xc7a100tcsg324 xc7a100tfgg484 xc7a200tsbg484 \ - xc7s25csga324 xc7s50csga324 + xc7s25csga324 xc7s50csga324 \ + xc7k325tffg676 xc7k325tffg900 XILINX_BIT_FILES := $(addsuffix .bit.gz,$(addprefix spiOverJtag_, $(XILINX_PARTS))) ALTERA_PARTS := 10cl025256 ep4ce2217 ep4ce1523 5ce223 5ce423 diff --git a/spiOverJtag/build.py b/spiOverJtag/build.py index 7796130..8c2910d 100755 --- a/spiOverJtag/build.py +++ b/spiOverJtag/build.py @@ -35,6 +35,9 @@ elif subpart[0:2] == '5c': elif subpart == "xc7a": family = "Artix" tool = "vivado" +elif subpart == "xc7k": + family = "Kintex 7" + tool = "vivado" elif subpart == "xc7s": family = "Spartan 7" tool = "vivado" @@ -60,6 +63,8 @@ if tool in ["ise", "vivado"]: "xc7a100tfgg484" : "xc7a_fgg484", "xc7a200tsbg484" : "xc7a_sbg484", "xc7a200tfbg484" : "xc7a_fbg484", + "xc7k325tffg676" : "xc7k_ffg676", + "xc7k325tffg900" : "xc7k_ffg900", "xc7s25csga324" : "xc7s_csga324", "xc7s50csga324" : "xc7s_csga324" }[part] diff --git a/spiOverJtag/constr_xc7k_ffg900.xdc b/spiOverJtag/constr_xc7k_ffg900.xdc new file mode 100644 index 0000000..b76a60c --- /dev/null +++ b/spiOverJtag/constr_xc7k_ffg900.xdc @@ -0,0 +1,10 @@ +set_property CFGBVS VCCO [current_design] +set_property CONFIG_VOLTAGE 3.3 [current_design] +set_property BITSTREAM.CONFIG.SPI_BUSWIDTH {4} [current_design] + +set_property -dict {PACKAGE_PIN U19 IOSTANDARD LVTTL} [get_ports {csn}] +set_property -dict {PACKAGE_PIN P24 IOSTANDARD LVTTL} [get_ports {sdi_dq0}] +set_property -dict {PACKAGE_PIN R25 IOSTANDARD LVTTL} [get_ports {sdo_dq1}] +set_property -dict {PACKAGE_PIN R20 IOSTANDARD LVTTL} [get_ports {wpn_dq2}] +set_property -dict {PACKAGE_PIN R21 IOSTANDARD LVTTL} [get_ports {hldn_dq3}] + diff --git a/spiOverJtag/xilinx_spiOverJtag.tcl b/spiOverJtag/xilinx_spiOverJtag.tcl index 1a8d6ad..0777075 100644 --- a/spiOverJtag/xilinx_spiOverJtag.tcl +++ b/spiOverJtag/xilinx_spiOverJtag.tcl @@ -15,6 +15,7 @@ set grade [dict create \ xc7a100tfgg484 -2 \ xc7a200tsbg484 -1 \ xc7k325tffg676 -1 \ + xc7k325tffg900 -2 \ xc7s50csga324 -1 \ ] @@ -28,6 +29,7 @@ set pkg_name [dict create \ xc7a200tsbg484 xc7a_sbg484 \ xc7a200tfbg484 xc7a_fbg484 \ xc7k325tffg676 xc7k_ffg676 \ + xc7k325tffg900 xc7k_ffg900 \ xc7s50csga324 xc7s_csga324 \ ]