130 lines
3.7 KiB
Python
130 lines
3.7 KiB
Python
# -*- coding: utf-8 -*-
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from sys import path as sys_path
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from os.path import abspath
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from pathlib import Path
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from json import loads
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ROOT = Path(__file__).resolve().parent
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sys_path.insert(0, abspath("."))
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from data import (
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ReadBoardDataFromYAML,
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BoardDataToTable,
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ReadFPGADataFromYAML,
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FPGADataToTable,
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ReadCableDataFromYAML,
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CableDataToTable
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)
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# -- General configuration ------------------------------------------------
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extensions = [
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# Standard Sphinx extensions
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"sphinx.ext.extlinks",
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"sphinx.ext.intersphinx",
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]
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templates_path = ["_templates"]
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source_suffix = {
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".rst": "restructuredtext",
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}
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master_doc = "index"
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project = u"openFPGALoader: universal utility for programming FPGA"
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copyright = u"2019-2022, Gwenhael Goavec-Merou and contributors"
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author = u"Gwenhael Goavec-Merou and contributors"
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version = "latest"
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release = version # The full version, including alpha/beta/rc tags.
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language = None
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exclude_patterns = []
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numfig = True
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# -- Options for HTML output ----------------------------------------------
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html_context = {}
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ctx = ROOT / "context.json"
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if ctx.is_file():
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html_context.update(loads(ctx.open("r").read()))
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if (ROOT / "_theme").is_dir():
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html_theme_path = ["."]
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html_theme = "_theme"
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html_theme_options = {
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"home_breadcrumbs": False,
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"vcs_pageview_mode": "blob",
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}
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else:
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html_theme = "alabaster"
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htmlhelp_basename = "OFLDoc"
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# -- Options for LaTeX output ---------------------------------------------
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latex_elements = {
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"papersize": "a4paper",
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}
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latex_documents = [
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(master_doc, "OFLDoc.tex", u"openFPGALoader: universal utility for programming FPGA (Documentation)", author, "manual"),
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]
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# -- Options for manual page output ---------------------------------------
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# One entry per manual page. List of tuples
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# (source start file, name, description, authors, manual section).
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man_pages = [(master_doc, "openFPGALoader", u"Universal utility for programming FPGA (Documentation)", [author], 1)]
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# -- Options for Texinfo output -------------------------------------------
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texinfo_documents = [
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(
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master_doc,
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"openFPGALoader",
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u"Universal utility for programming FPGA (Documentation)",
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author,
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"openFPGALoader",
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"HDL verification.",
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"Miscellaneous",
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),
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]
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# -- Sphinx.Ext.InterSphinx -----------------------------------------------
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intersphinx_mapping = {
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"python": ("https://docs.python.org/3/", None),
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"constraints": ("https://hdl.github.io/constraints", None)
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}
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# -- Sphinx.Ext.ExtLinks --------------------------------------------------
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extlinks = {
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"wikipedia": ("https://en.wikipedia.org/wiki/%s", None),
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"ghsharp": ("https://github.com/trabucayre/openFPGALoader/issues/%s", "#"),
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"ghissue": ("https://github.com/trabucayre/openFPGALoader/issues/%s", "issue #"),
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"ghpull": ("https://github.com/trabucayre/openFPGALoader/pull/%s", "pull request #"),
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"ghsrc": ("https://github.com/trabucayre/openFPGALoader/blob/master/%s", None),
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}
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# -- Generate partial board compatibility page (`board.inc`) with data from `boards.yml`
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with (ROOT / "compatibility/boards.inc").open("w", encoding="utf-8") as wptr:
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wptr.write(BoardDataToTable(ReadBoardDataFromYAML()))
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# -- Generate partial FPGA compatibility page (`fpga.inc`) with data from `FPGAs.yml`
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with (ROOT / "compatibility/fpga.inc").open("w", encoding="utf-8") as wptr:
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wptr.write(FPGADataToTable(ReadFPGADataFromYAML()))
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# -- Generate partial Cable compatibility page (`cable.inc`) with data from `cable.yml`
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with (ROOT / "compatibility/cable.inc").open("w", encoding="utf-8") as wptr:
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wptr.write(CableDataToTable(ReadCableDataFromYAML()))
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