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openFPGALoader
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Adding ability to configure https://theretroweb.com/expansioncards/s/celestica-fpga-accelerator-du-pcb-001-003 with hint from https://fpga.com.ua/index.php?product_id=329&route=product%2Fproduct

This commit is contained in:
blurbdust 2026-02-09 14:07:07 -06:00
parent a91dd9f628
commit 31ffeb8290
4 changed files with 6 additions and 3 deletions
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bpiOverJtag/bpiOverJtag_xc7k480tffg1156.bit.gz
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bpiOverJtag/constr_xc7k480t_bpi_ffg1156.xdc
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@ -4,6 +4,7 @@
set_property CFGBVS GND [current_design]
set_property CONFIG_VOLTAGE 1.8 [current_design]
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLNONE [current_design]
## Address bus [25:1]
set_property -dict {PACKAGE_PIN AD26 IOSTANDARD LVCMOS18} [get_ports {bpi_addr[1]}]

4
src/bpiFlash.cpp
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@ -357,7 +357,9 @@ bool BPIFlash::erase_block(uint32_t addr)
/* Verify erase by reading first few words */
if (_verbose) {
bpi_write(0, FLASH_CMD_READ_ARRAY);
/* Send READ_ARRAY to the erased block's address (not addr 0),
* because multi-bank flash requires per-bank mode commands */
bpi_write(word_addr, FLASH_CMD_READ_ARRAY);
usleep(100);
char buf[128];
snprintf(buf, sizeof(buf), "Verify erase at 0x%06x:", addr);

4
src/xilinx.cpp
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@ -880,11 +880,11 @@ void Xilinx::program_mem(ConfigBitstreamParser *bitfile)
* the TLR (Test-Logic-Reset) state.
*/
_jtag->shiftIR(get_ircode(_ircode_map, "JPROGRAM"), NULL, _irlen);
/* test */
/* Poll INIT_B (bit 4 of IR capture) until config memory is cleared */
tx_buf = get_ircode(_ircode_map, "BYPASS");
do {
_jtag->shiftIR(tx_buf, rx_buf, _irlen);
} while (!(rx_buf[0] &0x01));
} while (!(rx_buf[0] & 0x10));
/*
* 8: Move into the RTI state. X 0 10,000(1)
*/