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spiOverJtag: reword FGG676 SPI-flash pin comment as package-level 

These pins are fixed by the XC7A*T-FGG676 package, not by the QMTech board.
Reword the comment to reflect that any XC7A35T/50T/75T/100T/200T in the FGG676
package routes the SPI-flash signals to the same balls. Keep the QMTech
schematic only as the cross-check reference. No pin values changed.

Addresses trabucayre review on constr_xc7a_fgg676.xdc.
This commit is contained in:
gHashTag 2026-06-20 07:32:36 +00:00
parent 6df17fddd8
commit 2b024ce2f9
1 changed files with 8 additions and 6 deletions
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14
spiOverJtag/constr_xc7a_fgg676.xdc
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@ -13,12 +13,14 @@ set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
# all-caps `JTAGCLK` is silently rejected and Vivado falls back to Cclk. # all-caps `JTAGCLK` is silently rejected and Vivado falls back to Cclk.
set_property BITSTREAM.STARTUP.STARTUPCLK JtagClk [current_design] set_property BITSTREAM.STARTUP.STARTUPCLK JtagClk [current_design]
# XC7A75T/100T/200T-FGG676 SPI flash pins on QMTech XC7A100T-2FGG676I core board. # SPI flash pins for the XC7A*T-FGG676 package (Bank 14 dual-purpose config IO:
# Verified against QMTECH_XC7A75T_100T_200T-CORE-BOARD-V01-20210109.pdf schematic # D00..D03, FCS_B). These pins are package-level: any XC7A35T/50T/75T/100T/200T
# (https://github.com/ChinaQMTECH/QMTECH_XC7A75T-100T-200T_Core_Board). # in the FGG676 package routes the dedicated SPI-flash signals to the same balls,
# These are Bank 14 dual-purpose user IO pins (D00..D03, FCS_B) wired to the # so this constraint is not specific to the QMTech board.
# on-board N25Q064A SPI flash (JEDEC 0x20BA17). CCLK is driven internally via # Pinout cross-checked against the QMTech XC7A75T/100T/200T core board schematic
# the STARTUPE2 primitive instantiated in xilinx_spiOverJtag.v. # (QMTECH_XC7A75T_100T_200T-CORE-BOARD-V01-20210109.pdf, on-board N25Q064A,
# JEDEC 0x20BA17). CCLK is driven internally via the STARTUPE2 primitive
# instantiated in xilinx_spiOverJtag.v.
set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVCMOS33} [get_ports {csn}] set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVCMOS33} [get_ports {csn}]
set_property -dict {PACKAGE_PIN R14 IOSTANDARD LVCMOS33} [get_ports {sdi_dq0}] set_property -dict {PACKAGE_PIN R14 IOSTANDARD LVCMOS33} [get_ports {sdi_dq0}]
set_property -dict {PACKAGE_PIN R15 IOSTANDARD LVCMOS33} [get_ports {sdo_dq1}] set_property -dict {PACKAGE_PIN R15 IOSTANDARD LVCMOS33} [get_ports {sdo_dq1}]