From 2b024ce2f921303491ed3a17acff25830f77b056 Mon Sep 17 00:00:00 2001 From: gHashTag Date: Sat, 20 Jun 2026 07:32:36 +0000 Subject: [PATCH] spiOverJtag: reword FGG676 SPI-flash pin comment as package-level These pins are fixed by the XC7A*T-FGG676 package, not by the QMTech board. Reword the comment to reflect that any XC7A35T/50T/75T/100T/200T in the FGG676 package routes the SPI-flash signals to the same balls. Keep the QMTech schematic only as the cross-check reference. No pin values changed. Addresses trabucayre review on constr_xc7a_fgg676.xdc. --- spiOverJtag/constr_xc7a_fgg676.xdc | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/spiOverJtag/constr_xc7a_fgg676.xdc b/spiOverJtag/constr_xc7a_fgg676.xdc index b179c41..5f4034e 100644 --- a/spiOverJtag/constr_xc7a_fgg676.xdc +++ b/spiOverJtag/constr_xc7a_fgg676.xdc @@ -13,12 +13,14 @@ set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] # all-caps `JTAGCLK` is silently rejected and Vivado falls back to Cclk. set_property BITSTREAM.STARTUP.STARTUPCLK JtagClk [current_design] -# XC7A75T/100T/200T-FGG676 SPI flash pins on QMTech XC7A100T-2FGG676I core board. -# Verified against QMTECH_XC7A75T_100T_200T-CORE-BOARD-V01-20210109.pdf schematic -# (https://github.com/ChinaQMTECH/QMTECH_XC7A75T-100T-200T_Core_Board). -# These are Bank 14 dual-purpose user IO pins (D00..D03, FCS_B) wired to the -# on-board N25Q064A SPI flash (JEDEC 0x20BA17). CCLK is driven internally via -# the STARTUPE2 primitive instantiated in xilinx_spiOverJtag.v. +# SPI flash pins for the XC7A*T-FGG676 package (Bank 14 dual-purpose config IO: +# D00..D03, FCS_B). These pins are package-level: any XC7A35T/50T/75T/100T/200T +# in the FGG676 package routes the dedicated SPI-flash signals to the same balls, +# so this constraint is not specific to the QMTech board. +# Pinout cross-checked against the QMTech XC7A75T/100T/200T core board schematic +# (QMTECH_XC7A75T_100T_200T-CORE-BOARD-V01-20210109.pdf, on-board N25Q064A, +# JEDEC 0x20BA17). CCLK is driven internally via the STARTUPE2 primitive +# instantiated in xilinx_spiOverJtag.v. set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVCMOS33} [get_ports {csn}] set_property -dict {PACKAGE_PIN R14 IOSTANDARD LVCMOS33} [get_ports {sdi_dq0}] set_property -dict {PACKAGE_PIN R15 IOSTANDARD LVCMOS33} [get_ports {sdo_dq1}]