ftdispi, ecpq: use enum for endianness and cs mode
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1a952f466a
commit
221e814509
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@ -45,14 +45,14 @@ void EPCQ::wait_wel()
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{
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{
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uint8_t cmd = RD_STATUS_REG, recv;
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uint8_t cmd = RD_STATUS_REG, recv;
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_spi.setCSmode(SPI_CS_MANUAL);
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_spi.setCSmode(FtdiSpi::SPI_CS_MANUAL);
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_spi.clearCs();
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_spi.clearCs();
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_spi.ft2232_spi_wr_and_rd(1, &cmd, NULL);
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_spi.ft2232_spi_wr_and_rd(1, &cmd, NULL);
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do {
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do {
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_spi.ft2232_spi_wr_and_rd(1, NULL, &recv);
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_spi.ft2232_spi_wr_and_rd(1, NULL, &recv);
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} while(!(recv & STATUS_REG_WEL));
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} while(!(recv & STATUS_REG_WEL));
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_spi.setCs();
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_spi.setCs();
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_spi.setCSmode(SPI_CS_AUTO);
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_spi.setCSmode(FtdiSpi::SPI_CS_AUTO);
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}
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}
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/* wait for WIP goes low by reading
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/* wait for WIP goes low by reading
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@ -62,14 +62,14 @@ void EPCQ::wait_wip()
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{
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{
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uint8_t cmd = RD_STATUS_REG, recv;
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uint8_t cmd = RD_STATUS_REG, recv;
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_spi.setCSmode( SPI_CS_MANUAL);
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_spi.setCSmode( FtdiSpi::SPI_CS_MANUAL);
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_spi.clearCs();
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_spi.clearCs();
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_spi.ft2232_spi_wr_and_rd(1, &cmd, NULL);
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_spi.ft2232_spi_wr_and_rd(1, &cmd, NULL);
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do {
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do {
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_spi.ft2232_spi_wr_and_rd(1, NULL, &recv);
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_spi.ft2232_spi_wr_and_rd(1, NULL, &recv);
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} while(0x00 != (recv & STATUS_REG_WIP));
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} while(0x00 != (recv & STATUS_REG_WIP));
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_spi.setCs();
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_spi.setCs();
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_spi.setCSmode( SPI_CS_AUTO);
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_spi.setCSmode( FtdiSpi::SPI_CS_AUTO);
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}
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}
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/* enable write enable */
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/* enable write enable */
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@ -7,12 +7,15 @@
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class FtdiSpi : public FTDIpp_MPSSE, SPIInterface {
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class FtdiSpi : public FTDIpp_MPSSE, SPIInterface {
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public:
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public:
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#define SPI_MSB_FIRST 0
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enum SPI_endianness {
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#define SPI_LSB_FIRST 1
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SPI_MSB_FIRST = 0,
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SPI_LSB_FIRST = 1
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#define SPI_CS_AUTO 0
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};
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#define SPI_CS_MANUAL 1
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enum SPI_CS_mode {
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SPI_CS_AUTO = 0,
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SPI_CS_MANUAL = 1
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};
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FtdiSpi(int vid, int pid, unsigned char interface, uint32_t clkHZ,
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FtdiSpi(int vid, int pid, unsigned char interface, uint32_t clkHZ,
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bool verbose);
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bool verbose);
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