From 221e814509a54a19f686c9a8d17e366e3d6feeac Mon Sep 17 00:00:00 2001
From: Gwenhael Goavec-Merou <gwenhael.goavec-merou@trabucayre.com>
Date: Tue, 6 Oct 2020 08:36:12 +0200
Subject: [PATCH] ftdispi, ecpq: use enum for endianness and cs mode

---
 src/epcq.cpp    |  8 ++++----
 src/ftdispi.hpp | 13 ++++++++-----
 2 files changed, 12 insertions(+), 9 deletions(-)

diff --git a/src/epcq.cpp b/src/epcq.cpp
index 9d219eb..9f2f7f8 100644
--- a/src/epcq.cpp
+++ b/src/epcq.cpp
@@ -45,14 +45,14 @@ void EPCQ::wait_wel()
 {
 	uint8_t cmd = RD_STATUS_REG, recv;
 
-	_spi.setCSmode(SPI_CS_MANUAL);
+	_spi.setCSmode(FtdiSpi::SPI_CS_MANUAL);
 	_spi.clearCs();
 	_spi.ft2232_spi_wr_and_rd(1, &cmd, NULL);
 	do {
 		_spi.ft2232_spi_wr_and_rd(1, NULL, &recv);
 	} while(!(recv & STATUS_REG_WEL));
 	_spi.setCs();
-	_spi.setCSmode(SPI_CS_AUTO);
+	_spi.setCSmode(FtdiSpi::SPI_CS_AUTO);
 }
 
 /* wait for WIP goes low by reading
@@ -62,14 +62,14 @@ void EPCQ::wait_wip()
 {
 	uint8_t cmd = RD_STATUS_REG, recv;
 
-	_spi.setCSmode( SPI_CS_MANUAL);
+	_spi.setCSmode( FtdiSpi::SPI_CS_MANUAL);
 	_spi.clearCs();
 	_spi.ft2232_spi_wr_and_rd(1, &cmd, NULL);
 	do {
 		_spi.ft2232_spi_wr_and_rd(1, NULL, &recv);
 	} while(0x00 != (recv & STATUS_REG_WIP));
 	_spi.setCs();
-	_spi.setCSmode( SPI_CS_AUTO);
+	_spi.setCSmode( FtdiSpi::SPI_CS_AUTO);
 }
 
 /* enable write enable */
diff --git a/src/ftdispi.hpp b/src/ftdispi.hpp
index 3def0e7..e60539e 100644
--- a/src/ftdispi.hpp
+++ b/src/ftdispi.hpp
@@ -7,12 +7,15 @@
 
 class FtdiSpi : public FTDIpp_MPSSE, SPIInterface {
  public:
-	#define SPI_MSB_FIRST 0
-	#define SPI_LSB_FIRST 1
-
-	#define SPI_CS_AUTO   0
-	#define SPI_CS_MANUAL 1
+	enum SPI_endianness {
+		SPI_MSB_FIRST = 0,
+		SPI_LSB_FIRST = 1
+	};
 
+	enum SPI_CS_mode {
+		SPI_CS_AUTO   = 0,
+		SPI_CS_MANUAL = 1
+	};
 
 	FtdiSpi(int vid, int pid, unsigned char interface, uint32_t clkHZ,
 		bool verbose);