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spiOverJtag: add xc7a100 bitstream

This commit is contained in:
Gwenhael Goavec-Merou 2020-09-22 15:02:42 +02:00
parent 9c89c43b4d
commit 20d72de3c4
4 changed files with 12 additions and 2 deletions
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2
spiOverJtag/Makefile
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@ -1,5 +1,5 @@
VIVADO := vivado -nolog -nojournal -mode batch -source VIVADO := vivado -nolog -nojournal -mode batch -source
MODELS := xc7a35 xc7s50 MODELS := xc7a35 xc7a100 xc7s50
BIT_FILES := $(addsuffix .bit,$(addprefix spiOverJtag_, $(MODELS))) BIT_FILES := $(addsuffix .bit,$(addprefix spiOverJtag_, $(MODELS)))
all: $(BIT_FILES) all: $(BIT_FILES)

10
spiOverJtag/constr_xc7a100.xdc Normal file
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@ -0,0 +1,10 @@
set_property CFGBVS VCCO [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH {4} [current_design]
set_property -dict {PACKAGE_PIN T19 IOSTANDARD LVTTL} [get_ports {csn}]
set_property -dict {PACKAGE_PIN P22 IOSTANDARD LVTTL} [get_ports {sdi_dq0}]
set_property -dict {PACKAGE_PIN R22 IOSTANDARD LVTTL} [get_ports {sdo_dq1}]
set_property -dict {PACKAGE_PIN P21 IOSTANDARD LVTTL} [get_ports {wpn_dq2}]
set_property -dict {PACKAGE_PIN R21 IOSTANDARD LVTTL} [get_ports {hldn_dq3}]

BIN
spiOverJtag/spiOverJtag_xc7a100.bit Normal file
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2
spiOverJtag/xilinx_spiOverJtag.tcl
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@ -6,7 +6,7 @@ set build_path tmp_${model}
file delete -force $build_path file delete -force $build_path
# Project creation # Project creation
set parts [dict create xc7a35 xc7a35ticsg324-1L xc7s50 xc7s50csga324-1] set parts [dict create xc7a35 xc7a35ticsg324-1L xc7a100 xc7a100tfgg484-2 xc7s50 xc7s50csga324-1]
create_project $project_name $build_path -part [dict get $parts $model] create_project $project_name $build_path -part [dict get $parts $model]
add_files -norecurse xilinx_spiOverJtag.vhd add_files -norecurse xilinx_spiOverJtag.vhd