diff --git a/spiOverJtag/Makefile b/spiOverJtag/Makefile
index 834b4b1..9c02cad 100644
--- a/spiOverJtag/Makefile
+++ b/spiOverJtag/Makefile
@@ -1,5 +1,5 @@
 VIVADO := vivado -nolog -nojournal -mode batch -source
-MODELS := xc7a35 xc7s50
+MODELS := xc7a35 xc7a100 xc7s50
 BIT_FILES := $(addsuffix .bit,$(addprefix spiOverJtag_, $(MODELS)))
 
 all: $(BIT_FILES)
diff --git a/spiOverJtag/constr_xc7a100.xdc b/spiOverJtag/constr_xc7a100.xdc
new file mode 100644
index 0000000..5e2b0e6
--- /dev/null
+++ b/spiOverJtag/constr_xc7a100.xdc
@@ -0,0 +1,10 @@
+set_property CFGBVS VCCO [current_design]
+set_property CONFIG_VOLTAGE 3.3 [current_design]
+set_property BITSTREAM.CONFIG.SPI_BUSWIDTH {4} [current_design]
+
+set_property -dict {PACKAGE_PIN T19 IOSTANDARD LVTTL} [get_ports {csn}]
+set_property -dict {PACKAGE_PIN P22 IOSTANDARD LVTTL} [get_ports {sdi_dq0}]
+set_property -dict {PACKAGE_PIN R22 IOSTANDARD LVTTL} [get_ports {sdo_dq1}]
+set_property -dict {PACKAGE_PIN P21 IOSTANDARD LVTTL} [get_ports {wpn_dq2}]
+set_property -dict {PACKAGE_PIN R21 IOSTANDARD LVTTL} [get_ports {hldn_dq3}]
+
diff --git a/spiOverJtag/spiOverJtag_xc7a100.bit b/spiOverJtag/spiOverJtag_xc7a100.bit
new file mode 100644
index 0000000..97c0b5e
Binary files /dev/null and b/spiOverJtag/spiOverJtag_xc7a100.bit differ
diff --git a/spiOverJtag/xilinx_spiOverJtag.tcl b/spiOverJtag/xilinx_spiOverJtag.tcl
index 4bfe615..33a9bf9 100644
--- a/spiOverJtag/xilinx_spiOverJtag.tcl
+++ b/spiOverJtag/xilinx_spiOverJtag.tcl
@@ -6,7 +6,7 @@ set build_path tmp_${model}
 file delete -force $build_path
 
 # Project creation
-set parts [dict create xc7a35 xc7a35ticsg324-1L xc7s50 xc7s50csga324-1]
+set parts [dict create xc7a35 xc7a35ticsg324-1L xc7a100 xc7a100tfgg484-2 xc7s50 xc7s50csga324-1]
 create_project $project_name $build_path -part [dict get $parts $model]
 
 add_files -norecurse xilinx_spiOverJtag.vhd